MC9S08AC16MEFJE

MC9S08AC16 MC9S08AC8 MC9S08AW16A MC9S08AW8A Data Sheet HCS08 Microcontrollers MC9S08AC16 Rev. 8 11/2009 freescale.com MC9S08AC16 Series Features MC9S08AC16 Series Devices • Consumer & Industrial — MC9S08AC16 — MC9S08AC8 Automotive — MC9S08AW16A — MC9S08AW8A 40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints. Support for up to 32 interrupt/reset sources Up to 16 KB of on-chip in-circuit programmable FLASH memory with block protection and security options Up to 1 KB of on-chip RAM Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming Optional computer operating properly (COP) reset with option to run from independent internal clock source or bus clock Low-voltage detection with reset or interrupt Illegal opcode detection with reset Illegal address detection with reset Wait plus two stops Peripherals • • • • ADC — 8-channel, 10-bit analog-to-digital converter with automatic compare function SCI — Two serial communications interface modules with optional 13-bit break SPI — Serial peripheral interface module IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; capable of higher baud rates with reduced loading Timers — Three 16-bit timer/pulse-width modulator (TPM) modules — Two 2-channel and one 4-channel; each has selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels KBI — 7-pin keyboard interrupt module Up to 38 general-purpose input/output (I/O) pins Software selectable pullups on ports when used as inputs Software selectable slew rate control on ports when used as outputs Software selectable drive strength on ports when used as outputs Master reset pin and power-on reset (POR) Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost 48-pin quad flat no-lead package (QFN) 44-pin low-profile quad flat package (LQFP) 42-pin shrink dual-in-line package (SDIP) 32-pin low-profile quad flat package (LQFP) • 8-Bit HCS08 Central Processor Unit (CPU) • • • • • • • • • • • • • • Input/Output • • Memory Options • • Clock Source Options Package Options • • • • System Protection • • • • • Power-Saving Modes MC9S08AC16 Series Data Sheet Covers MC9S08AC16 MC9S08AC8 MC9S08AW16A MC9S08AW8A MC9S08AC16 Rev. 8 11/2009 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision Number 0 1 2 3 4 5 6 Revision Date 12/2007 12/2007 2/2008 3/2008 5/2008 6/2008 7/2008 Initial Release. Updated the package designators for the 32 LQFP and 44 LQFP to be LC and LD respectively. Corrected the SPI block module to be V3. AC market launch.Verified that the ADC Temp Sensor values were correct. Incorporated general release edits and updates, revised the Stop2 and Stop3 max values, added the RoHS logo, and updated the back cover addresses. Corrected the note in the TPM introduction. Changed all instances of S9S08AWxxA to MC9S08AWxxA except in Appendix B. Added 42SDIP package option. Corrected SPI registers in Table 4-2. Added VBG in Table A-6. Corrected title of Table 6-3, Figure 6-13, Figure 6-14, Table 6-5 and Figure 6-19. Added errata for the following sections: • Throughout (remove stop1 instances) • Table 4-1 • Table 4-2 • Section 9.2, “Keyboard Pin Sharing” • Section 9.3, “Features • Table A-6 • Table A-7 • Figure A-12 Updated the whole document for MC9S08AW16A/MC9S08AW8A to support the third TPM module. Updated the TPM 1 channel to 4 for the 32-pin packages in the Table 1-1. Updated the bit 2 of IRQSC register in the Table 4-2. Updated the Temp Sensor Voltage in the Table A-9. Description of Changes 7 5/2009 8 11/20/2009 This product incorporates SuperFlash® technology licensed from SST. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. MC9S08AC16 Series Data Sheet, Rev. 8 6 Freescale Semiconductor List of Chapters Chapter Title Page Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Appendix A Appendix B Introduction.............................................................................. 19 Pins and Connections ............................................................. 25 Modes of Operation ................................................................. 35 Memory ..................................................................................... 41 Resets, Interrupts, and System Configuration ..................... 63 Parallel Input/Output ............................................................... 81 Central Processor Unit (S08CPUV2) .................................... 107 Internal Clock Generator (S08ICGV4) .................................. 127 Keyboard Interrupt (S08KBIV1) ............................................ 153 Timer/PWM (S08TPMV3) ....................................................... 159 Serial Communications Interface (S08SCIV4)..................... 189 Serial Peripheral Interface (S08SPIV3) ................................ 209 Inter-Integrated Circuit (S08IICV2) ....................................... 225 Analog-to-Digital Converter (S08ADC10V1)........................ 243 Development Support ........................................................... 271 Electrical Characteristics and Timing Specifications ....... 293 Ordering Information and Mechanical Drawings............... 319 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 7 Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 Overview .........................................................................................................................................19 MCU Block Diagrams .....................................................................................................................20 System Clock Distribution ..............................................................................................................22 Chapter 2 Pins and Connections 2.1 2.2 2.3 Introduction .....................................................................................................................................25 Device Pin Assignment ...................................................................................................................25 Recommended System Connections ...............................................................................................30 2.3.1 Power (VDD, 2 x VSS, VDDAD, VSSAD) ...........................................................................32 2.3.2 Oscillator (XTAL, EXTAL) ..............................................................................................32 2.3.3 RESET ..............................................................................................................................32 2.3.4 Background/Mode Select (BKGD/MS) ............................................................................33 2.3.5 ADC Reference Pins (VREFH, VREFL) .............................................................................33 2.3.6 External Interrupt Pin (IRQ) .............................................................................................33 2.3.7 General-Purpose I/O and Peripheral Ports ........................................................................34 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................35 Features ...........................................................................................................................................35 Run Mode ........................................................................................................................................35 Active Background Mode ...............................................................................................................35 Wait Mode .......................................................................................................................................36 Stop Modes ......................................................................................................................................36 3.6.1 Stop2 Mode .......................................................................................................................37 3.6.2 Stop3 Mode .......................................................................................................................38 3.6.3 Active BDM Enabled in Stop Mode .................................................................................38 3.6.4 LVD Enabled in Stop Mode ..............................................................................................39 3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................39 Chapter 4 Memory 4.1 MC9S08AC16 Series Memory Map ...............................................................................................41 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 9 Section Number 4.2 4.3 4.4 Title Page 4.5 4.6 Register Addresses and Bit Assignments ........................................................................................43 RAM ................................................................................................................................................49 FLASH ............................................................................................................................................50 4.4.1 Features .............................................................................................................................50 4.4.2 Program and Erase Times .................................................................................................50 4.4.3 Program and Erase Command Execution .........................................................................51 4.4.4 Burst Program Execution ..................................................................................................52 4.4.5 Access Errors ....................................................................................................................54 4.4.6 FLASH Block Protection ..................................................................................................54 4.4.7 Vector Redirection ............................................................................................................55 Security ............................................................................................................................................55 FLASH Registers and Control Bits .................................................................................................57 4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................57 4.6.2 FLASH Options Register (FOPT and NVOPT) ................................................................58 4.6.3 FLASH Configuration Register (FCNFG) .......................................................................59 4.6.4 FLASH Protection Register (FPROT and NVPROT) ......................................................60 4.6.5 FLASH Status Register (FSTAT) ......................................................................................60 4.6.6 FLASH Command Register (FCMD) ...............................................................................61 Chapter 5 Resets, Interrupts, and System Configuration 5.1 5.2 5.3 5.4 5.5 Introduction .....................................................................................................................................63 Features ...........................................................................................................................................63 MCU Reset ......................................................................................................................................63 Computer Operating Properly (COP) Watchdog .............................................................................64 Interrupts .........................................................................................................................................65 5.5.1 Interrupt Stack Frame .......................................................................................................66 5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................66 5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................67 Low-Voltage Detect (LVD) System ................................................................................................69 5.6.1 Power-On Reset Operation ...............................................................................................69 5.6.2 LVD Reset Operation ........................................................................................................69 5.6.3 LVD Interrupt Operation ...................................................................................................69 5.6.4 Low-Voltage Warning (LVW) ...........................................................................................69 Real-Time Interrupt (RTI) ...............................................................................................................69 MCLK Output .................................................................................................................................70 Reset, Interrupt, and System Control Registers and Control Bits ...................................................70 5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................71 5.9.2 System Reset Status Register (SRS) .................................................................................72 5.9.3 System Background Debug Force Reset Register (SBDFR) ............................................73 5.9.4 System Options Register (SOPT) .....................................................................................74 5.9.5 System MCLK Control Register (SMCLK) .....................................................................75 MC9S08AC16 Series Data Sheet, Rev. 8 10 Freescale Semiconductor 5.6 5.7 5.8 5.9 Section Number 5.9.6 5.9.7 5.9.8 5.9.9 5.9.10 Title Page System Device Identification Register (SDIDH, SDIDL) ................................................75 System Real-Time Interrupt Status and Control Register (SRTISC) ................................76 System Power Management Status and Control 1 Register (SPMSC1) ...........................77 System Power Management Status and Control 2 Register (SPMSC2) ...........................79 System Options Register 2 (SOPT2) ................................................................................80 Chapter 6 Parallel Input/Output 6.1 6.2 6.3 Introduction .....................................................................................................................................81 Features ...........................................................................................................................................83 Pin Descriptions ..............................................................................................................................83 6.3.1 Port A ................................................................................................................................83 6.3.2 Port B ................................................................................................................................84 6.3.3 Port C ................................................................................................................................84 6.3.4 Port D ................................................................................................................................85 6.3.5 Port E ................................................................................................................................85 6.3.6 Port F .................................................................................................................................86 6.3.7 Port G ................................................................................................................................86 Parallel I/O Control .........................................................................................................................87 Pin Control ......................................................................................................................................88 6.5.1 Internal Pullup Enable ......................................................................................................88 6.5.2 Output Slew Rate Control Enable .....................................................................................88 6.5.3 Output Drive Strength Select ............................................................................................88 Pin Behavior in Stop Modes ............................................................................................................89 Parallel I/O and Pin Control Registers ............................................................................................89 6.7.1 Port A I/O Registers (PTAD and PTADD) ........................................................................89 6.7.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) .................................................90 6.7.3 Port B I/O Registers (PTBD and PTBDD) ........................................................................92 6.7.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) .................................................93 6.7.5 Port C I/O Registers (PTCD and PTCDD) ........................................................................94 6.7.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) .................................................95 6.7.7 Port D I/O Registers (PTDD and PTDDD) .......................................................................97 6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) ................................................98 6.7.9 Port E I/O Registers (PTED and PTEDD) ........................................................................99 6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) ................................................100 6.7.11 Port F I/O Registers (PTFD and PTFDD) .......................................................................102 6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) .................................................103 6.7.13 Port G I/O Registers (PTGD and PTGDD) .....................................................................104 6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ..............................................105 6.4 6.5 6.6 6.7 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 11 Section Number Title Chapter 7 Central Processor Unit (S08CPUV2) Page 7.1 7.2 7.3 7.4 7.5 Introduction ...................................................................................................................................107 7.1.1 Features ...........................................................................................................................107 Programmer’s Model and CPU Registers .....................................................................................108 7.2.1 Accumulator (A) .............................................................................................................108 7.2.2 Index Register (H:X) ......................................................................................................108 7.2.3 Stack Pointer (SP) ...........................................................................................................109 7.2.4 Program Counter (PC) ....................................................................................................109 7.2.5 Condition Code Register (CCR) .....................................................................................109 Addressing Modes .........................................................................................................................110 7.3.1 Inherent Addressing Mode (INH) ................................................................................... 111 7.3.2 Relative Addressing Mode (REL) ..................................................................................111 7.3.3 Immediate Addressing Mode (IMM) ..............................................................................111 7.3.4 Direct Addressing Mode (DIR) ......................................................................................111 7.3.5 Extended Addressing Mode (EXT) ................................................................................ 111 7.3.6 Indexed Addressing Mode ..............................................................................................111 Special Operations .........................................................................................................................112 7.4.1 Reset Sequence ...............................................................................................................113 7.4.2 Interrupt Sequence ..........................................................................................................113 7.4.3 Wait Mode Operation ......................................................................................................114 7.4.4 Stop Mode Operation ......................................................................................................114 7.4.5 BGND Instruction ...........................................................................................................114 HCS08 Instruction Set Summary ..................................................................................................115 Chapter 8 Internal Clock Generator (S08ICGV4) 8.1 Introduction ...................................................................................................................................129 8.1.1 Features ...........................................................................................................................129 8.1.2 Modes of Operation ........................................................................................................130 8.1.3 Block Diagram ................................................................................................................131 External Signal Description ..........................................................................................................131 8.2.1 EXTAL — External Reference Clock / Oscillator Input ................................................131 8.2.2 XTAL — Oscillator Output ............................................................................................131 8.2.3 External Clock Connections ...........................................................................................132 8.2.4 External Crystal/Resonator Connections ........................................................................132 Register Definition ........................................................................................................................132 8.3.1 ICG Control Register 1 (ICGC1) ....................................................................................133 8.3.2 ICG Control Register 2 (ICGC2) ....................................................................................134 8.3.3 ICG Status Register 1 (ICGS1) .......................................................................................135 8.3.4 ICG Status Register 2 (ICGS2) .......................................................................................136 8.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................136 MC9S08AC16 Series Data Sheet, Rev. 8 12 Freescale Semiconductor 8.2 8.3 Section Number 8.4 Title Page 8.5 8.3.6 ICG Trim Register (ICGTRM) ........................................................................................137 Functional Description ..................................................................................................................137 8.4.1 Off Mode (Off) ................................................................................................................138 8.4.2 Self-Clocked Mode (SCM) .............................................................................................138 8.4.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................139 8.4.4 FLL Engaged Internal Unlocked ....................................................................................140 8.4.5 FLL Engaged Internal Locked ........................................................................................140 8.4.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................140 8.4.7 FLL Engaged, External Clock (FEE) Mode ...................................................................140 8.4.8 FLL Lock and Loss-of-Lock Detection ..........................................................................141 8.4.9 FLL Loss-of-Clock Detection .........................................................................................142 8.4.10 Clock Mode Requirements .............................................................................................143 8.4.11 Fixed Frequency Clock ...................................................................................................144 8.4.12 High Gain Oscillator .......................................................................................................144 Initialization/Application Information ..........................................................................................144 8.5.1 Introduction .....................................................................................................................144 8.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................146 8.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................148 8.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................150 8.5.5 Example #4: Internal Clock Generator Trim ..................................................................152 Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 9.2 9.3 9.4 Introduction ...................................................................................................................................153 Keyboard Pin Sharing ...................................................................................................................153 Features .........................................................................................................................................153 9.3.1 KBI Block Diagram ........................................................................................................155 Register Definition ........................................................................................................................155 9.4.1 KBI Status and Control Register (KBISC) .....................................................................156 9.4.2 KBI Pin Enable Register (KBIPE) ..................................................................................157 Functional Description ..................................................................................................................157 9.5.1 Pin Enables .....................................................................................................................157 9.5.2 Edge and Level Sensitivity .............................................................................................157 9.5.3 KBI Interrupt Controls ....................................................................................................158 9.5 Chapter 10 Timer/PWM (S08TPMV3) 10.1 Introduction ...................................................................................................................................159 10.2 Features .........................................................................................................................................159 10.3 TPMV3 Differences from Previous Versions ................................................................................161 10.3.1 Migrating from TPMV1 ..................................................................................................163 10.3.2 Features ...........................................................................................................................164 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 13 Section Number Title Page 10.4 10.5 10.6 10.7 10.8 10.9 10.3.3 Modes of Operation ........................................................................................................164 10.3.4 Block Diagram ................................................................................................................165 Signal Description .........................................................................................................................167 10.4.1 Detailed Signal Descriptions ..........................................................................................167 Register Definition ........................................................................................................................171 10.5.1 TPM Status and Control Register (TPMxSC) ................................................................171 10.5.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................172 10.5.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................173 10.5.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................174 10.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................176 Functional Description ..................................................................................................................177 10.6.1 Counter ............................................................................................................................178 10.6.2 Channel Mode Selection .................................................................................................179 Reset Overview .............................................................................................................................183 10.7.1 General ............................................................................................................................183 10.7.2 Description of Reset Operation .......................................................................................183 Interrupts .......................................................................................................................................183 10.8.1 General ............................................................................................................................183 10.8.2 Description of Interrupt Operation .................................................................................183 The Differences from TPM v2 to TPM v3 ....................................................................................185 Chapter 11 Serial Communications Interface (S08SCIV4) 11.1 Introduction ...................................................................................................................................189 11.1.1 Features ...........................................................................................................................191 11.1.2 Modes of Operation ........................................................................................................191 11.1.3 Block Diagram ................................................................................................................192 11.2 Register Definition ........................................................................................................................194 11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................194 11.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................195 11.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................196 11.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................197 11.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................199 11.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................200 11.2.7 SCI Data Register (SCIxD) .............................................................................................201 11.3 Functional Description ..................................................................................................................201 11.3.1 Baud Rate Generation .....................................................................................................201 11.3.2 Transmitter Functional Description ................................................................................202 11.3.3 Receiver Functional Description ....................................................................................203 11.3.4 Interrupts and Status Flags ..............................................................................................205 11.3.5 Additional SCI Functions ...............................................................................................206 MC9S08AC16 Series Data Sheet, Rev. 8 14 Freescale Semiconductor Section Number Title Chapter 12 Serial Peripheral Interface (S08SPIV3) Page 12.1 Introduction ...................................................................................................................................209 12.1.1 Features ...........................................................................................................................211 12.1.2 Block Diagrams ..............................................................................................................211 12.1.3 SPI Baud Rate Generation ..............................................................................................213 12.2 External Signal Description ..........................................................................................................214 12.2.1 SPSCK — SPI Serial Clock ............................................................................................214 12.2.2 MOSI — Master Data Out, Slave Data In ......................................................................214 12.2.3 MISO — Master Data In, Slave Data Out ......................................................................214 12.2.4 SS — Slave Select ..........................................................................................................214 12.3 Modes of Operation .......................................................................................................................215 12.3.1 SPI in Stop Modes ..........................................................................................................215 12.4 Register Definition ........................................................................................................................215 12.4.1 SPI Control Register 1 (SPI1C1) ....................................................................................215 12.4.2 SPI Control Register 2 (SPI1C2) ....................................................................................216 12.4.3 SPI Baud Rate Register (SPI1BR) ..................................................................................217 12.4.4 SPI Status Register (SPI1S) ............................................................................................218 12.4.5 SPI Data Register (SPI1D) .............................................................................................219 12.5 Functional Description ..................................................................................................................220 12.5.1 SPI Clock Formats ..........................................................................................................220 12.5.2 SPI Interrupts ..................................................................................................................223 12.5.3 Mode Fault Detection .....................................................................................................223 Chapter 13 Inter-Integrated Circuit (S08IICV2) 13.1 Introduction ...................................................................................................................................225 13.1.1 Features ...........................................................................................................................227 13.1.2 Modes of Operation ........................................................................................................227 13.1.3 Block Diagram ................................................................................................................227 13.2 External Signal Description ..........................................................................................................228 13.2.1 SCL — Serial Clock Line ...............................................................................................228 13.2.2 SDA — Serial Data Line ................................................................................................228 13.3 Register Definition ........................................................................................................................228 13.3.1 IIC Address Register (IIC1A) .........................................................................................229 13.3.2 IIC Frequency Divider Register (IIC1F) ........................................................................229 13.3.3 IIC Control Register (IIC1C1) ........................................................................................232 13.3.4 IIC Status Register (IIC1S) .............................................................................................232 13.3.5 IIC Data I/O Register (IIC1D) ........................................................................................233 13.3.6 IIC Control Register 2 (IIC1C2) .....................................................................................234 13.4 Functional Description ..................................................................................................................235 13.4.1 IIC Protocol .....................................................................................................................235 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 15 Section Number Title Page 13.4.2 10-bit Address .................................................................................................................238 13.4.3 General Call Address ......................................................................................................239 13.5 Resets ............................................................................................................................................239 13.6 Interrupts .......................................................................................................................................239 13.6.1 Byte Transfer Interrupt ....................................................................................................239 13.6.2 Address Detect Interrupt .................................................................................................240 13.6.3 Arbitration Lost Interrupt ................................................................................................240 13.7 Initialization/Application Information ..........................................................................................241 Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.1 Overview .......................................................................................................................................243 14.2 Channel Assignments ....................................................................................................................243 14.2.1 Alternate Clock ...............................................................................................................244 14.2.2 Hardware Trigger ............................................................................................................244 14.2.3 Temperature Sensor ........................................................................................................245 14.2.4 Features ...........................................................................................................................247 14.2.5 Block Diagram ................................................................................................................247 14.3 External Signal Description ..........................................................................................................248 14.3.1 Analog Power (VDDAD) ..................................................................................................249 14.3.2 Analog Ground (VSSAD) .................................................................................................249 14.3.3 Voltage Reference High (VREFH) ...................................................................................249 14.3.4 Voltage Reference Low (VREFL) ....................................................................................249 14.3.5 Analog Channel Inputs (ADx) ........................................................................................249 14.4 Register Definition ........................................................................................................................249 14.4.1 Status and Control Register 1 (ADC1SC1) ....................................................................249 14.4.2 Status and Control Register 2 (ADC1SC2) ....................................................................251 14.4.3 Data Result High Register (ADC1RH) ...........................................................................252 14.4.4 Data Result Low Register (ADC1RL) ............................................................................252 14.4.5 Compare Value High Register (ADC1CVH) ..................................................................253 14.4.6 Compare Value Low Register (ADC1CVL) ...................................................................253 14.4.7 Configuration Register (ADC1CFG) ..............................................................................253 14.4.8 Pin Control 1 Register (APCTL1) ..................................................................................255 14.4.9 Pin Control 2 Register (APCTL2) ..................................................................................256 14.4.10Pin Control 3 Register (APCTL3) ..................................................................................257 14.5 Functional Description ..................................................................................................................258 14.5.1 Clock Select and Divide Control ....................................................................................258 14.5.2 Input Select and Pin Control ...........................................................................................259 14.5.3 Hardware Trigger ............................................................................................................259 14.5.4 Conversion Control .........................................................................................................259 14.5.5 Automatic Compare Function .........................................................................................262 14.5.6 MCU Wait Mode Operation ............................................................................................262 MC9S08AC16 Series Data Sheet, Rev. 8 16 Freescale Semiconductor Section Number Title Page 14.5.7 MCU Stop3 Mode Operation ..........................................................................................262 14.5.8 MCU Stop1 and Stop2 Mode Operation .........................................................................263 14.6 Initialization Information ..............................................................................................................263 14.6.1 ADC Module Initialization Example .............................................................................263 14.7 Application Information ................................................................................................................265 14.7.1 External Pins and Routing ..............................................................................................265 14.7.2 Sources of Error ..............................................................................................................267 Chapter 15 Development Support 15.1 Introduction ...................................................................................................................................271 15.1.1 Features ...........................................................................................................................272 15.2 Background Debug Controller (BDC) ..........................................................................................272 15.2.1 BKGD Pin Description ...................................................................................................273 15.2.2 Communication Details ..................................................................................................274 15.2.3 BDC Commands .............................................................................................................278 15.2.4 BDC Hardware Breakpoint .............................................................................................280 15.3 On-Chip Debug System (DBG) ....................................................................................................281 15.3.1 Comparators A and B .....................................................................................................281 15.3.2 Bus Capture Information and FIFO Operation ...............................................................281 15.3.3 Change-of-Flow Information ..........................................................................................282 15.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................282 15.3.5 Trigger Modes .................................................................................................................283 15.3.6 Hardware Breakpoints ....................................................................................................285 15.4 Register Definition ........................................................................................................................285 15.4.1 BDC Registers and Control Bits .....................................................................................285 15.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................287 15.4.3 DBG Registers and Control Bits .....................................................................................288 Appendix A Electrical Characteristics and Timing Specifications A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 Introduction ....................................................................................................................................293 Parameter Classification.................................................................................................................293 Absolute Maximum Ratings...........................................................................................................293 Thermal Characteristics..................................................................................................................294 ESD Protection and Latch-Up Immunity .......................................................................................296 DC Characteristics..........................................................................................................................297 Supply Current Characteristics.......................................................................................................301 ADC Characteristics.......................................................................................................................304 Internal Clock Generation Module Characteristics ........................................................................307 A.9.1 ICG Frequency Specifications .........................................................................................308 A.10 AC Characteristics..........................................................................................................................311 MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 17 Section Number Title Page A.10.1 Control Timing ................................................................................................................311 A.10.2 Timer/PWM (TPM) Module Timing ...............................................................................312 A.11 SPI Characteristics .........................................................................................................................314 A.12 FLASH Specifications....................................................................................................................316 A.13 EMC Performance..........................................................................................................................317 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................319 B.2 Orderable Part Numbering System ................................................................................................320 B.3 Mechanical Drawings.....................................................................................................................321 MC9S08AC16 Series Data Sheet, Rev. 8 18 Freescale Semiconductor Chapter 1 Introduction 1.1 Overview The MC9S08AC16 Series devices are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for memory sizes and package types. • • NOTE The MC9S08AC16 and MC9S08AC8 devices are qualified for, and are intended to be used in, consumer and industrial applications. The MC9S08AW16A and MC9S08AW8A devices are qualified for, and are intended to be used in, automotive applications. Table 1-1 summarizes the feature set available in the MCUs. MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 19 Chapter 1 Introduction Table 1-1. Features by MCU and Package Consumer and Industrial “AC” Devices Feature FLASH size (bytes) RAM size (bytes) Pin quantity ADC channels TPM1 channels TPM2 channels TPM3 channels KBI pins GPIO pins Consumer & Industrial Qualified Automotive Qualified 1 MC9S08AC16 16K 1024 MC9S08AC8 8K 768 48 8 4 2 2 7 38 44 8 4 2 2 6 34 yes no 42 8 4 2 2 6 32 32 6 4 2 2 4 22 48 8 4 2 2 7 38 44 8 4 2 2 6 34 yes no 42 8 4 2 2 6 32 32 6 4 2 2 4 22 Automotive “AW” Devices Feature FLASH size (bytes) RAM size (bytes) Pin quantity ADC channels TPM1 channels1 TPM2 channels TPM3 channels KBI pins GPIO pins Consumer & Industrial Qualified Automotive Qualified 1 MC9S08AW16A 16K 1024 MC9S08AW8A 8K 768 48 8 4 2 2 7 38 44 8 4 2 2 6 34 no yes 32 6 4 2 2 4 22 48 8 4 2 2 7 38 44 8 4 2 2 6 34 no yes 32 6 4 2 2 4 22 There are 4 channels on TPM1 but two of them (TPM1CH2 and TPM1CH3) are not bonded to 32-pin LQFP package. These two channels can be used for soft timer function. 1.2 MCU Block Diagrams The block diagram shows the structure of the MC9S08AC16 Series MCU. MC9S08AC16 Series Data Sheet, Rev. 8 20 Freescale Semiconductor Chapter 1 Introduction VDDAD VSSAD VREFL VREFH HCS08 CORE BKGD/MS BDC CPU 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) DEBUG MODULE (DBG) 4 AD1P11–AD1P8 PORT A 4 AD1P3–AD1P0 PTA7 PTA2 PTA1 PTA0 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD3/KBIP6/AD1P11 PTD2/KBIP5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 SDA1 IIC MODULE (IIC1) SCL1 PORT C PORT D RESET IRQ/TPMCLK HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR 7-BIT KEYBOARD INTERRUPT MODULE (KBI) EXTAL XTAL 2 KBIP6–KBIP5 5 KBIP4–KBIP0 RxD1 TxD1 RxD2 TxD2 SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CH3 TPM1CH2 TPM2CH1 TPM2CH0 TPM3CH1 TPM3CH0 TPMCLK SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) SERIAL PERIPHERAL INTERFACE MODULE (SPI1) PORT B USER FLASH 16,384 BYTES OR 8192 BYTES PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 PTE1/RxD1 PTE0/TxD1 USER RAM 1024 BYTES OR 768 BYTES VDD VSS VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) PORT F 4-CHANNEL TIMER/PWM MODULE (TPM1) PORT E PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 PTF1/TPM1CH3 PTF0/TPM1CH2 = Not available on 32-, 42-, or 44-pin packages = Not available on 32- or 42-pin packages = Not available on 32-pin packages Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. PTD3, PTD2, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Figure 1-1. MC9S08AC16 Block Diagram MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 21 PORT G 2-CHANNEL TIMER/PWM MODULE (TPM3) PTG6/EXTAL PTG5/XTAL PTG4/KBIP4 PTG3/KBIP3 PTG2/KBIP2 PTG1/KBIP1 PTG0/KBIP0 Chapter 1 Introduction Table 1-2 lists the functional versions of the on-chip modules. Table 1-2. Versions of On-Chip Modules Module Analog-to-Digital Converter Internal Clock Generator Inter-Integrated Circuit Keyboard Interrupt Serial Communications Interface Serial Peripheral Interface Timer Pulse-Width Modulator Central Processing Unit (ADC) (ICG) (IIC) (KBI) (SCI) (SPI) (TPM) (CPU) Version 1 4 2 1 4 3 3 2 1.3 System Clock Distribution SYSTEM CONTROL LOGIC RTI TPMCLK ICGERCLK FFE TPM1 TPM2 IIC1 SCI1 SCI2 SPI1 ³2 ICG XCLK** COP ICGOUT ICGLCLK* ³2 BUSCLK 1 kHz CPU BDC TPM3 ADC1 RAM FLASH FLASH has frequency requirements for program and erase operation. See the Electricals appendix. * ICGLCLK is the alternate BDC clock source for the MC9S08AC16 Series. ** XCLK is the fixed-frequency clock. ADC has min and max frequency requirements. See the Electricals appendix and the ADC chapter. Figure 1-2. System Clock Distribution Diagram Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module MC9S08AC16 Series Data Sheet, Rev. 8 22 Freescale Semiconductor Chapter 1 Introduction • • • — Control bits inside the ICG determine which source is connected. FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2. Otherwise the fixed-frequency clock will be BUSCLK. ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. Can also be used as the ALTCLK input to the ADC module. MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 23 Chapter 1 Introduction MC9S08AC16 Series Data Sheet, Rev. 8 24 Freescale Semiconductor Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment 37 PTG4/KB1IP4 PTA2 24 42 PTG6/EXTAL 46 PTC2/MCLK Figure 2-1 shows the 48-pin QFN pin assignments for the MC9S08AC16 Series device. 45 PTC1/SDA1 41 PTG5/XTAL 48 PTC5/RxD2 44 PTC0/SCL1 47 PTC3/TxD2 40 BKGD/MS 38 VREFH PTA1 23 39 VREFL 43 VSS PTC4 1 IRQ/TPMCLK 2 RESET 3 PTF0/TPM1CH2 4 PTF1/TPM1CH3 5 PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 PTF6 8 PTE0/TxD1 9 PTE1/RxD1 10 PTE2/TPM1CH0 11 PTE3/TPM1CH1 12 PTE4/SS1 13 PTE5/MISO1 14 PTE6/MOSI1 15 PTE7/SPSCK1 16 VSS 17 36 PTG3/KBIP3 35 PTD3/KBIP6/AD1P11 34 PTD2/KBIP5/AD1P10 33 VSSAD 32 VDDAD 48-Pin QFN 31 PTD1/AD1P9 30 PTD0/AD1P8 29 PTB3/AD1P3 28 PTB2/AD1P2 27 PTB1/TPM3CH1/AD1P1 26 PTB0/TPM3CH0/AD1P0 25 PTA7 VDD 18 PTG0/KBIP0 19 PTG1/KBIP1 20 PTG2/KBIP2 21 Figure 2-1. MC9S08AC16 Series in 48-Pin QFN Package MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 25 PTA0 22 Chapter 2 Pins and Connections Figure 2-2. shows the 44-pin LQFP pin assignments for the MC9S08AC16 Series device. PTC2/MCLK PTG6/EXTAL PTC5/RxD2 PTC1/SDA1 PTC3/TxD2 PTG5/XTAL PTC0/SCL1 BKGD/MS 44 PTC4 1 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 11 13 12 PTE4/SS1 PTE7/SPSCK1 VSS VDD PTG0/KBIP0 PTG1/KBIP1 PTG2/KBIP2 PTA0 PTE5/MISO1 PTE6/MOSI1 14 15 16 17 18 19 20 21 2 3 4 5 6 7 8 9 10 43 42 41 40 39 38 37 36 35 VREFH 34 33 PTG3/KBIP3 32 31 30 29 PTD3/KBIP6/AD1P11 PTD2/KBIP5/AD1P10 VSSAD VDDAD PTD1/AD1P9 PTD0/AD1P8 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 23 PTB0/TPM3CH0/AD1P0 22 PTA1 28 27 26 25 24 44-Pin LQFP Figure 2-2. MC9S08AC16 Series in 44-Pin LQFP Package MC9S08AC16 Series Data Sheet, Rev. 8 26 Freescale Semiconductor VREFL VSS Chapter 2 Pins and Connections Figure 2-3 shows the 42-pin SDIP pin assignments for the MC9S08AC16 Series device. PTC0/SCL1 PTC1/SDA1 PTC2/MCLK PTC3/TxD2 PTC5/RxD2 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTE7/SPSCK1 VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL VREFH PTG3/KBIP3 PTD3/KBIP6/AD1P11 PTD2/KBIP5/AD1P10 VSSAD VDDAD PTD1/AD1P9 PTD0/AD1P8 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTA0 PTG2/KBIP2 PTG1/KBIP1 PTG0/KBIP0 42-Pin SDIP 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Figure 2-3. MC9S08AC16 Series in 42-Pin SDIP Package MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 27 Chapter 2 Pins and Connections Figure 2-4 shows the 32-pin LQFP pin assignments for the MC9S08AC16 Series device. PTG6/EXTAL PTC1/SDA1 PTC0/SCL1 PTG5/XTAL BKGD/MS 32 IRQ/TPMCLK 1 RESET PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 2 3 4 5 6 7 8 10 9 PTE5/MISO1 PTE7/SPSCK1 VSS PTE4/SS1 VDD PTG0/KBIP0 PTE6/MOSI1 PTG1/KBIP1 11 12 13 14 15 16 31 30 29 28 27 26 25 23 22 24 PTD3/AD1P11/KBIP6 PTD2/AD1P10/KBIP5 VSSAD VDDAD PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 VREFH 21 20 19 18 17 32-Pin LQFP Figure 2-4. MC9S08AC16 Series in 32-Pin LQFP Package MC9S08AC16 Series Data Sheet, Rev. 8 28 Freescale Semiconductor VREFL VSS Chapter 2 Pins and Connections Table 2-1. Pin Availability by Package Pin-Count Pin Number 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 44 1 2 3 4 5 6 7 — 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 — 42 — 6 7 8 9 10 11 — 12 13 14 15 16 17 18 19 20 21 22 23 24 25 — — 32 Highest Alt 2 Pin Number 48 25 IRQ TPM1CH2 TPM1CH3 TPM2CH0 TPM2CH1 TxD1 RxD1 TPM1CH0 TPM1CH1 SS1 MISO1 MOSI1 SPSCK1 VSS VDD KBIP0 KBIP1 KBIP2 TPMCLK RESET 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 44 — 23 24 25 26 27 28 29 30 31 32 33 — 34 35 36 37 38 39 40 41 42 43 44 42 — 26 27 28 29 30 31 32 33 34 35 36 — 37 38 39 40 41 42 1 2 3 4 5 32 Highest Alt 2 — PTC4 1 2 — PTF0 — PTF1 3 4 5 6 7 8 9 PTF4 PTF5 PTE0 PTE1 PTE2 PTE3 PTE4 — PTA7 17 PTB0 18 PTB1 19 PTB2 20 PTB3 — PTD0 — PTD1 21 22 23 PTD2 24 PTD3 — PTG3 — PTG4 25 26 27 BKGD 28 PTG5 29 PTG6 30 31 PTC0 32 PTC1 — PTC2 — PTC3 — PTC5 MS XTAL EXTAL VSS SCL1 SDA1 MCLK TxD2 RxD2 KBIP4 VREFH VREFL AD1P10 AD1P11 TPM3CH0 TPM3CH1 AD1P2 AD1P3 AD1P8 AD1P9 VDDAD VSSAD KBIP5 KBIP6 KBIP3 AD1P0 AD1P1 — PTF6 10 PTE5 11 PTE6 12 PTE7 13 14 15 PTG0 16 PTG1 — PTG2 — PTA0 — PTA1 — PTA2 Table 2-2. Pin Function Reference Signal Function Port Pins Serial peripheral interface Keyboard interrupts Timer/PWM Inter-integrated circuit Serial communications interface Oscillator/clocking Analog-to-digital Power/core Reset and interrupts Example(s) PTAx, PTBx SS, MISO, MOSI, SPSCK KBIPx TCLK, TPMCHx SCL, SDA TxD, RxD EXTAL, XTAL ADPx BKGD/MS, VDD, VSS RESET, IRQ Reference Chapter 6, “Parallel Input/Output” Chapter 12, “Serial Peripheral Interface (S08SPIV3)” Chapter 9, “Keyboard Interrupt (S08KBIV1)” Chapter 10, “Timer/PWM (S08TPMV3)” Chapter 13, “Inter-Integrated Circuit (S08IICV2)” Chapter 11, “Serial Communications Interface (S08SCIV4)” Chapter 8, “Internal Clock Generator (S08ICGV4)” Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” Chapter 2, “Pins and Connections” Chapter 5, “Resets, Interrupts, and System Configuration” MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 29 Chapter 2 Pins and Connections 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08AC16 Series application systems. MC9S08AC16 Series Data Sheet, Rev. 8 30 Freescale Semiconductor Chapter 2 Pins and Connections VREFH CBYAD 0.1 μF SYSTEM POWER + 5V VDD CBLK + 10 μF VDDAD MC9S08AC16 PTA0 VSSAD VREFL VDD CBY 0.1 μF VSS (x2) PORT A PTA1 PTA2 PTA7 PTB0/AD1P0/TPM3CH0 PORT B PTB1/AD1P1/TPM3CH1 PTB2/AD1P2 PTB3/AD1P3 NOTE 1 RF C1 X1 C2 RS XTAL NOTE 2 EXTAL NOTE 2 PORT C PTC0/SCL1 PTC1/SDA1 PTC2/MCLK PTC3/TxD2 PTC4 PTC5/RxD2 I/O AND PERIPHERAL INTERFACE TO APPLICATION BACKGROUND HEADER VDD BKGD/MS VDD 4.7 kΩ–10 kΩ 0.1 μF OPTIONAL MANUAL RESET RESET NOTE 3 PORT D PTD0/AD1P8 PTD1/AD1P9 PTD2/AD1P10/KBIP5 PTD3/AD1P11/KBIP6 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PORT E PTE3/TPM1CH1 PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTE7/SPSCK1 PTF0/TPM1CH2 PORT F PTF1/TPM1CH3 PTF4/TPM2CH0 PTF5/TPM2CH1 PTF6 SYSTEM VDD 4.7 kΩ– 10 kΩ 0.1 μF ASYNCHRONOUS INTERRUPT INPUT TPMCLK/IRQ NOTE 3 PTG0/KBIP0 PTG1/KBIP1 PTG2/KBIP2 PTG3/KBIP3 PTG4/KBIP4 PTG5/XTAL PTG6/EXTAL PORT G NOTES: 1. Not required if using the internal clock option. 2. XTAL and EXTAL are PTG5 and PTG6 respectively. 3. RC filters on RESET and IRQ are recommended for EMC-sensitive applications. Figure 2-5. Basic System Connections MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 31 Chapter 2 Pins and Connections 2.3.1 Power (VDD, 2 x VSS, VDDAD, VSSAD) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the paired VDD and VSS power pins as practical to suppress high-frequency noise. The MC9S08AC16 has a second VSS pin. This pin should be connected to the system ground plane or to the primary VSS pin through a low-impedance connection. VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to the ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the analog power pins as practical to suppress high-frequency noise. 2.3.2 Oscillator (XTAL, EXTAL) Out of reset the MCU uses an internally generated clock (self-clocked mode — fSelf_reset) equivalent to about 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, see the Chapter 8, “Internal Clock Generator (S08ICGV4).” The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin. Refer to Figure 2-5 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 which are usually the same size. As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.3.3 RESET RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make MC9S08AC16 Series Data Sheet, Rev. 8 32 Freescale Semiconductor Chapter 2 Pins and Connections external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 bus cycles. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS). In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-5 for an example. 2.3.4 Background/Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset which forces the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.3.5 ADC Reference Pins (VREFH, VREFL) The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs respectively for the ADC module. 2.3.6 External Interrupt Pin (IRQ) The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin does not perform any function. In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for an example. MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 33 Chapter 2 Pins and Connections 2.3.7 General-Purpose I/O and Peripheral Ports The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the appropriate chapter from Table 2-2. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. See the Chapter 6, “Parallel Input/Output” chapter for more details. Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTD3, PTD2, and PTG4 pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. NOTE When an alternative function is first enabled it is possible to get a spurious edge to the module, user software should clear out any associated flags before interrupts are enabled. Table 2-1 illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. It is recommended that all modules that share a pin be disabled before enabling another module. MC9S08AC16 Series Data Sheet, Rev. 8 34 Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08AC16 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • Features Active background mode for code development Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained Stop modes: — System clocks stopped; voltage regulator in standby — Stop2 — Partial power down of internal circuits, RAM contents retained — Stop3 — All internal circuits powered for fast recovery • 3.3 Run Mode This is the normal operating mode for the MC9S08AC16 Series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 35 Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08AC16 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer to Chapter 15, “Development Support.” 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In both stop modes, all internal clocks are halted. If the STOPE bit is not set when MC9S08AC16 Series Data Sheet, Rev. 8 36 Freescale Semiconductor Chapter 3 Modes of Operation the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08AC16 Series family of devices does not include stop1 mode. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1. Stop Mode Behavior CPU, Digital Peripherals, FLASH Off Standby Mode PPDC RAM ICG ADC Regulator I/O Pins RTI Stop2 Stop3 1 1 0 Standby Standby Off Off1 Disabled Optionally on Standby Standby States held States held Optionally on Optionally on Crystal oscillator can be configured to run in stop3. Please see the ICG registers. 3.6.1 Stop2 Mode The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. To enter stop2, the user must execute a STOP instruction with stop2 selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to operate in stop (LVDSE = LVDE = 1). If the LVD is enabled in stop, then the MCU enters stop3 upon the execution of the STOP instruction regardless of the state of PPDC. Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by user software before pin latches are opened. When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ADC. Upon entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a logic 1 is written to PPDACK in SPMSC2. Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ/TPMCLK, or by an RTI interrupt. IRQ/TPMCLK is always an active low input when the MCU is in stop2, regardless of how it was configured before entering stop2. Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 37 Chapter 3 Modes of Operation register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.2 Stop3 Mode To enter stop3, the user must execute a STOP instruction with stop3 selected (PPDC = 0) and stop mode enabled (STOPE = 1). Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The ICG enters its standby state, as does the voltage regulator and the ADC. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exit from stop3 is done by asserting RESET or by an interrupt from one of the following sources: the real-time interrupt (RTI), LVD system, ADC, IRQ, KBI, or SCI. If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector. A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. 3.6.3 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in Chapter 15, “Development Support” of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the background debug mode is enabled. MC9S08AC16 Series Data Sheet, Rev. 8 38 Freescale Semiconductor Chapter 3 Modes of Operation Table 3-2. BDM Enabled Stop Mode Behavior CPU, Digital Peripherals, FLASH Standby Mode PPDC RAM ICG ADC Regulator I/O Pins RTI Stop3 0 Standby Active Optionally on Active States held Optionally on 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the LVD is enabled. Table 3-3. LVD Enabled Stop Mode Behavior CPU, Digital Peripherals, FLASH Standby Mode PPDC RAM ICG ADC Regulator I/O Pins RTI Stop3 0 Standby Off Optionally on Active States held Optionally on 3.6.5 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop3 Mode” for specific information on system behavior in stop modes. I/O Pins • All I/O pin states remain unchanged when the MCU enters stop3 mode. • If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop. Memory • All RAM and register contents are preserved while the MCU is in stop3 mode. • All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and pin states remain latched until the PPDACK bit is written. The user may save any memory-mapped register data into RAM before entering stop2 and restore the data upon exit from stop2. • The contents of the FLASH memory are non-volatile and are preserved in any of the stop modes. ICG — In stop3 mode, the ICG enters its low-power standby state. The oscillator may be kept running when the ICG is in standby by setting OSCSTEN. In stop2 mode, the ICG is turned off. The oscillator cannot be kept running in stop2 even if OSCSTEN is set. If the MCU is configured to go into stop2 mode, the ICG will be reset upon wake-up from stop and must be reinitialized. MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 39 Chapter 3 Modes of Operation TPM — When the MCU enters stop mode, the clock to the TPM1 and TPM2 modules stop. The modules halt operation. If the MCU is configured to go into stop2 mode, the TPM modules will be reset upon wake-up from stop and must be reinitialized. ADC — When the MCU enters stop mode, the ADC will enter a low-power standby state unless the asynchronous clock source, ADACK, is enabled. Conversions can occur in stop3 if ADACK is enabled. If the MCU is configured to go into stop2 mode, the ADC will be reset upon wake-up from stop and must be re-initialized. KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources that are capable of waking the MCU from stop3. The KBI is disabled in stop2 and must be reinitialized after waking up. SCI — When the MCU enters stop mode, the clocks to the SCI1 and SCI2 modules stop. The modules halt operation. If the MCU is configured to go into stop2 mode, the SCI modules will be reset upon wake-up from stop and must be reinitialized. SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation. If the MCU is configured to go into stop2 mode, the SPI module will be reset upon wake-up from stop and must be reinitialized. IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation. If the MCU is configured to go into stop2 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters either of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. MC9S08AC16 Series Data Sheet, Rev. 8 40 Freescale Semiconductor Chapter 4 Memory 4.1 MC9S08AC16 Series Memory Map Figure 4-1 shows the memory maps for the MC9S08AC16 Series MCUs. On-chip memory in the MC9S08AC16 Series of MCU consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x006F) • High-page registers (0x1800 through 0x185F) • Nonvolatile registers (0xFFB0 through 0xFFBF) 0x0000 0x006F 0x0070 0x046F 0x0470 DIRECT PAGE REGISTERS RAM 1024 BYTES UNIMPLEMENTED 5008 BYTES 0x17FF 0x1800 HIGH PAGE REGISTERS 0x185F 0x1860 0x185F 0x1860 0x17FF 0x1800 HIGH PAGE REGISTERS 0x0000 0x006F 0x0070 0x036F 0x0370 0x046F 0x0470 DIRECT PAGE REGISTERS RAM 768 BYTES RESERVED — 256 BYTES UNIMPLEMENTED 5008 BYTES UNIMPLEMENTED 42,912 BYTES UNIMPLEMENTED 42,912 BYTES 0xBFFF 0xC000 FLASH 16,384 BYTES 0xBFFF 0xC000 0xDFFF 0xE000 RESERVED 8192 BYTES FLASH 8192 BYTES MC9S08AC8 and MC9S08AW8A 0xFFFF MC9S08AC16 and MC9S08AW16A 0xFFFF Figure 4-1. MC9S08AC16 Series Memory Maps MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 41 Chapter 4 Memory 4.1.1 Reset and Interrupt Vector Assignments Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08AC16 Series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1. Reset and Interrupt Vectors Address (High/Low) 0xFFC0:FFC1 through 0xFFC4:FFC5 0xFFC6:FFC7 0xFFC8:FFC9 0xFFCA:FFCB 0xFFCC:FFCD 0xFFCE:FFCF 0xFFD0:FFD1 0xFFD2:FFD3 0xFFD4:FFD5 0xFFD6:FFD7 0xFFD8:FFD9 0xFFDA:FFDB 0xFFDC:FFDD 0xFFDE:FFDF 0xFFE0:FFE1 0xFFE2:FFE3 0xFFE4:FFE5 0xFFE6:FFE7 0xFFE8:FFE9 0xFFEA:FFEB 0xFFEC:FFED 0xFFEE:FFEF 0xFFF0:FFF1 0xFFF2:FFF3 0xFFF4:FFF5 0xFFF6:FFF7 0xFFF8:FFF9 0xFFFA:FFFB 0xFFFC:FFFD 0xFFFE:FFFF Vector Unused Vector Space (available for user program) TPM3 overflow TPM3 channel 1 TPM3 channel 0 RTI IIC1 ADC1 Conversion KBI SCI2 Transmit SCI2 Receive SCI2 Error SCI1 Transmit SCI1 Receive SCI1 Error SPI1 TPM2 Overflow TPM2 Channel 1 TPM2 Channel 0 TPM1 Overflow Unused Unused TPM1 Channel 3 TPM1 Channel 2 TPM1 Channel 1 TPM1 Channel 0 ICG Low Voltage Detect IRQ SWI Reset Vector Name — Vtpm3ovf Vtpm3ch1 Vtpm3ch0 Vrti Viic1 Vadc1 Vkeyboard1 Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi1 Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf — — Vtpm1ch3 Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vswi Vreset MC9S08AC16 Series Data Sheet, Rev. 8 42 Freescale Semiconductor Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08AC16 Series are divided into these three groups: • Direct-page registers are located in the first 112 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — Three values which are loaded into working registers at reset — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 43 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 PTAD7 PTADD7 R R 0 0 R R PTED7 PTEDD7 R R 0 0 — — COCO ADACT 0 ADR7 0 ADCV7 ADLPC ADPC7 ADPC15 ADPC23 — — 0 — 0 0 TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 6 R R R R R R R R PTED6 PTEDD6 PTFD6 PTFDD6 PTGD6 PTGDD6 — — AIEN ADTRG 0 ADR6 0 ADCV6 ADPC6 ADPC14 ADPC22 — — IRQPDD — KBEDG6 KBIPE6 TOIE 14 6 14 6 CH0IE 14 6 ADIV ADPC5 ADPC13 ADPC21 — — IRQEDG — KBEDG5 KBIPE5 CPWMS 13 5 13 5 MS0B 13 5 5 R R R R PTCD5 PTCDD5 R R PTED5 PTEDD5 PTFD5 PTFDD5 PTGD5 PTGDD5 — — ADCO ACFE 0 ADR5 0 ADCV5 ACFGT 0 ADR4 0 ADCV4 ADLSMP ADPC4 ADPC12 ADPC20 — — IRQPE — KBEDG4 KBIPE4 CLKSB 12 4 12 4 MS0A 12 4 0 0 ADR3 0 ADCV3 ADPC3 ADPC11 ADPC19 — — IRQF — KBF KBIPE3 CLKSA 11 3 11 3 ELS0B 11 3 MODE ADPC2 ADPC10 ADPC18 — — IRQACK — KBACK KBIPE2 PS2 10 2 10 2 ELS0A 10 2 4 R R R R PTCD4 PTCDD4 R R PTED4 PTEDD4 PTFD4 PTFDD4 PTGD4 PTGDD4 — — 3 R R PTBD3 PTBDD3 PTCD3 PTCDD3 PTDD3 PTDDD3 PTED3 PTEDD3 R R PTGD3 PTGDD3 — — 2 PTAD2 PTADD2 PTBD2 PTBDD2 PTCD2 PTCDD2 PTDD2 PTDDD2 PTED2 PTEDD2 R R PTGD2 PTGDD2 — — ADCH 0 0 ADR2 0 ADCV2 R ADR9 ADR1 ADCV9 ADCV1 ADPC1 ADPC9 ADPC17 — — IRQIE — KBIE KBIPE1 PS1 9 1 9 1 0 9 1 R ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 ADPC16 — — IRQMOD — KBIMOD KBIPE0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 1 PTAD1 PTADD1 PTBD1 PTBDD1 PTCD1 PTCDD1 PTDD1 PTDDD1 PTED1 PTEDD1 PTFD1 PTFDD1 PTGD1 PTGDD1 — — Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 PTDD0 PTDDD0 PTED0 PTEDD0 PTFD0 PTFDD0 PTGD0 PTGDD0 — — 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E– 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A– 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 PTAD PTADD PTBD PTBDD PTCD PTCDD PTDD PTDDD PTED PTEDD PTFD PTFDD PTGD PTGDD Reserved ADC1SC1 ADC1SC2 ADC1RH ADC1RL ADC1CVH ADC1CVL ADC1CFG APCTL1 APCTL2 APCTL3 Reserved IRQSC Reserved KBISC KBIPE TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL ADICLK MC9S08AC16 Series Data Sheet, Rev. 8 44 Freescale Semiconductor Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 CH1F Bit 15 Bit 7 CH2F Bit 15 Bit 7 CH3F Bit 15 Bit 7 — LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 HGO LOLRE CLKST 0 0 0 0 6 CH1IE 14 6 CH2IE 14 6 CH3IE 14 6 — RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 RANGE 5 MS1B 13 5 MS2B 13 5 MS3B 13 5 — 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 REFS MFD REFST 0 0 LOLS 0 0 FLT TRIM — SPIE 0 0 SPRF Bit 7 — SPE 0 SPPR2 0 6 — SPTIE 0 SPPR1 SPTEF 5 — MSTR MODFEN SPPR0 MODF 4 — CPOL BIDIROE 0 0 3 — CPHA 0 SPR2 0 2 — SSOE SPISWAI SPR1 0 1 — LSBFE SPC0 SPR0 0 Bit 0 4 MS1A 12 4 MS2A 12 4 MS3A 12 4 — SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 CLKS LOCRE LOCK 0 LOCS 0 FLT 3 ELS1B 11 3 ELS2B 11 3 ELS3B 11 3 — SBR11 SBR3 WAKE TE OR RWUID ORIE 3 SBR11 SBR3 WAKE TE OR RWUID ORIE 3 2 ELS1A 10 2 ELS2A 10 2 ELS3A 10 2 — SBR10 SBR2 ILT RE NF BRK13 NEIE 2 SBR10 SBR2 ILT RE NF BRK13 NEIE 2 OSCSTEN 1 0 9 1 0 9 1 0 9 1 — SBR9 SBR1 PE RWU FE LBKDE FEIE 1 SBR9 SBR1 PE RWU FE LBKDE FEIE 1 LOCD RFD ERCS 0 ICGIF DCOS Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 0 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031– 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 TPM1C1SC TPM1C1VH TPM1C1VL TPM1C2SC TPM1C2VH TPM1C2VL TPM1C3SC TPM1C3VH TPM1C3VL Reserved SCI1BDH SCI1BDL SCI1C1 SCI1C2 SCI1S1 SCI1S2 SCI1C3 SCI1D SCI2BDH SCI2BDL SCI2C1 SCI2C2 SCI2S1 SCI2S2 SCI2C3 SCI2D ICGC1 ICGC2 ICGS1 ICGS2 ICGFLTU ICGFLTL ICGTRM Reserved SPI1C1 SPI1C2 SPI1BR SPI1S SPI1D MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 45 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 — — AD7 MULT IICEN TCF GCAEN — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — — IICIE IAAS ADEXT — — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — — MST BUSY 0 — — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — — TX ARBL DATA 0 — — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — — 0 — — CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — — AD10 — — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — — AD9 — — PS1 9 1 9 1 0 9 1 0 9 1 — — AD8 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — TXAK 0 6 — — AD6 5 — — AD5 4 — — AD4 3 — — AD3 ICR RSTA SRW 0 IICIF 0 RXAK 2 — — AD2 1 — — AD1 Bit 0 — — 0 0x0055– 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E– 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B– 0x006F Reserved IIC1A IIC1F IIC1C1 IIC1S IIC1D IIC1C2 Reserved TPM2SC TPM2CNTH TPM2CNTL TPM2MODH TPM2MODL TPM2C0SC TPM2C0VH TPM2C0VL TPM2C1SC TPM2C1VH TPM2C1VL Reserved High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table 4-3. High-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 POR 0 COPE 0 — — REV3 ID7 RTIF LVDF LVWF — 6 PIN 0 COPT 0 — — REV2 ID6 RTIACK LVDACK LVWACK — 5 COP 0 STOPE 0 — — REV1 ID5 RTICLKS LVDIE LVDV — 4 ILOP 0 — MPE — — REV0 ID4 RTIE LVDRE LVWV — 3 ILAD 0 0 0 — — ID11 ID3 0 LVDSE PPDF — — — ID10 ID2 RTIS2 LVDE PPDACK — 2 ICG 0 0 1 LVD 0 — MCSEL — — ID9 ID1 RTIS1 01 — — — — ID8 ID0 RTIS0 BGBE PPDC — Bit 0 0 BDFR — 0x1800 0x1801 0x1802 0x1803 0x1804 – 0x1805 0x1806 0x1807 0x1808 0x1809 0x180A 0x180B SRS SBDFR SOPT SMCLK Reserved SDIDH SDIDL SRTISC SPMSC1 SPMSC2 Reserved MC9S08AC16 Series Data Sheet, Rev. 8 46 Freescale Semiconductor Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 COPCLKS — — Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 DBGEN TRGSEL AF — — DIVLD KEYEN — 0 FPS7 FCBEF FCMD7 — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — — PTAPE7 PTASE7 PTADS7 — 6 — — — 14 6 14 6 14 6 ARM BEGIN BF — — PRDIV8 FNORED — 0 FPS6 FCCF FCMD6 — — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — — R R R — 5 — — — 13 5 13 5 13 5 TAG 0 ARMF — — DIV5 0 — KEYACC FPS5 FPVIOL FCMD5 — — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — — R R R — 4 — — — 12 4 12 4 12 4 BRKEN 0 0 — — DIV4 0 — 0 FPS4 FACCERR FCMD4 — — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — — R R R — 3 — — — 11 3 11 3 11 3 RWA TRG3 CNT3 — — DIV3 0 — 0 FPS3 0 FCMD3 — — CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — — R R R — 2 — — — 10 2 10 2 10 2 RWAEN TRG2 CNT2 — — DIV2 0 — 0 FPS2 FBLANK FCMD2 — — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — — PTAPE2 PTASE2 PTADS2 — 1 — — — 9 1 9 1 9 1 RWB TRG1 CNT1 — — DIV1 SEC01 — 0 FPS1 0 FCMD1 — — PS1 9 1 9 1 0 9 1 0 9 1 — — PTAPE1 PTASE1 PTADS1 — Bit 0 — — — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 RWBEN TRG0 CNT0 — — DIV0 SEC00 — 0 FPDIS 0 FCMD0 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — PTAPE0 PTASE0 PTADS0 — 0x180C 0x180D– 0x180F 0x1810 0x1811 0x1812 0x1813 0x1814 0x1815 0x1816 0x1817 0x1818 0x1819– 0x181F 0x1820 0x1821 0x1822 0x1823 0x1824 0x1825 0x1826 0x1827– 0x182F 0x1830 0x1831 0x1832 0x1833 0x1834 0x1835 0x1836 0x1837 0x1838 0x1839 0x183A 0x183B 0x183F 0x1840 0x1841 0x1842 0x1843 SOPT2 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL DBGC DBGT DBGS Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Reserved TPM3SC TPM3CNTH TPM3CNTL TPM3MODH TPM3MODL TPM3C0SC TPM3C0VH TPM3C0VL TPM3C1SC TPM3C1VH TPM3C1VL Reserved PTAPE PTASE PTADS Reserved MC9S08AC16 Series Data Sheet, Rev. 8 Freescale Semiconductor 47 Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 R R R — 0 0 0 — R R R — PTEPE7 PTESE7 PTEDS7 — R R R — 0 0 0 — — 6 R R R — R R R — R R R — PTEPE6 PTESE6 PTEDS6 — PTFPE6 PTFSE6 PTFDS6 — PTGPE6 PTGSE6 PTGDS6 — — 5 R R R — PTCPE5 PTCSE5 PTCDS5 — R R R — PTEPE5 PTESE5 PTEDS5 — PTFPE5 PTFSE5 PTFDS5 — PTGPE5 PTGSE5 PTGDS5 — — 4 R R R — PTCPE4 PTCSE4 PTCDS4 — R R R — PTEPE4 PTESE4 PTEDS4 — PTFPE4 PTFSE4 PTFDS4 — PTGPE4 PTGSE4 PTGDS4 — — 3 PTBPE3 PTBSE3 PTBDS3 — PTCPE3 PTCSE3 PTCDS3 — PTDPE3 PTDSE3 PTDDS3 — PTEPE3 PTESE3 PTEDS3 — R R R — PTGPE3 PTGSE3 PTGDS3 — — 2 PTBPE2 PTBSE2 PTBDS2 — PTCPE2 PTCSE2 PTCDS2 — PTDPE2 PTDSE2 PTDDS2 — PTEPE2 PTESE2 PTEDS2 — R R R — PTGPE2 PTGSE2 PTGDS2 — — 1 PTBPE1 PTBSE1 PTBDS1 — PTCPE1 PTCSE1 PTCDS1 — PTDPE1 PTDSE1 PTDDS1 — PTEPE1 PTESE1 PTEDS1 — PTFPE1 PTFSE1 PTFDS1 — PTGPE1 PTGSE1 PTGDS1 — — Bit 0 PTBPE0 PTBSE0 PTBDS0 — PTCPE0 PTCSE0 PTCDS0 — PTDPE0 PTDSE0 PTDDS0 — PTEPE0 PTESE0 PTEDS0 — PTFPE0 PTFSE0 PTFDS0 — PTGPE0 PTGSE0 PTGDS0 — — 0x1844 0x1845 0x1846 0x1847 0x1848 0x1849 0x184A 0x184B 0x184C 0x184D 0x184E 0x184F 0x1850 0x1851 0x1852 0x1853 0x1854 0x1855 0x1856 0x1857 0x1858 0x1859 0x185A 0x185B– 0x185F 1 PTBPE PTBSE PTBDS Reserved PTCPE PTCSE PTCDS Reserved PTDPE PTDSE PTDDS Reserved PTEPE PTESE PTEDS Reserved PTFPE PTFSE PTFDS Reserved PTGPE PTGSE PTGDS Reserved This reserved bit must always be written to 0. Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. MC9S08AC16 Series Data Sheet, Rev. 8 48 Freescale Semiconductor Chapter 4 Memory Table 4-4. Nonvolatile Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0xFFB0 – NVBACKKEY 0xFFB7 0xFFB8 – Reserved 0xFFBB 0xFFBC Reserved for storage of 250 kHz ICGTRM value NVPROT Reserved for storage of 243 kHz ICGTRM value NVOPT — — — FPS7 — KEYEN — — — FPS6 — FNORED — — — FPS5 — 0 8-Byte Comparison Key — — — FPS4 — 0 — — — FPS3 — 0 — — — FPS2 — 0 — — — FPS1 — SEC01 — — — FPDIS — SEC00 0xFFBD 0xFFBE 0xFFBF Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08AC16 Series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08AC16 Series, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP