MC9S08DZ48

MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16 Data Sheet: Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice. HCS08 Microcontrollers MC9S08DZ60 Rev. 1 Draft E 6/2006 freescale.com PRELIMINARY MC9S08DZ60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (20-MHz bus) • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources Peripherals • ADC — 24-channel, 10-bit resolution, 2.5 µs conversion time, automatic compare function, 1.7 mV/°C temperature sensor, internal bandgap reference channel • ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage • MSCAN — CAN protocol - Version 2.0 A, B; standard and extended data frames; Support for remote frames; Five receive buffers with FIFO storage scheme; Flexible identifier acceptance filters programmable as: 2 x 32-bit, 4 x 16-bit, or 8 x 8-bit • SCIx — Two SCIs supporting LIN 2.0 Protocol and SAE J2602 protocols; Full duplex non-return to zero (NRZ); Master extended break generation; Slave extended break detection; Wakeup on active edge • SPI — Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting • IIC — Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; General Call Address; Interrupt driven byte-by-byte data transfer • TPMx — One 6-channel (TPM1) and one 2-channel (TPM2); Selectable input capture, output compare, or buffered edge-aligned PWM on each channel • RTC — (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; Real-time clock capabilities using external crystal and RTC for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components On-Chip Memory • FLASH read/program/erase over full operating voltage and temperature — MC9S08DZ60 = 60K — MC9S08DZ48 = 48K — MC9S08DZ32 = 32K — MC9S08DZ16 = 16K • Up to 2K EEPROM in-circuit programmable memory; 8-byte single-page or 4-byte dual-page erase sector; Program and Erase while executing FLASH; Erase abort • Up to 4K random-access memory (RAM) Power-Saving Modes • Two very low power stop modes • Reduced power wait mode • Very low power real time interrupt for use in run, wait, and stop Clock Source Options • Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz • Multi-purpose Clock Generator (MCG) — PLL and FLL modes; Internal reference clock with trim adjustment; External reference with oscillator/resonator options System Protection • Watchdog computer operating properly (COP) reset with option to run from backup dedicated 1-kHz internal clock source or bus clock • Low-voltage detection with reset or interrupt; selectable trip points • Illegal opcode detection with reset • Illegal address detection with reset • FLASH block protect • Loss-of-lock protection Input/Output • 53 general-purpose input/output (I/O) pins and 1 input-only pin • 24 interrupt pins with selectable polarity on each pin • Hysteresis and configurable pull device on all input pins. • Configurable slew rate and drive strength on all output pins. Package Options • • • • 64-pin low-profile quad flat-pack (LQFP) — 10x10 mm 64-pin quad flat-pack no lead (QFN) — 9x9 mm 48-pin low-profile quad flat-pack (LQFP) — 7x7 mm 32-pin low-profile quad flat-pack (LQFP) — 7x7 mm Development Support • Single-wire background debug interface • On-chip, in-circuit emulation (ICE) with real-time bus capture MC9S08DZ60 Data Sheet Covers MC9S08DZ60 MC9S08DZ48 MC9S08DZ32 MC9S08DZ16 MC9S08DZ60 Rev. 1 Draft E 6/2006 This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved. PRELIMINARY Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number 1 Draft E Revision Date 06/28/2006 Description of Changes Advance Information for alpha samples customers © Freescale Semiconductor, Inc., 2006. All rights reserved. This product incorporates SuperFlash® Technology licensed from SST. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 6 PRELIMINARY Freescale Semiconductor List of Chapters Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Appendix A Appendix B Device Overview .............................................................................. 19 Pins and Connections ..................................................................... 25 Modes of Operation ......................................................................... 33 Memory ............................................................................................. 39 Resets, Interrupts, and General System Control.......................... 67 Parallel Input/Output Control.......................................................... 83 Central Processor Unit (S08CPUV3) ............................................ 111 Multi-Purpose Clock Generator (S08MCGV1) ............................. 131 Analog Comparator (S08ACMPV3) .............................................. 159 Analog-to-Digital Converter (S08ADCV1).................................... 167 Inter-Integrated Circuit (S08IICV2) ............................................... 195 Freescale’s Controller Area Network (S08MSCANV1) ............... 215 Serial Peripheral Interface (S08SPIV3) ........................................ 269 Serial Communications Interface (S08SCIV4)............................. 287 Real-Time Counter (S08RTCV1) ................................................... 307 Timer Pulse-Width Modulator (S08TPMV2) ................................. 317 Development Support ................................................................... 333 Electrical Characteristics.............................................................. 357 Ordering Information and Mechanical Drawings........................ 383 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 7 Contents Section Number Title Chapter 1 Device Overview 1.1 1.2 1.3 Devices in the MC9S08DZ60 Series ...............................................................................................19 MCU Block Diagram ......................................................................................................................20 System Clock Distribution ..............................................................................................................22 Page Chapter 2 Pins and Connections 2.1 2.2 Device Pin Assignment ...................................................................................................................25 Recommended System Connections ...............................................................................................28 2.2.1 Power ................................................................................................................................29 2.2.2 Oscillator ...........................................................................................................................29 2.2.3 RESET ..............................................................................................................................29 2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................30 2.2.5 ADC Reference Pins (VREFH, VREFL) ..............................................................................30 2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................30 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................33 Features ...........................................................................................................................................33 Run Mode ........................................................................................................................................33 Active Background Mode ................................................................................................................33 Wait Mode .......................................................................................................................................34 Stop Modes ......................................................................................................................................35 3.6.1 Stop3 Mode .......................................................................................................................35 3.6.2 Stop2 Mode .......................................................................................................................36 3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................37 Chapter 4 Memory 4.1 4.2 4.3 4.4 4.5 MC9S08DZ60 Series Memory Map ...............................................................................................39 Reset and Interrupt Vector Assignments .........................................................................................40 Register Addresses and Bit Assignments ........................................................................................41 RAM ................................................................................................................................................49 FLASH and EEPROM ....................................................................................................................49 4.5.1 Features .............................................................................................................................49 4.5.2 Program and Erase Times .................................................................................................50 4.5.3 Program and Erase Command Execution .........................................................................50 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor Subject to Change 9 Section Number 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.5.10 4.5.11 Title Page Burst Program Execution ..................................................................................................52 Sector Erase Abort ............................................................................................................54 Access Errors ....................................................................................................................55 Block Protection ................................................................................................................56 Vector Redirection ............................................................................................................56 Security .............................................................................................................................56 EEPROM Mapping ...........................................................................................................58 FLASH and EEPROM Registers and Control Bits ...........................................................58 Chapter 5 Resets, Interrupts, and General System Control 5.1 5.2 5.3 5.4 5.5 Introduction .....................................................................................................................................67 Features ...........................................................................................................................................67 MCU Reset ......................................................................................................................................67 Computer Operating Properly (COP) Watchdog .............................................................................68 Interrupts .........................................................................................................................................69 5.5.1 Interrupt Stack Frame .......................................................................................................70 5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................70 5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................71 Low-Voltage Detect (LVD) System ................................................................................................73 5.6.1 Power-On Reset Operation ...............................................................................................73 5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................73 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................73 MCLK Output .................................................................................................................................73 Reset, Interrupt, and System Control Registers and Control Bits ...................................................74 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................75 5.8.2 System Reset Status Register (SRS) .................................................................................76 5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................77 5.8.4 System Options Register 1 (SOPT1) ................................................................................78 5.8.5 System Options Register 2 (SOPT2) ................................................................................79 5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................80 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................81 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................82 5.6 5.7 5.8 Chapter 6 Parallel Input/Output Control 6.1 6.2 6.3 Port Data and Data Direction ..........................................................................................................83 Pull-up, Slew Rate, and Drive Strength ...........................................................................................84 Pin Interrupts ...................................................................................................................................85 6.3.1 Edge Only Sensitivity .......................................................................................................85 6.3.2 Edge and Level Sensitivity ................................................................................................85 6.3.3 Pull-up/Pull-down Resistors .............................................................................................86 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 10 Subject to Change Freescale Semiconductor Section Number 6.4 6.5 Title Page 6.3.4 Pin Interrupt Initialization .................................................................................................86 Pin Behavior in Stop Modes ............................................................................................................86 Parallel I/O and Pin Control Registers ............................................................................................86 6.5.1 Port A Registers ................................................................................................................87 6.5.2 Port B Registers ................................................................................................................91 6.5.3 Port C Registers ................................................................................................................95 6.5.4 Port D Registers ................................................................................................................98 6.5.5 Port E Registers ...............................................................................................................102 6.5.6 Port F Registers ...............................................................................................................105 6.5.7 Port G Registers ..............................................................................................................108 Chapter 7 Central Processor Unit (S08CPUV3) 7.1 7.2 Introduction ...................................................................................................................................111 7.1.1 Features ...........................................................................................................................111 Programmer’s Model and CPU Registers .....................................................................................112 7.2.1 Accumulator (A) .............................................................................................................112 7.2.2 Index Register (H:X) .......................................................................................................112 7.2.3 Stack Pointer (SP) ...........................................................................................................113 7.2.4 Program Counter (PC) ....................................................................................................113 7.2.5 Condition Code Register (CCR) .....................................................................................113 Addressing Modes .........................................................................................................................115 7.3.1 Inherent Addressing Mode (INH) ...................................................................................115 7.3.2 Relative Addressing Mode (REL) ...................................................................................115 7.3.3 Immediate Addressing Mode (IMM) ..............................................................................115 7.3.4 Direct Addressing Mode (DIR) ......................................................................................115 7.3.5 Extended Addressing Mode (EXT) ................................................................................116 7.3.6 Indexed Addressing Mode ..............................................................................................116 Special Operations .........................................................................................................................117 7.4.1 Reset Sequence ...............................................................................................................117 7.4.2 Interrupt Sequence ..........................................................................................................117 7.4.3 Wait Mode Operation ......................................................................................................118 7.4.4 Stop Mode Operation ......................................................................................................118 7.4.5 BGND Instruction ...........................................................................................................119 HCS08 Instruction Set Summary ..................................................................................................120 7.3 7.4 7.5 Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) 8.1 Introduction ...................................................................................................................................131 8.1.1 Features ...........................................................................................................................133 8.1.2 Modes of Operation ........................................................................................................135 External Signal Description ..........................................................................................................135 Register Definition ........................................................................................................................136 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor Subject to Change 11 8.2 8.3 Section Number Title Page 8.4 8.5 8.3.1 MCG Control Register 1 (MCGC1) ...............................................................................136 8.3.2 MCG Control Register 2 (MCGC2) ...............................................................................137 8.3.3 MCG Trim Register (MCGTRM) ...................................................................................138 8.3.4 MCG Status and Control Register (MCGSC) .................................................................139 8.3.5 MCG Control Register 3 (MCGC3) ...............................................................................140 Functional Description ..................................................................................................................142 8.4.1 Operational Modes ..........................................................................................................142 8.4.2 Mode Switching ..............................................................................................................146 8.4.3 Bus Frequency Divider ...................................................................................................146 8.4.4 Low Power Bit Usage .....................................................................................................146 8.4.5 Internal Reference Clock ................................................................................................147 8.4.6 External Reference Clock ...............................................................................................147 8.4.7 Fixed Frequency Clock ...................................................................................................147 Initialization / Application Information ........................................................................................148 8.5.1 MCG Module Initialization Sequence ............................................................................148 8.5.2 MCG Mode Switching ....................................................................................................149 8.5.3 Calibrating the Internal Reference Clock (IRC) .............................................................156 Chapter 9 Analog Comparator (S08ACMPV3) 9.1 Introduction ...................................................................................................................................159 9.1.1 ACMP Configuration Information ..................................................................................159 9.1.2 Features ...........................................................................................................................161 9.1.3 Modes of Operation ........................................................................................................161 9.1.4 Block Diagram ................................................................................................................161 External Signal Description ..........................................................................................................163 Register Definition ........................................................................................................................163 Functional Description ..................................................................................................................165 9.2 9.3 9.4 Chapter 10 Analog-to-Digital Converter (S08ADCV1) 10.1 Introduction ...................................................................................................................................167 10.1.1 Channel Assignments ......................................................................................................167 10.1.2 Analog Power and Ground Signal Names ......................................................................167 10.1.3 Alternate Clock ...............................................................................................................168 10.1.4 Hardware Trigger ............................................................................................................168 10.1.5 Temperature Sensor ........................................................................................................169 10.1.6 Features ...........................................................................................................................171 10.1.7 Block Diagram ................................................................................................................171 10.2 External Signal Description ..........................................................................................................172 10.2.1 Analog Power (VDDAD) ..................................................................................................173 10.2.2 Analog Ground (VSSAD) .................................................................................................173 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 12 Subject to Change Freescale Semiconductor Section Number Title Page 10.3 10.4 10.5 10.6 10.2.3 Voltage Reference High (VREFH) ...................................................................................173 10.2.4 Voltage Reference Low (VREFL) .....................................................................................173 10.2.5 Analog Channel Inputs (ADx) ........................................................................................173 Register Definition ........................................................................................................................173 10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................173 10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................175 10.3.3 Data Result High Register (ADCRH) .............................................................................176 10.3.4 Data Result Low Register (ADCRL) ..............................................................................176 10.3.5 Compare Value High Register (ADCCVH) ....................................................................177 10.3.6 Compare Value Low Register (ADCCVL) .....................................................................177 10.3.7 Configuration Register (ADCCFG) ................................................................................177 10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................179 10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................180 10.3.10Pin Control 3 Register (APCTL3) ..................................................................................181 Functional Description ..................................................................................................................182 10.4.1 Clock Select and Divide Control ....................................................................................182 10.4.2 Input Select and Pin Control ...........................................................................................183 10.4.3 Hardware Trigger ............................................................................................................183 10.4.4 Conversion Control .........................................................................................................183 10.4.5 Automatic Compare Function .........................................................................................186 10.4.6 MCU Wait Mode Operation ............................................................................................186 10.4.7 MCU Stop3 Mode Operation ..........................................................................................186 10.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................187 Initialization Information ..............................................................................................................187 10.5.1 ADC Module Initialization Example .............................................................................187 Application Information ................................................................................................................189 10.6.1 External Pins and Routing ..............................................................................................189 10.6.2 Sources of Error ..............................................................................................................191 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction ...................................................................................................................................195 11.1.1 Features ...........................................................................................................................199 11.1.2 Modes of Operation ........................................................................................................199 11.1.3 Block Diagram ................................................................................................................200 11.2 External Signal Description ..........................................................................................................200 11.2.1 SCL — Serial Clock Line ...............................................................................................200 11.2.2 SDA — Serial Data Line ................................................................................................200 11.3 Register Definition ........................................................................................................................201 11.3.1 IIC Address Register (IICA) ...........................................................................................201 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................202 11.3.3 IIC Control Register (IICC) ............................................................................................204 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor Subject to Change 13 Section Number Title Page 11.3.4 IIC Status Register (IICS) ...............................................................................................205 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................206 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................207 11.4 Functional Description ..................................................................................................................208 11.4.1 IIC Protocol .....................................................................................................................208 11.4.2 10-bit Address .................................................................................................................212 11.4.3 General Call Address ......................................................................................................212 11.5 Resets ............................................................................................................................................213 11.6 Interrupts .......................................................................................................................................213 11.6.1 Byte Transfer Interrupt ....................................................................................................213 11.6.2 Address Detect Interrupt .................................................................................................213 11.6.3 Arbitration Lost Interrupt ................................................................................................213 Chapter 12 Freescale’s Controller Area Network (S08MSCANV1) 12.1 Introduction ...................................................................................................................................215 12.1.1 Features ...........................................................................................................................217 12.1.2 Modes of Operation ........................................................................................................217 12.1.3 Block Diagram ................................................................................................................218 12.2 External Signal Description ..........................................................................................................218 12.2.1 RXCAN — CAN Receiver Input Pin .............................................................................218 12.2.2 TXCAN — CAN Transmitter Output Pin .....................................................................218 12.2.3 CAN System ...................................................................................................................218 12.3 Register Definition ........................................................................................................................219 12.3.1 MSCAN Control Register 0 (CANCTL0) ......................................................................219 12.3.2 MSCAN Control Register 1 (CANCTL1) ......................................................................222 12.3.3 MSCAN Bus Timing Register 0 (CANBTR0) ...............................................................223 12.3.4 MSCAN Bus Timing Register 1 (CANBTR1) ...............................................................224 12.3.5 MSCAN Receiver Interrupt Enable Register (CANRIER) .............................................227 12.3.6 MSCAN Transmitter Flag Register (CANTFLG) ..........................................................228 12.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER) ........................................229 12.3.8 MSCAN Transmitter Message Abort Request Register (CANTARQ) ...........................230 12.3.9 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) .................231 12.3.10MSCAN Transmit Buffer Selection Register (CANTBSEL) .........................................231 12.3.11MSCAN Identifier Acceptance Control Register (CANIDAC) ......................................232 12.3.12MSCAN Miscellaneous Register (CANMISC) ..............................................................233 12.3.13MSCAN Receive Error Counter (CANRXERR) ............................................................234 12.3.14MSCAN Transmit Error Counter (CANTXERR) ..........................................................235 12.3.15MSCAN Identifier Acceptance Registers (CANIDAR0-7) ............................................235 12.3.16MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) .................................236 12.4 Programmer’s Model of Message Storage ....................................................................................237 12.4.1 Identifier Registers (IDR0–IDR3) ...................................................................................240 12.4.2 IDR0–IDR3 for Standard Identifier Mapping .................................................................242 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 14 Subject to Change Freescale Semiconductor Section Number Title Page 12.4.3 Data Segment Registers (DSR0-7) .................................................................................243 12.4.4 Data Length Register (DLR) ...........................................................................................244 12.4.5 Transmit Buffer Priority Register (TBPR) ......................................................................245 12.4.6 Time Stamp Register (TSRH–TSRL) .............................................................................245 12.5 Functional Description ..................................................................................................................246 12.5.1 General ............................................................................................................................246 12.5.2 Message Storage .............................................................................................................247 12.5.3 Identifier Acceptance Filter .............................................................................................250 12.5.4 Modes of Operation ........................................................................................................257 12.5.5 Low-Power Options ........................................................................................................258 12.5.6 Reset Initialization ..........................................................................................................264 12.5.7 Interrupts .........................................................................................................................264 12.6 Initialization/Application Information ..........................................................................................266 12.6.1 MSCAN initialization .....................................................................................................266 12.6.2 Bus-Off Recovery ...........................................................................................................267 Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction ...................................................................................................................................269 13.1.1 Features ...........................................................................................................................271 13.1.2 Block Diagrams ..............................................................................................................272 13.1.3 SPI Baud Rate Generation ..............................................................................................273 13.2 External Signal Description ..........................................................................................................274 13.2.1 SPSCK — SPI Serial Clock ............................................................................................274 13.2.2 MOSI — Master Data Out, Slave Data In ......................................................................274 13.2.3 MISO — Master Data In, Slave Data Out ......................................................................274 13.2.4 SS — Slave Select ...........................................................................................................274 13.3 Modes of Operation .......................................................................................................................275 13.3.1 SPI in Stop Modes ..........................................................................................................275 13.4 Register Definition ........................................................................................................................275 13.4.1 SPI Control Register 1 (SPIC1) ......................................................................................275 13.4.2 SPI Control Register 2 (SPIC2) ......................................................................................276 13.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................277 13.4.4 SPI Status Register (SPIS) ..............................................................................................278 13.4.5 SPI Data Register (SPID) ................................................................................................279 13.5 Functional Description ..................................................................................................................280 13.5.1 SPI Clock Formats ..........................................................................................................280 13.5.2 SPI Interrupts ..................................................................................................................283 13.5.3 Mode Fault Detection .....................................................................................................283 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor Subject to Change 15 Section Number Title Page 13.6 Initialization/Application Information ..........................................................................................283 13.6.1 SPI Module Initialization Example .................................................................................283 Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction ...................................................................................................................................287 14.1.1 SCI2 Configuration Information .....................................................................................287 14.1.2 Features ...........................................................................................................................289 14.1.3 Modes of Operation ........................................................................................................289 14.1.4 Block Diagram ................................................................................................................290 14.2 Register Definition ........................................................................................................................292 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................292 14.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................293 14.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................294 14.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................295 14.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................297 14.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................298 14.2.7 SCI Data Register (SCIxD) .............................................................................................299 14.3 Functional Description ..................................................................................................................299 14.3.1 Baud Rate Generation .....................................................................................................299 14.3.2 Transmitter Functional Description ................................................................................300 14.3.3 Receiver Functional Description .....................................................................................301 14.3.4 Interrupts and Status Flags ..............................................................................................303 14.3.5 Additional SCI Functions ...............................................................................................304 Chapter 15 Real-Time Counter (S08RTCV1) 15.1 Introduction ...................................................................................................................................307 15.1.1 RTC Clock Signal Names ...............................................................................................307 15.1.2 Features ...........................................................................................................................309 15.1.3 Modes of Operation ........................................................................................................309 15.1.4 Block Diagram ................................................................................................................310 15.2 External Signal Description ..........................................................................................................310 15.3 Register Definition ........................................................................................................................310 15.3.1 RTC Status and Control Register (RTCSC) ....................................................................311 15.3.2 RTC Counter Register (RTCCNT) ..................................................................................312 15.3.3 RTC Modulo Register (RTCMOD) ................................................................................312 15.4 Functional Description ..................................................................................................................313 15.4.1 RTC Operation Example .................................................................................................314 15.5 Initialization/Application Information ..........................................................................................314 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 16 Subject to Change Freescale Semiconductor Section Number Title Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) Page 16.1 Introduction ...................................................................................................................................317 16.1.1 Features ...........................................................................................................................319 16.1.2 Block Diagram ................................................................................................................319 16.2 External Signal Description ..........................................................................................................321 16.2.1 External TPM Clock Sources ..........................................................................................321 16.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................321 16.3 Register Definition ........................................................................................................................321 16.3.1 Timer x Status and Control Register (TPMxSC) ............................................................322 16.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ................................................323 16.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ...............................324 16.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) ......................................325 16.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ......................................326 16.4 Functional Description ..................................................................................................................327 16.4.1 Counter ............................................................................................................................327 16.4.2 Channel Mode Selection .................................................................................................328 16.4.3 Center-Aligned PWM Mode ...........................................................................................330 16.5 TPM Interrupts ..............................................................................................................................331 16.5.1 Clearing Timer Interrupt Flags .......................................................................................331 16.5.2 Timer Overflow Interrupt Description ............................................................................331 16.5.3 Channel Event Interrupt Description ..............................................................................332 16.5.4 PWM End-of-Duty-Cycle Events ...................................................................................332 Chapter 17 Development Support 17.1 Introduction ...................................................................................................................................333 17.1.1 Features ...........................................................................................................................335 17.2 Background Debug Controller (BDC) ..........................................................................................335 17.2.1 BKGD Pin Description ...................................................................................................336 17.2.2 Communication Details ..................................................................................................337 17.2.3 BDC Commands .............................................................................................................341 17.2.4 BDC Hardware Breakpoint .............................................................................................343 17.3 On-Chip Debug System (DBG) ....................................................................................................344 17.3.1 Comparators A and B ......................................................................................................344 17.3.2 Bus Capture Information and FIFO Operation ...............................................................344 17.3.3 Change-of-Flow Information ..........................................................................................345 17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................345 17.3.5 Trigger Modes .................................................................................................................346 17.3.6 Hardware Breakpoints ....................................................................................................348 17.4 Register Definition ........................................................................................................................348 17.4.1 BDC Registers and Control Bits .....................................................................................348 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor Subject to Change 17 Section Number Title Page 17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................350 17.4.3 DBG Registers and Control Bits .....................................................................................351 Appendix A Electrical Characteristics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 Introduction ...................................................................................................................................357 Parameter Classification ................................................................................................................357 Absolute Maximum Ratings ..........................................................................................................357 Thermal Characteristics .................................................................................................................358 ESD Protection and Latch-Up Immunity ......................................................................................359 DC Characteristics .........................................................................................................................360 Supply Current Characteristics ......................................................................................................364 Analog Comparator (ACMP) Electricals ......................................................................................366 ADC Characteristics ......................................................................................................................367 External Oscillator (XOSC) Characteristics .................................................................................371 MCG Specifications ......................................................................................................................372 AC Characteristics .........................................................................................................................373 A.12.1 Control Timing ...............................................................................................................374 A.12.2 Timer/PWM ....................................................................................................................375 A.12.3 MSCAN ..........................................................................................................................376 A.12.4 SPI ...................................................................................................................................377 A.13 FLASH and EEPROM ..................................................................................................................380 A.14 EMC Performance .........................................................................................................................381 A.14.1 Radiated Emissions .........................................................................................................381 A.14.2 Conducted Transient Susceptibility ................................................................................381 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................383 B.1.1 MC9S08DZ60 Series Devices ........................................................................................383 B.2 Mechanical Drawings ....................................................................................................................383 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 18 Subject to Change Freescale Semiconductor Chapter 1 Device Overview MC9S08DZ60 Series devices provide significant value to customers looking to combine CAN and embedded EEPROM in their applications. This combination will provide lower costs, enhanced performance, and higher quality. 1.1 Devices in the MC9S08DZ60 Series This data sheet covers members of the MC9S08DZ60 Series of MCUs: • MC9S08DZ60 • MC9S08DZ48 • MC9S08DZ32 • MC9S08DZ16 Table 1-1 summarizes the feature set available in the MC9S08DZ60 Series. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 19 Chapter 1 Device Overview t Table 1-1. MC9S08DZ60 Series Features by MCU and Pin Count Feature FLASH size (bytes) RAM size (bytes) EEPROM size (bytes) Pin quantity ACMP1 ACMP2 ADC channels DBG IIC IRQ MCG MSCAN RTC SCI1 SCI2 SPI TPM1 channels TPM2 channels XOSC COP Watchdog 1 MC9S08DZ60 60032 4096 2048 64 yes 24 48 yes 1 MC9S08DZ48 49152 3072 1536 32 no 10 64 yes 24 48 yes1 16 32 yes no 10 yes yes yes yes yes yes yes yes yes yes 24 64 MC9S08DZ32 33792 2048 1024 48 yes1 16 32 no 10 MC9S08DZ16 16896 1024 512 48 yes1 16 32 no 10 16 6 6 4 6 6 4 2 yes yes 6 6 4 6 4 ACMP2O is not available. 1.2 MCU Block Diagram Figure 1-1 is the MC9S08DZ60 Series system-level block diagram. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 20 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 1 Device Overview HCS08 CORE PORT A CPU BKGD/MS ANALOG COMPARATOR (ACMP1) ACMP1O ACMP1ACMP1+ BDC BKP PTA7/PIA7/ADP7/IRQ PTA6/PIA6/ADP6 PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 PTA3/PIA3/ADP3/ACMP1O PTA2/PIA2/ADP2/ACMP1PTA1/PIA1/ADP1/ACMP1+ PTA0/PIA0/ADP0/MCLK PTB7/PIB7/ADP15 PTB6/PIB6/ADP14 PTB5/PIB5/ADP13 PTB4/PIB4/ADP12 PTB3/PIB3/ADP11 PTB2/PIB2/ADP10 PTB1/PIB1/ADP9 PTB0/PIB0/ADP8 PTC7/ADP23 PTC6/ADP22 PTC5/ADP21 PTC4/ADP20 PTC3/ADP19 PTC2/ADP18 PTC1/ADP17 PTC0/ADP16 PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 PTD1/PID1/TPM2CH1 PTD0/PID0/TPM2CH0 PTE7/RxD2/RXCAN PTE6/TxD2/TXCAN PTE5/SDA/MISO PTE4/SCL/MOSI PTE3/SPSCK PTE2/SS PTE1/RxD1 PTE0/TxD1 PTF7 PTF6/ACMP2O PTF5/ACMP2PTF4/ACMP2+ PTF3/TPM2CLK/SDA PTF2/TPM1CLK/SCL PTF1/RxD2 PTF0/TxD2 PTG5 PTG4 PTG3 PTG2 PTG1/XTAL PTG0/EXTAL HCS08 SYSTEM CONTROL RESET RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP INT VREFH VREFL VDDA VSSA LVD IRQ 24-CHANNEL,10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 8 IRQ ADP7-ADP0 ADP15-ADP8 ADP23-ADP16 PORT C 2-CHANNEL TIMER/PWM MODULE (TPM2) USER EEPROM MC9S08DZ60 = 2K CONTROLLER AREA NETWORK (MSCAN) SERIAL PERIPHERAL INTERFACE MODULE (SPI) SERIAL COMMUNICATIONS INTERFACE (SCI1) ANALOG COMPARATOR (ACMP2) IIC MODULE (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) MULTI-PURPOSE CLOCK GENERATOR (MCG) OSCILLATOR (XOSC) - VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages - VDD and VSS pins are each internally connected to two pads in 32-pin package XTAL EXTAL TPM2CH1, TPM2CH0 TPM2CLK RxCAN TXCAN MISO MOSI SPSCK SS RxD1 TxD1 ACMP2O ACMP2ACMP2+ SDA SCL RxD2 TxD2 DEBUG MODULE (DBG) REAL-TIME COUNTER (RTC) VDD VDD VSS VSS VOLTAGE REGULATOR - Pin not connected in 48-pin and 32-pin packages - Pin not connected in 32-pin package Figure 1-1. MC9S08DZ60 Block Diagram MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 21 PORT G PORT F PORT E USER RAM MC9S08DZ60 = 4K PORT D USER FLASH MC9S08DZ60 = 60K MC9S08DZ48 = 48K MC9S08DZ32 = 32K MC9S08DZ16 = 16K 6-CHANNEL TIMER/PWM MODULE (TPM1) TPM1CH5 TPM1CH0 6 TPM1CLK PORT B Chapter 1 Device Overview Table 1-2 provides the functional version of the on-chip modules. Table 1-2. Module Versions Module Central Processor Unit Multi-Purpose Clock Generator Analog Comparator Analog-to-Digital Converter Inter-Integrated Circuit Freescale’s CAN Serial Peripheral Interface Serial Communications Interface Real-Time Counter Timer Pulse Width Modulator Debug Module (CPU) (MCG) (ACMP) (ADC) (IIC) (MSCAN) (SPI) (SCI) (RTC) (TPM) (DBG) Version 3 1 3 1 2 1 3 4 1 2 2 1.3 System Clock Distribution Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following are the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of MCGOUT. • LPO — Independent 1-kHz clock that can be selected as the source for the COP and RTC modules. • MCGOUT — Primary output of the MCG and is twice the bus frequency. • MCGLCLK — Development tools can select this clock source to speed up BDC communications in systems where BUSCLK is configured to run at a very slow frequency. • MCGERCLK — External reference clock can be selected as the RTC clock source. It can also be used as the alternate clock for the ADC and MSCAN. • MCGIRCLK — Internal reference clock can be selected as the RTC clock source. • MCGFFCLK — Fixed frequency clock can be selected as clock source for the TPM1 and TPM2. • TPM1CLK — External input clock source for TPM1. • TPM2CLK — External input clock source for TPM2. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 22 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 1 Device Overview TPM1CLK 1 kHZ LPO MCGERCLK MCGIRCLK MCG TPM1 TPM2CLK TPM2 IIC SCI1 SCI2 SPI RTC COP MCGFFCLK ÷2 ÷2 BUSCLK FFCLK* MCGOUT MCGLCLK XOSC CPU BDC ADC MSCAN FLASH EEPROM EXTAL XTAL * The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. ADC has min and max frequency requirements. See the ADC chapter and electricals appendix for details. FLASH and EEPROM have frequency requirements for program and erase operation. See the electricals appendix for details. Figure 1-2. MC9S08DZ60 System Clock Distribution Diagram MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 23 Chapter 1 Device Overview MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 24 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment This section shows the pin assignments for MC9S08DZ60 Series MCUs in the available packages. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTA6/PIA6/ADP6 PTB5/PIB5/ADP13 PTA5/PIA5/ADP5 PTC4/ADP20 PTB4/PIB4/ADP12 PTA4/PIA4/ADP4 VDDA VREFH VREFL VSSA PTA3/PIA3/ADP3/ACMP1O PTB3/PIB3/ADP11 PTC3/ADP19 PTA2/PIA2/ADP2/ACMP1PTB2/PIB2/ADP10 PTA1/PIA1/ADP1/ACMP1+ 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 25 PTE2/SS PTE3/SPSCK PTE4/SCL/MOSI PTE5/SDA/MISO PTG2 PTG3 PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL PTF3/TPM2CLK/SDA PTG4 PTG5 PTE6/TxD2/TXCAN PTE7/RxD2/RXCAN PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTB6/PIB6/ADP14 PTC5/ADP21 PTA7/PIA7/ADP7/IRQ PTC6/ADP22 PTB7/PIB7/ADP15 PTC7/ADP23 VDD VSS PTG0/EXTAL PTG1/XTAL RESET PTF4/ACMP2+ PTF5/ACMP2PTF6/ACMP2O PTE0/TxD1 PTE1/RxD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin QFN and LQFP PTB1/PIB1/ADP9 PTC2/ADP18 PTA0/PIA0/ADP0/MCLK PTC1/ADP17 PTB0/PIB0/ADP8 PTC0/ADP16 BKGD/MS PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 VDD VSS PTF7 PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 Figure 2-1. 64-Pin LQFP/QFN Chapter 2 Pins and Connections 48 47 46 45 44 43 42 41 40 39 38 37 PTA6/PIA6/ADP6 PTB5/PIB5/ADP13 PTA5/PIA5/ADP5 PTB4/PIB4/ADP12 PTA4/PIA4/ADP4 VDDA/VREFH VSSA/VREFL PTA3/PIA3/ADP3/ACMP1O PTB3/PIB3/ADP11 PTA2/PIA2/ADP2/ACMP1PTB2/PIB2/ADP10 PTA1/PIA1/ADP1/ACMP1+ PTB6/PIB6/ADP14 PTA7/PIA7/ADP7/IRQ PTB7/PIB7/ADP15 VDD VSS PTG0/EXTAL PTG1/XTAL RESET PTF4/ACMP2+ PTF5/ACMP2PTE0/TxD1 PTE1/RxD1 36 35 34 33 32 31 30 29 28 27 26 25 VREFH and VREFL are internally connected to VDDA and VSSA, respectively. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 26 PRELIMINARY Subject to Change Freescale Semiconductor PTE2/SS PTE3/SPSCK PTE4/SCL/MOSI PTE5/SDA/MISO PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL PTF3/TPM2CLK/SDA PTE6/TxD2/TXCAN PTE7/RxD2/RXCAN PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48-Pin LQFP PTB1/PIB1/ADP9 PTA0/PIA0/ADP0/MCLK PTB0/PIB0/ADP8 BKGD/MS PTD7/PID7/TPM1CH5 PTD6/PID6/TPM1CH4 VDD VSS PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 PTD2/PID2/TPM1CH0 Figure 2-2. 48-Pin LQFP Chapter 2 Pins and Connections PTA3/ADP3/ACMPO PTA5/PIA5/ADP5 PTA4/PIA4/ADP4 VDDA/VREFH VSSA/VREFL 32 PTA7/PIA7/ADP7/IRQ 1 VDD VSS PTG0/EXTAL PTG1/XTAL RESET PTE0/TxD1 PTE1/RxD1 8 10 9 PTE6/TxD2/TXCAN PTE5/SDA/MISO PTE7/RxD2/RXCAN PTD0/PID0/TPM2CH0 PTE4/SCL/MOSI PTE2/SS PTE3/SPSCK 11 12 13 14 15 2 3 4 5 6 7 31 30 29 28 27 26 25 24 PTB1/PIB1/ADP9 23 22 21 PTA0/PIA0/ADP0/MCLK PTB0/PIB0/ADP8 BKGD/MS PTD5/PID5/TPM1CH3 PTD4/PID4/TPM1CH2 PTD3/PID3/TPM1CH1 17 PTD2/PID2/TPM1CH0 16 PTD1/PID1/TPM2CH1 32-Pin LQFP 20 19 18 VREFH and VREFL are internally connected to VDDA and VSSA, respectively. Figure 2-3. 32-Pin LQFP MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 27 PTA1/ADP1/ACMP+ PTA2/ADP2/ACMP- PTA6/PIA6/ADP6 Chapter 2 Pins and Connections 2.2 Recommended System Connections VDDA CBYAD 0.1 µF VREFH MC9S08DZ60 Figure 2-4 shows pin connections that are common to MC9S08DZ60 Series application systems. PTA0/PIA0/ADP0/MCLK PTA1/PIA1/ADP1/ACMP1+ PTA2/PIA2/ADP2/ACMP1VREFL VSSA CBY 0.1 µF SYSTEM POWER VDD IRQ VSS + 5V VDD CBLK + 10 µF CBY 0.1 µF VSS BACKGROUND HEADER VDD PORT B PTB0/PIB0/ADP8 PTB1/PIB1/ADP9 PTB2/PIB2/ADP10 PTB3/PIB3/ADP11 PTB4/PIB4/ADP12 PTB5/PIB5/ADP13 PTB6/PIB6/ADP14 PTB7/PIB7/ADP15 PTC0/ADP16 PTC1/ADP17 PTC2/ADP18 PTC3/ADP19 PTC4/ADP20 PTC5/ADP21 PTC6/ADP22 PTC7/ADP23 PORT A PTA3/PIA3/ADP3/ACMP1O PTA4/PIA4/ADP4 PTA5/PIA5/ADP5 PTA6/PIA6/ADP6 PTA7/PIA7/ADP7/IRQ BKGD/MS RESET OPTIONAL MANUAL RESET PORT C RF C1 C2 RS PTD0/PID0/TPM2CH0 PTD1/PID1/TPM2CH1 PTG0/EXTAL PTG1/XTAL PTG2 PTG3 PTG4 PTG5 PTF0/TxD2 PTF1/RxD2 PTF2/TPM1CLK/SCL PTF3/TPM2CLK/SDA PTF4/ACMP2+ PTF5/ACMP2– PTF6/ACMP2O PTF7 PTD2/PID2/TPM1CH0 PORT G PORT D PTD3/PID3/TPM1CH1 PTD4/PID4/TPM1CH2 PTD5/PID5/TPM1CH3 PTD6/PID6/TPM1CH4 PTD7/PID7/TPM1CH5 PTE0/TxD1 PTE1/RxD1 PTE2/SS PTE3/SPSCK PTE4/SCL/MOSI PTE5/SDA/MISO PTE6/TxD2/TXCAN PTE7/RxD2/RXCAN X1 PORT F PORT E Figure 2-4. Basic System Connections (Shown in 64-Pin Package) MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 28 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 2 Pins and Connections 2.2.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-µF ceramic bypass capacitor located as near to the MCU power pins as practical to suppress high-frequency noise. The MC9S08DZ60 Series has two VDD pins except on the 32-pin package. Each pin must have a bypass capacitor for best noise suppression. VDDA and VSSA are the analog power supply pins for the MCU. This voltage source supplies power to the ADC module. A 0.1-µF ceramic bypass capacitor should be located as near to the MCU power pins as practical to suppress high-frequency noise. 2.2.2 Oscillator Immediately after reset, the MCU uses an internally generated clock provided by the multi-purpose clock generator (MCG) module. For more information on the MCG, see Chapter 8, “Multi-Purpose Clock Generator (S08MCGV1).” The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin. Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors and some metal film resistors have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity, and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 (which are usually the same size). As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.2.3 RESET RESET is a dedicated pin with a pull-up device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 29 Chapter 2 Pins and Connections Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for about 66 bus cycles. After the 66 cycles are completed, the pin is released and will be pulled up by the internal pull-up resistor, unless it is held low externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin is the cause of the MCU reset. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry expects the reset pin sample to return a logic 1. If the pin is still low at this sample point, the reset is assumed to be from an external source. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system reset status register (SRS). Never connect any significant capacitance to the reset pin because that would interfere with the circuit and sequence that detects the source of reset. If an external capacitance prevents the reset pin from rising to a valid logic 1 before the reset sample point, all resets will appear to be external resets. 2.2.4 Background / Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin functions as the background pin and can be used for background debug communication. While functioning as a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standard output driver, and no output slew rate control. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD low during the rising edge of reset which forces the MCU to active background mode. The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall times on the BKGD/MS pin. 2.2.5 ADC Reference Pins (VREFH, VREFL) The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively, for the ADC module. 2.2.6 General-Purpose I/O and Peripheral Ports The MC9S08DZ60 Series series of MCUs support up to 53 general-purpose I/O pins and 1 input-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, MSCAN, etc.). When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 30 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 2 Pins and Connections pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pull-up devices disabled. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output Control.” NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not float. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 31 Chapter 2 Pins and Connections Table 2-1. Pin Availability by Package Pin-Count Pin Number 64 48 32 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 Highest Alt 2 Pin Number 64 48 32 Highest Alt 2 TPM1CH0 TPM1CH1 TPM1CH2 TPM1CH3 VSS VDD — PTB6 1 PTA7 — PTB7 2 3 4 PTG0 5 PTG1 6 — PTF4 33 25 17 PTD2 34 26 18 PTD3 IRQ 35 27 19 PTD4 36 28 20 PTD5 37 — — PTF7 38 29 — 39 30 — 40 31 — PTD6 41 32 — PTD7 42 33 21 43 — — PTC0 44 34 22 PTB0 45 — — PTC1 46 35 23 PTA0 47 — — PTC2 48 36 24 PTB1 49 37 25 PTA1 50 38 — PTB2 51 39 26 PTA2 52 — — PTC3 53 40 — PTB3 54 41 27 PTA3 TxD2 4 4 — — PTC5 — — PTC6 — — PTC7 PID6 PID7 BKGD ADP16 PIB0 PIA0 PIB1 PIA1 PIB2 PIA2 PIB3 PIA3 ADP8 ADP17 ADP0 ADP18 ADP9 ADP11 ADP10 ADP2 ADP19 ADP11 ADP3 TPM1CH4 TPM1CH5 MS 13 10 — PTF5 14 — — PTF6 15 11 16 12 17 13 7 PTE0 8 PTE1 9 PTE2 MCLK ACMP1+1 ACMP1-1 18 14 10 PTE3 19 15 11 PTE4 20 16 12 PTE5 21 — — PTG2 22 — — PTG3 23 17 — PTF0 24 18 — PTF1 25 19 — PTF2 26 20 — PTF3 27 — — PTG4 28 — — PTG5 29 21 13 PTE6 30 22 14 PTE7 31 23 15 PTD0 32 24 16 PTD1 PID0 PID1 TxD2 4 4 MOSI MISO SDA3 ACMP1O VSSA VREFL VREFH VDDA 55 56 57 58 42 28 43 29 PIA4 PIB4 PIA5 PIB5 PIA6 ADP4 ADP12 ADP20 ADP5 ADP13 ADP6 RxD2 TPM1CLK SCL3 TPM2CLK SDA 3 59 44 30 PTA4 60 45 — PTB4 TXCAN RxCAN TPM2CH0 TPM2CH1 61 — — PTC4 62 46 31 PTA5 63 47 — PTB5 64 48 32 PTA6 RxD2 1. If both of these analog modules are enabled, they both will have access to the pin. 2. Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on this pin when internal pull-up is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD. 3. The IIC module pins can be repositioned using IICPS bit in the SOPT1 register. The default reset locations are on PTF2 and PTF3. 4. The SCI2 module pins can be repositioned using SCI2PS bit in the SOPT1 register. The default reset locations are on PTF0 and PTF1. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 32 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08DZ60 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • Features Active background mode for code development Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation is maintained Stop modes — System clocks are stopped and voltage regulator is in standby — Stop3 — All internal circuits are powered for fast recovery — Stop2 — Partial power down of internal circuits; RAM content is retained 3.3 Run Mode This is the normal operating mode for the MC9S08DZ60 Series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD/MS pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 33 Chapter 3 Modes of Operation Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user application program (GO) The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08DZ60 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter. 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 34 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 3 Modes of Operation 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in SOPT1 register is set. In both stop modes, all internal clocks are halted. The MCG module can be configured to leave the reference clocks running. See Chapter 8, “Multi-Purpose Clock Generator (S08MCGV1),” for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. The selected mode is entered following the execution of a STOP instruction. Table 3-1. Stop Mode Selection STOPE 0 1 1 1 1 1 ENBDM 1 x 1 0 0 0 LVDE x x LVDSE PPDC x x x3 0 1 Stop Mode Stop modes disabled; illegal opcode reset if STOP instruction executed Stop3 with BDM enabled 2 Stop3 with voltage regulator active Stop3 Stop2 Both bits must be 1 Either bit a 0 Either bit a 0 ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, “BDC Status and Control Register (BDCSCR)”. 2 When in Stop3 mode with BDM enabled, The S IDD will be near RIDD levels because internal clocks are enabled. 3 If LVD = 1 in stop, the MCU enters stop3, regardless of the configuration of PPDC. 3.6.1 Stop3 Mode Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Exit from stop3 is done by asserting RESET or an asynchronous interrupt pin. The asynchronous interrupt pins are IRQ, PIA0–PIA7, PIB0–PIB7, and PID0–PID7. Exit from stop3 can also be done by the low-voltage detect (LVD) reset, low-voltage warning (LVW) interrupt, ADC conversion complete interrupt, real-time clock (RTC) interrupt, MSCAN wake-up interrupt, or SCI receiver interrupt. If stop3 is exited by means of the RESET pin, the MCU will be reset and operation will resume after fetching the reset vector. Exit by means of an interrupt will result in the MCU fetching the appropriate interrupt vector. 3.6.1.1 LVD Enabled in Stop3 Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate the LVD must be left enabled when entering stop3. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 35 Chapter 3 Modes of Operation 3.6.1.2 Active BDM Enabled in Stop3 Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described in Chapter 17, “Development Support.” If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. 3.6.2 Stop2 Mode Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2. Exit from stop2 is performed by asserting RESET or PTA7/ADP7/IRQ. NOTE PTA7/ADP7/IRQ is an active low wake-up and must be configured as an input prior to executing a STOP instruction to avoid an immediate exit from stop2. PTA7/ADP7/IRQ can be disabled as a wake-up if it is configured as a high driven output. For lowest power consumption in stop2, this pin should not be left open if configured as input (enable the internal pullup; or tie an external pullup/down device; or set pin as output). In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled. Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD trip point (low trip point selected due to POR) • The CPU takes the reset vector In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2. To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 36 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 3 Modes of Operation writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop3 Mode” and Section 3.6.1, “Stop3 Mode” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Mode Peripheral Stop2 CPU RAM FLASH/EEPROM Parallel Port Registers ACMP ADC IIC MCG MSCAN RTC SCI SPI TPM Voltage Regulator XOSC I/O Pins 1 2 3 4 5 6 Stop3 Standby Standby Standby Standby Optionally On1 Optionally On2 Standby Optionally On3 Standby On4 Optionally On4 Standby Standby Standby 5 Off Standby Off Off Off Off Off Off Off Optionally Off Off Off Optionally On Off States Held Optionally On5 Optionally On6 States Held Requires the LVD to be enabled, else in standby. Requires the asynchronous ADC clock and LVD to be enabled, else in standby. IRCLKEN and IREFSTEN set in MCGC1, else in standby. Requires the RTC to be enabled, else in standby. Requires the LVD or BDC to be enabled. ERCLKEN and EREFSTEN set in MCGC2 for, else in standby. For high frequency range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 37 Chapter 3 Modes of Operation MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 38 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 4 Memory 4.1 MC9S08DZ60 Series Memory Map On-chip memory in the MC9S08DZ60 Series consists of RAM, EEPROM, and FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) • High-page registers (0x1800 through 0x18FF) • Nonvolatile registers (0xFFB0 through 0xFFBF) 0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 4096 BYTES 0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 3072 BYTES 0x0C7F 0x0C80 FLASH 896 BYTES UNIMPLEMENTED 2176 BYTES 0x14FF 0x1500 EEPROM 2 x 1024 BYTES EEPROM 2 x 768 BYTES 0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 2048 BYTES 0x087F 0x0880 0x0000 DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 1024 BYTES 0x047F 0x0480 0x107F 0x1080 0x13FF 0x1400 UNIMPLEMENTED 3456 BYTES 0x15FF 0x1600 UNIMPLEMENTED 4736 BYTES 0x16FF 0x1700 EEPROM 0x17FF 2 x 256 BYTES 0x1800 HIGH PAGE REGISTERS 256 BYTES 0x18FF 0x1900 0x17FF 0x1800 HIGH PAGE REGISTERS 256 BYTES 0x18FF 0x1900 0x17FF 0x1800 HIGH PAGE REGISTERS 256 BYTES 0x18FF 0x1900 0x17FF 0x1800 HIGH PAGE REGISTERS 256 BYTES 0x18FF 0x1900 EEPROM 2 x 512 BYTES UNIMPLEMENTED 9984 BYTES 0x3FFF 0x4000 UNIMPLEMENTED 25,344 BYTES UNIMPLEMENTED 42,240 BYTES 0x7BFF 0x7C00 0xBDFF 0xBE00 FLASH 59136 BYTES FLASH 49152 BYTES FLASH 33792 BYTES 0xFFFF MC9S08DZ32 MC9S08DZ16 FLASH 16896 BYTES 0xFFFF MC9S08DZ60 0xFFFF MC9S08DZ48 0xFFFF Figure 4-1. MC9S08DZ60 Memory Map MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 39 Chapter 4 Memory 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the MC9S08DZ60 Series equate file provided by Freescale Semiconductor. Table 4-1. Reset and Interrupt Vectors Address (High/Low) 0xFFC0:0xFFC1 0xFFC2:0xFFC3 0xFFC4:0xFFC5 0xFFC6:0xFFC7 0xFFC8:0xFFC9 0xFFCA:0xFFCB 0xFFCC:0xFFCD 0xFFCE:0xFFCF 0xFFD0:0xFFD1 0xFFD2:0xFFD3 0xFFD4:0xFFD5 0xFFD6:0xFFD7 0xFFD8:0xFFD9 0xFFDA:0xFFDB 0xFFDC:0xFFDD 0xFFDE:0xFFDF 0xFFE0:0xFFE1 0xFFE2:0xFFE3 0xFFE4:0xFFE5 0xFFE6:0xFFE7 0xFFE8:0xFFE9 0xFFEA:0xFFEB 0xFFEC:0xFFED 0xFFEE:0xFFEF 0xFFF0:0xFFF1 0xFFF2:0xFFF3 0xFFF4:0xFFF5 0xFFF6:0xFFF7 0xFFF8:0xFFF9 0xFFFA:0xFFFB 0xFFFC:0xFFFD 0xFFFE:0xFFFF Vector ACMP2 ACMP1 MSCAN Transmit MSCAN Receive MSCAN errors MSCAN wake up RTC IIC ADC Conversion Port A, Port B, Port D SCI2 Transmit SCI2 Receive SCI2 Error SCI1 Transmit SCI1 Receive SCI1 Error SPI TPM2 Overflow TPM2 Channel 1 TPM2 Channel 0 TPM1 Overflow TPM1 Channel 5 TPM1 Channel 4 TPM1 Channel 3 TPM1 Channel 2 TPM1 Channel 1 TPM1 Channel 0 MCG Loss of lock Low-Voltage Detect IRQ SWI Reset Vector Name Vacmp2 Vacmp1 Vcantx Vcanrx Vcanerr Vcanwu Vrtc Viic Vadc Vport Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch5 Vtpm1ch4 Vtpm1ch3 Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vlol Vlvd Virq Vswi Vreset MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 40 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 4 Memory 4.3 Register Addresses and Bit Assignments The registers in the MC9S08DZ60 Series are divided into these groups: • Direct-page registers are located in the first 128 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — NVPROT and NVOPT are loaded into working registers at reset — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires only the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-5, the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-5, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 41 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 PTAD7 PTADD7 PTBD7 PTBDD7 PTCD7 PTCDD7 PTDD7 PTDDD7 PTED7 PTEDD7 PTFD7 PTFDD7 0 0 ACME ACME COCO ADACT 0 ADR7 0 ADCV7 ADLPC ADPC7 ADPC15 ADPC23 — — 0 — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 ADPC6 ADPC14 ADPC22 — — IRQPDD — — TOIE 14 6 14 6 CH0IE 14 6 6 PTAD6 PTADD6 PTBD6 PTBDD6 PTCD6 PTCDD6 PTDD6 PTDDD6 PTED6 PTEDD6 PTFD6 PTFDD6 0 0 ACBGS ACBGS AIEN ADTRG 0 ADR6 0 ADCV6 ADIV ADPC5 ADPC13 ADPC21 — — IRQEDG — — CPWMS 13 5 13 5 MS0B 13 5 5 PTAD5 PTADD5 PTBD5 PTBDD5 PTCD5 PTCDD5 PTDD5 PTDDD5 PTED5 PTEDD5 PTFD5 PTFDD5 PTGD5 PTGDD5 ACF ACF ADCO ACFE 0 ADR5 0 ADCV5 ACFGT 0 ADR4 0 ADCV4 ADLSMP ADPC4 ADPC12 ADPC20 — — IRQPE — — CLKSB 12 4 12 4 MS0A 12 4 — 0 ADR3 0 ADCV3 ADPC3 ADPC11 ADPC19 — — IRQF — — CLKSA 11 3 11 3 ELS0B 11 3 MODE ADPC2 ADPC10 ADPC18 — — IRQACK — — PS2 10 2 10 2 ELS0A 10 2 4 PTAD4 PTADD4 PTBD4 PTBDD4 PTCD4 PTCDD4 PTDD4 PTDDD4 PTED4 PTEDD4 PTFD4 PTFDD4 PTGD4 PTGDD4 ACIE ACIE 3 PTAD3 PTADD3 PTBD3 PTBDD3 PTCD3 PTCDD3 PTDD3 PTDDD3 PTED3 PTEDD3 PTFD3 PTFDD3 PTGD3 PTGDD3 ACO ACO 2 PTAD2 PTADD2 PTBD2 PTBDD2 PTCD2 PTCDD2 PTDD2 PTDDD2 PTED2 PTEDD2 PTFD2 PTFDD2 PTGD2 PTGDD2 ACOPE ACOPE ADCH — 0 ADR2 0 ADCV2 — ADR9 ADR1 ADCV9 ADCV1 ADPC1 ADPC9 ADPC17 — — IRQIE — — PS1 9 1 9 1 0 9 1 — ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 ADPC16 — — IRQMOD — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 1 PTAD1 PTADD1 PTBD1 PTBDD1 PTCD1 PTCDD1 PTDD1 PTDDD1 PTED1 PTEDD1 PTFD1 PTFDD1 PTGD1 PTGDD1 ACMOD1 ACMOD1 Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 PTDD0 PTDDD0 PTED0 PTEDD0 PTFD0 PTFDD0 PTGD0 PTGDD0 ACMOD0 ACMOD0 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A– 0x001B 0x001C 0x001D– 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 PTAD PTADD PTBD PTBDD PTCD PTCDD PTDD PTDDD PTED PTEDD PTFD PTFDD PTGD PTGDD ACMP1SC ACMP2SC ADCSC1 ADCSC2 ADCRH ADCRL ADCCVH ADCCVL ADCCFG APCTL1 APCTL2 APCTL3 Reserved IRQSC Reserved TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL ADICLK MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 42 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 CH1F Bit 15 Bit 7 CH2F Bit 15 Bit 7 CH3F Bit 15 Bit 7 CH4F Bit 15 Bit 7 CH5F Bit 15 Bit 7 — LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 CLKS BDIV LOLS LOLIE 0 LOCK PLLS 0 RANGE PLLST CME 0 6 CH1IE 14 6 CH2IE 14 6 CH3IE 14 6 CH4IE 14 6 CH5IE 14 6 — RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 5 MS1B 13 5 MS2B 13 5 MS3B 13 5 MS4B 13 5 MS5B 13 5 — 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 4 MS1A 12 4 MS2A 12 4 MS3A 12 4 MS4A 12 4 MS5A 12 4 — SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 RDIV HGO TRIM IREFST 0 0 0 0 CLKST OSCINIT VDIV 0 0 FTRIM LP 3 ELS1B 11 3 ELS2B 11 3 ELS3B 11 3 ELS4B 11 3 ELS5B 11 3 — SBR11 SBR3 WAKE TE OR RWUID ORIE 3 SBR11 SBR3 WAKE TE OR RWUID ORIE 3 2 ELS1A 10 2 ELS2A 10 2 ELS3A 10 2 ELS4A 10 2 ELS5A 10 2 — SBR10 SBR2 ILT RE NF BRK13 NEIE 2 SBR10 SBR2 ILT RE NF BRK13 NEIE 2 IREFS EREFS 1 0 9 1 0 9 1 0 9 1 0 9 1 0 9 1 — SBR9 SBR1 PE RWU FE LBKDE FEIE 1 SBR9 SBR1 PE RWU FE LBKDE FEIE 1 IRCLKEN Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 IREFSTEN 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D TPM1C1SC TPM1C1VH TPM1C1VL TPM1C2SC TPM1C2VH TPM1C2VL TPM1C3SC TPM1C3VH TPM1C3VL TPM1C4SC TPM1C4VH TPM1C4VL TPM1C5SC TPM1C5VH TPM1C5VL Reserved SCI1BDH SCI1BDL SCI1C1 SCI1C2 SCI1S1 SCI1S2 SCI1C3 SCI1D SCI2BDH SCI2BDL SCI2C1 SCI2C2 SCI2S1 SCI2S2 SCI2C3 SCI2D MCGC1 MCGC2 MCGTRM MCGSC MCGC3 MCGT ERCLKEN EREFSTEN MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 43 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 — — SPIE 0 0 SPRF 0 Bit 7 — — AD7 MULT IICEN TCF GCAEN — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — RTIF IICIE IAAS ADEXT — — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — RTCLKS MST BUSY 0 — — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — TX ARBL DATA 0 — — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — RTIE RTCCNT RTCMOD — — — — — — — — — — — — — — — — — — — — — — — — 0 — — CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — AD10 — — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — RTCPS AD9 — — PS1 9 1 9 1 0 9 1 0 9 1 — AD8 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — TXAK 0 6 — — SPE 0 SPPR2 0 0 6 — — AD6 5 — — SPTIE 0 SPPR1 SPTEF 0 5 — — AD5 4 — — MSTR MODFEN SPPR0 MODF 0 4 — — AD4 3 — — CPOL BIDIROE 0 0 0 3 — — AD3 ICR RSTA SRW 0 IICIF 0 RXAK 2 — — CPHA 0 SPR2 0 0 2 — — AD2 1 — — SSOE SPISWAI SPR1 0 0 1 — — AD1 Bit 0 — — LSBFE SPC0 SPR0 0 0 Bit 0 — — 0 0x004E– 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056– 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E– 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F 0x0070– 0x007F Reserved SPIC1 SPIC2 SPIBR SPIS Reserved SPID Reserved IICA IICF IICC IICS IICD IICC2 Reserved TPM2SC TPM2CNTH TPM2CNTL TPM2MODH TPM2MODL TPM2C0SC TPM2C0VH TPM2C0VL TPM2C1SC TPM2C1VH TPM2C1VL Reserved RTCSC RTCCNT RTCMOD Reserved Reserved High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 44 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 POR 0 COPT COPCLKS — — — ID7 — LVWF 0 — — Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 DBGEN TRGSEL AF — — DIVLD KEYEN 0 0 FCBEF — — PTAPE7 PTASE7 PTADS7 — 0 PTAPS7 PTAES7 EPS FCCF — — PTAPE6 PTASE6 PTADS6 — 0 PTAPS6 PTAES6 FPVIOL — — PTAPE5 PTASE5 PTADS5 — 0 PTAPS5 PTAES5 FACCERR FCMD — — PTAPE4 PTASE4 PTADS4 — 0 PTAPS4 PTAES4 — — PTAPE3 PTASE3 PTADS3 — PTAIF PTAPS3 PTAES3 — — PTAPE2 PTASE2 PTADS2 — PTAACK PTAPS2 PTAES2 — — PTAPE1 PTASE1 PTADS1 — PTAIE PTAPS1 PTAES1 — — PTAPE0 PTASE0 PTADS0 — PTAMOD PTAPS0 PTAES0 0 COPW — — — ID6 — LVWACK 0 — — 14 6 14 6 14 6 ARM BEGIN BF — — PRDIV8 FNORED EPGSEL EPGMOD KEYACC 0 0 Reserved 1 6 PIN 0 5 COP 0 STOPE 0 — — — ID5 — LVWIE LVDV — — 13 5 13 5 13 5 TAG 0 ARMF — — 4 ILOP 0 SCI2PS ADHTS — — — ID4 — LVDRE LVWV — — 12 4 12 4 12 4 BRKEN 0 0 — — 3 ILAD 0 IICPS 0 — — ID11 ID3 — LVDSE PPDF — — 11 3 11 3 11 3 RWA TRG3 CNT3 — — DIV 0 0 0 FPS 2 LOCS 0 0 — — ID10 ID2 — LVDE PPDACK — — 10 2 10 2 10 2 RWAEN TRG2 CNT2 — — 0 0 0 FBLANK 1 LVD 0 0 MCSEL — — ID9 ID1 — 0 — — — 9 1 9 1 9 1 RWB TRG1 CNT1 — — SEC 0 0 0 Bit 0 0 BDFR 0 — — ID8 ID0 — BGBE PPDC — — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 RWBEN TRG0 CNT0 — — 0x1800 0x1801 0x1802 0x1803 0x1804 – 0x1805 0x1806 0x1807 0x1808 0x1809 0x180A 0x180B– 0x180F 0x1810 0x1811 0x1812 0x1813 0x1814 0x1815 0x1816 0x1817 0x1818 0x1819– 0x181F 0x1820 0x1821 0x1822 0x1823 0x1824 0x1825 0x1826 0x1827– 0x183F 0x1840 0x1841 0x1842 0x1843 0x1844 0x1845 0x1846 SRS SBDFR SOPT1 SOPT2 Reserved SDIDH SDIDL Reserved SPMSC1 SPMSC2 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL DBGC DBGT DBGS Reserved FCDIV FOPT FTSTMOD FCNFG FPROT FSTAT FCMD Reserved PTAPE PTASE PTADS Reserved PTASC PTAPS PTAES MRDS 0 0 0 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 45 Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 — PTBPE7 PTBSE7 PTBDS7 — 0 PTBPS7 PTBES7 — PTCPE7 PTCSE7 PTCDS7 — — PTDPE7 PTDSE7 PTDDS7 — 0 PTDPS7 PTDES7 — PTEPE7 PTESE7 PTEDS7 — — PTFPE7 PTFSE7 PTFDS7 — — 0 0 0 — — RXFRM CANE SJW1 6 — PTBPE6 PTBSE6 PTBDS6 — 0 PTBPS6 PTBES6 — PTCPE6 PTCSE6 PTCDS6 — — PTDPE6 PTDSE6 PTDDS6 — 0 PTDPS6 PTDES6 — PTEPE6 PTESE6 PTEDS6 — — PTFPE6 PTFSE6 PTFDS6 — — 0 0 0 — — RXACT CLKSRC SJW0 5 — PTBPE5 PTBSE5 PTBDS5 — 0 PTBPS5 PTBES5 — PTCPE5 PTCSE5 PTCDS5 — — PTDPE5 PTDSE5 PTDDS5 — 0 PTDPS5 PTDES5 — PTEPE5 PTESE5 PTEDS5 — — PTFPE5 PTFSE5 PTFDS5 — — PTGPE5 PTGSE5 PTGDS5 — — CSWAI LOOPB BRP5 4 — PTBPE4 PTBSE4 PTBDS4 — 0 PTBPS4 PTBES4 — PTCPE4 PTCSE4 PTCDS4 — — PTDPE4 PTDSE4 PTDDS4 — 0 PTDPS4 PTDES4 — PTEPE4 PTESE4 PTEDS4 — — PTFPE4 PTFSE4 PTFDS4 — — PTGPE4 PTGSE4 PTGDS4 — — SYNCH LISTEN BRP4 3 — PTBPE3 PTBSE3 PTBDS3 — PTBIF PTBPS3 PTBES3 — PTCPE3 PTCSE3 PTCDS3 — — PTDPE3 PTDSE3 PTDDS3 — PTDIF PTDPS3 PTDES3 — PTEPE3 PTESE3 PTEDS3 — — PTFPE3 PTFSE3 PTFDS3 — — PTGPE3 PTGSE3 PTGDS3 — — TIME BORM BRP3 2 — PTBPE2 PTBSE2 PTBDS2 — PTBACK PTBPS2 PTBES2 — PTCPE2 PTCSE2 PTCDS2 — — PTDPE2 PTDSE2 PTDDS2 — PTDACK PTDPS2 PTDES2 — PTEPE2 PTESE2 PTEDS2 — — PTFPE2 PTFSE2 PTFDS2 — — PTGPE2 PTGSE2 PTGDS2 — — WUPE WUPM BRP2 1 — PTBPE1 PTBSE1 PTBDS1 — PTBIE PTBPS1 PTBES1 — PTCPE1 PTCSE1 PTCDS1 — — PTDPE1 PTDSE1 PTDDS1 — PTDIE PTDPS1 PTDES1 — PTEPE1 PTESE1 PTEDS1 — — PTFPE1 PTFSE1 PTFDS1 — — PTGPE1 PTGSE1 PTGDS1 — — SLPRQ SLPAK BRP1 Bit 0 — PTBPE0 PTBSE0 PTBDS0 — PTBMOD PTBPS0 PTBES0 — PTCPE0 PTCSE0 PTCDS0 — — PTDPE0 PTDSE0 PTDDS0 — PTDMOD PTDPS0 PTDES0 — PTEPE0 PTESE0 PTEDS0 — — PTFPE0 PTFSE0 PTFDS0 — — PTGPE0 PTGSE0 PTGDS0 — — INITRQ INITAK BRP0 0x1847 0x1848 0x1849 0x184A 0x184B 0x184C 0x184D 0x184E 0x184F 0x1850 0x1851 0x1852 0x1853– 0x1857 0x1858 0x1859 0x185A 0x185B 0x185C 0x185D 0x185E 0x185F 0x1860 0x1861 0x1862 0x1863– 0x1867 0x1868 0x1869 0x186A 0x186B– 0x186F 0x1870 0x1871 0x1872 0x1873– 0x187F 0x1880 0x1881 0x1882 Reserved PTBPE PTBSE PTBDS Reserved PTBSC PTBPS PTBES Reserved PTCPE PTCSE PTCDS Reserved PTDPE PTDSE PTDDS Reserved PTDSC PTDPS PTDES Reserved PTEPE PTESE PTEDS Reserved PTFPE PTFSE PTFDS Reserved PTGPE PTGSE PTGDS Reserved CANCTL0 CANCTL1 CANBTR0 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 46 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 RXERR7 TXERR7 AC7 AM7 AC7 AM7 TSR15 TSR7 — — 6 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6 AC6 AM6 AC6 AM6 TSR14 TSR6 — — 5 TSEG21 RSTAT1 RSTATE1 0 0 0 0 0 IDAM1 0 0 RXERR5 TXERR5 AC5 AM5 AC5 AM5 TSR13 TSR5 — — 4 TSEG20 RSTAT0 RSTATE0 0 0 0 0 0 IDAM0 0 0 RXERR4 TXERR4 AC4 AM4 AC4 AM4 TSR12 TSR4 — — 3 TSEG13 TSTAT1 TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3 AC3 AM3 AC3 AM3 TSR11 TSR3 — — 2 TSEG12 TSTAT0 TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 AC2 AM2 AC2 AM2 TSR10 TSR2 — — 1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 TX1 IDHIT1 0 0 RXERR1 TXERR1 AC1 AM1 AC1 AM1 TSR9 TSR1 — — Bit 0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0 TX0 IDHIT0 0 BOHOLD RXERR0 TXERR0 AC0 AM0 AC0 AM0 TSR8 TSR0 — — 0x1883 0x1884 0x1885 0x1886 0x1887 0x1888 0x1889 0x188A 0x188B 0x188C 0x188D 0x188E 0x188F 0x1890 – 0x1893 0x1894 – 0x1897 0x1898 – 0x189B 0x189C – 0x189F 0x18BE 0x18BF 0x18C0– 0x18FF 1 CANBTR1 CANRFLG CANRIER CANTFLG CANTIER CANTARQ CANTAAK CANTBSEL CANIDAC Reserved CANMISC CANRXERR CANTXERR CANIDAR0 – CANIDAR3 CANIDMR0 – CANIDMR3 CANIDAR4 – CANIDAR7 CANIDMR4 – CANIDMR7 CANTTSRH CANTTSRL Reserved This bit is reserved. User must write a 1 to this bit. Failing to do so may result in unexpected behavior. Figure 4-4 shows the common 13-byte data structure of receive and transmit buffers for standard identifier mapping. See Chapter 11, “Freescale’s Controller Area Network (S08MSCANV1),” for details on extended and standard identifier mapping. Table 4-4. MSCAN Foreground and Receive Transmit Buffer Layout — Standard Mapping 0x18A0 0x18A1 0x18A2 0x18A3 0x18A4 – 0x18AB 0x18AC 0x18AD 0x18AE CANRIDR0 CANRIDR1 CANRIDR2 CANRIDR3 CANRDSR0 – CANRDSR7 CANRDLR Reserved CANRTSRH ID10 ID2 — — DB7 — — TSR15 ID9 ID1 — — DB6 — — TSR14 ID8 ID0 — — DB5 — — TSR13 ID7 RTR — — DB4 — — TSR12 ID6 IDE — — DB3 DLC3 — TSR11 ID5 — — — DB2 DLC2 — TSR10 ID4 — — — DB1 DLC1 — TSR9 ID3 — — — DB0 DLC0 — TSR8 MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E Freescale Semiconductor PRELIMINARY Subject to Change 47 Chapter 4 Memory Table 4-4. MSCAN Foreground and Receive Transmit Buffer Layout — Standard Mapping 0x18AF 0x18B0 0x18B1 0x18B2 0x18B3 0x18B4 – 0x18BB 0x18BC 0x18BD CANRTSRL CANTIDR0 CANTIDR1 CANTIDR2 CANTIDR3 CANTDSR0 – CANTDSR7 CANTDLR CANTTBPR TSR7 ID10 ID2 — — DB7 — PRIO7 TSR6 ID9 ID1 — — DB6 — PRIO6 TSR5 ID8 ID0 — — DB5 — PRIO5 TSR4 ID7 RTR — — DB4 — PRIO4 TSR3 ID6 IDE — — DB3 DLC3 PRIO3 TSR2 ID5 — — — DB2 DLC2 PRIO2 TSR1 ID4 — — — DB1 DLC1 PRIO1 TSR0 ID3 — — — DB0 DLC0 PRIO0 Nonvolatile FLASH registers, shown in Table 4-5, are located in the FLASH memory. These registers include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Table 4-5. Nonvolatile Register Summary Address Register Name Reserved for storage of FTRIM Res. for storage of MCGTRM Bit 7 0 6 0 5 0 4 0 TRIM 8-Byte Comparison Key — — EPS — KEYEN — FNORED — EPGMOD — 0 — 0 — — — — — — — — FPS — 0 — SEC — — — — — — — 3 0 2 0 1 0 Bit 0 FTRIM 0xFFAE 0xFFAF 0xFFB0– 0xFFB7 0xFFB8– 0xFFBC 0xFFBD 0xFFBE 0xFFBF NVBACKKEY Reserved NVPROT Reserved NVOPT Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0). MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E 48 PRELIMINARY Subject to Change Freescale Semiconductor Chapter 4 Memory 4.4 RAM The MC9S08DZ60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data while the MCU is in low-power wait, stop2, or stop3 mode. At power-on the contents of RAM are uninitialized. RAM data is unaffected by any reset if the supply voltage does not drop below the minimum value for RAM retention (VRAM). For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08DZ60 Series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP