MC9S08GW64CLH

Freescale Freescale Semiconductor Data Sheet: Advance Information An Energy Efficient Solution by Freescale Document Number: MC9S08GW64 Rev. 1, 5/2010 MC9S08GW64 Series Covers: MC9S08GW64 and MC9S08GW32 8-Bit HCS08 Central Processor Unit (CPU) MC9S08GW64 80-LQFP Case 917A 14 × 14 64-LQFP Case 840F 10 × 10 comparator can be used as hardware breakpoint. Full mode, Comparator A compares address and Comparator B compares data. Supports both tag and force breakpoints Peripherals – New version of S08 core with same performace as traditional S08 and lower power – Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 2.15 V to 1.8 V, across temperature range of –40 °C to 85 °C – HC08 instruction set with added BGND instruction – Support for up to 48 interrupt/reset sources On-Chip Memory – Flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents Power-Saving Modes – Two low power stop modes and reduced power wait mode – Low power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents – Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter – 6 μs typical wakeup time from stop3 mode Clock Source Options – Oscillator (XOSC1) — Loop-control Pierce oscillator; Crystal or ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS – Oscillator (XOSC2) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz; optional clock source for ICS – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference (XOSC1, XOSC2); precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage warning with interrupt – Low-voltage detection with reset or interrupt – Illegal opcode and illegal address detection with reset – Flash block protection Development Support – LCD — up to 4×40 or 8×36 LCD driver with internal charge pump and option to provide an internally regulated LCD reference that can be trimmed for contrast control – ADC16 — two analog-to-digital converters; 16-bit resolution; one dedicated differential per ADC; up to 16-ch; up to 2.5 μs conversion time for 12-bit mode; automatic compare function; hardware averaging; calibration registers; temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V – PRACMP —three rail to rail programmable reference analog comparator; up to 8 inputs; on-chip programmable reference generator output; selectable interrupt on rising, falling, or either edge of comparator output; operation in stop3 – SCI — four full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge; SCI0 designed for AMR operation; TxD of SCI1 and SCI2 can be modulated with timers and RxD can recieved through PRACMP; – SPI— three full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting; SPI0 designed for AMR opeartion – IIC — up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supporting broadcast mode and 10-bit addressing; supporting SM BUS functionality; can wake from stop3 – FTM — 2-channel FTMs; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – IRTC — independent real-time clock, independent power domain, 32 bytes RAM, 32.768 kHz input clock optional output to ICS, hardware calendar, hardware compensation due to crystal or temperature characteristics, tamper detection and indicator – PCRC — 16/32 bit programmable cyclic redundancy check for high-speed CRC calculation – MTIM — two 8-bit and one 16-bit timers; configurable clock inputs and interrupt generation on overflow – PDB — programmable delay block; optimized for scheduling ADC conversions – PCNT — position counter; working in stop3 mode without waking CPU; can be used to generate waveforms like timer Input/Output – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus 3 more breakpoints in breakpoint unit) – Breakpoint (BKPT) debug module containing three comparators (A, B, and C) with ability to match addresses in 64 KB space. Each – 57 GPIOs including one output-only pin – Eight KBI interrupts with selectable polarity – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins. Package Options – 80-pin LQFP, 64-pin LQFP This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Table of Contents 1 2 3 Devices in the MC9S08GW64 Series. . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .10 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .10 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .12 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18 3.8 External Oscillator (XOSCVLP) Characteristics . . . . . .20 3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .21 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Analog Comparator (PRACMP) Electricals . . . . . . . . . 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 VREF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . Package Information and Mechanical Drawings . . . . . . . . . . 24 25 26 29 29 34 35 35 36 36 36 4 5 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date Description of Changes 1 5/26/2010 Initial public release Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08GW64RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08GW64 Series MCU Data Sheet, Rev. 1 2 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Devices in the MC9S08GW64 Series 1 Devices in the MC9S08GW64 Series Table 1. MC9S08GW64 Series Features by MCU and Package Feature Package FLASH RAM ADC01 Single-ended Channels ADC0 Differential Channels2 ADC1 Single-ended Channels ADC1 Differential Channels BKPT ICS IIC IRQ IRTC KBI MTIM8 MTIM16 PCNT PCRC PDB PRACMP SCI SPI FTM LCD VREFO XOSC I/O pins3 57 8×36 4×40 yes 2 45 57 7-ch MC9S08GW64 80-pin LQFP 65,536 Bytes 4,032 Bytes 7-ch 7-ch 64-pin LQFP MC9S08GW32 80-pin LQFP 32,768 Bytes 2,048 Bytes 7-ch 64-pin LQFP Table 1 summarizes the feature set available in the MC9S08GW64 series of MCUs. 1 0 1 0 7-ch 7-ch 7-ch 7-ch 1 yes yes yes yes yes 8-ch 2 yes yes yes yes 3 4 3 2-ch 1 1 yes yes yes yes yes 8-ch 2 yes yes yes yes 3 4 3 2-ch 1 8×24 4×28 yes 8×36 4×40 yes 2 8×24 4×28 yes 45 MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 3 Devices in the MC9S08GW64 Series 1 There are two 16-bit ADC modules, so two parallel conversions at two channels can be made simultaneously. 2 Each differential channel consists of two pins (DADPx and DADMx). 3 The I/O pins include one output-only pin. The block diagram in Figure 1 shows the structure of the MC9S08GW64 series MCUs. MC9S08GW64 Series MCU Data Sheet, Rev. 1 4 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Devices in the MC9S08GW64 Series VDDA/VSSA VREFH/VREFL VDDA/VSSA VREFH/VREFL AD[20] ADC1 VDDA/VSSA VREFH/VREFL AD[20] ADC0 Port A,F,G,H: AD[15:2] DADP/M[1] trig[1] sel[1] KBI trig[0] sel[0] Port A,F,G,H: AD[15:2] DADP/M[0] Port B, D: KBIP[7:0] 2-Channel FTM Port A, C, F: FTMCH[0:1] FTMCLK 16-bit MTIM3 Port A, F: MTIMCLK Port B Port A PDB trig[1:0] sel[1:0] Port A: EXTRIG PTA0/MOSI2/PCNTCH0/SCL/AD2 PTA1/MISO2/PCNTCH1/SDA/AD3 PTA2/SCLK2/FTMCH0/PCNT0/CMPP0 PTA3/SS2/FTMCH1/PCNT1/CMPP1 PTA4/MTIMCLK/RxD2/PCNT2/CMPP2 PTA5/FTMCLK/TxD2/EXTRIG/IRQ PTA6/CMPOUT0/CLKOUT/BKGD/MS PTB0/KBIP0/TxD1/EXTAL2 PTB1/KBIP1/RxD1/XTAL2 PTB2/KBIP2/MOSI0/MISO0/RxD0 PTB3/KBIP3/MISO0/MOSI0/TxD0 PTB4/KBIP4/SCLK0/SCL PTB5/KBIP5/SS0/SDA PTB6/KBIP6/RxD2/LCD0 PTB7/KBIP7/TxD2/LCD1 PTC0/MOSI1/LCD2 PTC1/MISO1/LCD3 PTC2/SCLK1/LCD4 PTC3/SS1/LCD5 PTC4/FTMCH0/RxD1/LCD6 PTC5/FTMCH1/TxD1/LCD7 PTC6/PCNTCH0/RxD3/LCD8 PTC7/PCNTCH1/TxD3/LCD9 PTD0/KBIP0/MOSI2/LCD10 PTD1/KBIP1/MISO2/LCD11 PTD2/KBIP2/SCLK2/LCD12 PTD3/KBIP3/SS2/LCD13 PTD4/KBIP4/LCD14 PTD5/KBIP5/CLKOUT/LCD15 PTD6/KBIP6/LCD16 PTD7/KBIP7/LCD17 PTE0/LCD18 PTE1/LCD19 PTE2/LCD20 PTE3/LCD21 PTE4/LCD22 PTE5/LCD23 PTE6/LCD24 PTE7/LCD25 PTF0/LCD26 PTF1/LCD27 PTF2/LCD28 PTF3/LCD29 PTF4/LCD30 PTF5/LCD31 PTF6/MTIMCLK/AD4/LCD32 PTF7/FTMCLK/AD5/LCD33 PTG0/MOSI1/AD6/LCD34 PTG1/MISO1/AD7/LCD35 PTG2/SCLK1/AD8/LCD36 PTG3/SS1/AD9/LCD37 PTG4/CMPOUT1/RxD3/AD10/LCD38 PTG5/CMPOUT2/TxD3/AD11/LCD39 PTG6/CMPP3/AD12/PCNT0/LCD40 PTG7/CMPP4/AD13/PCNT1/LCD41 PTH0/CMPP5/AD14/PCNT2/LCD42 PTH1/RTCCLKOUT/CMPP6/AD15/LCD43 VREFO VDD VSS1 VSS2 VREG 8-bit MTIM1 Port A, F: MTIMCLK PCRC 8-bit MTIM2 S08 Core V6 CPU SPI0 Port B: MOSI0 MISO0 SCLK0 SS0 Port C, G: MOSI1 MISO1 SCLK1 SS1 Port A, D: MOSI2 MISO2 SCLK2 SS2 Port A, B: SDA SCL Port B: RxD0 TxD0 Port B, C: RxD1 TxD1 Port A, B: RxD2 TxD2 Port C, G: RxD3 TxD3 Port A, G, H: CMPP0/1/2/3/4/5/6 CMPOUT0 Port A, G, H: CMPP0/1/2/3/4/5/6 CMPOUT1 Port A, G, H: CMPP0/1/2/3/4/5/6 CMPOUT2 Port H Port F Port G Port D Port E BKGD/MS BKPT INT SPI1 SPI2 RESETB SIM IIC COP LVD SCI0 FLASH GW64 64 KB GW32 32 KB RAM GW64 4 KB GW32 2 KB Internal Clock Source REF CLK IRCLK PRACMP0 Clock Check & Select SCI3 SCI1 SCI2 XTAL2 EXTAL2 XTAL1 EXTAL1 VBAT TAMPER1 TAMPER2 XOSC2 CLKO XOSC1 CLKO PRACMP1 PRACMP2 PCNT Independent RTC The RTC is in a separate power domain LCD Port A, C: PCNT0 PCNT1 PCNT2 PCNTCH0 PCNTCH1 Port B, C, D, E, F, G, H: LCD[0:43] Figure 1. MC9S08GW64 Series Block Diagram MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 5 Port C Port A, F: MTIMCLK Pin Assignments 2 Pin Assignments VCAP1 VCAP2 VLL1 VLL2 VLL3 VSS PTE5/LCD23 PTE4/LCD22 PTE3/LCD21 PTE2/LCD20 PTE1/LCD19 PTE0/LCD18 PTD7/KBIP7/LCD17 PTD6/KBIP6/LCD16 PTD5/KBIP5/CLKOUT/LCD15 PTD4/KBIP4/LCD14 PTD3/KBIP3/SS2/LCD13 PTD2/KBIP2/SCLK2/LCD12 PTD1/KBIP1/MISO2/LCD11 PTD0/KBIP0/MOSI2/LCD10 PTE6/LCD24 PTE7/LCD25 PTF0/LCD26 PTF1/LCD27 PTF2/LCD28 PTF3/LCD29 PTF4/LCD30 PTF5/LCD31 PTF6/MTIMCLK/AD4/LCD32 PTF7/FTMCLK/AD5/LCD33 PTG0/MOSI1/AD6/LCD34 PTG1/MISO1/AD7/LCD35 PTG2/SCLK1/AD8/LCD36 PTG3/SS1/AD9/LCD37 PTG4/CMPOUT1/RxD3/AD10/LCD38 PTG5/CMPOUT2/TxD3/AD11/LCD39 PTG6/CMPP3/AD12/PCNT0/LCD40 PTG7/CMPP4/AD13/PCNT1/LCD41 PTH0/CMPP5/AD14/PCNT2/LCD42 PTH1/RTCCLKOUT/AD15/LCD43 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 This section shows the pin assignments for the MC9S08GW64 series devices. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 LQFP PTC7/PCNTCH1/TxD3/LCD9 PTC6/PCNTCH0/RxD3/LCD8 PTC5/FTMCH1/TxD1/LCD7 PTC4/FTMCH0/RxD1/LCD6 PTC3/SS1/LCD5 PTC2/SCLK1/LCD4 PTC1/MISO1/LCD3 PTC0/MOSI1/LCD2 PTB7/KBIP7/TxD2/LCD1 PTB6/KBIP6/RxD2/LCD0 PTB5/KBIP5/SS0/SDA PTB4/KBIP4/SCLK0/SCL PTB3/KBIP3/MISO0/MOSI0/TxD0 PTB2/KBIP2/MOSI0/MISO0/RxD0 RESET PTB1/KBIP1/RxD1/CMPP6/XTAL2 PTB0/KBIP0/TxD1/EXTAL2 VSS VDD PTA6/CMPOUT0/CLKOUT/BKGD/MS Figure 2. MC9S08GW64 Series in 80-Pin LQFP Package 6 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE VDDA VREFH VSSA VREFL DADP0 DADM0 VREFO DADP1 DADM1 VBAT EXTAL1 XTAL1 TAMPER1 TAMPER2 PTA0/MOSI2/PCNTCH0/SCL/AD2 PTA1/MISO2/PCNTCH1/SDA/AD3 PTA2/SCLK2/FTMCH0/PCNT0/CMPP0 PTA3/SS2/FTMCH1/PCNT1/CMPP1 PTA4/MTIMCLK/RxD2/PCNT2/CMPP2 PTA5/FTMCLK/TxD2/EXTRIG/IRQ 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor Pin Assignments PTE6/LCD24 PTE7/LCD25 PTF0/LCD26 PTF1/LCD27 PTF6/MTIMCLK/AD4/LCD32 PTF7/FTMCLK/AD5/LCD33 PTG0/MOSI1/AD6/LCD34 PTG1/MISO1/AD7/LCD35 PTG2/SCLK1/AD8/LCD36 PTG3/SS1/AD9/LCD37 PTG4/CMPOUT1/RxD3/AD10/LCD38 PTG5/CMPOUT2/TxD3/AD11/LCD39 PTG6/CMPP3/AD12/PCNT0/LCD40 PTG7/CMPP4/AD13/PCNT1/LCD41 PTH0/CMPP5/AD14/PCNT2/LCD42 PTH1/RTCCLKOUT/AD15/LCD43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCAP1 VCAP2 VLL1 VLL2 VLL3 VSS PTE5/LCD23 PTE4/LCD22 PTD7/KBIP7/LCD17 PTD6/KBIP6/LCD16 PTD5/KBIP5/CLKOUT/LCD15 PTD4/KBIP4/LCD14 PTD3/KBIP3/SS2/LCD13 PTD2/KBIP2/SCLK2/LCD12 PTD1/KBIP1/MISO2/LCD11 PTD0/KBIP0/MOSI2/LCD10 64 LQFP PTC7/PCNTCH1/TxD3/LCD9 PTC6/PCNTCH0/RxD3/LCD8 PTC5/FTMCH1/TxD1/LCD7 PTC4/FTMCH0/RxD1/LCD6 PTB7/KBIP7/TxD2/LCD1 PTB6/KBIP6/RxD2/LCD0 PTB5/KBIP5/SS0/SDA PTB4/KBIP4/SCLK0/SCL PTB3/KBIP3/MISO0/MOSI0/TxD0 PTB2/KBIP2/MOSI0/MISO0/RxD0 RESET PTB1/KBIP1/RxD1/CMPP6/XTAL2 PTB0/KBIP0/TxD1/EXTAL2 VSS VDD PTA6/CMPOUT0/CLKOUT/BKGD/MS VDDA/VREFH VSSA/VREFL Figure 3. MC9S08GW64 Series in 64-Pin LQFP Package Table 2. Pin Availability by Package Pin-Count 80 1 2 3 4 5 6 64 1 2 3 4 Port Pin PTE6 PTE7 PTF0 PTF1 PTF2 PTF3 Default func PTE6 PTE7 PTF0 PTF1 PTF2 PTF3 LCD26 LCD27 LCD28 LCD29 Alt 1 Alt 2 LCD24 LCD25 Alt3 Alt4 MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 7 VREFO DADP1 DADM1 VBAT EXTAL1 XTAL1 TAMPER1 TAMPER2 PTA0/MOSI2/PCNTCH0/SCL/AD2 PTA1/MISO2/PCNTCH1/SDA/AD3 PTA2/SCLK2/FTMCH0/PCNT0/CMPP0 PTA3/SS2/FTMCH1/PCNT1/CMPP1 PTA4/MTIMCLK/RxD2/PCNT2/CMPP2 PTA5/FTMCLK/TxD2/EXTRIG/IRQ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Assignments Table 2. Pin Availability by Package Pin-Count (continued) 80 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 17 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 18 5 6 7 8 9 10 11 12 13 14 15 16 64 Port Pin PTF4 PTF5 PTF6 PTF7 PTG0 PTG1 PTG2 PTG3 PTG4 PTG5 PTG6 PTG7 PTH0 PTH1 VDDA VREFH VSSA Default func PTF4 PTF5 PTF6 PTF7 PTG0 PTG1 PTG2 PTG3 PTG4 PTG5 PTG6 PTG7 PTH0 PTH1 VDDA VREFH VSSA Alt 1 LCD30 LCD31 MTIMCLK FTMCLK MOSI1 MISO1 SCLK1 SS1 CMPOUT1 CMPOUT2 CMPP3 CMPP4 CMPP5 RTCCLKOUT Alt 2 Alt3 Alt4 AD4 AD5 AD6 AD7 AD8 AD9 RxD3 TxD3 AD12 AD13 AD14 AD15 LCD32 LCD33 LCD34 LCD35 LCD36 LCD37 AD10 AD11 PCNT0 PCNT1 PCNT2 LCD43 LCD38 LCD39 LCD40 LCD41 LCD42 VREFL DADP0 DADM0 VREFO DADP1 DADM1 VBAT EXTAL1 XTAL1 TAMPER11 TAMPER2 PTA0 PTA1 PTA2 PTA3 PTA4 PTA52 PTA63 VREFL DADP0 DADM0 VREFO DADP1 DADM1 VBAT EXTAL1 XTAL1 TAMPER1 TAMPER2 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 BKGD/MS MOSI2 MISO2 SCLK2 SS2 MTIMCLK FTMCLK CMPOUT0 PCNTCH0 PCNTCH1 FTMCH0 FTMCH1 RxD2 TxD2 CLKOUT SCL SDA PCNT0 PCNT1 PCNT2 EXTRIG BKGD/MS AD2 AD3 CMPP0 CMPP1 CMPP2 IRQ MC9S08GW64 Series MCU Data Sheet, Rev. 1 8 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Pin Assignments Table 2. Pin Availability by Package Pin-Count (continued) 80 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 57 58 59 60 45 46 47 48 49 50 51 52 53 54 55 56 64 34 35 36 37 38 39 40 41 42 43 44 Port Pin VDD VSS PTB0 PTB11 RESET PTB2 PTB3 4 Default func VDD VSS PTB0 PTB1 RESET PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 VSS VLL3 Alt 1 Alt 2 Alt3 Alt4 KBIP0 KBIP1 TxD1 RxD1 EXTAL2 CMPP6 XTAL2 KBIP2 KBIP3 KBIP4 KBIP5 KBIP6 KBIP7 MOSI1 MISO1 SCLK1 SS1 FTMCH0 FTMCH1 PCNTCH0 PCNTCH1 KBIP0 KBIP1 KBIP2 KBIP3 KBIP4 KBIP5 KBIP6 KBIP7 LCD18 LCD19 LCD20 LCD21 MOSI0 MISO0 SCLK0 SS0 RxD2 TxD2 LCD2 LCD3 LCD4 LCD5 RxD1 TxD1 RxD3 TxD3 MOSI2 MISO2 SCLK2 SS2 LCD14 CLKOUT LCD16 LCD17 MISO0 MOSI0 SCL SDA LCD0 LCD1 RxD0 TxD0 PTB43 PTB5 3 PTB6 PTB7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 VSS VLL3 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD15 LCD22 LCD23 MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 9 Electrical Characteristics Table 2. Pin Availability by Package Pin-Count (continued) 80 77 78 79 80 1 2 64 61 62 63 64 Port Pin VLL2 VLL1 VCAP2 VCAP1 Default func VLL2 VLL1 VCAP2 VCAP1 Alt 1 Alt 2 Alt3 Alt4 TAMPER0 pin is dedicatedly used for Battery Removal Tamper and not exposed on any SoC pins. PTA5 is with double drive strength. 3 PTA6 is an output-only pin when it is configured as GPIO. 4 PTB2, PTB3 and PTB4 are compatible with 5 V devices with a pullup device. 3 3.1 Electrical Characteristics Introduction This section contains electrical and timing specifications for the MC9S08GW64 sries of microcontrollers available at the time of publication. 3.2 Parameter Classification Table 3. Parameter Classifications P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: T D NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this MC9S08GW64 Series MCU Data Sheet, Rev. 1 10 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 4. Absolute Maximum Ratings Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins except PTA5 and PTB1)1, 2, 3 Instantaneous maximum current Single pin limit (applies to PTA5 and PTB1)1,2,3 Storage temperature range 1 Symbol VDD IDD VIn ID Value –0.3 to +3.8 120 –0.3 to VDD + 0.3 ± 25 Unit V mA V mA ID Tstg ± 50 –55 to 150 mA °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 80-pin LQFP 64-pin LQFP Thermal resistance Four-layer board 80-pin LQFP 64-pin LQFP θJA TBD TBD °C/W θJA TBD TBD °C/W Symbol TA TJ Value TL to TH –40 to 85 95 Unit °C °C MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 11 Electrical Characteristics The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) where: Eqn. 1 TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 1.8 V ILoad = –0.6 mA VDD > 2.7 V ILoad = –10 mA VDD > 1.8 V ILoad = –3 mA VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 — — — — — — — — — — — — — — — — — — — — — 100 0.5 0.5 0.5 0.5 0.5 0.5 100 3 C Output high voltage P C All LCD/GPIO pins low-drive strength All LCD/GPIO pins high-drive strength VOH VDD >1.8 V ILoad = –0.5 mA VDD > 2.7 V ILoad = –2.5 mA VDD > 1.8 V ILoad = –1 mA V 4 5 D Output high current C Output low voltage P C Max total IOH for all ports All non-LCD pins low-drive strength All non-LCD pins high-drive strength IOHT VOL VDD > 1.8 V ILoad = 0.6 mA VDD > 2.7 V ILoad = 10 mA VDD > 1.8 V ILoad = 3 mA mA V — — — — — — — 6 C Output low voltage P C All LCD/GPIO pins low-drive strength All LCD/GPIO pins high-drive strength VOL VDD > 1.8 V ILoad = 0.5 mA VDD > 2.7 V ILoad = 3 mA VDD > 1.8 V ILoad = 1 mA V 7 D Output low current Max total IOL for all ports IOLT mA MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 13 Electrical Characteristics Table 8. DC Characteristics (continued) Num C 8 9 10 11 P Input high C voltage P Input low C voltage C Input hysteresis P Input leakage current P Hi-Z (off-state) leakage current P Total leakage current2 P Pullup, Pulldown resistors P Pullup, Pulldown resistors Characteristic all digital inputs all digital inputs all digital inputs all input only pins (per pin) all input/output (per pin) Symbol VIH VIL Vhys |IIn| VIn = VDD or VSS Condition VDD > 2.7 V VDD > 1.8 V VDD > 2.7 V VDD > 1.8 V Min 0.70 x VDD 0.85 x VDD — — 0.06 x VDD — Typ1 — — — — — 0.025 Max — — 0.35 x VDD 0.30 x VDD — 1 mV μA Unit V 12 |IOZ| VIn = VDD or VSS — 0.025 1 μA 13 Total leakage current for all pins all digital inputs, when enabled all digital inputs, when enabled |IInT| VIn = VDD or VSS — — 2 μA 14 RPU, RPD RPU, RPD IIC VIN < VSS, VIN > VDD 17.5 — 52.5 kΩ 15 17.5 — 52.5 kΩ 16 D DC injection Single pin limit current 3, 4, Total MCU limit, includes 5 sum of all stressed pins C Input Capacitance, all pins C RAM retention voltage C iRTC RAM retention voltage C POR re-arm voltage D POR re-arm time Low-voltage High range — VDD falling C detection High range — VDD rising threshold Low-voltage Low range — VDD falling C detection Low range — VDD rising threshold Low-voltage VDD falling, LVWV = 1 C warning VDD rising, LVWV = 1 threshold C Low-voltage VDD falling, LVWV = 0 warning VDD rising, LVWV = 0 6 –0.2 –5 — — — 0.6 1.05 1.4 — 2.16 2.23 1.85 1.92 2.46 2.49 2.16 2.23 80 1.17 0.2 5 8 1.0 — 2.0 — 2.22 2.27 1.91 1.99 2.56 2.71 2.23 2.26 — 1.18 mA mA pF V V V μs V 17 18 19 20 21 22 CIn VRAM ViRAM VPOR tPOR VLVDH — — — 0.9 10 2.11 2.16 1.80 V 23 VLVDL 1.86 2.36 V 24 VLVWH 2.52 2.10 2.15 — 1.15 25 26 27 1 VLVWL Vhys VBG V mV V C Low-voltage inhibit reset/recover hysteresis P Bandgap Voltage Reference7 Typical values are measured at 25°C. Characterized, not tested MC9S08GW64 Series MCU Data Sheet, Rev. 1 14 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics 2 3 4 5 6 7 Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250nA. All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). POR will occur below the minimum voltage. Factory trimmed at VDD = 3.0 V, Temp = 25°C PullUp Resistor 45 44 Resistor (kOhm) 43 42 41 40 39 38 1.9 2.2 2.5 2.8 VDD(V) 3.1 3.4 85C Resistor (kOhm) 41.5 41 40.5 40 39 39.5 38.5 38 37.5 37 1.9 2.2 PullDown Resistor 85C 25C -40C TBD -40C 25C 2.5 2.8 VDD(V) 3.1 3.4 Figure 4. Non LCD pins I/O Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) 1.60 1.40 1.20 VOL(V) 1.00 0.80 0.60 0.40 0.20 0.00 0 1 3 VOL vs IOL (Low Drive) 0.39 Typical VOL vs VDD (IOL = 2mA) 85C 0.34 25C -40C TBD -40C 85C 25C VOL(V) 0.29 0.24 0.19 0.14 5 7 9 IOL(mA) 11 13 15 17 19 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 Figure 5. Typical Low-Side Driver (Sink) Characteristics(Non LCD pins) — Low Drive (PTxDSn = 0) MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 15 Electrical Characteristics 1.00 0.90 0.80 0.70 VOL(V) 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0 1 3 VOL vs IOL (High Drive) Typical VOL vs VDD 0.8 0.7 0.6 85oC 25oC -40 oC TBD -40C VOL(V) 85C 25C 0.5 0.4 0.3 0.2 0.1 IOL = 10mA IOL = 6mA IOL = 3mA 5 7 9 IOL(m ) A 11 13 15 17 19 0.0 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD pins) — High Drive (PTxDSn = 1) 1.80 1.60 1.40 1.20 VOH(V) 1.00 0.80 0.60 0.40 0.20 0.00 0 -2 -4 VOH vs IOH (Low Drive) 0.84 0.74 Typical VDD - VOH vs VDD (IOH = -2mA) 85C 25C -40C TBD 25C 0.54 0.44 0.34 0.24 0.14 -40C VDD - VOH(V) 85C 0.64 -6 -8 -10 -12 IOH(mA) -14 -16 -18 -20 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 Figure 7. Typical High-Side (Source) Characteristics (Non LCD pins)— Low Drive (PTxDSn = 0) VOH vs IOH (High Drive) Typical VDD - VOH vs VDD 1.0 0.9 85oC 25oC -40 oC 1.40 1.20 1.00 VOH(V) 0.80 0.60 0.40 0.20 0.00 0 -2 -4 0.8 TBD Room Cold VDD - VOH(V) Hot 0.7 0.6 0.5 0.4 0.3 0.2 0.1 IOH = -10mA IOH = -6mA IOH = -3mA 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 -6 -8 -10 -12 IOH(mA) -14 -16 -18 -20 0.0 Figure 8. Typical High-Side (Source) Characteristics(Non LCD pins) — High Drive (PTxDSn = 1) MC9S08GW64 Series MCU Data Sheet, Rev. 1 16 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics 1.60 1.40 1.20 VOL vs IOL (Low Drive) 0.39 Typical VOL vs VDD (IOL = 2mA) 85C 0.34 25C -40C VOL(V) 1.00 0.80 0.60 0.40 0.20 0.00 0 1 3 5 7 9 IOL(mA) 11 13 15 17 TBD -40C 85C 25C VOL(V) 0.29 0.24 0.19 0.14 19 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 Figure 9. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO pins) — Low Drive (PTxDSn = 0) VOL vs IOL (High Drive) Typical VOL vs VDD 0.8 0.7 0.6 85oC 25oC -40 oC 1.00 0.90 0.80 0.70 VOL(V) 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0 1 3 TBD -40C VOL(V) 85C 25C 0.5 0.4 0.3 0.2 0.1 IOL = 10mA IOL = 6mA IOL = 3mA 5 7 9 IOL(m ) A 11 13 15 17 19 0.0 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 Figure 10. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1) VOH vs IOH (Low Drive) Typical VDD - VOH vs VDD (IOH = -2mA) 85C 25C -40C 1.80 1.60 1.40 1.20 VOH(V) 1.00 0.80 0.60 0.40 0.20 0.00 0 -2 -4 0.84 0.74 TBD 25C 0.54 0.44 0.34 0.24 0.14 -6 -8 -10 -12 IOH(mA) -14 -16 -18 -20 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 -40C Figure 11. Typical High-Side (Source) Characteristics (LCD/GPIO pins)— Low Drive (PTxDSn = 0) MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 17 VDD - VOH(V) 85C 0.64 Electrical Characteristics 1.40 1.20 1.00 VOH(V) 0.80 0.60 0.40 0.20 0.00 0 -2 -4 VOH vs IOH (High Drive) Typical VDD - VOH vs VDD 1.0 0.9 0.8 85oC 25oC -40 oC TBD Room Cold VDD - VOH(V) Hot 0.7 0.6 0.5 0.4 0.3 0.2 0.1 IOH = -10mA IOH = -6mA IOH = -3mA 1.8 2 2.2 2.4 2.6 2.8 VDD(V) 3 3.2 3.4 3.6 -6 -8 -10 -12 IOH(mA) -14 -16 -18 -20 0.0 Figure 12. Typical High-Side (Source) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1) 3.7 Supply Current Characteristics Table 9. Supply Current Characteristics This section includes information about power supply current in various operating modes. Num 1 C C T Parameter Run supply current FEI mode, all modules on, running from Flash Run supply current FEI mode, all modules off, running from Flash Run supply current LPRS=0, all modules off, running from Flash Symbol RIDD Bus Freq 20 MHz 2 MHz VDD (V) 3 Typ1 17.4 2.6 10.5 Max TBD TBD — — — — — — — — TBD TBD — — Unit mA Temp (°C) –40 to 85°C 2 C T RIDD 20 MHz 2 MHz 3 3 mA –40 to 85°C 1.6 158 148 3 T T RIDD 16 kHz FBILP 16 kHz FBELP μA –40 to 85°C 4 T T Run supply current LPRS=1, all modules off; running from Flash RIDD 16 kHz FBILP 16 kHz FBELP 3 160 23 μA –40 to 85°C 5 T T Run supply current LPRS=1, all modules off; running from RAM Wait mode supply current, all modules off RIDD 16 kHz FBILP 16 kHz FBELP 3 137 8 μA –40 to 85°C 6 C C WIDD WIDD 20 MHz 2 MHz 16 kHz FBILP 16 kHz FBELP 3 5.4 1.1 mA μA μA –40 to 85°C –40 to 85°C –40 to 85°C 7 T T 3 3 131 123 Wait mode supply current LPRS = 0, all modules off MC9S08GW64 Series MCU Data Sheet, Rev. 1 18 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics Table 9. Supply Current Characteristics Num 8 C T T 9 C Parameter Symbol WIDD Wait mode supply current LPRS = 1, all modules off Stop2 mode supply current S2IDD Bus Freq 16 kHz FBILP 16 kHz FBELP N/A VDD (V) 3 3 3 Typ1 159 5.6 300 TBD TBD TBD N/A C 2 TBD TBD TBD 10 P Stop3 mode supply current No clocks active S3IDD N/A 3 474 TBD TBD TBD N/A C 1 Max — — TBD — TBD — — — — TBD — TBD — — — — Unit μA μA Temp (°C) –40 to 85°C –40 to 85°C –40 to 25°C 50°C 70°C 85°C –40 to 25°C 70°C 85°C –40 to 25°C 50°C 70°C 85°C –40 to 25°C 70°C 85°C nA nA 2 TBD TBD TBD Typical values are measured at 25°C. Characterized, not tested. Table 10. Stop Mode Adders Temperature (°C) Num 1 2 3 4 5 6 7 C T T T T T T T LPO ERREFSTEN IREFSTEN LVD1 PRACMP1 VREFO IRTC 1 Parameter Condition -40 TBD RANGE = HGO = 0 TBD TBD LVDSE = 1 Not using the bandgap (BGBE = 0) Not using the bandgap (BGBE = 0) Not using the bandgap (BGBE = 0) TBD TBD TBD TBD 25 TBD TBD TBD TBD TBD TBD TBD 70 TBD TBD TBD TBD TBD TBD TBD 85 TBD TBD TBD TBD TBD TBD TBD Units nA nA μA μA μA μA μA MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 19 Electrical Characteristics Table 10. Stop Mode Adders (continued) Temperature (°C) Num 8 9 C T T Parameter ADC1 LCD Condition -40 ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for driving 192 Segments, 32Hz frame rate, No LCD glass connected. 32KHz clock, without PWM output 32KHz clock, with PWM output TBD TBD 25 TBD TBD 70 TBD TBD 85 TBD TBD μA μA Units 10 11 1 T T PCNT1 PCNT1 TBD TBD TBD TBD TBD TBD TBD TBD μA μA Not available in stop2 mode. 3.8 External Oscillator (XOSCVLP) Characteristics Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient) Reference Figure 13 and Figure 14 for crystal or resonator circuits. Num 1 C Characteristic Symbol Min Typ1 Max Unit C Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) D Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings D Feedback resistor Low range, low power (RANGE=0, HGO=0)2 Low range, high gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) D Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz C Crystal start-up time 4 Low range, low power Low range, high gain High range, low power High range, high gain t t flo fhi fhi 32 1 1 — — — 38.4 16 8 kHz MHz MHz 2 C1,C2 See Note 2 See Note 3 MΩ — — — — — — — — — — — — — — 10 1 — 100 0 0 0 0 600 400 5 15 — — — — — — 0 10 20 — — — — 3 RF 4 RS kΩ 5 CSTL ms CSTH MC9S08GW64 Series MCU Data Sheet, Rev. 1 20 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient) Num 6 C Characteristic Symbol Min Typ1 Max Unit D Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode FBE or FBELP mode fextal 0.03125 0 — — 20 20 MHz MHz Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. 1 2 XOSCVLP EXTAL XTAL RS RF C1 Crystal or Resonator C2 Figure 13. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure 14. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Internal Clock Source (ICS) Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) Num 1 2 3 C P P T Characteristic Average internal reference frequency — factory trimmed at VDD = 3.6 V and temperature = 25 °C Average internal reference frequency - trimmed Internal reference start-up time Symbol fint_ft fint_t tIRST Min — 31.25 — Typ1 32.768 — — Max — 39.063 6 Unit kHz kHz μs MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 21 Electrical Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued) Num 4 5 6 7 8 9 10 11 1 2 C P P C C C C Characteristic DCO output frequency range - untrimmed DCO output frequency range - trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Total deviation from trimmed DCO output frequency over voltage and temperature Total deviation from trimmed DCO output frequency over fixed voltage and temperature range of 0°C to 70 °C Symbol fdco_ut fdco_t Δfdco_res_t Δfdco_res_t Δfdco_t Δfdco_t tAcquire CJitter Min 12.8 16 — — — — — — Typ1 16.8 — ± 0.1 ± 0.2 + 0.5 -1.0 ± 0.5 — 0.02 Max 21.33 20 ± 0.2 ± 0.4 ±2 ±1 1 0.2 Unit MHz MHz %fdco %fdco %fdco %fdco ms %fdco C FLL acquisition time 2 C Long term jitter of DCO output clock (averaged over 2-ms interval) 3 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter percentage for a given interval. MC9S08GW64 Series MCU Data Sheet, Rev. 1 22 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics Figure 15. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 23 Electrical Characteristics 3.10.1 Control Timing Table 13. Control Timing Num 1 2 3 4 5 6 7 C D D D D D D Rating Bus frequency (tcyc = 1/fBus) Internal low power oscillator period External reset pulse width2 Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time — Non-LCD Pins Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Symbol fBus tLPO textrst trstdrv tMSSU tMSH Min dc 700 100 34 x tcyc 500 100 Typ1 — — — — — — Max 20 1300 — — — — Unit MHz μs ns ns ns μs D tILIH, tIHIL 100 1.5 x tcyc 100 1.5 x tcyc — — — — — — — — ns 8 D tILIH, tIHIL ns 9 tRise, tFall — — 16 23 — — ns C Port rise and fall time — Non-LCD Pins High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 10 1 2 3 4 5 6 tRise, tFall — — — 5 9 6 — — 10 ns C Voltage Regulator Recovery time tVRR us Typical values are based on characterization data at VDD = 3.0 V, 25°C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C. Except for LCD pins in Open Drain mode. textrst RESET PIN Figure 16. Reset Timing MC9S08GW64 Series MCU Data Sheet, Rev. 1 24 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 17. IRQ/KBIPx Timing 3.10.2 Timer (TPM/FTM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TPM Input Timing No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW tTCLK tclkh Min 0 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit Hz tcyc tcyc tcyc tcyc TCLK tclkl Figure 18. Timer External Clock tICPW FTMCHn FTMCHn tICPW MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 25 Electrical Characteristics 3.10.3 SPI Timing Table 15. SPI Timing No. — D C Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol fop fBus/2048 0 tSPSCK 2 4 tLead 1/2 1 1/2 1 tcyc – 30 tcyc – 30 tSU 30 30 tHI 0 25 ta tdis tv — — tHO 0 0 tRI tRO tFI tFO — — — — — — tcyc – 25 25 tcyc – 25 25 ns ns ns ns ns ns 60 60 ns ns — — — — 1 1 ns ns tcyc tcyc — — ns ns 2048 — — — — — 1024 tcyc — tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns fBus/2 fBus/4 Min Max Unit Hz Table 15 and Figure 19 through Figure 22 describe the timing requirements for the SPI system1,2. 1 D 2 D tLag 3 D tWSPSCK 4 D 5 D 6 D 7 8 9 D D D 10 D 11 D 12 D 1.There is 20 pF load on the SPI ports. 2.There are three types of SPI ports in MC9S08GW64 Series. They are ports for AMR, ports shared with LCD pads and normal ports. This timing is for normal ports condition. MC9S08GW64 Series MCU Data Sheet, Rev. 1 26 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 MS BIN2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 19. SPI Master Timing (CPHA = 0) SS1 (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 4 4 11 12 12 11 3 5 MSB IN2 6 BIT 6 . . . 1 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 20. SPI Master Timing (CPHA =1) MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 27 Electrical Characteristics SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT) NOTE: 12 11 3 4 4 11 12 8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1 10 10 SEE NOTE 1 SLAVE LSB OUT LSB IN 1. Not defined but normally MSB of character just received. Figure 21. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 1 7 MOSI (INPUT) 2 12 3 11 4 4 11 12 9 SLAVE 5 MSB IN MSB OUT 6 10 BIT 6 . . . 1 SLAVE LSB OUT 8 BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received. Figure 22. SPI Slave Timing (CPHA = 1) MC9S08GW64 Series MCU Data Sheet, Rev. 1 28 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics 3.11 Analog Comparator (PRACMP) Electricals Table 16. PRACMP Electrical Specifications N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C D C C C D C C P C C C C C C Characteristic Supply voltage Supply current (active) (PRG enabled) Supply current (active) (PRG disabled) Supply current (ACMP and PRG all disabled) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Programmable reference generator inputs Programmable reference generator inputs Programmable reference generator setup delay Programmable reference generator step size Programmable reference generator voltage range Symbol VPWR IDDACT1 IDDACT2 IDDDIS VAIN VAIO VH IALKG tAINIT VIn1(VDD) VIn2(VDD25) tPRGST Vstep Vprgout Min 1.8 — — — VSS – 0.3 — 3.0 — — 1.8 1.8 TBD –0.25 VIn/32 Typical — — — — — 5 — — — — — TBD 1 — Max 3.6 60 40 2 VDD 40 20.0 1 1.0 VDD 2.75 TBD 0.25 Vin Unit V μA μA nA V mV mV nA μs V V ns LSB V 3.12 ADC Characteristics These specs all assume seperate VDDAD supply for ADC and isolated pad segment for ADC supplies and differential inputs.. Spec’s should be de-rated for VREFH = Vbg condition. Table 17. 16-bit ADC Operating Conditions Num 1 2 3 Supply voltage Ground voltage Ref Voltage High Charact eristic Conditions Absolute Delta to VDD (VDD–VDDA) 2 Symb VDDA ΔVDDA ΔVSSA Min 1.8 –100 –100 Typ1 — 0 0 Max 3.6 100 100 Unit V mV mV Comment Delta to VSS (VSS–VSSA)2 4 VREFH 1.15 VDDA VDDA V MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 29 Electrical Characteristics Table 17. 16-bit ADC Operating Conditions Num Charact eristic Ref Voltage Low Input Voltage Input Capacit ance Input Resista nce 16 bit modes fADCK > 8MHz 4MHz < fADCK < 8MHz fADCK < 4MHz 13/12 bit modes fADCK > 8MHz 4MHz < fADCK < 8MHz fADCK < 4MHz 11/10 bit modes fADCK > 8MHz 4MHz < fADCK < 8MHz fADCK < 4MHz 9/8 bit modes fADCK > 8MHz fADCK < 8MHz ADC Convers ion Clock Freq. ADLPC = 0, ADHSC = 1 ADLPC = 0, ADHSC = 0 ADLPC = 1, ADHSC = 0 fADCK 16-bit modes 8/10/12-bit modes Conditions Symb Min Typ1 Max Unit Comment 5 VREFL VSSA VSSA VSSA V 6 VADIN VREFL — 8 4 VREFH 10 5 V 7 CADIN — pF 8 RADIN — 2 5 kΩ 9 — — — — — — — — — — — 1.0 1.0 1.0 — — — — — — — — — — — — — — 0.5 1 2 1 2 5 2 5 10 5 10 10 5 2.5 MHz 10 Analog Source Resista nce External to MCU kΩ Assumes ADLSMP=0 RAS 11 12 13 14 15 1 Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. MC9S08GW64 Series MCU Data Sheet, Rev. 1 30 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + – + – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 23. ADC Input Impedance Equivalency Diagram Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDAD, VREFL = VSSAD, FADCK < 10MHz) Characteristic Supply Current Conditions1 ADLPC = 1, ADHSC = 0 ADLPC = 0, ADHSC = 0 ADLPC=0, ADHSC=1 Supply Current ADC Asynchronous Clock Source Stop, Reset, Module Off ADLPC = 1, ADHSC = 0 ADLPC = 0, ADHSC = 0 ADLPC = 0, ADHSC = 1 Sample Time Conversion Time 1 2 C Symb Min — Typ2 215 540 610 0.072 2.4 5.2 6.2 Max — — — — — — — Unit Comment T IDDA — — μA ADLSMP = 0 ADCO = 1 C IDDA — — μA P fADACK — — MHz tADACK = 1/fADACK See reference manual for sample times See reference manual for conversion times All accuracy numbers assume the ADC is calibrated with VREFH = VDDAD Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. MC9S08GW64 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 31 Electrical Characteristics Table 19. 16-bit ADC Characteristics(VREFH = VDDAD > 2.7V, VREFL = VSSAD, FADCK < 4MHz, ADHSC=1) Characteristic Total Unadjusted Error Conditions1 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Differential Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Integral Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Zero-Scale Error 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode C T T T T T T T T T T T T T T T T EZS INL DNL Symb TUE Min — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Typ2 ±16 ±20 ±1.5 ±1.75 ±0.7 ±0.8 ±0.5 ±0.5 ±2.5 ±2.5 ±0.7 ±0.7 ±0.5 ±0.5 ±0.2 ±0.2 ±6.0 ±10.0 ±1.0 ±1.0 ±0.5 ±0.5 ±0.3 ±0.3 ±4.0 ±4.0 ±0.7 ±0.7 ±0.4 ±0.4 ±0.2 ±0.2 Max +24/-24 +32/-20 ±2.0 ±2.5 ±1.0 ±1.25 ±1.0 ±1.0 ±3 ±3 ±1 ±1 ±0.75 ±0.75 ±0.5 ±0.5 ±12.0 ±16.0 ±2.0 ±2.0 ±1.0 ±1.0 ±0.5 ±0.5 +16/0 +16/-38 ±2.0 ±2.0 ±1.0 ±1.0 ±0.5 ±0.5 LSB2 VADIN = VSSAD LSB2 LSB2 Unit LSB3 Comment 32x Hardware Averaging (AVGE = %1 AVGS = %11) MC9S08GW64 Series MCU Data Sheet, Rev. 1 32 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Electrical Characteristics Table 19. 16-bit ADC Characteristics(VREFH = VDDAD > 2.7V, VREFL = VSSAD, FADCK < 4MHz, ADHSC=1) Characteristic Full-Scale Error Conditions1 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Quantization Error Effective Number of Bits 16 bit modes