MC9S08JE128VMB

Freescale Semiconductor Data Sheet: Advanced Information An Energy-Efficient Solution from Freescale Document Number: MC9S08JE128 Rev. 3, 04/2010 Covers: MC9S08JE128 and MC9S08JE64 – 8-Bit HCS08 Central Processor Unit (CPU) – – – – – – Up to 48-MHz CPU above 2.4 V, 40 MHz CPU above 2.1 V, and 20 MHz CPU above 1.8 V across temperature of -40°C to 105°C HCS08 instruction set with added BGND instruction Support for up to 32 interrupt/reset sources 128 K Dual Array Flash read/program/erase over full operating voltage and temperature 12 KB Random-access memory (RAM) Security circuitry to prevent unauthorized access to RAM and Flash Two ultra-low power stop modes. Peripheral clock enable register can disable clocks to unused modules to reduce currents Time of Day (TOD) — Ultra-low power 1/4 sec counter with up to 64s timeout. Ultra-low power external oscillator that can be used in stop modes to provide accurate clock source to the TOD. 6 usec typical wake up time from stop3 mode Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or ceramic resonator dedicated for TOD operation. Oscillator (XOSC2) — for high frequency crystal input for MCG reference to be used for system clock and USB operations. Multipurpose Clock Generator (MCG) — PLL and FLL; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports CPU frequencies from 4 kHz to 48 MHz. Watchdog computer operating properly (COP) reset Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock Low-voltage detection with reset or interrupt; selectable trip points; separate low-voltage warning with optional interrupt; selectable trip points Illegal opcode and illegal address detection with reset Flash block protection for each array to prevent accidental write/erasure Hardware CRC to support fast cyclic redundancy checks Single-wire background debug interface Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1 data) Breakpoint capability to allow single breakpoint setting during in-circuit debugging On-chip in-circuit emulator (ICE) debug module containing 3 comparators and 9 trigger modes CMT— Carrier Modulator timer for remote control communications. Carrier generator, modulator and driver for dedicated infrared out. Can be used as an output compare timer. IIC— Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven 64-LQFP 10mm x 10mm 80-LQFP 12mm x 12mm 81-MapBGA 10mm x10mm – On-Chip Memory – – Power-Saving Modes – – – – – Clock Source Options – – – – – System Protection – – – – byte-by-byte data transfer; supports broadcast mode and 11-bit addressing PRACMP — Analog comparator with selectable interrupt; compare option to programmable internal reference voltage; operation in stop3 SCI — Two serial communications interfaces with optional 13-bit break; option to connect Rx input to PRACMP output on SCI1 and SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge SPI1— Serial peripheral interface (SPI) with 64-bit FIFO buffer; 16-bit or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting SPI2— Serial peripheral interface with full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting TPM — Two 4-channel Timer/PWM Module; Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; external clock input/pulse accumulator USB — Supports USB in full-speed device configuration. On-chip transceiver and 3.3V regulator help save system cost, fully compliant with USB Specification 2.0. Allows control, bulk, interrupt and isochronous transfers. ADC12 — 12-bit Successive approximation ADC with up to 4 dedicated differential channels and 8 single-ended channels; range compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V, Configurable hardware trigger for 8 Channel select and result registers PDB — Programmable delay block with 16-bit counter and modulus and prescale to set reference clock to bus divided by 1 to bus divided by 2048; 8 trigger outputs for ADC12 module provides periodic coordination of ADC sampling sequence with sequence completion interrupt; Back-to-Back mode and Timed mode DAC — 12-bit resolution; 16-word data buffers with configurable watermark. Up to 47 GPIOs and 2 output-only pin and 1 input-only pin. Voltage Reference output (VREFO). Dedicated infrared output pin (IRO) with high current sink capability. Up to 16 KBI pins with selectable polarity. 81-MBGA 10x10 mm 80-LQFP 12x12 mm 64-LQFP 10x10 mm – – – – – Input/Output – – – – – – – Development Support Package Options – Peripherals – – This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages MC9S08JE128 series Contents 1 Devices in the MC9S08JE128 series.................. 3 2 Preliminary Electrical Characteristics............. 12 2.1 Parameter Classification ......................................................... 2.2 Absolute Maximum Ratings .................................................... 2.3 Thermal Characteristics .......................................................... 2.4 Electrostatic Discharge (ESD) Protection Characteristics ...... 2.5 DC Characteristics .................................................................. 2.6 Supply Current Characteristics ............................................... 2.7 Comparator (PRACMP) Electricals......................................... 2.8 12-Bit Digital-to-Analog Converter (DAC12LV) Electricals ...... 2.9 ADC Characteristics................................................................ 2.10 MCG and External Oscillator (XOSC) Characteristics .......... 2.11 AC Characteristics ................................................................ 2.12 SPI Characteristics ............................................................... 2.13 Flash Specifications .............................................................. 2.14 USB Electricals ..................................................................... 12 13 14 15 16 19 21 22 23 28 31 32 35 36 2.15 VREF Specifications............................................................. 35 3 Ordering Information......................................... 41 3.1 Device Numbering System..................................................... 42 3.2 Package Information............................................................... 42 3.3 Mechanical Drawings ............................................................. 42 4 Revision History ................................................ 43 Related Documentation Find the most current versions of all documents at: http://www.freescale.com. Reference Manual —MC9S08JE128RM Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. – This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Devices in the MC9S08JE128 series 1 Devices in the MC9S08JE128 series Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 3 The following table summarizes the feature set available in the MC9S08JE128 series of MCUs. Table 1. MC9S08JE128 series Features by MCU and Package Feature Pin quantity FLASH size (bytes) RAM size (bytes) Programmable Analog Comparator (PRACMP) Debug Module (DBG) Multipurpose Clock Generator (MCG) Inter-Integrated Communication (IIC) Interrupt Request Pin (IRQ) Keyboard Interrupt (KBI) Port I/O1 Dedicated Analog Input Pins Power and Ground Pins Time Of Day (TOD) Serial Communications (SCI1) Serial Communications (SCI2) Serial Peripheral Interface 1 (SPI1 (FIFO)) Serial Peripheral Interface 2 (SPI2) Carrier Modulator Timer pin (IRO) TPM input clock pin (TPMCLK) TPM1 channels TPM2 channels XOSC1 XOSC2 USB Programmable Delay Block (PDB) SAR ADC differential channels2 SAR ADC single-ended channels Voltage reference output pin (VREFO) 1 2 MC9S08JE128 81 80 131072 12K yes yes yes yes yes 16 47 16 46 12 8 yes yes yes yes yes yes yes 4 4 4 yes yes yes yes 4 8 4 8 yes 3 6 2 7 33 64 MC9S08JE64 64 65535 12K yes yes yes yes yes 7 33 12 8 yes yes yes yes yes yes yes 4 2 yes yes yes yes 3 6 yes Port I/O count does not include two (2) output-only and one (1) input-only pins. Each differential channel is comprised of 2 pin inputs. Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Devices in the MC9S08JE128 series A complete description of the modules included on each device is provided in the following table. Table 2. Versions of On-Chip Modules Module Analog-to-Digital Converter (ADC12) Digital to Analog Converter (DAC) Programmable Delay Block Inter-Integrated Circuit (IIC) Central Processing Unit (CPU) On-Chip In-Circuit Debug/Emulator (DBG) Multi-Purpose Clock Generator (MCG) Low Power Oscillator (XOSCVLP) Carrier Modulator Timer (CMT) Programable Analog Comparator (PRACMP) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Time of Day (TOD) Universal Serial Bus (USB) Timer Pulse-Width Modulator (TPM) System Integration Module (SIM) Cyclic Redundancy Check (CRC) Keyboard Interrupt (KBI) Voltage Reference (VREF) Voltage Regulator (VREG) Interrupt Request (IRQ) Flash Wrapper GPIO Port Control Version 1 1 1 3 5 3 3 1 1 1 4 5 1 1 3 1 3 2 1 1 3 1 2 1 The block diagram in Figure 1 shows the structure of the MC9S08JE128 series MCU. 4 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Freescale Semiconductor Devices in the MC9S08JE128 series Figure 1. MC9S08JE128 series Block Diagram Non-Disclosure Agreement Required Preliminary — Subject to Change 5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Devices in the MC9S08JE128 series 1.1 Pin Assignments Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages This section shows the pin assignments for the MC9S08JE128 series devices. 1.1.1 64-Pin LQFP The following two figures show the 64-pin LQFP pinout configuration. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VDD1 VSS1 VBUS USB_DP USB_DM VUSB33 PTF2/TX2/TPM2CH0 PTF1/RX2/TPM2CH1 PTE6/RX2 PTE5/TX2 VDD3 VSS3 PTE4/CMPP3/TPMCLK/IRQ PTA0/SS1 IRO PTA4 PTA5 PTA6 PTA7 PTB0 PTB1/BLMS VSSA VREFL NC NC DADP2 NC DADM2 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTD7/RX1 PTD6/TX1 PTD5/SCL/TPM1CH3 PTD4/SDA/TPM1CH2 PTD3/TPM1CH1 PTD2/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2 PTC0/MOSI2 NC DACO DADP3 NC DADM3 DADP0 DADM0 VREFO Figure 2. 64-Pin LQFP 6 VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Devices in the MC9S08JE128 series 1.1.2 80-Pin LQFP Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 7 The following figure shows the 80-pin LQFP pinout configuration. PTA0/SS1 IRO PTA1/KBI1P0/TX1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/ADP5 PTA4 PTA5 PTA6 PTA7 PTB0 PTB1/BLMS VSSA VREFL NC NC DADP2 NC DADM2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VDD1 VSS1 VBUS USB_DP USB_DM VUSB33 PTF5/KBI2P7 PTF4/SDA PTF3/SCL PTF2/TX2/TPM2CH0 PTF1/RX2/TPM2CH1 PTF0/TPM2CH2 PTE7/TPM2CH3 PTE6/RX2 PTE5/TX2 VDD3 VSS3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80-LQFP PTE4/CMPP3/TPMCLK/IRQ PTE3/KBI2P6 PTE2/KBI2P5 PTE1/KBI2P4 PTE0/KBI2P3 PTD7/RX1 PTD6/TX1 PTD5/SCL/TPM1CH3 PTD4/SDA/TPM1CH2 PTD3/TPM1CH1 PTD2/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change DADM0 VREFO DADP1 DADM1 VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 PTB6/KBI1P3 PTB7/KBI1P4 PTC0/MOSI2 DADP3 NC DADM3 DADP0 DACO 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 3. 80-Pin LQFP Devices in the MC9S08JE128 series 1.1.3 81-Pin MAPBGA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages The following figure shows the 81-pin MAPBGA pinout configuration. 1 2 3 4 5 6 7 8 9 A IRO PTG0 PTF6 USB_DP VBUS VUSB33 PTF4 PTF3 PTE4 B PTF7 PTA0 PTG1 USB_DM PTF5 PTE7 PTF1 PTF0 PTE3 C PTA4 PTA5 PTA6 PTA1 PTF2 PTE6 PTE5 PTE2 PTE1 D PTA7 PTB0 PTB1 PTA2 PTA3 PTD5 PTD7 PTE0 E DADM2 VDD2 VDD3 VDD1 PTD2 PTD3 PTD6 F DADP2 VSS2 VSS3 VSS1 PTB7 PTC7 PTD4 G DADP0 DACO DADP3 DADM3 VREFO PTB6 PTC0 PTC1 PTC2 H DADM0 DADM1 DADP1 PTC3 PTC4 PTD0 PTC5 PTC6 J VSSA VREFL VREFH VDDA PTB2 PTB3 PTD1 PTB4 PTB5 Figure 4. 81-Pin MAPBGA 8 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Devices in the MC9S08JE128 series 1.2 Pin Assignments by Packages Table 3. Package Pin Assignments Package Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 9 81 MAPBGA 80 LQFP 64 LQFP Default Function ALT1 ALT2 ALT3 Composite Pin Name B2 A1 C4 D5 D6 C1 C2 C3 D2 D3 D4 J1 J2 D1 E1 F2 F1 E2 F3 E3 G2 G3 H4 G4 G1 H1 G5 H3 H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 — — — 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 — — PTA0 IRO PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTA7 PTB0 PTB1 VSSA VREFL NC NC DADP2 NC DADM2 NC NC DACO DADP3 NC DADM3 DADP0 DADM0 VREFO DADP1 DADM1 SS1 — KBI1P0 KBI1P1 KBI1P2 — — — — — BLMS — — — — — — — — — — — — — — — — — — — — TX1 RX1 ADP5 — — — — — — — — — — — — — — — — — — — — — — — — — — — ADP4 — — — — — — — — — — — — — — — — — — — — — — — — — PTA0/SS1 IRO PTA1/KBI1P0/TX1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/ADP5 PTA4 PTA5 PTA6 PTA7 PTB0 PTB1/BLMS VSSA VREFL NC NC DADP2 NC DADM2 NC NC DACO DADP3 NC DADM3 DADP0 DADM0 VREFO DADP1 DADM1 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Devices in the MC9S08JE128 series Table 3. Package Pin Assignments (Continued) Package 81 MAPBGA ALT1 ALT2 ALT3 Composite Pin Name Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 80 LQFP 64 LQFP 25 26 27 28 29 30 31 32 — — 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 — — — — 49 Default Function J3 J4 F4 J5 J6 E4 J8 J9 G6 F7 G7 G8 G9 H5 H6 H8 H9 F8 H7 J7 E7 E8 F9 D7 E9 D8 D9 C9 C8 B9 A9 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VREFH VDDA VSS2 PTB2 PTB3 VDD2 PTB4 PTB5 PTB6 PTB7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 PTE0 PTE1 PTE2 PTE3 PTE4 — — — EXTAL1 XTAL1 — EXTAL2 XTAL2 KBI1P3 KBI1P4 MOSI2 MISO2 KBI1P5 KBI1P6 KBI1P7 KBI2P0 KBI2P1 KBI2P2 BKGD CMPP2 TPM1CH0 TPM1CH1 SDA SCL TX1 RX1 KBI2P3 KBI2P4 KBI2P5 KBI2P6 CMPP3 — — — — — — — — — — — — SPSCK2 SS2 CMPP0 CMPP1 PRACMPO CLKOUT MS RESET — — TPM1CH2 TPM1CH3 — — — — — — TPMCLK — — — — — — — — — — — — ADP6 ADP7 ADP8 ADP9 ADP10 ADP11 — — — — — — — — — — — — IRQ VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 PTB6/KBI1P3 PTB7/KBI1P4 PTC0/MOSI2 PTC1/MISO2 PTC2/KBI1P5/SPSCK2/ADP6 PTC3/KBI1P6/SS2/ADP7 PTC4/KBI1P7/CMPP0/ADP8 PTC5/KBI2P0/CMPP1/ADP9 PTC6/KBI2P1/PRACMPO/ADP10 PTC7/KBI2P2/CLKOUT/ADP11 PTD0/BKGD/MS PTD1/CMPP2/RESET PTD2TPM1CH0 PTD3/TPM1CH1 PTD4/SDA/TPM1CH2 PTD5/SCL/TPM1CH3 PTD6/TX1 PTD7/RX1 PTE0/KBI2P3 PTE1/KBI2P4 PTE2/KBI2P5 PTE3/KBI2P6 PTE4/CMPP3/TPMCLK/IRQ 10 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Devices in the MC9S08JE128 series Table 3. Package Pin Assignments (Continued) Package 81 MAPBGA ALT1 ALT2 ALT3 Composite Pin Name Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 11 80 LQFP 64 LQFP 50 51 52 53 — — 54 55 — — — 56 57 58 59 60 61 62 63 64 — Default Function F5 E5 C7 C6 B6 B8 B7 C5 A8 A7 B5 A6 B4 A4 A5 F6 E6 A3 B1 A2 B3 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 — VSS3 VDD3 PTE5 PTE6 PTE7 PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 VUSB33 USB_DM USB_DP VBUS VSS1 VDD1 PTF6 PTF7 PTG0 PTG1 — — TX2 RX2 TPM2CH3 TPM2CH2 RX2 TX2 SCL SDA KBI2P7 — — — — — — MOSI1 MISO1 SPSCK1 — — — — — — — TPM2CH1 TPM2CH0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VSS3 VDD3 PTE5/TX2 PTE6/RX2 PTE7/TPM2CH3 PTF0/TPM2CH2 PTF1/RX2/TPM2CH1 PTF2/TX2/TPM2CH0 PTF3/SCL PTF4/SDA PTF5/KBI2P7 VUSB33 USB_DM USB_DP VBUS VSS1 VDD1 PTF6/MOSI1 PTF7/MISO1 PTG0/SPSCK1 PTG1 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2 Preliminary Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages This section contains electrical specification tables and reference timing diagrams for the MC9S08JE128/64 microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this data sheet supersede any values found in the module specifications. 2.1 Parameter Classification Table 4. Parameter Classifications P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: T D NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 12 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.2 Absolute Maximum Ratings Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. Table 5. Absolute Maximum Ratings # 1 2 3 4 5 1 Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range Symbol VDD IDD VIn ID Tstg Value –0.3 to +3.8 120 –0.3 to VDD + 0.3 ± 25 –55 to 150 Unit V mA V mA °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). Freescale Semiconductor 13 Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.3 Thermal Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 6. Thermal Characteristics # 1 Symbol TA Rating Operating temperature range (packaged): MC9S08JE128 MC9S08JE64 2 3 TJMAX θJA Maximum junction temperature Thermal resistance1,2,3,4 Single-layer board — 1s 81-pin MBGA 80-pin LQFP 64-pin LQFP 4 θJA Thermal resistance1, 2, 3, 4 Four-layer board — 2s2p 81-pin MBGA 80-pin LQFP 64-pin LQFP 47 40 49 77 55 68 °C/W –40 to 105 –40 to 105 135 °C °C/W Value Unit °C 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s — Single layer board, one signal layer 4 2s2p — Four layer board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) where: Eqn. 1 TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 2.7 V all digital 0.85 x VDD inputs, 2.7 V > VDD ≥ 1.8 V — — V P — — V P 16 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 9. DC Characteristics (Continued) Num Symbol 7 VIL Characteristic Input low voltage all digital inputs all digital inputs, VDD > 2.7 V all digital inputs, 2.7 > VDD ≥ 1.8 V 8 Vhys |IIn| 9 |IOZ| |IOZ| 11 Input hysteresis Input leakage current Hi-Z (off-state) leakage current Leakage current for analog output pins (DACO, VREFO) Total Leakage Current3 Pull-up resistors Internal pull-down resistors4 DC injection current 5, 6, 7 Single pin limit VSS > VIN > VDD all digital inputs — — — 0.35 x VDD 0.30 x VDD V P V P Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 17 Condition Min Typ1 Max Unit C — — 0.06 x VDD — — — — 0.25 (TBD) 1(TBD) (TBD) mV μA C all input only VIn = VDD or pins VSS (Per pin) all input/output VIn = VDD or (per pin) VSS all input/output VIn = VDD or (per pin) VSS P μA μA P 10 — — — — P 12 13 14 |IInT| RPU RPD For all pins — — — 17.5 17.5 — — — 2 52.5 52.5 μA kΩ kΩ D P P 15 IIC –0.2 — 0.2 mA D Total MCU limit, includes sum of all stressed pins VSS > VIN > VDD 16 17 18 19 CIn VRAM VPOR tPOR Input Capacitance, all pins RAM retention voltage POR re-arm voltage8 POR re-arm time — — — — –5 — — 0.9 10 — — 0.6 1.4 — 5 8 1.0 1.79 — mA pF V V μs D C C C D Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 9. DC Characteristics (Continued) Num Symbol Characteristic VDD falling Condition Min Typ1 Max Unit C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 20 VLVDH9 Low-voltage detection threshold — high range — VDD rising — VLVDL 21 Low-voltage detection threshold — low range9 VDD falling 2.11 2.16 2.22 V P 2.16 2.23 2.27 V P — VDD rising — VLVWH Low-voltage warning threshold — high range9 VDD falling 1.80 1.84 1.88 V P 1.88 1.93 1.96 V P 22 — VDD rising — VLVWL Low-voltage warning threshold — low range9 VDD falling 2.36 2.46 2.56 V P 2.36 2.46 2.56 V P 23 — VDD rising — 24 25 Vhys VBG Low-voltage inhibit reset/recover hysteresis10 Bandgap Voltage Reference11 — — 2.11 2.16 2.22 V P 2.16 — 1.15 2.23 50 1.17 2.27 — 1.18 V mV V P C P 1 2 3 4 5 6 Typical values are measured at 25°C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. Total Leakage current is the sum value for all GPIO pins; this leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. Measured with VIn = VDD. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 18 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 7 Freescale Semiconductor 19 Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 8 Maximum is highest voltage that POR is guaranteed. 9 Run at 1 MHz bus frequency 10 Low voltage detection and warning limits measured at 1 MHz bus frequency. 11 Factory trimmed at VDD = 3.0 V, Temp = 25°C Preliminary Electrical Characteristics 2.6 # Supply Current Characteristics Table 10. Supply Current Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Symbol RIDD 1 Parameter Run supply current Bus Freq VDD (V) Typ1 Max Unit Temp (°C) C FEI mode All modules ON 24 MHz 24 MHz 20 MHz 8 MHz 1 MHz RIDD 2 Run supply current FEI mode; All modules OFF 3 3 3 3 3 20 20 18 8 1.8 24 TBD — — — mA mA mA mA mA –40 to 25 105 –40 to 105 –40 to 105 –40 to 105 P P T T T 24 MHz 20 MHz 8 MHz 1 MHz RIDD 3 Run supply current LPS=0; All modules OFF 3 3 3 3 12.3 10.5 4.8 1.3 TBD — — — mA mA mA mA –40 to 105 –40 to 105 –40 to 105 –40 to 105 C T T T 16 kHz FBILP 16 kHz FBELP 4 RIDD Run supply LPS=1, all modules OFF current 3 3 TBD TBD — — μA μA –40 to 105 –40 to 105 T T 16 kHz FBELP 16 kHz FBELP 3 3 TBD TBD — — μA μA 0 to 70 –40 to 105 T T 20 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 10. Supply Current Characteristics (Continued) # Symbol Parameter Bus Freq VDD (V) Typ1 Max Unit Temp (°C) C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 21 5 WIDD Wait mode FEI mode, all modules OFF supply current 24 MHz 20 MHz 8 MHz 1 MHz 6 S2IDD Stop2 mode supply current 3 3 3 3 TBD TBD TBD TBD 6 — — — mA mA mA mA –40 to 105 –40 to 105 –40 to 105 –40 to 105 C T T T N/A N/A N/A N/A N/A N/A N/A N/A 7 S3IDD Stop3 mode No clocks active supply current 3 3 3 3 2 2 2 2 0.39 TBD 7 16 TBD TBD TBD TBD 0.6 TBD TBD TBD TBD TBD TBD TBD µA µA µA µA µA µA µA µA –40 to 25 70 85 105 –40 to 25 70 85 105 P C C P C C C C N/A N/A N/A N/A N/A N/A N/A N/A 3 3 3 3 2 2 2 2 0.55 TBD 14 37 TBD TBD 14 TBD 0.9 TBD TBD TBD TBD TBD TBD TBD µA µA µA µA µA µA µA µA –40 to 25 70 85 105 –40 to 25 70 85 105 P C C P C C C C 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 11. Typical Stop Mode Adders Temperature (°C) # 1 2 3 4 5 6 Parameter LPO EREFSTEN IREFSTEN1 TOD LVD1 ACMP1 ADC1 7 DAC1 Condition -40 — RANGE = HGO = 0 — Does not include clock source current LVDSE = 1 Not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) High power mode; no load on DACO 50 600 (TBD) 68 50 114 18 75 25 75 650 (TBD) 70 75 115 20 85 70 100 750 (TBD) 77 100 123 23 100 85 150 850 (TBD) 86 150 135 33 115 105 250 1000 (TBD) 120 250 170 65 165 nA nA µA nA µA µA µA D D T D T T T Units C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 8 1 500 500 500 500 500 µA T Not available in stop2 mode. 2.7 PRACMP Electricals Table 12. PRACMP Electrical Specifications # 1 2 3 4 5 6 7 8 9 Characteristic Supply voltage Supply current (active) (PRG enabled) Supply current (active) (PRG disabled) Supply current (ACMP and PRG all disabled) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Symbol VPWR IDDACT1 IDDACT2 IDDDIS VAIN VAIO VH IALKG tAINIT Min 1.8 — — — VSS – 0.3 — 3.0 — — Typical — — — — — 5 — — — Max 3.6 60 40 2 VDD 40 20.0 1 1.0 Unit V μA μA nA V mV mV nA μs C P C C D — T T D T 22 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 12. PRACMP Electrical Specifications # 10 11 12 13 Characteristic Programmable reference generator inputs Programmable reference generator setup delay Programmable reference generator step size Programmable reference generator voltage range Symbol VIn2(VDD25) tPRGST Vstep Vprgout Min 1.8 — –0.25 VIn/32 Typical — 1 1 — Max 2.75 — 0.25 Vin Unit V µs LSB V C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 23 — D D P 2.8 12-bit DAC Electricals Table 13. DAC 12LV Operating Requirements # 1 2 3 4 5 Output load current IL Characteristic Supply voltage Reference voltage Temperature Output load capacitance Symbol VDDA VDACR TA CL — — 100 1 pF mA C C Min 1.8 1.15 –40 Max 3.6 3.6 105 V V Unit C P C C Notes °C A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 14. DAC 12-Bit Operating Behaviors Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages # 1 2 3 Characteristic Resolution Supply current low-power mode Supply current high-power mode Full-scale Settling time (±0.5 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) low-power mode Full-scale Settling time (±0.5 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) high-power mode Code-to-code Settling time (±0.5 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) low-power mode Code-to-code Settling time (±0.5 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) high-power mode DAC output voltage range low (high-power mode, no load, DAC set to 0) DAC output voltage range high (high-power mode, no load, DAC set to 0x0FFF) Integral non-linearity error Differential non-linearity error VDACR is > 2.4 V Offset error Gain error Power supply rejection ratio VDD ≥ 2.4 V Temperature drift of offset voltage (DAC set to 0x0800) Offset aging coefficient Symbol N IDDA_DACLP IDDA_DACHP TsFSLP — 200 (TBD) µs C Min 12 50 120 Max 12 100 500 (TBD) Unit bit µA µA C C C C Notes 4 TsFSHP — 30 µs C 5 TsC-CLP — 5 µs C 6 TsC-CHP — 1(TBD) µs C 7 Vdacoutl — 8 100 (TBD) mV C Vdacouth 9 10 11 12 13 14 VDACR100 — — — — 60 — ±8 ±1 ± 0.5 ± 0.5 (TBD) — mV LSB LSB %FSR %FSR dB C C C C C C INL DNL EO EG PSRR Tco 15 16 — 2 (TBD) TBD mV µV/yr C C See Typical Drift figure that follows. Ac — Figure 5. Offset at Half Scale vs Temperature 24 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.9 ADC Characteristics Table 15. 12-bit ADC Operating Conditions # 1 2 3 4 5 6 7 8 Symb Characteristic Conditions Absolute Delta to VDD (VDD-VDDAD)2 Delta to VSS (VSS-VSSAD)2 Min 1.8 -100 -100 1.13 VSSAD VREFL — — Typ1 — 0 0 Max 3.6 +100 +100 Unit V mV mV V V V pF kΩ C D D D D D D C C External to MCU Assumes ADLSMP=0 12-bit mode fADCK > 4 MHz fADCK < 4 MHz 11/10-bit mode fADCK > 8 MHz 4 MHz < fADCK < 8 MHz fADCK < 4 MHz 9/8-bit mode fADCK > 4 MHz fADCK < 4 MHz fADCK 10 ADC Conversion Clock Freq. High Speed (ADLPC=0, ADHSC=1) High Speed (ADLPC=0, ADHSC=0) Low Power (ADLPC=1, ADHSC=1) — — — — — — — 1.0 — — — — — — — — 2 5 2 5 10 5 10 8.0 MHz 1.0 — 5.0 MHz 1.0 — 2.5 MHz D D D kΩ kΩ kΩ kΩ kΩ kΩ kΩ C C C C C C C Comment Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 25 VDDAD Supply voltage ΔVDDAD ΔVSSAD Ground voltage VREFH Ref Voltage High VREFL Ref Voltage Low VADIN Input Voltage VDDAD VDDAD VSSAD VSSAD — 4 2 VREFH 5 5 CADIN Input Capacitance RADIN Input Resistance RAS Analog Source Resistance 9 Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT RAS RADIN ADC SAR ENGINE + VADIN VAS + – CAS – RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 6. ADC Input Impedance Equivalency Diagram 26 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages ZAS Pad leakage due to input protection SIMPLIFIED CHANNEL SELECT CIRCUIT Preliminary Electrical Characteristics Table 16. 12-bit SAR ADC Characteristics full operating range (VREFH = VDDAD, > 1.8, VREFL = VSSAD ≤ 8 MHz) Conditions1 ADLPC=1, ADHSC=0 ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1 Supply Current ADC Asynchronou s Clock Source Sample Time Conversion Time Total Unadjusted Error Stop, Reset, Module Off ADLPC=1, ADHSC=0 ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1 See Block Guide for sample times See Block Guide for conversion times 12-bit single-ended mode TUE — ±1.75 ±3.5 LSB3 T 32x Hardware Averaging (AVGE = %1 AVGS = %11) fADACK IDDAD IDDAD Symb Min — — — — — — — Typ2 215 470 610 0.01 2.4 5.2 6.2 Max — — — — — — — MHz P tADACK = 1/fADACK μA C μA T ADLSMP=0 ADCO=1 Unit C Comment Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 27 Characterist ic Supply Current 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Differential Non-Linearity 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Integral Non-Linearity 12-bit single-ended mode INL DNL — — — — — — — — — — ±0.7 ±0.8 ±0.5 ±0.5 ±0.7 ±0.5 ±0.5 ±0.2 ±0.2 ±1.0 ±1.5 ±1.5 ±1.0 ±1.0 ±1 ±0.75 ±0.75 ±0.5 ±0.5 ±2.5 LSB2 LSB2 T T T T T T 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode — — — — ±0.5 ±0.5 ±0.3 ±0.3 ±1.0 ±1.0 ±0.5 ±0.5 T T Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 16. 12-bit SAR ADC Characteristics full operating range (VREFH = VDDAD, > 1.8, VREFL = VSSAD ≤ 8 MHz) (Continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Characterist ic Zero-Scale Error Conditions1 12-bit single-ended mode Symb EZS Min — Typ2 ±0.7 Max ±2.0 Unit LSB2 C T Comment VADIN = VSSAD 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Full-Scale Error 12-bit single-ended mode EFS — — — — — ±0.4 ±0.4 ±0.2 ±0.2 ±1.0 ±1.0 ±1.0 ±0.5 ±0.5 ±3.5 LSB2 T T T VADIN = VDDAD 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Quantization Error Input Leakage Error All modes all modes EQ EIL — — — — — ±0.4 ±0.4 ±0.2 ±0.2 — IIn * RAS ±1.5 ±1.5 ±0.5 ±0.5 ±0.5 LSB2 mV T T D D IIn = leakage current (refer to DC characteristi cs) Temp Sensor Slope m –40°C – 25°C 25°C – 125°C — — 1.646 1.769 701.2 — — — mV/× C C Temp Sensor Voltage 1 2 25°C VTEMP2 5 — mV C All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3 1 LSB = (V N REFH - VREFL)/2 28 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.10 # MCG and External Oscillator (XOSC) Characteristics Table 17. MCG (Temperature Range = –40 to 105°C Ambient) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 29 Rating Symbol tirefst Min — — 31.25 16 fdco_t 32 40 Δfdco_res_t — — — Δfdco_t — tfll_acquire tpll_acquire CJitter fvco fpll_ref Long term Entry6 fpll_jitter_625 ns Typical 55 31.25 — — — — ± 0.1 ± 0.2 ±1.0 ± 0.5 — — 0.02 — — 0.5664 — — — Max 100 — 39.0625 20 Unit μs C D C 1 Internal reference startup time factory trimmed at VDD=3.0 V and 2 Average internal reference frequency temp=25°C user trimmed 3 DCO output frequency range trimmed Low range (DRS=00) Mid range (DRS=01) High range1 (DRS=10) 4 quency at fixed voltage and temperature Resolution of trimmed DCO output fre- with FTRIM fint_ft kHz C C MHz C C C C p %fdco C 40 60 ± 0.2 ± 0.4 ±2 ±1 1 1 0.2 55.0 2.0 — ± 2.98 ± 5.97 tfll_acquire+ 1075(1/fint_t) tpll_acquire+ 1075(1/fpll_re f) without FTRIM %fdco over voltage and temperature Total deviation of trimmed DCO output 5 frequency over voltage and tempera- over fixed voltage ture and temp range of 0 - 70 °C 6 Acquisition time FLL2 PLL 3 — — — 7.0 1.0 — ± 1.49 ± 4.47 — C ms %fdco MHz MHz %fpll % D C D D D D D D s D 7 Long term Jitter of DCO output clock (averaged over 2mS interval) 4 8 VCO operating frequency 9 PLL reference frequency range of PLL 10 Jitter625ns 5output clock measured over 11 Lock frequency tolerance Dlock Dunl tfll_lock Exit7 FLL 12 Lock time PLL tpll_lock — (3/5) x fint_t (16/5) x fint_t — 13 14 1 2 Loss of external clock minimum frequency - RANGE = 0 floc_low floc_high — — — — kHz kHz D D Loss of external clock minimum frequency - RANGE = 1 This should not exceed the maximum CPU frequency for this device. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 3 7 Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock. Table 18. XOSC (Temperature Range = –40 to 105°C Ambient) # Characteristic Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) • Low range (RANGE = 0) flo • High range (RANGE = 1), • FEE or FBE mode 2 1 • High range (RANGE = 1), • High gain (HGO = 1), • FBELP mode • High range (RANGE = 1), • Low power (HGO = 0), • FBELP mode 2 Load capacitors Feedback resistor 3 High range (1 MHz to 16 MHz) Series resistor — Low range 4 High Gain (HGO = 1) Series resistor — High range • Low Gain (HGO = 0) • High Gain (HGO = 1) 5 ≥ 8 MHz 4 MHz 1 MHz RS — — — 0 0 0 0 10 20 kΩ Low Gain (HGO = 0) — RS — — — 1 0 100 — — — kΩ Low range (32 kHz to 38.4 kHz) fhi fhi 32 1 1 — — — 38.4 5 16 kHz MHz MHz Symbol Min Typ1 Max Unit fhi 1 — 8 MHz C1 C2 RF — See Note 3 — 10 MΩ 30 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 5 625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps CAN Bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. 6 Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in lock, then the MCG may stay in lock. Preliminary Electrical Characteristics Table 18. XOSC (Temperature Range = –40 to 105°C Ambient) # Crystal start-up time 4, 5 Characteristic Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) 6 High range, low gain (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) 1 2 Symbol t Min — Typ1 Max — Unit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 31 CSTL 200 — 400 5 15 — — — ms tCSTH — — Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 See crystal or resonator manufacturer’s recommendation. 4 This parameter is characterized and not tested on each device. 5 Proper PC board layout procedures must be followed to achieve specifications. o Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.11 AC Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages This section describes ac timing characteristics for each peripheral system. 2.11.1 # 1 Control Timing Table 19. Control Timing Symbol fBus Parameter Bus frequency (tcyc = 1/fBus) VDD ≥ 1.8 V VDD > 2.1 V VDD > 2.4 V dc dc dc 800 100 66 x tcyc 500 100 — — — 24 990 (TBD) — — — — 1500 — — — — 10 20 D D D D D D D D D 100 1.5 x tcyc 100 1.5 x tcyc — — D — — ns ns μs ns ns ns ns Min Typical1 Max C Unit MHz 2 3 4 5 6 tLPO textrst trstdrv tMSSU tMSH Internal low-power oscillator period External reset pulse width2 (tcyc = 1/fSelf_reset) Reset low drive Active background debug mode latch setup time Active background debug mode latch hold time IRQ pulse width • Asynchronous path2 • Synchronous path3 KBIPx pulse width • Asynchronous path2 • Synchronous path3 7 tILIH, tIHIL 8 tILIH, tIHIL 32 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics Table 19. Control Timing # 9 Symbol tRise, tFall Parameter Port rise and fall time (load = 50 pF)4, Low Drive Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 1 2 Min Typical1 Max C Unit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages ns — 11 — D — 35 — D — 40 — D — 75 — D Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40 °C to 105 °C. textrst RESET PIN Figure 7. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 8. IRQ/KBIPx Timing Freescale Semiconductor 33 Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.11.2 TPM Timing Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 20. TPM Input Timing # 1 2 3 4 5 C — — D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width tTPMext tclkh Symbol fTPMext tTPMext tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit MHz tcyc tcyc tcyc tcyc TPMxCLK tclkl Figure 9. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure 10. Timer Input Capture Pulse 34 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.12 SPI Characteristics Table 21. SPI Timing No.1 1 SPSCK period 2 Enable lead time 3 Enable lag time 4 Clock (SPSCK) high or low time 5 Data setup time (inputs) 6 Data hold time (inputs) 7 8 9 10 Data hold time (outputs) 11 Rise time 12 Fall time 13 Input Output tFI tFO — — tcyc – 25 25 ns ns D Input Output tRI tRO — — tcyc – 25 25 ns ns D Master Slave Slave access time3 Slave MISO disable time 4 Table 21 and Figure 11 through Figure 14 describe the timing requirements for the SPI system. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 35 Characteristic2 Operating frequency Master Slave Symbol fop Min fBus/2048 0 Max fBus/2 fBus/4 2048 — — — — — 1024 tcyc — — — — — 1 1 25 25 — — Unit Hz Hz tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc ns ns ns ns C D tSPSCK Master Slave tLead Master Slave tLag Master Slave tWSPSCK Master Slave Master Slave Master Slave tSU tSU tHI tHI ta tdis tv Master Slave tHO 0 0 D — — D tcyc – 30 tcyc – 30 15 15 0 25 — — D 2 4 1/2 1 1/2 1 D D D D D D D Data valid (after SPSCK edge) 2 Numbers in this column identify elements in Figure 11 through Figure 14. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 1 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 11 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 12 2 5 4 3 5 4 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 11. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 2 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 11 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 12 BIT 6 . . . 1 LSB OUT LSB IN 3 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 12. SPI Master Timing (CPHA = 1) 36 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Preliminary Electrical Characteristics SS (INPUT) 2 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) NOTE: 3 5 4 5 4 11 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 12 SLAVE LSB OUT SEE NOTE 9 1. Not defined, but normally MSB of character just received Figure 13. SPI Slave Timing (CPHA = 0) SS (INPUT) 2 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 11 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 12 BIT 6 . . . 1 SLAVE LSB OUT 9 3 NOTE: 1. Not defined, but normally LSB of character just received Figure 14. SPI Slave Timing (CPHA = 1) Freescale Semiconductor 37 Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Preliminary Electrical Characteristics 2.13 Flash Specifications Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory chapter in the Reference Manual for this device (MC9S08JE128RM). Table 22. Flash Characteristics # 1 2 3 4 5 6 7 8 9 10 1 2 Characteristic Supply voltage for program/erase -40°C to 105°C Supply voltage for read operation Internal FCLK frequency1 Internal FCLK period (1/FCLK) Byte program time (random location) Byte program time (burst mode) Page erase time2 Mass erase time 2 2 2 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass Min 1.8 1.8 150 5 Typical — — — — 9 4 4000 20,000 Max 3.6 3.6 200 6.67 Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc C D D D D P P P P C C Program/erase TL to TH = –40°C to + 105°C T = 25°C Data retention4 tD_ret endurance3 10,000 — 15 — 100,000 100 — — — cycles years The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 38 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.14 USB Electricals Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages 39 The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the standard or require additional information, this space would be used to communicate that information. Table 23. Internal USB 3.3 V Voltage Regulator Characteristics # 1 2 3 4 Characteristic Regulator operating voltage VREG output VUSB33 input with internal VREG disabled VREG Quiescent Current Symbol Vregin Vregout Vusb33in IVRQ Min 3.9 3 3 — Typ — 3.3 3.3 0.5 Max 5.5 3.6 3.6 — Unit V V V mA C C P C C Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Preliminary Electrical Characteristics 2.15 Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 VREF Electrical Specifications Table 24. VREF Electrical Specifications Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Characteristic Supply voltage Temperature Output Load Capacitance Maximum Load Voltage Reference Output with Factory Trim. VDD = 3 V. Temperature Drift (Vmin - Vmax across the full temperature range) Aging Coefficient Powered down Current (Off Mode, VREFEN=0, VRSTEN=0) Bandgap only (MODE_LV[1:0] = 00) Low-Power buffer (MODE_LV[1:0] = 01) Tight-Regulation buffer (MODE_LV[1:0] = 10) Load Regulation MODE_LV = 10 Line Regulation (Power Supply Rejection) Symbol VDDA TA CL — Vout Tdrift Ac I I I I — DC AC Min 1.80 –40 — — 1.140 — — — — — — — — TBD Max 3.6 105 100 10 1.160 10 (TBD) TBD 0.10 75 125 1.1 100 TBD — Unit V °C nf mA V mV1 ppm/year µA µA µA mA µV/mA mV dB C C D — P T C C T T T C C C See typical chart below. Table 25. VREF Limited Range Operating Requirements # 1 Characteristic Temperature Symbol TA Min 0 Max 50 Unit °C C C Notes Table 26. VREF Limited Range Operating Behaviors # 1 Characteristic Voltage Reference Output with Factory Trim Symbol Vout Min TBD Max TBD Unit µA C C Notes 40 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Ordering Information Figure 15. Typical Output vs. Temperature TBD Figure 16. Typical Output vs. VDD 3 Ordering Information This appendix contains ordering information for the device numbering system. MC9S08JE128 and MC9S08JE64 devices. Freescale Semiconductor 41 Non-Disclosure Agreement Required Preliminary — Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Ordering Information 3.1 Device Numbering System MC 9 S08 JE Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family 128 V XX Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages Example of the device numbering system: Package designator (see Table 28) Temperature range (V = –40°C to 105°C) (C = –40°C to 85°C) Approximate Flash size in Kbytes Table 27. Device Numbering System Device Number1 Flash 131,072 MC9S08JE128 MC9S08JE64 1 Memory RAM 12,288 12,288 12,288 12,288 Available Packages2 64 LQFP 80 LQFP 81 MAPBGA 64 LQFP 131,072 131,072 65,536 See Table 2 for a complete description of modules included on each device. 2 See Table 28 for package information. 3.2 Package Information Table 28. Package Descriptions Package Type Low Quad Flat Package Low Quad Flat Package MAPBGA Package Abbreviation LQFP LQFP Map PBGA Designator LH LK MB Case No. 840F-02 917-01 1662-01 Document No. Pin Count 64 80 81 98ASS23234W 98ASS23174W 98ASA10670D 3.3 Mechanical Drawings Table 28 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08JE128 series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table 28, or • Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table 28) in the “Enter Keyword” search box at the top of the page. 42 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary — Subject to Change Revision History 4 Revision History Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC9S08JE128 products in 81 MAPBGA packages To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev 0 1 2 Date 6/2009 7/2009 04/2010 Initial release of the Data Sheet. Description of Changes Updated MCG and XOSC Average internal reference frequency. Updated electrical characteristic data. Freescale Semiconductor 43 Non-Disclosure Agreement Required Preliminary — Subject to Change How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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