MC9S08LC36

MC9S08LC60 MC9S08LC36 Data Sheet: Technical Data HCS08 Microcontrollers MC9S08LC60 Rev. 4 07/2007 freescale.com MC9S08LC60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • 40-MHz HCS08 CPU HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) In-Circuit Emulator (ICE) debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. ICE debug module supports both tag and force breakpoints. Support for up to 32 interrupt/reset sources Peripherals • LCD (liquid crystal display driver) — Compatible with 5-V or 3-V LCD glass displays; functional in wait and stop3 low-power modes; selectable frontplane and backplane configurations: – – • 4 x 40 or 3 x 41 (80-pin package) 4 x 32 or 3 x 33 (64-pin package) • • • Memory Options • Dual on-chip in-circuit programmable FLASH memories with block protection and security options; 60K and 36K options available Program/erase of one FLASH array while executing from another On-chip random-access memory (RAM); 4K and 2.5K options available • • • • • • Power-Saving Features • • • Wait plus three stops Software disable of clock monitor and low-voltage interrupt (LVI) for lowest stop current Software-generated real-time clock (RTC) functions using real-time interrupt (RTI) • ACMP (analog comparator) — option to compare to internal reference voltage; output is software selectable to be driven to the input capture of TPM1 channel 0. ADC (analog-to-digital converter) — 8-channel, 12-bit with automatic compare function, asynchronous clock source, temperature sensor and internal bandgap reference channel. ADC is hardware triggerable using the RTI counter. SCI (serial communications interface) — available single-wire mode SPI1 and SPI2 — Two serial peripheral interface modules KBI — Two 8-pin keyboard interrupt modules with software selectable rising or falling edge detect IIC — Inter-integrated circuit bus module capable of operation up to 100 kbps with maximum bus loading; capable of higher baudrates with reduced loading TPM1 and TPM2 — Two timer/pulse-width modulators with selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels. Configurable Clock Source • Clock source options include crystal, resonator, external clock, or internally generated clock with precision nonvolatile memory (NVM) trimming Automatic clock monitor function Input/Output • Up to 24 general-purpose input/output (I/O) pins; includes two output-only pins and one input-only pin Software selectable pullups on ports when used as input. Selection is on an individual port bit basis. Software selectable slew rate control on ports when used as outputs (selection is on an individual port bit basis) Software selectable drive strength control on ports when used as outputs (selection is on an individual port bit basis) Internal pullup on RESET and IRQ pin to reduce customer system cost • • • System Protection • • • Optional computer operating properly (COP) reset Low-voltage detection with reset or interrupt Illegal opcode detection with reset • Package Options • • • 64-pin low-profile quad flat package (LQFP) 80-pin LQFP MC9S08LC60 Series Data Sheet Covers MC9S08LC60 MC9S08LC36 MC9S08LC60 Rev. 4 07/2007 This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007. All rights reserved. Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Number 1 2 3 4 Revision Date 02/2007 05/2007 06/2007 07/2007 Description of Changes Initial advance information release. Incorporated changes to the LCDSupply Field Descriptions for the CPCADJ field, added a Run Idd chart, performed some minor formatting edits and fixed a couple of typos. Updated the Appendix with ESD tables, package info, and mechanical drawings. Updated the Appendix with ESD tables, package info, and mechanical drawings for the 80-pin LQFP package. This product incorporates SuperFlash® technology licensed from SST. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007. All rights reserved. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 6 Freescale Semiconductor List of Chapters Chapter Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Appendix A Appendix B Title Page Device Overview .............................................................................. 21 Pins and Connections ..................................................................... 25 Modes of Operation ......................................................................... 33 Memory ............................................................................................. 39 Resets, Interrupts, and System Configuration ............................. 63 Parallel Input/Output ....................................................................... 81 Keyboard Interrupt (S08KBIV2) ...................................................... 95 Central Processor Unit (S08CPUV2) ............................................ 103 Liquid Crystal Display Driver (S08LCDV1) .................................. 123 Internal Clock Generator (S08ICGV4) .......................................... 169 Timer Pulse-Width Modulator (S08TPMV2) ................................. 197 Serial Communications Interface (S08SCIV3)............................. 213 Serial Peripheral Interface (S08SPIV3) ........................................ 233 Inter-Integrated Circuit (S08IICV1) ............................................... 249 Analog-to-Digital Converter (S08ADC12V1)................................ 267 Analog Comparator (S08ACMPV2) .............................................. 293 Development Support ................................................................... 301 Electrical Characteristics.............................................................. 323 Ordering Information and Mechanical Drawings........................ 351 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 7 Table of Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 1.4 Introduction .....................................................................................................................................21 Devices in the MC9S08LC60 Series ...............................................................................................21 MCU Block Diagram ......................................................................................................................22 System Clock Distribution ..............................................................................................................23 Chapter 2 Pins and Connections 2.1 2.2 2.3 Introduction .....................................................................................................................................25 Device Pin Assignment ...................................................................................................................25 Recommended System Connections ...............................................................................................27 2.3.1 Power (VDD, VSS, VDDAD, VSSAD) ...............................................................................29 2.3.2 ADC Reference Pins (VREFH, VREFL) ...........................................................................29 2.3.3 Oscillator (XTAL, EXTAL) ............................................................................................29 RESET Pin ......................................................................................................................30 2.3.4 2.3.5 Background / Mode Select (BKGD/MS) .......................................................................30 2.3.6 LCD Pins ........................................................................................................................31 2.3.6.1 LCD Power Pins .............................................................................................31 2.3.6.2 LCD Frontplane and Backplane Driver Pins ..................................................31 2.3.7 General-Purpose I/O and Peripheral Ports .....................................................................31 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................33 Features ...........................................................................................................................................33 Run Mode ........................................................................................................................................33 Active Background Mode ................................................................................................................33 Wait Mode .......................................................................................................................................34 Stop Modes ......................................................................................................................................35 3.6.1 Stop3 Mode ....................................................................................................................35 3.6.1.1 LVD Enabled in Stop Mode ............................................................................36 3.6.1.2 Active BDM Enabled in Stop Mode ...............................................................36 3.6.2 Stop2 Mode ....................................................................................................................36 3.6.3 Stop1 Mode ....................................................................................................................37 3.6.4 On-Chip Peripheral Modules in Stop Modes .................................................................37 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 9 Section Number Title Chapter 4 Memory Page 4.1 4.2 4.3 4.4 4.5 4.6 MC9S08LC60 Series Memory Map ...............................................................................................39 4.1.1 Reset and Interrupt Vector Assignments ........................................................................40 Register Addresses and Bit Assignments ........................................................................................42 RAM ................................................................................................................................................47 FLASH ............................................................................................................................................48 4.4.1 Features ...........................................................................................................................49 4.4.2 Program and Erase Times ...............................................................................................49 4.4.3 Program and Erase Command Execution .......................................................................50 4.4.4 Burst Program Execution ...............................................................................................51 4.4.5 Access Errors ..................................................................................................................53 4.4.6 FLASH Block Protection ...............................................................................................53 4.4.7 Vector Redirection ..........................................................................................................54 Security ............................................................................................................................................54 FLASH Registers and Control Bits .................................................................................................56 4.6.1 FLASH Clock Divider Register (FCDIV) ......................................................................56 4.6.2 FLASH Options Register (FOPT and NVOPT) .............................................................57 4.6.3 FLASH Configuration Register (FCNFG) .....................................................................58 4.6.4 FLASH Protection Register (FPROT and NVPROT) ....................................................58 4.6.5 FLASH Status Register (FSTAT) ...................................................................................60 4.6.6 FLASH Command Register (FCMD) ............................................................................61 Chapter 5 Resets, Interrupts, and System Configuration 5.1 5.2 5.3 5.4 5.5 Introduction .....................................................................................................................................63 Features ...........................................................................................................................................63 MCU Reset ......................................................................................................................................63 Computer Operating Properly (COP) Watchdog .............................................................................64 Interrupts .........................................................................................................................................65 5.5.1 Interrupt Stack Frame .....................................................................................................66 5.5.2 External Interrupt Request (IRQ) Pin .............................................................................67 5.5.2.1 Pin Configuration Options ..............................................................................67 5.5.2.2 Edge and Level Sensitivity ..............................................................................67 5.5.3 Interrupt Vectors, Sources, and Local Masks .................................................................67 Low-Voltage Detect (LVD) System ................................................................................................69 5.6.1 Power-On Reset Operation .............................................................................................69 5.6.2 LVD Reset Operation .....................................................................................................69 5.6.3 LVD Interrupt Operation ................................................................................................69 5.6.4 Low-Voltage Warning (LVW) ........................................................................................69 Real-Time Interrupt (RTI) ...............................................................................................................69 Reset, Interrupt, and System Control Registers and Control Bits ...................................................70 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) .........................................70 5.8.2 System Reset Status Register (SRS) ...............................................................................72 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 10 Freescale Semiconductor 5.6 5.7 5.8 Section Number 5.8.3 5.8.4 5.8.5 5.8.6 5.8.7 5.8.8 5.8.9 5.8.10 Title Page System Background Debug Force Reset Register (SBDFR) ..........................................73 System Options Register (SOPT1) .................................................................................73 System Options Register (SOPT2) .................................................................................74 System Device Identification Register (SDIDH, SDIDL) ..............................................75 System Real-Time Interrupt Status and Control Register (SRTISC) .............................76 System Power Management Status and Control 1 Register (SPMSC1) .........................77 System Power Management Status and Control 2 Register (SPMSC2) .........................78 System Power Management Status and Control 3 Register (SPMSC3) .........................79 Chapter 6 Parallel Input/Output 6.1 6.2 Pin Behavior in Stop Modes ............................................................................................................83 Parallel I/O Registers .......................................................................................................................83 6.2.1 Port A Registers ..............................................................................................................83 6.2.1.1 Port A Data Registers (PTAD) ........................................................................84 6.2.1.2 Port A Data Direction Registers (PTADD) .....................................................84 6.2.2 Port A Control Registers ................................................................................................85 6.2.2.1 Internal Pullup Enable (PTAPE) .....................................................................85 6.2.2.2 Output Slew Rate Control Enable (PTASE) ...................................................86 6.2.2.3 Output Drive Strength Select (PTADS) ..........................................................86 6.2.3 Port B Registers ..............................................................................................................87 6.2.3.1 Port B Data Registers (PTBD) ........................................................................87 6.2.3.2 Port B Data Direction Registers (PTBDD) .....................................................88 6.2.4 Port B Control Registers .................................................................................................88 6.2.4.1 Internal Pullup Enable (PTBPE) .....................................................................88 6.2.4.2 Output Slew Rate Control Enable (PTBSE) ...................................................89 6.2.4.3 Output Drive Strength Select (PTBDS) ..........................................................90 6.2.5 Port C Registers ..............................................................................................................90 6.2.5.1 Port C Data Registers (PTCD) ........................................................................91 6.2.5.2 Port C Data Direction Registers (PTCDD) .....................................................91 6.2.6 Port C Control Registers .................................................................................................91 6.2.6.1 Internal Pullup Enable (PTCPE) .....................................................................92 6.2.6.2 Output Slew Rate Control Enable (PTCSE) ...................................................93 6.2.6.3 Output Drive Strength Select (PTCDS) ..........................................................93 Chapter 7 Keyboard Interrupt (S08KBIV2) 7.1 Introduction .....................................................................................................................................95 7.1.1 Features ...........................................................................................................................97 7.1.2 Modes of Operation ........................................................................................................97 7.1.2.1 KBI in Wait Mode ...........................................................................................97 7.1.2.2 KBI in Stop Modes .........................................................................................97 7.1.2.3 KBI in Active Background Mode ...................................................................97 7.1.3 Block Diagram ................................................................................................................97 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 11 Section Number 7.2 7.3 Title Page 7.4 External Signal Description ............................................................................................................98 Register Definition ..........................................................................................................................99 7.3.1 KBIx Status and Control Register (KBIxSC) .................................................................99 7.3.2 KBIx Pin Enable Register (KBIxPE) .............................................................................99 7.3.3 KBIx Edge Select Register (KBIxES) ..........................................................................100 Functional Description ..................................................................................................................100 7.4.1 Edge Only Sensitivity ...................................................................................................101 7.4.2 Edge and Level Sensitivity ...........................................................................................101 7.4.3 KBI Pullup/Pulldown Resistors ....................................................................................101 7.4.4 KBI Initialization ..........................................................................................................101 Chapter 8 Central Processor Unit (S08CPUV2) 8.1 8.2 Introduction ...................................................................................................................................103 8.1.1 Features .........................................................................................................................103 Programmer’s Model and CPU Registers .....................................................................................104 8.2.1 Accumulator (A) ...........................................................................................................104 8.2.2 Index Register (H:X) ....................................................................................................104 8.2.3 Stack Pointer (SP) .........................................................................................................105 8.2.4 Program Counter (PC) ..................................................................................................105 8.2.5 Condition Code Register (CCR) ...................................................................................105 Addressing Modes .........................................................................................................................107 8.3.1 Inherent Addressing Mode (INH) ................................................................................107 8.3.2 Relative Addressing Mode (REL) ................................................................................107 8.3.3 Immediate Addressing Mode (IMM) ...........................................................................107 8.3.4 Direct Addressing Mode (DIR) ....................................................................................107 8.3.5 Extended Addressing Mode (EXT) ..............................................................................108 8.3.6 Indexed Addressing Mode ............................................................................................108 8.3.6.1 Indexed, No Offset (IX) ................................................................................108 8.3.6.2 Indexed, No Offset with Post Increment (IX+) .............................................108 8.3.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................108 8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................108 8.3.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................108 8.3.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................108 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................109 Special Operations .........................................................................................................................109 8.4.1 Reset Sequence .............................................................................................................109 8.4.2 Interrupt Sequence ........................................................................................................109 8.4.3 Wait Mode Operation ...................................................................................................110 8.4.4 Stop Mode Operation ...................................................................................................110 8.4.5 BGND Instruction ........................................................................................................111 HCS08 Instruction Set Summary ..................................................................................................112 8.3 8.4 8.5 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 12 Freescale Semiconductor Section Number Title Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Page 9.1 9.2 9.3 9.4 9.5 Introduction ...................................................................................................................................123 9.1.1 Features .........................................................................................................................125 9.1.2 Modes of Operation ......................................................................................................125 9.1.3 Block Diagram ..............................................................................................................126 External Signal Description ..........................................................................................................127 9.2.1 BP[2:0] .........................................................................................................................127 9.2.2 FP[39:0] ........................................................................................................................127 9.2.3 BP3/FP40 ......................................................................................................................127 9.2.4 VLCD .............................................................................................................................127 9.2.5 VLL1, VLL2, VLL3 ........................................................................................................127 9.2.6 Vcap1, Vcap2 ...............................................................................................................128 Register Definition ........................................................................................................................128 9.3.1 LCD Control Register 0 (LCDCR0) .............................................................................128 9.3.2 LCD Control Register 1 (LCDCR1) .............................................................................129 9.3.3 LCD Frontplane Enable Registers 0–5 (FPENR0–FPENR5) ......................................130 9.3.4 LCDRAM Registers (LCDRAM) ................................................................................131 9.3.4.1 LCDRAM Registers as On/Off Selector (LCDDRMS = 0) .........................133 9.3.4.2 LCDRAM Registers as Blink Enable/Disable (LCDDRMS = 1) .................133 9.3.5 LCD Clock Source Register (LCDCLKS) ...................................................................133 9.3.6 LCD Voltage Supply Register (LCDSUPPLY) ............................................................134 9.3.7 LCD Blink Control Register (LCDBCTL) ...................................................................135 9.3.8 LCD Command and Status Register (LCDCMD) ........................................................136 Functional Description ..................................................................................................................137 9.4.1 LCD Driver Description ...............................................................................................138 9.4.1.1 LCD Duty Cycle ...........................................................................................138 9.4.1.2 LCD Bias ......................................................................................................139 9.4.1.3 LCD Module Waveform Base Clock and Frame Frequency ........................139 9.4.1.4 LCD Waveform Examples ............................................................................141 9.4.2 LCDRAM Registers .....................................................................................................149 9.4.2.1 LCDRAM Data Clear Command ..................................................................149 9.4.2.2 LCDRAM Data Blank Command .................................................................149 9.4.3 LCD Blinking ...............................................................................................................149 9.4.3.1 LCD Segment Blinking .................................................................................150 9.4.3.2 Blink Frequency ............................................................................................150 9.4.4 LCD Charge Pump, Voltage Divider, and Power Supply Operation ............................150 9.4.4.1 LCD Charge Pump and Voltage Divider .......................................................152 9.4.4.2 LCD Power Supply and Voltage Buffer Configuration .................................153 9.4.5 Resets ............................................................................................................................155 9.4.6 Interrupts .......................................................................................................................155 Initialization Section .....................................................................................................................155 9.5.1 Initialization Sequence .................................................................................................156 9.5.2 Initialization Examples .................................................................................................157 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 13 Section Number Title Page 9.6 9.5.2.1 Initialization Example 1 ................................................................................158 9.5.2.2 Initialization Example 2 ................................................................................159 9.5.2.3 Initialization Example 3 ................................................................................161 9.5.2.4 Initialization Example 4 ................................................................................162 Application Information ................................................................................................................163 9.6.1 LCD Seven Segment Example Description ..................................................................163 9.6.1.1 LCD Module Waveforms ..............................................................................165 9.6.1.2 Segment On Driving Waveform ....................................................................166 9.6.1.3 Segment Off Driving Waveform ...................................................................166 9.6.2 LCD Contrast Control ..................................................................................................166 9.6.3 LCD Power Consumption ............................................................................................167 Chapter 10 Internal Clock Generator (S08ICGV4) 10.1 Introduction ...................................................................................................................................169 10.2 Introduction ...................................................................................................................................171 10.2.1 Features .........................................................................................................................171 10.2.2 Modes of Operation ......................................................................................................172 10.2.3 Block Diagram ..............................................................................................................173 10.3 External Signal Description ..........................................................................................................173 10.3.1 EXTAL — External Reference Clock / Oscillator Input ..............................................173 10.3.2 XTAL — Oscillator Output ..........................................................................................173 10.3.3 External Clock Connections .........................................................................................174 10.3.4 External Crystal/Resonator Connections ......................................................................174 10.4 Register Definition ........................................................................................................................175 10.4.1 ICG Control Register 1 (ICGC1) .................................................................................175 10.4.2 ICG Control Register 2 (ICGC2) .................................................................................177 10.4.3 ICG Status Register 1 (ICGS1) ....................................................................................178 10.4.4 ICG Status Register 2 (ICGS2) ....................................................................................179 10.4.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ...............................................................179 10.4.6 ICG Trim Register (ICGTRM) .....................................................................................180 10.5 Functional Description ..................................................................................................................180 10.5.1 Off Mode (Off) .............................................................................................................181 10.5.1.1 BDM Active ..................................................................................................181 10.5.1.2 OSCSTEN Bit Set .........................................................................................181 10.5.1.3 Stop/Off Mode Recovery ..............................................................................181 10.5.2 Self-Clocked Mode (SCM) ...........................................................................................181 10.5.3 FLL Engaged, Internal Clock (FEI) Mode ...................................................................182 10.5.4 FLL Engaged Internal Unlocked ..................................................................................183 10.5.5 FLL Engaged Internal Locked ......................................................................................183 10.5.6 FLL Bypassed, External Clock (FBE) Mode ...............................................................183 10.5.7 FLL Engaged, External Clock (FEE) Mode .................................................................183 10.5.7.1 FLL Engaged External Unlocked .................................................................184 10.5.7.2 FLL Engaged External Locked .....................................................................184 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 14 Freescale Semiconductor Section Number Title Page 10.5.8 FLL Lock and Loss-of-Lock Detection ........................................................................184 10.5.9 FLL Loss-of-Clock Detection ......................................................................................185 10.5.10 Clock Mode Requirements ...........................................................................................186 10.5.11 Fixed Frequency Clock .................................................................................................187 10.5.12 High Gain Oscillator .....................................................................................................187 10.6 Initialization/Application Information ..........................................................................................187 10.6.1 Introduction ..................................................................................................................187 10.6.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ........................189 10.6.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ............................191 10.6.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ....................193 10.6.5 Example #4: Internal Clock Generator Trim ................................................................195 Chapter 11 Timer Pulse-Width Modulator (S08TPMV2) 11.1 Introduction ...................................................................................................................................197 11.1.1 Features .........................................................................................................................199 11.1.2 Block Diagram ..............................................................................................................199 11.2 External Signal Description ..........................................................................................................201 11.2.1 External TPM Clock Sources .......................................................................................201 11.2.2 TPMxCHn — TPMx Channel n I/O Pins .....................................................................201 11.3 Register Definition ........................................................................................................................201 11.3.1 Timer x Status and Control Register (TPMxSC) ..........................................................202 11.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) .............................................203 11.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) .............................204 11.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) ....................................205 11.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ....................................206 11.4 Functional Description ..................................................................................................................207 11.4.1 Counter .........................................................................................................................207 11.4.2 Channel Mode Selection ...............................................................................................208 11.4.2.1 Input Capture Mode ......................................................................................208 11.4.2.2 Output Compare Mode .................................................................................209 11.4.2.3 Edge-Aligned PWM Mode ...........................................................................209 11.4.3 Center-Aligned PWM Mode ........................................................................................210 11.5 TPM Interrupts ..............................................................................................................................211 11.5.1 Clearing Timer Interrupt Flags .....................................................................................211 11.5.2 Timer Overflow Interrupt Description ..........................................................................211 11.5.3 Channel Event Interrupt Description ............................................................................212 11.5.4 PWM End-of-Duty-Cycle Events .................................................................................212 Chapter 12 Serial Communications Interface (S08SCIV3) 12.1 Introduction ...................................................................................................................................213 12.1.1 Features .........................................................................................................................216 12.1.2 Modes of Operation ......................................................................................................216 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 15 Section Number Title Page 12.1.3 Block Diagram ..............................................................................................................217 12.2 Register Definition ........................................................................................................................219 12.2.1 SCI Baud Rate Registers (SCIBDH, SCIBHL) ............................................................219 12.2.2 SCI Control Register 1 (SCIC1) ...................................................................................220 12.2.3 SCI Control Register 2 (SCIC2) ...................................................................................221 12.2.4 SCI Status Register 1 (SCIS1) ......................................................................................222 12.2.5 SCI Status Register 2 (SCIS2) ......................................................................................224 12.2.6 SCI Control Register 3 (SCIC3) ...................................................................................224 12.2.7 SCI Data Register (SCID) ............................................................................................225 12.3 Functional Description ..................................................................................................................226 12.3.1 Baud Rate Generation ...................................................................................................226 12.3.2 Transmitter Functional Description ..............................................................................226 12.3.2.1 Send Break and Queued Idle .........................................................................227 12.3.3 Receiver Functional Description ..................................................................................228 12.3.3.1 Data Sampling Technique .............................................................................228 12.3.3.2 Receiver Wakeup Operation .........................................................................229 12.3.4 Interrupts and Status Flags ...........................................................................................229 12.4 Additional SCI Functions ..............................................................................................................230 12.4.1 8- and 9-Bit Data Modes ..............................................................................................230 12.4.2 Stop Mode Operation ...................................................................................................231 12.4.3 Loop Mode ...................................................................................................................231 12.4.4 Single-Wire Operation ..................................................................................................231 Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction ...................................................................................................................................233 13.1.1 Features .........................................................................................................................235 13.1.2 Block Diagrams ............................................................................................................235 13.1.2.1 SPI System Block Diagram ..........................................................................235 13.1.2.2 SPI Module Block Diagram ..........................................................................236 13.1.3 SPI Baud Rate Generation ............................................................................................237 13.2 External Signal Description ..........................................................................................................238 13.2.1 SPSCK — SPI Serial Clock .........................................................................................238 13.2.2 MOSI — Master Data Out, Slave Data In ....................................................................238 13.2.3 MISO — Master Data In, Slave Data Out ....................................................................238 13.2.4 SS — Slave Select ........................................................................................................238 13.3 Modes of Operation .......................................................................................................................239 13.3.1 SPI in Stop Modes ........................................................................................................239 13.4 Register Definition ........................................................................................................................239 13.4.1 SPI Control Register 1 (SPIxC1) ..................................................................................239 13.4.2 SPI Control Register 2 (SPIxC2) ..................................................................................240 13.4.3 SPI Baud Rate Register (SPIxBR) ...............................................................................241 13.4.4 SPI Status Register (SPIxS) ..........................................................................................242 13.4.5 SPI Data Register (SPIxD) ...........................................................................................243 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 16 Freescale Semiconductor Section Number Title Page 13.5 Functional Description ..................................................................................................................244 13.5.1 SPI Clock Formats ........................................................................................................244 13.5.2 SPI Interrupts ................................................................................................................247 13.5.3 Mode Fault Detection ...................................................................................................247 Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.1 Introduction ...................................................................................................................................249 14.1.1 Features .........................................................................................................................251 14.1.2 Modes of Operation ......................................................................................................251 14.1.3 Block Diagram ..............................................................................................................252 14.2 External Signal Description ..........................................................................................................252 14.2.1 SCL — Serial Clock Line .............................................................................................252 14.2.2 SDA — Serial Data Line ..............................................................................................252 14.3 Register Definition ........................................................................................................................252 14.3.1 IIC Address Register (IICA) .........................................................................................253 14.3.2 IIC Frequency Divider Register (IICF) ........................................................................253 14.3.3 IIC Control Register (IICC) ..........................................................................................256 14.3.4 IIC Status Register (IICS) ............................................................................................257 14.3.5 IIC Data I/O Register (IICD) ........................................................................................258 14.4 Functional Description ..................................................................................................................259 14.4.1 IIC Protocol ..................................................................................................................259 14.4.1.1 START Signal ...............................................................................................260 14.4.1.2 Slave Address Transmission .........................................................................260 14.4.1.3 Data Transfer .................................................................................................260 14.4.1.4 STOP Signal ..................................................................................................261 14.4.1.5 Repeated START Signal ...............................................................................261 14.4.1.6 Arbitration Procedure ....................................................................................261 14.4.1.7 Clock Synchronization ..................................................................................261 14.4.1.8 Handshaking .................................................................................................262 14.4.1.9 Clock Stretching ............................................................................................262 14.5 Resets ............................................................................................................................................262 14.6 Interrupts .......................................................................................................................................262 14.6.1 Byte Transfer Interrupt .................................................................................................263 14.6.2 Address Detect Interrupt ...............................................................................................263 14.6.3 Arbitration Lost Interrupt .............................................................................................263 14.7 Initialization/Application Information ..........................................................................................264 Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.1 Introduction ...................................................................................................................................267 15.1.1 ADC Configuration Information ..................................................................................267 15.1.1.1 Channel Assignments ....................................................................................267 15.1.1.2 Alternate Clock .............................................................................................268 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 17 Section Number Title Page 15.2 15.3 15.4 15.5 15.6 15.1.1.3 Hardware Trigger ..........................................................................................268 15.1.1.4 Analog Pin Enables .......................................................................................268 15.1.1.5 Temperature Sensor ......................................................................................268 15.1.1.6 Low-Power Mode Operation ........................................................................269 15.1.2 Features .........................................................................................................................270 15.1.3 Block Diagram ..............................................................................................................270 External Signal Description ..........................................................................................................271 15.2.1 Analog Power (VDDAD) ................................................................................................272 15.2.2 Analog Ground (VSSAD) ..............................................................................................272 15.2.3 Voltage Reference High (VREFH) .................................................................................272 15.2.4 Voltage Reference Low (VREFL) ..................................................................................272 15.2.5 Analog Channel Inputs (ADx) ......................................................................................272 Register Definition ........................................................................................................................272 15.3.1 Status and Control Register 1 (ADCSC1) ....................................................................272 15.3.2 Status and Control Register 2 (ADCSC2) ....................................................................274 15.3.3 Data Result High Register (ADCRH) ..........................................................................275 15.3.4 Data Result Low Register (ADCRL) ............................................................................275 15.3.5 Compare Value High Register (ADCCVH) ..................................................................276 15.3.6 Compare Value Low Register (ADCCVL) ...................................................................276 15.3.7 Configuration Register (ADCCFG) ..............................................................................276 15.3.8 Pin Control 1 Register (APCTL1) ................................................................................278 15.3.9 Pin Control 2 Register (APCTL2) ................................................................................279 15.3.10 Pin Control 3 Register (APCTL3) ................................................................................280 Functional Description ..................................................................................................................281 15.4.1 Clock Select and Divide Control ..................................................................................281 15.4.2 Input Select and Pin Control .........................................................................................282 15.4.3 Hardware Trigger ..........................................................................................................282 15.4.4 Conversion Control .......................................................................................................282 15.4.4.1 Initiating Conversions ...................................................................................282 15.4.4.2 Completing Conversions ...............................................................................283 15.4.4.3 Aborting Conversions ...................................................................................283 15.4.4.4 Power Control ...............................................................................................283 15.4.4.5 Sample Time and Total Conversion Time .....................................................283 15.4.5 Automatic Compare Function ......................................................................................285 15.4.6 MCU Wait Mode Operation .........................................................................................285 15.4.7 MCU Stop3 Mode Operation .......................................................................................285 15.4.7.1 Stop3 Mode With ADACK Disabled ............................................................285 15.4.7.2 Stop3 Mode With ADACK Enabled .............................................................286 15.4.8 MCU Stop1 and Stop2 Mode Operation ......................................................................286 Initialization Information ..............................................................................................................286 15.5.1 ADC Module Initialization Example ...........................................................................286 15.5.1.1 Initialization Sequence ..................................................................................286 15.5.1.2 Pseudo — Code Example .............................................................................287 Application Information ................................................................................................................288 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 18 Freescale Semiconductor Section Number 15.6.1 Title Page 15.6.2 External Pins and Routing ............................................................................................288 15.6.1.1 Analog Supply Pins ......................................................................................288 15.6.1.2 Analog Reference Pins ..................................................................................289 15.6.1.3 Analog Input Pins .........................................................................................289 Sources of Error ............................................................................................................290 15.6.2.1 Sampling Error ..............................................................................................290 15.6.2.2 Pin Leakage Error .........................................................................................290 15.6.2.3 Noise-Induced Errors ....................................................................................290 15.6.2.4 Code Width and Quantization Error .............................................................291 15.6.2.5 Linearity Errors .............................................................................................291 15.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes ......................................292 Chapter 16 Analog Comparator (S08ACMPV2) 16.1 Introduction ...................................................................................................................................293 16.1.1 ACMP/TPM1 Configuration Information ....................................................................293 16.1.2 AMCPO Availability ....................................................................................................293 16.1.3 Features .........................................................................................................................295 16.1.4 Modes of Operation ......................................................................................................295 16.1.4.1 ACMP in Wait Mode ....................................................................................295 16.1.4.2 ACMP in Stop Modes ...................................................................................295 16.1.4.3 ACMP in Active Background Mode .............................................................295 16.1.5 Block Diagram ..............................................................................................................295 16.2 External Signal Description ..........................................................................................................297 16.3 Register Definition ........................................................................................................................297 16.3.1 ACMP Status and Control Register (ACMPSC) ..........................................................298 16.4 Functional Description ..................................................................................................................299 Chapter 17 Development Support 17.1 Introduction ...................................................................................................................................301 17.1.1 Features .........................................................................................................................301 17.2 Background Debug Controller (BDC) ..........................................................................................302 17.2.1 BKGD Pin Description .................................................................................................302 17.2.2 Communication Details ................................................................................................303 17.2.3 BDC Commands ...........................................................................................................307 17.2.4 BDC Hardware Breakpoint ..........................................................................................309 17.3 On-Chip Debug System (DBG) ....................................................................................................310 17.3.1 Comparators A and B ...................................................................................................310 17.3.2 Bus Capture Information and FIFO Operation .............................................................310 17.3.3 Change-of-Flow Information ........................................................................................311 17.3.4 Tag vs. Force Breakpoints and Triggers .......................................................................311 17.3.5 Trigger Modes ..............................................................................................................312 17.3.6 Hardware Breakpoints ..................................................................................................314 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 19 Section Number Title Page 17.4 Register Definition ........................................................................................................................314 17.4.1 BDC Registers and Control Bits ...................................................................................314 17.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................315 17.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................316 17.4.2 System Background Debug Force Reset Register (SBDFR) ........................................316 17.4.3 DBG Registers and Control Bits ..................................................................................317 17.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................317 17.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................317 17.4.3.3 Debug Comparator B High Register (DBGCBH) .........................................317 17.4.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................317 17.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................318 17.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................318 17.4.3.7 Debug Control Register (DBGC) ..................................................................319 17.4.3.8 Debug Trigger Register (DBGT) ..................................................................320 17.4.3.9 Debug Status Register (DBGS) .....................................................................321 Appendix A Electrical Characteristics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 Introduction ...................................................................................................................................323 Absolute Maximum Ratings ..........................................................................................................323 Thermal Characteristics .................................................................................................................324 Electrostatic Discharge (ESD) Protection Characteristics ............................................................325 DC Characteristics .........................................................................................................................326 Supply Current Characteristics ......................................................................................................330 ADC Characteristics ......................................................................................................................333 LCD Characteristics ......................................................................................................................336 Internal Clock Generation Module Characteristics .......................................................................339 A.9.1 ICG Frequency Specifications ........................................................................................339 A.10 AC Characteristics .........................................................................................................................341 A.10.1 Control Timing ...............................................................................................................342 A.10.2 Timer/PWM (TPM) Module Timing ..............................................................................343 A.10.3 SPI Timing ......................................................................................................................344 A.11 FLASH Specifications ...................................................................................................................347 A.12 EMC Performance .........................................................................................................................348 A.12.1 Radiated Emissions .........................................................................................................348 A.12.2 Conducted Transient Susceptibility ................................................................................349 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................351 B.2 Mechanical Drawings ....................................................................................................................351 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 20 Freescale Semiconductor Chapter 1 Device Overview 1.1 Introduction MC9S08LC60 Series MCUs are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 Devices in the MC9S08LC60 Series Table 1-1 lists the devices available in the MC9S08LC60 Series and summarizes the differences among them. Table 1-1. Devices in the MC9S08LC60 Series Device MC9S08LC60 MC9S08LC36 FLASH A 32K 24K FLASH B 28K 12K RAM 4K 2.5K Package 80 LQFP 64 LQFP Table 1-2. Package Options by Feature Package Feature 80-Pin ACMP ADC IIC IRQ KBI1 KBI2 SCI SPI1 SPI2 TPM1 TPM2 Shared I/O pins (max) LCD yes 8-ch yes yes 8 8 yes yes yes 2-ch 2-ch 24 - I/O 2 - Output only 1- Input only 4x40 3x41 64-Pin yes 2-ch yes yes 2 8 yes yes yes 2-ch 2-ch 18 - I/O 2 - Output only 1- Input only 4x32 3x33 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 21 Chapter 1 Device Overview 1.3 MCU Block Diagram HCS08 CORE CPU INT 4 BKGD BKP 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) ADP[7:4] ADP3 ADP2 ADP1 ADP0 PTA[7:4]/KBI1P[7:4]/ADP[7:4] ON-CHIP ICE DEBUG MODULE (DBG) Figure 1-1 shows the structure of the MC9S08LC60 Series MCUs. HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT ANALOG COMPARATOR (ACMP) ACMP– ACMP+ PORT A PTA3/KBI1P3/ADP3/ACMP– PTA2/KBI1P2/ADP2/ACMP+ RTI IRQ COP LVD 8-BIT KEYBOARD INTERRUPT (KBI1) 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] IIC MODULE (IIC) USER FLASH B (LC60 = 28,464 BYTES) (LC36 = 12,288 BYTES) SDA RESET 5 PORT B USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) SS1 SPSCK1 MISO1 MOSI1 SCL PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 PTB5/MOSI1/SCL PTB4/MISO1/SDA PTB3/KBI2P2 PTB2/RESET 8-BIT KEYBOARD INTERRUPT (KBI2) 3 XTAL EXTAL IRQ PTB1/KBI2P1/XTAL PTB0/KBI2P0/EXTAL PTC7/KBI2P7/IRQ/TPMCLK PTC6/BKGD/MS PTC5/KBI2P6/TPM2CH1 PTC4/KBI2P5/TPM2CH0 PORT C USER RAM (LC60 = 4096 BYTES) (LC36 = 2560 BYTES) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VLCD VLL1 VLL2 VLL3 VCAP1 VCAP2 BP[2:0] BP3/FP40 FP[39:0] VDD VSS VOLTAGE REGULATOR LIQUID CRYSTAL DISPLAY DRIVER LCD 2-CHANNEL TIMER/PWM (TPM2) 2-CHANNEL TIMER/PWM (TPM1) TPM2CH1 TPM2CH0 TPMCLK TPM1CH0 TPM1CH1 SS2 SPSCK2 MOSI2 MISO2 TxD PTC3/SS2/TPM1CH1 PTC2/SPSCK2/TPM1CH0 SERIAL PERIPHERAL INTERFACE (SPI2) SERIAL COMMUNICATIONS INTERFACE (SCI) PTC1/MOSI2/TxD PTC0/MISO2/RxD RxD VREFH VREFL VDDAD VSSAD NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1). 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. Input-only RESET is shared with output-only PTB2. Default function after reset is RESET. 6. IRQ is shared with PTC7/KBI2P7/TPMCLK. Default function after reset is output-only PTC7. 7. PTC6/BKGD/MS is an output only pin 8. FP[39:32], PTA[1:0], and PTA[7:4] are not available in the 64 LQFP. 9. ACMPO is not available. Figure 1-1. MC9S08LC60 Series Block Diagram MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 22 Freescale Semiconductor Chapter 1 Device Overview Table 1-3 lists the functional versions of the on-chip modules. Table 1-3. Module Versions Module Analog Comparator (ACMP) Analog-to-Digital Converter (ADC) Internal Clock Generator (ICG) Inter-Integrated Circuit (IIC) Keyboard Interrupt (KBI) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Timer Pulse-Width Modulator (TPM) Liquid Crystal Display Module (LCD) Central Processing Unit (CPU) Version 2 1 4 1 2 3 3 2 1 2 1.4 1-kHz System Clock Distribution TPMCLK SYSTEM CONTROL LOGIC ICGERCLK FFE RTI TPM1 TPM2 IIC SCI SPI1 SPI2 ACMP ÷2 ICG FIXED FREQ CLOCK (XCLK) ICGOUT ICGLCLK* ÷2 BUSCLK CPU BDC LCD COP ADC RAM FLASH FLASH has frequency requirements for program and erase operation. See the Electricals Appendix. * ICGLCLK is the alternate BDC clock source for the MC9S08LC60 Series. ADC has min and max frequency requirements. See Chapter 1, “Introduction” and the Electricals Appendix. Figure 1-2. System Clock Distribution Diagram Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 23 Chapter 1 Device Overview Control bits inside the ICG determine which source is connected. • FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK. Otherwise the fixed-frequency clock will be BUSCLK. • ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 24 Freescale Semiconductor Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment Figure 2-1 and Figure 2-2 show the pin assignments for the MC9S08LC60 Series devices in its available packages. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 25 Chapter 2 Pins and Connections FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1 BP2 BP3/FP40 Vcap1 Vcap2 VLL1 VLL2 VLL3 VLCD PTA0/KBI1P0/ADP0 PTA1/KBI1P1/ADP1 PTA2/KBI1P2/ADP2/ACMP + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MC9S08LC60 Series 80-Pin LQFP FP27 FP28 FP29 FP30 FP31 FP32 FP33 FP34 FP35 FP36 FP37 FP38 FP39 PTC7/KBI2P7/IRQ/TPMCLK PTC6/ BKGD/MS PTC5/KBI2P6/TPM2CH1 PTC4/KBI2P5/TPM2CH0 PTC3/SS2/TPM1CH1 PTC2/SPSCK2/TPM1CH0 PTC1/MOSI2/TxD Figure 2-1. MC9S08LC60 Series in 80-Pin LQFP Package MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 26 Freescale Semiconductor PTA3/KBI1P3/ADP3/ACMP– PTA4/KBI1P4/ADP4 PTA5/KBI1P5/ADP5 PTA6/KBI1P6/ADP6 PTA7/KBI1P7/ADP7 VSSAD VREFL VREFH VDDAD PTB0/KBI2P0/EXTAL PTB1/KBI2P1/XTAL VDD VSS PTB2/RESET PTB3/KBI2P2 PTB4/MISO1/SDA PTB5/MOSI1/SCL PTB6/KBI2P3/SPSCK1 PTB7/KBI2P4/SS1 PTC0/MISO2/RxD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Chapter 2 Pins and Connections 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1 BP2 BP3/FP40 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MC9S08LC60 Series 64-Pin LQFP FP22 FP23 FP24 FP25 FP26 FP27 FP28 FP29 FP30 FP31 PTC7/KBI2P7/IRQ/TPMCLK PTC6 /BKGD/MS PTC5/KBI2P6/TPM2CH1 PTC4/KBI2P5/TPM2CH0 PTC3/SS2/TPM1CH1 PTC2/SPSCK2/TPM1CH0 Note: VREFH/VREFL are internally connected to VDDAD/VSSAD in the 64-pin package. Figure 2-2. MC9S08LC60 Series in 64-Pin LQFP Package 2.3 Recommended System Connections Figure 2-3 shows pin connections that are common to most MC9S08LC60 Series application systems in the 80-pin package. Connections will be similar to the 64-pin package except for the number of I/O pins available. A more detailed discussion of system connections follows. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 27 PTA2/KBI1P2/ADP2/ACMP+ PTA3/KBI1P3/ADP3/ACMP– VSSAD/VREFL VDDAD/VREFH PTB0/KBI2P0/EXTAL PTB1/KBI2P1/XTAL VDD VSS PTB2/RESET PTB3/KBI2P2 PTB4/MISO1/SDA PTB5/MOSI1/SCL PTB6/KBI2P3/SPSCK1 PTB7/KBI2P4/SS1 PTC0/MISO2/RxD PTC1/MOSI2/TxD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Chapter 2 Pins and Connections VREFH CBYAD 0.1 μF SYSTEM POWER + 3V VDD VDDAD MC9S08LC60 PTA[7:4]/KBI1P[7:4]/ADP[7:4] PTA3/KBI1P3/ADP3/ACMP– PTA2/KBI1P2/ADP2/ACMP+ PTA[1:0]/KBI1P[1:0]/ADP[1:0] PORT A VSSAD VREFL VDD PORT B CBY 0.1 μF VSS PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 PTB5/MOSI1/SCL PTB4/MISO1/SDA PTB3/KBI2P2 PTB2/RESET PTB1/KBI2P1/XTAL PTB0/KBI2P0/EXTAL INTERFACE TO I/O AND PTC7/KBI2P7/IRQ/TPMCLK PTC6/BKGD/MS PTC5/KBI2P6/TPM2CH1 PTC4/KBI2P5/TPM2CH0 PTC3/SS2/TPM1CH1 PTC2/SPSCK2/TPM1CH0 PTC1/MOSI2/TxD PTC0/MISO2/RxD PERIPHERAL APPLICATION SYSTEM CBLK + 10 μF NOTE 1 RF C1 C2 RS PTB1/KBI2P1/XTAL X1 BACKGROUND HEADER VDD VDD 4.7 kΩ to 10 kΩ NOTE 2 PTC6/BKGD/MS PORT C PTB0/KBI2P0/EXTAL BP[2:0] BP3/FP40 LCD PTB2/RESET NOTE6 FP[39:0] NOTE 6 0.1 μF OPTIONAL MANUAL RESET NOTE 5 X VLCD VLL1 VLL2 NOTE 4 CBYLCD CBYLCD VLL3 CBYLCD VCAP1 CLCD VCAP2 NOTES: 1. Not required if using the internal oscillator option. 2. BKGD/MS is the same pin as PTC6. 3. The 64-pin LQFP combines (VSSAD to VREFL) and combines (VDDAD to VREFH) 4. VLCD, VLL1, VLL2, and VLL3 can be powered internally using VDD or externally based on software configuration of the LCD module. (Shown as internally powered). 5. VLCD is a “no connect” when the LCD module is being powered via VDD. 6. An RC filter on RESET is recommended for EMC-sensitive applications. Figure 2-3. Basic System Connections MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 28 Freescale Semiconductor Chapter 2 Pins and Connections 2.3.1 Power (VDD, VSS, VDDAD, VSSAD) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-μF ceramic bypass capacitor located as close to the MCU power pins as practical to suppress high-frequency noise. VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to the ADC. A 0.1-μF ceramic bypass capacitor should be located as close to the MCU power pins as practical to suppress high-frequency noise. 2.3.2 ADC Reference Pins (VREFH, VREFL ) VREFH and VREFL are the voltage reference high and voltage reference low pins, respectively, for the ADC module. In the 64-pin package, VREFH and VREFL are shared with VDDAD and VSSAD, respectively. 2.3.3 Oscillator (XTAL, EXTAL) Out of reset, the MCU uses an internally generated clock (self-clocked mode — fSelf_reset), that is approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, see Chapter 10, “Internal Clock Generator (S08ICGV4).” The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin, and the XTAL output pin can be used as general I/O. Refer to Figure 2-3 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 which are usually the same size. As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 29 Chapter 2 Pins and Connections 2.3.4 RESET Pin After POR, the configuration of the PTB2/RESET pin defaults to RESET. Clearing the RSTPE bit in SOPT1 register configures the pin to be the PTB2 general-purpose, output only pin. After configured as PTB2, the pin will remain PTB2 until the next reset. The RESET pin can be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET pin (RSTPE = 1), an internal pullup device is automatically enabled. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. The PTB2/RESET pin will default to the RESET pin when a POR enters active background mode. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, when the pin is configured as the RESET pin, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 cycles of fSelf_reset, released, and sampled again approximately 38 cycles of fSelf_reset later. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS). In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-3 for an example. 2.3.5 Background / Mode Select (BKGD/MS) The background / mode select (BKGD/MS) shares its function with an output-only port pin, PTC6. While in reset, the pin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin (BKGDPE = 1), the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. When used as an I/O port, the pin is limited to output only. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset which forces the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 30 Freescale Semiconductor Chapter 2 Pins and Connections 2.3.6 2.3.6.1 LCD Pins LCD Power Pins The VLCD, VLL1, VLL2, VLL3, Vcap1, and Vcap2 pins are dedicated to providing power to the LCD module. For detailed information about these pins see the LCD chapter. 2.3.6.2 LCD Frontplane and Backplane Driver Pins 44 pins are dedicated to frontplane and backplane drivers; on the 64-pin package, 36 pins are dedicated. Immediately after reset, the LCD driver pins are high-impedance. For detailed information about LCD frontplane and backplane driver pins, see the LCD chapter. 2.3.7 General-Purpose I/O and Peripheral Ports MC9S08LC60 Series MCUs support up to 24 general-purpose I/O pins which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard interrupts, etc.). On each MC9S08LC60 Series device, there is one input-only and two output-only port pins. When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pullup device. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output.” Immediately after reset, all pins that are not output-only are configured as high-impedance general-purpose inputs with internal pullup devices disabled. After reset, the output-only port function is not enabled but is configured for low output drive strength with slew rate control enabled. The PTC6 pin defaults to BKGD/MS on any reset. NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 31 Chapter 2 Pins and Connections Table 2-1. Pin Availability by Package Pin-Count Pin Number 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Highest Alt3 Pin Number 80 41 42 43 44 45 46 47 48 49 50 Highest Alt3 64 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 — — 17 18 — — — — 19 Alt 1 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP0 BP1 BP2 BP3 Vcap1 Vcap2 VLL1 VLL2 VLL3 VLCD Alt 2 64 32 33 34 35 36 37 38 — — — — — — — — 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Alt 1 MOSI2 SPSCK2 SS2 KBI2P5 KBI2P6 BKGD KBI2P7 FP39 FP38 FP37 FP36 FP35 FP34 FP33 FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 Alt 2 TxD TPM1CH0 TPM1CH1 TPM2CH0 TPM2CH1 MS IRQ TPMCLK FP40 51 52 53 54 55 56 57 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTA7 KBI1P0 KBI1P1 KBI1P2 KBI1P3 KBI1P4 KBI1P5 KBI1P6 KBI1P7 ADP0 ADP1 ADP2 ADP3 ADP4 ADP5 ADP6 ADP7 VSSAD VREFL VREFH VDDAD ACMP+ ACMP– 58 59 60 61 62 63 64 65 66 67 68 69 70 71 VDD VSS 72 73 74 75 20 — — 23 24 25 26 27 28 29 30 31 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTC0 RESET KBI2P2 MISO1 MOSI1 KBI2P3 KBI2P4 MISO2 SDA SCL SPSCK1 SS1 RxD PTB0 PTB1 KBI2P0 KBI2P1 EXTAL XTAL 76 77 78 78 80 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 32 Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08LC60 Series are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • Features Active background mode for code development Wait mode: — CPU halts operation to conserve power — System clocks running — Full voltage regulation is maintained Stop modes: — CPU and bus clocks stopped — Stop1: Full power-down of internal circuits for maximum power savings — Stop2: Partial power-down of internal circuits, RAM contents retained — Stop3: All internal circuits powered for fast recovery; RAM and register contents are retained; LCD module can be configured to remain operational • 3.3 Run Mode Run is the normal operating mode for the MC9S08LC60 Series. This mode is selected upon the MCU exiting reset if the BKGD/MS pin is high. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provides the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the time the MCU exits reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 33 Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When MC9S08LC60 Series MCUs are shipped from the Freescale factory, the FLASH program memory is erased by default unless specifically noted, so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter. 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in the condition code register (CCR) is cleared when the CPU enters wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available while the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 34 Freescale Semiconductor Chapter 3 Modes of Operation 3.6 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In any stop mode, the bus and CPU clocks are halted. The ICG module can be configured to leave the reference clocks running. see Chapter 10, “Internal Clock Generator (S08ICGV4)” for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. The stop mode behavior of the MCU is configured by setting the appropriate bits in the SPMSC1 and SPMSC2 registers The selected mode is entered following the execution of a STOP instruction. Table 3-1. Stop Mode Selection STOPE 0 1 1 1 1 1 1 ENBDM 1 x 1 0 0 0 0 LVDE and LVDSE x x 1 0 0 0 PDC x x x 0 1 1 PPDC x x x x 1 0 Stop Mode Stop modes disabled; illegal opcode reset if STOP instruction executed Stop3 with BDM enabled 2 Stop3 with voltage regulator active Stop33 Stop2 Stop1 ENBDM is located in the BDCSCR which is only accessible through BDC commands, see the Development Support section. 2 When in Stop3 mode with BDM enabled, The SIDD will be near RIDD levels because internal clocks are enabled. 3 The LCD module can operate in stop3 if LCDSTP3 in LCDCR1 is asserted. 3.6.1 Stop3 Mode Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time interrupt (RTI), LVD, ADC, IRQ or the KBI. If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector. A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 35 Chapter 3 Modes of Operation 3.6.1.1 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate the LVD must be left enabled when entering stop3. 3.6.1.2 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described in the Development Support chapter of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. 3.6.2 Stop2 Mode Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop2 as in stop1 with the exception of the RAM. Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2. Exit from stop2 is performed by asserting the wake-up pins or RESET or IRQ. NOTE IRQ always functions as an active-low wakeup input when the MCU is in stop2, regardless of how the pin is configured before entering stop2. In addition, the real-time interrupt (RTI) can wake the MCU from stop2 if enabled. Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD trip point (low trip point selected due to POR) • The CPU takes the reset vector In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2. To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 36 Freescale Semiconductor Chapter 3 Modes of Operation before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 Stop1 Mode Stop1 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop1, providing the lowest possible standby current. Upon entering stop1, all I/O pins automatically transition to their default reset states. Exit from stop1 is performed by asserting the wake-up pins or RESET or IRQ. NOTE IRQ always functions as an active-low wakeup input when the MCU is in stop1, regardless of how the pin is configured before entering stop1. In addition, the real-time interrupt (RTI) can wake the MCU from stop1 if enabled. Upon wake-up from stop1 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD trip point (low trip point selected due to POR) • The CPU takes the reset vector In addition to the above, upon waking up from stop1, the PDF bit in SPMSC2 is set. This flag is used to direct user code to go to a stop1 recovery routine. PDF remains set until a 1 is written to PPDACK in SPMSC2. 3.6.4 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.3, “Stop1 Mode,” Section 3.6.2, “Stop2 Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 37 Chapter 3 Modes of Operation Table 3-2. Stop Mode Behavior Mode Peripheral Stop1 CPU RAM FLASH Parallel Port Registers ADC ACMP ICG IIC LCD SCI SPI TPM Voltage Regulator I/O Pins 1 2 Stop2 Off Standby Off Off Off Off Off Off Off Off Off Off Standby States Held Stop3 Standby Standby Standby Standby Optionally On1 Standby Optionally On2 Standby Optionally On3 Standby Standby Standby Standby States Held Off Off Off Off Off Off Off Off Off Off Off Off Off Hi-Z Requires the asynchronous ADC clock and LVD to be enabled, else in standby. OSCSPEN set in ICGC1, else in standby. 3 LCDSTP3 = 1 in the LCDCR1 register. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 38 Freescale Semiconductor Chapter 4 Memory 4.1 MC9S08LC60 Series Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08LC60 Series consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x005F) • High-page registers (0x1800 through 0x186F) • Nonvolatile registers (0xFFB0 through 0xFFBF) MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 39 Chapter 4 Memory 0x0000 DIRECT PAGE REGISTERS 0x005F 0x0060 DIRECT PAGE REGISTERS RAM 2560 BYTES 0x0000 0x005F 0x0060 RAM 4096 BYTES 0x0A5F 0x0A60 0x105F 0x1060 FLASH B 1952 BYTES 0x17FF 0x1800 HIGH PAGE REGISTERS 0x186F 0x1870 FLASH B 26,512 BYTES UNIMPLEMENTED 0x17FF 0x1800 HIGH PAGE REGISTERS 0x186F 0x1870 FLASH B 12,288 BYTES 0x486F 0x4870 0x7FFF 0x8000 FLASH A 32,768 BYTES UNIMPLEMENTED 0x9FFF 0xA000 FLASH A 24,576 BYTES 0xFFFF MC9S08LC60 MC9S08LC36 0xFFFF Figure 4-1. MC9S08LC60 Series Memory Map 4.1.1 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08LC60 Series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1. Reset and Interrupt Vectors Address (High/Low) 0xFFC0–0xFFC1 Vector Unused Vector Space (available for user program) Vector Name 0xFFD0–0xFFD1 0xFFD2–0xFFD3 LCD Vlcd MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 40 Freescale Semiconductor Chapter 4 Memory Table 4-1. Reset and Interrupt Vectors Address (High/Low) 0xFFD4–0xFFD5 0xFFD6–0xFFD7 0xFFD8–0xFFD9 0xFFDA–0xFFDB 0xFFDC–0xFFDD 0xFFDE–0xFFDF 0xFFE0–0xFFE1 0xFFE2–0xFFE3 0xFFE4–0xFFE5 0xFFE6–0xFFE7 0xFFE8–0xFFE9 0xFFEA–0xFFEB 0xFFEC–0xFFED 0xFFEE–0xFFEF 0xFFF0–0xFFF1 0xFFF2–0xFFF3 0xFFF4–0xFFF5 0xFFF6–0xFFF7 0xFFF8–0xFFF9 0xFFFA–0xFFFB 0xFFFC–0xFFFD 0xFFFE–0xFFFF Vector RTI IIC ACMP ADC Conversion Keyboard 2 Keyboard 1 SCI Transmit SCI Receive SCI Error SPI 2 SPI 1 TPM2 Overflow TPM2 Channel 1 TPM2 Channel 0 TPM1 Overflow TPM1 Channel 1 TPM1 Channel 0 ICG Low Voltage Detect IRQ SWI Reset Vector Name Vrti Viic Vacmp Vadc Vkeyboard2 Vkeyboard1 Vscitx Vscirx Vscierr Vspi2 Vspi1 Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vswi Vreset MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 41 Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08LC60 Series are divided into these three groups: • Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — NVPROT and NVOPT are loaded into working registers at reset — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 42 Freescale Semiconductor Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 1 of 3) Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 Register Name PTAD PTADD PTBD PTBDD PTCD PTCDD IRQSC Reserved KBI1SC KBI1PE KBI1ES Reserved KBI2SC KBI2PE KBI2ES ACMPSC ADCSC1 ADCSC2 ADCRH ADCRL ADCCVH ADCCVL ADCCFG APCTL1 IICA IICF IICC IICS IICD Reserved Reserved Reserved SCIBDH SCIBDL SCIC1 SCIC2 SCIS1 SCIS2 SCIC3 SCID SPI1C1 SPI1C2 — — — 0 SBR7 LOOPS TIE TDRE 0 R8 Bit 7 SPIE 0 — — — 0 SBR6 SCISWAI TCIE TC 0 T8 6 SPE 0 — — — 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 SPTIE 0 — — — SBR12 SBR4 M ILIE IDLE 0 TXINV 4 MSTR MODFEN IICEN TCF MULT IICIE IAAS MST BUSY TX ARBL DATA — — — SBR11 SBR3 WAKE TE OR 0 ORIE 3 CPOL BIDIROE — — — SBR10 SBR2 ILT RE NF BRK13 NEIE 2 CPHA 0 — — — SBR9 SBR1 PE RWU FE 0 FEIE 1 SSOE SPISWAI — — — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 LSBFE SPC0 TXAK 0 Bit 7 PTAD7 PTADD7 PTBD7 PTBDD7 PTCD7 PTCDD7 0 — 0 KBIPE7 KBEDG7 — 0 KBIPE7 KBEDG7 ACME COCO ADACT 0 ADR7 0 ADCV7 ADLPC ADPC7 6 PTAD6 PTADD6 PTBD6 PTBDD6 PTCD6 PTCDD6 IRQPDD — 0 KBIPE6 KBEDG6 — 0 KBIPE6 KBEDG6 ACBGS AIEN ADTRG 0 ADR6 0 ADCV6 ADPC6 ADIV ADPC5 5 PTAD5 PTADD5 PTBD5 PTBDD5 PTCD5 PTCDD5 IRQEDG — 0 KBIPE5 KBEDG5 — 0 KBIPE5 KBEDG5 ACF ADCO ACFE 0 ADR5 0 ADCV5 ACFGT 0 ADR4 0 ADCV4 ADLSMP ADPC4 ADDR ICR RSTA SRW 0 IICIF 0 RXAK — ADR11 ADR3 ADCV11 ADCV3 ADPC3 4 PTAD4 PTADD4 PTBD4 PTBDD4 PTCD4 PTCDD4 IRQPE — 0 KBIPE4 KBEDG4 — 0 KBIPE4 KBEDG4 ACIE 3 PTAD3 PTADD3 PTBD3 PTBDD3 PTCD3 PTCDD3 IRQF — KBF KBIPE3 KBEDG3 — KBF KBIPE3 KBEDG3 ACO 2 PTAD2 PTADD2 PTBD2 PTBDD2 PTCD2 PTCDD2 IRQACK — KBACK KBIPE2 KBEDG2 — KBACK KBIPE2 KBEDG2 R1 ADCH — ADR10 ADR2 ADCV10 ADCV2 ADPC2 — ADR9 ADR1 ADCV9 ADCV1 ADPC1 — ADR8 ADR0 ADCV8 ADCV0 ADPC0 0 1 PTAD1 PTADD1 PTBD1 PTBDD1 PTCD1 PTCDD1 IRQIE — KBIE KBIPE1 KBEDG1 — KBIE KBIPE1 KBEDG1 Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 IRQMOD — KBIMOD KBIPE0 KBEDG0 — KBIMOD KBIPE0 KBEDG0 ACMOD MODE ADICLK MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 43 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 2 of 3) Address 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 Register Name SPI1BR SPI1S Reserved SPI1D Reserved Reserved SPI2C1 SPI2C2 SPI2BR SPI2S Reserved SPI2D Reserved Reserved ICGC1 ICGC2 ICGS1 ICGS2 ICGFLTU ICGFLTL ICGTRM Reserved TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL TPM1C1SC TPM1C1VH TPM1C1VL Reserved Reserved Reserved Reserved Reserved TPM2SC TPM2CNTH TPM2CNTL TPM2MODH 0 TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — — — — — TOF Bit 15 Bit 7 Bit 15 0 TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — — — — — TOIE 14 6 14 0 CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — — — — — CPWMS 13 5 13 0 CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — — — — — CLKSB 12 4 12 0 0 Bit 7 0 SPRF 0 Bit 7 0 0 SPIE 0 0 SPRF 0 Bit 7 0 0 HGO LOLRE CLKST 0 0 6 SPPR2 0 0 6 0 0 SPE 0 SPPR2 0 0 6 0 0 RANGE 5 SPPR1 SPTEF 0 5 0 0 SPTIE 0 SPPR1 SPTEF 0 5 0 0 REFS MFD REFST 0 0 LOLS 0 0 FLT TRIM 0 CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — — — — — CLKSA 11 3 11 0 PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — — — — — PS2 10 2 10 0 PS1 9 1 9 1 0 9 1 0 9 1 — — — — — PS1 9 1 9 0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — — — — PS0 Bit 8 Bit 0 Bit 8 4 SPPR0 MODF 0 4 0 0 MSTR MODFEN SPPR0 MODF 0 4 0 0 CLKS LOCRE LOCK 0 LOCS 0 FLT 3 0 0 0 3 0 0 CPOL BIDIROE 0 0 0 3 0 0 2 SPR2 0 0 2 0 0 CPHA 0 SPR2 0 0 2 0 0 OSCSTEN 1 SPR1 0 0 1 0 0 SSOE SPISWAI SPR1 0 0 1 0 0 LOCD RFD ERCS 0 ICGIF DCOS Bit 0 SPR0 0 0 Bit 0 0 0 LSBFE SPC0 SPR0 0 0 Bit 0 0 0 0 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 44 Freescale Semiconductor Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 3 of 3) Address 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B– 0x005F 1 Register Name TPM2MODL TPM2C0SC TPM2C0VH TPM2C0VL TPM2C1SC TPM2C1VH TPM2C1VL Reserved Bit 7 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — 6 6 CH0IE 14 6 CH1IE 14 6 — 5 5 MS0B 13 5 MS1B 13 5 — 4 4 MS0A 12 4 MS1A 12 4 — 3 3 ELS0B 11 3 ELS1B 11 3 — 2 2 ELS0A 10 2 ELS1A 10 2 — 1 1 0 9 1 0 9 1 — Bit 0 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — For the MC9S08LC60 Series, the AMCPO pin is not available, so the ACOPE bit in the ACMPSC register is reserved and does not have any effect. High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table 4-3. High-Page Register Summary Address Register Name 0x1800 0x1801 0x1802 0x1803 0x1804 0x1805 0x1806 0x1807 0x1808 0x1809 0x180A 0x180B 0x180C 0x180D– 0x180F 0x1810 0x1811 0x1812 0x1813 0x1814 0x1815 0x1816 0x1817 0x1818 0x1819– 0x181F 0x1820 0x1821 0x1822 0x1823 SRS SBDFR SOPT1 SOPT2 Reserved Reserved SDIDH SDIDL SRTISC SPMSC1 SPMSC2 Reserved SPMSC3 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL DBGC DBGT DBGS Reserved FCDIV FOPT Reserved FCNFG Bit 7 POR 0 COPE COPCLKS — — REV3 ID7 RTIF LVDF 0 — LVWF — Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 DBGEN TRGSEL AF — DIVLD KEYEN — 0 6 PIN 0 COPT 0 — — REV2 ID6 RTIACK LVDACK 0 — LVWACK — 14 6 14 6 14 6 ARM BEGIN BF — PRDIV8 FNORED — 0 5 COP 0 STOPE 0 — — REV1 ID5 RTICLKS LVDIE 0 — LVDV — 13 5 13 5 13 5 TAG 0 ARMF — DIV5 0 — KEYACC 4 ILOP 0 — 0 — — REV0 ID4 RTIE LVDRE PDF — LVWV — 12 4 12 4 12 4 BRKEN 0 0 — DIV4 0 — 0 3 0 0 0 0 — — ID11 ID3 0 LVDSE PPDF — 0 — 11 3 11 3 11 3 RWA TRG3 CNT3 — DIV3 0 — 0 2 ICG 0 0 0 — — ID10 ID2 RTIS2 LVDE PPDACK — 0 — 10 2 10 2 10 2 RWAEN TRG2 CNT2 — DIV2 0 — 0 1 LVD 0 BKGDPE 0 — — ID9 ID1 RTIS1 0 PDC — 0 — 9 1 9 1 9 1 RWB TRG1 CNT1 — DIV1 SEC01 — 0 Bit 0 0 BDFR RSTPE ACIC — — ID8 ID0 RTIS0 BGBE PPDC — 0 — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 RWBEN TRG0 CNT0 — DIV0 SEC00 — 0 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 45 Chapter 4 Memory Table 4-3. High-Page Register Summary (continued) Address Register Name 0x1824 0x1825 0x1826 0x1827– 0x182F 0x1830 0x1831 0x1832 0x1833 0x1834 0x1835 0x1836 0x1837 0x1838 0x1839 0x183A 0x183B0x187F 0x1840 0x1841 0x1842 0x1843 0x1844 0x1845 0x1846 0x1847 0x1848 0x1849 0x184A 0x184B 0x184C 0x184D 0x184E 0x184F 0x1850 0x1851 0x1852 0x1853 0x1854 0x1855 0x1856 0x1857 0x1858 0x1859 0x185A 0x185B 0x185C FPROT FSTAT FCMD Reserved PTAPE PTASE PTADS Reserved PTBPE PTBSE PTBDS Reserved PTCPE PTCSE PTCDS Reserved LCDCR0 LCDCR1 FPENR0 FPENR1 FPENR2 FPENR3 FPENR4 FPENR5 LCDRAM0 LCDRAM1 LCDRAM2 LCDRAM3 LCDRAM4 LCDRAM5 LCDRAM6 LCDRAM7 LCDRAM8 LCDRAM9 LCDRAM10 LCDRAM11 LCDRAM12 LCDRAM13 LCDRAM14 LCDRAM15 LCDRAM16 LCDRAM17 LCDRAM18 LCDRAM19 LCDRAM20 Bit 7 FPS7 FCBEF FCMD7 — — PTAPE7 PTASE7 PTADS7 0 PTBPE7 PTBSE7 PTBDS7 0 PTCPE7 PTCSE7 PTCDS7 — LCDEN LCDIEN FP7EN FP15EN FP23EN FP31EN FP39EN 0 FP1BP3 FP3BP3 FP5BP3 FP7BP3 FP9BP3 FP11BP3 FP13BP3 FP15BP3 FP17BP3 FP19BP3 FP21BP3 FP23BP3 FP25BP3 FP27BP3 FP29BP3 FP31BP3 FP33BP3 FP35BP3 FP37BP3 FP39BP3 0 6 FPS6 FCCF FCMD6 — — PTAPE6 PTASE6 PTADS6 0 PTBPE6 PTBSE6 PTBDS6 0 PTCPE6 PTCSE6 PTCDS6 — LPWAVE 0 FP6EN FP14EN FP22EN FP30EN FP38EN 0 FP1BP2 FP3BP2 FP5BP2 FP7BP2 FP9BP2 FP11BP2 FP13BP2 FP15BP2 FP17BP2 FP19BP2 FP21BP2 FP23BP2 FP25BP2 FP27BP2 FP29BP2 FP31BP2 FP33BP2 FP35BP2 FP37BP2 FP39BP2 0 5 FPS5 FPVIOL FCMD5 — — PTAPE5 PTASE5 PTADS5 0 PTBPE5 PTBSE5 PTBDS5 0 PTCPE5 PTCSE5 PTCDS5 — LCLK2 0 FP5EN FP13EN FP21EN FP29EN FP37EN 0 FP1BP1 FP3BP1 FP5BP1 FP7BP1 FP9BP1 FP11BP1 FP13BP1 FP15BP1 FP17BP1 FP19BP1 FP21BP1 FP23BP1 FP25BP1 FP27BP1 FP29BP1 FP31BP1 FP33BP1 FP35BP1 FP37BP1 FP39BP1 0 4 FPS4 FACCERR FCMD4 — — PTAPE4 PTASE4 PTADS4 0 PTBPE4 PTBSE4 PTBDS4 0 PTCPE4 PTCSE4 PTCDS4 — LCLK1 0 FP4EN FP12EN FP20EN FP28EN FP36EN 0 FP1BP0 FP3BP0 FP5BP0 FP7BP0 FP9BP0 FP11BP0 FP13BP0 FP15BP0 FP17BP0 FP19BP0 FP21BP0 FP23BP0 FP25BP0 FP27BP0 FP29BP0 FP31BP0 FP33BP0 FP35BP0 FP37BP0 FP39BP0 0 3 FPS3 0 FCMD3 — — PTAPE3 PTASE3 PTADS3 0 PTBPE3 PTBSE3 PTBDS3 0 PTCPE3 PTCSE3 PTCDS3 — LCLK0 0 FP3EN FP11EN FP19EN FP27EN FP35EN 0 FP0BP3 FP2BP3 FP4BP3 FP6BP3 FP8BP3 FP10BP3 FP12BP3 FP14BP3 FP16BP3 FP18BP3 FP20BP3 FP22BP3 FP24BP3 FP26BP3 FP28BP3 FP30BP3 FP32BP3 FP34BP3 FP36BP3 FP38BP3 FP40BP3 2 FPS2 FBLANK FCMD2 — — PTAPE2 PTASE2 PTADS2 0 PTBPE2 PTBSE2 PTBDS2 0 PTCPE2 PTCSE2 PTCDS2 — 0 0 FP2EN FP10EN FP18EN FP26EN FP34EN 0 FP0BP2 FP2BP2 FP4BP2 FP6BP2 FP8BP2 FP10BP2 FP12BP2 FP14BP2 FP16BP2 FP18BP2 FP20BP2 FP22BP2 FP24BP2 FP26BP2 FP28BP2 FP30BP2 FP32BP2 FP34BP2 FP36BP2 FP38BP2 FP40BP2 1 FPS1 0 FCMD1 — — PTAPE1 PTASE1 PTADS1 0 PTBPE1 PTBSE1 PTBDS1 0 PTCPE1 PTCSE1 PTCDS1 — DUTY1 LCDWAI FP1EN FP9EN FP17EN FP25EN FP33EN 0 FP0BP1 FP2BP1 FP4BP1 FP6BP1 FP8BP1 FP10BP1 FP12BP1 FP14BP1 FP16BP1 FP18BP1 FP20BP1 FP22BP1 FP24BP1 FP26BP1 FP28BP1 FP30BP1 FP32BP1 FP34BP1 FP36BP1 FP38BP1 FP40BP1 Bit 0 FPDIS 0 FCMD0 — — PTAPE0 PTASE0 PTADS0 0 PTBPE0 PTBSE0 PTBDS0 0 PTCPE0 PTCSE0 PTCDS0 — DUTY0 LCDSTP3 FP0EN FP8EN FP16EN FP24EN FP32EN FP40EN FP0BP0 FP2BP0 FP4BP0 FP6BP0 FP8BP0 FP10BP0 FP12BP0 FP14BP0 FP16BP0 FP18BP0 FP20BP0 FP22BP0 FP24BP0 FP26BP0 FP28BP0 FP30BP0 FP32BP0 FP34BP0 FP36BP0 FP38BP0 FP40BP0 MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 46 Freescale Semiconductor Chapter 4 Memory Table 4-3. High-Page Register Summary (continued) Address Register Name 0x185D– 0x1861 0x1862 0x1863 0x1864 0x1865 0x1866– 0x186F Reserved LCDCLKS LCDSUPPLY LCDBCTL LCDCMD Reserved Bit 7 — 6 — 5 — CLKADJ5 CPCADJ1 0 0 — 4 — 3 — 2 — 1 — Bit 0 — SOURCE DIV16 LCDCPEN LCDCPMS BLINK 0 LCDIF 0 — — CLKADJ4 CLKADJ3 CLKADJ2 CLKADJ1 CLKADJ0 CPCADJ0 HDRVBUF BBYPASS VSUPPLY1 VSUPPLY0 0 BLKMODE BRATE2 BRATE1 BRATE0 0 LCDDRMS 0 LCDCLR BLANK — — — — — Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Table 4-4. Nonvolatile Register Summary Address 0xFFB0– 0xFFB7 0xFFB8– 0xFFBC 0xFFBD 0xFFBE 0xFFBF 1 Register Name NVBACKKEY Reserved NVPROT NVICGTRM1 NVOPT Bit 7 6 5 4 3 2 1 Bit 0 8-Byte Comparison Key — FPS7 KEYEN — FPS6 FNORED — FPS5 0 — FPS4 0 — FPS3 0 — FPS2 0 — FPS1 SEC01 — FPDIS SEC00 NVTRIM Freescale Semiconductor provides a factory trim to set the FIRG to 243 kHz. If user code changes the value of the NVICGTRM register, the factory trim value will be lost. User code should save the content of NVICGTRM before any mass erase operation. Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08LC60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 47 Chapter 4 Memory The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08LC60 Series, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP