MC9S08LH64CLK

Freescale Semiconductor Data Sheet: Advanced Information An Energy Efficient Solution by Freescale Document Number: MC9S08LH64 Rev. 4, 04/2010 MC9S08LH64 Series Covers: MC9S08LH64 and MC9S08LH36 • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range of –40 °C to 85 °C – Up to 20 MHz at 2.1 V to 1.8 V across temperature range of –40 °C to 85 °C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources • On-Chip Memory – Dual array flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two low-power stop modes – Reduced-power wait mode – Low-power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents – Very low-power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to time-of-day (TOD) module – 6 μs typical wakeup time from stop3 mode • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting bus frequencies from 1 MHz to 20 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage warning with interrupt – Low-voltage detection with reset or interrupt – Illegal opcode detection with reset; illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface 64-LQFP Case 840F 80-LQFP Case 917A – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) – On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes • Peripherals – LCD — Up to 8×36 or 4×40 LCD driver with internal charge pump and option to provide an internally-regulated LCD reference that can be trimmed for contrast control – ADC —16-bit resolution; with a dedicated differential ADC input, and 8 single-ended ADC inputs; up to 2.5 μs conversion time; hardware averaging; calibration registers, automatic compare function; temperature sensor; operation in stop3; fully functional from 3.6 V to 1.8 V – IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcast mode; 10-bit addressing – ACMP — Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal reference voltage; outputs can be optionally routed to TPM module; operation in stop3 – SCIx — Two full-duplex non-return to zero (NRZ) modules (SCI1 and SCI2); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge – SPI — Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting – TPMx — Two 2-channel (TPM1 and TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – TOD — (Time-of-day) 8-bit, quarter second counter with match register; external clock source for precise time base, time-of-day, calendar, or task scheduling functions – VREFx — Trimmable via an 8-bit register in 0.5 mV steps; automatically loaded with room temperature value upon reset; can be enabled to operate in stop3 mode; trim register is not available in stop modes • Input/Output – Dedicated accurate voltage reference output pin, 1.2 V output (VREFOx); trimmable with 0.5 mV resolution – Up to 39 GPIOs, two output-only pins – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins • Package Options – 14mm × 14mm 80-pin LQFP, 10 mm × 10 mm 64-pin LQFP © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Contents 1 2 3 Devices in the MC9S08LH64 Series . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . 11 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23 3.8 External Oscillator (XOSCVLP) Characteristics . . . . . . 25 3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . . 26 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.13 VREF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .42 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .42 4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .43 4 • Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev 1 2 3 4 Date 10/2007 7/2008 1/2009 4/8/2010 Description of Changes Intial Release of the electrical characteristics in the Reference Manual. Initial Release after product redefinition and restructuring of information into a separate Data Sheet and Reference Manual. Refreshed the draft to include the new VREF module and the latest revisions. Completed RIDD in the Table 9; updated ERREFSTEN in the Table 10; changed all VDDAD to VDDA, VSSAD to VSSA; updated the min. of VREFH; Added 64-pin LQFP package information for LH36 MCU; Updated V Room Temp in the Table 20. Updated S2IDD at VDD = 2 and Temp at –40 to 25 °C Added 64-pin LQFP package for LH36. Updated ADC data in the 3.12/33 Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual —MC9S08LH64RM Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 1 Devices in the MC9S08LH64 Series Table 1. MC9S08LH64 Series Features by MCU and Package Feature Package MC9S08LH64 80-pin LQFP 64-pin LQFP 80-pin LQFP MC9S08LH36 64-pin LQFP Table 1 summarizes the feature set available in the MC9S08LH64 Series of MCUs. FLASH RAM ACMP ADC Single-ended Channels ADC Differential Channels1 IIC IRQ KBI SCI1 SCI2 SPI TPM1 TPM2 TOD LCD VREFO1 VREFO2 I/O pins2 1 2 64 KB (32,768 and 32,768 Arrays) 4000 yes 8-ch 8-ch 36 KB (24,576 and 12,288 Arrays) 4000 yes 8-ch 8-ch 1 yes yes 8 yes yes yes 2-ch 2-ch yes 8×36 4×40 yes no 39 0 1 yes yes 8 yes yes yes 2-ch 2-ch yes 0 8×24 4×28 no yes 37 8×36 4×40 yes no 39 8×24 4×28 no yes 37 Each differential channel consists of two pins (DADPx and DADMx). The 39 I/O pins include two output-only pins and 18 LCD GPIO. The block diagram in Figure 1 shows the structure of the MC9S08LH64 Series MCU. MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 3 HCS08 CORE CPU INT ON-CHIP ICE DEBUG MODULE (DBG) PORT A PTA7/KBIP7/ADP11/ACMP– PTA6/KBIP6/ADP10/ACMP+ PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/MOSI/SCL/KBIP3/ADP7 PTA2/MISO/SDA/KBIP2/ADP6 BKGD BKP TIME OF DAY MODULE (TOD) KBI[7:0] HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-BIT KEYBOARD INTERRUPT (KBI) BKGD/MS SERIAL PERIPHERAL INTERFACE (SPI) PTA1/SPSCK/KBIP1/ADP5 PTA0/SS/KBIP0/ADP4 SS SPSCK MISO MOSI SCL PORT B COP IRQ LVD RESET IRQ PTB7/TxD2/SS PTB6/RxD2/SPSCK IIC MODULE (IIC) SDA TPM2CH0 PTB5/MOSI/SCL PTB4/MISO/SDA USER FLASH A (LH64 = 32,768 BYTES) (LH36 = 24,576 BYTES) 2-CHANNEL TIMER/PWM (TPM2) TPM2CH1 TCLK TPM1CH0 PTB2/RESET PTB1/XTAL PTB0/EXTAL ∞ USER FLASH B (LH64 = 32,768 BYTES) (LH36 = 12,288 BYTES) 2-CHANNEL TIMER/PWM (TPM1) TPM1CH1 TCLK TxD1 RxD1 PTC7/IRQ/TCLK PTC6/ACMPO//BKGD/MS ◊ PTC5/TPM2CH1 PTC4/TPM2CH0 PORT C USER RAM 4K BYTES SERIAL COMMUNICATIONS INTERFACE (SCI1) PTC3/TPM1CH1 PTC2/TPM1CH0 PTC1/TxD1 PTC0/RxD1 INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR XTAL EXTAL SERIAL COMMUNICATIONS INTERFACE (SCI2) TxD2 RxD2 ♦ ♦ VDDA VSSA VREFH VREFL VDD VSS VOLTAGE REGULATOR VREF1 VREF2 ADP[11:4] DADP0 • • 16-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) DADP0 DADM0 • • PORT D DADM0 PTD[7:0]/LCD[7:0] PORT E • ♦ VREFO1 VREFO2 VLCD VLL1 VLL2 VLL3 VCAP1 VCAP2 ANALOG COMPARATOR (ACMP) ACMP– ACMP+ ACMPO PTE[7:0]/LCD[13:20] • Pins not available on 64-pin packages. LCD[8:12] and LCD[31:37] are not LIQUID CRYSTAL DISPLAY LCD NOTES ♦ VREFH and VREFL are internally connected to VDDA and VSSA for the 64-pin ∞ When PTB2 is configured as RESET, the pin becomes bi-directional with output being an open-drain drive. package. VREFO2 is only available on the 64-pin package. available on the 64-pin package. LCD[43:0] ◊ When PTC6 is configured as BKGD, the pin becomes bi-directional. Figure 1. MC9S08LH64 Series Block Diagram MC9S08LH64 Series MCU Data Sheet, Rev. 4 4 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor 2 Pin Assignments This section shows the pin assignments for the This section shows the pin assignments for the MC9S08LH64 Series devices. PTE2/LCD15 PTE3/LCD16 PTE4/LCD17 PTE5/LCD18 PTE6/LCD19 PTE7/LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTE1/LCD14 PTE0/LCD13 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 5 PTA6/KBIP6/ADP10/ACMP+ PTA7/KBIP7/ADP11/ACMP– VSSA/VREFL VDDA/VREFH PTB0/EXTAL PTB1/XTAL VDD VSS PTB2/RESET VREFO2 PTB4/MISO/SDA PTB5/MOSI/SCL PTB6/RxD2/SPSCK PTB7/TxD2/SS PTC0/RxD1 PTC1/TxD1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LCD38 LCD39 LCD40 LCD41 PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 Figure 2. 64-Pin LQFP PTA6/KBIP6/ADP10/ACMP+ PTA7/KBIP7/ADP11/ACMP– VSSA VREFL Figure 3. 80-Pin LQFP Table 2. Pin Availability by Package Pin-Count Highest Alt3 Alt4 LCD7 LCD6 MC9S08LH64 Series MCU Data Sheet, Rev. 4 6 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Table 2. Pin Availability by Package Pin-Count (continued) Highest Alt3 Alt4 64 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Port Pin PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD PTA6 PTA7 VSSA VREFL DADP0 DADM0 VREFO1 VREFH VDDA PTB0 PTB1 VDD VSS PTB2 VREFO2 PTB4 PTB5 PTB6 PTB7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 Alt 1 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 KBIP6 KBIP7 ADP10 ADP11 ACMP+ ACMP– EXTAL XTAL RESET MISO MOSI RxD2 TxD2 RxD1 TxD1 TPM1CH0 TPM1CH1 TPM2CH0 TPM2CH1 ACMPO BKGD MS SDA SCL SPSCK SS MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 7 Table 2. Pin Availability by Package Pin-Count (continued) Highest Alt3 Alt4 64 38 39 40 41 42 43 44 45 46 47 48 Port Pin PTC7 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 LCD41 LCD40 LCD39 LCD38 LCD37 LCD36 LCD35 LCD34 LCD33 LCD32 LCD31 LCD30 LCD29 LCD28 LCD27 LCD26 LCD25 LCD24 LCD23 LCD22 LCD21 PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 Alt 1 IRQ KBIP0 KBIP1 KBIP2 KBIP3 KBIP4 KBIP5 SS SPSCK SDA SCL ADP8 ADP9 MISO MOSI LCD43 LCD42 ADP4 ADP5 ADP6 ADP7 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 LCD14 MC9S08LH64 Series MCU Data Sheet, Rev. 4 8 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Introduction 3 3.1 Electrical Characteristics Introduction This section contains electrical and timing specifications for the MC9S08LH64 Series of microcontrollers available at the time of publication. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 3. Parameter Classifications P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. T D NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 9 Thermal Characteristics Table 4. Absolute Maximum Ratings Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range 1 Symbol VDD IDD VIn ID Tstg Value –0.3 to +3.8 120 –0.3 to VDD + 0.3 ± 25 –55 to 150 Unit V mA V mA °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 80-pin LQFP 64-pin LQFP Thermal resistance Four-layer board 80-pin LQFP 64-pin LQFP θJA 42 54 °C/W θJA 55 73 °C/W Symbol TA TJ Value TL to TH –40 to 85 95 Unit °C °C The average chip-junction temperature (TJ) in °C can be obtained from: MC9S08LH64 Series MCU Data Sheet, Rev. 4 10 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor ESD Protection and Latch-Up Immunity TJ = TA + (PD × θJA) Eqn. 1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 1.8 V ILoad = –0.6 mA VDD > 2.7 V ILoad = –10 mA VDD > 1.8 V ILoad = –3 mA VDD > 1.8 V ILoad = –0.5 mA VDD > 2.7 V ILoad = –2.5 mA VDD > 1.8 V ILoad = –1 mA IOHT VDD >1.8 V ILoad = 0.6 mA VDD > 2.7 V ILoad = 10 mA VDD > 1.8 V ILoad = 3 mA Symbol Condition Min 1.8 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 — — Typ1 Max 3.6 — V Unit V — — — — C 3 Output high P voltage C 4 D Output high current — — V — — — — — 100 mA C 5 Output low P voltage C — — 0.5 V — — — — 0.5 0.5 MC9S08LH64 Series MCU Data Sheet, Rev. 4 12 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor DC Characteristics Table 8. DC Characteristics (continued) Num C C 6 Output low P voltage C 7 8 9 10 D Output low current Characteristic PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength Max total IOL for all ports all digital inputs all digital inputs all digital inputs all input only pins (Per pin) VOL Symbol Condition VDD > 1.8 V ILoad = 0.5 mA VDD > 2.7 V ILoad = 3 mA VDD > 1.8 V ILoad = 1 mA IOLT VIH VIL Vhys |IIn| VIn = VDD or VSS VDD > 2.7 V VDD > 1.8 V VDD > 2.7 V VDD > 1.8 V Min — Typ1 — Max 0.5 V Unit — — — 0.70 x VDD 0.85 x VDD — — 0.06 x VDD — — — — — — — — — 0.5 0.5 100 — — 0.35 x VDD 0.30 x VDD — mA P Input high C voltage P Input low C voltage C Input hysteresis V mV μA 11 Input P leakage current Hi-Z (off-state) P leakage current Total P leakage current3 Pullup, P Pulldown resistors Pullup, P Pulldown resistors 0.025 1 12 all input/output (per pin) |IOZ| VIn = VDD or VSS — 0.025 1 μA 13 Total leakage current for all pins all non-LCD pins when enabled LCD/GPIO pins when enabled |IInT| RPU, RPD RPU, RPD VIn = VDD or VSS — — 3 μA 14 17.5 — 52.5 kΩ 15 35 –0.2 — — — — 0.6 1.4 — 1.84 1.92 2.14 80 1.17 77 0.2 5 8 1.0 2.0 — 1.88 1.96 2.2 — 1.18 kΩ mA mA pF V V μs V V mV V 16 17 18 19 20 21 22 23 24 DC injection Single pin limit D current 4, 5, Total MCU limit, includes 6 sum of all stressed pins C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage D POR re-arm time P Low-voltage detection threshold P Low-voltage warning threshold P Low-voltage inhibit reset/recover hysteresis 7 IIC CIn VRAM VPOR tPOR VLVD VLVW Vhys VBG VIN < VSS, VIN > VDD –5 — — 0.9 10 VDD falling VDD rising VDD falling VDD rising 1.80 1.88 2.08 — 1.15 P Bandgap Voltage Reference8 MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 13 DC Characteristics 1 2 3 4 5 6 7 8 Typical values are measured at 25°C. Characterized, not tested All I/O pins except for LCD pins in Open Drain mode. Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). POR will occur below the minimum voltage. Factory trimmed at VDD = 3.0 V, Temp = 25 °C Figure 4. Non LCD pins I/O Pullup Typical Resistor Values MC9S08LH64 Series MCU Data Sheet, Rev. 4 14 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor DC Characteristics Figure 5. Typical Low-Side Driver (Sink) Characteristics (Non LCD Pins) — Low Drive (PTxDSn = 0) MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 15 DC Characteristics Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1) MC9S08LH64 Series MCU Data Sheet, Rev. 4 16 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor DC Characteristics Figure 7. Typical High-Side (Source) Characteristics (Non LCD Pins)— Low Drive (PTxDSn = 0) MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 17 DC Characteristics Figure 8. Typical High-Side (Source) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1) MC9S08LH64 Series MCU Data Sheet, Rev. 4 18 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor DC Characteristics Figure 9. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0) MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 19 DC Characteristics Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1) MC9S08LH64 Series MCU Data Sheet, Rev. 4 20 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor DC Characteristics Figure 11. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0) MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 21 DC Characteristics Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1) MC9S08LH64 Series MCU Data Sheet, Rev. 4 22 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Supply Current Characteristics 3.7 Supply Current Characteristics Table 9. Supply Current Characteristics This section includes information about power supply current in various operating modes. Bus Freq 20 MHz Run supply current FEI mode, all modules on Num C T Parameter Symbol VDD (V) Typ1 13.75 Max 17.9 — — — — — — Unit Temp (°C) 1 T T T T T T RIDD 8 MHz 1 MHz 20 MHz 3 7 2 8.9 mA –40 to 85 2 Run supply current FEI mode, all modules off RIDD 8 MHz 1 MHz 32 kHz FBILP 16 kHz FBELP 3 5.5 0.9 185 mA –40 to 85 3 T T 4 T T 5 T T P C 6 P C C C P C 7 P C C C 1 Run supply current LPS=0, all modules off RIDD 3 115 μA — — — — — 6 — — 1.3 6 13 1.0 5 10 1.8 8.0 20 1.5 6.8 14 μA μA mA μA –-40 to 85 Run supply current LPS=1, all modules off, running from Flash Run supply current LPS=1, all modules off, running from RAM 21.9 RIDD 16 kHz FBELP 3 7.3 20 MHz WIDD 8 MHz 1 MHz 3 4.57 2 0.73 0.4 3 S2IDD n/a 2 4 8.5 0.35 3.9 7.7 0.65 3 S3IDD n/a 2 5.7 12.2 0.6 5 11.5 0 to 70 –40 to 85 0 to 70 –40 to 85 –40 to 85 –40 to 25 70 85 –40 to 25 70 85 –40 to 25 70 85 –40 to 25 70 85 Wait mode supply current FEI mode, all modules off Stop2 mode supply current Stop3 mode supply current No clocks active Typical values are measured at 25 °C. Characterized, not tested MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 23 Supply Current Characteristics Table 10. Stop Mode Adders Temperature (°C) Num 1 2 3 4 5 6 7 C T T T T T T T LPO ERREFSTEN IREFSTEN TOD LVD1 ACMP ADC1 1 1 Parameter Condition –40 100 RANGE = HGO = 0 750 63 Does not include clock source current LVDSE = 1 Not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for driving 192 segments, 32 Hz frame rate, No LCD glass connected. 50 110 12 95 25 100 750 70 50 110 12 95 70 150 800 77 75 112 20 101 85 175 850 81 100 115 23 120 Units nA nA μA nA μA μA μA 8 1 T LCD 1 1 6 13 μA Not available in stop2 mode. Figure 13. Typical Run IDD for FBE and FEI, IDD vs. VDD (ACMP and ADC off, All Other Modules Enabled) MC9S08LH64 Series MCU Data Sheet, Rev. 4 24 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor External Oscillator (XOSCVLP) Characteristics 3.8 External Oscillator (XOSCVLP) Characteristics Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient) Reference Figure 14 and Figure 15 for crystal or resonator circuits. Num C Characteristic Symbol Min Typ1 Max Unit 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) Load capacitors Low range (RANGE=0), low power (HGO=0) D Other oscillator settings Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, high gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high gain C High range, low power High range, high gain D Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode FBE or FBELP mode flo fhi fhi 32 1 1 — — — 38.4 16 8 kHz MHz MHz 2 C1,C2 See Note 2 See Note 3 3 RF — — — — — — — — — — — — — 0.03125 0 — 10 1 — 100 0 0 0 0 600 400 5 15 — — — — — — — — 0 10 20 — — — — 20 20 MΩ 4 RS kΩ t t 5 CSTL ms CSTH 6 1 2 fextal MHz MHz Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 25 Internal Clock Source (ICS) Characteristics XOSCVLP EXTAL XTAL RS RF C1 Crystal or Resonator C2 Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Internal Clock Source (ICS) Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient) Typ1 32.7 — 32.7 60 16.8 33.6 — — ±0.1 ±0.2 Num 1 2 3 4 5 C Characteristic Symbol fint_ut fint_t fint_t tIRST Min 25 31.25 — — 12.8 Max 41.66 39.06 — 100 21.33 Unit kHz kHz kHz μs MHz C Average internal reference frequency — untrimmed P P T P Average internal reference frequency — user-trimmed Average internal reference frequency — factory-trimmed Internal reference start-up time Low range (DFR = 00) Mid range (DFR = 01) Low range (DFR = 00) Mid range (DFR = 01) DCO output frequency C range — untrimmed P DCO output frequency range — trimmed fdco_ut 25.6 16 42.67 20 MHz 40 ±0.2 ±0.4 %fdco %fdco 6 P C C fdco_t Δfdco_res_t Δfdco_res_t 32 — — 7 8 Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) MC9S08LH64 Series MCU Data Sheet, Rev. 4 26 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor AC Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient) (continued) Num 9 10 11 12 1 2 C C C Characteristic Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 °C to 70 °C Symbol Δfdco_t Δfdco_t tAcquire CJitter Min — — — — Typ1 +0.5 –1.0 ±0.5 — 0.02 Max ±2 ±1 1 0.2 Unit %fdco %fdco ms %fdco C FLL acquisition time2 C Long term jitter of DCO output clock (averaged over 2-ms interval)3 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 27 AC Characteristics 3.10.1 Control Timing Table 13. Control Timing Num 1 2 3 4 5 6 C D D D D D D Rating Bus frequency (tcyc = 1/fBus) VDD ≤ 2.1V VDD > 2.1V Internal low power oscillator period External reset pulse Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) width2 Symbol fBus tLPO textrst trstdrv tMSSU tMSH Min dc dc 700 100 34 x tcyc 500 100 Typ1 — — — — — — — Max 10 20 1300 — — — — Unit MHz μs ns ns ns μs 7 D tILIH, tIHIL 100 1.5 × tcyc 100 1.5 × tcyc — — — — — — — — ns 8 D tILIH, tIHIL ns tRise, tFall 9 C — — 16 23 — — ns tRise, tFall — — 5 9 — — ns 1 2 3 4 5 6 Typical values are based on characterization data at VDD = 3.0 V, 25 °C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C. Except for LCD pins in Open Drain mode. textrst RESET PIN Figure 17. Reset Timing MC9S08LH64 Series MCU Data Sheet, Rev. 4 28 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor AC Characteristics tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 18. IRQ/KBIPx Timing 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TPM Input Timing No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit Hz tcyc tcyc tcyc tcyc tTCLK tclkh TCLK tclkl Figure 19. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 20. Timer Input Capture Pulse MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 29 AC Characteristics 3.10.3 SPI Timing Table 15. SPI Timing Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system. No. — C D Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol fop Min fBus/2048 0 2 4 1/2 1 1/2 1 tcyc – 30 tcyc – 30 15 15 0 25 — — Max fBus/2 fBus/4 2048 — — — — — 1024 tcyc — — — — — 1 1 Unit Hz 1 D tSPSCK tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc 2 D tLead 3 D tLag 4 D tWSPSCK 5 D tSU 6 D tHI 7 D D ta tdis 8 9 D tv — — 0 0 — — — — 25 25 — — tcyc – 25 25 tcyc – 25 25 ns ns ns ns ns ns ns ns 10 D tHO 11 D tRI tRO tFI tFO 12 D MC9S08LH64 Series MCU Data Sheet, Rev. 4 30 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor AC Characteristics SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 MS BIN2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 21. SPI Master Timing (CPHA = 0) SS1 (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 4 4 11 12 12 11 3 5 MSB IN2 6 BIT 6 . . . 1 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 22. SPI Master Timing (CPHA =1) MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 31 AC Characteristics SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT) NOTE: 12 11 3 4 4 11 12 8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1 10 10 SEE NOTE 1 SLAVE LSB OUT LSB IN 1. Not defined but normally MSB of character just received. Figure 23. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 1 7 MOSI (INPUT) 2 12 3 11 4 4 11 12 9 SLAVE ‘c MSB IN MSB OUT 6 10 BIT 6 . . . 1 SLAVE LSB OUT c BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 24. SPI Slave Timing (CPHA = 1) MC9S08LH64 Series MCU Data Sheet, Rev. 4 32 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Analog Comparator (ACMP) Electricals 3.11 C D P D P C P C Analog Comparator (ACMP) Electricals Table 16. Analog Comparator Electrical Specifications Characteristic Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT 3.0 — — Min 1.8 — VSS – 0.3 Typical — 20 — 20 9.0 — — Max 3.6 35 VDD 40 15.0 1.0 1.0 Unit V μA V mV mV μA μs Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay 3.12 ADC Characteristics Table 17. 16-bit ADC Operating Conditions Num 1 2 3 Charact eristic Supply voltage Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacit ance Input Resista nce Conditions Absolute Delta to VDD (VDD–VDDA)2 Symb VDDA ΔVDDA ΔVSSA Min 1.8 –100 –100 Typ1 — 0 0 Max 3.6 100 100 Unit V mV mV Comment Delta to VSS (VSS–VSSA)2 4 VREFH 1.15 VDDA VDDA V 5 VREFL VSSA VSSA VSSA V 6 VADIN 16-bit modes 8/10/12-bit modes VREFL — 8 4 VREFH 10 5 V 7 CADIN — pF 8 RADIN — 2 5 kΩ MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 33 ADC Characteristics Table 17. 16-bit ADC Operating Conditions Num Charact eristic Conditions 16 bit modes fADCK > 8MHz 4MHz < fADCK < 8MHz fADCK < 4MHz 13/12 bit modes fADCK > 8MHz 4MHz < fADCK < 8MHz fADCK < 4MHz 11/10 bit modes fADCK > 8MHz 4MHz < fADCK < 8MHz fADCK < 4MHz 9/8 bit modes fADCK > 8MHz fADCK < 8MHz ADC Convers ion Clock Freq. ADLPC = 0, ADHSC = 1 ADLPC = 0, ADHSC = 0 ADLPC = 1, ADHSC = 0 fADCK Symb Min Typ1 Max Unit Comment 9 — — — — — — — — — — — 1.0 1.0 1.0 — — — — — — — — — — — — — — 0.5 1 2 1 2 5 2 5 10 5 10 8 5 2.5 MHz 10 Analog Source Resista nce External to MCU kΩ Assumes ADLSMP=0 RAS 11 12 13 14 15 1 Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. MC9S08LH64 Series MCU Data Sheet, Rev. 4 34 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor ADC Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + – + – CAS RADIN INPUT PIN RADIN For Differential Mode, this figure applies to both inputs INPUT PIN RADIN CADIN INPUT PIN Figure 25. ADC Input Impedance Equivalency Diagram Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDA > 1.8, VREFL = VSSA, FADCK < 8MHz) Characteristic Supply Current Conditions1 ADLPC = 1, ADHSC = 0 ADLPC = 0, ADHSC = 0 ADLPC=0, ADHSC=1 Supply Current ADC Asynchronous Clock Source Stop, Reset, Module Off ADLPC = 1, ADHSC = 0 ADLPC = 0, ADHSC = 0 ADLPC = 0, ADHSC = 1 Sample Time Conversion Time See reference manual for sample times See reference manual for conversion times P fADACK C IDDA T IDDA C Symb Min — — — — — — — Typ2 215 470 610 0.01 2.4 5.2 6.2 Max — — — — — — — MHz tADACK = 1/fADACK μA μA ADLSMP = 0 ADCO = 1 Unit Comment MC9S08LH64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 35 ADC Characteristics Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDA > 1.8, VREFL = VSSA, FADCK < 8MHz) Characteristic Total Unadjusted Error Conditions1 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Differential Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Integral Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Zero-Scale Error 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode C T T T T T T T T T T T T T T T T EZS INL DNL Symb TUE Min — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Typ2 ±16 ±20 ±1.5 ±1.75 ±0.7 ±0.8 ±0.5 ±0.5 ±2.5 ±2.5 ±0.7 ±0.7 ±0.5 ±0.5 ±0.2 ±0.2 ±6.0 ±10.0 ±1.0 ±1.0 ±0.5 ±0.5 ±0.3 ±0.3 ±4.0 ±4.0 ±0.7 ±0.7 ±0.4 ±0.4 ±0.2 ±0.2 Max +48/-40 +56/-28 ±3.0 ±3.5 ±1.5 ±1.5 ±1.0 ±1.0 +5/-3 +5/-3 ±1 ±1 ±0.75 ±0.75 ±0.5 ±0.5 ±16.0 ±20.0 ±2.5 ±2.5 ±1.0 ±1.0 ±0.5 ±0.5 +32/-24 +24/-16 ±2.5 ±2.0 ±1.0 ±1.0 ±0.5 ±0.5 LSB2 VADIN = VSSA LSB2 LSB2 Unit LSB3 Comment 32x Hardware Averaging (AVGE = %1 AVGS = %11) MC9S08LH64 Series MCU Data Sheet, Rev. 4 36 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor ADC Characteristics Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDA > 1.8, VREFL = VSSA, FADCK < 8MHz) Characteristic Full-Scale Error Conditions1 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Quantization Error Effective Number of Bits 16 bit modes 2.7V, VREFL = VSSA, FADCK < 4MHz, ADHSC=1) Characteristic Total Unadjusted Error Conditions1 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Differential Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Integral Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Zero-Scale Error 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode C T T T T T T T T T T T T T T T T EZS INL DNL Symb TUE Min — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Typ2 ±16 ±20 ±1.5 ±1.75 ±0.7 ±0.8 ±0.5 ±0.5 ±2.5 ±2.5 ±0.7 ±0.7 ±0.5 ±0.5 ±0.2 ±0.2 ±6.0 ±10.0 ±1.0 ±1.0 ±0.5 ±0.5 ±0.3 ±0.3 ±4.0 ±4.0 ±0.7 ±0.7 ±0.4 ±0.4 ±0.2 ±0.2 Max +24/-24 +32/-20 ±2.0 ±2.5 ±1.0 ±1.25 ±1.0 ±1.0 ±3 ±3 ±1 ±1 ±0.75 ±0.75 ±0.5 ±0.5 ±12.0 ±16.0 ±2.0 ±2.0 ±1.0 ±1.0 ±0.5 ±0.5 +16/0 +16/-8 ±2.0 ±2.0 ±1.0 ±1.0 ±0.5 ±0.5 LSB2 VADIN = VSSA LSB2 LSB2 Unit LSB3 Comment 32x Hardware Averaging (AVGE = %1 AVGS = %11) MC9S08LH64 Series MCU Data Sheet, Rev. 4 38 PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor ADC Characteristics Table 19. 16-bit ADC Characteristics(VREFH = VDDA > 2.7V, VREFL = VSSA, FADCK < 4MHz, ADHSC=1) Characteristic Full-Scale Error Conditions1 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Quantization Error Effective Number of Bits 16 bit modes