Freescale Semiconductor Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08LL64 Rev. 4, 08/2009
MC9S08LL64 Series
Covers: MC9S08LL64 and MC9S08LL36
• 8-Bit HCS08 Central Processor Unit (CPU) – Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range of –40 °C to 85 °C – Up to 20 MHz at 2.1 V to 1.8 V across temperature range of –40 °C to 85 °C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources • On-Chip Memory – Dual array flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two low-power stop modes – Reduced-power wait mode – Low-power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents – Very low-power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to time-of-day (TOD) module – 6 μs typical wakeup time from stop3 mode • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting bus frequencies from 1 MHz to 20 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage warning with interrupt – Low-voltage detection with reset or interrupt – Illegal opcode detection with reset; illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface
64-LQFP Case 840F
80-LQFP Case 917A
– Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) – On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes • Peripherals – LCD — Up to 8×36 or 4×40 LCD driver with internal charge pump and option to provide an internally-regulated LCD reference that can be trimmed for contrast control – ADC —10-channel, 12-bit resolution; up to 2.5 μs conversion time; automatic compare function; temperature sensor; operation in stop3; fully functional from 3.6 V to 1.8 V – IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcast mode; 10-bit addressing – ACMP — Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal reference voltage; outputs can be optionally routed to TPM module; operation in stop3 – SCIx — Two full-duplex non-return to zero (NRZ) modules (SCI1 and SCI2); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge – SPI — Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting – TPMx — Two 2-channel (TPM1 and TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – TOD — (Time-of-day) 8-bit, quarter second counter with match register; external clock source for precise time base, time-of-day, calendar, or task scheduling functions – VREFx — Trimmable via an 8-bit register in 0.5 mV steps; automatically loaded with room temperature value upon reset; can be enabled to operate in stop3 mode; trim register is not available in stop modes. • Input/Output – Dedicated accurate voltage reference output pin, 1.2 V output (VREFOx); trimmable with 0.5 mV resolution – Up to 39 GPIOs, two output-only pins – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins • Package Options – 14mm × 14mm 80-pin LQFP, 10 mm × 10 mm 64-pin LQFP
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Contents
1 2 3 Devices in the MC9S08LL64 Series. . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . 11 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23 3.8 External Oscillator (XOSCVLP) Characteristics . . . . . . 24 3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . . 26 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.13 VREF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .40 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .41 4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .41
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev 1 2 3 4 Date 7/2008 01/2009 03/2009 08/2009 Description of Changes Intial Release of the electrical characteristics in the Reference Manual. Initial Release after product redefinition and restructuring of information into a separate Data Sheet and Reference Manual. Incorporated revisions for customer release. Completed all the TBDs. Corrected Pin out in the Figure 2, Figure 3 and Table 2. Updated VOH, |IIn|, |IOZ|, RPU, RPD, added |IINT| in the Table 8. Updated Table 9. Updated ERREFSTEN and added LCD in the Table 10. Updated fADACK, ETUE, DNL, INL, EZS and EFS in the Table 18. Updated V Room Temp in the Table 19.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual — MC9S08LL64RM Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 2 Freescale Semiconductor
1
Devices in the MC9S08LL64 Series
Table 1. MC9S08LL64 Series Features by MCU and Package
Feature Package MC9S08LL64 80-pin LQFP 64-pin LQFP MC9S08LL36 64-pin LQFP 36 KB (24,576 and 12,288 Arrays) 4000 yes 8-ch yes yes 8 yes yes yes 2-ch 2-ch yes 8×36 4×40 yes no 39 8×24 4×28 no yes 37 — 8-ch yes yes 8 yes yes yes 2-ch — yes 8×24 4×28 no yes 37
Table 1 summarizes the feature set available in the MC9S08LL64 series of MCUs.
FLASH RAM ACMP ADC IIC IRQ KBI SCI1 SCI2 SPI TPM1 TPM2 TOD LCD VREFO1 VREFO2 I/O pins1
1
64 KB (32,768 and 32,768 Arrays) 4000 yes 10-ch
The 39 I/O pins include two output-only pins and 18 LCD GPIO.
The block diagram in Figure 1 shows the structure of the MC9S08LL64 series MCU.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 3
HCS08 CORE CPU INT
ON-CHIP ICE DEBUG MODULE (DBG) PORT A
PTA7/KBIP7/ADP11/ACMP– PTA6/KBIP6/ADP10/ACMP+ PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6
BKGD
BKP
TIME OF DAY MODULE (TOD) KBI[7:0]
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT
8-BIT KEYBOARD INTERRUPT (KBI) BKGD/MS SERIAL PERIPHERAL INTERFACE (SPI)
PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 SS SPSCK MISO MOSI SCL PORT B
COP IRQ LVD
RESET IRQ
PTB7/TxD2/SS PTB6/RxD2/SPSCK
IIC MODULE (IIC)
SDA TPM2CH0
PTB5/MOSI/SCL PTB4/MISO/SDA
USER FLASH A (LL64 = 32,768 BYTES) (LL36 = 24,576 BYTES)
2-CHANNEL TIMER/PWM (TPM2)
TPM2CH1 TCLK TPM1CH0
PTB2/RESET PTB1/XTAL PTB0/EXTAL
∞
USER FLASH B (LL64 = 32,768 BYTES) (LL36 = 12,288 BYTES)
2-CHANNEL TIMER/PWM (TPM1)
TPM1CH1 TCLK TxD1 RxD1 PTC7/IRQ/TCLK PTC6/ACMPO//BKGD/MS ◊ PTC5/TPM2CH1 PTC4/TPM2CH0 PORT C
USER RAM 4 KB
SERIAL COMMUNICATIONS INTERFACE (SCI1)
PTC3/TPM1CH1 PTC2/TPM1CH0 PTC1/TxD1 PTC0/RxD1
INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR
XTAL EXTAL
SERIAL COMMUNICATIONS INTERFACE (SCI2)
TxD2 RxD2
♦ ♦
VDDA VSSA VREFH VREFL VDD VSS VOLTAGE REGULATOR VREF1 VREF2
ADP[11:4]
ADP0 ADP12
• •
12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
ADP0 ADP12
• •
PORT D
PTD[7:0]/LCD[7:0]
PORT E
• ♦
VREFO1 VREFO2 VLCD VLL1 VLL2 VLL3 VCAP1 VCAP2
ANALOG COMPARATOR (ACMP)
ACMP– ACMP+ ACMPO
PTE[7:0]/LCD[13:20]
NOTES
LIQUID CRYSTAL DISPLAY (LCD)
• Pins are not available on 64-pin packages. LCD[8:12] and LCD[31:37] are ♦ VREFH and VREFL are internally connected to VDDA and VSSA for the 64-pin ∞ When PTB2 is configured as RESET, the pin becomes bi-directional with
package. VREFO2 is available only on the 64-pin package. output being an open-drain drive. not available on the 64-pin package.
LCD[43:0]
◊ When PTC6 is configured as BKGD, the pin becomes bi-directional. Figure 1. MC9S08LL64 Series Block Diagram
MC9S08LL64 Series MCU Data Sheet, Rev. 4 4 Freescale Semiconductor
2
Pin Assignments
This section shows the pin assignments for the This section shows the pin assignments for the MC9S08LL64 series devices.
PTE2/LCD15 PTE3/LCD16 PTE4/LCD17 PTE5/LCD18 PTE6/LCD19 PTE7/LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PTE1/LCD14 PTE0/LCD13 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64-Pin LQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Freescale Semiconductor
PTA6/KBIP6/ADP10/ACMP+ PTA7/KBIP7/ADP11/ACMP– VSSA/VREFL VDDA/VREFH PTB0/EXTAL PTB1/XTAL VDD VSS PTB2/RESET VREFO2 PTB4/MISO/SDA PTB5/MOSI/SCL PTB6/RxD2/SPSCK PTB7/TxD2/SS PTC0/RxD1 PTC1/TxD1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LCD38 LCD39 LCD40 LCD41 PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0
Figure 2. 64-Pin LQFP
MC9S08LL64 Series MCU Data Sheet, Rev. 4 5
PTA6/KBIP6/ADP10/ACMP+ PTA7/KBIP7/ADP11/ACMP– VSSA VREFL
Figure 3. 80-Pin LQFP Table 2. Pin Availability by Package Pin-Count
Highest Alt3 Alt4
MC9S08LL64 Series MCU Data Sheet, Rev. 4 6 Freescale Semiconductor
PTB0/EXTAL PTB1/XTAL VDD VSS PTB2/RESET PTB4/MISO/SDA PTB5/MOSI/SCL PTB6/RxD2/SPSCK PTB7/TxD2/SS PTC0/RxD1 PTC1/TxD1
ADP0 ADP12 VREFO1 VREFH VDDA
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PTE0/LCD13 LCD12 LCD11 LCD10 LCD9 LCD8 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PTE1/LCD14 PTE2/LCD15 PTE3/LCD16 PTE4/LCD17 PTE5/LCD18 PTE6/LCD19 PTE7/LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 LCD31 LCD32 LCD33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80-Pin LQFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
LCD34 LCD35 LCD36 LCD37 LCD38 LCD39 LCD40 LCD41 PTA5/KBIP5/ADP9/LCD42 PTA4/KBIP4/ADP8/LCD43 PTA3/KBIP3/SCL/MOSI/ADP7 PTA2/KBIP2/SDA/MISO/ADP6 PTA1/KBIP1/SPSCK/ADP5 PTA0/KBIP0/SS/ADP4 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0
Table 2. Pin Availability by Package Pin-Count (continued)
Highest Alt3 Alt4
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 7
Table 2. Pin Availability by Package Pin-Count (continued)
Highest Alt3 Alt4
MC9S08LL64 Series MCU Data Sheet, Rev. 4 8 Freescale Semiconductor
Introduction
3
3.1
Electrical Characteristics
Introduction
This section contains electrical and timing specifications for the MC9S08LL64 series of microcontrollers available at the time of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications P C
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
T D
NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 9
Thermal Characteristics
Table 4. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value –0.3 to +3.8 120 –0.3 to VDD + 0.3 ± 25 –55 to 150
Unit V mA V mA °C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 80-pin LQFP 64-pin LQFP Thermal resistance Four-layer board 80-pin LQFP 64-pin LQFP θJA 42 54 °C/W θJA 55 73 °C/W Symbol TA TJ Value TL to TH –40 to 85 95 Unit °C °C
The average chip-junction temperature (TJ) in °C can be obtained from:
MC9S08LL64 Series MCU Data Sheet, Rev. 4 10 Freescale Semiconductor
ESD Protection and Latch-Up Immunity
TJ = TA + (PD × θJA)
Eqn. 1
where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 1.8 V ILoad = –0.6 mA VDD > 2.7 V ILoad = –10 mA VDD > 1.8 V ILoad = –3 mA VDD > 1.8 V ILoad = –0.5 mA VDD > 2.7 V ILoad = –2.5 mA VDD > 1.8 V ILoad = –1 mA IOHT VDD >1.8 V ILoad = 0.6 mA VDD > 2.7 V ILoad = 10 mA VDD > 1.8 V ILoad = 3 mA Symbol Condition Min 1.8 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 — — Typ1 Max 3.6 — V Unit V
— —
— —
C 3 Output high P voltage C 4 D Output high current
—
— V
— — —
— — 100
mA
C 5 Output low P voltage C
—
—
0.5 V
— —
— —
0.5 0.5
MC9S08LL64 Series MCU Data Sheet, Rev. 4 12 Freescale Semiconductor
DC Characteristics
Table 8. DC Characteristics (continued)
Num C C 6 Output low P voltage C 7 8 9 10 D Output low current Characteristic PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength Max total IOL for all ports all digital inputs all digital inputs all digital inputs all input only pins (Per pin) VOL Symbol Condition VDD > 1.8 V ILoad = 0.5 mA VDD > 2.7 V ILoad = 3 mA VDD > 1.8 V ILoad = 1 mA IOLT VIH VIL Vhys |IIn| VIn = VDD or VSS VDD > 2.7 V VDD > 1.8 V VDD > 2.7 V VDD > 1.8 V Min — Typ1 — Max 0.5 V Unit
— — — 0.70 × VDD 0.85 × VDD — — 0.06 × VDD —
— — — — — — — —
0.5 0.5 100 — — 0.35 × VDD 0.30 × VDD —
mA
P Input high C voltage P Input low C voltage C Input hysteresis
V
mV μA
11
Input P leakage current Hi-Z (off-state) P leakage current Total P leakage current3 Pullup, P Pulldown resistors Pullup, P Pulldown resistors DC injection D current 4, 5,
6
0.025
1
12
all input/output (per pin)
|IOZ|
VIn = VDD or VSS
—
0.025
1
μA
13
Total leakage current for all pins all non-LCD pins when enabled LCD/GPIO pins when enabled Single pin limit Total MCU limit, includes sum of all stressed pins
|IInT| RPU, RPD RPU, RPD
VIn = VDD or VSS
—
—
3
μA
14
17.5
—
52.5
kΩ
15
35 –0.2
— — — — 0.6 1.4 — 1.84 1.92 2.14 80 1.17
77 0.2 5 8 1.0 2.0 — 1.88 1.96 2.2 — 1.18
kΩ mA mA pF V V μs V V mV V
16 17 18 19 20 21 22 23 24
IIC CIn VRAM VPOR tPOR VLVD VLVW Vhys VBG
VIN < VSS, VIN > VDD
–5 — — 0.9 10
C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage D POR re-arm time P Low-voltage detection threshold P Low-voltage warning threshold P Low-voltage inhibit reset/recover hysteresis
7
VDD falling VDD rising VDD falling VDD rising
1.80 1.88 2.08 — 1.15
P Bandgap Voltage Reference8
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 13
DC Characteristics
1 2 3 4 5 6
7 8
Typical values are measured at 25 °C. Characterized, not tested. All I/O pins except for LCD pins are in open drain mode. Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). POR will occur below the minimum voltage. Factory trimmed at VDD = 3.0 V, Temp = 25 °C
Figure 4. Non LCD pins I/O Pullup Typical Resistor Values
MC9S08LL64 Series MCU Data Sheet, Rev. 4 14 Freescale Semiconductor
DC Characteristics
Figure 5. Typical Low-Side Driver (Sink) Characteristics (Non LCD Pins) — Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 15
DC Characteristics
Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 16 Freescale Semiconductor
DC Characteristics
Figure 7. Typical High-Side (Source) Characteristics (Non LCD Pins)— Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 17
DC Characteristics
Figure 8. Typical High-Side (Source) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 18 Freescale Semiconductor
DC Characteristics
Figure 9. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 19
DC Characteristics
Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 20 Freescale Semiconductor
DC Characteristics
Figure 11. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 21
DC Characteristics
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 22 Freescale Semiconductor
Supply Current Characteristics
3.7
Supply Current Characteristics
Table 9. Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Bus Freq 20 MHz Run supply current FEI mode, all modules on Run supply current FEI mode, all modules off RIDD 10 MHz 1 MHz 20 MHz RIDD 10 MHz 1 MHz Run supply current LPS=0, all modules on Run supply current LPS=1, all modules off, running from Flash Run supply current LPS=1, all modules off, running from RAM Wait mode supply current FEI mode, all modules off 16 kHz FBILP 16 kHz FBELP 3 3 VDD (V) Temp (°C)
Num
C T
Parameter
Symbol
Typ1 13.75 7 2 8.9 5.5 0.9 185
Max 17.9 — — — — — —
Unit
1
T T T T T T
mA
–40 to 85
2
mA
–40 to 85
3 T T 4 T T 5 T T P C 6 P C C C P C 7 P C C C
1
RIDD
3 115 — — 25
μA
–-40 to 85
0 to 70 –40 to 85 μA 0 to 70 –40 to 85
RIDD
16 kHz FBELP
— —
3 7.3
— 6 — — 1.3 6 13 1 5 10 1.8 8 20 1.5 6.8 14 μA μA mA
20 MHz WIDD 8 MHz 1 MHz 3
4.57 2 0.73 0.4 3 4 8.5 0.35 2 3.9 7.7 0.65 3 5.7 12.2 0.6 2 5 11.5
–40 to 85
–40 to 25 70 85 –40 to 25 70 85 –40 to 25 70 85 –40 to 25 70 85
Stop2 mode supply current
S2IDD
n/a
Stop3 mode supply current No clocks active
S3IDD
n/a
Typical values are measured at 25 °C. Characterized, not tested
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 23
External Oscillator (XOSCVLP) Characteristics
Table 10. Stop Mode Adders
Temperature (°C) Num 1 2 3 4 5 6 7 C T T T T T T T Parameter LPO ERREFSTEN IREFSTEN TOD LVD1 ACMP ADC1
1 1
Condition –40 100 RANGE = HGO = 0 750 63 Does not include clock source current LVDSE = 1 Not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for driving 192 segments, 32 Hz frame rate, No LCD glass connected. 50 110 12 95 25 100 750 70 50 110 12 95 70 150 800 77 75 112 20 101 85 175 850 81 100 115 23 120
Units nA nA μA nA μA μA μA
8
T
LCD
1
1
6
13
μA
1
Not available in stop2 mode.
Figure 13. Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC and ACMP off, All Other Modules Enabled)
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 14 and Figure 15 for crystal or resonator circuits.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 24 Freescale Semiconductor
External Oscillator (XOSCVLP) Characteristics
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num C Characteristic Symbol Min Typ1 Max Unit
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings
flo fhi fhi C1,C2
32 1 1
— — —
38.4 16 8
kHz MHz MHz
2
D
See Note 2 See Note 3
3
Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, high gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high gain C High range, low power High range, high gain Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode D FBE or FBELP mode
RF
— — — — — — — — — — — — —
— 10 1 — 100 0 0 0 0 600 400 5 15
— — — — — — 0 10 20 — — — —
MΩ
4
RS
kΩ
t t
5
CSTL
ms
CSTH
6
1 2
fextal
0.03125 0
— —
20 20
MHz MHz
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 25
Internal Clock Source (ICS) Characteristics
XOSCVLP EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP EXTAL XTAL
Crystal or Resonator
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num 1 2 3 4 5
C
Characteristic
Symbol fint_ut fint_t fint_t tIRST
Min 25 31.25 — — 12.8
Typ1 32.7 — 32.7 60 16.8 33.6 — — ±0.1 ± 0.2
Max 41.66 39.06 — 100 21.33
Unit kHz kHz kHz μs MHz
C Average internal reference frequency — untrimmed P P T P Average internal reference frequency — user-trimmed Average internal reference frequency — factory-trimmed Internal reference start-up time Low range (DFR = 00) Mid range (DFR = 01) Low range (DFR = 00) Mid range (DFR = 01)
DCO output frequency C range — untrimmed P DCO output frequency range — trimmed
fdco_ut
25.6 16
42.67 20 MHz 40 ±0.2 ±0.4 %fdco %fdco
6 P 7 8 C C
fdco_t Δfdco_res_t Δfdco_res_t
32 — —
Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 26 Freescale Semiconductor
AC Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num 9 10 11 12
1 2
C C C
Characteristic Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 °C to 70 °C
Symbol Δfdco_t Δfdco_t tAcquire CJitter
Min — — — —
Typ1 + 0.5 –1.0 ± 0.5 — 0.02
Max ±2 ±1 1 0.2
Unit %fdco %fdco ms %fdco
C FLL acquisition time2 C Long term jitter of DCO output clock (averaged over 2 ms interval)3
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 27
AC Characteristics
3.10.1
Control Timing
Table 13. Control Timing
Num 1 2 3 4 5 6
C D D D D D D
Rating Bus frequency (tcyc = 1/fBus) VDD ≤ 2.1V VDD > 2.1V Internal low power oscillator period External reset pulse width2 Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
Symbol fBus tLPO textrst trstdrv tMSSU tMSH
Min dc dc 700 100 34 × tcyc 500 100
Typ1 — — — — — — —
Max 10 20 1300 — — — —
Unit MHz μs ns ns ns μs
7
D
tILIH, tIHIL
100 1.5 × tcyc 100 1.5 × tcyc
— — — —
— — — —
ns
8
D
tILIH, tIHIL
ns
tRise, tFall
— —
16 23
— —
ns
9
C
tRise, tFall
— —
5 9
— —
ns
1 2 3 4 5 6
Typical values are based on characterization data at VDD = 3.0 V, 25 °C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C. Except for LCD pins in open drain mode.
textrst RESET PIN
Figure 17. Reset Timing
MC9S08LL64 Series MCU Data Sheet, Rev. 4 28 Freescale Semiconductor
AC Characteristics
tIHIL IRQ/KBIPx
IRQ/KBIPx tILIH
Figure 18. IRQ/KBIPx Timing
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 14. TPM Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit Hz tcyc tcyc tcyc tcyc
tTCLK tclkh TCLK tclkl
Figure 19. Timer External Clock
tICPW TPMCHn
TPMCHn tICPW
Figure 20. Timer Input Capture Pulse
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 29
AC Characteristics
3.10.3
SPI Timing
Table 15. SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
No. — C D Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol fop Min fBus/2048 0 2 4 1/2 1 1/2 1 tcyc – 30 tcyc – 30 15 15 0 25 — — Max fBus/2 fBus/4 2048 — — — — — 1024 tcyc — — — — — 1 1 Unit Hz
1
D
tSPSCK
tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc
2
D
tLead
3
D
tLag
4
D
tWSPSCK
5
D
tSU
6 7 8 9
D
tHI
D D
ta tdis
D
tv
— — 0 0 — — — —
25 25 — — tcyc – 25 25 tcyc – 25 25
ns ns ns ns ns ns ns ns
10
D
tHO
11
D
tRI tRO tFI tFO
12
D
MC9S08LL64 Series MCU Data Sheet, Rev. 4 30 Freescale Semiconductor
AC Characteristics
SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 MS BIN2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3
NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
SS1 (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 4 4 11 12 12 11 3
5 MSB IN2
6 BIT 6 . . . 1 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 31
AC Characteristics
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT)
NOTE:
12
11
3
4
4
11
12 8
9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1
10
10
SEE NOTE 1
SLAVE LSB OUT
LSB IN
1. Not defined but normally MSB of character just received.
Figure 23. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 1 7 MOSI (INPUT) 2 12 3 11
4
4
11
12
9 SLAVE ‘c MSB IN MSB OUT 6
10 BIT 6 . . . 1 SLAVE LSB OUT
c
BIT 6 . . . 1
LSB IN
NOTE: 1. Not defined but normally LSB of character just received
Figure 24. SPI Slave Timing (CPHA = 1)
MC9S08LL64 Series MCU Data Sheet, Rev. 4 32 Freescale Semiconductor
Analog Comparator (ACMP) Electricals
3.11
No 1 2 3 4 5 6 7 C D P D P C P C
Analog Comparator (ACMP) Electricals
Table 16. Analog Comparator Electrical Specifications
Characteristic Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT Min 1.8 — VSS – 0.3 — 3.0 — — Typical — 20 — 20 9.0 — — Max 3.6 35 VDD 40 15.0 1.0 1.0 Unit V μA V mV mV μA μs
3.12
ADC Characteristics
Table 17. 12-Bit ADC Operating Conditions
No.
Characteristic
Conditions Absolute
Symb VDDA ΔVDDA
Min 1.8 –100
Typ1 — 0
Max 3.6 100
Unit V mV
1
Supply voltage
Delta to VDD (VDD – VDDA)2 Delta to VSS (VSS – VSSA)2 — — — 8/10/12-bit modes —
2 3 4 5 6 7
1
Ground voltage Reference voltage high Reference voltage low Input voltage Input capacitance Input resistance
ΔVSSA VREFH VREFL VADIN CADIN RADIN
–100 1.8 VSSA VREFL — —
0 VDDA VSSA — 4 5
100 VDDA VSSA VREFH 5 7
mV V V V pF kΩ
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 33
ADC Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ –
+ –
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 25. ADC Input Impedance Equivalency Diagram
MC9S08LL64 Series MCU Data Sheet, Rev. 4 34 Freescale Semiconductor
ADC Characteristics
Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
# Characteristic Conditions ADLPC = 1 ADHSC = 0 ADLSMP = 0 ADCO = 1 ADLPC = 1 ADHSC = 1 ADLSMP = 0 ADCO = 1 ADLPC = 0 ADHSC = 0 ADLSMP = 0 ADCO = 1 ADLPC = 0 ADHSC = 1 ADLSMP = 0 ADCO = 1 Stop, reset, module off High speed (ADLPC = 0) P Low power (ADLPC = 1) Single/first continuous ADLSMP = 0 7 Sample time ADHSC = 0 ADLSMP = 0 ADLSTS = XX ADHSC = 1 ADLSMP = 0 ADLSTS = XX Subsequent continuous ADLSMP = 0 8 Sample time ADHSC = 0 ADLSMP = 0 ADLSTS = XX ADHSC = 1 ADLSMP = 0 ADLSTS = XX C ts — 4 — ADCK C ts — 6 — ADCK fADACK 1.25 2 3.3 C Symb Min Typ1 Max Unit Comment
1
Supply current
T
IDDA
—
200
—
μA
2
Supply current
T
IDDA
—
280
—
μA
3
Supply current
T
IDDA
—
370
—
μA
4
Supply current
T
IDDA
—
0.61
—
mA
5
Supply current
IDDA
— 2
0.01 3.3
0.8 5
μA
6
ADC asynchronous clock source
MHz
tADACK = 1/fADACK
C
ts
—
10
—
C
ts
—
8
—
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 35
ADC Characteristics
Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
# Characteristic Conditions Subsequent Continuous or Single/First Continuous ADLSMP = 1 ADHSC = 0 ADLSMP = 1 ADLSTS = 00 ADHSC = 0 ADLSMP = 1 ADLSTS = 01 ADHSC = 0 ADLSMP = 1 ADLSTS = 10 9 Sample time ADHSC = 0 ADLSMP = 1 ADLSTS = 11 ADHSC = 1 ADLSMP = 1 ADLSTS = 00 ADHSC = 1 ADLSMP = 1 ADLSTS = 01 ADHSC = 1 ADLSMP = 1 ADLSTS = 10 ADHSC = 1 ADLSMP = 1 ADLSTS = 11 12-bit mode 3.6 > VDDA > 2.7V 10 Total unadjusted error 12-bit mode, 2.7 > VDDA > 1.8V 10-bit mode 8-bit mode 12-bit mode 11 Differential non-linearity 10-bit mode3 8-bit mode3 C ts — 24 — C Symb Min Typ1 Max Unit Comment
C
ts
—
16
—
C
ts
—
10
—
C
ts
—
6
—
C
ts
—
28
—
C
ts
—
20
—
C
ts
—
14
—
C
ts
—
10 –2.5 to 3.25 ±3.25
—
T T T T T T T DNL
—
±4 –5.5 to 6.5 ±2.5 ±1.0 –1.5 to 2.5 ±1.0 ±0.5 LSB2 Includes quantization
ETUE — — — — —
LSB2
±1 ±0.5 –1 to 1.75 ±0.5 ±0.3
MC9S08LL64 Series MCU Data Sheet, Rev. 4 36 Freescale Semiconductor
ADC Characteristics
Table 18. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
# Characteristic Conditions 12-bit mode 12 Integral non-linearity 10-bit mode 8-bit mode 12-bit mode 13 Zero-scale error 10-bit mode 8-bit mode 12-bit mode 14 Full-scale error 10-bit mode 8-bit mode 12-bit mode 15 Quantization error 10-bit mode 8-bit mode 12-bit mode 16 Input leakage error 10-bit mode 8-bit mode 17 Temp sensor slope Temp sensor voltage –40 °C– 25 °C 25 °C– 125 °C 25°C D m — D VTEMP25 — 1.769 701.2 — — mV D EIL D EQ C T T T T T T T T T EFS EZS INL Symb Min — — — — — — — — — — — — — — — — Typ1 –1.5 to 2.25 ±0.5 ±0.3 ±1 ±0.5 ±0.5 ±1.0 ±0.5 ±0.5 –1 to 0 — — ±2 ±0.2 ±0.1 1.646 Max ±2.75 ±1.0 ±0.5 –1.25 to 1 ±1 ±0.5 –3.5 to 2.25 ±1 ±0.5 — ±0.5 ±0.5 — ±4 ±1.2 — mV/°C LSB2 Pad leakage4 * RAS LSB2 LSB2 VADIN = VDDA LSB2 VADIN = VSSA LSB2 Unit Comment
18
1
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH – VREFL)/2N 3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes. 4 Based on input pad leakage current. Refer to pad electricals.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 37
VREF Specifications
3.13
Num 1 2 3
VREF Specifications
Table 19. VREF Electrical Specifications
Characteristic Symbol VDD Top — Typical — — — Min 1.80 –40 — Max 3.60 105 10 Unit V °C mA
Supply voltage Operating temperature range Maximum load
Operation across Temperature 4 5 6 V Room Temp Untrimmed –40 °C Trimmed –40 °C Untrimmed 0 °C 7 Trimmed 0 °C 8 9 10 11 12 13 14 15 16 Untrimmed 50 °C Trimmed 50 °C Untrimmed 85 °C Trimmed 85 °C Untrimmed 125 °C Trimmed 125 °C Load bandwidth Load regulation mode = 10 at 1mA load Line regulation (power supply rejection) AC — –60 dB Power Consumption 17 18 19 20 21 Powered down Current (Stop Mode, VREFEN = 0, VRSTEN = 0) Bandgap only (Mode[1:0] 00) Low-power buffer (Mode[1:0] 01) Tight-regulation buffer (Mode[1:0] 10) RESERVED (Mode[1:0] 11) I I I I — — — — — — — — — — — .100 75 125 1.1 — μA μA μA mA — Trimmed 0 °C Untrimmed 50 °C Trimmed 50 °C Untrimmed 85 °C Trimmed 85 °C Untrimmed 125 °C Trimmed 125 °C — Mode = 10 DC — — — — — — — — — — V Room Temp Untrimmed –40 °C Trimmed –40 °C Untrimmed 0 °C 1.15 — — — — — V mV mV mV mV mV mV mV mV mV mV — μV/mA mV
–2 to –6 from Room Temp Voltage ±1 from Room Temp Voltage +1 to –2 from Room Temp Voltage ±0.5 from Room Temp Voltage +1 to –2 from Room Temp Voltage ±0.5 from Room Temp Voltage 0 to –4 from Room Temp Voltage ±0.5 from Room Temp Voltage –2 to –6 from Room Temp Voltage ±1 from Room Temp Voltage — 20 — 100
±0.1 from Room Temp Voltage
MC9S08LL64 Series MCU Data Sheet, Rev. 4 38 Freescale Semiconductor
LCD Specifications
3.14
LCD Specifications
Table 20. LCD Electricals, 3-V Glass
No. 1 2 3 4 5 6 7 8 9 10 11
1 2
C D D D D D D D D D
Characteristic LCD supply voltage LCD frame frequency LCD charge pump capacitance LCD bypass capacitance LCD glass capacitance VIREG VIREG trim resolution VIREG ripple VLCD buffered adder2 HRefSel = 0 HRefSel = 1 HRefSel = 0 HRefSel = 1
Symbol VLCD fFrame CLCD CBYLCD Cglass VIREG ΔRTRIM — — IBuff
Min .9 28 — — — .89 1.49 1.5 — — —
Typ 1.5 30 100 100 2000 1.00 1.67 — — — 1
Max 1.8 58 100 100 8000 1.15 1.851 — .1 .15
Unit V Hz nF nF pF V % VIREG V μA
VIREG Max can not exceed VDD –.15 V VSUPPLY = 10, BYPASS = 0
3.15
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section.
Table 21. Flash Characteristics
No. 1 2 3 4 5 6 7 8 9 C D D D D P P P P D Characteristic Supply voltage for program/erase –40 °C to 85 °C Supply voltage for read operation Internal FCLK frequency1 location)2 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP — Min 1.8 1.8 150 5 Typical — — — — 9 4 4000 20,000 4 — Max 3.6 3.6 200 6.67 Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc mA
Internal FCLK period (1/FCLK) Byte program time (random Byte program time (burst Page erase time2
2
mode)2
Mass erase time Byte program
current3
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 39
EMC Performance
Table 21. Flash Characteristics (continued)
No. 10 11 12
1 2
C D C C
Characteristic Page erase current3 Program/erase endurance TL to TH = –40°C to 85°C T = 25°C Data retention5
4
Symbol RIDDPE —
Min — 10,000
Typical 6 — 100,000 100
Max — — — —
Unit mA cycles years
tD_ret
15
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
3.16
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
3.16.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East).
4
Ordering Information
Table 22. Device Numbering System
Device Number1 Flash MC9S08LL64 MC9S08LL36 64 KB 64 KB 36 KB Memory RAM 4000 4000 4000 80 LQFP 64 LQFP 64 LQFP Available Packages2
This appendix contains ordering information for the device numbering system MC9S08LL64 and MC9S08LL36 devices. See Table 1 for feature summary by package information.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 40 Freescale Semiconductor
Device Numbering System
1 2
See Table 1 for a complete description of modules included on each device. See Table 23 for package information.
4.1
Device Numbering System
MC 9 S08 LL 64 Status (MC = Fully qualified) Memory (9 = Flash-based) Core Family C XX
Example of the device numbering system:
Package designator (see Table 23) Temperature range (C = –40 °C to 85 °C) Approximate flash size in KB
4.2
Package Information
Table 23. Package Descriptions
Pin Count 80 64
Package Type Low Quad Flat Package Low Quad Flat Package
Abbreviation LQFP LQFP
Designator LK LH
Case No. 917A 840F
Document No. 98ASS23237W 98ASS23234W
4.3
Mechanical Drawings
Table 23 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08LL64 series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table 23, or • Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table 23) in the “Enter Keyword” search box at the top of the page.
MC9S08LL64 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 41
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M C9S08LL64
Rev. 4, 08/2009
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