Freescale Semiconductor Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08LL16 Rev. 6, 10/2010
MC9S08LL16 Series
Covers: MC9S08LL16 and MC9S08LL8
Features
• 8-Bit HCS08 Central Processor Unit (CPU) – Up to 20-MHz CPU at 3.6V to 1.8V across temperature range of -40°C to 85°C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources • On-Chip Memory – Dual Array FLASH read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and FLASH contents • Power-Saving Modes – Two low power stop modes – Reduced power wait mode – Low power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents. – Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter – 6 usec typical wake up time from stop3 mode • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1MHz to 10 MHz. • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock – Low-Voltage Warning with interrupt – Low-Voltage Detection with reset or interrupt – Illegal opcode and illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)
64-LQFP Case 840F
48-LQFP Case 932
48-QFN 1314
– On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints • Peripherals – LCD — 4x28 or 8x24 LCD driver with internal charge pump and option to provide an internally regulated LCD reference that can be trimmed for contrast control. – ADC — 8-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V – ACMP — Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 – SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge – SPI— Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting – IIC — IIC with up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing – TPMx — Two 2-channel (TPM1 and TPM2); Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; – TOD— (Time Of Day) 8-bit quarter second counter with match register; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components. • Input/Output – 38 GPIOs, 2 output-only pins – 8 KBI interrupts with selectable polarity – Hysteresis and configurable pull up device on all input pins; Configurable slew rate and drive strength on all output pins. • Package Options – 64-LQFP, 48-LQFP and 48-QFN
Table of Contents
1 2 3 Devices in the MC9S08LL16 Series . . . . . . . . . . . . . . 4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9 3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . 10 3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 11 3.5 ESD Protection and Latch-Up Immunity . . . . . . 12 3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 13 3.7 Supply Current Characteristics . . . . . . . . . . . . . 25 3.8 External Oscillator (XOSCVLP) Characteristics 27 3.9 Internal Clock Source (ICS) Characteristics . . . 28 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . .30 3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . . .30 3.10.2TPM Module Timing . . . . . . . . . . . . . . . . .31 3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .32 3.11 Analog Comparator (ACMP) Electricals . . . . . . .35 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .35 3.13 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . .39 3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .39 3.15 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .40 3.15.1Radiated Emissions . . . . . . . . . . . . . . . . .40 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.1 Device Numbering System . . . . . . . . . . . . . . . . .41
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev Date Description of Changes
1 2 3
9/2008 10/2008 01/2009
Initial Release. Updated electrical characteristics. Corrected 48-Pin QFN/LQFP pinouts for pins 29, 30, 32, and 32 in Figure 3. Extracted Stop Mode Adders from the Supply Current table and created a Separate table for the data (See Table 10). Added missing power consumption parameters in Supply Current Characteristics (Table 9). Completed all the TBDs. Changed VDDAD to VDDA, VSSAD to VSSA, IDDAD to IDDA. Corrected the data in the Table 8, and added |IInT|. Completed the Figure in the
4
07/21/2009
Section 3.6, “DC Characteristics.”
Corrected RIDD in FEI mode with all modules on, WIDD at 8 MHz, FEI mode with all modules off, S2IDD, S3IDD; added ApS3IDD in the Table 9. Corrected ETUE, DNL, INL, EZS, EFS, EQ, and EIL in the Table 18. 5 6 10/13/2009 10/27/2010 Updated RPU/RPD data in the Table 8. Added Figure 5. Changed the Max. of RPU/RPD at PTA[4:5], PTD[0:77] and PTE[0:7] to 69.5 kin the Table 8.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 2 Freescale Semiconductor
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08LL16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 3
Devices in the MC9S08LL16 Series
1
Devices in the MC9S08LL16 Series
Table 1. MC9S08LL16 Series Features by MCU and Package
Feature Package MC9S08LL16 64-pin LQFP 48-pin QFN/LQFP MC9S08LL8 48-pin QFN/LQFP 10,240 (8K and 2K arrays) 2080 yes 8-ch yes yes 8 yes yes 2-ch Yes 8x16 4x20 31
t
Table 1 summarizes the feature set available in the MC9S08LL16 series of MCUs.
FLASH RAM ACMP ADC IIC IRQ KBI SCI SPI TPM1 TPM2 TOD LCD I/O pins1
1
16,384 (Dual 8K Arrays) 2080 yes 8-ch yes yes 8 yes yes 2-ch 2-ch Yes 8x24 4x28 38 2080 yes 8-ch yes yes 8 yes yes 2-ch Yes 8x16 4x20 31
I/O does not include two output-only port pins.
The block diagram in Figure 1 shows the structure of the MC9S08LL16 series MCU.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 4 Freescale Semiconductor
Devices in the MC9S08LL16 Series
HCS08 CORE CPU INT
ON-CHIP ICE DEBUG MODULE (DBG) PORT A
PTA0/KBIP0/SS/ADP0 PTA1/KBIP1/SPSCK/ADP1 PTA2/KBIP2/SDA/MISO/ADP2 PTA3/KBIP3/SCL/MOSI/ADP3 PTA4/KBIP4/ADP4/LCD30 PTA5/KBIP5/ADP5/LCD31 PTA6/KBIP6/ADP6/ACMP+ PTA7/KBIP7/ADP7/ACMP–
SS SPSCK MISO
MOSI
BKGD
BKP
TIME OF DAY MODULE (TOD) KBI[7:0]
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT
8-BIT KEYBOARD INTERRUPT (KBI) BKGD/MS SERIAL PERIPHERAL INTERFACE (SPI)
COP IRQ LVD
RESET IRQ
PTB7/SS PTB6/SPSCK
SCL PORT B IIC MODULE (IIC) SDA TPM2CH0 PTB5/MOSI/SCL PTB4/MISO/SDA PTB3 PTB2/RESET PTB1/XTAL PTB0/EXTAL
USER FLASH A (LL16 = 8K BYTES) (LL8 = 8K BYTES)
2-CHANNEL TIMER/PWM (TPM2)
TPM2CH1 TCLK TPM1CH0
USER FLASH B (LL16 = 8K BYTES) (LL8 = 2K BYTES)
2-CHANNEL TIMER/PWM (TPM1)
TPM1CH1 TCLK
USER RAM (LL16 = 2K BYTES) (LL8 = 2K BYTES) INTERNAL CLOCK Source (ICS) LOW-POWER OSCILLATOR VLCD VLL1 VLL2 VLL3 VCAP1 VCAP2 LCD[31:0] LIQUID CRYSTAL DISPLAY DRIVER LCD XTAL
SERIAL COMMUNICATIONS INTERFACE (SCI)
TxD
RxD PORT C
PTC7/IRQ/TCLK PTC6/ACMPO//BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0
PTC3/TPM1CH1 PTC2/TPM1CH0 PTC1/TxD
EXTAL
PTC0/RxD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
PORT D
AD[7:0]
PTD[7:0]/LCD[7:0]
ANALOG COMPARATOR (ACMP)
ACMP–
ACMP+ ACMPO PORT E PTE[7:0]/LCD[15:8]
VDD VSS
VOLTAGE REGULATOR
KEY:
Pins not available on 48-pin packages. LCD[23:16] not available on 48-pin packages.
VDDA/VREFH VSSA/VREFL
Notes: When PTB2 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device. When PTC6 is configured as BKGD, pin becomes bi-directional.
Figure 1. MC9S08LL16 Series Block Diagram
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 5
Pin Assignments
2
Pin Assignments
This section shows the pin assignments for the MC9S08LL16 series devices.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PTE2/LCD10 PTE3/LCD11 PTE4/LCD12 PTE5/LCD13 PTE6/LCD14 PTE7/LCD15 LCD16 LCD17 LCD18 LCD19 LCD20 LCD21 LCD22 LCD23 LCD24 LCD25
Note: VREFH/VREFL are internally connected to VDDA/VSSA.
Figure 2. MC9S08LL16 Series in 64-pin LQFP Package
MC9S08LL16 Series MCU Data Sheet, Rev. 6 6 Freescale Semiconductor
PTA6/KBIP6/ADP6/ACMP+ PTA7/KBIP7/ADP7/ACMP– VSSA/VREFL VDDA/VREFH PTB0/EXTAL PTB1/XTAL VDD VSS PTB2/RESET PTB3 PTB4/MISO/SDA PTB5/MOSI/SCL PTB6/SPSCK PTB7/SS PTC0/RxD PTC1/TxD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PTE1/LCD9 PTE0/LCD8 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64-Pin LQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LCD26 LCD27 LCD28 LCD29 PTA5/KBIP5/ADP5/LCD30 PTA4/KBIP4/ADP4/LCD31 PTA3/KBIP3/SCL/MOSI/ADP3 PTA2/KBIP2/SDA/MISO/ADP2 PTA1/KBIP1/SPSCK/ADP1 PTA0/KBIP0/SS/ADP0 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0
Pin Assignments
PTE5/LCD13
PTE6/LCD14
PTE2/LCD10
PTE3/LCD11
PTE0/LCD8
PTE1/LCD9
PTE7/LCD15
PTE4/LCD12
LCD24
LCD26 38
48 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4/ PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 12 14 13 PTA7/KBIP7/ADP7/ACMP– PTA6/KBIP6/ADP6/ACMP+ PTB0/EXTAL VDDA/VREFH PTB2/RESET VLL3 15 16 VSSA/VREFL 17 18 19 PTB1/XTAL 20 VDD 21 VSS 22 23 1 2 3 4 5 6 7 8 9 10 11 47 46 45 44 43 42 41 40 39
37 36 LCD28 35 34 33 32 LCD29 PTA5/KBIP5/ADP5/LCD30 PTA4/KBIP4/ADP4/LCD31 PTA3/KBIP3/SCL/MOSI/ADP3 PTA2/KBIP2/SDA/MISO/ADP2 PTA1/KBIP1/SPSCK/ADP1 PTA0/KBIP0/SS/ADP0 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC3/TPM1CH1 25 PTC2/TPM1CH0 24
LCD27 31 30 29 28 27 26
48-Pin QFN/LQFP
LCD25
Note: VREFH/VREFL are internally connected to VDDA/VSSA
Figure 3. MC9S08LL16 Series in 48-Pin QFN/LQFP Packages
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 7
PTC0/RxD
PTC1/TxD
Pin Assignments
Table 2. Pin Availability by Package Pin-Count
Highest Alt3 Alt4
48
47 48 1 2 3 4 5 6 7 8 9 10 11 12 13 — 14 15 16 PTA6 PTA7 PTE1 PTE0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Port Pin
LCD9 LCD8 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 Vcap1 Vcap2 VLL1 VLL2 VLL3 VLCD KBIP6 KBIP7
Alt 1
ADP6 ADP7
ACMP+ ACMP– VSSA VREFL VREFH VDDA
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
17
18
19 20 21 22 — — — — — 23 24 25 26 — — 27 28 29
PTB0 PTB1
EXTAL XTAL VDD VSS
PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTA0
RESET
— — — —
MISO MOSI SPSCK SS RxD TxD TPM1CH0 TPM1CH1 TPM2CH0 TPM2CH1
SDA SCL
ACMPO
BKGD IRQ
MS TCLK SS ADP0
KBIP0
—
MC9S08LL16 Series MCU Data Sheet, Rev. 6 8 Freescale Semiconductor
Electrical Characteristics
Table 2. Pin Availability by Package Pin-Count (continued)
Highest Alt3
SPSCK MISO MOSI LCD31 LCD30 ADP1 ADP2 ADP3
48
30 31 32 33 34 35 36 37 38 39 40 — — — — PTA1 PTA2 PTA3 PTA4 PTA5
Port Pin
KBIP1 KBIP2 KBIP3 KBIP4 KBIP5 LCD29 LCD28 LCD27 LCD26 LCD25 LCD24 LCD23 LCD22 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10
Alt 1
— SDA SCL ADP4 ADP5
Alt4
3
3.1
Electrical Characteristics
Introduction
This section contains electrical and timing specifications for the MC9S08LL16 series of microcontrollers available at the time of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 9
Electrical Characteristics
Table 3. Parameter Classifications P C
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
T D
NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 4. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value –0.3 to 3.8 120 –0.3 to VDD + 0.3 25 –55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTB2 are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
MC9S08LL16 Series MCU Data Sheet, Rev. 6 10 Freescale Semiconductor
Electrical Characteristics
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 64-pin LQFP 48-pin QFN 48-pin LQFP Thermal resistance Four-layer board 64-pin LQFP 48-pin QFN 48-pin LQFP JA 54 30 57 C/W JA 72 84 81 C/W Symbol TA TJM Value TL to TH –40 to 85 95 Unit C C
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA) Eqn. 3-1
where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint PI/O Pint = IDD VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K (TJ + 273C) Eqn. 3-2
Solving Equation 3-1 and Equation 3-2 for K gives:
K = PD (TA + 273C) + JA (PD)2 Eqn. 3-3
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 11
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 3-1 and Equation 3-2 iteratively for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions Model Description Symbol
R1 C — R1 C —
Value
1500 100 3 0 200 3 –2.5 7.5
Unit
Series resistance Human Body Model Storage capacitance Number of pulses per pin Charge Device Model Series resistance Storage capacitance Number of pulses per pin Minimum input voltage limit Latch-up Maximum input voltage limit
pF
pF
V V
Table 7. ESD and Latch-Up Protection Characteristics No.
1 2 3
1
Rating1
Human body model (HBM) Charge device model (CDM) Latch-up current at TA = 85C
Symbol
VHBM VCDM ILAT
Min
2000 500 100
Max
— — —
Unit
V V mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 12 Freescale Semiconductor
Electrical Characteristics
3.6
DC Characteristics
Table 8. DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Num C 1 C 2 Output high P voltage C Characteristic Operating voltage PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7]2, low-drive strength PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7]2, high-drive strength PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength Max total IOH for all ports PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7], low-drive strength PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7], high-drive strength PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength Max total IOL for all ports all digital inputs all digital inputs all digital inputs all input only pins (per pin) VOL VOL VOH VOH VDD >1.8 V ILoad = –0.6 mA VDD > 2.7 V ILoad = –10 mA VDD > 1.8 V ILoad = –3 mA VDD > 1.8 V ILoad = –0.5 mA VDD > 2.7 V ILoad = –3 mA VDD > 1.8 V ILoad = –1 mA IOHT VDD >1.8 V ILoad = 0.6 mA VDD > 2.7 V ILoad = 10 mA VDD > 1.8 V ILoad = 3 mA VDD > 1.8 V ILoad = 0.5 mA VDD > 2.7 V ILoad = 3 mA VDD > 1.8 V ILoad = 1 mA IOLT VIH VIL Vhys |IIn| VIn = VDD or VSS VDD 2.7 V VDD 1.8 V VDD 2.7 V VDD 1.8 V Symbol Condition Min 1.8 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 VDD – 0.5 — — Typ1 Max 3.6 — V Unit V
— —
— —
C 3 Output high P voltage C 4 D Output high current
—
— V
— — —
— — 100
mA
C 5 Output low P voltage C
—
—
0.5 V
— —
— —
0.5 0.5
C 6 Output low P voltage C 7 8 9 10 11 D Output low current
—
—
0.5 V
— — — 0.70 VDD 0.85 VDD — — 0.06 VDD —
— — — — — — — — 0.025
0.5 0.5 100 — — 0.35 x VDD 0.30 x VDD — 1
mA
P Input high C voltage P Input low C voltage C P Input hysteresis Input leakage current
V
mV A
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 13
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C 12 Characteristic all input/output (per pin) Total leakage current for all pins PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7] PTA[4:5], PTD[0:7], PTE[0:7] Single pin limit Total MCU limit, includes sum of all stressed pins IIC CIn VRAM VPOR tPOR VLVD VLVW Vhys VBG VDD falling VDD rising VDD falling VDD rising VIN < VSS, VIN > VDD Symbol |IOZ| |IInT| Condition VIn = VDD or VSS VIn = VDD or VSS Min — Typ1 0.025 — Max 1 Unit A A
Hi-Z (off-state) P leakage current P Total leakage current3
13
—
2 52.5
14
P Pullup, pulldown resistors when P enabled D DC injection current 4, 5, 6
RPU, RPD
—
17.5
— 69.5
k
–0.2 –5 — — 0.9 10 1.80 1.88 2.08 — 1.15
— — — 0.6 1.4 — 1.84 1.92 2.14 80 1.17
0.2 5 8 1.0 2.0 — 1.88 1.96 2.2 — 1.18
mA mA pF V V s V V mV V
15 16 17 18 19 20 21 22 23
1 2 3 4 5 6
C Input capacitance, all pins C RAM retention voltage C POR re-arm voltage D POR re-arm time P Low-voltage detection threshold P Low-voltage warning threshold P Low-voltage inhibit reset/recover hysteresis P Bandgap voltage reference
8 7
7 8
Typical values are measured at 25 C. Characterized, not tested All I/O pins except for LCD pins in open drain mode. Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). POR will occur below the minimum voltage. Factory trimmed at VDD = 3.0 V, Temp = 25 C.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 14 Freescale Semiconductor
Electrical Characteristics
Figure 4. Non-LCD pins I/O Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 15
Electrical Characteristics
Figure 5. LCD/GPIO Pins I/O Pullup/Pulldown Typical Resistor Values
MC9S08LL16 Series MCU Data Sheet, Rev. 6 16 Freescale Semiconductor
Electrical Characteristics
Figure 6. Typical Low-Side Driver (Sink) Characteristics (Non-LCD pins) — Low Drive (PTxDSn = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 17
Electrical Characteristics
Figure 7. Typical Low-Side Driver (Sink) Characteristics(Non-LCD pins) — High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 18 Freescale Semiconductor
Electrical Characteristics
Figure 8. Typical High-Side (Source) Characteristics (Non-LCD Pins) — Low Drive (PTxDSn = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 19
Electrical Characteristics
Figure 9. Typical High-Side (Source) Characteristics(Non-LCD Pins) — High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 20 Freescale Semiconductor
Electrical Characteristics
Preliminary
IOL (mA)
Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — Low Drive (PTxDSn = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 21
Electrical Characteristics
Figure 11. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO Pins) — High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 22 Freescale Semiconductor
Electrical Characteristics
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — Low Drive (PTxDSn = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 23
Electrical Characteristics
Figure 13. Typical High-Side (Source) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 24 Freescale Semiconductor
Electrical Characteristics
3.7
Supply Current Characteristics
Table 9. Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Parameter Run supply current FEI mode, all modules on Run supply current FEI mode, all modules off Bus Freq 8 MHz 1 MHz 10 MHz 1 MHz 16 kHz FBILP 16 kHz FBELP 16 kHz FBILP 16 kHz FBELP 16 kHz FBILP 16 kHz FBELP 8 MHz 1 MHz 16 kHz FBELP 3 3 VDD (V) Temp (C) –40 to 85 C –40 to 85 C
Num 1
C P T T T T
Symbol RIDD RIDD
Typ1 4.2 1 3.60 0.50 165
Max 5.7 1.52 — — —
Unit mA
2
mA
3 T T 4 T T 5 T 6 7 P C T
Run supply current LPRS=0, all modules off
RIDD
3 105 77 3 21 77 3 7.3 3 3 1.4 0.8 1.3 350 — 3.5 1.15 — 930 — 4000 — — — — 1030 — 6000 — — — — — — — —
A
–40 to 85 C
Run supply current LPRS=1, all modules off; running from Flash
RIDD
A
–40 to 85 C
Run supply current LPRS=1, all modules off; running from RAM Wait mode supply current FEI mode, all modules off Wait mode supply current LPRS = 1, all modules off
RIDD
A
–40 to 85 C
WIDD WIDD
mA A
–40 to 85 C –40 to 85 C –40 to 25 C 50 C 70 C 85 C –40 to 25 C 70 C 85 C –40 to 25 C 50 C 70 C 85 C –40 to 25 C 70 C 85 C
P 8 Stop2 mode supply current S2IDD
n/a
3
1000 2500 5100 250
nA
C
n/a
2
2000 4000 400
P 9 Stop3 mode supply current No clocks active C S3IDD
n/a
3
1300 4000 8000 350
nA
n/a
2
3000 6000
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 25
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
Num 10 11
1 2
C C C
Parameter Application Stop3 mode supply current2 Application Stop3 mode supply current2
Symbol ApS3IDD ApS3IDD
Bus Freq n/a n/a
VDD (V) 3 3
Typ1 6.1 7.5
Max — —
Unit A A
Temp (C) 25 C 50 C
Typical values are measured at 25 C. Characterized, not tested. 32 kHz crystal enabled in low power mode. TOD module enabled. VIREG enabled for 3 V LCD glass 500pf 8x24 LCD glass at 32 Hz frame rate with LCD Charge pump clock set to low setting and every other segment “on.”
Table 10. Stop Mode Adders
Temperature (C) Num 1 2 3 4 5 6 7 C T T T T T T T LPO ERREFSTEN IREFSTEN1 TOD LVD1 ACMP1 ADC1 Does not include clock source current LVDSE = 1 Not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for driving 192 Segments, 32Hz frame rate, No LCD glass connected. RANGE = HGO = 0 Parameter Condition –40 100 250 63 50 110 12 95 25 100 360 70 50 110 12 95 70 150 400 77 75 112 20 101 85 175 460 81 100 115 23 120 nA nA A nA A A A Units
8
T
LCD
1
1
4.2
12
A
1
Not available in stop2 mode.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 26 Freescale Semiconductor
Electrical Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Refer to Figure 14 and Figure 15 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85 C Ambient)
Num C Characteristic Symbol Min Typ1 Max Unit
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) Load capacitors Low range (RANGE=0), low power (HGO=0) D Other oscillator settings Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, high gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high gain C High range, low power High range, high gain Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode D FBE or FBELP mode
flo fhi fhi
32 1 1
— — —
38.4 16 8
kHz MHz MHz
2
C1,C2
See Note 2 See Note 3
3
RF
— — — — — — — — — — — — —
— 10 1 — 100 0 0 0 0 600 400 5 15
— — — — — — 0 10 20 — — — —
M
4
RS
k
t t
5
CSTL
ms
CSTH
6
1 2
fextal
0.03125 0
— —
20 20
MHz MHz
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 27
Electrical Characteristics
XOSCVLP EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP EXTAL XTAL
Crystal or Resonator
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient)
Num 1 2 3 4 5 6 7 8
C P P T P P C C C
Characteristic Average internal reference frequency — factory trimmed at VDD = 3.6 V and temperature = 25 C Average internal reference frequency - trimmed Internal reference start-up time DCO output frequency range - untrimmed DCO output frequency range - trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Total deviation from trimmed DCO output frequency over voltage and temperature
Symbol fint_ft fint_t tIRST fdco_ut fdco_t fdco_res_t fdco_res_t fdco_t
Min — 31.25 — 12.8 16 — — —
Typ1 32.768 — — 16.8 — 0.1 0.2 + 0.5 –1.0
Max — 39.063 6 21.33 20 0.2 0.4 2
Unit kHz kHz s MHz MHz %fdco %fdco %fdco
MC9S08LL16 Series MCU Data Sheet, Rev. 6 28 Freescale Semiconductor
Electrical Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued)
Num 9 10 11
1 2
C C
Characteristic Total deviation from trimmed DCO output frequency over fixed voltage and temperature range of 0C to 70 C
Symbol fdco_t tAcquire CJitter
Min — — —
Typ1 0.5 — 0.02
Max 1 1 0.2
Unit %fdco ms %fdco
C FLL acquisition time 2 C Long term jitter of DCO output clock (averaged over 2-ms interval) 3
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter percentage for a given interval.
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 29
Electrical Characteristics
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Control Timing
Table 13. Control Timing
Num 1 2 3 4 5 6
C D D D D D D
Rating Bus frequency (tcyc = 1/fBus) Internal low power oscillator period External reset pulse width2 Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time — Non-LCD Pins Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
Symbol fBus tLPO textrst trstdrv tMSSU tMSH
Min dc 700 100 34 tcyc 500 100
Typ1 — — — — — —
Max 10 1300 — — — —
Unit MHz s ns ns ns s
7
D
tILIH, tIHIL
100 1.5 tcyc 100 1.5 tcyc
— — — —
— — — —
ns
D 8
tILIH, tIHIL
ns
tRise, tFall
— —
16 23
— —
ns
9
C
Port rise and fall time — Non-LCD Pins High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
C
tRise, tFall
— — —
5 9 6
— — 10
ns
10
1 2 3 4 5 6
Voltage Regulator Recovery time
tVRR
us
Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 85 C. Except for LCD pins in Open Drain mode.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 30 Freescale Semiconductor
Electrical Characteristics
textrst RESET PIN
Figure 17. Reset Timing
tIHIL IRQ/KBIPx
IRQ/KBIPx tILIH
Figure 18. IRQ/KBIPx Timing
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 14. TP Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit Hz tcyc tcyc tcyc tcyc
tTCLK tclkh TCLK tclkl
Figure 19. Timer External Clock
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 31
Electrical Characteristics
tICPW TPMCHn
TPMCHn tICPW
Figure 20. Timer Input Capture Pulse
3.10.3
SPI Timing
Table 15. SPI Timing
No. — D C Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Symbol fop Min fBus/2048 0 2 4 12 1 12 1 tcyc –30 tcyc – 30 15 15 0 25 — — Max fBus/2 fBus/4 2048 — — — — — 1024 tcyc — — — — — 1 1 Unit Hz
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
1
D
tSPSCK
tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc
2
D
tLead
3
D
tLag
4
D
tWSPSCK
5
D
tSU
6
D
tHI
7 8 9
D D
ta tdis
D
tv
— —
25 25
ns ns
MC9S08LL16 Series MCU Data Sheet, Rev. 6 32 Freescale Semiconductor
Electrical Characteristics
Table 15. SPI Timing (continued)
No. C D Function Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol tHO Min 0 0 — — — — Max — — tcyc – 25 25 tcyc – 25 25 Unit ns ns ns ns ns ns
10
11
D
tRI tRO tFI tFO
12
D
SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 MS BIN2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3
NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 33
Electrical Characteristics
SS1 (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 4 4 11 12 12 11 3
5 MSB IN2
6 BIT 6 . . . 1 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT)
NOTE:
12
11
3
4
4
11
12 8
9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1
10
10
SEE NOTE 1
SLAVE LSB OUT
LSB IN
1. Not defined but normally MSB of character just received.
Figure 23. SPI Slave Timing (CPHA = 0)
MC9S08LL16 Series MCU Data Sheet, Rev. 6 34 Freescale Semiconductor
Electrical Characteristics
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 1 7 MOSI (INPUT) 2 12 3 11
4
4
11
12
9 SLAVE 5 MSB IN MSB OUT 6
10 BIT 6 . . . 1 SLAVE LSB OUT
8
BIT 6 . . . 1
LSB IN
NOTE: 1. Not defined but normally LSB of character just received.
Figure 24. SPI Slave Timing (CPHA = 1)
3.11
C D C D P C P C
Analog Comparator (ACMP) Electricals
Table 16. Analog Comparator Electrical Specifications
Characteristic Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT 3.0 — — Min 1.8 — VSS – 0.3 Typical — 20 — 20 9.0 — — Max 3.6 35 VDD 40 15.0 1.0 1.0 Unit V A V mV mV A s
Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay
3.12
ADC Characteristics
Table 17. 12-bit ADC Operating Conditions
Conditions Absolute Symb VDDA VDDA VSSA Min 1.8 –100 –100 Typ1 — 0 0 Max 3.6 100 100 Unit V mV mV Comment
Characteristic Supply voltage Ground voltage
Delta to VDD (VDD–VDDA)2 Delta to VSS (VSS–VSSA)2
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 35
Electrical Characteristics
Table 17. 12-bit ADC Operating Conditions
Characteristic Ref Voltage High Input Voltage Input Capacitance Input Resistance 12-bit mode fADCK > 4MHz fADCK < 4MHz Analog Source Resistance 10-bit mode fADCK > 4MHz fADCK < 4MHz 8-bit mode (all valid fADCK) ADC Conversion Clock Freq.
1
Conditions
Symb VREFH VADIN CADIN RADIN
Min 1.8 VREFL — —
Typ1 VDDA — 4.5 5
Max VDDA VREFH 5.5 7
Unit V V pF k
Comment
— — RAS — — — 0.4 fADCK 0.4
— — — — — — —
2 5 k 5 10 10 8.0 MHz 4.0 External to MCU
High speed (ADLPC = 0) Low power (ADLPC = 1)
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ –
+ –
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 25. ADC Input Impedance Equivalency Diagram
MC9S08LL16 Series MCU Data Sheet, Rev. 6 36 Freescale Semiconductor
Electrical Characteristics
Table 18. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
C Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 ADC Asynchronous Clock Source Conversion Time (Including sample time) High Speed (ADLPC=0) Low Power (ADLPC=1) Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Short Sample (ADLSMP=0) Sample Time C T Total Unadjusted Error P T T P T T P T Integral Non-Linearity Differential Non-Linearity Long Sample (ADLSMP=1) 12-bit mode, 3.6>VDDA>2.7V 12-bit mode, 2.7>VDDA>1.8V 10-bit mode 8-bit mode 12-bit mode 10-bit mode3 8-bit mode3 12-bit mode 10-bit mode 8-bit mode INL DNL ETUE tADS tADC fADACK Conditions Symb Min Typ1 Max Unit Comment
T
IDDA
—
120
—
A
T
IDDA
—
200
—
A
T
IDDA
—
290
—
A
P
IDDA
—
0.53
1
mA
P C P C P
2 1.25 — — — — — — — — — — — — — —
3.3 2 20 40 3.5 23.5 –1 to 3 –1 to 3 1 0.5 1 0.5 0.3 1.5 0.5 0.3
5 MHz 3.3 — — — — –2.5 to 5.5 –3.0 to 6.0 2.5 1.0 –1.5 to 2.0 1.0 0.5 –2.5 to 1.0 1.0 0.5 LSB2 LSB2 LSB2 ADCK cycles
tADACK = 1/fADACK See ADC chapter in the LL16 Reference Manual for conversion time variances
ADCK cycles
Includes quantization
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 37
Electrical Characteristics
Table 18. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
C T P T T P T Full-Scale Error Zero-Scale Error Characteristic Conditions 12-bit mode 10-bit mode 8-bit mode 12-bit mode 10-bit mode 8-bit mode 12-bit mode D Quantization Error 10-bit mode 8-bit mode 12-bit mode D Input Leakage Error 10-bit mode 8-bit mode D Temp Sensor Slope Temp Sensor Voltage –40 C to 25 C 25 C to 85 C 25 C m — VTEMP25 — 1.769 701.2 — — mV EIL EQ EFS EZS Symb Min — — — — — — — — — — — — — Typ1 1.5 0.5 0.5 1 0.5 0.5 –1 to 0 — — 2 0.2 0.1 1.646 Max 2.5 1.5 0.5 –3.5 to 1.0 1 0.5 — 0.5 0.5 — 4 1.2 — mV/C LSB2 Pad leakage4 * RAS LSB2 LSB2 VADIN = VDDA LSB2 VADIN = VSSA Unit Comment
D
1
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH – VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 38 Freescale Semiconductor
Electrical Characteristics
3.13
LCD Specifications
Table 19. LCD Electricals, 3 V Glass
C D D D D D D D D D
1 2
Characteristic LCD Supply Voltage LCD Frame Frequency LCD Charge Pump Capacitance LCD Bypass Capacitance LCD Glass Capacitance VIREG VIREG TRIM Resolution VIREG Ripple VLCD Buffered Adder2 HRefSel = 0 HRefSel = 1 HRefSel = 0 HRefSel = 1
Symbol VLCD fFrame CLCD CBYLCD Cglass VIREG RTRIM
Min 0.9 28
Typ 1.5 30 100 100 2000
Max 1.8 58 100 100 8000 1.15 1.851
Unit V Hz nF nF pF V % VIREG
.89 1.49 1.5
1.00 1.67
0.1 0.15 IBuff 1
V A
VIREG Max can not exceed VDD – 0.15 V VSUPPLY = 10, BYPASS = 0
3.14
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 39
Electrical Characteristics
Table 20. Flash Characteristics
C D D D D P P P P D D C C
1 2
Characteristic Supply voltage for program/erase -40C to 85C Supply voltage for read operation Internal FCLK frequency
1
Symbol Vprog/erase VRead fFCLK tFcyc
2
Min 1.8 1.8 150 5
Typical
Max 3.6 3.6 200 6.67
Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
Internal FCLK period (1/FCLK) Byte program time (random location) Byte program time (burst mode) Page erase time
2 2 3 2
tprog tBurst tPage tMass RIDDBP RIDDPE — — 10,000 tD_ret 15
9 4 4000 20,000 4 6 — 100,000 100 — — — — —
Mass erase time
Byte program current Page erase current3
mA mA cycles years
Program/erase TL to TH = –40C to + 85C T = 25C Data retention5
endurance4
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
3.15
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
3.15.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East).
MC9S08LL16 Series MCU Data Sheet, Rev. 6 40 Freescale Semiconductor
Ordering Information
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels.
Table 21. Radiated Emissions, Electric Field
Parameter Symbol VRE_TEM Conditions VDD = 3.3 V TA = 25 oC package type 64-pin LQFP Frequency 0.15 – 50 MHz 50 – 150 MHz 150 – 500 MHz 500 – 1000 MHz IEC Level SAE Level
1
fOSC/fBUS 32 kHz crystal 10 MHz bus
Level1 (Max) –7 –9 –6 –6 N 1
Unit dBV
Radiated emissions, electric field
— —
Data based on qualification test results.
4
Ordering Information
This section contains the ordering information and the device numbering system for the MC9S08LL16 Series.
4.1
Device Numbering System
MC 9 S08 LL 16 Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family C XX
Example of the device numbering system:
Package designator (see Table 22) Temperature range (C = –40 C to 85 C) Approximate FLASH size in KB
5
Package Information and Mechanical Drawings
Table 22 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08LL16 Series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table 22, or • Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table 22) in the “Enter Keyword” search box at the top of the page.
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 41
Package Information and Mechanical Drawings
Table 22. Package Descriptions
Pin Count 64 48 48 Package Type Low Quad Flat Package Low Quad Flat Package Quad Flat No-Leads Abbreviation LQFP LQFP QFN Designator LH LF GT Case No. 840F 932 1314 Document No. 98ASS23234W 98ASH00962A 98ARH99048A
MC9S08LL16 Series MCU Data Sheet, Rev. 6 42 Freescale Semiconductor
Package Information and Mechanical Drawings
MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 43
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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008-2009. All rights reserved. MC9S08LL16 Rev. 6 10/2010
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