MC9S08QD4VPS

MC9S08QD4 MC9S08QD2 S9S08QD4 S9S08QD2 Data Sheet HCS08 Microcontrollers MC9S08QD4 Rev. 3 11/2007 freescale.com MC9S08QD4 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • Flash block protect • • • • • 16 MHz HCS08 CPU (central processor unit) HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) Support for up to 32 interrupt/reset sources Peripherals • • Memory • • • Flash read/program/erase over full operating voltage and temperature Flash size: — MC9S08QD4/S9S08QD4: 4096 bytes — MC9S08QD2/S9S08QD2: 2048 bytes RAM size — MC9S08QD4/S9S08QD4: 256 bytes — MC9S08QD2/S9S08QD2: 128 bytes • • ADC — 4-channel, 10-bit analog-to-digital converter with automatic compare function, asynchronous clock source, temperature sensor and internal bandgap reference channel. ADC is hardware triggerable using the RTI counter. TIM1 — 2-channel timer/pulse-width modulator; each channel can be used for input capture, output compare, buffered edge-aligned PWM, or buffered center-aligned PWM TIM2 — 1-channel timer/pulse-width modulator; each channel can be used for input capture, output compare, buffered edge-aligned PWM, or buffered center-aligned PWM KBI — 4-pin keyboard interrupt module with software selectable polarity on edge or edge/level modes Input/Output Power-Saving Modes • • Wait plus three stops • • • Clock Source Options • ICS — Internal clock source module (ICS) containing a frequency-locked-loop (FLL) controlled by internal. Precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage. Four General-purpose input/output (I/O) pins, one input-only pin and one output-only pin. Outputs 10 mA each, 60 mA maximum for package. Software selectable pullups on ports when used as input Software selectable slew rate control and drive strength on ports when used as output Internal pullup on RESET and IRQ pin to reduce customer system cost System Protection Development Support • • • • Watchdog computer operating properly (COP) reset with option to run from dedicated 32 kHz internal clock source or bus clock Low-voltage detection with reset or interrupt Illegal opcode detection with reset Illegal address detection with reset • Single-wire background debug interface Package Options • • • 8-pin SOIC package 8-pin PDIP (Only for MC9S08QD4 and MC9S08QD2) All package options are RoHS compliant MC9S08QD4 Data Sheet Covers: MC9S08QD4 MC9S08QD2 S9S08QD4 S9S08QD2 MC9S08QD4 Rev. 3 11/2007 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number 1 2 3 Revision Date 15 Sep 06 09 Jan 07 19 Nov. 07 Initial public release Added MC9S08QD2 information; added “M” temperature range (–40 °C to 125 °C); updated temperature sensor equation in the ADC chapter. Added S9S08QD4 and S9S08QD2 information for automotive applications. Revised "Accessing (read or write) any flash control register..." to “ Writing any flash control register...” in Section 4.5.5, “Access Errors.” Description of Changes This product incorporates SuperFlash® technology licensed from SST. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007. All rights reserved. MC9S08QD4 Series MCU Data Sheet, Rev. 3 6 Freescale Semiconductor List of Chapters Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Appendix A Appendix B Device Overview ...................................................................... 17 External Signal Description .................................................... 21 Modes of Operation ................................................................. 27 Memory Map and Register Definition .................................... 33 Resets, Interrupts, and General System Control.................. 53 Parallel Input/Output Control.................................................. 69 Central Processor Unit (S08CPUV2) ...................................... 75 Analog-to-Digital Converter (ADC10V1) ................................ 95 Internal Clock Source (S08ICSV1)........................................ 123 Keyboard Interrupt (S08KBIV2) ............................................ 137 Timer/Pulse-Width Modulator (S08TPMV2) ......................... 145 Development Support ........................................................... 161 Electrical Characteristics...................................................... 175 Ordering Information and Mechanical Drawings................ 193 MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 7 Contents Section Number Title Chapter 1 Device Overview 1.1 1.2 1.3 Introduction .....................................................................................................................................17 Devices in the MC9S08QD4 Series ................................................................................................17 1.2.1 MCU Block Diagram ........................................................................................................19 System Clock Distribution ..............................................................................................................20 Page Chapter 2 External Signal Description 2.1 2.2 Device Pin Assignment ...................................................................................................................21 Recommended System Connections ...............................................................................................21 2.2.1 Power ................................................................................................................................22 2.2.2 Oscillator ...........................................................................................................................23 2.2.3 Reset (Input Only) ............................................................................................................23 2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................23 2.2.5 General-Purpose I/O and Peripheral Ports ........................................................................24 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................27 Features ...........................................................................................................................................27 Run Mode ........................................................................................................................................27 Active Background Mode ...............................................................................................................27 Wait Mode .......................................................................................................................................28 Stop Modes ......................................................................................................................................28 3.6.1 Stop2 Mode .......................................................................................................................29 3.6.2 Stop3 Mode .......................................................................................................................30 3.6.3 Active BDM Enabled in Stop Mode .................................................................................30 3.6.4 LVD Enabled in Stop Mode ..............................................................................................31 3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................31 Chapter 4 Memory Map and Register Definition 4.1 4.2 4.3 4.4 4.5 MC9S08QD4 Series Memory Maps ...............................................................................................33 Reset and Interrupt Vector Assignments .........................................................................................34 Register Addresses and Bit Assignments ........................................................................................35 RAM ................................................................................................................................................38 Flash ................................................................................................................................................39 4.5.1 Features .............................................................................................................................39 MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 9 4.6 4.7 4.5.2 Program and Erase Times .................................................................................................39 4.5.3 Program and Erase Command Execution .........................................................................40 4.5.4 Burst Program Execution ..................................................................................................41 4.5.5 Access Errors ....................................................................................................................43 4.5.6 Flash Block Protection ......................................................................................................44 4.5.7 Vector Redirection ............................................................................................................45 Security ............................................................................................................................................45 Flash Registers and Control Bits .....................................................................................................46 4.7.1 Flash Clock Divider Register (FCDIV) ............................................................................46 4.7.2 Flash Options Register (FOPT and NVOPT) ....................................................................48 4.7.3 Flash Configuration Register (FCNFG) ...........................................................................49 4.7.4 Flash Protection Register (FPROT and NVPROT) ..........................................................49 4.7.5 Flash Status Register (FSTAT) ..........................................................................................50 4.7.6 Flash Command Register (FCMD) ...................................................................................51 Chapter 5 Resets, Interrupts, and General System Control 5.1 5.2 5.3 5.4 5.5 Introduction .....................................................................................................................................53 Features ...........................................................................................................................................53 MCU Reset ......................................................................................................................................53 Computer Operating Properly (COP) Watchdog .............................................................................54 Interrupts .........................................................................................................................................55 5.5.1 Interrupt Stack Frame .......................................................................................................56 5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................56 5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................57 Low-Voltage Detect (LVD) System ................................................................................................58 5.6.1 Power-On Reset Operation ...............................................................................................59 5.6.2 LVD Reset Operation ........................................................................................................59 5.6.3 LVD Interrupt Operation ...................................................................................................59 5.6.4 Low-Voltage Warning (LVW) ...........................................................................................59 Real-Time Interrupt (RTI) ...............................................................................................................59 Reset, Interrupt, and System Control Registers and Control Bits ...................................................60 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................60 5.8.2 System Reset Status Register (SRS) .................................................................................61 5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................62 5.8.4 System Options Register 1 (SOPT1) ................................................................................63 5.8.5 System Options Register 2 (SOPT2) ................................................................................64 5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................64 5.8.7 System Real-Time Interrupt Status and Control Register (SRTISC) ................................65 5.8.8 System Power Management Status and Control 1 Register (SPMSC1) ...........................66 5.8.9 System Power Management Status and Control 2 Register (SPMSC2) ...........................67 5.6 5.7 5.8 Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Direction ..........................................................................................................69 MC9S08QD4 Series MCU Data Sheet, Rev. 3 10 Freescale Semiconductor 6.2 6.3 6.4 Pin Control — Pullup, Slew Rate and Drive Strength ....................................................................70 Pin Behavior in Stop Modes ............................................................................................................70 Parallel I/O Registers ......................................................................................................................71 6.4.1 Port A Registers ................................................................................................................71 6.4.2 Port A Control Registers ...................................................................................................72 Chapter 7 Central Processor Unit (S08CPUV2) 7.1 7.2 Introduction .....................................................................................................................................75 7.1.1 Features .............................................................................................................................75 Programmer’s Model and CPU Registers .......................................................................................76 7.2.1 Accumulator (A) ...............................................................................................................76 7.2.2 Index Register (H:X) ........................................................................................................76 7.2.3 Stack Pointer (SP) .............................................................................................................77 7.2.4 Program Counter (PC) ......................................................................................................77 7.2.5 Condition Code Register (CCR) .......................................................................................77 Addressing Modes ...........................................................................................................................79 7.3.1 Inherent Addressing Mode (INH) .....................................................................................79 7.3.2 Relative Addressing Mode (REL) ....................................................................................79 7.3.3 Immediate Addressing Mode (IMM) ................................................................................79 7.3.4 Direct Addressing Mode (DIR) ........................................................................................79 7.3.5 Extended Addressing Mode (EXT) ..................................................................................80 7.3.6 Indexed Addressing Mode ................................................................................................80 Special Operations ...........................................................................................................................81 7.4.1 Reset Sequence .................................................................................................................81 7.4.2 Interrupt Sequence ............................................................................................................81 7.4.3 Wait Mode Operation ........................................................................................................82 7.4.4 Stop Mode Operation ........................................................................................................82 7.4.5 BGND Instruction .............................................................................................................83 HCS08 Instruction Set Summary ....................................................................................................84 7.3 7.4 7.5 Chapter 8 Analog-to-Digital Converter (ADC10V1) 8.1 Introduction .....................................................................................................................................95 8.1.1 Module Configurations .....................................................................................................96 8.1.2 Features .............................................................................................................................99 8.1.3 Block Diagram ..................................................................................................................99 External Signal Description ..........................................................................................................100 8.2.1 Analog Power (VDDAD) ..................................................................................................101 8.2.2 Analog Ground (VSSAD) .................................................................................................101 8.2.3 Voltage Reference High (VREFH) ...................................................................................101 8.2.4 Voltage Reference Low (VREFL) ....................................................................................101 8.2.5 Analog Channel Inputs (ADx) ........................................................................................101 Register Definition ........................................................................................................................101 8.3.1 Status and Control Register 1 (ADCSC1) ......................................................................101 MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 11 8.2 8.3 8.4 8.5 8.6 8.3.2 Status and Control Register 2 (ADCSC2) ......................................................................103 8.3.3 Data Result High Register (ADCRH) .............................................................................104 8.3.4 Data Result Low Register (ADCRL) ..............................................................................104 8.3.5 Compare Value High Register (ADCCVH) ....................................................................105 8.3.6 Compare Value Low Register (ADCCVL) .....................................................................105 8.3.7 Configuration Register (ADCCFG) ................................................................................105 8.3.8 Pin Control 1 Register (APCTL1) ..................................................................................107 8.3.9 Pin Control 2 Register (APCTL2) ..................................................................................108 8.3.10 Pin Control 3 Register (APCTL3) ..................................................................................109 Functional Description ..................................................................................................................110 8.4.1 Clock Select and Divide Control ....................................................................................110 8.4.2 Input Select and Pin Control ...........................................................................................111 8.4.3 Hardware Trigger ............................................................................................................ 111 8.4.4 Conversion Control ......................................................................................................... 111 8.4.5 Automatic Compare Function .........................................................................................114 8.4.6 MCU Wait Mode Operation ............................................................................................114 8.4.7 MCU Stop3 Mode Operation ..........................................................................................114 8.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................115 Initialization Information ..............................................................................................................115 8.5.1 ADC Module Initialization Example .............................................................................115 Application Information ................................................................................................................117 8.6.1 External Pins and Routing ..............................................................................................117 8.6.2 Sources of Error ..............................................................................................................119 Chapter 9 Internal Clock Source (S08ICSV1) 9.1 Introduction ...................................................................................................................................123 9.1.1 ICS Configuration Information .......................................................................................123 9.1.2 Features ...........................................................................................................................125 9.1.3 Modes of Operation ........................................................................................................125 9.1.4 Block Diagram ................................................................................................................126 External Signal Description ..........................................................................................................127 Register Definition ........................................................................................................................127 9.3.1 ICS Control Register 1 (ICSC1) .....................................................................................127 9.3.2 ICS Control Register 2 (ICSC2) .....................................................................................128 9.3.3 ICS Trim Register (ICSTRM) .........................................................................................129 9.3.4 ICS Status and Control (ICSSC) .....................................................................................129 Functional Description ..................................................................................................................130 9.4.1 Operational Modes ..........................................................................................................130 9.4.2 Mode Switching ..............................................................................................................132 9.4.3 Bus Frequency Divider ...................................................................................................132 9.4.4 Low Power Bit Usage .....................................................................................................133 9.4.5 Internal Reference Clock ................................................................................................133 9.4.6 Optional External Reference Clock ................................................................................133 9.4.7 Fixed Frequency Clock ...................................................................................................134 MC9S08QD4 Series MCU Data Sheet, Rev. 3 12 Freescale Semiconductor 9.2 9.3 9.4 9.5 Module Initialization ....................................................................................................................134 9.5.1 ICS Module Initialization Sequence ...............................................................................134 Chapter 10 Keyboard Interrupt (S08KBIV2) 10.1 Introduction ...................................................................................................................................137 10.1.1 Features ...........................................................................................................................139 10.1.2 Modes of Operation ........................................................................................................139 10.1.3 Block Diagram ................................................................................................................139 10.2 External Signal Description ..........................................................................................................140 10.3 Register Definition ........................................................................................................................140 10.3.1 KBI Status and Control Register (KBISC) .....................................................................140 10.3.2 KBI Pin Enable Register (KBIPE) ..................................................................................141 10.3.3 KBI Edge Select Register (KBIES) ................................................................................141 10.4 Functional Description ..................................................................................................................142 10.4.1 Edge Only Sensitivity .....................................................................................................142 10.4.2 Edge and Level Sensitivity .............................................................................................142 10.4.3 KBI Pullup/Pulldown Resistors ......................................................................................143 10.4.4 KBI Initialization ............................................................................................................143 Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.1 Introduction ...................................................................................................................................145 11.1.1 TPM2 Configuration Information ...................................................................................145 11.1.2 TCLK1 and TCLK2 Configuration Information ............................................................145 11.1.3 Features ...........................................................................................................................147 11.1.4 Block Diagram ................................................................................................................147 11.2 External Signal Description ..........................................................................................................149 11.2.1 External TPM Clock Sources .........................................................................................149 11.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................149 11.3 Register Definition ........................................................................................................................149 11.3.1 Timer Status and Control Register (TPMxSC) ...............................................................150 11.3.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) ...................................................151 11.3.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) ..................................152 11.3.4 Timer Channel n Status and Control Register (TPMxCnSC) .........................................153 11.3.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) .........................................154 11.4 Functional Description ..................................................................................................................155 11.4.1 Counter ............................................................................................................................155 11.4.2 Channel Mode Selection .................................................................................................156 11.4.3 Center-Aligned PWM Mode ...........................................................................................158 11.5 TPM Interrupts ..............................................................................................................................159 11.5.1 Clearing Timer Interrupt Flags .......................................................................................159 11.5.2 Timer Overflow Interrupt Description ............................................................................159 11.5.3 Channel Event Interrupt Description ..............................................................................160 11.5.4 PWM End-of-Duty-Cycle Events ...................................................................................160 MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 13 Chapter 12 Development Support 12.1 Introduction ...................................................................................................................................161 12.1.1 Forcing Active Background ............................................................................................161 12.1.2 Module Configuration .....................................................................................................161 12.1.3 Features ...........................................................................................................................162 12.2 Background Debug Controller (BDC) ..........................................................................................162 12.2.1 BKGD Pin Description ...................................................................................................163 12.2.2 Communication Details ..................................................................................................163 12.2.3 BDC Commands .............................................................................................................166 12.2.4 BDC Hardware Breakpoint .............................................................................................169 12.3 Register Definition ........................................................................................................................169 12.3.1 BDC Registers and Control Bits .....................................................................................170 12.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................172 Appendix A Electrical Characteristics Introduction ...................................................................................................................................175 Absolute Maximum Ratings ..........................................................................................................175 Thermal Characteristics .................................................................................................................176 ESD Protection and Latch-Up Immunity ......................................................................................177 DC Characteristics .........................................................................................................................177 Supply Current Characteristics ......................................................................................................184 Internal Clock Source Characteristics ...........................................................................................186 AC Characteristics .........................................................................................................................188 A.8.1 Control Timing ...............................................................................................................188 A.8.2 Timer/PWM (TPM) Module Timing ..............................................................................189 A.9 ADC Characteristics ......................................................................................................................190 A.10 Flash Specifications .......................................................................................................................191 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................193 B.1.1 Device Numbering Scheme ............................................................................................193 B.2 Mechanical Drawings ....................................................................................................................194 MC9S08QD4 Series MCU Data Sheet, Rev. 3 14 Freescale Semiconductor MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 15 Chapter 1 Device Overview 1.1 Introduction MC9S08QD4 series MCUs are members of the low-cost, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 Devices in the MC9S08QD4 Series This data sheet covers: • MC9S08QD4 • MC9S08QD2 • S9S08QD4 • S9S08QD2 • • NOTE The MC9S08QD4 and MC9S08QD2 devices are qualified for, and are intended to be used in, consumer and industrial applications. The S9S08QD4 and S9S08QD2 devices are qualified for, and are intended to be used in, automotive applications. Table 1-1 summarizes the features available in the MCUs. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 17 Chapter 1 Device Overview Table 1-1. Features by MCU and Package Consumer and Industrial Devices Feature Flash RAM ADC Bus speed Operating voltage 16-bit Timer GPIO LVI Package options Consumer & Industrial Qualified Automotive Qualified yes no MC9S08QD4 4 KB 256 B 4-ch, 10-bit 8 MHz at 5 V 2.7 to 5.5 V One 1-ch; one 2-ch Four I/O; one input-only; one output-only Yes 8-pin PDIP; 8-pin NB SOIC yes no MC9S08QD2 2 KB 128 B Automotive Devices Feature Flash RAM ADC Bus speed Operating voltage 16-bit Timer GPIO LVI Package options Consumer & Industrial Qualified Automotive Qualified no yes S9S08QD4 4 KB 256 B 4-ch, 10-bit 8 MHz at 5 V 2.7 to 5.5 V One 1-ch; one 2-ch Four I/O; one input-only; one output-only Yes 8-pin NB SOIC no yes S9S08QD2 2 KB 128 B MC9S08QD4 Series MCU Data Sheet, Rev. 3 18 Freescale Semiconductor Chapter 1 Device Overview 1.2.1 MCU Block Diagram BKGD/MS IRQ HCS08 CORE CPU BDC 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) 4 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD PORT A TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA0/KBI1P0/TPM1CH0/ADC1P0 USER FLASH 4096 / 2048 BYTES 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 USER RAM 256 / 128 BYTES 16 MHz INTERNAL CLOCK SOURCE (ICS) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL NOTES: 1 Port pins are software configurable with pullup device if input port. 2 Port pins are software configurable for output drive strength. 3 Port pins are software configurable for output slew rate control. 4 IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1). 5 RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). 6 PTA5 does not contain a clamp diode to V DD and must not be driven above VDD. The voltage measured on this pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD. 7 PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). 8 When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 1-1. MC9S08QD4 Series Block Diagram Table 1-2 provides the functional versions of the on-chip modules. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 19 Chapter 1 Device Overview Table 1-2. Versions of On-Chip Modules Module Analog-to-Digital Converter Central Processing Unit Internal Clock Source Keyboard Interrupt Timer Pulse-Width Modulator (ADC) (CPU) (ICS) (KBI) (TPM) Version 1 2 1 2 2 1.3 System Clock Distribution Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. All memory mapped registers associated with the modules are clocked with BUSCLK. TCLK1 SYSTEM CONTROL LOGIC RTI ICSIRCLK ICSFFCLK COP TPM1 TPM2 TCLK2 ÷2 FIXED FREQ CLOCK (XCLK) ICS ICSOUT ÷2 CPU BUSCLK ICSLCLK1 BDC ADC2 FLASH3 1 2 ICSLCLK is the alternate BDC clock source for the MC9S08QD4 series. ADC has min. and max frequency requirements. See ADC chapter and Appendix A, “Electrical Characteristics.” 3 Flash has frequency requirements for program and erase operation.See Appendix A, “Electrical Characteristics.” Figure 1-2. System Clock Distribution Diagram MC9S08QD4 Series MCU Data Sheet, Rev. 3 20 Freescale Semiconductor Chapter 2 External Signal Description This chapter describes signals that connect to package pins. It includes pinout diagrams, table of signal properties, and detailed discussions of signals. 2.1 Device Pin Assignment Figure 2-1 shows the pin assignments for the 8-pin packages. PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS VDD VSS 1 2 3 4 8 7 6 5 PTA0/KBI1P0/TPM1CH0/ADC1P0 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA2/KBI1P2/TCLK1/ADC1P2 PTA3/KBI1P3/TCLK2/ADC1P3 Figure 2-1. 8-Pin Packages 2.2 Recommended System Connections Figure 2-2 shows pin connections that are common to almost all MC9S08QD4 series application systems. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 21 Chapter 2 External Signal Description MC9S08QD4 SYSTEM POWER + 5V CBLK 10 μF VDD + CBY 0.1 μF VSS VDD PORT A PTA0/KBI1P0/TPM1CH0/ADC1P0 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA2/KBI1P2/TCLK1/ADC1P2 PTA3/KBI1P3/TCLK2/ADC1P3 PTA4/TPM2CH0O/BKGD/MS PTA5/TPM2CH0I/IRQ/RESET I/O AND PERIPHERAL INTERFACE TO APPLICATION SYSTEM BACKGROUND HEADER VDD BKGD NOTE 1 RESET OPTIONAL MANUAL RESET ASYNCHRONOUS INTERRUPT INPUT IRQ NOTE 2 NOTES: 1. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM command. 2. IRQ has optional internal pullup/pulldown device Figure 2-2. Basic System Connections 2.2.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry, the ADC module, and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins: a bulk electrolytic capacitor, such as a 10μF tantalum capacitor, to provide bulk charge storage for the overall system, and a bypass capacitor, such as a 0.1μF ceramic capacitor, located as near to the MCU power pins as practical to suppress high-frequency noise. MC9S08QD4 Series MCU Data Sheet, Rev. 3 22 Freescale Semiconductor Chapter 2 External Signal Description 2.2.2 Oscillator Out of reset the MCU uses an internally generated clock provided by the internal clock source (ICS) module. The internal frequency is nominally 16 MHz and the default ICS settings will provide for a 4 MHz bus out of reset. For more information on the ICS, see the Internal Clock Source chapter. 2.2.3 Reset (Input Only) After a power-on reset (POR) into user mode, the PTA5/TPM2CH0I/IRQ/RESET pin defaults to a general-purpose input port pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET input pin. Once configured as RESET, the pin will remain RESET until the next POR. The RESET pin can be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET pin (RSTPE = 1), an internal pullup device is automatically enabled. After a POR into active background mode, the PTA5/TPM2CH0I/IRQ/RESET pin defaults to the RESET pin. When TPM2 is configured for input capture, the pin will be the input capture pin TPM2CH0I. NOTE This pin does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on the internally pulled up RESET pin may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD. 2.2.4 Background / Mode Select (BKGD/MS) During a power-on-reset (POR) or background debug force reset (see Section 5.8.3, “System Background Debug Force Reset Register (SBDFR)” for more information), the PTA4/TPM2CH0O/BKGD/MS pin functions as a mode select pin. Immediately after any reset, the pin functions as the background pin and can be used for background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal pullup device is automatically enabled. The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is set following any reset of the MCU and must be cleared to use the PTA4/TPM2CH0O/BKGD/MS pins alternative pin functions. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug force reset, which will force the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 23 Chapter 2 External Signal Description Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.2.5 General-Purpose I/O and Peripheral Ports The MC9S08QD4 series of MCUs support up to 4 general-purpose I/O pins, 1 input-only pin and 1 output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard interrupts, etc.). On each of the MC9S08QD4 series devices there is one input-only and one output-only port pin. When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pullup device. For information about controlling these pins as general-purpose I/O pins, see the Chapter 6, “Parallel Input/Output Control.” For information about how and when on-chip peripheral systems use these pins, see the appropriate chapter referenced in Table 2-1. Immediately after reset, all pins that are not output-only are configured as high-impedance, general-purpose inputs with internal pullup devices disabled. After reset, the output-only port function is not enabled but is configured for low output drive strength with slew rate control enabled. The PTA4 pin defaults to BKGD/MS on any reset. NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program must either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. 2.2.5.1 Pin Control Registers To select drive strength or enable slew rate control or pullup devices, the user writes to the appropriate pin control register located in the high-page register block of the memory map. The pin control registers operate independently of the parallel I/O registers and allow control of a port on an individual pin basis. 2.2.5.1.1 Internal Pullup Enable An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the parallel I/O control logic or any shared peripheral function, regardless of the state of the corresponding pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function. The KBI module and IRQ function when enabled for rising edge detection causes an enabled internal pull device to be configured as a pulldown. MC9S08QD4 Series MCU Data Sheet, Rev. 3 24 Freescale Semiconductor Chapter 2 External Signal Description 2.2.5.2 Output Slew Rate Control Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs. 2.2.5.3 Output Drive Strength Select An output pin can be selected to have high output drive strength by setting the corresponding bit in one of the drive strength select registers (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this, the EMC emissions may be affected by enabling pins as high drive. Table 2-1. Pin Sharing Priority Lowest Highest Port Pins PTA0 PTA1 PTA2 PTA3 PTA4 PTA52 1 2 Alternative Function KBI1P0 KBI1P1 KBI1P2 KBI1P3 TPM2CH0O TPM2CH0I Alternative Function TPM1CH0 TPM1CH1 TCLK1 TCLK2 BKGD/MS IRQ Alternative Function ADC1P03 ADC1P13 ADC1P23 ADC1P33 RESET Reference1 KBI1, ADC1, and TPM1 Chapters KBI1, ADC1, and TPM1 Chapters KBI1, ADC1, and TPM1 Chapters KBI1, ADC1, and TPM2 Chapters TPM2 Chapters IRQ4, and TPM2 Chapters See the module section listed for information on modules that share these pins. Pin does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD. 3 If both of these analog modules are enabled both will have access to the pin. 4 See Section 5.8, “Reset, Interrupt, and System Control Registers and Control Bits,” for information on configuring the IRQ module. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 25 Chapter 2 External Signal Description MC9S08QD4 Series MCU Data Sheet, Rev. 3 26 Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08QD4 series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • Features Active background mode for code development Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained Stop modes: — CPU and bus clocks stopped — Stop2 — Partial power down of internal circuits, RAM contents retained — Stop3 — All internal circuits powered for fast recovery • 3.3 Run Mode This is the normal operating mode for the MC9S08QD4 series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC provides the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 27 Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) The active background mode is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time. When MC9S08QD4 series devices are shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted, so no program can be executed in run mode until the flash memory is initially programmed. The active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. For additional information about the active background mode, refer to Chapter 12, “Development Support.” 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In both stop modes, all internal clocks are halted. If the STOPE bit is not set when MC9S08QD4 Series MCU Data Sheet, Rev. 3 28 Freescale Semiconductor Chapter 3 Modes of Operation the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08QD4 series does not include stop1 mode. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1. Stop Mode Behavior CPU, Digital Peripherals, Flash Off Standby Mode PPDC RAM ICS ADC1 Regulator I/O Pins RTI Stop2 Stop3 1 1 0 Standby Standby Off Off1 Disabled Optionally on Standby Standby States held States held Optionally on Optionally on ICS can be configured to run in stop3. Please see the ICS registers. 3.6.1 Stop2 Mode The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. To enter stop2, the user must execute a STOP instruction with stop2 selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to operate in stop (LVDSE = 0 or LVDE = 0). If the LVD is enabled in stop, then the MCU enters stop3 upon the execution of the STOP instruction regardless of the state of PPDC. Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by user software before pin latches are opened. When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ADC. Upon entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a logic 1 is written to PPDACK in SPMSC2. Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before entering stop2. NOTE Although this IRQ pin is automatically configured as active low input, the pullup associated with the IRQ pin is not automatically enabled. Therefore, if an external pullup is not used, the internal pullup must be enabled by setting IRQPE in IRQSC. Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 29 Chapter 3 Modes of Operation After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.2 Stop3 Mode Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time interrupt (RTI), LVD, ADC, IRQ, or the KBI. If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector. 3.6.3 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in Chapter 12, “Development Support,” of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the background debug mode is enabled. MC9S08QD4 Series MCU Data Sheet, Rev. 3 30 Freescale Semiconductor Chapter 3 Modes of Operation Table 3-2. BDM Enabled Stop Mode Behavior CPU, Digital Peripherals, Flash Standby Mode PPDC RAM ICS ADC1 Regulator I/O Pins RTI Stop3 0 Standby Active Optionally on Active States held Optionally on 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the LVD is enabled. Table 3-3. LVD Enabled Stop Mode Behavior CPU, Digital Peripherals, Flash Standby Mode PPDC RAM ICS Off1 ADC1 Regulator I/O Pins RTI Stop3 1 0 Standby Optionally on Active States held Optionally on ICS can be configured to run in stop3. Please see the ICS registers. 3.6.5 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2 Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes. Table 3-4. Stop Mode Behavior Mode Peripheral Stop2 CPU RAM Flash Parallel Port Registers ADC1 ICS TPM1 & TPM2 Voltage Regulator I/O Pins 1 Stop3 Standby Standby Standby Standby Optionally On1 Standby Standby Standby States Held Off Standby Off Off Off Off Off Standby States Held Requires the asynchronous ADC clock and LVD to be enabled, else in standby. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 31 Chapter 3 Modes of Operation MC9S08QD4 Series MCU Data Sheet, Rev. 3 32 Freescale Semiconductor Chapter 4 Memory Map and Register Definition 4.1 MC9S08QD4 Series Memory Maps As shown in Figure 4-1, on-chip memory in the MC9S08QD4 series MCU consists of RAM, flash program memory for non-volatile data storage, and I/O and control/status registers. The registers are divided into these groups: • Direct-page registers (0x0000 through 0x005F) • High-page registers (0x1800 through 0x184F) • Non-volatile registers (0xFFB0 through 0xFFBF) 0x0000 0x005F 0x0060 0x015F 0x0160 0x17FF 0x1800 DIRECT PAGE REGISTERS RAM 256 BYTES 0x0000 0x005F 0x0060–0x07F 0x0080–0x0FF 0x0100–0x015F UNIMPLEMENTED 5,792 BYTES DIRECT PAGE REGISTERS RESERVED — 32 BYTES RAM — 128 BYTES RESERVED — 96 BYTES UNIMPLEMENTED 5,792 BYTES 0x17FF 0x1800 0x184F 0x1850 HIGH PAGE REGISTERS 0x184F 0x1850 HIGH PAGE REGISTERS UNIMPLEMENTED 55,216 BYTES UNIMPLEMENTED 55,216 BYTES 0xEFFF 0xF000 0xEFFF 0xF000 FLASH 4096 BYTES 0xF7FF 0xF800 0xFFFF RESERVED — 2048 BYTES FLASH 2048 BYTES 0xFFFF MC9S08QD4 MC9S08QD2 Figure 4-1. MC9S08QD4 Series Memory Maps MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 33 Chapter 4 Memory Map and Register Definition 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QD4 series. Table 4-1. Reset and Interrupt Vectors Address (High/Low) 0xFFC0:FFC1 Vector Unused Vector Space (available for user program) Vector Name 0xFFCE:FFCF 0xFFD0:FFD1 0xFFD2:FFD3 0xFFD4:FFD5 0xFFD6:FFD7 0xFFD8:FFD9 0xFFDA:FFDB 0xFFDC:FFDD 0xFFDE:FFDF 0xFFE0:FFE1 0xFFE2:FFE3 0xFFE4:FFE5 0xFFE6:FFE7 0xFFE8:FFE9 0xFFEA:FFEB 0xFFEC:FFED 0xFFEE:FFEF 0xFFF0:FFF1 0xFFF2:FFF3 0xFFF4:FFF5 0xFFF6:FFF7 0xFFF8:FFF9 0xFFFA:FFFB 0xFFFC:FFFD 0xFFFE:FFFF RTI Reserved Reserved Reserved ADC1 Conversion KBI Interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved TPM2 Overflow Reserved TPM2 Channel 0 TPM1 Overflow TPM1 Channel 1 TPM1 Channel 0 Reserved IRQ Low Voltage Detect SWI Reset Vrti — — — Vadc1 Vkeyboard1 — — — — — — — Vtpm2ovf — Vtpm2ch0 Vtpm1ovf Vtpm1ch1 Vtpm1ch0 — IRQ Vlvd Vswi Vreset MC9S08QD4 Series MCU Data Sheet, Rev. 3 34 Freescale Semiconductor Chapter 4 Memory Map and Register Definition 4.3 Register Addresses and Bit Assignments The registers in the MC9S08QD4 series are divided into these groups: • Direct-page registers are located in the first 96 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM. • The nonvolatile register area consists of a block of 16 locations in flash memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — NVPROT and NVOPT are loaded into working registers at reset — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode that requires only the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. Table 4-2. Direct-Page Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 0x0001 0x0002– 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 PTAD PTADD Reserved KBISC KBIPE KBIES IRQSC ADCSC1 ADCSC2 ADCRH ADCRL ADCCVH ADCCVL ADCCFG 0 0 — — 0 KBIPE7 KBEDG7 0 COCO ADACT 0 ADR7 0 ADCV7 ADLPC 0 0 — — 0 KBIPE6 KBEDG6 IRQPDD AIEN ADTRG 0 ADR6 0 ADCV6 ADIV PTAD5 PTADD5 — — 0 KBIPE5 KBEDG5 IRQEDG ADCO ACFE 0 ADR5 0 ADCV5 PTAD4 PTADD4 — — 0 KBIPE4 KBEDG4 IRQPE ACFGT 0 ADR4 0 ADCV4 ADLSMP PTAD3 PTADD3 — — KBF KBIPE3 KBEDG3 IRQF — 0 ADR3 0 ADCV3 PTAD2 PTADD2 — — KBACK KBIPE2 KBEDG2 IRQACK ADCH — 0 ADR2 0 ADCV2 PTAD1 PTADD1 — — KBIE KBIPE1 KBEDG1 IRQIE — ADR9 ADR1 ADCV9 ADCV1 PTAD0 PTADD0 — — KBIMOD KBIPE0 KBEDG0 IRQMOD — ADR8 ADR0 ADCV8 ADCV0 MODE ADICLK MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 35 Chapter 4 Memory Map and Register Definition Table 4-2. Direct-Page Register Summary (continued) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0017 0x0018 0x0019 0x001A– 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028– 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B– 0x005F APCTL1 Reserved Reserved Reserved TPM2SC TPM2CNTH TPM2CNTL TPM2MODH TPM2MODL TPM2C0SC TPM2C0VH TPM2C0VL Reserved ICSC1 ICSC2 ICSTRM ICSSC Reserved TPMSC TPMCNTH TPMCNTL TPMMODH TPMMODL TPMC0SC TPMC0VH TPMC0VL TPMC1SC TPMC1VH TPMC1VL Reserved — — — — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 — — 0 BDIV 0 — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — — — — — — — TOIE 14 6 14 6 CH0IE 14 6 — — CLKS — — — — — CPWMS 13 5 13 5 MS0B 13 5 — — 0 0 — — — — — CLKSB 12 4 12 4 MS0A 12 4 — — 0 0 TRIM 0 — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — — ADPC3 — — — — CLKSA 11 3 11 3 ELS0B 11 3 — — 0 LP 0 — CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — — ADPC2 — — — — PS2 10 2 10 2 ELS0A 10 2 — — 1 0 CLKST — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — — ADPC1 — — — — PS1 9 1 9 1 0 9 1 — — 1 0 0 — PS1 9 1 9 1 0 9 1 0 9 1 — — ADPC0 — — — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — IREFSTEN 0 FTRIM — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — 0 — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — — 0 — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — — High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. MC9S08QD4 Series MCU Data Sheet, Rev. 3 36 Freescale Semiconductor Chapter 4 Memory Map and Register Definition Table 4-3. High-Page Register Summary Address 0x1800 0x1801 0x1802 0x1803 0x1804 0x1805 0x1806 0x1807 0x1808 0x1809 0x180A 0x180B– 0x181F 0x1820 0x1821 0x1822 0x1823 0x1824 0x1825 0x1826 0x1827– 0x183F 0x1840 0x1841 0x1842 0x1843– 0x1847 1 Register Name SRS SBDFR SOPT1 SOPT2 Reserved Reserved SDIDH SDIDL SRTISC SPMSC1 SPMSC2 Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Reserved PTAPE PTASE PTADS Reserved Bit 7 POR 0 COPE COPCLKS — — REV3 ID7 RTIF LVDF LVWF — — DIVLD KEYEN — 0 FCBEF — — 0 0 0 — — 6 PIN 0 COPT 0 — — REV2 ID6 RTIACK LVDACK LVWACK — — PRDIV8 FNORED — 0 FCCF — — 0 0 0 — — 5 COP 0 STOPE 0 — — REV1 ID5 RTICLKS LVDIE LVDV — — 0 — KEYACC FPVIOL — — PTAPE5 PTASE5 PTADS5 — — 4 ILOP 0 0 0 — — REV0 ID4 RTIE LVDRE LVWV — — 0 — 0 FPS FACCERR FCMD — — PTAPE4 PTASE4 PTADS4 — — 3 ILAD 0 0 0 — — ID11 ID3 0 LVDSE PPDF — — DIV 0 — 0 0 — — PTAPE3 PTASE3 PTADS3 — — 2 0 0 0 0 — — ID10 ID2 LVDE PPDACK — — 0 — 0 FBLANK — — PTAPE2 PTASE2 PTADS2 — — 1 LVD 0 BKGDPE 0 — — ID9 ID1 RTIS 01 — — — SEC01 — 0 0 — — PTAPE1 PTASE1 PTADS1 — — Bit 0 0 BDFR RSTPE 0 — — ID8 ID0 BGBE PPDC — — SEC00 — 0 FPDIS 0 — — PTAPE0 PTASE0 PTADS0 — — This reserved bit must always be written to 0. Nonvolatile flash registers, shown in Table 4-4, are located in the flash memory. These registers include an 8-byte backdoor key that optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the flash memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 37 Chapter 4 Memory Map and Register Definition Table 4-4. Nonvolatile Register Summary Address Register Name Bit 7 — — ADR7 6 — — ADR6 5 — — ADR5 4 — — ADR4 3 — — ADR3 2 — — ADR2 1 — — ADR1 Bit 0 — — ADR0 0xFFAA – Reserved 0xFFAC 0xFFAD Reserved for ADCRL of AD26 value during ICS trim Reserved for ADCRH of AD26 value during ICS trim and ICS Trim value “FTRIM” Reserved for ICS Trim value “TRIM” 0xFFAE ADR9 ADR8 — — — — — FTRIM 0xFFAF TRIM 8-Byte Comparison Key — — — KEYEN — — — FNORED — — — 0 — — FPS — 0 — 0 — 0 — SEC01 — — — — — — — — FPDIS — SEC00 0xFFB0 – NVBACKKEY 0xFFB7 0xFFB8 – Reserved 0xFFBC 0xFFBD 0xFFBE 0xFFBF NVPROT Unused NVOPT Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally through the background debug interface) and verifying that flash is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). The ICS factory-trimmed value will be stored in 0xFFAE (bit-0) and 0xFFAF. Development tools, such as programmers can trim the ICS and the internal temperature sensor (via the ADC) and store the values in 0xFFAD–0xFFAF. 4.4 RAM The MC9S08QD4 series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention (VRAM). MC9S08QD4 Series MCU Data Sheet, Rev. 3 38 Freescale Semiconductor Chapter 4 Memory Map and Register Definition For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08QD4 series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP fADCK Subsequent continuous 10-bit; fBUS > fADCK Subsequent continuous 8-bit; fBUS > fADCK/11 Subsequent continuous 10-bit; fBUS > fADCK/11 ADICLK 0x, 10 0x, 10 0x, 10 0x, 10 11 11 11 11 xx xx xx xx ADLSMP 0 0 1 1 0 0 1 1 0 0 1 1 Max Total Conversion Time 20 ADCK cycles + 5 bus clock cycles 23 ADCK cycles + 5 bus clock cycles 40 ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 μs + 20 ADCK + 5 bus clock cycles 5 μs + 23 ADCK + 5 bus clock cycles 5 μs + 40 ADCK + 5 bus clock cycles 5 μs + 43 ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles 40 ADCK cycles The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is: Conversion time = 23 ADCK cyc 8 MHz/1 + 5 bus cyc 8 MHz = 3.5 μs Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 113 Analog-to-Digital Converter (S08ADC10V1) 8.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than the compare value, COCO is set. The value generated by the addition of the conversion result and the two’s complement of the compare value is transferred to ADCRH and ADCRL. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon the setting of COCO if the ADC interrupt is enabled (AIEN = 1). NOTE The compare function can be used to monitor the voltage on a channel while the MCU is in either wait or stop3 mode. The ADC interrupt will wake the MCU when the compare condition is met. 8.4.6 MCU Wait Mode Operation The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled. The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait mode if the ADC interrupt is enabled (AIEN = 1). 8.4.7 MCU Stop3 Mode Operation The STOP instruction is used to put the MCU in a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 8.4.7.1 Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08QD4 Series MCU Data Sheet, Rev. 3 114 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 8.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3 mode if the ADC interrupt is enabled (AIEN = 1). NOTE It is possible for the ADC module to wake the system from low power stop and cause the MCU to begin consuming run-level currents without generating a system level interrupt. To prevent this scenario, software must ensure that the data transfer blocking mechanism (discussed in Section 8.4.4.2, “Completing Conversions,”) is cleared when entering stop3 and continuing ADC conversions. 8.4.8 MCU Stop1 and Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode. All module registers contain their reset values following exit from stop1 or stop2. Therefore the module must be re-enabled and re-configured following exit from stop1 or stop2. 8.5 Initialization Information This section gives an example which provides some basic direction on how a user would initialize and configure the ADC module. The user has the flexibility of choosing between configuring the module for 8-bit or 10-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 8-6, Table 8-7, and Table 8-8 for information used in this example. NOTE Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 8.5.1 8.5.1.1 ADC Module Initialization Example Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 115 Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 8.5.1.2 Pseudo — Code Example In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will be derived from the bus clock divided by 1. ADCCFG = 0x98 (%10011000) Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed) Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1 Bit 4 ADLSMP 1 Configures for long sample time Bit 3:2 MODE 10 Sets mode at 10-bit conversions Bit 1:0 ADICLK 00 Selects bus clock as input clock source ADCSC2 = 0x00 (%00000000) Bit 7 ADACT 0 Bit 6 ADTRG 0 Bit 5 ACFE 0 Bit 4 ACFGT 0 Bit 3:2 00 Bit 1:0 00 ADCSC1 = 0x41 (%01000001) Bit 7 COCO 0 Bit 6 AIEN 1 Bit 5 ADCO 0 Bit 4:0 ADCH 00001 Flag indicates if a conversion is in progress Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel ADCRH/L = 0xxx Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion data cannot be overwritten with data from the next conversion. ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins MC9S08QD4 Series MCU Data Sheet, Rev. 3 116 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT NO CONTINUE Figure 8-14. Initialization Flowchart for Example 8.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 8.6.1 External Pins and Routing The following sections discuss the external pins associated with the ADC module and how they must be used for best results. 8.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (VDDAD and VSSAD) which are available as separate pins on some devices. On other devices, VSSAD is shared on the same pin as the MCU digital VSS, and on others, both VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 117 Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This must be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 8.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The high reference is VREFH, which may be shared on the same pin as VDDAD on some devices. The low reference is VREFL, which may be shared on the same pin as VSSAD on some devices. When available on a separate pin, VREFH may be connected to the same potential as VDDAD, or may be driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH must never exceed VDDAD). When available on a separate pin, VREFL must be connected to the same voltage potential as VSSAD. Both VREFH and VREFL must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. Inductance in this path must be minimum (parasitic only). 8.6.1.3 Analog Input Pins The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin control register bit always be set when using a pin as an analog input. This avoids problems with contention because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input buffer draws dc current when its input is not at either VDD or VSS. Setting the pin control register bits for all pins used as analog inputs must be done to achieve lowest operating current. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to VSSA. For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to $3FF (full scale 10-bit representation) or $FF (full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. There will be a brief current associated with VREFL when the sampling capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins must not be transitioning during conversions. MC9S08QD4 Series MCU Data Sheet, Rev. 3 118 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 8.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 8.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept below 5 kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 8.6.2.2 Pin Leakage Error Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high. If this error cannot be tolerated by the application, keep RAS lower than VDDAD / (2N*ILEAK) for less than 1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode). 8.6.2.3 Noise-Induced Errors System noise which occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1 μF low-ESR capacitor from VREFH to VREFL. • There is a 0.1 μF low-ESR capacitor from VDDAD to VSSAD. • If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from VDDAD to VSSAD. • VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane. • Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion. — For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT instruction or STOP instruction. — For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: • Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSAD (this will improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 119 Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 8.6.2.4 Code Width and Quantization Error The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH - VREFL) / 2N Eqn. 8-2 There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB. 8.6.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system must be aware of them because they affect overall accuracy. These errors are: • Zero-scale error (EZS) (sometimes called offset) — This error is defined as the difference between the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is used. • Full-scale error (EFS) — This error is defined as the difference between the actual code width of the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the difference between the actual $3FE code width and its ideal (1LSB) is used. • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. • Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. • Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 8.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the MC9S08QD4 Series MCU Data Sheet, Rev. 3 120 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 8.6.2.3, “Noise-Induced Errors,” will reduce this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 121 Analog-to-Digital Converter (S08ADC10V1) MC9S08QD4 Series MCU Data Sheet, Rev. 3 122 Freescale Semiconductor Chapter 9 Internal Clock Source (S08ICSV1) 9.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by an internal reference clock. The module can provide this FLL clock or the internal reference clock as a source for the MCU system clock, ICSOUT. Whichever clock source is chosen, ICSOUT is passed through a bus clock divider (BDIV) which allows a lower final output clock frequency to be derived. ICSOUT is two times the bus frequency. Figure 9-1 Shows the MC9S08QD4 series with the ICS module highlighted. 9.1.1 ICS Configuration Information Bit-1 and bit-2 of ICS control register 1 (ICSC1) always read as 1. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 123 Chapter 9 Internal Clock Source (S08ICSV1) BKGD/MS IRQ HCS08 CORE CPU BDC 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) 4 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD PORT A TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA0/KBI1P0/TPM1CH0/ADC1P0 USER FLASH 4096 / 2048 BYTES 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 USER RAM 256 / 128 BYTES 16 MHz INTERNAL CLOCK SOURCE (ICS) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL NOTES: 1 Port pins are software configurable with pullup device if input port. 2 Port pins are software configurable for output drive strength. 3 Port pins are software configurable for output slew rate control. 4 IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1). 5 RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). 6 PTA5 does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD. 7 PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). 8 When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 9-1. MC9S08QD4 Series Block Diagram Highlighting ICS Block MC9S08QD4 Series MCU Data Sheet, Rev. 3 124 Freescale Semiconductor Internal Clock Source (S08ICSV1) 9.1.2 Features Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accuracy — 0.2% resolution using internal 32 kHz reference — 2% deviation over voltage and temperature using internal 32 kHz reference • Internal or external reference clocks up to 5 MHz can be used to control the FLL — 3 bit select for reference divider is provided • Internal reference clock has 9 trim bits available • Internal or external reference clocks can be selected as the clock source for the MCU • Whichever clock is selected as the source can be divided down — 2 bit select for clock divider is provided – Allowable dividers are: 1, 2, 4, 8 – BDC clock is provided as a constant divide by 2 of the DCO output • Control signals for a low power oscillator as the external reference clock are provided — HGO, RANGE, EREFS, ERCLKEN, EREFSTEN • FLL engaged internal mode is automatically selected out of reset 9.1.3 Modes of Operation There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. 9.1.3.1 FLL Engaged Internal (FEI) In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL which is controlled by the internal reference clock. The BDC clock is supplied from the FLL. 9.1.3.2 FLL Engaged External (FEE) In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an external reference clock. The BDC clock is supplied from the FLL. 9.1.3.3 FLL Bypassed Internal (FBI) In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied from the FLL. 9.1.3.4 FLL Bypassed Internal Low Power (FBILP) In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. The BDC clock is not available. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 125 Internal Clock Source (S08ICSV1) 9.1.3.5 FLL Bypassed External (FBE) In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is supplied from the FLL. 9.1.3.6 FLL Bypassed External Low Power (FBELP) In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is not available. 9.1.3.7 Stop (STOP) In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source. 9.1.4 Block Diagram Figure 9-2 is the ICS block diagram. RANGE HGO Optional External Reference Clock Source Block EREFS EREFSTEN ERCLKEN IRCLKEN IREFSTEN CLKS BDIV ICSERCLK ICSIRCLK / 2n Internal Reference Clock IREFS LP n=0-3 ICSOUT 9 TRIM DCO DCOOUT /2 ICSLCLK ICSFFCLK 9 / 2n n=0-7 FLL RDIV Internal Clock Source Block RDIV_CLK Filter Figure 9-2. Internal Clock Source (ICS) Block Diagram MC9S08QD4 Series MCU Data Sheet, Rev. 3 126 Freescale Semiconductor Internal Clock Source (S08ICSV1) 9.2 External Signal Description There are no ICS signals that connect off chip. 9.3 9.3.1 Register Definition ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 R CLKS W Reset: 0 0 0 0 0 1 0 0 RDIV IREFS IRCLKEN IREFSTEN Figure 9-3. ICS Control Register 1 (ICSC1) Table 9-1. ICS Control Register 1 Field Descriptions Field 7:6 CLKS Description Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value of the BDIV bits. 00 Output of FLL is selected. 01 Internal reference clock is selected. 10 External reference clock is selected. 11 Reserved, defaults to 00. Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. 000 Encoding 0 — Divides reference clock by 1 (reset default) 001 Encoding 1 — Divides reference clock by 2 010 Encoding 2 — Divides reference clock by 4 011 Encoding 3 — Divides reference clock by 8 100 Encoding 4 — Divides reference clock by 16 101 Encoding 5 — Divides reference clock by 32 110 Encoding 6 — Divides reference clock by 64 111 Encoding 7 — Divides reference clock by 128 Internal Reference Select — The IREFS bit selects the reference clock source for the FLL. 1 Internal reference clock selected 0 External reference clock selected Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as ICSIRCLK. 1 ICSIRCLK active 0 ICSIRCLK inactive Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock remains enabled when the ICS enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop 5:3 RDIV 2 IREFS 1 IRCLKEN 0 IREFSTEN MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 127 Internal Clock Source (S08ICSV1) 9.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 1 0 R BDIV W Reset: 0 1 0 0 0 0 0 0 RANGE HGO LP EREFS ERCLKEN EREFSTEN Figure 9-4. ICS Control Register 2 (ICSC2) Table 9-2. ICS Control Register 2 Field Descriptions Field 7:6 BDIV Description Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus frequency. 00 Encoding 0 — Divides selected clock by 1 01 Encoding 1 — Divides selected clock by 2 (reset default) 10 Encoding 2 — Divides selected clock by 4 11 Encoding 3 — Divides selected clock by 8 Frequency Range Select — Selects the frequency range for the external oscillator. 1 High frequency range selected for the external oscillator 0 Low frequency range selected for the external oscillator High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation. 1 Configure external oscillator for high gain operation 0 Configure external oscillator for low power operation Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes. 1 FLL is disabled in bypass modes unless BDM is active 0 FLL is not disabled in bypass mode External Reference Select — The EREFS bit selects the source for the external reference clock. 1 Oscillator requested 0 External Clock Source requested External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK. 1 ICSERCLK active 0 ICSERCLK inactive 5 RANGE 4 HGO 3 LP 2 EREFS 1 ERCLKEN 0 External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock EREFSTEN remains enabled when the ICS enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop MC9S08QD4 Series MCU Data Sheet, Rev. 3 128 Freescale Semiconductor Internal Clock Source (S08ICSV1) 9.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: Reset: 1 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U Figure 9-5. ICS Trim Register (ICSTRM) Table 9-3. ICS Trim Register Field Descriptions Field 7:0 TRIM Description ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period. An additional fine trim bit is available in ICSSC as the FTRIM bit. 9.3.4 ICS Status and Control (ICSSC) 7 6 5 4 3 2 1 0 R W POR: Reset: 0 0 0 0 CLKST OSCINIT FTRIM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U Figure 9-6. ICS Status and Control Register (ICSSC) Table 9-4. ICS Status and Control Register Field Descriptions Field 7:4 3:2 CLKST Reserved, must be cleared. Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected. 10 FLL Bypassed, External reference clock is selected. 11 Reserved. OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE, or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is cleared only when either ERCLKEN or EREFS are cleared. ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. Description 1 0 MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 129 Internal Clock Source (S08ICSV1) 9.4 9.4.1 Functional Description Operational Modes IREFS=1 CLKS=00 FLL Engaged Internal (FEI) IREFS=0 CLKS=10 BDM Enabled or LP =0 FLL Bypassed External Low Power(FBELP) IREFS=0 CLKS=10 BDM Disabled and LP=1 IREFS=1 CLKS=01 BDM Enabled or LP=0 FLL Bypassed Internal Low Power(FBILP) IREFS=1 CLKS=01 BDM Disabled and LP=1 FLL Bypassed External (FBE) FLL Bypassed Internal (FBI) FLL Engaged External (FEE) IREFS=0 CLKS=00 Entered from any state when MCU enters stop Stop Returns to state that was active before MCU entered stop, unless reset occurs while in stop. Figure 9-7. Clock Switching Modes The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the allowed movements between the states. 9.4.1.1 FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: • CLKS bits are written to 00 • IREFS bit is written to 1 • RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to 39.0625 kHz. In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference clock is enabled. MC9S08QD4 Series MCU Data Sheet, Rev. 3 130 Freescale Semiconductor Internal Clock Source (S08ICSV1) 9.4.1.2 • • • FLL Engaged External (FEE) The FLL engaged external (FEE) mode is entered when all the following conditions occur: CLKS bits are written to 00 IREFS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by the external reference clock.The FLL loop will lock the frequency to 512 times the filter frequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external reference clock is enabled. 9.4.1.3 FLL Bypassed Internal (FBI) The FLL bypassed internal (FBI) mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1. • BDM mode is active or LP bit is written to 0 In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512 times the Filter frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC communications, and the internal reference clock is enabled. 9.4.1.4 FLL Bypassed Internal Low Power (FBILP) The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1. • BDM mode is not active and LP bit is written to 1 In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal reference clock is enabled. 9.4.1.5 FLL Bypassed External (FBE) The FLL bypassed external (FBE) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is active or LP bit is written to 0. In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512 MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 131 Internal Clock Source (S08ICSV1) times the filter frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC communications, and the external reference clock is enabled. 9.4.1.6 FLL Bypassed External Low Power (FBELP) The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is not active and LP bit is written to 1. In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external reference clock is enabled. 9.4.1.7 Stop Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static except in the following cases: ICSIRCLK will be active in stop mode when all the following conditions occur: • IRCLKEN bit is written to 1 • IREFSTEN bit is written to 1 ICSERCLK will be active in stop mode when all the following conditions occur: • ERCLKEN bit is written to 1 • EREFSTEN bit is written to 1 9.4.2 Mode Switching When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will begin locking again after a few full cycles of the resulting divided reference frequency. The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is not available, the previous clock will remain selected. 9.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. MC9S08QD4 Series MCU Data Sheet, Rev. 3 132 Freescale Semiconductor Internal Clock Source (S08ICSV1) 9.4.4 Low Power Bit Usage The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0. 9.4.5 Internal Reference Clock When IRCLKEN is set the internal reference clock signal will be presented as ICSIRCLK, which can be used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period of the internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM register. Writing a larger value will slow down the ICSIRCLK frequency, and writing a smaller value to the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode. The TRIM and FTRIM value will not be affected by a reset. Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing specifications (see the Device Overview chapter). If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. All MCU devices are factory programmed with a trim value in a reserved memory location. This value can be copied to the ICSTRM register during reset initialization. The factory trim value does not include the FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the FTRIM bit accordingly. 9.4.6 Optional External Reference Clock The ICS module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz in all modes. When the ERCLKEN is set, the external reference clock signal will be presented as ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support (see the Device Overview chapter). If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 133 Internal Clock Source (S08ICSV1) 9.4.7 Fixed Frequency Clock The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK). In FLL engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS bypass modes, ICSFFE will get asserted for the following combinations of BDIV and RDIV values: • BDIV=00 (divide by 1), RDIV ≥ 010 • BDIV=01 (divide by 2), RDIV ≥ 011 • BDIV=10 (divide by 4), RDIV ≥ 100 • BDIV=11 (divide by 8), RDIV ≥ 101 9.5 Module Initialization This section describes how to initialize and configure the ICS module. The following sections contain two initialization examples. 9.5.1 ICS Module Initialization Sequence The ICS comes out of POR configured for FEI mode with the BDIV set for divide-by 2. The internal reference will stabilize in tIRST microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in tAcquire milliseconds. Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the ICSSC register, and 0xFFAF for storing the 8-bit trim value for the ICSTRM register. The MCU will not automatically copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these values from FLASH to the registers. NOTE The BDIV value must not be changed to divide-by 1 without first trimming the internal reference. Failure to do so could result in the MCU running out of specification. 9.5.1.1 Initialization Sequence, Internal Clock Mode to External Clock Mode To change from FEI or FBI clock modes to FEE or FBE clock modes, follow this procedure: 1. Enable the external clock source by setting the appropriate bits in ICSC2. — If FBE will be the selected mode, also set the LP bit at this time to minimize power consumption. 2. If necessary, wait for the external clock source to stabilize. Typical crystal startup times are given in Electrical Characteristics appendix. If EREFS is set in step 1, then the OSCINIT bit will set as soon as the oscillator has completed the initialization cycles. 3. Write to ICSC1 to select the clock mode. MC9S08QD4 Series MCU Data Sheet, Rev. 3 134 Freescale Semiconductor Internal Clock Source (S08ICSV1) — If entering FEE, set the reference divider and clear the IREFS bit to switch to the external reference. — The internal reference can optionally be kept running by setting the IRCLKEN bit. This is useful if the application will switch back and forth between internal clock and external clock modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode. 4. The CLKST bits can be monitored to determine when the mode switch has completed. If FEE was selected, the bus clock will be stable in tAcquire milliseconds. The CLKST bits will not change when switching from FEI to FEE. 9.5.1.2 Initialization Sequence, External Clock Mode to Internal Clock Mode To change from FEE or FBE clock modes to FEI or FBI clock modes, follow this procedure: 1. If saved, copy the TRIM and FTRIM values from FLASH to the ICSTRM and ICSSC registers. This needs to be done only once after POR. 2. Enable the internal clock reference by selecting FBI (CLKS = 0:1) or selecting FEI (CLKS = 0:0, RDIV = 0:0:0, and IREFS = 1) in ICSC1. 3. Wait for the internal clock reference to stabilize. The typical startup time is given in the Electrical Characteristics appendix. 4. Write to ICSC2 to disable the external clock. — The external reference can optionally be kept running by setting the ERCLKEN bit. This is useful if the application will switch back and forth between internal clock and external clock modes. For minimum power consumption, leave the external reference disabled while in an internal clock mode. — If FBI will be the selected mode, also set the LP bit at this time to minimize power consumption. NOTE The internal reference must be enabled and running before disabling the external clock. Therefore it is imperative to execute steps 2 and 3 before step 4. 5. The CLKST bits in the ICSSC register can be monitored to determine when the mode switch has completed. The CLKST bits will not change when switching from FEE to FEI. If FEI was selected, the bus clock will be stable in tAcquire milliseconds. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 135 Internal Clock Source (S08ICSV1) MC9S08QD4 Series MCU Data Sheet, Rev. 3 136 Freescale Semiconductor Chapter 10 Keyboard Interrupt (S08KBIV2) 10.1 Introduction The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources. Only four (KBI1P0–KBI1P3) of the possible interrupts are implemented on the MC9S08QD4 series MCU. These inputs are selected by the KBIPE bits. Figure 10-1 Shows the MC9S08QD4 series with the KBI module and pins highlighted. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 137 Chapter 10 Keyboard Interrupt (S08KBIV2) BKGD/MS IRQ HCS08 CORE CPU BDC 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) 4 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD PORT A TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA0/KBI1P0/TPM1CH0/ADC1P0 USER FLASH 4096 / 2048 BYTES 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 USER RAM 256 / 128 BYTES 16 MHz INTERNAL CLOCK SOURCE (ICS) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL NOTES: 1 Port pins are software configurable with pullup device if input port. 2 Port pins are software configurable for output drive strength. 3 Port pins are software configurable for output slew rate control. 4 IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1). 5 RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). 6 PTA5 does not contain a clamp diode to V DD and must not be driven above VDD. The voltage measured on this pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD. 7 PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). 8 When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 10-1. MC9S08QD4 Series Block Diagram Highlighting KBI Block and Pins MC9S08QD4 Series MCU Data Sheet, Rev. 3 138 Freescale Semiconductor Keyboard Interrupts (S08KBIV2) 10.1.1 Features The KBI features include: • Up to eight keyboard interrupt pins with individual pin enable bits. • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. • One software enabled keyboard interrupt. • Exit from low-power modes. 10.1.2 Modes of Operation This section defines the KBI operation in wait, stop, and background debug modes. 10.1.2.1 KBI in Wait Mode The KBI continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is enabled (KBIE = 1). 10.1.2.2 KBI in Stop Modes The KBI operates asynchronously in stop3 mode if enabled before executing the STOP instruction. Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of stop3 mode if the KBI interrupt is enabled (KBIE = 1). During either stop1 or stop2 mode, the KBI is disabled. In some systems, the pins associated with the KBI may be sources of wakeup from stop1 or stop2, see the stop modes section in the Modes of Operation chapter. Upon wake-up from stop1 or stop2 mode, the KBI module will be in the reset state. 10.1.2.3 KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 10.1.3 Block Diagram The block diagram for the keyboard interrupt module is shown Figure 10-2. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 139 Keyboard Interrupts (S08KBIV2) KBACK 1 VDD S KBIPE0 D CLR Q CK KBEDG0 1 KEYBOARD INTERRUPT FF S KBIPEn KBMOD STOP RESET BUSCLK KBF SYNCHRONIZER KBIP0 0 STOP BYPASS KBIPn KBEDGn 0 KBI INTERRU PT KBIE Figure 10-2. KBI Block Diagram 10.2 External Signal Description The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests. The signal properties of KBI are shown in Table 10-1. Table 10-1. Signal Properties Signal KBIPn Function Keyboard interrupt pins I/O I 10.3 Register Definition The KBI includes three registers: • An 8-bit pin status and control register. • An 8-bit pin enable register. • An 8-bit edge select register. Refer to the direct-page register summary in the Memory chapter for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. Some MCUs may have more than one KBI, so register names include placeholder characters to identify which KBI is being referenced. 10.3.1 KBI Status and Control Register (KBISC) KBISC contains the status flag and control bits, which are used to configure the KBI. MC9S08QD4 Series MCU Data Sheet, Rev. 3 140 Freescale Semiconductor Keyboard Interrupts (S08KBIV2) 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 KBF 0 KBIE KBACK KBMOD 0 0 0 = Unimplemented 0 0 0 0 0 Figure 10-3. KBI Status and Control Register Table 10-2. KBISC Register Field Descriptions Field 7:4 3 KBF 2 KBACK 1 KBIE 0 KBMOD Unused register bits, always read 0. Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF. 0 No keyboard interrupt detected. 1 Keyboard interrupt detected. Keyboard Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads as 0. Keyboard Interrupt Enable — KBIE determines whether a keyboard interrupt is requested. 0 Keyboard interrupt request not enabled. 1 Keyboard interrupt request enabled. Keyboard Detection Mode — KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard interrupt pins.0Keyboard detects edges only. 1 Keyboard detects both edges and levels. Description 10.3.2 KBI Pin Enable Register (KBIPE) KBIPE contains the pin enable control bits. 7 6 5 4 3 2 1 0 R KBIPE7 W Reset: 0 0 0 0 0 0 0 0 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 Figure 10-4. KBI Pin Enable Register Table 10-3. KBIPE Register Field Descriptions Field 7:0 KBIPEn Description Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. 10.3.3 KBI Edge Select Register (KBIES) KBIES contains the edge select control bits. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 141 Keyboard Interrupts (S08KBIV2) 7 6 5 4 3 2 1 0 R KBEDG7 W Reset: 0 0 0 0 0 0 0 0 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 Figure 10-5. KBI Edge Select Register Table 10-4. KBIES Register Field Descriptions Field 7:0 KBEDGn Description Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 Falling edge/low level. 1 Rising edge/high level. 10.4 Functional Description This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes. The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPEn bits in the keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin. Each KBI pin can be configured as edge sensitive or edge and level sensitive based on the KBMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES). 10.4.1 Edge Only Sensitivity Synchronous logic is used to detect edges. A falling edge is detected when an enabled keyboard interrupt (KBIPEn=1) input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 (the deasserted level) during one bus cycle and then a logic 1 (the asserted level) during the next cycle.Before the first edge is detected, all enabled keyboard interrupt input signals must be at the deasserted logic levels. After any edge is detected, all enabled keyboard interrupt input signals must return to the deasserted level before any new edge can be detected. A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC. 10.4.2 Edge and Level Sensitivity A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in MC9S08QD4 Series MCU Data Sheet, Rev. 3 142 Freescale Semiconductor Keyboard Interrupts (S08KBIV2) KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK. 10.4.3 KBI Pullup/Pulldown Resistors The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register. If an internal resistor is enabled, the KBIES register is used to select whether the resistor is a pullup (KBEDGn = 0) or a pulldown (KBEDGn = 1). 10.4.4 KBI Initialization When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. To prevent a false interrupt request during keyboard initialization, the user must do the following: 1. Mask keyboard interrupts by clearing KBIE in KBISC. 2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES. 3. If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 143 Keyboard Interrupts (S08KBIV2) MC9S08QD4 Series MCU Data Sheet, Rev. 3 144 Freescale Semiconductor Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.1 Introduction Figure 11-1 shows the MC9S08QD4 series block diagram with the TPM module and pins highlighted. 11.1.1 TPM2 Configuration Information The TPM2 module consist of a single channel, TPM2CH0, that is multiplexed with input pin PTA4 and output pin PTA5. When TPM2 is configured for input capture, the TPM2CH0 will connect to the PTA5 (TPM2CH0I). When TPM2 is configured for output compare, the TPM2CH0 will connect to the PTA4 (TPM2CH0O). When TPM2 is disabled, PTA4 and PTA5 function as standard port pins. 11.1.2 TCLK1 and TCLK2 Configuration Information The TCLK1 and TCLK2 are the external clock source inputs for TPM1 and TPM2 respectively. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 145 Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) BKGD/MS IRQ HCS08 CORE CPU BDC 4-BIT KEYBOARD INTERRUPT MODULE (KBI) 1-CH 16-BIT TIMER/PWM MODULE (TPM2) 2-CH 16-BIT TIMER/PWM MODULE (TPM1) 4 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD PORT A TPM2CH0 TCLK2 TPM1CH0 TPM1CH1 TCLK1 PTA5/TPM2CH0I/IRQ/RESET PTA4/TPM2CH0O/BKGD/MS PTA3/KBI1P3/TCLK2/ADC1P3 PTA2/KBI1P2/TCLK1/ADC1P2 PTA1/KBI1P1/TPM1CH1/ADC1P1 PTA0/KBI1P0/TPM1CH0/ADC1P0 USER FLASH 4096 / 2048 BYTES 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 4 USER RAM 256 / 128 BYTES 16 MHz INTERNAL CLOCK SOURCE (ICS) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL NOTES: 1 Port pins are software configurable with pullup device if input port. 2 Port pins are software configurable for output drive strength. 3 Port pins are software configurable for output slew rate control. 4 IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1). 5 RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). 6 PTA5 does not contain a clamp diode to V DD and must not be driven above VDD. The voltage measured on this pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD. 7 PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). 8 When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 11-1. MC9S08QD4 Series Block Diagram Highlighting TPM Block and Pins MC9S08QD4 Series MCU Data Sheet, Rev. 3 146 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) 11.1.3 Features The TPM has the following features: • Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all channels • Clock sources independently selectable per TPM (multiple TPMs device) • Selectable clock sources (device dependent): bus clock, fixed system clock, external pin • Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs device) • Channel features: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs 11.1.4 Block Diagram Figure 11-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 147 Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK XCLK TPMxCLK SYNC CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 CLKSB CPWMS MAIN 16-BIT COUNTER 16-BIT COMPARATOR CLKSA PS2 PS1 PS0 COUNTER RESET TOF TOIE INTERRUPT LOGIC TPMxMODH:TPMxMO CHANNEL 0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL 16-BIT LATCH MS0B MS0A CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A PORT LOGIC TPMxCH0 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TPMxC1VH:TPMxC1VL 16-BIT LATCH ELS1B ELS1A PORT LOGIC CH1F INTERRUPT LOGIC TPMxCH1 MS1B MS1A CH1IE ... ... CHANNEL n 16-BIT COMPARATOR TPMxCnVH:TPMxCnVL 16-BIT LATCH MSnB MSnA CHnIE CHnF ELSnB ELSnA ... PORT LOGIC TPMxCHn INTERRUPT LOGIC Figure 11-2. TPM Block Diagram The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter regardless of the data value written. MC9S08QD4 Series MCU Data Sheet, Rev. 3 148 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 11.2 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 11.2.1 External TPM Clock Sources When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and consequently the 16-bit counter for TPMx are driven by an external clock source, TPMxCLK, connected to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL) or frequency-locked loop (FLL) frequency jitter effects. On some devices the external clock input is shared with one of the TPM channels. When a TPM channel is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not trying to use the same pin. 11.2.2 TPMxCHn — TPMx Channel n I/O Pins Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). See the Pins and Connections chapter for additional information about shared pin functions. 11.3 Register Definition The TPM includes: • An 8-bit status and control register (TPMxSC) • A 16-bit counter (TPMxCNTH:TPMxCNTL) • A 16-bit modulo register (TPMxMODH:TPMxMODL) Each timer channel has: • An 8-bit status and control register (TPMxCnSC) • A 16-bit channel value register (TPMxCnVH:TPMxCnVL) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all TPM registers. This section refers to registers and control bits only by their names. A MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 149 Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 Timer Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R W Reset TOF TOIE 0 0 CPWMS 0 CLKSB 0 CLKSA 0 PS2 0 PS1 0 PS0 0 = Unimplemented or Reserved Figure 11-3. Timer Status and Control Register (TPMxSC) Table 11-1. TPMxSC Register Field Descriptions Field 7 TOF Description Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is generated when TOF equals 1. Reset clears TOIE. 0 TOF interrupts inhibited (use software polling) 1 TOF interrupts enabled Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS. 0 All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register 1 All TPMx channels operate in center-aligned PWM mode Clock Source Select — As shown in Table 11-2, this 2-bit field is used to disable the TPM system or select one of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the bus clock by an on-chip synchronization circuit. Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in Table 11-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the TPM system. 6 TOIE 5 CPWMS 4:3 CLKS[B:A] 2:0 PS[2:0] MC9S08QD4 Series MCU Data Sheet, Rev. 3 150 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) Table 11-2. TPM Clock Source Selection CLKSB:CLKSA 0:0 0:1 1:0 1:1 1 TPM Clock Source to Prescaler Input No clock selected (TPMx disabled) Bus rate clock (BUSCLK) Fixed system clock (XCLK) External source (TPMxCLK)1,2 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2 If the external clock input is shared with channel n and is selected as the TPM clock source, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so channel n does not try to use the same pin for a conflicting function. Table 11-3. Prescale Divisor Selection PS2:PS1:PS0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 TPM Clock Source Divided-By 1 2 4 8 16 32 64 128 11.3.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or TPMxCNTL, or any write to the timer status/control register (TPMxSC). Reset clears the TPM counter registers. 7 6 5 4 3 2 1 0 R W Reset Bit 15 14 13 12 11 10 9 Bit 8 Any write to TPMxCNTH clears the 16-bit counter. 0 0 0 0 0 0 0 0 Figure 11-4. Timer Counter Register High (TPMxCNTH) MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 151 Timer/Pulse-Width Modulator (S08TPMV2) 7 6 5 4 3 2 1 0 R W Reset Bit 7 6 5 4 3 2 1 Bit 0 Any write to TPMxCNTL clears the 16-bit counter. 0 0 0 0 0 0 0 0 Figure 11-5. Timer Counter Register Low (TPMxCNTL) When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 11.3.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock (CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits TOF and overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo disabled). 7 6 5 4 3 2 1 0 R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 Figure 11-6. Timer Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 11-7. Timer Counter Modulo Register Low (TPMxMODL) It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. MC9S08QD4 Series MCU Data Sheet, Rev. 3 152 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) 11.3.4 Timer Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R CHnF W Reset 0 0 0 0 0 0 CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 = Unimplemented or Reserved Figure 11-8. Timer Channel n Status and Control Register (TPMxCnSC) Table 11-4. TPMxCnSC Register Field Descriptions Field 7 CHnF Description Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event occurred on channel n Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE. 0 Channel n interrupt requests disabled (use software polling) 1 Channel n interrupt requests enabled Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 11-5. Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for input capture mode or output compare mode. Refer to Table 11-5 for a summary of channel mode and setup controls. Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown in Table 11-5, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin. 6 CHnIE 5 MSnB 4 MSnA 3:2 ELSn[B:A] MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 153 Timer/Pulse-Width Modulator (S08TPMV2) Table 11-5. Mode, Edge, and Level Selection CPWMS X 0 MSnB:MSnA XX 00 ELSnB:ELSnA 00 01 10 11 01 00 01 10 11 1X 1 XX 10 X1 10 X1 Edge-aligned PWM Center-aligned PWM Output compare Mode Configuration Pin not used for TPM channel; use as an external clock for the TPM or revert to general-purpose I/O Input capture Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up) If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. 11.3.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel value registers are cleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 Figure 11-9. Timer Channel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 11-10. Timer Channel Value Register Low (TPMxCnVL) In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written. MC9S08QD4 Series MCU Data Sheet, Rev. 3 154 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 11.4 Functional Description All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 11.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset. After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive. Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source for the TPM can be selected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate. Refer to Section 11.3.1, “Timer Status and Control Register (TPMxSC)” and Table 11-2 for more information about clock source selection. When the microcontroller is in active background mode, the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter. As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 155 Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1. The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the main 16-bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the first byte was read. The counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. The main timer counter can be reset manually at any time by writing any value to either byte of the timer count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. 11.4.2 Channel Mode Selection Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and buffered edge-aligned PWM. 11.4.2.1 Input Capture Mode With the input capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter into the channel value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. MC9S08QD4 Series MCU Data Sheet, Rev. 3 156 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) 11.4.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin. In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 11.4.2.3 Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible. As Figure 11-11 shows, the output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output compare forces the PWM signal high. OVERFLOW PERIOD PULSE WIDTH OVERFLOW OVERFLOW TPMxC OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 11-11. PWM Period and Pulse Width (ELSnA = 0) When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 157 Timer/Pulse-Width Modulator (S08TPMV2) 11.4.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width = 2 x (TPMxCnVH:TPMxCnVL) period = 2 x (TPMxMODH:TPMxMODL); for TPMxMODH:TPMxMODL = 0x0001–0x7FFF Eqn. 11-1 Eqn. 11-2 If the channel value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting period is much longer than required for normal applications. TPMxMODH:TPMxMODL = 0x0000 is a special case that must not be used with center-aligned PWM mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. Figure 11-12 shows the output compare value in the TPM channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. COUNT = OUTPUT COMPARE (COUNT DOWN) COUNT = 0 OUTPUT COMPARE (COUNT UP) COUNT = TPMxMODH:TPMx TPMxMODH:TPMx TPM1C PULSE WIDTH 2x 2x PERIOD Figure 11-12. CPWM Period and Pulse Width (ELSnA = 0) Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers, TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are MC9S08QD4 Series MCU Data Sheet, Rev. 3 158 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to PWM channels, not output compares. Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they will all update simultaneously at the start of a new period. Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 11.5 TPM Interrupts The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. See the Resets, Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine. 11.5.1 Clearing Timer Interrupt Flags TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1) followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 11.5.2 Timer Overflow Interrupt Description The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 159 Timer/Pulse-Width Modulator (S08TPMV2) 11.5.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in Section 11.5.1, “Clearing Timer Interrupt Flags.” When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section 11.5.1, “Clearing Timer Interrupt Flags.” 11.5.4 PWM End-of-Duty-Cycle Events For channels that are configured for PWM operation, there are two possibilities: • When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. • When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. The flag is cleared by the 2-step sequence described in Section 11.5.1, “Clearing Timer Interrupt Flags.” MC9S08QD4 Series MCU Data Sheet, Rev. 3 160 Freescale Semiconductor Chapter 12 Development Support 12.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip flash and other nonvolatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes). Debug is done through commands fed into the target MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. 12.1.1 Forcing Active Background The method for forcing active background mode depends on the specific HCS08 derivative. For the MC9S08QD4 series, you can force active background mode by holding the BKGD pin low as the MCU exits the reset condition independent of what caused the reset. If no debug pod is connected to the BKGD pin, the MCU will always reset into normal operating mode. 12.1.2 Module Configuration The alternative BDC clock source for MC9S08QD4 series is the ICGCLK. See Chapter 9, “Internal Clock Source (S08ICSV1),” for more information about ICGCLK and how to select clock sources. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 161 Development Support 12.1.3 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode 12.2 Background Debug Controller (BDC) All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • Active background mode commands require that the target MCU is in active background mode (the user program is not running). Active background mode commands allow the CPU registers to be read or written, and allow the user to trace one user instruction at a time, or GO to the user program from active background mode. • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET, and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. MC9S08QD4 Series MCU Data Sheet, Rev. 3 162 Freescale Semiconductor Development Support BKGD 1 NO CONNECT 3 NO CONNECT 5 2 GND 4 RESET 6 VDD Figure 12-1. BDM Tool Connector 12.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the user’s application program. This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer to Section 12.2.2, “Communication Details.” If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 12.2.2, “Communication Details,” for more detail. When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface. 12.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 163 Development Support when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles. Figure 12-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT TIME TARGET SENSES BIT LEVEL EARLIEST START OF NEXT BIT Figure 12-2. BDC Host-to-Target Serial Bit Timing Figure 12-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host must sample the bit level about 10 cycles after it started the bit time. MC9S08QD4 Series MCU Data Sheet, Rev. 3 164 Freescale Semiconductor Development Support BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 12-3. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 12-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 165 Development Support BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME SPEEDUP PULSE BKGD PIN 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 12-4. BDM Target-to-Host Serial Bit Timing (Logic 0) 12.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program. Table 12-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 12-1 to describe the coding structure of the BDC commands. MC9S08QD4 Series MCU Data Sheet, Rev. 3 166 Freescale Semiconductor Development Support / d AAAA RD WD RD16 WD16 SS CC RBKP WBKP = = = = = = = = = = = Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) separates parts of the command delay 16 target BDC clock cycles a 16-bit address in the host-to-target direction 8 bits of read data in the target-to-host direction 8 bits of write data in the host-to-target direction 16 bits of read data in the target-to-host direction 16 bits of write data in the host-to-target direction the contents of BDCSCR in the target-to-host direction (STATUS) 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 167 Development Support Table 12-1. BDC Command Summary Command Mnemonic SYNC ACK_ENABLE ACK_DISABLE BACKGROUND READ_STATUS WRITE_CONTROL READ_BYTE READ_BYTE_WS READ_LAST WRITE_BYTE WRITE_BYTE_WS READ_BKPT WRITE_BKPT GO TRACE1 TAGGO READ_A READ_CCR READ_PC READ_HX READ_SP READ_NEXT READ_NEXT_WS WRITE_A WRITE_CCR WRITE_PC WRITE_HX WRITE_SP WRITE_NEXT WRITE_NEXT_WS 1 Active BDM/ Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM n/a1 D5/d D6/d 90/d E4/SS C4/CC Coding Structure Description Request a timed reference pulse to determine target BDC communication speed Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled (ignore if ENBDM bit equals 0) Read BDC status from BDCSCR Write BDC controls in BDCSCR Read a byte from target memory Read a byte and report status Re-read byte from address just read and report status Write a byte to target memory Write a byte and report status Read BDCBKPT breakpoint register Write BDCBKPT breakpoint register Go to execute the user application program starting at the address currently in the PC Trace 1 user instruction at the address in the PC, then return to active background mode Same as GO but enable external tagging (HCS08 devices have no external tagging pin) Read accumulator (A) Read condition code register (CCR) Read program counter (PC) Read H and X register pair (H:X) Read stack pointer (SP) Increment H:X by one then read memory byte located at H:X Increment H:X by one then read memory byte located at H:X. Report status and data. Write accumulator (A) Write condition code register (CCR) Write program counter (PC) Write H and X register pair (H:X) Write stack pointer (SP) Increment H:X by one, then write memory byte located at H:X Increment H:X by one, then write memory byte located at H:X. Also report status. E0/AAAA/d/RD E1/AAAA/d/SS/RD E8/SS/RD C0/AAAA/WD/d C1/AAAA/WD/d/SS E2/RBKP C2/WBKP 08/d 10/d 18/d 68/d/RD 69/d/RD 6B/d/RD16 6C/d/RD16 6F/d/RD16 70/d/RD 71/d/SS/RD 48/WD/d 49/WD/d 4B/WD16/d 4C/WD16/d 4F/WD16/d 50/WD/d 51/WD/d/SS The SYNC command is a special operation that does not have a command code. MC9S08QD4 Series MCU Data Sheet, Rev. 3 168 Freescale Semiconductor Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16 cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128 BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 12.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. 12.3 Register Definition This section contains the descriptions of the BDC registers and control bits. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 169 Development Support This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 12.3.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For example, the ENBDM control bit may not be written while the MCU is in active background mode. (This prevents the ambiguous condition of the control bit forbidding active background mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08QD4 Series MCU Data Sheet, Rev. 3 170 Freescale Semiconductor Development Support 12.3.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 5 4 3 2 1 0 R ENBDM W Normal Reset Reset in Active BDM: 0 1 BDMACT BKPTEN 0 1 0 0 FTS 0 0 CLKSW 0 1 WS WSF DVF 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-5. BDC Status and Control Register (BDCSCR) Table 12-2. BDCSCR Register Field Descriptions Field 7 ENBDM Description Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands Background Mode Active Status — This is a read-only status bit. 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock source. 0 Alternate BDC clock source 1 MCU bus clock 6 BDMACT 5 BKPTEN 4 FTS 3 CLKSW MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 171 Development Support Table 12-2. BDCSCR Register Field Descriptions (continued) Field 2 WS Description Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host must issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. 0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to active background mode Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode Data Valid Failure Status — This status bit is not used in the MC9S08QD4 series because it does not have any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 1 WSF 0 DVF 12.3.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. Breakpoints are normally set while the target MCU is in active background mode before running the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section 12.2.4, “BDC Hardware Breakpoint.” 12.3.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. MC9S08QD4 Series MCU Data Sheet, Rev. 3 172 Freescale Semiconductor Development Support 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 BDFR1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 12-6. System Background Debug Force Reset Register (SBDFR) Table 12-3. SBDFR Register Field Description Field 0 BDFR Description Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 173 Development Support MC9S08QD4 Series MCU Data Sheet, Rev. 3 174 Freescale Semiconductor Appendix A Electrical Characteristics A.1 Introduction This chapter contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table A-1. Absolute Maximum Ratings Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range 1 Symbol VDD IDD VIn ID Tstg Value –0.3 to +5.8 120 –0.3 to VDD + 0.3 ± 25 –55 to 150 Unit V mA V mA °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 175 Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table A-2. Thermal Characteristics Rating Operating temperature range (packaged) Thermal resistance (single-layer board) 8-pin PDIP 8-pin NB SOIC Thermal resistance (four-layer board) 8-pin PDIP 8-pin NB SOIC Symbol TA Value TL to TH –40 to 125 113 150 72 87 Unit °C θJA °C/W θJA °C/W The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. A-1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O VDD Single pin limit Total MCU limit, includes sum of all stressed pins Input capacitance (all non-supply pins) 1 2 3 4 5 6 Symbol |IOZ| RPU RPD Min — 17.5 17.5 VDD – 1.5 VDD – 1.5 VDD – 0.8 VDD – 0.8 VDD – 1.5 VDD – 1.5 VDD – 0.8 VDD – 0.8 Typical 0.025 Max 1.0 52.5 52.5 Unit μA κW κW VOH — — — — — — — — — — — — — — — — — — — — — — — — V — — — — 100 60 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 100 60 mA mA |IOHT| — — — — — — — — — — VOL V IOLT |IIC| — — — — CIn — 0.2 5 7 mA mA pF RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR. This parameter is characterized and not tested on each device. Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 179 Appendix A Electrical Characteristics Typical Low-side Driver (LDS) Characteristics, VDD = 5.0 V, PORTA 14 12 10 IOL/mA 8 6 4 2 0 0 0.4 0.8 1.2 VOL/V 1.6 2 2.4 2.8 125 105 85 25 0 –40 Figure A-1. Typical Low-Side Driver (Sink) Characteristics Low Drive (PTxDSn = 0), VDD = 5.0V, VOL vs. IOL Typical Low-side Driver (LDS) Characteristics, VDD = 3.0 V, PORTA 6 125 5 4 IOL/mA 3 2 1 0 0 0.2 0.4 0.6 0.8 VOL/V 1 1.2 1.4 –1.6 105 85 25 0 –40 Figure A-2. Typical Low-Side Driver (Sink) Characteristics Low Drive (PTxDSn = 0), VDD = 3.0 V, VOL vs. IOL MC9S08QD4 Series MCU Data Sheet, Rev. 3 180 Freescale Semiconductor Appendix A Electrical Characteristics Typical Low-side Driver (HDS) Characteristics, VDD = 5.0 V, PORTA 40 35 30 IOL/mA 25 20 15 10 5 0 0 0.4 0.8 1.2 1.6 VOL/V 2 2.4 2.8 125 105 85 25 0 –40 Figure A-3. Typical Low-Side Driver (Sink) Characteristics High Drive (PTxDSn = 1), VDD = 5.0 V, VOL vs. IOL Typical Low-side Driver (HDS) Characteristics, VDD = 3.0 V, PORTA 14 12 10 IOL/mA 8 6 4 2 0 0 0.2 0.4 0.6 0.8 VOL/V 1 1.2 1.4 1.6 125 105 85 25 0 –40 Figure A-4. Typical Low-Side Driver (Sink) Characteristics High Drive (PTxDSn = 1), VDD = 3.0 V, VOL vs. IOL MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 181 Appendix A Electrical Characteristics Typical High-side Driver (LDS) Characteristics, VDD = 5.0 V, PORTA 0 –1 –2 IOH/mA –3 –4 –5 –6 –7 –8 2.4 2.8 3.2 3.6 4 VOH/V 4.4 4.8 5.2 125 105 85 25 0 –40 Figure A-5. Typical High-Side Driver (Source) Characteristics Low Drive (PTxDSn = 0), VDD = 5.0 V, VOH vs. IOH Typical High-side Driver (LDS) Characteristics, VDD = 3.0 V, PORTA 0 –0.5 –1 IOH/mA –1.5 –2 –2.5 –3 1.6 1.8 2 2.2 2.4 VOH/V 2.6 2.8 3 125 105 85 25 0 –40 Figure A-6. Typical High-Side Driver (Source) Characteristics Low Drive (PTxDSn = 0), VDD = 3.0 V, VOH vs. IOH MC9S08QD4 Series MCU Data Sheet, Rev. 3 182 Freescale Semiconductor Appendix A Electrical Characteristics Typical High-side Driver (HDS) Characteristics, VDD = 5.0 V, PORTA 0 –5 –10 IOH/mA –15 –20 –25 –30 2.4 2.8 3.2 4 3.6 VOH/V 4.4 4.8 5.2 125 105 85 25 0 –40 Figure A-7. Typical High-Side Driver (Source) Characteristics High Drive (PTxDSn = 1), VDD = 5.0 V, VOH vs. IOH Typical High-side Driver (HDS) Characteristics, VDD = 3.0 V, PORTA 0 –2 –4 IOH/mA –6 –8 –10 –12 1.6 1.8 2 2.2 2.4 VOH/V 2.6 2.8 3 125 105 85 25 0 –40 Figure A-8. Typical High-Side Driver (Source) Characteristics High Drive (PTxDSn = 1), VDD = 3.0 V, VOH vs. IOH MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 183 Appendix A Electrical Characteristics A.6 Supply Current Characteristics Table A-6. Supply Current Characteristics Parameter Symbol RIDD RIDD WIDD This section includes information about power supply current in various operating modes VDD (V) 5 3 5 3 5 3 Typical1 0.95 0.90 3.5 3.4 1.55 1.50 Max2 1.54 1.5 56 5 2.2 2.2 Unit mA Run supply current3 measured at (CPU clock = 2 MHz, fBus = 1 MHz) Run supply current5 measured at (CPU clock = 16 MHz, fBus = 8 MHz) Wait mode supply current7 measured at (CPU clock = 16 MHz, fBus = 8 MHz) Stop2 mode supply current (Consumer and Industrial MC9S08QDx) –40 to 85°C –40 to 125°C –40 to 85°C –40 to 125°C Stop2 mode supply current (Automotive S9S08QDx) –40 to 85°C –40 to 125°C –40 to 85°C –40 to 125°C Stop3 mode supply current (Consumer and Industrial MC9S08QDx) –40 to 85° C –40 to 125°C –40 to 85° C –40 to 125°C Stop3 mode supply current (Automotive S9S08QDx) –40 to 85° C –40 to 125°C –40 to 85° C –40 to 125°C RTI adder to stop2 or stop310, 25°C LVD adder to stop3 (LVDE = LVDSE = 1) Adder to stop3 for oscillator enabled (IREFSTEN = 1) 1 2 mA mA 5 0.80 7.58 20 4 7.08 15 μA 3 S2IDD 5 0.80 μA 0.80 7.59 25 4 7.08 20 μA 3 0.80 μA 5 0.90 8.08 254 7.18 20 μA 3 S3IDD s 5 0.90 μA 0.90 8.08 304 7.18 25 μA 3 5 3 5 3 5 3 0.90 400 350 110 90 75 65 μA nA nA μA μA μA μA Typicals are measured at 25°C. Values given here are preliminary estimates prior to completing characterization. MC9S08QD4 Series MCU Data Sheet, Rev. 3 184 Freescale Semiconductor Appendix A Electrical Characteristics 3 4 All modules except ADC active, and does not include any dc loads on port pins Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. 5 All modules except ADC active, and does not include any dc loads on port pins 6 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. 7 Most customers are expected to find that the auto-wakeup from a stop mode can be used instead of the higher current wait mode. 8 This parameter is characterized and not tested on each device. 9 This parameter is characterized and not tested on each device. 10 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Wait mode typical is 560 μA at 3 V with fBus = 1 MHz. Typical RIDD (VDD=5.0 V, ADC off) vs. Bus Freq. 4.00 3.50 3.00 RIDD/mA 2.50 2.00 1.50 1.00 0.50 0.00 0 2 4 Bus/MHz 6 8 10 125 105 85 25 0 –40 Figure A-9. Typical Run IDD vs. Bus Freq. (FEI) (ADC off) MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 185 Appendix A Electrical Characteristics A.7 Internal Clock Source Characteristics Table A-7. Internal Clock Source Specifications Characteristic Symbol fint_ut fint_t fdco_ut fdco_t Min 25 — 12.8 — — Δfdco_res_t — — ± 0.3 ± 0.2 Typ1 31.25 31.25 16 16 — Max 41.66 — 21.33 — ± 0.2 %fdco Unit kHz kHz MHz MHz Average internal reference frequency - untrimmed Average internal reference frequency - trimmed DCO output frequency range - untrimmed DCO output frequency range - trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature (Consumer and Industrial MC9S08QDx)2 Resolution of trimmed DCO output frequency at fixed voltage and temperature (Automotive S9S08QDx)2 –40°C to 0°C 0 to 125°C Total deviation of trimmed DCO output frequency over voltage and temperature 2 Consumer and Industrial MC9S08QDx Automotive S9S08QDx FLL acquisition time 2,3 Long term Jitter of DCO output clock (averaged over 2 ms interval) 4 1 2 Δfdco_t — — ±2 ±3 1 %fdco tacquire CJitter — — ms %fdco 0.6 Data in Typical column was characterized at 3.0 V and 3.0 V, 25°C or is typical recommended value. Characterized, but not tested. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f BUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. MC9S08QD4 Series MCU Data Sheet, Rev. 3 186 Freescale Semiconductor Appendix A Electrical Characteristics Deviation of DCO Output from Trimmed Frequency (8 MHz, 5.5 V) 0.80% 0.70% 0.60% 0.50% 0.40% Deviation 0.30% 0.20% 0.10% 0.00% –0.10% –0.20% –0.30% –0.40% –40 –20 0 20 40 60 Temp. /C 80 100 120 140 Figure A-10. Typical Deviation of DCO Output vs. Temperature Deviation of DCO Output from Trimmed Frequency (8 MHz, 25 °C) 0.20% 0.15% 0.10% Deviation 0.05% 0.00% –0.05% –0.10% –0.15% –0.20% 2.5 3 3.5 4 VDD / V 4.5 5 5.5 6 Figure A-11. Typical Deviation of DCO Output vs. Operating Voltage MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 187 Appendix A Electrical Characteristics A.8 AC Characteristics This section describes AC timing characteristics for each peripheral system. A.8.1 Control Timing Table A-8. Control Timing Parameter Symbol fBus tRTI textrst tILIH, tIHIL Min 1 700 100 100 1.5 tcyc 100 1.5 tcyc — — tMSSU tMSH 500 100 Typical1 — — — Max 8 1300 — Unit MHz μs ns ns Bus frequency (tcyc = 1/fBus) Real-time interrupt internal oscillator period External reset pulse width2 IRQ pulse width Asynchronous path2 Synchronous path3 KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 5 1 2 — — tILIH, tIHIL tRise, tFall — — ns 3 30 — — — — — — ns ns μs Data in Typical column was characterized at 3.0 V, 25°C. This is the shortest pulse that is guaranteed to be recognized. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 125°C. 5 To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. textrst RESET PIN Figure A-12. Reset Timing MC9S08QD4 Series MCU Data Sheet, Rev. 3 188 Freescale Semiconductor Appendix A Electrical Characteristics tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure A-13. IRQ/KBIPx Timing A.8.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-9. TPM/MTIM Input Timing Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit MHz tcyc tcyc tcyc tcyc tText tclkh TCLK tclkl Figure A-14. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure A-15. Timer Input Capture Pulse MC9S08QD4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 189 Appendix A Electrical Characteristics A.9 ADC Characteristics Table A-10. ADC Characteristics Conditions VDDAD < 3.6 V (3.0 V Typ) VDDAD < 5.5 V (5.0 V Typ) VDDAD < 3.6 V (3.0 V Typ) VDDAD < 5.5 V (5.0 V Typ) VDDAD < 3.6 V (3.0 V Typ) VDDAD < 5.5 V (5.0 V Typ) VDDAD < 3.6V (3.0 V Typ) VDDAD < 5.5V (5.0 V Typ) Stop, Reset, Module Off IDDAD IDDAD VREFH VREFL High Speed (ADLPC = 0) Low Power (ADLPC = 1) High Speed (ADLPC = 0) Low Power (ADLPC = 1) Short Sample (ADLSMP = 0) Long Sample (ADLSMP = 1) tADC fADCK fADACK IDDAD IDDAD IDDAD Symb Min — — — — — — — — — 2.7 VSSAD 0.4 0.4 2.5 1.25 20 40 4 24 VREFL — — — 2.637 10.547 0 0 0 0 0 0 Typ1 110 130 200 220 320 360 580 660