MC9S08QE8C32

Freescale Semiconductor Data Sheet: Advance Information Document Number: MC9S08QE8 Rev. 3, 1/2008 MC9S08QE8 Series Covers: MC9S08QE8 and MC9S08QE4 Features • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of –40°C to 85°C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources • On-Chip Memory – Flash read/program/erase over full operating voltage and temperature – Random-Access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two low power stop modes – Reduced power wait mode – Low power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents – Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter – 6 μs typical wake-up time from stop3 mode • Clock Source Options – Oscillator (XOSC) — Loop-Control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting bus frequencies from 1 MHz to 10 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-Voltage warning with interrupt – Low-Voltage detection with reset or interrupt – Illegal opcode detection with reset – Illegal address detection with reset – Flash block protection • Development Support – Single-Wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) – On-Chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes; eight deep FIFO for storing change-of-flow addresses and event-only data; debug module supports both tag and force breakpoints 32-Pin LQFP Case 873A 20-Pin SOIC 751D-07 16-Pin PDIP 648 28-Pin SOIC 751F-05 16-Pin TSSOP 948F • Peripherals – ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V – ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 – SCI — Full-Duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake-up on active edge – SPI — Full-Duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting – IIC — Up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supporting broadcast mode and 10-bit addressing – TPMx — Two 3-channel (TPM1 and TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – RTC — (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components; runs in all MCU modes • Input/Output – 26 GPIOs, one output-only pin and one input-only pin – Eight KBI interrupts with selectable polarity – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins. • Package Options – 32-pin LQFP, 28-pin SOIC, 20-pin SOIC, 16-pin PDIP, 16-pin TSSOP This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2007–2008. All rights reserved. Preliminary Subject to Change Without Notice Table of Contents 1 2 3 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 8 3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 8 3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . 9 3.5 ESD Protection and Latch-Up Immunity . . . . . . 10 3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 11 3.7 Supply Current Characteristics . . . . . . . . . . . . . 15 3.8 External Oscillator (XOSCVLP) Characteristics 16 3.9 Internal Clock Source (ICS) Characteristics . . . 17 3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 18 3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 19 3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 20 3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .20 Analog Comparator (ACMP) Electricals . . . . . . .23 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .24 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .27 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .28 3.14.1Conducted Transient Susceptibility. . . . . .28 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .29 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .29 3.11 3.12 3.13 3.14 4 5 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev 2 3 Date 7 Nov 2007 22 Jan 2008 Description of Changes Initial preliminary product preview release. Initial public release. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08QE8RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08QE8 Series, Rev. 3 2 Preliminary Subject to Change Without Notice Freescale Semiconductor MCU Block Diagram 1 MCU Block Diagram BKGD/MS The block diagram, Figure 1, shows the structure of MC9S08QE8 series MCU. HCS08 CORE CPU BDC DEBUG MODULE (DBG) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ LVD REAL-TIME COUNTER (RTC) SCL IRQ SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) RxD TxD SS MISO MOSI SPSCK USER FLASH (MC9S08QE8 = 8192 BYTES) (MC9S08QE4 = 4096 BYTES) USER RAM (MC9S08QE8 = 512 BYTES) (MC9S08QE4 = 256 BYTES) PORT A IIC MODULE (IIC) SDA PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TCLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 PTA1/KBIP1/TPM2CH0/ADP1/ACMP1– PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS SERIAL PERIPHERAL INTERFACE MODULE (SPI) PORT B 16-BIT TIMER PWM MODULE (TPM1) TCLK TPM1CH0 TPM1CH1 TPM1CH2 TCLK TPM2CH0 TPM2CH1 TPM2CH2 PTB4/TPM2CH1/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 PTC7/ACMP2– PTC6/ACMP2+ PTC5/ACMP2O 20 MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSCVLP) VSS VDD VOLTAGE REGULATOR EXTAL XTAL VSSA VDDA VSSA VDDA VSSA/VREFL VDDA/VREFH VREFL VREFH 16-BIT TIMER PWM MODULE (TPM2) PORT C ANALOG COMPARATOR (ACMP1) ANALOG COMPARATOR (ACMP2) 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC12) ACMP1O ACMP1– ACMP1+ ACMP2O ACMP2– ACMP2+ PTC4 PTC3 PTC2 PTC1/TPM2CH2 PTC0/TPM1CH2 PTD3 PORT D ADP9–ADP0 PTD2 PTD1 PTD0 KEYBOARD INTERRUPT MODULE (KBI) KBIP7–KBIP0 pins not available on 16-pin packages pins not available on 16-pin or 20-pin packages pins not available on 16-pin, 20-pin or 28-pin packages Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pullup device. When PTA4 is configured as BKGD, pin becomes bi-directional. For the 16-pin and 20-pin packages, VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively. Figure 1. MC9S08QE8 Series Block Diagram MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 3 Pin Assignments 2 Pin Assignments PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ 26 PTA1/KBIP1/TPM2CH0ADP1/ACMP1– 25 24 PTA2/KBIP2/SDA/ADP2 23 PTA3/KBIP3/SCL/ADP3 22 PTD2 21 PTD3 20 PTA6/TPM1CH2/ADP8 19 PTA7/TPM2CH2/ADP9 18 PTB0/KBIP4/RxD/ADP4 17 PTB1/KBIP5/TxD/ADP5 9 PTB5/TPM1CH1/SS 10 PTB4/TPM2CH1/MISO 16 PTB2/KBIP6/SPSCK/ADP6 This section shows the pin assignments for the MC9S08QE8 series devices. PTA4/ACMP1O/BKGD/MS PTA5/IRQ/TCLK/RESET PTC5/ACMP2O PTC6/ACMP2+ 28 PTC4 32 PTD1 1 PTD0 2 VDD 3 VDDA/VREFH 4 VSSA/VREFL 5 VSS 6 PTB7/SCL/EXTAL 7 PTB6/SDA/XTAL 8 31 30 29 PTC7/ACMP2– 27 14 PTC0/TPM1CH2 11 PTC3 12 PTC2 13 PTC1/TPM2CH2 15 PTB3/KBIP7/MOSI/ADP7 Pins shown in bold type are lost in the next lower pin count package. Figure 2. MC9S08QE8 Series in 32-LQFP MC9S08QE8 Series, Rev. 3 4 Preliminary Subject to Change Without Notice Freescale Semiconductor Pin Assignments PTC5/ACMP2O PTC4 PTA5/IRQ/TCLK/RESET PTA4/ACMP1O/BKGD/MS VDD VDDA/VREFH VSSA/VREFL VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3 PTC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PTC6/ACMP2+ PTC7/ACMP2– PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTA1/KBIP1/TPM2CH0/ADP1/ACMP1– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 PTC0/TPM1CH2 PTC1/TPM2CH2 Pins shown in bold type are lost in the next lower pin count package. Figure 3. MC9S08QE8 Series in 28-pin SOIC Package PTA5/IRQ/TCLK/RESET PTA4/ACMP1O/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3 PTC2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTA1/KBIP1/TPM2CH0/ADP1/ACMP1– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 PTC0/TPM1CH2 PTC1/TPM2CH2 Pins shown in bold type are lost in the next lower pin count package. Figure 4. MC9S08QE8 Series in 20-pin SOIC Package MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 5 Pin Assignments PTA5/IRQ/TCLK/RESET PTA4/ACMP1O/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTA0/KBIP0/TPM1CH0/ADP0/ACMP1+ PTA1/KBIP1/TPM2CH0ADP1/ACMP1– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 Figure 5. MC9S08QE8 Series in 16-pin PDIP and TSSOP Packages MC9S08QE8 Series, Rev. 3 6 Preliminary Subject to Change Without Notice Freescale Semiconductor Pin Assignments Table 2-1. Pin Availability by Package Pin-Count Pin Number 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 Highest Alt 3 Alt 4 28 — — 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 — — 23 24 25 26 27 28 1 2 3 4 20 — — 3 — — 4 5 6 7 8 9 10 11 12 13 14 15 16 — — — — 17 18 19 20 — — — — 1 2 Port Pin PTD1 PTD0 Alt 1 VDD VDDA/VREFH VSSA/VREFL VSS SCL 1 1 EXTAL XTAL SS MISO SDA TPM1CH1 TPM2CH1 MOSI SPSCK TxD RxD ADP7 ADP6 ADP5 ADP4 ADP9 ADP8 SCL1 SDA 1 ADP3 ADP2 ACMP1–4 ACMP1+4 ACMP2– ACMP2+ ACMP2O ADP04 TPM2CH0 ADP14 TPM1CH0 TCLK BKGD RESET MS IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2, default reset locations are PTA3 and PTA2. 2 TPM2CH2 pin can be repositioned using TPM2CH2PS in SOPT2, default reset location is PTA7. 3 TPM1CH2 pin can be repositioned using TPM1CH2PS in SOPT2, default reset location is PTA6. 4 If ADC and ACMP1 are enabled, both modules will have access to the pin. MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 7 Electrical Characteristics 3 3.1 Electrical Characteristics Introduction This section contains electrical and timing specifications for the MC9S08QE8 series of microcontrollers available at the time of publication. 3.2 Parameter Classification Table 2. Parameter Classifications P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: T D NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Table 3. Absolute Maximum Ratings Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range Symbol VDD IDD VIn ID Tstg Value –0.3 to 3.8 120 –0.3 to VDD + 0.3 ±25 –55 to 150 Unit V mA V mA °C MC9S08QE8 Series, Rev. 3 8 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 4. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 32-pin LQFP 28-pin SOIC 20-pin SOIC 16-pin PDIP 16-pin TSSOP Thermal resistance Four-layer board 32-pin LQFP 28-pin SOIC 20-pin SOIC 16-pin PDIP 16-pin TSSOP θJA 47 42 52 47 78 °C/W θJA 66 57 71 64 108 °C/W Symbol TA TJM Value TL to TH –40 to 85 95 Unit °C °C The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) where: Eqn. 1 MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 9 Electrical Characteristics TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 1.8 V, ILoad = –2 mA VOH VDD > 2.7 V, ILoad = –10 mA VDD > 1.8V, ILoad = –2 mA IOHT — VDD > 1.8 V, ILoad = 0.6 mA VOL VDD > 2.7 V, ILoad = 10 mA VDD > 1.8 V, ILoad = 3 mA IOLT VIH VIL Vhys |IIn| — VDD > 2.7 V VDD > 1.8 V VDD > 2.7 V VDD > 1.8 V — VDD – 0.5 VDD – 0.5 VDD – 0.5 — — — — — 0.70 x VDD 0.85 x VDD — — 0.06 x VDD — — — — — — — — — — — — — — — — — 100 0.5 0.5 0.5 100 — — 0.35 x VDD 0.30 x VDD — mV μA V mA V mA V 3 Max total IOH for all ports All I/O pins, low-drive strength All I/O pins, high-drive strength Max total IOL for all ports all digital inputs all digital inputs all digital inputs all input only pins (Per pin) P Input high C voltage P Input low C voltage C Input hysteresis 9 Input P leakage current Hi-Z (off-state) P leakage current Pullup, P Pulldown resistors VIn = VDD or VSS 0.1 1 10 all input/output (per pin) all digital inputs, when enabled (all I/O pins other than PTA5/IRQ/TCLK/RESET |IOZ| VIn = VDD or VSS — 0.1 1 μA 11a RPU, RPD — 17.5 — 52.5 kΩ MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 11 Electrical Characteristics Table 7. DC Characteristics (continued) Num C Pullup, C Pulldown resistors DC injection C current 3, 4, 5 Characteristic Symbol RPU, RPD (Note ) 2 Condition Min. Typical1 Max. Unit 11b (PTA5/IRQ/TCLK/RESET) — 17.5 — 52.5 kΩ Single pin limit Total MCU limit, includes sum of all stressed pins IIC CIn VRAM VPOR tPOR VLVD VLVW Vhys VBG VIN < VSS, VIN > VDD — — — — VDD falling VDD rising VDD falling VDD rising — — –0.2 –5 — — 0.9 10 1.80 1.88 2.08 — 1.15 — — — 0.6 1.4 — 1.84 1.92 2.14 80 1.17 0.2 5 8 1.0 2.0 — 1.88 1.96 2.24 — 1.18 mA mA pF V V μs V V mV V 12 13 14 15 16 17 18 19 20 1 2 3 4 5 C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage D POR re-arm time P Low-voltage detection threshold P Low-voltage warning threshold P Low-voltage inhibit reset/recover hysteresis 6 P Bandgap Voltage Reference7 6 7 Typical values are measured at 25°C. Characterized, not tested The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when measured externally on the pin. All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Factory trimmed at VDD = 3.0 V, Temp = 25 °C 40 PULL-UP RESISTOR (kΩ) 35 30 25 20 PULLUP RESISTOR TYPICALS PULLDOWN RESISTANCE (kΩ) 85°C 25°C –40°C 40 35 30 25 20 PULLDOWN RESISTOR TYPICALS 85°C 25°C –40°C 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 3.6 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) MC9S08QE8 Series, Rev. 3 12 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 1.2 1 0.8 VOL (V) 0.6 0.4 0.2 0 0 TYPICAL VOL VS IOL AT VDD = 3.0 V 85°C 25°C –40°C 0.2 0.15 VOL (V) 0.1 0.05 0 TYPICAL VOL VS VDD 85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA 5 10 IOL (mA) 15 20 1 2 VDD (V) 3 4 Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VOL VS IOL AT VDD = 3.0 V 85°C 25°C –40°C 1 0.8 0.6 VOL (V) TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 IOL = 3 mA 1 2 VDD (V) 3 4 IOL = 6 mA 85°C 25°C –40°C 0.4 0.2 0 0 10 IOL (mA) 20 30 IOL = 10 mA Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1) TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 85°C 25°C –40°C 1.2 1 VDD – VOH (V) 0.8 0.6 0.4 0.2 0 0 0.25 0.2 VDD – VOH (V) 0.15 0.1 0.05 0 TYPICAL VDD – VOH VS VDD AT SPEC IOH 85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA –5 –10 IOH (mA)) –15 –20 1 2 VDD (V) 3 4 Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 13 Electrical Characteristics TYPICAL VDD – VOH VS VDD AT SPEC IOH 85°C 25°C –40°C 0.4 0.8 TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V VDD – VOH (V) 0.6 0.4 0.2 0 0 VDD – VOH (V) 85°C 25°C –40°C 0.3 0.2 0.1 0 1 IOH = –10 mA IOH = –6 mA IOH = –3 mA 2 VDD (V) 3 4 –5 –10 –15 –20 IOH (mA) –25 –30 Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1) MC9S08QE8 Series, Rev. 3 14 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table 8. Supply Current Characteristics Num 1 C P T T T T 3 T T 4 T T 5 T 6 7 8 T T T P C P C T T T T T T T Stop3 adders: Stop2 and Stop 3 adders: Parameter Run supply current FEI mode, all modules on Run supply current FEI mode, all modules off Symbol RIDD RIDD Bus Freq 10 MHz 1 MHz 10 MHz 1 MHz 16 kHz FBILP 16 kHz FBELP 16 kHz FBILP 16 kHz FBELP 16 kHz FBILP 16 kHz FBELP 10 MHz 1 MHz 16 kHz FBELP — — — — — — — — — — — 3 3 3 VDD (V) Typical1 5.60 0.80 3.60 0.51 165 3 105 77 3 21 77 3 7.3 3 3 3 2 3 2 — — 570 290 1 300 250 400 350 — — — — 2500 2000 6000 5500 — — — — — — — μA μA nA –40 to 85°C –40 to 85°C –40 to 85°C –40 to 85°C –40 to 85°C –40 to 85°C — — μA –40 to 85°C — — μA –40 to 85°C Max 8.2 — — — — μA –40 to 85°C mA Unit mA Temp (°C) –40 to 85°C –40 to 85°C 2 Run supply current LPRS=0, all modules off RIDD Run supply current LPRS=1, all modules off; running from Flash RIDD Run supply current LPRS=1, all modules off; running from RAM Wait mode supply current FEI mode, all modules off Wait mode supply current LPRS = 1, all modules off Stop2 mode supply current Stop3 mode supply current no clocks active RTC using LPO RTC using low power crystal oscillator EREFSTEN=1 IREFSTEN=1 LVD ACMP2 ADC3 RIDD WIDD WIDD S2IDD S3IDD — — — — — — — 9 10 11 12 13 14 15 16 1 2 nA nA 200 500 300 70 –40 to 85°C nA nA μA μA μA μA –40 to 85°C –40 to 85°C 100 20 0.007 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Also applies to LPRun and LPWait modes. 3 ADC current measured on V DDA pin on 28-pin and 32-pin devices, adder to VDD on 16-pin and 20-pin packages. MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 15 Electrical Characteristics 3.8 External Oscillator (XOSCVLP) Characteristics Table 9. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient) Refer to Figure 11 and Figure 12 for crystal or resonator circuits. Num C Characteristic Symbol Min. Typical1 Max. Unit 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings flo fhi fhi C1,C2 32 1 1 — — — 38.4 16 8 kHz MHz MHz 2 D See Note2 See Note3 3 Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, high gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high gain C High range, low power High range, high gain Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode D FBE or FBELP mode t t RF — — — — — — — — — — — — — — 10 1 — 100 0 0 0 0 600 400 5 15 — — — — — — 0 10 20 — — — — MΩ 4 RS kΩ CSTL 5 ms CSTH 6 1 2 fextal 0.03125 0 — — 20 20 MHz MHz Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. MC9S08QE8 Series, Rev. 3 16 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics XOSCVLP EXTAL XTAL RS RF C1 Crystal or Resonator C2 Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Num 1 2 3 4 5 6 7 C P P T P P C C Internal Clock Source (ICS) Characteristics Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) Characteristic Average internal reference frequency — factory trimmed at VDD = 3.6 V and temperature = 25°C Internal reference frequency — user trimmed Internal reference start-up time DCO output frequency range — trimmed2 DCO output frequency2 Reference = 32768 Hz and DMX32 = 1 Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Symbol fint_ft fint_ut tIRST fdco_u fdco_DMX32 Δfdco_res_t Δfdco_res_t Min. — 31.25 — 48 — — — Typical1 32.768 — 60 — 59.77 ± 0.1 ± 0.2 Max. — 39.06 100 60 — ± 0.2 ± 0.4 Unit kHz kHz μs MHz MHz %fdco %fdco MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 17 Electrical Characteristics Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued) Num 8 9 10 11 1 2 C C C Characteristic Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0°C to 70 °C Symbol Δfdco_t Δfdco_t tAcquire CJitter Min. — — — — Typical1 + 0.5 -1.0 ± 0.5 — 0.02 Max. ±2 ±1 1 0.2 Unit %fdco %fdco ms %fdco C FLL acquisition time3 C Long term jitter of DCO output clock (averaged over 2-ms interval)4 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 1.00% 0.50% 0.00% Deviation (%) -60 -40 -20 -0.50% 0 20 40 60 80 100 120 -1.00% TBD Temperature -1.50% -2.00% Figure 13. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. MC9S08QE8 Series, Rev. 3 18 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.10.1 Num 1 2 3 4 5 6 C D D D D D D Control Timing Table 11. Control Timing Rating Bus frequency (tcyc = 1/fBus) Internal low power oscillator period External reset pulse width2 Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Symbol fBus tLPO textrst trstdrv tMSSU tMSH Min dc 700 100 34 x tcyc 500 100 Typical1 — — — — — — Max 10 1300 — — — — Unit MHz μs ns ns ns μs 7 D tILIH, tIHIL 100 1.5 × tcyc 100 1.5 × tcyc — — — — — — — — ns 8 D tILIH, tIHIL ns tRise, tFall — — 16 23 — — ns 9 C Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 1 2 tRise, tFall — — 5 9 — — ns Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 85°C. textrst RESET PIN Figure 14. Reset Timing MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 19 Electrical Characteristics tIHIL KBIPx IRQ/KBIPx tILIH Figure 15. IRQ/KBIPx Timing 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 12. TPM Input Timing No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit Hz tcyc tcyc tcyc tcyc tTCLK tclkh TCLK tclkl Figure 16. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 17. Timer Input Capture Pulse 3.10.3 SPI Timing Table 13 and Figure 18 through Figure 21 describe the timing requirements for the SPI system. MC9S08QE8 Series, Rev. 3 20 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 13. SPI Timing No. — C D Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol fop Min fBus/2048 0 2 4 1/2 1 1/2 1 tcyc – 30 tcyc – 30 15 15 0 25 — — — — 0 0 — — — — Max fBus/2 fBus/4 2048 — — — — — 1024 tcyc — — — — — 1 1 25 25 — — tcyc – 25 25 tcyc – 25 25 Unit Hz 1 D tSPSCK tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc ns ns ns ns ns ns ns ns 2 D tLead 3 D tLag 4 D tWSPSCK 5 D tSU 6 7 8 9 D D D D tHI ta tdis tv 10 D tHO 11 D tRI tRO tFI tFO 12 D MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 21 Electrical Characteristics SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) MSB IN2 9 MOSI (OUTPUT) MSB OUT2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 18. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT(2) MSB IN(2) 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 6 BIT 6 . . . 1 LSB IN 4 11 12 12 11 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 19. SPI Master Timing (CPHA =1) MC9S08QE8 Series, Rev. 3 22 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT) NOTE: 12 11 3 4 4 11 12 8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1 10 10 SEE NOTE SLAVE LSB OUT LSB IN 1. Not defined but normally MSB of character just received Figure 20. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) 2 12 3 11 4 4 11 12 9 SLAVE 5 MSB IN MSB OUT 6 10 BIT 6 . . . 1 SLAVE LSB OUT 8 BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 21. SPI Slave Timing (CPHA = 1) 3.11 C D P Analog Comparator (ACMP) Electricals Table 14. Analog Comparator Electrical Specifications Characteristic Symbol VDD IDDAC Min 1.8 — Typical — 20 Max 3.6 35 Unit V μA Supply voltage Supply current (active) MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 23 Electrical Characteristics Table 14. Analog Comparator Electrical Specifications (continued) C D P C P C Characteristic Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Symbol VAIN VAIO VH IALKG tAINIT Min VSS – 0.3 — 3.0 — — Typical — 20 9.0 — — Max VDD 40 15.0 1.0 1.0 Unit V mV mV μA μs 3.12 ADC Characteristics Table 15. 12-bit ADC Operating Conditions Conditions Absolute Delta to VDD (VDD-VDDAD)2 Symb VDDAD ΔVDDAD ΔVSSAD VREFH VADIN CADIN RADIN Min 1.8 –100 –100 1.8 VREFL — — Typ1 — 0 0 VDDAD — 4.5 5 Max 3.6 +100 +100 VDDAD VREFH 5.5 7 Unit V mV mV V V pF kΩ Comment — — — — — — — Characteristic Supply voltage Ground voltage Ref Voltage High Input Voltage Input Capacitance Input Resistance Analog Source Resistance Delta to VSS (VSS-VSSAD)2 — — — — 12 bit mode fADCK > 4MHz fADCK < 4MHz 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) — — RAS — — — 0.4 fADCK 0.4 — — — — — — — 2 5 kΩ 5 10 10 8.0 MHz 4.0 — External to MCU ADC Conversion Clock Freq. 1 High Speed (ADLPC=0) Low Power (ADLPC=1) Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. MC9S08QE8 Series, Rev. 3 24 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + – + – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 22. ADC Input Impedance Equivalency Diagram Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) C Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 ADC Asynchronous Clock Source Conditions Symbol Min. Typical1 Max. Unit Comment T — IDDAD — 120 — μA — T — IDDAD — 202 — μA — T — IDDAD — 288 — μA — P — IDDAD — 0.532 1 mA — P C High Speed (ADLPC=0) Low Power (ADLPC=1) fADACK 2 1.25 3.3 2 5 MHz 3.3 tADACK = 1/fADACK MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 25 Electrical Characteristics Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) C P C P Sample Time C T P T T P T T P T T C T T P T T P T Full-Scale Error Zero-Scale Error Integral Non-Linearity Differential Non-Linearity Total Unadjusted Error (28-pin and 32-pin packages) Total Unadjusted Error (16-pin and 20-pin package) Long Sample (ADLSMP=1) 12 bit mode 10 bit mode ETUE 8 bit mode 12 bit mode 10 bit mode ETUE 8 bit mode 12 bit mode 10 bit mode3 8 bit mode3 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode 8 bit mode 12 bit mode D Quantization Error 10 bit mode 8 bit mode EQ EFS EZS INL DNL — — — — — — — — — — — — — — — — ±0.7 ±1.75 ±0.5 ±0.3 ±1.5 ±0.5 ±0.3 ±1.5 ±0.5 ±0.5 ±1.0 ±0.5 ±0.5 –1 to 0 — — ±1.5 — ±1.0 ±0.5 — ±1.0 ±0.5 — ±1.5 ±0.5 — ±1 ±0.5 — ±0.5 ±0.5 LSB2 — LSB2 VADIN = VDDAD LSB2 VADIN = VSSAD LSB2 — LSB2 — — — — ±0.5 ±4.0 ±1.5 ±1.0 — ±3.5 LSB2 Characteristic Conversion Time (Including sample time) Conditions Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Short Sample (ADLSMP=0) tADS — — — 23.5 ±3.0 ±1 — — ±2.5 LSB2 For 28-pin and 32-pin packages only. Includes quantization For 16-pin and 20-pin packages only. Includes quantization tADC — — 40 3.5 — — ADCK cycles Symbol Min. — Typical1 20 Max. — ADCK cycles Unit Comment See ADC chapter in the QE8 Reference Manual for conversion time variances MC9S08QE8 Series, Rev. 3 26 Preliminary Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) C Characteristic Conditions 12 bit mode D Input Leakage Error 10 bit mode 8 bit mode D Temp Sensor Slope Temp Sensor Voltage –40°C to 25°C 25°C to 85°C 25°C m — VTEMP25 — 1.769 701.2 — — mV EIL Symbol Min. — — — — Typical1 ±2 ±0.2 ±0.1 1.646 Max. — ±4 ±1.2 — mV/°C LSB2 Pad leakage4 *RAS Unit Comment D 1 Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH – VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. 3.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table 17. Flash Characteristics C D D D D P P P P Characteristic Supply voltage for program/erase –40°C to 85°C Supply voltage for read operation Internal FCLK frequency1 location)2 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE — tD_ret — — 10,000 15 Min 1.8 1.8 150 5 Typical — — — — 9 4 4000 20,000 4 6 — 100,000 100 — — — — — Max 3.6 3.6 200 6.67 Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc mA mA cycles years Internal FCLK period (1/FCLK) Byte program time (random Byte program time (burst Page erase Mass erase time2 time2 current3 endurance4 current3 mode)2 Byte program Page erase C C 1 2 Program/erase TL to TH = –40°C to + 85°C T = 25°C Data retention5 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 27 Electrical Characteristics 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 3.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 3.14.1 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 18. Table 18. Conducted Susceptibility, EFT/B Parameter Symbol Conditions fOSC/fBUS Result A Conducted susceptibility, electrical fast transient/burst (EFT/B) VDD = 3.3 V TA = +25oC package type 32 LQFP 8 MHz crystal 8 MHz bus B C D 1 Amplitude1 (Min) 2.3 4.0 Unit VCS_EFT kV >4.0 >4.0 Data based on qualification test results. Not tested in production. The susceptibility performance classification is described in Table 19. Table 19. Susceptibility Performance Classification Result A B No failure Self-recovering failure Soft failure Performance Criteria The MCU performs as designed during and after exposure. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. C MC9S08QE8 Series, Rev. 3 28 Preliminary Subject to Change Without Notice Freescale Semiconductor Ordering Information Table 19. Susceptibility Performance Classification (continued) Result D Hard failure Performance Criteria The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation. E Damage 4 Ordering Information This section contains ordering information for the device numbering system. Example of the device numbering system: MC 9 S08 QE 8 Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family C XX Package designator (see Table 20) Temperature range (C = –40°C to 85°C) Approximate flash size in Kbytes 5 Package Information Table 20. Package Descriptions Pin Count 32 28 20 16 16 Package Type Low Quad Flat Package Small Outline Integrated Circuit Small Outline Integrated Circuit Plastic Dual In-line Package Thin Shrink Small Outline Package Abbreviation LQFP SOIC SOIC PDIP TSSOP Designator LC WL WJ PG TG Case No. 873A 751F 751D 648 948F Document No. 98ASH70029A 98ASB42345B 98ASB42343B 98ASB42431B 98ASH70247A 5.1 Mechanical Drawings The following pages are mechanical drawings for the packages described in Table 20. MC9S08QE8 Series, Rev. 3 Freescale Semiconductor Preliminary Subject to Change Without Notice 29 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007–2008. All rights reserved. Preliminary Subject to Change Without Notice