MC9S08QG8CDNE

MC9S08QG8 MC9S08QG4 Data Sheet HCS08 Microcontrollers MC9S08QG8 Rev. 5 11/2009 freescale.com MC9S08QG8/4 Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • 20-MHz HCS08 CPU (central processor unit) HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data Debug module supports both tag and force breakpoints Support for up to 32 interrupt/reset sources Peripherals • ADC — 8-channel, 10-bit analog-to-digital converter with automatic compare function, asynchronous clock source, temperature sensor, and internal bandgap reference channel; ADC is hardware triggerable using the RTI counter ACMP — Analog comparator module with option to compare to internal reference; output can be optionally routed to TPM module SCI — Serial communications interface module with option for 13-bit break capabilities SPI — Serial peripheral interface module IIC — Inter-integrated circuit bus module TPM— 2-channel timer/pulse-width modulator; each channel can be used for input capture, output compare, buffered edge-aligned PWM, or buffered center-aligned PWM MTIM — 8-bit modulo timer module with 8-bit prescaler KBI — 8-pin keyboard interrupt module with software selectable polarity on edge or edge/level modes • • • • • • • Memory Options • • FLASH read/program/erase over full operating voltage and temperature MC9S08QG8 — 8 Kbytes FLASH, 512 bytes RAM MC9S08QG4 — 4 Kbytes FLASH, 256 bytes RAM • • Power-Saving Modes • Wait plus three stops Input/Output • 12 general-purpose input/output (I/O) pins, one input-only pin and one output-only pin; outputs 10 mA each, 60 mA max for package Software selectable pullups on ports when used as input Software selectable slew rate control and drive strength on ports when used as output Internal pullup on RESET and IRQ pins to reduce customer system cost Clock Source Options • ICS — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz XOSC — Low-power oscillator module with software selectable crystal or ceramic resonator range, 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz, and supports external clock source input up to 20 MHz • • • • Development Support • • Single-wire background debug interface On-chip, in-circuit emulation (ICE) with real-time bus capture System Protection • Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock Low-voltage detection with reset or interrupt Illegal opcode detection with reset Illegal address detection with reset FLASH block protect Package Options • • • • • • • 24-pin quad flat no lead (QFN) package 16-pin plastic dual in-line package (PDIP) — MC9S08QG8 only 16-pin quad flat no lead (QFN) package 16-pin thin shrink small outline package (TSSOP) 8-pin dual flat no lead (DFN) package 8-pin PDIP — MC9S08QG4 only 8-pin narrow body small outline integrated circuit (SOIC) package • • • • MC9S08QG8 Data Sheet Covers MC9S08QG8 MC9S08QG4 MC9S08QG8 Rev. 5 11/2009 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev No. Revision Date Description of Changes Previous version was 1.01; revision numbering will increment by integers from now on. Clarified PTA5 pullup behavior note; clarified that FCDIV is write once after reset; expanded FPROT/NVPROT register description added note for servicing the COP if the COP is enabled during an erase function; added requirements for using ACMP0 in ACMP introduction; added factory trim value section to ICS introduction; debug section added to Development Support chapter; updated RTI period and added RTI graph to control timing section; other minor grammar edits. Added 24-pin QFN package and updated the A-5. DC Characteristics table Supply Voltage row. Incorporated core team markups from shared review. See Project Sync issue #3313 for archive. Added new part number information for the maskset revision 4. Corrected bit 0 of KBISC register in the Table 4-2. 2 Draft A 06/08/2006 3 4 5 10/2007 2/2008 11/2009 © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. This product incorporates SuperFlash® Technology licensed from SST. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 8 PRELIMINARY Freescale Semiconductor List of Chapters Chapter Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Appendix A Appendix B Title Page Device Overview ...................................................................... 19 External Signal Description .................................................... 23 Modes of Operation ................................................................. 33 Memory Map and Register Definition .................................... 39 Resets, Interrupts, and General System Control.................. 59 Parallel Input/Output Control.................................................. 77 Central Processor Unit (S08CPUV2) ...................................... 87 Analog Comparator (S08ACMPV2) ...................................... 107 Analog-to-Digital Converter (S08ADC10V1)........................ 115 Internal Clock Source (S08ICSV1)........................................ 143 Inter-Integrated Circuit (S08IICV1) ....................................... 155 Keyboard Interrupt (S08KBIV2) ............................................ 173 Modulo Timer (S08MTIMV1).................................................. 181 Serial Communications Interface (S08SCIV3)..................... 191 Serial Peripheral Interface (S08SPIV3) ................................ 211 Timer/Pulse-Width Modulator (S08TPMV2) ......................... 227 Development Support ........................................................... 243 Electrical Characteristics...................................................... 265 Ordering Information and Mechanical Drawings................ 289 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 7 Contents Section Number Title Page Chapter 1 Device Overview 1.1 Introduction ..................................................................................................................................... 19 1.1.1 Devices in the MC9S08QG8/4 Series ...............................................................................19 1.1.2 MCU Block Diagram.........................................................................................................20 Chapter 2 External Signal Description 2.1 2.2 Device Pin Assignment ................................................................................................................... 23 Recommended System Connections ............................................................................................... 25 2.2.1 Power .................................................................................................................................26 2.2.2 Oscillator (XOSC) .............................................................................................................27 2.2.3 Reset (Input Only) .............................................................................................................27 2.2.4 Background / Mode Select (BKGD/MS)...........................................................................28 2.2.5 General-Purpose I/O and Peripheral Ports.........................................................................28 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction ..................................................................................................................................... 33 Features ........................................................................................................................................... 33 Run Mode........................................................................................................................................ 33 Active Background Mode ............................................................................................................... 33 Wait Mode ....................................................................................................................................... 34 Stop Modes...................................................................................................................................... 35 3.6.1 Stop3 Mode........................................................................................................................35 3.6.2 Stop2 Mode........................................................................................................................36 3.6.3 Stop1 Mode........................................................................................................................37 3.6.4 On-Chip Peripheral Modules in Stop Modes.....................................................................37 Chapter 4 Memory Map and Register Definition 4.1 4.2 4.3 4.4 4.5 MC9S08QG8/4 Memory Map ........................................................................................................ 39 Reset and Interrupt Vector Assignments ......................................................................................... 40 Register Addresses and Bit Assignments........................................................................................ 41 RAM................................................................................................................................................ 45 FLASH ............................................................................................................................................ 46 4.5.1 Features ..............................................................................................................................47 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 9 Section Number Title Page 4.6 4.7 4.5.2 Program and Erase Times ..................................................................................................47 4.5.3 Program and Erase Command Execution ..........................................................................48 4.5.4 Burst Program Execution...................................................................................................49 4.5.5 Access Errors .....................................................................................................................51 4.5.6 FLASH Block Protection...................................................................................................51 4.5.7 Vector Redirection .............................................................................................................52 Security............................................................................................................................................ 52 FLASH Registers and Control Bits................................................................................................. 54 4.7.1 FLASH Clock Divider Register (FCDIV) .........................................................................54 4.7.2 FLASH Options Register (FOPT and NVOPT).................................................................55 4.7.3 FLASH Configuration Register (FCNFG) ........................................................................56 4.7.4 FLASH Protection Register (FPROT and NVPROT) .......................................................56 4.7.5 FLASH Status Register (FSTAT).......................................................................................57 4.7.6 FLASH Command Register (FCMD)................................................................................58 Chapter 5 Resets, Interrupts, and General System Control 5.1 5.2 5.3 5.4 5.5 Introduction ..................................................................................................................................... 59 Features ........................................................................................................................................... 59 MCU Reset...................................................................................................................................... 59 Computer Operating Properly (COP) Watchdog............................................................................. 60 Interrupts ......................................................................................................................................... 61 5.5.1 Interrupt Stack Frame ........................................................................................................62 5.5.2 External Interrupt Request Pin (IRQ) ................................................................................62 5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................63 Low-Voltage Detect (LVD) System ................................................................................................ 65 5.6.1 Power-On Reset Operation ................................................................................................65 5.6.2 LVD Reset Operation.........................................................................................................65 5.6.3 LVD Interrupt Operation....................................................................................................65 5.6.4 Low-Voltage Warning (LVW)............................................................................................65 Real-Time Interrupt (RTI) ............................................................................................................... 65 Reset, Interrupt, and System Control Registers and Control Bits................................................... 66 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC).............................................67 5.8.2 System Reset Status Register (SRS) ..................................................................................68 5.8.3 System Background Debug Force Reset Register (SBDFR).............................................69 5.8.4 System Options Register 1 (SOPT1) .................................................................................70 5.8.5 System Options Register 2 (SOPT2) .................................................................................71 5.8.6 System Device Identification Register (SDIDH, SDIDL).................................................72 5.8.7 System Real-Time Interrupt Status and Control Register (SRTISC).................................73 5.8.8 System Power Management Status and Control 1 Register (SPMSC1) ............................74 5.8.9 System Power Management Status and Control 2 Register (SPMSC2) ............................75 5.8.10 System Power Management Status and Control 3 Register (SPMSC3) ............................76 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 10 Freescale Semiconductor 5.6 5.7 5.8 Section Number Title Chapter 6 Parallel Input/Output Control Page 6.1 6.2 6.3 6.4 Port Data and Data Direction .......................................................................................................... 77 Pin Control — Pullup, Slew Rate, and Drive Strength ................................................................... 78 Pin Behavior in Stop Modes............................................................................................................ 79 Parallel I/O Registers ...................................................................................................................... 79 6.4.1 Port A Registers .................................................................................................................79 6.4.2 Port A Control Registers....................................................................................................80 6.4.3 Port B Registers .................................................................................................................83 6.4.4 Port B Control Registers ....................................................................................................84 Chapter 7 Central Processor Unit (S08CPUV2) 7.1 7.2 Introduction ..................................................................................................................................... 87 7.1.1 Features ..............................................................................................................................87 Programmer’s Model and CPU Registers ....................................................................................... 88 7.2.1 Accumulator (A) ................................................................................................................88 7.2.2 Index Register (H:X) .........................................................................................................88 7.2.3 Stack Pointer (SP) ..............................................................................................................89 7.2.4 Program Counter (PC) .......................................................................................................89 7.2.5 Condition Code Register (CCR) ........................................................................................89 Addressing Modes........................................................................................................................... 91 7.3.1 Inherent Addressing Mode (INH)......................................................................................91 7.3.2 Relative Addressing Mode (REL) .....................................................................................91 7.3.3 Immediate Addressing Mode (IMM).................................................................................91 7.3.4 Direct Addressing Mode (DIR) .........................................................................................91 7.3.5 Extended Addressing Mode (EXT) ...................................................................................92 7.3.6 Indexed Addressing Mode .................................................................................................92 Special Operations........................................................................................................................... 93 7.4.1 Reset Sequence ..................................................................................................................93 7.4.2 Interrupt Sequence .............................................................................................................93 7.4.3 Wait Mode Operation.........................................................................................................94 7.4.4 Stop Mode Operation.........................................................................................................94 7.4.5 BGND Instruction..............................................................................................................95 HCS08 Instruction Set Summary .................................................................................................... 96 7.3 7.4 7.5 Chapter 8 Analog Comparator (S08ACMPV2) 8.1 Introduction ................................................................................................................................... 107 8.1.1 ACMP Configuration Information...................................................................................107 8.1.2 ACMP/TPM Configuration Information .........................................................................107 8.1.3 Features ............................................................................................................................109 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 11 Section Number Title Page 8.2 8.3 8.4 8.1.4 Modes of Operation .........................................................................................................109 8.1.5 Block Diagram .................................................................................................................109 External Signal Description .......................................................................................................... 111 Register Definition ........................................................................................................................ 111 8.3.1 ACMP Status and Control Register (ACMPSC) .............................................................112 Functional Description .................................................................................................................. 113 Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.1 Introduction ................................................................................................................................... 115 9.1.1 Module Configurations ....................................................................................................117 9.1.2 Features ............................................................................................................................119 9.1.3 Block Diagram .................................................................................................................119 External Signal Description .......................................................................................................... 120 9.2.1 Analog Power (VDDAD)...................................................................................................121 9.2.2 Analog Ground (VSSAD)..................................................................................................121 9.2.3 Voltage Reference High (VREFH) ....................................................................................121 9.2.4 Voltage Reference Low (VREFL) .....................................................................................121 9.2.5 Analog Channel Inputs (ADx) .........................................................................................121 Register Definition ........................................................................................................................ 121 9.3.1 Status and Control Register 1 (ADCSC1) .......................................................................121 9.3.2 Status and Control Register 2 (ADCSC2) .......................................................................123 9.3.3 Data Result High Register (ADCRH)..............................................................................124 9.3.4 Data Result Low Register (ADCRL)...............................................................................124 9.3.5 Compare Value High Register (ADCCVH).....................................................................125 9.3.6 Compare Value Low Register (ADCCVL) ......................................................................125 9.3.7 Configuration Register (ADCCFG).................................................................................125 9.3.8 Pin Control 1 Register (APCTL1) ...................................................................................127 9.3.9 Pin Control 2 Register (APCTL2) ...................................................................................128 9.3.10 Pin Control 3 Register (APCTL3) ...................................................................................129 Functional Description .................................................................................................................. 130 9.4.1 Clock Select and Divide Control .....................................................................................130 9.4.2 Input Select and Pin Control ............................................................................................131 9.4.3 Hardware Trigger.............................................................................................................131 9.4.4 Conversion Control..........................................................................................................131 9.4.5 Automatic Compare Function..........................................................................................134 9.4.6 MCU Wait Mode Operation.............................................................................................134 9.4.7 MCU Stop3 Mode Operation...........................................................................................134 9.4.8 MCU Stop1 and Stop2 Mode Operation..........................................................................135 Initialization Information .............................................................................................................. 135 9.5.1 ADC Module Initialization Example ..............................................................................135 Application Information................................................................................................................ 137 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 12 Freescale Semiconductor 9.2 9.3 9.4 9.5 9.6 Section Number Title Page 9.6.1 External Pins and Routing ...............................................................................................137 9.6.2 Sources of Error ...............................................................................................................139 Chapter 10 Internal Clock Source (S08ICSV1) 10.1 Introduction ................................................................................................................................... 143 10.1.1 Module Configuration......................................................................................................143 10.1.2 Factory Trim Value ..........................................................................................................143 10.1.3 Features ............................................................................................................................145 10.1.4 Modes of Operation .........................................................................................................145 10.1.5 Block Diagram .................................................................................................................146 10.2 External Signal Description .......................................................................................................... 147 10.3 Register Definition ........................................................................................................................ 147 10.3.1 ICS Control Register 1 (ICSC1) ......................................................................................147 10.3.2 ICS Control Register 2 (ICSC2) ......................................................................................148 10.3.3 ICS Trim Register (ICSTRM)..........................................................................................149 10.3.4 ICS Status and Control (ICSSC)......................................................................................149 10.4 Functional Description .................................................................................................................. 150 10.4.1 Operational Modes...........................................................................................................150 10.4.2 Mode Switching ...............................................................................................................152 10.4.3 Bus Frequency Divider ....................................................................................................152 10.4.4 Low Power Bit Usage ......................................................................................................153 10.4.5 Internal Reference Clock .................................................................................................153 10.4.6 Optional External Reference Clock .................................................................................153 10.4.7 Fixed Frequency Clock ....................................................................................................153 Chapter 11 Inter-Integrated Circuit (S08IICV1) 11.1 Introduction ................................................................................................................................... 155 11.1.1 Module Configuration......................................................................................................155 11.1.2 Features ............................................................................................................................157 11.1.3 Modes of Operation .........................................................................................................157 11.1.4 Block Diagram .................................................................................................................158 11.2 External Signal Description .......................................................................................................... 158 11.2.1 SCL — Serial Clock Line ................................................................................................158 11.2.2 SDA — Serial Data Line .................................................................................................158 11.3 Register Definition ........................................................................................................................ 158 11.3.1 IIC Address Register (IICA)............................................................................................159 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................159 11.3.3 IIC Control Register (IICC) .............................................................................................162 11.3.4 IIC Status Register (IICS)................................................................................................163 11.3.5 IIC Data I/O Register (IICD) ...........................................................................................164 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 13 Section Number Title Page 11.4 Functional Description .................................................................................................................. 165 11.4.1 IIC Protocol......................................................................................................................165 11.5 Resets ............................................................................................................................................ 168 11.6 Interrupts ....................................................................................................................................... 168 11.6.1 Byte Transfer Interrupt.....................................................................................................169 11.6.2 Address Detect Interrupt ..................................................................................................169 11.6.3 Arbitration Lost Interrupt.................................................................................................169 11.7 Initialization/Application Information .......................................................................................... 170 Chapter 12 Keyboard Interrupt (S08KBIV2) 12.1 Introduction ................................................................................................................................... 173 12.1.1 Features ............................................................................................................................175 12.1.2 Modes of Operation .........................................................................................................175 12.1.3 Block Diagram .................................................................................................................175 12.2 External Signal Description .......................................................................................................... 176 12.3 Register Definition ........................................................................................................................ 176 12.3.1 KBI Status and Control Register (KBISC) ......................................................................176 12.3.2 KBI Pin Enable Register (KBIPE)...................................................................................177 12.3.3 KBI Edge Select Register (KBIES) .................................................................................177 12.4 Functional Description .................................................................................................................. 178 12.4.1 Edge Only Sensitivity ......................................................................................................178 12.4.2 Edge and Level Sensitivity ..............................................................................................178 12.4.3 KBI Pullup/Pulldown Resistors .......................................................................................179 12.4.4 KBI Initialization .............................................................................................................179 Chapter 13 Modulo Timer (S08MTIMV1) 13.1 Introduction ................................................................................................................................... 181 13.1.1 MTIM/TPM Configuration Information..........................................................................181 13.1.2 Features ............................................................................................................................183 13.1.3 Modes of Operation .........................................................................................................183 13.1.4 Block Diagram .................................................................................................................184 13.2 External Signal Description .......................................................................................................... 184 13.3 Register Definition ........................................................................................................................ 184 13.3.1 MTIM Status and Control Register (MTIMSC) ..............................................................186 13.3.2 MTIM Clock Configuration Register (MTIMCLK)........................................................187 13.3.3 MTIM Counter Register (MTIMCNT)............................................................................188 13.3.4 MTIM Modulo Register (MTIMMOD)...........................................................................188 13.4 Functional Description .................................................................................................................. 189 13.4.1 MTIM Operation Example ..............................................................................................190 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 14 Freescale Semiconductor Section Number Title Page Chapter 14 Serial Communications Interface (S08SCIV3) 14.1 Introduction ................................................................................................................................... 191 14.1.1 Features ............................................................................................................................194 14.1.2 Modes of Operation .........................................................................................................194 14.1.3 Block Diagram .................................................................................................................195 14.2 Register Definition ........................................................................................................................ 197 14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBHL) ...............................................................197 14.2.2 SCI Control Register 1 (SCIC1) ......................................................................................198 14.2.3 SCI Control Register 2 (SCIC2) ......................................................................................199 14.2.4 SCI Status Register 1 (SCIS1) .........................................................................................200 14.2.5 SCI Status Register 2 (SCIS2) .........................................................................................202 14.2.6 SCI Control Register 3 (SCIC3) ......................................................................................202 14.2.7 SCI Data Register (SCID)................................................................................................203 14.3 Functional Description .................................................................................................................. 204 14.3.1 Baud Rate Generation ......................................................................................................204 14.3.2 Transmitter Functional Description .................................................................................204 14.3.3 Receiver Functional Description .....................................................................................206 14.3.4 Interrupts and Status Flags...............................................................................................207 14.4 Additional SCI Functions.............................................................................................................. 208 14.4.1 8- and 9-Bit Data Modes..................................................................................................208 14.4.2 Stop Mode Operation.......................................................................................................209 14.4.3 Loop Mode.......................................................................................................................209 14.4.4 Single-Wire Operation .....................................................................................................209 Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction ................................................................................................................................... 211 15.1.1 Features ............................................................................................................................213 15.1.2 Block Diagrams ...............................................................................................................213 15.1.3 SPI Baud Rate Generation ...............................................................................................215 15.2 External Signal Description .......................................................................................................... 216 15.2.1 SPSCK — SPI Serial Clock.............................................................................................216 15.2.2 MOSI — Master Data Out, Slave Data In .......................................................................216 15.2.3 MISO — Master Data In, Slave Data Out .......................................................................216 15.2.4 SS — Slave Select ...........................................................................................................216 15.3 Modes of Operation....................................................................................................................... 217 15.3.1 SPI in Stop Modes ...........................................................................................................217 15.4 Register Definition ........................................................................................................................ 217 15.4.1 SPI Control Register 1 (SPIC1) .......................................................................................217 15.4.2 SPI Control Register 2 (SPIC2) .......................................................................................218 15.4.3 SPI Baud Rate Register (SPIBR).....................................................................................219 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 15 Section Number Title Page 15.4.4 SPI Status Register (SPIS) ...............................................................................................220 15.4.5 SPI Data Register (SPID) ................................................................................................221 15.5 Functional Description .................................................................................................................. 222 15.5.1 SPI Clock Formats ...........................................................................................................222 15.5.2 SPI Interrupts ...................................................................................................................225 15.5.3 Mode Fault Detection ......................................................................................................225 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV2) 16.1 Introduction ................................................................................................................................... 227 16.1.1 ACMP/TPM Configuration Information .........................................................................227 16.1.2 MTIM/TPM Configuration Information..........................................................................227 16.1.3 Features ............................................................................................................................229 16.1.4 Block Diagram .................................................................................................................229 16.2 External Signal Description .......................................................................................................... 231 16.2.1 External TPM Clock Sources ..........................................................................................231 16.2.2 TPMCHn — TPM Channel n I/O Pins ............................................................................231 16.3 Register Definition ........................................................................................................................ 231 16.3.1 Timer Status and Control Register (TPMSC) ..................................................................232 16.3.2 Timer Counter Registers (TPMCNTH:TPMCNTL)........................................................233 16.3.3 Timer Counter Modulo Registers (TPMMODH:TPMMODL) .......................................234 16.3.4 Timer Channel n Status and Control Register (TPMCnSC) ............................................235 16.3.5 Timer Channel Value Registers (TPMCnVH:TPMCnVL)..............................................236 16.4 Functional Description .................................................................................................................. 237 16.4.1 Counter.............................................................................................................................237 16.4.2 Channel Mode Selection ..................................................................................................238 16.4.3 Center-Aligned PWM Mode............................................................................................240 16.5 TPM Interrupts .............................................................................................................................. 241 16.5.1 Clearing Timer Interrupt Flags ........................................................................................241 16.5.2 Timer Overflow Interrupt Description.............................................................................241 16.5.3 Channel Event Interrupt Description ...............................................................................242 16.5.4 PWM End-of-Duty-Cycle Events ....................................................................................242 Chapter 17 Development Support 17.1 Introduction ................................................................................................................................... 243 17.1.1 Module Configuration......................................................................................................243 17.1.2 Features ............................................................................................................................244 17.2 Background Debug Controller (BDC) .......................................................................................... 244 17.2.1 BKGD Pin Description ....................................................................................................245 17.2.2 Communication Details ...................................................................................................246 17.2.3 BDC Commands ..............................................................................................................248 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 16 Freescale Semiconductor Section Number Title Page 17.2.4 BDC Hardware Breakpoint..............................................................................................251 17.3 On-Chip Debug System (DBG) .................................................................................................... 252 17.3.1 Comparators A and B ......................................................................................................252 17.3.2 Bus Capture Information and FIFO Operation ................................................................252 17.3.3 Change-of-Flow Information ...........................................................................................253 17.3.4 Tag vs. Force Breakpoints and Triggers ..........................................................................253 17.3.5 Trigger Modes..................................................................................................................254 17.3.6 Hardware Breakpoints .....................................................................................................256 17.4 Register Definition ........................................................................................................................ 256 17.4.1 BDC Registers and Control Bits ......................................................................................256 17.4.2 System Background Debug Force Reset Register (SBDFR)...........................................258 17.4.3 DBG Registers and Control Bits......................................................................................259 Appendix A Electrical Characteristics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 Introduction ....................................................................................................................................265 Absolute Maximum Ratings...........................................................................................................265 Thermal Characteristics..................................................................................................................266 ESD Protection and Latch-Up Immunity .......................................................................................268 DC Characteristics..........................................................................................................................269 Supply Current Characteristics.......................................................................................................272 External Oscillator (XOSC) and Internal Clock Source (ICS) Characteristics..............................274 AC Characteristics..........................................................................................................................276 A.8.1 Control Timing ................................................................................................................276 A.8.2 TPM/MTIM Module Timing ...........................................................................................277 A.8.3 SPI Timing .......................................................................................................................278 Analog Comparator (ACMP) Electricals .......................................................................................282 ADC Characteristics.......................................................................................................................282 FLASH Specifications....................................................................................................................285 EMC Performance..........................................................................................................................286 A.12.1 Radiated Emissions..........................................................................................................286 A.12.2 Conducted Transient Susceptibility .................................................................................286 A.9 A.10 A.11 A.12 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................289 B.1.1 Device Numbering Scheme .............................................................................................289 B.2 Mechanical Drawings.....................................................................................................................289 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 17 Section Number Title Page MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 18 Freescale Semiconductor Chapter 1 Device Overview 1.1 Introduction The MC9S08QG8 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for features associated with each device in this series. 1.1.1 Devices in the MC9S08QG8/4 Series Table 1-1. Devices in the MC9S08QG8/4 Series Device Table 1-1 summarizes the features available in the MC9S08QG8/4 series of MCUs. Feature MC9S08QG8 Package FLASH RAM XOSC ICS ACMP ADC DBG IIC IRQ KBI MTIM SCI SPI TPM yes yes 2-ch 12 I/O 1 Output only 1 Input only 24 QFN yes yes 2-ch 12 I/O 1 Output only 1 Input only 8-pin 8-ch yes yes yes yes 8-ch yes yes yes 8-pin yes no no 1-ch 4 I/O 1 Output only 1 Input only yes yes 2-ch 12 I/O 1 Output only 1 Input only 4-pin 8-pin 4-ch 8-ch yes 24-Pin 16-Pin 8K 512 no yes 8-Pin 24-Pin MC9S08QG4 16-Pin 4K 256 yes yes yes 8-ch yes yes yes 8-pin yes yes yes 2-ch 12 I/O 1 Output only 1 Input only no no 1-ch 4 I/O 1 Output only 1 Input only 4-pin 4-ch yes no 8-Pin I/O pins Package Types 16 PDIP 16 QFN 16 TSSOP 8 DFN 8 SOIC 24 QFN 16 QFN 16 TSSOP 8 DFN 8 PDIP 8 SOIC MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 19 Chapter 1 Device Overview 1.1.2 MCU Block Diagram BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices; see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 1-1. MC9S08QG8/4 Block Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 20 Freescale Semiconductor PORT B Chapter 1 Device Overview Table 1-2 provides the functional versions of the on-chip modules. Table 1-2. Versions of On-Chip Modules Module Analog Comparator Analog-to-Digital Converter Central Processing Unit IIC Module Internal Clock Source Keyboard Interrupt Modulo Timer Serial Communications Interface Serial Peripheral Interface Timer Pulse-Width Modulator Low-Power Oscillator Debug Module (ACMP) (ADC) (CPU) (IIC) (ICS) (KBI) (MTIM) (SCI) (SPI) (TPM) (XOSC) (DBG) Version 2 1 2 1 1 2 1 3 3 2 1 2 System Clock Distribution Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. All memory mapped registers associated with the modules are clocked with BUSCLK. EXTAL XTAL TCLK XOSC ICSFFE ICSFFCLK SYSTEM CONTROL LOGIC TPM MTIM IIC SCI SPI ÷2 FIXED FREQ CLOCK (XCLK) ICS ICSOUT ICSLCLK** ÷2 BUSCLK 1-kHz ICSERCLK* COP BDC RTI CPU ADC ADC has min and max frequency requirements. See the ADC chapter and Appendix A, “Electrical Characteristics.” FLASH FLASH has frequency requirements for program and erase operation. See Appendix A, “Electrical Characteristics.” * ICSERCLK requires XOSC module. ** ICSLCLK is the alternate BDC clock source for the MC9S08QG8/4. Figure 1-2. System Clock Distribution Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 21 Chapter 1 Device Overview MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 22 Freescale Semiconductor Chapter 2 External Signal Description This section describes signals that connect to package pins. It includes pinout diagrams, table of signal properties, and detailed discussions of signals. 2.1 Device Pin Assignment The following figures show the pin assignments for the available packages. Refer to Table 1-1 to see which package types are available for each device in the series. PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VSS 1 2 3 4 8 7 6 5 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 8-PIN ASSIGNMENT PDIP/SOIC PTA5/IRQ/TCLK/RESET 1 PTA4/ACMPO/BKGD/MS 2 VDD 3 VSS 4 8 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 7 PTA1/KBIP1/ADP1/ACMP– 6 PTA2/KBIP2/SDA/ADP2 5 PTA3/KBIP3/SCL/ADP3 8-PIN ASSIGNMENT DFN Figure 2-1. 8-Pin Packages MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 23 Chapter 2 External Signal Description PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPMCH1/SS PTB4/MISO 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 16-PIN ASSIGNMENT PDIP PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPMCH1/SS PTB4/MISO 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 16-PIN ASSIGNMENT TSSOP 16 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 14 PTA2/KBIP2/SDA/ADP2 7 PTB5/TPMCH1/SS PTA5/IRQ/TCLK/RESET 1 PTA4/ACMPO/BKGD/MS 2 VDD 3 VSS 4 5 6 16-PIN ASSIGNMENT QFN Figure 2-2. 16-Pin Packages MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 24 Freescale Semiconductor PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB4/MISO 8 13 PTA3/KBIP3/SCL/ADP3 12 PTB0/KBIP4/RxD/ADP4 11 PTB1/KBIP5/TxD/ADP5 10 PTB2/KBIP6/SPSCK/ADP6 9 PTB3/KBIP7/MOSI/ADP7 15 PTA1/KBIP1/ADP1/ACMP– Chapter 2 External Signal Description Pin 1 indicator PTA0/KBIP0/TPMCH0/ADP0/ACMP+ NC PTA5/IRQ/TCLK/RESET NC NC NC PTA4/ACMP0/BKGD/MS 1 VDD 2 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL 5 PTB5/TPMCH1/SS 6 24 23 22 21 20 19 18 PTA1/KBIP1/ADP1/ACMP‚ 17 PTA2/KBIP2/SDA/ADP2 MC9S08QG8/4 VSS 3 16 PTA3/KBIP3/SCL/ADP3 15 PTB0/KBIP4/RxD/ADP4 14 PTB1/KBIP5/TxD/ADP5 78 9 NC 13 PTB2/KBIP6/SPSCK/ADP6 10 11 12 PTB4/MISO PTB3/KBIP7/MOSI/ADP7 Figure 2-3. 24-Pin Packages 2.2 Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08QG8/4 application systems. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 25 NC NC NC Chapter 2 External Signal Description MC9S08QG8/4 SYSTEM POWER + 3V CBLK 10 μF VDD + CBY 0.1 μF VSS NOTE 1 RF C1 X1 C2 RS VDD PORT A PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK/RESET XTAL NOTE 2 EXTAL NOTE 2 I/O AND PERIPHERAL INTERFACE TO APPLICATION SYSTEM BACKGROUND HEADER VDD VDD BKGD PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PORT B RESET/IRQ 0.1 μF PTB3/KBIP7/MOSI/ADP7 PTB4/MISO PTB5/TPMCH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL ASYNCHRONOUS INTERRUPT INPUT 4.7 kΩ–10 kΩ OPTIONAL MANUAL RESET NOTES: 1. Not required if using the internal clock option. 2. XTAL is the same pin as PTB6; EXTAL the same pin as PTB7. 3. The RESET pin can only be used to reset into user mode; you can not enter BDM using the RESET pin. BDM can be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing the BDM command. 4. IRQ feature has optional internal pullup device. 5. RC filter on RESET/IRQ pin recommended for noisy environments. Figure 2-4. Basic System Connections 2.2.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry, ACMP and ADC modules, and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins: a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system, and a bypass capacitor, such as a 0.1-μF ceramic capacitor, located as near to the MCU power pins as practical to suppress high-frequency noise. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 26 Freescale Semiconductor Chapter 2 External Signal Description 2.2.2 Oscillator (XOSC) Out of reset, the MCU uses an internally generated clock provided by the internal clock source (ICS) module. The internal frequency is nominally 16-MHz and the default ICS settings will provide for a 8-MHz bus out of reset. For more information on the ICS, see Chapter 10, “Internal Clock Source (S08ICSV1).” The oscillator module (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in ICSC2. Rather than a crystal or ceramic resonator, an external clock source can be connected to the EXTAL input pin. Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup, and its value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity, and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2, which are usually the same size. As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.2.3 Reset (Input Only) After a power-on reset (POR), the PTA5/IRQ/TCLK/RESET pin defaults to a general-purpose input port pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET input pin. After configured as RESET, the pin will remain RESET until the next POR. The RESET pin can be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET pin (RSTPE = 1), an internal pullup device is automatically enabled. NOTE This pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on the internally pulled-up RESET pin will not be pulled to VDD. The internal gates connected to this pin are pulled to VDD. The RESET pullup should not be used to pull up components external to the MCU. NOTE In EMC-sensitive applications, an external RC filter is recommended on the RESET pin, if enabled. See Figure 2-4 for an example. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 27 Chapter 2 External Signal Description 2.2.4 Background / Mode Select (BKGD/MS) During a power-on-reset (POR) or background debug force reset (see 5.8.3, “System Background Debug Force Reset Register (SBDFR),” for more information), the PTA4/ACMPO/BKGD/MS pin functions as a mode select pin. Immediately after any reset, the pin functions as the background pin and can be used for background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal pullup device is automatically enabled. The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is set following any reset of the MCU and must be cleared to use the PTA4/ACMPO/BKGD/MS pin’s alternative pin functions. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug force reset, which will force the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.2.5 General-Purpose I/O and Peripheral Ports The MC9S08QG8/4 series of MCUs support up to 12 general-purpose I/O pins, 1 input-only pin, and 1 output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard interrupts, etc.). On each MC9S08QG8/4 device, there is one input-only and one output-only port pin. When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pullup device. For information about controlling these pins as general-purpose I/O pins, see the Chapter 6, “Parallel Input/Output Control.” For information about how and when on-chip peripheral systems use these pins, see the appropriate chapter referenced in Table 2-2. Immediately after reset, all pins that are not output-only are configured as high-impedance general-purpose inputs with internal pullup devices disabled. After reset, the output-only port function is not enabled but is configured for low output drive strength with slew rate control enabled. The PTA4 pin defaults to BKGD/MS on any reset. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 28 Freescale Semiconductor Chapter 2 External Signal Description NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program must either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. When using the 8-pin devices, the user must either enable on-chip pullup devices or change the direction of non-bonded out port B pins to outputs so the pins do not float. 2.2.5.1 Pin Control Registers To select drive strength or enable slew rate control or pullup devices, the user writes to the appropriate pin control register located in the high page register block of the memory map. The pin control registers operate independently of the parallel I/O registers and allow control of a port on an individual pin basis. 2.2.5.1.1 Internal Pullup Enable An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the parallel I/O control logic or any shared peripheral function, regardless of the state of the corresponding pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function. The KBI module, when enabled for rising edge detection, causes an enabled internal pull device to be configured as a pulldown. 2.2.5.2 Output Slew Rate Control Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs. 2.2.5.3 Output Drive Strength Select An output pin can be selected to have high output drive strength by setting the corresponding bit in one of the drive strength select registers (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this, the EMC emissions may be affected by enabling pins as high drive. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 29 Chapter 2 External Signal Description Table 2-1. Pin Sharing Priority Priority Pin Number 24-pin 16-pin 24 1 2 3 4 5 6 10 12 13 14 15 16 17 18 20 1 Lowest Port Pin PTA5 PTA4 1 Highest Alt 1 IRQ Alt 2 TCLK ACMPO BKGD Alt 3 Alt 4 RESET MS VDD VSS 8-pin 1 2 3 4 — — — — — — — — 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 PTA3 PTA2 PTA1 PTA0 KBIP7 KBIP6 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 SCL2 SDA2 TPMCH1 MISO MOSI SPSCK TxD RxD SCL2 SDA2 TPMCH0 EXTAL XTAL SS ADP7 ADP6 ADP5 ADP4 ADP3 ADP2 ADP13 ADP03 ACMP–3 ACMP+3 Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on the internally pulled-up RESET pin will not be pulled to VDD. The internal gates connected to this pin are pulled to VDD. 2 IIC pins can be repositioned using IICPS in SOPT2; default reset locations are on PTA2 and PTA3. 3 If ACMP and ADC are both enabled, both will have access to the pin. Table 2-2. Pin Function Reference Signal Function Port Pins Analog comparator Serial peripheral interface Keyboard interrupts Timer/PWM Inter-integrated circuit Serial communications interface Oscillator/clocking Analog-to-digital Power/core Reset and interrupts Example(s) PTAx, PTBx ACMPO, ACMP–, ACMP+ SS, MISO, MOSI, SPSCK KBIPx TCLK, TPMCHx SCL, SDA TxD, RxD EXTAL, XTAL ADPx BKGD/MS, VDD, VSS RESET, IRQ Reference Chapter 6, “Parallel Input/Output Control” Chapter 8, “Analog Comparator (S08ACMPV2)” Chapter 15, “Serial Peripheral Interface (S08SPIV3) Chapter 12, “Keyboard Interrupt (S08KBIV2)” Chapter 16, “Timer/Pulse-Width Modulator (S08TPMV2)” Chapter 11, “Inter-Integrated Circuit (S08IICV1)” Chapter 14, “Serial Communications Interface (S08SCIV3) Chapter 10, “Internal Clock Source (S08ICSV1)” Chapter 9, “Analog-to-Digital Converter (S08ADC10V1)” Chapter 2, “External Signal Description” Chapter 5, “Resets, Interrupts, and General System Control” MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 30 Freescale Semiconductor Chapter 2 External Signal Description NOTE When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software should clear out any associated flags before interrupts are enabled. Table 2-1 shows the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. It is recommended that all modules that share a pin be disabled before enabling anther module. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 31 Chapter 2 External Signal Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 32 Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08QG8/4 are described in this section. Entry into each mode, exit from each mode, and functionality while in each mode are described. 3.2 • • Features Active background mode for code development Wait mode: — CPU halts operation to conserve power — System clocks running — Full voltage regulation is maintained Stop modes: CPU and bus clocks stopped — Stop1: Full powerdown of internal circuits for maximum power savings — Stop2: Partial powerdown of internal circuits; RAM contents retained — Stop3: All internal circuits powered for fast recovery; RAM and register contents are retained • 3.3 Run Mode Run is the normal operating mode for the MC9S08QG8/4. This mode is selected upon the MCU exiting reset if the BKGD/MS pin is high. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provides the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low during POR or immediately after issuing a background debug force reset (see 5.8.3, “System Background Debug Force Reset Register (SBDFR)”) • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 33 Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user application program (GO) The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08QG8/4 is shipped from the Freescale factory, the FLASH program memory is erased by default unless specifically noted, so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter. 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in the condition code register (CCR) is cleared when the CPU enters wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available while the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 34 Freescale Semiconductor Chapter 3 Modes of Operation 3.6 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In any stop mode, the bus and CPU clocks are halted. The ICS module can be configured to leave the reference clocks running. See Chapter 10, “Internal Clock Source (S08ICSV1),” for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. The selected mode is entered following the execution of a STOP instruction. Table 3-1. Stop Mode Selection STOPE 0 1 1 1 1 1 1 ENBDM 1 x 1 0 0 0 0 LVDE x x LVDSE PDC x x x 0 1 1 PPDC x x x x 1 0 Stop Mode Stop modes disabled; illegal opcode reset if STOP instruction executed Stop3 with BDM enabled 2 Stop3 with voltage regulator active Stop3 Stop2 Stop1 Both bits must be 1 Either bit a 0 Either bit a 0 Either bit a 0 ENBDM is located in the BDCSCR which is only accessible through BDC commands; see Section 17.4.1.1, “BDC Status and Control Register (BDCSCR)”. 2 When in Stop3 mode with BDM enabled, the S IDD will be near RIDD levels because internal clocks are enabled. 3.6.1 Stop3 Mode Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time interrupt (RTI), LVD, ADC, IRQ, or the KBI. If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector. 3.6.1.1 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate the LVD must be left enabled when entering stop3. 3.6.1.2 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described in Chapter 17, “Development Support.” If ENBDM is set when the CPU executes a MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 35 Chapter 3 Modes of Operation STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. 3.6.2 Stop2 Mode Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop2 as in stop1 with the exception of the RAM. Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2. Exit from stop2 is performed by asserting the wake-up pin (PTA5) on the MCU. NOTE PTA5/IRQ/TCLK/RESET always functions as an active-low wakeup input when the MCU is in stop2, regardless of how the pin is configured before entering stop2. The pullup is not automatically enabled. To use the internal pullup, set the PTAPE5 bit in the PTAPE register In addition, the real-time interrupt (RTI) can wake the MCU from stop2, if enabled. Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD trip point (low trip point selected due to POR) • The CPU takes the reset vector In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2. To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 36 Freescale Semiconductor Chapter 3 Modes of Operation 3.6.3 Stop1 Mode Stop1 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop1, providing the lowest possible standby current. Upon entering stop1, all I/O pins automatically transition to their default reset states. Exit from stop1 is performed by asserting the wake-up pin (PTA5) on the MCU. NOTE PTA5/IRQ/TCLK/RESET always functions as an active-low wakeup input when the MCU is in stop2, regardless of how the pin is configured before entering stop2. The pullup is not automatically enabled. To use the internal pullup, set the PTAPE5 bit in the PTAPE register In addition, the real-time interrupt (RTI) can wake the MCU from stop1 if enabled. Upon wake-up from stop1 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD trip point (low trip point selected due to POR) • The CPU takes the reset vector In addition to the above, upon waking up from stop1, the PDF bit in SPMSC2 is set. This flag is used to direct user code to go to a stop1 recovery routine. PDF remains set until a 1 is written to PPDACK in SPMSC2. 3.6.4 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.3, “Stop1 Mode,” Section 3.6.2, “Stop2 Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Mode Peripheral Stop1 CPU RAM FLASH Parallel Port Registers ADC ACMP ICS IIC Off Off Off Off Off Off Off Off Stop2 Off Standby Off Off Off Off Off Off Stop3 Standby Standby Standby Standby Optionally On1 Standby Optionally On2 Standby MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 37 Chapter 3 Modes of Operation Table 3-2. Stop Mode Behavior (continued) Mode Peripheral Stop1 MTIM SCI SPI TPM Voltage Regulator XOSC I/O Pins 1 2 Stop2 Off Off Off Off Standby Off States Held Stop3 Standby Standby Standby Standby Standby Optionally On3 States Held Off Off Off Off Off Off Hi-Z Requires the asynchronous ADC clock and LVD to be enabled, else in standby. IRCLKEN and IREFSTEN set in ICSC1, else in standby. 3 ERCLKEN and EREFSTEN set in ICSC2, else in standby. For high frequency range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 38 Freescale Semiconductor Chapter 4 Memory Map and Register Definition 4.1 MC9S08QG8/4 Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08QG8/4 series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into these groups: • Direct-page registers (0x0000 through 0x005F) • High-page registers (0x1800 through 0x184F) • Nonvolatile registers (0xFFB0 through 0xFFBF) 0x0000 0x005F 0x0060 DIRECT PAGE REGISTERS RAM 512 BYTES 0x025F 0x0260 0x17FF 0x1800 UNIMPLEMENTED 5536 BYTES HIGH PAGE REGISTERS 0x184F 0x1850 0x184F 0x1850 0x0000 0x005F 0x0060 0x015F 0x0160 0x025F 0x0260 0x17FF 0x1800 DIRECT PAGE REGISTERS RAM 256 BYTES RESERVED 256 BYTES UNIMPLEMENTED 5536 BYTES HIGH PAGE REGISTERS UNIMPLEMENTED 51,120 BYTES UNIMPLEMENTED 51,120 BYTES 0xDFFF 0xE000 FLASH 8192 BYTES 0xDFFF 0xE000 RESERVED 0xEFFF 0xF000 4096 BYTES FLASH 4096 BYTES 0xFFFF 0xFFFF MC9S08QG8 MC9S08QG4 Figure 4-1. MC9S08QG8/4 Memory Map MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 39 Chapter 4 Memory Map and Register Definition 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QG8/4. Table 4-1. Reset and Interrupt Vectors Address (High:Low) 0xFFC0:FFC1 Vector Unused Vector Space (available for user program) Vector Name 0xFFCE:FFCF 0xFFD0:FFD1 0xFFD2:FFD3 0xFFD4:FFD5 0xFFD6:FFD7 0xFFD8:FFD9 0xFFDA:FFDB 0xFFDC:FFDD 0xFFDE:FFDF 0xFFE0:FFE1 0xFFE2:FFE3 0xFFE4:FFE5 0xFFE6:FFE7 0xFFE8:FFE9 0xFFEA:FFEB 0xFFEC:FFED 0xFFEE:FFEF 0xFFF0:FFF1 0xFFF2:FFF3 0xFFF4:FFF5 0xFFF6:FFF7 0xFFF8:FFF9 0xFFFA:FFFB 0xFFFC:FFFD 0xFFFE:FFFF RTI Reserved Reserved ACMP ADC Conversion KBI Interrupt IIC SCI Transmit SCI Receive SCI Error SPI MTIM Overflow Reserved Reserved Reserved Reserved TPM Overflow TPM Channel 1 TPM Channel 0 Reserved Low Voltage Detect IRQ SWI Reset Vrti — — Vacmp Vadc Vkeyboard Viic Vscitx Vscirx Vscierr Vspi Vmtim — — — — Vtpmovf Vtpmch1 Vtpmch0 — Vlvd Virq Vswi Vreset MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 40 Freescale Semiconductor Chapter 4 Memory Map and Register Definition 4.3 Register Addresses and Bit Assignments The registers in the MC9S08QG8/4 are divided into these groups: • Direct-page registers are located in the first 96 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located from 0x1800 and above in the memory map. This leaves more room in the direct page for more frequently used registers and RAM. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — NVPROT and NVOPT are loaded into working registers at reset. — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory. Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode that requires only the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. Table 4-2. Direct-Page Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 0x0001 0x0002 0x0003 0x0004– 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 PTAD PTADD PTBD PTBDD Reserved KBISC KBIPE KBIES IRQSC ADCSC1 ADCSC2 ADCRH ADCRL 0 0 PTBD7 PTBDD7 — — 0 KBIPE7 KBEDG7 0 COCO ADACT 0 ADR7 0 0 PTBD6 PTBDD6 — — 0 KBIPE6 KBEDG6 IRQPDD AIEN ADTRG 0 ADR6 PTAD5 PTADD5 PTBD5 PTBDD5 — — 0 KBIPE5 KBEDG5 0 ADCO ACFE 0 ADR5 PTAD4 PTADD4 PTBD4 PTBDD4 — — 0 KBIPE4 KBEDG4 IRQPE ACFGT 0 ADR4 PTAD3 PTADD3 PTBD3 PTBDD3 — — KBF KBIPE3 KBEDG3 IRQF — 0 ADR3 PTAD2 PTADD2 PTBD2 PTBDD2 — — KBACK KBIPE2 KBEDG2 IRQACK ADCH — 0 ADR2 PTAD1 PTADD1 PTBD1 PTBDD1 — — KBIE KBIPE1 KBEDG1 IRQIE — ADR9 ADR1 PTAD0 PTADD0 PTBD0 PTBDD0 — — KBMOD KBIPE0 KBEDG0 IRQMOD — ADR8 ADR0 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 41 Chapter 4 Memory Map and Register Definition Table 4-2. Direct-Page Register Summary (continued) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B– 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E ADCCVH ADCCVL ADCCFG APCTL1 Reserved Reserved ACMPSC Reserved SCIBDH SCIBDL SCIC1 SCIC2 SCIS1 SCIS2 SCIC3 SCID SPIC1 SPIC2 SPIBR SPIS Reserved SPID Reserved Reserved IICA IICF IICC IICS IICD Reserved Reserved Reserved ICSC1 ICSC2 ICSTRM ICSSC MTIMSC MTIMCLK MTIMCNT 0 ADCV7 ADLPC ADPC7 0 0 ACME — — 0 SBR7 LOOPS TIE TDRE 0 R8 Bit 7 SPIE 0 0 SPRF 0 Bit 7 — — MULT IICEN TCF — — — CLKS BDIV 0 TOF 0 0 ADCV6 ADIV ADPC6 0 0 ACBGS — — 0 SBR6 SCISWAI TCIE TC 0 T8 6 SPE 0 SPPR2 0 0 6 — — 0 ADCV5 ADPC5 0 0 ACF — — 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 SPTIE 0 SPPR1 SPTEF 0 5 — — 0 ADCV4 ADLSMP ADPC4 0 0 ACIE — — SBR12 SBR4 M ILIE IDLE 0 TXINV 4 MSTR MODFEN SPPR0 MODF 0 4 — — ADDR 0 ADCV3 ADPC3 0 0 ACO — — SBR11 SBR3 WAKE TE OR 0 ORIE 3 CPOL BIDIROE 0 0 0 3 — — ICR MODE 0 ADCV2 ADPC2 0 0 ACOPE — — SBR10 SBR2 ILT RE NF BRK13 NEIE 2 CPHA 0 SPR2 0 0 2 — — ADCV9 ADCV1 ADPC1 0 0 ADCV8 ADCV0 ADPC0 0 0 ADICLK ACMOD — — SBR9 SBR1 PE RWU FE 0 FEIE 1 SSOE SPISWAI SPR1 0 0 1 — — — — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 LSBFE SPC0 SPR0 0 0 Bit 0 — — 0 IICIE IAAS — — — MST BUSY — — — RANGE TX ARBL DATA — — — RDIV HGO TRIM 0 TSTP CLKS TXAK 0 — — — LP RSTA SRW — — — IREFS EREFS 0 IICIF — — — IRCLKEN 0 RXAK — — — IREFSTEN ERCLKEN EREFSTEN OSCINIT FTRIM 0 0 TOIE 0 0 TRST CLKST 0 0 PS 0 COUNT MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 42 Freescale Semiconductor Chapter 4 Memory Map and Register Definition Table 4-2. Direct-Page Register Summary (continued) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x003F 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B– 0x005F MTIMMOD TPMSC TPMCNTH TPMCNTL TPMMODH TPMMODL TPMC0SC TPMC0VH TPMC0VL TPMC1SC TPMC1VH TPMC1VL Reserved TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — — MOD CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — — PS1 9 1 9 1 0 9 1 0 9 1 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table 4-3. High-Page Register Summary Address 0x1800 0x1801 0x1802 0x1803 0x1804 0x1805 0x1806 0x1807 0x1808 0x1809 0x180A 0x180B 0x180C 0x180D– 0x180F 0x1810 0x1811 0x1812 0x1813 0x1814 0x1815 Register Name SRS SBDFR SOPT1 SOPT2 Reserved Reserved SDIDH SDIDL SRTISC SPMSC1 SPMSC2 Reserved SPMSC3 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL Bit 7 POR 0 COPE COPCLKS — — — ID7 RTIF LVDF 0 — LVWF — — Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 6 PIN 0 COPT 0 — — — ID6 RTIACK LVDACK 0 — LVWACK — — 14 6 14 6 14 6 5 COP 0 STOPE 0 — — — ID5 RTICLKS LVDIE 0 — LVDV — — 13 5 13 5 13 5 4 ILOP 0 — 0 — — — ID4 RTIE LVDRE PDF — LVWV — — 12 4 12 4 12 4 3 ILAD 0 0 0 — — ID11 ID3 0 LVDSE PPDF — — — — 11 3 11 3 11 3 LVDE PPDACK — — — — 10 2 10 2 10 2 2 0 0 0 0 — — ID10 ID2 1 LVD 0 BKGDPE IICPS — — ID9 ID1 RTIS 0 PDC — — — — 9 1 9 1 9 1 BGBE PPDC — — — — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 0 0 BDFR RSTPE ACIC — — ID8 ID0 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 43 Chapter 4 Memory Map and Register Definition Table 4-3. High-Page Register Summary (continued) Address 0x1816 0x1817 0x1818 0x1819– 0x181F 0x1820 0x1821 0x1822 0x1823 0x1824 0x1825 0x1826 0x1827– 0x183F 0x1840 0x1841 0x1842 0x1843 0x1844 0x1845 0x1846 0x1847 Register Name DBGC DBGT DBGS Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Reserved PTAPE PTASE PTADS Reserved PTBPE PTBSE PTBDS Reserved — — 0 0 0 — PTBPE7 PTBSE7 PTBDS7 — — — 0 0 0 — PTBPE6 PTBSE6 PTBDS6 — — — PTAPE5 PTASE5 PTADS5 — PTBPE5 PTBSE5 PTBDS5 — — — PTAPE4 PTASE4 PTADS4 — PTBPE4 PTBSE4 PTBDS4 — FCBEF FCCF FPVIOL Bit 7 DBGEN TRGSEL AF — — DIVLD KEYEN — 0 6 ARM BEGIN BF — — PRDIV8 FNORED — 0 0 — KEYACC 0 — 0 FPS FACCERR FCMD — — PTAPE3 PTASE3 PTADS3 — PTBPE3 PTBSE3 PTBDS3 — — — PTAPE2 PTASE2 PTADS2 — PTBPE2 PTBSE2 PTBDS2 — — — PTAPE1 PTASE1 PTADS1 — PTBPE1 PTBSE1 PTBDS1 — — — PTAPE0 PTASE0 PTADS0 — PTBPE0 PTBSE0 PTBDS0 — 0 FBLANK 0 0 — 0 5 TAG 0 ARMF — — 4 BRKEN 0 0 — — 3 RWA TRG3 CNT3 — — DIV 0 — 0 SEC01 — 0 SEC00 — 0 FPDIS 0 2 RWAEN TRG2 CNT2 — — 1 RWB TRG1 CNT1 — — Bit 0 RWBEN TRG0 CNT0 — — Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key that optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 44 Freescale Semiconductor Chapter 4 Memory Map and Register Definition Table 4-4. Nonvolatile Register Summary Address 0xFFAE 0xFFAF Register Name Reserved for Storage of FTRIM Reserved for Storage of ICSTRM Bit 7 0 6 0 5 0 4 0 TRIM 8-Byte Comparison Key — — — KEYEN — — — FNORED — — — 0 — — FPS — 0 — 0 — 0 — SEC01 — — — — — — — — FPDIS — SEC00 3 0 2 0 1 0 Bit 0 FTRIM 0xFFB0 – NVBACKKEY 0xFFB7 0xFFB8 – Unused 0xFFBC 0xFFBD 0xFFBE 0xFFBF NVPROT Unused NVOPT Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.4 RAM The MC9S08QG8/4 includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention (VRAM). For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08QG8/4, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP fADCK Subsequent continuous 10-bit; fBUS > fADCK Subsequent continuous 8-bit; fBUS > fADCK/11 Subsequent continuous 10-bit; fBUS > fADCK/11 ADICLK 0x, 10 0x, 10 0x, 10 0x, 10 11 11 11 11 xx xx xx xx ADLSMP 0 0 1 1 0 0 1 1 0 0 1 1 Max Total Conversion Time 20 ADCK cycles + 5 bus clock cycles 23 ADCK cycles + 5 bus clock cycles 40 ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 μs + 20 ADCK + 5 bus clock cycles 5 μs + 23 ADCK + 5 bus clock cycles 5 μs + 40 ADCK + 5 bus clock cycles 5 μs + 43 ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles 40 ADCK cycles The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is: Conversion time = 23 ADCK cyc 8 MHz/1 + 5 bus cyc 8 MHz = 3.5 μs Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 133 Analog-to-Digital Converter (S08ADC10V1) 9.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than the compare value, COCO is set. The value generated by the addition of the conversion result and the two’s complement of the compare value is transferred to ADCRH and ADCRL. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon the setting of COCO if the ADC interrupt is enabled (AIEN = 1). NOTE The compare function can be used to monitor the voltage on a channel while the MCU is in either wait or stop3 mode. The ADC interrupt will wake the MCU when the compare condition is met. 9.4.6 MCU Wait Mode Operation The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled. The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait mode if the ADC interrupt is enabled (AIEN = 1). 9.4.7 MCU Stop3 Mode Operation The STOP instruction is used to put the MCU in a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 9.4.7.1 Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 134 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 9.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3 mode if the ADC interrupt is enabled (AIEN = 1). NOTE It is possible for the ADC module to wake the system from low power stop and cause the MCU to begin consuming run-level currents without generating a system level interrupt. To prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in Section 9.4.4.2, “Completing Conversions) is cleared when entering stop3 and continuing ADC conversions. 9.4.8 MCU Stop1 and Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode. All module registers contain their reset values following exit from stop1 or stop2. Therefore the module must be re-enabled and re-configured following exit from stop1 or stop2. 9.5 Initialization Information This section gives an example which provides some basic direction on how a user would initialize and configure the ADC module. The user has the flexibility of choosing between configuring the module for 8-bit or 10-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 9-6, Table 9-7, and Table 9-8 for information used in this example. NOTE Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 9.5.1 9.5.1.1 ADC Module Initialization Example Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 135 Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 9.5.1.2 Pseudo — Code Example In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will be derived from the bus clock divided by 1. ADCCFG = 0x98 (%10011000) Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed) Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1 Bit 4 ADLSMP 1 Configures for long sample time Bit 3:2 MODE 10 Sets mode at 10-bit conversions Bit 1:0 ADICLK 00 Selects bus clock as input clock source ADCSC2 = 0x00 (%00000000) Bit 7 ADACT 0 Bit 6 ADTRG 0 Bit 5 ACFE 0 Bit 4 ACFGT 0 Bit 3:2 00 Bit 1:0 00 ADCSC1 = 0x41 (%01000001) Bit 7 COCO 0 Bit 6 AIEN 1 Bit 5 ADCO 0 Bit 4:0 ADCH 00001 Flag indicates if a conversion is in progress Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel ADCRH/L = 0xxx Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion data cannot be overwritten with data from the next conversion. ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 136 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT NO CONTINUE Figure 9-14. Initialization Flowchart for Example 9.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 9.6.1 External Pins and Routing The following sections discuss the external pins associated with the ADC module and how they should be used for best results. 9.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (VDDAD and VSSAD) which are available as separate pins on some devices. On other devices, VSSAD is shared on the same pin as the MCU digital VSS, and on others, both VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 137 Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 9.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The high reference is VREFH, which may be shared on the same pin as VDDAD on some devices. The low reference is VREFL, which may be shared on the same pin as VSSAD on some devices. When available on a separate pin, VREFH may be connected to the same potential as VDDAD, or may be driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH must never exceed VDDAD). When available on a separate pin, VREFL must be connected to the same voltage potential as VSSAD. Both VREFH and VREFL must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. Inductance in this path must be minimum (parasitic only). 9.6.1.3 Analog Input Pins The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin control register bit always be set when using a pin as an analog input. This avoids problems with contention because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input buffer draws dc current when its input is not at either VDD or VSS. Setting the pin control register bits for all pins used as analog inputs should be done to achieve lowest operating current. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to VSSA. For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to $3FF (full scale 10-bit representation) or $FF (full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. There will be a brief current associated with VREFL when the sampling capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 138 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 9.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 9.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept below 5 kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 9.6.2.2 Pin Leakage Error Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high. If this error cannot be tolerated by the application, keep RAS lower than VDDAD / (2N*ILEAK) for less than 1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode). 9.6.2.3 Noise-Induced Errors System noise which occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1 μF low-ESR capacitor from VREFH to VREFL. • There is a 0.1 μF low-ESR capacitor from VDDAD to VSSAD. • If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from VDDAD to VSSAD. • VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane. • Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion. — For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT instruction or STOP instruction. — For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: • Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSAD (this will improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 139 Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 9.6.2.4 Code Width and Quantization Error The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH - VREFL) / 2N Eqn. 9-2 There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB. 9.6.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. These errors are: • Zero-scale error (EZS) (sometimes called offset) — This error is defined as the difference between the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is used. • Full-scale error (EFS) — This error is defined as the difference between the actual code width of the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the difference between the actual $3FE code width and its ideal (1LSB) is used. • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. • Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. • Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 9.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 140 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 9.6.2.3 will reduce this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 141 Analog-to-Digital Converter (S08ADC10V1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 142 Freescale Semiconductor Chapter 10 Internal Clock Source (S08ICSV1) 10.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external reference clock. The module can provide this FLL clock or either of the internal or external reference clocks as a source for the MCU system clock. There are also signals provided to control a low power oscillator (XOSC) module to allow the use of an external crystal/resonator as the external reference clock. Whichever clock source is chosen, it is passed through a reduced bus divider (BDIV) which allows a lower final output clock frequency to be derived. The bus frequency will be one-half of the ICSOUT frequency. NOTE The external reference clock is not available on all packages. See Table 1-1 for external clock availability for each package option. 10.1.1 Module Configuration When the internal reference is enabled in stop mode (IREFSTEN = 1), the voltage regulator must also be enabled in stop mode by setting the LVDE and LVDSE bits in the SPMSC1 register. On this MCU, the internal reference is not connected to any module that is operational in stop mode. Therefore, the IREFSTEN bit in the ICSC1 register should always be cleared. Figure 10-1 shows the MC9S08QG8/4 block diagram with the ICS highlighted. 10.1.2 Factory Trim Value A factory trim value is stored in FLASH during production testing. To be used, this value must be copied from FLASH memory to the ICSTRM register. A factory value for this FTRIM bit is also stored in FLASH and must be copied into the FTRIM bit in the ICSSC register. See Table 4-4 for the FLASH locations of the factory ICSTRM and FTRIM values. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 143 Chapter 10 Internal Clock Source (S08ICSV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices, see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 10-1. MC9S08QG8/4 Block Diagram Highlighting ICS Block and Pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 144 Freescale Semiconductor PORT B Internal Clock Source (S08ICSV1) 10.1.3 Features Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accuracy — 0.2% resolution using internal 32 kHz reference — 2% deviation over voltage and temperature using internal 32 kHz reference • External reference clock up to 5 MHz can be used to control the FLL — 3 bit select for reference divider is provided • Internal reference clock has 9 trim bits available • Internal or external reference clock can be selected as the clock source for the MCU • Whichever clock is selected as the source can be divided down — 2 bit select for clock divider is provided – Allowable dividers are: 1, 2, 4, 8 – BDC clock is provided as a constant divide by 2 of the DCO output • Control signals for a low power oscillator as the external reference clock are provided — HGO, RANGE, EREFS, ERCLKEN, EREFSTEN • FLL engaged internal mode is automatically selected out of reset 10.1.4 Modes of Operation The ICS features the following modes of operation: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. 10.1.4.1 FLL Engaged Internal (FEI) In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL which is controlled by the internal reference clock. The BDC clock is supplied from the FLL. 10.1.4.2 FLL Engaged External (FEE) In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an external reference clock. The BDC clock is supplied from the FLL. 10.1.4.3 FLL Bypassed Internal (FBI) In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied from the FLL. 10.1.4.4 FLL Bypassed Internal Low Power (FBILP) In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. The BDC clock is not available. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 145 Internal Clock Source (S08ICSV1) 10.1.4.5 FLL Bypassed External (FBE) In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is supplied from the FLL. 10.1.4.6 FLL Bypassed External Low Power (FBELP) In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is not available. 10.1.4.7 Stop (STOP) In stop mode, the FLL is disabled and the internal or external reference clock can be selected to be enabled or disabled. The BDC clock is not available. ICS does not provide an MCU clock source. 10.1.5 Block Diagram This section contains the ICS block diagram. RANGE HGO Optional External Reference Clock Source Block EREFS EREFSTEN ERCLKEN IRCLKEN IREFSTEN CLKS BDIV ICSERCLK ICSIRCLK / 2n Internal Reference Clock IREFS LP n=0-3 ICSOUT 9 TRIM DCO DCOOUT /2 ICSLCLK ICSFFCLK 9 / 2n n=0-7 FLL RDIV Internal Clock Source Block RDIV_CLK Filter Figure 10-2. Internal Clock Source (ICS) Block Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 146 Freescale Semiconductor Internal Clock Source (S08ICSV1) 10.2 External Signal Description No ICS signal connects off chip. 10.3 10.3.1 Register Definition ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 R CLKS W Reset: 0 0 0 0 0 1 0 0 RDIV IREFS IRCLKEN IREFSTEN Figure 10-3. ICS Control Register 1 (ICSC1) Table 10-1. ICS Control Register 1 Field Descriptions Field 7:6 CLKS Description Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value of the BDIV bits. 00 Output of FLL is selected. 01 Internal reference clock is selected. 10 External reference clock is selected. 11 Reserved, defaults to 00. Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. 000 Encoding 0 — Divides reference clock by 1 (reset default) 001 Encoding 1 — Divides reference clock by 2 010 Encoding 2 — Divides reference clock by 4 011 Encoding 3 — Divides reference clock by 8 100 Encoding 4 — Divides reference clock by 16 101 Encoding 5 — Divides reference clock by 32 110 Encoding 6 — Divides reference clock by 64 111 Encoding 7 — Divides reference clock by 128 Internal Reference Select — The IREFS bit selects the reference clock source for the FLL. 1 Internal reference clock selected 0 External reference clock selected Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as ICSIRCLK. 1 ICSIRCLK active 0 ICSIRCLK inactive Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock remains enabled when the ICS enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop 5:3 RDIV 2 IREFS 1 IRCLKEN 0 IREFSTEN MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 147 Internal Clock Source (S08ICSV1) 10.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 1 0 R BDIV W Reset: 0 1 0 0 0 0 0 0 RANGE HGO LP EREFS ERCLKEN EREFSTEN Figure 10-4. ICS Control Register 2 (ICSC2) Table 10-2. ICS Control Register 2 Field Descriptions Field 7:6 BDIV Description Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus frequency. 00 Encoding 0 — Divides selected clock by 1 01 Encoding 1 — Divides selected clock by 2 (reset default) 10 Encoding 2 — Divides selected clock by 4 11 Encoding 3 — Divides selected clock by 8 Frequency Range Select — Selects the frequency range for the external oscillator. 1 High frequency range selected for the external oscillator 0 Low frequency range selected for the external oscillator High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation. 1 Configure external oscillator for high gain operation 0 Configure external oscillator for low power operation Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes. 1 FLL is disabled in bypass modes unless BDM is active 0 FLL is not disabled in bypass mode External Reference Select — The EREFS bit selects the source for the external reference clock. 1 Oscillator requested 0 External Clock Source requested External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK. 1 ICSERCLK active 0 ICSERCLK inactive 5 RANGE 4 HGO 3 LP 2 EREFS 1 ERCLKEN 0 External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock EREFSTEN remains enabled when the ICS enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 148 Freescale Semiconductor Internal Clock Source (S08ICSV1) 10.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: Reset: 1 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U Figure 10-5. ICS Trim Register (ICSTRM) Table 10-3. ICS Trim Register Field Descriptions Field 7:0 TRIM Description ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period. An additional fine trim bit is available in ICSSC as the FTRIM bit. 10.3.4 ICS Status and Control (ICSSC) 7 6 5 4 3 2 1 0 R W POR: Reset: 0 0 0 0 CLKST OSCINIT FTRIM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U Figure 10-6. ICS Status and Control Register (ICSSC) Table 10-4. ICS Status and Control Register Field Descriptions Field 3:2 CLKST Description Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected.10FLL Bypassed, External reference clock is selected. 11 Reserved. OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE, or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared. ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. 1 FTRIM 0 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 149 Internal Clock Source (S08ICSV1) 10.4 10.4.1 Functional Description Operational Modes The states of the ICS are shown as a state diagram and are described in the following sections. The arrows indicate the allowed movements between the states. IREFS=1 CLKS=00 FLL Engaged Internal (FEI) IREFS=0 CLKS=10BDM Enabled or LP =0 FLL Bypassed External Low Power(FBELP) IREFS=0 CLKS=10 BDM Disabled and LP=1 IREFS=1 CLKS=01 BDM Enabled or LP=0 FLL Bypassed Internal Low Power(FBILP) IREFS=1 CLKS=01 BDM Disabled and LP=1 FLL Bypassed External (FBE) FLL Bypassed Internal (FBI) FLL Engaged External (FEE) IREFS=0 CLKS=00 Entered from any state when MCU enters stop Stop Returns to state that was active before MCU entered stop, unless RESET occurs while in stop. Figure 10-7. Clock Switching Modes 10.4.1.1 FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation out of any reset and is entered when all the following conditions occur: • CLKS bits are written to 00 • IREFS bit is written to 1 • RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz. In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference clock is enabled. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 150 Freescale Semiconductor Internal Clock Source (S08ICSV1) 10.4.1.2 • • • FLL Engaged External (FEE) The FLL engaged external (FEE) mode is entered when all the following conditions occur: CLKS bits are written to 00 IREFS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by the external reference clock.The FLL loop will lock the frequency to 512 times the filter frequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external reference clock is enabled. 10.4.1.3 FLL Bypassed Internal (FBI) The FLL bypassed internal (FBI) mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1 • BDM mode is active or LP bit is written to 0 In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512 times the filter frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC communications, and the internal reference clock is enabled. 10.4.1.4 FLL Bypassed Internal Low Power (FBILP) The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1. • BDM mode is not active and LP bit is written to 1 In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal reference clock is enabled. 10.4.1.5 FLL Bypassed External (FBE) The FLL bypassed external (FBE) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is active or LP bit is written to 0. In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 151 Internal Clock Source (S08ICSV1) times the filter frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC communications, and the external reference clock is enabled. 10.4.1.6 FLL Bypassed External Low Power (FBELP) The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is not active and LP bit is written to 1. In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external reference clock is enabled. 10.4.1.7 Stop ICS stop mode is entered whenever the MCU enters stop. In this mode, all ICS clock signals are stopped except in the following cases: ICSIRCLK will be active in stop mode when all the following conditions occur: • IRCLKEN bit is written to 1 • IREFSTEN bit is written to 1 ICSERCLK will be active in stop mode when all the following conditions occur: • ERCLKEN bit is written to 1 • EREFSTEN bit is written to 1 10.4.2 Mode Switching When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will begin locking again after a few full cycles of the resulting divided reference frequency. The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is not available, the previous clock will remain selected. 10.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 152 Freescale Semiconductor Internal Clock Source (S08ICSV1) 10.4.4 Low Power Bit Usage The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0. 10.4.5 Internal Reference Clock When IRCLKEN is set the internal reference clock signal will be presented as ICSIRCLK, which can be used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period of the internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM register. Writing a larger value will slow down the ICSIRCLK frequency, and writing a smaller value to the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode. The TRIM and FTRIM value will not be affected by a reset. Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing specifications (see the Device Overview chapter). If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. All MCU devices are factory programmed with a trim value in a reserved memory location. This value can be copied to the ICSTRM register during reset initialization. The factory trim value does not include the FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the FTRIM bit accordingly. 10.4.6 Optional External Reference Clock The ICS module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz in all modes. When the ERCLKEN is set, the external reference clock signal will be presented as ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support (see the Device Overview chapter). If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. 10.4.7 Fixed Frequency Clock The ICS provides the divided FLL reference clock as ICSFFCLK for use as an additional clock source for peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK). In FLL engaged mode (FEI and FEE), this is always true and ICSFFE is always high. In ICS Bypass modes, ICSFFE will get asserted for the following combinations of BDIV and RDIV values: MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 153 Internal Clock Source (S08ICSV1) • • • • BDIV=00 (divide by 1), RDIV ≥ 010 BDIV=01 (divide by 2), RDIV ≥ 011 BDIV=10 (divide by 4), RDIV ≥ 100 BDIV=11 (divide by 8), RDIV ≥ 101 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 154 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV1) 11.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. 11.1.1 Module Configuration The IIC module pins, SDA and SCL can be repositioned under software control using IICPS in SOPT2 as as shown in Table 11-1. IICPS in SOPT2 selects which general-purpose I/O ports are associated with IIC operation. Table 11-1. IIC Position Options IICPS in SOPT2 0 (default) 1 Port Pin for SDA PTA2 PTB6 Port Pin for SCL PTA3 PTB7 Figure 11-1 is the MC9S08QG8/4 block diagram with the IIC block highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 155 Chapter 11 Inter-Integrated Circuit (S08IICV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices, see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 11-1. MC9S08QG8/4 Block Diagram Highlighting IIC Block and Pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 156 Freescale Semiconductor PORT B Inter-Integrated Circuit (S08IICV1) 11.1.2 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation • Acknowledge bit generation/detection • Bus busy detection 11.1.3 Modes of Operation The IIC functions the same in normal and monitor modes. A brief description of the IIC in the various MCU modes is given here. • Run mode — This is the basic mode of operation. To conserve power in this mode, disable the module. • Wait mode — The module will continue to operate while the MCU is in wait mode and can provide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop2 will reset the register contents. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 157 Inter-Integrated Circuit (S08IICV1) 11.1.4 Block Diagram ADDRESS INTERRUPT ADDR_DECODE DATA_MUX DATA BUS Figure 11-2 is a block diagram of the IIC. CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC START STOP ARBITRATION CONTROL CLOCK CONTROL IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE SCL SDA Figure 11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 11.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. 11.3 Register Definition This section consists of the IIC register descriptions in address order. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 158 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 0 R ADDR W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-3. IIC Address Register (IICA) Table 11-2. IICA Register Field Descriptions Field 7:1 ADDR[7:1] Description IIC Address Register — The ADDR contains the specific slave address to be used by the IIC module. This is the address the module will respond to when addressed as a slave. 11.3.2 IIC Frequency Divider Register (IICF) 7 6 5 4 3 2 1 0 R MULT W Reset 0 0 0 0 0 0 0 0 ICR Figure 11-4. IIC Frequency Divider Register (IICF) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 159 Inter-Integrated Circuit (S08IICV1) Table 11-3. IICF Register Field Descriptions Field 7:6 MULT Description IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to define the SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT register (multiplier factor mul) is used to generate IIC baud rate. IIC baud rate = bus speed (Hz)/(mul * SCL divider) SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC data). The ICR is used to determine the SDA hold value. SDA hold time = bus period (s) * SDA hold value Table 11-4 provides the SCL divider and SDA hold values for corresponding values of the ICR. These values can be used to set IIC baud rate and SDA hold time. For example: Bus speed = 8 MHz MULT is set to 01 (mul = 2) Desired IIC baud rate = 100 kbps IIC baud rate = bus speed (Hz)/(mul * SCL divider) 100000 = 8000000/(2*SCL divider) SCL divider = 40 Table 11-4 shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result in an SDA hold value of 9. SDA hold time = bus period (s) * SDA hold value SDA hold time = 1/8000000 * 9 = 1.125 μs If the generated SDA hold value is not acceptable, the MULT bits can be used to change the ICR. This will result in a different SDA hold value. 5:0 ICR MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 160 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) Table 11-4. IIC Divider and Hold Values ICR (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F SCL Divider 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 SDA Hold Value 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 ICR (hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F SCL Divider 160 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 SDA Hold Value 17 17 33 33 49 49 65 65 33 33 65 65 97 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 161 Inter-Integrated Circuit (S08IICV1) 11.3.3 IIC Control Register (IICC) 7 6 5 4 3 2 1 0 R IICEN W Reset 0 0 0 0 0 IICIE MST TX TXAK 0 RSTA 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. IIC Control Register (IICC) Table 11-5. IICC Register Field Descriptions Field 7 IICEN 6 IICIE 5 MST Description IIC Enable — The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled. 1 IIC is enabled. IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested. 0 IIC interrupt request not enabled. 1 IIC interrupt request enabled. Master Mode Select — The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode of operation changes from master to slave. 0 Slave Mode. 1 Master Mode. Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. 0 Receive. 1 Transmit. Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge cycles for both master and slave receivers. 0 An acknowledge signal will be sent out to the bus after receiving one data byte. 1 No acknowledge signal response is sent. Repeat START — Writing a one to this bit will generate a repeated START condition provided it is the current master. This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration. 4 TX 3 TXAK 2 RSTA MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 162 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) 11.3.4 IIC Status Register (IICS) 7 6 5 4 3 2 1 0 R W Reset TCF IAAS 1 0 BUSY ARBL 0 0 0 SRW IICIF RXAK 0 0 0 0 = Unimplemented or Reserved Figure 11-6. IIC Status Register (IICS) Table 11-6. IICS Register Field Descriptions Field 7 TCF Description Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress. 1 Transfer complete. Addressed as a Slave — The IAAS bit is set when the calling address matches the programmed slave address. Writing the IICC register clears this bit. 0 Not addressed. 1 Addressed as a slave. Bus Busy — The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set when a START signal is detected and cleared when a STOP signal is detected. 0 Bus is idle. 1 Bus is busy. Arbitration Lost — This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software, by writing a one to it. 0 Standard bus operation. 1 Loss of arbitration. Slave Read/Write — When addressed as a slave the SRW bit indicates the value of the R/W command bit of the calling address sent to the master. 0 Slave receive, master writing to slave. 1 Slave transmit, master reading from slave. IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing a one to it in the interrupt routine. One of the following events can set the IICIF bit: • One byte transfer completes • Match of slave address to calling address • Arbitration lost 0 No interrupt pending. 1 Interrupt pending. Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received. 1 No acknowledge received. 6 IAAS 5 BUSY 4 ARBL 2 SRW 1 IICIF 0 RXAK MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 163 Inter-Integrated Circuit (S08IICV1) 11.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure 11-7. IIC Data I/O Register (IICD) Table 11-7. IICD Register Field Descriptions Field 7:0 DATA Description Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transmitting out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. Note that the TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IICD will not initiate the receive. Reading the IICD will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back. In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the address transfer and should comprise of the calling address (in bit 7–bit 1) concatenated with the required R/W bit (in position bit 0). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 164 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) 11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • START signal • Slave address transmission • Data transfer • STOP signal The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Figure 11-8. MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 LSB 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 START SIGNAL MSB SCL 1 2 CALLING ADDRESS READ/ ACK WRITE BIT LSB MSB 9 1 2 3 DATA BYTE NO STOP ACK SIGNAL BIT LSB 3 4 5 6 7 8 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START SIGNAL CALLING ADDRESS READ/ ACK WRITE BIT REPEATED START SIGNAL NEW CALLING ADDRESS READ/ NO STOP WRITE ACK SIGNAL BIT Figure 11-8. IIC Bus Transmission Signals MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 165 Inter-Integrated Circuit (S08IICV1) 11.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 11-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 11.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 11-8). No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit an address that is equal to its own slave address. The IIC cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate correctly even if it is being addressed by another master. 11.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 11-8. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a STOP signal. • Commences a new calling by generating a repeated START signal. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 166 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) 11.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 11-8). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. 11.4.1.5 Repeated START Signal As shown in Figure 11-8, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 Clock Synchronization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus. The devices start counting their low period and after a device’s clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 11-9). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 167 Inter-Integrated Circuit (S08IICV1) START COUNTING HIGH PERIOD DELAY SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure 11-9. IIC Clock Synchronization 11.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 11.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 11.5 Resets The IIC is disabled after reset. The IIC cannot cause an MCU reset. 11.6 Interrupts The IIC generates a single interrupt. An interrupt from the IIC is generated when any of the events in Table 11-8 occur provided the IICIE bit is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine. The user can determine the interrupt type by reading the status register. Table 11-8. Interrupt Summary Interrupt Source Complete 1-byte transfer Match of received calling address Arbitration Lost Status TCF IAAS ARBL Flag IICIF IICIF IICIF Local Enable IICIE IICIE IICIE MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 168 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) 11.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 11.6.3 Arbitration Lost Interrupt The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A START cycle is attempted when the bus is busy. • A repeated START cycle is requested in slave mode. • A STOP condition is detected when the master did not request it. This bit must be cleared by software by writing a one to it. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 169 Inter-Integrated Circuit (S08IICV1) 11.7 1. 2. 3. 4. Initialization/Application Information Module Initialization (Slave) Write: IICA — to set the slave address Write: IICC — to enable IIC and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in Figure 11-11 1. 2. 3. 4. 5. 6. 7. Module Initialization (Master) Write: IICF — to set the IIC baud rate (example provided in this chapter) Write: IICC — to enable IIC and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in Figure 11-11 Write: IICC — to enable TX Write: IICC — to enable MST (master mode) Write: IICD — with the address of the target slave. (The LSB of this byte will determine whether the communication is master receive or transmit.) Module Use The routine shown in Figure 11-11 can handle both master and slave IIC operations. For slave operation, an incoming IIC message that contains the proper address will begin IIC communication. For master operation, communication must be initiated by writing to the IICD register. Register Model IICA MULT ADDR 0 Address to which the module will respond when addressed as a slave (in slave mode) IICF ICR Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER)) IICC IICS IICD IICEN TCF IICIE IAAS MST BUSY TX ARBL DATA Data register; Write to transmit IIC data read to read IIC data TXAK 0 RSTA SRW 0 IICIF 0 RXAK Module configuration Module status flags Figure 11-10. IIC Module Quick Start MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 170 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) Clear IICIF Y Master Mode ? N TX Tx/Rx ? RX Y Arbitration Lost ? N Last Byte Transmitted ? N Y Clear ARBL RXAK=0 ? Y N Last Byte to Be Read ? N N Y IAAS=1 ? Y Y IAAS=1 ? N Address Transfer Y End of Addr Cycle (Master Rx) ? N Y 2nd Last Byte to Be Read ? N Y (Read) SRW=1 ? N (Write) Data Transfer TX/RX ? TX RX Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) Set TX Mode Y ACK from Receiver ? N Read Data from IICD and Store Write Data to IICD Tx Next Byte Switch to Rx Mode Set RX Mode Switch to Rx Mode Dummy Read from IICD Generate Stop Signal (MST = 0) Read Data from IICD and Store Dummy Read from IICD Dummy Read from IICD RTI Figure 11-11. Typical IIC Interrupt Routine MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 171 Inter-Integrated Circuit (S08IICV1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 172 Freescale Semiconductor Chapter 12 Keyboard Interrupt (S08KBIV2) 12.1 Introduction The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources. Figure 12-1 Shows the MC9S08QG8/4 block guide with the KBI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 173 Chapter 12 Keyboard Interrupt (S08KBIV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices, see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 12-1. MC9S08QG8/4 Block Diagram Highlighting KBI Block and Pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 174 Freescale Semiconductor PORT B Keyboard Interrupts (S08KBIV2) 12.1.1 Features The KBI features include: • Up to eight keyboard interrupt pins with individual pin enable bits. • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. • One software enabled keyboard interrupt. • Exit from low-power modes. 12.1.2 Modes of Operation This section defines the KBI operation in wait, stop, and background debug modes. 12.1.2.1 KBI in Wait Mode The KBI continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is enabled (KBIE = 1). 12.1.2.2 KBI in Stop Modes The KBI operates asynchronously in stop3 mode if enabled before executing the STOP instruction. Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of stop3 mode if the KBI interrupt is enabled (KBIE = 1). During either stop1 or stop2 mode, the KBI is disabled. In some systems, the pins associated with the KBI may be sources of wakeup from stop1 or stop2, see the stop modes section in the Modes of Operation chapter. Upon wake-up from stop1 or stop2 mode, the KBI module will be in the reset state. 12.1.2.3 KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 12.1.3 Block Diagram The block diagram for the keyboard interrupt module is shown Figure 12-2. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 175 Keyboard Interrupts (S08KBIV2) KBACK 1 VDD S KBIPE0 D CLR Q CK KBEDG0 1 KEYBOARD INTERRUPT FF S KBIPEn KBMOD STOP RESET BUSCLK KBF SYNCHRONIZER KBIP0 0 STOP BYPASS KBIPn KBEDGn 0 KBI INTERRU PT KBIE Figure 12-2. KBI Block Diagram 12.2 External Signal Description The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests. The signal properties of KBI are shown in Table 12-1. Table 12-1. Signal Properties Signal KBIPn Function Keyboard interrupt pins I/O I 12.3 Register Definition The KBI includes three registers: • An 8-bit pin status and control register. • An 8-bit pin enable register. • An 8-bit edge select register. Refer to the direct-page register summary in the Memory chapter for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. Some MCUs may have more than one KBI, so register names include placeholder characters to identify which KBI is being referenced. 12.3.1 KBI Status and Control Register (KBISC) KBISC contains the status flag and control bits, which are used to configure the KBI. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 176 Freescale Semiconductor Keyboard Interrupts (S08KBIV2) 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 KBF 0 KBIE KBACK KBMOD 0 0 0 = Unimplemented 0 0 0 0 0 Figure 12-3. KBI Status and Control Register Table 12-2. KBISC Register Field Descriptions Field 7:4 3 KBF 2 KBACK 1 KBIE 0 KBMOD Unused register bits, always read 0. Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF. 0 No keyboard interrupt detected. 1 Keyboard interrupt detected. Keyboard Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads as 0. Keyboard Interrupt Enable — KBIE determines whether a keyboard interrupt is requested. 0 Keyboard interrupt request not enabled. 1 Keyboard interrupt request enabled. Keyboard Detection Mode — KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard interrupt pins.0Keyboard detects edges only. 1 Keyboard detects both edges and levels. Description 12.3.2 KBI Pin Enable Register (KBIPE) KBIPE contains the pin enable control bits. 7 6 5 4 3 2 1 0 R KBIPE7 W Reset: 0 0 0 0 0 0 0 0 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 Figure 12-4. KBI Pin Enable Register Table 12-3. KBIPE Register Field Descriptions Field 7:0 KBIPEn Description Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. 12.3.3 KBI Edge Select Register (KBIES) KBIES contains the edge select control bits. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 177 Keyboard Interrupts (S08KBIV2) 7 6 5 4 3 2 1 0 R KBEDG7 W Reset: 0 0 0 0 0 0 0 0 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 Figure 12-5. KBI Edge Select Register Table 12-4. KBIES Register Field Descriptions Field 7:0 KBEDGn Description Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 Falling edge/low level. 1 Rising edge/high level. 12.4 Functional Description This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes. The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPEn bits in the keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin. Each KBI pin can be configured as edge sensitive or edge and level sensitive based on the KBMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES). 12.4.1 Edge Only Sensitivity Synchronous logic is used to detect edges. A falling edge is detected when an enabled keyboard interrupt (KBIPEn=1) input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 (the deasserted level) during one bus cycle and then a logic 1 (the asserted level) during the next cycle.Before the first edge is detected, all enabled keyboard interrupt input signals must be at the deasserted logic levels. After any edge is detected, all enabled keyboard interrupt input signals must return to the deasserted level before any new edge can be detected. A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC. 12.4.2 Edge and Level Sensitivity A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 178 Freescale Semiconductor Keyboard Interrupts (S08KBIV2) KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK. 12.4.3 KBI Pullup/Pulldown Resistors The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register. If an internal resistor is enabled, the KBIES register is used to select whether the resistor is a pullup (KBEDGn = 0) or a pulldown (KBEDGn = 1). 12.4.4 KBI Initialization When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. To prevent a false interrupt request during keyboard initialization, the user should do the following: 1. Mask keyboard interrupts by clearing KBIE in KBISC. 2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES. 3. If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 179 Keyboard Interrupts (S08KBIV2) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 180 Freescale Semiconductor Chapter 13 Modulo Timer (S08MTIMV1) 13.1 Introduction The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. The central component of the MTIM is the 8-bit counter, which can operate as a free-running counter or a modulo counter. A timer overflow interrupt can be enabled to generate periodic interrupts for time-based software loops. Figure 13-1 shows the MC9S08QG8/4 block diagram with the MTIM highlighted. 13.1.1 MTIM/TPM Configuration Information The external clock for the MTIM module, TCLK, is selected by setting CLKS = 1:1 or 1:0 in MTIMCLK, which selects the TCLK pin input. The TCLK input on PTA5 can be enabled as external clock inputs to both the MTIM and TPM modules simultaneously. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 181 Chapter 13 Modulo Timer (S08MTIMV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices, see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 13-1. MC9S08QG8/4 Block Diagram Highlighting MTIM Block and Pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 182 Freescale Semiconductor PORT B Modulo Timer (S08MTIMV1) 13.1.2 Features Timer system features include: • 8-bit up-counter — Free-running or 8-bit modulo limit — Software controllable interrupt on overflow — Counter reset bit (TRST) — Counter stop bit (TSTP) • Four software selectable clock sources for input to prescaler: — System bus clock — rising edge — Fixed frequency clock (XCLK) — rising edge — External clock source on the TCLK pin — rising edge — External clock source on the TCLK pin — falling edge • Nine selectable clock prescale values: — Clock source divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256 13.1.3 Modes of Operation This section defines the MTIM’s operation in stop, wait and background debug modes. 13.1.3.1 MTIM in Wait Mode The MTIM continues to run in wait mode if enabled before executing the WAIT instruction. Therefore, the MTIM can be used to bring the MCU out of wait mode if the timer overflow interrupt is enabled. For lowest possible current consumption, the MTIM should be stopped by software if not needed as an interrupt source during wait mode. 13.1.3.2 MTIM in Stop Modes The MTIM is disabled in all stop modes, regardless of the settings before executing the STOP instruction. Therefore, the MTIM cannot be used as a wake up source from stop modes. Waking from stop1 and stop2 modes, the MTIM will be put into its reset state. If stop3 is exited with a reset, the MTIM will be put into its reset state. If stop3 is exited with an interrupt, the MTIM continues from the state it was in when stop3 was entered. If the counter was active upon entering stop3, the count will resume from the current value. 13.1.3.3 MTIM in Active Background Mode The MTIM suspends all counting until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written to a 1 or MTIMMOD written). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 183 Modulo Timer (S08MTIMV1) 13.1.4 Block Diagram The block diagram for the modulo timer module is shown Figure 13-2. BUSCLK XCLK TCLK SYNC CLOCK SOURCE SELECT PRESCALE AND SELECT DIVIDE BY 8-BIT COUNTER (MTIMCNT) TRST TSTP CLKS PS 8-BIT COMPARATOR MTIM INTERRU PT TOF TOIE 8-BIT MODULO (MTIMMOD) Figure 13-2. Modulo Timer (MTIM) Block Diagram 13.2 External Signal Description The MTIM includes one external signal, TCLK, used to input an external clock when selected as the MTIM clock source. The signal properties of TCLK are shown in Table 13-1. Table 13-1. Signal Properties Signal TCLK Function External clock source input into MTIM I/O I The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter must be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency. The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for the pin location and priority of this function. 13.3 Register Definition Figure 13-3 is a summary of MTIM registers. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 184 Freescale Semiconductor Modulo Timer (S08MTIMV1) Figure 13-3. MTIM Register Summary Name R MTIMSC W R MTIMCLK W R MTIMCNT W R MTIMMOD W MOD COUNT 0 0 CLKS PS 7 6 5 4 3 2 1 0 TOF TOIE 0 TSTP TRST 0 0 0 0 Each MTIM includes four registers: • An 8-bit status and control register • An 8-bit clock configuration register • An 8-bit counter register • An 8-bit modulo register Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all MTIM registers.This section refers to registers and control bits only by their names and relative address offsets. Some MCUs may have more than one MTIM, so register names include placeholder characters to identify which MTIM is being referenced. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 185 Modulo Timer (S08MTIMV1) 13.3.1 MTIM Status and Control Register (MTIMSC) MTIMSC contains the overflow status flag and control bits which are used to configure the interrupt enable, reset the counter, and stop the counter. 7 6 5 4 3 2 1 0 R W Reset: TOF TOIE 0 TSTP TRST 0 1 0 0 0 0 0 0 0 0 0 0 Figure 13-4. MTIM Status and Control Register Table 13-2. MTIM Status and Control Register Field Descriptions Field 7 TOF Description MTIM Overflow Flag — This read-only bit is set when the MTIM counter register overflows to $00 after reaching the value in the MTIM modulo register. Clear TOF by reading the MTIMSC register while TOF is set, then writing a 0 to TOF. TOF is also cleared when TRST is written to a 1 or when any value is written to the MTIMMOD register. 0 MTIM counter has not reached the overflow value in the MTIM modulo register. 1 MTIM counter has reached the overflow value in the MTIM modulo register. MTIM Overflow Interrupt Enable — This read/write bit enables MTIM overflow interrupts. If TOIE is set, then an interrupt is generated when TOF = 1. Reset clears TOIE. Do not set TOIE if TOF = 1. Clear TOF first, then set TOIE. 0 TOF interrupts are disabled. Use software polling. 1 TOF interrupts are enabled. MTIM Counter Reset — When a 1 is written to this write-only bit, the MTIM counter register resets to $00 and TOF is cleared. Reading this bit always returns 0. 0 No effect. MTIM counter remains at current state. 1 MTIM counter is reset to $00. MTIM Counter Stop — When set, this read/write bit stops the MTIM counter at its current value. Counting resumes from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. Unused register bits, always read 0. 6 TOIE 5 TRST 4 TSTP 3:0 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 186 Freescale Semiconductor Modulo Timer (S08MTIMV1) 13.3.2 MTIM Clock Configuration Register (MTIMCLK) MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS). 7 6 5 4 3 2 1 0 R W Reset: 0 0 CLKS PS 0 0 0 0 0 0 0 0 Figure 13-5. MTIM Clock Configuration Register Table 13-3. MTIM Clock Configuration Register Field Description Field 7:6 5:4 CLKS Unused register bits, always read 0. Clock Source Select — These two read/write bits select one of four different clock sources as the input to the MTIM prescaler. Changing the clock source while the counter is active does not clear the counter. The count continues with the new clock source. Reset clears CLKS to 000. 00 Encoding 0. Bus clock (BUSCLK) 01 Encoding 1. Fixed-frequency clock (XCLK) 10 Encoding 3. External source (TCLK pin), falling edge 11 Encoding 4. External source (TCLK pin), rising edge All other encodings default to the bus clock (BUSCLK). Clock Source Prescaler — These four read/write bits select one of nine outputs from the 8-bit prescaler. Changing the prescaler value while the counter is active does not clear the counter. The count continues with the new prescaler value. Reset clears PS to 0000. 0000 Encoding 0. MTIM clock source ÷ 1 0001 Encoding 1. MTIM clock source ÷ 2 0010 Encoding 2. MTIM clock source ÷ 4 0011 Encoding 3. MTIM clock source ÷ 8 0100 Encoding 4. MTIM clock source ÷ 16 0101 Encoding 5. MTIM clock source ÷ 32 0110 Encoding 6. MTIM clock source ÷ 64 0111 Encoding 7. MTIM clock source ÷ 128 1000 Encoding 8. MTIM clock source ÷ 256 All other encodings default to MTIM clock source ÷ 256. Description 3:0 PS MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 187 Modulo Timer (S08MTIMV1) 13.3.3 MTIMCNT MTIM Counter Register (MTIMCNT) is the read-only value of the current MTIM count of the 8-bit counter. 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 COUNT 0 0 0 0 Figure 13-6. MTIM Counter Register Table 13-4. MTIM Counter Register Field Description Field 7:0 COUNT Description MTIM Count — These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register. Reset clears the count to $00. 13.3.4 MTIM Modulo Register (MTIMMOD) 7 6 5 4 3 2 1 0 R MOD W Reset: 0 0 0 0 0 0 0 0 Figure 13-7. MTIM Modulo Register Table 13-5. MTIM Modulo Register Field Descriptions Field 7:0 MOD Description MTIM Modulo — These eight read/write bits contain the modulo value used to reset the count and set TOF. A value of $00 puts the MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to $00 and clears TOF. Reset sets the modulo to $00. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 188 Freescale Semiconductor Modulo Timer (S08MTIMV1) 13.4 Functional Description The MTIM is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software selectable interrupt logic. The MTIM counter (MTIMCNT) has three modes of operation: stopped, free-running, and modulo. Out of reset, the counter is stopped. If the counter is started without writing a new value to the modulo register, then the counter will be in free-running mode. The counter is in modulo mode when a value other than $00 is in the modulo register while the counter is running. After any MCU reset, the counter is stopped and reset to $00, and the modulus is set to $00. The bus clock is selected as the default clock source and the prescale value is divide by 1. To start the MTIM in free-running mode, simply write to the MTIM status and control register (MTIMSC) and clear the MTIM stop bit (TSTP). Four clock sources are software selectable: the internal bus clock, the fixed frequency clock (XCLK), and an external clock on the TCLK pin, selectable as incrementing on either rising or falling edges. The MTIM clock select bits (CLKS1:CLKS0) in MTIMSC are used to select the desired clock source. If the counter is active (TSTP = 0) when a new clock source is selected, the counter will continue counting from the previous value using the new clock source. Nine prescale values are software selectable: clock source divided by 1, 2, 4, 8, 16, 32, 64, 128, or 256. The prescaler select bits (PS[3:0]) in MTIMSC select the desired prescale value. If the counter is active (TSTP = 0) when a new prescaler value is selected, the counter will continue counting from the previous value using the new prescaler value. The MTIM modulo register (MTIMMOD) allows the overflow compare value to be set to any value from $01 to $FF. Reset clears the modulo value to $00, which results in a free running counter. When the counter is active (TSTP = 0), the counter increments at the selected rate until the count matches the modulo value. When these values match, the counter overflows to $00 and continues counting. The MTIM overflow flag (TOF) is set whenever the counter overflows. The flag sets on the transition from the modulo value to $00. Writing to MTIMMOD while the counter is active resets the counter to $00 and clears TOF. Clearing TOF is a two-step process. The first step is to read the MTIMSC register while TOF is set. The second step is to write a 0 to TOF. If another overflow occurs between the first and second steps, the clearing process is reset and TOF will remain set after the second step is performed. This will prevent the second occurrence from being missed. TOF is also cleared when a 1 is written to TRST or when any value is written to the MTIMMOD register. The MTIM allows for an optional interrupt to be generated whenever TOF is set. To enable the MTIM overflow interrupt, set the MTIM overflow interrupt enable bit (TOIE) in MTIMSC. TOIE should never be written to a 1 while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 189 Modulo Timer (S08MTIMV1) 13.4.1 MTIM Operation Example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register. selected clock source MTIM clock (PS=%0010) MTIMCNT $A7 $A8 $A9 $AA $00 $01 TOF MTIMMOD: $AA Figure 13-8. MTIM counter overflow example In the example of Figure 13-8, the selected clock source could be any of the five possible choices. The prescaler is set to PS = %0010 or divide-by-4. The modulo value in the MTIMMOD register is set to $AA. When the counter, MTIMCNT, reaches the modulo value of $AA, the counter overflows to $00 and continues counting. The timer overflow flag, TOF, sets when the counter value changes from $AA to $00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 190 Freescale Semiconductor Chapter 14 Serial Communications Interface (S08SCIV3) 14.1 Introduction Figure 14-1 shows the MC9S08QG8/4 block diagram with the SCI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 191 Chapter 14 Serial Communications Interface (S08SCIV3) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices, see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 14-1. MC9S08QG8/4 Block Diagram Highlighting SCI Block and Pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 192 Freescale Semiconductor PORT B Chapter 14 Serial Communications Interface (S08SCIV3) Module Initialization: Write: Write: Write; Write: SCIBDH:SCIBDL SCFC1 SCIC2 SCIC3 to set to configure to configure to enable baud rate 1-wire/2-wire, 9/8-bit data, wakeup, and parity, if used. interrupts, enable Rx and Tx, RWU Enable Rx wakeup, SBK sends break character Rx error interrupt sources. Also controls pin direction in 1-wire modes. R8 and T8 only used in 9-bit data modes. Module Use: Wait for TDRE, then write data to SCID Wait for RDRF, then read data from SCID A small number of applications will use RWU to manage automatic receiver wakeup, SBK to send break characters, and R8 and T8 for 9-bit data. SCIBDH SCIBDL SBR7 SBR6 SBR5 SBR12 SBR4 SBR11 SBR3 SBR10 SBR2 SBR9 SBR1 SBR8 SBR0 Baud rate = BUSCLK / (16 x SBR12:SBR0) SCIC1 LOOPS SCISWAI RSRC M WAKE ILT PE PT Module configuration SCIC2 TIE TCIE RIE ILIE TE RE RWU SBK Local interrupt enables Tx and Rx enable Rx wakeup and send break OR Rx error flags BRK13 RAF NF FE PF SCIS1 TDRE Interrupt flags TC RDRF IDLE SCIS2 Configure LIN support options and monitor receiver activity SCIS3 R8 9th data bits Rx/Tx pin Tx data path direction in polarity single-wire mode SCIID R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 T8 TXDIR TXINV ORIE NEIE FEIE PEIE Local interrupt enables R2/T2 R1/T1 R0/T0 Read: Rx data; write: Tx data Figure 14-2. SCI Module Quick Start MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 193 Serial Communications Interface (S08SCIV3) 14.1.1 Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wakeup by idle-line or address-mark • Optional 13-bit break character • Selectable transmitter output polarity 14.1.2 Modes of Operation See Section 14.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop mode • Single-wire mode MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 194 Freescale Semiconductor Serial Communications Interface (S08SCIV3) 14.1.3 Block Diagram INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER RSRC LOOP CONTROL Figure 14-3 shows the transmitter portion of the SCI. (Figure 14-4 shows the receiver portion of the SCI.) STOP M 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 LSB 1 × BAUD RATE CLOCK H START TO RECEIVE DATA IN L TO TxD PIN SHIFT DIRECTION LOAD FROM SCID PREAMBLE (ALL 1s) T8 PE PT TE SBK TXDIR BRK13 PARITY GENERATION BREAK (ALL 0s) SHIFT ENABLE TXINV SCI CONTROLS TxD TRANSMIT CONTROL TO TxD PIN LOGIC TxD DIRECTION TDRE TIE TC TCIE Tx INTERRUPT REQUEST Figure 14-3. SCI Transmitter Block Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 195 Serial Communications Interface (S08SCIV3) Figure 14-4 shows the receiver portion of the SCI. INTERNAL BUS (READ-ONLY) SCID – Rx BUFFER 16 × BAUD RATE CLOCK DIVIDE BY 16 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 ALL 1s MSB FROM RxD PIN DATA RECOVERY H LSB 0 M STOP SHIFT DIRECTION LOOPS RSRC SINGLE-WIRE LOOP CONTROL WAKE ILT WAKEUP LOGIC RWU FROM TRANSMITTER RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PE PT PARITY CHECKING PF PEIE ERROR INTERRUPT REQUEST Rx INTERRUPT REQUEST Figure 14-4. SCI Receiver Block Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 196 Freescale Semiconductor START L Serial Communications Interface (S08SCIV3) 14.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to SCIBDH to buffer the high half of the new value and then write to SCIBDL. The working value in SCIBDH does not change until SCIBDL is written. SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled (RE or TE bits in SCIC2 are written to 1). 7 6 5 4 3 2 1 0 R W Reset 0 0 0 SBR12 SBR11 0 SBR10 0 SBR9 0 SBR8 0 0 0 0 0 = Unimplemented or Reserved Figure 14-5. SCI Baud Rate Register (SCIBDH) Table 14-1. SCIBDH Register Field Descriptions Field 4:0 SBR[12:8] Description Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 14-2. 7 6 5 4 3 2 1 0 R SBR7 W Reset 0 0 0 0 0 1 0 0 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Figure 14-6. SCI Baud Rate Register (SCIBDL) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 197 Serial Communications Interface (S08SCIV3) Table 14-2. SCIBDL Register Field Descriptions Field 7:0 SBR[7:0] Description Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 14-1. 14.2.2 SCI Control Register 1 (SCIC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 R LOOPS W Reset 0 0 0 0 0 0 0 0 SCISWAI RSRC M WAKE ILT PE PT Figure 14-7. SCI Control Register 1 (SCIC1) Table 14-3. SCIC1 Register Field Descriptions Field 7 LOOPS Description Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. SCI Stops in Wait Mode 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU. 1 SCI clocks freeze while CPU is in wait mode. Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. 9-Bit or 8-Bit Mode Select 0 Normal — start + 8 data bits (LSB first) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop. Receiver Wakeup Method Select — Refer to Section 14.3.3.2, “Receiver Wakeup Operation” for more information. 0 Idle-line wakeup. 1 Address-mark wakeup. Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to Section 14.3.3.2.1, “Idle-Line Wakeup” for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. 6 SCISWAI 5 RSRC 4 M 3 WAKE 2 ILT MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 198 Freescale Semiconductor Serial Communications Interface (S08SCIV3) Table 14-3. SCIC1 Register Field Descriptions (continued) Field 1 PE Description Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. 0 PT 14.2.3 SCI Control Register 2 (SCIC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R TIE W Reset 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK Figure 14-8. SCI Control Register 2 (SCIC2) Table 14-4. SCIC2 Register Field Descriptions Field 7 TIE 6 TCIE 5 RIE 4 ILIE 3 TE Description Transmit Interrupt Enable (for TDRE) 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1. Transmission Complete Interrupt Enable (for TC) 0 Hardware interrupts from TC disabled (use polling). 1 Hardware interrupt requested when TC flag is 1. Receiver Interrupt Enable (for RDRF) 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF flag is 1. Idle Line Interrupt Enable (for IDLE) 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress. Refer to Section 14.3.2.1, “Send Break and Queued Idle,” for more details. When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 199 Serial Communications Interface (S08SCIV3) Table 14-4. SCIC2 Register Field Descriptions (continued) Field 2 RE Description Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1, the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. 0 Receiver off. 1 Receiver on. Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer to Section 14.3.3.2, “Receiver Wakeup Operation,” for more details. 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wakeup condition. Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10 or 11 bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Refer to Section 14.3.2.1, “Send Break and Queued Idle,” for more details. 0 Normal transmitter operation. 1 Queue break character(s) to be sent. 1 RWU 0 SBK 14.2.4 SCI Status Register 1 (SCIS1) This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status flags. 7 6 5 4 3 2 1 0 R W Reset TDRE TC RDRF IDLE OR NF FE PF 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-9. SCI Status Register 1 (SCIS1) Table 14-5. SCIS1 Register Field Descriptions Field 7 TDRE Description Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIS1 with TDRE = 1 and then write to the SCI data register (SCID). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being transmitted. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things: • Write to the SCI data register (SCID) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SBK in SCIC2 6 TC MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 200 Freescale Semiconductor Serial Communications Interface (S08SCIV3) Table 14-5. SCIS1 Register Field Descriptions (continued) Field 5 RDRF Description Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID). 0 Receive data register empty. 1 Receive data register full. Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from SCID yet. In this case, the new character (and all associated error information) is lost because there is no room to move it into SCID. To clear OR, read SCIS1 with OR = 1 and then read the SCI data register (SCID). 0 No overrun. 1 Receive overrun (new SCI data lost). Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and then read the SCI data register (SCID). 0 No noise detected. 1 Noise detected in the received character in SCID. Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIS1 with FE = 1 and then read the SCI data register (SCID). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error. Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the SCI data register (SCID). 0 No parity error. 1 Parity error. 4 IDLE 3 OR 2 NF 1 FE 0 PF MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 201 Serial Communications Interface (S08SCIV3) 14.2.5 SCI Status Register 2 (SCIS2) This register has one read-only status flag. Writes have no effect. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 BRK13 0 RAF 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-10. SCI Status Register 2 (SCIS2) Table 14-6. SCIS2 Register Field Descriptions Field 2 BRK13 Description Break Character Length — BRK13 is used to select a longer break character length. Detection of a framing error is not affected by the state of this bit. 0 Break character is 10 bit times (11 if M = 1) 1 Break character is 13 bit times (14 if M = 1) Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. 0 SCI receiver idle waiting for a start bit. 1 SCI receiver active (RxD input not idle). 0 RAF 14.2.6 SCI Control Register 3 (SCIC3) 7 6 5 4 3 2 1 0 R W Reset R8 T8 0 0 TXDIR 0 TXINV 0 ORIE 0 NEIE 0 FEIE 0 PEIE 0 = Unimplemented or Reserved Figure 14-11. SCI Control Register 3 (SCIC3) Table 14-7. SCIC3 Register Field Descriptions Field 7 R8 Description Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the MSB of the buffered data in the SCID register. When reading 9-bit data, read R8 before reading SCID because reading SCID completes automatic flag clearing sequences which could allow R8 and SCID to be overwritten with new data. Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire 9-bit value is transferred to the SCI shift register after SCID is written so T8 should be written (if it needs to change from its previous value) before SCID is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCID is written. 6 T8 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 202 Freescale Semiconductor Serial Communications Interface (S08SCIV3) Table 14-7. SCIC3 Register Field Descriptions (continued) Field 5 TXDIR Description TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1. Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF = 1. Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE = 1. Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF = 1. 4 TXINV1 3 ORIE 2 NEIE 1 FEIE 0 PEIE 1 Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle. 14.2.7 SCI Data Register (SCID) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. 7 6 5 4 3 2 1 0 R W Reset R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 0 Figure 14-12. SCI Data Register (SCID) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 203 Serial Communications Interface (S08SCIV3) 14.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI. 14.3.1 Baud Rate Generation As shown in Figure 14-13, the clock source for the SCI baud rate generator is the bus-rate clock. MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY 16 Tx BAUD RATE BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] × 16 Figure 14-13. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ±4 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 14.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown in Figure 14-3. The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIC2. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the SCI data register (SCID). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0, MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 204 Freescale Semiconductor Serial Communications Interface (S08SCIV3) selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCID. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD1 high, waiting for more characters to transmit. Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 Send Break and Queued Idle The SBK control bit in SCIC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE = 1) occurs. When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD1 pin. If there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin that is shared with TxD1 is an output driving a logic 1. This ensures that the TxD1 line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below. Table 14-8. Break Character Length BRK13 0 0 1 1 M 0 1 0 1 Break Character Length 10 bit times 11 bit times 13 bit times 14 bit times MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 205 Serial Communications Interface (S08SCIV3) 14.3.3 Receiver Functional Description In this section, the receiver block diagram (Figure 14-4) is used as a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained. The receiver is enabled by setting the RE bit in SCIC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to Section 14.4.1, “8- and 9-Bit Data Modes.” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section 14.3.4, “Interrupts and Status Flags,” for more details about flag clearing. 14.3.3.1 Data Sampling Technique The SCI receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD1 serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 206 Freescale Semiconductor Serial Communications Interface (S08SCIV3) In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 14.3.3.2 Receiver Wakeup Operation Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU = 1, it inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). When the RWU bit is set, the idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. It therefore will not generate an interrupt when this idle character occurs. The receiver will wake up and wait for the next data transmission which will set RDRF and generate an interrupt if enabled. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 Address-Mark Wakeup When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB of an address frame clears the receivers RWU bit before the stop bit is received and sets the RDRF flag. 14.3.4 Interrupts and Status Flags The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 207 Serial Communications Interface (S08SCIV3) masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCID. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD1 high. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID. The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then reading SCID. When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD1 line remains idle for an extended period of time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading SCID. After IDLE has been cleared, it cannot become set again until the receiver has received at least one new character and has set RDRF. If the associated error was detected in the received character that caused RDRF to be set, the error flags — noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF. These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag gets set instead and the data and any associated NF, FE, or PF condition is lost. 14.4 Additional SCI Functions The following sections describe additional SCI functions. 14.4.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIC3. For the receiver, the ninth bit is held in R8 in SCIC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 208 Freescale Semiconductor Serial Communications Interface (S08SCIV3) If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. 14.4.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module. 14.4.3 Loop Mode When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD1 pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 14.4.4 Single-Wire Operation When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD1 pin. The RxD1 pin is not used and reverts to a general-purpose port I/O pin. In single-wire mode, the TXDIR bit in SCIC3 controls the direction of serial data on the TxD1 pin. When TXDIR = 0, the TxD1 pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD1 pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD1 pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 209 Serial Communications Interface (S08SCIV3) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 210 Freescale Semiconductor Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction Figure 15-1 shows the MC9S08QG8/4 block diagram with the SPI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 211 Chapter 15 Serial Peripheral Interface (S08SPIV3) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices, see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 15-1. MC9S08QG8/4 Block Diagram Highlighting SPI Block and Pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 212 Freescale Semiconductor PORT B Serial Peripheral Interface (S08SPIV3) 15.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 15.1.2 Block Diagrams This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate. 15.1.2.1 SPI System Block Diagram Figure 15-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave select output. MASTER MOSI SPI SHIFTER 7 6 5 4 3 2 1 0 MISO MISO 7 6 MOSI SPI SHIFTER 5 4 3 2 1 0 SLAVE SPSCK CLOCK GENERATOR SPSCK SS SS Figure 15-2. SPI System Connections MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 213 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 15-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 15.1.2.2 SPI Module Block Diagram Figure 15-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls connections between MCU pins and the SPI module. When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 214 Freescale Semiconductor Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM SHIFT OUT SPI SHIFT REGISTER SHIFT IN SPC0 BIDIROE LSBFE SHIFT DIRECTION SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY M S MISO (SISO) S MOSI (MOMI) Rx BUFFER (READ SPID) MASTER CLOCK BUS RATE CLOCK MSTR SPIBR CLOCK GENERATOR MASTER/SLAVE MODE SELECT MODFEN MODE FAULT DETECTION SSOE CLOCK LOGIC SLAVE CLOCK M S MASTER/ SLAVE SPSCK SS SPRF SPTEF SPTIE SPI INTERRUPT REQUEST MODF SPIE Figure 15-3. SPI Module Block Diagram 15.1.3 SPI Baud Rate Generation As shown in Figure 15-4, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 215 Serial Peripheral Interface (S08SPIV3) PRESCALER BUS CLOCK DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 CLOCK RATE DIVIDER DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 MASTER SPI BIT RATE SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure 15-4. SPI Baud Rate Generation 15.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that are not controlled by the SPI. 15.2.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 15.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 15.2.3 MISO — Master Data In, Slave Data Out When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 15.2.4 SS — Slave Select When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select output (SSOE = 1). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 216 Freescale Semiconductor Serial Peripheral Interface (S08SPIV3) 15.3 15.3.1 Modes of Operation SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered. 15.4 Register Definition The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SPI registers. This section refers to registers and control bits only by their names, and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.4.1 SPI Control Register 1 (SPIC1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. 7 6 5 4 3 2 1 0 R SPIE W Reset 0 0 0 0 0 1 0 0 SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Figure 15-5. SPI Control Register 1 (SPIC1) Table 15-1. SPIC1 Field Descriptions Field 7 SPIE Description SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF) and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt SPI System Enable — Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty. 0 SPI system inactive 1 SPI system enabled SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested 6 SPE 5 SPTIE MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 217 Serial Peripheral Interface (S08SPIV3) Table 15-1. SPIC1 Field Descriptions (continued) Field 4 MSTR 3 CPOL Description Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 15.5.1, “SPI Clock Formats” for more details. 0 Active-high SPI clock (idles low) 1 Active-low SPI clock (idles high) Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer to Section 15.5.1, “SPI Clock Formats” for more details. 0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer 1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 15-2. LSB First (Shifter Direction) 0 SPI serial data transfers start with most significant bit 1 SPI serial data transfers start with least significant bit 2 CPHA 1 SSOE 0 LSBFE Table 15-2. SS Pin Function MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode General-purpose I/O (not SPI) General-purpose I/O (not SPI) SS input for mode fault Automatic SS output Slave Mode Slave select input Slave select input Slave select input Slave select input NOTE Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These changes should be performed as separate operations or unexpected behavior may occur. 15.4.2 SPI Control Register 2 (SPIC2) This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 MODFEN BIDIROE 0 0 SPISWAI 0 0 SPC0 0 0 0 0 0 = Unimplemented or Reserved Figure 15-6. SPI Control Register 2 (SPIC2) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 218 Freescale Semiconductor Serial Peripheral Interface (S08SPIV3) Table 15-3. SPIC2 Register Field Descriptions Field 4 MODFEN Description Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 15-2 for more details). 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1, BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect. 0 Output driver disabled so SPI data I/O pin acts as an input 1 SPI I/O pin enabled as an output SPI Stop in Wait Mode 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the output driver for the single bidirectional SPI I/O pin. 0 SPI uses separate pins for data input and data output 1 SPI configured for single-wire bidirectional operation 3 BIDIROE 1 SPISWAI 0 SPC0 15.4.3 SPI Baud Rate Register (SPIBR) This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time. 7 6 5 4 3 2 1 0 R W Reset 0 SPPR2 0 0 SPPR1 0 SPPR0 0 0 SPR2 0 0 SPR1 0 SPR0 0 = Unimplemented or Reserved Figure 15-7. SPI Baud Rate Register (SPIBR) Table 15-4. SPIBR Register Field Descriptions Field 6:4 SPPR[2:0] 2:0 SPR[2:0] Description SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler as shown in Table 15-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider (see Figure 15-4). SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in Table 15-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 15-4). The output of this divider is the SPI bit rate clock for master mode. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 219 Serial Peripheral Interface (S08SPIV3) Table 15-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Prescaler Divisor 1 2 3 4 5 6 7 8 Table 15-6. SPI Baud Rate Divisor SPR2:SPR1:SPR0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Rate Divisor 2 4 8 16 32 64 128 256 15.4.4 SPI Status Register (SPIS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0. Writes have no meaning or effect. 7 6 5 4 3 2 1 0 R W Reset SPRF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure 15-8. SPI Status Register (SPIS) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 220 Freescale Semiconductor Serial Peripheral Interface (S08SPIV3) Table 15-7. SPIS Register Field Descriptions Field 7 SPRF Description SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register. 0 No data available in the receive data buffer 1 Data available in the receive data buffer SPI Transmit Buffer Empty Flag — This bit is set when there is room in the transmit data buffer. It is cleared by reading SPIS with SPTEF set, followed by writing a data value to the transmit buffer at SPID. SPIS must be read with SPTEF = 1 before writing data to SPID or the SPID write will be ignored. SPTEF generates an SPTEF CPU interrupt request if the SPTIE bit in the SPIC1 is also set. SPTEF is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 0 SPI transmit buffer not empty 1 SPI transmit buffer empty Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1, then writing to SPI control register 1 (SPIC1). 0 No mode fault error 1 Mode fault error detected 5 SPTEF 4 MODF 15.4.5 R SPI Data Register (SPID) 7 6 5 4 3 2 1 0 Bit 7 W Reset 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Figure 15-9. SPI Data Register (SPID) Reads of this register return the data read from the receive data buffer. Writes to this register write data to the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer initiates an SPI transfer. Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte. Data may be read from SPID any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 221 Serial Peripheral Interface (S08SPIV3) 15.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts. During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, SPTEF is set, and a new transfer is started. Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable (LSBFE) bit is set, SPI data is shifted LSB first. When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See Section 15.5.1, “SPI Clock Formats” for more details. Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the transmit buffer has room for a new character. The SPRF flag indicates when a received character is available in the receive data buffer. The received character must be read out of the receive buffer (read SPID) before the next transfer is finished or a receive overrun error results. In the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 15.5.1 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. Figure 15-10 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 222 Freescale Semiconductor Serial Peripheral Interface (S08SPIV3) MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SS OUT (MASTER) SS IN (SLAVE) Figure 15-10. SPI Clock Formats (CPHA = 1) When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive high level between transfers. Figure 15-11 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 223 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) SPSCK (CPOL = 0) 1 2 ... 6 7 8 SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SS OUT (MASTER) SS IN (SLAVE) Figure 15-11. SPI Clock Formats (CPHA = 0) When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between transfers. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 224 Freescale Semiconductor Serial Peripheral Interface (S08SPIV3) 15.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check the flag bits to determine what event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 15.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1), and slave select output enable is clear (SSOE = 0). The mode fault detection feature can be used in a system where more than one SPI device might become a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected. When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled. MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User software should verify the error condition has been corrected before changing the SPI back to master mode. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 225 Serial Peripheral Interface (S08SPIV3) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 226 Freescale Semiconductor Chapter 16 Timer/Pulse-Width Modulator (S08TPMV2) 16.1 Introduction Figure 16-1 shows the MC9S08QG8/4 block diagram with the TPM highlighted. 16.1.1 ACMP/TPM Configuration Information The ACMP module can be configured to connect the output of the analog comparator to TPM input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPMCH0 pin is not available externally regardless of the configuration of the TPM module. 16.1.2 MTIM/TPM Configuration Information The external clock for the TPM module, TPMCLK, is selected by setting CLKS[B:A] = 1:1 in TPMSC, which selects the TCLK pin input. The TCLK input on PTA5 can be enabled as external clock inputs to both the MTIM and TPM modules simultaneously. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 227 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER MODULE (MTIM) SCL PORT A IIC MODULE (IIC) SDA 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) 4 ACMPO ACMP– ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16-BIT TIMER/PWM MODULE (TPM) SERIAL PERIPHERAL INTERFACE MODULE (SPI) TxD RxD PTB7/SCL/EXTAL PTB6/SDA/XTAL TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) ANALOG COMPARATOR (ACMP) PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL 4 TPMCH0 TPMCH1 SS MISO MOSI SPSCK PTB5/TPMCH1/SS PTB4/MISO PTB3/KBIP7/MOSI/ADP7 PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) EXTAL XTAL NOTES: 1 2 3 4 5 6 7 8 9 Not all pins or pin functions are available on all devices, see Table 1-1 for available functions on each device. Port pins are software configurable with pullup device if input port. Port pins are software configurable for output drive strength. Port pins are software configurable for output slew rate control. IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 16-1. MC9S08QG8/4 Block Diagram Highlighting TPM Block and Pins MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 228 Freescale Semiconductor PORT B Timer/Pulse-Width Modulator (S08TPMV2) 16.1.3 Features The TPM has the following features: • Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all channels • Clock sources independently selectable per TPM (multiple TPMs device) • Selectable clock sources (device dependent): bus clock, fixed system clock, external pin • Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs device) • Channel features: — Each channel may be input capture, output compare, or buffered edge-aligned PWM — Rising-edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs 16.1.4 Block Diagram Figure 16-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 229 Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK XCLK TPMxCLK SYNC CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 CLKSB CPWMS MAIN 16-BIT COUNTER 16-BIT COMPARATOR TPMMODH:TPMMODL CHANNEL 0 16-BIT COMPARATOR TPMC0VH:TPMC0VL 16-BIT LATCH MS0B ELS0B CLKSA PS2 PS1 PS0 COUNTER RESET TOF TOIE INTERRUPT LOGIC ELS0A PORT LOGIC CH0F INTERRUPT LOGIC TPMCH0 MS0A CH0IE INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TPMC1VH:TPMC1VL 16-BIT LATCH ELS1B ELS1A PORT LOGIC CH1F INTERRUPT LOGIC TPMCH1 MS1B MS1A CH1IE ... ... CHANNEL n 16-BIT COMPARATOR TPMCnVH:TPMCnVL 16-BIT LATCH MSnB MSnA CHnIE CHnF ELSnB ELSnA ... PORT LOGIC TPMCHn INTERRUPT LOGIC Figure 16-2. TPM Block Diagram The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMMODH:TPMMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any write to either byte of the TPMCNT counter resets the counter regardless of the data value written. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 230 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 16.2 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 16.2.1 External TPM Clock Sources When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and consequently the 16-bit counter for TPM are driven by an external clock source, TPMxCLK, connected to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL) or frequency-locked loop (FLL) frequency jitter effects. On some devices the external clock input is shared with one of the TPM channels. When a TPM channel is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not trying to use the same pin. 16.2.2 TPMCHn — TPM Channel n I/O Pins Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). See the Pins and Connections chapter for additional information about shared pin functions. 16.3 Register Definition The TPM includes: • An 8-bit status and control register (TPMSC) • A 16-bit counter (TPMCNTH:TPMCNTL) • A 16-bit modulo register (TPMMODH:TPMMODL) Each timer channel has: • An 8-bit status and control register (TPMCnSC) • A 16-bit channel value register (TPMCnVH:TPMCnVL) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all TPM registers. This section refers to registers and control bits only by their names. A MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 231 Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 16.3.1 Timer Status and Control Register (TPMSC) TPMSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R W Reset TOF TOIE 0 0 CPWMS 0 CLKSB 0 CLKSA 0 PS2 0 PS1 0 PS0 0 = Unimplemented or Reserved Figure 16-3. Timer Status and Control Register (TPMSC) Table 16-1. TPMSC Register Field Descriptions Field 7 TOF Description Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is generated when TOF equals 1. Reset clears TOIE. 0 TOF interrupts inhibited (use software polling) 1 TOF interrupts enabled Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS. 0 All TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register 1 All TPM channels operate in center-aligned PWM mode Clock Source Select — As shown in Table 16-2, this 2-bit field is used to disable the TPM system or select one of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the bus clock by an on-chip synchronization circuit. Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in Table 16-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the TPM system. 6 TOIE 5 CPWMS 4:3 CLKS[B:A] 2:0 PS[2:0] MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 232 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) Table 16-2. TPM Clock Source Selection CLKSB:CLKSA 0:0 0:1 1:0 1:1 1 TPM Clock Source to Prescaler Input No clock selected (TPM disabled) Bus rate clock (BUSCLK) Fixed system clock (XCLK) External source (TPMCLK)1,2 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2 If the external clock input is shared with channel n and is selected as the TPM clock source, the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try to use the same pin for a conflicting function. Table 16-3. Prescale Divisor Selection PS2:PS1:PS0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 TPM Clock Source Divided-By 1 2 4 8 16 32 64 128 16.3.2 Timer Counter Registers (TPMCNTH:TPMCNTL) The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMCNTH or TPMCNTL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMCNTH or TPMCNTL, or any write to the timer status/control register (TPMSC). Reset clears the TPM counter registers. 7 6 5 4 3 2 1 0 R W Reset Bit 15 14 13 12 11 10 9 Bit 8 Any write to TPMCNTH clears the 16-bit counter. 0 0 0 0 0 0 0 0 Figure 16-4. Timer Counter Register High (TPMCNTH) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 233 Timer/Pulse-Width Modulator (S08TPMV2) 7 6 5 4 3 2 1 0 R W Reset Bit 7 6 5 4 3 2 1 Bit 0 Any write to TPMCNTL clears the 16-bit counter. 0 0 0 0 0 0 0 0 Figure 16-5. Timer Counter Register Low (TPMCNTL) When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 16.3.3 Timer Counter Modulo Registers (TPMMODH:TPMMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock (CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing to TPMMODH or TPMMODL inhibits TOF and overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo disabled). 7 6 5 4 3 2 1 0 R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 Figure 16-6. Timer Counter Modulo Register High (TPMMODH) 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 16-7. Timer Counter Modulo Register Low (TPMMODL) It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 234 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) 16.3.4 Timer Channel n Status and Control Register (TPMCnSC) TPMCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R CHnF W Reset 0 0 0 0 0 0 CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 = Unimplemented or Reserved Figure 16-8. Timer Channel n Status and Control Register (TPMCnSC) Table 16-4. TPMCnSC Register Field Descriptions Field 7 CHnF Description Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event occurred on channel n Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE. 0 Channel n interrupt requests disabled (use software polling) 1 Channel n interrupt requests enabled Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 16-5. Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for input capture mode or output compare mode. Refer to Table 16-5 for a summary of channel mode and setup controls. Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown in Table 16-5, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin. 6 CHnIE 5 MSnB 4 MSnA 3:2 ELSn[B:A] MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 235 Timer/Pulse-Width Modulator (S08TPMV2) Table 16-5. Mode, Edge, and Level Selection CPWMS X 0 MSnB:MSnA XX 00 ELSnB:ELSnA 00 01 10 11 01 00 01 10 11 1X 1 XX 10 X1 10 X1 Edge-aligned PWM Center-aligned PWM Output compare Mode Configuration Pin not used for TPM channel; use as an external clock for the TPM or revert to general-purpose I/O Input capture Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up) If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. 16.3.5 Timer Channel Value Registers (TPMCnVH:TPMCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel value registers are cleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 Figure 16-9. Timer Channel Value Register High (TPMCnVH) 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 16-10. Timer Channel Value Register Low (TPMCnVL) In input capture mode, reading either byte (TPMCnVH or TPMCnVL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMCnSC register is written. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 236 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) In output compare or PWM modes, writing to either byte (TPMCnVH or TPMCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 16.4 Functional Description All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function. The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMSC. When CPWMS is set to 1, timer counter TPMCNT changes to an up-/down-counter and all channels in the associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 16.4.1 Counter All timer functions are based on the main 16-bit counter (TPMCNTH:TPMCNTL). This section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset. After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive. Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source for the TPM can be selected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate. Refer to Section 16.3.1, “Timer Status and Control Register (TPMSC)” and Table 16-2 for more information about clock source selection. When the microcontroller is in active background mode, the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter. As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMMODH:TPMMODL. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 237 Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMMODH:TPMMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1. The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the main 16-bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. Whenever either byte of the counter is read (TPMCNTH or TPMCNTL), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the first byte was read. The counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. The main timer counter can be reset manually at any time by writing any value to either byte of the timer count TPMCNTH or TPMCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. 16.4.2 Channel Mode Selection Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and buffered edge-aligned PWM. 16.4.2.1 Input Capture Mode With the input capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter into the channel value registers (TPMCnVH:TPMCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMCnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 238 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) 16.4.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin. In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control register (TPMCnSC). An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. 16.4.2.3 Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMMODH:TPMMODL). The duty cycle is determined by the setting in the timer channel value register (TPMCnVH:TPMCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible. As Figure 16-11 shows, the output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output compare forces the PWM signal high. OVERFLOW PERIOD PULSE WIDTH OVERFLOW OVERFLOW TPMCH OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 16-11. PWM Period and Pulse Width (ELSnA = 0) When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel value register (TPMCnVH:TPMCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPMCnVH or TPMCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the TPMCNTH:TPMCNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 239 Timer/Pulse-Width Modulator (S08TPMV2) 16.4.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMCnVH:TPMCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMMODH:TPMMODL. TPMMODH:TPMMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width = 2 x (TPMCnVH:TPMCnVL) period = 2 x (TPMMODH:TPMMODL); for TPMMODH:TPMMODL = 0x0001–0x7FFF Eqn. 16-1 Eqn. 16-2 If the channel value register TPMCnVH:TPMCnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If TPMCnVH:TPMCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting period is much longer than required for normal applications. TPMMODH:TPMMODL = 0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. Figure 16-12 shows the output compare value in the TPM channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMMODH:TPMMODL, then counts down until it reaches zero. This sets the period equal to two times TPMMODH:TPMMODL. COUNT = OUTPUT COMPARE (COUNT DOWN) COUNT = 0 OUTPUT COMPARE (COUNT UP) COUNT = TPMMODH:TPMM TPMMODH:TPMM TPM1C PULSE WIDTH 2x 2x PERIOD Figure 16-12. CPWM Period and Pulse Width (ELSnA = 0) Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers, TPMMODH, TPMMODL, TPMCnVH, and TPMCnVL, actually write to buffer registers. Values are MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 240 Freescale Semiconductor Timer/Pulse-Width Modulator (S08TPMV2) transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMCNT overflow requirement only applies to PWM channels, not output compares. Optionally, when TPMCNTH:TPMCNTL = TPMMODH:TPMMODL, the TPM can generate a TOF interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they will all update simultaneously at the start of a new period. Writing to TPMSC cancels any values written to TPMMODH and/or TPMMODL and resets the coherency mechanism for the modulo registers. Writing to TPMCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMCnVH:TPMCnVL. 16.5 TPM Interrupts The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. See the Resets, Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine. 16.5.1 Clearing Timer Interrupt Flags TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1) followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 16.5.2 Timer Overflow Interrupt Description The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 241 Timer/Pulse-Width Modulator (S08TPMV2) 16.5.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in Section 16.5.1, “Clearing Timer Interrupt Flags.” When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section 16.5.1, “Clearing Timer Interrupt Flags.” 16.5.4 PWM End-of-Duty-Cycle Events For channels that are configured for PWM operation, there are two possibilities: • When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. • When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. The flag is cleared by the 2-step sequence described in Section 16.5.1, “Clearing Timer Interrupt Flags.” MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 242 Freescale Semiconductor Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins. Debug is done through commands fed into the target MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. 17.1.1 Module Configuration The alternate BDC clock source is the ICSLCLK. This clock source is selected by clearing the CLKSW bit in the BDCSCR register. For details on ICSLCLK, see Section 10.4, “Functional Description” of the ICS chapter. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 243 Development Support 17.1.2 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode Features of the ICE system include: • Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W • Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: — Basic: A-only, A OR B — Sequence: A then B — Full: A AND B data, A AND NOT B data — Event (store data): Event-only B, A then event-only B — Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B) 17.2 Background Debug Controller (BDC) All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • Active background mode commands require that the target MCU is in active background mode (the user program is not running). Active background mode commands allow the CPU registers to be MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 244 Freescale Semiconductor Development Support • read or written, and allow the user to trace one user instruction at a time, or GO to the user program from active background mode. Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET, and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. BKGD 1 NO CONNECT 3 NO CONNECT 5 2 GND 4 RESET 6 VDD Figure 17-1. BDM Tool Connector 17.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the user’s application program. This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer to Section 17.2.2, “Communication Details.” If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 245 Development Support driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 17.2.2, “Communication Details,” for more detail. When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface. 17.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles. Figure 17-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 246 Freescale Semiconductor Development Support BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT TIME TARGET SENSES BIT LEVEL EARLIEST START OF NEXT BIT Figure 17-2. BDC Host-to-Target Serial Bit Timing Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 247 Development Support Figure 17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME SPEEDUP PULSE BKGD PIN 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 17-4. BDM Target-to-Host Serial Bit Timing (Logic 0) 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program. Table 17-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 17-1 to describe the coding structure of the BDC commands. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 248 Freescale Semiconductor Development Support / d AAAA RD WD RD16 WD16 SS CC RBKP WBKP = = = = = = = = = = = Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) separates parts of the command delay 16 target BDC clock cycles a 16-bit address in the host-to-target direction 8 bits of read data in the target-to-host direction 8 bits of write data in the host-to-target direction 16 bits of read data in the target-to-host direction 16 bits of write data in the host-to-target direction the contents of BDCSCR in the target-to-host direction (STATUS) 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 249 Development Support Table 17-1. BDC Command Summary Command Mnemonic SYNC ACK_ENABLE ACK_DISABLE BACKGROUND READ_STATUS WRITE_CONTROL READ_BYTE READ_BYTE_WS READ_LAST WRITE_BYTE WRITE_BYTE_WS READ_BKPT WRITE_BKPT GO TRACE1 TAGGO READ_A READ_CCR READ_PC READ_HX READ_SP READ_NEXT READ_NEXT_WS WRITE_A WRITE_CCR WRITE_PC WRITE_HX WRITE_SP WRITE_NEXT WRITE_NEXT_WS 1 Active BDM/ Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM n/a1 D5/d D6/d 90/d E4/SS C4/CC Coding Structure Description Request a timed reference pulse to determine target BDC communication speed Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled (ignore if ENBDM bit equals 0) Read BDC status from BDCSCR Write BDC controls in BDCSCR Read a byte from target memory Read a byte and report status Re-read byte from address just read and report status Write a byte to target memory Write a byte and report status Read BDCBKPT breakpoint register Write BDCBKPT breakpoint register Go to execute the user application program starting at the address currently in the PC Trace 1 user instruction at the address in the PC, then return to active background mode Same as GO but enable external tagging (HCS08 devices have no external tagging pin) Read accumulator (A) Read condition code register (CCR) Read program counter (PC) Read H and X register pair (H:X) Read stack pointer (SP) Increment H:X by one then read memory byte located at H:X Increment H:X by one then read memory byte located at H:X. Report status and data. Write accumulator (A) Write condition code register (CCR) Write program counter (PC) Write H and X register pair (H:X) Write stack pointer (SP) Increment H:X by one, then write memory byte located at H:X Increment H:X by one, then write memory byte located at H:X. Also report status. E0/AAAA/d/RD E1/AAAA/d/SS/RD E8/SS/RD C0/AAAA/WD/d C1/AAAA/WD/d/SS E2/RBKP C2/WBKP 08/d 10/d 18/d 68/d/RD 69/d/RD 6B/d/RD16 6C/d/RD16 6F/d/RD16 70/d/RD 71/d/SS/RD 48/WD/d 49/WD/d 4B/WD16/d 4C/WD16/d 4F/WD16/d 50/WD/d 51/WD/d/SS The SYNC command is a special operation that does not have a command code. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 250 Freescale Semiconductor Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16 cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128 BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 17.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the BDC module. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 251 Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. The system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user’s memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Most of the debug module’s functions are used during development, and user programs rarely access any of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section 17.3.6, “Hardware Breakpoints.” 17.3.1 Comparators A and B Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actually executed as opposed to only being read from memory into the instruction queue. The comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s write data bus is used. Otherwise, the CPU’s read data bus is used. The currently selected trigger mode determines what the debugger logic does when a comparator detects a qualified match condition. A match can cause: • Generation of a breakpoint to the CPU • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) 17.3.2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 252 Freescale Semiconductor Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port. In the event-only trigger modes (see Section 17.3.5, “Trigger Modes”), 8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-flow address or a change-of-flow address appears during the next two bus cycles after a trigger event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is not armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 17.3.3 Change-of-Flow Information To minimize the amount of information stored in the FIFO, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. With knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-flow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are not conditional, these events do not cause change-of-flow information to be stored in the FIFO. Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow information. 17.3.4 Tag vs. Force Breakpoints and Triggers Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 253 Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 17.3.5 Trigger Modes The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace), or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected (end trigger). A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally known at a particular address. The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines whether the CPU request will be a tag request or a force request. A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 254 Freescale Semiconductor Development Support A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of comparator B is not used. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within the same bus cycle to cause a trigger. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger event occurs each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. Inside Range (A ≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 255 Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 17.4 Register Definition This section contains the descriptions of the BDC and DBG registers and control bits. Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 17.4.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For example, the ENBDM control bit may not be written while the MCU is in active background mode. (This prevents the ambiguous condition of the control bit forbidding active background mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 256 Freescale Semiconductor Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 5 4 3 2 1 0 R ENBDM W Normal Reset Reset in Active BDM: 0 1 BDMACT BKPTEN 0 1 0 0 FTS 0 0 CLKSW 0 1 WS WSF DVF 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-5. BDC Status and Control Register (BDCSCR) Table 17-2. BDCSCR Register Field Descriptions Field 7 ENBDM Description Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands Background Mode Active Status — This is a read-only status bit. 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock source. 0 Alternate BDC clock source 1 MCU bus clock 6 BDMACT 5 BKPTEN 4 FTS 3 CLKSW MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 257 Development Support Table 17-2. BDCSCR Register Field Descriptions (continued) Field 2 WS Description Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. 0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to active background mode Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode Data Valid Failure Status — This status bit is not used in the MC9S08QG8/4 because it does not have any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 1 WSF 0 DVF 17.4.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. Breakpoints are normally set while the target MCU is in active background mode before running the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section 17.2.4, “BDC Hardware Breakpoint.” 17.4.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 258 Freescale Semiconductor Development Support 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 BDFR1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 17-6. System Background Debug Force Reset Register (SBDFR) Table 17-3. SBDFR Register Field Description Field 0 BDFR Description Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 17.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so they are accessible to normal application programs. These registers are rarely if ever accessed by normal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic. 17.4.3.1 Debug Comparator A High Register (DBGCAH) This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.2 Debug Comparator A Low Register (DBGCAL) This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.3 Debug Comparator B High Register (DBGCBH) This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 259 Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information. 17.4.3.6 Debug FIFO Low Register (DBGFL) This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case. Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 260 Freescale Semiconductor Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R DBGEN W Reset 0 0 0 0 0 0 0 0 ARM TAG BRKEN RWA RWAEN RWB RWBEN Figure 17-7. Debug Control Register (DBGC) Table 17-4. DBGC Register Field Descriptions Field 7 DBGEN 6 ARM Description Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. 0 DBG disabled 1 DBG enabled Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match. 0 R/W is not used in comparison A 1 R/W is used in comparison A R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match. 0 R/W is not used in comparison B 1 R/W is used in comparison B 5 TAG 4 BRKEN 3 RWA 2 RWAEN 1 RWB 0 RWBEN MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 261 Development Support 17.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 5 4 3 2 1 0 R TRGSEL W Reset 0 0 BEGIN 0 0 TRG3 TRG2 0 TRG1 0 TRG0 0 0 0 0 = Unimplemented or Reserved Figure 17-8. Debug Trigger Register (DBGT) Table 17-5. DBGT Register Field Descriptions Field 7 TRGSEL Description Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) Select Trigger Mode — Selects one of nine triggering modes, as described below. 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A ≤ address ≤ B 1000 Outside range: address < A or address > B 1001 – 1111 (No trigger) 6 BEGIN 3:0 TRG[3:0] 17.4.3.9 Debug Status Register (DBGS) This is a read-only status register. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 262 Freescale Semiconductor Development Support 7 6 5 4 3 2 1 0 R W Reset AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-9. Debug Status Register (DBGS) Table 17-6. DBGS Register Field Descriptions Field 7 AF Description Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming. 0 Comparator A has not matched 1 Comparator A match Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B condition was met since arming. 0 Comparator B has not matched 1 Comparator B match Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1 to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8 6 BF 5 ARMF 3:0 CNT[3:0] MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 263 Development Support MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 264 Freescale Semiconductor Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table A-1. Absolute Maximum Ratings Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range 1 Symbol VDD IDD VIn ID Tstg Value –0.3 to +3.8 120 –0.3 to VDD + 0.3 ± 25 –55 to 150 Unit V mA V mA °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 265 Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table A-2. Thermal Characteristics Rating Operating temperature range (packaged) C M Thermal resistance Single-layer board 8-pin PDIP 8-pin NB SOIC 8-pin DFN 16-pin PDIP 16-pin TSSOP 16-pin QFN 24-pin QFN Thermal resistance Four-layer board 8-pin PDIP 8-pin NB SOIC 8-pin DFN 16-pin PDIP 16-pin TSSOP 16-pin QFN 24-pin QFN θJA 72 87 41 53 86 36 44 °C/W θJA 113 150 179 78 133 132 125 °C/W TA Symbol Value TL to TH –40 to 85 –40 to 125 °C Unit The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. A-1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 266 Freescale Semiconductor Appendix A Electrical Characteristics Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 2.3 V) (all digital inputs) Input high voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs) Input low voltage (VDD > 2.3 V) (all digital inputs) Input low voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs) Input hysteresis (all digital inputs) Input leakage current (Per pin) VIn = VDD or VSS, all input only pins High impedance (off-state) leakage current (per pin) VIn = VDD or VSS, all input/output Internal pullup resistors3,4 VPOR VBG VIH 1.18 0.70 × VDD 0.85 × VDD — VIL Vhys |IIn| |IOZ| RPU — 0.06 × VDD — — 17.5 0.025 0.025 VLVWL VLVWH VLVDL 1.80 1.88 2.35 2.35 2.08 2.16 1.82 1.90 2.40 2.40 2.1 2.19 1.4 1.20 1.21 — V — 0.35 × VDD 0.30 × VDD — 1.0 1.0 52.5 V V μA μA kΩ 1.91 1.99 2.5 2.5 2.2 2.27 V V V V V VLVDH 2.08 2.16 2.1 2.19 2.2 2.27 V Symbol VRAM Min VPOR1, 2 Typical Max — Unit V MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 269 Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Parameter Internal pulldown resistor (KBI) Output high voltage — low drive (PTxDSn = 0) IOH = –2 mA (VDD ≥ 1.8 V) Output high voltage — high drive (PTxDSn = 1) IOH = –10 mA (VDD ≥ 2.7 V) IOH = –6 mA (VDD ≥ 2.3 V) IOH = –3 mA (VDD ≥ 1.8 V) Maximum total IOH for all port pins Output low voltage — low drive (PTxDSn = 0) IOL = 2.0 mA (VDD ≥ 1.8 V) Output low voltage — high drive (PTxDSn = 1) IOL = 10.0 mA (VDD ≥ 2.7 V) IOL = 6 mA (VDD ≥ 2.3 V) IOL = 3 mA (VDD ≥ 1.8 V) Maximum total IOL for all port pins DC injection current 2, 5, 6, 7 VIN < VSS, VIN > VDD Single pin limit Total MCU limit, includes sum of all stressed pins Input capacitance (all non-supply pins) 1 2 3 4 5 6 7 Symbol RPD Min 17.5 VDD – 0.5 Typical Max 52.5 — Unit kΩ VOH VDD – 0.5 | IOHT | — — VOL — — — — — — — 60 0.5 V mA V 0.5 0.5 0.5 60 mA IOLT IIC –0.2 –5 — 0.2 5 7 mA mA pF CIn RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR. This parameter is characterized and not tested on each device. Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown. PTA5/IRQ/TCLK/RESET pullup resistor may not pullup to the specified minimum VIH. However, all ports are functionally tested to guarantee that a logic 1 will be read on any port input when the pullup is enabled and no DC load is present on the pin. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 270 Freescale Semiconductor Appendix A Electrical Characteristics PULLUP RESISTOR TYPICALS 40 PULLUP RESISTOR (kΩ) 35 30 25 20 PULLDOWN RESISTOR (kΩ) 85°C 25°C –40°C 40 35 30 25 20 PULLDOWN RESISTOR TYPICALS 85°C 25°C –40°C 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 3.6 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure A-1. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) 1.2 1 0.8 VOL (V) 0.6 0.4 0.2 0 0 TYPICAL VOL VS IOL AT VDD = 3.0 V 85°C 25°C –40°C 0.2 0.15 VOL (V) 0.1 0.05 0 TYPICAL VOL VS VDD 85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA 5 10 IOL (mA) 15 20 1 2 VDD (V) 3 4 Figure A-2. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0) 1 0.8 0.6 VOL (V) TYPICAL VOL VS IOL AT VDD = 3.0 V 85°C 25°C –40°C TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 IOL = 3 mA 1 2 VDD (V) 3 4 IOL = 6 mA 85°C 25°C –40°C 0.4 0.2 0 0 10 IOL (mA) 20 30 IOL = 10 mA Figure A-3. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 271 Appendix A Electrical Characteristics 1.2 1 VDD – VOH (V) 0.8 0.6 0.4 0.2 0 0 TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 85°C 25°C –40°C 0.25 0.2 VDD – VOH (V) 0.15 0.1 0.05 0 TYPICAL VDD – VOH VS VDD AT SPEC IOH 85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA –5 –10 IOH (mA)) –15 –20 1 2 VDD (V) 3 4 Figure A-4. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) 0.4 0.8 TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V TYPICAL VDD – VOH VS VDD AT SPEC IOH 85°C 25°C –40°C VDD – VOH (V) 0.6 0.4 0.2 0 0 VDD – VOH (V) 85°C 25°C –40°C 0.3 0.2 0.1 0 1 IOH = –10 mA IOH = –6 mA IOH = –3 mA 2 VDD (V) 3 4 –5 –10 –15 –20 IOH (mA) –25 –30 Figure A-5. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1) A.6 Supply Current Characteristics Table A-7. Supply Current Characteristics Parameter Symbol RIDD RIDD WIDD S1IDD 2 VDD (V)1 3 2 3 2 3 3 Typical2 3.5 mA 2.5 mA 490 μA 370 μA 1mA 475 nA 470 nA 600 nA 550 nA 750 nA 680 nA Max 5mA — 1mA — 1.5mA 10μA 1.2μA — 15 μA 2 μA — 35 μA 6 μA — T (°C) 125 125 125 125 125 125 85 85 125 85 85 125 85 85 This section includes information about power supply current in various operating modes. Run supply current measured in FBE mode at fBus = 8 MHz Run supply current 3 measured in FBE mode at fBus = 1 MHz Wait mode supply current 4 measured in FBE at 8 MHz Stop1 mode supply current 3 Stop2 mode supply current S2IDD 3 2 Stop3 mode supply current S3IDD 3 2 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 272 Freescale Semiconductor Appendix A Electrical Characteristics Table A-7. Supply Current Characteristics Parameter RTI adder to stop1, stop2 or stop3 4 LVD adder to stop3 (LVDE = LVDSE = 1) Adder to stop3 for oscillator enabled 5 (EREFSTEN =1) 1 2 Symbol — — — VDD (V)1 3 2 3 2 3 2 Typical2 300 nA 300 nA 70 μA 60 μA 5 μA 4 μA Max — — — — — — T (°C) 85 85 85 85 85 85 3-V values are 100% tested; 2-V values are characterized but not tested. Typicals are measured at 25°C. 3 Does not include any DC loads on port pins. 4 Most customers are expected to find that auto-wakeup from a stop mode can be used instead of the higher current wait mode. 5 Values given under the following conditions: low range operation (RANGE = 0), Loss-of-clock disabled (LOCD = 1), low-power oscillator (HGO = 0). 4 FEE 2-MHz Crystal, 8-MHz Bus 3 2 IDD (mA) 1 FEE 32-kHz Crystal, 1-MHz Bus FBE 2-MHz Crystal, 1-MHz Bus 0 1.8 2.1 2.4 2.7 VDD (V) 3 3.3 3.6 Figure A-6. Typical Run IDD for FBE and FEE, IDD vs. VDD (ACMP and ADC off, All Other Modules Enabled) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 273 Appendix A Electrical Characteristics A.7 External Oscillator (XOSC) and Internal Clock Source (ICS) Characteristics Reference Figure A-7 for crystal or resonator circuit. Table A-8. XOSC and ICS Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Internal reference frequency — factory trimmed at VDD = 3.6V and temperature = 25°C Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode 1 High range (RANGE = 1), high gain (HGO = 1), FBELP mode High range (RANGE = 1), low power (HGO = 0), FBELP mode Load capacitors Feedback resistor Low range (32 kHz to 38.4 kHz) High range (1 MHz to 16 MHz) Series resistor — Low range Low Gain (HGO = 0) High Gain (HGO = 1) Series resistor — High range Low Gain (HGO = 0) High Gain (HGO = 1) ≥ 8 MHz 4 MHz 1 MHz Crystal start-up time 3, 4 Low range, low power Low range, high power High range, low power High range, high power Internal reference start-up time Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode 2 FBELP mode Internal reference frequency - untrimmed5 Internal reference frequency - trimmed DCO output frequency range - untrimmed5 fdco= 512 * fint_ut DCO output frequency range - trimmed RS — — Symbol fint_ft Min — Typ 31.25 Max — Unit kHz flo fhi fhi fhi C1 C2 32 1 1 1 — — — — See Note 2 38.4 5 16 8 kHz MHz MHz MHz RF 10 1 MΩ MΩ kΩ 0 100 — — RS — — — — — — — — 0 0 0 200 400 5 15 60 0 10 20 — — — — 100 kΩ t CSTL t CSTH ms tIRST fextal fint_ut fint_t fdco_ut fdco_t μs 0.03125 0 25 31.25 12.8 16 — — 32.7 — 16.8 — 5 20 41.66 39.06 21.33 20 MHz MHz kHz kHz MHz MHz MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 274 Freescale Semiconductor Appendix A Electrical Characteristics Table A-8. XOSC and ICS Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Resolution of trimmed DCO output frequency at fixed voltage and temperature 4 Total deviation of DCO output from trimmed frequency:3 At 8MHz over full voltage and temperature range (M Suffix) At 8MHz over full voltage and temperature rang (C Suffix) At 8MHz and 3.6V from 0 to 70°C FLL acquisition time 4,6 Long term jitter of DCO output clock (averaged over 2-ms interval) 7 1 2 3 4 5 6 Symbol Δfdco_res_t Min — Typ ±0.1 –1.5 to ±0.5 –1.0 to ±0.5 ±0.5 Max ± 0.2 ±3 ±2 ±1 1.5 Unit %fdco — Δfdco_t — — tAcquire CJitter — %fdco (C Suffix) ms %fdco 0.02 0.2 7 When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. See crystal or resonator manufacturer’s recommendation. This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. XOSC EXTAL XTAL RS RF C1 Crystal or Resonator C2 Figure A-7. Typical Crystal or Resonator Circuit MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 275 Appendix A Electrical Characteristics A.8 AC Characteristics This section describes timing characteristics for each peripheral system. A.8.1 Control Timing Table A-9. Control Timing Parameter Symbol fBus tRTI textrst tILIH Min 0 700 100 100 1.5 tcyc 100 1.5 tcyc — — 500 100 Typ1 — 1000 — — Max 10 1300 — — Unit MHz μs ns ns Bus frequency (tcyc = 1/fBus) Real-time interrupt internal oscillator period External reset pulse width2 IRQ pulse width Asynchronous path2 Synchronous path3 KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 5 1 2 tILIH, tIHIL — — ns tRise, tFall tMSSU tMSH 3 30 — — — — — — ns ns μs Data in Typical column was characterized at 3.0 V, 25°C. This is the shortest pulse that is guaranteed to be recognized. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 85°C. 5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 276 Freescale Semiconductor Appendix A Electrical Characteristics Period (μs) 1600 1400 1200 1000 800 600 400 200 0 –40 –20 0 20 40 Temperature (°C) 60 80 100 120 140 Figure A-8. Typical RTI Clock Period vs. Temperature textrst RESET PIN Figure A-9. Reset Timing tIHIL KBIPx IRQ/KBIPx tILIH Figure A-10. IRQ/KBIPx Timing A.8.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 277 Appendix A Electrical Characteristics Table A-10. TPM/MTIM Input Timing Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit Hz tcyc tcyc tcyc tcyc tTCLK tclkh TCLK tclkl Figure A-11. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure A-12. Timer Input Capture Pulse A.8.3 SPI Timing Table A-11. SPI Timing Table A-11 and Figure A-13 through Figure A-16 describe the timing requirements for the SPI system. No. Operating frequency Master Slave 1 SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Function Symbol fop Min fBus/2048 0 Max fBus/2 fBus/4 2048 — — — — — Unit Hz tSPSCK 2 4 tLead 1/2 1 1/2 1 tcyc tcyc tSPSCK tcyc tSPSCK tcyc 2 3 tLag MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 278 Freescale Semiconductor Appendix A Electrical Characteristics Table A-11. SPI Timing (continued) No. 4 Function Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol tWSPSCK tcyc – 30 tcyc – 30 tSU 15 15 tHI 0 25 ta tdis tv — — tHO 0 0 tRI tRO tFI tFO — — — — — — tcyc – 25 25 tcyc – 25 25 ns ns ns ns ns ns 25 25 ns ns — — — — 1 1 ns ns tcyc tcyc — — ns ns 1024 tcyc — ns ns Min Max Unit 5 6 7 8 9 10 11 12 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 279 Appendix A Electrical Characteristics SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 MSB IN2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-13. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT(2) 6 MSB IN(2) BIT 6 . . . 1 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN 4 11 12 12 11 3 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-14. SPI Master Timing (CPHA =1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 280 Freescale Semiconductor Appendix A Electrical Characteristics SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT) NOTE: 12 11 3 4 4 11 12 8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1 10 10 SEE NOTE SLAVE LSB OUT LSB IN 1. Not defined but normally MSB of character just received Figure A-15. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 3 11 10 BIT 6 . . . 1 SLAVE LSB OUT 8 NOTE: 1. Not defined but normally LSB of character just received Figure A-16. SPI Slave Timing (CPHA = 1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 281 Appendix A Electrical Characteristics A.9 Analog Comparator (ACMP) Electricals Table A-12. Analog Comparator Electrical Specifications Characteristic Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT 3.0 — — Min 1.80 — VSS – 0.3 Typical — 20 — 20 9.0 — — Max 3.6 — VDD 40 15.0 1.0 1.0 Unit V μA V mV mV μA μs Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay A.10 ADC Characteristics Table A-13. 3 Volt 10-bit ADC Operating Conditions Conditions Absolute Symbol VDD VADIN CADIN RADIN 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) RAS — — — fADCK 0.4 0.4 — — — — — 5 10 10 8.0 4.0 MHz Min 1.8 VSS — — Typical1 — — 4.5 5 Max 3.6 VDD 5.5 7 Unit V V pF kΩ kΩ External to MCU Comment Characteristic Supply voltage Input voltage Input capacitance Input resistance Analog source resistance ADC conversion clock frequency 1 High Speed (ADLPC=0) Low Power (ADLPC=1) Typical values assume VDD = 3.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 282 Freescale Semiconductor Appendix A Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + – + – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure A-17. ADC Input Impedance Equivalency Diagram Table A-14. 3 Volt 10-bit ADC Characteristics Characteristic Supply current ADLPC=1 ADLSMP=1 ADCO=1 Supply current ADLPC=1 ADLSMP=0 ADCO=1 Supply current ADLPC=0 ADLSMP=1 ADCO=1 Supply current ADLPC=0 ADLSMP=0 ADCO=1 ADC asynchronous clock source High speed (ADLPC=0) Low power (ADLPC=1) Conditions Symb IDDAD Min — Typ1 120 Max — Unit μA Comment IDDAD — 202 — μA IDDAD — 288 — μA IDDAD — 532 646 μA fADACK 2 1.25 3.3 2 5 3.3 MHz tADACK = 1/fADACK MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 283 Appendix A Electrical Characteristics Table A-14. 3 Volt 10-bit ADC Characteristics (continued) Characteristic Conversion time (including sample time) Sample time Conditions Short sample (ADLSMP=0) Long sample (ADLSMP=1) Short sample (ADLSMP=0) Long sample (ADLSMP=1) Total unadjusted error 10 bit mode 8 bit mode Differential non-linearity 10 bit mode 8 bit mode DNL ETUE tADS Symb tADC Min — — — — — — — — Typ1 20 40 3.5 23.5 ±1.5 ±0.7 ±0.5 ±0.3 ±0.5 ±0.3 ±1.5 ±0.5 ±1.0 ±0.5 — — ±0.2 ±0.1 1.646 1.769 701.2 Max — — — — ±3.5 ±1.5 ±1.0 ±0.5 ±1.0 ±0.5 ±2.1 ±0.7 ±1.5 ±0.5 ±0.5 ±0.5 ±4 ±1.2 — — — mV mV/°C LSB2 Pad leakage3 * RAS LSB2 LSB2 VADIN = VDD LSB2 VADIN = VSS LSB2 LSB2 Unit ADCK cycles ADCK cycles LSB2 Comment See Table 9-12 for conversion time variances Includes quantization Monotonicity and no missing codes guaranteed Integral non-linearity 10 bit mode 8 bit mode INL — — Zero-scale error 10 bit mode 8 bit mode EZS — — Full-scale error 10 bit mode 8 bit mode EFS 0 0 Quantization error 10 bit mode 8 bit mode EQ — — Input leakage error 10 bit mode 8 bit mode EIL 0 0 Temp sensor slope Temp sensor voltage 1 -40°C– 25°C 25°C– 85°C 25°C m — — VTEMP25 — Typical values assume VDD = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Based on input pad leakage current. Refer to pad electricals. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 284 Freescale Semiconductor Appendix A Electrical Characteristics A.11 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table A-15. FLASH Characteristics Characteristic Supply voltage for program/erase: T ≤ 85°C T > 85 °C Supply voltage for read operation Internal FCLK frequency1 location)(2) VRead fFCLK tFcyc tprog tBurst tPage tMass 10,000 tD_ret 15 Vprog/erase 1.8 2.1 1.8 150 5 — — — — — 9 4 4000 20,000 — 100,000 100 — — — 3.6 3.6 3.6 200 6.67 V kHz μs tFcyc tFcyc tFcyc tFcyc cycles years V Symbol Min Typical Max Unit Internal FCLK period (1/FCLK) Byte program time (random Byte program time (burst Page erase Mass erase time2 time(2) endurance3 mode)(2) Program/erase TL to TH = –40°C to + 125°C T = 25°C Data retention4 1 2 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how Motorola defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Motorola defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 285 Appendix A Electrical Characteristics A.12 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. A.12.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table A-16. Radiated Emissions, Electric Field Parameter Symbol VRE_TEM Conditions VDD = 3.3 V TA = +25oC package type 16 TSSOP Frequency 0.15 – 50 MHz 50 – 150 MHz 150 – 500 MHz 500 – 1000 MHz IEC Level SAE Level 1 fOSC/fBUS 4-MHz crystal 10-MHz bus Level1 (Max) TBD TBD TBD TBD TBD TBD Unit dBμV Radiated emissions, electric field — — Data based on qualification test results. A.12.2 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below Table A-17. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 286 Freescale Semiconductor Appendix A Electrical Characteristics Table A-17. Conducted Susceptibility, EFT/B Parameter Symbol Conditions fOSC/fBUS Result A Conducted susceptibility, electrical fast transient/burst (EFT/B) VDD = 3.3V TA = +25oC package type TBD TBD crystal TBD bus B C D 1 Amplitude1 (Min) TBD TBD Unit VCS_EFT kV TBD TBD Data based on qualification test results. Not tested in production. The susceptibility performance classification is described in Table A-18. Table A-18. Susceptibility Performance Classification Result A B No failure Self-recovering failure Soft failure Performance Criteria The MCU performs as designed during and after exposure. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation. C D Hard failure E Damage MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 287 Appendix A Electrical Characteristics MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 288 Freescale Semiconductor Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information Table B-1. Device Numbering System Device Number1 FLASH MC9S08QG8 8K Memory RAM 512 24-Pin 24 QFN Available Packages2 16-Pin 16 PDIP 16 QFN 16 TSSOP 16 QFN 16 TSSOP 8-Pin 8 DFN 8 NB SOIC 8 DFN 8 PDIP 8 NB SOIC This section contains ordering information for MC9S08QG8 and MC9S08QG4 devices. MC9S08QG4 1 2 4K 256 24 QFN See Table 1-1 for a complete description of modules included on each device. See Table B-2 for package information. B.1.1 Device Numbering Scheme MC 9 S08 QG 8 (4) X XX E RoHS compliance indicator (E = yes) Package designator (see Table B-2) Temperature range (C = –40°C to +85°C) (M = –40°C to +125°C) 4M77B1. Memory Size (in Kbytes) Status (MC = Fully Qualified) Memory (9 = FLASH-based) Core 1 Family Only maskset 4M77B has this additional number. B.2 Mechanical Drawings The following pages are mechanical specifications for MC9S08QG8/4 package options. See Table B-2 for the document number for each package type. Table B-2. Package Information Pin Count 24 16 16 16 Type QFN PDIP QFN TSSOP Designator FK PB FF DT Document No. 98ARL10605D 98ASB42431B 98ARE10614D 98ASH70247A MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 289 Appendix B Ordering Information and Mechanical Drawings Table B-2. Package Information (continued) Pin Count 8 8 8 Type DFN PDIP NB SOIC Designator FQ PA DN Document No. 98ARL10557D 98ASB42420B 98ASB42564B MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 290 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2009. All rights reserved. M C9S08QG8 Rev. 5, 11/2009