MC9S08RC16CFJE

MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 Data Sheet HCS08 Microcontrollers MC9S08RG60/D Rev. 1.11 06/2005 freescale.com MC9S08RG60 Data Sheet Covers: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 MC9S08RG60/D Rev. 1.11 06/2005 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Version Number 1.11 Revision Date 06/2005 Description of Changes Added 48 QFN package and official mechanical drawings; suppled TBD values for IRO VOL; updated tRTI values; re-emphasized that KBI2 will not wake the MCU from stop2 mode. This product contains SuperFlash® technology licensed from SST. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. List of Chapters Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Appendix A Appendix B Introduction............................................................................. 15 Pins and Connections ............................................................ 19 Modes of Operation ................................................................ 29 Memory .................................................................................... 35 Resets, Interrupts, and System Configuration .................... 57 Parallel Input/Output .............................................................. 73 Central Processor Unit (S08CPUV2) ..................................... 87 Carrier Modulator Timer (S08CMTV1)................................. 107 Keyboard Interrupt (S08KBIV1) ........................................... 123 Timer/PWM Module (S08TPMV1)......................................... 129 Serial Communications Interface (S08SCIV1).................... 145 Serial Communications Interface (S08SCIV1).................... 147 Serial Peripheral Interface (S08SPIV3) ............................... 163 Analog Comparator (S08ACMPV1) ..................................... 179 Development Support .......................................................... 183 Electrical Characteristics..................................................... 205 Ordering Information and Mechanical Drawings............... 219 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 5 Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 1.4 Overview .........................................................................................................................................15 Features ...........................................................................................................................................15 1.2.1 Devices in the MC9S08RC/RD/RE/RG Series ..............................................................16 MCU Block Diagram ......................................................................................................................17 System Clock Distribution ..............................................................................................................18 Chapter 2 Pins and Connections 2.1 2.2 2.3 Introduction .....................................................................................................................................19 Device Pin Assignment ...................................................................................................................19 Recommended System Connections ...............................................................................................21 2.3.1 Power ..............................................................................................................................23 2.3.2 Oscillator ........................................................................................................................23 2.3.3 PTD1/RESET .................................................................................................................23 2.3.4 Background/Mode Select (PTD0/BKGD/MS) ...............................................................24 2.3.5 IRO Pin Description .......................................................................................................24 2.3.6 General-Purpose I/O and Peripheral Ports .....................................................................24 2.3.7 Signal Properties Summary ............................................................................................25 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................29 Features ...........................................................................................................................................29 Run Mode ........................................................................................................................................29 Active Background Mode ................................................................................................................29 Wait Mode .......................................................................................................................................30 Stop Modes ......................................................................................................................................31 3.6.1 Stop1 Mode ....................................................................................................................31 3.6.2 Stop2 Mode ....................................................................................................................31 3.6.3 Stop3 Mode ....................................................................................................................32 3.6.4 Active BDM Enabled in Stop Mode ...............................................................................33 3.6.5 LVD Reset Enabled ........................................................................................................33 3.6.6 On-Chip Peripheral Modules in Stop Mode ...................................................................33 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 7 Section Number Title Chapter 4 Memory Page 4.1 4.2 4.3 4.4 4.5 4.6 MC9S08RC/RD/RE/RG Memory Map ..........................................................................................35 4.1.1 Reset and Interrupt Vector Assignments ........................................................................36 Register Addresses and Bit Assignments ........................................................................................38 RAM ................................................................................................................................................42 FLASH ............................................................................................................................................42 4.4.1 Features ...........................................................................................................................43 4.4.2 Program and Erase Times ...............................................................................................43 4.4.3 Program and Erase Command Execution .......................................................................44 4.4.4 Burst Program Execution ...............................................................................................45 4.4.5 Access Errors ..................................................................................................................46 4.4.6 FLASH Block Protection ...............................................................................................47 4.4.7 Vector Redirection ..........................................................................................................48 Security ............................................................................................................................................48 FLASH Registers and Control Bits .................................................................................................49 4.6.1 FLASH Clock Divider Register (FCDIV) ......................................................................49 4.6.2 FLASH Options Register (FOPT and NVOPT) .............................................................51 4.6.3 FLASH Configuration Register (FCNFG) .....................................................................51 4.6.4 FLASH Protection Register (FPROT and NVPROT) ....................................................52 4.6.5 FLASH Status Register (FSTAT) ...................................................................................54 4.6.6 FLASH Command Register (FCMD) ............................................................................55 Chapter 5 Resets, Interrupts, and System Configuration 5.1 5.2 5.3 5.4 5.5 Introduction .....................................................................................................................................57 Features ...........................................................................................................................................57 MCU Reset ......................................................................................................................................57 Computer Operating Properly (COP) Watchdog .............................................................................58 Interrupts .........................................................................................................................................58 5.5.1 Interrupt Stack Frame .....................................................................................................59 5.5.2 External Interrupt Request (IRQ) Pin .............................................................................60 5.5.2.1 Pin Configuration Options ..............................................................................60 5.5.2.2 Edge and Level Sensitivity ..............................................................................61 5.5.3 Interrupt Vectors, Sources, and Local Masks .................................................................61 Low-Voltage Detect (LVD) System ................................................................................................62 5.6.1 Power-On Reset Operation .............................................................................................63 5.6.2 LVD Reset Operation .....................................................................................................63 5.6.3 LVD Interrupt and Safe State Operation ........................................................................63 5.6.4 Low-Voltage Warning (LVW) ........................................................................................63 Real-Time Interrupt (RTI) ...............................................................................................................64 5.6 5.7 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 8 Freescale Semiconductor Section Number 5.8 Title Page Reset, Interrupt, and System Control Registers and Control Bits ...................................................64 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) .........................................64 5.8.2 System Reset Status Register (SRS) ...............................................................................65 5.8.3 System Background Debug Force Reset Register (SBDFR) ..........................................67 5.8.4 System Options Register (SOPT) ...................................................................................68 5.8.5 System Device Identification Register (SDIDH, SDIDL) ..............................................69 5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) .............................70 5.8.7 System Power Management Status and Control 1 Register (SPMSC1) .........................71 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) .........................72 Chapter 6 Parallel Input/Output 6.1 6.2 6.3 Introduction .....................................................................................................................................73 Features ...........................................................................................................................................73 Pin Descriptions ..............................................................................................................................74 6.3.1 Port A ..............................................................................................................................74 6.3.2 Port B ..............................................................................................................................74 6.3.3 Port C ..............................................................................................................................75 6.3.4 Port D ..............................................................................................................................75 6.3.5 Port E ..............................................................................................................................76 Parallel I/O Controls ........................................................................................................................76 6.4.1 Data Direction Control ...................................................................................................76 6.4.2 Internal Pullup Control ...................................................................................................77 Stop Modes ......................................................................................................................................77 Parallel I/O Registers and Control Bits ...........................................................................................77 6.6.1 Port A Registers (PTAD, PTAPE, and PTADD) ............................................................78 6.6.2 Port B Registers (PTBD, PTBPE, and PTBDD) ............................................................79 6.6.3 Port C Registers (PTCD, PTCPE, and PTCDD) ............................................................81 6.6.4 Port D Registers (PTDD, PTDPE, and PTDDD) ...........................................................82 6.6.5 Port E Registers (PTED, PTEPE, and PTEDD) .............................................................84 6.4 6.5 6.6 Chapter 7 Central Processor Unit (S08CPUV2) 7.1 7.2 Introduction .....................................................................................................................................87 7.1.1 Features ...........................................................................................................................87 Programmer’s Model and CPU Registers .......................................................................................88 7.2.1 Accumulator (A) .............................................................................................................88 7.2.2 Index Register (H:X) ......................................................................................................88 7.2.3 Stack Pointer (SP) ...........................................................................................................89 7.2.4 Program Counter (PC) ....................................................................................................89 7.2.5 Condition Code Register (CCR) .....................................................................................89 Addressing Modes ...........................................................................................................................90 7.3.1 Inherent Addressing Mode (INH) ..................................................................................91 7.3.2 Relative Addressing Mode (REL) ..................................................................................91 7.3.3 Immediate Addressing Mode (IMM) .............................................................................91 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 9 7.3 Section Number 7.3.4 7.3.5 7.3.6 Title Page 7.4 7.5 Direct Addressing Mode (DIR) ......................................................................................91 Extended Addressing Mode (EXT) ................................................................................91 Indexed Addressing Mode ..............................................................................................91 7.3.6.1 Indexed, No Offset (IX) ..................................................................................92 7.3.6.2 Indexed, No Offset with Post Increment (IX+) ...............................................92 7.3.6.3 Indexed, 8-Bit Offset (IX1) .............................................................................92 7.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .........................................92 7.3.6.5 Indexed, 16-Bit Offset (IX2) ...........................................................................92 7.3.6.6 SP-Relative, 8-Bit Offset (SP1) ......................................................................92 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) ....................................................................92 Special Operations ...........................................................................................................................92 7.4.1 Reset Sequence ...............................................................................................................93 7.4.2 Interrupt Sequence ..........................................................................................................93 7.4.3 Wait Mode Operation .....................................................................................................94 7.4.4 Stop Mode Operation .....................................................................................................94 7.4.5 BGND Instruction ..........................................................................................................94 HCS08 Instruction Set Summary ....................................................................................................95 Chapter 8 Carrier Modulator Timer (S08CMTV1) 8.1 8.2 8.3 8.4 8.5 Introduction ...................................................................................................................................107 Features .........................................................................................................................................108 CMT Block Diagram .....................................................................................................................108 Pin Description ..............................................................................................................................108 Functional Description ..................................................................................................................109 8.5.1 Carrier Generator ..........................................................................................................110 8.5.2 Modulator .....................................................................................................................112 8.5.2.1 Time Mode ....................................................................................................113 8.5.2.2 Baseband Mode .............................................................................................114 8.5.2.3 FSK Mode .....................................................................................................114 8.5.3 Extended Space Operation ...........................................................................................115 8.5.3.1 EXSPC Operation in Time Mode .................................................................115 8.5.3.2 EXSPC Operation in FSK Mode ..................................................................116 8.5.4 Transmitter ....................................................................................................................116 8.5.5 CMT Interrupts .............................................................................................................117 8.5.6 Wait Mode Operation ...................................................................................................117 8.5.7 Stop Mode Operation ...................................................................................................117 8.5.8 Background Mode Operation .......................................................................................118 CMT Registers and Control Bits ...................................................................................................118 8.6.1 Carrier Generator Data Registers (CMTCGH1, CMTCGL1, CMTCGH2, and CMTCGL2) ..............................................................................................................118 8.6.2 CMT Output Control Register (CMTOC) ....................................................................120 8.6.3 CMT Modulator Status and Control Register (CMTMSC) ..........................................121 8.6.4 CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3, and CMTCMD4) .............................................................................................................122 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 10 Freescale Semiconductor 8.6 Section Number Title Chapter 9 Keyboard Interrupt (S08KBIV1) Page 9.1 9.2 9.3 9.4 Introduction ...................................................................................................................................123 KBI Block Diagram ......................................................................................................................125 Keyboard Interrupt (KBI) Module ................................................................................................125 9.3.1 Pin Enables ...................................................................................................................125 9.3.2 Edge and Level Sensitivity ...........................................................................................125 9.3.3 KBI Interrupt Controls .................................................................................................126 KBI Registers and Control Bits .....................................................................................................126 9.4.1 KBI x Status and Control Register (KBIxSC) ..............................................................127 9.4.2 KBI x Pin Enable Register (KBIxPE) ..........................................................................128 Chapter 10 Timer/PWM Module (S08TPMV1) 10.1 10.2 10.3 10.4 Introduction ...................................................................................................................................129 Features .........................................................................................................................................129 TPM Block Diagram .....................................................................................................................131 Pin Descriptions ............................................................................................................................132 10.4.1 External TPM Clock Sources .......................................................................................132 10.4.2 TPM1CHn — TPM1 Channel n I/O Pins .....................................................................132 10.5 Functional Description ..................................................................................................................132 10.5.1 Counter .........................................................................................................................133 10.5.2 Channel Mode Selection ...............................................................................................134 10.5.2.1 Input Capture Mode ......................................................................................134 10.5.2.2 Output Compare Mode .................................................................................134 10.5.2.3 Edge-Aligned PWM Mode ...........................................................................134 10.5.3 Center-Aligned PWM Mode ........................................................................................135 10.6 TPM Interrupts ..............................................................................................................................137 10.6.1 Clearing Timer Interrupt Flags .....................................................................................137 10.6.2 Timer Overflow Interrupt Description ..........................................................................137 10.6.3 Channel Event Interrupt Description ............................................................................137 10.6.4 PWM End-of-Duty-Cycle Events .................................................................................138 10.7 TPM Registers and Control Bits ...................................................................................................138 10.7.1 Timer Status and Control Register (TPM1SC) .............................................................139 10.7.2 Timer Counter Registers (TPM1CNTH:TPM1CNTL) ................................................140 10.7.3 Timer Counter Modulo Registers (TPM1MODH:TPM1MODL) ................................141 10.7.4 Timer Channel n Status and Control Register (TPM1CnSC) .......................................142 10.7.5 Timer Channel Value Registers (TPM1CnVH:TPM1CnVL) .......................................143 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 11 Section Number Title Page Chapter 11 Serial Communications Interface (S08SCIV1) 11.1 Introduction ...................................................................................................................................145 Chapter 12 Serial Communications Interface (S08SCIV1) 12.1 Introduction ...................................................................................................................................147 12.1.1 Features .........................................................................................................................147 12.1.2 Modes of Operation ......................................................................................................147 12.1.3 Block Diagram ..............................................................................................................148 12.2 Register Definition ........................................................................................................................150 12.2.1 SCI Baud Rate Registers (SCI1BDH, SCI1BHL) ........................................................150 12.2.2 SCI Control Register 1 (SCI1C1) .................................................................................151 12.2.3 SCI Control Register 2 (SCI1C2) .................................................................................152 12.2.4 SCI Status Register 1 (SCI1S1) ....................................................................................153 12.2.5 SCI Status Register 2 (SCI1S2) ....................................................................................155 12.2.6 SCI Control Register 3 (SCI1C3) .................................................................................155 12.2.7 SCI Data Register (SCI1D) ..........................................................................................156 12.3 Functional Description ..................................................................................................................157 12.3.1 Baud Rate Generation ...................................................................................................157 12.3.2 Transmitter Functional Description ..............................................................................157 12.3.2.1 Send Break and Queued Idle .........................................................................158 12.3.3 Receiver Functional Description ..................................................................................158 12.3.3.1 Data Sampling Technique .............................................................................159 12.3.3.2 Receiver Wakeup Operation .........................................................................159 12.3.4 Interrupts and Status Flags ...........................................................................................160 12.3.5 Additional SCI Functions .............................................................................................161 12.3.5.1 8- and 9-Bit Data Modes ...............................................................................161 12.3.5.2 Stop Mode Operation ....................................................................................161 12.3.5.3 Loop Mode ....................................................................................................161 12.3.5.4 Single-Wire Operation ..................................................................................162 Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Features .........................................................................................................................................164 13.2 Block Diagrams .............................................................................................................................164 13.2.1 SPI System Block Diagram ..........................................................................................164 13.2.2 SPI Module Block Diagram .........................................................................................165 13.2.3 SPI Baud Rate Generation ............................................................................................167 13.3 Functional Description ..................................................................................................................167 13.3.1 SPI Clock Formats ........................................................................................................168 13.3.2 SPI Pin Controls ...........................................................................................................170 13.3.2.1 SPSCK1 — SPI Serial Clock ........................................................................170 13.3.2.2 MOSI1 — Master Data Out, Slave Data In ..................................................170 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 12 Freescale Semiconductor Section Number Title Page 13.3.2.3 MISO1 — Master Data In, Slave Data Out ..................................................170 13.3.2.4 SS1 — Slave Select .......................................................................................170 13.3.3 SPI Interrupts ................................................................................................................171 13.3.4 Mode Fault Detection ...................................................................................................171 13.4 SPI Registers and Control Bits ......................................................................................................171 13.4.1 SPI Control Register 1 (SPI1C1) ..................................................................................172 13.4.2 SPI Control Register 2 (SPI1C2) ..................................................................................173 13.4.3 SPI Baud Rate Register (SPI1BR) ...............................................................................174 13.4.4 SPI Status Register (SPI1S) ..........................................................................................176 13.4.5 SPI Data Register (SPI1D) ...........................................................................................177 Chapter 14 Analog Comparator (S08ACMPV1) 14.1 14.2 14.3 14.4 Features .........................................................................................................................................180 Block Diagram ..............................................................................................................................180 Pin Description ..............................................................................................................................180 Functional Description ..................................................................................................................181 14.4.1 Interrupts .......................................................................................................................181 14.4.2 Wait Mode Operation ...................................................................................................181 14.4.3 Stop Mode Operation ...................................................................................................181 14.4.4 Background Mode Operation .......................................................................................181 14.5 ACMP Status and Control Register (ACMP1SC) .........................................................................182 Chapter 15 Development Support 15.1 Introduction ...................................................................................................................................183 15.1.1 Features .........................................................................................................................183 15.2 Background Debug Controller (BDC) ..........................................................................................184 15.2.1 BKGD Pin Description .................................................................................................184 15.2.2 Communication Details ................................................................................................185 15.2.3 BDC Commands ...........................................................................................................189 15.2.4 BDC Hardware Breakpoint ..........................................................................................191 15.3 On-Chip Debug System (DBG) ....................................................................................................192 15.3.1 Comparators A and B ...................................................................................................192 15.3.2 Bus Capture Information and FIFO Operation .............................................................192 15.3.3 Change-of-Flow Information ........................................................................................193 15.3.4 Tag vs. Force Breakpoints and Triggers .......................................................................193 15.3.5 Trigger Modes ..............................................................................................................194 15.3.6 Hardware Breakpoints ..................................................................................................196 15.4 Register Definition ........................................................................................................................196 15.4.1 BDC Registers and Control Bits ...................................................................................196 15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................197 15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................198 15.4.2 System Background Debug Force Reset Register (SBDFR) ........................................198 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 13 Section Number 15.4.3 Title Page DBG Registers and Control Bits ..................................................................................199 15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................199 15.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................199 15.4.3.3 Debug Comparator B High Register (DBGCBH) .........................................199 15.4.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................199 15.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................200 15.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................200 15.4.3.7 Debug Control Register (DBGC) ..................................................................201 15.4.3.8 Debug Trigger Register (DBGT) ..................................................................202 15.4.3.9 Debug Status Register (DBGS) .....................................................................203 Appendix A Electrical Characteristics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 Introduction ...................................................................................................................................205 Absolute Maximum Ratings ..........................................................................................................205 Thermal Characteristics .................................................................................................................206 Electrostatic Discharge (ESD) Protection Characteristics ............................................................207 DC Characteristics .........................................................................................................................207 Supply Current Characteristics ......................................................................................................211 Analog Comparator (ACMP) Electricals ......................................................................................211 Oscillator Characteristics ..............................................................................................................212 AC Characteristics .........................................................................................................................212 A.9.1 Control Timing ...............................................................................................................212 A.9.2 Timer/PWM (TPM) Module Timing .............................................................................213 A.9.3 SPI Timing ......................................................................................................................214 A.10 FLASH Specifications ...................................................................................................................218 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................219 B.2 Mechanical Drawings ....................................................................................................................220 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 14 Freescale Semiconductor Chapter 1 Introduction 1.1 Overview The MC9S08RC/RD/RE/RG are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in this family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 Features Features of the MC9S08RC/RD/RE/RG Family of devices are listed here. Please see Table 1-1 for the features that are available on the different family members. HCS08 CPU (Central Processor Unit) • • • • Object code fully upward-compatible with M68HC05 and M68HC08 Families HC08 instruction set with added BGND instruction Support for up to 32 interrupt/reset sources Power-saving modes: wait plus three stops On-Chip Memory • On-chip in-circuit programmable FLASH memory with block protection and security option • On-chip random-access memory (RAM) • Low power oscillator capable of operating from crystal or resonator from 1 to 16 MHz • 8 MHz internal bus frequency • On-chip analog comparator with internal reference (ACMP1) • Full rail-to-rail supply operation • Option to compare to a fixed internal bandgap reference voltage • • • • • • • • • • • Full-duplex, standard non-return-to-zero (NRZ) format Double-buffered transmitter and receiver with separate enables Programmable 8-bit or 9-bit character length Programmable baud rates (13-bit modulo divider) Master or slave mode operation Full-duplex or single-wire bidirectional option Programmable transmit bit rate Double-buffered transmit and receive Serial clock phase and polarity options Slave select output Selectable MSB-first or LSB-first shifting Oscillator (OSC) Analog Comparator (ACMP1) Serial Communications Interface Module (SCI1) Serial Peripheral Interface Module (SPI1) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 15 Introduction Timer/Pulse-Width Modulator (TPM1) • 2-channel, 16-bit timer/pulse-width modulator (TPM1) module that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM • Selectable input capture, output compare, and edge-aligned or center-aligned PWM capability on each channel • Providing 12 keyboard interrupts • Eight with falling-edge/low-level plus four with selectable polarity • KBI1 inputs can be configured for edge-only sensitivity or edge-and-level sensitivity • Dedicated infrared output (IRO) pin • Drives IRO pin for remote control communications • Can be disconnected from IRO pin and used as output compare timer • IRO output pin has high-current sink capability • Background debugging system (see also the Development Support chapter) • Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) • Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints. • Eight high-current pins (limited by maximum package dissipation) • Software selectable pullups on ports when used as input. Selection is on an individual port bit basis. During output mode, pullups are disengaged. • 39 general-purpose input/output (I/O) pins, depending on package selection • • • • • • • • • 28-pin plastic dual in-line package (PDIP) 28-pin small outline integrated circuit (SOIC) 32-pin low-profile quad flat package (LQFP) 44-pin low-profile quad flat package (LQFP) 48-pin quad flat package (QFN) Optional computer operating properly (COP) reset Low-voltage detection with reset or interrupt Illegal opcode detection with reset Illegal address detection with reset (some devices don’t have illegal addresses) Keyboard Interrupt Ports (KBI1, KBI2) Carrier Modulator Timer (CMT) Development Support Port Pins Package Options System Protection 1.2.1 Devices in the MC9S08RD/RE/RG Series Table 1-1 lists the devices available in the MC9S08RD/RE/RG series and summarizes the differences in functions and configuration among them. Table 1-1. Devices in the MC9S08RD/RE/RG Series Device 9S08RG32/60 9S08RE8/16/32/60 9S08RD8/16/32/60 FLASH 32K/60K 8/16K/32K/60K 8/16K/32K/60K RAM 2K/2K 1K/1K/2K/2K 1K/1K/2K/2K ACMP(1) Yes Yes No SCI Yes Yes Yes SPI Yes No No 1. Available only in 32-, 44-, and 48-pin LQFP packages. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 16 Freescale Semiconductor Introduction 1.3 MCU Block Diagram HCS08 CORE INTERNAL BUS PORT A 7 PTA7/KBI1P7– PTA1/KBI1P1 PTA0/KBI1P0 This block diagram shows the structure of the MC9S08RC/RD/RE/RG MCUs BDC CPU DEBUG MODULE (DBG) NOTES1, 2, 6 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PORT B 4-BIT KEYBOARD INTERRUPT MODULE (KBI2) PTB7/TPM1CH1 PTE6 PTB5 PTB4 PTB3 PTB2 PTB1/RxD1 PTB0/TxD1 NOTES 1, 5 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) USER FLASH (RC/RD/RE/RG60 = 63,364 BYTES) (RC/RD/RE/RG32 = 32,768 BYTES) (RC/RD/RE16 = 16,384 BYTES) (RC/RD/RE8 = 8192 BYTES) PORT C ANALOG COMPARATOR MODULE (ACMP1) PTC7/SS1 PTC6/SPSCK1 PTC5/MISO1 PTC4/MOSI1 PTC3/KBI2P3 PTC2/KBI2P2 PTC1/KBI2P1 PTC0/KBI2P0 PTD6/TPM1CH0 PTD5/ACMP1+ PTD4/ACMP1– PTD3 PTD2/IRQ PTD1/RESET PTD0/BKGD/MS NOTE 1 PORT D USER RAM (RC/RD/RE/RG32/60 = 2048 BYTES) (RC/RD/RE8/16 = 1024 BYTES) 2-CHANNEL TIMER/PWM MODULE (TPM1) NOTES 1, 3, 4 EXTAL XTAL LOW-POWER OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE (SPI1) PORT E 8 PTE7– PTE0 NOTE 1 VDD VSS VOLTAGE REGULATOR CARRIER MODULATOR TIMER MODULE (CMT) IRO NOTE 5 NOTES: 1. Port pins are software configurable with pullup device if input port 2. PTA0 does not have a clamp diode to VDD. PTA0 should not be driven above VDD. Also, PTA0 does not pullup to VDD when internal pullup is enabled. 3. IRQ pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1) 4. The RESET pin contains integrated pullup device enabled if reset enabled (RSTPE = 1) 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Figure 1-1. MC9S08RC/RD/RE/RG Block Diagram Table 1-2 lists the functional versions of the on-chip modules. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 17 Introduction Table 1-2. Block Versions Module Analog Comparator (ACMP) Carrier Modulator Transmitter (CMT) Keyboard Interrupt (KBI) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Timer Pulse-Width Modulator (TPM) Central Processing Unit (CPU) Debug Module (DBG) FLASH System Control Version 1 1 1 1 3 1 2 1 1 2 1.4 System Clock Distribution RTI OSC RTICLKS SYSTEM CONTROL LOGIC TPM CMT SCI SPI RTI OSCOUT* OSC ÷2 BUSCLK CPU BDC ACMP RAM FLASH FLASH has frequency requirements for program and erase operation. See Appendix A. * OSCOUT is the alternate BDC clock source for the MC9S08RC/RD/RE/RG. Figure 1-2. System Clock Distribution Diagram Table 1-2 shows a simplified clock connection diagram for the MCU. The CPU operates at the input frequency of the oscillator. The bus clock frequency is half of the oscillator frequency and is used by all of the internal circuits with the exception of the CPU and RTI. The RTI can use either the oscillator input or the internal RTI oscillator as its clock source. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 18 Freescale Semiconductor Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment 44 PTA7/KBI1P7 PTA6/KBI1P6 PTA5/KBI1P5 PTA4/KBI1P4 PTA3/KBI1P3 34 PTA1/KBI1P1 33 PTA0/KBI1P0 32 31 30 29 28 27 26 25 24 13 14 15 16 17 18 19 20 21 23 PTC6/SPSCK1 22 PTD6/TPM1CH0 PTD5/ACMP1+ PTD4/ACMP1– EXTAL XTAL PTD3 PTD2/IRQ PTD1/RESET PTD0/BKGD/MS PTC7/SS1 PTA2/KBI1P2 PTC5/MISO1 35 PTE7 PTE6 43 42 41 40 39 38 PTE5 37 PTE3 PTE4 PTB0/TxD1 1 PTB1/RxD1 PTB2 PTB3 PTB4 VDD VSS IRO PTB5 PTB6 PTB7/TPM1CH1 11 PTC0/KBI2P0 12 2 3 4 5 6 7 8 9 10 PTC2/KBI2P2 PTC1/KBI2P1 PTC3/KBI2P3 Figure 2-1. MC9S08RC/RD/RE/RG in 44-Pin LQFP Package MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 19 PTC4/MOSI1 PTE0 PTE1 PTE2 36 Pins and Connections 32 PTA7/KBI1P7 PTA6/KBI1P6 PTA5/KBI1P5 PTA4/KBI1P4 PTA3/KBI1P3 PTA2/KBI1P2 PTA1/KBI1P1 26 31 30 29 28 27 PTB0/TxD1 PTB1/RxD1 PTB2 VDD VSS IRO PTB6 PTB7/TPM1CH1 1 2 3 4 5 6 7 25 PTA0/KBI1P0 24 23 22 21 20 19 18 PTD6/TPM1CH0 PTD5/ACMP1+ PTD4/ACMP1– EXTAL XTAL PTD2/IRQ PTD1/RESET PTD0/BKGD/MS 10 11 12 13 14 PTC6/SPSCK1 PTC4/MISO1 PTC0/KBI2P0 PTC1/KBI2P1 PTC2/KBI2P2 PTC3/KBI2P3 PTC5/MISO1 15 9 Figure 2-2. MC9S08RC/RD/RE/RG in 32-Pin LQFP Package PTC7/SS1 PTA4/KBI1P4 PTA3/KBI1P3 PTA2/KBI1P2 PTA1/KBI1P1 PTA0/KBI1P0 PTD6/TPM1CH0 EXTAL XTAL PTD1/RESET PTD0/BKGD/MS PTC7/SS1 PTC6/SPSCK1 PTC5/MISO1 PTC4/MOSI1 PTA5/KBI1P5 PTA6/KBI1P6 PTA7/KBI1P7 PTB0/TxD1 PTB1/RxD1 PTB2 VDD VSS IRO PTB7/TPM1CH1 PTC0/KBI2P0 PTC1/KBI2P1 PTC2/KBI2P2 PTC3/KBI2P3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Figure 2-3. MC9S08RC/RD/RE/RG in 28-Pin SOIC Package and 28-Pin PDIP Package MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 20 Freescale Semiconductor 16 8 17 Pins and Connections 47 PTA7/KBI1P7 46 PTA6/KBI1P6 45 PTA5/KBI1P5 44 PTA4/KBI1P4 39 PTA3/KBI1P3 38 PTA2/KBI1P2 37 PTA1/KBI1P1 36 NC 35 PTA0/KBI1P0 34 PTD6/TPM1CH0 33 PTD5/ACMP1+ 32 PTD4/ACMP1– 31 EXTAL 30 XTAL 29 PTD3 28 PTD2/IRQ 27 PTD1/RESET 26 PTD0/BKGD/MS 25 PTC7/SS1 PTC0/KBI2P0 13 PTC1/KBI2P1 14 PTC2/KBI2P2 15 PTC3/KBI2P3 16 PTE0 17 PTE1 18 PTE2 19 PTE3 20 PTC4/MOSI1 21 PTC5/MISO1 22 PTC6/SPSCK1 23 NC 24 43 PTE7 42 PTE6 41 PTE5 PTB0/TxD1 1 PTB1/RxD1 2 PTB2 3 PTB3 4 PTB4 5 VDD 6 VSS 7 IRQ 8 PTB5 9 PTB6 10 PTB7/TPM1CH1 11 NC 12 Figure 2-4. MC9S08RC/RD/RE/RG in 48-Pin QFN Package 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08RC/RD/RE/RG application systems. A more detailed discussion of system connections follows. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 21 40 PTE4 48 NC Pins and Connections MC9S08RC/RD/RE/RG SYSTEM POWER + 3V VDD VDD CBLK + 10 µF CBY 0.1 µF VSS RF XTAL C2 X1 C1 EXTAL BACKGROUND HEADER PORT A PTA0/KBI1P0 PTA1/KBI1P1 PTA2/KBI1P2 PTA3/KBI1P3 PTA4/KBI1P4 PTA5/KBI1P5 PTA6/KBI1P6 PTA7/KBI1P7 PTB0/TxD1 PTB1/RxD1 PTB2 PORT B PTB3 PTB4 PTB5 PTB6 VDD 1 BKGD/MS NOTE 1 PTB7/TPM1CH1 PTC0/KBI2P0 PTC1/KBI2P1 PTC2/KBI2P2 RESET NOTE 2 PORT C PTC3/KBI2P3 PTC4/MOSI1 PTC5/MISO1 PTC6/SPSCK1 PTC7/SS1 PTD0/BKGD/MS PTD1/RESET PTD2/IRQ PORT D PTD3 PTD4/ACMP1– PTD5/ACMP1+ PTD6/TPM1CH0 I/O AND PERIPHERAL INTERFACE TO APPLICATION SYSTEM OPTIONAL MANUAL RESET IRO PTE0 PTE1 PTE2 PORT E PTE3 PTE4 PTE5 PTE6 PTE7 NOTES: 1. BKGD/MS is the same pin as PTD0. 2. RESET is the same pin as PTD1. Figure 2-5. Basic System Connections MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 22 Freescale Semiconductor Pins and Connections 2.3.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-µF ceramic bypass capacitor located as near to the MCU power pins as practical to suppress high-frequency noise. 2.3.2 Oscillator The oscillator in the MC9S08RC/RD/RE/RG is a traditional Pierce oscillator that can accommodate a crystal or ceramic resonator in the range of 1 MHz to 16 MHz. Refer to Figure 2-5 for the following discussion. RF should be a low-inductance resistor such as a carbon composition resistor. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its value is not generally critical. Typical systems use 1 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance that is the series combination of C1 and C2, which are usually the same size. As a first-order approximation, use 5 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.3.3 PTD1/RESET The external pin reset function is shared with an output-only port function on the PTD1/RESET pin. The reset function is enabled when RSTPE in SOPT is set. RSTPE is set following any reset of the MCU and must be cleared in order to use this pin as an output-only port. Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for about 34 cycles of fSelf_reset, released, and sampled again about 38 cycles of fSelf_reset later. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry expects the reset pin sample to return a logic 1. If the pin is still low at this sample point, the reset is assumed to be from an external source. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS). Never connect any significant capacitance to the reset pin because that would interfere with the circuit and sequence that detects the source of reset. If an external capacitance prevents the reset pin from rising to a valid logic 1 before the reset sample point, all resets will appear to be external resets. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 23 Pins and Connections 2.3.4 Background/Mode Select (PTD0/BKGD/MS) The background/mode select function is shared with an output-only port function on the PTD0/BKDG/MS pin. While in reset, the pin functions as a mode select pin. Immediately after reset rises, the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, this pin has an internal pullup device enabled. To use as an output-only port, BKGDPE in SOPT must be cleared. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset, which forces the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.3.5 IRO Pin Description The IRO pin is the output of the CMT. See the Carrier Modulator Timer (CMT) Module Chapter for a detailed description of this pin function. 2.3.6 General-Purpose I/O and Peripheral Ports The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. (Not all pins are available in all packages. See Table 2-2.) Immediately after reset, all 37 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. For information about controlling these pins as general-purpose I/O pins, see the Chapter 6, “Parallel Input/Output." For information about how and when on-chip peripheral systems use these pins, refer to the appropriate chapter from Table 2-1. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 24 Freescale Semiconductor Pins and Connections Table 2-1. Pin Sharing References Port Pins PTA7–PTA0 PTB7 PTB6–PTB2 PTB1 PTB0 PTC7 PTC6 PTC5 PTC4 PTC3–PTC0 PTD6 PTD5 PTD4 PTD2 PTD1 PTD0 PTE7–PTE0 Alternate Function KBI1P7–KBI1P0 TPM1CH1 — RxD1 TxD1 SS1 SPSCK1 MISO1 MOSI1 KBI2P3–KBI2P0 TPM1CH0 ACMP1+ ACMP1– IRQ RESET BKGD/MS — Chapter 6, “Parallel Input/Output” Reference(1) Chapter 9, “Keyboard Interrupt (S08KBIV1)” Chapter 10, “Timer/PWM Module (S08TPMV1)” Chapter 6, “Parallel Input/Output” Chapter 11, “Serial Communications Interface (S08SCIV1)” Chapter 13, “Serial Peripheral Interface (S08SPIV3)” Chapter 9, “Keyboard Interrupt (S08KBIV1)” Chapter 10, “Timer/PWM Module (S08TPMV1)” Chapter 14, “Analog Comparator (S08ACMPV1)” Chapter 5, “Resets, Interrupts, and System Configuration” 1. See this chapter for information about modules that share these pins. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. See the Chapter 6, “Parallel Input/Output,” for more details. Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4 pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. Similarly, when PTD2 is configured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. 2.3.7 Signal Properties Summary Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the common pin interfaces are hardwired to internal circuits. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 25 Pins and Connections Table 2-2. Signal Properties Pin Name VDD VSS XTAL EXTAL IRO PTA0/KBI1P0 PTA1/KBI1P1 PTA2/KBI1P2 PTA3/KBI1P3 PTA4/KBI1P4 PTA5/KBI1P5 PTA6/KBI1P6 PTA7/KBI1P7 PTB0/TxD1 PTB1/RxD1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7/TPM1CH1 PTC0/KBI2P0 PTC1/KBI2P1 PTC2/KBI2P2 PTC3/KBI2P3 PTC4/MOSI1 PTC5/MISO1 PTC6/SPSCK1 PTC7/SS1 PTD0/BKGD/MS PTD1/RESET O I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Dir(1) High Current Pin — — — — Y N N N N N N N N Y Y Y Y Y Y Y Y N N N N N N N N N N Pullup(2) — — — — — SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC(4) SWC(3) Output-only when configured as PTD0 pin. Pullup enabled. Output-only when configured as PTD1 pin. Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 32-, 44-, and 48-pin packagess Crystal oscillator output Crystal oscillator input Infrared output PTA0 does not have a clamp diode to VDD. PTA0 should not be driven above VDD. Comments(3) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 26 Freescale Semiconductor Pins and Connections Table 2-2. Signal Properties (continued) Pin Name PTD2/IRQ PTD3 PTD4/ACMP1– PTD5/ACMP1+ PTD6/TPM1CH0 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 PTE6 PTE7 Dir(1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O High Current Pin N N N N N N N N N N N N N Pullup(2) SWC(5) SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC SWC Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Available only in 44- and 48-pin packages Comments(3) Available only in 32-, 44-, and 48-pin packagess Available only in 44- and 48-pin packages Available only in 32-, 44-, and 48-pin packagess Available only in 32-, 44-, and 48-pin packagess 1. Unless otherwise indicated, all digital inputs have input hysteresis. 2. SWC is software-controlled pullup resistor, the register is associated with the respective port. 3. Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user’s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float. 4. When these pins are configured as RESET or BKGD/MS pullup device is enabled. 5. When configured for the IRQ function, this pin will have a pullup device enabled when the IRQ is set for falling edge detection and a pulldown device enabled when the IRQ is set for rising edge detection. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 27 Pins and Connections MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 28 Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08RC/RD/RE/RG are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • Features Active background mode for code development Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained Stop modes: — System clocks stopped; voltage regulator in standby — Stop1 — Full power down of internal circuits for maximum power savings — Stop2 — Partial power down of internal circuits, RAM remains operational — Stop3 — All internal circuits powered for fast recovery • 3.3 Run Mode This is the normal operating mode for the MC9S08RC/RD/RE/RG. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at $FFFE:$FFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 29 Modes of Operation After active background mode is entered, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode, include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08RC/RD/RE/RG is shipped from the Freescale Semiconductor factory, the FLASH program memory is usually erased so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter. 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 30 Freescale Semiconductor Modes of Operation 3.6 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1. Stop Mode Behavior Mode Stop1 Stop2 Stop3 PDC 1 1 0 PPDC 0 1 Don’t care CPU, Digital Peripherals, FLASH Off Off Standby RAM Off Standby Standby OSC Off Off Off ACMP Standby Standby Standby Regulator Standby Standby Standby I/O Pins Reset States held States held RTI Off Optionally on Optionally on 3.6.1 Stop1 Mode Stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the MCU to be powered down. To enter stop1, the user must execute a STOP instruction with the PDC bit in SPMSC2 set and the PPDC bit clear. Stop1 can be entered only if the LVD reset is disabled (LVDRE = 0). When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned off. The voltage regulator is in a low-power standby state, as are the OSC and ACMP. Exit from stop1 is done by asserting any of the wakeup pins on the MCU: RESET, IRQ, or KBI1, which have been enabled. IRQ and KBI pins are always active-low when used as wakeup pins in stop1 regardless of how they were configured before entering stop1. Upon wakeup from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will take the reset vector. 3.6.2 Stop2 Mode Stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. To select entry into stop2 upon execution of a STOP instruction, the user must execute a STOP instruction with the PPDC and PDC bits in SPMSC2 set. Stop2 can be entered only if LVDRE = 0. Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers that they want to restore after exit of stop2, to locations in RAM. Upon exit from stop2, these values can be restored by user software. When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ACMP. Upon entry MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 31 Modes of Operation into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a 1 is written to PPDACK in SPMSC2. Exit from stop2 is done by asserting any of the wakeup pins: RESET, IRQ, or KBI1 that have been enabled, or through the real-time interrupt. IRQ and KBI1 pins are always active-low when used as wakeup pins in stop2 regardless of how they were configured before entering stop2. (KBI2 will not wake the MCU from stop2.) Upon wakeup from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written to PPDACK in SPMSC2. For pins that were configured as general-purpose I/O, the user must copy the contents of the I/O port registers, which have been saved in RAM, back to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will be in their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 Stop3 Mode Upon entering stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The OSC is turned off, the ACMP is disabled, and the voltage regulator is put in standby. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exit from stop3 is done by asserting RESET, any asynchronous interrupt pin that has been enabled, or through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI1 and KBI2 pins. If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector. A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 32 Freescale Semiconductor Modes of Operation 3.6.4 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Development Support chapter of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. The MCU cannot enter either stop1 mode or stop2 mode if ENBDM is set. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After active background mode is entered, all background commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the active background mode is enabled. Table 3-2. BDM Enabled Stop Mode Behavior Mode Stop3 PDC Don’t care PPDC Don’t care CPU, Digital Peripherals, FLASH Standby RAM Standby OSC On ACMP Standby Regulator On I/O Pins States held RTI Optionally on 3.6.5 LVD Reset Enabled The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD reset is enabled in stop by setting the LVDRE bit in SPMSC1 when the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user attempts to enter either stop1 or stop2 with the LVD reset enabled (LVDRE = 1) the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when LVD reset is enabled. Table 3-3. LVD Enabled Stop Mode Behavior Mode Stop3 PDC Don’t care PPDC Don’t care CPU, Digital Peripherals, FLASH Standby RAM Standby OSC On ACMP Standby Regulator On I/O Pins States held RTI Optionally on 3.6.6 On-Chip Peripheral Modules in Stop Mode When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to the peripheral systems are halted to reduce power consumption. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 33 Modes of Operation I/O Pins • All I/O pin states remain unchanged when the MCU enters stop3 mode. • If the MCU is configured to go into stop2 mode, all I/O pin states are latched before entering stop. Pin states remain latched until the PPDACK bit is written. • If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state upon entry into stop. Memory • All RAM and register contents are preserved while the MCU is in stop3 mode. • All registers will be reset upon wakeup from stop2, but the contents of RAM are preserved. The user may save any memory-mapped register data into RAM before entering stop2 and restore the data upon exit from stop2. • All registers will be reset upon wakeup from stop1 and the contents of RAM are not preserved. The MCU must be initialized as upon reset. The contents of the FLASH memory are non-volatile and are preserved in any of the stop modes. OSC — In any of the stop modes, the OSC stops running. TPM — When the MCU enters stop mode, the clock to the TPM module stops. The modules halt operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM module will be reset upon wakeup from stop and must be reinitialized. ACMP — When the MCU enters any stop mode, the ACMP will enter a low-power standby state. No compare operation will occur while in stop. If the MCU is configured to go into stop2 or stop1 mode, the ACMP will be reset upon wakeup from stop and must be reinitialized. KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources. During stop1 or stop2, enabled KBI1 pins function as wakeup inputs. When functioning as a wakeup, a KBI pin is always active low regardless of how it was configured before entering stop1 or stop2. SCI — When the MCU enters stop mode, the clock to the SCI module stops. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the SCI module will be reset upon wakeup from stop and must be reinitialized. SPI — When the MCU enters stop mode, the clock to the SPI module stops. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wakeup from stop and must be reinitialized. CMT — When the MCU enters stop mode, the clock to the CMT module stops. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the CMT module will be reset upon wakeup from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD reset function is enabled or BDM is enabled. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 34 Freescale Semiconductor Chapter 4 Memory 4.1 MC9S08RC/RD/RE/RG Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08RC/RD/RE/RG series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: • Direct-page registers ($0000 through $0045 for 32K and 60K parts, and $0000 through $003F for 16K and 8K parts) • High-page registers ($1800 through $182B) • Nonvolatile registers ($FFB0 through $FFBF) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 35 Memory $0000 DIRECT PAGE REGISTERS $0045 $0046 RAM 2048 BYTES $0845 $0846 FLASH 4026 BYTES $0000 $0045 $0046 $0845 $0846 UNIMPLEMENTED 5056 BYTES $17FF $1800 $182B $182C $17FF $1800 $182B $182C $0000 $003F $0040 $043F $0440 $0000 $003F $0040 $043F $0440 DIRECT PAGE REGISTERS RAM 2048 BYTES UNIMPLEMENTED 4026 BYTES DIRECT PAGE REGISTERS RAM 1024 BYTES(1) DIRECT PAGE REGISTERS RAM 1024 BYTES(1) UNIMPLEMENTED 5056 BYTES $17FF $1800 $182B $182C $17FF $1800 $182B $182C HIGH PAGE REGISTERS HIGH PAGE REGISTERS HIGH PAGE REGISTERS HIGH PAGE REGISTERS UNIMPLEMENTED 26580 BYTES UNIMPLEMENTED 42964 BYTES $8000 FLASH 59348 BYTES UNIMPLEMENTED 51156 BYTES FLASH 32768 BYTES $BFFF $C000 FLASH 16384 BYTES FLASH 8192 BYTES $FFFF MC9S08RC/RD/RE/RG60 MC9S08RC/RD/RE/RG32 MC9S08RC/RD/RE16 $FFFF MC9S08RC/RD/RE8 $DFFF $E000 $FFFF Figure 4-1. MC9S08RC/RD/RE/RG Memory Map 4.1.1 Reset and Interrupt Vector Assignments Figure 4-2 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08RC/RD/RE/RG. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to the Chapter 5, “Resets, Interrupts, and System Configuration." MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 36 Freescale Semiconductor Memory Figure 4-2. Reset and Interrupt Vectors Vector Number 16 through 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address (High/Low) $FFC0:FFC1 Vector Unused Vector Space (available for user program) Vector Name $FFDE:FFDF $FFE0:FFE1 $FFE2:FFE3 $FFE4:FFE5 $FFE6:FFE7 $FFE8:FFE9 $FFEA:FFEB $FFEC:FFED $FFEE:FFEF $FFF0:FFF1 $FFF2:FFF3 $FFF4:FFF5 $FFF6:FFF7 $FFF8:FFF9 $FFFA:FFFB $FFFC:FFFD $FFFE:FFFF SCI SPI(1) RTI KBI2 KBI1 ACMP (2) Vspi1 Vrti Vkeyboard2 Vkeyboard1 Vacmp1 Vcmt Vsci1tx Vsci1rx Vsci1err Vtpm1ovf Vtpm1ch1 Vtpm1ch0 Virq Vlvd Vswi Vreset (3) CMT Transmit(3) (3) SCI Receive SCI Error TPM Overflow TPM Channel 1 TPM Channel 0 IRQ Low Voltage Detect SWI Reset 1. The SPI module is not included on the MC9S08RC/RD/RE devices. This vector location is unused for those devices. 2. The analog comparator (ACMP) module is not included on the MC9S08RD devices. This vector location is unused for those devices. 3. The SCI module is not included on the MC9S08RC devices. This vector location is unused for those devices. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 37 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08RC/RD/RE/RG are divided into these three groups: • Direct-page registers are located within the first 256 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above $1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0–$FFBF. Nonvolatile register locations include: — Three values that are loaded into working registers at reset — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-1 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-1 can use the more efficient direct addressing mode, which requires only the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-2 and Table 4-3, the whole address in column one is shown in bold. In Table 4-1, Table 4-2, and Table 4-3, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 38 Freescale Semiconductor Memory Table 4-1. Direct-Page Register Summary Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 Register Name PTAD PTAPE Reserved PTADD PTBD PTBPE Reserved PTBDD PTCD PTCPE Reserved PTCDD PTDD PTDPE Reserved PTDDD PTED PTEPE Reserved PTEDD KBI1SC KBI1PE KBI2SC KBI2PE SCI1BDH SCI1C1 (1) Bit 7 PTAD7 PTAPE7 — PTADD7 PTBD7 PTBPE7 — PTBDD7 PTCD7 PTCPE7 — PTCDD7 0 0 — 0 PTED7 PTEPE7 — PTEDD7 KBEDG7 KBIPE7 0 0 0 SBR7 LOOPS TIE TDRE 0 R8 R7/T7 PH7 PL7 SH7 SL7 IROL EOCF MB15 MB7 SB15 SB7 6 PTAD6 PTAPE6 — PTADD6 PTBD6 PTBPE6 — PTBDD6 PTCD6 PTCPE6 — PTCDD6 PTDD6 PTDPE6 — PTDDD6 PTED6 PTEPE6 — PTEDD6 KBEDG6 KBIPE6 0 0 0 SBR6 SCISWAI TCIE TC 0 T8 R6/T6 PH6 PL6 SH6 SL6 CMTPOL MB14 MB6 SB14 SB6 5 PTAD5 PTAPE5 — PTADD5 PTBD5 PTBPE5 — PTBDD5 PTCD5 PTCPE5 — PTCDD5 PTDD5 PTDPE5 — PTDDD5 PTED5 PTEPE5 — PTEDD5 KBEDG5 KBIPE5 0 0 0 SBR5 RSRC RIE RDRF 0 TXDIR R5/T5 PH5 PL5 SH5 SL5 IROPEN MB13 MB5 SB13 SB5 4 PTAD4 PTAPE4 — PTADD4 PTBD4 PTBPE4 — PTBDD4 PTCD4 PTCPE4 — PTCDD4 PTDD4 PTDPE4 — PTDDD4 PTED4 PTEPE4 — PTEDD4 KBEDG4 KBIPE4 0 0 SBR12 SBR4 M ILIE IDLE 0 0 R4/T4 PH4 PL4 SH4 SL4 0 EXSPC MB12 MB4 SB12 SB4 3 PTAD3 PTAPE3 — PTADD3 PTBD3 PTBPE3 — PTBDD3 PTCD3 PTCPE3 — PTCDD3 PTDD3 PTDPE3 — PTDDD3 PTED3 PTEPE3 — PTEDD3 KBF KBIPE3 KBF KBIPE3 SBR11 SBR3 WAKE TE OR 0 ORIE R3/T3 PH3 PL3 SH3 SL3 0 BASE MB11 MB3 SB11 SB3 2 PTAD2 PTAPE2 — PTADD2 PTBD2 PTBPE2 — PTBDD2 PTCD2 PTCPE2 — PTCDD2 PTDD2 PTDPE2 — PTDDD2 PTED2 PTEPE2 — PTEDD2 KBACK KBIPE2 KBACK KBIPE2 SBR10 SBR2 ILT RE NF 0 NEIE R2/T2 PH2 PL2 SH2 SL2 0 FSK MB10 MB2 SB10 SB2 1 PTAD1 PTAPE1 — PTADD1 PTBD1 PTBPE1 — PTBDD1 PTCD1 PTCPE1 — PTCDD1 PTDD1 PTDPE1 — PTDDD1 PTED1 PTEPE1 — PTEDD1 KBIE KBIPE1 KBIE KBIPE1 SBR9 SBR1 PE RWU FE 0 FEIE R1/T1 PH1 PL1 SH1 SL1 0 EOCIE MB9 MB1 SB9 SB1 Bit 0 PTAD0 PTAPE0 — PTADD0 PTBD0 PTBPE0 — PTBDD0 PTCD0 PTCPE0 — PTCDD0 PTDD0 PTDPE0 — PTDDD0 PTED0 PTEPE0 — PTEDD0 KBIMOD KBIPE0 KBIMOD KBIPE0 SBR8 SBR0 PT SBK PF RAF PEIE R0/T0 PH0 PL0 SH0 SL0 0 MCGEN MB8 MB0 SB8 SB0 SCI1BDL(1) (1) SCI1C2(1) SCI1S1(1) SCI1S2(1) SCI1C3(1) SCI1D(1) CMTCGH1 CMTCGL1 CMTCGH2 CMTCGL2 CMTOC CMTMSC CMTCMD1 CMTCMD2 CMTCMD3 CMTCMD4 CMTDIV1 CMTDIV0 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 39 Memory Table 4-1. Direct-Page Register Summary (continued) Address $002A $002B $002C– $002F $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B– $003F $0040 $0041 $0042 $0043 $0044 $0045 Register Name IRQSC ACMP1SC(2) Reserved TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL TPM1C1SC TPM1C1VH TPM1C1VL Reserved SPI1C1(3) SPI1C2(3) SPI1BR (3) Bit 7 0 ACME — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — — SPIE 0 0 SPRF — Bit 7 6 0 ACBGS — — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — — SPE 0 SPPR2 0 — 6 5 IRQEDG ACF — — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — — SPTIE 0 SPPR1 SPTEF — 5 4 IRQPE ACIE — — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — — MSTR MODFEN SPPR0 MODF — 4 3 IRQF ACO — — CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — — CPOL BIDIROE 0 0 — 3 2 IRQACK — — — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — — CPHA 0 SPR2 0 — 2 1 IRQIE ACMOD1 — — PS1 9 1 9 1 0 9 1 0 9 1 — — SSOE SPISWAI SPR1 0 — 1 Bit 0 IRQMOD ACMOD0 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — LSBFE SPC0 SPR0 0 — Bit 0 SPI1S(3) Reserved SPI1D(3) 1. The SCI module is not included on the MC9S08RC devices. This is a reserved location for those devices. 2. The analog comparator (ACMP) module is not included on the MC9S08RD devices. This is a reserved location for those devices. 3. The SPI module is not included on the MC9S08RC/RD/RE devices. These are reserved locations on the 32K and 60K versions of these devices. The address range $0040–$004F are RAM locations on the 16K and 8K devices. There are no MC9S08RG8/16 devices. High-page registers, shown in Table 4-2, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at $1800. Table 4-2. High-Page Register Summary Address $1800 $1801 $1802 $1803– $1804 $1805 $1806 $1807 $1808 Register Name SRS SBDFR SOPT Reserved Reserved SDIDH SDIDL SRTISC Bit 7 POR 0 7 — — 0 REV3 ID7 RTIF 6 PIN 0 COPT — — 0 REV2 ID6 RTIACK 5 COP 0 STOPE — — 0 REV1 ID5 RTICLKS 4 ILOP 0 — — — 0 REV0 ID4 RTIE 3 ILAD 0 0 — — 0 ID11 ID3 0 (1) 2 0 0 0 — — 0 ID10 ID2 RTIS2 1 LVD 0 BKGDPE — — 0 ID9 ID1 RTIS1 Bit 0 0 BDFR RSTPE — — 0 ID8 ID0 RTIS0 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 40 Freescale Semiconductor Memory Table 4-2. High-Page Register Summary (continued) Address $1809 $180A $180B– $180F $1810 $1811 $1812 $1813 $1814 $1815 $1816 $1817 $1818 $1819– $181F $1820 $1821 $1822 $1823 $1824 $1825 $1826 $1827– $182B Register Name SPMSC1 SPMSC2 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL DBGC DBGT DBGS Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Reserved Bit 7 LVDF LVWF — — Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 DBGEN TRGSEL AF — — DIVLD KEYEN — 0 FPOPEN FCBEF FCMD7 — — 6 LVDACK LVWACK — — 14 6 14 6 14 6 ARM BEGIN BF — — PRDIV8 FNORED — 0 FPDIS FCCF FCMD6 — — 5 LVDIE 0 — — 13 5 13 5 13 5 TAG 0 ARMF — — DIV5 0 — KEYACC FPS2 FPVIOL FCMD5 — — 4 SAFE 0 — — 12 4 12 4 12 4 BRKEN 0 0 — — DIV4 0 — 0 FPS1 FACCERR FCMD4 — — 3 LVDRE PPDF — — 11 3 11 3 11 3 RWA TRG3 CNT3 — — DIV3 0 — 0 FPS0 0 FCMD3 — — 2 — PPDACK — — 10 2 10 2 10 2 RWAEN TRG2 CNT2 — — DIV2 0 — 0 0 FBLANK FCMD2 — — 1 — PDC — — 9 1 9 1 9 1 RWB TRG1 CNT1 — — DIV1 SEC01 — 0 0 0 FCMD1 — — Bit 0 — PPDC — — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 RWBEN TRG0 CNT0 — — DIV0 SEC00 — 0 0 0 FCMD0 — — 1. The ILAD bit is only present on 16K and 8K versions of the devices. Nonvolatile FLASH registers, shown in Table 4-3, are located in the FLASH memory. These registers include an 8-byte backdoor key that optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Table 4-3. Nonvolatile Register Summary Address $FFB0– $FFB7 $FFB8– $FFBC $FFBD $FFBE $FFBF Register Name NVBACKKEY Reserved NVPROT Reserved NVOPT — — FPOPEN — KEYEN — — FPDIS — FNORED — — FPS2 — 0 Bit 7 6 5 4 3 2 1 Bit 0 8-Byte Comparison Key — — FPS1 — 0 — — FPS0 — 0 — — 0 — 0 — — 0 — SEC01 — — 0 — SEC00 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor 41 Memory Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08RC/RD/RE/RG includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit-manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to $00FF. In the MC9S08RC/RD/RE/RG, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP