DOCUMENT NUMBER
9S12DJ64DGV1/D
MC9S12DJ64
Device User Guide
V01.20
Covers also
MC9S12D64, MC9S12A64, MC9S12D32,
MC9S12A32
Original Release Date: 19 Nov. 2001
Revised: 6 April 2005
Freescale Semiconductor, Inc.
Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Freescale does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was
negligent regarding the design or manufacture of the part.
1
Revision History
Version Revision Effective
Number
Date
Date
Author
Description of Changes
V01.00
16 NOV
2001
19 NOV
2001
Initial version based on MC9SDP256-2.09 Version.
V01.01
18 FEB
2002
18 FEB
2002
In table 7 I/O Characteristics" of the electrical characteristics
replaced tPULSE with tpign and tpval in lines "Port ... Interrupt Input
Pulse filtered" and "Port ... Interrupt Input Pulse passed"
respectively.
6 MAR
2002
Table "Oscillator Characteristics": removed "Oscillator start-up time
from POR or STOP" row
Table "5V I/O Characteristics": Updated
Partial Drive IOH = +–2mA and Full Drive IOH = –10mA
Table "ATD Operating Characteristics": Distinguish IREFfor 1 and 2
ATD blocks on
Table "ATD Electrical Characteristics": Update CINS to 22 pF
Table "Operating Conditions": Changed VDD and VDDPLL to 2.35 V
(min)
Removed Document number except from Cover Sheet
Updated Table "Document References"
4 June
2002
Table "5V I/O Characteristics" : Corrected Input Capacitance to 6pF
Section: "Device Pinout" (112-pin and 80-pin): added in diagrams
RXCAN0 to PJ6 and TXCAN0 to PJ7
Table "PLL Characteristics": Updated parameters K1 and f1
Figure "Basic PLL functional diagram": Inserted XFC pin in diagram
Enhanced section "XFC Component Selection"
Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode
4 July
2002
Added 1L86D to Table "Assigned Part ID numbers"
Corrected MEMSIZ1 value in Table "Memory size registers"
Subsection "Device Memory Map: Removed Flash mapping from
$0000 to $3FFF.
Table "Signal Properties": Added column "Internal Pull Resistor".
Preface Table "Document References": Changed to full naming for
each block.
Table "Interrupt Vector Locations", Column "Local Enable":
Corrected several register and bit names.
30 July
2002
Figure "Recommended PCB Layout for 80QFP: Corrected
VREGEN pin position
Thermal values for junction to board and package
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified mode of Operations chapter
Section "Printed Circuit Board Layout Proposals": added Pierce
Oscillator examples for 112LQFP and 80QFP
V01.02
V01.03
V01.04
V01.05
6 MAR
2002
4 June
2002
4 July
2002
30 July
2002
MC9S12DJ64 Device User Guide — V01.20
Version Revision Effective
Number
Date
Date
V01.06
20 Aug.
2002
Author
Description of Changes
20 Aug.
2002
NVM electricals updated
Subsection "Detailed Register Map: Address corrections
Preface, Table "Document references": added OSC User Guide
New section "Oscillator (OSC) Block Description"
V01.07
20 Sept.
2002
20 Sept.
2002
Electrical Characteristics:
-> Section "General": removed preliminary disclaimer
->Table "Supply Current Characteristics":
changed max Run IDD from 65mA to 50mA
changes max Wait IDD from 40mA to 30mA
changed max Stop IDD from 50uA to 100uA
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
V01.08
25 Sept.
2002
25 Sept.
2002
Table "5V I/O Characteristics": Corrected Input Leakage Current to
+/- 1 uA
Section "Part ID assignment": Located on start of next page for
better readability
V01.09
10 Oct.
2002
10 Oct.
2002
Added MC9S12A64 derivative to cover sheet and "Derivative
Differences" Table
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
V01.10
8 Nov.
2002
8 Nov.
2002
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing CAN0
and/or BDLC
Table "ESD and Latch-up Test Conditions": changed pulse numbers
from 3 to 1
Table "ESD and Latch-Up Protection Characteristics": changed
parameter classification from C to T
Table "5V I/O Characteristics": removed foot note from "Input
Leakage Current"
Table " Supply Current Characteristics": updated Stop and Pseudo
Stop currents
V01.11
24 Jan.
2003
24 Jan.
2003
Subsection "Detailed Register Map": Corrected several entries
Subsection "Unsecuring the Microcontroller": Added more details
Table "Operating Conditions": improved footnote 1 wording, applied
footnote 1 to PLL Supply Voltage.
31 Mar.
2003
Tables "SPI Master/Slave Mode Timing Characteristics: Corrected
Operating Frequency
Appendix ’NVM, Flash and EEPROM’: Replaced ’burst
programming’ by ’row programming
Table "Operating Conditions": corrected minimum bus frequency to
0.25MHz
Section "Feature List": ECT features changed to "Four pulse
accumulators ..."
V01.12
31 Mar.
2003
V01.13
20 May
2003
20 May
2003
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides
Table "Signal Properties" corrected pull resistor reset state for PE7
and PE4-PE2.
Table "Absolute Maximum Ratings" corrected footnote on clamp of
TEST pin.
V01.14
10 June
2003
10 June
2003
Added cycle definition to "CPU 12 Block Description".
Added register reset values to MMC and MEBI block descriptions.
Diagram "Clock Connections": Connect Bus Clock to HCS12 Core
3
MC9S12DJ64 Device User Guide — V01.20
Version Revision Effective
Number
Date
Date
Author
Description of Changes
V01.15
22 July
2003
22 July
2003
Mentioned "S12 LRAE" bootloader in Flash section
Section Document References: corrected S12 CPU document
reference
V01.16
24 Feb.
2004
24 Feb.
2004
Added 3L86D maskset with corresponding Part ID
Table Oscillator Characteristics: Added more details for EXTAL pin
V01.17
21 May
2004
21 May
2004
Added 4L86D maskset with corresponding Part ID
Table "MC9S12DJ64 Memory Map out of Reset": corrected $1000 $3fff memory in single chip modes to "unimplemented".
V01.18
13 July
2004
13 July
2004
Added MC9S12D32 and MC9S12A32
V01.19
2 Sept.
2004
2 Sept.
2004
Appendix, Table "Oscillator Characteristics": changed
item 13 VIH,EXTAL min value from 0.7*VDDPLL to 0.75*VDDPLL
item 14 VIL,EXTAL max value from 0.3*VDDPLL to 0.25*VDDPLL
V01.20
6 April
2005
6 April
2005
Table "Assigned Part ID Numbers": added mask set number
0M89C
Table "NVM Reliability Characteristics": added footnote concerning
data retention
4
MC9S12DJ64 Device User Guide — V01.20
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.5.1
1.6
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.2
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.1
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.2
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.3
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.4
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.5
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.6
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .56
2.3.7
PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .57
2.3.8
PAD[14:08] / AN[14:08] — Port AD Input Pins ATD1 . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.9
PAD07 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . .57
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .57
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5
MC9S12DJ64 Device User Guide — V01.20
2.3.21
2.3.22
2.3.23
2.3.24
2.3.25
2.3.26
2.3.27
2.3.28
2.3.29
2.3.30
2.3.31
2.3.32
2.3.33
2.3.34
2.3.35
2.3.36
2.3.37
2.3.38
2.3.39
2.3.40
2.3.41
2.3.42
2.3.43
2.3.44
2.3.45
2.3.46
2.3.47
2.3.48
2.3.49
2.3.50
2.3.51
2.3.52
2.3.53
2.3.54
2.3.55
2.3.56
6
PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PH3 / KWH3 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PH2 / KWH2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PH1 / KWH1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PH0 / KWH0 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PJ7 / KWJ7 / SCL / TXCAN0 — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .60
PJ6 / KWJ6 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . .61
PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PM7 — Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PM6 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PM5 / TXCAN0 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PM4 / RXCAN0 / MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PM3 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PM2 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
PP3 / KWP3 / PWM3 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PP2 / KWP2 / PWM2 — Port P I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PP1 / KWP1 / PWM1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PP0 / KWP0 / PWM0 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
MC9S12DJ64 Device User Guide — V01.20
2.3.57 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.4.1
VDDX, VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . .65
2.4.2
VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
65
2.4.3
VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins . . . . . . . . . . . . . . .65
2.4.4
VDDA, VSSA — Power Supply Pins for ATD0/ATD1 and VREG . . . . . . . . . . . . . . .65
2.4.5
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.4.6
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.4.7
VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Section 3 System Clock Description
3.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 4 Modes of Operation
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Section 5 Resets and Interrupts
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2.1
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.3
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.3.1
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.3.2
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Section 6 HCS12 Core Block Description
7
MC9S12DJ64 Device User Guide — V01.20
6.1
6.1.1
6.2
6.2.1
6.3
6.3.1
6.4
6.5
6.5.1
6.6
CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . . . .77
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . . . .77
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . .78
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 7 Clock and Reset Generator (CRG) Block Description
7.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 8 Oscillator (OSC) Block Description
8.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 9 Enhanced Capture Timer (ECT) Block Description
Section 10 Analog to Digital Converter (ATD) Block Description
Section 11 Inter-IC Bus (IIC) Block Description
Section 12 Serial Communications Interface (SCI) Block Description
Section 13 Serial Peripheral Interface (SPI) Block Description
Section 14 J1850 (BDLC) Block Description
Section 15 Pulse Width Modulator (PWM) Block Description
Section 16 Flash EEPROM 64K Block Description
Section 17 EEPROM 1K Block Description
Section 18 RAM Block Description
Section 19 MSCAN Block Description
8
MC9S12DJ64 Device User Guide — V01.20
Section 20 Port Integration Module (PIM) Block Description
Section 21 Voltage Regulator (VREG) Block Description
Section 22 Printed Circuit Board Layout Proposals
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.1
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.2
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.3
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
A.1.4
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
A.1.5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.6
ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
A.1.7
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
A.1.8
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.1.9
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.2.1
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.2.2
Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.2.3
ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.3.1
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.3.2
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
A.5.1
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
A.5.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
A.5.3
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A.7.1
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A.7.2
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
A.8.1
General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9
MC9S12DJ64 Device User Guide — V01.20
Appendix B Package Information
B.1
B.2
B.3
10
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
MC9S12DJ64 Device User Guide — V01.20
List of Figures
Figure 0-1
Figure 1-1
Figure 1-2
Figure 1-3
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 3-1
Figure 22-1
Figure 22-2
Figure 22-3
Figure 22-4
Figure A-1
Figure A-2
Figure A-3
Figure A-4
Figure A-5
Figure A-6
Figure A-7
Figure A-8
Figure A-9
Figure B-1
Figure B-2
Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
MC9S12DJ64 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
MC9S12DJ64 Memory Map out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MC9S12D32 Memory Map out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Pin Assignments in 112-pin LQFP for MC9S12DJ64 . . . . . . . . . . . . . . . . . . . . .52
Pin Assignments in 80-pin QFP for MC9S12DJ64 and MC9S12D32 . . . . . . . . .53
PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Recommended PCB Layout 112LQFP Colpitts Oscillator. . . . . . . . . . . . . . . . . .82
Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .83
Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .84
Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .85
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 124
80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 125
11
MC9S12DJ64 Device User Guide — V01.20
12
MC9S12DJ64 Device User Guide — V01.20
List of Tables
Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 1-1 Device Memory Map for MC9S12DJ64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 1-2 Device Memory Map for MC9S12D32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) ................30
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) ...............................30
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) ............................................................31
$0017 - $0019 Reserved ..................................................................................................31
$001A - $001B Device ID Register (Table 1-4) ................................................................31
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-5) ..............31
$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) ................31
$001F - $001F INT map 2 of 2 (HCS12 Interrupt) ............................................................32
$0020 - $0027 Reserved ..................................................................................................32
$0028 - $002F BKP (HCS12 Breakpoint) .........................................................................32
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) ...............................32
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) ................32
$0034 - $003F CRG (Clock and Reset Generator) ..........................................................33
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) .................................33
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..............................36
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................37
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................39
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................39
$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................40
$00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................40
$00E8 - $00EF BDLC (Bytelevel Data Link Controller J1850) ..........................................41
$00F0 - $00FF Reserved ..................................................................................................41
$0100 - $010F Flash Control Register (fts64k) ................................................................41
$0110 - $011B EEPROM Control Register (eets1k) ........................................................42
$011C - $011F Reserved for RAM Control Register ........................................................42
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................43
$0140 - $017F CAN0 (Freescale Scalable CAN - FSCAN) ..............................................44
Table 1-3 Detailed FSCAN Foreground Receive and Transmit Buffer Layout . . . . . . . . . . .45
$0180 - $023F Reserved ..................................................................................................46
13
MC9S12DJ64 Device User Guide — V01.20
$0240 - $027F PIM (Port Integration Module) ..................................................................46
$0280 - $03FF Reserved ..................................................................................................48
Table 1-4 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 1-5 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 2-2 MC9S12DJ64 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .64
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . .105
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table A-17 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
14
MC9S12DJ64 Device User Guide — V01.20
Derivative Differences and Document References
Derivative Differences
Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the
compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
Table 0-1 Derivative Differences
Generic device
MC9S12DJ64
MC9S12D64
MC9S12A64
MC9S12D32
MC9S12A32
CAN0
1
1
0
1
0
J1850/BDLC
1
0
0
0
0
Packages
112LQFP, 80QFP
112LQFP, 80QFP
112LQFP, 80QFP
80QFP
80QFP
Mask Set
L86D
L86D
L86D
L86D
L86D
Temp Options
M, V, C
M, V, C
C
M, V, C
C
Package Codes
PV, FU
PV, FU
PV, FU
FU
FU
Note
An errata exists
contact Sales
office
An errata exists
contact Sales
office
An errata exists
contact Sales
office
An errata exists
contact Sales
office
An errata exists
contact Sales
office
MC9S12 DJ64 C FU
Package Option
Temperature Option
Device Title
Controller Family
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
FU =
80QFP
PV = 112LQFP
Figure 0-1 Order Partnumber Example
The following items should be considered when using a derivative.
•
•
Registers
–
Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a
derivative without CAN0 (see Table 0-1).
–
Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC (see Table 0-1).
Interrupts
–
Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for
unused interrupts, if using a derivative without CAN0 (see Table 0-1).
–
Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused
interrupts, if using a derivative without BDLC (see Table 0-1).
15
MC9S12DJ64 Device User Guide — V01.20
•
•
Ports
–
The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5,
PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0 (see Table 0-1).
–
The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
derivative without BDLC (see Table 0-1).
–
Do not write MODRR1 and MODRR0 Bit of Module Routing Register (PIM_9DJ64 Block
User Guide), if using a derivative without CAN0 (see Table 0-1).
Pins not available in 80 pin QFP package
–
Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
–
Port J[1:0]
Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must
be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at
Base+$026C.
–
Port K
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefor care must be taken not to clear this bit.
–
Port M[7:6]
PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–
Port P6
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
–
Port S[7:4]
PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–
PAD[15:8] (ATD1 channels)
Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1
registers!
Document References
The Device User Guide provides information about the MC9S12DJ64 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes all
the individual Block Guides of the implemented modules. In a effort to reduce redundancy all module
specific information is located only in the respective Block Guide. If applicable, special implementation
details of the module are given in the block description sections of this document.
See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide.
16
MC9S12DJ64 Device User Guide — V01.20
Table 0-2 Document References
Versi
on
User Guide
Document Order Number
HCS12 CPU Reference Manual
V02
S12CPUV2/D
HCS12 Module Mapping Control (MMC) Block Guide
V04
S12MMCV4/D
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide
V03
S12MEBIV3/D
HCS12 Interrupt (INT) Block Guide
V01
S12INTV1/D
HCS12 Background Debug (BDM) Block Guide
V04
S12BDMV4/D
HCS12 Breakpoint (BKP) Block Guide
V01
S12BKPV1/D
Clock and Reset Generator (CRG) Block User Guide
V04
S12CRGV4/D
Oscillator (OSC) Block User Guide
V02
S12OSCV2/D
Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide
V01
S12ECT16B8CV1/D
Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide
V02
S12ATD10B8CV2/D
Inter IC Bus (IIC) Block User Guide
V02
S12IICV2/D
Asynchronous Serial Interface (SCI) Block User Guide
V02
S12SCIV2/D
Serial Peripheral Interface (SPI) Block User Guide
V02
S12SPIV2/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide
V01
S12PWM8B8CV1/D
64K Byte Flash (FTS64K) Block User Guide
V01
S12FTS64KV1/D
1K Byte EEPROM (EETS1K) Block User Guide
V01
S12EETS1KV1/D
Byte Level Data Link Controller -J1850 (BDLC) Block User Guide
V01
S12BDLCV1/D
Freescale Scalable CAN (MSCAN) Block User Guide V02
S12MSCANV2/D
Voltage Regulator (VREG) Block User Guide
V01
S12VREGV1/D
Port Integration Module (PIM_9DJ64) Block User Guide
V01
S12PIM9DJ64V1/D
17
MC9S12DJ64 Device User Guide — V01.20
18
MC9S12DJ64 Device User Guide — V01.20
Section 1 Introduction
1.1 Overview
The MC9S12DJ64 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of Flash EEPROM, 4K
bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), one
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wakeup capability, a CAN 2.0 A, B software compatible modules
(MSCAN12), and an Inter-IC Bus. The MC9S12DJ64 has full 16-bit data paths throughout. However, the
external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower
cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to
suit operational requirements.
1.2 Features
•
HCS12 Core
–
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
–
MEBI (Multiplexed External Bus Interface)
–
MMC (Module Mapping Control)
–
INT (Interrupt control)
–
BKP (Breakpoints)
–
BDM (Background Debug Mode)
•
CRG (low current Colpitts or Pierce oscillator, PLL, reset, clocks, COP watchdog, real time
interrupt, clock monitor)
•
8-bit and 4-bit ports with interrupt functionality
•
–
Digital filtering
–
Programmable rising or falling edge trigger
Memory
–
64K Flash EEPROM
–
1K byte EEPROM
19
MC9S12DJ64 Device User Guide — V01.20
–
•
•
•
•
•
•
Two 8-channel Analog-to-Digital Converters
–
10-bit resolution
–
External conversion trigger capability
1M bit per second, CAN 2.0 A, B software compatible module
–
Five receive and three transmit buffers
–
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
–
Four separate interrupt channels for Rx, Tx, error and wake-up
–
Low-pass filter wake-up function
–
Loop-back for self test operation
Enhanced Capture Timer
–
16-bit main counter with 7-bit prescaler
–
8 programmable input capture or output compare channels
–
Four 8-bit or two 16-bit pulse accumulators
8 PWM channels
–
Programmable period and duty cycle
–
8-bit 8-channel or 16-bit 4-channel
–
Separate control for each pulse width and duty cycle
–
Center-aligned or left-aligned outputs
–
Programmable clock select logic with a wide range of frequencies
–
Fast emergency shutdown input
–
Usable as interrupt inputs
Serial interfaces
–
Two asynchronous Serial Communications Interfaces (SCI)
–
Synchronous Serial Peripheral Interface (SPI)
Byte Data Link Controller (BDLC)
–
•
•
20
4K byte RAM
SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible
for Low-Speed (=100nF
C5
VDDPLL filter cap
ceramic X7R
100nF
C6
VDDX filter cap
X7R/tantalum
>=100nF
C7
OSC load cap
C8
OSC load cap
C9 / CS
PLL loop filter cap
C10 / CP
PLL loop filter cap
C11 / CDC
DC cutoff cap
Colpitts mode only, if recommended by
quartz manufacturer
R1
PLL loop filter res
See PLL specification chapter
R2 / RB
PLL loop filter res
R3 / RS
PLL loop filter res
Q1
Quartz
See PLL specification chapter
Pierce mode only
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins(C1 - C6).
•
Central point of the ground star should be the VSSR pin.
•
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
•
VSSPLL must be directly connected to VSSR.
•
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
•
Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
•
Central power input should be fed in at the VDDA/VSSA pins.
81
MC9S12DJ64 Device User Guide — V01.20
Figure 22-1 Recommended PCB Layout 112LQFP Colpitts Oscillator
VREGEN
C6
VDDX
VSSX
VSSA
C3
VDDA
VDD1
C1
VSS1
VSS2
C2
VDD2
VSSR
C4
C7
82
C8
C10
C9
R1
C11
C5
VDDR
Q1
VSSPLL
VDDPLL
MC9S12DJ64 Device User Guide — V01.20
Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator
VREGEN
C6
VDDX
VSSX
VSSA
C3
VDDA
VDD1
VSS2
C1
C2
VSS1
VDD2
VSSR
C4
C5
VDDR
C7
C8
C11
Q1
C10
C9
R1
VSSPLL
VDDPLL
83
MC9S12DJ64 Device User Guide — V01.20
Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator
VREGEN
C6
VDDX
VSSX
VSSA
C3
VDDA
VDD1
C1
VSS1
VSS2
C2
VDD2
VSSR
VSSPLL
C4
R3
C5
VDDR
R2
Q1
84
C7
R1
C8
C10
C9
VDDPLL
MC9S12DJ64 Device User Guide — V01.20
Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator
VREGEN
C6
VDDX
VSSX
VSSA
C3
VDDA
VDD1
VSS2
C1
C2
VSS1
VDD2
VSSPLL
VSSR
C4
R3
C5
VDDR
R2
Q1
C7
C8
C10
C9
R1
VSSPLL
VDDPLL
85
MC9S12DJ64 Device User Guide — V01.20
86
MC9S12DJ64 Device User Guide — V01.20
Appendix A Electrical Characteristics
A.1 General
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE:
This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12DJ64 and MC9S12D32 utilize several pins to supply power to the I/O ports, A/D converter,
oscillator, PLL and internal logic.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage
regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the
oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
87
MC9S12DJ64 Device User Guide — V01.20
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.3.5 VREGEN
This pin is used to enable the on chip voltage regulator.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
88
MC9S12DJ64 Device User Guide — V01.20
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings1
Num
Rating
Symbol
Min
Max
Unit
1
I/O, Regulator and Analog Supply Voltage
VDD5
-0.3
6.0
V
2
Digital Logic Supply Voltage 2
VDD
-0.3
3.0
V
3
PLL Supply Voltage 2
VDDPLL
-0.3
3.0
V
4
Voltage difference VDDX to VDDR and VDDA
∆VDDX
-0.3
0.3
V
5
Voltage difference VSSX to VSSR and VSSA
∆VSSX
-0.3
0.3
V
6
Digital I/O Input Voltage
VIN
-0.3
6.0
V
7
Analog Reference
VRH, VRL
-0.3
6.0
V
8
XFC, EXTAL, XTAL inputs
VILV
-0.3
3.0
V
9
TEST input
VTEST
-0.3
10.0
V
10
Instantaneous Maximum Current
Single pin limit for all digital I/O pins 3
ID
-25
+25
mA
11
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL4
I
DL
-25
+25
mA
12
Instantaneous Maximum Current
Single pin limit for TEST 5
IDT
-0.25
0
mA
13
Storage Temperature Range
T
– 65
155
°C
stg
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
4. Those pins are internally clamped to VSSPLL and VDDPLL.
5. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
89
MC9S12DJ64 Device User Guide — V01.20
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Human Body
Machine
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ohm
Storage Capacitance
C
100
pF
Number of Pulse per pin
positive
negative
-
1
1
Series Resistance
R1
0
Ohm
Storage Capacitance
C
200
pF
Number of Pulse per pin
positive
negative
-
3
3
Minimum input voltage limit
-2.5
V
Maximum input voltage limit
7.5
V
Latch-up
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
Rating
Symbol
Min
Max
Unit
1
T Human Body Model (HBM)
VHBM
2000
-
V
2
T Machine Model (MM)
VMM
200
-
V
3
T Charge Device Model (CDM)
VCDM
500
-
V
4
Latch-up Current at TA = 125°C
T positive
negative
ILAT
+100
-100
-
mA
5
Latch-up Current at TA = 27°C
T positive
negative
ILAT
+200
-200
-
mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
90
MC9S12DJ64 Device User Guide — V01.20
NOTE:
Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature TA and the junction temperature TJ. For power dissipation
calculations refer to Section A.1.8 Power Dissipation and Thermal
Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
Typ
Max
Unit
I/O, Regulator and Analog Supply Voltage
VDD5
4.5
5
5.25
V
Digital Logic Supply Voltage 1
VDD
2.35
2.5
2.75
V
PLL Supply Voltage 1
VDDPLL
2.35
2.5
2.75
V
Voltage Difference VDDX to VDDR and VDDA
∆VDDX
-0.1
0
0.1
V
Voltage Difference VSSX to VSSR and VSSA
∆VSSX
-0.1
0
0.1
V
Oscillator
fosc
0.5
-
16
MHz
Bus Frequency
fbus
0.252
-
25
MHz
Operating Junction Temperature Range
T
J
-40
-
100
°C
Operating Ambient Temperature Range 3
T
A
-40
27
85
°C
J
-40
-
120
°C
TA
-40
27
105
°C
Operating Junction Temperature Range
TJ
-40
-
140
°C
Operating Ambient Temperature Range 3
TA
-40
27
125
°C
MC9S12DJ64C
MC9S12DJ64V
Operating Junction Temperature Range
Operating Ambient Temperature Range 3
T
MC9S12DJ64M
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
given operating range applies when this regulator is disabled and the device is powered from an external source.
2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation.
3. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
T J = T A + ( P D • Θ JA )
T J = Junction Temperature, [°C ]
91
MC9S12DJ64 Device User Guide — V01.20
T A = Ambient Temperature, [°C ]
P D = Total Chip Power Dissipation, [W]
Θ JA = Package Thermal Resistance, [°C/W]
The total power dissipation can be calculated from:
P D = P INT + P IO
P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled
P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA
2
P IO =
R DSON ⋅ I IO
i
i
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
For RDSON is valid:
V OL
R DSON = ------------ ;for outputs driven low
I OL
respectively
V DD5 – V OH
R DSON = ------------------------------------ ;for outputs driven high
I OH
2. Internal voltage regulator enabled
P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA
IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.
2
P IO =
R DSON ⋅ I IO
i
i
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
92
MC9S12DJ64 Device User Guide — V01.20
Table A-5 Thermal Package Characteristics1
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
T Thermal Resistance LQFP112, single sided PCB2
θJA
–
–
54
o
2
T
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
θJA
–
–
41
o
3
T Junction to Board LQFP112
θJB
–
–
31
oC/W
4
T Junction to Case LQFP112
θJC
–
–
11
o
5
T Junction to Package Top LQFP112
ΨJT
–
–
2
o
6
T Thermal Resistance QFP 80, single sided PCB
θJA
–
–
51
oC/W
7
T
θJA
–
–
41
oC/W
8
T Junction to Board QFP80
θJB
–
–
27
oC/W
9
T Junction to Case QFP80
θJC
–
–
14
oC/W
10
T Junction to Package Top QFP80
ΨJT
–
–
3
oC/W
Thermal Resistance QFP 80, double sided PCB with
2 internal planes
C/W
C/W
C/W
C/W
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-3
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all pins feature pull up/down resistances.
93
MC9S12DJ64 Device User Guide — V01.20
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
1
P Input High Voltage
V
2
P Input Low Voltage
V
3
C Input Hysteresis
4
Input Leakage Current (pins in high impedance input
P mode)
V =V
or VSS5
in
DD5
5
Output High Voltage (pins in output mode)
P Partial Drive IOH = –2mA
Full Drive IOH = –10mA
V
6
Output Low Voltage (pins in output mode)
P Partial Drive IOL = +2mA
Full Drive IOL = +10mA
7
IH
IL
Min
Typ
Max
Unit
0.65*VDD5
-
VDD5 + 0.3
V
VSS5 - 0.3
-
0.35*VDD5
V
V
250
HYS
mV
–1
-
1
µA
VDD5 – 0.8
-
-
V
V
OL
-
-
0.8
V
Internal Pull Up Device Current,
P tested at V Max.
IPUL
-
-
–130
µA
Internal Pull Up Device Current,
C tested at V Min.
IPUH
-10
-
-
µA
Internal Pull Down Device Current,
P tested at V Min.
IPDH
-
-
130
µA
Internal Pull Down Device Current,
C tested at V Max.
IPDL
10
-
-
µA
11
D Input Capacitance
Cin
6
-
pF
12
Injection current1
T Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
-
2.5
25
mA
13
P Port H, J, P Interrupt Input Pulse filtered2
tpign
3
µs
14
P Port H, J, P Interrupt Input Pulse passed2
tpval
IL
8
IH
9
IH
10
IL
Iin
OH
-2.5
-25
10
µs
NOTES:
1. Refer to Section A.1.4 Current Injection, for more details
2. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
94
MC9S12DJ64 Device User Guide — V01.20
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Run supply currents
Single Chip, Internal regulator enabled
IDD5
50
IDDW
30
5
1
P
2
P
P
All modules enabled, PLL on
only RTI enabled 1
C
P
C
C
P
C
P
C
P
Pseudo Stop Current (RTI and COP disabled) 1, 2
-40°C
27°C
70°C
85°C
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
C
C
C
C
C
C
C
Pseudo Stop Current (RTI and COP enabled) 1, 2
-40°C
27°C
70°C
85°C
105°C
125°C
140°C
Min
Typ
Max
Unit
mA
Wait Supply current
3
4
IDDPS
IDDPS
370
400
450
550
600
650
800
850
1200
mA
500
1600
µA
2100
5000
570
600
650
750
850
1200
1500
µA
Stop Current 2
5
C
P
C
C
P
C
P
C
P
-40°C
27°C
70°C
85°C
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
IDDS
12
25
100
130
160
200
350
400
600
100
1200
µA
1700
5000
95
MC9S12DJ64 Device User Guide — V01.20
NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed
96
MC9S12DJ64 Device User Guide — V01.20
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
VRL
VRH
VSSA
VDDA/2
Typ
Max
Unit
VDDA/2
VDDA
V
V
5.25
V
Reference Potential
1
D
Low
High
2
C Differential Reference Voltage1
VRH-VRL
4.50
3
D ATD Clock Frequency
fATDCLK
0.5
2.0
MHz
4
D
14
7
28
14
Cycles
µs
5
D
12
6
26
13
Cycles
µs
6
D Recovery Time (VDDA=5.0 Volts)
tREC
20
µs
7
P Reference Supply current 2 ATD blocks on
IREF
0.750
mA
8
P Reference Supply current 1 ATD block on
IREF
0.375
mA
5.00
ATD 10-Bit Conversion Period
Clock Cycles2 NCONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10
ATD 8-Bit Conversion Period
Clock Cycles2
Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8
TCONV8
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
97
MC9S12DJ64 Device User Guide — V01.20
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN).
A.2.2.3 Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than
VRL unless the current is higher than specified as disruptive condition.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
RS
-
-
1
KΩ
10
22
pF
2.5
mA
1
C Max input Source Resistance
2
Total Input Capacitance
T Non Sampling
Sampling
3
C Disruptive Analog Input Current
INA
4
C Coupling Ratio positive current injection
Kp
10-4
A/A
5
C Coupling Ratio negative current injection
Kn
10-2
A/A
98
CINN
CINS
-2.5
MC9S12DJ64 Device User Guide — V01.20
A.2.3 ATD accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz
Num C
Rating
Symbol
Min
1
P 10-Bit Resolution
LSB
2
P 10-Bit Differential Nonlinearity
DNL
–1
3
P 10-Bit Integral Nonlinearity
INL
–2.5
4
P 10-Bit Absolute Error1
AE
-3
5
P 8-Bit Resolution
LSB
6
P 8-Bit Differential Nonlinearity
DNL
–0.5
7
P 8-Bit Integral Nonlinearity
INL
–1.0
AE
-1.5
8
P 8-Bit Absolute
Error1
Typ
Max
5
Unit
mV
1
Counts
±1.5
2.5
Counts
±2.0
3
Counts
20
mV
0.5
Counts
±0.5
1.0
Counts
±1.0
1.5
Counts
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
DNL ( i ) = ------------------------ – 1
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
INL ( n ) =
∑
i=1
Vn – V0
DNL ( i ) = -------------------- – n
1LSB
99
MC9S12DJ64 Device User Guide — V01.20
DNL
10-Bit Absolute Error Boundary
LSB
Vi-1
Vi
$3FF
8-Bit Absolute Error Boundary
$3FE
$3FD
$3FC
$FF
$3FB
$3FA
$3F9
$3F8
$FE
$3F7
$3F6
$3F4
8-Bit Resolution
10-Bit Resolution
$3F5
$FD
$3F3
9
Ideal Transfer Curve
8
2
7
10-Bit Transfer Curve
6
5
4
1
3
8-Bit Transfer Curve
2
1
0
5
10
15
20
25
30
35
40
45
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-1 ATD Accuracy Definitions
NOTE:
100
Figure A-1 shows only definitions, for specification values refer to Table A-10.
MC9S12DJ64 Device User Guide — V01.20
A.3 NVM, Flash and EEPROM
NOTE:
Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.3.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP.
The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
1
1
t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f NVMOP
f bus
A.3.1.2 Row Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively by keeping
the command pipeline filled. The time to program a consecutive word can be calculated as:
1
1
t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ---------f NVMOP
f bus
The time to program a whole row is:
t brpgm = t swpgm + 31 ⋅ t bwpgm
Row programming is more than 2 times faster than single word programming.
A.3.1.3 Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
101
MC9S12DJ64 Device User Guide — V01.20
1
t era ≈ 4000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
A.3.1.4 Mass Erase
Erasing a NVM block takes:
1
t mass ≈ 20000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
A.3.1.5 Blank Check
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t check ≈ location ⋅ t cyc + 10 ⋅ t cyc
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
50 1
MHz
1
D External Oscillator Clock
fNVMOSC
0.5
2
D Bus frequency for Programming or Erase Operations
fNVMBUS
1
3
D Operating Frequency
fNVMOP
150
200
kHz
4
P Single Word Programming Time
tswpgm
46 2
74.5 3
µs
5
D Flash Burst Programming consecutive word 4
tbwpgm
20.4 2
31 3
µs
6
D Flash Burst Programming Time for 32 Words 4
tbrpgm
678.4 2
1035.5 3
µs
7
P Sector Erase Time
tera
20 5
26.7 3
ms
8
P Mass Erase Time
tmass
100 5
133 3
ms
9
D Blank Check Time Flash per block
tcheck
11 6
32778 7
tcyc
10
D Blank Check Time EEPROM per block
tcheck
11 6
20587
tcyc
MHz
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus.
3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus.
Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. Burst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block
102
MC9S12DJ64 Device User Guide — V01.20
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Data Retention at an average junction temperature of
TJavg = 85°C1
tNVMRET
15
Years
nFLPE
10,000
Cycles
1
C
2
C Flash number of Program/Erase cycles
3
C
EEPROM number of Program/Erase cycles
(–40°C ≤ TJ ≤ 0°C)
nEEPE
10,000
Cycles
4
C
EEPROM number of Program/Erase cycles
(0°C < TJ ≤ 140°C)
nEEPE
100,000
Cycles
NOTES:
1. Total time at the maximum guaranteed device operating temperature
工商网监
湘ICP备2023018690号
