MC9S12Q128

MC9S12Q128 Reference Manual Covers MC9S12Q Family HCS12 Microcontrollers Rev 1.10 MC9S12Q128 05/2010 freescale.com To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the S12 CPU. For S12 CPU information please refer to the CPU S12 Reference Manual. Date January 2006 Revision Level 01.05 Description Updated LVI levels in electrical parameter section Fixed incorrect reference to TSCR2 Added 0M66G PART ID number Corrected missing overbars on pin names Added units to MSCAN timing table Corrected CRGFLG contents in register summary Corrected unintended symbol font Added emulation package info. Corrected TIM and PWM channel count in PIM section Updated ATD section Corrected typos and inconsistent register listing format Added new PartID Updated TIM section (see TIM rev. history) May 2006 01.06 Dec 2006 01.07 May 2007 01.08 Dec 2007 May 2010 01.09 01.10 Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 MC9S12Q Device Overview (MC9S12Q128-Family) . . . . . . . . 17 Port Integration Module (PIM9C32) . . . . . . . . . . . . . . . . . . . . . 73 Module Mapping Control (MMCV4) . . . . . . . . . . . . . . . . . . . . 109 Multiplexed External Bus Interface (MEBIV3) . . . . . . . . . . . . 129 Interrupt (INTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Background Debug Module (BDMV4) . . . . . . . . . . . . . . . . . . 165 Debug Module (DBGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Analog-to-Digital Converter (ATD10B8C) . . . . . . . . . . . . . . . 223 Clocks and Reset Generator (CRGV4) . . . . . . . . . . . . . . . . . . 251 Scalable Controller Area Network (S12MSCANV2) . . . . . . . . 287 Oscillator (OSCV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Pulse-Width Modulator (PWM8B4CV1). . . . . . . . . . . . . . . . . 347 Serial Communications Interface (S12SCIV2) . . . . . . . . . . . . 379 Serial Peripheral Interface (SPIV3) . . . . . . . . . . . . . . . . . . . . . 409 Timer Module (TIM16B6C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Dual Output Voltage Regulator (VREG3V3V2) . . . . . . . . . . . 455 32 Kbyte Flash Module (S12FTS32KV1) . . . . . . . . . . . . . . . . . 463 64 Kbyte Flash Module (S12FTS64KV4) . . . . . . . . . . . . . . . . . 497 96 Kbyte Flash Module (S12FTS96KV1) . . . . . . . . . . . . . . . . . 531 128 Kbyte Flash Module (S12FTS128K1V1) . . . . . . . . . . . . . . 565 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Appendix B Emulation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 Appendix E Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 Freescale Semiconductor MC9S12Q128 Rev 1.10 3 4 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2.1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2.2 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.2.3 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.3.1 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.3.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.3.3 Pin Initialization for 48- and 52-Pin LQFP Bond Out Versions . . . . . . . . . . . . . . . . . . . 49 1.3.4 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.3.5 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.5.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 1.5.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.5.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.6.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Device Specific Information and Module Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.7.1 PPAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.7.2 BDM Alternate Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.7.3 Extended Address Range Emulation Implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 1.7.4 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.7.5 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.7.6 Clock Reset Generator And VREG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.7.7 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.7.8 MODRR Register Port T And Port P Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.7.9 Port AD Dependency On PIM And ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Recommended Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.2 2.3 Freescale Semiconductor MC9S12Q128 Rev 1.10 5 2.4 2.5 2.6 2.7 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.4.2 Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.4.3 Port A, B, E and BKGD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.4.4 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.4.5 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.6.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 2.6.2 Recovery from STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Chapter 3 Module Mapping Control (MMCV4) Block Description 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.4.1 Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.4.2 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.4.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.2 3.3 3.4 Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.4.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.4.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.4.4 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.2 4.3 4.4 6 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 5 Interrupt (INTV1) Block Description 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.4.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.6.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.6.2 Highest Priority I-Bit Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.6.3 Interrupt Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.2 5.3 5.4 5.5 5.6 5.7 Chapter 6 Background Debug Module (BDMV4) Block Description 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.2.1 BKGD — Background Interface Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.2.2 TAGHI — High Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.2.3 TAGLO — Low Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 6.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.4.11 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.4.12 Serial Communication Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.4.13 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.2 6.3 6.4 Freescale Semiconductor MC9S12Q128 Rev 1.10 7 6.4.14 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Chapter 7 Debug Module (DBGV1) Block Description 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 7.4.1 DBG Operating in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 7.4.2 DBG Operating in DBG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 7.4.3 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 7.2 7.3 7.4 7.5 7.6 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.1 AN7 / ETRIG / PAD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.2 AN6 / PAD6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.3 AN5 / PAD5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.4 AN4 / PAD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.5 AN3 / PAD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.6 AN2 / PAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.7 AN1 / PAD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.8 AN0 / PAD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.9 VRH, VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.2.10 VDDA, VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8.4.2 Digital Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 8.2 8.3 8.4 8.5 8 MC9S12Q128 Rev 1.10 Freescale Semiconductor 8.6 8.7 8.5.1 Setting up and starting an A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 8.5.2 Aborting an A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 9.2.1 VDDPLL, VSSPLL — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 253 9.2.2 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 9.2.3 RESET — Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 9.4.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 9.4.2 System Clocks Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 9.4.3 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 9.4.4 Clock Quality Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 9.4.5 Computer Operating Properly Watchdog (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 9.4.6 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 9.4.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 9.4.8 Low-Power Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.4.9 Low-Power Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.4.10 Low-Power Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 9.5.1 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.5.2 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.5.3 Power-On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.6.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.6.3 Self-Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.2 9.3 9.4 9.5 9.6 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Freescale Semiconductor MC9S12Q128 Rev 1.10 9 10.2 10.3 10.4 10.5 10.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 10.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 10.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 10.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 10.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 10.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Chapter 11 Oscillator (OSCV2) Block Description 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 11.2.1 VDDPLL and VSSPLL — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 344 11.2.2 EXTAL and XTAL — Clock/Crystal Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 11.2.3 XCLKS — Colpitts/Pierce Oscillator Selection Signal . . . . . . . . . . . . . . . . . . . . . . . . . 345 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.4.1 Amplitude Limitation Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.4.2 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 11.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Chapter 12 Pulse-Width Modulator (PWM8B4C) Block Description 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.2.1 PWM3 — Pulse Width Modulator Channel 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.2.2 PWM2 — Pulse Width Modulator Channel 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 10 MC9S12Q128 Rev 1.10 Freescale Semiconductor 12.3 12.4 12.5 12.6 12.2.3 PWM1 — Pulse Width Modulator Channel 1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.2.4 PWM0 — Pulse Width Modulator Channel 0 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 12.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 12.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 13.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 13.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.2.1 TXD-SCI Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.2.2 RXD-SCI Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 13.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 13.4.2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 13.4.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 13.4.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 13.4.5 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 13.4.6 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 13.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 13.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 13.5.2 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 13.5.3 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Freescale Semiconductor MC9S12Q128 Rev 1.10 11 14.3 14.4 14.5 14.6 14.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 14.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 14.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 14.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 14.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 14.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 14.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 14.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 14.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 14.4.7 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 14.4.8 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 14.4.9 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 14.6.1 MODF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 14.6.2 SPIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 14.6.3 SPTEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Chapter 15 Timer Module (TIM16B6CV1) Block Description 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 15.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 15.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 434 15.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 434 15.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 434 15.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 434 15.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 434 15.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 434 15.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 15.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 15.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 15.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 15.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 15.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 12 MC9S12Q128 Rev 1.10 Freescale Semiconductor 15.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 15.6.1 Channel [7:2] Interrupt (C[7:2]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 15.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 15.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 15.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 16.2.1 VDDR — Regulator Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 16.2.2 VDDA, VSSA — Regulator Reference Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 16.2.3 VDD, VSS — Regulator Output1 (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 16.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 16.2.5 VREGEN — Optional Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 16.4.1 REG — Regulator Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.4.2 Full-Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.4.3 Reduced-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.4.4 LVD — Low-Voltage Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.4.5 POR — Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.4.6 LVR — Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.4.7 CTRL — Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.5.2 Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.6.1 LVI — Low-Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 17.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 17.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Freescale Semiconductor MC9S12Q128 Rev 1.10 13 17.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 17.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 17.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 17.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.4.3 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.4.4 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 17.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 18.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 18.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 18.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 18.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 18.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 18.4.3 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 18.4.4 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 18.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 19.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 19.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 19.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 19.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 19.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 19.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 14 MC9S12Q128 Rev 1.10 Freescale Semiconductor 19.4.3 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 19.4.4 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 19.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 20.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 20.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 20.4.3 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 20.4.4 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 20.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 Appendix A Electrical Characteristics A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 A.2.1 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 A.2.2 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 A.2.3 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 A.2.4 ATD Accuracy (5V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 A.2.5 ATD Accuracy (3.3V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 A.3 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 A.4 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 A.4.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 Freescale Semiconductor MC9S12Q128 Rev 1.10 15 A.4.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 A.4.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 A.5 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 A.5.1 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 A.5.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 A.6 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 A.6.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 A.6.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 A.7 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 A.7.1 Voltage Regulator Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 A.7.2 Chip Power-up and LVI/LVR Graphical Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . 629 A.7.3 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 Appendix B Emulation Information B.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 B.1.1 PK[2:0] / XADDR[16:14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 Appendix C Package Information C.1 General C.1.1 C.1.2 C.1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 52-Pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 48-Pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 Appendix D Derivative Differences Appendix E Ordering Information 16 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.1 Introduction The MC9S12Q128-Family is a 48/52/80 pin Flash-based MCU family, which delivers the power and flexibility of the 16 Bit core to a whole new range of cost and space sensitive, general purpose Industrial and Automotive network applications All MC9S12Q128-Familymembers feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM (or ROM), up to 4K bytes of RAM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), a 6-channel 16-bit timermodule (TIM), a 4-channel 8-bit pulse width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC). All MC9S12Q128-Family devices feature full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with wake-up capability from stop or wait mode. The MC9S12Q128-Family devices are available in 48-, 52-, and 80-pin QFP packages, with the 80-pin version pin compatible to the HCS12 A, B,, C and D Family derivatives. 1.1.1 • Features 16-bit HCS12 core: — HCS12 CPU – Upward compatible with M68HC11 instruction set – Interrupt stacking and programmer’s model identical to M68HC11 – Instruction queue – Enhanced indexed addressing — MMC (memory map and interface) — INT (interrupt control) — BDM (background debug mode) — DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer) — MEBI (multiplexed expansion bus interface) available only in 80-pin package version Wake-up interrupt inputs: — Up to 12 port bits available for wake up interrupt function with digital filtering • Freescale Semiconductor MC9S12Q128 Rev 1.10 17 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) • • • • • • • Memory options: — 32Kbyte ROM or Flash EEPROM (erasable in 512-byte sectors) 64K, 96K, or 128Kbyte ROM or Flash EEPROM (erasable in 1024-byte sectors) — 1K, 2K, 3K or 4K Byte RAM Analog-to-digital converters: — One 8-channel module with 10-bit resolution — External conversion trigger capability — One 1M bit per second, CAN 2.0 A, B software compatible module — Five receive and three transmit buffers — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit — Four separate interrupt channels for Rx, Tx, error, and wake-up — Low-pass filter wake-up function — Loop-back for self test operation Timer module (TIM): — 6-Channel timer — Each channel configurable as either input capture or output compare — Simple PWM mode — Modulo reset of timer counter — 16-bit pulse accumulator — External event counting — Gated time accumulation PWM module: — Programmable period and duty cycle — 8-bit 4-channel or 16-bit 2-channel — Separate control for each pulse width and duty cycle — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies — Fast emergency shutdown input Serial interfaces: — One asynchronous serial communications interface (SCI) — One synchronous serial peripheral interface (SPI) CRG (clock reset generator module) — Windowed COP watchdog — Real time interrupt — Clock monitor — Pierce or low current Colpitts oscillator — Phase-locked loop clock frequency multiplier — Limp home mode in absence of external clock — Low power 0.5MHz to 16MHz crystal oscillator reference clock :Operating frequency 18 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) • • • — 16MHz equivalent to 8MHz Bus Speed for single chip — 16MHz equivalent to 8MHz Bus Speed in expanded bus modes — Option of 32 MHz equivalent to 16MHz Bus Speed Internal 2.5V regulator: — Supports an input voltage range from 2.97V to 5.5V — Low power mode capability — Includes low voltage reset (LVR) circuitry — Includes low voltage interrupt (LVI) circuitry 48-pin LQFP, 52-pin LQFP, or 80-pin QFP package: — Up to 58 I/O lines with 5V input and drive capability (80-pin package) — Up to 2 dedicated 5V input only lines (IRQ, XIRQ) — 5V 8 A/D converter inputs and 5V I/O Development support: — Single-wire background debug™ mode (BDM) — On-chip hardware breakpoints — Enhanced DBG12 debug features 1.1.2 Modes of Operation User modes (expanded modes are only available in the 80-pin package version). • Normal and emulation operating modes: — Normal single-chip mode — Normal expanded wide mode — Normal expanded narrow mode — Emulation expanded wide mode — Emulation expanded narrow mode • Special operating modes: — Special single-chip mode with active background debug mode — Special test mode (Freescale use only) — Special peripheral mode (Freescale use only) • Low power modes: — Stop mode — Pseudo stop mode — Wait mode Freescale Semiconductor MC9S12Q128 Rev 1.10 19 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.1.3 Block Diagram Figure 1-1. MC9S12Q128-Family Block Diagram VSSR VDDR VDDX VSSX VDDA VSSA VRH VRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VDDA VSSA VRH VRL PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PJ6 PJ7 PS0 PS1 PS2 PS3 PM0 PM1 PM2 PM3 PM4 PM5 ATD Voltage Regulator DDRAD DDRT Keypad Interrupt DDRP DDRJ DDRS DDRM Key Int VDD2 VSS2 VDD1 VSS1 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST/VPP 32K, 64K, 96K, 128K Byte Flash/ROM 1K, 2K, 3K, 4K Byte RAM Single-wire Background Debug12 Module HCS12 CPU Timer Module PLL Clock and Reset Generation Module COP Watchdog Clock Monitor Periodic Interrupt IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PW0 PW1 PW2 PW3 MUX XIRQ IRQ System R/W Integration LSTRB/TAGLO Module ECLK (SIM) MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS DDRE PWM Module PTE PWM Module is only available on the 128K and 96K Versions Multiplexed Address/Data Bus SCI DDRA PTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RXD TXD DDRB PTB MSCAN PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 RXCAN TXCAN MISO SS MOSI SCK ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Multiplexed Wide Bus DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 SPI Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package Internal Logic 2.5V VDD1,2 VSS1,2 I/O Driver 5V VDDX VSSX PLL 2.5V VDDPLL VSSPLL A/D Converter 5V VDDA VSSA VRL is bonded internally to VSSA for 52 and 48 Pin packages Voltage Regulator 5V & I/O VDDR VSSR 20 MC9S12Q128 Rev 1.10 Freescale Semiconductor PTM PTS PTJ PTP PTT PTAD Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.2 1.2.1 Memory Map and Registers Device Memory Map Table 1-1 shows the device register map after reset.The figures on the following pages illustrate the full device memory map. Table 1-1. Device Register Map Overview Address 0x0000–0x0017 0x0018 0x0019 0x001A–0x001B 0x001C–0x001F 0x0020–0x002F 0x0030–0x0033 0x0034–0x003F 0x0040–0x006F 0x0070–0x007F 0x0080–0x009F 0x00A0–0x00C7 0x00D0–0x00D7 0x00E0–0x00FF 0x0100–0x010F 0x0110–0x013F 0x0140–0x017F 0x0180–0x023F 0x0240–0x027F Reserved Voltage regulator (VREG) Device ID register Core (MEMSIZ, IRQ, HPRIO) Core (DBG) Core (PPAGE(1)) Clock and reset generator (CRG) Standard timer module (TIM) Reserved Analog-to-digital converter (ATD) Reserved Reserved Pulse width modulator (PWM) Flash control register Reserved Scalable controller area network (MSCAN) Reserved Port integration module (PIM) Module Core (ports A, B, E, modes, inits, test) Size 24 1 1 2 4 16 4 12 48 16 32 40 8 8 8 32 16 48 64 192 64 0x00C8–0x00CF Serial communications interface (SCI) 0x00D8–0x00DF Serial peripheral interface (SPI) 0x0280–0x03FF Reserved 384 1. External memory paging is not supported on this device (Section 1.7.1, “PPAGE”). Freescale Semiconductor MC9S12Q128 Rev 1.10 21 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) $0000 $0000 $0400 $03FF $0000 1K Register Space Mappable to any 2K Boundary 16K Fixed Flash EEPROM/ROM $3FFF $3000 $3000 $3FFF $4000 $4000 4K Bytes RAM Mappable to any 4K Boundary 16K Fixed Flash EEPROM/ROM $7FFF $8000 $8000 16K Page Window 8 * 16K Flash EEPROM/ROM Pages EXT $BFFF $C000 $C000 16K Fixed Flash EEPROM/ROM $FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 1-2. MCxS12Q128 User Configurable Memory Map 22 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) $0000 $0000 $0400 $03FF $0000 1K Register Space Mappable to any 2K Boundary 16K Fixed Flash EEPROM/ROM $3FFF $3400 $3400 $3FFF $4000 $4000 3K Bytes RAM Mappable to any 4K Boundary 16K Fixed Flash EEPROM/ROM $7FFF $8000 $8000 16K Page Window 6 * 16K Flash EEPROM/ROM Pages EXT $BFFF $C000 $C000 16K Fixed Flash EEPROM/ROM $FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0400 - $0FFF: 3K RAM Flash Erase Sector Size is 1024 Bytes Figure 1-3. MCxS12Q96 User Configurable Memory Map Freescale Semiconductor MC9S12Q128 Rev 1.10 23 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) $0000 $0000 $0400 $03FF $0000 1K Register Space Mappable to any 2K Boundary 16K Fixed Flash EEPROM/ROM $3FFF $3800 $3800 $3FFF $4000 $4000 2K Bytes RAM Mappable to any 4K Boundary 16K Fixed Flash EEPROM/ROM $7FFF $8000 $8000 16K Page Window 4 * 16K Flash EEPROM/ROM Pages $BFFF $C000 $C000 16K Fixed Flash EEPROM/ROM $FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS SPECIAL SINGLE CHIP $FFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes Figure 1-4. MCxS12Q64 User Configurable Memory Map 24 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) $0000 $0000 $0400 $03FF 1K Register Space Mappable to any 2K Boundary $3C00 $3C00 $3FFF 1K Bytes RAM Mappable to any 2K Boundary $4000 $8000 $8000 16K Page Window 2 * 16K Flash EEPROM/ROM Pages $BFFF $C000 $C000 16K Fixed Flash EEPROM/ROM $FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS SPECIAL SINGLE CHIP $FFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0C00 - $0FFF: 1K RAM Flash Erase Sector Size is 512 Bytes Figure 1-5. MCxS12Q32 User Configurable Memory Map Freescale Semiconductor MC9S12Q128 Rev 1.10 25 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.2.2 Detailed Register Map The detailed register map of the MC9S12Q128-Family is listed in address order below. 0x0000–0x000F Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved MEBI Map 1 of 3 (HCS12 Multiplexed External Bus Interface) Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 0 0 0 0 Bit 5 5 5 5 5 0 0 0 0 Bit 4 4 4 4 4 0 0 0 0 Bit 3 3 3 3 3 0 0 0 0 Bit 2 2 2 2 2 0 0 0 0 Bit 1 1 1 1 1 0 0 0 0 Bit 1 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0 0 0 Bit 0 0 0 6 6 0 5 5 PIPOE MODA 0 0 0 0 4 4 NECLK 0 3 3 LSTRE IVIS 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 MODB 0 0 0 0 EMK PUPBE RDPB 0 0 EME PUPAE RDPA ESTR 0 PUPEE RDPE 0 0 26 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0010–0x0014 Address 0x0010 0x0011 0x0012 0x0013 0x0014 Name INITRM INITRG INITEE MISC Reserved MMC Map 1 of 4 (HCS12 Module Mapping Control) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: RAM15 0 Bit 6 RAM14 REG14 EE14 0 0 Bit 5 RAM13 REG13 EE13 0 0 Bit 4 RAM12 REG12 EE12 0 0 Bit 3 RAM11 REG11 EE11 EXSTR1 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 RAMHAL 0 EE15 0 0 EEON ROMON 0 EXSTR0 0 ROMHM 0 0x0015–0x0016 Address 0x0015 0x0016 Name ITCR ITEST INT Map 1 of 2 (HCS12 Interrupt) Bit 7 Read: Write: Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0 INTE INTC INTA 0x0017–0x0017 Address 0x0017 Name Reserved MMC Map 2 of 4 (HCS12 Module Mapping Control) Bit 7 Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0018–0x0018 Address 0x0018 Name Reserved Miscellaneous Peripherals (Device User Guide) Bit 7 Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0019–0x0019 Address $0019 Name VREGCTRL VREG3V3 (Voltage Regulator) Bit 7 Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 LVDS Bit 1 LVIE Bit 0 LVIF Freescale Semiconductor MC9S12Q128 Rev 1.10 27 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x001A–0x001B Address Name Miscellaneous Peripherals (Device User Guide) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001A 0x001B PARTIDH PARTIDL Read: Write: Read: Write: ID15 ID7 ID14 ID6 ID13 ID5 ID12 ID4 ID11 ID3 ID10 ID2 ID9 ID1 ID8 ID0 0x001C–0x001D Address 0x001C 0x001D Name MEMSIZ0 MEMSIZ1 MMC Map 3 of 4 (HCS12 Module Mapping Control, Device User Guide) Bit 7 Read: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reg_sw0 0 rom_sw0 eep_sw1 0 eep_sw0 0 0 0 ram_sw2 0 ram_sw1 pag_sw1 ram_sw0 pag_sw0 Write: Read: rom_sw1 Write: 0x001E–0x001E Address 0x001E Name INTCR MEBI Map 2 of 3 (HCS12 Multiplexed External Bus Interface) Bit 7 Read: Write: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRQE IRQEN 0 0 0 0 0 0 0x001F–0x001F Address 0x001F Name HPRIO INT Map 2 of 2 (HCS12 Interrupt) Bit 7 Read: Write: PSEL7 Bit 6 PSEL6 Bit 5 PSEL5 Bit 4 PSEL4 Bit 3 PSEL3 Bit 2 PSEL2 Bit 1 PSEL1 Bit 0 0 0x0020–0x002F Address 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 Name DBGC1 DBGSC DBGTBH DBGTBL DBGCNT DBGCCX DBG (Including BKP) Map 1 of 1 (HCS12 Debug) Bit 7 Bit 6 Bit 5 TRGSEL CF Bit 13 Bit 5 Bit 4 BEGIN 0 Bit 12 Bit 4 Bit 11 Bit 3 CNT Bit 10 Bit 2 Bit 3 DBGBRK Bit 2 0 Bit 1 Bit 0 Read: DBGEN ARM Write: Read: AF BF Write: Read: Bit 15 Bit 14 Write: Read: Bit 7 Bit 6 Write: Read: TBF 0 Write: Read: PAGSEL Write: CAPMOD TRG Bit 9 Bit 1 Bit 8 Bit 0 EXTCMP 28 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0020–0x002F Address 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F Name DBGCCH DBGCCL DBGC2 BKPCT0 DBGC3 BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L DBG (Including BKP) Map 1 of 1 (HCS12 Debug) (continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 11 3 BKCEN RWAEN Bit 2 10 2 TAGC RWA Bit 1 9 1 RWCEN RWBEN Bit 0 Bit 8 Bit 0 RWC RWB Read: Bit 15 14 13 12 Write: Read: Bit 7 6 5 4 Write: Read: BKABEN FULL BDM TAGAB Write: Read: BKAMBH BKAMBL BKBMBH BKBMBL Write: Read: PAGSEL Write: Read: Bit 15 14 13 12 Write: Read: Bit 7 6 5 4 Write: Read: PAGSEL Write: Read: Bit 15 14 13 12 Write: Read: Bit 7 6 5 4 Write: EXTCMP 11 3 EXTCMP 11 3 10 2 9 1 Bit 8 Bit 0 10 2 9 1 Bit 8 Bit 0 0x0030–0x0031 Address 0x0030 0x0031 Name PPAGE Reserved MMC Map 4 of 4 (HCS12 Module Mapping Control) Bit 7 Read: Write: Read: Write: 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0 0x0032–0x0033 Address Name MEBI Map 3 of 3 (HCS12 Multiplexed External Bus Interface) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address $0032 $0033 Name Reserved Reserved Read: Write: Read: Write: Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 Freescale Semiconductor MC9S12Q128 Rev 1.10 29 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0034–0x003F Address 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP CRG (Clock and Reset Generator) Bit 7 Read: 0 Write: Read: 0 Write: Read: TOUT7 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Read: 0 Write: Read: WCOP Write: Read: RTIBYP Write: Read: TCTL7 Write: Read: 0 Write: Bit 7 Bit 6 0 0 TOUT6 Bit 5 SYN5 0 TOUT5 Bit 4 SYN4 0 TOUT4 Bit 3 SYN3 REFDV3 TOUT3 LOCK 0 Bit 2 SYN2 REFDV2 TOUT2 TRACK 0 Bit 1 SYN1 REFDV1 TOUT1 Bit 0 SYN0 REFDV0 TOUT0 SCM 0 PORF 0 LVRF 0 LOCKIF LOCKIE ROAWAI ACQ RTR4 0 SCMIF SCMIE RTIWAI PCE RTR1 CR1 FCM TCTL1 0 1 PSTP PLLON RTR6 RSBCK COPBYP TCTL6 0 6 SYSWAI AUTO RTR5 0 0 TCTL5 0 5 PLLWAI 0 CWAI PRE RTR2 CR2 0 TCTL2 0 2 COPWAI SCME RTR0 CR0 0 TCTL0 0 Bit 0 RTR3 0 0 TCLT3 0 3 PLLBYP TCTL4 0 4 0x0040-0x006F TIM Address 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 Bit 7 Read: IOS7 Write: 0 Read: Write: FOC7 Read: OC7M7 Write: Read: OC7D7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: TEN Write: Bit 6 IOS6 0 FOC6 Bit 5 IOS5 0 FOC5 Bit 4 IOS4 0 FOC4 Bit 3 IOS3 0 FOC3 Bit 2 IOS2 0 FOC2 Bit 1 Bit 0 0 0 OC7M6 OC7D6 14 6 OC7M5 OC7D5 13 5 OC7M4 OC7D4 12 4 OC7M3 OC7D3 11 3 OC7M2 OC7D2 10 2 9 1 Bit 8 Bit 0 TSWAI TSFRZ TFFCA 0 0 0 0 30 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0040-0x006F TIM Address 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B Name TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 Reserved Reserved Reserved Reserved TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) Bit 7 Read: TOV7 Write: Read: OM7 Write: Read: OM3 Write: Read: EDG7B Write: Read: EDG3B Write: Read: C7I Write: Read: TOI Write: Read: C7F Write: Read: TOF Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Bit 6 TOV6 OL7 OL3 EDG7A EDG3A C6I 0 Bit 5 TOV5 OM6 OM2 EDG6B EDG2B C5I 0 Bit 4 TOV4 OL6 OL2 EDG6A EDG2A C4I 0 Bit 3 TOV3 OM5 Bit 2 TOV2 OL5 Bit 1 Bit 0 OM4 OL4 EDG5B EDG5A EDG4B EDG4A C3I TCRE C3F 0 C2I PR2 C2F 0 C1I PR1 C0I PR0 C6F 0 C5F 0 C4F 0 0 0 14 6 14 6 14 6 14 6 13 5 13 5 13 5 13 5 12 4 12 4 12 4 12 4 11 3 11 3 11 3 11 3 10 2 10 2 10 2 10 2 9 1 9 1 9 1 9 1 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Freescale Semiconductor MC9S12Q128 Rev 1.10 31 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0040-0x006F TIM Address 0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F Name TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACNT (hi) PACNT (lo) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 0 Bit 6 14 6 14 6 PAEN Bit 5 13 5 13 5 PAMOD Bit 4 12 4 12 4 PEDGE Bit 3 11 3 11 3 CLK1 Bit 2 10 2 10 2 CLK0 Bit 1 9 1 9 1 PAOVI Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI 0 0 0 0 0 0 PAOVF 9 PAIF Bit 8 Bit 15 14 13 12 11 10 Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 ep 0x0040-0x006F TIM 32 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0080–0x009F Address 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x0090 0x0091 0x0092 0x0093 0x0094 0x0095 Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 Reserved ATDSTAT1 Reserved ATDDIEN Reserved PORTAD ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATD (Analog-to-Digital Converter 10 Bit 8 Channel) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 ASCIF ADPU 0 AFFC S8C SMP1 DSGN 0 0 0 0 0 CCF6 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 0 CCF5 0 ETRIGLE S2C PRS4 MULT FIFOR 0 0 0 0 CCF4 0 ETRIGP S1C PRS3 0 0 0 0 0 0 CCF3 0 ETRIG FIFO PRS2 CC CC2 0 0 0 0 CCF2 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 0 CCF1 0 FRZ0 PRS0 CA CC0 0 0 SRES8 DJM SCF 0 0 0 0 CCF7 0 SC 0 CCF0 0 Bit 7 0 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 6 0 6 14 Bit6 14 Bit6 14 Bit6 5 0 5 13 0 13 0 13 0 4 0 4 12 0 12 0 12 0 3 0 3 11 0 11 0 11 0 2 0 2 10 0 10 0 10 0 1 0 1 9 0 9 0 9 0 Bit 0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 Freescale Semiconductor MC9S12Q128 Rev 1.10 33 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0080–0x009F Address 0x0096 0x0097 0x0098 0x0099 0x009A 0x009B 0x009C 0x009D 0x009E 0x009F Name ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L ATD (Analog-to-Digital Converter 10 Bit 8 Channel) (continued) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 13 0 13 0 13 0 13 0 13 0 Bit 4 12 0 12 0 12 0 12 0 12 0 Bit 3 11 0 11 0 11 0 11 0 11 0 Bit 2 10 0 10 0 10 0 10 0 10 0 Bit 1 9 0 9 0 9 0 9 0 9 0 Bit 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 0x00A0–0x00C7 Address Name Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00A0– 0x00C7 Reserved Read: Write: 0 0 0 0 0 0 0 0 0x00C8–0x00CF Address 0x00C8 0x00C9 0x00CA 0x00CB 0x00CC Name SCIBDH SCIBDL SCICR1 SCICR2 SCISR1 SCI (Asynchronous Serial Interface) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 SBR12 SBR4 M ILIE IDLE Bit 3 SBR11 SBR3 WAKE TE OR Bit 2 SBR10 SBR2 ILT RE NF Bit 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF SBR7 LOOPS TIE TDRE SBR6 SCISWAI TCIE TC SBR5 RSRC RIE RDRF 34 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x00C8–0x00CF Address 0x00CD 0x00CE 0x00CF Name SCISR2 SCIDRH SCIDRL SCI (Asynchronous Serial Interface) (continued) Bit 7 Read: Write: Read: Write: Read: Write: 0 R8 R7 T7 Bit 6 0 Bit 5 0 0 R5 T5 Bit 4 0 0 R4 T4 Bit 3 0 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0 T8 R6 T6 0x00D0–0x00D7 Address 0x00D0– 0x00D7 Name Reserved Reserved Bit 7 Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x00D8–0x00DF Address 0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE 0x00DF Name SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved Reserved SPI (Serial Peripheral Interface) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: SPIE 0 0 SPIF 0 Bit 6 SPE 0 Bit 5 SPTIE 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 MODFEN BIDIROE SPPR0 MODF 0 0 0 0 SPPR2 0 0 SPPR1 SPTEF 0 SPR2 0 0 Bit7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit0 0 0 Freescale Semiconductor MC9S12Q128 Rev 1.10 35 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x00E0-0x00FF PWM Address 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x00E7 0x00E8 0x00E9 0x00EA 0x00EB 0x00EC 0x00ED 0x00EE 0x00EF 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC PWMSCLA PWMSCLB PWMSCNTA PWMSCNTB PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 Reserved Reserved PWMPER0 PWMPER1 PWMPER2 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 0 0 0 0 0 0 0 0 Bit 6 0 0 0 Bit 5 Bit 4 Bit 3 PWME3 PPOL3 PCLK3 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 PCKB2 0 PCKB1 PCKB0 0 CAE3 CON23 CON01 0 0 PSWAI 0 0 0 0 0 0 0 0 Bit 7 Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 6 6 0 0 6 0 6 0 6 0 6 0 5 5 0 0 5 0 5 0 5 0 5 0 4 4 0 0 4 0 4 0 4 0 4 0 3 3 0 0 3 0 3 0 3 0 3 0 2 2 0 0 2 0 2 0 2 0 2 0 1 1 0 0 1 0 1 0 1 0 1 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 7 Bit 7 Bit 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 Bit 0 Bit 0 Bit 0 36 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x00E0-0x00FF PWM Address 0x00E5 0x00E6 0x00E7 0x00E8 0x00E9 0x00EA 0x00EB 0x00EC 0x00ED Name PWMPER3 Reserved Reserved PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0 Bit 7 Bit 7 Bit 7 Bit 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 0x00EE PWMIF PWMIE 0 PWMRSTR PWMLVL T 0 PWM5IN PWM5INL PWM5ENA 0x00EF 0 0 0 0 0 0 0 0 0x0100–0x010F Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 Name FCLKDIV FSEC FTSTMOD FCNFG FPROT FSTAT FCMD Reserved for Factory Test Flash Control Register Bit 7 Read: FDIVLD Write: Read: KEYEN1 Write: Read: 0 Write: Read: CBEIE Write: Read: FPOPEN Write: Read: CBEIF Write: Read: 0 Write: Read: 0 Write: Bit 6 PRDIV8 KEYEN0 Bit 5 FDIV5 NV5 Bit 4 FDIV4 NV4 Bit 3 FDIV3 NV3 0 0 Bit 2 FDIV2 NV2 0 0 Bit 1 FDIV1 SEC1 0 0 Bit 0 FDIV0 SEC0 0 CCIE NV6 CCIF 0 KEYACC FPHDIS PVIOL CMDB5 0 WRALL 0 0 0 FPHS1 ACCERR 0 0 FPHS0 0 0 0 FPLDIS BLANK CMDB2 0 FPLS1 0 0 0 FPLS0 0 CMDB6 0 CMDB0 0 Freescale Semiconductor MC9S12Q128 Rev 1.10 37 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0100–0x010F Address 0x0108 0x0109 0x010A 0x010B 0x010C 0x010D 0x010E 0x010F Name Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved Reserved Reserved Reserved Flash Control Register (continued) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 0x0110–0x013F Address 0x0110– 0x003F Name Reserved Reserved Bit 7 Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0140–0x017F Address 0x0140 0x0141 0x0142 0x0143 0x0144 0x0145 0x0146 0x0147 Name CANCTL0 CANCTL1 CANBTR0 CANBTR1 CANRFLG CANRIER CANTFLG CANTIER CAN (Scalable Controller Area Network — MSCAN) Bit 7 Read: RXFRM Write: Read: CANE Write: Read: SJW1 Write: Read: SAMP Write: Read: WUPIF Write: Read: WUPIE Write: Read: 0 Write: Read: 0 Write: Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME 0 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 LISTEN BRP4 TSEG20 RSTAT0 BRP3 TSEG13 TSTAT1 BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 RSTATE1 RSTATE0 TSTATE1 TSTATE0 0 0 0 0 0 0 TXE2 TXEIE2 38 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0140–0x017F Address 0x0148 0x0149 0x014A 0x014B 0x014C 0x014D 0x014E 0x014F 0x0150– 0x0153 0x0154– 0x0157 0x0158– 0x015B 0x015C– 0x015F 0x0160– 0x016F 0x0170– 0x017F Name CANTARQ CANTAAK CANTBSEL CANIDAC Reserved Reserved CANRXERR CANTXERR CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 CANIDAR4 CANIDAR7 CANIDMR4 CANIDMR7 CANRXFG CANTXFG CAN (Scalable Controller Area Network — MSCAN) (continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 Write: Read: 0 0 0 0 0 TX2 TX1 TX0 Write: Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 Write: Read: 0 0 0 0 0 0 0 0 Write: Read: 0 0 0 0 0 0 0 0 Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-2 Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-2 Write: Table 1-2. Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address 0xXXX0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15 0xXXX1 ID9 ID8 ID7 0xXXX2 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR 0xXXX3 Freescale Semiconductor MC9S12Q128 Rev 1.10 39 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Table 1-2. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address Name Bit 7 DB7 Bit 6 DB6 Bit 5 DB5 Bit 4 DB4 Bit 3 DB3 DLC3 Bit 2 DB2 DLC2 Bit 1 DB1 DLC1 Bit 0 DB0 DLC0 0xXXX4– CANxRDSR0– Read: 0xXXXB CANxRDSR7 Write: Read: 0xXXXC CANRxDLR Write: Read: 0xXXXD Reserved Write: Read: 0xXXXE CANxRTSRH Write: Read: 0xXXXF CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: 0xxx10 Read: Standard ID Write: Extended ID Read: CANxTIDR1 Write: 0xxx11 Read: Standard ID Write: Extended ID Read: CANxTIDR2 Write: 0xxx12 Read: Standard ID Write: Extended ID Read: CANxTIDR3 Write: 0xxx13 Read: Standard ID Write: 0xxx14– CANxTDSR0– Read: 0xxx1B CANxTDSR7 Write: Read: 0xxx1C CANxTDLR Write: Read: 0xxx1D CONxTTBPR Write: Read: 0xxx1E CANxTTSRH Write: Read: 0xxx1F CANxTTSRL Write: TSR15 TSR7 TSR14 TSR6 TSR13 TSR5 TSR12 TSR4 TSR11 TSR3 TSR10 TSR2 TSR9 TSR1 TSR8 TSR0 ID28 ID10 ID20 ID2 ID14 ID27 ID9 ID19 ID1 ID13 ID26 ID8 ID18 ID0 ID12 ID25 ID7 SRR=1 RTR ID11 ID24 ID6 IDE=1 IDE=0 ID10 ID23 ID5 ID17 ID22 ID4 ID16 ID21 ID3 ID15 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR DB7 DB6 DB5 DB4 DB3 DLC3 DB2 DLC2 PRIO2 TSR10 TSR2 DB1 DLC1 PRIO1 TSR9 TSR1 DB0 DLC0 PRIO0 TSR8 TSR0 PRIO7 TSR15 TSR7 PRIO6 TSR14 TSR6 PRIO5 TSR13 TSR5 PRIO4 TSR12 TSR4 PRIO3 TSR11 TSR3 0x0180–0x023F Address 0x0180– 0x023F Name Reserved Reserved Bit 7 Read: Write: 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 40 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0240–0x027F Address 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 0x0247 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 Name PTT PTIT DDRT RDRT PERT PPST Reserved MODRR PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM PIM (Port Interface Module) (Sheet 1 of 3) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: PTT7 PTIT7 Bit 6 PTT6 PTIT6 Bit 5 PTT5 PTIT5 Bit 4 PTT4 PTIT4 Bit 3 PTT3 PTIT3 Bit 2 PTT2 PTIT2 Bit 1 PTT1 PTIT1 Bit 0 PTT0 PTIT0 DDRT7 RDRT7 PERT7 PPST7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRT7 RDRT6 PERT6 PPST6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRT5 RDRT5 PERT5 PPST5 0 0 0 0 0 0 0 0 0 0 DDRT4 RDRT4 PERT4 PPST4 0 DDRT3 RDRT3 PERT3 PPST3 0 DDRT2 RDRT2 PERT2 PPST2 0 DDRT1 RDRT1 PERT1 PPST1 0 DDRT0 RDRT0 PERT0 PPST0 0 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 0 0 0 0 0 0 0 0 PTS3 PTIS3 PTS2 PTIS2 PTS1 PTIS1 PTS0 PTIS0 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM5 PTIM5 PTM4 PTIM4 PTM3 PTIM3 PTM2 PTIM2 PTM1 PTIM1 PTM0 PTIM0 DDRM5 RDRM5 PERM5 PPSM5 DDRM4 RDRM4 PERM4 PPSM4 DDRM3 RDRM3 PERM3 PPSM3 DDRM2 RDRM2 PERM2 PPSM2 DDRM1 RDRM1 PERM1 PPSM1 DDRM0 RDRM0 PERM0 PPSM0 Freescale Semiconductor MC9S12Q128 Rev 1.10 41 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0240–0x027F Address 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 0x0266 0x0267 0x0268 0x0269 0x026A 0x026B 0x026C Name WOMM Reserved PTP PTIP DDRP RDRP PERP PPSP PIEP PIFP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PTJ PTIJ DDRJ RDRJ PERJ PIM (Port Interface Module) (Sheet 2 of 3) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: 0 0 Bit 6 0 0 Bit 5 WOMM5 0 Bit 4 WOMM4 0 Bit 3 WOMM3 0 Bit 2 WOMM2 0 Bit 1 WOMM1 0 Bit 0 WOMM0 0 PTP7 PTIP7 PTP6 PTIP6 PTP5 PTIP5 PTP4 PTIP4 PTP3 PTIP3 PTP2 PTIP2 PTP1 PTIP1 PTP0 PTIP0 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7 0 0 0 0 0 0 0 0 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 0 0 0 0 0 0 0 0 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTJ7 PTIJ7 PTJ6 PTIJ6 DDRJ7 RDRJ7 PERJ7 DDRJ7 RDRJ6 PERJ6 42 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0240–0x027F Address 0x026D 0x026E 0x026F 0x0270 0x0271 0x0272 0x0273 0x0274 0x0275 0x02760x027F Name PPSJ PIEJ PIFJ PTAD PTIAD DDRAD RDRAD PERAD PPSAD Reserved PIM (Port Interface Module) (Sheet 3 of 3) Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: PPSJ7 PIEJ7 PIFJ7 PTAD7 PTIAD7 Bit 6 PPSJ6 PIEJ6 PIFJ6 PTAD6 PTIAD6 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0 PTAD5 PTIAD5 PTAD4 PTIAD4 PTAD3 PTIAD3 PTAD2 PTIAD2 PTAD1 PTIAD1 PTAD0 PTIJ7 DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 PERAD7 PPSAD7 0 PERAD6 PPSAD6 0 PERAD5 PPSAD5 0 PERAD4 PPSAD4 0 PERAD3 PPSAD3 0 PERAD2 PPSAD2 0 PERAD1 PPSAD1 0 PERAD0 PPSAD0 0 0x0280–0x03FF Address 0x0280– 0x2FF Name Reserved Reserved Space Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 Read: Write: Read: 0x0300 Unimplemented –0x03FF Write: Freescale Semiconductor MC9S12Q128 Rev 1.10 43 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.2.3 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and ox001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID numbers for production mask sets. Table 1-3. Assigned Part ID Numbers MC9S12Q32 MC9S12Q32 MC9S12Q64, MC9S12Q96, MC9S12Q128 MC9S12Q64, MC9S12Q96, MC9S12Q128 MC3S12Q32 MC3S12Q32 MC3S12Q64, MC3S12Q96, MC3S12Q128 MC3S12Q64, MC3S12Q96, MC3S12Q128 2L45J 1M34C 2L09S 0M66G 2L45J 1M34C 2L09S 0M66G $3302 $3311 $3102 $3103 $3302 $3311 $3102 $3103 The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses 0x001C and 0x001D after reset). Table 1-4 shows the read-only values of these registers. Refer to Module Mapping and Control (MMC) Block Guide for further details. Table 1-4. Memory Size Registers Device MC9S12Q32 MC9S12Q64 MC9S12Q96 MC9S12Q128 Register Name MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 MEMSIZ0 MEMSIZ1 Value $00 $80 $01 $C0 $01 $C0 $01 $C0 44 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3 1.3.1 Signal Description Device Pinouts Figure 1-6. Pin Assignments in 80-Pin QFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4 PP5/KWP5 PP7/KWP7 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 PP6/KWP6/ROMCTL PS3 PS2 PS1/TXD PS0/RXD VSSA VRL PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0 PW0/PT0 PW1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MC9S12Q128-Family VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package The MODRR register within the PIM allows for mapping of PWM channels to Port T in the absence of Port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages. Note that when mapping PWM channels to Port T in an 80QFP option, the associated PWM channels are then mapped to both Port P and Port T Freescale Semiconductor ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MC9S12Q128 Rev 1.10 45 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) PM0/RXCAN PM1/TXCAN PP4/KWP4 PP5/KWP5 PM2/MISO PM4/MOSI PM5/SCK 43 52 51 50 49 48 47 46 45 PM3/SS VDDX VSSX 44 42 41 40 PS0/RXD VSSA PS1/TXD PW3/KWP3/PP3 PW0/PT0 PW1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 PA2 PA1 PA0 MC9S12Q128-Family 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 EXTAL XCLKS/PE7 ECLK/PE4 VSSR VDDR RESET VDDPLL VSSPLL XTAL * Signals shown in Bold italic are not available on the 48 Pin Package Figure 1-7. Pin Assignments in 52-Pin LQFP 46 MC9S12Q128 Rev 1.10 TEST/VPP IRQ/PE1 XIRQ/PE0 XFC 26 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) PM0/RXCAN PM1/TXCAN PP5/KWP5 PM4/MOSI PM2/MISO PM5/SCK 40 48 47 46 45 44 43 42 41 39 38 PW0/PT0 PW1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB4 37 PS0/RXD VSSA PS1/TXD PM3/SS VDDX VSSX 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 PA0 XIRQ/PE0 MC9S12Q128-Family 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 XTAL 23 XCLKS/PE7 ECLK/PE4 RESET VDDPLL VSSPLL EXTAL Figure 1-8. Pin Assignments in 48-Pin LQFP Freescale Semiconductor MC9S12Q128 Rev 1.10 TEST/VPP IRQ/PE1 VSSR VDDR XFC 24 47 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.2 Signal Properties Summary Table 1-5. Signal Properties Internal Pull Resistor Description CTRL Reset State NA NA None NA NA Up Up External reset pin PLL loop filter pin Test pin only Background debug, mode pin, tag signal high Port E I/O pin, access, clock select Port E I/O pin and pipe status Port E I/O pin and pipe status Port E I/O pin, bus clock output Port E I/O pin, low strobe, tag signal low Port E I/O pin, R/W in expanded modes Port E input, external interrupt pin Port E input, non-maskable interrupt pin Port A I/O pin and multiplexed address/data Port A I/O pin and multiplexed address/data Port A I/O pin and multiplexed address/data Port B I/O pin and multiplexed address/data Port B I/O pin and multiplexed address/data Port B I/O pin and multiplexed address/data Oscillator pins Pin Name Function 1 EXTAL XTAL RESET XFC TEST BKGD PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PA[7:3] PA[2:1] PA[0] PB[7:5] PB[4] PB[3:0] PAD[7:0] PP[7] PP[6] PP[5] PP[4:3] Pin Name Function 2 — — — — VPP MODC NOACC IPIPE1 IPIPE0 ECLK LSTRB R/W IRQ XIRQ ADDR[15:1/ DATA[15:1] ADDR[10:9/ DATA[10:9] ADDR[8]/ DATA[8] ADDR[7:5]/ DATA[7:5] ADDR[4]/ DATA[4] ADDR[3:0]/ DATA[3:0] AN[7:0] KWP[7] KWP[6] KWP[5] KWP[4:3] Pin Name Function 3 — — — — — TAGHI XCLKS MODB MODA — TAGLO — — — — — — — — — — — ROMCTL PW5 PW[3] Power Domain VDDPLL VDDPLL VDDX VDDPLL VSSX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDA VDDX VDDX VDDX VDDX NA NA None NA NA Up PUCR While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR Mode Dep(1) Mode Dep1 Mode Dep1 Up Up Disabled Disabled Disabled Disabled Disabled Disabled PERAD/P Port AD I/O pins and ATD inputs Disabled PSAD PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP Disabled Disabled Disabled Disabled Port P I/O pins and keypad wake-up Port P I/O pins, keypad wake-up, and ROMON enable. Port P I/O pin, keypad wake-up, PW5 output Port P I/O pin, keypad wake-up, PWM output 48 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Table 1-5. Signal Properties (continued) Internal Pull Resistor Description CTRL PP[2:0] PJ[7:6] PM5 PM4 PM3 PM2 PM1 PM0 PS[3:2] PS1 PS0 PT[7:5] PT[4:0] KWP[2:0] KWJ[7:6] SCK MOSI SS MISO TXCAN RXCAN — TXD RXD IOC[7:5] IOC[4:2] PW[2:0] — — — — — — — — — — — PW[3:0] VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX PERP/ PPSP PERJ/ PPSJ PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST Reset State Disabled Disabled Up Up Up Up Up Up Up Up Up Disabled Port P I/O pins, keypad wake-up, PWM outputs Port J I/O pins and keypad wake-up Port M I/O pin and SPI SCK signal Port M I/O pin and SPI MOSI signal Port M I/O pin and SPI SS signal Port M I/O pin and SPI MISO signal Port M I/O pin and CAN transmit signal Port M I/O pin and CAN receive signal Port S I/O pins Port S I/O pin and SCI transmit signal Port S I/O pin and SCI receive signal Port T I/O pins shared with timer (TIM) Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Power Domain PERT/ Port T I/O pins shared with timer and PWM Disabled PPST 1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For example, in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to S12_MEBI user guide for PEAR register details. 1.3.3 Pin Initialization for 48- and 52-Pin LQFP Bond Out Versions Not Bonded Pins: If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the following pins: (48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2] (52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2] Freescale Semiconductor MC9S12Q128 Rev 1.10 49 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.4 1.3.4.1 Detailed Signal Descriptions EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 1.3.4.2 RESET — External Reset Pin RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing. 1.3.4.3 TEST / VPP — Test Pin This pin is reserved for test and must be tied to VSS in all applications. 1.3.4.4 XFC — PLL Loop Filter Pin Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. XFC R0 MCU CS VDDPLL VDDPLL CP Figure 1-9. PLL Loop Filter Connections 1.3.4.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when the state of this pin is latched to the MODC bit. 50 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.4.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins PA7–PA0 are general purpose input or output pins,. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:1] pins are not available in the 48-pin package version. PA[7:3] are not available in the 52-pin package version. 1.3.4.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins PB7–PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:5] and PB[3:0] pins are not available in the 48-pin nor 52-pin package version. 1.3.4.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7 PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus.The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce oscillator. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL. EXTAL CDC1 MCU C1 Crystal or Ceramic Resonator XTAL C2 VSSPLL 1. Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal. Please contact the crystal manufacturer for crystal DC. Figure 1-10. Colpitts Oscillator Connections (PE7 = 1) EXTAL C1 MCU RS1 XTAL C2 VSSPLL 1. RS can be zero (shorted) when used with higher frequency crystals, refer to manufacturer’s data. RB Crystal or Ceramic Resonator Figure 1-11. Pierce Oscillator Connections (PE7 = 0) Freescale Semiconductor MC9S12Q128 Rev 1.10 51 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) EXTAL CMOS Compatible External Oscillator (VDDPLL Level) MCU XTAL Not Connected Figure 1-12. External Clock Connections (PE7 = 0) 1.3.4.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low. PE[6] is not available in the 48- / 52-pin package versions. 1.3.4.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low. This pin is not available in the 48- / 52-pin package versions. 1.3.4.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output ECLK is the output connection for the internal bus clock. It is used to demultiplex the address and data in expanded modes and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency out of reset. The ECLK pin is initially configured as ECLK output with stretch in all expanded modes. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. All clocks, including the E clock, are halted when the MCU is in stop mode. It is possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. Reference the MISC register (EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. Alternatively PE4 can be used as a general purpose input or output pin. 1.3.4.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB) In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR register. This signal is used in write operations. Therefore external low byte writes will not be possible until this function is enabled. This pin is also used as TAGLO in special expanded modes and is multiplexed with the LSTRB function. This pin is not available in the 48- / 52-pin package versions. 52 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.4.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. This pin is not available in the 48- / 52-pin package versions. 1.3.4.14 PE1 / IRQ — Port E Input Pin [1] / Maskable Interrupt Pin The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code register. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. 1.3.4.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin The XIRQ input provides a means of requesting a non-maskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. 1.3.4.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0] PAD7–PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter. In order to use a PAD pin as a standard input, the corresponding ATDDIEN register bit must be set. These bits are cleared out of reset to configure the PAD pins for A/D operation. When the A/D converter is active in multi-channel mode, port inputs are scanned and converted irrespective of Port AD configuration. Thus Port AD pins that are configured as digital inputs or digital outputs are also converted in the A/D conversion sequence. 1.3.4.17 PP[7] / KWP[7] — Port P I/O Pin [7] PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit stop or wait mode. This pin is not available in the 48- / 52-pin package versions. 1.3.4.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6] PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit stop or wait mode. This pin is not available in the 48- / 52-pin package versions. During MCU expanded modes of operation, this pin is used to enable Freescale Semiconductor MC9S12Q128 Rev 1.10 53 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. • PP6 = 1 in emulation modes equates to ROMON = 0 (ROM space externally mapped) • PP6 = 0 in expanded modes equates to ROMON = 0 (ROM space externally mapped) 1.3.4.19 PP[5:0] / KWP[5:0] / PW[3:0] — Port P I/O Pins [5:0] PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit stop or wait mode. PP[3:0] are also shared with the PWM output signals, PW[3:0].Pins PP[2:0] are only available in the 80pin package version. Pins PP[4:3] are not available in the 48-pin package version. 1.3.4.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] PJ[7:6] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit stop or wait mode. These pins are not available in the 48-pin package version nor in the 52-pin package version. 1.3.4.21 PM5 / SCK — Port M I/O Pin 5 PM5 is a general purpose input or output pin and also the serial clock pin SCK for the serial peripheral interface (SPI). 1.3.4.22 PM4 / MOSI — Port M I/O Pin 4 PM4 is a general purpose input or output pin and also the master output (during master mode) or slave input (during slave mode) pin for the serial peripheral interface (SPI). 1.3.4.23 PM3 / SS — Port M I/O Pin 3 PM3 is a general purpose input or output pin and also the slave select pin SS for the serial peripheral interface (SPI). 1.3.4.24 PM2 / MISO — Port M I/O Pin 2 PM2 is a general purpose input or output pin and also the master input (during master mode) or slave output (during slave mode) pin for the serial peripheral interface (SPI). 1.3.4.25 PM1 / TXCAN — Port M I/O Pin 1 PM1 is a general purpose input or output pin and the transmit pin, TXCAN, of the CAN module if available. 1.3.4.26 PM0 / RXCAN — Port M I/O Pin 0 PM0 is a general purpose input or output pin and the receive pin, RXCAN, of the CAN module if available. 54 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.4.27 PS[3:2] — Port S I/O Pins [3:2] PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48- / 52-pin package versions. 1.3.4.28 PS1 / TXD — Port S I/O Pin 1 PS1 is a general purpose input or output pin and the transmit pin, TXD, of serial communication interface (SCI). 1.3.4.29 PS0 / RXD — Port S I/O Pin 0 PS0 is a general purpose input or output pin and the receive pin, RXD, of serial communication interface (SCI). 1.3.4.30 PT[7:5] / IOC[7:5] — Port T I/O Pins [7:5] PT7–PT5 are general purpose input or output pins. They can also be configured as the timer system input capture or output compare pins IOC7-IOC5. 1.3.4.31 PT[4:0] / IOC[4:2] / PW[3:0]— Port T I/O Pins [4:0] PT4–PT0 are general purpose input or output pins. They can also be configured as the timer system input capture or output compare pins IOC[n] or as the PWM outputs PW[n]. 1.3.5 1.3.5.1 Power Supply Pins VDDX,VSSX — Power and Ground Pins for I/O Drivers External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. 1.3.5.2 VDDR, VSSR — Power and Ground Pins for I/O Drivers and for Internal Voltage Regulator External power and ground for the internal voltage regulator. Connecting VDDR to ground disables the internal voltage regulator. 1.3.5.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR is tied to ground. Freescale Semiconductor MC9S12Q128 Rev 1.10 55 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.5.4 VDDA, VSSA — Power Supply Pins for ATD and VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter. 1.3.5.5 VRH, VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter. 1.3.5.6 VDDPLL, VSSPLL — Power Supply Pins for PLL Provides operating voltage and ground for the oscillator and the phased-locked loop. This allows the supply voltage to the oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. Table 1-6. Power and Ground Connection Summary Mnemonic VDD1, VDD2 VSS1, VSS2 VDDR VSSR VDDX VSSX VDDA VSSA VRH VRL VDDPLL VSSPLL Nominal Voltage (V) 2.5 0 5.0 0 5.0 0 5.0 0 5.0 0 2.5 0 Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltage low for the ATD converter. In the 48 and 52 LQFP packages VRL is bonded to VSSA. Provides operating voltage and ground for the phased-locked loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. External power and ground, supply to pin drivers. Description Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. In the 48 and 52 LQFP packages VDD2 and VSS2 are not available. External power and ground, supply to internal voltage regulator. NOTE All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load. 56 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.4 System Clock Description The clock and reset generator provides the internal clock signals for the core and all peripheral modules. Figure 1-13 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. S12_CORE Core Clock Flash RAM TIM ATD EXTAL PIM SCI CRG Bus Clock Oscillator Clock XTAL VREG TPM SPI MSCAN Not on 9S12GC Figure 1-13. Clock Connections 1.5 Modes of Operation Eight possible modes determine the device operating configuration. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device. 1.5.1 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Freescale Semiconductor MC9S12Q128 Rev 1.10 57 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Table 1-7. Mode Selection BKGD = MODC 0 PE6 = MODB 0 PE5 = MODA 0 PP6 = ROMCTL X 0 1 X 0 1 X 0 1 X 0 1 ROMON Bit 1 1 0 0 1 0 1 0 1 1 0 1 Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 For further explanation on the modes refer to the S12_MEBI block guide. Table 1-8. Clock Selection Based on PE7 PE7 = XCLKS 1 0 Description Colpitts Oscillator selected Pierce Oscillator/external clock selected 1.5.2 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • Protection of the contents of FLASH, • Operation in single-chip mode, • Operation from external memory with internal FLASH disabled. The user must be reminded that part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user’s program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters. 1.5.2.1 Securing the Microcontroller Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. 58 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration. 1.5.2.2 1.5.2.2.1 Operation of the Secured Microcontroller Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 1.5.2.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be blocked. 1.5.2.3 Unsecuring the Microcontroller In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details. Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 1.5.3 Low-Power Modes The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in stop, pseudo stop, and wait mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG). 1.5.3.1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts. 1.5.3.2 Pseudo Stop This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the real time interrupt (RTI) or watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full stop mode, but the wake up time from this mode is significantly shorter. Freescale Semiconductor MC9S12Q128 Rev 1.10 59 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.5.3.3 Wait This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay active. For further power consumption reduction the peripherals can individually turn off their local clocks. 1.5.3.4 Run Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save power. 1.6 Resets and Interrupts Consult the Exception Processing section of the CPU12 Reference Manual for information. 1.6.1 Vectors Table 1-9. Interrupt Vector Locations Table 1-9 lists interrupt sources and vectors in default order of priority. Vector Address Interrupt Source External reset, power on reset, or low voltage reset (see CRG flags register to determine reset source) Clock monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real time Interrupt CCR Mask Local Enable HPRIO Value to Elevate 0xFFFE, 0xFFFF None None — 0xFFFC, 0xFFFD 0xFFFA, 0xFFFB 0xFFF8, 0xFFF9 0xFFF6, 0xFFF7 0xFFF4, 0xFFF5 0xFFF2, 0xFFF3 0xFFF0, 0xFFF1 $FFEE, $FFEF $FFEC, $FFED 0xFFEA, 0xFFEB 0xFFE8, 0xFFE9 0xFFE6, 0xFFE7 0xFFE4, 0xFFE5 0xFFE2, 0xFFE3 0xFFE0, 0xFFE1 0xFFDE, 0xFFDF 0xFFDC, 0xFFDD None None None None X-Bit I bit I bit Reserved Reserved COPCTL (CME, FCME) COP rate select None None None INTCR (IRQEN) CRGINT (RTIE) — — — — — 0x00F2 0x00F0 Standard timer channel 2 Standard timer channel 3 Standard timer channel 4 Standard timer channel 5 Standard timer channel 6 Standard timer channel 7 Standard timer overflow Pulse accumulator A overflow I bit I bit I bit I bit I bit I bit I bit I bit TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TMSK2 (TOI) PACTL (PAOVI) 0x00EA 0x00E8 0x00E6 0x00E4 0x00E2 0x00E0 0x00DE 0x00DC 60 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Table 1-9. Interrupt Vector Locations (continued) Vector Address 0xFFDA, 0xFFDB 0xFFD8, 0xFFD9 0xFFD6, 0xFFD7 0xFFD4, 0xFFD5 0xFFD2, 0xFFD3 0xFFD0, 0xFFD1 0xFFCE, 0xFFCF 0xFFCC, 0xFFCD 0xFFCA, 0xFFCB 0xFFC8, 0xFFC9 0xFFC6, 0xFFC7 0xFFC4, 0xFFC5 0xFFBA to 0xFFC3 0xFFB8, 0xFFB9 0xFFB6, 0xFFB7 0xFFB4, 0xFFB5 0xFFB2, 0xFFB3 0xFFB0, 0xFFB1 0xFF90 to 0xFFAF 0xFF8E, 0xFF8F 0xFF8C, 0xFF8D 0xFF8A, 0xFF8B 0xFF80 to 0xFF89 VREG LVI Port P FLASH CAN wake-up CAN errors CAN receive CAN transmit CRG PLL lock CRG self clock mode Port J ATD Interrupt Source Pulse accumulator input edge SPI SCI CCR Mask I bit I bit I bit Reserved I bit Reserved I bit Reserved Reserved Reserved I bit I bit Reserved I bit I bit I bit I bit I bit Reserved I bit Reserved I bit Reserved CTRL0 (LVIE) 0x008A PIEP (PIEP7-0) 0x008E FCNFG (CCIE, CBEIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) 0x00B8 0x00B6 0x00B4 0x00B2 0x00B0 PLLCR (LOCKIE) PLLCR (SCMIE) 0x00C6 0x00C4 PIEP (PIEP7-6) 0x00CE ATDCTL2 (ASCIE) 0x00D2 Local Enable PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) HPRIO Value to Elevate 0x00DA 0x00D8 0x00D6 Freescale Semiconductor MC9S12Q128 Rev 1.10 61 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.6.2 Resets Resets are a subset of the interrupts featured in Table 1-9. The different sources capable of generating a system reset are summarized in Table 1-10. When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. 1.6.2.1 Reset Summary Table Table 1-10. Reset Summary Reset Power-on Reset External Reset Low Voltage Reset Clock Monitor Reset COP Watchdog Reset Priority 1 1 1 2 3 Source CRG module RESET pin VREG module CRG module CRG module Vector 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFC, 0xFFFD 0xFFFA, 0xFFFB 1.6.2.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports. Refer to Figure 1-2. to Figure 1-5. footnotes for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. NOTE For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 1-5 for affected pins. 1.7 1.7.1 Device Specific Information and Module Dependencies PPAGE External paging is not supported on these devices. In order to access the 16K flash blocks in the address range 0x8000–0xBFFF the PPAGE register must be loaded with the corresponding value for this range. Refer to Table 1-11 for device specific page mapping. For all devices Flash Page 3F is visible in the 0xC000–0xFFFF range if ROMON is set. For all devices (except MC9S12GC16) Page 3E is also visible in the 0x4000–0x7FFF range if ROMHM is cleared and ROMON is set. For all devices apart from MC9S12Q32 Flash Page 3D is visible in the 0x0000–0x3FFF range if ROMON is set... 62 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Table 1-11. Device Specific Flash PAGE Mapping Device MC9S12Q32 PAGE 3E 3F 3C MC9S12Q64 3D 3E 3F 3A 3B MC9S12Q96 3C 3D 3E 3F 38 39 3A MC9S12Q128 3B 3C 3D 3E 3F PAGE Visible with PPAGE Contents $00,$02,$04,$06,$08,$0A,$0C,$0E,$10,$12......$2C,$2E,$30,$32,$34,$36,$38,$3A,$3C,$3E $01,$03,$05,$07,$09,$0B,$0D,$0F,$11,$13.....$2D,$2F,$31,$33,$35,$37,$39,$3B,$3D,$3F $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F $02,$0A,$12,$1A,$22,$2A,$32,$3A $03,$0B,$13,$1B,$23,$2B,$33,$3B $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F $00,$08,$10,$18,$20,$28,$30,$38 $01,$09,$11,$19,$21,$29,$31,$39 $02,$0A,$12,$1A,$22,$2A,$32,$3A $03,$0B,$13,$1B,$23,$2B,$33,$3B $04,$0C,$14,$1C,$24,$2C,$34,$3C $05,$0D,$15,$1D,$25,$2D,$35,$3D $06,$0E,$16,$1E,$26,$2E,$36,$3E $07,$0F,$17,$1F,$27,$2F,$37,$3F 1.7.2 BDM Alternate Clock The BDM section reference to alternate clock is equivalent to the oscillator clock. 1.7.3 Extended Address Range Emulation Implications In order to emulate the devices, external addressing of a 128K memory map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK[2:0]. This package version is for emulation only and not provided as a general production package. The reset state of DDRK is 0x0000, configuring the pins as inputs. The reset state of PUPKE in the PUCR register is “1” enabling the internal Port K pullups. In this reset state the pull-ups provide a defined state and prevent a floating input, thereby preventing unnecessary current flow at the input stage. To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE should not be changed by software. Freescale Semiconductor MC9S12Q128 Rev 1.10 63 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.7.4 VREGEN The VREGEN input mentioned in the VREG section is device internal, connected internally to VDDR. 1.7.5 VDD1, VDD2, VSS1, VSS2 In the 80-pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally. The extra pin pair enables systems using the 80-pin package to employ better supply routing and further decoupling. 1.7.6 Clock Reset Generator And VREG Interface The low voltage reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. NOTE If the voltage regulator is shut down by connecting VDDR to ground then the LVRF flag in the CRG flags register (CRGFLG) is undefined. 1.7.7 Analog-to-Digital Converter In the 48- and 52-pin package versions, the VRL pad is bonded internally to the VSSA pin. 1.7.8 MODRR Register Port T And Port P Mapping The MODRR register within the PIM allows for mapping of PWM channels to port T in the absence of port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages. Note that when mapping PWM channels to port T in an 80QFP option, the associated PWM channels are then mapped to both port P and port T. MODRR[4] must not be set for. 1.7.9 Port AD Dependency On PIM And ATD Registers The port AD pins interface to the PIM module. However, the port pin digital state can be read from either the PORTAD register in the ATD register map or from the PTAD register in the PIM register map. In order to read a digital pin value from PORTAD the corresponding ATDDIEN bit must be set and the corresponding DDRDA bit cleared. If the corresponding ATDDIEN bit is cleared then the pin is configured as an analog input and the PORTAD bit reads back as "1". In order to read a digital pin value from PTAD, the corresponding DDRAD bit must be cleared, to configure the pin as an input. Furthermore in order to use a port AD pin as an analog input, the corresponding DDRAD bit must be cleared to configure the pin as an input 64 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.8 Recommended Printed Circuit Board Layout The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins. • Central point of the ground star should be the VSSR pin. • Use low ohmic low inductance connections between VSS1, VSS2, and VSSR. • VSSPLL must be directly connected to VSSR. • Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for C6, C7, C11, and Q1 as small as possible. • Do not place other signals or supplies underneath area occupied by C6, C7, C5, and Q1 and the connection area to the MCU. • Central power input should be fed in at the VDDA/VSSA pins. Table 1-12. Recommended Component Values Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 R1 R2 R3 / RB R4 / RS Purpose VDD1 filter capacitor VDDR filter capacitor VDDPLL filter capacitor PLL loop filter capacitor See PLL specification chapter PLL loop filter capacitor OSC load capacitor See PLL specification chapter OSC load capacitor VDD2 filter capacitor (80 QFP only) VDDA filter capacitor VDDX filter capacitor DC cutoff capacitor Pierce Mode Select Pullup PLL loop filter resistor PLL loop filter resistor Pierce mode only PLL loop filter resistor Ceramic X7R Ceramic X7R X7R/tantalum 220nF 100nF >=100nF Type Ceramic X7R X7R/tantalum Ceramic X7R Value 220nF, 470nF(1) >=100nF 100nF Colpitts mode only, if recommended by quartz manufacturer Pierce Mode Only See PLL Specification chapter Q1 Quartz — — 1. In 48LQFP and 52LQFP package versions, VDD2 is not available. Thus 470nF must be connected to VDD1. Freescale Semiconductor MC9S12Q128 Rev 1.10 65 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-14. Recommended PCB Layout (48 LQFP) Colpitts Oscillator 66 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-15. Recommended PCB Layout (52 LQFP) Colpitts Oscillator Freescale Semiconductor MC9S12Q128 Rev 1.10 67 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-16. Recommended PCB Layout (80 QFP) Colpitts Oscillator 68 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-17. Recommended PCB Layout for 48 LQFP Pierce Oscillator Freescale Semiconductor MC9S12Q128 Rev 1.10 69 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-18. Recommended PCB Layout for 52 LQFP Pierce Oscillator 70 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-19. Recommended PCB Layout for 80QFP Pierce Oscillator Freescale Semiconductor MC9S12Q128 Rev 1.10 71 Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 72 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.1 Introduction The Port Integration Module establishes the interface between the peripheral modules and the I/O pins for all ports. This chapter covers: • Port A, B, and E related to the core logic and the multiplexed bus interface • Port T connected to the TIM module (PWM module can be routed to port T as well) • Port S connected to the SCI module • Port M associated to the MSCAN and SPI module • Port P connected to the PWM module, external interrupt sources available • Port J pins can be used as external interrupt sources and standard I/O’s The following I/O pin configurations can be selected: • Available on all I/O pins: — Input/output selection — Drive strength reduction — Enable and select of pull resistors • Available on all Port P and Port J pins: — Interrupt enable and status flags The implementation of the Port Integration Module is device dependent. 2.1.1 Features A standard port has the following minimum features: • Input/output selection • 5-V output drive with two selectable drive strength • 5-V digital and analog input • Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt inputs with glitch filtering Freescale Semiconductor MC9S12Q128 Rev 1.10 73 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.1.2 Block Diagram Figure 2-1 is a block diagram of the PIM. Port Integration Module MUX PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PS0 PS1 PS2 PS3 PM0 PM1 PM2 PM3 PM4 PM5 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Interrupt Logic PJ6 PJ7 IRQ Logic Port J PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 AN0 AN1 AN2 AN3 AN4 ATD AN5 AN6 AN7 SCI RXD TXD CAN SPI RXCAN TXCAN MISO MOSI SCK SS A/D PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CORE ADDR8/DATA8 ADDR9/DATA9 ADDR10/DATA10 ADDR11/DATA11 ADDR12/DATA12 ADDR13/DATA13 ADDR14/DATA14 ADDR15/DATA15 Port A Figure 2-1. PIM Block Diagram Note: The MODRR register within the PIM allows for mapping of PWM channels to Port T in the absence of Port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages. Note that when mapping PWM channels to Port T in an 80QFP option, the associated PWM channels are then mapped to both Port P and Port T. 74 MC9S12Q128 Rev 1.10 Freescale Semiconductor Port E ADDR0/DATA0 ADDR1/DATA1 ADDR2/DATA2 ADDR3/DATA3 ADDR4/DATA4 ADDR5/DATA5 ADDR6/DATA6 ADDR7/DATA7 Port B Port M Port S Port P PWM PWM0 PWM1 PWM2 PWM3 Port T TIM BKGD/MODC/TAGHI XIRQ IRQ R/W LSTRB/TAGLO ECLK IPIPE0/MODA IPIPE1/MODB NOACC/XCLKS BKGD PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.2 Signal Description This section lists and describes the signals that do connect off-chip. Table 2-1 shows all pins and their functions that are controlled by the PIM module. If there is more than one function associated to a pin, the priority is indicated by the position in the table from top (highest priority) to down (lowest priority). Table 2-1. Pin Functions and Priorities Port Port T Pin Name PT[7:0] Pin Function PWM[3:0] IOC[7:2] GPIO Port S PS3 PS2 PS1 GPIO GPIO TXD GPIO PS0 RXD GPIO Port M PM5 PM4 PM3 PM2 PM1 PM0 Port P PP[7:0] SCK MOSI SS MISO TXCAN RXCAN PWM[3:0] GPIO[7:0] PP[6] Port J Port AD PJ[7:6] PAD[7:0] ROMON GPIO ATD[7:0] GPIO[7:0] Port A PA[7:0] ADDR[15:8]/ DATA[15:8]/ GPIO ADDR[7:0]/ DATA[7:0]/ GPIO Description PWM outputs (only available if enabled in MODRR register) Standard timer channels General-purpose I/O General-purpose I/O General purpose I/O Serial communication interface transmit pin General-purpose I/O Serial communication interface receive pin General-purpose I/O SPI clock SPI transmit pin SPI slave select line SPI receive pin MSCAN transmit pin MSCAN receive pin PWM outputs General purpose I/O with interrupt ROMON input signal General purpose I/O with interrupt ATD analog inputs General purpose I/O Refer to MEBI Block Guide. Pin Function after Reset GPIO Port B PB[7:0] Refer to MEBI Block Guide. Freescale Semiconductor MC9S12Q128 Rev 1.10 75 Chapter 2 Port Integration Module (PIM9C32) Block Description Table 2-1. Pin Functions and Priorities (continued) Port Pin Name Pin Function NOACC/ XCLKS/ GPIO IPIPE1/ MODB/ GPIO IPIPE0/ MODA/ GPIO ECLK/GPIO LSTRB/ TAGLO/ GPIO R/W/ GPIO IRQ/GPI XIRQ/GPI Description Pin Function after Reset PE7 PE6 PE5 Port E PE4 PE3 Refer to MEBI Block Guide. PE2 PE1 PE0 2.3 Memory Map and Registers This section provides a detailed description of all registers. 2.3.1 Address Module Memory Map Name R W TIM PWM R W R W R W R W R W Bit 7 PTT7 IOC7 PTIT7 6 PTT6 IOC6 PTIT6 5 PTT5 IOC5 PTIT5 4 PTT4 IOC4 PTIT4 3 PTT3 IOC3 PWM3 PTIT3 2 PTT2 IOC2 PWM2 PTIT2 1 PTT1 Bit 0 PTT0 Figure 2-2 shows the register map of the Port Integration Module. 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 PTT PTIT DDRT RDRT PERT PPST PWM1 PTIT1 PWM0 PTIT0 DDRT7 RDRT7 PERT7 PPST7 DDRT6 RDRT6 PERT6 PPST6 DDRT5 RDRT5 PERT5 PPST5 DDRT4 RDRT4 PERT4 PPST4 DDRT3 RDRT3 PERT3 PPST3 DDRT2 RDRT2 PERT2 PPST2 DDRT1 RDRT1 PERT1 PPST1 DDRT0 RDRT0 PERT0 PPST0 = Unimplemented or Reserved Figure 2-2. Quick Reference to PIM Registers (Sheet 1 of 3) 76 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description Address Name R 0x0006 Reserved W R 0x0007 MODRR W R 0x0008 PTS W SCI R 0x0009 PTIS W R 0x000A DDRS W R 0x000B RDRS W R 0x000C PERS W R 0x000D PPSS W R 0x000E WOMS W R 0x000F Reserved W R W 0x0010 PTM MSCAN / SPI R 0x0011 PTIM W R 0x0012 DDRM W R 0x0013 RDRM W R 0x0014 PERM W R 0x0015 PPSM W R 0x0016 WOMM W R 0x0017 Reserved W R 0x0018 PTP W PWM R 0x0019 PTIP W Bit 7 0 0 0 — 0 0 0 0 0 0 0 0 6 0 0 0 — 0 0 0 0 0 0 0 0 5 0 0 0 — 0 0 0 0 0 0 0 4 0 3 0 2 0 1 0 Bit 0 0 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 0 — 0 0 0 0 0 0 0 PTS3 — PTIS3 PTS2 — PTIS2 PTS1 TXD PTIS1 PTS0 RXD PTIS0 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM5 SCK PTIM5 PTM4 MOSI PTIM4 PTM3 SS PTIM3 PTM2 MISO PTIM2 PTM1 TXCAN PTIM1 PTM0 RXCAN PTIM0 — 0 0 0 0 0 0 0 — 0 0 0 0 0 0 0 DDRM5 RDRM5 PERM5 PPSM5 WOMM5 0 DDRM4 RDRM4 PERM4 PPSM4 WOMM4 0 DDRM3 RDRM3 PERM3 PPSM3 WOMM3 0 DDRM2 RDRM2 PERM2 PPSM2 WOMM2 0 DDRM1 RDRM1 PERM1 PPSM1 WOMM1 0 DDRM0 RDRM0 PERM0 PPSM0 WOMM0 0 PTP7 — PTIP7 PTP6 — PTIP6 PTP5 — PTIP5 PTP4 — PTIP4 PTP3 PWM3 PTIP3 PTP2 PWM2 PTIP2 PTP1 PWM1 PTIP1 PTP0 PWM0 PTIP0 = Unimplemented or Reserved Figure 2-2. Quick Reference to PIM Registers (Sheet 2 of 3) Freescale Semiconductor MC9S12Q128 Rev 1.10 77 Chapter 2 Port Integration Module (PIM9C32) Block Description Address 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F Name DDRP RDRP PERP PPSP PIEP PIFP R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7 0 6 DDRP6 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 0 5 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 0 0 0 0 0 0 0 0 0 4 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 0 0 0 0 0 0 0 0 0 3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 0 0 0 0 0 0 0 0 0 2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 0 0 0 0 0 0 0 0 0 1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 0 0 0 0 0 0 0 0 0 Bit 0 DDRP0 RDRP0 PERP0 PPSP0 PIEP0 PIFP0 0 0 0 0 0 0 0 0 0 0x0020– Reserved 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ PTAD PTIAD DDRAD RDRAD PERAD PPSAD PTJ7 PTIJ7 PTJ6 PTIJ6 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 PTAD7 PTIAD7 DDRJ6 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 PTAD6 PTIAD6 PTAD5 PTIAD5 PTAD4 PTIAD4 PTAD3 PTIAD3 PTAD2 PTIAD2 PTAD1 PTIAD1 PTAD0 PTIAD0 DDRAD7 RDRAD7 PERAD7 PPSAD7 0 DDRAD6 RDRAD6 PERAD6 PPSAD6 0 DDRAD5 RDRAD5 PERAD5 PPSAD5 0 DDRAD4 RDRAD4 PERAD4 PPSAD4 0 DDRAD3 RDRAD3 PERAD3 PPSAD3 0 DDRAD2 RDRAD2 PERAD2 PPSAD2 0 DDRAD1 RDRAD1 PERAD1 PPSAD1 0 DDRAD0 RDRAD0 PERAD0 PPSAD0 0 0x0036– Reserved 0x003F = Unimplemented or Reserved Figure 2-2. Quick Reference to PIM Registers (Sheet 3 of 3) 78 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2 Register Descriptions Table 2-2 summarizes the effect on the various configuration bits — data direction (DDR), input/output level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active. Table 2-2. Pin Configuration Summary DDR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 IO X X X X X X X 0 1 0 1 0 1 0 RDR X X X X X X X 0 0 1 1 0 0 1 PE 0 1 1 0 0 1 1 X X X X X X X PS X 0 1 0 1 0 1 X X X X 0 1 0 1 IE(1) 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Function Input Input Input Input Input Input Input Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1 Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1 Pull Device Disabled Pull up Pull down Disabled Disabled Pull up Pull down Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Interrupt Disabled Disabled Disabled Falling edge Rising edge Falling edge rising edge Disabled Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge 1 1 1 X 1. Applicable only on ports P and J. NOTE All bits of all registers in this module are completely synchronous to internal clocks during a register read. Freescale Semiconductor MC9S12Q128 Rev 1.10 79 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1 2.3.2.1.1 Port T Registers Port T I/O Register (PTT) Module Base + 0x0000 7 6 5 4 3 2 1 0 R PTT7 W TIM PWM Reset 0 0 0 0 IOC7 IOC6 IOC5 IOC4 IOC3 PWM3 0 IOC2 PWM2 0 PWM1 0 PWM0 0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 = Unimplemented or Reserved Figure 2-3. Port T I/O Register (PTT) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. If a TIM-channel is defined as output, the related port T is assigned to IOC function. In addition to the possible timer functionality of port T pins PWM channels can be routed to port T. For this the Module Routing Register (MODRR) needs to be configured. Table 2-3. Port T[4:0] Pin Functionality Configurations(1) MODRR[x] 0 0 0 0 1 1 1 PWME[x] 0 0 1 1 0 0 1 TIMEN[x] (2) Port T[x] Output General Purpose I/O Timer General Purpose I/O Timer General Purpose I/O Timer PWM 0 1 0 1 0 1 0 1 1 1 PWM 1. All fields in the that are not shaded are standard use cases. 2. TIMEN[x] means that the timer is enabled (TSCR1[7]), the related channel is configured for output compare function (TIOS[x] or special output on a timer overflow event — configurable in TTOV[x]) and the timer output is routed to the port pin (TCTL1/TCTL2). 80 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1.2 Port T Input Register (PTIT) Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 — — — — — — — — = Unimplemented or Reserved Figure 2-4. Port T Input Register (PTIT) Read: Anytime. Write: Never, writes to this register have no effect. Table 2-4. PTIT Field Descriptions Field 7–0 PTIT[7:0] Description Port T Input Register — This register always reads back the status of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. 2.3.2.1.3 Port T Data Direction Register (DDRT) Module Base + 0x0002 7 6 5 4 3 2 1 0 R DDRT7 W Reset 0 0 0 0 0 0 0 0 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 Figure 2-5. Port T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. Table 2-5. DDRT Field Descriptions Field 7–0 DDRT[7:0] Description Data Direction Port T — This register configures each port T pin as either input or output. The standard TIM / PWM modules forces the I/O state to be an output for each standard TIM / PWM module port associated with an enabled output compare. In these cases the data direction bits will not change. The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. The timer input capture always monitors the state of the pin. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register. Freescale Semiconductor MC9S12Q128 Rev 1.10 81 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1.4 Port T Reduced Drive Register (RDRT) Module Base + 0x0003 7 6 5 4 3 2 1 0 R RDRT7 W Reset 0 0 0 0 0 0 0 0 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 Figure 2-6. Port T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. Table 2-6. RDRT Field Descriptions Field 7–0 RDRT[7:0] Description Reduced Drive Port T — This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 2.3.2.1.5 Port T Pull Device Enable Register (PERT) Module Base + 0x0004 7 6 5 4 3 2 1 0 R PERT7 W Reset 0 0 0 0 0 0 0 0 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 Figure 2-7. Port T Pull Device Enable Register (PERT) Read: Anytime. Write: Anytime. Table 2-7. PERT Field Descriptions Field 7–0 PERT[7:0] Description Pull Device Enable — This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 82 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1.6 Port T Polarity Select Register (PTTST) Module Base + 0x0005 7 6 5 4 3 2 1 0 R PPST7 W Reset 0 0 0 0 0 0 0 0 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 Figure 2-8. Port T Polarity Select Register (PPST) Read: Anytime. Write: Anytime. Table 2-8. PPST Field Descriptions Field 7–0 PPST[7:0] Description Pull Select Port T — This register selects whether a pull-down or a pull-up device is connected to the pin. 0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 2.3.2.1.7 Port T Module Routing Register (MODRR) Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset 0 0 0 MODRR4 MODRR3 0 MODRR2 0 MODRR1 0 MODRR0 0 — — — 0 = Unimplemented or Reserved Figure 2-9. Port T Module Routing Register (MODRR) Read: Anytime. Write: Anytime. NOTE MODRR[4] must be kept clear on devices featuring a 4 channel PWM. Table 2-9. MODRR Field Descriptions Field Description 4–0 Module Routing Register Port T — This register selects the module connected to port T. MODRR[4:0] 0 Associated pin is connected to TIM module 1 Associated pin is connected to PWM module Freescale Semiconductor MC9S12Q128 Rev 1.10 83 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2 2.3.2.2.1 Port S Registers Port S I/O Register (PTS) Module Base + 0x0008 7 6 5 4 3 2 1 0 R W SCI Reset 0 0 0 0 PTS3 PTS2 — 0 PTS1 TXD 0 PTS0 RXD 0 — 0 — 0 — 0 — 0 — 0 = Unimplemented or Reserved Figure 2-10. Port S I/O Register (PTS) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. The SCI port associated with transmit pin 1 is configured as output if the transmitter is enabled and the SCI pin associated with receive pin 0 is configured as input if the receiver is enabled. Please refer to SCI Block User Guide for details. 2.3.2.2.2 Port S Input Register (PTIS) Module Base + 0x0009 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 PTIS3 PTIS2 PTIS1 PTIS0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-11. Port S Input Register (PTIS) Read: Anytime. Write: Never, writes to this register have no effect. Table 2-10. PTIS Field Descriptions Field 3–0 PTIS[3:0] Description Port S Input Register — This register always reads back the status of the associated pins. This also can be used to detect overload or short circuit conditions on output pins. 84 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2.3 Port S Data Direction Register (DDRS) Module Base + 0x000A 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 DDRS3 DDRS2 0 DDRS1 0 DDRS0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-12. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. Table 2-11. DDRS Field Descriptions Field 3–0 DDRS[3:0] Description Direction Register Port S — This register configures each port S pin as either input or output. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if the SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register. Freescale Semiconductor MC9S12Q128 Rev 1.10 85 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2.4 Port S Reduced Drive Register (RDRS) Module Base + 0x000B 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 RDRS3 RDRS2 0 RDRS1 0 RDRS0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-13. Port S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. Table 2-12. RDRS Field Descriptions Field 3–0 RDRS[3:0] Description Reduced Drive Port S — This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 2.3.2.2.5 Port S Pull Device Enable Register (PERS) Module Base + 0x000C 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 PERS3 PERS2 1 PERS1 1 PERS0 1 0 0 0 0 1 = Unimplemented or Reserved Figure 2-14. Port S Pull Device Enable Register (PERS) Read: Anytime. Write: Anytime. Table 2-13. PERS Field Descriptions Field 3–0 PERS[3:0] Description Reduced Drive Port S — This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as output in wired-or (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 86 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2.6 Port S Polarity Select Register (PPSS) Module Base + 0x000D 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 PPSS3 PPSS2 0 PPSS1 0 PPSS0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-15. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. Table 2-14. PPSS Field Descriptions Field 3–0 PPSS[3:0] Description Pull Select Port S — This register selects whether a pull-down or a pull-up device is connected to the pin. 0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input or as wired-or output. 1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input. 2.3.2.2.7 Port S Wired-OR Mode Register (WOMS) Module Base + 0x000E 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 WOMS3 WOMS2 0 WOMS1 0 WOMS0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-16. Port S Wired-Or Mode Register (WOMS) Read: Anytime. Write: Anytime. Table 2-15. WOMS Field Descriptions Field Description 3–0 Wired-OR Mode Port S — This register configures the output pins as wired-or. If enabled the output is driven WOMS[3:0] active low only (open-drain). A logic level of “1” is not driven. This bit has no influence on pins used as inputs. 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Freescale Semiconductor MC9S12Q128 Rev 1.10 87 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3 2.3.2.3.1 Port M Registers Port M I/O Register (PTM) Module Base + 0x0010 7 6 5 4 3 2 1 0 R W MSCAN/ SPI Reset 0 0 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 — 0 — 0 SCK 0 MOSI 0 SS 0 MISO 0 TXCAN 0 RXCAN 0 = Unimplemented or Reserved Figure 2-17. Port M I/O Register (PTM) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. The SPI pin configurations (PM[5:2]) is determined by several status bits in the SPI module. Please refer to the SPI Block User Guide for details. 2.3.2.3.2 Port M Input Register (PTIM) Module Base + 0x0011 7 6 5 4 3 2 1 0 R W Reset 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 — — — — — — — — = Unimplemented or Reserved Figure 2-18. Port M Input Register (PTIM) Read: Anytime. Write: Never, writes to this register have no effect. Table 2-16. PTIM Field Descriptions Field 5–0 PTIM[5:0] Description Port M Input Register — This register always reads back the status of the associated pins. This also can be used to detect overload or short circuit conditions on output pins. 88 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3.3 Port M Data Direction Register (DDRM) Module Base + 0x0012 7 6 5 4 3 2 1 0 R W Reset 0 0 DDRM5 DDRM4 0 DDRM3 0 DDRM2 0 DDRM1 0 DDRM0 0 — — 0 = Unimplemented or Reserved Figure 2-19. Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. Table 2-17. DDRM Field Descriptions Field 5–0 DDRM[5:0] Description Data Direction Port M — This register configures each port S pin as either input or output If SPI or MSCAN is enabled, the SPI and MSCAN modules determines the pin directions. Please refer to the SPI and MSCAN Block User Guides for details. If the associated SCI or MSCAN transmit or receive channels are enabled, this register has no effect on the pins. The pins are forced to be outputs if the SCI or MSCAN transmit channels are enabled, they are forced to be inputs if the SCI or MSCAN receive channels are enabled. The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. Freescale Semiconductor MC9S12Q128 Rev 1.10 89 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3.4 Port M Reduced Drive Register (RDRM) Module Base + 0x0013 7 6 5 4 3 2 1 0 R W Reset 0 0 RDRM5 RDRM4 0 RDRM3 0 RDRM2 0 RDRM1 0 RDRM0 0 0 0 0 = Unimplemented or Reserved Figure 2-20. Port M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. Table 2-18. RDRM Field Descriptions Field 5–0 RDRM[5:0] Description Reduced Drive Port M — This register configures the drive strength of each port M output pin as either full or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 2.3.2.3.5 Port M Pull Device Enable Register (PERM) Module Base + 0x0014 7 6 5 4 3 2 1 0 R W Reset 0 0 PERM5 PERM4 1 PERM3 1 PERM2 1 PERM1 1 PERM0 1 0 0 1 = Unimplemented or Reserved Figure 2-21. Port M Pull Device Enable Register (PERM) Read: Anytime. Write: Anytime. Table 2-19. PERM Field Descriptions Field 5–0 PERM[5:0] Description Pull Device Enable Port M — This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as output in wired-or (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 90 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3.6 Port M Polarity Select Register (PPSM) Module Base + 0x0015 7 6 5 4 3 2 1 0 R W Reset 0 0 PPSM5 PPSM4 0 PPSM3 0 PPSM2 0 PPSM1 0 PPSM0 0 0 0 0 = Unimplemented or Reserved Figure 2-22. Port M Polarity Select Register (PPSM) Read: Anytime. Write: Anytime. Table 2-20. PPSM Field Descriptions Field 5–0 PPSM[5:0] Description Polarity Select Port M — This register selects whether a pull-down or a pull-up device is connected to the pin. 0 A pull-up device is connected to the associated port M pin, if enabled by the associated bit in register PERM and if the port is used as input or as wired-or output. 1 A pull-down device is connected to the associated port M pin, if enabled by the associated bit in register PERM and if the port is used as input. 2.3.2.3.7 Port M Wired-OR Mode Register (WOMM) Module Base + 0x0016 7 6 5 4 3 2 1 0 R W Reset 0 0 WOMM5 WOMM4 0 WOMM3 0 WOMM2 0 WOMM1 0 WOMM0 0 0 0 0 = Unimplemented or Reserved Figure 2-23. Port M Wired-OR Mode Register (WOMM) Read: Anytime. Write: Anytime. Table 2-21. WOMM Field Descriptions Field Description 5–0 Wired-OR Mode Port M — This register configures the output pins as wired-or. If enabled the output is driven WOMM[5:0] active low only (open-drain). A logic level of “1” is not driven. This bit has no influence on pins used as inputs. 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Freescale Semiconductor MC9S12Q128 Rev 1.10 91 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4 2.3.2.4.1 Port P Registers Port P I/O Register (PTP) Module Base + 0x0018 7 6 5 4 3 2 1 0 R PTP7 W PWM Reset — 0 — 0 — 0 — 0 PWM3 0 PWM2 0 PWM1 0 PWM0 0 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 Figure 2-24. Port P I/O Register (PTP) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 2.3.2.4.2 Port P Input Register (PTIP) Module Base + 0x0019 7 6 5 4 3 2 1 0 R W Reset PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 — — — — — — — — = Unimplemented or Reserved Figure 2-25. Port P Input Register (PTIP) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be also used to detect overload or short circuit conditions on output pins. 92 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4.3 Port P Data Direction Register (DDRP) Module Base + 0x001A 7 6 5 4 3 2 1 0 R DDRP7 W Reset 0 0 0 0 0 0 0 0 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 Figure 2-26. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. Table 2-22. DDRP Field Descriptions Field 7–0 DDRP[7:0] Description Data Direction Port P — This register configures each port P pin as either input or output. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register. 2.3.2.4.4 Port P Reduced Drive Register (RDRP) Module Base + 0x001B 7 6 5 4 3 2 1 0 R RDRP7 W Reset 0 0 0 0 0 0 0 0 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 Figure 2-27. Port P Reduced Drive Register (RDRP) Read: Anytime. Write: Anytime. Table 2-23. RDRP Field Descriptions Field 7–0 RDRP[7:0] Description Reduced Drive Port P — This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor MC9S12Q128 Rev 1.10 93 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4.5 Port P Pull Device Enable Register (PERP) Module Base + 0x001C 7 6 5 4 3 2 1 0 R PERP7 W Reset 0 0 0 0 0 0 0 0 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 Figure 2-28. Port P Pull Device Enable Register (PERP) Read: Anytime. Write: Anytime. Table 2-24. PERP Field Descriptions Field 7–0 PERP[7:0] Description Pull Device Enable Port P — This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 2.3.2.4.6 Port P Polarity Select Register (PPSP) Module Base + 0x001D 7 6 5 4 3 2 1 0 R PPSP7 W Reset 0 0 0 0 0 0 0 0 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 Figure 2-29. Port P Polarity Select Register (PPSP) Read: Anytime. Write: Anytime. Table 2-25. PPSP Field Descriptions Field 7–0 PPSP[7:0] Description Pull Select Port P — This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 94 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4.7 Port P Interrupt Enable Register (PIEP) Module Base + 0x001E 7 6 5 4 3 2 1 0 R PIEP7 W Reset 0 0 0 0 0 0 0 0 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 Figure 2-30. Port P Interrupt Enable Register (PIEP) Read: Anytime. Write: Anytime. Table 2-26. PIEP Field Descriptions Field 7–0 PIEP[7:0] Description Pull Select Port P — This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port P. 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 2.3.2.4.8 Port P Interrupt Flag Register (PIFP) Module Base + 0x001F 7 6 5 4 3 2 1 0 R PIFP7 W Reset 0 0 0 0 0 0 0 0 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 Figure 2-31. Port P Interrupt Flag Register (PIFP) Read: Anytime. Write: Anytime. Table 2-27. PIFP Field Descriptions Field 7–0 PIFP[7:0] Description Interrupt Flags Port P — Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register. To clear this flag, write a “1” to the corresponding bit in the PIFP register. Writing a “0” has no effect. 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag. Freescale Semiconductor MC9S12Q128 Rev 1.10 95 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5 2.3.2.5.1 Port J Registers Port J I/O Register (PTJ) Module Base + 0x0028 7 6 5 4 3 2 1 0 R PTJ7 W Reset 0 0 PTJ6 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-32. Port J I/O Register (PTJ) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 2.3.2.5.2 Port J Input Register (PTIJ) Module Base + 0x0029 7 6 5 4 3 2 1 0 R W Reset PTIJ7 PTIJ6 0 0 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-33. Port J Input Register (PTIJ) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. 96 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5.3 Port J Data Direction Register (DDRJ) Module Base + 0x002A 7 6 5 4 3 2 1 0 R DDRJ7 W Reset 0 0 DDRJ6 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-34. Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. Table 2-28. DDRJ Field Descriptions Field 7–6 DDRJ[7:6] Description Data Direction Port J — This register configures port pins J[7:6] as either input or output. DDRJ[7:6] — Data Direction Port J 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTJ or PTIJ registers, when changing the DDRJ register. 2.3.2.5.4 Port J Reduced Drive Register (RDRJ) Module Base + 0x002B 7 6 5 4 3 2 1 0 R RDRJ7 W Reset 0 0 RDRJ6 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-35. Port J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. Table 2-29. RDRJ Field Descriptions Field 7–6 RDRJ[7:6] Description Reduced Drive Port J — This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor MC9S12Q128 Rev 1.10 97 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5.5 Port J Pull Device Enable Register (PERJ) Module Base + 0x002C 7 6 5 4 3 2 1 0 R PERJ7 W Reset 0 0 PERJ6 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-36. Port J Pull Device Enable Register (PERJ) Read: Anytime. Write: Anytime. Table 2-30. PERJ Field Descriptions Field 7–6 PERJ[7:6] Description Reduced Drive Port J — This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as wired-or output. This bit has no effect if the port is used as push-pull output. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 2.3.2.5.6 Port J Polarity Select Register (PPSJ) Module Base + 0x002D 7 6 5 4 3 2 1 0 R PPSJ7 W Reset 0 0 PPSJ6 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-37. Port J Polarity Select Register (PPSJ) Read: Anytime. Write: Anytime. Table 2-31. PPSJ Field Descriptions Field 7–6 PPSJ[7:6] Description Reduced Drive Port J — This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as general purpose input. 1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. 98 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5.7 Port J Interrupt Enable Register (PIEJ) Module Base + 0x002E 7 6 5 4 3 2 1 0 R PIEJ7 W Reset 0 0 PIEJ6 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-38. Port J Interrupt Enable Register (PIEJ) Read: Anytime. Write: Anytime. Table 2-32. PIEJ Field Descriptions Field 7–6 PIEJ[7:6] Description Interrupt Enable Port J — This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port J. 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 2.3.2.5.8 Port J Interrupt Flag Register (PIFJ) Module Base + 0x002F 7 6 5 4 3 2 1 0 R PIFJ7 W Reset 0 0 PIFJ6 0 0 0 0 0 0 — — — — — — = Unimplemented or Reserved Figure 2-39. Port J Interrupt Flag Register (PIFJ) Read: Anytime. Write: Anytime. Table 2-33. PIFJ Field Descriptions Field 7–6 PIFJ[7:6] Description Interrupt Flags Port J — Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSJ register. To clear this flag, write “1” to the corresponding bit in the PIFJ register. Writing a “0” has no effect. 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag. Freescale Semiconductor MC9S12Q128 Rev 1.10 99 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6 2.3.2.6.1 Port AD Registers Port AD I/O Register (PTAD) Module Base + 0x0030 7 6 5 4 3 2 1 0 R PTAD7 W Reset 0 0 0 0 0 0 0 0 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 Figure 2-40. Port AD I/O Register (PTAD) Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 2.3.2.6.2 Port AD Input Register (PTIAD) Module Base + 0x0031 7 6 5 4 3 2 1 0 R W Reset PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIAD0 — — — — — — — — = Unimplemented or Reserved Figure 2-41. Port AD Input Register (PTIAD) Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. 100 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6.3 Port AD Data Direction Register (DDRAD) Module Base + 0x0032 7 6 5 4 3 2 1 0 R DDRAD7 W Reset 0 0 0 0 0 0 0 0 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 Figure 2-42. Port AD Data Direction Register (DDRAD) Read: Anytime. Write: Anytime. Table 2-34. DDRAD Field Descriptions Field Description 7–0 Data Direction Port AD — This register configures port pins AD[7:0] as either input or output. DDRAD[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTAD or PTIAD registers, when changing the DDRAD register. 2.3.2.6.4 Port AD Reduced Drive Register (RDRAD) Module Base + 0x0033 7 6 5 4 3 2 1 0 R RDRAD7 W Reset 0 0 0 0 0 0 0 0 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 Figure 2-43. Port AD Reduced Drive Register (RDRAD) Read: Anytime. Write: Anytime. Table 2-35. RDRAD Field Descriptions Field Description 7–0 Reduced Drive Port AD — This register configures the drive strength of each port AD output pin as either full RDRAD[7:0] or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor MC9S12Q128 Rev 1.10 101 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6.5 Port AD Pull Device Enable Register (PERAD) Module Base + 0x0034 7 6 5 4 3 2 1 0 R PERAD7 W Reset 0 0 0 0 0 0 0 0 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 Figure 2-44. Port AD Pull Device Enable Register (PERAD) Read: Anytime. Write: Anytime. Table 2-36. PERAD Field Descriptions Field Description 7–0 Pull Device Enable Port AD — This register configures whether a pull-up or a pull-down device is activated, if PERAD[7:0] the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. It is not possible to enable pull devices when a associated ATD channel is enabled simultaneously. 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 2.3.2.6.6 Port AD Polarity Select Register (PPSAD) Module Base + 0x0035 7 6 5 4 3 2 1 0 R PPSAD7 W Reset 0 0 0 0 0 0 0 0 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 Figure 2-45. Port AD Polarity Select Register (PPSAD) Read: Anytime. Write: Anytime. Table 2-37. PPSAD Field Descriptions Field Description 7–0 Pull Select Port AD — This register selects whether a pull-down or a pull-up device is connected to the pin. PPSAD[7:0] 0 A pull-up device is connected to the associated port AD pin, if enabled by the associated bit in register PERAD and if the port is used as input. 1 A pull-down device is connected to the associated port AD pin, if enabled by the associated bit in register PERAD and if the port is used as input. 102 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.4 Functional Description Each pin can act as general purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a pushpull output. 2.4.1 2.4.1.1 Registers I/O Register This register holds the value driven out to the pin if the port is used as a general purpose I/O. Writing to this register has only an effect on the pin if the port is used as general purpose output. When reading this address, the value of the pins are returned if the data direction register bits are set to 0. If the data direction register bits are set to 1, the contents of the I/O register is returned. This is independent of any other configuration (Figure 2-46). PTI 0 1 PAD PT 0 1 0 1 Data Out DDR Module Output Enable Module Enable Figure 2-46. Illustration of I/O Pin Functionality 2.4.1.2 Input Register This is a read-only register and always returns the value of the pin (Figure 2-46). 2.4.1.3 Data Direction Register This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-46). Freescale Semiconductor MC9S12Q128 Rev 1.10 103 Chapter 2 Port Integration Module (PIM9C32) Block Description 2.4.1.4 Reduced Drive Register If the port is used as an output the register allows the configuration of the drive strength. 2.4.1.5 Pull Device Enable Register This register turns on a pull-up or pull-down device. It becomes only active if the pin is used as an input or as a wired-or output. 2.4.1.6 Polarity Select Register This register selects either a pull-up or pull-down device if enabled. It becomes only active if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-OR output. 2.4.2 2.4.2.1 Port Descriptions Port T This port is associated with the Standard Capture Timer. PWM output channels can be rerouted from port P to port pins T. In all modes, port T pins can be used for either general-purpose I/O, Standard Capture Timer I/O or as PWM channels module, if so configured by MODRR. During reset, port T pins are configured as high-impedance inputs. 2.4.2.2 Port S This port is associated with the serial SCI module. Port S pins PS[3:0] can be used either for generalpurpose I/O, or with the SCI subsystem. During reset, port S pins are configured as inputs with pull-up. 2.4.2.3 Port M This port is associated with the MSCAN and SPI module. Port M pins PM[5:0] can be used either for general-purpose I/O, with the MSCAN or SPI subsystems. During reset, port M pins are configured as inputs with pull-up. 2.4.2.4 Port AD This port is associated with the ATD module. Port AD pins can be used either for general-purpose I/O, or for the ATD subsystem. There are 2 data port registers associated with the Port AD: PTAD[7:0], located in the PIM and PORTAD[7:0] located in the ATD. To use PTAD[n] as a standard input port, the corresponding DDRD[n] must be cleared. To use PTAD[n] as a standard output port, the corresponding DDRD[n] must be set NOTE: To use PORTAD[n], located in the ATD as an input port register, DDRD[n] must be cleared and ATDDIEN[n] must be set. Please refer to ATD Block Guide for details. 104 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 2 Port Integration Module (PIM9C32) Block Description 2.4.2.5 Port P The PWM module is connected to port P. Port P pins can be used as PWM outputs. Further the Keypad Wake-Up function is implemented on pins PP[7:0]. During reset, port P pins are configured as highimpedance inputs. Port P offers 8 general purpose I/O pins with edge triggered interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. All 8 bits/pins share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in STOP or WAIT mode. A digital filter on each pin prevents pulses (Figure 2-48) shorter than a specified time from generating an interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-47 and Table 2-38). Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set tpign tpval Figure 2-47. Interrupt Glitch Filter on Port P and J (PPS = 0) Table 2-38. Pulse Detection Criteria STOP Mode Pulse Value Unit Value Unit Bus clocks tpign = 10 µs 1. These values include the spread of the oscillator frequency over temperature, voltage and process. STOP(1) Mode tpulse Figure 2-48. Pulse Illustration Freescale Semiconductor MC9S12Q128 Rev 1.10 105 Chapter 2 Port Integration Module (PIM9C32) Block Description A valid edge on input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by a single RC oscillator in the Port Integration Module. To maximize current saving the RC oscillator runs only if the following condition is true on any pin: Sample count B • Comparator C provides an additional tag or force breakpoint when capture mode is not configured in LOOP1 mode. • Sixty-four word (16 bits wide) trace buffer for storing change-of-flow information, event only data and other bus information. — Source address of taken conditional branches (long, short, bit-conditional, and loop constructs) — Destination address of indexed JMP, JSR, and CALL instruction. — Destination address of RTI, RTS, and RTC instructions — Vector address of interrupts, except for SWI and BDM vectors 192 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description — — — — Data associated with event B trigger modes Detail report mode stores address and data for all cycles except program (P) and free (f) cycles Current instruction address when in profiling mode BGND is not considered a change-of-flow (cof) by the debugger 7.1.2 Modes of Operation There are two main modes of operation: breakpoint mode and debug mode. Each one is mutually exclusive of the other and selected via a software programmable control bit. In the breakpoint mode there are two sub-modes of operation: • Dual address mode, where a match on either of two addresses will cause the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). • Full breakpoint mode, where a match on address and data will cause the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). In debug mode, there are several sub-modes of operation. • Trigger modes There are many ways to create a logical trigger. The trigger can be used to capture bus information either starting from the trigger or ending at the trigger. Types of triggers (A and B are registers): — A only — A or B — A then B — Event only B (data capture) — A then event only B (data capture) — A and B, full mode — A and not B, full mode — Inside range — Outside range • Capture modes There are several capture modes. These determine which bus information is saved and which is ignored. — Normal: save change-of-flow program fetches — Loop1: save change-of-flow program fetches, ignoring duplicates — Detail: save all bus operations except program and free cycles — Profile: poll target from external device 7.1.3 Block Diagram Figure 7-1 is a block diagram of this module in breakpoint mode. Figure 7-2 is a block diagram of this module in debug mode. Freescale Semiconductor MC9S12Q128 Rev 1.10 193 Chapter 7 Debug Module (DBGV1) Block Description CLOCKS AND CONTROL SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI, FORCE BDM, AND TAGS CONTROL SIGNALS RESULTS SIGNALS CONTROL BITS READ/WRITE CONTROL BKP CONTROL SIGNALS ...... ...... EXPANSION ADDRESS ADDRESS WRITE DATA READ DATA REGISTER BLOCK BKPCT0 BKPCT1 COMPARE BLOCK BKP READ DATA BUS WRITE DATA BUS BKP0X COMPARATOR EXPANSION ADDRESSES BKP0H COMPARATOR ADDRESS HIGH ADDRESS LOW BKP0L COMPARATOR EXPANSION ADDRESSES BKP1X COMPARATOR DATA HIGH BKP1H COMPARATOR DATA/ADDRESS HIGH MUX DATA/ADDRESS LOW MUX READ DATA HIGH COMPARATOR READ DATA LOW COMPARATOR ADDRESS HIGH DATA LOW ADDRESS LOW BKP1L COMPARATOR Figure 7-1. DBG Block Diagram in BKP Mode 194 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description DBG READ DATA BUS ADDRESS BUS CONTROL WRITE DATA BUS READ DATA BUS READ/WRITE DBG MODE ENABLE CHANGE-OF-FLOW INDICATORS MCU IN BDM DETAIL EVENT ONLY CPU PROGRAM COUNTER STORE POINTER INSTRUCTION LAST CYCLE REGISTER BUS CLOCK M U X 64 x 16 BIT WORD TRACE BUFFER PROFILE CAPTURE MODE TRACE BUFFER OR PROFILING DATA ADDRESS/DATA/CONTROL REGISTERS COMPARATOR A COMPARATOR B COMPARATOR C CONTROL MATCH_A MATCH_B MATCH_C LOOP1 TRACER BUFFER CONTROL LOGIC TAG FORCE M U X WRITE DATA BUS READ DATA BUS M U X M U X LAST INSTRUCTION ADDRESS PROFILE CAPTURE REGISTER READ/WRITE Figure 7-2. DBG Block Diagram in DBG Mode 7.2 External Signal Description The DBG sub-module relies on the external bus interface (generally the MEBI) when the DBG is matching on the external bus. The tag pins in Table 7-1 (part of the MEBI) may also be a part of the breakpoint operation. Table 7-1. External System Pins Associated with DBG and MEBI Pin Name BKGD/MODC/ TAGHI PE3/LSTRB/ TAGLO Pin Functions TAGHI TAGLO Description When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue. In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue. Freescale Semiconductor MC9S12Q128 Rev 1.10 195 Chapter 7 Debug Module (DBGV1) Block Description 7.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is shown in Figure 7-3. Detailed descriptions of the registers and bits are given in the subsections that follow. 7.3.1 Module Memory Map Table 7-2. DBGV1 Memory Map Address Offset 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F Debug Control Register (DBGC1) Debug Status and Control Register (DBGSC) Debug Trace Buffer Register High (DBGTBH) Debug Trace Buffer Register Low (DBGTBL) Debug Count Register (DBGCNT) Debug Comparator C Extended Register (DBGCCX) Debug Comparator C Register High (DBGCCH) Debug Comparator C Register Low (DBGCCL) Debug Control Register 2 (DBGC2) / (BKPCT0) Debug Control Register 3 (DBGC3) / (BKPCT1) Debug Comparator A Extended Register (DBGCAX) / (/BKP0X) Debug Comparator A Register High (DBGCAH) / (BKP0H) Debug Comparator A Register Low (DBGCAL) / (BKP0L) Debug Comparator B Extended Register (DBGCBX) / (BKP1X) Debug Comparator B Register High (DBGCBH) / (BKP1H) Debug Comparator B Register Low (DBGCBL) / (BKP1L) Use Access R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7.3.2 Register Descriptions This section consists of the DBG register descriptions in address order. Most of the register bits can be written to in either BKP or DBG mode, although they may not have any effect in one of the modes. However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are DBGEN and ARM Name(1) 0x0020 DBGC1 0x0021 DBGSC R W R W = Unimplemented or Reserved Bit 7 DBGEN AF 6 ARM BF 5 TRGSEL CF 4 BEGIN 0 3 DBGBRK 2 0 1 Bit 0 CAPMOD TRG Figure 7-3. DBG Register Summary 196 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description Name(1) 0x0022 DBGTBH 0x0023 DBGTBL 0x0024 DBGCNT 0x0025 DBGCCX((2)) 0x0026 DBGCCH(2) 0x0027 DBGCCL(2) 0x0028 DBGC2 BKPCT0 0x0029 DBGC3 BKPCT1 0x002A DBGCAX BKP0X 0x002B DBGCAH BKP0H 0x002C DBGCAL BKP0L 0x002D DBGCBX BKP1X 0x002E DBGCBH BKP1H 0x002F DBGCBL BKP1L R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBF 0 CNT PAGSEL EXTCMP Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB PAGSEL EXTCMP Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 PAGSEL EXTCMP Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 7-3. DBG Register Summary (continued) Freescale Semiconductor MC9S12Q128 Rev 1.10 197 Chapter 7 Debug Module (DBGV1) Block Description 1. The DBG module is designed for backwards compatibility to existing BKP modules. Register and bit names have changed from the BKP module. This column shows the DBG register name, as well as the BKP register name for reference. 2. Comparator C can be used to enhance the BKP mode by providing a third breakpoint. 7.3.2.1 Debug Control Register 1 (DBGC1) NOTE All bits are used in DBG mode only. Module Base + 0x0020 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R DBGEN W Reset 0 0 0 0 0 ARM TRGSEL BEGIN DBGBRK 0 CAPMOD 0 0 0 = Unimplemented or Reserved Figure 7-4. Debug Control Register (DBGC1) NOTE This register cannot be written if BKP mode is enabled (BKABEN in DBGC2 is set). Table 7-3. DBGC1 Field Descriptions Field 7 DBGEN Description DBG Mode Enable Bit — The DBGEN bit enables the DBG module for use in DBG mode. This bit cannot be set if the MCU is in secure mode. 0 DBG mode disabled 1 DBG mode enabled Arm Bit — The ARM bit controls whether the debugger is comparing and storing data in the trace buffer. See Section 7.4.2.4, “Arming the DBG Module,” for more information. 0 Debugger unarmed 1 Debugger armed Note: This bit cannot be set if the DBGEN bit is not also being set at the same time. For example, a write of 01 to DBGEN[7:6] will be interpreted as a write of 00. Trigger Selection Bit — The TRGSEL bit controls the triggering condition for comparators A and B in DBG mode. It serves essentially the same function as the TAGAB bit in the DBGC2 register does in BKP mode. See Section 7.4.2.1.2, “Trigger Selection,” for more information. TRGSEL may also determine the type of breakpoint based on comparator A and B if enabled in DBG mode (DBGBRK = 1). Please refer to Section 7.4.3.1, “Breakpoint Based on Comparator A and B.” 0 Trigger on any compare address match 1 Trigger before opcode at compare address gets executed (tagged-type) Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace buffer. See Section 7.4.2.8.1, “Storing with Begin-Trigger,” and Section 7.4.2.8.2, “Storing with End-Trigger,” for more details. 0 Trigger at end of stored data 1 Trigger before storing data 6 ARM 5 TRGSEL 4 BEGIN 198 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description Table 7-3. DBGC1 Field Descriptions (continued) Field 3 DBGBRK Description DBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint based on comparator A and B to the CPU upon completion of a tracing session. Please refer to Section 7.4.3, “Breakpoints,” for further details. 0 CPU break request not enabled 1 CPU break request enabled Capture Mode Field — See Table 7-4 for capture mode field definitions. In LOOP1 mode, the debugger will automatically inhibit redundant entries into capture memory. In detail mode, the debugger is storing address and data for all cycles except program fetch (P) and free (f) cycles. In profile mode, the debugger is returning the address of the last instruction executed by the CPU on each access of trace buffer address. Refer to Section 7.4.2.6, “Capture Modes,” for more information. 1:0 CAPMOD Table 7-4. CAPMOD Encoding CAPMOD 00 01 10 11 Description Normal LOOP1 DETAIL PROFILE Freescale Semiconductor MC9S12Q128 Rev 1.10 199 Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.2 Debug Status and Control Register (DBGSC) Module Base + 0x0021 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R W Reset AF BF CF 0 TRG 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-5. Debug Status and Control Register (DBGSC) Table 7-5. DBGSC Field Descriptions Field 7 AF Description Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming. This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Trigger A did not match 1 Trigger A match Trigger B Match Flag — The BF bit indicates if trigger B match condition was met since arming.This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Trigger B did not match 1 Trigger B match Comparator C Match Flag — The CF bit indicates if comparator C match condition was met since arming.This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Comparator C did not match 1 Comparator C match Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown Table 7-6. See Section 7.4.2.5, “Trigger Modes,” for more detail. 6 BF 5 CF 3:0 TRG Table 7-6. Trigger Mode Encoding TRG Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 ↓ 1111 Meaning A only A or B A then B Event only B A then event only B A and B (full mode) A and Not B (full mode) Inside range Outside range Reserved (Defaults to A only) 200 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.3 Debug Trace Buffer Register (DBGTB) Module Base + 0x0022 Starting address location affected by INITRG register setting. 15 14 13 12 11 10 9 8 R W Reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 u u u u u u u u = Unimplemented or Reserved Figure 7-6. Debug Trace Buffer Register High (DBGTBH) Module Base + 0x0023 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R W Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 u u u u u u u u = Unimplemented or Reserved Figure 7-7. Debug Trace Buffer Register Low (DBGTBL) Table 7-7. DBGTB Field Descriptions Field 15:0 Description Trace Buffer Data Bits — The trace buffer data bits contain the data of the trace buffer. This register can be read only as a word read. Any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed. In addition, this register may appear to contain incorrect data if it is not read with the same capture mode bit settings as when the trace buffer data was recorded (See Section 7.4.2.9, “Reading Data from Trace Buffer”). Because reads will reflect the contents of the trace buffer RAM, the reset state is undefined. Freescale Semiconductor MC9S12Q128 Rev 1.10 201 Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.4 Debug Count Register (DBGCNT) Module Base + 0x0024 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R W Reset TBF 0 CNT 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-8. Debug Count Register (DBGCNT) Table 7-8. DBGCNT Field Descriptions Field 7 TBF 5:0 CNT Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was last armed. If this bit is set, then all 64 words will be valid data, regardless of the value in CNT[5:0]. The TBF bit is cleared when ARM in DBGC1 is written to a 1. Count Value — The CNT bits indicate the number of valid data words stored in the trace buffer. Table 7-9 shows the correlation between the CNT bits and the number of valid data words in the trace buffer. When the CNT rolls over to 0, the TBF bit will be set and incrementing of CNT will continue if DBG is in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a 1. Table 7-9. CNT Decoding Table TBF 0 0 0 CNT 000000 000001 000010 .. .. 111110 111111 000000 Description No data valid 1 word valid 2 words valid .. .. 62 words valid 63 words valid 64 words valid; if BEGIN = 1, the ARM bit will be cleared. A breakpoint will be generated if DBGBRK = 1 64 words valid, oldest data has been overwritten by most recent data 0 1 1 000001 .. .. 111111 202 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.5 Debug Comparator C Extended Register (DBGCCX) Module Base + 0x0025 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP Figure 7-9. Debug Comparator C Extended Register (DBGCCX) Table 7-10. DBGCCX Field Descriptions Field 7:6 PAGSEL 5:0 EXTCMP Description Page Selector Field — In both BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 7-11. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively). Comparator C Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown in Table 7-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Note: Comparator C can be used when the DBG module is configured for BKP mode. Extended addressing comparisons for comparator C use PAGSEL and will operate differently to the way that comparator A and B operate in BKP mode. Table 7-11. PAGSEL Decoding(1) PAGSEL 00 01 10(3) 112 Description Normal (64k) PPAGE (256 — 16K pages) DPAGE (reserved) (256 — 4K pages) EPAGE (reserved) (256 — 1K pages) EXTCMP Not used EXTCMP[5:0] is compared to address bits [21:16](2) EXTCMP[3:0] is compared to address bits [19:16] EXTCMP[1:0] is compared to address bits [17:16] Comment No paged memory PPAGE[7:0] / XAB[21:14] becomes address bits [21:14]1 DPAGE / XAB[21:14] becomes address bits [19:12] EPAGE / XAB[21:14] becomes address bits [17:10] 1. See Figure 7-10. 2. Current HCS12 implementations have PPAGE limited to 6 bits. Therefore, EXTCMP[5:4] should be set to 00. 3. Data page (DPAGE) and Extra page (EPAGE) are reserved for implementation on devices that support paged data and extra space. Freescale Semiconductor MC9S12Q128 Rev 1.10 203 Chapter 7 Debug Module (DBGV1) Block Description DBGCXX PAGSEL 7 6 0 5 0 4 3 EXTCMP 2 1 BIT 0 BIT 15 DBGCXH[15:12] BIT 14 BIT 13 BIT 12 BKP/DBG MODE 9 8 SEE NOTE 1 PORTK/XAB XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14 PPAGE PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 SEE NOTE 2 NOTES: 1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 7-11. 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00. Figure 7-10. Comparator C Extended Comparison in BKP/DBG Mode 7.3.2.6 Debug Comparator C Register (DBGCC) Module Base + 0x0026 Starting address location affected by INITRG register setting. 15 14 13 12 11 10 R W Reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-11. Debug Comparator C Register High (DBGCCH) Module Base + 0x0027 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R W Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-12. Debug Comparator C Register Low (DBGCCL) 204 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description Table 7-12. DBGCC Field Descriptions Field 15:0 Description Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare the address bus bits [15:0] to a logic 1 or logic 0. See Table 7-13. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode. Table 7-13. Comparator C Compares PAGSEL x0 x1 EXTCMP Compare No compare EXTCMP[5:0] = XAB[21:16] High-Byte Compare DBGCCH[7:0] = AB[15:8] DBGCCH[7:0] = XAB[15:14],AB[13:8] 7.3.2.7 Debug Control Register 2 (DBGC2) Module Base + 0x0028 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R W BKABEN(1) FULL BDM TAGAB BKCEN(2) TAGC2 RWCEN2 RWC2 Reset 0 0 0 0 0 0 0 0 1. When BKABEN is set (BKP mode), all bits in DBGC2 are available. When BKABEN is cleared and DBG is used in DBG mode, bits FULL and TAGAB have no meaning. 2. These bits can be used in BKP mode and DBG mode (when capture mode is not set in LOOP1) to provide a third breakpoint. Figure 7-13. Debug Control Register 2 (DBGC2) Table 7-14. DBGC2 Field Descriptions Field 7 BKABEN Description Breakpoint Using Comparator A and B Enable — This bit enables the breakpoint capability using comparator A and B, when set (BKP mode) the DBGEN bit in DBGC1 cannot be set. 0 Breakpoint module off 1 Breakpoint module on Full Breakpoint Mode Enable — This bit controls whether the breakpoint module is in dual mode or full mode. In full mode, comparator A is used to match address and comparator B is used to match data. See Section 7.4.1.2, “Full Breakpoint Mode,” for more details. 0 Dual address mode enabled 1 Full breakpoint mode enabled Background Debug Mode Enable — This bit determines if the breakpoint causes the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). 0 Go to software interrupt on a break request 1 Go to BDM on a break request 6 FULL 5 BDM Freescale Semiconductor MC9S12Q128 Rev 1.10 205 Chapter 7 Debug Module (DBGV1) Block Description Table 7-14. DBGC2 Field Descriptions (continued) Field 4 TAGAB Description Comparator A/B Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint. 0 On match, break at the next instruction boundary (force) 1 On match, break if/when the instruction is about to be executed (tagged) Breakpoint Comparator C Enable Bit — This bit enables the breakpoint capability using comparator C. 0 Comparator C disabled for breakpoint 1 Comparator C enabled for breakpoint Note: This bit will be cleared automatically when the DBG module is armed in loop1 mode. Comparator C Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint. 0 On match, break at the next instruction boundary (force) 1 On match, break if/when the instruction is about to be executed (tagged) Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled for comparator C. RWCEN is not useful for tagged breakpoints. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for comparator C. The RWC bit is not used if RWCEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched 3 BKCEN 2 TAGC 1 RWCEN 0 RWC 7.3.2.8 Debug Control Register 3 (DBGC3) Module Base + 0x0029 Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R W BKAMBH(1) BKAMBL1 BKBMBH(2) BKBMBL2 RWAEN RWA 0 RWBEN 0 RWB 0 Reset 0 0 0 0 0 1. In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0’s. 2. In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data. Figure 7-14. Debug Control Register 3 (DBGC3) 206 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description Table 7-15. DBGC3 Field Descriptions Field Description 7:6 Breakpoint Mask High Byte for First Address — In dual or full mode, these bits may be used to mask (disable) BKAMB[H:L] the comparison of the high and/or low bytes of the first address breakpoint. The functionality is as given in Table 7-16. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {DBGCAX[5:0], DBGCAH[5:0], DBGCAL[7:0]}, where DBGAX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {DBGCAH[7:0], DBGCAL[7:0]} which corresponds to CPU address [15:0]. Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several physical addresses may match with a single logical address. This problem may be avoided by using DBG mode to generate breakpoints. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKAMBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCAX compares. 5:4 Breakpoint Mask High Byte and Low Byte of Data (Second Address) — In dual mode, these bits may be BKBMB[H:L] used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The functionality is as given in Table 7-17. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {DBGCBX[5:0], DBGCBH[5:0], DBGCBL[7:0]} where DBGCBX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {DBGCBH[7:0], DBGCBL[7:0]} which corresponds to CPU address [15:0]. Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several physical addresses may match with a single logical address. This problem may be avoided by using DBG mode to generate breakpoints. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKBMBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCBX compares. In full mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. The functionality is as given in Table 7-18. 3 RWAEN Read/Write Comparator A Enable Bit — The RWAEN bit controls whether read or write comparison is enabled for comparator A. See Section 7.4.2.1.1, “Read or Write Comparison,” for more information. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator A Value Bit — The RWA bit controls whether read or write is used in compare for comparator A. The RWA bit is not used if RWAEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched 2 RWA Freescale Semiconductor MC9S12Q128 Rev 1.10 207 Chapter 7 Debug Module (DBGV1) Block Description Table 7-15. DBGC3 Field Descriptions (continued) Field 1 RWBEN Description Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled for comparator B. See Section 7.4.2.1.1, “Read or Write Comparison,” for more information. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator B Value Bit — The RWB bit controls whether read or write is used in compare for comparator B. The RWB bit is not used if RWBEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched Note: RWB and RWBEN are not used in full mode. 0 RWB Table 7-16. Breakpoint Mask Bits for First Address BKAMBH:BKAMBL x:0 0:1 1:1 1. If PPAGE is selected. Address Compare Full address compare 256 byte address range 16K byte address range DBGCAX Yes (1) DBGCAH Yes Yes No DBGCAL Yes No No Yes1 Yes 1 Table 7-17. Breakpoint Mask Bits for Second Address (Dual Mode) BKBMBH:BKBMBL x:0 0:1 1:1 1. If PPAGE is selected. Address Compare Full address compare 256 byte address range 16K byte address range DBGCBX Yes(1) Yes1 Yes 1 DBGCBH Yes Yes No DBGCBL Yes No No Table 7-18. Breakpoint Mask Bits for Data Breakpoints (Full Mode) BKBMBH:BKBMBL 0:0 0:1 1:0 Data Compare High and low byte compare High byte Low byte DBGCBX No (1) 1 1 DBGCBH Yes Yes No No DBGCBL Yes No Yes No No No 1:1 No compare No1 1. Expansion addresses for breakpoint B are not applicable in this mode. 208 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.9 Debug Comparator A Extended Register (DBGCAX) Module Base + 0x002A Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP Figure 7-15. Debug Comparator A Extended Register (DBGCAX) Table 7-19. DBGCAX Field Descriptions Field 7:6 PAGSEL Description Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 720. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively). In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address is in the FLASH/ROM memory space. 5:0 EXTCMP Comparator A Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown in Table 7-20 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Table 7-20. Comparator A or B Compares Mode BKP (1) EXTCMP Compare No compare EXTCMP[5:0] = XAB[19:14] No compare High-Byte Compare DBGCxH[7:0] = AB[15:8] DBGCxH[5:0] = AB[13:8] DBGCxH[7:0] = AB[15:8] Not FLASH/ROM access FLASH/ROM access PAGSEL = 00 DBG (2) PAGSEL = 01 EXTCMP[5:0] = XAB[21:16] DBGCxH[7:0] = XAB[15:14], AB[13:8] 1. See Figure 7-16. 2. See Figure 7-10 (note that while this figure provides extended comparisons for comparator C, the figure also pertains to comparators A and B in DBG mode only). Freescale Semiconductor MC9S12Q128 Rev 1.10 209 Chapter 7 Debug Module (DBGV1) Block Description PAGSEL DBGCXX 0 0 5 4 EXTCMP 3 2 1 BIT 0 PORTK/XAB XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14 PPAGE PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 SEE NOTE 2 NOTES: 1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state). 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Figure 7-16. Comparators A and B Extended Comparison in BKP Mode 7.3.2.10 Debug Comparator A Register (DBGCA) Module Base + 0x002B Starting address location affected by INITRG register setting. 15 14 13 12 11 10 9 8 R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Figure 7-17. Debug Comparator A Register High (DBGCAH) Module Base + 0x002C Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 7-18. Debug Comparator A Register Low (DBGCAL) Table 7-21. DBGCA Field Descriptions Field 15:0 15:0 Description Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the address bus bits [15:0] to a logic 1 or logic 0. See Table 7-20. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 210 MC9S12Q128 Rev 1.10 Freescale Semiconductor BKP MODE SEE NOTE 1 Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.11 Debug Comparator B Extended Register (DBGCBX) Module Base + 0x002D 7 6 5 4 3 2 1 0 R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP Figure 7-19. Debug Comparator B Extended Register (DBGCBX) Table 7-22. DBGCBX Field Descriptions Field 7:6 PAGSEL Description Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 711. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively.) In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address is in the FLASH/ROM memory space. 5:0 EXTCMP Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown in Table 7-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see Table 7-20. 7.3.2.12 Debug Comparator B Register (DBGCB) Module Base + 0x002E Starting address location affected by INITRG register setting. 15 14 13 12 11 10 9 8 R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Figure 7-20. Debug Comparator B Register High (DBGCBH) Freescale Semiconductor MC9S12Q128 Rev 1.10 211 Chapter 7 Debug Module (DBGV1) Block Description Module Base + 0x002F Starting address location affected by INITRG register setting. 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 7-21. Debug Comparator B Register Low (DBGCBL) Table 7-23. DBGCB Field Descriptions Field 15:0 15:0 Description Comparator B Compare Bits — The comparator B compare bits control whether comparator B compares the address bus bits [15:0] or data bus bits [15:0] to a logic 1 or logic 0. See Table 7-20. 0 Compare corresponding address bit to a logic 0, compares to data if in Full mode 1 Compare corresponding address bit to a logic 1, compares to data if in Full mode 7.4 Functional Description This section provides a complete functional description of the DBG module. The DBG module can be configured to run in either of two modes, BKP or DBG. BKP mode is enabled by setting BKABEN in DBGC2. DBG mode is enabled by setting DBGEN in DBGC1. Setting BKABEN in DBGC2 overrides the DBGEN in DBGC1 and prevents DBG mode. If the part is in secure mode, DBG mode cannot be enabled. 7.4.1 DBG Operating in BKP Mode In BKP mode, the DBG will be fully backwards compatible with the existing BKP_ST12_A module. The DBGC2 register has four additional bits that were not available on existing BKP_ST12_A modules. As long as these bits are written to either all 1s or all 0s, they should be transparent to the user. All 1s would enable comparator C to be used as a breakpoint, but tagging would be enabled. The match address register would be all 0s if not modified by the user. Therefore, code executing at address 0x0000 would have to occur before a breakpoint based on comparator C would happen. The DBG module in BKP mode supports two modes of operation: dual address mode and full breakpoint mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before the tagged instruction executes. The action taken upon a successful match can be to either place the CPU in background debug mode or to initiate a software interrupt. The breakpoint can operate in dual address mode or full breakpoint mode. Each of these modes is discussed in the subsections below. 7.4.1.1 Dual Address Mode When dual address mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter background debug mode or to initiate a software interrupt based upon the state of BDM in 212 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. No data breakpoints are allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. The BKxMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion. The RWx and RWxEN bits in DBGC3 select whether the type of bus cycle to match is a read, write, or read/write when performing forced breakpoints. 7.4.1.2 Full Breakpoint Mode Full breakpoint mode requires a match on address and data for a breakpoint to occur. Upon a successful match, the system will enter background debug mode or initiate a software interrupt based upon the state of BDM in DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. R/W matches are also allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. When TAGAB is set in DBGC2, only addresses are compared and data is ignored. The BKAMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly, is a range breakpoint, or is in page space. The BKBMBH:L bits in DBGC3 select whether the data is matched on the high byte, low byte, or both bytes. RWA and RWAEN bits in DBGC2 select whether the type of bus cycle to match is a read or a write when performing forced breakpoints. RWB and RWBEN bits in DBGC2 are not used in full breakpoint mode. NOTE The full trigger mode is designed to be used for either a word access or a byte access, but not both at the same time. Confusing trigger operation (seemingly false triggers or no trigger) can occur if the trigger address occurs in the user program as both byte and word accesses. 7.4.1.3 Breakpoint Priority Breakpoint operation is first determined by the state of the BDM module. If the BDM module is already active, meaning the CPU is executing out of BDM firmware, breakpoints are not allowed. In addition, while executing a BDM TRACE command, tagging into BDM is not allowed. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests. This condition applies to both forced and tagged breakpoints. In all cases, BDM related breakpoints will have priority over those generated by the Breakpoint sub-block. This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the breakpoint sub-block. Freescale Semiconductor MC9S12Q128 Rev 1.10 213 Chapter 7 Debug Module (DBGV1) Block Description NOTE BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. Even if the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. When program control returns from a tagged breakpoint through an RTI or a BDM GO command, it will return to the instruction whose tag generated the breakpoint. Unless breakpoints are disabled or modified in the service routine or active BDM session, the instruction will be tagged again and the breakpoint will be repeated. In the case of BDM breakpoints, this situation can also be avoided by executing a TRACE1 command before the GO to increment the program flow past the tagged instruction. 7.4.1.4 Using Comparator C in BKP Mode The original BKP_ST12_A module supports two breakpoints. The DBG_ST12_A module can be used in BKP mode and allow a third breakpoint using comparator C. Four additional bits, BKCEN, TAGC, RWCEN, and RWC in DBGC2 in conjunction with additional comparator C address registers, DBGCCX, DBGCCH, and DBGCCL allow the user to set up a third breakpoint. Using PAGSEL in DBGCCX for expanded memory will work differently than the way paged memory is done using comparator A and B in BKP mode. See Section 7.3.2.5, “Debug Comparator C Extended Register (DBGCCX),” for more information on using comparator C. 7.4.2 DBG Operating in DBG Mode Enabling the DBG module in DBG mode, allows the arming, triggering, and storing of data in the trace buffer and can be used to cause CPU breakpoints. The DBG module is made up of three main blocks, the comparators, trace buffer control logic, and the trace buffer. NOTE In general, there is a latency between the triggering event appearing on the bus and being detected by the DBG circuitry. In general, tagged triggers will be more predictable than forced triggers. 7.4.2.1 Comparators The DBG contains three comparators, A, B, and C. Comparator A compares the core address bus with the address stored in DBGCAH and DBGCAL. Comparator B compares the core address bus with the address stored in DBGCBH and DBGCBL except in full mode, where it compares the data buses to the data stored in DBGCBH and DBGCBL. Comparator C can be used as a breakpoint generator or as the address comparison unit in the loop1 mode. Matches on comparator A, B, and C are signaled to the trace buffer 214 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to match the upper addresses as shown in Table 7-11. NOTE If a tagged-type C breakpoint is set at the same address as an A/B taggedtype trigger (including the initial entry in an inside or outside range trigger), the C breakpoint will have priority and the trigger will not be recognized. 7.4.2.1.1 Read or Write Comparison Read or write comparisons are useful only with TRGSEL = 0, because only opcodes should be tagged as they are “read” from memory. RWAEN and RWBEN are ignored when TRGSEL = 1. In full modes (“A and B” and “A and not B”) RWAEN and RWA are used to select read or write comparisons for both comparators A and B. Table 7-24 shows the effect for RWAEN, RWA, and RW on the DBGCB comparison conditions. The RWBEN and RWB bits are not used and are ignored in full modes. Table 7-24. Read or Write Comparison Logic Table RWAEN bit 0 0 1 1 1 1 RWA bit x x 0 0 1 1 RW signal 0 1 0 1 0 1 Comment Write data bus Read data bus Write data bus No data bus compare since RW=1 No data bus compare since RW=0 Read data bus 7.4.2.1.2 Trigger Selection The TRGSEL bit in DBGC1 is used to determine the triggering condition in DBG mode. TRGSEL applies to both trigger A and B except in the event only trigger modes. By setting TRGSEL, the comparators A and B will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes (tagged-type trigger). With the TRGSEL bit cleared, a comparator match forces a trigger when the matching condition occurs (force-type trigger). NOTE If the TRGSEL is set, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. 7.4.2.2 Trace Buffer Control (TBC) The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored in the trace buffer based on the trigger mode and the match signals from the comparator. The TBC also determines whether a request to break the CPU should occur. Freescale Semiconductor MC9S12Q128 Rev 1.10 215 Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.3 Begin- and End-Trigger The definitions of begin- and end-trigger as used in the DBG module are as follows: • Begin-trigger: Storage in trace buffer occurs after the trigger and continues until 64 locations are filled. • End-trigger: Storage in trace buffer occurs until the trigger, with the least recent data falling out of the trace buffer if more than 64 words are collected. 7.4.2.4 Arming the DBG Module In DBG mode, arming occurs by setting DBGEN and ARM in DBGC1. The ARM bit in DBGC1 is cleared when the trigger condition is met in end-trigger mode or when the Trace Buffer is filled in begin-trigger mode. The TBC logic determines whether a trigger condition has been met based on the trigger mode and the trigger selection. 7.4.2.5 Trigger Modes The DBG module supports nine trigger modes. The trigger modes are encoded as shown in Table 7-6. The trigger mode is used as a qualifier for either starting or ending the storing of data in the trace buffer. When the match condition is met, the appropriate flag A or B is set in DBGSC. Arming the DBG module clears the A, B, and C flags in DBGSC. In all trigger modes except for the event-only modes and DETAIL capture mode, change-of-flow addresses are stored in the trace buffer. In the event-only modes only the value on the data bus at the trigger event B will be stored. In DETAIL capture mode address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. 7.4.2.5.1 A Only In the A only trigger mode, if the match condition for A is met, the A flag in DBGSC is set and a trigger occurs. 7.4.2.5.2 A or B In the A or B trigger mode, if the match condition for A or B is met, the corresponding flag in DBGSC is set and a trigger occurs. 7.4.2.5.3 A then B In the A then B trigger mode, the match condition for A must be met before the match condition for B is compared. When the match condition for A or B is met, the corresponding flag in DBGSC is set. The trigger occurs only after A then B have matched. NOTE When tagging and using A then B, if addresses A and B are close together, then B may not complete the trigger sequence. This occurs when A and B are in the instruction queue at the same time. Basically the A trigger has not yet occurred, so the B instruction is not tagged. Generally, if address B is at 216 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description least six addresses higher than address A (or B is lower than A) and there are not changes of flow to put these in the queue at the same time, then this operation should trigger properly. 7.4.2.5.4 Event-Only B (Store Data) In the event-only B trigger mode, if the match condition for B is met, the B flag in DBGSC is set and a trigger occurs. The event-only B trigger mode is considered a begin-trigger type and the BEGIN bit in DBGC1 is ignored. Event-only B is incompatible with instruction tagging (TRGSEL = 1), and thus the value of TRGSEL is ignored. Please refer to Section 7.4.2.7, “Storage Memory,” for more information. This trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. TRGSEL and BEGIN will not be ignored and this trigger mode will behave as if it were “B only”. 7.4.2.5.5 A then Event-Only B (Store Data) In the A then event-only B trigger mode, the match condition for A must be met before the match condition for B is compared, after the A match has occurred, a trigger occurs each time B matches. When the match condition for A or B is met, the corresponding flag in DBGSC is set. The A then event-only B trigger mode is considered a begin-trigger type and BEGIN in DBGC1 is ignored. TRGSEL in DBGC1 applies only to the match condition for A. Please refer to Section 7.4.2.7, “Storage Memory,” for more information. This trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. TRGSEL and BEGIN will not be ignored and this trigger mode will be the same as A then B. 7.4.2.5.6 A and B (Full Mode) In the A and B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A and B trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in the DBGSC register are set and a trigger occurs. If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and comparator B matches are ignored. If TRGSEL = 0, full-word data matches on an odd address boundary (misaligned access) do not work unless the access is to a RAM that manages misaligned accesses in a single clock cycle (which is typical of RAM modules used in HCS12 MCUs). 7.4.2.5.7 A and Not B (Full Mode) In the A and not B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A and not B trigger mode, if the match condition for A and not B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and comparator B matches are ignored. As described in Section 7.4.2.5.6, “A and B (Full Mode),” full-word data compares on misaligned accesses will not match expected data (and thus will cause a trigger in this mode) unless the access is to a RAM that manages misaligned accesses in a single clock cycle. Freescale Semiconductor MC9S12Q128 Rev 1.10 217 Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.5.8 Inside Range (A ≤ address ≤ B) In the inside range trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If a match condition on only A or only B occurs no flags are set. If TRGSEL = 1, the inside range is accurate only to word boundaries. If TRGSEL = 0, an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is within the range. 7.4.2.5.9 Outside Range (address < A or address > B) In the outside range trigger mode, if the match condition for A or B is met, the corresponding flag in DBGSC is set and a trigger occurs. If TRGSEL = 1, the outside range is accurate only to word boundaries. If TRGSEL = 0, an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. 7.4.2.5.10 Control Bit Priorities The definitions of some of the control bits are incompatible with each other. Table 7-25 and the notes associated with it summarize how these incompatibilities are managed: • Read/write comparisons are not compatible with TRGSEL = 1. Therefore, RWAEN and RWBEN are ignored. • Event-only trigger modes are always considered a begin-type trigger. See Section 7.4.2.8.1, “Storing with Begin-Trigger,” and Section 7.4.2.8.2, “Storing with End-Trigger.” • Detail capture mode has priority over the event-only trigger/capture modes. Therefore, event-only modes have no meaning in detail mode and their functions default to similar trigger modes. Table 7-25. Resolution of Mode Conflicts Normal / Loop1 Mode Tag A only A or B A then B Event-only B A then event-only B A and B (full mode) A and not B (full mode) Inside range Outside range 1 2 5 5 6 6 1, 3 4 5 5 6 6 3 4 Force Tag Force Detail 1 — Ignored — same as force 2 — Ignored for comparator B 3 — Reduces to effectively “B only” 4 — Works same as A then B 5 — Reduces to effectively “A only” — B not compared 6 — Only accurate to word boundaries 218 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.6 Capture Modes The DBG in DBG mode can operate in four capture modes. These modes are described in the following subsections. 7.4.2.6.1 Normal Mode In normal mode, the DBG module uses comparator A and B as triggering devices. Change-of-flow information or data will be stored depending on TRG in DBGSC. 7.4.2.6.2 Loop1 Mode The intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the trace buffer, the DBG module writes this value into the C comparator and the C comparator is placed in ignore address mode. This will prevent duplicate address entries in the trace buffer resulting from repeated bit-conditional branches. Comparator C will be cleared when the ARM bit is set in loop1 mode to prevent the previous contents of the register from interfering with loop1 mode operation. Breakpoints based on comparator C are disabled. Loop1 mode only inhibits duplicate source address entries that would typically be stored in most tight looping constructs. It will not inhibit repeated entries of destination addresses or vector addresses, because repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the C comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below: LOOP INCX ; 1-byte instruction fetched by 1st P-cycle of BRCLR BRCLR CMPTMP,#$0c,LOOP ; the BRCLR instruction also will be fetched by 1st P-cycle of BRCLR * A,LOOP2 ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE LOOP2 BRN NOP DBNE NOTE Loop1 mode does not support paged memory, and inhibits duplicate entries in the trace buffer based solely on the CPU address. There is a remote possibility of an erroneous address match if program flow alternates between paged and unpaged memory space. Freescale Semiconductor MC9S12Q128 Rev 1.10 219 Chapter 7 Debug Module (DBGV1) Block Description 7.4.2.6.3 Detail Mode In the detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where his code was in error. 7.4.2.6.4 Profile Mode This mode is intended to allow a host computer to poll a running target and provide a histogram of program execution. Each read of the trace buffer address will return the address of the last instruction executed. The DBGCNT register is not incremented and the trace buffer does not get filled. The ARM bit is not used and all breakpoints and all other debug functions will be disabled. 7.4.2.7 Storage Memory The storage memory is a 64 words deep by 16-bits wide dual port RAM array. The CPU accesses the RAM array through a single memory location window (DBGTBH:DBGTBL). The DBG module stores trace information in the RAM array in a circular buffer format. As data is read via the CPU, a pointer into the RAM will increment so that the next CPU read will receive fresh information. In all trigger modes except for event-only and detail capture mode, the data stored in the trace buffer will be change-of-flow addresses. change-of-flow addresses are defined as follows: • Source address of conditional branches (long, short, BRSET, and loop constructs) taken • Destination address of indexed JMP, JSR, and CALL instruction • Destination address of RTI, RTS, and RTC instructions • Vector address of interrupts except for SWI and BDM vectors In the event-only trigger modes only the 16-bit data bus value corresponding to the event is stored. In the detail capture mode, address and then data are stored for all cycles except program fetch (P) and free (f) cycles. 7.4.2.8 7.4.2.8.1 Storing Data in Memory Storage Buffer Storing with Begin-Trigger Storing with begin-trigger can be used in all trigger modes. When DBG mode is enabled and armed in the begin-trigger mode, data is not stored in the trace buffer until the trigger condition is met. As soon as the trigger condition is met, the DBG module will remain armed until 64 words are stored in the trace buffer. If the trigger is at the address of the change-of-flow instruction the change-of-flow associated with the trigger event will be stored in the trace buffer. 7.4.2.8.2 Storing with End-Trigger Storing with end-trigger cannot be used in event-only trigger modes. When DBG mode is enabled and armed in the end-trigger mode, data is stored in the trace buffer until the trigger condition is met. When the trigger condition is met, the DBG module will become de-armed and no more data will be stored. If 220 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 7 Debug Module (DBGV1) Block Description the trigger is at the address of a change-of-flow address the trigger event will not be stored in the trace buffer. 7.4.2.9 Reading Data from Trace Buffer The data stored in the trace buffer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is enabled and not armed. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid words can be determined. CNT will not decrement as data is read from DBGTBH:DBGTBL. The trace buffer data is read by reading DBGTBH:DBGTBL with a 16-bit read. Each time DBGTBH:DBGTBL is read, a pointer in the DBG will be incremented to allow reading of the next word. Reading the trace buffer while the DBG module is armed will return invalid data and no shifting of the RAM pointer will occur. NOTE The trace buffer should be read with the DBG module enabled and in the same capture mode that the data was recorded. The contents of the trace buffer counter register (DBGCNT) are resolved differently in detail mode verses the other modes and may lead to incorrect interpretation of the trace buffer data. 7.4.3 Breakpoints There are two ways of getting a breakpoint in DBG mode. One is based on the trigger condition of the trigger mode using comparator A and/or B, and the other is using comparator C. External breakpoints generated using the TAGHI and TAGLO external pins are disabled in DBG mode. 7.4.3.1 Breakpoint Based on Comparator A and B A breakpoint request to the CPU can be enabled by setting DBGBRK in DBGC1. The value of BEGIN in DBGC1 determines when the breakpoint request to the CPU will occur. When BEGIN in DBGC1 is set, begin-trigger is selected and the breakpoint request will not occur until the trace buffer is filled with 64 words. When BEGIN in DBGC1 is cleared, end-trigger is selected and the breakpoint request will occur immediately at the trigger cycle. There are two types of breakpoint requests supported by the DBG module, tagged and forced. Tagged breakpoints are associated with opcode addresses and allow breaking just before a specific instruction executes. Forced breakpoints are not associated with opcode addresses and allow breaking at the next instruction boundary. The type of breakpoint based on comparators A and B is determined by TRGSEL in the DBGC1 register (TRGSEL = 1 for tagged breakpoint, TRGSEL = 0 for forced breakpoint). Table 7-26 illustrates the type of breakpoint that will occur based on the debug run. Freescale Semiconductor MC9S12Q128 Rev 1.10 221 Chapter 7 Debug Module (DBGV1) Block Description Table 7-26. Breakpoint Setup BEGIN 0 0 0 0 1 1 1 1 TRGSEL 0 0 1 1 0 0 1 1 DBGBRK 0 1 0 1 0 1 0 1 Type of Debug Run Fill trace buffer until trigger address (no CPU breakpoint — keep running) Fill trace buffer until trigger address, then a forced breakpoint request occurs Fill trace buffer until trigger opcode is about to execute (no CPU breakpoint — keep running) Fill trace buffer until trigger opcode about to execute, then a tagged breakpoint request occurs Start trace buffer at trigger address (no CPU breakpoint — keep running) Start trace buffer at trigger address, a forced breakpoint request occurs when trace buffer is full Start trace buffer at trigger opcode (no CPU breakpoint — keep running) Start trace buffer at trigger opcode, a forced breakpoint request occurs when trace buffer is full 7.4.3.2 Breakpoint Based on Comparator C A breakpoint request to the CPU can be created if BKCEN in DBGC2 is set. Breakpoints based on a successful comparator C match can be accomplished regardless of the mode of operation for comparator A or B, and do not affect the status of the ARM bit. TAGC in DBGC2 is used to select either tagged or forced breakpoint requests for comparator C. Breakpoints based on comparator C are disabled in LOOP1 mode. NOTE Because breakpoints cannot be disabled when the DBG is armed, one must be careful to avoid an “infinite breakpoint loop” when using tagged-type C breakpoints while the DBG is armed. If BDM breakpoints are selected, executing a TRACE1 instruction before the GO instruction is the recommended way to avoid re-triggering a breakpoint if one does not wish to de-arm the DBG. If SWI breakpoints are selected, disarming the DBG in the SWI interrupt service routine is the recommended way to avoid retriggering a breakpoint. 7.5 Resets The DBG module is disabled after reset. The DBG module cannot cause a MCU reset. 7.6 Interrupts The DBG contains one interrupt source. If a breakpoint is requested and BDM in DBGC2 is cleared, an SWI interrupt will be generated. 222 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.1 Introduction The ATD10B8C is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. The block is designed to be upwards compatible with the 68HC11 standard 8-bit A/D converter. In addition, there are new operating modes that are unique to the HC12 design. 8.1.1 • • • • • • • • • • • • Features 8/10-bit resolution. 7 µsec, 10-bit single conversion time. Sample buffer amplifier. Programmable sample time. Left/right justified, signed/unsigned result data. External trigger control. Conversion completion interrupt generation. Analog input multiplexer for eight analog input channels. Analog/digital input pin multiplexing. 1-to-8 conversion sequence lengths. Continuous conversion mode. Multiple channel scans. 8.1.2 8.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. Freescale Semiconductor MC9S12Q128 Rev 1.10 223 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.1.2.2 • MCU Operating Modes • • Stop Mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This aborts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time, tSR, before initiating a new ATD conversion sequence. Wait Mode Entering wait mode the ATD conversion either continues or aborts for low power depending on the logical value of the AWAIT bit. Freeze Mode In freeze mode the ATD10B8C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. 8.1.3 Block Diagram Figure 8-1 is a block diagram of the ATD. ATD10B8C BUS CLOCK CLOCK PRESCALER ATD CLOCK CONVERSION COMPLETE INTERRUPT MODE AND TIMING CONTROL RESULTS ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 VRH VRL VDDA VSSA AN7 / PAD7 AN6 / PAD6 AN5 / PAD5 AN4 / PAD4 AN3 / PAD3 AN2 / PAD2 AN1 / PAD1 AN0 / PAD0 ANALOG MUX SUCCESSIVE APPROXIMATION REGISTER (SAR) AND DAC + SAMPLE & HOLD 1 1 – COMPARATOR ATD INPUT ENABLE REGISTER PORT AD DATA REGISTER Figure 8-1. ATD10B8C Block Diagram 224 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.2 Signal Description The ATD10B8C has a total of 12 external pins. 8.2.1 AN7 / ETRIG / PAD7 This pin serves as the analog input channel 7. It can be configured to provide an external trigger for the ATD conversion. It can be configured as general-purpose digital I/O. 8.2.2 AN6 / PAD6 This pin serves as the analog input channel 6. It can be configured as general-purpose digital I/O. 8.2.3 AN5 / PAD5 This pin serves as the analog input channel 5. It can be configured as general-purpose digital I/O. 8.2.4 AN4 / PAD4 This pin serves as the analog input channel 4. It can be configured as general-purpose digital I/O. 8.2.5 AN3 / PAD3 This pin serves as the analog input channel 3. It can be configured as general-purpose digital I/O. 8.2.6 AN2 / PAD2 This pin serves as the analog input channel 2. It can be configured as general-purpose digital I/O. 8.2.7 AN1 / PAD1 This pin serves as the analog input channel 1. It can be configured as general-purpose digital I/O. 8.2.8 AN0 / PAD0 This pin serves as the analog input channel 0. It can be configured as general-purpose digital I/O. 8.2.9 VRH, VRL VRH is the high reference voltage and VRL is the low reference voltage for ATD conversion. 8.2.10 VDDA, VSSA These pins are the power supplies for the analog circuitry of the ATD10B8C block. Freescale Semiconductor MC9S12Q128 Rev 1.10 225 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the ATD10B8C. 8.3.1 Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F Module Memory Map Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Unimplemented ATDTEST0 ATDTEST1 Unimplemented ATDSTAT1 Unimplemented ATDDIEN Unimplemented PORTAD R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W = Unimplemented or Reserved PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 IEN7 0 IEN6 0 IEN5 0 IEN4 0 IEN3 0 IEN2 0 IEN1 0 IEN0 0 0 0 0 0 0 0 0 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 U U U U U U U SC 0 U U U U U U U U SRES8 DJM SCF 0 ADPU 0 AFFC S8C SMP1 DSGN 0 0 AWAI S4C SMP0 SCAN ETORF 0 ETRIGLE S2C PRS4 MULT FIFOR 0 ETRIGP S1C PRS3 0 0 0 ETRIGE FIFO PRS2 CC CC2 0 ASCIE FRZ1 PRS1 CB CC1 0 ASCIF 0 0 0 0 0 0 0 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Figure 8-2 gives an overview on all ATD10B8C registers. FRZ0 PRS0 CA CC0 0 Figure 8-2. ATD Register Summary (Sheet 1 of 4) 226 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Address Name Bit 7 R BIT 9 MSB BIT 7 MSB W R BIT 1 u 6 BIT 8 BIT 6 BIT 0 u BIT 8 BIT 6 BIT 0 u BIT 8 BIT 6 BIT 0 u BIT 8 BIT 6 BIT 0 u BIT 8 BIT 6 BIT 0 u BIT 8 BIT 6 BIT 0 u BIT 8 BIT 6 BIT 0 u 5 BIT 7 BIT 5 0 0 BIT 7 BIT 5 0 0 BIT 7 BIT 5 0 0 BIT 7 BIT 5 0 0 BIT 7 BIT 5 0 0 BIT 7 BIT 5 0 0 BIT 7 BIT 5 0 0 4 BIT 6 BIT 4 0 0 BIT 6 BIT 4 0 0 BIT 6 BIT 4 0 0 BIT 6 BIT 4 0 0 BIT 6 BIT 4 0 0 BIT 6 BIT 4 0 0 BIT 6 BIT 4 0 0 3 BIT 5 BIT 3 0 0 BIT 5 BIT 3 0 0 BIT 5 BIT 3 0 0 BIT 5 BIT 3 0 0 BIT 5 BIT 3 0 0 BIT 5 BIT 3 0 0 BIT 5 BIT 3 0 0 2 BIT 4 BIT 2 0 0 BIT 4 BIT 2 0 0 BIT 4 BIT 2 0 0 BIT 4 BIT 2 0 0 BIT 4 BIT 2 0 0 BIT 4 BIT 2 0 0 BIT 4 BIT 2 0 0 1 BIT 3 BIT 1 0 0 BIT 3 BIT 1 0 0 BIT 3 BIT 1 0 0 BIT 3 BIT 1 0 0 BIT 3 BIT 1 0 0 BIT 3 BIT 1 0 0 BIT 3 BIT 1 0 0 Bit 0 BIT 2 BIT 0 0 0 BIT 2 BIT 0 0 0 BIT 2 BIT 0 0 0 BIT 2 BIT 0 0 0 BIT 2 BIT 0 0 0 BIT 2 BIT 0 0 0 BIT 2 BIT 0 0 0 Left Justified Result Data 0x0010 ATDDR0H 0x0011 ATDDR0L W 0x0012 ATDDR1H R BIT 9 MSB BIT 7 MSB W R BIT 1 u 0x0013 ATDDR1L W 0x0014 ATDDR2H R BIT 9 MSB BIT 7 MSB W R BIT 1 u 0x0015 ATDDR2L W 0x0016 ATDDR3H R BIT 9 MSB BIT 7 MSB W R BIT 1 u 0x0017 ATDDR3L W 0x0018 ATDDR4H R BIT 9 MSB BIT 7 MSB W R BIT 1 u 0x0019 ATDDR4L W 0x001A ATDDR5H R BIT 9 MSB BIT 7 MSB W R BIT 1 u 0x001B ATDDR5L W 0x001C ATDDR6H R BIT 9 MSB BIT 7 MSB W R BIT 1 u 0x001D ATDDR6L W = Unimplemented or Reserved Figure 8-2. ATD Register Summary (Sheet 2 of 4) Freescale Semiconductor MC9S12Q128 Rev 1.10 227 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Address 0x001E Name ATDDR7H Bit 7 R BIT 9 MSB BIT 7 MSB W R BIT 1 u 6 BIT 8 BIT 6 BIT 0 u 5 BIT 7 BIT 5 0 0 4 BIT 6 BIT 4 0 0 3 BIT 5 BIT 3 0 0 2 BIT 4 BIT 2 0 0 1 BIT 3 BIT 1 0 0 Bit 0 BIT 2 BIT 0 0 0 0x001F ATDDR7L W Right Justified Result Data R 0x0010 ATDDR0H W R 0x0011 ATDDR0L W R 0x0012 ATDDR1H W R 0x0013 ATDDR1L W R 0x0014 ATDDR2H W R 0x0015 ATDDR2L W R 0x0016 ATDDR3H W R 0x0017 ATDDR3L W R 0x0018 ATDDR4H W R 0x0019 ATDDR4L W R 0x001A ATDDR5H W R 0x001B ATDDR5L W = Unimplemented or Reserved BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 Figure 8-2. ATD Register Summary (Sheet 3 of 4) 228 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Address 0x001C Name R ATDDR6H W R Bit 7 0 0 BIT 7 BIT 7 MSB 0 0 BIT 7 BIT 7 MSB 6 0 0 BIT 6 BIT 6 0 0 BIT 6 BIT 6 5 0 0 BIT 5 BIT 5 0 0 BIT 5 BIT 5 4 0 0 BIT 4 BIT 4 0 0 BIT 4 BIT 4 3 0 0 BIT 3 BIT 3 0 0 BIT 3 BIT 3 2 0 0 BIT 2 BIT 2 0 0 BIT 2 BIT 2 1 BIT 9 MSB 0 BIT 1 BIT 1 BIT 9 MSB 0 BIT 1 BIT 1 Bit 0 BIT 8 0 BIT 0 BIT 0 BIT 8 0 BIT 0 BIT 0 0x001D ATDDR6L W R 0x001E ATDDR7H W R 0x001F ATDDR7L W = Unimplemented or Reserved Figure 8-2. ATD Register Summary (Sheet 4 of 4) NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. Freescale Semiconductor MC9S12Q128 Rev 1.10 229 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2 Register Descriptions This section describes in address order all the ATD10B8C registers and their individual bits. 8.3.2.1 Reserved Register (ATDCTL0) Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-3. Reserved Register (ATDCTL0) Read: Always read $00 in normal modes Write: Unimplemented in normal modes 8.3.2.2 Reserved Register (ATDCTL1) Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-4. Reserved Register (ATDCTL1) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality. 230 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.3 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt, and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0002 7 6 5 4 3 2 1 0 R ADPU W Reset 0 0 0 0 0 0 0 AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF 0 = Unimplemented or Reserved Figure 8-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 8-1. ATDCTL2 Field Descriptions Field 7 ADPU Description ATD Power Down — This bit provides on/off control over the ATD10B8C block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled. 0 Power down ATD 1 Normal ATD functionality ATD Fast Flag Clear All 0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). 1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the ATD10B8C block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode. 0 ATD continues to run in Wait mode 1 Halt conversion and power down ATD during Wait mode After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this conversion should be ignored. External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 8-2 for details. External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 8-2 for details. External Trigger Mode Enable — This bit enables the external trigger on ATD channel 7. The external trigger allows to synchronize sample and ATD conversions processes with external events. 0 Disable external trigger 1 Enable external trigger Note: The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled. 6 AFFC 5 AWAI 4 ETRIGLE 3 ETRIGP 2 ETRIGE Freescale Semiconductor MC9S12Q128 Rev 1.10 231 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-1. ATDCTL2 Field Descriptions (continued) Field 1 ASCIE 0 ASCIF Description ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 8.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect. 0 No ATD interrupt occurred 1 ATD sequence complete interrupt pending Table 8-2. External Trigger Configurations ETRIGLE 0 0 1 1 ETRIGP 0 1 0 1 External Trigger Sensitivity Falling edge Rising edge Low level High level 8.3.2.4 ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0003 7 6 5 4 3 2 1 0 R W Reset 0 S8C 0 0 S4C 1 S2C 0 S1C 0 FIFO 0 FRZ1 0 FRZ0 0 = Unimplemented or Reserved Figure 8-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 8-3. ATDCTL3 Field Descriptions Field 6–3 S8C, S4C, S2C, S1C Description Conversion Sequence Length — These bits control the number of conversions per sequence. Table 8-4 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. 232 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-3. ATDCTL3 Field Descriptions (continued) Field 2 FIFO Description Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. The conversion counter value (CC2-0 in ATDSTAT0) can be used to determine where in the result register file, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). 1–0 FRIZ[1:0] Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 8-5. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. Table 8-4. Conversion Sequence Length Coding S8C 0 0 0 0 0 0 0 0 1 S4C 0 0 0 0 1 1 1 1 X S2C 0 0 1 1 0 0 1 1 X S1C 0 1 0 1 0 1 0 1 X Number of Conversions per Sequence 8 1 2 3 4 5 6 7 8 Table 8-5. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 0 0 1 1 FRZ0 0 1 0 1 Behavior in Freeze Mode Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately Freescale Semiconductor MC9S12Q128 Rev 1.10 233 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. Module Base + 0x0004 7 6 5 4 3 2 1 0 R SRES8 W Reset 0 0 0 0 0 1 0 1 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Figure 8-7. ATD Control Register 4 (ATDCTL4) Read: Anytime Write: Anytime Table 8-6. ATDCTL4 Field Descriptions Field 7 SRES8 Description A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits; however, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10-bit resolution 1 8-bit resolution Sample Time Select — These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 8-7 lists the lengths available for the second sample phase. ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: [ BusClock ] ATDclock = ----------------------------- × 0.5 [ PRS + 1 ] Note: The maximum ATD conversion clock frequency is half the Bus Clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is Bus Clock divided by 12. Table 8-8 illustrates the divide-by operation and the appropriate range of the Bus Clock. 6–5 SMP[1:0] 4–0 PRS[4:0} Table 8-7. Sample Time Select SMP1 0 0 1 1 SMP0 0 1 0 1 Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 16 A/D conversion clock periods 234 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-8. Clock Prescaler Values Prescale Value Total Divisor Value Maximum Bus Clock(1) Minimum Bus Clock(2) 1 MHz 4 MHz Divide by 2 00000 2 MHz 8 MHz Divide by 4 00001 3 MHz 12 MHz Divide by 6 00010 4 MHz 16 MHz Divide by 8 00011 5 MHz 20 MHz Divide by 10 00100 6 MHz 24 MHz Divide by 12 00101 7 MHz 28 MHz Divide by 14 00110 8 MHz 32 MHz Divide by 16 00111 9 MHz 36 MHz Divide by 18 01000 10 MHz 40 MHz Divide by 20 01001 11 MHz 44 MHz Divide by 22 01010 12 MHz 48 MHz Divide by 24 01011 13 MHz 52 MHz Divide by 26 01100 14 MHz 56 MHz Divide by 28 01101 15 MHz 60 MHz Divide by 30 01110 16 MHz 64 MHz Divide by 32 01111 17 MHz 68 MHz Divide by 34 10000 18 MHz 72 MHz Divide by 36 10001 19 MHz 76 MHz Divide by 38 10010 20 MHz 80 MHz Divide by 40 10011 21 MHz 84 MHz Divide by 42 10100 22 MHz 88 MHz Divide by 44 10101 23 MHz 92 MHz Divide by 46 10110 24 MHz 96 MHz Divide by 48 10111 25 MHz 100 MHz Divide by 50 11000 26 MHz 104 MHz Divide by 52 11001 27 MHz 108 MHz Divide by 54 11010 28 MHz 112 MHz Divide by 56 11011 29 MHz 116 MHz Divide by 58 11100 30 MHz 120 MHz Divide by 60 11101 31 MHz 124 MHz Divide by 62 11110 32 MHz 128 MHz Divide by 64 11111 1. Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2. Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column. Freescale Semiconductor MC9S12Q128 Rev 1.10 235 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. Module Base + 0x0005 7 6 5 4 3 2 1 0 R DJM W Reset 0 0 0 0 DSGN SCAN MULT 0 CC 0 0 CB 0 CA 0 = Unimplemented or Reserved Figure 8-8. ATD Control Register 5 (ATDCTL5) Read: Anytime Write: Anytime Table 8-9. ATDCTL5 Field Descriptions Field 7 DJM Description Result Register Data Justification — This bit controls justification of conversion data in the result registers. See Section 8.3.2.13, “ATD Conversion Result Registers (ATDDRHx/ATDDRLx)” for details. 0 Left justified data in the result registers 1 Right justified data in the result registers Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed data is not available in right justification. See Section 8.3.2.13, “ATD Conversion Result Registers (ATDDRHx/ATDDRLx)” for details. 0 Unsigned data representation in the result registers 1 Signed data representation in the result registers Table 8-10 summarizes the result data formats available and how they are set up using the control bits. Table 8-11 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. 5 Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed SCAN continuously or only once. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) 4 Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified MULT analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code. 0 Sample only one channel 1 Sample across several channels 2–1 Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are CC, CB, CA sampled and converted to digital codes. Table 8-12 lists the coding used to select the various analog input channels. In the case of single channel scans (MULT = 0), this selection code specified the channel examined. In the case of multi-channel scans (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing channel selection code; selection codes that reach the maximum value wrap around to the minimum value. 6 DSGN 236 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-10. Available Result Data Formats SRES8 1 1 1 0 0 0 DJM 0 0 1 0 0 1 DSGN 0 1 X 0 1 X Result Data Formats Description and Bus Bit Mapping 8-bit / left justified / unsigned — bits 8–15 8-bit / left justified / signed — bits 8–15 8-bit / right justified / unsigned — bits 0–7 10-bit / left justified / unsigned — bits 6–15 10-bit / left justified / signed — bits 6–15 10-bit / right justified / unsigned — bits 0–9 Table 8-11. Left Justified, Signed, and Unsigned ATD Output Codes. Input Signal VRL = 0 Volts VRH = 5.12 Volts 5.120 Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Signed 8-Bit Codes 7F 7F 7E 01 00 FF 81 80 Unsigned 8-Bit Codes FF FF FE 81 80 7F 01 00 Signed 10-Bit Codes 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 Unsigned 10-Bit Codes FFC0 FF00 FE00 8100 8000 7F00 0100 0000 Table 8-12. Analog Input Channel Select Coding CC 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Freescale Semiconductor MC9S12Q128 Rev 1.10 237 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the sequence complete flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 6 5 4 3 2 1 0 R SCF W Reset 0 0 ETORF 0 0 FIFOR 0 0 CC2 CC1 CC0 0 0 0 0 = Unimplemented or Reserved Figure 8-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (no effect on (CC2, CC1, CC0)) Table 8-13. ATDSTAT0 Field Descriptions Field 7 SCF Description Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is cleared when one of the following occurs: A) Write “1” to SCF B) Write to ATDCTL5 (a new conversion sequence is started) C) If AFFC=1 and read of a result register 0 Conversion sequence not completed 1 Conversion sequence has completed External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the following occurs: A) Write “1” to ETORF B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No External trigger over run error has occurred 1 External trigger over run error has occurred 5 ETORF 238 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description Table 8-13. ATDSTAT0 Field Descriptions (continued) Field 4 FIFOR Description FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e. the old data has been lost). This flag is cleared when one of the following occurs: A) Write “1” to FIFOR B) Start a new conversion sequence (write to ATDCTL5 or external trigger) 0 No over run has occurred 1 An over run condition exists Conversion Counter — These 3 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. For example, CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in nonFIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-2) clears the conversion counter even if FIFO=1. 2–0 CC[2:0] 8.3.2.8 Reserved Register (ATDTEST0) Module Base + 0x0008 7 6 5 4 3 2 1 0 R W Reset U U U U U U U U 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-10. Reserved Register (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality. Freescale Semiconductor MC9S12Q128 Rev 1.10 239 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.9 ATD Test Register 1 (ATDTEST1) This register contains the SC bit used to enable special channel conversions. Module Base + 0x0009 7 6 5 4 3 2 1 0 R W Reset U U U U U U U SC 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-11. ATD Test Register 1 (ATDTEST1) Read: Anytime, returns unpredictable values for Bit 7 and Bit 6 Write: Anytime Table 8-14. ATDTEST1 Field Descriptions Field 0 SC Description Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC, CB, and CA of ATDCTL5. Table 8-15 lists the coding. 0 Special channel conversions disabled 1 Special channel conversions enabled Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result in unpredictable ATD behavior. Table 8-15. Special Channel Select Coding SC 1 1 1 1 1 CC 0 1 1 1 1 CB X 0 0 1 1 CA X 0 1 0 1 Analog Input Channel Reserved VRH VRL (VRH+VRL) / 2 Reserved 240 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.10 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags. Module Base + 0x000B 7 6 5 4 3 2 1 0 R W Reset CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-12. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 8-16. ATDSTAT1 Field Descriptions Field 7–0 CCF[7:0] Description Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A flag CCFx (x = 7, 6, 5, 4, 3, 2, 1, 0) is cleared when one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx C) If AFFC = 1 and read of result register ATDDRx 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx Freescale Semiconductor MC9S12Q128 Rev 1.10 241 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.11 ATD Input Enable Register (ATDDIEN) Module Base + 0x000D 7 6 5 4 3 2 1 0 R IEN7 W Reset 0 0 0 0 0 0 0 0 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Figure 8-13. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 8-17. ATDDIEN Field Descriptions Field 7–0 IEN[7:0] Description ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. 242 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.12 Port Data Register (PORTAD) The data port associated with the ATD is general purpose I/O. The port pins are shared with the analog A/D inputs AN7–AN0. Module Base + 0x000F 7 6 5 4 3 2 1 0 R W Reset Pin Function PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 1 AN7 1 AN6 1 AN5 1 AN4 1 AN3‘ 1 AN2 1 AN1 1 AN0 = Unimplemented or Reserved Figure 8-14. Port Data Register (PORTAD) Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital I/0. Table 8-18. PORTAD Field Descriptions Field 7 PTAD[7:0] Description A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled (IENx = 1) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0), read returns a “1”. Reset sets all PORTAD bits to “1”. 8.3.2.13 ATD Conversion Result Registers (ATDDRHx/ATDDRLx) The A/D conversion results are stored in 8 read-only result registers ATDDRHx/ATDDRLx. The result data is formatted in the result registers based on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime, no effect in normal modes Freescale Semiconductor MC9S12Q128 Rev 1.10 243 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.3.2.13.1 Left Justified Result Data Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H 7 6 5 4 3 2 1 0 R BIT 9 MSB W BIT 7 MSB Reset 0 BIT 8 BIT 6 0 BIT 7 BIT 5 0 BIT 6 BIT 4 0 BIT 5 BIT 3 0 BIT 4 BIT 2 0 BIT 3 BIT 1 0 BIT 2 BIT 0 0 10-bit data 8-bit data Figure 8-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH) Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L 7 6 5 4 3 2 1 0 R W Reset BIT 1 U 0 BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10-bit data 8-bit data Figure 8-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) 8.3.2.13.2 Right Justified Result Data Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 0 BIT 8 0 0 10-bit data 8-bit data Figure 8-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH) Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L 7 6 5 4 3 2 1 0 BIT 7 W BIT 7 MSB Reset 0 R BIT 6 BIT 6 0 BIT 5 BIT 5 0 BIT 4 BIT 4 0 BIT 3 BIT 3 0 BIT 2 BIT 2 0 BIT 1 BIT 1 0 BIT 0 BIT 0 0 10-bit data 8-bit data Figure 8-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) 244 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.4 Functional Description The ATD10B8C is structured in an analog and a digital sub-block. 8.4.1 Analog Sub-block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 8.4.1.1 Sample and Hold Machine The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node.The second stage connects the input directly to the storage node to complete the sample for high accuracy. When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA. 8.4.1.2 Analog Input Multiplexer The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine. 8.4.1.3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. 8.4.1.4 Analog-to-Digital (A/D) Machine The A/D machine performs analog-to-digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output codes. Freescale Semiconductor MC9S12Q128 Rev 1.10 245 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.4.2 Digital Sub-block This subsection explains some of the digital features in more detail. See 7 for all details. 8.4.2.1 External Trigger Input (ETRIG) The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The input signal (ATD channel 7) is programmable to be edge or level sensitive with polarity control. Table 8-19 gives a brief description of the different combinations of control bits and their affect on the external trigger function . Table 8-19. External Trigger Control Bits ETRIGLE X X 0 0 1 1 ETRIGP X X 0 1 0 1 ETRIGE 0 0 1 1 1 1 SCAN 0 1 X X X X Description Ignores external trigger. Performs one conversion sequence and stops. Ignores external trigger. Performs continuous conversion sequences. Falling edge triggered. Performs one conversion sequence per trigger. Rising edge triggered. Performs one conversion sequence per trigger. Trigger active low. Performs continuous conversions while trigger is active. Trigger active high. Performs continuous conversions while trigger is active. During a conversion, if additional active edges are detected the overrun error flag ETORF is set. In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one Bus Clock cycle plus any skew or delay introduced by the trigger circuitry. NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled. Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun; therefore, the flag is not set. If the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately. 246 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.4.2.2 General-Purpose Digital Port Operation The channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. Alternatively they can be configured as digital I/O signals with the port I/O data being held in PORTAD. The analog/digital multiplex operation is performed in the pads. The pad is always connected to the analog inputs of the ATD10B8C. The pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input. 8.4.2.3 Low-Power Modes The ATD10B8C can be configured for lower MCU power consumption in three different ways: 1. Stop Mode: This halts A/D conversion. Exit from Stop mode will resume A/D conversion, But due to the recovery time the result of this conversion should be ignored. 2. Wait Mode with AWAI = 1: This halts A/D conversion. Exit from Wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. 3. Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. NOTE The reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state. 8.5 8.5.1 Initialization/Application Information Setting up and starting an A/D conversion The following describes a typical setup procedure for starting A/D conversions. It is highly recommended to follow this procedure to avoid common mistakes. Each step of the procedure will have a general remark and a typical example 8.5.1.1 Step 1 Power up the ATD and concurrently define other settings in ATDCTL2 Example: Write to ATDCTL2: ADPU=1 -> powers up the ATD, ASCIE=1 enable interrupt on finish of a conversion sequence. 8.5.1.2 Step 2 Wait for the ATD Recovery Time tREC before you proceed with Step 3. Example: Use the CPU in a branch loop to wait for a defined number of bus clocks. Freescale Semiconductor MC9S12Q128 Rev 1.10 247 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.5.1.3 Step 3 Configure how many conversions you want to perform in one sequence and define other settings in ATDCTL3. Example: Write S4C=1 to do 4 conversions per sequence. 8.5.1.4 Step 4 Configure resolution, sampling time and ATD clock speed in ATDCTL4. Example: Use default for resolution and sampling time by leaving SRES8, SMP1 and SMP0 clear. For a bus clock of 40MHz write 9 to PR4-0, this gives an ATD clock of 0.5*40MHz/(9+1) = 2MHz which is within the allowed range for fATDCLK. 8.5.1.5 Step 5 Configure starting channel, single/multiple channel, continuous or single sequence and result data format in ATDCTL5. Writing ATDCTL5 will start the conversion, so make sure your write ATDCTL5 in the last step. Example: Leave CC,CB,CA clear to start on channel AN0. Write MULT=1 to convert channel AN0 to AN3 in a sequence (4 conversion per sequence selected in ATDCTL3). 8.5.2 8.5.2.1 Aborting an A/D conversion Step 1 Disable the ATD Interrupt by writing ASCIE=0 in ATDCTL2. This will also abort any ongoing conversion sequence. It is important to clear the interrupt enable at this point, prior to step 3, as depending on the device clock gating it may not always be possible to clear it or the SCF flag once the module is disabled (ADPU=0). 8.5.2.2 Step 2 Clear the SCF flag by writing a 1 in ATDSTAT0. (Remaining flags will be cleared with the next start of a conversions, but SCF flag should be cleared to avoid SCF interrupt.) 8.5.2.3 Step 3 Power down ATD by writing ADPU=0 in ATDCTL2. 8.6 Resets At reset the ATD10B8C is in a power down state. The reset state of each individual bit is listed within Section 8.3.2, “Register Descriptions” which details the registers and their bit-field. 248 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 8.7 Interrupts The interrupt requested by the ATD10B8C is listed in Table 8-20. Refer to MCU specification for related vector address and priority. Table 8-20. ATD10B8C Interrupt Vectors Interrupt Source Sequence complete interrupt CCR Mask I bit Local Enable ASCIE in ATDCTL2 See Section 8.3.2, “Register Descriptions” for further details. Freescale Semiconductor MC9S12Q128 Rev 1.10 249 Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description 250 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.1 Introduction This specification describes the function of the clocks and reset generator (CRGV4). 9.1.1 Features The main features of this block are: • Phase-locked loop (PLL) frequency multiplier — Reference divider — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — CPU interrupt on entry or exit from locked condition — Self-clock mode in absence of reference clock • System clock generator — Clock quality check — Clock switch for either oscillator- or PLL-based system clocks — User selectable disabling of clocks during wait mode for reduced power consumption • Computer operating properly (COP) watchdog timer with time-out clear window • System reset generation from the following possible sources: — Power-on reset — Low voltage reset Refer to the device overview section for availability of this feature. — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12Q128 Rev 1.10 251 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value. • Wait mode This mode allows to disable the system and core clocks depending on the configuration of the individual bits in the CLKSEL register. • Stop mode Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode (PSTP = 0) and pseudo-stop mode (PSTP = 1). — Full stop mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. — Pseudo-stop mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set the COP and RTI will continue to run, else they remain frozen. • Self-clock mode Self-clock mode will be entered if the clock monitor enable bit (CME) and the self-clock mode enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of clock. As soon as self-clock mode is entered the CRGV4 starts to perform a clock quality check. Self-clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). Self-clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 9.1.3 Block Diagram Figure 9-1 shows a block diagram of the CRGV4. 252 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Voltage Regulator Power-on Reset Low Voltage Reset 1 CRG RESET COP Timeout XCLKS EXTAL XTAL Clock Monitor CM fail Reset Generator Clock Quality Checker COP RTI System Reset OSCCLK Oscillator Bus Clock Core Clock Oscillator Clock Registers XFC VDDPLL VSSPLL PLLCLK PLL Clock and Reset Control Real-Time Interrupt PLL Lock Interrupt Self-Clock Mode Interrupt 1 Refer to the device overview section for availability of the low-voltage reset feature. Figure 9-1. CRG Block Diagram 9.2 External Signal Description This section lists and describes the signals that connect off chip. 9.2.1 VDDPLL, VSSPLL — PLL Operating Voltage, PLL Ground These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required VDDPLL and VSSPLL must be connected properly. 9.2.2 XFC — PLL Loop Filter Pin A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter to eliminate the VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be tied to VDDPLL. Freescale Semiconductor MC9S12Q128 Rev 1.10 253 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description VDDPLL CS MCU RS CP XFC Figure 9-2. PLL Loop Filter Connections 9.2.3 RESET — Reset Pin RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered. 9.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the CRGV4. 9.3.1 Module Memory Map Table 9-1 gives an overview on all CRGV4 registers. Table 9-1. CRGV4 Memory Map Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A CRG Synthesizer Register (SYNR) CRG Reference Divider Register (REFDV) CRG Test Flags Register (CTFLG)(1) CRG Flags Register (CRGFLG) CRG Interrupt Enable Register (CRGINT) CRG Clock Select Register (CLKSEL) CRG PLL Control Register (PLLCTL) CRG RTI Control Register (RTICTL) CRG COP Control Register (COPCTL) CRG Force and Bypass Test Register CRG Test Control Register (FORBYP)(2) (CTCTL)(3) Use Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x000B CRG COP Arm/Timer Reset (ARMCOP) 1. CTFLG is intended for factory test purposes only. 2. FORBYP is intended for factory test purposes only. 3. CTCTL is intended for factory test purposes only. 254 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description NOTE Register address = base address + address offset, where the base address is defined at the MCU level and the address offset is defined at the module level. 9.3.2 Register Descriptions This section describes in address order all the CRGV4 registers and their individual bits. Register Name 0x0000 SYNR 0x0001 REFDV 0x0002 CTFLG 0x0003 CRGFLG 0x0004 CRGINT 0x0005 CLKSEL 0x0006 PLLCTL 0x0007 RTICTL 0x0008 COPCTL 0x0009 FORBYP 0x000A CTCTL R W R W R W R W R W R W R W R W R W R W R W = Unimplemented or Reserved 0 0 0 0 0 0 0 0 WCOP 0 RTIF PORF 0 LVRF 0 LOCKIF LOCK TRACK SCMIF SCM 0 0 0 0 0 0 Bit 7 0 6 0 5 SYN5 0 4 SYN4 0 3 SYN3 2 SYN2 1 SYN1 Bit 0 SYN0 REFDV3 0 REFDV2 0 REFDV1 0 REFDV0 0 RTIE LOCKIE 0 0 SCMIE 0 PLLSEL PSTP SYSWAI ROAWAI PLLWAI 0 CWAI RTIWAI COPWAI CME 0 PLLON AUTO ACQ PRE PCE SCME RTR6 RTR5 0 RTR4 0 RTR3 0 RTR2 RTR1 RTR0 RSBCK 0 CR2 0 CR1 0 CR0 0 0 0 0 Figure 9-3. CRG Register Summary Freescale Semiconductor MC9S12Q128 Rev 1.10 255 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Register Name 0x000B ARMCOP R W Bit 7 0 Bit 7 6 0 Bit 6 5 0 Bit 5 4 0 Bit 4 3 0 Bit 3 2 0 Bit 2 1 0 Bit 1 Bit 0 0 Bit 0 = Unimplemented or Reserved Figure 9-3. CRG Register Summary (continued) 9.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (fSCM). ( SYNR + 1 ) PLLCLK = 2xOSCCLKx --------------------------------( REFDV + 1 ) NOTE If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2 Bus Clock must not exceed the maximum operating system frequency. Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset 0 0 SYN5 SYNR 0 SYN3 0 SYN2 0 SYN1 0 SYN0 0 0 0 0 = Unimplemented or Reserved Figure 9-4. CRG Synthesizer Register (SYNR) Read: anytime Write: anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit. 256 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.2 CRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1. Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 REFDV3 REFDV2 0 REFDV1 0 REFDV0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-5. CRG Reference Divider Register (REFDV) Read: anytime Write: anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit. 9.3.2.3 Reserved Register (CTFLG) This register is reserved for factory testing of the CRGV4 module and is not available in normal modes. Module Base + 0x0002 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-6. CRG Reserved Register (CTFLG) Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRGV4 functionality. Freescale Semiconductor MC9S12Q128 Rev 1.10 257 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.4 CRG Flags Register (CRGFLG) This register provides CRG status bits and flags. Module Base + 0x0003 7 6 5 4 3 2 1 0 R RTIF W Reset 0 Note 1 Note 2 0 PORF LVRF LOCKIF LOCK TRACK SCMIF SCM 0 0 0 0 1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved Figure 9-7. CRG Flag Register (CRGFLG) Read: anytime Write: refer to each bit for individual write conditions Table 9-2. CRGFLG Field Descriptions Field 7 RTIF Description Real-Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. Power-on Reset Flag — PORF is set to 1 when a power-on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power-on reset has not occurred. 1 Power-on reset has occurred. Low-Voltage Reset Flag — If low voltage reset feature is not available (see the device overview chapter), LVRF always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self-clock mode. Writes have no effect. 0 PLL VCO is not within the desired tolerance of the target frequency. 1 PLL VCO is within the desired tolerance of the target frequency. Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode. Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status. 6 PORF 5 LVRF 4 LOCKIF 3 LOCK 2 TRACK 258 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-2. CRGFLG Field Descriptions (continued) Field 1 SCMIF Description Self-Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self-Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect. 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self-clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency fSCM. 0 SCM 9.3.2.5 CRG Interrupt Enable Register (CRGINT) This register enables CRG interrupt requests. Module Base + 0x0004 7 6 5 4 3 2 1 0 R RTIE W Reset 0 0 0 LOCKIE 0 0 SCMIE 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-8. CRG Interrupt Enable Register (CRGINT) Read: anytime Write: anytime Table 9-3. CRGINT Field Descriptions Field 7 RTIE 4 LOCKIE 1 SCMIE Description Real-Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Self-Clock Mode Interrupt Enable Bit 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set. Freescale Semiconductor MC9S12Q128 Rev 1.10 259 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.6 CRG Clock Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 9-17 for details on the effect of each bit. Module Base + 0x0005 7 6 5 4 3 2 1 0 R PLLSEL W Reset 0 0 0 0 0 0 0 0 PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI Figure 9-9. CRG Clock Select Register (CLKSEL) Read: anytime Write: refer to each bit for individual write conditions Table 9-4. CLKSEL Field Descriptions Field 7 PLLSEL Description PLL Select Bit — Write anytime. Writing a 1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters self-clock mode, stop mode or wait mode with PLLWAI bit set. 0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2). 1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2). Pseudo-Stop Bit — Write: anytime — This bit controls the functionality of the oscillator during stop mode. 0 Oscillator is disabled in stop mode. 1 Oscillator continues to run in stop mode (pseudo-stop). The oscillator amplitude is reduced. Refer to oscillator block description for availability of a reduced oscillator amplitude. Note: Pseudo-stop allows for faster stop recovery and reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly increased power consumption. Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susceptibility (EMS) tests. System Clocks Stop in Wait Mode Bit — Write: anytime 0 In wait mode, the system clocks continue to run. 1 In wait mode, the system clocks stop. Note: RTI and COP are not affected by SYSWAI bit. Reduced Oscillator Amplitude in Wait Mode Bit — Write: anytime — Refer to oscillator block description chapter for availability of a reduced oscillator amplitude. If no such feature exists in the oscillator block then setting this bit to 1 will not have any effect on power consumption. 0 Normal oscillator amplitude in wait mode. 1 Reduced oscillator amplitude in wait mode. Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susceptibility (EMS) tests. PLL Stops in Wait Mode Bit — Write: anytime — If PLLWAI is set, the CRGV4 will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during wait mode but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be set manually if PLL clock is required. While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting wait mode. 0 PLL keeps running in wait mode. 1 PLL stops in wait mode. 6 PSTP 5 SYSWAI 4 ROAWAI 3 PLLWAI 260 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-4. CLKSEL Field Descriptions (continued) Field 2 CWAI 1 RTIWAI 0 COPWAI Core Stops in Wait Mode Bit — Write: anytime 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode. RTI Stops in Wait Mode Bit — Write: anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode. COP Stops in Wait Mode Bit — Normal modes: Write once —Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP dividers whenever the part goes into wait mode. Description 9.3.2.7 CRG PLL Control Register (PLLCTL) This register controls the PLL functionality. Module Base + 0x0006 7 6 5 4 3 2 1 0 R CME W Reset 1 1 1 1 PLLON AUTO ACQ 0 PRE 0 0 PCE 0 SCME 1 = Unimplemented or Reserved Figure 9-10. CRG PLL Control Register (PLLCTL) Read: anytime Write: refer to each bit for individual write conditions Table 9-5. PLLCTL Field Descriptions Field 7 CME Description Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock mode. Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause unpredictable operation of the MCU. Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss of clock will not be detected. Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1. 0 PLL is turned off. 1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically. 6 PLLON Freescale Semiconductor MC9S12Q128 Rev 1.10 261 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-5. PLLCTL Field Descriptions (continued) Field 5 AUTO Description Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect. 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. RTI Enable during Pseudo-Stop Bit — PRE enables the RTI during pseudo-stop mode. Write anytime. 0 RTI stops running during pseudo-stop mode. 1 RTI continues running during pseudo-stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo-stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set. COP Enable during Pseudo-Stop Bit — PCE enables the COP during pseudo-stop mode. Write anytime. 0 COP stops running during pseudo-stop mode 1 COP continues running during pseudo-stop mode Note: If the PCE bit is cleared the COP dividers will go static while pseudo-stop mode is active. The COP dividers will not initialize like in wait mode with COPWAI bit set. Self-Clock Mode Enable Bit — Normal modes: Write once —Special modes: Write anytime — SCME can not be cleared while operating in self-clock mode (SCM=1). 0 Detection of crystal clock failure causes clock monitor reset (see Section 9.5.1, “Clock Monitor Reset”). 1 Detection of crystal clock failure forces the MCU in self-clock mode (see Section 9.4.7.2, “Self-Clock Mode”). 4 ACQ 2 PRE 1 PCE 0 SCME 9.3.2.8 CRG RTI Control Register (RTICTL) This register selects the timeout period for the real-time interrupt. Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset 0 RTR6 0 0 RTR5 0 RTR4 0 RTR3 0 RTR2 0 RTR1 0 RTR0 0 = Unimplemented or Reserved Figure 9-11. CRG RTI Control Register (RTICTL) Read: anytime Write: anytime NOTE A write to this register initializes the RTI counter. 262 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-6. RTICTL Field Descriptions Field 6:4 RTR[6:4] 3:0 RTR[3:0] Description Real-Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 9-7. Real-Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity. Table 9-7 shows all possible divide values selectable by the RTICTL register. The source clock for the RTI is OSCCLK. Table 9-7. RTI Frequency Divide Rates RTR[6:4] = RTR[3:0] 000 (OFF) OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* 001 (210) 210 2x210 3x210 4x210 5x210 6x210 7x210 8x210 9x210 10x210 11x210 12x210 13x210 14x210 15x210 16x210 010 (211) 211 2x211 3x211 4x211 5x211 6x211 7x211 8x211 9x211 10x211 11x211 12x211 13x211 14x211 15x211 16x211 011 (212) 212 2x212 3x212 4x212 5x212 6x212 7x212 8x212 9x212 10x212 11x212 12x212 13x212 14x212 15x212 16x212 100 (213) 213 2x213 3x213 4x213 5x213 6x213 7x213 8x213 9x213 10x213 11x213 12x213 13x213 14x213 15x213 16x213 101 (214) 214 2x214 3x214 4x214 5x214 6x214 7x214 8x214 9x214 10x214 11x214 12x214 13x214 14x214 15x214 16x214 110 (215) 215 2x215 3x215 4x215 5x215 6x215 7x215 8x215 9x215 10x215 11x215 12x215 13x215 14x215 15x215 16x215 111 (216) 216 2x216 3x216 4x216 5x216 6x216 7x216 8x216 9x216 10x216 11x216 12x216 13x216 14x216 15x216 16x216 0000 (÷1) 0001 (÷2) 0010 (÷3) 0011 (÷4) 0100 (÷5) 0101 (÷6) 0110 (÷7) 0111 (÷8) 1000 (÷9) 1001 (÷10) 1010 (÷11) 1011 (÷12) 1100 (÷ 13) 1101 (÷14) 1110 (÷15) 1111 (÷ 16) * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor MC9S12Q128 Rev 1.10 263 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.9 CRG COP Control Register (COPCTL) This register controls the COP (computer operating properly) watchdog. Module Base + 0x0008 7 6 5 4 3 2 1 0 R WCOP W Reset 0 0 RSBCK 0 0 0 CR2 CR1 0 CR0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-12. CRG COP Control Register (COPCTL) Read: anytime Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode Write: RSBCK: once Table 9-8. COPCTL Field Descriptions Field 7 WCOP Description Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, 0x0055 can be written as often as desired. As soon as 0x00AA is written after the 0x0055, the timeout logic restarts and the user must wait until the next window before writing to ARMCOP. Table 9-9 shows the exact duration of this window for the seven available COP rates. 0 Normal COP operation 1 Window COP operation COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode. COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 9-9). The COP timeout period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register. 6 RSBCK 2:0 CR[2:0] Table 9-9. COP Watchdog Rates(1) CR2 CR1 CR0 OSCCLK Cycles to Time Out 0 0 0 COP disabled 0 0 1 214 0 1 0 216 0 1 1 218 1 0 0 220 1 0 1 222 1 1 0 223 1 1 1 224 1. OSCCLK cycles are referenced from the previous COP time-out reset (writing 0x0055/0x00AA to the ARMCOP register) 264 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. Module Base + 0x0009 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-13. Reserved Register (FORBYP) Read: always read 0x0000 except in special modes Write: only in special modes 9.3.2.11 Reserved Register (CTCTL) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special test modes can alter the CRG’s functionality. Module Base + 0x000A 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-14. Reserved Register (CTCTL) Read: always read 0x0080 except in special modes Write: only in special modes Freescale Semiconductor MC9S12Q128 Rev 1.10 265 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Module Base + 0x000B 7 6 5 4 3 2 1 0 R W Reset 0 Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 Figure 9-15. ARMCOP Register Diagram Read: always reads 0x0000 Write: anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than 0x0055 or 0x00AA causes a COP reset. To restart the COP time-out period you must write 0x0055 followed by a write of 0x00AA. Other instructions may be executed between these writes but the sequence (0x0055, 0x00AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of 0x0055 writes or sequences of 0x00AA writes are allowed. When the WCOP bit is set, 0x0055 and 0x00AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset. 9.4 Functional Description This section gives detailed informations on the internal operation of the design. 9.4.1 Phase Locked Loop (PLL) The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register. [ SYNR + 1 ] PLLCLK = 2 × OSCCLK × --------------------------------[ REFDV + 1 ] CAUTION Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. If (PLLSEL = 1), Bus Clock = PLLCLK / 2 266 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency fSCM. REFERENCE EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL OSCCLK REFDV FEEDBACK LOCK DETECTOR LOCK REFERENCE PROGRAMMABLE DIVIDER VDDPLL/VSSPLL PDET PHASE DETECTOR UP DOWN CPUMP VCO CRYSTAL MONITOR LOOP PROGRAMMABLE DIVIDER SYN VDDPLL LOOP FILTER XFC PIN PLLCLK supplied by: VDDPLL/VSSPLL VDD/VSS Figure 9-16. PLL Functional Diagram 9.4.1.1 PLL Operation The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 16 (REFDV+1) to output the reference clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR +1)] to output the feedback clock. See Figure 9-16. The phase detector then compares the feedback clock, with the reference clock. Correction pulses are generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the next subsection. The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL. 9.4.1.2 Acquisition and Tracking Modes The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor MC9S12Q128 Rev 1.10 267 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The PLL filter can be manually or automatically configured into one of two possible operating modes: • Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register. • Tracking mode In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as the source for the system and core clocks. If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1): • The TRACK bit is a read-only indicator of the mode of the filter. • The TRACK bit is set when the VCO frequency is within a certain tolerance, ∆trk, and is clear when the VCO frequency is out of a certain tolerance, ∆unt. • The LOCK bit is a read-only indicator of the locked state of the PLL. • The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared when the VCO frequency is out of a certain tolerance, ∆unl. • CPU interrupts can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode. • After turning on the PLL by setting the PLLON bit software must wait a given time (tacq) before entering tracking mode (ACQ = 0). • After entering tracking mode software must wait a given time (tal) before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1). 268 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.4.2 System Clocks Generator PLLSEL or SCM WAIT(CWAI,SYSWAI), STOP PHASE LOCK LOOP PLLCLK 1 0 SYSCLK Core Clock WAIT(SYSWAI), STOP SCM WAIT(RTIWAI), STOP(PSTP,PRE), RTI enable ÷2 CLOCK PHASE GENERATOR Bus Clock EXTAL OSCILLATOR OSCCLK 1 RTI 0 XTAL WAIT(COPWAI), STOP(PSTP,PCE), COP enable Clock Monitor WAIT(SYSWAI), STOP Oscillator Clock COP STOP(PSTP) Gating Condition = Clock Gate Oscillator Clock (running during Pseudo-Stop Mode Figure 9-17. System Clocks Generator The clock generator creates the clocks used in the MCU (see Figure 9-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self-clock mode (see Section 9.4.7.2, “Self-Clock Mode”), oscillator clock source is switched to PLLCLK running at its minimum frequency fSCM. The bus clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU. The core clock is twice the bus clock as shown in Figure 9-18. But note that a CPU cycle corresponds to one bus clock. PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum Freescale Semiconductor MC9S12Q128 Rev 1.10 269 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. CORE CLOCK: BUS CLOCK / ECLK Figure 9-18. Core Clock and Bus Clock Relationship 9.4.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The CRGV4 then asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME control bit. 9.4.4 Clock Quality Checker The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker provides a more accurate check in addition to the clock monitor. A clock quality check is triggered by any of the following events: • Power-on reset (POR) • Low voltage reset (LVR) • Wake-up from full stop mode (exit full stop) • Clock monitor fail indication (CM fail) A time window of 50000 VCO clock cycles1 is called check window. A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See Figure 9-19 as an example. check window 1 2 3 49999 50000 VCO clock OSCCLK 12345 4096 4095 osc ok Figure 9-19. Check Window Example 1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM. 270 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The sequence for clock quality check is shown in Figure 9-20. CM fail Clock OK POR LVR exit full stop Clock Monitor Reset Enter SCM num=0 yes no SCM active? num=50 check window num=num+1 yes yes no SCME=1 ? no osc ok ? yes SCM active? no no num No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock failure --> Scenario 1: OSCCLK recovers prior to exiting Wait Mode. – MCU remains in Wait Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., – SCM deactivated, – PLL disabled depending on PLLWAI, – VREG remains enabled (never gets disabled in Wait Mode). – MCU remains in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit Wait Mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit Wait Mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting Wait Mode. – MCU remains in Wait Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag, – Keep performing Clock Quality Checks (could continue infinitely) while in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. CRG Actions Freescale Semiconductor MC9S12Q128 Rev 1.10 277 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-11. Outcome of Clock Loss in Wait Mode (continued) CME 1 SCME 1 SCMIE 1 Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. CRG Actions 9.4.10 Low-Power Operation in Stop Mode All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo-stop mode. In addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual power-saving modes (if available). This is the main difference between pseudo-stop mode and wait mode. After executing the STOP instruction the core requests the CRG to switch the MCU into stop mode. If the PLLSEL bit remains set when entering stop mode, the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active. If pseudo-stop mode (PSTP = 1) is entered from self-clock mode the CRG will continue to check the clock quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If full stop mode (PSTP = 0) is entered from self-clock mode an ongoing clock quality check will be stopped. A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit. 278 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Core req’s Stop Mode. Clear PLLSEL, Disable PLL Exit Stop w. ext.RESET Wait Mode left due to external Enter Stop Mode no INT ? no PSTP=1 ? yes CME=1 ? no INT ? no yes yes CM fail ? yes no no Clock OK ? Exit Stop w. CMRESET no SCME=1 ? yes yes Exit Stop w. CMRESET yes no SCME=1 ? yes SCMIE=1 ? Generate SCM Interrupt (Wakeup from Stop) no Exit Stop Mode yes Exit Stop Mode SCM=1 ? Exit Stop Mode Exit Stop Mode no yes Enter SCM Enter SCM Enter SCM Continue w. normal OP Figure 9-24. Stop Mode Entry/Exit Sequence 9.4.10.1 Wake-Up from Pseudo-Stop (PSTP=1) Wake-up from pseudo-stop is the same as wake-up from wait mode. There are also three different scenarios for the CRG to restart the MCU from pseudo-stop mode: • • • External reset Clock monitor fail Wake-up interrupt Freescale Semiconductor MC9S12Q128 Rev 1.10 279 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and the MCU is in run mode again. If the clock monitor is enabled (CME = 1) the MCU is able to leave pseudo-stop mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (see Section 9.4.4, “Clock Quality Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo-stop mode. If any other interrupt source (e.g. RTI) triggers exit from pseudo-stop mode the MCU immediately continues with normal operation. Because the PLL has been powered-down during stop mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 9-12 summarizes the outcome of a clock loss while in pseudo-stop mode. 280 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-12. Outcome of Clock Loss in Pseudo-Stop Mode CME 0 1 1 SCME X 0 1 SCMIE X X 0 Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode. – MCU remains in Pseudo-Stop Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., – SCM deactivated, – PLL disabled, – VREG disabled. – MCU remains in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit Pseudo-Stop Mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit Pseudo-Stop Mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting Pseudo-Stop Mode. – MCU remains in Pseudo-Stop Mode, – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – Set SCMIF interrupt flag, – Keep performing Clock Quality Checks (could continue infinitely) while in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock – Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. CRG Actions Freescale Semiconductor MC9S12Q128 Rev 1.10 281 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Table 9-12. Outcome of Clock Loss in Pseudo-Stop Mode (continued) CME 1 SCME 1 SCMIE 1 Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start Clock Quality Check, – SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. – Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. CRG Actions 9.4.10.2 Wake-up from Full Stop (PSTP=0) The MCU requires an external interrupt or an external reset in order to wake-up from stop mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 9.4.4, “Clock Quality Checker”). After completing the clock quality check the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Full stop mode is exited and the MCU is in run mode again. If the MCU is woken-up by an interrupt, the CRG will also perform a maximum of 50 clock check_windows (see Section 9.4.4, “Clock Quality Checker”). If the clock quality check is successful, the CRG will release all system and core clocks and will continue with normal operation. If all clock checks within the timeout-window are failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending on the setting of the SCME bit. Because the PLL has been powered-down during stop mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. NOTE In full stop mode, the clock monitor is disabled and any loss of clock will not be detected. 9.5 Resets This section describes how to reset the CRGV4 and how the CRGV4 itself controls the reset of the MCU. It explains all special reset requirements. Because the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 9.3, “Memory Map and Register 282 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Definition.” All reset sources are listed in Table 9-13. Refer to the device overview chapter for related vector addresses and priorities. Table 9-13. Reset Summary Reset Source Power-on Reset Low Voltage Reset External Reset Clock Monitor Reset COP Watchdog Reset Local Enable None None None PLLCTL (CME=1, SCME=0) COPCTL (CR[2:0] nonzero) The reset sequence is initiated by any of the following events: • • • • • Low level is detected at the RESET pin (external reset). Power on is detected. Low voltage is detected. COP watchdog times out. Clock monitor failure is detected and self-clock mode was disabled (SCME = 0). Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see Figure 9-25). Because entry into reset is asynchronous it does not require a running SYSCLK. However, the internal reset circuit of the CRGV4 cannot sequence out of current reset condition without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the RESET pin is released. The reset generator of the CRGV4 waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Table 9-14 shows which vector will be fetched. Table 9-14. Reset Vector Selection Sampled RESET Pin (64 Cycles After Release) 1 1 1 0 Clock Monitor Reset Pending 0 1 0 X COP Reset Pending 0 X 1 X Vector Fetch POR / LVR / External Reset Clock Monitor Reset COP Reset POR / LVR / External Reset with rise of RESET pin NOTE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. Freescale Semiconductor MC9S12Q128 Rev 1.10 283 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too. RESET )( )( RESET pin released CRG drives RESET pin low SYSCLK ) ( 128+n cycles possibly SYSCLK not running with n being min 3 / max 6 cycles depending on internal synchronization delay ) ( 64 cycles ) ( possibly RESET driven low externally Figure 9-25. RESET Timing 9.5.1 • • • Clock Monitor Reset Clock monitor is enabled (CME=1) Loss of clock is detected Self-clock mode is disabled (SCME=0) The CRGV4 generates a clock monitor reset in case all of the following conditions are true: The reset event asynchronously forces the configuration registers to their default settings (see Section 9.3, “Memory Map and Register Definition”). In detail the CME and the SCME are reset to logical ‘1’ (which doesn’t change the state of the CME bit, because it has already been set). As a consequence, the CRG immediately enters self-clock mode and starts its internal reset sequence. In parallel the clock quality check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and leaves self-clock mode. Because the clock quality checker is running in parallel to the reset generator, the CRG may leave self-clock mode while completing the internal reset sequence. When the reset sequence is finished the CRG checks the internally latched state of the clock monitor fail circuit. If a clock monitor fail is indicated processing begins by fetching the clock monitor reset vector. 9.5.2 Computer Operating Properly Watchdog (COP) Reset When COP is enabled, the CRG expects sequential write of 0x0055 and 0x00AA (in this order) to the ARMCOP register during the selected time-out period. As soon as this is done, the COP time-out period restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x0055 or 0x00AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled 284 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 9 Clocks and Reset Generator (CRGV4) Block Description writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector. 9.5.3 Power-On Reset, Low Voltage Reset The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts poweron reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode. Figure 9-26 and Figure 9-27 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low. RESET Clock Quality Check (no Self-Clock Mode) )( Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 9-26. RESET Pin Tied to VDD (by a Pull-Up Resistor) RESET Clock Quality Check (no Self-Clock Mode) )( Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 9-27. RESET Pin Held Low Externally Freescale Semiconductor MC9S12Q128 Rev 1.10 285 Chapter 9 Clocks and Reset Generator (CRGV4) Block Description 9.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 9-15. Refer to the device overview chapter for related vector addresses and priorities. Table 9-15. CRG Interrupt Vectors Interrupt Source Real-time interrupt LOCK interrupt SCM interrupt CCR Mask I bit I bit I bit Local Enable CRGINT (RTIE) CRGINT (LOCKIE) CRGINT (SCMIE) 9.6.1 Real-Time Interrupt The CRGV4 generates a real-time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to 0. The real-time interrupt flag (RTIF) is set to 1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during pseudo-stop mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from pseudo-stop if the RTI interrupt is enabled. 9.6.2 PLL Lock Interrupt The CRGV4 generates a PLL lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit. 9.6.3 Self-Clock Mode Interrupt The CRGV4 generates a self-clock mode interrupt when the SCM condition of the system has changed, either entered or exited self-clock mode. SCM conditions can only change if the self-clock mode enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power-on reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details on the clock quality check refer to Section 9.4.4, “Clock Quality Checker.” If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1). SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to 1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit. 286 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1 Introduction Freescale’s scalable controller area network (S12MSCANV2) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software. 10.1.1 Glossary ACK: Acknowledge of CAN message CAN: Controller Area Network CRC: Cyclic Redundancy Code EOF: End of Frame FIFO: First-In-First-Out Memory IFS: Inter-Frame Sequence SOF: Start of Frame CPU bus: CPU related read/write data bus CAN bus: CAN protocol related serial bus oscillator clock: Direct clock from external oscillator bus clock: CPU bus realated clock CAN clock: CAN protocol related clock Freescale Semiconductor MC9S12Q128 Rev 1.10 287 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1.2 Block Diagram MSCAN Oscillator Clock Bus Clock CANCLK MUX Presc. Tq Clk Receive/ Transmit Engine RXCAN TXCAN Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Wake-Up Interrupt Req. Control and Status Message Filtering and Buffering Configuration Registers Wake-Up Low Pass Filter Figure 10-1. MSCAN Block Diagram 10.1.3 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mbps1 — Support for remote frames • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization using a “local priority” concept • Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters • Programmable wakeup functionality with integrated low-pass filter • Programmable loopback mode supports self-test operation • Programmable listen-only mode for monitoring of CAN bus • Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) • Programmable MSCAN clock source either bus clock or oscillator clock • Internal timer for time-stamping of received and transmitted messages • Three low-power modes: sleep, power down, and MSCAN enable • Global initialization of configuration registers 1. Depending on the actual bit timing and the clock jitter of the PLL. 288 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.1.4 Modes of Operation The following modes of operation are specific to the MSCAN. See Section 10.4, “Functional Description,” for details. • Listen-Only Mode • MSCAN Sleep Mode • MSCAN Initialization Mode • MSCAN Power Down Mode 10.2 External Signal Description The MSCAN uses two external pins: 10.2.1 RXCAN — CAN Receiver Input Pin RXCAN is the MSCAN receiver input pin. 10.2.2 TXCAN — CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state 10.2.3 CAN System A typical CAN system with MSCAN is shown in Figure 10-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations. CAN node 1 MCU CAN Controller (MSCAN) CAN node 2 CAN node n TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure 10-2. CAN System Freescale Semiconductor MC9S12Q128 Rev 1.10 289 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 10.3.1 Module Memory Map Figure 10-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The detailed register descriptions follow in the order they appear in the register map. 290 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Register Name 0x0000 CANCTL0 0x0001 CANCTL1 0x0002 CANBTR0 0x0003 CANBTR1 0x0004 CANRFLG 0x0005 CANRIER 0x0006 CANTFLG 0x0007 CANTIER 0x0008 CANTARQ 0x0009 CANTAAK 0x000A CANTBSEL 0x000B CANIDAC 0x000C–0x000D Reserved 0x000E CANRXERR 0x000F CANTXERR R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 6 RXACT 5 4 SYNCH 3 2 1 Bit 0 RXFRM CSWAI TIME WUPE SLPRQ SLPAK INITRQ INITAK CANE CLKSRC LOOPB LISTEN WUPM SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 SAMP TSEG22 TSEG21 RSTAT1 TSEG20 RSTAT0 TSEG13 TSTAT1 TSEG12 TSTAT0 TSEG11 TSEG10 WUPIF CSCIF OVRIF RXF WUPIE 0 CSCIE 0 RSTATE1 0 RSTATE0 0 TSTATE1 0 TSTATE0 OVRIE RXFIE TXE2 TXE1 TXE0 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 0 0 0 0 0 ABTRQ2 ABTAK2 ABTRQ1 ABTAK1 ABTRQ0 ABTAK0 0 0 0 0 0 0 0 0 0 0 TX2 IDHIT2 TX1 IDHIT1 TX0 IDHIT0 0 0 IDAM1 0 IDAM0 0 0 0 0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 = Unimplemented or Reserved u = Unaffected Figure 10-3. MSCAN Register Summary Freescale Semiconductor MC9S12Q128 Rev 1.10 291 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Register Name 0x0010–0x0013 CANIDAR0–3 0x0014–0x0017 CANIDMRx 0x0018–0x001B CANIDAR4–7 0x001C–0x001F CANIDMR4–7 0x0020–0x002F CANRXFG 0x0030–0x003F CANTXFG R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 See Section 10.3.3, “Programmer’s Model of Message Storage” See Section 10.3.3, “Programmer’s Model of Message Storage” = Unimplemented or Reserved u = Unaffected Figure 10-3. MSCAN Register Summary (continued) 10.3.2 Register Descriptions This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read. 10.3.2.1 MSCAN Control Register 0 (CANCTL0) The CANCTL0 register provides various control bits of the MSCAN module as described below. Module Base + 0x0000 7 6 5 4 3 2 1 0 R RXFRM W Reset: 0 RXACT CSWAI 0 = Unimplemented 0 SYNCH TIME 0 0 WUPE 0 SLPRQ 0 INITRQ 1 Figure 10-4. MSCAN Control Register 0 (CANCTL0) 292 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode). Table 10-1. CANCTL0 Register Field Descriptions Field 7 RXFRM(1) Description Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this flag 1 A valid message was received since last clearing of this flag Receiver Active Status — This read-only flag indicates the MSCAN is receiving a message. The flag is controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle2 1 MSCAN is receiving a message (including when arbitration is lost)(2) CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode Synchronized Status — This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 10.3.3, “Programmer’s Model of Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode when traffic on CAN is detected (see Section 10.4.5.4, “MSCAN Sleep Mode”). 0 Wake-up disabled — The MSCAN ignores traffic on CAN 1 Wake-up enabled — The MSCAN is able to restart 6 RXACT 5 CSWAI(3) 4 SYNCH 3 TIME 2 WUPE(4) Freescale Semiconductor MC9S12Q128 Rev 1.10 293 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-1. CANCTL0 Register Field Descriptions (continued) Field 1 SLPRQ(5) Description Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (see Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ cannot be set while the WUPIF flag is set (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running — The MSCAN functions normally 1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle 0 Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see INITRQ(6),(7) Section 10.4.5.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). The following registers enter their hard reset state and restore their default values: CANCTL0(8), CANRFLG(9), CANRIER(10), CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0. 0 Normal operation 1 MSCAN in initialization mode 1. The MSCAN must be in normal mode for this bit to become set. 2. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states. 3. In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the CPU enters wait (CSWAI = 1) or stop mode (see Section 10.4.5.2, “Operation in Wait Mode” and Section 10.4.5.3, “Operation in Stop Mode”). 4. The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 5. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 6. The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 7. In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 8. Not including WUPE, INITRQ, and SLPRQ. 9. TSTAT1 and TSTAT0 are not affected by initialization mode. 10. RSTAT1 and RSTAT0 are not affected by initialization mode. 10.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. 294 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x0001 7 6 5 4 3 2 1 0 R CANE W Reset: 0 0 0 1 0 0 CLKSRC LOOPB LISTEN WUPM SLPAK INITAK 0 1 = Unimplemented Figure 10-5. MSCAN Control Register 1 (CANCTL1) Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). Table 10-2. CANCTL1 Register Field Descriptions Field 7 CANE 6 CLKSRC MSCAN Enable 0 MSCAN module is disabled 1 MSCAN module is enabled MSCAN Clock Source — This bit defines the clock source for the MSCAN module (only for systems with a clock generation module; Section 10.4.3.2, “Clock System,” and Section Figure 10-42., “MSCAN Clocking Scheme,”). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. 0 Loopback self test disabled 1 Loopback self test enabled Listen Only Mode — This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section 10.4.4.4, “Listen-Only Mode”). In addition, the error counters are frozen. Listen only mode supports applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 10.4.5.4, “MSCAN Sleep Mode”). 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup Description 5 LOOPB 4 LISTEN 2 WUPM Freescale Semiconductor MC9S12Q128 Rev 1.10 295 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-2. CANCTL1 Register Field Descriptions (continued) Field 1 SLPAK Description Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the flag if it detects activity on the CAN bus while in sleep mode. 0 Running — The MSCAN operates normally 1 Sleep mode active — The MSCAN has entered sleep mode Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode (see Section 10.4.5.5, “MSCAN Initialization Mode”). It is used as a handshake flag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running — The MSCAN operates normally 1 Initialization mode active — The MSCAN has entered initialization mode 0 INITAK 296 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0002 7 6 5 4 3 2 1 0 R SJW1 W Reset: 0 0 0 0 0 0 0 0 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Figure 10-6. MSCAN Bus Timing Register 0 (CANBTR0) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-3. CANBTR0 Register Field Descriptions Field 7:6 SJW[1:0] 5:0 BRP[5:0] Description Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 10-4). Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 10-5). Table 10-4. Synchronization Jump Width SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles Table 10-5. Baud Rate Prescaler BRP5 0 0 0 0 : 1 BRP4 0 0 0 0 : 1 BRP3 0 0 0 0 : 1 BRP2 0 0 0 0 : 1 BRP1 0 0 1 1 : 1 BRP0 0 1 0 1 : 1 Prescaler value (P) 1 2 3 4 : 64 Freescale Semiconductor MC9S12Q128 Rev 1.10 297 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module. Module Base + 0x0003 7 6 5 4 3 2 1 0 R SAMP W Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Figure 10-7. MSCAN Bus Timing Register 1 (CANBTR1) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-6. CANBTR1 Register Field Descriptions Field 7 SAMP Description Sampling — This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit. 1 Three samples per bit(1). If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0). 6:4 Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG2[2:0] of the sample point (see Figure 10-43). Time segment 2 (TSEG2) values are programmable as shown in Table 10-7. 3:0 Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 10-43). Time segment 1 (TSEG1) values are programmable as shown in Table 10-8. 1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). Table 10-7. Time Segment 2 Values TSEG22 0 0 : 1 TSEG21 0 0 : 1 TSEG20 0 1 : 0 Time Segment 2 1 Tq clock cycle(1) 2 Tq clock cycles : 7 Tq clock cycles 1 1 1 8 Tq clock cycles 1. This setting is not valid. Please refer to Table 10-34 for valid settings. 298 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-8. Time Segment 1 Values TSEG13 0 0 0 0 : 1 TSEG12 0 0 0 0 : 1 TSEG11 0 0 1 1 : 1 TSEG10 0 1 0 1 : 0 Time segment 1 1 Tq clock cycle(1) 2 Tq clock cycles1 3 Tq clock cycles1 4 Tq clock cycles : 15 Tq clock cycles 1 1 1 1 16 Tq clock cycles 1. This setting is not valid. Please refer to Table 10-34 for valid settings. The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 10-7 and Table 10-8). Eqn. 10-1 ( Prescaler value ) Bit Time = ----------------------------------------------------- • ( 1 + TimeSegment1 + TimeSegment2 ) f CANCLK 10.3.2.5 MSCAN Receiver Flag Register (CANRFLG) A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register. Module Base + 0x0004 7 6 5 4 3 2 1 0 R WUPIF W Reset: 0 0 CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF 0 0 0 0 0 0 = Unimplemented Figure 10-8. MSCAN Receiver Flag Register (CANRFLG) NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are readonly; write of 1 clears flag; write of 0 is ignored. 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. Freescale Semiconductor MC9S12Q128 Rev 1.10 299 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-9. CANRFLG Register Field Descriptions Field 7 WUPIF Description Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 10.4.5.4, “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status 6 CSCIF 5:4 Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As RSTAT[1:0] soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is: 00 RxOK: 0 ≤ receive error counter ≤ 96 01 RxWRN: 96 < receive error counter ≤ 127 10 RxERR: 127 < receive error counter 11 Bus-off(1): transmit error counter > 255 3:2 Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. TSTAT[1:0] As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK: 0 ≤ transmit error counter ≤ 96 01 TxWRN: 96 < transmit error counter ≤ 127 10 TxERR: 127 < transmit error counter ≤ 255 11 Bus-Off: transmit error counter > 255 1 OVRIF Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this flag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG 1. Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2. To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition. 0 RXF(2) 300 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER) This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register. Module Base + 0x0005 7 6 5 4 3 2 1 0 R WUPIE W Reset: 0 0 0 0 0 0 0 0 CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Figure 10-9. MSCAN Receiver Interrupt Enable Register (CANRIER) NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode Table 10-10. CANRIER Register Field Descriptions Field 7 WUPIE(1) 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request. 5:4 Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state RSTATE[1:0] changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”(2) state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 3:2 Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. Freescale Semiconductor MC9S12Q128 Rev 1.10 301 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-10. CANRIER Register Field Descriptions (continued) Field 1 OVRIE 0 RXFIE Description Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request. 1. WUPIE and WUPE (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery mechanism from stop or wait is required. 2. Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 10.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register. Module Base + 0x0006 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 TXE2 TXE1 1 TXE0 1 0 0 0 0 0 1 = Unimplemented Figure 10-10. MSCAN Transmitter Flag Register (CANTFLG) NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored 302 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-11. CANTFLG Register Field Descriptions Field 2:0 TXE[2:0] Description Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 10.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). When listen-mode is active (see Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx flags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled) 10.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt flags. Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 TXEIE2 TXEIE1 0 TXEIE0 0 0 0 0 0 0 0 = Unimplemented Figure 10-11. MSCAN Transmitter Interrupt Enable Register (CANTIER) NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table 10-12. CANTIER Register Field Descriptions Field 2:0 TXEIE[2:0] Description Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. Freescale Semiconductor MC9S12Q128 Rev 1.10 303 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ) The CANTARQ register allows abort request of queued messages as described below. Module Base + 0x0008 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 ABTRQ2 ABTRQ1 0 ABTRQ0 0 0 0 0 0 0 0 = Unimplemented Figure 10-12. MSCAN Transmitter Message Abort Request Register (CANTARQ) NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table 10-13. CANTARQ Register Field Descriptions Field Description 2:0 Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge flags (ABTAK, see Section 10.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE flag is set. 0 No abort request 1 Abort request pending 304 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Module Base + 0x0009 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). Read: Anytime Write: Unimplemented for ABTAKx flags Table 10-14. CANTAAK Register Field Descriptions Field Description 2:0 Abort Acknowledge — This flag acknowledges that a message was aborted due to a pending abort request ABTAK[2:0] from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted. Freescale Semiconductor MC9S12Q128 Rev 1.10 305 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. Module Base + 0x000A 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 TX2 TX1 0 TX0 0 0 0 0 0 0 0 = Unimplemented Figure 10-14. MSCAN Transmit Buffer Selection Register (CANTBSEL) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode Table 10-15. CANTBSEL Register Field Descriptions Field 2:0 TX[2:0] Description Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. • LDD CANTFLG; value read is 0b0000_0110 • STD CANTBSEL; value written is 0b0000_0110 • LDD CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers. 306 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identifier acceptance control as described below. Module Base + 0x000B 7 6 5 4 3 2 1 0 R W Reset: 0 0 IDAM1 IDAM0 0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 0 0 0 = Unimplemented Figure 10-15. MSCAN Identifier Acceptance Control Register (CANIDAC) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are readonly Table 10-16. CANIDAC Register Field Descriptions Field 5:4 IDAM[1:0] 2:0 IDHIT[2:0] Description Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 10.4.3, “Identifier Acceptance Filter”). Table 10-17 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded. Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see Section 10.4.3, “Identifier Acceptance Filter”). Table 10-18 summarizes the different settings. Table 10-17. Identifier Acceptance Mode Settings IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Two 32-bit acceptance filters Four 16-bit acceptance filters Eight 8-bit acceptance filters Filter closed Table 10-18. Identifier Acceptance Hit Indication IDHIT2 0 0 0 0 1 1 1 1 IDHIT1 0 0 1 1 0 0 1 1 IDHIT0 0 1 0 1 0 1 0 1 Identifier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit Freescale Semiconductor MC9S12Q128 Rev 1.10 307 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well. 10.3.2.13 MSCAN Reserved Registers These registers are reserved for factory testing of the MSCAN module and is not available in normal system operation modes. Module Base + 0x000C, 0x000D 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-16. MSCAN Reserved Registers Read: Always read 0x0000 in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality. 10.3.2.14 MSCAN Receive Error Counter (CANRXERR) This register reflects the status of the MSCAN receive error counter. Module Base + 0x000E 7 6 5 4 3 2 1 0 R W Reset: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-17. MSCAN Receive Error Counter (CANRXERR) Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented 308 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. 10.3.2.15 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter. Module Base + 0x000F 7 6 5 4 3 2 1 0 R W Reset: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-18. MSCAN Transmit Error Counter (CANTXERR) Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. Freescale Semiconductor MC9S12Q128 Rev 1.10 309 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.16 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 10.3.3.1, “Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 10.4.3, “Identifier Acceptance Filter”). For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1, CANIDMR0/1) are applied. Module Base + 0x0010 (CANIDAR0) 0x0011 (CANIDAR1) 0x0012 (CANIDAR2) 0x0013 (CANIDAR3) 7 6 5 4 3 2 1 0 R W Reset AC7 0 7 AC6 0 6 AC5 0 5 AC4 0 4 AC3 0 3 AC2 0 2 AC1 0 1 AC0 0 0 R W Reset AC7 0 7 AC6 0 6 AC5 0 5 AC4 0 4 AC3 0 3 AC2 0 2 AC1 0 1 AC0 0 0 R W Reset AC7 0 7 AC6 0 6 AC5 0 5 AC4 0 4 AC3 0 3 AC2 0 2 AC1 0 1 AC0 0 0 R W Reset AC7 0 AC6 0 AC5 0 AC4 0 AC3 0 AC2 0 AC1 0 AC0 0 Figure 10-19. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-19. CANIDAR0–CANIDAR3 Register Field Descriptions Field 7:0 AC[7:0] Description Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. 310 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x0018 (CANIDAR4) 0x0019 (CANIDAR5) 0x001A (CANIDAR6) 0x001B (CANIDAR7) 7 6 5 4 3 2 1 0 R W Reset AC7 0 7 AC6 0 6 AC5 0 5 AC4 0 4 AC3 0 3 AC2 0 2 AC1 0 1 AC0 0 0 R W Reset AC7 0 7 AC6 0 6 AC5 0 5 AC4 0 4 AC3 0 3 AC2 0 2 AC1 0 1 AC0 0 0 R W Reset AC7 0 7 AC6 0 6 AC5 0 5 AC4 0 4 AC3 0 3 AC2 0 2 AC1 0 1 AC0 0 0 R W Reset AC7 0 AC6 0 AC5 0 AC4 0 AC3 0 AC2 0 AC1 0 AC0 0 Figure 10-20. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-20. CANIDAR4–CANIDAR7 Register Field Descriptions Field 7:0 AC[7:0] Description Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. Freescale Semiconductor MC9S12Q128 Rev 1.10 311 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.2.17 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.” To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.” Module Base + 0x0014 (CANIDMR0) 0x0015 (CANIDMR1) 0x0016 (CANIDMR2) 0x0017 (CANIDMR3) 7 6 5 4 3 2 1 0 R W Reset AM7 0 7 AM6 0 6 AM5 0 5 AM4 0 4 AM3 0 3 AM2 0 2 AM1 0 1 AM0 0 0 R W Reset AM7 0 7 AM6 0 6 AM5 0 5 AM4 0 4 AM3 0 3 AM2 0 2 AM1 0 1 AM0 0 0 R W Reset AM7 0 7 AM6 0 6 AM5 0 5 AM4 0 4 AM3 0 3 AM2 0 2 AM1 0 1 AM0 0 0 R W Reset AM7 0 AM6 0 AM5 0 AM4 0 AM3 0 AM2 0 AM1 0 AM0 0 Figure 10-21. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-21. CANIDMR0–CANIDMR3 Register Field Descriptions Field 7:0 AM[7:0] Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit 312 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7) 7 6 5 4 3 2 1 0 R W Reset AM7 0 7 AM6 0 6 AM5 0 5 AM4 0 4 AM3 0 3 AM2 0 2 AM1 0 1 AM0 0 0 R W Reset AM7 0 7 AM6 0 6 AM5 0 5 AM4 0 4 AM3 0 3 AM2 0 2 AM1 0 1 AM0 0 0 R W Reset AM7 0 7 AM6 0 6 AM5 0 5 AM4 0 4 AM3 0 3 AM2 0 2 AM1 0 1 AM0 0 0 R W Reset AM7 0 AM6 0 AM5 0 AM4 0 AM3 0 AM2 0 AM1 0 AM0 0 Figure 10-22. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-22. CANIDMR4–CANIDMR7 Register Field Descriptions Field 7:0 AM[7:0] Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit Freescale Semiconductor MC9S12Q128 Rev 1.10 313 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.3 Programmer’s Model of Message Storage The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. Table 10-23. Message Buffer Organization Offset Address 0x00X0 0x00X1 0x00X2 0x00X3 0x00X4 0x00X5 0x00X6 0x00X7 0x00X8 0x00X9 0x00XA 0x00XB 0x00XC 0x00XD 0x00XE Identifier Register 0 Identifier Register 1 Identifier Register 2 Identifier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Transmit Buffer Priority Register(1) Time Stamp Register (High Byte)(2) Register Access 0x00XF Time Stamp Register (Low Byte)(3) 1. Not applicable for receive buffers 2. Read-only for CPU 3. Read-only for CPU Figure 10-23 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 10-24. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1. Exception: The transmit priority registers are 0 out of reset. 314 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Register Name 0x00X0 IDR0 0x00X1 IDR1 0x00X2 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLR R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 ID28 6 ID27 5 ID26 4 ID25 3 ID24 2 ID23 1 ID22 Bit0 ID21 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 = Unused, always read ‘x’ Figure 10-23. Receive/Transmit Message Buffer — Extended Identifier Mapping Read: For transmit buffers, anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only when RXF flag is set (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Freescale Semiconductor MC9S12Q128 Rev 1.10 315 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Write: For transmit buffers, anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for receive buffers. Reset: Undefined (0x00XX) because of RAM-based implementation Register Name IDR0 0x00X0 IDR1 0x00X1 IDR2 0x00X2 IDR3 0x00X3 R W R W R W R W Bit 7 ID10 6 ID9 5 ID8 4 ID7 3 ID6 2 ID5 1 ID4 Bit 0 ID3 ID2 ID1 ID0 RTR IDE (=0) = Unused, always read ‘x’ Figure 10-24. Receive/Transmit Message Buffer — Standard Identifier Mapping 10.3.3.1 Identifier Registers (IDR0–IDR3) The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE, and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0], RTR, and IDE bits. 10.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping Module Base + 0x00X1 7 6 5 4 3 2 1 0 R ID28 W Reset: x x x x x x x x ID27 ID26 ID25 ID24 ID23 ID22 ID21 Figure 10-25. Identifier Register 0 (IDR0) — Extended Identifier Mapping Table 10-24. IDR0 Register Field Descriptions — Extended Field 7:0 ID[28:21] Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. 316 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X1 7 6 5 4 3 2 1 0 R ID20 W Reset: x x x x x x x x ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 Figure 10-26. Identifier Register 1 (IDR1) — Extended Identifier Mapping Table 10-25. IDR1 Register Field Descriptions — Extended Field 7:5 ID[20:18] 4 SRR 3 IDE Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Substitute Remote Request — This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. 2:0 ID[17:15] Module Base + 0x00X2 7 6 5 4 3 2 1 0 R ID14 W Reset: x x x x x x x x ID13 ID12 ID11 ID10 ID9 ID8 ID7 Figure 10-27. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 10-26. IDR2 Register Field Descriptions — Extended Field 7:0 ID[14:7] Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Freescale Semiconductor MC9S12Q128 Rev 1.10 317 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X3 7 6 5 4 3 2 1 0 R ID6 W Reset: x x x x x x x x ID5 ID4 ID3 ID2 ID1 ID0 RTR Figure 10-28. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 10-27. IDR3 Register Field Descriptions — Extended Field 7:1 ID[6:0] 0 RTR Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Remote Transmission Request — This flag reflects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame 10.3.3.1.2 IDR0–IDR3 for Standard Identifier Mapping Module Base + 0x00X0 7 6 5 4 3 2 1 0 R ID10 W Reset: x x x x x x x x ID9 ID8 ID7 ID6 ID5 ID4 ID3 Figure 10-29. Identifier Register 0 — Standard Mapping Table 10-28. IDR0 Register Field Descriptions — Standard Field 7:0 ID[10:3] Description Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 10-29. 318 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X1 7 6 5 4 3 2 1 0 R ID2 W Reset: x x x x x x x x ID1 ID0 RTR IDE (=0) = Unused; always read ‘x’ Figure 10-30. Identifier Register 1 — Standard Mapping Table 10-29. IDR1 Register Field Descriptions Field 7:5 ID[2:0] 4 RTR Description Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 10-28. Remote Transmission Request — This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) 3 IDE Module Base + 0x00X2 7 6 5 4 3 2 1 0 R W Reset: x x x x x x x x = Unused; always read ‘x’ Figure 10-31. Identifier Register 2 — Standard Mapping Freescale Semiconductor MC9S12Q128 Rev 1.10 319 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Module Base + 0x00X3 7 6 5 4 3 2 1 0 R W Reset: x x x x x x x x = Unused; always read ‘x’ Figure 10-32. Identifier Register 3 — Standard Mapping 10.3.3.2 Data Segment Registers (DSR0-7) The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register. Module Base + 0x0004 (DSR0) 0x0005 (DSR1) 0x0006 (DSR2) 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7) 7 6 5 4 3 2 1 0 R DB7 W Reset: x x x x x x x x DB6 DB5 DB4 DB3 DB2 DB1 DB0 Figure 10-33. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table 10-30. DSR0–DSR7 Register Field Descriptions Field 7:0 DB[7:0] Data bits 7:0 Description 320 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. Module Base + 0x00XB 7 6 5 4 3 2 1 0 R DLC3 W Reset: x x x x x x x x DLC2 DLC1 DLC0 = Unused; always read “x” Figure 10-34. Data Length Register (DLR) — Extended Identifier Mapping Table 10-31. DLR Register Field Descriptions Field 3:0 DLC[3:0] Description Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 10-32 shows the effect of setting the DLC bits. Table 10-32. Data Length Codes Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8 10.3.3.4 Transmit Buffer Priority Register (TBPR) This register defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: • All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. • The transmission buffer with the lowest local priority field wins the prioritization. Freescale Semiconductor MC9S12Q128 Rev 1.10 321 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. Module Base + 0xXXXD 7 6 5 4 3 2 1 0 R PRIO7 W Reset: 0 0 0 0 0 0 0 0 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 Figure 10-35. Transmit Buffer Priority Register (TBPR) Read: Anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). 10.3.3.5 Time Stamp Register (TSRH–TSRL) If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers. Module Base + 0xXXXE 7 6 5 4 3 2 1 0 R W Reset: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 x x x x x x x x Figure 10-36. Time Stamp Register — High Byte (TSRH) Module Base + 0xXXXF 7 6 5 4 3 2 1 0 R W Reset: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 x x x x x x x x Figure 10-37. Time Stamp Register — Low Byte (TSRL) 322 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Read: Anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented 10.4 10.4.1 Functional Description General This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction. Freescale Semiconductor MC9S12Q128 Rev 1.10 323 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.2 Message Storage CAN Receive / Transmit Engine CPU12 Memory Mapped I/O Rx0 Rx1 Rx2 Rx3 Rx4 RXF RxBG MSCAN Receiver Tx0 RxFG CPU bus TXE0 TxBG Tx1 PRIO TXE1 TxFG MSCAN CPU bus PRIO Tx2 TXE2 Transmitter TxBG PRIO Figure 10-38. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 324 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. • The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the “local priority” concept described in Section 10.4.2.2, “Transmit Structures.” 10.4.2.2 Transmit Structures The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 10-38. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 10.3.3, “Programmer’s Model of Message Storage”). An additional Section 10.3.3.4, “Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (see Section 10.3.3.4, “Transmit Buffer Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a message, if required (see Section 10.3.3.5, “Time Stamp Register (TSRH–TSRL)”). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section 10.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag. Freescale Semiconductor MC9S12Q128 Rev 1.10 325 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 10.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”.) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0). 10.4.2.3 Receive Structures The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (see Figure 10-38). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 10-38). This scheme simplifies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (see Section 10.3.3, “Programmer’s Model of Message Storage”). The receiver full flag (RXF) (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”) signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identifier, this flag is set. On reception, each message is checked to see whether it passes the filter (see Section 10.4.3, “Identifier Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO2, sets the RXF flag, and generates a receive interrupt (see Section 10.4.7.3, “Receive Interrupt”) to the CPU3. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF flag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. 326 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers and another message is correctly received from the CAN bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 10.4.7.5, “Error Interrupt”). The MSCAN remains able to transmit messages while the receiver FIFO being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted. 10.4.3 Identifier Acceptance Filter The MSCAN identifier acceptance registers (see Section 10.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”) define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identifier mask registers (see Section 10.3.2.17, “MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)”). A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits in the CANIDAC register (see Section 10.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more filters match), the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes (see Bosch CAN 2.0A/B protocol specification): • Two identifier acceptance filters, each to be applied to: — The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame: – Remote transmission request (RTR) – Identifier extension (IDE) – Substitute remote request (SRR) — The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages1. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Figure 10-39 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit. • Four identifier acceptance filters, each to be applied to 1. Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers Freescale Semiconductor MC9S12Q128 Rev 1.10 327 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) • • — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 10-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits. Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier. Figure 10-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 4 to 7 hits. Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set. IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3 CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 0 Hit) Figure 10-39. 32-bit Maskable Identifier Acceptance Filter 328 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) CAN 2.0B Extended Identifier CAN 2.0A/B Standard Identifier ID28 ID10 IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 10-40. 16-bit Maskable Identifier Acceptance Filters Freescale Semiconductor MC9S12Q128 Rev 1.10 329 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10 IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3 AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID Accepted (Filter 0 Hit) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID Accepted (Filter 1 Hit) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID Accepted (Filter 2 Hit) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID Accepted (Filter 3 Hit) Figure 10-41. 8-bit Maskable Identifier Acceptance Filters 330 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) serve as a lock to protect the following registers: — MSCAN control 1 register (CANCTL1) — MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) — MSCAN identifier acceptance control register (CANIDAC) — MSCAN identifier acceptance registers (CANIDAR0–CANIDAR7) — MSCAN identifier mask registers (CANIDMR0–CANIDMR7) • The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 10.4.5.6, “MSCAN Power Down Mode,” and Section 10.4.5.5, “MSCAN Initialization Mode”). • The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN. 10.4.3.2 Clock System Figure 10-42 shows the structure of the MSCAN clock generation circuitry. MSCAN Bus Clock CANCLK CLKSRC Prescaler (1 .. 64) Time quanta clock (Tq) CLKSRC Oscillator Clock Figure 10-42. MSCAN Clocking Scheme The clock source bit (CLKSRC) in the CANCTL1 register (10.3.2.2/10-294) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required. Freescale Semiconductor MC9S12Q128 Rev 1.10 331 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN. Eqn. 10-2 f CANCLK = ----------------------------------------------------Tq ( Prescaler value ) A bit time is subdivided into three segments as described in the Bosch CAN specification. (see Figure 1043): • SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. • Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. • Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. Eqn. 10-3 f Tq Bit Rate = -------------------------------------------------------------------------------( number of Time Quanta ) NRZ Signal SYNC_SEG Time Segment 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8 ... 25 Time Quanta = 1 Bit Time Time Segment 2 (PHASE_SEG2) 2 ... 8 1 Transmit Point Sample Point (single or triple sampling) Figure 10-43. Segments within the Bit Time 332 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-33. Time Segment Syntax Syntax SYNC_SEG Transmit Point Description System expects transitions to occur on the CAN bus during this period. A node in transmit mode transfers a new value to the CAN bus at this point. A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample. Sample Point The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (see Section 10.3.2.3, “MSCAN Bus Timing Register 0 (CANBTR0)” and Section 10.3.2.4, “MSCAN Bus Timing Register 1 (CANBTR1)”). Table 10-34 gives an overview of the CAN compliant segment settings and the related parameter values. NOTE It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. Table 10-34. CAN Standard Compliant Bit Time Segment Settings Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchronization Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3 10.4.4 10.4.4.1 Modes of Operation Normal Modes The MSCAN module behaves as described within this specification in all normal system operation modes. 10.4.4.2 Special Modes The MSCAN module behaves as described within this specification in all special system operation modes. Freescale Semiconductor MC9S12Q128 Rev 1.10 333 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification. 10.4.4.4 Listen-Only Mode In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmision. If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although the CAN bus may remain in recessive state externally. 10.4.4.5 Security Modes The MSCAN module has no security features. 10.4.5 Low-Power Options If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 10-35 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1). 334 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) Table 10-35. CPU vs. MSCAN Operating Modes MSCAN Mode CPU Mode Normal Sleep CSWAI = X(1) SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X Power Down Reduced Power Consumption Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X RUN WAIT STOP 1. ‘X’ means don’t care. 10.4.5.1 Operation in Run Mode As shown in Table 10-35, only MSCAN sleep mode is available as low power option when the CPU is in run mode. 10.4.5.2 Operation in Wait Mode The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts its internal controllers and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the lowpower modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 10-35. 10.4.5.3 Operation in Stop Mode The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits Table 10-35. 10.4.5.4 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity: Freescale Semiconductor MC9S12Q128 Rev 1.10 335 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) • • • If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode. Bus Clock Domain CAN Clock Domain SLPRQ Flag SLPRQ CPU Sleep Request SYNC sync. SLPRQ SLPAK Flag sync. SLPAK SYNC SLPAK MSCAN in Sleep Mode Figure 10-44. Sleep Request / Acknowledge Cycle NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 10-44). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. If the WUPE bit in CANCLT0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure 10-45). WUPE must be set before entering sleep mode to take effect. 336 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) The MSCAN is able to leave sleep mode (wake up) only when: • CAN bus activity occurs and WUPE = 1 or • the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits. CAN Activity StartUp Wait for Idle CAN Activity SLPRQ (CAN Activity & WUPE) | SLPRQ CAN Activity & SLPRQ Idle Sleep (CAN Activity & WUPE) | CAN Activity & SLPRQ CAN Activity CAN Activity Tx/Rx Message Active CAN Activity Figure 10-45. Simplified State Transitions for Entering/Leaving Sleep Mode Freescale Semiconductor MC9S12Q128 Rev 1.10 337 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.5.5 MSCAN Initialization Mode In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. See Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode. Bus Clock Domain CAN Clock Domain INIT Flag INITRQ CPU Init Request SYNC sync. INITRQ INITAK Flag sync. INITAK SYNC INITAK Figure 10-46. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Section Figure 10-46., “Initialization Request/Acknowledge Cycle”). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active. 338 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.5.6 MSCAN Power Down Mode The MSCAN is in power down mode (Table 10-35) when • CPU is in stop mode or • CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again. 10.4.5.7 Programmable Wake-Up Function The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see control bit WUPE in Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The sensitivity to existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line while in sleep mode (see control bit WUPM in Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from—for example—electromagnetic interference within noisy environments. 10.4.6 Reset Initialization The reset state of each individual bit is listed in Section 10.3.2, “Register Descriptions,” which details all the registers and their bit-fields. 10.4.7 Interrupts This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated flags. Each interrupt is listed and described separately. Freescale Semiconductor MC9S12Q128 Rev 1.10 339 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 10.4.7.1 Description of Interrupt Operation The MSCAN supports four interrupt vectors (see Table 10-36), any of which can be individually masked (for details see sections from Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER),” to Section 10.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter. Table 10-36. Interrupt Vectors Interrupt Source Wake-Up Interrupt (WUPIF) Error Interrupts Interrupt (CSCIF, OVRIF) Receive Interrupt (RXF) Transmit Interrupts (TXE[2:0]) CCR Mask I bit I bit I bit I bit Local Enable CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) 10.4.7.2 Transmit Interrupt At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set. 10.4.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer. 10.4.7.4 Wake-Up Interrupt A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode. WUPE (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must be enabled. 10.4.7.5 Error Interrupt An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: • Overrun — An overrun condition of the receiver FIFO as described in Section 10.4.2.3, “Receive Structures,” occurred. • CAN Status Change — The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rxwarning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see Section 10.3.2.5, 340 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) “MSCAN Receiver Flag Register (CANRFLG)” and Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). 10.4.7.6 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” or the Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG).” Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. 10.4.7.7 Recovery from Stop or Wait The MSCAN can recover from stop or wait via the wake-up interrupt. This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wakeup option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1). 10.5 10.5.1 Initialization/Application Information MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode and enter normal mode If the configuration of registers which are writable in initialization mode needs to be changed only when the MSCAN module is in normal mode: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode Freescale Semiconductor MC9S12Q128 Rev 1.10 341 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2) 342 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 11 Oscillator (OSCV2) Block Description 11.1 Introduction The OSCV2 module provides two alternative oscillator concepts: • A low noise and low power Colpitts oscillator with amplitude limitation control (ALC) • A robust full swing Pierce oscillator with the possibility to feed in an external square wave 11.1.1 Features The Colpitts OSCV2 option provides the following features: • Amplitude limitation control (ALC) loop: — Low power consumption and low current induced RF emission — Sinusoidal waveform with low RF emission — Low crystal stress (an external damping resistor is not required) — Normal and low amplitude mode for further reduction of power and emission • An external biasing resistor is not required The Pierce OSC option provides the following features: • Wider high frequency operation range • No DC voltage applied across the crystal • Full rail-to-rail (2.5 V nominal) swing oscillation with low EM susceptibility • Fast start up Common features: • Clock monitor (CM) • Operation from the VDDPLL 2.5 V (nominal) supply rail 11.1.2 Modes of Operation Two modes of operation exist: • Amplitude limitation controlled Colpitts oscillator mode suitable for power and emission critical applications • Full swing Pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequency operation and harsh environments Freescale Semiconductor MC9S12Q128 Rev 1.10 343 Chapter 11 Oscillator (OSCV2) Block Description 11.2 External Signal Description This section lists and describes the signals that connect off chip. 11.2.1 VDDPLL and VSSPLL — PLL Operating Voltage, PLL Ground These pins provide the operating voltage (VDDPLL) and ground (VSSPLL) for the OSCV2 circuitry. This allows the supply voltage to the OSCV2 to be independently bypassed. 11.2.2 EXTAL and XTAL — Clock/Crystal Source Pins These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. All the MCU internal system clocks are derived from the EXTAL input frequency. In full stop mode (PSTP = 0) the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The Crystal circuit is changed from standard. The Colpitts circuit is not suited for overtone resonators and crystals. EXTAL CDC* MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal. Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. C1 Crystal or Ceramic Resonator Figure 11-1. Colpitts Oscillator Connections (XCLKS = 0) NOTE The Pierce circuit is not suited for overtone resonators and crystals without a careful component selection. 344 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 11 Oscillator (OSCV2) Block Description EXTAL MCU RS* XTAL C4 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer’s data. C3 Crystal or Ceramic Resonator RB Figure 11-2. Pierce Oscillator Connections (XCLKS = 1) EXTAL MCU XTAL CMOS-Compatible External Oscillator (VDDPLL Level) Not Connected Figure 11-3. External Clock Connections (XCLKS = 1) 11.2.3 XCLKS — Colpitts/Pierce Oscillator Selection Signal The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether the Pierce oscillator/external clock circuitry is used. The XCLKS signal is sampled during reset with the rising edge of RESET. Table 11-1 lists the state coding of the sampled XCLKS signal. Refer to the device overview chapter for polarity of the XCLKS pin. Table 11-1. Clock Selection Based on XCLKS XCLKS 0 1 Description Colpitts oscillator selected Pierce oscillator/external clock selected Freescale Semiconductor MC9S12Q128 Rev 1.10 345 Chapter 11 Oscillator (OSCV2) Block Description 11.3 Memory Map and Register Definition The CRG contains the registers and associated bits for controlling and monitoring the OSCV2 module. 11.4 Functional Description The OSCV2 block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback. A buffered EXTAL signal, OSCCLK, becomes the internal reference clock. To improve noise immunity, the oscillator is powered by the VDDPLL and VSSPLL power supply pins. The Pierce oscillator can be used for higher frequencies compared to the low power Colpitts oscillator. 11.4.1 Amplitude Limitation Control (ALC) The Colpitts oscillator is equipped with a feedback system which does not waste current by generating harmonics. Its configuration is “Colpitts oscillator with translated ground.” The transconductor used is driven by a current source under the control of a peak detector which will measure the amplitude of the AC signal appearing on EXTAL node in order to implement an amplitude limitation control (ALC) loop. The ALC loop is in charge of reducing the quiescent current in the transconductor as a result of an increase in the oscillation amplitude. The oscillation amplitude can be limited to two values. The normal amplitude which is intended for non power saving modes and a small amplitude which is intended for low power operation modes. Please refer to the CRG block description chapter for the control and assignment of the amplitude value to operation modes. 11.4.2 Clock Monitor (CM) The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates a failure which asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function is enabled/disabled by the CME control bit, described in the CRG block description chapter. 11.5 Interrupts OSCV2 contains a clock monitor, which can trigger an interrupt or reset. The control bits and status bits for the clock monitor are described in the CRG block description chapter. 346 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.1 Introduction The pulse width modulation (PWM) definition is based on the HC12 PWM definitions. The PWM8B4C module contains the basic features from the HC11 with some of the enhancements incorporated on the HC12, that is center aligned output mode and four available clock sources. The PWM8B4C module has four channels with independent control of left and center aligned outputs on each channel. Each of the PWM channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs 12.1.1 • • • • • • • • • • Features Four independent PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Programmable PWM enable/disable for each channel Software selection of PWM duty pulse polarity for each channel Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches 0) or when the channel is disabled. Programmable center or left aligned outputs on individual channels Four 8-bit channel or two16-bit channel PWM resolution Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies. Programmable clock select logic Emergency shutdown 12.1.2 Modes of Operation There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. Freescale Semiconductor MC9S12Q128 Rev 1.10 347 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.1.3 Block Diagram PWM8B4C PWM Channels Bus Clock Clock Select PWM Clock Control Channel 3 Period and Duty Counter PWM3 Channel 2 Enable Period and Duty Counter PWM2 Polarity Channel 1 Period and Duty Counter PWM1 Alignment Channel 0 Period and Duty Counter PWM0 Figure 12-1. PWM8B4C Block Diagram 12.2 External Signal Description The PWM8B4C module has a total of four external pins. 12.2.1 PWM3 — Pulse Width Modulator Channel 3 Pin This pin serves as waveform output of PWM channel 3. 12.2.2 PWM2 — Pulse Width Modulator Channel 2 Pin This pin serves as waveform output of PWM channel 2. 12.2.3 PWM1 — Pulse Width Modulator Channel 1 Pin This pin serves as waveform output of PWM channel 1. 348 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.2.4 PWM0 — Pulse Width Modulator Channel 0 Pin This pin serves as waveform output of PWM channel 0. 12.3 Memory Map and Registers This subsection describes in detail all the registers and register bits in the PWM8B4C module. The special-purpose registers and register bit functions that would not normally be made available to device end users, such as factory test control registers and reserved registers are clearly identified by means of shading the appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions. 12.3.1 Module Memory Map The following paragraphs describe the content of the registers in the PWM8B4C module. The base address of the PWM8B4C module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. Table 12-2 shows the memory map for the PWM8B4C module. NOTE Register address = base address + address offset, where the base address is defined at the MCU level and the address offset is defined at the module level. Freescale Semiconductor MC9S12Q128 Rev 1.10 349 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2 Register Descriptions The following paragraphs describe in detail all the registers and register bits in the PWM8B4C module. Address 0x0000 0x0001 0x0002 Name PWME PWMPOL PWMCLK R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 0 0 0 0 0 0 0 0 0 6 0 0 0 5 4 3 PWME3 PPOL3 PCLK3 PCKB1 PCKB0 0 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 0x0003 PWMPRCLK 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 PWMCAE PWMCTL PWMTST PWMPRSC PWMSCLA PWMSCLB PCKB2 0 CAE2 CON23 0 0 CON01 0 0 PSWAI 0 0 Bit 7 Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 6 6 0 0 6 0 6 0 6 0 6 0 5 5 0 0 5 0 5 0 5 0 5 0 4 4 0 0 4 0 4 0 4 0 4 0 3 3 0 0 3 0 3 0 3 0 3 0 2 2 0 0 2 0 2 0 2 0 2 0 1 1 0 0 1 0 1 0 1 0 1 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 0x000A PWMSCNTA 0x000B PWMSCNTB 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 Reserved Reserved PWMPER0 Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 12-2. PWM Register Summary 350 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Address 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E Name PWMPER1 PWMPER2 PWMPER3 Reserved Reserved PWMDTY0 PWMPER1 PWMPER2 PWMPER3 Reserved Reserved PWMSDB R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 7 Bit 7 Bit 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 7 Bit 7 Bit 7 Bit 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 PWMIF PWMIE 0 PWMLVL PWMRSTRT 0 PWM5IN PWM5INL PWM5ENA = Unimplemented or Reserved Figure 12-2. PWM Register Summary (continued) 12.3.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The first PWM cycle after enabling the channel can be irregular. An exception to this is when channels are concatenated. After concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low-order PWMEx bit. In this case, the high-order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all PWM channels are disabled (PWME3–PWME0 = 0), the prescaler counter shuts off for power savings. Freescale Semiconductor MC9S12Q128 Rev 1.10 351 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset 0 0 PWME3 PWME2 0 PWME1 0 PWME0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-3. PWM Enable Register (PWME) Read: anytime Write: anytime Table 12-1. PWME Field Descriptions Field 3 PWME3 Description Pulse Width Channel 3 Enable 0 Pulse width channel 3 is disabled. 1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when its clock source begins its next cycle. Pulse Width Channel 2 Enable 0 Pulse width channel 2 is disabled. 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled. Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled. 2 PWME2 1 PWME1 0 PWME0 352 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.2 PWM Polarity Register (PWMPOL) The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is 1, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is 0 the output starts low and then goes high when the duty count is reached. Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset 0 0 PPOL3 PPOL2 0 PPOL1 0 PPOL0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-4. PWM Polarity Register (PWMPOL) Read: anytime Write: anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition Table 12-2. PWMPOL Field Descriptions Field 3 PPOL3 2 PPOL2 1 PPOL1 0 PPOL0 Description Pulse Width Channel 3 Polarity 0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached. Pulse Width Channel 2 Polarity 0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached. Pulse Width Channel 1 Polarity 0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached. Pulse Width Channel 0 Polarity 0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached 1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached. Freescale Semiconductor MC9S12Q128 Rev 1.10 353 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.3 PWM Clock Select Register (PWMCLK) Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below. Module Base + 0x0002 7 6 5 4 3 2 1 0 R W Reset 0 0 PCLK3 PCLK2 0 PCLK1 0 PCLK0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-5. PWM Clock Select Register (PWMCLK) Read: anytime Write: anytime NOTE Register bits PCLK0 to PCLK3 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 12-3. PWMCLK Field Descriptions Field 3 PCLK3 2 PCLK2 1 PCLK1 0 PCLK0 Description Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3. 1 Clock SB is the clock source for PWM channel 3. Pulse Width Channel 2 Clock Select 0 Clock B is the clock source for PWM channel 2. 1 Clock SB is the clock source for PWM channel 2. Pulse Width Channel 1 Clock Select 0 Clock A is the clock source for PWM channel 1. 1 Clock SA is the clock source for PWM channel 1. Pulse Width Channel 0 Clock Select 0 Clock A is the clock source for PWM channel 0. 1 Clock SA is the clock source for PWM channel 0. 354 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK) This register selects the prescale clock source for clocks A and B independently. Module Base + 0x0003 7 6 5 4 3 2 1 0 R W Reset 0 PCKB2 0 0 PCKB1 0 PCKB0 0 0 PCKA2 0 0 PCKA1 0 PCKA0 0 = Unimplemented or Reserved Figure 12-6. PWM Prescaler Clock Select Register (PWMPRCLK) Read: anytime Write: anytime NOTE PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime. If the clock prescale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 12-4. PWMPRCLK Field Descriptions Field 6–5 PCKB[2:0] 2–0 PCKA[2:0] Description Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These three bits determine the rate of clock B, as shown in Table 12-5. Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5. These three bits determine the rate of clock A, as shown in Table 12-6. Table 12-5. Clock B Prescaler Selects PCKB2 0 0 0 0 1 1 1 1 PCKB1 0 0 1 1 0 0 1 1 PCKB0 0 1 0 1 0 1 0 1 Value of Clock B Bus Clock Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 Freescale Semiconductor MC9S12Q128 Rev 1.10 355 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Table 12-6. Clock A Prescaler Selects PCKA2 0 0 0 0 1 1 1 1 PCKA1 0 0 1 1 0 0 1 1 PCKA0 0 1 0 1 0 1 0 1 Value of Clock A Bus Clock Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 12.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference Section 12.4.2.5, “Left Aligned Outputs,” and Section 12.4.2.6, “Center Aligned Outputs,” for a more detailed description of the PWM output modes. Module Base + 0x0004 7 6 5 4 3 2 1 0 R W Reset 0 0 CAE3 CAE2 0 CAE1 0 CAE0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-7. PWM Center Align Enable Register (PWMCAE) Read: anytime Write: anytime NOTE Write these bits only when the corresponding channel is disabled. Table 12-7. PWMCAE Field Descriptions Field 3 CAE3 2 CAE2 Description Center Aligned Output Mode on Channel 3 1 Channel 3 operates in left aligned output mode. 1 Channel 3 operates in center aligned output mode. Center Aligned Output Mode on Channel 2 0 Channel 2 operates in left aligned output mode. 1 Channel 2 operates in center aligned output mode. 356 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Table 12-7. PWMCAE Field Descriptions (continued) Field 1 CAE1 0 CAE0 Description Center Aligned Output Mode on Channel 1 0 Channel 1 operates in left aligned output mode. 1 Channel 1 operates in center aligned output mode. Center Aligned Output Mode on Channel 0 0 Channel 0 operates in left aligned output mode. 1 Channel 0 operates in center aligned output mode. 12.3.2.6 PWM Control Register (PWMCTL) The PWMCTL register provides for various control of the PWM module. Module Base + 0x0005 7 6 5 4 3 2 1 0 R W Reset 0 CON23 0 0 0 CON01 0 PSWAI 0 PFRZ 0 0 0 0 0 = Unimplemented or Reserved Figure 12-8. PWM Control Register (PWMCTL) Read: anytime Write: anytime There are control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. When channels 2 and 3 are concatenated, channel 2 registers become the high-order bytes of the double-byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high-order bytes of the double-byte channel. Reference Section 12.4.2.7, “PWM 16-Bit Functions,” for a more detailed description of the concatenation PWM function. NOTE Change these bits only when both corresponding channels are disabled. Freescale Semiconductor MC9S12Q128 Rev 1.10 357 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Table 12-8. PWMCTL Field Descriptions Field 5 CON23 Description Concatenate Channels 2 and 3 0 Channels 2 and 3 are separate 8-bit PWMs. 1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high-order byte and channel 3 becomes the low-order byte. Channel 3 output pin is used as the output for this 16-bit PWM (bit 3 of port PWMP). Channel 3 clock select control bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. Concatenate Channels 0 and 1 0 Channels 0 and 1 are separate 8-bit PWMs. 1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high-order byte and channel 1 becomes the low-order byte. Channel 1 output pin is used as the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 Allow the clock to the prescaler to continue while in wait mode. 1 Stop the input clock to the prescaler whenever the MCU is in wait mode. PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that after normal program flow is continued, the counters are re-enabled to simulate real-time operations. Because the registers remain accessible in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation. 4 CON01 3 PSWAI 2 PFRZ 358 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0006 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-9. Reserved Register (PWMTST) Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality. 12.3.2.8 Reserved Register (PWMPRSC) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-10. Reserved Register (PWMPRSC) Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality. Freescale Semiconductor MC9S12Q128 Rev 1.10 359 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.9 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Module Base + 0x0008 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 12-11. PWM Scale A Register (PWMSCLA) Read: anytime Write: anytime (causes the scale counter to load the PWMSCLA value) 12.3.2.10 PWM Scale B Register (PWMSCLB) PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock B / (2 * PWMSCLB) NOTE When PWMSCLB = 0x0000, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Module Base + 0x0009 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 12-12. PWM Scale B Register (PWMSCLB) Read: anytime Write: anytime (causes the scale counter to load the PWMSCLB value). 360 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.11 Reserved Registers (PWMSCNTx) The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes. Module Base + 0x000A 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-13. Reserved Register (PWMSCNTA) Module Base + 0x000B 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-14. Reserved Register (PWMSCNTB) Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality. 12.3.2.12 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register – 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is also cleared at the end of the effective period (see Section 12.4.2.5, “Left Aligned Outputs,” and Section 12.4.2.6, “Center Aligned Outputs,” for more details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more detailed information on the operation of the counters, reference Section 12.4.2.4, “PWM Timer Counters.” Freescale Semiconductor MC9S12Q128 Rev 1.10 361 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low- or high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. Module Base + 0x000C 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 12-15. PWM Channel Counter Registers (PWMCNT0) Module Base + 0x000D 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 12-16. PWM Channel Counter Registers (PWMCNT1) Module Base + 0x000E 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 12-17. PWM Channel Counter Registers (PWMCNT2) Module Base + 0x000F 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 12-18. PWM Channel Counter Registers (PWMCNT3) Read: anytime Write: anytime (any value written causes PWM counter to be reset to 0x0000). 362 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.13 PWM Channel Period Registers (PWMPERx) There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel. The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to 0x0000) • The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. Reference Section 12.4.2.3, “PWM Period and Duty,” for more information. To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel: • Left aligned output (CAEx = 0) • PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1) • PWMx period = channel clock period * (2 * PWMPERx) For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases.” Module Base + 0x0012 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 12-19. PWM Channel Period Registers (PWMPER0) Module Base + 0x0013 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 12-20. PWM Channel Period Registers (PWMPER1) Freescale Semiconductor MC9S12Q128 Rev 1.10 363 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Module Base + 0x0014 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 12-21. PWM Channel Period Registers (PWMPER2) Module Base + 0x0015 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 12-22. PWM Channel Period Registers (PWMPER3) Read: anytime Write: anytime 12.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to 0x0000) • The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. Reference Section 12.4.2.3, “PWM Period and Duty,” for more information. 364 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is 1, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. If the polarity bit is 0, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a % of period) for a particular channel: • Polarity = 0 (PPOLx = 0) Duty cycle = [(PWMPERx–PWMDTYx)/PWMPERx] * 100% • Polarity = 1 (PPOLx = 1) Duty cycle = [PWMDTYx / PWMPERx] * 100% • For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases.” Module Base + 0x0018 7 6 5 4 3 2 1 0 R W Reset Bit 7 1 6 1 5 1 4 1 3 1 2 1 1 1 Bit 0 1 Figure 12-23. PWM Channel Duty Registers (PWMDTY0) Module Base + 0x0019 7 6 5 4 3 2 1 0 R W Reset Bit 7 1 6 1 5 1 4 1 3 1 2 1 1 1 Bit 0 1 Figure 12-24. PWM Channel Duty Registers (PWMDTY1) Module Base + 0x001A 7 6 5 4 3 2 1 0 R W Reset Bit 7 1 6 1 5 1 4 1 3 1 2 1 1 1 Bit 0 1 Figure 12-25. PWM Channel Duty Registers (PWMDTY2) Module Base + 0x001B 7 6 5 4 3 2 1 0 R W Reset Bit 7 1 6 1 5 1 4 1 3 1 2 1 1 1 Bit 0 1 Figure 12-26. PWM Channel Duty Registers (PWMDTY3) Read: anytime Write: anytime Freescale Semiconductor MC9S12Q128 Rev 1.10 365 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. Module Base + 0x00E 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 PWM5ENA 0 0 0 0 = Unimplemented or Reserved Figure 12-27. PWM Shutdown Register (PWMSDN) Read: anytime Write: anytime Table 12-9. PWMSDN Field Descriptions Field 0 PWM Emergency Shutdown Enable PWM5ENA 0 PWM emergency feature disabled. 1 PWM emergency feature is enabled. Description CAUTION User Software must ensure that this bit remains clear 366 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.4 12.4.1 Functional Description PWM Clock Select There are four available clocks called clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 12-28 shows the four different clocks and how the scaled clocks are created. 12.4.1.1 Prescale The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all six PWM channels are disabled (PWME5–PWME0 = 0) This is useful for reducing power by disabling the prescale counter. Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value selected for clock A is determined by the PCKA2, PCKA1, and PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, and PCKB0 bits also in the PWMPRCLK register. Freescale Semiconductor MC9S12Q128 Rev 1.10 367 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Clock A M U X PCLK0 Clock to PWM Ch 0 Clock A/2, A/4, A/6,....A/512 PCKA2 PCKA1 PCKA0 Count = 1 Load PWMSCLA M U X PCLK2 M U X PCLK3 Clock B Clock to PWM Ch 3 DIV 2 Clock SA 8-Bit Down Counter M U X PCLK1 M U X Clock to PWM Ch 1 Clock to PWM Ch 2 Divide by Prescaler Taps: 4 8 16 32 64 128 Clock B/2, B/4, B/6,....B/512 M U X 8-Bit Down Counter Count = 1 Load PWMSCLB DIV 2 Clock SB 2 Bus Clock PFRZ FREEZE PWME5:0 PRESCALE PCKB2 PCKB1 PCKB0 SCALE CLOCK SELECT Figure 12-28. PWM Clock Select Block Diagram 368 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.4.1.2 Clock Scale The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches 1, two things happen; a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. NOTE Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register. NOTE Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = 0x0000, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. As an example, consider the case in which the user writes 0x00FF into the PWMSCLA register. Clock A for this case will be bus clock divided by 4. A pulse will occur at a rate of once every 255 x 4 bus cycles. Passing this through the divide by two circuit produces a clock signal at a bus clock divided by 2040 rate. Similarly, a value of 0x0001 in the PWMSCLA register when clock A is bus clock divided by 4 will produce a bus clock divided by 8 rate. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to 0x0001 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs. Freescale Semiconductor MC9S12Q128 Rev 1.10 369 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.4.1.3 Clock Select Each PWM channel has the capability of selecting one of two clocks. For channels 0, and 1 the clock choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. 12.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8 bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Figure 12-29 shows a block diagram for PWM timer. Clock Source 8-Bit Counter GATE (clock edge sync) 8-Bit Compare = T PWMDTYx R 8-Bit Compare = PWMPERx PPOLx Q Q PWMCNTx From Port PWMP Data Register up/down reset M U X M U X To Pin Driver Q Q T R CAEx PWMEx Figure 12-29. PWM Timer Channel Block Diagram 370 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.4.2.1 PWM Enable Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 12.4.2.7, “PWM 16-Bit Functions,” for more detail. NOTE The first PWM cycle after enabling the channel can be irregular. On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. 12.4.2.2 PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip-flop. When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is 0, the output starts low and then goes high when the duty count is reached. 12.4.2.3 PWM Period and Duty Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to 0x0000) • The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, because the counter is readable it is possible to know where the count is with respect to the duty value and software can be used to make adjustments. NOTE When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. Freescale Semiconductor MC9S12Q128 Rev 1.10 371 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.4.2.4 PWM Timer Counters Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (reference Figure 12-28 for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 12-29. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 12-29 and described in Section 12.4.2.5, “Left Aligned Outputs,” and Section 12.4.2.6, “Center Aligned Outputs.” Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to resume when the channel is re-enabled. When the channel is disabled, writing 0 to the period register will cause the counter to reset on the next selected clock. NOTE If the user wants to start a new “clean” PWM waveform without any “history” from the old waveform, the user must write to channel counter (PWMCNTx) prior to enabling the PWM channel (PWMEx = 1). Generally, writes to the counter are done prior to enabling a channel to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled except that the new period is started immediately with the output set according to the polarity bit. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. The counter is cleared at the end of the effective period (see Section 12.4.2.5, “Left Aligned Outputs,” and Section 12.4.2.6, “Center Aligned Outputs,” for more details). Table 12-10. PWM Timer Counter Conditions Counter Clears (0x0000) When PWMCNTx register written to any value Effective period ends Counter Counts When PWM channel is enabled (PWMEx = 1). Counts from last value in PWMCNTx. Counter Stops When PWM channel is disabled (PWMEx = 0) 372 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.4.2.5 Left Aligned Outputs The PWM timer provides the choice of two types of outputs, left aligned or center aligned outputs. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and a period register as shown in the block diagram in Figure 12-29. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop as shown in Figure 12-29 as well as performing a load from the double buffer period and duty register to the associated registers as described in Section 12.4.2.3, “PWM Period and Duty.” The counter counts from 0 to the value in the period register – 1. NOTE Changing the PWM output mode from left aligned output to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 12-30. PWM Left Aligned Output Waveform To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel. • PWMx frequency = clock (A, B, SA, or SB) / PWMPERx • PWMx duty cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock source = bus clock, where bus clock = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx frequency = 10 MHz/4 = 2.5 MHz PWMx period = 400 ns PWMx duty cycle = 3/4 *100% = 75% Freescale Semiconductor MC9S12Q128 Rev 1.10 373 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Shown below is the output waveform generated. E = 100 ns DUTY CYCLE = 75% PERIOD = 400 ns Figure 12-31. PWM Left Aligned Output Example Waveform 12.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to 0x0000. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 12-29. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state. When the PWM counter decrements and reaches 0, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed as described in Section 12.4.2.3, “PWM Period and Duty.” The counter counts from 0 up to the value in the period register and then back down to 0. Thus the effective period is PWMPERx*2. NOTE Changing the PWM output mode from left aligned output to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx PWMPERx Period = PWMPERx*2 PWMDTYx PWMPERx Figure 12-32. PWM Center Aligned Output Waveform 374 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel. • PWMx frequency = clock (A, B, SA, or SB) / (2*PWMPERx) • PWMx duty cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty cycle = [PWMDTYx / PWMPERx] * 100% As an example of a center aligned output, consider the following case: Clock source = bus clock, where bus clock = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx frequency = 10 MHz/8 = 1.25 MHz PWMx period = 800 ns PWMx duty cycle = 3/4 *100% = 75% Shown below is the output waveform generated. E = 100 ns E = 100 ns DUTY CYCLE = 75% PERIOD = 800 ns Figure 12-33. PWM Center Aligned Output Example Waveform 12.4.2.7 PWM 16-Bit Functions The PWM timer also has the option of generating 4-channels of 8-bits or 2-channels of 16-bits for greater PWM resolution}. This 16-bit channel option is achieved through the concatenation of two 8-bit channels. The PWMCTL register contains three control bits, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. Channels 2 and 3 are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. NOTE Change these bits only when both corresponding channels are disabled. When channels 2 and 3 are concatenated, channel 2 registers become the high-order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high-order bytes of the double byte channel. Freescale Semiconductor MC9S12Q128 Rev 1.10 375 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description Clock Source 3 High PWMCNT2 Low PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High PWMCNT0 Low PWCNT1 Period/Duty Compare PWM1 Figure 12-34. PWM 16-Bit Mode When using the 16-bit concatenated mode, the clock source is determined by the low-order 8-bit channel clock select control bits. That is channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low-order 8-bit channel as also shown in Figure 12-34. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low-order 8-bit channel as well. After concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low-order PWMEx bit. In this case, the high-order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low-order CAEx bit. The high-order CAEx bit has no effect. Table 12-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 12-11. 16-bit Concatenation Mode Summary CONxx CON23 CON01 PWMEx PWME3 PWME1 PPOLx PPOL3 PPOL1 PCLKx PCLK3 PCLK1 CAEx CAE3 CAE1 PWMx Output PWM3 PWM1 376 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 12.4.2.8 PWM Boundary Cases Table 12-12 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation): Table 12-12. PWM Boundary Cases PWMDTYx 0x0000 (indicates no duty) 0x0000 (indicates no duty) XX XX >= PWMPERx PWMPERx >0x0000 >0x0000 0x0000(1) (indicates no period) 0x00001 (indicates no period) XX PPOLx 1 0 1 0 1 0 PWMx Output Always Low Always High Always High Always Low Always High Always Low >= PWMPERx XX 1. Counter = 0x0000 and does not count. 12.5 Resets The reset state of each individual bit is listed within the register description section (see Section 12.3, “Memory Map and Registers,” which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured as an up counter out of reset. • All the channels are disabled and all the counters don’t count. 12.6 Interrupts The PWM8B4C module interrupt is disabled when PWM5ENA is clear. CAUTION User Software must ensure that PWM5ENA remains clear A description of the registers involved and affected due to this interrupt is explained in Section 12.3.2.15, “PWM Shutdown Register (PWMSDN).” Freescale Semiconductor MC9S12Q128 Rev 1.10 377 Chapter 12 Pulse-Width Modulator (PWM8B4CRev 01.24) Block Description 378 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.1 Introduction This block guide provide an overview of serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 13.1.1 Glossary IRQ — Interrupt Request LSB — Least Significant Bit MSB — Most Significant Bit NRZ — Non-Return-to-Zero RZI — Return-to-Zero-Inverted RXD — Receive Pin SCI — Serial Communication Interface TXD — Transmit Pin 13.1.2 Features The SCI includes these distinctive features: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) format • 13-bit baud rate selection • Programmable 8-bit or 9-bit data format • Separately enabled transmitter and receiver • Programmable transmitter output parity • Two receiver wake up methods: — Idle line wake-up — Address mark wake-up • Interrupt-driven operation with eight flags: — Transmitter empty Freescale Semiconductor MC9S12Q128 Rev 1.10 379 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description • • • — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection 13.1.3 Modes of Operation The SCI operation is the same independent of device resource mapping and bus interface mode. Different power modes are available to facilitate power saving. 13.1.3.1 Run Mode Normal mode of operation. 13.1.3.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. • If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI. 13.1.3.3 Stop Mode The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. 380 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.1.4 Block Diagram Figure 13-1 is a high level block diagram of the SCI module, showing the interaction of various functional blocks. SCI DATA REGISTER IRQ GENERATION IDLE IRQ RX DATA IN RECEIVE SHIFT REGISTER BUS CLOCK RECEIVE & WAKE UP CONTROL RDR/OR IRQ BAUD GENERATOR ÷16 DATA FORMAT CONTROL TRANSMIT CONTROL IRQ GENERATION TDRE IRQ TRANSMIT SHIFT REGISTER TC IRQ SCI DATA REGISTER TXDATA OUT Figure 13-1. SCI Block Diagram 13.2 External Signal Description The SCI module has a total of two external pins: 13.2.1 TXD-SCI Transmit Pin This pin serves as transmit data output of SCI. 13.2.2 RXD-SCI Receive Pin This pin serves as receive data input of the SCI. Freescale Semiconductor MC9S12Q128 Rev 1.10 ORING IRQ TO CPU 381 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3 Memory Map and Registers This section provides a detailed description of all memory and registers. 13.3.1 Module Memory Map The memory map for the SCI module is given below in Figure 13-2. The Address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register. Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 Name SCIBDH SCIBDL SCICR1 SCICR2 SCISR1 SCISR2 SCIDRH SCIDRL R W R W R W R W R W R W R W R W Bit 7 0 6 0 5 0 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 2 SBR10 SBR2 ILT RE NF 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0 SBR7 LOOPS TIE TDRE 0 R8 R7 T7 SBR6 SCISWAI TCIE TC 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 BRK13 0 R2 T2 TXDIR 0 R1 T1 T8 R6 T6 = Unimplemented or Reserved Figure 13-2. SCI Register Summary 13.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register location do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. 382 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.1 SCI Baud Rate Registers (SCIBDH and SCHBDL) Module Base + 0x_0000 7 6 5 4 3 2 1 0 R W Reset 0 0 0 SBR12 SBR11 0 SBR10 0 SBR9 0 SBR8 0 0 0 0 0 Module Base + 0x_0001 7 6 5 4 3 2 1 0 R SBR7 W Reset 0 0 0 0 0 1 0 0 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 = Unimplemented or Reserved Figure 13-3. SCI Baud Rate Registers (SCIBDH and SCIBDL) The SCI Baud Rate Register is used by the counter to determine the baud rate of the SCI. The formula for calculating the baud rate is: SCI baud rate = SCI module clock / (16 x BR) where: BR is the content of the SCI baud rate registers, bits SBR12 through SBR0. The baud rate registers can contain a value from 1 to 8191. Read: Anytime. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: Anytime Table 13-1. SCIBDH AND SCIBDL Field Descriptions Field 4–0 7–0 SBR[12:0] Description SCI Baud Rate Bits — The baud rate for the SCI is determined by these 13 bits. Note: The baud rate generator is disabled until the TE bit or the RE bit is set for the first time after reset. The baud rate generator is disabled when BR = 0. Writing to SCIBDH has no effect without writing to SCIBDL, since writing to SCIBDH puts the data in a temporary location until SCIBDL is written to. Freescale Semiconductor MC9S12Q128 Rev 1.10 383 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.2 SCI Control Register 1 (SCICR1) Module Base + 0x_0002 7 6 5 4 3 2 1 0 R LOOPS W Reset 0 0 0 0 0 0 0 0 SCISWAI RSRC M WAKE ILT PE PT Figure 13-4. SCI Control Register 1 (SCICR1) Read: Anytime Write: Anytime Table 13-2. SCICR1 Field Descriptions Field 7 LOOPS Description Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function.See Table 13-3. 0 Normal operation enabled 1 Loop operation enabled Note: The receiver input is determined by the RSRC bit. SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode. 0 SCI enabled in wait mode 1 SCI disabled in wait mode Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long. 0 One start bit, eight data bits, one stop bit 1 One start bit, nine data bits, one stop bit Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD. 0 Idle line wakeup 1 Address mark wakeup Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled 1 Parity function enabled Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 Even parity 1 Odd parity 6 SCISWAI 5 RSRC 4 M 3 WAKE 2 ILT 1 PE 0 PT 384 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-3. Loop Functions LOOPS 0 1 1 RSRC x 0 1 Normal operation Loop mode with Rx input internally connected to Tx output Single-wire mode with Rx input connected to TXD Function 13.3.2.3 SCI Control Register 2 (SCICR2) Module Base + 0x_0003 7 6 5 4 3 2 1 0 R TIE W Reset 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK Figure 13-5. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 13-4. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 0 TDRE interrupt requests disabled 1 TDRE interrupt requests enabled Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate interrupt requests. 0 TC interrupt requests disabled 1 TC interrupt requests enabled Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests. 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit — RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled 6 TCIE 5 RIE 4 ILIE 3 TE 2 RE Freescale Semiconductor MC9S12Q128 Rev 1.10 385 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-4. SCICR2 Field Descriptions (continued) Field 1 RWU Description Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters 0 SBK 13.3.2.4 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI Data Register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing. Module Base + 0x_0004 7 6 5 4 3 2 1 0 R W Reset TDRE TC RDRF IDLE OR NF FE PF 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. SCI Status Register 1 (SCISR1) Read: Anytime Write: Has no meaning or effect Table 13-5. SCISR1 Field Descriptions Field 7 TDRE Description Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL). 0 No byte transferred to transmit shift register 1 Byte transferred to transmit shift register; transmit data register empty Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD out signal becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete). 0 Transmission in progress 1 No transmission in progress 6 TC 386 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-5. SCISR1 Field Descriptions (continued) Field 5 RDRF Description Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL). 0 Data not available in SCI data register 1 Received data available in SCI data register Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M=0) or 11 consecutive logic 1s (if M=1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL). 0 No overrun 1 Overrun Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received. Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL). 0 No framing error 1 Framing error Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error 4 IDLE 3 OR 2 NF 1 FE 0 PF Freescale Semiconductor MC9S12Q128 Rev 1.10 387 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.5 SCI Status Register 2 (SCISR2) Module Base + 0x_0005 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 BK13 TXDIR 0 RAF 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-7. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime; writing accesses SCI status register 2; writing to any bits except TXDIR and BRK13 (SCISR2[1] & [2]) has no effect Table 13-6. SCISR2 Field Descriptions Field 2 BK13 Description Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit. 0 Break Character is 10 or 11 bit long 1 Break character is 13 or 14 bit long Transmitter Pin Data Direction in Single-Wire Mode. — This bit determines whether the TXD pin is going to be used as an input or output, in the Single-Wire mode of operation. This bit is only relevant in the Single-Wire mode of operation. 0 TXD pin to be used as an input in Single-Wire mode 1 TXD pin to be used as an output in Single-Wire mode Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress 1 TXDIR 0 RAF 388 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.3.2.6 SCI Data Registers (SCIDRH and SCIDRL) Module Base + 0x_0006 7 6 5 4 3 2 1 0 R W Reset R8 T8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Module Base + 0x_0007 7 6 5 4 3 2 1 0 R W Reset R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 0 = Unimplemented or Reserved Figure 13-8. SCI Data Registers (SCIDRH and SCIDRL) Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect Table 13-7. SCIDRH AND SCIDRL Field Descriptions Field 7 R8 6 T8 7–0 R[7:0] T[7:0] Description Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). Received Bits — Received bits seven through zero for 9-bit or 8-bit data formats Transmit Bits — Transmit bits seven through zero for 9-bit or 8-bit formats NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. Freescale Semiconductor MC9S12Q128 Rev 1.10 389 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 13-9 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, NRZ serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. SCI DATA REGISTER R8 RXD RECEIVE SHIFT REGISTER RE RECEIVE AND WAKEUP CONTROL RWU LOOPS RSRC M BUS CLOCK BAUD RATE GENERATOR WAKE DATA FORMAT CONTROL ILT PE PT TE ÷16 TRANSMIT CONTROL LOOPS SBK RSRC T8 TRANSMIT SHIFT REGISTER SCI DATA REGISTER TDRE TC TCIE TIE RIE NF FE PF RAF IDLE RDRF RDRF/OR IRQ IDLE IRQ OR ILIE SBR12–SBR0 IRQ TO CPU TDRE IRQ TXD Figure 13-9. SCI Block Diagram 390 MC9S12Q128 Rev 1.10 Freescale Semiconductor TC IRQ Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.1 Data Format The SCI uses the standard NRZ mark/space data format illustrated in Figure 13-10 below. 8-BIT DATA FORMAT BIT M IN SCICR1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY OR DATA BIT BIT 7 STOP BIT PARITY OR DATA BIT BIT 7 BIT 8 STOP BIT NEXT START BIT 9-BIT DATA FORMAT BIT M IN SCICR1 SET START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 NEXT START BIT Figure 13-10. SCI Data Formats Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters.A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits Table 13-8. Example of 8-Bit Data Formats Start Bit 1 1 Data Bits 8 7 Address Bits 0 0 Parity Bits 0 1 Stop Bit 1 1 0 1 1 7 1(1) 1. The address bit identifies the frame as an address character. See Section 13.4.4.6, “Receiver Wakeup”. When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 13-9. Example of 9-Bit Data Formats Start Bit 1 1 Data Bits 9 8 Address Bits 0 0 (1) Parity Bits 0 1 Stop Bit 1 1 0 1 1 8 1 1. The address bit identifies the frame as an address character. See Section 13.4.4.6, “Receiver Wakeup”. Freescale Semiconductor MC9S12Q128 Rev 1.10 391 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.2 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12–SBR0 bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error: Integer division of the module clock may not give the exact target frequency. Table 13-10 lists some examples of achieving target baud rates with a module clock frequency of 25 MHz SCI baud rate = SCI module clock / (16 * SCIBR[12:0]) Table 13-10. Baud Rates (Example: Module Clock = 25 MHz) Bits SBR[12-0] 41 81 163 326 651 1302 2604 5208 Receiver Clock (Hz) 609,756.1 308,642.0 153,374.2 76,687.1 38,402.5 19,201.2 9600.6 4800.0 Transmitter Clock (Hz) 38,109.8 19,290.1 9585.9 4792.9 2400.2 1200.1 600.0 300.0 Target Baud Rate 38,400 19,200 9600 4800 2400 1200 600 300 Error (%) .76 .47 .16 .15 .01 .01 .00 .00 392 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.3 Transmitter INTERNAL BUS BUS CLOCK BAUD DIVIDER ÷ 16 SCI DATA REGISTERS 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 START SBR12–SBR0 STOP M H L TXD MSB PREAMBLE (ALL ONES) T8 LOAD FROM SCIDR LOOP CONTROL BREAK (ALL 0s) TO RXD PT PARITY GENERATION SHIFT ENABLE PE LOOPS RSRC TRANSMITTER CONTROL TDRE INTERRUPT REQUEST TDRE TIE TC TCIE TE SBK TC INTERRUPT REQUEST Figure 13-11. Transmitter Block Diagram 13.4.3.1 Transmitter Character Length The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). 13.4.3.2 Character Transmission To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the Tx output signal, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by Freescale Semiconductor MC9S12Q128 Rev 1.10 393 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word length, parity, and other configuration bits (LOOPS,RSRC,M,WAKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for Each Byte: a. Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. d) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (msb) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. When the transmit shift register is not transmitting a frame, the Tx output signal goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. 394 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L. 13.4.3.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: • Sets the framing error flag, FE • Sets the receive data register full flag, RDRF • Clears the SCI data registers (SCIDRH/L) • May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see Section 13.3.2.4, “SCI Status Register 1 (SCISR1)” and Section 13.3.2.5, “SCI Status Register 2 (SCISR2)” 13.4.3.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the Tx output signal becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. Freescale Semiconductor MC9S12Q128 Rev 1.10 395 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the Tx output signal. Setting TE after the stop bit appears on Tx output signal causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. NOTE If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin 13.4.4 Receiver INTERNAL BUS SBR12–SBR0 SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0 RXD LOOP CONTROL RE RAF LOOPS RSRC M WAKE ILT PE PT DATA RECOVERY ALL ONES H FROM TXD MSB FE NF WAKEUP LOGIC PE RWU PARITY CHECKING IDLE ILIE RDRF R8 IDLE INTERRUPT REQUEST RDRF/OR INTERRUPT REQUEST RIE OR Figure 13-12. SCI Receiver Block Diagram 13.4.4.1 Receiver Character Length The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). 396 MC9S12Q128 Rev 1.10 Freescale Semiconductor START L STOP BUS CLOCK BAUD DIVIDER Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.4.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the Rx input signal. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 13.4.4.3 Data Sampling The receiver samples the Rx input signal at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 13-13) is resynchronized: • After every start bit • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. START BIT Rx Input Signal SAMPLES 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 LSB START BIT QUALIFICATION START BIT VERIFICATION DATA SAMPLING RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT4 Figure 13-13. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-11 summarizes the results of the start bit verification samples. Table 13-11. Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 Start Bit Verification Yes Yes Yes No Noise Flag 0 1 1 0 Freescale Semiconductor MC9S12Q128 Rev 1.10 397 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Table 13-11. Start Bit Verification RT3, RT5, and RT7 Samples 100 101 110 111 Start Bit Verification Yes No No No Noise Flag 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-12 summarizes the results of the data bit samples. Table 13-12. Data Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-13 summarizes the results of the stop bit samples. Table 13-13. Stop Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 398 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description In Figure 13-14 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. START BIT Rx Input Signal SAMPLES 1 1 1 0 1 1 1 0 0 0 0 0 0 0 LSB RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 LSB RT6 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT3 RT7 Figure 13-14. Start Bit Search Example 1 In Figure 13-15, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. PERCEIVED START BIT ACTUAL START BIT Rx Input Signal SAMPLES 1 1 1 1 1 0 1 0 0 0 0 0 RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT5 Figure 13-15. Start Bit Search Example 2 Freescale Semiconductor MC9S12Q128 Rev 1.10 399 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description In Figure 13-16, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. PERCEIVED START BIT ACTUAL START BIT Rx input Signal SAMPLES 1 1 1 0 0 1 0 0 0 0 LSB RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 LSB RT2 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT9 RT3 Figure 13-16. Start Bit Search Example 3 Figure 13-17 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. PERCEIVED AND ACTUAL START BIT Rx Input Signal SAMPLES 1 1 1 1 1 1 1 1 1 0 1 0 RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT1 Figure 13-17. Start Bit Search Example 4 400 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description Figure 13-18 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. START BIT NO START BIT FOUND 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 LSB Rx Input Signal SAMPLES RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 LSB RT2 RT CLOCK COUNT RESET RT CLOCK RT1 RT3 Figure 13-18. Start Bit Search Example 5 In Figure 13-19, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. START BIT Rx Input Signal SAMPLES 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT1 Figure 13-19. Start Bit Search Example 6 Freescale Semiconductor MC9S12Q128 Rev 1.10 401 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.4.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. 13.4.4.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit.A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 13.4.4.5.1 Slow Data Tolerance Figure 13-20 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 13-20. Slow Data Let’s take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles =151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 13-20, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 – 144) / 151) x 100 = 4.63% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. 402 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description With the misaligned character shown in Figure 13-20, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% 13.4.4.5.2 Fast Data Tolerance Figure 13-21 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. STOP IDLE OR NEXT FRAME RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 13-21. Fast Data For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 13-21, the receiver counts 154 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 – 154) / 160) x 100 = 3.75% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 13-21, the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 – 170) / 176) x 100 = 3.40% 13.4.4.6 Receiver Wakeup To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. Freescale Semiconductor MC9S12Q128 Rev 1.10 403 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. 13.4.4.6.1 Idle Input Line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the Rx Input signal clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the Rx Input signal. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1). 13.4.4.6.2 Address Mark Wakeup (WAKE = 1) In this wakeup method, a logic 1 in the most significant bit (msb) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the msb position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the Rx Input signal. The logic 1 msb of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames.{sci_wake} NOTE With the WAKE bit clear, setting the RWU bit after the Rx Input signal has been idle can cause the receiver to wake up immediately. 404 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.4.5 Single-Wire Operation Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. TRANSMITTER Tx OUTPUT SIGNAL Tx INPUT SIGNAL RECEIVER RXD Figure 13-22. Single-Wire Operation (LOOPS = 1, RSRC = 1) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the Rx Input signal to the receiver. Setting the RSRC bit connects the receiver input to the output of the TXD pin driver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. 13.4.6 Loop Operation In loop operation the transmitter output goes to the receiver input. The Rx Input signal is disconnected from the SCI . TRANSMITTER Tx OUTPUT SIGNAL RECEIVER RXD Figure 13-23. Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the Rx Input signal to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). 13.5 13.5.1 Initialization Information Reset Initialization The reset state of each individual bit is listed in Section 13.3, “Memory Map and Registers” which details the registers and their bit fields. All special functions or modes which are initialized during or just following reset are described within this section. Freescale Semiconductor MC9S12Q128 Rev 1.10 405 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.5.2 13.5.2.1 Interrupt Operation System Level Interrupt Sources There are five interrupt sources that can generate an SCI interrupt in to the CPU. They are listed in Table 13-14. Table 13-14. SCI Interrupt Source Interrupt Source Transmitter Transmitter Receiver Receiver Flag TDRE TC RDRF OR IDLE ILIE Local Enable TIE TCIE RIE 406 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 13.5.2.2 Interrupt Descriptions The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 13.5.2.2.1 TDRE Description The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL). 13.5.2.2.2 TC Description The TC interrupt is set by the SCI when a transmission has been completed.A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent. 13.5.2.2.3 RDRF Description The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 13.5.2.2.4 OR Description The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 13.5.2.3 IDLE Description The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 13.5.3 Recovery from Wait Mode The SCI interrupt request can be used to bring the CPU out of wait mode. Freescale Semiconductor MC9S12Q128 Rev 1.10 407 Chapter 13 Serial Communications Interface (S12SCIV2) Block Description 408 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 14.1.1 Features The SPIV3 includes these distinctive features: • Master mode and slave mode • Bidirectional mode • Slave select output • Mode fault error flag with CPU interrupt capability • Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode 14.1.2 Modes of Operation The SPI functions in three modes, run, wait, and stop. • Run Mode This is the basic mode of operation. • Wait Mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. • Stop Mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. This is a high level description only, detailed descriptions of operating modes are contained in Section 14.4, “Functional Description.” Freescale Semiconductor MC9S12Q128 Rev 1.10 409 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.1.3 Block Diagram Figure 14-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. SPI 2 SPI Control Register 1 BIDIROE SPI Control Register 2 2 SPC0 SPI Status Register SPIF SPI Interrupt Request Baud Rate Generator Counter Bus Clock Prescaler Clock Select SPPR 3 SPR 3 Shifter SPI Baud Rate Register LSBFE=1 8 SPI Data Register 8 LSBFE=0 MSB LSBFE=0 LSBFE=1 LSBFE=0 LSBFE=1 LSB data out data in Baud Rate Shift Clock Sample Clock MODF SPTEF Slave Control CPOL CPHA MOSI Interrupt Control Phase + SCK in Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK out Polarity Control Master Control Port Control Logic SCK SS Figure 14-1. SPI Block Diagram 14.2 External Signal Description This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPIV3 module has a total of four external pins. 14.2.1 MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. 410 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. 14.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when its configured as a master and its used as an input to receive the slave select signal when the SPI is configured as slave. 14.2.4 SCK — Serial Clock Pin This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of slave. 14.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the SPI. The memory map for the SPIV3 is given below in Table 14-1. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect. 14.3.1 Module Memory Map Table 14-1. SPIV3 Memory Map Address Use Access R/W R/W(1) R/W1 R(2) — 2,(3) R/W — 2,3 — 2,3 0x0000 SPI Control Register 1 (SPICR1) 0x0001 SPI Control Register 2 (SPICR2) 0x0002 SPI Baud Rate Register (SPIBR) 0x0003 SPI Status Register (SPISR) 0x0004 Reserved 0x0005 SPI Data Register (SPIDR) 0x0006 Reserved 0x0007 Reserved 1. Certain bits are non-writable. 2. Writes to this register are ignored. 3. Reading from this register returns all zeros. Freescale Semiconductor MC9S12Q128 Rev 1.10 411 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Name 0x0000 SPICR1 0x0001 SPICR2 0x0002 SPIBR 0x0003 SPISR 0x0004 Reserved 0x0005 SPIDR 0x0006 Reserved 0x0007 Reserved R W R W R W R W R W R W R W R W = Unimplemented or Reserved Bit 7 6 5 4 3 2 2 Bit 0 SPIF 0 SPPR2 0 SPPR1 SPTEF 7 SPIE 0 6 SPE 0 5 SPTIE 0 4 MSTR 3 CPOL 2 CPHA 0 1 SSOE 0 LSBFE MODFEN BIDIROE 0 SPISWAI SPC0 SPPR0 MODF SPR2 0 SPR1 0 SPR0 0 0 Figure 14-2. SPI Register Summary 14.3.2.1 SPI Control Register 1 (SPICR1) Module Base 0x0000 7 6 5 4 3 2 1 0 R SPIE W Reset 0 0 0 0 0 1 0 0 SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Figure 14-3. SPI Control Register 1 (SPICR1) Read: anytime Write: anytime 412 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-2. SPICR1 Field Descriptions Field 7 SPIE 6 SPE Description SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. SPI Master/Slave Mode Select Bit — This bit selects, if the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode 1 SPI is in master mode SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 14-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first. 5 SPTIE 4 MSTR 3 CPOL 2 CPHA 1 SSOE 0 LSBFE Table 14-3. SS Input / Output Selection MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode SS not used by SPI SS not used by SPI SS input with MODF feature SS is slave select output Slave Mode SS input SS input SS input SS input Freescale Semiconductor MC9S12Q128 Rev 1.10 413 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.3.2.2 SPI Control Register 2 (SPICR2) Module Base 0x0001 7 6 5 4 3 2 1 0 R W Reset 0 0 0 MODFEN BIDIROE 0 0 SPISWAI 0 0 SPC0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-4. SPI Control Register 2 (SPICR2) Read: anytime Write: anytime; writes to the reserved bits have no effect Table 14-4. SPICR2 Field Descriptions Field 4 MODFEN Description Mode Fault Enable Bit — This bit allows the MODF failure being detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration refer to Table 14-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 SS port pin is not used by the SPI 1 SS port pin with MODF feature Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled 1 Output buffer enabled SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode 1 Stop SPI clock generation when in wait mode Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 14-5. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state 3 BIDIROE 1 SPISWAI 0 SPC0 Table 14-5. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Mode of Operation Normal 0 X Slave Out Slave In Master In MISO not used by SPI Master Out Master In Master I/O 414 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-5. Bidirectional Pin Configurations (continued) Pin Mode Bidirectional SPC0 1 BIDIROE 0 1 MISO Slave In Slave I/O MOSI MOSI not used by SPI 14.3.2.3 SPI Baud Rate Register (SPIBR) Module Base 0x0002 7 6 5 4 3 2 1 0 R W Reset 0 SPPR2 0 0 SPPR1 0 SPPR0 0 0 SPR2 0 0 SPR1 0 SPR0 0 = Unimplemented or Reserved Figure 14-5. SPI Baud Rate Register (SPIBR) Read: anytime Write: anytime; writes to the reserved bits have no effect Table 14-6. SPIBR Field Descriptions Field 6:4 SPPR[2:0] 2:0 SPR[2:0} Description SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 14-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 14-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. The baud rate divisor equation is as follows: BaudRateDivisor = ( SPPR + 1 ) • 2 ( SPR + 1 ) The baud rate can be calculated with the following equation: Baud Rate = BusClock ⁄ BaudRateDivisor Freescale Semiconductor MC9S12Q128 Rev 1.10 415 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPPR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 SPR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 SPR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Baud Rate Divisor 2 4 8 16 32 64 128 256 4 8 16 32 64 128 256 512 6 12 24 48 96 192 384 768 8 16 32 64 128 256 512 1024 10 20 40 80 160 320 640 Baud Rate 12.5 MHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 4.16667 MHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.13 kHz 39.06 kHz 416 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Table 14-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Baud Rate Divisor 1280 12 24 48 96 192 384 768 1536 14 28 56 112 224 448 896 1792 16 32 64 128 256 512 1024 2048 Baud Rate 19.53 kHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 16.28 kHz 1.78571 MHz 892.86 kHz 446.43 kHz 223.21 kHz 111.61 kHz 55.80 kHz 27.90 kHz 13.95 kHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 12.21 kHz NOTE In slave mode of SPI S-clock speed DIV2 is not supported. Freescale Semiconductor MC9S12Q128 Rev 1.10 417 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.3.2.4 SPI Status Register (SPISR) Module Base 0x0003 7 6 5 4 3 2 1 0 R W Reset SPIF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure 14-6. SPI Status Register (SPISR) Read: anytime Write: has no effect Table 14-8. SPISR Field Descriptions Field 7 SPIF Description SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data Register. 0 Transfer not yet complete 1 New data copied to SPIDR SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI Data Register without reading SPTEF = 1, is effectively ignored. 0 SPI Data register not empty 1 SPI Data register empty Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 14.3.2.2, “SPI Control Register 2 (SPICR2).” The flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to the SPI Control Register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. 5 SPTEF 4 MODF 14.3.2.5 SPI Data Register (SPIDR) Module Base 0x0005 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 2 Bit 0 = Unimplemented or Reserved Figure 14-7. SPI Data Register (SPIDR) Read: anytime; normally read only after SPIF is set 418 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Write: anytime The SPI Data Register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when the SPI Data Register is ready to accept new data. Reading the data can occur anytime from after the SPIF is set to before the end of the next transfer. If the SPIF is not serviced by the end of the successive transfers, those data bytes are lost and the data within the SPIDR retains the first byte until SPIF is serviced. 14.4 Functional Description The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While SPE bit is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) The main element of the SPI system is the SPI Data Register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI Data Register becomes the output data for the slave, and data read from the master SPI Data Register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete, received data is moved into the receive data register. Data may be read from this double-buffered system any time before the next transfer has completed. This 8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI Control Register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 14.4.3, “Transmission Formats”). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI Control Register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. Freescale Semiconductor MC9S12Q128 Rev 1.10 419 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI Data Register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock. • S-clock The SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. • MOSI and MISO Pins In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. • SS Pin If MODFEN and SSOE bit are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also requested. When a write to the SPI Data Register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see Section 14.4.3, “Transmission Formats”). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, BIDIROE with SPC0 set, SPPR2–SPPR0 and SPR2–SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master has to ensure that the remote slave is set back to idle state. 420 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. • SCK Clock In slave mode, SCK is the SPI clock input from the master. • MISO and MOSI Pins In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2. • SS Pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low the first bit in the SPI Data Register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register takes place. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI Data Register. To indicate transfer is complete, the SPIF flag in the SPI Status Register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0 and BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and has to be avoided. Freescale Semiconductor MC9S12Q128 Rev 1.10 421 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device, slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. MASTER SPI MISO MOSI SCK BAUD RATE GENERATOR SS MISO MOSI SCK SS SLAVE SPI SHIFT REGISTER SHIFT REGISTER VDD Figure 14-8. Master/Slave Transfer Block Diagram 14.4.3.1 Clock Phase and Polarity Controls Using two bits in the SPI Control Register1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. 14.4.3.2 CPHA = 0 Transfer Format The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. 422 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI Data Register should now be in the slave data register and the data that was in the slave data register should be in the master. • The SPIF flag in the SPI Status Register is set indicating that the transfer is complete. Figure 14-9 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. End of Idle State SCK Edge Nr. SCK (CPOL = 0) SCK (CPOL = 1) 1 2 Begin 3 4 5 6 Transfer 7 8 9 10 11 12 End 13 14 15 16 Begin of Idle State CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. Bit 1 Bit 6 tT tI tL LSB Minimum 1/2 SCK for tT, tl, tL MSB Figure 14-9. SPI Clock Format 0 (CPHA = 0) In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI Data Register is not transmitted, instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions then the content of the SPI Data Register is transmitted. Freescale Semiconductor MC9S12Q128 Rev 1.10 If next transfer begins here SAMPLE I MOSI/MISO 423 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time. 14.4.3.3 CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th SCK edge: • Data that was previously in the SPI Data Register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. • The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 14-10 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. • Back-to-back transfers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI Data Register, this byte is send out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge. 424 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description End of Idle State SCK Edge Nr. SCK (CPOL = 0) SCK (CPOL = 1) 1 2 3 Begin 4 5 6 7 Transfer 8 9 10 11 12 End 13 14 15 16 Begin of Idle State CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): tT tI tL MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB tL = Minimum leading time before the first SCK edge, not required for back to back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back to back transfers Figure 14-10. SPI Clock Format 1 (CPHA = 1) 14.4.4 SPI Baud Rate Generation Baud rate generation consists of a series of divider stages. Six bits in the SPI Baud Rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Figure 14-11 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8 etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 14-7 for baud rate calculations for all bit conditions, based on a 25-MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. Freescale Semiconductor MC9S12Q128 Rev 1.10 If next transfer begins here SAMPLE I MOSI/MISO 425 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. BaudRateDivisor = ( SPPR + 1 ) • 2 ( SPR + 1 ) Figure 14-11. Baud Rate Divisor Equation 14.4.5 14.4.5.1 Special Features SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 14-3. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters. 14.4.5.2 Bidirectional Mode (MOSI or MISO) The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see Table 14-9). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. Table 14-9. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out MOSI Slave Mode MSTR = 0 Serial In SPI MISO Serial Out MISO MOSI Normal Mode SPC0 = 0 SPI Serial In Serial Out MOMI BIDIROE Serial In BIDIROE SPI Serial Out SISO Bidirectional Mode SPC0 = 1 SPI Serial In 426 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode, in this case MISO becomes occupied by the SPI and MOSI is not used. This has to be considered, if the MISO pin is used for other purpose. 14.4.6 Error Conditions The SPI has one error condition: • Mode fault error 14.4.6.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI Status Register is set automatically provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. Freescale Semiconductor MC9S12Q128 Rev 1.10 427 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.4.7 Operation in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled. 14.4.8 Operation in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. — If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. — If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e. If the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. A SPIF flag and SPIDR copy is only generated if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur. 14.4.9 Operation in Stop Mode Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit. 428 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 14.5 Reset The reset values of registers and signals are described in the Memory Map and Registers section (see Section 14.3, “Memory Map and Register Definition”) which details the registers and their bit-fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. • Reading from the SPIDR after reset will always read a byte of zeros. 14.6 Interrupts The SPIV3 only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPIV3 makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF and SPTEF are logically ORed to generate an interrupt request. 14.6.1 MODF MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 14-3). After MODF is set, the current transfer is aborted and the following bit is changed: • MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 14.3.2.4, “SPI Status Register (SPISR).” 14.6.2 SPIF SPIF occurs when new data has been received and copied to the SPI Data Register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process which is described in Section 14.3.2.4, “SPI Status Register (SPISR).” In the event that the SPIF is not serviced before the end of the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be ignored and no new data will be copied into the SPIDR. 14.6.3 SPTEF SPTEF occurs when the SPI Data Register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process which is described in Section 14.3.2.4, “SPI Status Register (SPISR).” Freescale Semiconductor MC9S12Q128 Rev 1.10 429 Chapter 14 Serial Peripheral Interface (SPIV3) Block Description 430 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) Table 15-1. TIM_16B4C Revision History Version Number 01.01 01.02 Effective Date Feb 06, 2006 Description of Changes Corrected typo for TSCR1 (instead was named TSCR2) May 21, 2010 -in 15.3.2.8/15-440,add Table 15-10 -in 15.3.2.11/15-443,TCRE bit description part,add Note -in 15.4.3/15-451,add Figure 15-29 15.1 Introduction The basic timer consists of a 16-bit, software-programmable counter driven by a seven-stage programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer contains 6 complete input capture/output compare channels and one pulse accumulator. The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator is used to operate as a simple event counter or a gated time accumulator. The pulse accumulator shares timer channel 7 when in event mode. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 15.1.1 Features The TIM16B6C includes these distinctive features: • Six input capture/output compare channels. • Clock prescaling. • 16-bit counter. • 16-bit pulse accumulator. 15.1.2 Stop: Modes of Operation Timer is off because clocks are stopped. Freescale Semiconductor MC9S12Q128 Rev 1.10 431 Chapter 15 Timer Module (TIM16B6C) Freeze: Wait: Normal: Timer counter keep on running, unless TSFRZ in TSCR (0x0006) is set to 1. Counters keep on running, unless TSWAI in TSCR (0x0006) is set to 1. Timer counter keep on running, unless TEN in TSCR (0x0006) is cleared to 0. 15.1.3 Block Diagrams Bus clock Prescaler 16-bit counter Channel 2 Input capture Output compare Channel 3 Input capture Output compare Registers Channel 4 Input capture Output compare Channel 5 Input capture Output compare Timer channel 7 interrupt Channel 6 Input capture Output compare 16-bit Pulse accumulator Channel 7 Input capture Output compare Timer overflow interrupt Timer channel 2 interrupt IOC2 IOC3 IOC4 IOC5 IOC6 PA overflow interrupt PA input interrupt IOC7 Figure 15-1. TIM16B6C Block Diagram 432 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) TIMCLK (Timer clock) CLK1 CLK0 4:1 MUX PACLK / 256 Prescaled clock (PCLK) PACLK / 65536 Clock select (PAMOD) PACLK Edge detector PT7 Intermodule Bus Interrupt PACNT MUX Divide by 64 M clock Figure 15-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer PTn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 15-3. Interrupt Flag Setting Pulse Accumulator Pad Channel 7 Output Compare OM7 OL7 OC7M7 Figure 15-4. Channel 7 Output Compare/Pulse Accumulator Logic NOTE For more information see the respective functional descriptions in Section 15.4, “Functional Description,” of this document. Freescale Semiconductor MC9S12Q128 Rev 1.10 433 Chapter 15 Timer Module (TIM16B6C) 15.2 External Signal Description The TIM16B6C module has a total of eight external pins. 15.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin This pin serves as input capture or output compare for channel 7. This can also be configured as pulse accumulator input. 15.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin This pin serves as input capture or output compare for channel 6. 15.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin This pin serves as input capture or output compare for channel 5. 15.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin This pin serves as input capture or output compare for channel 4. Pin 15.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin This pin serves as input capture or output compare for channel 3. 15.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin NOTE For the description of interrupts see Section 15.6, “Interrupts”. This pin serves as input capture or output compare for channel 2. 15.3 Memory Map and Registers This section provides a detailed description of all memory and registers. 15.3.1 Module Memory Map The following paragraphs describe the content of the registers in the TIM16B6C module. The memory map for the TIM16B6C module is given below in Figure 15-5. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B6C module and the address offset for each register. 434 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Address Name R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F TIOS CFORC OC7M OC7D TCNTH TCNTL TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 IOS7 0 FOC7 OC7M7 OC7D7 TCNT15 TCNT7 TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF IOS6 0 FOC6 OC7M6 OC7D6 TCNT14 TCNT6 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 IOS5 0 FOC5 OC7M5 OC7D5 TCNT13 TCNT5 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 IOS4 0 FOC4 OC7M4 OC7D4 TCNT12 TCNT4 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 IOS3 0 FOC3 OC7M3 OC7D3 TCNT11 TCNT3 0 IOS2 0 FOC2 OC7M2 OC7D2 TCNT10 TCNT2 0 TCNT9 TCNT1 0 TCNT8 TCNT0 0 0 0 TOV3 OM5 TOV2 OL5 OM4 OL4 EDG5B EDG5A EDG4B EDG4A C3I TCRE C3F 0 C2I PR2 C2F 0 C1I PR1 C0I PR0 C6F 0 C5F 0 C4F 0 0 0 = Unimplemented or Reserved Figure 15-5. TIM16B6C Register Summary Freescale Semiconductor MC9S12Q128 Rev 1.10 435 Chapter 15 Timer Module (TIM16B6C) Address Name Bit 7 6 5 4 3 2 1 Bit 0 R 0x0010– Reserved 0x0013 W R 0x0014– 0x001F TCxH– TCxL W R W 0x0020 0x0021 0x0022 0x0023 PACTL PAFLG PACNTH PACNTL R W R W R W R W PACNT15 PACNT7 PACNT14 PACNT6 PACNT13 PACNT5 PACNT12 PACNT4 PACNT11 PACNT3 PACNT10 PACNT2 0 Bit 15 Bit 7 0 Bit 14 Bit 6 PAEN 0 Bit 13 Bit 5 PAMOD 0 Bit 12 Bit 4 PEDGE 0 Bit 11 Bit 3 CLK1 0 Bit 10 Bit 2 CLK0 0 Bit 9 Bit 1 PAOVI PAOVF PACNT9 PACNT1 Bit 8 Bit 0 PAI PAIF PACNT8 PACNT0 R 0x0024– Reserved 0x002F W = Unimplemented or Reserved Figure 15-5. TIM16B6C Register Summary (continued) 15.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 7 6 5 4 3 2 1 0 R IOS7 W Reset 0 0 0 0 0 0 0 0 IOS6 IOS5 IOS4 IOS3 IOS2 Figure 15-6. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime Write: Anytime Table 15-2. TIOS Field Descriptions Field 7:2 IOS[7:2] Description Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture. 1 The corresponding channel acts as an output compare. 436 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.3.2.2 Timer Compare Force Register (CFORC) Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset 0 FOC7 0 0 FOC6 0 0 FOC5 0 0 FOC4 0 0 FOC3 0 0 FOC2 0 0 0 0 0 Figure 15-7. Timer Compare Force Register (CFORC) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 15-3. CFORC Field Descriptions Field 7:2 FOC[7:2] Description Force Output Compare Action for Channel 7:2— A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. Note: A successful channel 7 output compare overrides any channel 6:2 compares. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won’t get set. 15.3.2.3 Output Compare 7 Mask Register (OC7M) Module Base + 0x0002 7 6 5 4 3 2 1 0 R OC7M7 W Reset 0 0 0 0 0 0 0 0 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 Figure 15-8. Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime Table 15-4. OC7M Field Descriptions Field 7:2 OC7M[7:2] Description Output Compare 7 Mask — Setting the OC7Mx (x ranges from 2 to 6) will set the corresponding port to be an output port when the corresponding TIOSx (x ranges from 2 to 6) bit is set to be an output compare. Note: A successful channel 7 output compare overrides any channel 6:2 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit. Freescale Semiconductor MC9S12Q128 Rev 1.10 437 Chapter 15 Timer Module (TIM16B6C) 15.3.2.4 Output Compare 7 Data Register (OC7D) Module Base + 0x0003 7 6 5 4 3 2 1 0 R OC7D7 W Reset 0 0 0 0 0 0 0 0 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 Figure 15-9. Output Compare 7 Data Register (OC7D) Read: Anytime Write: Anytime Table 15-5. OC7D Field Descriptions Field 7:2 OC7D[7:2] Description Output Compare 7 Data — A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. 15.3.2.5 Timer Count Register (TCNT) Module Base + 0x0004 15 14 13 12 11 10 9 9 R W Reset TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0 0 0 0 0 0 0 0 Figure 15-10. Timer Count Register High (TCNTH) Module Base + 0x0005 7 6 5 4 3 2 1 0 R W Reset TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 Figure 15-11. Timer Count Register Low (TCNTL) The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. 438 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.3.2.6 Timer System Control Register 1 (TSCR1) Module Base + 0x0006 7 6 5 4 3 2 1 0 R TEN W Reset 0 0 0 0 TSWAI TSFRZ TFFCA 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 15-12. Timer System Control Register 1 (TSCR1) Read: Anytime Write: Anytime Table 15-6. TSCR1 Field Descriptions Field 7 TEN Description Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is generated by the timer prescaler. Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears the PAOVF and PAIF flags in the PAFLG register (0x0021). This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. 6 TSWAI 5 TSFRZ 4 TFFCA Freescale Semiconductor MC9S12Q128 Rev 1.10 439 Chapter 15 Timer Module (TIM16B6C) 15.3.2.7 Timer Toggle On Overflow Register 1 (TTOV) Module Base + 0x0007 7 6 5 4 3 2 1 0 R TOV7 W Reset 0 0 0 0 0 0 0 0 TOV6 TOV5 TOV4 TOV3 TOV2 Figure 15-13. Timer Toggle On Overflow Register 1 (TTOV) Read: Anytime Write: Anytime Table 15-7. TTOV Field Descriptions Field 7:2 TOV[7:2] Description Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. 15.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 7 6 5 4 3 2 1 0 R OM7 W Reset 0 0 0 0 0 0 0 0 OL7 OM6 OL6 OM5 OL5 OM4 OL4 Figure 15-14. Timer Control Register 1 (TCTL1) Module Base + 0x0009 7 6 5 4 3 2 1 0 R OM3 W Reset 0 0 0 0 0 0 0 0 OL3 OM2 OL2 Figure 15-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime 440 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) Table 15-8. TCTL1/TCTL2 Field Descriptions Field 7:2 OMx Description Output Mode — These control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. Output Level — These control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. 7:2 OLx Table 15-9. Compare Result Output Action OMx 0 0 1 1 OLx 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCx output line Clear OCx output line to zero Set OCx output line to one To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the OC7M register must also be cleared. To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in the OC7M register must also be cleared. The settings for these bits can be seen in Table 15-10 Table 15-10. The OC7 and OCx event priority OC7M7=0 OC7Mx=1 TC7=TCx TC7>TCx IOCx=OC7Dx IOCx=OC7Dx IOC7=OM7/O +OMx/OLx L7 IOC7=OM7/O L7 OC7Mx=0 TC7=TCx TC7>TCx IOCx=OMx/OLx IOC7=OM7/OL7 OC7Mx=1 TC7=TCx TC7>TCx IOCx=OC7Dx IOCx=OC7Dx IOC7=OC7D7 +OMx/OLx IOC7=OC7D7 OC7M7=1 OC7Mx=0 TC7=TCx TC7>TCx IOCx=OMx/OLx IOC7=OC7D7 Note: in Table 15-10, the IOS7 and IOSx should be set to 1 IOSx is the register TIOS bit x, OC7Mx is the register OC7M bit x, TCx is timer Input Capture/Output Compare register, IOCx is channel x, OMx/OLx is the register TCTL1/TCTL2, OC7Dx is the register OC7D bit x. Freescale Semiconductor MC9S12Q128 Rev 1.10 441 Chapter 15 Timer Module (TIM16B6C) IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value. 15.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4) Module Base + 0x000A 7 6 5 4 3 2 1 0 R EDG7B W Reset 0 0 0 0 0 0 0 0 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A Figure 15-16. Timer Control Register 3 (TCTL3) Module Base + 0x000B 7 6 5 4 3 2 1 0 R EDG3B W Reset 0 0 0 0 0 0 0 0 EDG3A EDG2B EDG2A Figure 15-17. Timer Control Register 4 (TCTL4) Read: Anytime Write: Anytime. Table 15-11. TCTL3/TCTL4 Field Descriptions Field 7:0 EDGnB EDGnA Description Input Capture Edge Control — These six pairs of control bits configure the input capture edge detector circuits. Table 15-12. Edge Detector Circuit Configuration EDGnB 0 0 1 1 EDGnA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) 442 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.3.2.10 Timer Interrupt Enable Register (TIE) Module Base + 0x000C 7 6 5 4 3 2 1 0 R C7I W Reset 0 0 0 0 0 0 0 0 C6I C5I C4I C3I C2I C1I C0I Figure 15-18. Timer Interrupt Enable Register (TIE) Read: Anytime Write: Anytime. CAUTION User software must ensure that C1I and C0I remain clear. Table 15-13. TIE Field Descriptions Field 7:0 C7I:C0I Description Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. 15.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 6 5 4 3 2 1 0 R TOI W Reset 0 0 0 0 TCRE PR2 0 PR1 0 PR0 0 0 0 0 0 = Unimplemented or Reserved Figure 15-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. Freescale Semiconductor MC9S12Q128 Rev 1.10 443 Chapter 15 Timer Module (TIM16B6C) Table 15-14. TSCR2 Field Descriptions Field 7 TOI 3 TCRE Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set. Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset inhibited and counter free runs. 1 Counter reset by a successful output compare 7. Note: If TC7 = 0x0000 and TCRE = 1, TCNT stays at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF will never be set when TCNT is reset from 0xFFFF to 0x0000. TCRE=1 and TC7!=0, the TCNT cycle period is TC7 x "prescaler counter width" + "1 Bus Clock", for a more detailed explanation please refer to Section 15.4.3, “Output Compare Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 15-15. 2 PR[2:0] Table 15-15. Timer Clock Selection PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Timer Clock Bus Clock / 1 Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 444 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E 7 6 5 4 3 2 1 0 R C7F W Reset 0 0 0 0 0 0 0 0 C6F C5F C4F C3F C2F Figure 15-20. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. Table 15-16. TRLG1 Field Descriptions Field 7:2 C[7:2]F Description Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output compare event occurs. Clear a channel flag by writing one to it. When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared. 15.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) Module Base + 0x000F 7 6 5 4 3 2 1 0 R TOF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 15-21. Main Timer Interrupt Flag 2 (TFLG2) TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. Table 15-17. TRLG2 Field Descriptions Field 7 TOF Description Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.) Freescale Semiconductor MC9S12Q128 Rev 1.10 445 Chapter 15 Timer Module (TIM16B6C) 15.3.2.14 Timer Input Capture/Output Compare Registers High and Low 2–7 (TCxH and TCxL) Module Base + 0x0014 = TC2H 0x0016 = TC3H 0x0018 = TC4H 0x001A = TC5H 0x001C = TC6H 0x001E = TC7H 14 13 12 11 10 9 0 15 R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Figure 15-22. Timer Input Capture/Output Compare Register x High (TCxH) Module Base + 0x0015 = TC2L 0x0017 = TC3L 0x0019 = TC4L 0x001B = TC5L 0x001D = TC6L 0x001F = TC7L 6 5 4 3 2 1 0 7 R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 15-23. Timer Input Capture/Output Compare Register x Low (TCxL) Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read: Anytime Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 446 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 7 6 5 4 3 2 1 0 R W Reset 0 PAEN 0 0 PAMOD 0 PEDGE 0 CLK1 0 CLK0 0 PAOVI 0 PAI 0 Unimplemented or Reserved Figure 15-24. 16-Bit Pulse Accumulator Control Register (PACTL) When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7. Read: Any time Write: Any time Table 15-18. PACTL Field Descriptions Field 6 PAEN Description Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse accumulator can function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator system disabled. 1 Pulse Accumulator system enabled. Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See Table 15-19. 0 Event counter mode. 1 Gated time accumulation mode. Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). For PAMOD bit = 0 (event counter mode). See Table 15-19. 0 Falling edges on IOC7 pin cause the count to be incremented. 1 Rising edges on IOC7 pin cause the count to be incremented. For PAMOD bit = 1 (gated time accumulation mode). 0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling edge on IOC7 sets the PAIF flag. 1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge on IOC7 sets the PAIF flag. Clock Select Bits — Refer to Table 15-20. Pulse Accumulator Overflow Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. 5 PAMOD 4 PEDGE 3:2 CLK[1:0] 1 PAOVI 0 PAI Freescale Semiconductor MC9S12Q128 Rev 1.10 447 Chapter 15 Timer Module (TIM16B6C) Table 15-19. Pin Action PAMOD 0 0 1 1 PEDGE 0 1 0 1 Pin Action Falling edge Rising edge Div. by 64 clock enabled with pin high level Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the ÷64 clock is generated by the timer prescaler. Table 15-20. Timer Clock Selection CLK1 0 0 1 1 CLK0 0 1 0 1 Timer Clock Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency For the description of PACLK please refer Figure 15-24. If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. 15.3.2.16 Pulse Accumulator Flag Register (PAFLG) Module Base + 0x0021 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 PAOVF PAIF 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 15-25. Pulse Accumulator Flag Register (PAFLG) Read: Anytime Write: Anytime When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register. 448 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) Table 15-21. PAFLG Field Descriptions Field 1 PAOVF 0 PAIF Description Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. This bit is cleared automatically by a write to the PAFLG register with bit 1 set. Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set. Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006) is set. 15.3.2.17 Pulse Accumulators Count Registers (PACNT) Module Base + 0x0022 15 14 13 12 11 10 9 0 R PACNT15 W Reset 0 0 0 0 0 0 0 0 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 Figure 15-26. Pulse Accumulator Count Register High (PACNTH) Module Base + 0x0023 7 6 5 4 3 2 1 0 R PACNT7 W Reset 0 0 0 0 0 0 0 0 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 Figure 15-27. Pulse Accumulator Count Register Low (PACNTL) Read: Anytime Write: Anytime These registers contain the number of active input edges on its input pin since the last reset. When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. NOTE Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock first. Freescale Semiconductor MC9S12Q128 Rev 1.10 449 Chapter 15 Timer Module (TIM16B6C) 15.4 Functional Description This section provides a complete functional description of the timer TIM16B6C block. Please refer to the detailed timer block diagram in Figure 15-28 as necessary. Bus Clock CLK[1:0] PR[2:1:0] PACLK PACLK/256 PACLK/65536 Channel 7 output compare MUX TCRE CxI CxF CLEAR COUNTER 16-BIT COUNTER TE CHANNEL 2 16-BIT COMPARATOR TC2 EDG0A EDG0B EDGE DETECT C2F OM:OL2 TOV2 IOC2 C3F OM:OL2 EDGE DETECT TOV2 IOC3 C2F CH. 2CAPTURE IOC2 PIN IOC2 PIN LOGIC CH. 2COMPARE TOF TOI INTERRUPT LOGIC TOF PRESCALER TCNT(hi):TCNT(lo) CHANNEL 3 16-BIT COMPARATOR TC3 EDG1A EDG1B C3F CH. 3 CAPTURE IOC3 PIN LOGIC CH. 3 COMPARE IOC3 PIN CHANNEL4 CHANNEL7 16-BIT COMPARATOR TC7 EDG7A EDG7B EDGE DETECT C7F OM:O73 TOV7 IOC7 C7F CH.7 CAPTURE PA INPUT IOC7 PIN LOGIC CH. 7 COMPARE IOC7 PIN PAOVF PACNT(hi):PACNT(lo) PEDGE PAE EDGE DETECT PACLK/65536 PACLK/256 INTERRUPT REQUEST PAOVI PAOVF 16-BIT COUNTER PACLK TEN INTERRUPT LOGIC DIVIDE-BY-64 PAI PAIF PAIF Bus Clock PAOVF PAOVI Figure 15-28. Detailed Timer Block Diagram 450 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.4.1 Prescaler The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64, or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). 15.4.2 Input Capture Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx. The minimum pulse width for the input capture input is greater than two bus clocks. An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. 15.4.3 Output Compare Setting the I/O select bit, IOSx, configures channel x as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx disconnects the pin from the output logic. Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel flag. A successful output compare on channel 7 overrides output compares on all other output compare channels. The output compare 7 mask register masks the bits in the output compare 7 data register. The timer counter reset enable bit, TCRE, enables channel 7 output compares to reset the timer counter. A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input. Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it will last only one bus cycle then reset to 0. Freescale Semiconductor MC9S12Q128 Rev 1.10 451 Chapter 15 Timer Module (TIM16B6C) Note: in Figure 15-29,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock Figure 15-29. The TCNT cycle diagram under TCRE=1 condition prescaler counter TC7 0 1 bus clock 1 ----TC7-1 TC7 0 TC7 event TC7 event 15.4.4 Pulse Accumulator The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes: Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI. Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two bus clocks. 15.4.5 Event Counter Mode Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7 pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to increment the count. NOTE The PACNT input and timer channel 7 use the same pin IOC7. To use the IOC7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare 7 mask bit, OC7M7. The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin since the last reset. The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear. 452 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 15 Timer Module (TIM16B6C) 15.4.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE bit selects low levels or high levels to enable the divided-by-64 clock. The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to generate interrupt requests. The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the last reset. NOTE The timer prescaler generates the divided-by-64 clock. If the timer is not active, there is no divided-by-64 clock. 15.5 Resets The reset state of each individual bit is listed within Section 15.3, “Memory Map and Registers” which details the registers and their bit fields. 15.6 Interrupts This section describes interrupts originated by the TIM16B6C block. Table 15-22 lists the interrupts generated by the TIM16B6C to communicate with the MCU. Table 15-22. TIM16B8CV1 Interrupts Interrupt C[7:2]F PAOVI PAOVF TOF 1. Chip dependent. Offset (1) Vector1 — — — — Priority1 — — — — Source Timer Channel 7–2 Pulse Accumulator Input Pulse Accumulator Overflow Timer Overflow Description Active high timer channel interrupts 7–0 Active high pulse accumulator input interrupt Pulse accumulator overflow interrupt Timer Overflow interrupt — — — — The TIM16B6C uses a total of 9 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. 15.6.1 Channel [7:2] Interrupt (C[7:2]F) This active high outputs will be asserted by the module to request a timer channel 7–2 interrupt to be serviced by the system controller. CAUTION User software must ensure that C1I and C0I remain clear. Freescale Semiconductor MC9S12Q128 Rev 1.10 453 Chapter 15 Timer Module (TIM16B6C) 15.6.2 Pulse Accumulator Input Interrupt (PAOVI) This active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller. 15.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) This active high output will be asserted by the module to request a timer pulse accumulator overflow interrupt to be serviced by the system controller. 15.6.4 Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller. 454 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.1 Introduction The VREG3V3V2 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V (typical). 16.1.1 Features The block VREG3V3V2 includes these distinctive features: • Two parallel, linear voltage regulators — Bandgap reference • Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) • Low-voltage reset (LVR) 16.1.2 Modes of Operation There are three modes VREG3V3V2 can operate in: • Full-performance mode (FPM) (MCU is not in stop mode) The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR (power-on reset) are available. • Reduced-power mode (RPM) (MCU is in stop mode) The purpose is to reduce power consumption of the device. The output voltage may degrade to a lower value than in full-performance mode, additionally the current sourcing capability is substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled. • Shutdown mode Controlled by VREGEN (see device overview chapter for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a high impedance state, only the POR feature is available, LVD and LVR are disabled. This mode must be used to disable the chip internal regulator VREG3V3V2, i.e., to bypass the VREG3V3V2 to use external supplies. Freescale Semiconductor MC9S12Q128 Rev 1.10 455 Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.1.3 Block Diagram Figure 16-1 shows the function principle of VREG3V3V2 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages. REG2 VDDR VDDA REG VDDPLL VSSPLL REG1 VDD LVD LVR LVR POR POR VSSA VSS VREGEN CTRL LVI REG: Regulator Core LVD: Low Voltage Detect CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset PIN Figure 16-1. VREG3V3 Block Diagram 456 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.2 External Signal Description Due to the nature of VREG3V3V2 being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 16-1 shows all signals of VREG3V3V2 associated with pins. Table 16-1. VREG3V3V2 — Signal Properties Name VDDR VDDA VSSA VDD VSS VDDPLL VSSPLL VREGEN (optional) Port — — — — — — — — Function VREG3V3V2 power input (positive supply) VREG3V3V2 quiet input (positive supply) VREG3V3V2 quiet input (ground) VREG3V3V2 primary output (positive supply) VREG3V3V2 primary output (ground) VREG3V3V2 secondary output (positive supply) VREG3V3V2 secondary output (ground) VREG3V3V2 (Optional) Regulator Enable Reset State — — — — — — — — Pull Up — — — — — — — — NOTE Check device overview chapter for connectivity of the signals. 16.2.1 VDDR — Regulator Power Input Signal VDDR is the power input of VREG3V3V2. All currents sourced into the regulator loads flow through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR can smoothen ripple on VDDR. For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without a VREGEN pin. 16.2.2 VDDA, VSSA — Regulator Reference Supply Signals VDDA/VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply. Freescale Semiconductor MC9S12Q128 Rev 1.10 457 Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.2.3 VDD, VSS — Regulator Output1 (Core Logic) Signals VDD/VSS are the primary outputs of VREG3V3V2 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode an external supply at VDD/VSS can replace the voltage regulator. 16.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Signals VDDPLL/VSSPLL are the secondary outputs of VREG3V3V2 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode an external supply at VDDPLL/VSSPLL can replace the voltage regulator. 16.2.5 VREGEN — Optional Regulator Enable This optional signal is used to shutdown VREG3V3V2. In that case VDD/VSS and VDDPLL/VSSPLL must be provided externally. Shutdown Mode is entered with VREGEN being low. If VREGEN is high, the VREG3V3V2 is either in Full Performance Mode or in Reduced Power Mode. For the connectivity of VREGEN see device overview chapter. NOTE Switching from FPM or RPM to shutdown of VREG3V3V2 and vice versa is not supported while the MCU is powered. 16.3 Memory Map and Register Definition This subsection provides a detailed description of all registers accessible in VREG3V3V2. 16.3.1 Module Memory Map Figure 16-2 provides an overview of all used registers. Table 16-2. VREG3V3V2 Memory Map Address Offset 0x0000 Use VREG3V3V2 Control Register (VREGCTRL) Access R/W 458 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.3.2 Register Descriptions The following paragraphs describe, in address order, all the VREG3V3V2 registers and their individual bits. 16.3.2.1 VREG3V3V2 — Control Register (VREGCTRL) The VREGCTRL register allows to separately enable features of VREG3V3V2. Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 LVDS LVIE LVIF 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-2. VREG3V3 — Control Register (VREGCTRL) Table 16-3. MCCTL1 Field Descriptions Field 2 LVDS 1 LVIE 0 LVIF Description Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect. 0 Input voltage VDDA is above level VLVID or RPM or shutdown mode. 1 Input voltage VDDA is below level VLVIA and FPM. Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set. Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. NOTE On entering the Reduced Power Mode the LVIF is not cleared by the VREG3V3V2. 16.4 Functional Description Block VREG3V3V2 is a voltage regulator as depicted in Figure 16-1. The regulator functional elements are the regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the interface to the digital core logic but also manages the operating modes of VREG3V3V2. Freescale Semiconductor MC9S12Q128 Rev 1.10 459 Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.4.1 REG — Regulator Core VREG3V3V2, respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only REG1 providing the supply at VDD/VSS is explained. The principle is also valid for REG2. The regulator is a linear series regulator with a bandgap reference in its Full Performance Mode and a voltage clamp in Reduced Power Mode. All load currents flow from input VDDR to VSS or VSSPLL, the reference circuits are connected to VDDA and VSSA. 16.4.2 Full-Performance Mode In Full Performance Mode, a fraction of the output voltage (VDD) and the bandgap reference voltage are fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver which basically is a large NMOS transistor connected to the output. 16.4.3 Reduced-Power Mode In Reduced Power Mode, the driver gate is connected to a buffered fraction of the input voltage (VDDR). The operational amplifier and the bandgap are disabled to reduce power consumption. 16.4.4 LVD — Low-Voltage Detect sub-block LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input voltage (VDDA–VSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode and Shutdown Mode. 16.4.5 POR — Power-On Reset This functional block monitors output VDD. If VDD is below VPORD, signal POR is high, if it exceeds VPORD, the signal goes low. The transition to low forces the CPU in the power-on sequence. Due to its role during chip power-up this module must be active in all operating modes of VREG3V3V2. 16.4.6 LVR — Low-Voltage Reset Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal LVR asserts and when rising above the deassertion level (VLVRD) signal LVR negates again. The LVR function is available only in Full Performance Mode. 16.4.7 CTRL — Regulator Control This part contains the register block of VREG3V3V2 and further digital functionality needed to control the operating modes. CTRL also represents the interface to the digital core logic. 460 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 16.5 Resets This subsection describes how VREG3V3V2 controls the reset of the MCU.The reset values of registers and signals are provided in Section 16.3, “Memory Map and Register Definition”. Possible reset sources are listed in Table 16-4. Table 16-4. VREG3V3V2 — Reset Sources Reset Source Power-on reset Low-voltage reset Always active Available only in Full Performance Mode Local Enable 16.5.1 Power-On Reset During chip power-up the digital core may not work if its supply voltage VDD is below the POR deassertion level (VPORD). Therefore, signal POR which forces the other blocks of the device into reset is kept high until VDD exceeds VPORD. Then POR becomes low and the reset generator of the device continues the start-up sequence. The power-on reset is active in all operation modes of VREG3V3V2. 16.5.2 Low-Voltage Reset For details on low-voltage reset see Section 16.4.6, “LVR — Low-Voltage Reset”. 16.6 Interrupts This subsection describes all interrupts originated by VREG3V3V2. The interrupt vectors requested by VREG3V3V2 are listed in Table 16-5. Vector addresses and interrupt priorities are defined at MCU level. Table 16-5. VREG3V3V2 — Interrupt Vectors Interrupt Source Low Voltage Interrupt (LVI) Local Enable LVIE = 1; Available only in Full Performance Mode 16.6.1 LVI — Low-Voltage Interrupt In FPM VREG3V3V2 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA the status bit LVDS is set to 1. Vice versa, LVDS is reset to 0 when VDDA rises above level VLVID. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1. NOTE On entering the Reduced Power Mode, the LVIF is not cleared by the VREG3V3V2. Freescale Semiconductor MC9S12Q128 Rev 1.10 461 Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description 462 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.1 Introduction The FTS32K module implements a 32 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 32 Kbytes organized as 512 rows of 64 bytes with an erase sector size of eight rows (512 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words. The Flash array is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both mass erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase is generated internally. It is not possible to read from a Flash array while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 17.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to program, erase, or erase verify the Flash array memory. 17.1.2 • • • • • • • • Features 32 Kbytes of Flash memory comprised of one 32 Kbyte array divided into 64 sectors of 512 bytes Automated program and erase algorithm Interrupts on Flash command completion and command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Flexible protection scheme to prevent accidental program or erase Single power supply for Flash program and erase operations Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12Q128 Rev 1.10 463 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.1.3 Modes of Operation See Section 17.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 17.4.1, “Flash Command Operations”. 17.1.4 Block Diagram Figure 17-1 shows a block diagram of the FTS32K module. FTS32K Flash Interface Command Pipeline Command Complete Interrupt Command Buffer Empty Interrupt Flash Array cmd2 addr2 data2 cmd1 addr1 data1 16K * 16 Bits sector 0 sector 1 Registers Protection sector 63 Security Oscillator Clock Clock Divider FCLK Figure 17-1. FTS32K Block Diagram 17.2 External Signal Description The FTS32K module contains no signals that connect off-chip. 464 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.3 Memory Map and Registers This section describes the FTS32K memory map and registers. 17.3.1 Module Memory Map The FTS32K memory map is shown in Figure 17-2. The HCS12 architecture places the Flash array addresses between 0x4000 and 0xFFFF, which corresponds to three 16 Kbyte pages. The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from address 0x8000 to 0xBFFF to any physical 16K byte page in the Flash array memory.1 The FPROT register (see Section 17.3.2.5) can be set to globally protect the entire Flash array. Three separate areas, one starting from the Flash array starting address (called lower) towards higher addresses, one growing downward from the Flash array end address (called higher), and the remaining addresses, can be activated for protection. The Flash array addresses covered by these protectable regions are shown in Figure 17-2. The higher address area is mainly targeted to hold the boot loader code since it covers the vector space. The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field described in Table 17-1. Table 17-1. Flash Configuration Field Flash Address 0xFF00–0xFF07 0xFF08–0xFF0C 0xFF0D 0xFF0E 0xFF0F Size (bytes) 8 5 1 1 1 Description Backdoor Key to unlock security Reserved Flash Protection byte Refer to Section 17.3.2.5, “Flash Protection Register (FPROT)” Reserved Flash Security/Options byte Refer to Section 17.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top fixed 16 Kbyte pages can be seen twice in the MCU memory map. Freescale Semiconductor MC9S12Q128 Rev 1.10 465 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) MODULE BASE + 0x0000 MODULE BASE + 0x000F FLASH_START = 0x4000 0x4200 0x4400 0x4800 Flash Protected Low Sectors 512 bytes, 1, 2, 4 Kbytes Flash Registers 16 bytes 0x5000 0x3E Flash Array 0x8000 16K PAGED MEMORY 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x3E–0x3F correspond to the PPAGE register content Figure 17-2. Flash Memory Map 466 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Table 17-2. Flash Array Memory Map Summary MCU Address Range 0x4000–0x7FFF PPAGE Unpaged (0x3E) Protectable Low Range 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x3E 0x8000–0x83FF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged (0x3F) N.A. 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 0x1C000–0x1FFFF 0x1C000–0x1FFFF N.A. 0x18000–0x1BFFF Protectable High Range N.A. Array Relative Address(1) 0x18000–0x1BFFF Freescale Semiconductor MC9S12Q128 Rev 1.10 467 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 17-3. Detailed descriptions of each register bit are provided. Register Name R W R 0x0001 FSEC W 0x0002 R RESERVED1 W 0x0000 FCLKDIV (1) Bit 7 FDIVLD KEYEN1 0 6 PRDIV8 KEYEN0 0 5 FDIV5 NV5 0 4 FDIV4 NV4 0 3 FDIV3 NV3 0 2 FDIV2 NV2 0 1 FDIV1 SEC1 0 Bit 0 FDIV0 SEC0 0 0x0003 FCNFG 0x0004 FPROT 0x0005 FSTAT 0x0006 FCMD 0x0007 RESERVED21 0x0008 FADDRHI1 0x0009 FADDRLO1 0x000A FDATAHI1 0x000B FDATALO1 0x000C RESERVED31 0x000D RESERVED41 0x000E RESERVED51 0x000F RESERVED61 R W R W R W R W R W R W R W R W R W R W R W R W R W CBEIE FPOPEN CBEIF 0 0 0 CCIE NV6 CCIF KEYACC FPHDIS PVIOL CMDB5 0 0 0 0 0 0 FPHS1 ACCERR 0 0 FPHS0 0 0 0 FPLDIS BLANK FPLS1 FAIL 0 0 FPLS0 DONE CMDB6 0 0 CMDB2 0 CMDB0 0 FABHI FABLO FDHI FDLO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-3. Flash Register Summary 1. Intended for factory test purposes only. 468 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset FDIVLD PRDIV8 0 0 FDIV5 0 FDIV4 0 FDIV3 0 FDIV2 0 FDIV1 0 FDIV0 0 = Unimplemented or Reserved Figure 17-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 17-3. FCLKDIV Field Descriptions Field 7 FDIVLD 6 PRDIV8 5–0 FDIV[5:0] Description Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash clock divider 1 The oscillator clock is divided by 8 before feeding into the Flash clock divider Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to Section 17.4.1.1, “Writing the FCLKDIV Register” for more information. 17.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 F F F F F F F F = Unimplemented or Reserved Figure 17-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence, indicated by F in Figure 17-5. Freescale Semiconductor MC9S12Q128 Rev 1.10 469 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Table 17-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 17-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 17-6. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 17-5. Flash KEYEN States KEYEN[1:0] 00 01 (1) Status of Backdoor Key Access DISABLED DISABLED ENABLED 10 11 DISABLED 1. Preferred KEYEN state to disable Backdoor Key Access. Table 17-6. Flash Security States SEC[1:0] 00 01(1) 10 Status of Security Secured Secured Unsecured 11 Secured 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 17.4.3, “Flash Module Security”. 17.3.2.3 RESERVED1 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-6. RESERVED1 All bits read 0 and are not writable. 470 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable. KEYACC is only writable if the KEYEN bit in the FSEC register is set to the enabled state (see Section 17.3.2.2). Table 17-7. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module. 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set (see Section 17.3.2.6) Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being completed in the Flash module. 0 Command Complete interrupts disabled 1 An interrupt will be requested whenever the CCIF flag is set (see Section 17.3.2.6) Enable Security Key Writing. 0 Flash writes are interpreted as the start of a command write sequence 1 Writes to the Flash array are interpreted as a backdoor key while reads of the Flash array return invalid data 6 CCIE 5 KEYACC 17.3.2.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase. Module Base + 0x0004 7 6 5 4 3 2 1 0 R FPOPEN W Reset F F F F F F F F NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 Figure 17-8. Flash Protection Register (FPROT) The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until Freescale Semiconductor MC9S12Q128 Rev 1.10 471 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 17-8. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to. A protected Flash sector is disabled by FPHDIS and FPLDIS while the size of the protected sector is defined by FPHS[1:0] and FPLS[1:0] in the FPROT register. Trying to alter any of the protected areas will result in a protect violation error and the PVIOL flag will be set in the FSTAT register (see Section 17.3.2.6). A mass erase of the whole Flash array is only possible when protection is fully disabled by setting the FPOPEN, FPLDIS, and FPHDIS bits. An attempt to mass erase a Flash array while protection is enabled will set the PVIOL flag in the FSTAT register. Table 17-8. FPROT Field Descriptions Field 7 FPOPEN Description Protection Function for Program or Erase — It is possible using the FPOPEN bit to either select address ranges to be protected using FPHDIS, FPLDIS, FPHS[1:0] and FPLS[1:0] or to select the same ranges to be unprotected. When FPOPEN is set, FPxDIS enables the ranges to be protected, whereby clearing FPxDIS enables protection for the range specified by the corresponding FPxS[1:0] bits. When FPOPEN is cleared, FPxDIS defines unprotected ranges as specified by the corresponding FPxS[1:0] bits. In this case, setting FPxDIS enables protection. Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 17-9. This function allows the main part of the Flash array to be protected while a small range can remain unprotected for EEPROM emulation. 0 The FPHDIS and FPLDIS bits define Flash address ranges to be unprotected 1 The FPHDIS and FPLDIS bits define Flash address ranges to be protected Nonvolatile Flag Bit — The NV6 bit should remain in the erased state for future enhancements. Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in the higher space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 17-10. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected sector in the lower space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 17-11. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. 6 NV6 5 FPHDIS 4–3 FPHS[1:0] 2 FPLDIS 1–0 FPLS[1:0] 472 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Table 17-9. Flash Protection Function FPOPEN 1 1 1 1 0 0 0 FPHDIS 1 1 0 0 1 0 1 FPHS[1] x x x x x x x FPHS[0] x x x x x x x FPLDIS 1 0 1 0 1 1 0 FPLS[1] x x x x x x x x FPLS[0] x x x x x x x x Function(1) No protection Protect low range Protect high range Protect high and low ranges Full Flash array protected Unprotected high range Unprotected low range Unprotected high and low ranges 0 0 x x 0 1. For range sizes refer to Table 17-10 and or Table 17-11. Table 17-10. Flash Protection Higher Address Range FPHS[1:0] 00 01 10 11 Address Range 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF Range Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Table 17-11. Flash Protection Lower Address Range FPLS[1:0] 00 01 10 11 Address Range 0x4000–0x41FF 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF Range Size 512 bytes 1 Kbyte 2 Kbytes 4 Kbytes Figure 17-9 illustrates all possible protection scenarios. Although the protection scheme is loaded from the Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. Freescale Semiconductor MC9S12Q128 Rev 1.10 473 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) FPHDIS = 1 FPLDIS = 1 Scenario 7 FPHDIS = 1 FPLDIS = 0 6 FPHDIS = 0 FPLDIS = 1 5 FPHDIS = 0 FPLDIS = 0 4 FPLS[1:0] 7 Freescale Semiconductor FPHS[1:0] FPLS[1:0] FPHS[1:0] 0xFFFF Scenario FPOPEN = 1 3 2 1 0 0xFFFF Protected Flash FPOPEN = 0 Figure 17-9. Flash Protection Scenarios 17.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed. All valid transitions between Flash protection scenarios are specified in Table 17-12. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. Table 17-12. Flash Protection Scenario Transitions From Protection Scenario 0 1 2 3 4 5 X To Protection Scenario(1) 0 X 1 X X X 2 X 3 X X X X X X X X X 4 5 6 474 MC9S12Q128 Rev 1.10 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Table 17-12. Flash Protection Scenario Transitions From Protection Scenario 6 To Protection Scenario(1) 0 1 X X 2 3 X X 4 X X X 5 6 X X X 7 7 X X 1. Allowed transitions marked with X. 17.3.2.6 Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution. Module Base + 0x0005 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL DONE 0 0 0 1 = Unimplemented or Reserved Figure 17-10. Flash Status Register (FSTAT) In normal modes, bits CBEIF, PVIOL, and ACCERR are readable and writable, bits CCIF and BLANK are readable and not writable, remaining bits, including FAIL and DONE, read 0 and are not writable. In special modes, FAIL is readable and writable while DONE is readable but not writable. FAIL must be clear in special modes when starting a command write sequence. Table 17-13. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 17-26). 0 Buffers are full 1 Buffers are ready to accept a new command Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 17-26). 0 Command in progress 1 All commands are completed 6 CCIF Freescale Semiconductor MC9S12Q128 Rev 1.10 475 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Table 17-13. FSTAT Field Descriptions Field 5 PVIOL Description Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command. 0 No protection violation detected 1 Protection violation has occurred Access Error — The ACCERR flag indicates an illegal access to the Flash array caused by either a violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in the FCMD register) or the execution of a CPU STOP instruction while a command is executing (CCIF=0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch another command. 0 No access error detected 1 Access error has occurred Flash Array Has Been Verified as Erased — The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased. The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 If an erase verify command has been requested, and the CCIF flag is set, then a 0 in BLANK indicates the array is not erased 1 Flash array verifies as erased Flag Indicating a Failed Flash Operation — In special modes, the FAIL flag will set if the erase verify operation fails (Flash array verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. While FAIL is set, it is not possible to launch another command. 0 Flash operation completed without error 1 Flash operation failed Flag Indicating a Failed Operation is not Active — In special modes, the DONE flag will clear if a program, erase, or erase verify operation is active. 0 Flash operation is active 1 Flash operation is not active 4 ACCERR 2 BLANK 1 FAIL 0 DONE 17.3.2.7 Flash Command Register (FCMD) The FCMD register defines the Flash commands. Module Base + 0x0006 7 6 5 4 3 2 1 0 R W Reset 0 CMDB6 0 0 CMDB5 0 0 0 CMDB2 0 CMDB0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. 476 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Table 17-14. FCMD Field Descriptions Field 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Description Valid Flash commands are shown in Table 17-15. An attempt to execute any command other than those listed in Table 17-15 will set the ACCERR bit in the FSTAT register (see Section 17.3.2.6). Table 17-15. Valid Flash Command List CMDB 0x05 0x20 0x40 0x41 NVM Command Erase verify Word program Sector erase Mass erase 17.3.2.8 RESERVED2 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-12. RESERVED2 All bits read 0 and are not writable. 17.3.2.9 \ Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 7 6 5 4 3 2 1 0 R W Reset 0 0 FABHI 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-13. Flash Address High Register (FADDRHI) Freescale Semiconductor MC9S12Q128 Rev 1.10 477 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Module Base + 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 17-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [8:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 17.3.2.10 Flash Data Register (FDATA) FDATAHI and FDATALO are the Flash data registers. Module Base + 0x000A 7 6 5 4 3 2 1 0 R FDHI W Reset 0 0 0 0 0 0 0 0 Figure 17-15. Flash Data High Register (FDATAHI) Module Base + 0x000B 7 6 5 4 3 2 1 0 R FDLO W Reset 0 0 0 0 0 0 0 0 Figure 17-16. Flash Data Low Register (FDATALO) In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 17.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. 478 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Module Base + 0x000C 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-17. RESERVED3 All bits read 0 and are not writable. 17.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-18. RESERVED4 All bits read 0 and are not writable. 17.3.2.13 RESERVED5 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000E 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-19. RESERVED5 All bits read 0 and are not writable. 17.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12Q128 Rev 1.10 479 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) Module Base + 0x000F 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-20. RESERVED6 All bits read 0 and are not writable. 17.4 17.4.1 Functional Description Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase FCLK is derived from the oscillator clock via a programmable divider. The FCMD register as well as the associated FADDR and FDATA registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the necessary data and address can be stored to the buffer while the previous command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row, as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated, if enabled. The next sections describe: • How to write the FCLKDIV register • Command write sequence used to program, erase or erase verify the Flash array • Valid Flash commands • Errors resulting from illegal Flash operations 17.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, it is first necessary to write the FCLKDIV register to divide the oscillator clock down to within the 150-kHz to 200-kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), 480 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 17-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz. As a result, the Flash algorithm timings are increased over optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% Command execution time will increase proportionally with the period of FCLK. CAUTION Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash array with an input clock < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash array due to overstress. Setting FCLKDIV to a value such that (1/FCLK + Tbus) < 5µs can result in incomplete programming or erasure of the Flash array cells. If the FCLKDIV register is written, the bit FDIVLD is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. Freescale Semiconductor MC9S12Q128 Rev 1.10 481 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) START Tbus < 1ms? yes PRDIV8=0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock 12.8MHz? yes no PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK=oscillator_clock PRDCLK[MHz]*(5+Tbus[ms]) an integer? yes no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ms])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ms])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[ms] > 5 AND FCLK > 0.15MHz ? no yes END yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 17-21. PRDIV8 and FDIV Bits Determination Procedure 482 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data, and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash array memory. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. When the CBEIF flag is cleared in step 3, the CCIF flag is cleared by the Flash command controller indicating that the command was successfully launched. For all command write sequences, the CBEIF flag will set after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. A buffered command will wait for the active operation to be completed before being launched. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. Freescale Semiconductor MC9S12Q128 Rev 1.10 483 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.1.3 Valid Flash Commands Table 17-16 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 17-16. Valid Flash Commands FCMD 0x05 0x20 0x40 0x41 Meaning Erase Verify Program Sector Erase Mass Erase Function on Flash Array Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion. Program a word (2 bytes) in the Flash array. Erase all 512 bytes in a sector of the Flash array. Erase all bytes in the Flash array. A mass erase of the full Flash array is only possible when FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 484 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 17-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the Flash array are verified to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. Freescale Semiconductor MC9S12Q128 Rev 1.10 485 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Array Address and Dummy Data Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes Erase Verify Status BLANK Set? no yes EXIT Flash Array Erased EXIT Flash Array Not Erased Figure 17-22. Example Erase Verify Command Flow 486 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 17-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. Freescale Semiconductor MC9S12Q128 Rev 1.10 487 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no Write: Flash Address and program Data yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. 2. Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 3. Bit Polling for Buffer Empty Check CBEIF Set? no yes Sequential Programming Decision Next Word? no Read: FSTAT register yes Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 17-23. Example Program Command Flow 488 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 512 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 17-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while MCU address bits [8:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 489 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Sector Address and Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 17-24. Example Sector Erase Command Flow 490 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 17-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash array to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 491 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Block Address and Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 17-25. Example Mass Erase Command Flow 492 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.1.4 17.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3. Writing to the Flash address space while CBEIF is not set 4. Writing a second word to the Flash address space before executing a program or erase command on the previously written word 5. Writing to any Flash register other than FCMD after writing a word to the Flash address space 6. Writing a second command to the FCMD register before executing the previously written command 7. Writing an invalid command to the FCMD register 8. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register 9. The part enters stop mode and a program or erase command is in progress. The command is aborted and any pending command is killed 10. When security is enabled, a command other than mass erase originating from a non-secure memory or from the background debug mode is written to the FCMD register 11. A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during the command write sequence. If the Flash array is read during execution of an algorithm (CCIF=0), the Flash module will return invalid data and the ACCERR flag will not be set. If an ACCERR flag is set in the FSTAT register, the Flash command controller is locked. It is not possible to launch another command until the ACCERR flag is cleared. 17.4.1.4.2 Protection Violation The PVIOL flag in the FSTAT register will be set during the command write sequence after the word write to the Flash address space if any of the following illegal Flash operations are performed, causing the command write sequence to immediately abort: 1. Writing a Flash address to program in a protected area of the Flash array (see Section 17.3.2.5). 2. Writing a Flash address to erase in a protected area of the Flash array. 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL flag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL flag is cleared. Freescale Semiconductor MC9S12Q128 Rev 1.10 493 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.2 17.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 17.4.5). 17.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost. The high voltage circuitry to the Flash array will be switched off when entering stop mode. CCIF and ACCERR flags will be set. Upon exit from stop mode, the CBEIF flag will be set and any buffered command will not be executed. The ACCERR flag must be cleared before returning to normal operation. NOTE As active Flash commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program and erase execution. 17.4.2.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 17-16 can be executed. If the MCU is secured and is in special single chip mode, the only possible command to execute is mass erase. 17.4.3 Flash Module Security The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 17.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security/options byte at address 0xFF0F in the Flash configuration field must be changed directly by programming address 0xFF0F when the device is unsecured and the higher address sector is unprotected. If the Flash security/options byte is left in the secure state, any reset will cause the MCU to return to the secure operating mode. 17.4.3.1 Unsecuring the MCU using Backdoor Key Access The MCU may only be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor key (four 16-bit words programmed at addresses 0xFF00–0xFF07). If KEYEN[1:0] = 1:0 and the KEYACC bit is set, a write to a backdoor key address in the Flash array triggers a comparison between the written data and the backdoor key data stored in the Flash array. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor key stored in the Flash array, the MCU will be unsecured. The data must be written to the backdoor key 494 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If KEYEN[1:0] = 1:0 in the FSEC register, the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the FCNFG register 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0xFF00 3. Clear the KEYACC bit in the FCNFG register 4. If all four 16-bit words match the backdoor key stored in Flash addresses 0xFF00–0xFF07, the MCU is unsecured and bits SEC[1:0] in the FSEC register are forced to the unsecure state of 1:0 The backdoor key access sequence is monitored by the internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following illegal operations will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor key programmed in the Flash array 2. If the four 16-bit words are written in the wrong sequence 3. If more than four 16-bit words are written 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF 5. If the KEYACC bit does not remain set while the four 16-bit words are written After the backdoor key access sequence has been correctly matched, the MCU will be unsecured. The Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the four word backdoor key by programming bytes 0xFF00–0xFF07 of the Flash configuration field. The security as defined in the Flash security/options byte at address 0xFF0F is not changed by using the backdoor key access sequence to unsecure. The backdoor key stored in addresses 0xFF00–0xFF07 is unaffected by the backdoor key access sequence. After the next reset sequence, the security state of the Flash module is determined by the Flash security/options byte at address 0xFF0F. The backdoor key access sequence has no effect on the program and erase protection defined in the FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor MC9S12Q128 Rev 1.10 495 Chapter 17 32 Kbyte Flash Module (S12FTS32KV1) 17.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 17-1: • FPROT — Flash Protection Register (see Section 17.3.2.5) • FSEC — Flash Security Register (see Section 17.3.2.2) 17.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/array being erased is not guaranteed. 17.4.5 Interrupts The Flash module can generate an interrupt when all Flash commands have completed execution or the Flash address, data, and command buffers are empty. Table 17-17. Flash Interrupt Sources Interrupt Source Flash Address, Data, and Command Buffers are empty All Flash commands have completed execution Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE CCIE Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 17.4.5.1 Description of Interrupt Operation Figure 17-26 shows the logic used for generating interrupts. The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the generation of interrupts. CBEIF CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 17-26. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 17.3.2.4, “Flash Configuration Register (FCNFG)” and Section 17.3.2.6, “Flash Status Register (FSTAT)”. 496 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.1 Introduction The FTS64K module implements a 64 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 64 Kbytes organized as 512 rows of 128 bytes with an erase sector size of eight rows (1024 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words. The Flash array is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both mass erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase is generated internally. It is not possible to read from a Flash array while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 18.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to program, erase, or erase verify the Flash array memory. 18.1.2 • • • • • • • • Features 64 Kbytes of Flash memory comprised of one 64 Kbyte array divided into 64 sectors of 1024 bytes Automated program and erase algorithm Interrupts on Flash command completion and command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Flexible protection scheme to prevent accidental program or erase Single power supply for Flash program and erase operations Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12Q128 Rev 1.10 497 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.1.3 Modes of Operation See Section 18.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 18.4.1, “Flash Command Operations”. 18.1.4 Block Diagram Figure 18-1 shows a block diagram of the FTS64K module. FTS64K Flash Interface Command Pipeline Command Complete Interrupt Command Buffer Empty Interrupt Flash Array cmd2 addr2 data2 cmd1 addr1 data1 32K * 16 Bits sector 0 sector 1 Registers Protection sector 63 Security Oscillator Clock Clock Divider FCLK Figure 18-1. FTS64K Block Diagram 18.2 External Signal Description The FTS64K module contains no signals that connect off-chip. 498 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.3 Memory Map and Registers This section describes the FTS64K memory map and registers. 18.3.1 Module Memory Map The FTS64K memory map is shown in Figure 18-2. The HCS12 architecture places the Flash array addresses between 0x4000 and 0xFFFF, which corresponds to three 16 Kbyte pages. The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from address 0x8000 to 0xBFFF to any physical 16K byte page in the Flash array memory.1 The FPROT register (see Section 18.3.2.5) can be set to globally protect the entire Flash array. Three separate areas, one starting from the Flash array starting address (called lower) towards higher addresses, one growing downward from the Flash array end address (called higher), and the remaining addresses, can be activated for protection. The Flash array addresses covered by these protectable regions are shown in Figure 18-2. The higher address area is mainly targeted to hold the boot loader code since it covers the vector space. The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field described in Table 18-1. Table 18-1. Flash Configuration Field Flash Address 0xFF00–0xFF07 0xFF08–0xFF0C 0xFF0D 0xFF0E 0xFF0F Size (bytes) 8 5 1 1 1 Description Backdoor Key to unlock security Reserved Flash Protection byte Refer to Section 18.3.2.5, “Flash Protection Register (FPROT)” Reserved Flash Security/Options byte Refer to Section 18.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top fixed 16 Kbyte pages can be seen twice in the MCU memory map. Freescale Semiconductor MC9S12Q128 Rev 1.10 499 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) MODULE BASE + 0x0000 MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 0x5000 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes Flash Registers 16 bytes 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x3C–0x3F correspond to the PPAGE register content Figure 18-2. Flash Memory Map 500 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Table 18-2. Flash Array Memory Map Summary MCU Address Range 0x0000–0x3FFF(2) 0x4000–0x7FFF PPAGE Unpaged (0x3D) Unpaged (0x3E) Protectable Low Range N.A. 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x3C 0x3D 0x3E N.A. N.A. 0x8000–0x83FF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged (0x3F) N.A. 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. 0x1C000–0x1FFFF 0x1C000–0x1FFFF N.A. N.A. N.A. 0x10000–0x13FFF 0x14000–0x17FFF 0x18000–0x1BFFF Protectable High Range N.A. N.A. Array Relative Address(1) 0x14000–0x17FFF 0x18000–0x1BFFF Freescale Semiconductor MC9S12Q128 Rev 1.10 501 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 18-3. Detailed descriptions of each register bit are provided. Register Name R W R 0x0001 FSEC W 0x0002 R RESERVED1 W 0x0000 FCLKDIV (1) Bit 7 FDIVLD KEYEN1 0 6 PRDIV8 KEYEN0 0 5 FDIV5 NV5 0 4 FDIV4 NV4 0 3 FDIV3 NV3 0 2 FDIV2 NV2 0 1 FDIV1 SEC1 0 Bit 0 FDIV0 SEC0 0 0x0003 FCNFG 0x0004 FPROT 0x0005 FSTAT 0x0006 FCMD 0x0007 RESERVED21 0x0008 FADDRHI1 0x0009 FADDRLO1 0x000A FDATAHI1 0x000B FDATALO1 0x000C RESERVED31 0x000D RESERVED41 0x000E RESERVED51 0x000F RESERVED61 R W R W R W R W R W R W R W R W R W R W R W R W R W CBEIE FPOPEN CBEIF 0 0 0 CCIE NV6 CCIF KEYACC FPHDIS PVIOL CMDB5 0 0 0 0 0 0 FPHS1 ACCERR 0 0 FPHS0 0 0 0 FPLDIS BLANK FPLS1 FAIL 0 0 FPLS0 DONE CMDB6 0 CMDB2 0 CMDB0 0 FABHI FABLO FDHI FDLO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-3. Flash Register Summary 1. Intended for factory test purposes only. 502 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset FDIVLD PRDIV8 0 0 FDIV5 0 FDIV4 0 FDIV3 0 FDIV2 0 FDIV1 0 FDIV0 0 = Unimplemented or Reserved Figure 18-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 18-3. FCLKDIV Field Descriptions Field 7 FDIVLD 6 PRDIV8 5–0 FDIV[5:0] Description Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash clock divider 1 The oscillator clock is divided by 8 before feeding into the Flash clock divider Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to Section 18.4.1.1, “Writing the FCLKDIV Register” for more information. 18.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 F F F F F F F F = Unimplemented or Reserved Figure 18-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence, indicated by F in Figure 18-5. Freescale Semiconductor MC9S12Q128 Rev 1.10 503 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Table 18-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 18-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 18-6. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 18-5. Flash KEYEN States KEYEN[1:0] 00 01 (1) Status of Backdoor Key Access DISABLED DISABLED ENABLED 10 11 DISABLED 1. Preferred KEYEN state to disable Backdoor Key Access. Table 18-6. Flash Security States SEC[1:0] 00 01(1) 10 Status of Security Secured Secured Unsecured 11 Secured 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 18.4.3, “Flash Module Security”. 18.3.2.3 RESERVED1 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-6. RESERVED1 All bits read 0 and are not writable. 504 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable. KEYACC is only writable if the KEYEN bit in the FSEC register is set to the enabled state (see Section 18.3.2.2). Table 18-7. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module. 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set (see Section 18.3.2.6) Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being completed in the Flash module. 0 Command Complete interrupts disabled 1 An interrupt will be requested whenever the CCIF flag is set (see Section 18.3.2.6) Enable Security Key Writing. 0 Flash writes are interpreted as the start of a command write sequence 1 Writes to the Flash array are interpreted as a backdoor key while reads of the Flash array return invalid data 6 CCIE 5 KEYACC 18.3.2.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase. Module Base + 0x0004 7 6 5 4 3 2 1 0 R FPOPEN W Reset F F F F F F F F NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 Figure 18-8. Flash Protection Register (FPROT) The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until Freescale Semiconductor MC9S12Q128 Rev 1.10 505 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 18-8. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to. A protected Flash sector is disabled by FPHDIS and FPLDIS while the size of the protected sector is defined by FPHS[1:0] and FPLS[1:0] in the FPROT register. Trying to alter any of the protected areas will result in a protect violation error and the PVIOL flag will be set in the FSTAT register (see Section 18.3.2.6). A mass erase of the whole Flash array is only possible when protection is fully disabled by setting the FPOPEN, FPLDIS, and FPHDIS bits. An attempt to mass erase a Flash array while protection is enabled will set the PVIOL flag in the FSTAT register. Table 18-8. FPROT Field Descriptions Field 7 FPOPEN Description Protection Function for Program or Erase — It is possible using the FPOPEN bit to either select address ranges to be protected using FPHDIS, FPLDIS, FPHS[1:0] and FPLS[1:0] or to select the same ranges to be unprotected. When FPOPEN is set, FPxDIS enables the ranges to be protected, whereby clearing FPxDIS enables protection for the range specified by the corresponding FPxS[1:0] bits. When FPOPEN is cleared, FPxDIS defines unprotected ranges as specified by the corresponding FPxS[1:0] bits. In this case, setting FPxDIS enables protection. Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 18-9. This function allows the main part of the Flash array to be protected while a small range can remain unprotected for EEPROM emulation. 0 The FPHDIS and FPLDIS bits define Flash address ranges to be unprotected 1 The FPHDIS and FPLDIS bits define Flash address ranges to be protected Nonvolatile Flag Bit — The NV6 bit should remain in the erased state for future enhancements. Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in the higher space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 18-10. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected sector in the lower space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 18-11. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. 6 NV6 5 FPHDIS 4–3 FPHS[1:0] 2 FPLDIS 1–0 FPLS[1:0] 506 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Table 18-9. Flash Protection Function FPOPEN 1 1 1 1 0 0 0 FPHDIS 1 1 0 0 1 0 1 FPHS[1] x x x x x x x FPHS[0] x x x x x x x FPLDIS 1 0 1 0 1 1 0 FPLS[1] x x x x x x x x FPLS[0] x x x x x x x x Function(1) No protection Protect low range Protect high range Protect high and low ranges Full Flash array protected Unprotected high range Unprotected low range Unprotected high and low ranges 0 0 x x 0 1. For range sizes refer to Table 18-10 and Table 18-11 or . Table 18-10. Flash Protection Higher Address Range FPHS[1:0] 00 01 10 11 Address Range 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF Range Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Table 18-11. Flash Protection Lower Address Range FPLS[1:0] 00 01 10 11 Address Range 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF Range Size 1 Kbyte 2 Kbytes 4 Kbytes 8 Kbytes Figure 18-9 illustrates all possible protection scenarios. Although the protection scheme is loaded from the Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. Freescale Semiconductor MC9S12Q128 Rev 1.10 507 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) FPHDIS = 1 FPLDIS = 1 Scenario 7 FPHDIS = 1 FPLDIS = 0 6 FPHDIS = 0 FPLDIS = 1 5 FPHDIS = 0 FPLDIS = 0 4 FPLS[1:0] 7 Freescale Semiconductor FPHS[1:0] FPLS[1:0] FPHS[1:0] 0xFFFF Scenario FPOPEN = 1 3 2 1 0 0xFFFF Protected Flash FPOPEN = 0 Figure 18-9. Flash Protection Scenarios 18.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed. All valid transitions between Flash protection scenarios are specified in Table 18-12. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. Table 18-12. Flash Protection Scenario Transitions From Protection Scenario 0 1 2 3 4 5 X To Protection Scenario(1) 0 X 1 X X X 2 X 3 X X X X X X X X X 4 5 6 508 MC9S12Q128 Rev 1.10 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Table 18-12. Flash Protection Scenario Transitions From Protection Scenario 6 To Protection Scenario(1) 0 1 X X 2 3 X X 4 X X X 5 6 X X X 7 7 X X 1. Allowed transitions marked with X. 18.3.2.6 Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution. Module Base + 0x0005 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL DONE 0 0 0 1 = Unimplemented or Reserved Figure 18-10. Flash Status Register (FSTAT) In normal modes, bits CBEIF, PVIOL, and ACCERR are readable and writable, bits CCIF and BLANK are readable and not writable, remaining bits, including FAIL and DONE, read 0 and are not writable. In special modes, FAIL is readable and writable while DONE is readable but not writable. FAIL must be clear in special modes when starting a command write sequence. Table 18-13. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 18-26). 0 Buffers are full 1 Buffers are ready to accept a new command Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 18-26). 0 Command in progress 1 All commands are completed 6 CCIF Freescale Semiconductor MC9S12Q128 Rev 1.10 509 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Table 18-13. FSTAT Field Descriptions Field 5 PVIOL Description Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command. 0 No protection violation detected 1 Protection violation has occurred Access Error — The ACCERR flag indicates an illegal access to the Flash array caused by either a violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in the FCMD register) or the execution of a CPU STOP instruction while a command is executing (CCIF=0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch another command. 0 No access error detected 1 Access error has occurred Flash Array Has Been Verified as Erased — The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased. The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 If an erase verify command has been requested, and the CCIF flag is set, then a 0 in BLANK indicates the array is not erased 1 Flash array verifies as erased Flag Indicating a Failed Flash Operation — In special modes, the FAIL flag will set if the erase verify operation fails (Flash array verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. While FAIL is set, it is not possible to launch another command. 0 Flash operation completed without error 1 Flash operation failed Flag Indicating a Failed Operation is not Active — In special modes, the DONE flag will clear if a program, erase, or erase verify operation is active. 0 Flash operation is active 1 Flash operation is not active 4 ACCERR 2 BLANK 1 FAIL 0 DONE 18.3.2.7 Flash Command Register (FCMD) The FCMD register defines the Flash commands. Module Base + 0x0006 7 6 5 4 3 2 1 0 R W Reset 0 CMDB6 0 0 CMDB5 0 0 0 CMDB2 0 CMDB0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. 510 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Table 18-14. FCMD Field Descriptions Field 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Description Valid Flash commands are shown in Table 18-15. An attempt to execute any command other than those listed in Table 18-15 will set the ACCERR bit in the FSTAT register (see Section 18.3.2.6). Table 18-15. Valid Flash Command List CMDB 0x05 0x20 0x40 0x41 NVM Command Erase verify Word program Sector erase Mass erase 18.3.2.8 RESERVED2 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-12. RESERVED2 All bits read 0 and are not writable. 18.3.2.9 \ Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 7 6 5 4 3 2 1 0 R W Reset 0 FABHI 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-13. Flash Address High Register (FADDRHI) \ Freescale Semiconductor MC9S12Q128 Rev 1.10 511 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Module Base + 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 18-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [9:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 18.3.2.10 Flash Data Register (FDATA) FDATAHI and FDATALO are the Flash data registers. Module Base + 0x000A 7 6 5 4 3 2 1 0 R FDHI W Reset 0 0 0 0 0 0 0 0 Figure 18-15. Flash Data High Register (FDATAHI) Module Base + 0x000B 7 6 5 4 3 2 1 0 R FDLO W Reset 0 0 0 0 0 0 0 0 Figure 18-16. Flash Data Low Register (FDATALO) In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 18.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. 512 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Module Base + 0x000C 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-17. RESERVED3 All bits read 0 and are not writable. 18.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-18. RESERVED4 All bits read 0 and are not writable. 18.3.2.13 RESERVED5 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000E 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-19. RESERVED5 All bits read 0 and are not writable. 18.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12Q128 Rev 1.10 513 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) Module Base + 0x000F 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-20. RESERVED6 All bits read 0 and are not writable. 18.4 18.4.1 Functional Description Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase FCLK is derived from the oscillator clock via a programmable divider. The FCMD register as well as the associated FADDR and FDATA registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the necessary data and address can be stored to the buffer while the previous command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row, as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated, if enabled. The next sections describe: • How to write the FCLKDIV register • Command write sequence used to program, erase or erase verify the Flash array • Valid Flash commands • Errors resulting from illegal Flash operations 18.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, it is first necessary to write the FCLKDIV register to divide the oscillator clock down to within the 150-kHz to 200-kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), 514 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 18-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz. As a result, the Flash algorithm timings are increased over optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% Command execution time will increase proportionally with the period of FCLK. CAUTION Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash array with an input clock < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash array due to overstress. Setting FCLKDIV to a value such that (1/FCLK + Tbus) < 5µs can result in incomplete programming or erasure of the Flash array cells. If the FCLKDIV register is written, the bit FDIVLD is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. Freescale Semiconductor MC9S12Q128 Rev 1.10 515 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) START Tbus < 1µs? yes PRDIV8=0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock 12.8MHz? yes no PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK=oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? no yes END yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 18-21. PRDIV8 and FDIV Bits Determination Procedure 516 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data, and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash array memory. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. When the CBEIF flag is cleared in step 3, the CCIF flag is cleared by the Flash command controller indicating that the command was successfully launched. For all command write sequences, the CBEIF flag will set after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. A buffered command will wait for the active operation to be completed before being launched. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. Freescale Semiconductor MC9S12Q128 Rev 1.10 517 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.1.3 Valid Flash Commands Table 18-16 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 18-16. Valid Flash Commands FCMD 0x05 0x20 0x40 0x41 Meaning Erase Verify Program Sector Erase Mass Erase Function on Flash Array Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion. Program a word (2 bytes) in the Flash array. Erase all 1024 bytes in a sector of the Flash array. Erase all bytes in the Flash array. A mass erase of the full Flash array is only possible when FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 518 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 18-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the Flash array are verified to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. Freescale Semiconductor MC9S12Q128 Rev 1.10 519 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Array Address and Dummy Data Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes Erase Verify Status BLANK Set? no yes EXIT Flash Array Erased EXIT Flash Array Not Erased Figure 18-22. Example Erase Verify Command Flow 520 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 18-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. Freescale Semiconductor MC9S12Q128 Rev 1.10 521 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no Write: Flash Address and program Data yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. 2. Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 3. Bit Polling for Buffer Empty Check CBEIF Set? no yes Sequential Programming Decision Next Word? no Read: FSTAT register yes Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 18-23. Example Program Command Flow 522 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 1024 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 18-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while MCU address bits [9:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 523 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Sector Address and Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 18-24. Example Sector Erase Command Flow 524 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 18-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash array to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 525 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Block Address and Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 18-25. Example Mass Erase Command Flow 526 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.1.4 18.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3. Writing to the Flash address space while CBEIF is not set 4. Writing a second word to the Flash address space before executing a program or erase command on the previously written word 5. Writing to any Flash register other than FCMD after writing a word to the Flash address space 6. Writing a second command to the FCMD register before executing the previously written command 7. Writing an invalid command to the FCMD register 8. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register 9. The part enters stop mode and a program or erase command is in progress. The command is aborted and any pending command is killed 10. When security is enabled, a command other than mass erase originating from a non-secure memory or from the background debug mode is written to the FCMD register 11. A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during the command write sequence. If the Flash array is read during execution of an algorithm (CCIF=0), the Flash module will return invalid data and the ACCERR flag will not be set. If an ACCERR flag is set in the FSTAT register, the Flash command controller is locked. It is not possible to launch another command until the ACCERR flag is cleared. 18.4.1.4.2 Protection Violation The PVIOL flag in the FSTAT register will be set during the command write sequence after the word write to the Flash address space if any of the following illegal Flash operations are performed, causing the command write sequence to immediately abort: 1. Writing a Flash address to program in a protected area of the Flash array (see Section 18.3.2.5). 2. Writing a Flash address to erase in a protected area of the Flash array. 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL flag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL flag is cleared. Freescale Semiconductor MC9S12Q128 Rev 1.10 527 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.2 18.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 18.4.5). 18.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost. The high voltage circuitry to the Flash array will be switched off when entering stop mode. CCIF and ACCERR flags will be set. Upon exit from stop mode, the CBEIF flag will be set and any buffered command will not be executed. The ACCERR flag must be cleared before returning to normal operation. NOTE As active Flash commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program and erase execution. 18.4.2.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 18-16 can be executed. If the MCU is secured and is in special single chip mode, the only possible command to execute is mass erase. 18.4.3 Flash Module Security The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 18.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security/options byte at address 0xFF0F in the Flash configuration field must be changed directly by programming address 0xFF0F when the device is unsecured and the higher address sector is unprotected. If the Flash security/options byte is left in the secure state, any reset will cause the MCU to return to the secure operating mode. 18.4.3.1 Unsecuring the MCU using Backdoor Key Access The MCU may only be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor key (four 16-bit words programmed at addresses 0xFF00–0xFF07). If KEYEN[1:0] = 1:0 and the KEYACC bit is set, a write to a backdoor key address in the Flash array triggers a comparison between the written data and the backdoor key data stored in the Flash array. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor key stored in the Flash array, the MCU will be unsecured. The data must be written to the backdoor key 528 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If KEYEN[1:0] = 1:0 in the FSEC register, the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the FCNFG register 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0xFF00 3. Clear the KEYACC bit in the FCNFG register 4. If all four 16-bit words match the backdoor key stored in Flash addresses 0xFF00–0xFF07, the MCU is unsecured and bits SEC[1:0] in the FSEC register are forced to the unsecure state of 1:0 The backdoor key access sequence is monitored by the internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following illegal operations will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor key programmed in the Flash array 2. If the four 16-bit words are written in the wrong sequence 3. If more than four 16-bit words are written 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF 5. If the KEYACC bit does not remain set while the four 16-bit words are written After the backdoor key access sequence has been correctly matched, the MCU will be unsecured. The Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the four word backdoor key by programming bytes 0xFF00–0xFF07 of the Flash configuration field. The security as defined in the Flash security/options byte at address 0xFF0F is not changed by using the backdoor key access sequence to unsecure. The backdoor key stored in addresses 0xFF00–0xFF07 is unaffected by the backdoor key access sequence. After the next reset sequence, the security state of the Flash module is determined by the Flash security/options byte at address 0xFF0F. The backdoor key access sequence has no effect on the program and erase protection defined in the FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor MC9S12Q128 Rev 1.10 529 Chapter 18 64 Kbyte Flash Module (S12FTS64KV4) 18.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 18-1: • FPROT — Flash Protection Register (see Section 18.3.2.5) • FSEC — Flash Security Register (see Section 18.3.2.2) 18.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/array being erased is not guaranteed. 18.4.5 Interrupts The Flash module can generate an interrupt when all Flash commands have completed execution or the Flash address, data, and command buffers are empty. Table 18-17. Flash Interrupt Sources Interrupt Source Flash Address, Data, and Command Buffers are empty All Flash commands have completed execution Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE CCIE Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 18.4.5.1 Description of Interrupt Operation Figure 18-26 shows the logic used for generating interrupts. The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the generation of interrupts. CBEIF CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 18-26. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 18.3.2.4, “Flash Configuration Register (FCNFG)” and Section 18.3.2.6, “Flash Status Register (FSTAT)”. 530 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.1 Introduction The FTS96K module implements a 96 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 96 Kbytes organized as 768 rows of 128 bytes with an erase sector size of eight rows (1024 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words. The Flash array is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both mass erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase is generated internally. It is not possible to read from a Flash array while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 19.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to program, erase, or erase verify the Flash array memory. 19.1.2 • • • • • • • • Features 96 Kbytes of Flash memory comprised of one 96 Kbyte array divided into 96 sectors of 1024 bytes Automated program and erase algorithm Interrupts on Flash command completion and command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Flexible protection scheme to prevent accidental program or erase Single power supply for Flash program and erase operations Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12Q128 Rev 1.10 531 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.1.3 Modes of Operation See Section 19.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 19.4.1, “Flash Command Operations”. 19.1.4 Block Diagram Figure 19-1 shows a block diagram of the FTS96K module. FTS96K Flash Interface Command Pipeline Command Complete Interrupt Command Buffer Empty Interrupt Flash Array cmd2 addr2 data2 cmd1 addr1 data1 48K * 16 Bits sector 0 sector 1 Registers Protection sector 95 Security Oscillator Clock Clock Divider FCLK Figure 19-1. FTS96K Block Diagram 19.2 External Signal Description The FTS96K module contains no signals that connect off-chip. 532 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.3 Memory Map and Registers This section describes the FTS96K memory map and registers. 19.3.1 Module Memory Map The FTS96K memory map is shown in Figure 19-2. The HCS12 architecture places the Flash array addresses between 0x4000 and 0xFFFF, which corresponds to three 16 Kbyte pages. The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from address 0x8000 to 0xBFFF to any physical 16K byte page in the Flash array memory.1 The FPROT register (see Section 19.3.2.5) can be set to globally protect the entire Flash array. Three separate areas, one starting from the Flash array starting address (called lower) towards higher addresses, one growing downward from the Flash array end address (called higher), and the remaining addresses, can be activated for protection. The Flash array addresses covered by these protectable regions are shown in Figure 19-2. The higher address area is mainly targeted to hold the boot loader code since it covers the vector space. The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field described in Table 19-1. Table 19-1. Flash Configuration Field Flash Address 0xFF00–0xFF07 0xFF08–0xFF0C 0xFF0D 0xFF0E 0xFF0F Size (bytes) 8 5 1 1 1 Description Backdoor Key to unlock security Reserved Flash Protection byte Refer to Section 19.3.2.5, “Flash Protection Register (FPROT)” Reserved Flash Security/Options byte Refer to Section 19.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top fixed 16 Kbyte pages can be seen twice in the MCU memory map. Freescale Semiconductor MC9S12Q128 Rev 1.10 533 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) MODULE BASE + 0x0000 MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 0x5000 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes Flash Registers 16 bytes 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x3A 0x3B 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x3A–0x3F correspond to the PPAGE register content Figure 19-2. Flash Memory Map 534 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Table 19-2. Flash Array Memory Map Summary MCU Address Range 0x0000–0x3FFF(2) 0x4000–0x7FFF PPAGE Unpaged (0x3D) Unpaged (0x3E) Protectable Low Range N.A. 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x3A 0x3B 0x3C 0x3D 0x3E N.A. N.A. N.A. N.A. 0x8000–0x83FF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged (0x3F) N.A. 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. 0x1C000–0x1FFFF 0x1C000–0x1FFFF N.A. N.A. N.A. N.A. N.A. 0x08000–0x0BFFF 0x0C000–0x0FFFF 0x10000–0x13FFF 0x14000–0x17FFF 0x18000–0x1BFFF Protectable High Range N.A. N.A. Array Relative Address(1) 0x14000–0x17FFF 0x18000–0x1BFFF Freescale Semiconductor MC9S12Q128 Rev 1.10 535 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 19-3. Detailed descriptions of each register bit are provided. Register Name R W R 0x0001 FSEC W 0x0002 R RESERVED1 W 0x0000 FCLKDIV (1) Bit 7 FDIVLD KEYEN1 0 6 PRDIV8 KEYEN0 0 5 FDIV5 NV5 0 4 FDIV4 NV4 0 3 FDIV3 NV3 0 2 FDIV2 NV2 0 1 FDIV1 SEC1 0 Bit 0 FDIV0 SEC0 0 0x0003 FCNFG 0x0004 FPROT 0x0005 FSTAT 0x0006 FCMD 0x0007 RESERVED21 0x0008 FADDRHI1 0x0009 FADDRLO1 0x000A FDATAHI1 0x000B FDATALO1 0x000C RESERVED31 0x000D RESERVED41 0x000E RESERVED51 0x000F RESERVED61 R W R W R W R W R W R W R W R W R W R W R W R W R W CBEIE FPOPEN CBEIF 0 0 CCIE NV6 CCIF KEYACC FPHDIS PVIOL CMDB5 0 0 0 0 0 0 FPHS1 ACCERR 0 0 FPHS0 0 0 0 FPLDIS BLANK FPLS1 FAIL 0 0 FPLS0 DONE CMDB6 0 CMDB2 0 CMDB0 0 FABHI FABLO FDHI FDLO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-3. Flash Register Summary 1. Intended for factory test purposes only. 536 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset FDIVLD PRDIV8 0 0 FDIV5 0 FDIV4 0 FDIV3 0 FDIV2 0 FDIV1 0 FDIV0 0 = Unimplemented or Reserved Figure 19-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 19-3. FCLKDIV Field Descriptions Field 7 FDIVLD 6 PRDIV8 5–0 FDIV[5:0] Description Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash clock divider 1 The oscillator clock is divided by 8 before feeding into the Flash clock divider Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to Section 19.4.1.1, “Writing the FCLKDIV Register” for more information. 19.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 F F F F F F F F = Unimplemented or Reserved Figure 19-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence, indicated by F in Figure 19-5. Freescale Semiconductor MC9S12Q128 Rev 1.10 537 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Table 19-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 19-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 19-6. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 19-5. Flash KEYEN States KEYEN[1:0] 00 01 (1) Status of Backdoor Key Access DISABLED DISABLED ENABLED 10 11 DISABLED 1. Preferred KEYEN state to disable Backdoor Key Access. Table 19-6. Flash Security States SEC[1:0] 00 01(1) 10 Status of Security Secured Secured Unsecured 11 Secured 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 19.4.3, “Flash Module Security”. 19.3.2.3 RESERVED1 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-6. RESERVED1 All bits read 0 and are not writable. 538 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable. KEYACC is only writable if the KEYEN bit in the FSEC register is set to the enabled state (see Section 19.3.2.2). Table 19-7. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module. 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set (see Section 19.3.2.6) Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being completed in the Flash module. 0 Command Complete interrupts disabled 1 An interrupt will be requested whenever the CCIF flag is set (see Section 19.3.2.6) Enable Security Key Writing. 0 Flash writes are interpreted as the start of a command write sequence 1 Writes to the Flash array are interpreted as a backdoor key while reads of the Flash array return invalid data 6 CCIE 5 KEYACC 19.3.2.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase. Module Base + 0x0004 7 6 5 4 3 2 1 0 R FPOPEN W Reset F F F F F F F F NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 Figure 19-8. Flash Protection Register (FPROT) The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until Freescale Semiconductor MC9S12Q128 Rev 1.10 539 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 19-8. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to. A protected Flash sector is disabled by FPHDIS and FPLDIS while the size of the protected sector is defined by FPHS[1:0] and FPLS[1:0] in the FPROT register. Trying to alter any of the protected areas will result in a protect violation error and the PVIOL flag will be set in the FSTAT register (see Section 19.3.2.6). A mass erase of the whole Flash array is only possible when protection is fully disabled by setting the FPOPEN, FPLDIS, and FPHDIS bits. An attempt to mass erase a Flash array while protection is enabled will set the PVIOL flag in the FSTAT register. Table 19-8. FPROT Field Descriptions Field 7 FPOPEN Description Protection Function for Program or Erase — It is possible using the FPOPEN bit to either select address ranges to be protected using FPHDIS, FPLDIS, FPHS[1:0] and FPLS[1:0] or to select the same ranges to be unprotected. When FPOPEN is set, FPxDIS enables the ranges to be protected, whereby clearing FPxDIS enables protection for the range specified by the corresponding FPxS[1:0] bits. When FPOPEN is cleared, FPxDIS defines unprotected ranges as specified by the corresponding FPxS[1:0] bits. In this case, setting FPxDIS enables protection. Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 19-9. This function allows the main part of the Flash array to be protected while a small range can remain unprotected for EEPROM emulation. 0 The FPHDIS and FPLDIS bits define Flash address ranges to be unprotected 1 The FPHDIS and FPLDIS bits define Flash address ranges to be protected Nonvolatile Flag Bit — The NV6 bit should remain in the erased state for future enhancements. Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in the higher space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 19-10. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected sector in the lower space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 19-11. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. 6 NV6 5 FPHDIS 4–3 FPHS[1:0] 2 FPLDIS 1–0 FPLS[1:0] 540 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Table 19-9. Flash Protection Function FPOPEN 1 1 1 1 0 0 0 FPHDIS 1 1 0 0 1 0 1 FPHS[1] x x x x x x x FPHS[0] x x x x x x x FPLDIS 1 0 1 0 1 1 0 FPLS[1] x x x x x x x x FPLS[0] x x x x x x x x Function(1) No protection Protect low range Protect high range Protect high and low ranges Full Flash array protected Unprotected high range Unprotected low range Unprotected high and low ranges 0 0 x x 0 1. For range sizes refer to Table 19-10 and Table 19-11 or . Table 19-10. Flash Protection Higher Address Range FPHS[1:0] 00 01 10 11 Address Range 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF Range Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Table 19-11. Flash Protection Lower Address Range FPLS[1:0] 00 01 10 11 Address Range 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF Range Size 1 Kbyte 2 Kbytes 4 Kbytes 8 Kbytes Figure 19-9 illustrates all possible protection scenarios. Although the protection scheme is loaded from the Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. Freescale Semiconductor MC9S12Q128 Rev 1.10 541 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) FPHDIS = 1 FPLDIS = 1 Scenario 7 FPHDIS = 1 FPLDIS = 0 6 FPHDIS = 0 FPLDIS = 1 5 FPHDIS = 0 FPLDIS = 0 4 FPLS[1:0] 7 Freescale Semiconductor FPHS[1:0] FPLS[1:0] FPHS[1:0] 0xFFFF Scenario FPOPEN = 1 3 2 1 0 0xFFFF Protected Flash FPOPEN = 0 Figure 19-9. Flash Protection Scenarios 19.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed. All valid transitions between Flash protection scenarios are specified in Table 19-12. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. Table 19-12. Flash Protection Scenario Transitions From Protection Scenario 0 1 2 3 4 5 X To Protection Scenario(1) 0 X 1 X X X 2 X 3 X X X X X X X X X 4 5 6 542 MC9S12Q128 Rev 1.10 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Table 19-12. Flash Protection Scenario Transitions From Protection Scenario 6 To Protection Scenario(1) 0 1 X X 2 3 X X 4 X X X 5 6 X X X 7 7 X X 1. Allowed transitions marked with X. 19.3.2.6 Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution. Module Base + 0x0005 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL DONE 0 0 0 1 = Unimplemented or Reserved Figure 19-10. Flash Status Register (FSTAT) In normal modes, bits CBEIF, PVIOL, and ACCERR are readable and writable, bits CCIF and BLANK are readable and not writable, remaining bits, including FAIL and DONE, read 0 and are not writable. In special modes, FAIL is readable and writable while DONE is readable but not writable. FAIL must be clear in special modes when starting a command write sequence. Table 19-13. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 19-26). 0 Buffers are full 1 Buffers are ready to accept a new command Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 19-26). 0 Command in progress 1 All commands are completed 6 CCIF Freescale Semiconductor MC9S12Q128 Rev 1.10 543 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Table 19-13. FSTAT Field Descriptions Field 5 PVIOL Description Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command. 0 No protection violation detected 1 Protection violation has occurred Access Error — The ACCERR flag indicates an illegal access to the Flash array caused by either a violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in the FCMD register) or the execution of a CPU STOP instruction while a command is executing (CCIF=0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch another command. 0 No access error detected 1 Access error has occurred Flash Array Has Been Verified as Erased — The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased. The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 If an erase verify command has been requested, and the CCIF flag is set, then a 0 in BLANK indicates the array is not erased 1 Flash array verifies as erased Flag Indicating a Failed Flash Operation — In special modes, the FAIL flag will set if the erase verify operation fails (Flash array verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. While FAIL is set, it is not possible to launch another command. 0 Flash operation completed without error 1 Flash operation failed Flag Indicating a Failed Operation is not Active — In special modes, the DONE flag will clear if a program, erase, or erase verify operation is active. 0 Flash operation is active 1 Flash operation is not active 4 ACCERR 2 BLANK 1 FAIL 0 DONE 19.3.2.7 Flash Command Register (FCMD) The FCMD register defines the Flash commands. Module Base + 0x0006 7 6 5 4 3 2 1 0 R W Reset 0 CMDB6 0 0 CMDB5 0 0 0 CMDB2 0 CMDB0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. 544 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Table 19-14. FCMD Field Descriptions Field 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Description Valid Flash commands are shown in Table 19-15. An attempt to execute any command other than those listed in Table 19-15 will set the ACCERR bit in the FSTAT register (see Section 19.3.2.6). Table 19-15. Valid Flash Command List CMDB 0x05 0x20 0x40 0x41 NVM Command Erase verify Word program Sector erase Mass erase 19.3.2.8 RESERVED2 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-12. RESERVED2 All bits read 0 and are not writable. 19.3.2.9 \ Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 7 6 5 4 3 2 1 0 R FABHI W Reset 0 0 0 0 0 0 0 0 Figure 19-13. Flash Address High Register (FADDRHI) \ Freescale Semiconductor MC9S12Q128 Rev 1.10 545 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Module Base + 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 19-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [9:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 19.3.2.10 Flash Data Register (FDATA) FDATAHI and FDATALO are the Flash data registers. Module Base + 0x000A 7 6 5 4 3 2 1 0 R FDHI W Reset 0 0 0 0 0 0 0 0 Figure 19-15. Flash Data High Register (FDATAHI) Module Base + 0x000B 7 6 5 4 3 2 1 0 R FDLO W Reset 0 0 0 0 0 0 0 0 Figure 19-16. Flash Data Low Register (FDATALO) In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 19.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. 546 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Module Base + 0x000C 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-17. RESERVED3 All bits read 0 and are not writable. 19.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-18. RESERVED4 All bits read 0 and are not writable. 19.3.2.13 RESERVED5 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000E 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-19. RESERVED5 All bits read 0 and are not writable. 19.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12Q128 Rev 1.10 547 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) Module Base + 0x000F 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-20. RESERVED6 All bits read 0 and are not writable. 19.4 19.4.1 Functional Description Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase FCLK is derived from the oscillator clock via a programmable divider. The FCMD register as well as the associated FADDR and FDATA registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the necessary data and address can be stored to the buffer while the previous command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row, as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated, if enabled. The next sections describe: • How to write the FCLKDIV register • Command write sequence used to program, erase or erase verify the Flash array • Valid Flash commands • Errors resulting from illegal Flash operations 19.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, it is first necessary to write the FCLKDIV register to divide the oscillator clock down to within the 150-kHz to 200-kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), 548 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 19-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz. As a result, the Flash algorithm timings are increased over optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% Command execution time will increase proportionally with the period of FCLK. CAUTION Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash array with an input clock < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash array due to overstress. Setting FCLKDIV to a value such that (1/FCLK + Tbus) < 5µs can result in incomplete programming or erasure of the Flash array cells. If the FCLKDIV register is written, the bit FDIVLD is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. Freescale Semiconductor MC9S12Q128 Rev 1.10 549 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) START Tbus < 1µs? yes PRDIV8=0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock 12.8MHz? yes no PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK=oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? no yes END yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 19-21. PRDIV8 and FDIV Bits Determination Procedure 550 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data, and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash array memory. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. When the CBEIF flag is cleared in step 3, the CCIF flag is cleared by the Flash command controller indicating that the command was successfully launched. For all command write sequences, the CBEIF flag will set after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. A buffered command will wait for the active operation to be completed before being launched. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. Freescale Semiconductor MC9S12Q128 Rev 1.10 551 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.1.3 Valid Flash Commands Table 19-16 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 19-16. Valid Flash Commands FCMD 0x05 0x20 0x40 0x41 Meaning Erase Verify Program Sector Erase Mass Erase Function on Flash Array Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion. Program a word (2 bytes) in the Flash array. Erase all 1024 bytes in a sector of the Flash array. Erase all bytes in the Flash array. A mass erase of the full Flash array is only possible when FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 552 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 19-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the Flash array are verified to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. Freescale Semiconductor MC9S12Q128 Rev 1.10 553 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Array Address and Dummy Data Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes Erase Verify Status BLANK Set? no yes EXIT Flash Array Erased EXIT Flash Array Not Erased Figure 19-22. Example Erase Verify Command Flow 554 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 19-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. Freescale Semiconductor MC9S12Q128 Rev 1.10 555 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no Write: Flash Address and program Data yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. 2. Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 3. Bit Polling for Buffer Empty Check CBEIF Set? no yes Sequential Programming Decision Next Word? no Read: FSTAT register yes Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 19-23. Example Program Command Flow 556 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 1024 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 19-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while MCU address bits [9:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 557 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Sector Address and Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 19-24. Example Sector Erase Command Flow 558 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 19-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash array to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 559 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Block Address and Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 19-25. Example Mass Erase Command Flow 560 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.1.4 19.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3. Writing to the Flash address space while CBEIF is not set 4. Writing a second word to the Flash address space before executing a program or erase command on the previously written word 5. Writing to any Flash register other than FCMD after writing a word to the Flash address space 6. Writing a second command to the FCMD register before executing the previously written command 7. Writing an invalid command to the FCMD register 8. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register 9. The part enters stop mode and a program or erase command is in progress. The command is aborted and any pending command is killed 10. When security is enabled, a command other than mass erase originating from a non-secure memory or from the background debug mode is written to the FCMD register 11. A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during the command write sequence. If the Flash array is read during execution of an algorithm (CCIF=0), the Flash module will return invalid data and the ACCERR flag will not be set. If an ACCERR flag is set in the FSTAT register, the Flash command controller is locked. It is not possible to launch another command until the ACCERR flag is cleared. 19.4.1.4.2 Protection Violation The PVIOL flag in the FSTAT register will be set during the command write sequence after the word write to the Flash address space if any of the following illegal Flash operations are performed, causing the command write sequence to immediately abort: 1. Writing a Flash address to program in a protected area of the Flash array (see Section 19.3.2.5). 2. Writing a Flash address to erase in a protected area of the Flash array. 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL flag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL flag is cleared. Freescale Semiconductor MC9S12Q128 Rev 1.10 561 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.2 19.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 19.4.5). 19.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost. The high voltage circuitry to the Flash array will be switched off when entering stop mode. CCIF and ACCERR flags will be set. Upon exit from stop mode, the CBEIF flag will be set and any buffered command will not be executed. The ACCERR flag must be cleared before returning to normal operation. NOTE As active Flash commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program and erase execution. 19.4.2.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 19-16 can be executed. If the MCU is secured and is in special single chip mode, the only possible command to execute is mass erase. 19.4.3 Flash Module Security The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 19.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security/options byte at address 0xFF0F in the Flash configuration field must be changed directly by programming address 0xFF0F when the device is unsecured and the higher address sector is unprotected. If the Flash security/options byte is left in the secure state, any reset will cause the MCU to return to the secure operating mode. 19.4.3.1 Unsecuring the MCU using Backdoor Key Access The MCU may only be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor key (four 16-bit words programmed at addresses 0xFF00–0xFF07). If KEYEN[1:0] = 1:0 and the KEYACC bit is set, a write to a backdoor key address in the Flash array triggers a comparison between the written data and the backdoor key data stored in the Flash array. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor key stored in the Flash array, the MCU will be unsecured. The data must be written to the backdoor key 562 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If KEYEN[1:0] = 1:0 in the FSEC register, the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the FCNFG register 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0xFF00 3. Clear the KEYACC bit in the FCNFG register 4. If all four 16-bit words match the backdoor key stored in Flash addresses 0xFF00–0xFF07, the MCU is unsecured and bits SEC[1:0] in the FSEC register are forced to the unsecure state of 1:0 The backdoor key access sequence is monitored by the internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following illegal operations will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor key programmed in the Flash array 2. If the four 16-bit words are written in the wrong sequence 3. If more than four 16-bit words are written 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF 5. If the KEYACC bit does not remain set while the four 16-bit words are written After the backdoor key access sequence has been correctly matched, the MCU will be unsecured. The Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the four word backdoor key by programming bytes 0xFF00–0xFF07 of the Flash configuration field. The security as defined in the Flash security/options byte at address 0xFF0F is not changed by using the backdoor key access sequence to unsecure. The backdoor key stored in addresses 0xFF00–0xFF07 is unaffected by the backdoor key access sequence. After the next reset sequence, the security state of the Flash module is determined by the Flash security/options byte at address 0xFF0F. The backdoor key access sequence has no effect on the program and erase protection defined in the FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor MC9S12Q128 Rev 1.10 563 Chapter 19 96 Kbyte Flash Module (S12FTS96KV1) 19.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 19-1: • FPROT — Flash Protection Register (see Section 19.3.2.5) • FSEC — Flash Security Register (see Section 19.3.2.2) 19.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/array being erased is not guaranteed. 19.4.5 Interrupts The Flash module can generate an interrupt when all Flash commands have completed execution or the Flash address, data, and command buffers are empty. Table 19-17. Flash Interrupt Sources Interrupt Source Flash Address, Data, and Command Buffers are empty All Flash commands have completed execution Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE CCIE Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 19.4.5.1 Description of Interrupt Operation Figure 19-26 shows the logic used for generating interrupts. The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the generation of interrupts. CBEIF CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 19-26. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 19.3.2.4, “Flash Configuration Register (FCNFG)” and Section 19.3.2.6, “Flash Status Register (FSTAT)”. 564 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.1 Introduction The FTS128K1 module implements a 128 Kbyte Flash (nonvolatile) memory. The Flash memory contains one array of 128 Kbytes organized as 1024 rows of 128 bytes with an erase sector size of eight rows (1024 bytes). The Flash array may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words. The Flash array is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both mass erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase is generated internally. It is not possible to read from a Flash array while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 20.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to program, erase, or erase verify the Flash array memory. 20.1.2 • • • • • • • • Features 128 Kbytes of Flash memory comprised of one 128 Kbyte array divided into 128 sectors of 1024 bytes Automated program and erase algorithm Interrupts on Flash command completion and command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Flexible protection scheme to prevent accidental program or erase Single power supply for Flash program and erase operations Security feature to prevent unauthorized access to the Flash array memory Freescale Semiconductor MC9S12Q128 Rev 1.10 565 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.1.3 Modes of Operation See Section 20.4.2, “Operating Modes” for a description of the Flash module operating modes. For program and erase operations, refer to Section 20.4.1, “Flash Command Operations”. 20.1.4 Block Diagram Figure 20-1 shows a block diagram of the FTS128K1 module. FTS128K1 Flash Interface Command Pipeline Command Complete Interrupt Command Buffer Empty Interrupt Flash Array cmd2 addr2 data2 cmd1 addr1 data1 64K * 16 Bits sector 0 sector 1 Registers Protection sector 127 Security Oscillator Clock Clock Divider FCLK Figure 20-1. FTS128K1 Block Diagram 20.2 External Signal Description The FTS128K1 module contains no signals that connect off-chip. 566 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.3 Memory Map and Registers This section describes the FTS128K1 memory map and registers. 20.3.1 Module Memory Map The FTS128K1 memory map is shown in Figure 20-2. The HCS12 architecture places the Flash array addresses between 0x4000 and 0xFFFF, which corresponds to three 16 Kbyte pages. The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from address 0x8000 to 0xBFFF to any physical 16K byte page in the Flash array memory.1 The FPROT register (see Section 20.3.2.5) can be set to globally protect the entire Flash array. Three separate areas, one starting from the Flash array starting address (called lower) towards higher addresses, one growing downward from the Flash array end address (called higher), and the remaining addresses, can be activated for protection. The Flash array addresses covered by these protectable regions are shown in Figure 20-2. The higher address area is mainly targeted to hold the boot loader code since it covers the vector space. The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field described in Table 20-1. Table 20-1. Flash Configuration Field Flash Address 0xFF00–0xFF07 0xFF08–0xFF0C 0xFF0D 0xFF0E 0xFF0F Size (bytes) 8 5 1 1 1 Description Backdoor Key to unlock security Reserved Flash Protection byte Refer to Section 20.3.2.5, “Flash Protection Register (FPROT)” Reserved Flash Security/Options byte Refer to Section 20.3.2.2, “Flash Security Register (FSEC)” 1. By placing 0x3E/0x3F in the HCS12 Core PPAGE register, the bottom/top fixed 16 Kbyte pages can be seen twice in the MCU memory map. Freescale Semiconductor MC9S12Q128 Rev 1.10 567 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) MODULE BASE + 0x0000 MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 0x5000 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes Flash Registers 16 bytes 0x6000 0x3E Flash Array 0x8000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3C 0x3D 003E 0x3F 0xC000 0xE000 0x3F Flash Protected High Sectors 2, 4, 8, 16 Kbytes 0xF000 0xF800 FLASH_END = 0xFFFF 0xFF00–0xFF0F (Flash Configuration Field) Note: 0x38–0x3F correspond to the PPAGE register content Figure 20-2. Flash Memory Map 568 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Table 20-2. Flash Array Memory Map Summary MCU Address Range 0x0000–0x3FFF(2) 0x4000–0x7FFF PPAGE Unpaged (0x3D) Unpaged (0x3E) Protectable Low Range N.A. 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF 0x8000–0xBFFF 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E N.A. N.A. N.A. N.A. N.A. N.A. 0x8000–0x83FF 0x8000–0x87FF 0x8000–0x8FFF 0x8000–0x9FFF 0x3F N.A. 0xB800–0xBFFF 0xB000–0xBFFF 0xA000–0xBFFF 0x8000–0xBFFF 0xC000–0xFFFF Unpaged (0x3F) N.A. 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF 1. Inside Flash block. 2. If allowed by MCU. 0x1C000–0x1FFFF 0x1C000–0x1FFFF N.A. N.A. N.A. N.A. N.A. N.A. N.A. 0x00000–0x03FFF 0x04000–0x07FFF 0x08000–0x0BFFF 0x0C000–0x0FFFF 0x10000–0x13FFF 0x14000–0x17FFF 0x18000–0x1BFFF Protectable High Range N.A. N.A. Array Relative Address(1) 0x14000–0x17FFF 0x18000–0x1BFFF Freescale Semiconductor MC9S12Q128 Rev 1.10 569 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 20-3. Detailed descriptions of each register bit are provided. Register Name R W R 0x0001 FSEC W 0x0002 R RESERVED1 W 0x0000 FCLKDIV (1) Bit 7 FDIVLD KEYEN1 0 6 PRDIV8 KEYEN0 0 5 FDIV5 NV5 0 4 FDIV4 NV4 0 3 FDIV3 NV3 0 2 FDIV2 NV2 0 1 FDIV1 SEC1 0 Bit 0 FDIV0 SEC0 0 0x0003 FCNFG 0x0004 FPROT 0x0005 FSTAT 0x0006 FCMD 0x0007 RESERVED21 0x0008 FADDRHI1 0x0009 FADDRLO1 0x000A FDATAHI1 0x000B FDATALO1 0x000C RESERVED31 0x000D RESERVED41 0x000E RESERVED51 0x000F RESERVED61 R W R W R W R W R W R W R W R W R W R W R W R W R W CBEIE FPOPEN CBEIF 0 0 CCIE NV6 CCIF KEYACC FPHDIS PVIOL CMDB5 0 0 0 0 0 0 FPHS1 ACCERR 0 0 FPHS0 0 0 0 FPLDIS BLANK FPLS1 FAIL 0 0 FPLS0 DONE CMDB6 0 CMDB2 0 CMDB0 0 FABHI FABLO FDHI FDLO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-3. Flash Register Summary 1. Intended for factory test purposes only. 570 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Module Base + 0x0000 7 6 5 4 3 2 1 0 R W Reset FDIVLD PRDIV8 0 0 FDIV5 0 FDIV4 0 FDIV3 0 FDIV2 0 FDIV1 0 FDIV0 0 = Unimplemented or Reserved Figure 20-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 20-3. FCLKDIV Field Descriptions Field 7 FDIVLD 6 PRDIV8 5–0 FDIV[5:0] Description Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash clock divider 1 The oscillator clock is divided by 8 before feeding into the Flash clock divider Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to Section 20.4.1.1, “Writing the FCLKDIV Register” for more information. 20.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Module Base + 0x0001 7 6 5 4 3 2 1 0 R W Reset KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 F F F F F F F F = Unimplemented or Reserved Figure 20-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable. The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence, indicated by F in Figure 20-5. Freescale Semiconductor MC9S12Q128 Rev 1.10 571 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Table 20-4. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of the backdoor key access KEYEN[1:0] to the Flash module as shown in Table 20-5. 5–2 NV[5:2] 1–0 SEC[1:0] Nonvolatile Flag Bits — The NV[5:2] bits are available to the user as nonvolatile flags. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 20-6. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 20-5. Flash KEYEN States KEYEN[1:0] 00 01 (1) Status of Backdoor Key Access DISABLED DISABLED ENABLED 10 11 DISABLED 1. Preferred KEYEN state to disable Backdoor Key Access. Table 20-6. Flash Security States SEC[1:0] 00 01(1) 10 Status of Security Secured Secured Unsecured 11 Secured 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 20.4.3, “Flash Module Security”. 20.3.2.3 RESERVED1 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0002 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-6. RESERVED1 All bits read 0 and are not writable. 572 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor key writes. Module Base + 0x0003 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable. KEYACC is only writable if the KEYEN bit in the FSEC register is set to the enabled state (see Section 20.3.2.2). Table 20-7. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module. 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set (see Section 20.3.2.6) Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being completed in the Flash module. 0 Command Complete interrupts disabled 1 An interrupt will be requested whenever the CCIF flag is set (see Section 20.3.2.6) Enable Security Key Writing. 0 Flash writes are interpreted as the start of a command write sequence 1 Writes to the Flash array are interpreted as a backdoor key while reads of the Flash array return invalid data 6 CCIE 5 KEYACC 20.3.2.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase. Module Base + 0x0004 7 6 5 4 3 2 1 0 R FPOPEN W Reset F F F F F F F F NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 Figure 20-8. Flash Protection Register (FPROT) The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0. FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until Freescale Semiconductor MC9S12Q128 Rev 1.10 573 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence, indicated by F in Figure 20-8. To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to. A protected Flash sector is disabled by FPHDIS and FPLDIS while the size of the protected sector is defined by FPHS[1:0] and FPLS[1:0] in the FPROT register. Trying to alter any of the protected areas will result in a protect violation error and the PVIOL flag will be set in the FSTAT register (see Section 20.3.2.6). A mass erase of the whole Flash array is only possible when protection is fully disabled by setting the FPOPEN, FPLDIS, and FPHDIS bits. An attempt to mass erase a Flash array while protection is enabled will set the PVIOL flag in the FSTAT register. Table 20-8. FPROT Field Descriptions Field 7 FPOPEN Description Protection Function for Program or Erase — It is possible using the FPOPEN bit to either select address ranges to be protected using FPHDIS, FPLDIS, FPHS[1:0] and FPLS[1:0] or to select the same ranges to be unprotected. When FPOPEN is set, FPxDIS enables the ranges to be protected, whereby clearing FPxDIS enables protection for the range specified by the corresponding FPxS[1:0] bits. When FPOPEN is cleared, FPxDIS defines unprotected ranges as specified by the corresponding FPxS[1:0] bits. In this case, setting FPxDIS enables protection. Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 20-9. This function allows the main part of the Flash array to be protected while a small range can remain unprotected for EEPROM emulation. 0 The FPHDIS and FPLDIS bits define Flash address ranges to be unprotected 1 The FPHDIS and FPLDIS bits define Flash address ranges to be protected Nonvolatile Flag Bit — The NV6 bit should remain in the erased state for future enhancements. Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in the higher space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 20-10. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected sector in the lower space of the Flash address map. 0 Protection/unprotection enabled 1 Protection/unprotection disabled Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected sector as shown in Table 20-11. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. 6 NV6 5 FPHDIS 4–3 FPHS[1:0] 2 FPLDIS 1–0 FPLS[1:0] 574 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Table 20-9. Flash Protection Function FPOPEN 1 1 1 1 0 0 0 FPHDIS 1 1 0 0 1 0 1 FPHS[1] x x x x x x x FPHS[0] x x x x x x x FPLDIS 1 0 1 0 1 1 0 FPLS[1] x x x x x x x x FPLS[0] x x x x x x x x Function(1) No protection Protect low range Protect high range Protect high and low ranges Full Flash array protected Unprotected high range Unprotected low range Unprotected high and low ranges 0 0 x x 0 1. For range sizes refer to Table 20-10 and Table 20-11 or . Table 20-10. Flash Protection Higher Address Range FPHS[1:0] 00 01 10 11 Address Range 0xF800–0xFFFF 0xF000–0xFFFF 0xE000–0xFFFF 0xC000–0xFFFF Range Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Table 20-11. Flash Protection Lower Address Range FPLS[1:0] 00 01 10 11 Address Range 0x4000–0x43FF 0x4000–0x47FF 0x4000–0x4FFF 0x4000–0x5FFF Range Size 1 Kbyte 2 Kbytes 4 Kbytes 8 Kbytes Figure 20-9 illustrates all possible protection scenarios. Although the protection scheme is loaded from the Flash array after reset, it is allowed to change in normal modes. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if no re-programming is required. Freescale Semiconductor MC9S12Q128 Rev 1.10 575 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) FPHDIS = 1 FPLDIS = 1 Scenario 7 FPHDIS = 1 FPLDIS = 0 6 FPHDIS = 0 FPLDIS = 1 5 FPHDIS = 0 FPLDIS = 0 4 FPLS[1:0] 7 Freescale Semiconductor FPHS[1:0] FPLS[1:0] FPHS[1:0] 0xFFFF Scenario FPOPEN = 1 3 2 1 0 0xFFFF Protected Flash FPOPEN = 0 Figure 20-9. Flash Protection Scenarios 20.3.2.5.1 Flash Protection Restrictions The general guideline is that protection can only be added, not removed. All valid transitions between Flash protection scenarios are specified in Table 20-12. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. Table 20-12. Flash Protection Scenario Transitions From Protection Scenario 0 1 2 3 4 5 X To Protection Scenario(1) 0 X 1 X X X 2 X 3 X X X X X X X X X 4 5 6 576 MC9S12Q128 Rev 1.10 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Table 20-12. Flash Protection Scenario Transitions From Protection Scenario 6 To Protection Scenario(1) 0 1 X X 2 3 X X 4 X X X 5 6 X X X 7 7 X X 1. Allowed transitions marked with X. 20.3.2.6 Flash Status Register (FSTAT) The FSTAT register defines the status of the Flash command controller and the results of command execution. Module Base + 0x0005 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL DONE 0 0 0 1 = Unimplemented or Reserved Figure 20-10. Flash Status Register (FSTAT) In normal modes, bits CBEIF, PVIOL, and ACCERR are readable and writable, bits CCIF and BLANK are readable and not writable, remaining bits, including FAIL and DONE, read 0 and are not writable. In special modes, FAIL is readable and writable while DONE is readable but not writable. FAIL must be clear in special modes when starting a command write sequence. Table 20-13. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 20-26). 0 Buffers are full 1 Buffers are ready to accept a new command Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 20-26). 0 Command in progress 1 All commands are completed 6 CCIF Freescale Semiconductor MC9S12Q128 Rev 1.10 577 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Table 20-13. FSTAT Field Descriptions Field 5 PVIOL Description Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash array memory area. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command. 0 No protection violation detected 1 Protection violation has occurred Access Error — The ACCERR flag indicates an illegal access to the Flash array caused by either a violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in the FCMD register) or the execution of a CPU STOP instruction while a command is executing (CCIF=0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch another command. 0 No access error detected 1 Access error has occurred Flash Array Has Been Verified as Erased — The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased. The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 If an erase verify command has been requested, and the CCIF flag is set, then a 0 in BLANK indicates the array is not erased 1 Flash array verifies as erased Flag Indicating a Failed Flash Operation — In special modes, the FAIL flag will set if the erase verify operation fails (Flash array verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. While FAIL is set, it is not possible to launch another command. 0 Flash operation completed without error 1 Flash operation failed Flag Indicating a Failed Operation is not Active — In special modes, the DONE flag will clear if a program, erase, or erase verify operation is active. 0 Flash operation is active 1 Flash operation is not active 4 ACCERR 2 BLANK 1 FAIL 0 DONE 20.3.2.7 Flash Command Register (FCMD) The FCMD register defines the Flash commands. Module Base + 0x0006 7 6 5 4 3 2 1 0 R W Reset 0 CMDB6 0 0 CMDB5 0 0 0 CMDB2 0 CMDB0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-11. Flash Command Register (FCMD) Bits CMDB6, CMDB5, CMDB2, and CMDB0 are readable and writable during a command write sequence while bits 7, 4, 3, and 1 read 0 and are not writable. 578 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Table 20-14. FCMD Field Descriptions Field 6, 5, 2, 0 CMDB[6:5] CMDB[2] CMDB[0] Description Valid Flash commands are shown in Table 20-15. An attempt to execute any command other than those listed in Table 20-15 will set the ACCERR bit in the FSTAT register (see Section 20.3.2.6). Table 20-15. Valid Flash Command List CMDB 0x05 0x20 0x40 0x41 NVM Command Erase verify Word program Sector erase Mass erase 20.3.2.8 RESERVED2 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x0007 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-12. RESERVED2 All bits read 0 and are not writable. 20.3.2.9 \ Flash Address Register (FADDR) FADDRHI and FADDRLO are the Flash address registers. Module Base + 0x0008 7 6 5 4 3 2 1 0 R FABHI W Reset 0 0 0 0 0 0 0 0 Figure 20-13. Flash Address High Register (FADDRHI) \ \ Freescale Semiconductor MC9S12Q128 Rev 1.10 579 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Module Base + 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 20-14. Flash Address Low Register (FADDRLO) In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI and FABLO bits are readable and writable. For sector erase, the MCU address bits [9:0] are ignored. For mass erase, any address within the Flash array is valid to start the command. 20.3.2.10 Flash Data Register (FDATA) FDATAHI and FDATALO are the Flash data registers. Module Base + 0x000A 7 6 5 4 3 2 1 0 R FDHI W Reset 0 0 0 0 0 0 0 0 Figure 20-15. Flash Data High Register (FDATAHI) Module Base + 0x000B 7 6 5 4 3 2 1 0 R FDLO W Reset 0 0 0 0 0 0 0 0 Figure 20-16. Flash Data Low Register (FDATALO) In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range. 20.3.2.11 RESERVED3 This register is reserved for factory testing and is not accessible to the user. 580 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Module Base + 0x000C 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-17. RESERVED3 All bits read 0 and are not writable. 20.3.2.12 RESERVED4 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000D 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-18. RESERVED4 All bits read 0 and are not writable. 20.3.2.13 RESERVED5 This register is reserved for factory testing and is not accessible to the user. Module Base + 0x000E 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-19. RESERVED5 All bits read 0 and are not writable. 20.3.2.14 RESERVED6 This register is reserved for factory testing and is not accessible to the user. Freescale Semiconductor MC9S12Q128 Rev 1.10 581 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) Module Base + 0x000F 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-20. RESERVED6 All bits read 0 and are not writable. 20.4 20.4.1 Functional Description Flash Command Operations Write operations are used for the program, erase, and erase verify algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase FCLK is derived from the oscillator clock via a programmable divider. The FCMD register as well as the associated FADDR and FDATA registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the necessary data and address can be stored to the buffer while the previous command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row, as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated, if enabled. The next sections describe: • How to write the FCLKDIV register • Command write sequence used to program, erase or erase verify the Flash array • Valid Flash commands • Errors resulting from illegal Flash operations 20.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, it is first necessary to write the FCLKDIV register to divide the oscillator clock down to within the 150-kHz to 200-kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323) = 4), 582 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 20-21. For example, if the oscillator clock frequency is 950 kHz and the bus clock is 10 MHz, FCLKDIV bits FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190 kHz. As a result, the Flash algorithm timings are increased over optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% Command execution time will increase proportionally with the period of FCLK. CAUTION Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash array with an input clock < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash array due to overstress. Setting FCLKDIV to a value such that (1/FCLK + Tbus) < 5µs can result in incomplete programming or erasure of the Flash array cells. If the FCLKDIV register is written, the bit FDIVLD is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. Freescale Semiconductor MC9S12Q128 Rev 1.10 583 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) START Tbus < 1µs? yes PRDIV8=0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock 12.8MHz? yes no PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK=oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? no yes END yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 20-21. PRDIV8 and FDIV Bits Determination Procedure 584 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data, and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash array memory. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. When the CBEIF flag is cleared in step 3, the CCIF flag is cleared by the Flash command controller indicating that the command was successfully launched. For all command write sequences, the CBEIF flag will set after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. A buffered command will wait for the active operation to be completed before being launched. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. Freescale Semiconductor MC9S12Q128 Rev 1.10 585 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.1.3 Valid Flash Commands Table 20-16 summarizes the valid Flash commands along with the effects of the commands on the Flash array. Table 20-16. Valid Flash Commands FCMD 0x05 0x20 0x40 0x41 Meaning Erase Verify Program Sector Erase Mass Erase Function on Flash Array Verify all bytes in the Flash array are erased. If the Flash array is erased, the BLANK bit will set in the FSTAT register upon command completion. Program a word (2 bytes) in the Flash array. Erase all 1024 bytes in a sector of the Flash array. Erase all bytes in the Flash array. A mass erase of the full Flash array is only possible when FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register are set prior to launching the command. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 586 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.1.3.1 Erase Verify Command The erase verify operation will verify that a Flash array is erased. An example flow to execute the erase verify operation is shown in Figure 20-22. The erase verify command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the Flash array are verified to be erased. If any address in the Flash array is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. Freescale Semiconductor MC9S12Q128 Rev 1.10 587 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Array Address and Dummy Data Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes Erase Verify Status BLANK Set? no yes EXIT Flash Array Erased EXIT Flash Array Not Erased Figure 20-22. Example Erase Verify Command Flow 588 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.1.3.2 Program Command The program operation will program a previously erased word in the Flash array using an embedded algorithm. An example flow to execute the program operation is shown in Figure 20-23. The program command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the program command. The data written will be programmed to the Flash array address written. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. Freescale Semiconductor MC9S12Q128 Rev 1.10 589 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no Write: Flash Address and program Data yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. 2. Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 3. Bit Polling for Buffer Empty Check CBEIF Set? no yes Sequential Programming Decision Next Word? no Read: FSTAT register yes Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 20-23. Example Program Command Flow 590 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.1.3.3 Sector Erase Command The sector erase operation will erase all addresses in a 1024 byte sector of the Flash array using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 20-24. The sector erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while MCU address bits [9:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 591 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Sector Address and Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 20-24. Example Sector Erase Command Flow 592 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.1.3.4 Mass Erase Command The mass erase operation will erase all addresses in a Flash array using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 20-25. The mass erase command write sequence is as follows: 1. Write to a Flash array address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash array to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. Freescale Semiconductor MC9S12Q128 Rev 1.10 593 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Block Address and Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 20-25. Example Mass Erase Command Flow 594 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.1.4 20.4.1.4.1 Illegal Flash Operations Access Error The ACCERR flag in the FSTAT register will be set during the command write sequence if any of the following illegal Flash operations are performed causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing the FCLKDIV register 2. Writing a misaligned word or a byte to the valid Flash address space 3. Writing to the Flash address space while CBEIF is not set 4. Writing a second word to the Flash address space before executing a program or erase command on the previously written word 5. Writing to any Flash register other than FCMD after writing a word to the Flash address space 6. Writing a second command to the FCMD register before executing the previously written command 7. Writing an invalid command to the FCMD register 8. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register 9. The part enters stop mode and a program or erase command is in progress. The command is aborted and any pending command is killed 10. When security is enabled, a command other than mass erase originating from a non-secure memory or from the background debug mode is written to the FCMD register 11. A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during the command write sequence. If the Flash array is read during execution of an algorithm (CCIF=0), the Flash module will return invalid data and the ACCERR flag will not be set. If an ACCERR flag is set in the FSTAT register, the Flash command controller is locked. It is not possible to launch another command until the ACCERR flag is cleared. 20.4.1.4.2 Protection Violation The PVIOL flag in the FSTAT register will be set during the command write sequence after the word write to the Flash address space if any of the following illegal Flash operations are performed, causing the command write sequence to immediately abort: 1. Writing a Flash address to program in a protected area of the Flash array (see Section 20.3.2.5). 2. Writing a Flash address to erase in a protected area of the Flash array. 3. Writing the mass erase command to the FCMD register while any protection is enabled. If the PVIOL flag is set, the Flash command controller is locked. It is not possible to launch another command until the PVIOL flag is cleared. Freescale Semiconductor MC9S12Q128 Rev 1.10 595 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.2 20.4.2.1 Operating Modes Wait Mode If the MCU enters wait mode while a Flash command is active (CCIF = 0), that command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the interrupts are enabled (see Section 20.4.5). 20.4.2.2 Stop Mode If the MCU enters stop mode while a Flash command is active (CCIF = 0), that command will be aborted and the data being programmed or erased is lost. The high voltage circuitry to the Flash array will be switched off when entering stop mode. CCIF and ACCERR flags will be set. Upon exit from stop mode, the CBEIF flag will be set and any buffered command will not be executed. The ACCERR flag must be cleared before returning to normal operation. NOTE As active Flash commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program and erase execution. 20.4.2.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 20-16 can be executed. If the MCU is secured and is in special single chip mode, the only possible command to execute is mass erase. 20.4.3 Flash Module Security The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 20.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security/options byte at address 0xFF0F in the Flash configuration field must be changed directly by programming address 0xFF0F when the device is unsecured and the higher address sector is unprotected. If the Flash security/options byte is left in the secure state, any reset will cause the MCU to return to the secure operating mode. 20.4.3.1 Unsecuring the MCU using Backdoor Key Access The MCU may only be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor key (four 16-bit words programmed at addresses 0xFF00–0xFF07). If KEYEN[1:0] = 1:0 and the KEYACC bit is set, a write to a backdoor key address in the Flash array triggers a comparison between the written data and the backdoor key data stored in the Flash array. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor key stored in the Flash array, the MCU will be unsecured. The data must be written to the backdoor key 596 MC9S12Q128 Rev 1.10 Freescale Semiconductor Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) addresses sequentially staring with 0xFF00-0xFF01 and ending with 0xFF06–0xFF07. The values 0x0000 and 0xFFFF are not permitted as keys. When the KEYACC bit is set, reads of the Flash array will return invalid data. The user code stored in the Flash array must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If KEYEN[1:0] = 1:0 in the FSEC register, the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the FCNFG register 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0xFF00 3. Clear the KEYACC bit in the FCNFG register 4. If all four 16-bit words match the backdoor key stored in Flash addresses 0xFF00–0xFF07, the MCU is unsecured and bits SEC[1:0] in the FSEC register are forced to the unsecure state of 1:0 The backdoor key access sequence is monitored by the internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following illegal operations will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor key programmed in the Flash array 2. If the four 16-bit words are written in the wrong sequence 3. If more than four 16-bit words are written 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF 5. If the KEYACC bit does not remain set while the four 16-bit words are written After the backdoor key access sequence has been correctly matched, the MCU will be unsecured. The Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the four word backdoor key by programming bytes 0xFF00–0xFF07 of the Flash configuration field. The security as defined in the Flash security/options byte at address 0xFF0F is not changed by using the backdoor key access sequence to unsecure. The backdoor key stored in addresses 0xFF00–0xFF07 is unaffected by the backdoor key access sequence. After the next reset sequence, the security state of the Flash module is determined by the Flash security/options byte at address 0xFF0F. The backdoor key access sequence has no effect on the program and erase protection defined in the FPROT register. It is not possible to unsecure the MCU in special single chip mode by executing the backdoor key access sequence in background debug mode. Freescale Semiconductor MC9S12Q128 Rev 1.10 597 Chapter 20 128 Kbyte Flash Module (S12FTS128K1V1) 20.4.4 Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash array memory according to Table 20-1: • FPROT — Flash Protection Register (see Section 20.3.2.5) • FSEC — Flash Security Register (see Section 20.3.2.2) 20.4.4.1 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/array being erased is not guaranteed. 20.4.5 Interrupts The Flash module can generate an interrupt when all Flash commands have completed execution or the Flash address, data, and command buffers are empty. Table 20-17. Flash Interrupt Sources Interrupt Source Flash Address, Data, and Command Buffers are empty All Flash commands have completed execution Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE CCIE Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 20.4.5.1 Description of Interrupt Operation Figure 20-26 shows the logic used for generating interrupts. The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the generation of interrupts. CBEIF CBEIE FLASH INTERRUPT REQUEST CCIF CCIE Figure 20-26. Flash Interrupt Implementation For a detailed description of these register bits, refer to Section 20.3.2.4, “Flash Configuration Register (FCNFG)” and Section 20.3.2.6, “Flash Status Register (FSTAT)”. 598 MC9S12Q128 Rev 1.10 Freescale Semiconductor Appendix A Electrical Characteristics Appendix A Electrical Characteristics A.1 General NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. The parts are specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the parts are not tested in production test in the intermediate range. This supplement contains the most accurate electrical information for the MC9S12Q128 microcontrollers available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE This classification will be added at a later release of the specification P: C: T: D: Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. They are regularly verified by production monitors. Those parameters are achieved by design characterization on a small sample size from typical devices. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. A.1.2 Power Supply The MC9S12Q128 members utilize several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the internal logic. The VDDA, VSSA pair supplies the A/D converter. The VDDX, VSSX pair supplies the I/O pins The VDDR, VSSR pair supplies the internal voltage regulator. Freescale Semiconductor MC9S12Q128 Rev 1.10 599 Appendix A Electrical Characteristics VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic. VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE In the following context VDD5 is used for either VDDA, VDDR, and VDDX; VSS5 is used for either VSSA, VSSR, and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX, and VDDR pins. VDD is used for VDD1, VDD2, and VDDPLL, VSS is used for VSS1, VSS2, and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2. A.1.3 Pins There are four groups of functional pins. A.1.3.1 5V I/O Pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD pin, and the RESET inputs.The internal structure of all those pins is identical; however some of the functionality may be disabled. For example, pull-up and pull-down resistors may be disabled permanently. A.1.3.2 Analog Reference This class is made up by the two VRH and VRL pins. In 48- and 52-pin package versions the VRL pad is bonded to the VSSA pin. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.4 Current Injection Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the 600 MC9S12Q128 Rev 1.10 Freescale Semiconductor Appendix A Electrical Characteristics injection current may flow out of VDD5 and could result in external power supply going out of regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1. Absolute Maximum Ratings Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Rating I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage PLL Supply Voltage 1 (1) Symbol VDD5 VDD VDDPLL ∆VDDX ∆VSSX VIN VRH, VRL VILV VTEST ID IDL I DT Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –25 –25 –0.25 – 40 – 40 Max 6.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 10.0 +25 +25 0 125 140 Unit V V V V V V V V V mA mA mA °C °C Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins (2) Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL(3) Instantaneous Maximum Current Single pin limit for TEST(4) Operating Temperature Range (packaged) Operating Temperature Range (junction) TA TJ – 65 155 °C 15 Storage Temperature Range Tstg 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 3. These pins are internally clamped to VSSPLL and VDDPLL 4. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications. Freescale Semiconductor MC9S12Q128 Rev 1.10 601 Appendix A Electrical Characteristics A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2. ESD and Latch-up Test Conditions Model Human Body Series Resistance Storage Capacitance Number of Pulse per pin Positive Negative Machine Series Resistance Storage Capacitance Number of Pulse per pin Positive Negative Latch-up Minimum input voltage limit Maximum input voltage limit — — — — 3 3 –2.5 7.5 V V — — R1 C 3 3 0 200 Ohm pF Description Symbol R1 C Value 1500 100 Unit Ohm pF Table A-3. ESD and Latch-Up Protection Characteristics Num 1 2 3 4 C C C C C Latch-up Current at 27°C 5 C Positive Negative ILAT +200 –200 — — mA Rating Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current at 125°C Positive Negative ILAT +100 –100 — — mA Symbol VHBM VMM VCDM Min 2000 200 500 Max — — — Unit V V V 602 MC9S12Q128 Rev 1.10 Freescale Semiconductor Appendix A Electrical Characteristics A.1.7 Operating Conditions This chapter describes the operating conditions of the devices. Unless otherwise noted those conditions apply to all the following data. NOTE Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” . Table A-4. Operating Conditions Rating Symbol VDD5 VDD VDDPLL ∆VDDX ∆VSSX fbus(2) Min 2.97 2.35 2.35 –0.1 –0.1 0.25 Typ 5 2.5 2.5 0 0 — Max 5.5 2.75 2.75 0.1 0.1 16 Unit V V V V V MHz I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage (1) PLL Supply Voltage 1 Voltage Difference VDDX to VDDA Voltage Difference VSSX to VSSR and VSSA Bus Frequency –40 — 140 °C Operating Junction Temperature Range TJ 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The operating conditions apply when this regulator is disabled and the device is powered from an external source. Using an external regulator, with the internal voltage regulator disabled, an external LVR must be provided. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. Freescale Semiconductor MC9S12Q128 Rev 1.10 603 Appendix A Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from: T T T J J A D = T + (P • Θ ) A D JA = Junction Temperature, [ ° C ] = Ambient Temperature, [ ° C ] = Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ ° C/W] P Θ JA The total power dissipation can be calculated from: P P D =P INT +P IO INT = Chip Internal Power Dissipation, [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = =I DD ⋅V DD +I DDPLL ⋅V DDPLL +I DDA ⋅V DDA P IO ∑ RDSON ⋅ IIOi2 i Which is the sum of all output currents on I/O ports associated with VDDX and VDDM. For RDSON is valid: R V OL = ----------- ;for outputs driven low DSON I OL respectively R V –V DD5 OH = ----------------------------------- ;for outputs driven high DSON I OH 2. Internal voltage regulator enabled P INT =I DDR ⋅V DDR +I DDA ⋅V DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. P IO = ∑ RDSON ⋅ IIOi2 i MC9S12Q128 Rev 1.10 Freescale Semiconductor Which is the sum of all output currents on I/O ports associated with VDDX and VDDR. 604 Appendix A Electrical Characteristics Table A-5. Thermal Package Characteristics(1) Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C T T T T T T T T T T T T T T Rating Thermal Resistance LQFP48, single layer PCB(2) Thermal Resistance LQFP48, double sided PCB with 2 internal planes(3) Junction to Board LQFP48 Junction to Case LQFP48 Junction to Package Top LQFP48 Thermal Resistance LQFP52, single sided PCB Thermal Resistance LQFP52, double sided PCB with 2 internal planes Junction to Board LQFP52 Junction to Case LQFP52 Junction to Package Top LQFP52 Thermal Resistance QFP 80, single sided PCB Thermal Resistance QFP 80, double sided PCB with 2 internal planes Junction to Board QFP80 Junction to Case QFP80 Symbol θJA θJA θJB θJC ΨJT θJA θJA θJB θJC ΨJT θJA θJA θJB θJC ΨJT Min — — — — — — — — — — — — — — — Typ — — — — — — — — — — — — — — — Max 69 53 30 20 4 65 49 31 17 3 52 42 28 18 4 Unit o o o o o o o C/W C/W C/W C/W C/W C/W C/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W 15 T Junction to Package Top QFP80 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7 Freescale Semiconductor MC9S12Q128 Rev 1.10 605 Appendix A Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Table A-6. 5V I/O Characteristics Conditions are 4.5< VDDX