MC9S12T64

Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com MC9S12T64 Specification Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family February 28th, 2003 – Revision 1.1.1 DOCUMENT NUMBER 9S12T64AF16V1/D Freescale Semiconductor, Inc. Revision History Revision History Rev. 1.0 1.1 - Initial Release. - Added document number information. - Modified a diagram of FBDM data transfer in SPI mode in FBDM section (page 543). - Corrected order number in ordering information (page 24). Contents Date Jan-28-2003 Feb-13-2003 Who 1.1.1 Feb-28-2003 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Sections MC9S12T64Revision 1.1.1 List of Sections For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . 25 Pinout and Signal Description . . . . . . . . . . . . . . . . . . . . 59 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Module Mapping Control (MMC) . . . . . . . . . . . . . . . . 121 Multiplexed External Bus Interface (MEBI) . . . . . . . . . 141 Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Voltage Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . 181 Low-Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 185 Flash EEPROM 64K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 CALRAM 2K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Port Integration Module (PIM) . . . . . . . . . . . . . . . . . . . 249 Clocks and Reset Generator (CRG) . . . . . . . . . . . . . . 271 Pulse Width Modulator (PWM8B8C) . . . . . . . . . . . . . . . 327 Enhanced Capture Timer (ECT) . . . . . . . . . . . . . . . . . . 371 Serial Communications Interface (SCI). . . . . . . . . . . . 419 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . 457 Analog to Digital Converter (ATD) . . . . . . . . . . . . . . . . 487 Fast Background Debug Module (FBDM) . . . . . . . . . . 517 Breakpoint (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 561 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... List of Sections MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. List of Sections For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Table of Contents List of Sections Table of Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... List of Figures List of Tables General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MC9S12T64 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MC9S12T64 Pin Assignments in 80-pin LQFP . . . . . . . . . . . . . . . . . 59 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Modules Variabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 MCU Variabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 MC9S12T64Revision 1.1.1 Table of Contents For More Information On This Product, Go to: www.freescale.com Central Processing Unit (CPU) Pinout and Signal Description System Configuration Registers Operating Modes Freescale Semiconductor, Inc. Table of Contents Secured Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Module Mapping Control (MMC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 121 122 123 125 133 138 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Multiplexed External Bus Interface (MEBI) 141 141 141 142 145 146 161 167 169 169 170 171 171 172 175 177 178 181 181 181 181 183 184 184 185 185 185 186 186 187 188 189 191 192 Resets and Interrupts Voltage Regulator (VREG) Low-Voltage Detector (LVD) MC9S12T64Revision 1.1.1 Table of Contents For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Flash EEPROM 64K CALRAM 2K Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 Modes of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 MC9S12T64Revision 1.1.1 Table of Contents For More Information On This Product, Go to: www.freescale.com Port Integration Module (PIM) Clocks and Reset Generator (CRG) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 Flash Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Freescale Semiconductor, Inc. Table of Contents Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Pulse Width Modulator (PWM8B8C) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 327 328 328 330 331 332 334 353 368 368 369 371 371 372 372 372 373 374 375 378 408 416 419 419 419 420 421 422 423 424 434 454 457 457 458 458 459 460 461 462 Enhanced Capture Timer (ECT) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) MC9S12T64Revision 1.1.1 Table of Contents For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Table of Contents Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484 Analog to Digital Converter (ATD) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .488 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .490 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .491 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .517 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .517 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .517 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .520 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .548 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .552 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .552 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .553 Breakpoint Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .560 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .560 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .560 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569 Flash EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .573 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .577 Reset, Oscillator and PLL Characteristics . . . . . . . . . . . . . . . . . . . .578 MC9S12T64Revision 1.1.1 Table of Contents For More Information On This Product, Go to: www.freescale.com Fast Background Debug Module (FBDM) Breakpoint (BKP) Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Table of Contents SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Glossary Literature Updates Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola SPS World Marketing World Wide Web Server . . . . . . . . Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . . 605 606 606 606 606 MC9S12T64Revision 1.1.1 Table of Contents For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Figures MC9S12T64Revision 1.1.1 List of Figures For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 MC9S12T64 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Accumulator B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Index Register X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Index Register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin Assignments in 80-pin LQFP for MC9S12T64 . . . . . . . . . . . . . . . . . 60 80-pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Module Mapping Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 122 Module Mapping Control Register Summary . . . . . . . . . . . . . . . . . . . . 123 MC9S12T64 Memory map after reset . . . . . . . . . . . . . . . . . . . . . . . . . . 139 MEBI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Queue Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Resets and Interrupts Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 VREG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 LVD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Flash 64K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Flash Data Memory Map in Normal Modes . . . . . . . . . . . . . . . . . . . . . . 199 Flash Data Memory Map in Special Modes. . . . . . . . . . . . . . . . . . . . . . 201 Flash Control Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 FADDR Address Mapping to Flash Relative Address . . . . . . . . . . . . . . 218 PRDIV8 and FDIV bits Determination Procedure . . . . . . . . . . . . . . . . . 222 Example Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Example Program Algorithm in Flash Super User Mode. . . . . . . . . . . . 227 Flash Interrupt Implementation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 CALRAM 2K Byte Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 CALRAM Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Copy Data from Flash EEPROM to CALRAM . . . . . . . . . . . . . . . . . . . . 244 Map CALRAM over Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 An Example Memory Map When Erase/Program Flash EEPROM . . . . 246 Remove CALRAM from memory mapping . . . . . . . . . . . . . . . . . . . . . . 247 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Figures Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 PIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 PIM9T64 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Illustration of I/O pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Block diagram of CRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Colpitts Crystal Connections (XCLKS=1). . . . . . . . . . . . . . . . . . . . . . . . 277 Pierce Oscillator Connections (XCLKS=0). . . . . . . . . . . . . . . . . . . . . . . 277 External Clock Connections (XCLKS=0) . . . . . . . . . . . . . . . . . . . . . . . . 278 CRG Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 PLL Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Core Clock and Bus Clock relationship . . . . . . . . . . . . . . . . . . . . . . . . . 300 Check Window definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Sequence for Clock Quality Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Clock Chain for COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Clock Chain for RTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Wait Mode Entry/Exit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Stop Mode Entry/Exit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 RESET pin tied to VDD (by a pull-up resistor) . . . . . . . . . . . . . . . . . . . . 322 RESET pin held low externally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 PWM8B8C Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 PWM Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 PWM Clock Select Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 PWM Timer Channel Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 357 PWM Left Aligned Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 361 PWM Left Aligned Output Example Waveform . . . . . . . . . . . . . . . . . . . 362 PWM Center Aligned Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . 363 PWM Center Aligned Output Example Waveform. . . . . . . . . . . . . . . . . 364 PWM 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Enhanced Capture Timer Register Map. . . . . . . . . . . . . . . . . . . . . . . . . 375 Timer Block Diagram in Latch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Timer Block Diagram in Queue Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 410 8-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 411 16-Bit Pulse Accumulators Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 412 Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 SCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 SCI Register Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Detailed SCI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Transmitter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 MC9S12T64Revision 1.1.1 List of Figures For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Figures MC9S12T64Revision 1.1.1 List of Figures For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Figure 103 Figure 104 Figure 105 Figure 106 Figure 107 Figure 108 Figure 109 Figure 110 Figure 111 Figure 112 Figure 113 Figure 114 Figure 115 Figure 116 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Bit Search Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Bit Search Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Bit Search Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Bit Search Example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Bit Search Example 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Bit Search Example 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . . . . . . . . . . . . Loop Operation (LOOPS = 1, RSRC = 0) . . . . . . . . . . . . . . . . . . . . . . . SPI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master/Slave Transfer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Clock Format 0 (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Clock Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Clock Divisor Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATD Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATD Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram of BDM in Single Wire Mode . . . . . . . . . . . . . . . . . . . . . Block Diagram of BDM in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . BDM Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BDM Command Structure - Single Wire Mode . . . . . . . . . . . . . . . . . . . BDM Command Structure - SPI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . BDM Host-to-Target Serial Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . BDM Target-to-Host Serial Bit Timing (Logic 1) . . . . . . . . . . . . . . . . . . BDM Target-to-Host Serial Bit Timing (Logic 0) . . . . . . . . . . . . . . . . . . 8-Bit Data Transfer in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Master Timing (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Slave Timing (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Slave Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 446 446 447 447 448 448 449 450 453 453 459 461 474 477 479 480 490 492 520 520 523 537 538 541 542 543 543 551 552 572 581 583 583 585 585 588 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... List of Figures MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. List of Figures For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. List of Tables MC9S12T64Revision 1.1.1 List of Tables For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 MC9S12T64 Device Ordering Information .......................................................... 24 MC9S12T64 Development Tools Ordering Information ...................................... 24 Addressing Mode Summary ................................................................................ 35 Instruction Set Summary ..................................................................................... 36 Register and Memory Notation............................................................................ 51 Source Form Notation ......................................................................................... 53 Operation Notation .............................................................................................. 54 Address Mode Notation ....................................................................................... 54 Machine Code Notation ....................................................................................... 55 Access Detail Notation ........................................................................................ 55 Condition Code State Notation ............................................................................ 58 MC9S12T64 Power and Ground Connection Summary ..................................... 64 MC9S12T64 Signal Description Summary .......................................................... 70 MC9S12T64 Port A, B, E, K, T, S, P Description Summary................................ 77 Port A, B, E, K, AD Pull-Up, Pull-Down and Reduced Drive Summary ............... 78 MMC Module Variable I/O Signals ...................................................................... 79 Assigned Part ID Numbers .................................................................................. 80 Module Availability in WAIT and RUN Modes .................................................... 83 MC9S12T64 Register Map .................................................................................. 86 Mode Selection.................................................................................................. 106 MODC, MODB, MODA Write Capability............................................................ 115 : Security Bits .................................................................................................... 118 EXSTR Stretch Bit Definition ............................................................................. 128 State of ROMON bit after reset ......................................................................... 129 Program space page index in special modes.................................................... 133 Mapping Precedence ........................................................................................ 134 Access Type in Expanded Modes ..................................................................... 135 64K Byte Physical Flash/ROM Allocated .......................................................... 135 External System Pins Associated With MEBI.................................................... 142 Access Type vs. Bus Control Pins .................................................................... 162 IPIPE[1:0] Decoding when E Clock is High ....................................................... 165 IPIPE[1:0] Decoding when E Clock is Low ........................................................ 165 Interrupt Vector Table........................................................................................ 172 LVDF Flag Indication ......................................................................................... 190 Flash Memory Mapping in Normal Modes......................................................... 198 Flash Memory Mapping in Special Modes ........................................................ 200 Flash Protection/Security Field.......................................................................... 202 Memory Map Summary In Normal Modes......................................................... 203 Example FCLKDIV settings ............................................................................... 207 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Tables Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Security States .................................................................................................. 208 Register Bank Selects ....................................................................................... 210 Loading of the Protection Register from Flash .................................................. 211 Higher Address Range Protection..................................................................... 212 Lower Address Range Protection ..................................................................... 213 Valid User Mode Commands ............................................................................ 216 Flash Interrupt Sources ..................................................................................... 232 Example CALRAM Mapping ............................................................................. 242 Port Reset State and Priority Summary ............................................................ 252 Pin Configuration Summary .............................................................................. 255 Clock Selection Based on XCLKS at reset ....................................................... 278 RTI Frequency Divide Rates ............................................................................. 289 COP Watchdog Rates ....................................................................................... 292 MCU configuration during Wait Mode ............................................................... 306 Outcome of Clock Loss in Wait Mode ............................................................... 309 Outcome of Clock Loss in Pseudo-Stop Mode ................................................. 314 Reset Summary ................................................................................................ 318 Reset Vector Selection...................................................................................... 319 Relation between PORLVDRF and LVDF......................................................... 323 CRG Interrupt Vectors....................................................................................... 324 Clock B Prescaler Selects ................................................................................. 341 Clock A Prescaler Selects ................................................................................. 341 PWM Timer Counter Conditions........................................................................ 360 16-bit Concatenation Mode Summary............................................................... 366 PWM Boundary Cases ...................................................................................... 367 Compare Result Output Action ......................................................................... 385 Edge Detector Circuit Configuration.................................................................. 386 Prescaler Selection ........................................................................................... 388 Pin Action .......................................................................................................... 392 Clock Selection ................................................................................................. 392 Modulus Counter Prescaler Select.................................................................... 397 Delay Counter Select ........................................................................................ 400 ECT Interrupts ................................................................................................... 416 Loop Functions.................................................................................................. 426 Example of 8-bit Data Formats ......................................................................... 436 Example of 9-Bit Data Formats ......................................................................... 436 Baud Rates (Example: Bus Clock = 16.0 MHz) ................................................ 437 Start Bit Verification.......................................................................................... 444 Data Bit Recovery ............................................................................................. 445 Stop Bit Recovery ............................................................................................. 445 SCI Interrupt Sources........................................................................................ 454 SS Input / Output Selection ............................................................................... 463 Bidirectional Pin Configurations ........................................................................ 465 SPI Baud Rate Selection (16 MHz Bus Clock).................................................. 466 Normal Mode and Bidirectional Mode ............................................................... 481 SPI Interrupt Signals ......................................................................................... 485 External Trigger Configurations ....................................................................... 495 MC9S12T64Revision 1.1.1 List of Tables For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Tables MC9S12T64Revision 1.1.1 List of Tables For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115 Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Conversion Sequence Length Coding. ..............................................................496 ATD Behavior in Freeze Mode (Breakpoint)......................................................498 Sample Time Select...........................................................................................499 Clock Prescaler Values......................................................................................501 Result Data Formats Available. .........................................................................503 Left Justified, Signed and Unsigned ATD Output Codes...................................503 Analog Input Channel Select Coding.................................................................504 Special Channel Select Coding .........................................................................507 External Trigger Control Bits..............................................................................513 ATD module Interrupt Vectors ...........................................................................515 Target Clock Selection Summary ......................................................................526 Hardware Commands........................................................................................532 Firmware Commands ........................................................................................534 SPI Mode Timing ...............................................................................................544 Tag Pin Function................................................................................................545 Breakpoint Mask Bits for First Address.............................................................554 Breakpoint Mask Bits for Second Address (Dual Address Mode) ....................555 Breakpoint Mask Bits for Data Breakpoints (Full Breakpoint Mode).................556 Absolute Maximum Ratings ...............................................................................564 Operating Conditions .........................................................................................565 Thermal Package Characteristics......................................................................567 5V I/O Characteristics........................................................................................567 Supply Current Characteristics ..........................................................................568 ATD Operating Characteristics ..........................................................................569 ATD Electrical Characteristics ...........................................................................570 ATD Conversion Performance..........................................................................571 NVM Timing Characteristics .............................................................................575 NVM Reliability Characteristics.........................................................................576 Voltage Regulator Recommended Load Capacitance.......................................577 Startup Characteristics .....................................................................................578 Oscillator Characteristics .................................................................................580 PLL Characteristics............................................................................................582 SPI Master Mode Timing Characteristics ..........................................................584 SPI Slave Mode Timing Characteristics ...........................................................586 Expanded Bus Timing Characteristics – 16MHz ...............................................589 Freescale Semiconductor, Inc... List of Tables MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. List of Tables For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. General Description Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MC9S12T64 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Introduction The MC9S12T64 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of Flash EEPROM, 2K bytes of RAM, 2K bytes of CALRAM (Calibration RAM), two asynchronous serial communications interfaces (SCI), one serial peripheral interface (SPI), an 8 channel IC/OC enhanced capture timer, an 8-channel 10-bit analog-to-digital converter (ADC), an 8-channel pulse-width modulator (PWM), 25 discrete digital I/O channels (Port A, Port B, Port E and Port K). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the System Integration Module (SIM). The MC9S12T64 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. MC9S12T64Revision 1.1.1 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Features • HCS12 Core – 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii. 20-bit ALU iv. Instruction queue v. Enhanced indexed addressing – MEBI (Multiplexed External Bus Interface) 1 – MMC (Module Mapping Control) – INT (Interrupt control) – BKP (Breakpoints) – FBDM (Fast Background Debug Mode) i. Synchronous Serial Peripheral Interface (SPI mode) to allow fast read and write of internal memory contents. ii. 4M bit per second in SPI mode at 16MHz bus iii. Single Wire Interface • • CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor) LVD (Low Voltage Detector) – Low Voltage Detector to pull reset when the VDDR Supply Voltage falls to LVD trip voltage. • 64K byte Flash EEPROM 2 – Two 32K byte Flash EEPROM blocks independently programmable and erasable Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 1. Internal Flash EEPROM must be disabled to connect external memory devices with the external bus. 2. Whole 64K bytes of Flash EEPROM can not be used at a time, since 1K byte register block and 2K byte RAM array are always overlapped with Flash EEPROM. MC9S12T64Revision 1.1.1 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Features – Programmable during calibration • 2K byte RAM – Single cycle misaligned 16-bit access • 2K byte CALRAM (Calibration RAM) – 2K byte calibration block over Flash EEPROM – Access cycle compatible to Flash EEPROM • 8 channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger • Enhanced Capture Timer – 16-bit main counter with 7-bit prescaler – 8 programmable input capture or output compare channels – Two 8-bit or one 16-bit pulse accumulators • 8 PWM channels – Programmable period and duty cycle – 8-bit 8-channel or 16-bit 4-channel – Separate control for each pulse width and duty cycle – Center-aligned or left-aligned outputs – Programmable clock select logic with a wide range of frequencies – Fast emergency shutdown input – Usable as interrupt inputs • Serial interfaces – Two asynchronous Serial Communications Interfaces (SCI) – One synchronous Serial Peripheral Interface (SPI) • Operating Condition – 32 MHz CPU equivalent to 16MHz bus operation Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description – 2.25 to 2.75V Digital Supply Voltage generated using an internal voltage regulator – 4.75V to 5.25V Analog and I/O Supply Voltage – 80-Pin LQFP • Technology: 0.25 micron CMOS MC9S12T64Revision 1.1.1 General Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description MC9S12T64 Block Diagram MC9S12T64 Block Diagram 32K Byte Flash EEPROM 32K Byte Flash EEPROM 2K Byte RAM 2K Byte CALRAM VDDR VSSR VREGEN VDD1,2 VSS1,2 AN0 AN1 AN2 AN3 AN4 AN5 AN6 ETRIG/AN7 VRH VRL VDDA VSSA ATD Voltage Regulator Low Voltage Detector SO SCKBDM/SPIMODE MODC/TAGHI/SI/BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET Fast Background Debug Module with SPI or Single wire Interface Clock and Reset Generation Module Port K CPU12 ROMONE/ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RxD0 TxD0 RxD1 TxD1 MISO MOSI SCK SS PK7 1 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 VDDX VSSX PLL Periodic Interrupt COP Watchdog Clock Monitor Breakpoints Enhanced Capture Timer 8 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 XIRQ IRQ R/W System LSTRB/TAGLO Integration ECLK Module MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS PWM 8 18 TEST SCI0 DDRS Multiplexed Address/Data Bus SPI PTS SCI1 DDRA PTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DDRB PTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 8 2 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 16 Internal Logic 2.5V VDD1,2 VSS1,2 I/O Driver 5V VDDX VSSX Multiplexed Wide Bus PLL 2.5V VDDPLL A/D Converter 5V VDDA VSSA Multiplexed Narrow Bus VSSPLL Voltage Regulator 5V & I/O VDDR VSSR Figure 1 MC9S12T64 Block Diagram MC9S12T64Revision 1.1.1 General Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 AD 12 Freescale Semiconductor, Inc... DDRK DDRT DDRP DDRE DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 PTE DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PTP PTT PTK Freescale Semiconductor, Inc. General Description Ordering Information Table 1 MC9S12T64 Device Ordering Information Temperature Package Range (˚C) –40 to +85 80-Pin LQFP –40 to +105 –40 to +125 Voltage Designator C V M 5V Bus: 16MHz (CPU: 32MHz) MC9S12T64CPK16 MC9S12T64VPK16 MC9S12T64MPK16 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Frequency Order Number Freescale Semiconductor, Inc... Table 2 MC9S12T64 Development Tools Ordering Information Description Details Order Number (1) 1. Contact local sales for this information. MC9S12T64Revision 1.1.1 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Introduction The HCS12 CPU is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set. The HCS12 CPU allows instructions with odd byte counts, including many single-byte instructions. This provides efficient use of ROM space. An instruction pipe buffers program information so the CPU always has immediate access to at least three bytes of machine code at the start of every instruction. The HCS12 CPU also offers an extensive set of indexed addressing capabilities. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Programming Model The Core CPU12 programming model, shown in Figure 2, is the same as that of the 68HC12 and 68HC11. The register set and data types used in the model are covered in the subsections that follow. 7 15 A 0 D 7 B 0 0 8-BIT ACCUMULATORS A AND B 16-BIT DOUBLE ACCUMULATOR D (A: B) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 15 X 0 INDEX REGISTER X 15 Y 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER SXHINZVC CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE IRQ INTERRUPT MASK (DISABLE) HALF-CARRY FOR BCD ARITHMETIC XIRQ INTERRUPT MASK (DISABLE) STOP DISABLE (IGNORE STOP INSTRUCTION) Figure 2 Programming Model Accumulators General-purpose 8-bit accumulators A and B hold operands and results of operations. Some instructions use the combined 8-bit accumulators, A:B, as a 16-bit double accumulator, D, with the most significant byte in A. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Programming Model 7 Read: Write: Reset: 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Figure 3 Accumulator A 7 Read: Write: Reset: 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Figure 4 Accumulator B Most operations can use accumulator A or B interchangeably. However, there are a few exceptions. Add, subtract, and compare instructions involving both A and B (ABA, SBA, and CBA) only operate in one direction, so it is important to verify that the correct operand is in the correct accumulator. The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations. There is no equivalent instruction to adjust accumulator B. Index Registers (X and Y) 16-bit index registers X and Y are used for indexed addressing. In indexed addressing, the contents of an index register are added to a 5-bit, 9-bit, or 16-bit constant or to the contents of an accumulator to form the effective address of the instruction operand. Having two index registers is especially useful for moves and in cases where operands from two separate tables are used in a calculation. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) 15 Read: Write: Reset: 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 Index Register X Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 15 Read: Write: Reset: 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 Index Register Y Stack Pointer (SP) The stack stores system context during subroutine calls and interrupts, and can also be used for temporary data storage. It can be located anywhere in the standard 64K byte address space and can grow to any size up to the total amount of memory available in the system. SP holds the 16-bit address of the last stack location used. Normally, SP is initialized by one of the first instructions in an application program. The stack grows downward from the address pointed to by SP. Each time a byte is pushed onto the stack, the stack pointer is automatically decremented, and each time a byte is pulled from the stack, the stack pointer is automatically incremented. When a subroutine is called, the address of the instruction following the calling instruction is automatically calculated and pushed onto the stack. Normally, a return from subroutine (RTS) is executed at the end of a subroutine. The return instruction loads the program counter with the previously stacked return address and execution continues at that address. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Programming Model 15 Read: Write: Reset: 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 7 Stack Pointer (SP) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family When an interrupt occurs, the CPU: Freescale Semiconductor, Inc... • • • • Completes execution of the current instruction Calculates the address of the next instruction and pushes it onto the stack Pushes the contents of all the CPU registers onto the stack Loads the program counter with the address pointed to by the interrupt vector, and begins execution at that address The stacked CPU registers are referred to as an interrupt stack frame. The Core stack frame is the same as that of the CPU. Program Counter (PC) PC is a 16-bit register that holds the address of the next instruction to be executed. The address in PC is automatically incremented each time an instruction is executed. 15 Read: Write: Reset: 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 Program Counter (PC) Condition Code Register (CCR) CCR has five status bits, two interrupt mask bits, and a STOP instruction mask bit. It is named for the five conditions indicated by the status bits. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) The status bits reflect the results of CPU operations. The five status bits are half-carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry bit is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow for branching based on the results of a CPU operation. Most instructions automatically update condition codes, so it is rarely necessary to execute extra instructions to load and test a variable. The condition codes affected by each instruction are shown in the HCS12 CORE User Guide. The following paragraphs describe common uses of the condition codes. There are other, more specialized uses. For instance, the C status bit is used to enable weighted fuzzy logic rule evaluation. Specialized usages are described in the relevant portions of this guide and in the HCS12 CORE User Guide. Bit 7 Read: S Write: Reset: 1 6 X 1 5 H 0 4 I 1 3 N 0 2 Z 0 1 V 0 Bit 0 C 0 Figure 9 Condition Code Register (CCR) S — STOP Mask Bit Clearing the S bit enables the STOP instruction. Execution of a STOP instruction causes the on-chip oscillator to stop. This may be undesirable in some applications. When the S bit is set, the CPU treats the STOP instruction as a no-operation (NOP) instruction and continues on to the next instruction. Reset sets the S bit. 1 = STOP instruction disabled 0 = STOP instruction enabled X — XIRQ Mask Bit Clearing the X bit enables interrupt requests on the XIRQ pin. The XIRQ input is an updated version of the nonmaskable interrupt (NMI) input found on earlier generations of Motorola microcontroller units MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Programming Model (MCUs). Nonmaskable interrupts are typically used to deal with major system failures such as loss of power. However, enabling nonmaskable interrupts before a system is fully powered and initialized can lead to spurious interrupts. The X bit provides a mechanism for masking nonmaskable interrupts until the system is stable. Reset sets the X bit. As long as the X bit remains set, interrupt service requests made via the XIRQ pin are not recognized. Software must clear the X bit to enable interrupt service requests from the XIRQ pin. Once software clears the X bit, enabling XIRQ interrupt requests, only a reset can set it again. The X bit does not affect I bit maskable interrupt requests. When the X bit is clear and an XIRQ interrupt request occurs, the CPU stacks the cleared X bit. It then automatically sets the X and I bits in the CCR to disable XIRQ and maskable interrupt requests during the XIRQ interrupt service routine. An RTI instruction at the end of the interrupt service routine restores the cleared X bit to the CCR, re-enabling XIRQ interrupt requests. 1 = XIRQ interrupt requests disabled 0 = XIRQ interrupt requests enabled H — Half-Carry Bit The H bit indicates a carry from bit 3 of the result during an addition operation. The DAA instruction uses the value of the H bit to adjust the result in accumulator A to BCD format. ABA, ADD, and ADC are the only instructions that update the H bit. 1 = Carry from bit 3 after ABA, ADD, or ADC instruction 0 = No carry from bit 3 after ABA, ADD, or ADC instruction I — Interrupt Mask Bit Clearing the I bit enables maskable interrupt sources. Reset sets the I bit. To enable maskable interrupt requests, software must clear the I bit. Maskable interrupt requests that occur while the I bit is set remain pending until the I bit is cleared. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) When the I bit is clear and a maskable interrupt request occurs, the CPU stacks the cleared I bit. It then automatically sets the I bit in the CCR to prevent other maskable interrupt requests during the interrupt service routine. An RTI instruction at the end of the interrupt service routine restores the cleared I bit to the CCR, reenabling maskable interrupt requests. The I bit can be cleared within the service routine, but implementing a nested interrupt scheme requires great care, and seldom improves system performance. 1 = Maskable interrupt requests disabled 0 = Maskable interrupt requests enabled N — Negative Bit The N bit is set when the MSB of the result is set. N is most commonly used in two’s complement arithmetic, where the MSB of a negative number is one and the MSB of a positive number is zero, but it has other uses. For instance, if the MSB of a register or memory location is used as a status bit, the user can test the bit by loading an accumulator. 1 = MSB of result set 0 = MSB of result clear Z — Zero Bit The Z bit is set when all the bits of the result are zeros. Compare instructions perform an internal implied subtraction, and the condition codes, including Z, reflect the results of that subtraction. The INX, DEX, INY, and DEY instructions affect the Z bit and no other condition bits. These operations can only determine = and ≠. 1 = Result all zeros 0 = Result not all zeros V — Overflow Bit The V bit is set when a two’s complement overflow occurs as a result of an operation. 1 = Overflow 0 = No overflow C — Carry Bit MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Programming Model The C bit is set when a carry occurs during addition or a borrow occurs during subtraction. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate through the C bit to facilitate multiple-word shifts. 1 = Carry or borrow 0 = No carry or borrow HCS12 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 7 15 A 0 D 7 B 0 0 8-BIT ACCUMULATORS A AND B 16-BIT DOUBLE ACCUMULATOR D (A : B) 15 X 0 INDEX REGISTER X 15 Y 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER SXHINZVC CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE IRQ INTERRUPT MASK (DISABLE) HALF-CARRY FOR BCD ARITHMETIC XIRQ INTERRUPT MASK (DISABLE) STOP DISABLE (IGNORE STOP INSTRUCTION) Figure 10 Programming Model MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Data Format Summary Following is a discussion of the data types used and their organization in memory for the Core. Data Types The CPU uses the following types of data: • Bits 5-bit signed integers 8-bit signed and unsigned integers 8-bit, 2-digit binary coded decimal numbers 9-bit signed integers 16-bit signed and unsigned integers 16-bit effective addresses 32-bit signed and unsigned integers Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... • • • • • • • NOTE: Negative integers are represented in two’s complement form. Five-bit and 9-bit signed integers are used only as offsets for indexed addressing modes. Sixteen-bit effective addresses are formed during addressing mode computations. Thirty-two-bit integer dividends are used by extended division instructions. Extended multiply and extended multiply-and-accumulate instructions produce 32-bit products. Memory Organization The standard HCS12 Core address space is 64K bytes. However, the CPU has special instructions to support paged memory expansion which increases the standard area by means of predefined windows within the available address space. See the Module Mapping Control (MMC) section for more information. Eight-bit values can be stored at any odd or even byte address in available memory. Sixteen-bit values occupy two consecutive memory locations; the high byte is in the lowest address, but does not have to be aligned to an even boundary. Thirty-two-bit values occupy four MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Addressing Modes consecutive memory locations; the high byte is in the lowest address, but does not have to be aligned to an even boundary. All I/O and all on-chip peripherals are memory-mapped. No special instruction syntax is required to access these addresses. On-chip register and memory mapping are determined at the SoC level and are configured during integration of the Core into the system. Freescale Semiconductor, Inc... Addressing Modes A summary of the addressing modes used by the Core is given in Table 3 below. The operation of each of these modes is shown in detail in the HCS12 CORE user guide. Table 3 Addressing Mode Summary Addressing Mode Inherent Source Form INST (no externally supplied operands) INST #opr8i or INST #opr16i INST opr8a INST opr16a INST rel8 or INST rel16 INST oprx5,xysp INST oprx3,–xys INST oprx3,+xys INST oprx3,xys– INST oprx3,xys+ INST abd,xysp INST oprx9,xysp Abbreviation INH Description Operands (if any) are in CPU registers. Immediate IMM Operand is included in instruction stream; 8-bit or 16-bit size implied by context. Operand is the lower 8-bits of an address in the range $0000–$00FF. Operand is a 16-bit address. Effective address is the value in PC plus an 8-bit or 16-bit relative offset value. Effective address is the value in X, Y, SP, or PC plus a 5-bit signed constant offset. Effective address is the value in X, Y, or SP autodecremented by 1 to 8. Effective address is the value in X, Y, or SP autoincremented by 1 to 8. Effective address is the value in X, Y, or SP. The value is postdecremented by 1 to 8. Effective address is the value in X, Y, or SP. The value is postincremented by 1 to 8. Effective address is the value in X, Y, SP, or PC plus the value in A, B, or D. Effective address is the value in X, Y, SP, or PC plus a 9-bit signed constant offset. Direct Extended Relative Indexed (5-bit offset) Indexed (predecrement) Indexed (preincrement) Indexed (postdecrement) Indexed (postincrement) Indexed (accumulator offset) Indexed (9-bit offset) DIR EXT REL IDX IDX IDX IDX IDX IDX IDX1 MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 3 Addressing Mode Summary (Continued) Addressing Mode Indexed (16-bit offset) Indexed-indirect (16-bit offset) Indexed-indirect (D accumulator offset) Source Form INST oprx16,xysp INST [oprx16,xysp] INST [D,xysp] Abbreviation IDX2 [IDX2] [D,IDX] Description Effective address is the value in X, Y, SP, or PC plus a 16-bit constant offset. The value in X, Y, SP, or PC plus a 16-bit constant offset points to the effective address. The value in X, Y, SP, or PC plus the value in D points to the effective address. Instruction Set Overview All memory and I/O are mapped in a common 64K byte address space, allowing the same set of instructions to access memory, I/O, and control registers. Load, store, transfer, exchange, and move instructions facilitate movement of data to and from memory and peripherals. There are instructions for signed and unsigned addition, division and multiplication with 8-bit, 16-bit, and some larger operands. Special arithmetic and logic instructions aid stacking operations, indexing, BCD calculation, and condition code register manipulation. There are also dedicated instructions for multiply and accumulate operations, table interpolation, and specialized mathematical calculations for fuzzy logic operations. A summary of the CPU instruction set is given in Figure 4 below. A detailed overview of the entire instruction set is covered in the HCS12 Core User Guide. Table 4 Instruction Set Summary Source Form ABA ABXSame as LEAX B,X ABYSame as LEAY B,Y Operation Add B to A; (A)+(B)⇒A Add B to X; (X)+(B)⇒X Add B to Y; (Y)+(B)⇒Y Address Mode INH IDX IDX Machine Coding (Hex) 18 06 1A E5 19 ED OO Pf Pf Access Detail SXHINZVC ––∆–∆∆∆∆ –––––––– –––––––– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form ADCA #opr8i ADCA opr8a ADCA opr16a ADCA oprx0_xysppc ADCA oprx9,xysppc ADCA oprx16,xysppc ADCA [D,xysppc] ADCA [oprx16,xysppc] ADCB #opr8i ADCB opr8a ADCB opr16a ADCB oprx0_xysppc ADCB oprx9,xysppc ADCB oprx16,xysppc ADCB [D,xysppc] ADCB [oprx16,xysppc] ADDA #opr8i ADDA opr8a ADDA opr16a ADDA oprx0_xysppc ADDA oprx9,xysppc ADDA oprx16,xysppc ADDA [D,xysppc] ADDA [oprx16,xysppc] ADDB #opr8i ADDB opr8a ADDB opr16a ADDB oprx0_xysppc ADDB oprx9,xysppc ADDB oprx16,xysppc ADDB [D,xysppc] ADDB [oprx16,xysppc] ADDD #opr16i ADDD opr8a ADDD opr16a ADDD oprx0_xysppc ADDD oprx9,xysppc ADDD oprx16,xysppc ADDD [D,xysppc] ADDD [oprx16,xysppc] ANDA #opr8i ANDA opr8a ANDA opr16a ANDA oprx0_xysppc ANDA oprx9,xysppc ANDA oprx16,xysppc ANDA [D,xysppc] ANDA [oprx16,xysppc] ANDB #opr8i ANDB opr8a ANDB opr16a ANDB oprx0_xysppc ANDB oprx9,xysppc ANDB oprx16,xysppc ANDB [D,xysppc] ANDB [oprx16,xysppc] ANDCC #opr8i Operation Add with carry to A; (A)+(M)+C⇒A or (A)+imm+C⇒A Address Mode IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM Machine Coding (Hex) 89 ii 99 dd B9 hh ll A9 xb A9 xb ff A9 xb ee ff A9 xb A9 xb ee ff C9 ii D9 dd F9 hh ll E9 xb E9 xb ff E9 xb ee ff E9 xb E9 xb ee ff 8B ii 9B dd BB hh ll AB xb AB xb ff AB xb ee ff AB xb AB xb ee ff CB ii DB dd FB hh ll EB xb EB xb ff EB xb ee ff EB xb EB xb ee ff C3 jj kk D3 dd F3 hh ll E3 xb E3 xb ff E3 xb ee ff E3 xb E3 xb ee ff 84 ii 94 dd B4 hh ll A4 xb A4 xb ff A4 xb ee ff A4 xb A4 xb ee ff C4 ii D4 dd F4 hh ll E4 xb E4 xb ff E4 xb ee ff E4 xb E4 xb ee ff 10 ii Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P SXHINZVC ––∆–∆∆∆∆ Add with carry to B; (B)+(M)+C⇒B or (B)+imm+C⇒B ––∆–∆∆∆∆ Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Add to A; (A)+(M)⇒A or (A)+imm⇒A ––∆–∆∆∆∆ Add to B; (B)+(M)⇒B or (B)+imm⇒B ––∆–∆∆∆∆ Add to D; (A:B)+(M:M+1)⇒A:B or (A:B)+imm⇒A:B ––––∆∆∆∆ AND with A; (A)•(M)⇒A or (A)•imm⇒A ––––∆∆0– AND with B; (B)•(M)⇒B or (B)•imm⇒B ––––∆∆0– AND with CCR; (CCR)•imm⇒CCR ⇓⇓⇓⇓⇓⇓⇓⇓ MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 4 Instruction Set Summary (Continued) Source Form ASL opr16aSame as LSL ASL oprx0_xysp ASL oprx9,xysppc ASL oprx16,xysppc ASL [D,xysppc] ASL [oprx16,xysppc] ASLASame as LSLA ASLBSame as LSLB ASLDSame as LSLD Operation Arithmetic shift left M 0 C b7 b0 Address Mode EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH 0 b0 Machine Coding (Hex) 78 hh ll 68 xb 68 xb ff 68 xb ee ff 68 xb 68 xb ee ff 48 58 59 Access Detail rPwO rPw rPwO frPwP fIfrPw fIPrPw O O O SXHINZVC ––––∆∆∆∆ Arithmetic shift left A Arithmetic shift left B Arithmetic shift left D ••• ••• ––––∆∆∆∆ Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family C b7 A b0 b7 B Freescale Semiconductor, Inc... ASR opr16a ASR oprx0_xysppc ASR oprx9,xysppc ASR oprx16,xysppc ASR [D,xysppc] ASR [oprx16,xysppc] ASRA ASRB BCC rel8Same as BHS BCLR opr8a, msk8 BCLR opr16a, msk8 BCLR oprx0_xysppc, msk8 BCLR oprx9,xysppc, msk8 BCLR oprx16,xysppc, msk8 BCS rel8Same as BLO BEQ rel8 BGE rel8 BGND BGT rel8 BHI rel8 BHS rel8Same as BCC BITA #opr8i BITA opr8a BITA opr16a BITA oprx0_xysppc BITA oprx9,xysppc BITA oprx16,xysppc BITA [D,xysppc] BITA [oprx16,xysppc] BITB #opr8i BITB opr8a BITB opr16a BITB oprx0_xysppc BITB oprx9,xysppc BITB oprx16,xysppc BITB [D,xysppc] BITB [oprx16,xysppc] Arithmetic shift right M b7 b0 C Arithmetic shift right A Arithmetic shift right B Branch if C clear; if C=0, then (PC)+2+rel⇒PC EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH REL DIR EXT IDX IDX1 IDX2 REL REL REL INH REL REL REL IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 77 hh ll 67 xb 67 xb ff 67 xb ee ff 67 xb 67 xb ee ff 47 57 24 rr 4D dd mm 1D hh ll mm 0D xb mm 0D xb ff mm 0D xb ee ff mm 25 rr 27 rr 2C rr 00 2E rr 22 rr 24 rr 85 ii 95 dd B5 hh ll A5 xb A5 xb ff A5 xb ee ff A5 xb A5 xb ee ff C5 ii D5 dd F5 hh ll E5 xb E5 xb ff E5 xb ee ff E5 xb E5 xb ee ff rPwO rPw rPwO frPwP fIfrPw fIPrPw O O PPP (branch) P (no branch) rPwO rPwP rPwO rPwP frPwPO PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) VfPPP PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf ––––∆∆∆∆ –––––––– ––––∆∆0– Clear bit(s) in M; (M)•mask byte⇒M Branch if C set; if C=1, then (PC)+2+rel⇒PC Branch if equal; if Z=1, then (PC)+2+rel⇒PC Branch if ≥ 0, signed; if N⊕V=0, then (PC)+2+rel⇒PC Enter background debug mode Branch if > 0, signed; if Z | (N⊕V)=0, then (PC)+2+rel⇒PC Branch if higher, unsigned; if C | Z=0, then (PC)+2+rel⇒PC Branchifhigherorsame,unsigned;if C=0,then(PC)+2+rel⇒PC Bit test A; (A)•(M) or (A)•imm –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– ––––∆∆0– Bit test B; (B)•(M) or (B)•imm ––––∆∆0– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form BLE rel8 BLO rel8Same as BCS BLS rel8 BLT rel8 BMI rel8 Operation Branch if ≤ 0,signed; if Z | (N⊕V)=1, then (PC)+2+rel⇒PC Branch if lower, unsigned; if C=1, then (PC)+2+rel⇒PC Branch if lower or same, unsigned; if C | Z=1, then (PC)+2+rel⇒PC Branch if < 0, signed; if N⊕V=1, then (PC)+2+rel⇒PC Branch if minus; if N=1, then (PC)+2+rel⇒PC Branch if not equal to 0; if Z=0, then (PC)+2+rel⇒PC Branch if plus; if N=0, then (PC)+2+rel⇒PC Branch always Branch if bit(s) clear; if (M)•(mask byte)=0, then (PC)+2+rel⇒PC Address Mode REL REL REL REL REL REL REL REL DIR EXT IDX IDX1 IDX2 REL DIR EXT IDX IDX1 IDX2 DIR EXT IDX IDX1 IDX2 REL Machine Coding (Hex) 2F rr 25 rr 23 rr 2D rr 2B rr 26 rr 2A rr 20 rr 4F dd mm rr 1F hh ll mm rr 0F xb mm rr 0F xb ff mm rr 0F xb ee ff mm rr 21 rr 4E dd mm rr 1E hh ll mm rr 0E xb mm rr 0E xb ff mm rr 0E xb ee ff mm rr 4C dd mm 1C hh ll mm 0C xb mm 0C xb ff mm 0C xb ee ff mm 07 rr Access Detail PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP rPPP rfPPP rPPP rfPPP PrfPPP P rPPP rfPPP rPPP rfPPP PrfPPP rPwO rPwP rPwO rPwP frPwPO SPPP SXHINZVC –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... BNE rel8 BPL rel8 BRA rel8 BRCLR opr8a, msk8, rel8 BRCLR opr16a, msk8, rel8 BRCLR oprx0_xysppc, msk8, rel8 BRCLR oprx9,xysppc, msk8, rel8 BRCLR oprx16,xysppc, msk8, rel8 BRN rel8 BRSET opr8, msk8, rel8 BRSET opr16a, msk8, rel8 BRSET oprx0_xysppc, msk8, rel8 BRSET oprx9,xysppc, msk8, rel8 BRSET oprx16,xysppc, msk8, rel8 BSET opr8, msk8 BSET opr16a, msk8 BSET oprx0_xysppc, msk8 BSET oprx9,xysppc, msk8 BSET oprx16,xysppc, msk8 BSR rel8 Branch never Branch if bit(s) set; if (M)•(mask byte)=0, then (PC)+2+rel⇒PC –––––––– –––––––– Set bit(s) in M (M) | mask byte⇒M ––––∆∆0– Branch to subroutine; (SP)–2⇒SP RTNH:RTNL⇒MSP:MSP+1 (PC)+2+rel⇒PC Branch if V clear; if V=0, then (PC)+2+rel⇒PC Branch if V set; if V=1, then (PC)+2+rel⇒PC Call subroutine in expanded memory (SP)–2⇒SP RTNH:RTNL⇒MSP:MSP+1 (SP)–1⇒SP; (PPG)⇒MSP pg⇒PPAGE register subroutine address⇒PC Compare A to B; (A)–(B) Clear C bit Clear I bit –––––––– BVC rel8 BVS rel8 CALL opr16a, page CALL oprx0_xysppc, page CALL oprx9,xysppc, page CALL oprx16,xysppc, page CALL [D,xysppc] CALL [oprx16, xysppc] CBA CLCSame as ANDCC #$FE CLISame as ANDCC #$EF REL REL EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH IMM IMM 28 rr 29 rr 4A hh ll pg 4B xb pg 4B xb ff pg 4B xb ee ff pg 4B xb 4B xb ee ff 18 17 10 FE 10 EF PPP (branch) P (no branch) PPP (branch) P (no branch) gnSsPPP gnSsPPP gnSsPPP fgnSsPPP fIignSsPPP fIignSsPPP OO P P –––––––– –––––––– –––––––– ––––∆∆∆∆ –––––––0 –––0–––– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 4 Instruction Set Summary (Continued) Source Form CLR opr16a CLR oprx0_xysppc CLR oprx9,xysppc CLR oprx16,xysppc CLR [D,xysppc] CLR [oprx16,xysppc] CLRA CLRB CLVSame as ANDCC #$FD CMPA #opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xysppc CMPA oprx9,xysppc CMPA oprx16,xysppc CMPA [D,xysppc] CMPA [oprx16,xysppc] CMPB #opr8i CMPB opr8a CMPB opr16a CMPB oprx0_xysppc CMPB oprx9,xysppc CMPB oprx16,xysppc CMPB [D,xysppc] CMPB [oprx16,xysppc] COM opr16a COM oprx0_xysppc COM oprx9,xysppc COM oprx16,xysppc COM [D,xysppc] COM [oprx16,xysppc] COMA COMB CPD #opr16i CPD opr8a CPD opr16a CPD oprx0_xysppc CPD oprx9,xysppc CPD oprx16,xysppc CPD [D,xysppc] CPD [oprx16,xysppc] CPS #opr16i CPS opr8a CPS opr16a CPS oprx0_xysppc CPS oprx9,xysppc CPS oprx16,xysppc CPS [D,xysppc] CPS [oprx16,xysppc] CPX #opr16i CPX opr8a CPX opr16a CPX oprx0_xysppc CPX oprx9,xysppc CPX oprx16,xysppc CPX [D,xysppc] CPX [oprx16,xysppc] Operation Clear M; $00⇒M Address Mode EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IMM IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] Machine Coding (Hex) 79 hh ll 69 xb 69 xb ff 69 xb ee ff 69 xb 69 xb ee ff 87 C7 10 FD 81 ii 91 dd B1 hh ll A1 xb A1 xb ff A1 xb ee ff A1 xb A1 xb ee ff C1 ii D1 dd F1 hh ll E1 xb E1 xb ff E1 xb ee ff E1 xb E1 xb ee ff 71 hh ll 61 xb 61 xb ff 61 xb ee ff 61 xb 61 xb ee ff 41 51 8C jj kk 9C dd BC hh ll AC xb AC xb ff AC xb ee ff AC xb AC xb ee ff 8F jj kk 9F dd BF hh ll AF xb AF xb ff AF xb ee ff AF xb AF xb ee ff 8E jj kk 9E dd BE hh ll AE xb AE xb ff AE xb ee ff AE xb AE xb ee ff Access Detail PwO Pw PwO PwP PIfw PIPw O O P P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf rPwO rPw rPwO frPwP fIfrPw fIPrPw O O PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf SXHINZVC ––––0100 Clear A; $00⇒A Clear B; $00⇒B Clear V Compare A (A)–(M) or (A)–imm ––––––0– ––––∆∆∆∆ Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Compare B (B)–(M) or (B)–imm ––––∆∆∆∆ Complement M; (M)=$FF–(M)⇒M ––––∆∆01 Complement A; (A)=$FF–(A)⇒A Complement B; (B)=$FF–(B)⇒B Compare D (A:B)–(M:M+1) or (A:B)–imm ––––∆∆∆∆ Compare SP (SP)–(M:M+1) or (SP)–imm ––––∆∆∆∆ Compare X (X)–(M:M+1) or (X)–imm ––––∆∆∆∆ MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form CPY #opr16i CPY opr8a CPY opr16a CPY oprx0_xysppc CPY oprx9,xysppc CPY oprx16,xysppc CPY [D,xysppc] CPY [oprx16,xysppc] DAA DBEQ abdxysp, rel9 Compare Y (Y)–(M:M+1) or (Y)–imm Operation Address Mode IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH REL (9-bit) Machine Coding (Hex) 8D jj kk 9D dd BD hh ll AD xb AD xb ff AD xb ee ff AD xb AD xb ee ff 18 07 04 lb rr Access Detail PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf OfO PPP (branch) PPO (no branch) PPP (branch) PPO (no branch) rPwO rPw rPwO frPwP fIfrPw fIPrPw O O Pf O O ffffffffffO OffffffffffO ORROfffRRfWWP SXHINZVC ––––∆∆∆∆ Decimal adjust A for BCD Decrement and branch if equal to 0 (counter)–1⇒counter if (counter)=0, then branch ––––∆∆?∆ –––––––– Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... DBNE abdxysp, rel9 Decrement and branch if not equal to 0; REL (counter)–1⇒counter; (9-bit) if (counter)≠0, then branch Decrement M; (M)–1⇒M EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH IDX INH INH 04 lb rr –––––––– DEC opr16a DEC oprx0_xysppc DEC oprx9,xysppc DEC oprx16,xysppc DEC [D,xysppc] DEC [oprx16,xysppc] DECA DECB DESSame as LEAS –1,SP DEX DEY EDIV EDIVS EMACS opr16a Decrement A; (A)–1⇒A Decrement B; (B)–1⇒B Decrement SP; (SP)–1⇒SP Decrement X; (X)–1⇒X Decrement Y; (Y)–1⇒Y 73 hh ll 63 xb 63 xb ff 63 xb ee ff 63 xb 63 xb ee ff 43 53 1B 9F 09 03 11 18 14 18 12 hh ll ––––∆∆∆– –––––––– –––––∆–– –––––∆–– ––––∆∆∆∆ ––––∆∆∆∆ ––––∆∆∆∆ Extended divide, unsigned; 32 by 16 INH to 16-bit; (Y:D)÷(X)⇒Y; remainder⇒D Extended divide,signed; 32 by 16 to 16-bit; (Y:D)÷(X)⇒Y remainder⇒D INH Extended multiply and accumulate, Special signed; (MX:MX+1)×(MY:MY+1)+ (M~M+3)⇒M~M+3; 16 by 16 to 32-bit Extended maximum in D; put larger of 2 unsigned 16-bit values in D MAX[(D), (M:M+1)]⇒D N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)] Extended maximum in M; put larger of 2 unsigned 16-bit values in M MAX[(D), (M:M+1)]⇒M:M+1 N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)] Extended minimum in D; put smaller of 2 unsigned 16-bit values in D MIN[(D), (M:M+1)]⇒D N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)] IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] EMAXD oprx0_xysppc EMAXD oprx9,xysppc EMAXD oprx16,xysppc EMAXD [D,xysppc] EMAXD [oprx16,xysppc] EMAXM oprx0_xysppc EMAXM oprx9,xysppc EMAXM oprx16,xysppc EMAXM [D,xysppc] EMAXM [oprx16,xysppc] EMIND oprx0_xysppc EMIND oprx9,xysppc EMIND oprx16,xysppc EMIND [D,xysppc] EMIND [oprx16,xysppc] 18 1A xb 18 1A xb ff 18 1A xb ee ff 18 1A xb 18 1A xb ee ff 18 1E xb 18 1E xb ff 18 1E xb ee ff 18 1E xb 18 1E xb ee ff 18 1B xb 18 1B xb ff 18 1B xb ee ff 18 1B xb 18 1B xb ee ff ORPf ORPO OfRPP OfIfRPf OfIPRPf ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ORPf ORPO OfRPP OfIfRPf OfIPRPf ––––∆∆∆∆ ––––∆∆∆∆ ––––∆∆∆∆ MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 4 Instruction Set Summary (Continued) Source Form EMINM oprx0_xysppc EMINM oprx9,xysppc EMINM oprx16,xysppc EMINM [D,xysppc] EMINM [oprx16,xysppc] EMUL EMULS Operation Extended minimum in M; put smaller of 2 unsigned 16-bit values in M MIN[(D), (M:M+1)]⇒M:M+1 N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)] Extended multiply, unsigned (D)×(Y)⇒Y:D; 16 by 16 to 32-bit Extended multiply, signed (D)×(Y)⇒Y:D; 16 by 16 to 32-bit Exclusive OR A (A)⊕(M)⇒A or (A)⊕imm⇒A Address Mode IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH Machine Coding (Hex) 18 1F xb 18 1F xb ff 18 1F xb ee ff 18 1F xb 18 1F xb ee ff 13 18 13 Access Detail ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ffO OfO OffO (if followed by page 2 instruction) P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf ORRffffffP SXHINZVC ––––∆∆∆∆ ––––∆∆–∆ ––––∆∆–∆ Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... EORA #opr8i EORA opr8a EORA opr16a EORA oprx0_xysppc EORA oprx9,xysppc EORA oprx16,xysppc EORA [D,xysppc] EORA [oprx16,xysppc] EORB #opr8i EORB opr8a EORB opr16a EORB oprx0_xysppc EORB oprx9,xysppc EORB oprx16,xysppc EORB [D,xysppc] EORB [oprx16,xysppc] ETBL oprx0_xysppc IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] 88 ii 98 dd B8 hh ll A8 xb A8 xb ff A8 xb ee ff A8 xb A8 xb ee ff C8 ii D8 dd F8 hh ll E8 xb E8 xb ff E8 xb ee ff E8 xb E8 xb ee ff 18 3F xb ––––∆∆0– Exclusive OR B (B)⊕(M)⇒B or (B)⊕imm⇒B ––––∆∆0– Extended table lookup and interpolate, IDX 16-bit; (M:M+1)+ [(B)×((M+2:M+3)–(M:M+1))]⇒D ––––∆∆–∆ Before executing ETBL, initialize B with fractional part of lookup value; initialize index register to point to first table entry (M:M+1). No extensions or indirect addressing allowed. EXG abcdxysp,abcdxysp Exchange register contents (r1)⇔(r2) r1 and r2 same size $00:(r1)⇒r2r1=8-bit; r2=16-bit (r1L)⇔(r2)r1=16-bit; r2=8-bit Fractional divide; (D)÷(X)⇒X remainder⇒D; 16 by 16-bit Increment and branch if equal to 0 (counter)+1⇒counter If (counter)=0, then branch INH B7 eb P –––––––– FDIV IBEQ abdxysp, rel9 INH REL (9-bit) 18 11 04 lb rr OffffffffffO PPP (branch) PPO (no branch) PPP (branch) PPO (no branch) OffffffffffO OffffffffffO rPwO rPw rPwO frPwP fIfrPw fIPrPw O O –––––∆∆∆ –––––––– IBNE abdxysp, rel9 Increment and branch if not equal to 0 REL (counter)+1⇒counter (9-bit) If (counter)≠0, then branch Integer divide, unsigned; (D)÷(X)⇒X Remainder⇒D; 16 by 16-bit Integer divide, signed; (D)÷(X)⇒X Remainder⇒D; 16 by 16-bit Increment M; (M)+1⇒M INH INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH 04 lb rr –––––––– IDIV IDIVS INC opr16a INC oprx0_xysppc INC oprx9,xysppc INC oprx16,xysppc INC [D,xysppc] INC [oprx16,xysppc] INCA INCB 18 10 18 15 72 hh ll 62 xb 62 xb ff 62 xb ee ff 62 xb 62 xb ee ff 42 52 –––––∆0∆ ––––∆∆∆∆ ––––∆∆∆– Increment A; (A)+1⇒A Increment B; (B)+1⇒B MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form INSSame as LEAS 1,SP INX INY JMP opr16a JMP oprx0_xysppc JMP oprx9,xysppc JMP oprx16,xysppc JMP [D,xysppc] JMP [oprx16,xysppc] Operation Increment SP; (SP)+1⇒SP Increment X; (X)+1⇒X Increment Y; (Y)+1⇒Y Jump Subroutine address⇒PC Address Mode IDX INH INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] REL REL REL REL Machine Coding (Hex) 1B 81 08 02 06 hh ll 05 xb 05 xb ff 05 xb ee ff 05 xb 05 xb ee ff 17 dd 16 hh ll 15 xb 15 xb ff 15 xb ee ff 15 xb 15 xb ee ff 18 24 qq rr 18 25 qq rr 18 27 qq rr 18 2C qq rr 18 2E qq rr 18 22 qq rr 18 24 qq rr 18 2F qq rr 18 25 qq rr 18 23 qq rr Pf O O PPP PPP PPP fPPP fIfPPP fIfPPP SPPP SPPP PPPS PPPS fPPPS fIfPPPS fIfPPPS OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP OPO OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) Access Detail SXHINZVC –––––––– –––––∆–– –––––∆–– –––––––– Freescale Semiconductor, Inc... JSR opr8a JSR opr16a JSR oprx0_xysppc JSR oprx9,xysppc JSR oprx16,xysppc JSR [D,xysppc] JSR [oprx16,xysppc] LBCC rel16Same as LBHS LBCS rel16Same as LBLO LBEQ rel16 LBGE rel16 LBGT rel16 LBHI rel16 LBHS rel16Same as LBCC LBLE rel16 LBLO rel16Same as LBCS LBLS rel16 Jump to subroutine (SP)–2⇒SP RTNH:RTNL⇒MSP:MSP+1 Subroutine address⇒PC –––––––– Long branch if C clear; if C=0, then (PC)+4+rel⇒PC Long branch if C set; if C=1, then (PC)+4+rel⇒PC Long branch if equal; if Z=1, then (PC)+4+rel⇒PC Long branch if ≥ 0, signed If N⊕V=0, then (PC)+4+rel⇒PC –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– Long branch if > 0, signed REL If Z | (N⊕V)=0, then (PC)+4+rel⇒PC Long branch if higher, unsigned If C | Z=0, then (PC)+4+rel⇒PC Long branch if higher or same, unsigned; If C=0, (PC)+4+rel⇒PC Long branch if ≤ 0, signed; if Z | (N⊕V)=1, then (PC)+4+rel⇒PC Long branch if lower, unsigned; if C=1, then (PC)+4+rel⇒PC Long branch if lower or same, unsigned; If C | Z=1, then (PC)+4+rel⇒PC Long branch if < 0, signed If N⊕V=1, then (PC)+4+rel⇒PC Long branch if minus If N=1, then (PC)+4+rel⇒PC Long branch if not equal to 0 If Z=0, then (PC)+4+rel⇒PC Long branch if plus If N=0, then (PC)+4+rel⇒PC Long branch always Long branch never Long branch if V clear If V=0,then (PC)+4+rel⇒PC Long branch if V set If V=1,then (PC)+4+rel⇒PC REL REL REL REL REL LBLT rel16 LBMI rel16 LBNE rel16 LBPL rel16 LBRA rel16 LBRN rel16 LBVC rel16 LBVS rel16 REL REL REL REL REL REL REL REL 18 2D qq rr 18 2B qq rr 18 26 qq rr 18 2A qq rr 18 20 qq rr 18 21 qq rr 18 28 qq rr 18 29 qq rr –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 4 Instruction Set Summary (Continued) Source Form LDAA #opr8i LDAA opr8a LDAA opr16a LDAA oprx0_xysppc LDAA oprx9,xysppc LDAA oprx16,xysppc LDAA [D,xysppc] LDAA [oprx16,xysppc] LDAB #opr8i LDAB opr8a LDAB opr16a LDAB oprx0_xysppc LDAB oprx9,xysppc LDAB oprx16,xysppc LDAB [D,xysppc] LDAB [oprx16,xysppc] LDD #opr16i LDD opr8a LDD opr16a LDD oprx0_xysppc LDD oprx9,xysppc LDD oprx16,xysppc LDD [D,xysppc] LDD [oprx16,xysppc] LDS #opr16i LDS opr8a LDS opr16a LDS oprx0_xysppc LDS oprx9,xysppc LDS oprx16,xysppc LDS [D,xysppc] LDS [oprx16,xysppc] LDX #opr16i LDX opr8a LDX opr16a LDX oprx0_xysppc LDX oprx9,xysppc LDX oprx16,xysppc LDX [D,xysppc] LDX [oprx16,xysppc] LDY #opr16i LDY opr8a LDY opr16a LDY oprx0_xysppc LDY oprx9,xysppc LDY oprx16,xysppc LDY [D,xysppc] LDY [oprx16,xysppc] LEAS oprx0_xysppc LEAS oprx9,xysppc LEAS oprx16,xysppc LEAX oprx0_xysppc LEAX oprx9,xysppc LEAX oprx16,xysppc LEAY oprx0_xysppc LEAY oprx9,xysppc LEAY oprx16,xysppc Load A (M)⇒A or imm⇒A Operation Address Mode IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 IDX IDX1 IDX2 IDX IDX1 IDX2 Machine Coding (Hex) 86 ii 96 dd B6 hh ll A6 xb A6 xb ff A6 xb ee ff A6 xb A6 xb ee ff C6 ii D6 dd F6 hh ll E6 xb E6 xb ff E6 xb ee ff E6 xb E6 xb ee ff CC jj kk DC dd FC hh ll EC xb EC xb ff EC xb ee ff EC xb EC xb ee ff CF jj kk DF dd FF hh ll EF xb EF xb ff EF xb ee ff EF xb EF xb ee ff CE jj kk DE dd FE hh ll EE xb EE xb ff EE xb ee ff EE xb EE xb ee ff CD jj kk DD dd FD hh ll ED xb ED xb ff ED xb ee ff ED xb ED xb ee ff 1B xb 1B xb ff 1B xb ee ff 1A xb 1A xb ff 1A xb ee ff 19 xb 19 xb ff 19 xb ee ff Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf Pf PO PP Pf PO PP Pf PO PP SXHINZVC ––––∆∆0– Load B (M)⇒B or imm⇒B ––––∆∆0– Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Load D (M:M+1)⇒A:B or imm⇒A:B ––––∆∆0– Load SP (M:M+1)⇒SP or imm⇒SP ––––∆∆0– Load X (M:M+1)⇒X or imm⇒X ––––∆∆0– Load Y (M:M+1)⇒Y or imm⇒Y ––––∆∆0– Load effective address into SP EA⇒SP Load effective address into X EA⇒X Load effective address into Y EA⇒Y –––––––– –––––––– –––––––– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form LSL opr16aSame as ASL LSL oprx0_xysppc LSL oprx9,xysppc LSL oprx16,xysppc LSL [D,xysppc] LSL [oprx16,xysppc] LSLASame as ASLA LSLBSame as ASLB LSLDSame as ASLD Operation Logical shift left M 0 C b7 b0 Address Mode EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH 0 b0 Machine Coding (Hex) 78 hh ll 68 xb 68 xb ff 68 xb ee ff 68 xb 68 xb ee ff 48 58 59 Access Detail rOPw rPw rPOw frPPw fIfrPw fIPrPw O O O SXHINZVC ––––∆∆∆∆ Logical shift left A Logical shift left B Logical shift left D ••• ••• ––––∆∆∆∆ C b7 A b0 b7 B LSR opr16a LSR oprx0_xysppc LSR oprx9,xysppc LSR oprx16,xysppc LSR [D,xysppc] LSR [oprx16,xysppc] LSRA LSRB LSRD Logical shift right M 0 b7 b0 C Logical shift right A Logical shift right B Logical shift right D 0 b7 A b0 b7 B b0 C EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH 74 hh ll 64 xb 64 xb ff 64 xb ee ff 64 xb 64 xb ee ff 44 54 49 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O O ––––0∆∆∆ ––––0∆∆∆ MAXA oprx0_xysppc MAXA oprx9,xysppc MAXA oprx16,xysppc MAXA [D,xysppc] MAXA [oprx16,xysppc] MAXM oprx0_xysppc MAXM oprx9,xysppc MAXM oprx16,xysppc MAXM [D,xysppc] MAXM [oprx16,xysppc] MEM Maximum in A; put larger of 2 unsigned 8-bit values in A MAX[(A), (M)]⇒A N, Z, V, C bits reflect result of internal compare [(A)–(M)] Maximum in M; put larger of 2 unsigned 8-bit values in M MAX[(A), (M)]⇒M N, Z, V, C bits reflect result of internal compare [(A)–(M)] IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] 18 18 xb 18 18 xb ff 18 18 xb ee ff 18 18 xb 18 18 xb ee ff 18 1C xb 18 1C xb ff 18 1C xb ee ff 18 1C xb 18 1C xb ee ff 01 OrPf OrPO OfrPP OfIfrPf OfIPrPf OrPw OrPwO OfrPwP OfIfrPw OfIPrPw RRfOw ––––∆∆∆∆ ––––∆∆∆∆ Determine grade of membership; Special µ (grade)⇒MY; (X)+4⇒X; (Y)+1⇒Y If (A)P2, then µ=0; else µ= MIN[((A)–P1)×S1, (P2–(A))×S2, $FF] (A)=current crisp input value; X points at 4 data bytes (P1, P2, S1, S2) of a trapezoidal membership function; Y points at fuzzy input (RAM location) Minimum in A; put smaller of 2 unsigned 8-bit values in A MIN[(A), (M)]⇒A N, Z, V, C bits reflect result of internal compare [(A)–(M)] Minimum in N; put smaller of two unsigned 8-bit values in M MIN[(A), (M)]⇒M N, Z, V, C bits reflect result of internal compare [(A)–(M)] Move byte Memory-to-memory 8-bit byte-move (M1)⇒M2 First operand specifies byte to move IDX IDX1 IDX2 [D,IDX] [IDX2] IDX IDX1 IDX2 [D,IDX] [IDX2] IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX ––?–???? MINA oprx0_xysppc MINA oprx9,xysppc MINA oprx16,xysppc MINA [D,xysppc] MINA [oprx16,xysppc] MINM oprx0_xysppc MINM oprx9,xysppc MINM oprx16,xysppc MINM [D,xysppc] MINM [oprx16,xysppc] MOVB #opr8, opr16a MOVB #opr8i, oprx0_xysppc MOVB opr16a, opr16a MOVB opr16a, oprx0_xysppc MOVB oprx0_xysppc, opr16a MOVB oprx0_xysppc, oprx0_xysppc 18 19 xb 18 19 xb ff 18 19 xb ee ff 18 19 xb 18 19 xb ee ff 18 1D xb 18 1D xb ff 18 1D xb ee ff 18 1D xb 18 1D xb ee ff 18 0B ii hh ll 18 08 xb ii 18 0C hh ll hh ll 18 09 xb hh ll 18 0D xb hh ll 18 0A xb xb OrPf OrPO OfrPP OfIfrPf OfIPrPf OrPw OrPwO OfrPwP OfIfrPw OfIPrPw OPwP OPwO OrPwPO OPrPw OrPwP OrPwO ––––∆∆∆∆ ––––∆∆∆∆ –––––––– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 4 Instruction Set Summary (Continued) Source Form MOVW #oprx16, opr16a MOVW #opr16i, oprx0_xysppc MOVW opr16a, opr16a MOVW opr16a, oprx0_xysppc MOVW oprx0_xysppc, opr16a MOVW oprx0_xysppc, oprx0_xysppc MUL NEG opr16a NEG oprx0_xysppc NEG oprx9,xysppc NEG oprx16,xysppc NEG [D,xysppc] NEG [oprx16,xysppc] NEGA NEGB NOP ORAA #opr8i ORAA opr8a ORAA opr16a ORAA oprx0_xysppc ORAA oprx9,xysppc ORAA oprx16,xysppc ORAA [D,xysppc] ORAA [oprx16,xysppc] ORAB #opr8i ORAB opr8a ORAB opr16a ORAB oprx0_xysppc ORAB oprx9,xysppc ORAB oprx16,xysppc ORAB [D,xysppc] ORAB [oprx16,xysppc] ORCC #opr8i PSHA PSHB PSHC PSHD PSHX PSHY PULA PULB PULC PULD Operation Move word Memory-to-memory 16-bit word-move (M1:M1+1)⇒M2:M2+1 First operand specifies word to move Address Mode IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM INH INH INH INH INH INH INH INH INH INH Machine Coding (Hex) 18 03 jj kk hh ll 18 00 xb jj kk 18 04 hh ll hh ll 18 01 xb hh ll 18 05 xb hh ll 18 02 xb xb 12 70 hh ll 60 xb 60 xb ff 60 xb ee ff 60 xb 60 xb ee ff 40 50 A7 8A ii 9A dd BA hh ll AA xb AA xb ff AA xb ee ff AA xb AA xb ee ff CA ii DA dd FA hh ll EA xb EA xb ff EA xb ee ff EA xb EA xb ee ff 14 ii 36 37 39 3B 34 35 32 33 38 3A Access Detail OPWPO OPPW ORPWPO OPRPW ORPWP ORPWO O rPwO rPw rPwO frPwP fIfrPw fIPrPw O O O P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P Os Os Os OS OS OS ufO ufO ufO UfO SXHINZVC –––––––– Multiply, unsigned (A)×(B)⇒A:B; 8 by 8-bit Negate M; 0–(M)⇒M or (M)+1⇒M –––––––∆ ––––∆∆∆∆ Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Negate A; 0–(A)⇒A or (A)+1⇒A Negate B; 0–(B)⇒B or (B)+1⇒B No operation OR accumulator A (A) | (M)⇒A or (A) | imm⇒A –––––––– ––––∆∆0– OR accumulator B (B) | (M)⇒B or (B) | imm⇒B ––––∆∆0– OR CCR; (CCR) | imm⇒CCR Push A; (SP)–1⇒SP; (A)⇒MSP Push B; (SP)–1⇒SP; (B)⇒MSP Push CCR; (SP)–1⇒SP; (CCR)⇒MSP Push D (SP)–2⇒SP; (A:B)⇒MSP:MSP+1 Push X (SP)–2⇒SP; (XH:XL)⇒MSP:MSP+1 Push Y (SP)–2⇒SP; (YH:YL)⇒MSP:MSP+1 Pull A (MSP)⇒A; (SP)+1⇒SP Pull B (MSP)⇒B; (SP)+1⇒SP Pull CCR (MSP)⇒CCR; (SP)+1⇒SP Pull D (MSP:MSP+1)⇒A:B; (SP)+2⇒SP ⇑–⇑⇑⇑⇑⇑⇑ –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– ∆⇓∆∆∆∆∆∆ –––––––– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form PULX PULY REV Operation Pull X (MSP:MSP+1)⇒XH:XL; (SP)+2⇒SP Pull Y (MSP:MSP+1)⇒YH:YL; (SP)+2⇒SP Rule evaluation, unweighted; find smallest rule input; store to rule outputs unless fuzzy output is larger Address Mode INH INH Special Machine Coding (Hex) 30 31 18 3A Access Detail UfO UfO Orf(t^tx)O* ff+Orft^** SXHINZVC –––––––– –––––––– ––?–??∆? *The t^tx loop is executed once for each element in the rule list. The ^ denotes a check for pending interrupt requests. **These are additional cycles caused by an interrupt: ff is the exit sequence and Orft^ is the re-entry sequence. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family REVW Freescale Semiconductor, Inc... Rule evaluation, weighted; rule weights optional; find smallest rule input; store to rule outputs unless fuzzy output is larger Special 18 3B ORf(t^Tx)O* or ORf(r^ffRf)O** ffff+ORft^*** ffff+ORfr^**** ––?–??∆ ! *With weighting not enabled, the t^Tx loop is executed once for each element in the rule list. The ^ denotes a check for pending interrupt requests. **With weighting enabled, the t^Tx loop is replaced by r^ffRf. ***Additional cycles caused by an interrupt when weighting is not enabled: ffff is the exit sequence and ORft^ is the re-entry sequence. **** Additional cycles caused by an interrupt when weighting is enabled: ffff is the exit sequence and ORfr^ is the re-entry sequence. ROL opr16a ROL oprx0_xysppc ROL oprx9,xysppc ROL oprx16,xysppc ROL [D,xysppc] ROL [oprx16,xysppc] ROLA ROLB ROR opr16a ROR oprx0_xysppc ROR oprx9,xysppc ROR oprx16,xysppc ROR [D,xysppc] ROR [oprx16,xysppc] RORA RORB RTC Rotate left M b7 b0 C Rotate left A Rotate left B Rotate right M b0 b7 EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH 75 hh ll 65 xb 65 xb ff 65 xb ee ff 65 xb 65 xb ee ff 45 55 76 hh ll 66 xb 66 xb ff 66 xb ee ff 66 xb 66 xb ee ff 46 56 0A rPwO rPw rPwO frPwP fIfrPw fIPrPw O O rPwO rPw rPwO frPwP fIfrPw fIPrPw O O uUnfPPP ––––∆∆∆∆ ––––∆∆∆∆ C Rotate right A Rotate right B Return from call; (MSP)⇒PPAGE (SP)+1⇒SP; (MSP:MSP+1)⇒PCH:PCL (SP)+2⇒SP Return from interrupt (MSP)⇒CCR; (SP)+1⇒SP (MSP:MSP+1)⇒B:A;(SP)+2⇒SP (MSP:MSP+1)⇒XH:XL;(SP)+4⇒SP (MSP:MSP+1)⇒PCH:PCL;(SP)+2⇒SP (MSP:MSP+1)⇒YH:YL;(SP)+4⇒SP Return from subroutine (MSP:MSP+1)⇒PCH:PCL; (SP)+2⇒SP Subtract B from A; (A)–(B)⇒A –––––––– RTI INH 0B uUUUUPPP or uUUUUfVfPPP* ∆⇓∆∆∆∆∆∆ *RTI takes 11 cycles if an interrupt is pending. RTS INH 3D UfPPP –––––––– SBA INH 18 16 OO ––––∆∆∆∆ MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 4 Instruction Set Summary (Continued) Source Form SBCA #opr8i SBCA opr8a SBCA opr16a SBCA oprx0_xysppc SBCA oprx9,xysppc SBCA oprx16,xysppc SBCA [D,xysppc] SBCA [oprx16,xysppc] SBCB #opr8i SBCB opr8a SBCB opr16a SBCB oprx0_xysppc SBCB oprx9,xysppc SBCB oprx16,xysppc SBCB [D,xysppc] SBCB [oprx16,xysppc] SECSame as ORCC #$01 SEISame as ORCC #$10 SEVSame as ORCC #$02 SEX abc,dxyspSame as TFR r1, r2 Operation Subtract with carry from A (A)–(M)–C⇒A or (A)–imm–C⇒A Address Mode IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM IMM IMM INH Machine Coding (Hex) 82 ii 92 dd B2 hh ll A2 xb A2 xb ff A2 xb ee ff A2 xb A2 xb ee ff C2 ii D2 dd F2 hh ll E2 xb E2 xb ff E2 xb ee ff E2 xb E2 xb ee ff 14 01 14 10 14 02 B7 eb Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P P P P SXHINZVC ––––∆∆∆∆ Subtract with carry from B (B)–(M)–C⇒B or (B)–imm–C⇒B ––––∆∆∆∆ Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Set C bit Set I bit Set V bit Sign extend; 8-bit r1 to 16-bit r2 $00:(r1)⇒r2 if bit 7 of r1 is 0 $FF:(r1)⇒r2 if bit 7 of r1 is 1 Store accumulator A (A)⇒M –––––––1 –––1–––– ––––––1– –––––––– STAA opr8a STAA opr16a STAA oprx0_xysppc STAA oprx9,xysppc STAA oprx16,xysppc STAA [D,xysppc] STAA [oprx16,xysppc] STAB opr8a STAB opr16a STAB oprx0_xysppc STAB oprx9,xysppc STAB oprx16,xysppc STAB [D,xysppc] STAB [oprx16,xysppc] STD opr8a STD opr16a STD oprx0_xysppc STD oprx9,xysppc STD oprx16,xysppc STD [D,xysppc] STD [oprx16,xysppc] STOP DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH 5A dd 7A hh ll 6A xb 6A xb ff 6A xb ee ff 6A xb 6A xb ee ff 5B dd 7B hh ll 6B xb 6B xb ff 6B xb ee ff 6B xb 6B xb ee ff 5C dd 7C hh ll 6C xb 6C xb ff 6C xb ee ff 6C xb 6C xb ee ff 18 3E Pw PwO Pw PwO PwP PIfw PIPw Pw PwO Pw PwO PwP PIfw PIPw PW PWO PW PWO PWP PIfW PIPW OOSSSSsf (enter stop mode) fVfPPP (exit stop mode) ff (continue stop mode) OO (if stop mode disabled by S=1) ––––∆∆0– Store accumulator B (B)⇒M ––––∆∆0– Store D (A:B)⇒M:M+1 ––––∆∆0– Stop processing; (SP)–2⇒SP RTNH:RTNL⇒MSP:MSP+1 (SP)–2⇒SP; (YH:YL)⇒MSP:MSP+1 (SP)–2⇒SP; (XH:XL)⇒MSP:MSP+1 (SP)–2⇒SP; (B:A)⇒MSP:MSP+1 (SP)–1⇒SP; (CCR)⇒MSP Stop all clocks –––––––– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form STS opr8a STS opr16a STS oprx0_xysppc STS oprx9,xysppc STS oprx16,xysppc STS [D,xysppc] STS [oprx16,xysppc] STX opr8a STX opr16a STX oprx0_xysppc STX oprx9,xysppc STX oprx16,xysppc STX [D,xysppc] STX [oprx16,xysppc] STY opr8a STY opr16a STY oprx0_xysppc STY oprx9,xysppc STY oprx16,xysppc STY [D,xysppc] STY [oprx16,xysppc] SUBA #opr8i SUBA opr8a SUBA opr16a SUBA oprx0_xysppc SUBA oprx9,xysppc SUBA oprx16,xysppc SUBA [D,xysppc] SUBA [oprx16,xysppc] SUBB #opr8i SUBB opr8a SUBB opr16a SUBB oprx0_xysppc SUBB oprx9,xysppc SUBB oprx16,xysppc SUBB [D,xysppc] SUBB [oprx16,xysppc] SUBD #opr16i SUBD opr8a SUBD opr16a SUBD oprx0_xysppc SUBD oprx9,xysppc SUBD oprx16,xysppc SUBD [D,xysppc] SUBD [oprx16,xysppc] SWI Operation Store SP (SPH:SPL)⇒M:M+1 Address Mode DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH Machine Coding (Hex) 5F dd 7F hh ll 6F xb 6F xb ff 6F xb ee ff 6F xb 6F xb ee ff 5E dd 7E hh ll 6E xb 6E xb ff 6E xb ee ff 6E xb 6E xb ee ff 5D dd 7D hh ll 6D xb 6D xb ff 6D xb ee ff 6D xb 6D xb ee ff 80 ii 90 dd B0 hh ll A0 xb A0 xb ff A0 xb ee ff A0 xb A0 xb ee ff C0 ii D0 dd F0 hh ll E0 xb E0 xb ff E0 xb ee ff E0 xb E0 xb ee ff 83 jj kk 93 dd B3 hh ll A3 xb A3 xb ff A3 xb ee ff A3 xb A3 xb ee ff 3F Access Detail PW PWO PW PWO PWP PIfW PIPW PW PWO PW PWO PWP PIfW PIPW PW PWO PW PWO PWP PIfW PIPW P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf VSPSSPSsP* SXHINZVC ––––∆∆0– Store X (XH:XL)⇒M:M+1 ––––∆∆0– Store Y (YH:YL)⇒M:M+1 ––––∆∆0– Subtract from A (A)–(M)⇒A or (A)–imm⇒A ––––∆∆∆∆ Subtract from B (B)–(M)⇒B or (B)–imm⇒B ––––∆∆∆∆ Subtract from D (A:B)–(M:M+1)⇒A:B or (A:B)–imm⇒A:B ––––∆∆∆∆ Software interrupt; (SP)–2⇒SP RTNH:RTNL⇒MSP:MSP+1 (SP)–2⇒SP; (YH:YL)⇒MSP:MSP+1 (SP)–2⇒SP; (XH:XL)⇒MSP:MSP+1 (SP)–2⇒SP; (B:A)⇒MSP:MSP+1 (SP)–1⇒SP; (CCR)⇒MSP;1⇒I (SWI vector)⇒PC Transfer A to B; (A)⇒B Transfer A to CCR; (A)⇒CCR Assembled as TFR A, CCR Transfer B to A; (B)⇒A –––1–––– *The CPU also uses VSPSSPSsP for hardware interrupts and unimplemented opcode traps. TAB TAP TBA INH INH INH 18 0E B7 02 18 0F OO P OO ––––∆∆0– ∆⇓∆∆∆∆∆∆ ––––∆∆0– MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 4 Instruction Set Summary (Continued) Source Form TBEQ abdxysp,rel9 TBL oprx0_xysppc TBNE abdxysp,rel9 TFR abcdxysp,abcdxysp Operation Test and branch if equal to 0 If (counter)=0, then (PC)+2+rel⇒PC Table lookup and interpolate, 8-bit (M)+[(B)×((M+1)–(M))]⇒A Test and branch if not equal to 0 If (counter)≠0, then (PC)+2+rel⇒PC Transfer from register to register (r1)⇒r2r1 and r2 same size $00:(r1)⇒r2r1=8-bit; r2=16-bit (r1L)⇒r2r1=16-bit; r2=8-bit Transfer CCR to A; (CCR)⇒A Trap unimplemented opcode; (SP)–2⇒SP RTNH:RTNL⇒MSP:MSP+1 (SP)–2⇒SP; (YH:YL)⇒MSP:MSP+1 (SP)–2⇒SP; (XH:XL)⇒MSP:MSP+1 (SP)–2⇒SP; (B:A)⇒MSP:MSP+1 (SP)–1⇒SP; (CCR)⇒MSP 1⇒I; (trap vector)⇒PC Test M; (M)–0 Address Mode REL (9-bit) IDX REL (9-bit) INH Machine Coding (Hex) 04 lb rr 18 3D xb 04 lb rr B7 eb Access Detail PPP (branch) PPO (no branch) ORfffP PPP (branch) PPO (no branch) P SXHINZVC –––––––– ––––∆∆–∆ –––––––– –––––––– or ∆⇓∆∆∆∆∆∆ Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... TPASame as TFR CCR,A TRAP trapnum INH INH B7 20 18 tn tn = $30–$39 or tn = $40–$FF P OVSPSSPSsP –––––––– –––1–––– TST opr16a TST oprx0_xysppc TST oprx9,xysppc TST oprx16,xysppc TST [D,xysppc] TST [oprx16,xysppc] TSTA TSTB TSXSame as TFR SP,X TSYSame as TFR SP,Y TXSSame as TFR X,SP TYSSame as TFR Y,SP WAI Test A; (A)–0 Test B; (B)–0 Transfer SP to X; (SP)⇒X Transfer SP to Y; (SP)⇒Y Transfer X to SP; (X)⇒SP Transfer Y to SP; (Y)⇒SP Wait for interrupt; (SP)–2⇒SP RTNH:RTNL⇒MSP:MSP+1 (SP)–2⇒SP; (YH:YL)⇒MSP:MSP+1 (SP)–2⇒SP; (XH:XL)⇒MSP:MSP+1 (SP)–2⇒SP; (B:A)⇒MSP:MSP+1 (SP)–1⇒SP; (CCR)⇒MSP EXT IDX IDX1 IDX2 [D,IDX] [IDX2] INH INH INH INH INH INH INH F7 hh ll E7 xb E7 xb ff E7 xb ee ff E7 xb E7 xb ee ff 97 D7 B7 75 B7 76 B7 57 B7 67 3E rPO rPf rPO frPP fIfrPf fIPrPf O O P P P P OSSSSsf (before interrupt) fVfPPP (after interrupt) ––––∆∆00 –––––––– –––––––– –––––––– –––––––– –––––––– or –––1–––– or –1–1–––– WAV ∑ i=1 B i=1 B Calculate Special 18 3C S i F i ⇒ Y:D weighted Of(frr^ffff)O** SSS+UUUrr^*** ––?–?∆?? ∑ Fi ⇒ X average; sum of products (SOP) and sum of weights (SOW)* *Initialize B, X, and Y: B=number of elements; X points at first element in Si list; Y points at first element in Fi list. All Si and Fi elements are 8-bit values. **The frr^ffff sequence is the loop for one iteration of SOP and SOW accumulation. The ^ denotes a check for pending interrupt requests. ***Additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence. Intermediate values use six stack bytes. wavr* Resume executing interrupted WAV Special 3C UUUrr^ffff(frr^ ffff)O** SSS+UUUrr^*** ––?–?∆?? MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 4 Instruction Set Summary (Continued) Source Form Operation Address Mode Machine Coding (Hex) Access Detail SXHINZVC *wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0. **The frr^ffff sequence is the loop for one iteration of SOP and SOW recovery. The ^ denotes a check for pending interrupt requests. ***These are additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence. XGDXSame as EXG D, X XGDYSame as EXG D, Y Exchange D with X; (D)⇔(X) Exchange D with Y; (D)⇔(Y) INH INH B7 C5 B7 C6 P P –––––––– –––––––– Table 5 Register and Memory Notation A or a Accumulator A An Bit n of accumulator A B or b Accumulator B Bn Bit n of accumulator B D or d Accumulator D Dn Bit n of accumulator D X or x Index register X XH High byte of index register X XL Low byte of index register X Xn Bit n of index register X Y or y Index register Y YH High byte of index register Y YL Low byte of index register Y Yn Bit n of index register Y SP or sp Stack pointer SPn Bit n of stack pointer PC or pc Program counter PCH High byte of program counter PCL Low byte of program counter CCR or c Condition code register M Address of 8-bit memory location Mn Bit n of byte at memory location M Rn Bit n of the result of an arithmetic or logical operation In Bit n of the intermediate result of an arithmetic or logical operation RTNH High byte of return address RTNL Low byte of return address ( ) Contents of MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Register and Memory Notation Freescale Semiconductor, Inc. Central Processing Unit (CPU) Source Form Notation The Source Form column of the summary in Table 4 gives essential information about assembler source forms. For complete information about writing source files for a particular assembler, refer to the documentation provided by the assembler vendor. Everything in the Source Form column, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, square brackets ( [ or ] ), plus signs (+), minus signs (–), and the register designation (A, B, D), are literal characters. The groups of italic characters shown in Table 6 represent variable information to be supplied by the programmer. These groups can include any alphanumeric character or the underscore character, but cannot include a space or comma. For example, the groups xysppc and oprx0_xysppc are both valid, but the two groups oprx0 xysppc are not valid because there is a space between them. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 6 Source Form Notation abc abcdxysp abd abdxysp dxysp msk8 opr8i Register designator for A, B, or CCR Register designator for A, B, CCR, D, X, Y, or SP Register designator for A, B, or D Register designator for A, B, D, X, Y, or SP Register designator for D, X, Y, or SP 8-bit mask value Some assemblers require the # symbol before the mask value. 16-bit immediate value 8-bit address value used with direct address mode 16-bit address value Indexed addressing postbyte code: oprx3,–xysp — Predecrement X , Y, or SP by 1–8 oprx3,+xysp — Preincrement X , Y, or SP by 1–8 oprx3,xysp– — Postdecrement X, Y, or SP by 1–8 oprx3,xysp+ — Postincrement X, Y, or SP by 1–8 oprx5,xysppc — 5-bit constant offset from X, Y, SP, or PC abd,xysppc — Accumulator A, B, or D offset from X, Y, SP, or PC Any positive integer from 1 to 8 for pre/post increment/decrement Any integer from –16 to +15 Any integer from –256 to +255 Any integer from –32,768 to +65,535 8-bit value for PPAGE register Some assemblers require the # symbol before this value. Label of branch destination within –256 to +255 locations Label of branch destination within –512 to +511 locations Any label within the 64-Kbyte memory space Any 8-bit integer from $30 to $39 or from $40 to $FF Register designator for X or Y or SP Register designator for X or Y or SP or PC Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 8-bit immediate value Freescale Semiconductor, Inc... opr16i opr8a opr16a oprx0_xysp oprx3 oprx5 oprx9 oprx16 page rel8 rel9 rel16 trapnum xysp xysppc MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Operation Notation Table 7 Operation Notation + – • | ⊕ × ÷ Add Subtract AND OR Exclusive OR Multiply Concatenate Transfer Exchange Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Divide Freescale Semiconductor, Inc... : ⇒ ⇔ Address Mode Notation Table 8 Address Mode Notation INH Inherent; no operands in instruction stream IMM Immediate; operand immediate value in instruction stream DIR Direct; operand is lower byte of address from $0000 to $00FF EXT Operand is a 16-bit address REL Two’s complement relative offset; for branch instructions IDX Indexed (no extension bytes); includes: 5-bit constant offset from X, Y, SP or PC Pre/post increment/decrement by 1–8 Accumulator A, B, or D offset IDX1 9-bit signed offset from X, Y, SP, or PC; 1 extension byte IDX2 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes [IDX2] Indexed-indirect; 16-bit offset from X, Y, SP, or PC [D, IDX] Indexed-indirect; accumulator D offset from X, Y, SP, or PC Machine Code Notation In the Machine Code (Hex) column of the summary in Table 4, digits 0–9 and upper case letters A–F represent hexadecimal values. Pairs of lower-case letters represent 8-bit values as shown in Table 9. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 9 Machine Code Notation dd 8-bit direct address from $0000 to $00FF; high byte is $00 ee High byte of a 16-bit constant offset for indexed addressing eb Exchange/transfer postbyte ff Low eight bits of a 9-bit signed constant offset in indexed addressing, or low byte of a 16-bit constant offset in indexed addressing hh High byte of a 16-bit extended address ii 8-bit immediate data value kk Low byte of a 16-bit immediate data value lb Loop primitive (DBNE) postbyte ll Low byte of a 16-bit extended address mm 8-bit immediate mask value for bit manipulation instructions; bits that are set indicate bits to be affected Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family jj High byte of a 16-bit immediate data value Freescale Semiconductor, Inc... pg Program page or bank number used in CALL instruction qq High byte of a 16-bit relative offset for long branches tn Trap number from $30 to $39 or from $40 to $FF rr Signed relative offset $80 (–128) to $7F (+127) relative to the byte following the relative offset byte, or low byte of a 16-bit relative offset for long branches xb Indexed addressing postbyte Access Detail Notation A single-letter code in the Access Detail column of Figure 4 represents a single CPU access cycle. An upper-case letter indicates a 16-bit access. Table 10 Access Detail Notation f Free cycle. During an f cycle, the CPU does not use the bus. An f cycle is always one cycle of the system bus clock. An f cycle can be used by a queue controller or the background debug system to perform a single-cycle access without disturbing the CPU. g Read PPAGE register. A g cycle is used only in CALL instructions and is not visible on the external bus. Since PPAGE is an internal 8-bit register, a g cycle is never stretched. I Read indirect pointer. Indexed-indirect instructions use the 16-bit indirect pointer from memory to address the instruction operand. An I cycle is a 16-bit read that can be aligned or misaligned. An I cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. An I cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. i Read indirect PPAGE value. An i cycle is used only in indexed-indirect CALL instructions. The 8-bit PPAGE value for the CALL destination is fetched from an indirect memory location. An i cycle is stretched only when controlled by a chip-select circuit that is programmed for slow memory. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 10 Access Detail Notation (Continued) n Write PPAGE register. An n cycle is used only in CALL and RTC instructions to write the destination value of the PPAGE register and is not visible on the external bus. Since the PPAGE register is an internal 8-bit register, an n cycle is never stretched. O Optional cycle. An O cycle adjusts instruction alignment in the instruction queue. An O cycle can be a free cycle (f) or a program word access cycle (P). When the first byte of an instruction with an odd number of bytes is misaligned, the O cycle becomes a P cycle to maintain queue order. If the first byte is aligned, the O cycle is an f cycle. The $18 prebyte for a page-two opcode is treated as a special one-byte instruction. If the prebyte is misaligned, the O cycle at the beginning of the instruction becomes a P cycle to maintain queue order. If the prebyte is aligned, the O cycle is an f cycle. If the instruction has an odd number of bytes, it has a second O cycle at the end. If the first O cycle is a P cycle (prebyte misaligned), the second O cycle is an f cycle. If the first O cycle is an f cycle (prebyte aligned), the second O cycle is a P cycle. An O cycle that becomes a P cycle can be extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. An O cycle that becomes an f cycle is never stretched. P Program word access. Program information is fetched as aligned 16-bit words. A P cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored externally. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. r 8-bit data read. An r cycle is stretched only when controlled by a chip-select circuit programmed for slow memory. R 16-bit data read. An R cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. An R cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. s Stack 8-bit data. An s cycle is stretched only when controlled by a chip-select circuit programmed for slow memory. S Stack 16-bit data. An S cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching if the address space is assigned to a chip-select circuit programmed for slow memory. An S cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single cycle misaligned word access. w 8-bit data write. A w cycle is stretched only when controlled by a chip-select circuit programmed for slow memory. W 16-bit data write. A W cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A W cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. u Unstack 8-bit data. A W cycle is stretched only when controlled by a chip-select circuit programmed for slow memory. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Overview Table 10 Access Detail Notation (Continued) U Unstack 16-bit data. A U cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A U cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single-cycle misaligned word access. V 16-bit vector fetch. Vectors are always aligned 16-bit words. A V cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... t 8-bit conditional read. A t cycle is either a data read cycle or a free cycle, depending on the data and flow of the REVW instruction. A t cycle is stretched only when controlled by a chip-select circuit programmed for slow memory. T 16-bit conditional read. A T cycle is either a data read cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. A T cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A T cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. x 8-bit conditional write. An x cycle is either a data write cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. An x cycle is stretched only when controlled by a chip-select circuit programmed for slow memory. Special Notation for Branch Taken/Not Taken PPP/P A short branch requires three cycles if taken, one cycle if not taken. Since the instruction consists of a single word containing both an opcode and an 8-bit offset, the not-taken case is simple — the queue advances, another program word fetch is made, and execution continues with the next instruction. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address. OPPP/OPO A long branch requires four cycles if taken, three cycles if not taken. An O cycle is required because all long branches are page two opcodes and thus include the $18 prebyte. The prebyte is treated as a one-byte instruction. If the prebyte is misaligned, the O cycle is a P cycle; if the prebyte is aligned, the O cycle is an f cycle. As a result, both the taken and not-taken cases use one O cycle for the prebyte. In the not-taken case, the queue must advance so that execution can continue with the next instruction, and another O cycle is required to maintain the queue. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address. MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Central Processing Unit (CPU) Condition Code State Notation Table 11 Condition Code State Notation – Not changed by operation 0 Cleared by operation 1 Set by operation ∆ Set or cleared by operation ⇓ May be cleared or remain set, but not set by operation ⇑ May be set or remain cleared, but not cleared by operation ! Used for a special purpose Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family ? May be changed by operation but final state not defined Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64 Pin Assignments in 80-pin LQFP . . . . . . . . . . . . . . . . . . 59 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MC9S12T64 Pin Assignments in 80-pin LQFP The MC9S12T64 is available in an 80-pin low-profile quad flat package (LQFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 11 shows pin assignments. In expanded narrow modes the lower byte data is multiplexed with higher byte data through pins PA7:0 (port A). MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... PORT S PORT T PORT AD PAD2 / AN2 PAD3 / AN3 PAD4 / AN4 PAD5 / AN5 PAD6 / AN6 PAD7 / AN7 / ETRIG PS0 / RxD0 PS1 / TxD0 PS2 / RxD1 PS3 / TxD1 PS4 / MISO PS5 / MOSI PS6 / SCK PS7 / SS VREGEN VSSX VDDX TEST PT0 / IOC0 PT1 / IOC1 MC9S12T64Revision 1.1.1 62 63 64 65 66 61 67 68 69 70 71 72 73 74 75 76 77 78 79 80 IOC2 / PT2 IOC3 / PT3 IOC4 / PT4 IOC5 / PT5 IOC6 / PT6 IOC7 / PT7 MODC/TAGHI/SI / BKGD PAD1 / AN1 PAD0 / AN0 VSSA VRL VRH VDDA PA7 / ADDR15/DATA15/DATA7 PA6 / ADDR14/DATA14/DATA6 PA5 / ADDR13/DATA13/DATA5 VSS2 VDD2 Pinout and Signal Description PORT A EBDM MC9S12T64 80-PIN LQFP PORT P 20 24 23 22 21 30 29 28 27 26 25 13 14 15 16 17 18 19 SCKBDM /SPIMODE SO VDD1 VSS1 PWM0 / PP0 PWM1 / PP1 PWM2 / PP2 PWM3 / PP3 PWM4 / PP4 PWM5 / PP5 PWM6 / PP6 PWM7 / PP7 ADDR0/DATA0 / PB0 1 2 3 4 5 6 7 8 9 10 11 12 PORT A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PA4 / ADDR12/DATA12/DATA4 PA3 / ADDR11/DATA11/DATA3 PA2 / ADDR10/DATA10/DATA2 PA1 / ADDR9/DATA9/DATA1 PA0 / ADDR8/DATA8/DATA0 PE7 / NOACC / XCLKS PE6 / MODB/IPIPE1 PE5 / MODA/IPIPE0 PE4 / ECLK Freescale Semiconductor, Inc. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Figure 11 Pin Assignments in 80-pin LQFP for MC9S12T64 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com R/W / PE2 IRQ / PE1 XIRQ / PE0 ADDR4/DATA4 / PB4 ADDR3/DATA3 / PB3 ADDR2/DATA2 / PB2 ADDR1/DATA1 / PB1 XFC VSSPLL XTAL EXTAL RESET ADDR7/DATA7 / PB7 ADDR6/DATA6 / PB6 ADDR5/DATA5 / PB5 TAGLO / LSTRB / PE3 ROMONE/ECS / PK7 VSSR VDDR VDDPLL PORT B PORT E Shaded pins are power and ground PORT K Freescale Semiconductor, Inc. Pinout and Signal Description MC9S12T64 Pin Assignments in 80-pin LQFP HD D 60 41 DIM A A1 A2 b c D E e HD HE L L1 Θ x y ZD ZE MIN. — 0.05 — 0.17 0.10 11.90 11.90 — 13.80 13.80 — 0.80 0.0 ° — — — — MILLIMETERS TYP. — 0.10 1.40 0.22 0.17 12.00 12.00 0.50 14.00 14.00 0.50 1.00 — — — 1.25 1.25 MAX. 1.70 0.15 — 0.27 0.20 12.10 12.10 — 14.20 14.20 — 1.20 10.0 ° 0.10 0.10 — — 61 40 E HE 80 21 1 20 L1 L A A1 ZD or ZE x e DETAIL A b (AFTER PLATING) y DETAIL A c (AFTER PLATING) A2 Θ Figure 12 80-pin LQFP Mechanical Dimensions MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Description Power Supply Pins MC9S12T64 power and ground pins are described below and summarized in Table 12. NOTE: All VSS pins must be connected together in the applications. VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. VDD1, VDD2, VSS1, VSS2 — Core Power Pins Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. No static load is allowed on these pins. The internal voltage regulator is turned off, if VREGEN is tied to ground. No load allowed except for bypass capacitors. NOTE: VDDA, VSSA — Power Supply Pins for ATD and VREG VDDA and VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides the reference for the internal voltage regulator.This allows the supply voltage to the A/D and the reference voltage to be bypassed independently. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... VDDX, VSSX — Power & Ground Pins for I/O Drivers External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. Freescale Semiconductor, Inc. Pinout and Signal Description Power Supply Pins VRH, VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog-to-digital converter. VDDPLL, VSSPLL — Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator. No load allowed except for bypass capacitors. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... NOTE: VREGEN — On Chip Voltage Regulator Enable Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally. NOTE: The voltage regulator must be enabled for proper LVD operation. If the voltage regulator is disabled, the LVD operation is unpredictable. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Table 12 MC9S12T64 Power and Ground Connection Summary Mnemonic VDD1 VSS1 VDD2 VSS2 VDDR VSSR VDDX VSSX VDDA VSSA VRL VRH VDDPLL VSSPLL VREGEN Pin Number 80 LQFP 10 11 50 51 34 35 77 76 55 58 57 56 33 31 75 Nominal Voltage 2.5 V 0V 2.5 V 0V 0V 5.0 V 0V 5.0 V 0V 0V 5.0 V 2.5 V 0V 5.0 V External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Description Internal power and ground generated by internal regulator Freescale Semiconductor, Inc... 5.0 V MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Signal Descriptions EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. Refer to the Clocks and Reset Generator (CRG) section for more information. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... RESET — External Reset Pin An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. TEST — Test Pin This input only pin is reserved for test. The TEST pin must be tied to VSS in all applications. NOTE: VREGEN — Voltage Regulator Enable Pin This input only pin enables or disables the on-chip voltage regulator. XFC — PLL Loop Filter Pin PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. Refer to the Clocks and Reset Generator (CRG) section for more information. BKGD / TAGHI / SI / MODC — Background Debug, Tag High, and Mode Pin The BKGD/TAGHI/SI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description This pin has an weak on-chip active pullup that is enabled at all times. It is assumed that there is an external pullup and that drivers connected to BKGD do not typically drive the high level. NOTE: The resistance of the internal pull-up may be too high depending on the speed and the load to ensure proper BDM communication. In this case an additional external pull-up resistor must be provided. SO pin This pin is used as a serial out data pin when FBDM is in SPI mode. During reset and immediately out of reset this pin will drive low. PAD[7:0] / AN0[7:0] — Port AD Input Pins [7:0] PAD7-PAD0 are general purpose input pins and analog inputs of the analog to digital converter. PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PE7 / NOACC / XCLKS — Port E I/O Pin 7 PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SPIMODE/SCKBDM pin This pin is used as serial clock when FBDM is in SPI mode. This pin has an weak on-chip active pull-down that is enabled at all times. FBDM will be in single wire mode as default. Pulling this pin high will put FBDM in SPI mode. Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions The XCLKS input controls whether a crystal in combination with the internal Colpitts oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low, Pierce oscillator/external clock circuit is configured on the EXTAL and XTAL pins. If the input is a logic high, the Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device, if the pin is left floating, the default configuration is the Colpitts oscillator circuit on EXTAL and XTAL. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low. PE5 / MODA / IPIPE0 — Port E I/O Pin 5 PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low. PE4 / ECLK — Port E I/O Pin 4 PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference. PE3 / LSTRB / TAGLO — Port E I/O Pin 3 PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue. PE2 / R/W — Port E I/O Pin 2 PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description PE1 / IRQ — Port E Input Pin 1 PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode. PE0 / XIRQ — Port E Input Pin 0 PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PK7 / ECS / ROMONE — Port K I/O Pin 7 PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). During MCU Normal Expanded and Emulation modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET, the state of this pin determines the state of the ROMON bit (MISC register) according to Table 24 in page 129. See page 128 for details about the ROMON bit. PP7 / PWM7 — Port P I/O Pin 7 PP7 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 7 output. PP6 / PWM6 — Port P I/O Pin 6 PP6 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 6 output. PP5 / PWM5 — Port P I/O Pin 5 PP5 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 5 output. PP4 / PWM4 — Port P I/O Pin 4 PP4 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 4 output. PP3 / PWM3 — Port P I/O Pin 3 PP3 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 3 output. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions PP2 / PWM2 — Port P I/O Pin 2 PP2 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 2 output. PP1 / PWM1 — Port P I/O Pin 1 PP1 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 1 output. PS7 / SS — Port S I/O Pin 7 PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface. PS6 / SCK — Port S I/O Pin 6 PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface. PS5 / MOSI — Port S I/O Pin 5 PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface. PS4 / MISO — Port S I/O Pin 4 PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface. PS3 / TXD1 — Port S I/O Pin 3 PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1). PS2 / RXD1 — Port S I/O Pin 2 PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1). PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0). MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family PP0 / PWM0 — Port P I/O Pin 0 PP0 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 0 output. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Description PS0 / RXD0 — Port S I/O Pin 0 PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0). PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT). Pin Function IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Pin Pin Name Powered Number by PT2 PT3 PT4 PT5 PT6 PT7 VDDX VDDX VDDX VDDX VDDX VDDX 1 2 3 4 5 6 Description Capture Timer Channel MODC/TAGHI/BKGD / SI BKGD VDDX 7 Pseudo_open_drain communication pin for the background debug mode. At the rising edge on RESET, the state of this pin activates the BDM (when BKGD = 1). When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue. Serial clock pin when FBDM is in SPI mode. Serial out data pin when FBDM is in SPI mode. 2.5V core supply SPIMODE/SCKBDM SO SPIMODE SO VDD1 VSS1 VDDX VDDX VDD1 VSS1 VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX 8 9 10 11 12 13 14 15 16 17 18 19 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 Pulse Width Modulator channel outputs MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Table 13 MC9S12T64 Signal Description Summary Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Table 13 MC9S12T64 Signal Description Summary (Continued) Pin Function ADDR0 / DATA0 ADDR1 / DATA1 ADDR2 / DATA2 ADDR3 / DATA3 ADDR4 / DATA4 ADDR5 / DATA5 ADDR6 / DATA6 ADDR7 / DATA7 RESET EXTAL XTAL Pin Pin Name Powered Number by PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 RESET EXTAL XTAL VSSPLL XFC VDDPLL VDDR VSSR ECS/ROMONE PK7 VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDPLL VDDPLL – VDDPLL – VDDR VSSR VDDR 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 An active low bidirectional control signal, RESET acts as an input to initialize the MCU to a known start-up state, and an output when COP or clock monitor or LVD causes a reset. Crystal driver and external clock input pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 2.5V PLL ground External PLL Filter Capacitor 2.5V PLL supply 5V Voltage Regulator and I/O Supply 5V Voltage Regulator and I/O Ground Emulation Chip select/ROMONE pin shares function with general-purpose I/O port. The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization. Because it is level sensitive, it can be connected to a multiple-source wired-OR network. Maskable interrupt request input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (IRQCR register). Indicates direction of data on expansion bus. Shares function with general-purpose I/O. Read/write in expanded modes. Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. Pin function TAGLO used in instruction low byte tagging. E Clock is the output connection for the external bus clock. ECLK is used as a timing reference and for address demultiplexing. External bus pins share function with general-purpose I/O port B. In single chip modes, the pins can be used for general-purpose I/O. In expanded modes, the pins are used for the external address and data buses. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Description Freescale Semiconductor, Inc... XIRQ PE0 VDDR 37 IRQ PE1 VDDR 38 R/W PE2 VDDR 39 LSTRB / TAGLO PE3 VDDR 40 ECLK PE4 VDDR 41 MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Table 13 MC9S12T64 Signal Description Summary (Continued) Pin Function MODA / IPIPE0 MODB / IPIPE1 Pin Pin Name Powered Number by PE5 PE6 VDDR VDDR 42 43 Description State of mode select pins during reset determine the initial operating mode of the MCU. After reset, MODB and MODA can be configured as instruction queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins. No Access. Indicates free cycles in expanded mode. Selects also Colpitts oscillator or Pierce oscillator/external clock during reset. Can be used as general purpose I/O pin. NOACC / XCLKS PE7 VDDR 44 ADDR8 / DATA8 / DATA0 ADDR9 / DATA9 / DATA1 ADDR10 / DATA10 / DATA2 ADDR11 / DATA11 / DATA3 ADDR12 / DATA12 / DATA4 PA0 PA1 PA2 PA3 PA4 VDD2 VSS2 VDDR VDDR VDDR VDDR VDDR VDD2 VSS2 VDDR VDDR VDDR – VDDA VDDA – VDDA VDDA VDDA VDDA VDDA VDDA VDDA 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 5.0V supply analog to digital converter analog to digital converter reference high analog to digital converter reference low ground analog to digital converter A/D Converter channel 0 A/D Converter channel 1 A/D Converter channel 2 A/D Converter channel 3 A/D Converter channel 4 A/D Converter channel 5 A/D Converter channel 6 2.5V core supply External bus pins share function with general-purpose I/O ports A. In single chip modes, the pins can be used for general-purpose I/O. In expanded modes, the pins are used for the external buses. External bus pins share function with general-purpose I/O ports A. In single chip modes, the pins can be used for general-purpose I/O. In expanded modes, the pins are used for the external buses. ADDR13 / DATA13 / DATA5 ADDR14 / DATA14 / DATA6 ADDR15 / DATA15 / DATA7 PA5 PA6 PA7 VDDA VRH VRL VSSA AN0 AN1 AN2 AN3 AN4 AN5 AN6 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Table 13 MC9S12T64 Signal Description Summary (Continued) Pin Function AN7 / ETRIG RxD0 TxD0 RxD1 TxD1 MISO Pin Pin Name Powered Number by PAD7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 VREGEN VSSX VDDX TEST_VPP IOC0 IOC1 TEST PT0 PT1 VDDA VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VSSX VDDX VDDX VDDX VDDX 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Description A/D Converter channel 7, or an external trigger for the ATD conversion SCI0 receive pin SCI0 transmit pin SCI1 receive pin SCI1 transmit pin Master out/slave in pin for serial peripheral interface Serial clock for serial peripheral interface system Slave select output for SPI master mode, input for slave mode or master mode. Internal Voltage Regulator Enable 5V I/O supply and Ground Configures the device for various test modes including SCAN testing. Also the programming voltage input for NVMs during factory test. This pin must be tied to ground in all applications. Capture Timer Channel Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Master in/slave out pin for serial peripheral interface Freescale Semiconductor, Inc... MOSI SCK SS VREGEN MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Port Signals The MC9S12T64 incorporates seven ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O. In addition to the pins described below, each port consists of a data register which can be read and written at any time, and, with the exception of port AD and PE[1:0], a data direction register which controls the direction of each pin. After reset all general purpose I/O pins are configured as input. Port A Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general purpose I/O. Data Direction Register A (DDRA) determines the primary direction of each pin. DDRA also determines the source of data for a read of PORTA. Register DDRA determines whether each port A pin is an input or output. DDRA is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRA makes the corresponding bit in port A an output; clearing a bit in DDRA makes the corresponding bit in port A an input. The default reset state of DDRA is all zeroes. This register is not in the on-chip map in expanded and peripheral modes. Port B Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7 through D0 respectively. When this port is not used for external addresses, such as in single-chip mode, these pins can be used as general purpose I/O. Data Direction Register B (DDRB) determines the primary direction of each pin. DDRB also determines the source of data for a read of PORTB. Register DDRB determines whether each port B pin is an input or output. DDRB is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRB makes the corresponding bit in port B MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Description Port Signals an output; clearing a bit in DDRB makes the corresponding bit in port B an input. The default reset state of DDRB is all zeroes. This register is not in the on-chip map in expanded and peripheral modes. Port E The XCLKS input selects between Colpitts oscillator or Pierce oscillator/an external clock configuration. Some of these pins have software selectable pullups (NOACC, ECLK, LSTRB, R/W, IRQ and XIRQ). A single control bit enables the pullups for all of these pins when they are configured as inputs. This register is not in the on-chip map in peripheral mode or in expanded modes when the EME bit is set. Port K This port is associated with the internal memory emulation pin. When the port is not enabled to emulate the internal memory, the port pin is used as general-purpose I/O. When input, this pin can be selected to be high impedance or pulled up, based upon the state of the PUPKE bit in the PUCR register. Register DDRK determines whether port K pin is an input or output when configured as general-purpose I/O. DDRK is not in the address map during expanded and peripheral mode operation with EMK set. Setting a bit in DDRK makes the corresponding bit in port K an output; clearing MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Port E is associated with external bus control signals and interrupt inputs. These include mode select (PE7/NOACC/XCLKS, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0), E clock, size (LSTRB/TAGLO), read / write (R/W), IRQ, and XIRQ. When the associated pin is not used for one of these specific functions, the pin can be used as general purpose I/O with the exception of IRQ and XIRQ. The Port E Assignment Register (PEAR) selects the function of each pin and DDRE determines whether each pin is an input or output when it is configured to be general purpose I/O. DDRE also determines the source of data for a read of PORTE. Freescale Semiconductor, Inc. Pinout and Signal Description a bit in DDRK makes the corresponding bit in port K an input. The default reset state of DDRK is all zeroes. This register is not in the map in peripheral mode or in expanded modes while the EMK bit in the MODE register is set. NOTE: The ports A, B, E, K, P, S, T can be configured in a very flexible way. For a full and detailed overview refer to Section Port Integration Module (PIM). Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... AD PORT This port is an analog input interface to the analog-to-digital subsystem. The digital function of the ports must explicitly be enabled on per pin basis using a control register in the ADC module. When the port data registers are read, they contain the digital levels appearing on the input pins at the time of the read. Input pins with signal potentials not meeting VIL or VIH specifications will have an indeterminate value. Use of any AD port pin except ETRIG for digital input does not preclude the use of any other port pin for analog input. Note that the digital/analog multiplexing function is performed in the input pad. The port registers are connected to the input pads through tristate buffers. These buffers are only activated when the port is configured as digital pin so that analog signal potentials on the input pins will not cause the buffers to draw excess supply current. Port S for SCI0, SCI1 and SPI There are two identical SCI ports. Each SCI module uses two external pins. The RxD0, RxD1 and TxD0, TxD1pins share general purpose port SCI P[3:0]. TxD0, TxD1 are available for general-purpose I/O when it is not configured for transmitter operation. RxD0, RxD1 are available for general-purpose I/O when it is not configured for receiver operation. The SPI module uses four external pins. SS, SCK, MOSI, and MISO pins share general purpose port PS[7:4]. Port T for Timer Port The timer module has eight external pins: PT[7:0]_IOC[7:0], for input capture and output compare functions. Two of the pins are also the pulse MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Port Signals accumulator inputs. All eight pins are available for general-purpose I/O when not configured for timer functions. Port P for PWM The PWM module has a total of 8 external pins on which the pulse width modulated waveforms are output. The 8 PWM outputs are multiplexed on the PP[7:0] pins. . Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Table 14 MC9S12T64 Port A, B, E, K, T, S, P Description Summary Port Name PE[7:0] PB[7:0] Data Direction Register PE[1:0] In PE[7:2] In/Out DDRE In/Out DDRB In/Out DDRA In/Out DDRK In/Out DDRT In/Out DDRS In/Out DDRP Description Mode selection, bus control signals and interrupt service request signals; or general-purpose I/O. Port A and port B pins are used for address and data in expanded modes. The port data registers are not in the address map during expanded and peripheral mode operation. When in the map, port A and port B can be read or written any time. DDRA and DDRB are not in the address map in expanded or peripheral modes. Emulation chip select signal or general-purpose I/O. Enhanced Capture Timer signals; or general-purpose I/O. SPI and SCI signals; or general-purpose I/O. PWM signals; or general-purpose I/O. PA[7:0] PK7 PT[7:0] PS[7:0] PP[7:0] Port Pull-Up Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced drive causes a slight increase in transition time depending on loading and should be used only for ports which have a light loading. Table 15 summarizes the port pull-up default status and controls. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout and Signal Description Table 15 Port A, B, E, K, AD Pull-Up, Pull-Down and Reduced Drive Summary Port Name Port A Port B Port E: Resistive Input Loads Pull-up Pull-up Enable Bit Register (Address) PUCR ($000C) PUCR ($000C) PUCR ($000C) — PUCR ($000C) Bit Name PUPA PUPB Reset State Disabled Disabled Reduced Drive Control Bit Register Reset Bit Name (Address) State RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) RDRIV ($000D) — RDPA RDPB Full drive Full drive Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PE7, PE[4:0] PE[6:5] Port K7 Port AD[7:0] Pull-up Pull-down (1) Pull-up None PUPE — PUPKE Enabled Enabled Enabled RDPE RDPE RDPK Full drive Full drive Full drive 1. Pull-down is only active when RESET is low. MC9S12T64Revision 1.1.1 Pinout and Signal Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Configuration Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Modules Variabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 MCU Variabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Introduction This section describes the variabilities of the modules that are present at the MCU level and how they are connected. Modules Variabilities MMC Table 16 MMC Module Variable I/O Signals Signal Name reg_sw0 ram_sw2:0 eep_sw1:0 rom_sw1:0 pag_sw1:0 I/O I I I I I Configuration Description Register Block Size set to 1K bytes RAM Memory Size set to 2K bytes CALRAM Size set to 2K bytes ROM Mapping Select set to 64K bytes 64K bytes on-chip / 0K bytes off-chip space Connected to 0 000 01 11 11 The information is also readable by the MCU at address $1C, $1D (MEMSIZ0 and MEMSIZ1) MC9S12T64Revision 1.1.1 System Configuration For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Configuration MCU Variabilities Part ID Register Assignments The PARTID register is located in the IPBI (IP-Bus interface) at address $__1A,$__1B. It contains a unique part ID for each revision of the chip. Table 17 contains the assigned part ID numbers. Table 17 Assigned Part ID Numbers Freescale Semiconductor, Inc... Part Number MC9S12T64 Mask Set Number L42M PARTID (1) $422X 1. The coding is as follows: Bit 15-12: Major Family identifier Bit 11-8: Minor Family identifier Bit 7-4: Major mask revision number including FAB transfers Bit 3-0: Minor - non full - mask set revisions (Motorola use only for production control. This field may be changed. User program should not refer this field as an identification number.) Part ID Register This register is used to designate the part ID. Each revision of the chip will have a unique value in the contents of this register Read anytime. Write never. . PARTIDH — Part ID Register High Address Offset: $001A (1) Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Refer to Table 17 = Unimplemented 1. Register Address = Base Address (INITRG) + Address Offset MC9S12T64Revision 1.1.1 System Configuration For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. System Configuration System Clock Description PARTIDL — Part ID Register High Address Offset: $001B (1) Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: ID7 ID6 ID5 ID4 ID3 (2) ID2 (2) ID1 (2) ID0 (2) Refer to Table 17 = Unimplemented — — — — 1. Register Address = Base Address (INITRG) + Address Offset Freescale Semiconductor, Inc... 2. Motorola use only for production control. This field may be changed. User program should not refer to this field as an identification number. System Clock Description The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 13 shows the clock connections from the CRG to all modules. The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the setting of the respective configuration bits. For example, a WAIT(SYSWAI) gating condition states that when the SYSWAI bit is set, the correspondent gate will be disabled during WAIT mode. Consult the CRG section in page 271 for details on clock generation and clock enabling conditions. Table 18 summarizes the enabling conditions of specific modules according to the MCU mode of operation. All modules listed in Table 18 cease operation when the MCU enters STOP mode. MC9S12T64Revision 1.1.1 System Configuration For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. System Configuration WAIT(CWAI,SYSWAI), STOP Core Clock S12_CORE 1/2 FBDM WAIT(SYSWAI), STOP Flash RAM EXTAL Oscillator Clock CRG XTAL Bus Clock CALRAM ECT ATD WAIT(SYSWAI), STOP PWM SCI0, SCI1 Gate Condition SPI PIM = Clock Gate LVD Figure 13 Clock Connections MC9S12T64Revision 1.1.1 System Configuration For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Configuration System Clock Description Table 18 Module Availability in WAIT and RUN Modes Module Name HCS12 Core Flash CALRAM SRAM PIM Wait Mode(1) (Disable Bit) Always Enabled Always Enabled Always Enabled Always Enabled Always Enabled PSWAI (PWMCTL Register) TSWAIT (TSCR1 Register) AWAI (ATDCTL2 Register) SPISWAI (SPICR2 Register) Disabled SCISWAI (SCIxCR1 Register) Run Mode (Enable Bit) Always Enabled Always Enabled Always Enabled Always Enabled Always Enabled Always Enabled(2) Always Enabled Always Enabled(2) SPE (SPICR1 Register) LVDE (LVDCR Register) Always Enabled Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PWM ECT ATD SPI LVD SCI0, SCI1 1. Assuming all system clocks are running during WAIT mode (SYSWAI=0 in CLKSEL register - see page 284) 2. Low power options available. See the correspondent module section for details MC9S12T64Revision 1.1.1 System Configuration For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... System Configuration MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. System Configuration For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Registers Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Register Block The register block can be mapped to any 2K byte boundary within the first 32K byte of the standard 64K byte address space by manipulating bits REG[14:11] in the INITRG register. INITRG establishes the upper five bits of the register block’s 16-bit address. The register block occupies 1K byte. Default addressing (after reset) is indicated in the table below. Non-user Registers Non-user registers are divided in three categories: Reserved, Unimplemented and Reserved for Factory Test. A detailed description follows below; Reserved registers return logic zero when read. Writes to these registers have no effect. Unimplemented registers return unpredictable values when read. Writes to these registers have no effect. Reserved for Factory Test registers return unpredictable values when read. Writes to these registers have no effect in Normal modes. Writing to these registers in Special modes might result in unpredictable MCU behavior. Reserved Registers Unimplemented Registers Reserved for Factory Test Registers MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map Addre ss $0000 $0001 $0002 $0003 Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 0 0 0 0 6 6 0 MODB 0 0 0 0 Bit 5 5 5 5 5 0 0 0 0 5 5 PIPOE MODA 0 0 0 0 Bit 4 4 4 4 4 0 0 0 0 4 4 NECLK 0 PUPEE RDPE 0 0 Bit 3 3 3 3 3 0 0 0 0 3 3 LSTRE IVIS 0 0 0 0 Bit 2 2 2 2 2 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 Bit 1 1 1 1 1 0 0 0 0 Bit 1 0 0 EMK PUPBE RDPB 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0 0 0 MEBI Bit 0 0 0 EME PUPAE RDPA ESTR 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e Freescale Semiconductor, Inc... $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $0010 $0011 $0012 $0013 Name INITRM INITRG INITCRM MISC Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved for Factory Test Reserved Reserved PARTIDH PARTIDL MEMSIZ0 MEMSIZ1 IRQCR HPRIO Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 RAM15 0 Bit 6 RAM14 REG14 Bit 5 RAM13 REG13 Bit 4 RAM12 REG12 Bit 3 RAM11 REG11 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 RAMHAL 0 CRAMON MMC Modul e CRAM15 CRAM14 CRAM13 CRAM12 CRAM11 0 0 0 0 EXSTR1 EXSTR0 ROMHM ROMON $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F Reads to this register return unpredictable values. Reads to this register return unpredictable values. Reads to this register return unpredictable values. Reads to this register return unpredictable values. 0 0 ID15 ID7 reg_sw0 0 0 ID14 ID6 0 0 0 ID13 ID5 0 0 ID12 ID4 0 0 ID11 ID3 0 0 0 PSEL3 0 0 ID10 ID2 0 0 ID9 ID1 0 0 ID8 ID0 Peripheral eep_sw1 eep_sw0 0 0 PSEL5 ram_sw2 ram_sw1 ram_sw0 MMC 0 0 PSEL2 rom_sw1 rom_sw0 IRQE PSEL7 0 0 PSEL4 pag_sw1 pag_sw0 0 PSEL1 IRQEN PSEL6 0 MEBI 0 MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $0020 $0021 $0022 $0023 Name GPR0 GPR1 GPR2 GPR3 GPR4 GPR5 GPR6 GPR7 BKPCT0 BKPCT1 BKP0X BKP0H BKP0L BKP1X BKP1H BKP1L PPAGE Reserved PORTK DDRK Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Modul e $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Bit 7 6 5 4 3 2 1 0 Write: Read: Bit 7 6 5 4 3 2 1 0 Write: Read: Bit 7 6 5 4 3 2 1 0 Write: Read: Bit 7 6 5 4 3 2 1 0 Write: Read: Bit 7 6 5 4 3 2 1 0 Write: Read: Bit 7 6 5 4 3 2 1 0 Write: Read: Bit 7 6 5 4 3 2 1 0 Write: Read Bit 7 6 5 4 3 2 1 0 Write: Read: 0 0 0 0 BKEN BKFULL BKBDM BKTAG Write: Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Write: Read: 0 0 0 0 0 0 0 0 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: General Purpose Registers Freescale Semiconductor, Inc... BKP MMC MEBI Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $0034 $0035 $0036 $0037 Name SYNR REFDV Reserved for Factory Test CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL Reserved for Factory Test Reserved for Factory Test ARMCOP Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Modul e $0038 $0039 $003A $003B $003C $003D $003E $003F MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 Write: Read: 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 Write: Read: Reads to this register return unpredictable values. Write: Read: 0 LOCK TRACK SCM PORLVD RTIF LOCKIF SCMIF RF Write: Read: 0 0 0 0 0 RTIE LOCKIE SCMIE Write: Read: PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI Write: Read: 0 CME PLLON AUTO ACQ PRE PCE SCME Write: Read: 0 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 Write: Read: 0 0 0 WCOP RSBCK CR2 CR1 CR0 Write: Read: Reads to this register return unpredictable values. Write: Read: Reads to this register return unpredictable values. Write: Read: 0 0 0 0 0 0 0 0 Write: Bit 7 6 5 4 3 2 1 Bit 0 CRG Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $0040 $0041 $0042 $0043 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 C5F 0 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 C4F 0 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 0 TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 Enhanced Capture Timer Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e Freescale Semiconductor, Inc... $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $0050 $0051 $0052 $0053 Name TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 Bit 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 Bit 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 Bit 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 Bit 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 Bit 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Enhanced Capture Timer Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e Freescale Semiconductor, Inc... $0054 $0055 $0056 $0057 $0058 $0059 $005A $005B $005C $005D $005E $005F MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $0060 $0061 $0062 $0063 Name PACTL PAFLG PACN3 (hi) PACN2 (lo) PACN1 (hi) PACN0 (lo) MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved Reserved for Factory Test Reserved Reserved Bit 7 Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: MCZI Write: Read: MCZF Write: Read: 0 Write: Read: 0 Write: Read: NOVW7 Write: Read: SH37 Write: Read: 0 Write: Read: Write: Read: 0 Write: Read: 0 Write: Bit 6 PAEN 0 6 6 6 6 MODMC 0 0 0 NOVW6 SH26 0 Bit 5 PAMOD 0 5 5 5 5 RDMCL 0 0 0 NOVW5 SH15 0 Bit 4 PEDGE 0 4 4 4 4 0 ICLAT 0 0 0 NOVW4 SH04 0 Bit 3 CLK1 0 3 3 3 3 0 FLMC POLF3 PA3EN 0 NOVW3 TFMOD 0 Bit 2 CLK0 0 2 2 2 2 MCEN POLF2 PA2EN 0 NOVW2 PACMX 0 Bit 1 PAOVI PAOVF 1 1 1 1 MCPR1 POLF1 PA1EN DLY1 NOVW1 BUFEN 0 Bit 0 PAI PAIF Bit 0 Bit 0 Bit 0 Bit 0 Enhanced Capture Timer MCPR0 POLF0 PA0EN DLY0 NOVW0 LATQ 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e Freescale Semiconductor, Inc... $0064 $0065 $0066 $0067 $0068 $0069 $006A $006B $006C $006D $006E $006F Reads to this register return unpredictable values. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $0070 $0071 $0072 $0073 Name PBCTL PBFLG PA3H PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) TC1H (hi) TC1H (lo) TC2H (hi) TC2H (lo) TC3H (hi) TC3H (lo) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 0 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 PBEN 0 6 6 6 6 14 6 14 6 14 6 14 6 14 6 Bit 5 0 0 5 5 5 5 13 5 13 5 13 5 13 5 13 5 Bit 4 0 0 4 4 4 4 12 4 12 4 12 4 12 4 12 4 Bit 3 0 0 3 3 3 3 11 3 11 3 11 3 11 3 11 3 Bit 2 0 0 2 2 2 2 10 2 10 2 10 2 10 2 10 2 Bit 1 PBOVI PBOVF 1 1 1 1 9 1 9 1 9 1 9 1 9 1 Bit 0 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Enhanced Capture Timer Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e Freescale Semiconductor, Inc... $0074 $0075 $0076 $0077 $0078 $0079 $007A $007B $007C $007D $007E $007F MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $0080 $081 $082 $0083 Name Reserved for Factory Test Reserved for Factory Test ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Modul e $0084 $0085 $0086 PRS0 CA CC0 $0087 Unimplemented $0088 $0089 Reserved for Factory Test ATDTEST1 SC $008A Unimplemented $008B ATDSTAT1 CCF0 $008C Unimplemented $008D ATDDIEN IEN0 $008E Unimplemented $008F PORTAD PTAD0 MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: Reads to this register return unpredictable values. Write: Read: Reads to this register return unpredictable values. Write: Read: ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE Write: Read: 0 S8C S4C S2C S1C FIFO FRZ1 Write: Read: SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 Write: Read: 0 DJM DSGN SCAN MULT CC CB Write: Read: SCF 0 ETORF FIFOR 0 CC2 CC1 Write: Read: Reads to this register return unpredictable values. Write: Read: Reads to this register return unpredictable values. Write: Read: Reads to these bits return unpredictable values. Write: Read: Reads to this register return unpredictable values. Write: Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 Write: Read: Reads to this register return unpredictable values. Write: Read: IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 Write: Read: Reads to this register return unpredictable values. Write: Read: PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 Write: ASCIF FRZ0 ATD Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $0090 $0091 $0092 $0093 Name ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 Bit 4 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 Bit 3 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 Bit 2 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 Bit 1 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 Bit 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 ATD Bit8 0 Bit8 0 Bit8 0 Bit8 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e Freescale Semiconductor, Inc... $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $00A0 $00A1 $00A2 $00A3 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL Reserved for Factory Test Reserved for Factory Test PWMSCLA PWMSCLB Reserved for Factory Test Reserved for Factory Test PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 PWME7 PPOL7 PCLK7 0 CAE7 CON67 Bit 6 PWME6 PPOL6 PCLKL6 PCKB2 CAE6 CON45 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e Freescale Semiconductor, Inc... $00A4 $00A5 $00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00AE $00AF Reads to this register return unpredictable values. Reads to this register return unpredictable values. PWM Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Reads to this register return unpredictable values. Reads to this register return unpredictable values. Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 6 0 6 0 6 0 6 0 5 0 5 0 5 0 5 0 4 0 4 0 4 0 4 0 3 0 3 0 3 0 3 0 2 0 2 0 2 0 2 0 1 0 1 0 1 0 1 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $00B0 $00B1 $00B2 $00B3 Name PWMCNT4 PWMCNT5 PWMCNT6 PWMCNT7 PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 Bit 2 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 Bit 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 PWM Modul e $00B4 $00B5 $00B6 $00B7 $00B8 $00B9 $00BA $00BB $00BC $00BD $00BE $00BF MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $00C0 $00C1 $00C2 $00C3 Name PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 PWMIF Bit 6 6 6 6 6 Bit 5 5 5 5 5 Bit 4 4 4 4 4 Bit 3 3 3 3 3 0 Bit 2 2 2 2 2 PWM7IN Bit 1 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Modul e PWM Freescale Semiconductor, Inc... $00C4 $00C5 $00C6 $00C7 $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Read: 0 Write: Read: 0 0 Write: Read: 0 0 Write: Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 0 PWMIE PWMRST PWMLVL RT 0 0 0 0 0 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 0 0 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 PWM7IN PWM7EN L A 0 0 0 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 0 0 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0 0 0 0 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 0 0 0 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 SCI0 MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $00D0 $00D1 $00D2 $00D3 Name SCI1BDH SCI1BDL SCI1CR1 SCI1CR2 SCI1SR1 SCI1SR2 SCI1DRH SCI1DRL SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved Reserved Bit 7 Bit 6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 MSTR Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 CPOL Bit 2 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0 LSBFE SPC0 SPR0 0 SPI 0 Bit0 0 0 SCI1 Modul e $00D4 $00D5 $00D6 $00D7 $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0 MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Read: SPIE SPE Write: Read: 0 0 Write: Read: 0 SPPR2 Write: Read: SPIF 0 Write: Read: 0 0 Write: Read: Bit7 6 Write: Read: 0 0 Write: Read: 0 0 Write: Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $00E0 $00E1 $00E2 $00E3 Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 PTT7 PTIT7 DDRT7 RDRT7 PERT7 PPST7 0 0 PTS7 PTIS7 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 Bit 6 PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6 0 0 PTS6 PTIS6 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 Bit 5 PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5 0 0 PTS5 PTIS5 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 Bit 4 PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4 0 0 PTS4 PTIS4 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 Bit 3 PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3 0 0 PTS3 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 Bit 2 PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2 0 0 PTS2 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 Bit 1 PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1 0 0 PTS1 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 Bit 0 PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0 0 0 PTS0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 Port S Port T Modul e $00E4 $00E5 $00E6 $00E7 $00E8 $00E9 $00EA $00EB $00EC $00ED $00EE $00EF MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Registers Register Block Table 19 MC9S12T64 Register Map (Continued) Addre ss $00F0 $00F1 $00F2 $00F3 Name PTP PTIP DDRP RDRP PERP PPSP Reserved Reserved LVDCR Reserved LVDSR Reserved CALCFG Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 PTP7 PTIP7 DDRP7 RDRP7 PERP7 PPSP7 0 0 LVDE 0 LVDF 0 FSUM 0 0 0 Bit 6 PTP6 PTIP6 DDRP7 RDRP6 PERP6 PPSP6 0 0 LVDRE 0 0 0 0 0 0 0 Bit 5 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 0 0 0 0 0 0 0 0 0 0 Bit 4 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 0 0 0 0 0 0 0 0 0 0 Bit 3 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 0 0 0 0 0 0 0 0 0 0 Bit 2 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 0 0 0 0 0 0 0 0 0 0 Bit 1 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 0 0 0 0 0 0 0 0 0 0 Bit 0 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 0 0 0 0 LVD 0 0 0 0 0 0 CALRAM Port P Modul e $00F4 $00F5 $00F6 $00F7 $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Registers Table 19 MC9S12T64 Register Map (Continued) Addre ss $0100 Name FCLKDIV Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Modul e MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 Write: Read: KEYEN NV6 NV5 NV4 NV3 NV2 SEC1 SEC0 $0101 FSEC Write: Read: Reads to this register return unpredictable values in normal modes. $0102 FTSTMOD Write: Read: 0 0 0 0 $0103 FCNFG CBEIE CCIE KEYACC BKSEL0 Write: Read: $0104 FPROT FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 Write: Read: CCIF 0 BLANK 0 0 $0105 FSTAT CBEIF PVIOL ACCERR Write: Read: 0 0 0 0 $0106 FCMD CMDB6 CMDB5 CMDB2 CMDB0 Write: Reads to this register return unpredictable values. Reserved for Read: $0107 Factory Test Write: Read: 0 $0108 FADDRHI AB15 AB14 AB13 AB12 AB11 AB10 AB9 Write: Read: $0109 FADDRLO AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 Write: Read: $010A FDATAHI D15 D14 D13 D12 D11 D10 D9 D8 Write: Read: $010B FDATALO D7 D6 D5 D4 D3 D2 D1 D0 Write: Read: 0 0 0 0 0 0 0 0 $010C Reserved Write: Read: 0 0 0 0 0 0 0 0 $010D Reserved Write: Read: 0 0 0 0 0 0 0 0 $010E Reserved Write: Read: 0 0 0 0 0 0 0 0 $010F Reserved Write: Read: Reads to this register return unpredictable values. $0110 Unimplemented $03FF Write: Freescale Semiconductor, Inc... Flash Control Freescale Semiconductor, Inc. Registers General Purpose Registers General Purpose Registers General Purpose Registers (GPR[0-7]) are the register spaces reside in the first 256 bytes of the memory map (when register block is mapped at $0000) which can be used as the storage spaces by the user program. GPR0-7 — General Purpose Registers Address Offset: $0020 – $0027 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Bit 7 Read: Write: Reset: 0 6 5 4 GPR0–7 3 2 1 Bit 0 0 0 0 0 0 0 0 = Reserved or unimplemented Read: Anytime Write: Anytime These registers will reset to 0 and can be written and read any time. MC9S12T64Revision 1.1.1 Registers For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Registers MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Registers For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Operating Modes Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Secured Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Introduction Eight possible operating modes determine the operating configuration of the MC9S12T64. Each mode has an associated default memory map and external bus configuration. Operating Modes The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (refer to Table 20). The MODC, MODB, and MODA bits in the MODE register show current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Modes Table 20 Mode Selection Input BKGD & bit MODC 0 0 0 Input & bit MODB 0 0 1 1 0 0 1 1 Input & bit MODA 0 1 0 1 0 1 0 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is “allowed” in all other modes but a serial command is required to make BDM “active”. Emulation Expanded Narrow, BDM allowed Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Special Test (Expanded Wide) (1), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral (1); BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed Freescale Semiconductor, Inc... 0 1 1 1 1 1. This mode is intended for Motorola factory testing of the MCU. There are two basic types of operating modes: Normal modes — some registers and bits are protected against accidental changes. Special modes — allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. The four 8-bit Ports (A, B, E and K) associated with the MEBI sub-block can serve as general purpose I/O pins or alternatively as the address, data and control signals for a multiplexed expansion bus. Address and data are multiplexed on Ports A and B. The control pin functions are dependent on the operating mode and the control registers PEAR and MODE. The initial state of bits in the PEAR and MODE registers are also established during reset to configure various aspects of the expansion MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Modes Operating Modes bus. After the system is running, application software can access the PEAR and MODE registers to modify the expansion bus configuration. Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPUs condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pullup. Bit 0 of Port E is a general purpose input or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPUs condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pullup. The ESTR bit in the EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis. Normal Operating Modes These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated. There is no external expansion bus in this mode. All pins of Ports A, B and K are configured as general purpose I/O pins. Port E bits 1 and 0 are available as general purpose input only pins with internal pullups enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance inputs with internal pullups enabled. The pins associated with Port E bits 7, 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. The associated control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single chip mode does not change the operation of the associated Port E pins. Normal Single-Chip Mode MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK in the PEAR register. Typically, the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Normal Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pullup resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose I/O pins. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the special variation of this mode. The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications. The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Modes Operating Modes in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. Normal Expanded Narrow Mode This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. Since the PEAR register can only be written once in this mode, use care to set all bits to the desired states during the single allowed write. The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to “1” in this mode, the state of LSTRE is overridden and Port E bit 3 cannot be reconfigured as the LSTRB output. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. The PE2/R/W pin is initially configured as a general purpose input with a pullup but this pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Modes location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. Internal Visibility Internal visibility is available when the MCU is operating in expanded wide modes, special test mode or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register. If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external to prevent possible corruption of external devices. During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. Emulation Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between emulation modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes. MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes Operating Modes Emulation Expanded Narrow Mode Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0, and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 are associated with PA7, and address A0 and data D0 are associated with PB0. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between emulation modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes. MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS=1. Freescale Semiconductor, Inc. Operating Modes Special Operating Modes There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. When the MCU is reset in this mode, the background debug mode is enabled and “active”. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead, the active background debug mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the MCU to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pullups disabled; however, writing to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with pullups enabled. PE4/ECLK is configured as the E clock output in this mode. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. The associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in this mode does not change the operation of the associated Port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK in the PEAR register. Typically, the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. Special Single-Chip Mode NOTE: When the MCU starts in the special single chip mode, the INITCRM and PPAGE registers are overwritten by the secure BDM firmware. The CPU registers also overwritten by the firmware. These overwritten values are unknown and not guaranteed. MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes Operating Modes Special Test Mode This mode is intended for Motorola factory testing of the MCU. In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. Peripheral Mode This mode is intended for Motorola factory testing of the MCU. In this mode, the CPU is inactive and an external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions. MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Test Operating Mode There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip peripherals. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes MODE Register (MODE) Address Offset: $000B (1) Bit 7 Read: 6 5 4 3 2 1 Bit 0 0 MODC MODB 0 0 1 1 0 0 1 1 0 IVIS MODA 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 EMK(2) 0 1 0 1 0 0 0 0 EME 0 1 0 1 0 0 0 0 Special Single Chip Emulation Exp Nar Special Test Emulation Exp Wide Normal Single Chip Normal Exp Narrow Peripheral Normal Exp Wide Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Write: Reset: 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Reset: Reset: Reset: Reset: Reset: Reset: Reset: = Unimplemented 1. Register Address = Base Address (INITRG) + Address Offset 2. PK[6:0] pins are not bonded out. Read: anytime (provided this register in the map) Write: each bit has specific write conditions. The MODE register is used to establish the operating mode and other miscellaneous functions (i.e. internal visibility and emulation of Port E and K). In peripheral modes this register is not accessible but it is reset as shown to configure system features. Changes to bits in the MODE register are delayed one cycle after the write. This register is not in the on-chip map in emulation and peripheral modes. MODC, MODB, MODA — Mode Select bits These bits indicate the current operating mode. MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Modes Operating Modes If MODA=1, then MODC, MODB, MODA are write never. If MODC=MODA=0, then MODC, MODB, MODA are write anytime except that you cannot change to or from peripheral mode. If MODC=1, MODB=0 and MODA=0, then MODC is write never, MODB, MODA are write once, except that you cannot change to peripheral, special test, special single chip, or emulation modes. MODC 0 0 0 0 1 1 1 1 MODB 0 0 1 1 0 0 1 1 MODA 0 1 0 1 0 1 0 1 Mode Special Single Chip Emulation Exp Narrow Special Test Emulation Exp Wide Normal Single Chip Normal Expanded Narrow (3) Special Peripheral Normal Expanded Wide (3) MODx Write Capability MODC, B, A write anytime but not to 110(2) no write MODC, B, A write anytime but not to 110(2) no write MODC write never, MODB, A write once but not to 110 no write no write no write 1. No writes to the MOD bits are allowed while operating in a SECURED mode. 2. If you are in a special single chip or special test mode and you write to this register, changing to normal single chip mode, then one allowed write to this register remains even if you write to a special mode. If you write to normal expanded or emulation mode, then no writes remain. 3. The external bus can not be used for memory expansion purpose with external memory devices, since this MCU does not have the PIX[5:0]/XADDR[19:14] pins to indicate page number. IVIS — Internal Visibility (for both read and write accesses) This bit determines whether internal accesses generate a bus cycle that is visible on the external bus. Refer to the page 110 about Internal Visibility. Normal: write once Emulation: write never Special: write anytime MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Table 21 MODC, MODB, MODA Write Capability(1) Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes 1 = Internal bus operations are visible on external bus. 0 = No visibility of internal bus operations on external bus. NOTE: The program page window ($8000–$BFFF) may not be correctly monitored with this internal visibility function, since there are no indications of PPAGE (page index register) to the outside from the MCU. EMK — Emulate Port K Normal: write once Special: write anytime 1 = If in any expanded mode or special peripheral mode, PORTK and DDRK are removed from the memory map. 0 = PORTK and DDRK are in the memory map so Port K can be used for general purpose I/O. In single-chip modes, PORTK and DDRK are always in the map regardless of the state of this bit. In peripheral modes, PORTK and DDRK are never in the map regardless of the state of this bit. EME — Emulate Port E Normal and Emulation: write never Special: write anytime 1 = If in any expanded mode or special peripheral mode, PORTE and DDRE are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. 0 = PORTE and DDRE are in the memory map so Port E can be used for general purpose I/O. In single-chip modes, PORTE and DDRE are always in the map regardless of the state of this bit. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Emulation: write never Background Debug Mode Background debug mode (BDM) is an auxiliary operating mode that is used for system development. BDM is implemented in on-chip hardware MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Modes Secured Mode of Operation and provides a full set of debug operations. Some BDM commands can be executed while the CPU is operating normally. Other BDM commands are firmware based, and require the BDM firmware to be enabled and active for execution. In special single-chip mode, BDM is enabled and active immediately out of reset. BDM is available in all other operating modes, but must be enabled before it can be activated. BDM should not be used in special peripheral mode because of potential bus conflicts. Freescale Semiconductor, Inc... Once enabled, background debug mode can be made active by a serial command sent via the BKGD pin or execution of a CPU12 BGND instruction. While background debug mode is active, the CPU can interpret special debugging commands, and read and write CPU registers, peripheral registers, and locations in memory. While BDM is active, the CPU executes code located in a small on-chip ROM mapped to addresses $FF20 to $FFFF, and BDM control registers are accessible at addresses $FF00 to $FF06. The BDM ROM replaces the regular system vectors while BDM is active. While BDM is active, the user memory from $FF00 to $FFFF is not in the map except through serial BDM commands. Secured Mode of Operation The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • • • • Protection of the contents of FLASH, Protection of the contents of CALRAM, Operation in single-chip mode, Operation from external memory with internal FLASH and CALRAM disabled. The user must be reminded that part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Operating Modes contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a “back door” in the user’s program. An example of this is the user downloads a “key” through the SCI which allows access to a programming routine that updates parameters stored in Flash EEPROM. The security byte resides in a portion of the Flash array. Two bits are used for security. The state of the security bits and the resulting state of security are shown in Table 22. Note that there are three secured bit combinations and only one unsecured combination. The user can select any of the three combinations to secure the microcontroller. Table 22 : Security Bits sec1 0 0 1 1 sec0 0 1 0 1 secreq 1 (secured) 1 (secured) 0 (unsecured) 1 (secured) NOTE: When the MCU is in the secured state and in the special single chip mode, reading the CALRAM array returns $FFFF for any word accesses or $FF for any byte accesses. Check the Flash section for more details on the security configuration. CAUTION: MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Securing the Microcontroller Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. Freescale Semiconductor, Inc. Operating Modes Secured Mode of Operation Operation of the Secured Microcontroller Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and The CALRAM will be disabled. BDM operations will be blocked. Unsecuring the Microcontroller In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an external program in expanded mode. Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. MC9S12T64Revision 1.1.1 Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Executing from External Memory Freescale Semiconductor, Inc... Operating Modes MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Operating Modes For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Module Mapping Control (MMC) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Overview The Module Mapping Control (MMC) sub-block of the Core performs all mapping and select operations for the on-chip and external memory blocks. The MMC also handles mapping functions for the system peripheral blocks and provides a global peripheral select to be decoded by the Motorola I.P. Bus when the Core is addressing a portion of the peripheral register map space. All bus-related data flow and multiplexing for the Core is handled within the MMC as well. Finally, the MMC also contains logic to determine the state of system security. Features • Registers for mapping of address space for on-chip RAM, CALRAM, and Flash EEPROM memory blocks and associated registers Memory mapping control and selection based upon address decode and system operating mode MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com • Freescale Semiconductor, Inc. Module Mapping Control (MMC) • • • • • • Core Address Bus control Core Data Bus control and multiplexing Core Security state decoding Emulation Chip Select signal generation (ECS) Internal memory expansion Miscellaneous system control functions via the MISC register Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Block Diagram The block diagram of the MMC is shown in Figure 14 below. MMC secure bdm_unsecure Stop, Wait SECURITY mmc_secure ADDRESS DECODE Read & Write Enables Clocks, Reset Mode Information INTERNAL MEMORY EXPANSION REGISTERS Port K Interface memory space select(s) peripheral select EBI Alternate Address bus EBI Alternate Write data bus EBI Alternate Read data bus Core select (s) Alternate Address bus (BDM) CPU Address bus CPU Read Data bus CPU Write Data bus CPU Control BUS CONTROL Alternate Write data bus (BDM) Alternate Read data bus (BDM) Figure 14 Module Mapping Control Block Diagram MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Module Mapping Control (MMC) Register Map Register Map A summary of the registers associated with the MMC sub-block is shown in Figure 15 below. Detailed descriptions of the registers and bits are given in the subsections that follow. Register Name INITRM read write read write Bit 7 RAM15 0 6 RAM14 5 RAM13 4 RAM12 3 RAM11 2 0 1 0 Bit 0 RAMHAL 0 Address Offset $0010 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... INITRG REG14 REG13 REG12 REG11 0 0 $0011 INITCRM read CRAM15 write read write read write read write read write read write read write reg_sw0 0 CRAM14 0 CRAM13 0 CRAM12 0 CRAM11 0 0 CRAMON $0012 MISC EXSTR1 EXSTR0 ROMHM ROMON $0013 Reserved for Factory Test Reads to this register return unpredictable values. $0014 Reserved for Factory Test Reads to this register return unpredictable values. $0015 Reserved for Factory Test Reads to this register return unpredictable values. $0016 Reserved for Factory Test Reads to this register return unpredictable values. $0017 ram_sw0 MEMSIZ0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 $001C MEMSIZ1 read rom_sw1 write read write read write 0 rom_sw0 0 0 0 0 pag_sw1 pag_sw0 $001D PPAGE 0 PIX5 0 PIX4 0 PIX3 0 PIX2 0 PIX1 0 PIX0 0 $0030 Reserved 0 0 $0031 = Unimplemented X = Indeterminate Figure 15 Module Mapping Control Register Summary MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... NOTE: MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) Freescale Semiconductor, Inc. Register Address = Base Address (INITRG) + Address Offset Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Module Mapping Control (MMC) Register Descriptions Register Descriptions Initialization of Internal RAM Position Register (INITRM) The MC9S12T64 has 2K bytes of fully static RAM that is used for storing instructions, variables, and temporary data during program execution. After reset, RAM addressing begins at location $0800 but can be assigned to any 2k boundary within the standard 64K byte address space. Mapping of internal RAM is controlled by five bits in the INITRM register and the value written in RAMHAL is always ignored. Read: Anytime. Write: Write once in Normal and Emulation modes. Write anytime in Special modes. NOTE: Writes to this register take one cycle to go into effect. Reset: $09 (RAM located from $0800 – $0FFF) Address Offset: $0010 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: RAM15 0 RAM14 0 RAM13 0 RAM12 0 RAM11 1 0 0 0 0 RAMHAL 1 = Unimplemented RAM[15:11] — Internal RAM map position This register initializes the internal RAM position. The RAM15-RAM11 bits define the 2K page the RAM resides in. RAMHAL - RAM High-align This bit can be written and read, but is ignored in determining the RAM position. 1 = Don’t Care 0 = Don’t Care MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Module Mapping Control (MMC) Initialization of Register Block Position Register (INITRG) This register initializes the internal register block position. Mapping of internal registers is controlled by five bits in the INITRG register. After reset the 1K byte register block resides at location $0000 but can be reassigned to any 2K byte boundary within the first 32K byte of the 64K byte address space. Read: Anytime. Write: Write once in Normal and Emulation modes. Write anytime in Special modes. NOTE: Writes to this register take one cycle to go into effect. Reset to $00 (Registers located from $0000 to $03FF) Address Offset: $0011 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: 0 0 REG14 0 REG13 0 REG12 0 REG11 0 0 0 0 0 0 0 = Unimplemented REG[14:11] — Internal register map position These four bits in combination with the leading zero supplied by bit 7 of INITRG determine the upper five bits of the base address for the system’s internal registers (i.e. the minimum base address is $0000 and the maximum is $7FFF). MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Module Mapping Control (MMC) Register Descriptions Initialization of CALRAM Position Register (INITCRM) This register initializes the CALRAM position. Mapping of CALRAM is controlled by six bits in the INITCRM register. The MC9S12T64 has 2K bytes of CALRAM which is activated by the CRAMON bit in the INITCRM register. After reset CALRAM address space begins at location $1000 but can be mapped to any 2K byte boundary within the standard 64K byte address space. Read: Anytime. Write: Anytime. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... NOTE: Writes to this register take one cycle to go into effect. Reset: $11 (CALRAM located from $1000 – $17FF) Address Offset: $0012 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: CRAM15 0 CRAM14 0 CRAM13 0 CRAM12 1 CRAM11 0 0 0 0 0 CRAMON 1 = Unimplemented CRAM[15:11] — Internal CALRAM map position These bits specify the upper five bits of the 16-bit CALRAM address. Read or write anytime. CRAMON — internal CALRAM On (Enabled) This bit enables the CALRAM in the memory map. Read or write anytime. 1 = Place CALRAM in the memory map at the address selected by CRAM15–CRAM11. 0 = Removes the CALRAM from the map. MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Module Mapping Control (MMC) Miscellaneous System Control Register (MISC) Additional mapping and external resource controls are available. To use external resources the part must be operated in one of the expanded modes. Read: Anytime Write: Refer to each bit for individual write conditions. NOTE: Writes to this register take one cycle to go into effect. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Address Offset: $0013 Bit 7 6 5 4 3 2 1 Bit 0 Mode Read: Write: Reset: Reset: Reset: 0 0 0 0 EXSTR1 EXSTR0 ROMHM ROMON (1) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 Normal Expanded or Emulation Mode Peripheral or Single Chip Mode Special Test Mode 1 0 = Unimplemented 1. Determined by state of PK7 pin during reset. See Table 24. EXSTR1, EXSTR0 — External Access Stretch Write: Once in Normal and Emulation modes and anytime in Special modes This two bit field determines the amount of clock stretch on accesses to the external address space as shown in Table 23 below. In single chip and peripheral modes these bits have no meaning or effect. Table 23 EXSTR Stretch Bit Definition Stretch bit EXSTR1 0 0 1 1 Stretch bit EXSTR0 0 1 0 1 Number of E Clocks Stretched 0 1 2 3 MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Module Mapping Control (MMC) Register Descriptions ROMHM — Flash EEPROM only in second half of memory map Write: Once in Normal and Emulation modes and anytime in Special modes 1 = Disables direct access to the 32K byte Flash EEPROM in location $0000 – $7FFF in the memory map. In special modes, the physical location of this 32K byte Flash can still be accessed through the Program Page window. 0 = The 32K byte Pages $3D(61) and $3E (62) of fixed Flash EEPROM in location $0000 – $7FFF can be accessed. ROMON — Enable Flash EEPROM Write: Once in Normal and Emulation modes and anytime in Special modes This bit is used to enable the Flash EEPROM memory in the memory map. In Normal Expanded or Emulation modes, the reset state of this bit is determined the state of the PK7 pin (Port K) during reset. See Table 24. 1 = Enables the Flash EEPROM in the memory map. 0 = Disables the Flash EEPROM from the memory map. Table 24 State of ROMON bit after reset State of PK7 during reset PK7=0 State of ROMON bit after reset Normal Expanded mode Emulation mode 0 1 PK7=1 1 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Module Mapping Control (MMC) Memory Size Register Zero (MEMSIZ0) The bits in this register provide read visibility to the system physical memory space allocations defined at system integration. Table 16 (page 79) in the System Configuration section shows the values assigned to these bits at system integration. Read: Anytime Write: Writes have no effect Address Offset: $001C Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 0 0 0 1 0 0 0 0 = Unimplemented reg_sw0 - Allocated System Register Space eep_sw1:eep_sw0 - Allocated System CALRAM Memory Space ram_sw2:ram_sw0 - Allocated System RAM Memory Space MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Module Mapping Control (MMC) Register Descriptions Memory Size Register One (MEMSIZ1) The bits in this register provide read visibility to the system physical memory space and on-chip/off-chip partitioning allocations defined at system integration. Table 16 (page 79) in the System Configuration section shows the values assigned to these bits at system integration. Read: Anytime Write: Writes have no effect Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0 1 1 0 0 0 0 1 1 = Unimplemented rom_sw1:rom_sw0 - Allocated System Flash EEPROM or ROM Physical Memory Space pag_sw1:pag_sw0 - Allocated Off-Chip Flash EEPROM or ROM Memory Space MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Address Offset: $001D Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Module Mapping Control (MMC) Program Page Index Register (PPAGE) This register determines the 16KB active page viewed through the Program Page Window from $8000 – $BFFF. CALL and RTC instructions have a special single wire mechanism to read and write this register without using the address bus. Read: anytime. Write: Not writable in Normal and Emulation modes. Write anytime in Special modes. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Reset to $3C (Flash EEPROM Page $3C located from $8000 to $BFFF) Address Offset: $0030 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: 0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0 0 1 1 1 1 0 0 = Reserved PIX5 – PIX0 — Program Page Index Bits 5-0 These six page index bits are used to select which of the 64 Flash EEPROM array pages is to be accessed in the Program Page Window. The 64KB address space of MC9S12T64 is divided in the four 16KB pages with their correspondent PPAGE values listed in Table 25. CAUTION: Proper functionality of the MCU is not guaranteed when PPAGE values other than the ones specified at Table 25,are used. Proper operation in Normal modes is not guaranteed if PPAGE values other than $3C are used. Normal writes to this register take one cycle to go into effect. Writes to this register using the special single wire mechanism of the CALL and NOTE: MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Module Mapping Control (MMC) Functional Description RTC instructions will be complete before the end of the associated instruction. Table 25 Program space page index in special modes PIX5 1 1 1 PIX4 1 1 1 1 PIX3 1 1 1 1 PIX2 1 1 1 1 PIX1 0 0 1 1 PIX0 0 1 0 1 Program Space Selected 16K Flash EEPROM Page $3C 16K Flash EEPROM Page $3D 16K Flash EEPROM Page $3E 16K Flash EEPROM Page $3F Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 1 Functional Description The MMC sub-block performs four basic functions of the Core operation: bus control, address decoding and select signal generation, memory expansion, and security decoding for the system. Each aspect is described in the following subsections. Bus Control The MMC controls the address bus and data buses that interface the Core with the rest of the system. This includes the multiplexing of the input data buses to the Core onto the main CPU read data bus and control of data flow from the CPU to the output address and data buses of the Core. In addition, the MMC handles all CPU read data bus swapping operations. Address Decoding As data flows on the Core address bus, the MMC decodes the address information, determines whether the internal Core register or firmware space, the peripheral space or a memory register or array space is being addressed and generates the correct select signal. This decoding operation also interprets the mode of operation of the system and the state of the mapping control registers in order to generate the proper select. The MMC also generates the Emulation Chip Select (ECS) signal. MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Module Mapping Control (MMC) Select Priority Although internal resources such as control registers and on-chip memory have default addresses, each can be relocated by changing the default values in control registers. Normally, I/O addresses, control registers, vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not overlap. The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in Table 26 below. If two or more blocks share the same address space, only the select signal for the block with the highest priority will become active. An example of this is if the registers and the RAM are mapped to the same space, the registers will have priority over the RAM and the portion of RAM mapped in this shared space will not be accessible. The expansion windows have the lowest priority. This means that registers, vectors, and on-chip memory are always visible to a program regardless of the values in the page select registers. Table 26 Mapping Precedence Precedence Highest ... ... ... ... Lowest Resource BDM space (Internal) when BDM is active this 256 byte block of registers and ROM appear at $FF00 – $FFFF Register Space – 1K bytes fully blocked for registers RAM (internal) – 2K bytes CALRAM – 2K bytes On-Chip Flash EEPROM – 64K bytes Remaining external In expanded modes, the data registers and data directions registers for Ports A and B are removed from the on-chip memory map and become external accesses. If the EME bit in the MODE register is set, the data and data direction registers for Port E are also removed from the on-chip memory map and become external accesses. In emulation modes, if the EMK bit in the MODE register is set, the data and data direction registers for Port K are removed from the on-chip memory map and become external accesses. External Memory Accesses All address space not used by internal resources is by default external memory space in expanded modes. In MC9S12T64, internal memory resources have to be disabled so that external memory can be accessed. The Flash EEPROM can be disabled by clearing the ROMON MC9S12T64Revision 1.1.1 Module Mapping Control (MMC) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Module Mapping Control (MMC) Functional Description in the MISC register during reset. In particular, one can also disable access to the first half of the FLASH EEPROM (locations $0000 - $7FFF) by setting the ROMHM bit. Although the CALRAM can also be disabled, ultimately it is the enabling condition FLASH EEPROM that determines if access will be external or internal. This is true because the FLASH EEPROM covers all the MCU address space and has a selection priority only superior to external accesses (See Table 26). Table 27 summarizes the conditions necessary for an access to be internal/external in expanded modes. Freescale Semiconductor, Inc... Table 27 Access Type in Expanded Modes ROMON /ROMHM 1/0 MCU Address Range $0000–$FFFF $0000–$7FFF 1/1 $8000–$FFFF 0/x $0000–$FFFF Type of Access Normal Mode Internal External only if internal resources cannot be accessed Internal External only if internal resources cannot be accessed Special Mode Internal External only if internal resources cannot be accessed Internal (1) External only if internal resources cannot be accessed 1. Accesses to all Flash pages, even to the ones disabled ($3D,$3E) by ROMHM bit, are allowed through the Program Page Window ($8000 17 Bus Clock Cycles Any LVDF Keeps Previous Value Keeps Previous Value Keeps Previous Value Or Becomes “1” Becomes “1” Keeps Previous Value At Level VDDR > VLVRR VDDR ≤ VLVR VLVR < VDDR < VLVRR MC9S12T64Revision 1.1.1 Low-Voltage Detector (LVD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Low-Voltage Detector (LVD) Functional Description Functional Description Figure 21 shows the structure of the LVD module. The LVD enable bit (LVDE) in the LVD control register (LVDCR) is set out of power-on reset, enabling the LVD to monitor the VDDR voltage. The LVD monitors the voltage on the VDDR pin by means of the bandgap reference circuit and the comparator.The LVDF flag in the LVD status register (LVDSR) is set whenever the VDDR voltage falls to VLVR level and remains at or below that level for 17 or more consecutive bus clock cycles. Under such condition, the part is reset if the LVD reset enable bit (LVDRE) in LVDCR is logical 1. Once an LVD reset occurs, the MCU remains in reset until VDDR rises above the voltage VLVRR. An LVD reset also drives the RESET pin low to provide low-voltage protection to external peripheral devices. Polled LVD Operation In applications that can operate at VDDR levels below the VLVR level, software can monitor VDDR by polling the LVDF bit. In the control register, the LVDE bit must be at logic 1 to enable the LVD module, and the LVDRE bit must be at logic 0 to disable LVD resets. Forced Reset Operation In applications that require VDDR to remain above the VLVR level, enabling LVD resets allows the LVD module to reset the MCU when VDDR falls to the VLVR level and remains at or below that level.In the control register, LVDE and LVDRE bits must be at logic 1 to enable the LVD module and to enable LVD resets. False Reset Protections The LVD module has two false reset protections. 1. The LVD module contains a hysteresis circuit to reduce the possibility of false resets due to power supply noise. 2. The VDDR pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVD module to reset the MCU, VDDR must fall to the VLVR level and remains at or below that level for 17 or more consecutive bus clock cycles. VDDR must be above VLVRR for only one bus clock cycle to bring the MCU out MC9S12T64Revision 1.1.1 Low-Voltage Detector (LVD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... Interrupts Low-Voltage Detector (LVD) MC9S12T64Revision 1.1.1 of reset. Freescale Semiconductor, Inc. The LVD module does not generate interrupt requests. Low-Voltage Detector (LVD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Flash EEPROM 64K Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Flash Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Overview This section describes the Flash EEPROM module which is a 64k byte Flash (Non-Volatile) Memory. The Flash array is organized as 2 blocks of 32k bytes. Each block is organized as 512 rows of 64 bytes. The Flash block’s erase sector size is 8 rows (512 bytes). The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words. Program and erase functions are controlled by a command driven interface. Both sector erase and mass erase of the entire 64k byte Flash block are supported. An erased bit reads ‘1’ and a programmed bit reads MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K ‘0’. The high voltage required to program and erase is generated internally by on-chip charge pumps. All Flash blocks can be programmed or erased at the same time, however it is not possible to read from a Flash block while it is being erased or programmed. The Flash is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external programming voltage sources. WARNING: A word must be erased before being programmed. Cumulative programming of bits within a word is not allowed. Glossary Banked Register A register operating on one Flash block which shares the same register address as the equivalent registers for the other Flash blocks. The active register bank is selected by a bank-select bit in the unbanked register space. Common Register A register which operates on all Flash blocks. Command Sequence A three-step MCU instruction sequence to program, erase or erase-verify a Flash block. Erase Sector 512 bytes of Flash (8 rows of 32 words) Flash Block 32K byte Flash macro organized as 16K by 16bit Words. Includes high voltage generation and parametric test features. Flash Module Includes Bus Interface, Command Control and two Flash blocks of 32K bytes. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Features Flash Page 16K bytes of Flash located in address range $0000–$3FFF, $4000–$7FFF, $8000–$FFFF or $C000–$FFFF. Flash Super User Mode The flash super user mode allows the user to use erasing/programming sequences with FADDR/FDATA registers. Features • • • • • • • • • 64K bytes of Flash memory comprising two 32K byte blocks Each block in the Flash module can be read, programmed or erased concurrently. Automated program and erase algorithm. Interrupts on Flash command completion and command buffer empty. Fast sector erase and word program operation. 2-stage command pipeline. Flexible protection scheme for protection against accidental program or erase. Single power supply program and erase. Security feature. Modes of Operation Secured Mode The Flash module provides the necessary security information to the rest of the chip. This information is stored within a byte in the Flash block 0 ($FF0F). This byte is read automatically after each reset and stored in a volatile register - FSEC. This information also protects the Flash MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Unbanked Register A register which operates on all flash blocks. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K module from intrusive reads via the external bus interface or the background debug mode. The customer can disable the security by executing a mass erase command or by providing a 64 bit key. Flash Super User Mode When in Flash super user mode FADDR (FADDRHI and FADDRLO) and FDATA (FDATAHI and FDATALO) registers can be used to program Flash array area which is overlapped by the CALRAM. Refer to section CALRAM 2K in page 235 for details. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Block Diagram Block Diagram FLASH EEPROM 64K Command Interface Common Registers Command Complete Interrupt Command Buffer Empty Interrupt Banked Registers Command Pipelines Flash 0-1 comm2 addr2 data2 comm1 addr1 data1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Flash-0 Array 16k * 16 Bits row0 row1 row512 Flash-1 Array 16k * 16 Bits row0 row1 row512 Protection Security Oscillator Clock Clock Divider EECLK Figure 22 Flash 64K Block Diagram MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K External Pin Descriptions This module contains no signals that connect off-chip. Module Memory Map Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Figure 23 shows the Flash memory map in normal modes. Figure 24 shows the Flash memory map in special modes. The HCS12 architecture places the Flash memory address between $0000 and $FFFF. Shown within the blocks are a protection/options field and user defined Flash protected sectors. The FPOPEN bit in the FPROT register (see page 211) can globally protect the entirety of the memory block. However, two protected areas in each block, one starting from the Flash starting block address (called lower) towards higher addresses and the other one growing downward from the Flash block end address (called higher) can be activated. The high Flash block is mainly targeted to hold the boot loader code since it covers the vector space. All the other areas may be used to keep critical parameters. The Flash module register space covers the addresses INITRG (Base Address) + $100 to INITRG + $10F. Flash Data Memory Map In Normal Modes In normal modes, two blocks are mapped to fixed address since the PPAGE register always points to the page $3C and cannot be changed. See Table 35 and Figure 23. Table 35 Flash Memory Mapping in Normal Modes MCU Address Range $0000–$3FFF $4000–$7FFF $8000–$BFFF $C000–$FFFF Page $3D $3E $3C (PPAGE) $3F Flash Block 1 1 0 0 Flash Relative Address $0000–$3FFF $4000–$7FFF $8000–$BFFF $C000–$FFFF MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Module Memory Map Flash Control Register (INITRG +$100–$10F) $0000 Flash Protect Low Area 0.5K, 1K, 2K, 4K bytes $3D $4000 $3E Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Block 1 0 Page $3D and $3E $3C and $3F Freescale Semiconductor, Inc... Flash Protect High Area 2K, 4K, 8K, 16K bytes $8000 Flash Protect Low Area 0.5K, 1K, 2K, 4K bytes $3C $C000 $3F Flash Protect High Area 2K, 4K, 8K, 16K bytes $FFFF $FF00–$FF0F, Access Key, Protection, Security Figure 23 Flash Data Memory Map in Normal Modes MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Flash Data Memory Map In Special Modes In special modes, the blocks will be mapped through an address window from $8000–$BFFF in 16K byte blocks. The additional address bits are located in the PPAGE register. See Table 36 and Figure 24. Table 36 Flash Memory Mapping in Special Modes MCU Address Range $0000–$3FFF $4000–$7FFF $8000–$BFFF Page $3D $3E PPAGE=$3D PPAGE=$3E PPAGE=$3C PPAGE=$3F $3F Flash Block 1 1 1 1 0 0 0 Flash Relative Address $0000–$3FFF $4000–$7FFF Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family $0000–$3FFF $4000–$7FFF $8000–$BFFF $C000–$FFFF $C000–$FFFF Freescale Semiconductor, Inc... “ “ “ $C000–$FFFF MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Module Memory Map Flash Control Register (INITRG +$100–$10F) $0000 Flash Protect Low Area 0.5K, 1K, 2K, 4K bytes $3D $4000 $3E Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Block 1 0 Page $3D and $3E $3C and $3F Freescale Semiconductor, Inc... Flash Protect High Area 2K, 4K, 8K, 16K bytes Block 1 $8000 16K bytes paged memory Block 0 $3D $3E $3C $3F $C000 $3F $3F Flash Protect High Area 2K, 4K, 8K, 16K bytes $FFFF $FF00–$FF0F, Access Key, Protection, Security Figure 24 Flash Data Memory Map in Special Modes MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Flash Protection Option Fields Security information that allows the MCU to prevent intrusive access to the Flash module is stored in the Flash block’s Flash Protection/Options field. A description of the 16 bytes used in this field is given in Table 37. Table 37 Flash Protection/Security Field Address $FF00–$FF07 $FF08–$FF0B Size 8 4 1 Description Backdoor comparison key Reserved Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... $FF0C Protection byte for Flash block 1 (The byte is loaded into FPROT banked register during reset) Protection byte for Flash block 0 (The byte is loaded into FPROT banked register during reset) Reserved Security Byte (The byte is loaded into FSEC register during reset) $FF0D $FF0E $FF0F 1 1 1 The Flash module has hardware interlocks which protect data from accidental corruption by sectors as shown in Table 38. Flash block 0 has a protected sector located at the higher address end, just below $FFFF, and another protected sector located at the lower address end, starting at address $8000. Flash block 1 has a protected sector located at the higher address end, just below $7FFF, and another protected sector located at the lower address end, starting at address $0000.The high address protected sectors in each Flash block can be sized from 2K MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Module Memory Map bytes to 16K bytes. The low address protected sectors in each Flash block can be sized from 0.5K bytes to 4K bytes. Table 38 Memory Map Summary In Normal Modes MCU Address Range Page Protectable Low Range $0000-$01FF $3D $0000-$03FF $0000-$07FF $0000-$0FFF $7800-$7FFF $3E N.A. $7000-$7FFF $6000-$7FFF $4000-$7FFF $8000-$81FF $3C $8000-$83FF $8000-$87FF $8000-$8FFF $F800-$7FFF $3F N.A. $F000-$7FFF $E000-$7FFF $C000-$7FFF N.A. N.A. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Protectable High Range Flash Block Freescale Semiconductor, Inc... $0000-$7FFF 1 $8000-$FFFF 0 NOTE: The use of backdoor keys $0000 and $FFFF is not allowed. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Register Memory Map The Flash module also contains a set of 16 control and status registers located in address space INITRG + $100 to INITRG + $10F. In order to accommodate two Flash blocks with a minimum register address space, a set of registers (INITRG+$104 to INITRG+$10B) is duplicated in two banks. The active bank is selected by the BKSEL bit in the unbanked Flash Configuration Register (FCNFG). A summary of these registers is given in Figure 25. Bit 7 6 5 FDIV5 NV5 4 FDIV4 NV4 3 FDIV3 NV3 2 FDIV2 NV2 1 FDIV1 SEC1 Bit 0 FDIV0 SEC0 Addr. Offset $0100 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Register name Freescale Semiconductor, Inc... FCLKDIV Read: FDIVLD PRDIV8 Write: Read: KEYEN Write: Read: Write: NV6 FSEC $0101 FTSTMOD Reads to this register return unpredictable values in normal modes. $0102 FCNFG Unbanked Registers Banked Registers Read: CBEIE Write: CCIE KEYACC 0 0 0 0 BKSEL $0103 FPROT Read: FPOPEN Write: Read: CBEIF Write: Read: Write: 0 NV6 CCIF FPHDIS FPHS1 FPHS0 FPLDIS 0 BLANK FPLS1 0 FPLS0 $0104 0 FSTAT PVIOL ACCERR 0 $0105 FCMD CMDB6 CMDB5 0 CMDB2 0 CMDB0 $0106 Reserved for Read: Factory Test Write: FADDRHI Read: Write: Read: Write: 0 Reads to this register return unpredictable values. $0107 AB15 AB14 AB13 AB12 AB11 AB10 AB9 $0108 FADDRLO AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 $0109 = Unimplemented or reserved Figure 25 Flash Control Register Map MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Module Memory Map Register name FDATAHI Read: Write: Bit 7 DHI7 6 DHI6 5 DHI5 4 DHI4 3 DHI3 2 DHI2 1 DHI1 Bit 0 DHI0 Addr. Offset $010A FDATALO Read: DLO7 Write: Read: Write: Read: Write: Read: Write: Read: Write: 0 DLO6 0 DLO5 0 DLO4 0 DLO3 0 DLO2 0 DLO1 0 DLO0 0 $010B Reserved $010C Freescale Semiconductor, Inc... Reserved $010D Reserved 0 0 0 0 0 0 0 0 $010E Reserved 0 0 0 0 0 0 0 0 $010F = Unimplemented or reserved Figure 25 Flash Control Register Map (Continued) NOTE: Register Address = Base Address (INITRG) + Address Offset MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions NOTE: All bits of all registers in this module are completely synchronous to internal clocks during a register read. FCLKDIV — Flash Clock Divider Register The FCLKDIV register is used to control timed events in program and erase algorithms. This register is unbanked. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Address Offset: $0100 Bit 7 Read: Write: Reset: 0 FDIVLD 6 PRDIV8 0 5 FDIV5 0 4 FDIV4 0 3 FDIV3 0 2 FDIV2 0 1 FDIV1 0 Bit 0 FDIV0 0 = Reserved or unimplemented Read: Anytime Write: Once in normal mode, anytime in special mode NOTE: Access to this register during Flash Super User mode (FSUM=1) will cause the ACCERR bit set. FDIVLD — Flash Clock Divider Loaded 1 = Register has been written to since the last reset. 0 = Register has not been written. PRDIV8 — Enable Prescaler by 8 1 = Enables a prescaler by 8, to divide the Flash module input oscillator clock before feeding into the FCLKDIV divider. 0 = The input oscillator clock is directly fed into the FCLKDIV divider FDIV[5:0] — Flash Clock Divider Bits The combination of PRDIV8 and FDIV[5:0] effectively divides the Flash module input oscillator clock down to a frequency of 150-200 KHz. The maximum divide ratio is 512. Table 35 show some FCLKDIV settings. Please refer to Writing the FCLKDIV Register in page 220 for details about how to calculate these values. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions Table 39 Example FCLKDIV settings Oscillator Frequency Bus Clock 1.0 MHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz 1.0 MHz 2.0MHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz 2.0 MHz 4.0MHz 4.0 MHz 8.0 MHz 16.0 MHz 8.0 MHz 16.0 MHz 16.0 MHz PRDIV8 FDIV[5:0] FCLK Frequency FCLK Period 1.0MHz 0 000101 166.66 KHz 6us Freescale Semiconductor, Inc... 0 001011 166.66 KHz 6us 0 001010 181.81 KHz 5.5us 0 0 010101 010100 181.81 KHz 190.47 KHz 5.5us 5.25us 16.0 MHz 32.0 MHz 1 1 001010 010100 181.81 KHz 190.47 KHz 5.5us 5.25us MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Flash EEPROM 64K FSEC — Flash Security Register Address Offset: $0101 This FSEC register holds all bits associated with the device security. This register is unbanked. Bit 7 Read: Write: Reset: F KEYEN 6 NV6 F 5 NV5 F 4 NV4 F 3 NV3 F 2 NV2 F 1 SEC1 F Bit 0 SEC0 F = Reserved or unimplemented Read: Anytime Write: Never NOTE: Access to this register during Flash Super User mode (FSUM=1) will cause the ACCERR bit set. The FSEC register is loaded from the Flash Protection/Options field byte at $FF0F during the reset sequence, indicated by “F” in the reset row of the register description. KEYEN — Enable backdoor key to security 1 = backdoor to Flash is enabled 0 = backdoor to Flash is disabled NV[6:2] — Non Volatile Flag Bits These 5 bits are available to the user as non-volatile flags. SEC[1:0] — Memory Security Bits The SEC[1:0] bits define the security state of the device as shown in Table 40. If the Flash is unsecured using the Backdoor Key Access, the SEC bits are forced to 10. Table 40 Security States SEC[1:0] 00 01 10 11 Description secured secured unsecured secured MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions The security function in the Flash module is described in page 231. FTSTMOD — Flash Test Mode Register Address Offset: $0102 The unbanked FTSTMOD register is used primarily to control the Flash Test modes. Bit 7 Read: Write: N/A 0 6 N/A 0 5 N/A 0 4 WRALL 0 3 0 0 2 0 0 1 0 0 Bit 0 N/A 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Reset: = Reserved or unimplemented In normal modes, all bits in the FTSTMOD register read zero and are not writable. The WRALL bit is writable only in special modes. The purpose of this bit is to launch a command on all blocks in parallel. This can be useful for mass erase and blank check operations. All other bits in this register must be written to zero at all times. WRALL —Write to all register banks. If this bit is set, all banked registers sharing the same address will be written simultaneously. 1 = Write to all register banks. 0 = Write only to the bank selected via BKSEL. FCNFG — Flash Configuration Register Address Offset: $0103 The FCNFG register enables the Flash interrupts, gates the security backdoor writes and selects the register bank to be operated on. This register is not banked. Bit 7 Read: Write: Reset: CBEIE 0 6 CCIE 0 5 KEYACC 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 BKSEL 0 = Reserved or unimplemented Read: Anytime Write: Anytime MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K NOTE: Access to this register during Flash Super User mode (FSUM=1) will cause the ACCERR bit set. CBEIE — Command Buffer Empty Interrupt Enable The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash. 1 = An interrupt will be requested whenever the CBEIF flag is set 0 = Command Buffer Empty interrupts disabled Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family CCIE — Command Complete Interrupt Enable Freescale Semiconductor, Inc... The CCIE bit enables the interrupts in case of all commands being completed in the Flash. 1 = An interrupt will be requested whenever the CCIF flag is set 0 = Command Complete interrupts disabled KEYACC — Enable Security Key Writing 1 = Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid data 0 = Flash writes are interpreted as the start of a program or erase sequence. BKSEL — Register Bank Select The BKSEL bit is used to select one among all available register banks. The register bank associated with Flash 0 is the default out of reset. The bank selection is according to Table 41. Table 41 Register Bank Selects BKSEL 0 1 Selected Register Bank Flash block 0 Flash block 1 MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions FPROT — Flash Protection Register Address Offset: $0104 The FPROT register defines which Flash sectors are protected against program or erase. This register is banked. Bit 7 Read: Write: Reset: FPOPEN F 6 NV6 F 5 FPHDIS F 4 FPHS1 F 3 FPHS0 F 2 FPLDIS F 1 FPLS1 F Bit 0 FPLS0 F Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... The FPROT register is readable in normal and special modes. Bit NV6 is not writable. FPOPEN, FPHDIS and FPLDIS bits in the FPROT register can only be written to the protected state (i.e. 0). FPLS[1:0] can be written anytime until bit FPLDIS is cleared. FPHS[1:0] bits can be written anytime until bit FPHDIS is cleared. If the FPOPEN bit is cleared, then the state of the FPHDIS, FPHS[1:0], FPLDIS and FPLS[1:0] bits is irrelevant. The FPROT register is loaded from Flash array during reset according to the following table. Table 42 Loading of the Protection Register from Flash Flash Address $FF0D $FF0C Protection byte for Flash block 0 Flash block 1 NOTE: Access to this register during Flash Super User mode (FSUM=1) will cause the ACCERR bit set. To change the Flash protection that will be loaded on reset, the upper sector of Flash must be unprotected, then the Flash Protect/Security byte located as described in Table 37 must be written to. A protected Flash sector is disabled by the bits FPHDIS and FPLDIS while the size of the protected sector is defined by FPHS[1:0] and FPLS[1:0] in the FPROT register. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Trying to alter any of the protected areas will result in a protect violation error and bit PVIOL will be set in the Flash Status Register FSTAT. A mass erase of a whole Flash block is only possible when protection is fully disabled by setting FPLDIS and FPHDIS bits. FPOPEN — Opens the Flash for program or erase. 1 = The Flash sectors not protected are enabled for program or erase. 0 = The whole Flash array is protected. In this case the FPHDIS, FPHS[1:0], FPLDIS and FPLS[1:0] bits within the protection register are don’t care. FPHDIS — Flash Protection Higher address range Disable The FPHDIS bit determines whether there is a protected area in the higher space of the Flash address map. 1 = Protection disabled 0 = Protection enabled FPHS[1:0] — Flash Protection Higher Address Size The FPHS[1:0] bits determine the size of the protected sector. Refer to Table 43. Table 43 Higher Address Range Protection Protected Address Range FPHS[1:0] Block 0 00 01 10 11 $F800–$FFFF $F000–$FFFF $E000–$FFFF $C000–$FFFF Block 1 $7800–$7FFF $7000–$7FFF $6000–$7FFF $4000–$7FFF Protected Size (Bytes) 2K 4K 8K 16K FPLDIS — Flash Protection Lower address range Disable The FPLDIS bit determines whether there is a protected sector in the lower space of the Flash address map. 1 = Protection disabled 0 = Protection enabled MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions FPLS[1:0] — Flash Protection Lower Address Size The FPLS[1:0] bits determine the size of the protected sector. Refer to Table 44. Table 44 Lower Address Range Protection Protected Address Range FPLS[1:0] Block 0 Block 1 $0000–$01FF $0000–$03FF $0000–$07FF $0000–$0FFF 00 01 10 11 $8000–$81FF $8000–$83FF $8000–$87FF $8000–$8FFF Protected Size (Bytes) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 512 Bytes 1K 2K 4K NV6 — Non Volatile Flag Bit This bit is available as non-volatile flag. FSTAT — Flash Status Register The FSTAT register defines the Flash state machine command status and Flash array access, protection and blank verify status. This register is banked. Address Offset: $0105 Bit 7 Read: Write: Reset: CBEIF 1 6 CCIF 1 5 PVIOL 0 4 ACCERR 0 3 0 0 2 BLANK 0 1 0 0 Bit 0 0 0 = Reserved or unimplemented Read: Anytime Write: Anytime to clear flags CBEIF — Command Buffer Empty Interrupt Flag The CBEIF flag indicates that the address, data and command buffers are empty so that a new command sequence can be started. The CBEIF flag is cleared by writing a “1” to CBEIF. Writing a “0” to the MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K CBEIF flag has no effect on CBEIF but sets ACCERR, which can be used to abort a command sequence. This bit, CBEIF, is used together with the enable bit CBEIE, to generate the interrupt request. 1 = Buffers are ready to accept a new command. 0 = Buffers are full. CCIF — Command Complete Interrupt Flag The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect. This bit, CCIF, is used together with the enable bit CCIE, to generate the interrupt request. 1 = All commands are completed 0 = Command in progress PVIOL — Protection Violation The PVIOL flag indicates an attempt was made to program or erase an address in a protected Flash memory area. The PVIOL flag is cleared by writing a “1” to PVIOL. Writing a “0” to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command. Refer to PVIOL flag set condition in page 229 for more information. 1 = A protection violation has occurred. 0 = No failure ACCERR — Flash Access Error The ACCERR flag indicates an illegal access to the Flash array. This can be either a violation of the command sequence, issuing an illegal command (illegal combination of the CMDBx bits in the FCMD register) or the execution of a CPU STOP instruction while a command is executing (CCIF=0). The ACCERR flag is cleared by writing a “1” to ACCERR. Writing a “0” to the ACCERR flag has no effect on ACCERR.While ACCERR is set, it is not possible to launch another command. Refer to ACCERR flag set condition in page 228 1 = Access error has occurred. 0 = No failure MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions BLANK — Array has been verified as erased The BLANK flag indicates that an Erase Verify command has checked the Flash block and found it to be blank. The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command sequence. Writing to the BLANK flag has no effect on BLANK. 1 = Flash block verifies as erased. 0 = If an Erase Verify command has been requested, and the CCIF flag is set, then a zero in BLANK indicates the block is not erased MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K FCMD — Flash Command Register Address Offset: $0106 The FCMD register defines the Flash commands. This register is banked. Bit 7 Read: Write: Reset: 0 0 6 CMDB6 0 5 CMDB5 0 4 0 0 3 0 0 2 CMDB2 0 1 0 0 Bit 0 CMDB0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime Write: Only writable during a command sequence CMDB6, 5, 2 and 0 — Valid Flash User mode commands are shown in Table 45. Any command other than those mentioned in Table 45 sets the ACCERR bit in the FSTAT register. Table 45 Valid User Mode Commands Command Meaning Remarks Verify all memory bytes of the Flash block are erased. If the array is erased the BLANK bit will set in the FSTAT register upon command completion. Program a word (two bytes) Erase 512 bytes of Flash Erase all the Flash array of the Flash block. A mass erase of the full block is only possible when FPLDIS, FPHDIS and FPOPEN are set. Generate an access error $05 Erase Verify $20 $40 $41 other Memory Program Sector Erase Mass Erase Illegal MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions FADDR — 16-bit Address Register Flash Address High (FADDRHI) Register Address Offset: $0108 FADDRHI and FADDRLO are the Flash address registers. These registers are banked. Bit 7 Read: Write: 0 0 6 AB15 0 5 AB14 0 4 AB13 0 3 AB12 0 2 AB11 0 1 AB10 0 Bit 0 AB9 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Reset: = Reserved or unimplemented Flash Address Low (FADDRLO) Register Address Offset: $0109 Bit 7 Read: Write: Reset: AB8 0 6 AB7 0 5 AB6 0 4 AB5 0 3 AB4 0 2 AB3 0 1 AB2 0 Bit 0 AB1 0 = Reserved or unimplemented Read: Only in the flash super user mode. In user modes, the FADDR (FADDRHI, FADDRLO) register reads zeros. Write: Only in the flash super user mode. For sector erase, the MCU address bits AB[8:0] are don’t care. For mass erase, any address within the block is valid to start the command. AB[15:1] — 64K byte Relative Address of Flash Array These address bits are used in the program/erase sequence in the flash super user mode. Refer to Low Power Options in page 229 for the program/erase sequence. The mapping of the address information in the FADDR register to the Flash relative address is shown in Figure 26. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K NOTE: The address bit AB0 is not stored, since no byte access from this register is possible. For sector erase, the MCU address bits AB[8:0] are don’t care. For mass erase, any address within the block is valid to start the command. FADDR Register Flash Relative Address 0 FADDRHI[6:0] FADDRLO[7:0] Figure 26 FADDR Address Mapping to Flash Relative Address MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family FADDRHI[6:0] FADDRLO[7:0] 0 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Register Descriptions FDATA — Flash 16-bit Data Buffer and Register Flash Data High (FDATAHI) Register Address Offset: $010A FDATAHI and FDATALO are the Flash data registers. These registers are banked. Bit 7 Read: 6 DHI6 0 5 DHI5 0 4 DHI4 0 3 DHI3 0 2 DHI2 0 1 DHI1 0 Bit 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Write: Reset: DHI7 0 DHI0 0 = Reserved or unimplemented Flash Data Low (FDATALO) Register Address Offset: $010B Bit 7 Read: Write: Reset: DLO7 0 6 DLO6 0 5 DLO5 0 4 DLO4 0 3 DLO3 0 2 DLO2 0 1 DLO1 0 Bit 0 DLO0 0 = Reserved or unimplemented Read: Only in the flash super user mode. In user modes, all FDATA bits read zero Write: Only in the flash super user mode. All FDATA(FDATAHI and FDATALO) bits read zero and are not writable when the Flash EEPROM module is not in the flash super user mode. DHI[7:0] and DLO[7:0] — 16-bit Data Register In flash super user mode, all FDATA bits are readable and writable when writing to an address within the Flash address range. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Functional Description Program and Erase Operation Write and read operations are both used for the program and erase algorithms described in this section. These algorithms are controlled by a state machine whose timebase FCLK is derived from the oscillator clock via a programmable divider. The command register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO), so that a new command along with the necessary data and address can be stored to the buffer while the previous command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row, as the high voltage generation can be kept ON in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the Flash status register. Interrupts for the Flash will be generated if enabled. The next four subsections describe: • • • • Writing the FCLKDIV Register How to write the FCLKDIV register. The write sequences used to program, erase and erase-verify the Flash. Valid Flash commands. Errors resulting from illegal Flash operations. Prior to issuing any program or erase command, it is first necessary to write the FCLKDIV register to divide the oscillator down to within the 150kHz to 200kHz range.The program and erase timings are also a function of the bus clock, such that the FCLKDIV determination must take this information into account. If we define: • • • FCLK as the clock of the Flash timing control block Tbus as the period of the bus clock INT(x) as taking the integer part of x (e.g. INT(4.323)=4), then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 27. For example, if the oscillator clock frequency is 4Mz and the bus clock is 25MHz, FCLKDIV bits FDIV[5:0] should be set to 20 (010100) and bit MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Functional Description PRDIV8 set to 0. The resulting FCLK is then 190kHz. As a result, the Flash algorithm timings are increased over optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% NOTE: WARNING: Command execution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash with an input clock < 150kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150kHz can destroy the Flash due to overstress. Setting FCLKDIV to a value such that (1/FCLK+1/(Bus Clock) ) < 5µs can result in incomplete programming or erasure of the memory array cells. If the FCLKDIV register is written, the bit FDIVLD is set automatically. If this bit is zero, the register has not been written since the last reset. Program and erase commands will not be executed if this register has not been written to. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K START Tbus < 1µs? yes PRDIV8=0 (reset) no PROGRAM/ERASE IMPOSSIBLE Freescale Semiconductor, Inc... oscillator clock 12.8MHz? yes PRDIV8=1 PRDCLK=oscillator clock/8 no PRDCLK=oscillator clock PRDCLK[MHz]*(5+(1/BusClock)[µs] ) no an integer? yes FDIV[5:0]=PRDCLK[MHz]*(5+(1/BusClock) [µs] ) - 1 FDIV[5:0]=INT(PRDCLK[MHz]*(5+(1/BusClock)[µs])) TRY TO INCREASE BusClock FCLK=(PRDCLK)/(1+FDIV[5:0]) (1/FCLK + 1/BusClock) [µs] > 5 AND FCLK > 0.15MHz ? yes END no yes FDIV[5:0]> 4? no PROGRAM/ERASE IMPOSSIBLE Figure 27 PRDIV8 and FDIV bits Determination Procedure MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Flash EEPROM 64K Functional Description Program and Erase Sequence in Normal Mode A Command State Machine is used to supervise the write sequencing for program and erase. The erase-verify command follows the same flow. Before starting a command sequence, it is necessary to verify that there is no pending access error or protection violation (the ACCERR and PVIOL flags should be cleared in the FSTAT register). It is then required to set the PPAGE register when in special modes. The procedure is as follows: 1. Verify that all ACCERR and PVIOL flags in the FSTAT register are cleared in all banks. This requires to check the FSTAT content for all combinations of the BKSEL bit in the FCNFG register. 2. Write to bit BKSEL in the FCNFG register to select the bank of registers corresponding to the 32K flash block to be programmed or erased (i.e. Flash 0 or 1). See Figure 23, 24 for further details. 3. In special modes, write to the core PPAGE register ($x030) to select one of the 16K pages to be programmed if programming in the $8000–$BFFF address range. There is no need to set PPAGE when programming in the $4000-$7FFF or $C000-$FFFF address ranges or when operating in normal modes. After this possible initialization step the CBEIF flag should be tested to ensure that the address, data and command buffers are empty. If so, the program/erase command write sequence can be started. The following 3-step command write sequence must be strictly adhered to and no intermediate writes to the Flash module are permitted between the 3 steps. It is possible to read any Flash register during a command sequence. The command sequence is as follows: 1. Write the aligned data word (16-bits) to be programmed to the valid Flash address space between $0000 and $FFFF. The address and data will be stored in internal buffers. For program, all address bits are valid. For erase, the value of the data bytes is don’t care. For mass erase the address can be anywhere in the available address space of the 32K byte block to be erased. For sector erase the address bits 8:0 are ignored for the Flash. 2. Write the program or erase command to the command buffer. These commands are listed in Table 45. 3. Clear the CBEIF flag by writing a “1” to it to launch the command. When the CBEIF flag is cleared, the CCIF flag is cleared by hardware indicating that the command was successfully launched. The ACCERR and PVIOL flags should be tested to MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K ensure the command sequence was valid. The CBEIF flag will be set again indicating the address, data and command buffers are ready for a new command sequence to begin. The completion of the command is indicated by the CCIF flag setting (Command Complete Interrupt Flag). The CCIF flag only sets when all active and pending commands have been completed. NOTE: A summary of the program algorithm is shown in Figure 28. For the erase algorithm, the user writes either a mass or sector erase command to the FCMD register. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The Command State Machine will flag errors in program or erase write sequences by means of the ACCERR (access error) and PVIOL (protection violation) flags in the FSTAT register. An erroneous command write sequence will abort and set the appropriate flag. If set, the user must clear the ACCERR or PVIOL flags before commencing another command write sequence. By writing a 0 to the CBEIF flag the command sequence can be aborted after the word write to the Flash address space or after writing a command to the FCMD register and before the command is launched. Writing a “0” to the CBEIF flag in this way will set the ACCERR flag. Freescale Semiconductor, Inc. Flash EEPROM 64K Functional Description START Read: Register FSTAT Are ACCERR or PVIOL set? yes Clear ACCERR and/or PVIOL no no Change BKSEL All Flash banks checked? yes Read: Register FCLKDIV Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Clock Register Written Check Bit FDIVLD set? yes no Write: Register FCLKDIV 1. Write: Array Address and Program Data Write: Register FCMD Program Command $20 Write: Register FSTAT Clear bit CBEIF $80 Read: Register FSTAT NOTE: command sequence aborted by writing $00 to FSTAT register. NOTE: command sequence aborted by writing $00 to FSTAT register. 2. 3. Protection Violation Check Bit PVIOL Set? no yes Write: Register FSTAT Clear bit PVIOL $20 Access Error Check Bit ACCERR Set? no yes Write: Register FSTAT Clear bit ACCERR $10 yes yes Next Write? no Address, Data, Command Buffer Empty Check Bit CBEIF Set? no Bit Polling for Command Completion Check Bit CCIF Set? no Read: Register FSTAT yes FINISH Figure 28 Example Program Algorithm MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Program and Erase Sequence in Flash Super User Mode The Flash EEPROM module requires that the USER program/erase operations be allowed via programming the address (FADDR) and data (FDATA) registers. The operation is controlled via the FSUM bit in the CALCFG register (refer to page 241). Super user operation is indicated when this bit is set. When FSUM = 1, a register write to the address register will start the monitor state machine for the operation. During this sequence the address presented on the core data bus is monitored for protection violation and operation sequence is monitored for access errors. The access error is set if the strict sequence of, address register access followed by the data register access is not observed. Address alignment is also checked for access error indications. The operation sequence is shown below: 1. Write the address word to be programmed to the valid Flash address space, shown in Table 35, to the FADDR register. The address will be stored in internal buffers. 2. Write the data word to the FDATA register. The data will be stored in internal buffers. NOTE: For program, all address bits are valid. For erase, the value of the data bytes is don’t care. For mass erase, the address can be anywhere in the available address space of the block to be erased. For sector erase the address bits[8:0] are ignored for the Flash. 3. Write the program or erase command to the command buffer. These commands are described in FCMD — Flash Command Register and listed in Table 45 in page 216. 4. Clear the CBEIF flag by writing a “1” to it to launch the command. When the CBEIF flag is cleared, the CCIF flag is cleared by hardware indicating that the command was successfully launched. The CBEIF flag will be set again indicating the address, data and command buffers are ready for a new command sequence to begin. A summary of the program algorithm is shown in Figure 29. For the erase algorithm, the user writes either a mass or sector erase command to the FCMD register. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Functional Description START Are ACCERR or PVIOL set? no yes Clear ACCERR and/or PVIOL Read: Register FSTAT Change BKSEL no All Flash banks checked? yes Clock Register Written Check Read: Register FCLKDIV yes Write: Register FCLKDIV Select BKSEL Enter Flash Super User Mode Write: Register FCNFG Write: Register CALCFG Set bit FSUM $80 Write: Array Address to FADDR Register Write: Array Data to FDATA Register Write: Register FCMD Program Command $20 Write: Register FSTAT Clear bit CBEIF $80 Read: Register FSTAT Bit PVIOL Set? no NOTE: command sequence aborted by writing $00 to FSTAT register. NOTE: command sequence aborted by writing $00 to FSTAT register. (1) 1. 2. 3. 4. Protection Violation Check yes Write: Register FSTAT Clear bit PVIOL $20 Access Error Check Bit ACCERR Set? no yes Write: Register FSTAT Clear bit ACCERR $10 yes yes Address, Data, Command Buffer Empty Check Bit CBEIF Set? no Next Write? no Bit Polling for Command Completion Check Bit CCIF Set? yes no Read: Register FSTAT Exit Flash Super User Mode Write: Register CALCFG Clear bit FSUM $00 (1) (1) The register CALCFG is in CALRAM. FINISH Figure 29 Example Program Algorithm in Flash Super User Mode MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Bit FDIVLD set? no Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Valid Flash Commands Figure 45 in page 216 summarizes the valid Flash User commands. Also shown are the effects of the commands on the Flash It is not permitted to program a Flash word without first erasing the sector in which that word resides. WARNING: Illegal Flash Operations This subsection describes the conditions that set ACCERR and PVIOL flags. The ACCERR flag will be set during the command write sequence if any of the following illegal operations are performed, causing the command write sequence to immediately abort: 1. Writing to the Flash address space before initializing FCLKDIV. 2. Writing to the Flash address space in the range $8000–$BFFF when PPAGE register does not select a 16K bytes page in the Flash block selected by the BKSEL bit in special modes. 3. Writing to the Flash address space $0000–$7FFF or $8000–$FFFF with the BKSEL bit in the FCNFG register not selecting the Flash block in normal modes. 4. Writing a misaligned word or a byte to the valid Flash address space. 5. Writing to the Flash address space while CBEIF is not set. 6. Writing a second word to the Flash address space before executing a program or erase command on the previously written word. 7. Writing to any Flash register other than FCMD after writing a word to the Flash address space. 8. Writing a second command to the FCMD register before executing the previously written command. 9. Writing an invalid user command to the FCMD register in user mode. 10. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the command register FCMD. 11. The part enters STOP mode and a program or erase command is in progress. The command is aborted and any pending command is killed. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... ACCERR flag set condition MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Low Power Options 12. When security is enabled, a command other than Mass-Erase or Erase-Verify originating from a non-secure memory or from the Background Debug Mode is written to FCMD. 13. A “0” is written to the CBEIF bit in the FSTAT register. 14. Violating the register write sequence (FADDR followed by FDATA) in Flash Super User Mode. The ACCERR flag will not be set if any Flash register is read during the command sequence. Freescale Semiconductor, Inc... If the Flash array is read during execution of an algorithm (i.e. CCIF bit in the FSTAT register is low) the read will return non valid data and the ACCERR flag will not be set. If an ACCERR flag is set in any of the banked FSTAT registers, the Command State Machine is locked. It is not possible to launch another command on any block until the ACCERR flag is cleared. PVIOL flag set condition The PVIOL flag will be set during the command write sequence after the word write to the Flash address space if any of the following illegal operations are performed, causing the command sequence to immediately abort: 1. Writing a Flash address to program in a protected area of the Flash. 2. Writing a Flash address to erase in a protected area of the Flash. 3. Writing the mass erase command to FCMD while any protection is enabled. If a PVIOL flag is set in any of the banked FSTAT registers, the Command State Machine is locked. It is not possible to launch another command on any block until the PVIOL flag is cleared. Low Power Options When the array or the registers are not being accessed clocking to the register block is shut off to save power. The only exceptions to this are MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Flash EEPROM 64K the flag bits in the FSTAT registers which are updated by internal state machines. Run Mode No special current saving modes available. Wait Mode Stop Mode No low power options exist for this module in stop mode. If a command is active (CCIF = 0) when the MCU enters the STOP mode, the command will be aborted and the high voltage circuitry to the Flash array will be switched off. CCIF and ACCERR flags will be set. If commands are active in more than one block when STOP occurs, then all the corresponding CCIF and ACCERR flags will be set. Upon exit from STOP the CBEIF flag is set and any pending command will not be executed. The ACCERR flag must be cleared before returning to normal operation. As active commands are immediately aborted when the MCU enters STOP mode, it is strongly recommended that the user does not use the STOP command during program and erase execution. WARNING: Background Debug Mode In Background Debug Mode (BDM), the FPROT registers are writable. If the chip is unsecured then all Flash commands listed in Table 45 in 216 can be executed. In special single chip mode if the chip is secured then the only possible command to execute is Mass Erase. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family When the MCU enters WAIT mode and any command is active (CCIF = 0) the command will be completed. If enabled, interrupts can be used to wake the MCU out of Wait mode. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Flash Security Flash Security The Flash module provides the necessary security information to the rest of the chip. After each reset, the Flash module determines the security state of the microcontroller as defined in section FSEC — Flash Security Register in page 208. The contents of the Flash Protection/Options byte at $FF0F in the Flash Protection/Options Field must be changed directly by programming $FF0F when the device is unsecured and the higher address sector is unprotected. If the Flash Protection/Options byte is left in the secure state, any reset will cause the microcontroller to return to the secure operating mode Reset Initialization Out of reset the module holds core activity while the Protection and Security registers are loaded from Flash 0. Thereafter, the Flash module is immediately accessible, operating in read mode. If a reset occurs while any command is in progress that command will be immediately aborted. The state of the word being programmed or the sector / block being erased is not guaranteed. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash EEPROM 64K Interrupts General This module can generate an interrupt when all commands are completed or the address, data and command buffers are empty. Table 46 Flash Interrupt Sources Interrupt Source Interrupt Flag CBEIF Flash Block 0 or 1 CCIF Flash Block 0 or 1 Local Enable Global (CCR) Mask I Bit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Flash Address, Data and Command Buffers empty All Commands are completed CBEIE CCIE I Bit Description of Interrupt Operation Figure 30 shows the logic used for generating interrupt via the relevant block. This system uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE in addition to the BKSEL bit, to discriminate for the interrupt generation. By taking account of the possible selected bank, the system is prevented from generating false interrupts when the command buffer is empty in an unselected bank. block0 CBEIF Block0 select block1 CBEIF Block1 select CBEIE block0 CCIF Block0 select block1 CCIF Block1 select CCIE Flash Interrupt Request Figure 30 Flash Interrupt Implementation. MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Flash EEPROM 64K Interrupts CAUTION: When programming or erasing Flash Block 0 the interrupt vectors are not readable. Therefore, it is not recommended to program or erase the Flash Block 0 with interrupts enabled. Recovery from STOP or WAIT The module can recover the part from WAIT, if the interrupts are enabled. There is no capability to recover from STOP. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Flash EEPROM 64K MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Flash EEPROM 64K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. CALRAM 2K Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Modes of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Glossary CALRAM Module Includes Bus Interface, Calibration Control and a 2K byte RAM block. Flash Super User Mode The flash super user mode allows the user to use erasing/programming sequences with FADDR/FDATA registers. MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CALRAM 2K Overview The 2K byte CALRAM (Calibration RAM) module can overlap with the Flash EEPROM array, and CPU can access data in the CALRAM instead of in the Flash EEPROM array. During overlapping, the Flash EEPROM array can be erased or programmed by entering the flash super user mode. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The CALRAM may be read or written as either bytes, aligned words or misaligned words. For compatibility with Flash EEPROM, access time is one bus cycle for byte and aligned word accesses, and two bus cycles for misaligned word accesses. When the MCU is in the secured state and in the special single chip mode, reading the CALRAM array returns $FFFF for any word accesses or $FF for any byte accesses instead of returning actual values stored in the array. Features • 2k bytes of CALRAM – 2K byte calibration block over Flash EEPROM – Access cycle compatible to Flash EEPROM – Flash EEPROM erase or program possible while the CALRAM overlaps with the Flash EEPROM – Re-mappable to any 2K byte boundary MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CALRAM 2K Modes of Operations Modes of Operations Secured Mode The flash module provides the necessary security information to the rest of the chip. This information is stored within a byte in the flash block 0. This byte is read automatically after each reset and stored in a volatile register in the flash module. This information also protects the CALRAM module from intrusive reads via the external bus interface or the background debug mode. Run Mode Normal mode of operation. Wait Mode The CALRAM modules operates normally during WAIT mode if the bus clock is enable. Stop Mode All clocks are stopped. MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... CALRAM 2K Block Diagram MC9S12T64Revision 1.1.1 CALRAM Block 2K Bytes Registers Control Module Bus Interface HCS12 Bus Flash Super User Mode Figure 31 CALRAM 2K Byte Block Diagram Freescale Semiconductor, Inc. CALRAM 2K For More Information On This Product, Go to: www.freescale.com Flash EEPROM Module Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. CALRAM 2K External Pin Descriptions External Pin Descriptions This module does not have external pins relevant for the user. Module Memory Map Overview The memory data is accessible in the address range $1000 - $17FF after reset and can be re-mapped to any 2k byte boundary within the MCU address space. The CALRAM module contains a control register in the same address space INITRG +$0FC - INITRG +$0FF. Data Memory Map CALRAM array can be mapped to any 2K byte boundary within the 64K byte address space. The CALRAM array address can be changed anytime through the INITCRM register. $0000 64K byte Address Space 2K bytes CALRAM Mappable to any 2K byte boundary (Re-mappable) $FFFF Figure 32 CALRAM Data Memory Map MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. CALRAM 2K Register Memory Map Register name CALCFG Read: Write: Read: Write: . Bit 7 FSUM 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Addr. Offset $00FC Reserved 0 0 0 0 0 0 0 0 $00FD$00FF Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... = Unimplemented or reserved NOTE: Register Address = Base Address (INITRG) + Address Offset MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CALRAM 2K Register Descriptions Register Descriptions CALCFG — Calibration Configuration Register Address Offset: $00FC Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Bit 7 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Freescale Semiconductor, Inc... Read: Write: Reset: FSUM 0 = Reserved or unimplemented Read: Anytime Write: Anytime The FSUM bit is used to establish the operating mode for the flash module. Setting this bit will put the flash module in the flash super user mode. FSUM — Flash Super User Mode bit When this bit is cleared, the Flash EEPROM module enters in normal mode. When this bit is set, the Flash EEPROM module enters in flash super user mode and FADDR (FADDRHI and FADDRLO) and FDATA (FDATAHI and FDATALO) registers can be used to program flash array area which is overlapped by the CALRAM. See Flash EEPROM section in page 193 for more information. 1 = Flash module is in Flash Super user mode 0 = Flash module is in Normal mode MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CALRAM 2K Functional Description The CALRAM is designed to replace data in the Flash EEPROM for calibration purposes without stopping the user’s control program. This function is controlled by the register INITCRM (see Module Mapping Control (MMC) in page 121) and the CALCFG register. The CRAM[15:11] bits in the register INITCRM are used to map the CALRAM to a 2K byte boundary. These write-anytime bits have to be written in order to choose the calibration block area in the Flash EEPROM. Since data in the CALRAM array is undefined after reset, data may be written in the array before mapping to the calibration area to prevent reading unpredictable values. Table 47 shows example CALRAM mapping. Table 47 Example CALRAM Mapping CRAM[15:11] 00000 00001 00010 ..... 11101 11110 11111 Address $0000 – $07FF $0800 – $0FFF $1000 – $17FF ..... $E800 – $EFFF $F000 – $F7FF $F800 – $FFFF There is another bit called CRAMON in the register INITCRM. This write-anytime bit makes the CALRAM array visible in the address specified by the CRAM bits. If this bit is set the CALRAM is used, otherwise the Flash memory is used. Flash Super User Mode Control MC9S12T64Revision 1.1.1 The FSUM bit in the register CALCFG determines if the Flash EEPROM module enters the flash super user mode. When FSUM is set, the Flash CALRAM 2K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Calibration Block Specified by INITCRM CALRAM can be mapped to any 2K byte boundary within the 64K byte memory space. Freescale Semiconductor, Inc. CALRAM 2K Functional Description EEPROM module is in the flash super user mode and the FADDR (FADDRHI and FADDRLO) and FDATA (FDATAHI and FDATALO) become visible in the memory map. These registers are used to erase or to program the Flash EEPROM array which is overlapped by the CALRAM. If the user needs to erase or to program a Flash EEPROM block while the CPU is running, it is necessary to make sure that CPU is running from another Flash EEPROM block or from another memory (e.g. RAM). During erasing or programming a Flash EEPROM block, the block cannot be read due to Flash EEPROM limitations. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CALRAM 2K Recommended Calibration Flow Following flow is recommended to calibrate the 2K byte Flash EEPROM array area. It is assumed that this flow is executed after reset without initialization of the registers INITCRM and CALCFG. 1. Copy a 2K byte block of data from the Flash EEPROM into the 2K byte CALRAM array. Figure 33 shows an example. This is the first step for calibration, but this step may be skipped when initialization for calibration block is not needed. The data to be calibrated in Flash EEPROM has to be located within the 2K byte area which is overlapped by the CALRAM. $0000 2K bytes CALRAM 2K bytes Data to be calibrated Flash EEPROM Block 1 $8000 Copy data from Flash EEPROM to CALRAM Flash EEPROM Block 0 $FFFF MCU Control program is running from this block Figure 33 Copy Data from Flash EEPROM to CALRAM MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. CALRAM 2K Functional Description 2. Initialize the CRAM[15:11] bits and set the CRAMON bit in the register INITCRM to overlap the 2K byte CALRAM array with the Flash EEPROM. Figure 34 shows an example of how to map the CALRAM over the Flash EEPROM. NOTE: Writes to the INITCRM register take one cycle to go into effect. $0000 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... CALRAM is mapped over a 2K area of Flash EEPROM 2K bytes CALRAM Flash EEPROM Block 1 $8000 MCU Control program is running from this block Flash EEPROM Block 0 $FFFF Figure 34 Map CALRAM over Flash EEPROM 3. Calibrate data in the CALRAM The user can start to change data in the CALRAM array for calibration purposes. MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CALRAM 2K 4. Set FSUM in the register CALCFG. After calibration is done, the FSUM bit is written to erase and to program the Flash EEPROM. Setting the FSUM bit enables the flash super user mode and the FADDR (FADDRHI and FADDRLO) and FDATA (FDATAHI and FDATALO) registers become visible in the memory map. Erase/program sequences in the flash super user mode must be used, since writing calibration data area only causes the CALRAM array to be written. See the erase/program sequence in the flash super user mode in page 229. Note that during erasing/programming a Flash EEPROM block, the data contained into the correspondent block cannot be read regardless if it is been overlapped by the CALRAM or not. $0000 Remaining Flash EEPROM cannot be correctly read during erasing or programming 2K bytes CALRAM Flash EEPROM Block 1 $8000 MCU Control program is running from this block Flash EEPROM Block 0 $FFFF Figure 35 An Example Memory Map When Erase/Program Flash EEPROM 5. Erase data in the Flash EEPROM. MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. CALRAM 2K Functional Description 6. Program data contained in the CALRAM with the Flash EEPROM. 7. Clear FSUM in the register CALCFG and clear CRAMON in the register INITCRM. After the FSUM bit is cleared, the Flash EEPROM module exits the flash super user mode and the registers FADDR and FDATA become invisible in the memory map. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... When the CRAMON bit is cleared, the CALRAM array disappears from the 64K byte address space and the calibrated data can be read from Flash EEPROM directly. Figure 36 shows the memory map obtained after calibration. NOTE: Writes to the INITCRM register take one cycle to go into effect. $0000 Calibrated Data programmed into the Flash EEPROM is shown 2K bytes Calibrated Data Flash EEPROM Block 1 $8000 MCU Control program is running from this block Flash EEPROM Block 0 $FFFF Figure 36 Remove CALRAM from memory mapping 8. If needed, continue calibration by repeating from the step 2. MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CALRAM 2K NOTE: During Flash program or erase, data cannot be read from a Flash EEPROM block that is under a erase or program operation. However, it is possible to read from a different block. For example: During erasing or programming the flash block 1, the flash block 1 should not be read while the flash block 0 could still be used for MCU control program storage. Freescale Semiconductor, Inc... Reset Initialization All registers get set/reset asynchronously. MC9S12T64Revision 1.1.1 CALRAM 2K For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Port Integration Module (PIM) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Overview The Port Integration Module establishes the interface between the peripheral modules and the I/O pins for all ports except A, B, E and K. Ports A, B, E and K are handled by the HC12 multiplexed bus interface and described in Multiplexed External Bus Interface (MEBI) section on page 141, due to their tight link with the external bus interface and special modes. The 8-bit port associated with the ATD is included in the ATD module due to their sensitivity to electrical noise, requiring special care on routing and design. This section covers port T connected to the timer module, the serial port S associated with 2 SCI and 1 SPI module and port P connected to the PWM. Each I/O pin is associated with a set of registers which configure items like input/output selection, drive strength reduction, and pull resistors enable and selection. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) The port integration module is device dependant which is reflected in its naming. A standard port has the following minimum features: • • • • Input/output selection 5V output drive with two selectable drive strength 5V digital and analog input Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Input with selectable pull-up or pull-down device Freescale Semiconductor, Inc... Optional features: • Open drain for wired-or connections MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Block Diagram Block Diagram IP-Bus Port Integration Module IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PW0 PW1 PW2 PW3 PW4 PW5 PW6 PW7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 RXD0 TXD0 RXD1 SCI1 TXD1 MISO SPI MOSI SCK SS SCI0 Figure 37 PIM Block Diagram MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PWM Port S Port P Port T ECT Freescale Semiconductor, Inc. Port Integration Module (PIM) External Pin Descriptions All ports start up as general purpose inputs on reset. Table 48 Port Reset State and Priority Summary Reset States Port Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Data Direction input input input Pull Mode hiz pull-up hiz Red. Drive disabled disabled disabled Wired-Or Mode n/a disabled n/a Interrupt n/a n/a n/a Priority T S P ECT > GPIO SCI, SPI > GPIO PWM > GPIO MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Register Map Register Map Register name PTT Bit 7 Read: PTT7 Write: Read: PTIT7 Write: Read: DDRT7 Write: Read: RDRT7 Write: Read: PERT7 Write: Read: PPST7 Write: Read: Write: Read: Write: 0 6 PTT6 PTIT6 5 PTT5 PTIT5 4 PTT4 PTIT4 3 PTT3 PTIT3 2 PTT2 PTIT2 1 PTT1 PTIT1 Bit 0 PTT0 PTIT0 Addr. Offset $00E0 PTIT $00E1 Freescale Semiconductor, Inc... DDRT DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 $00E2 RDRT RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 $00E3 PERT PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 $00E4 PPST PPST6 0 PPST5 0 PPST4 0 PPST3 0 PPST2 0 PPST1 0 PPST0 $00E5 0 Reserved $00E6 Reserved 0 0 0 0 0 0 0 0 $00E7 PTS Read: PTS7 Write: Read: PTIS7 Write: PTS6 PTIS6 PTS5 PTIS5 PTS4 PTIS4 PTS3 PTIS3 PTS2 PTIS2 PTS1 PTIS1 PTS0 PTIS0 $00E8 PTIS $00E9 DDRS Read: DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 $00EA Write: Read: RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 $00EB Write: Read: PERS7 Write: PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 $00EC RDRS PERS = Unimplemented or reserved Figure 38 PIM9T64 Register Map MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Port Integration Module (PIM) Register name Bit 7 Read: PPSS7 Write: 6 5 4 3 2 1 Bit 0 Addr. Offset PPSS PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 $00ED WOMS Read: WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 $00EE Write: Read: Write: 0 0 0 0 0 0 0 0 $00EF Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Reserved Freescale Semiconductor, Inc... PTP Read: PTP7 Write: Read: PTIP7 Write: PTP6 PTIP6 PTP5 PTIP5 PTP4 PTIP4 PTP3 PTIP3 PTP2 PTIP2 PTP1 PTIP1 PTP0 PTIP0 $00F0 PTIP $00F1 DDRP Read: DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 $00F2 Write: Read: RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 $00F3 Write: Read: PERP7 Write: Read: PPSP7 Write: Read: Write: Read: Write: 0 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 $00F4 RDRP PERP PPSP PPSP6 0 PPSP5 0 PPSP4 0 PPSP3 0 PPSP2 0 PPSP1 0 PPSP0 $00F5 0 Reserved $00F6 Reserved 0 0 0 0 0 0 0 0 $00F7 = Unimplemented or reserved Figure 38 PIM9T64 Register Map (Continued) NOTE: Register Address = Base Address (INITRG) + Address Offset MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Register Descriptions Register Descriptions The following table summarizes the effect on the various configuration bits, data direction (DDR), output level (I/O), reduced drive (RDR), pull enable (PE), and polarity select (PS) for the ports. The configuration bit PS is used for the purposing of selecting either a pull-up or pull-down device if PE is active. Freescale Semiconductor, Inc... Table 49 Pin Configuration Summary DDR 0 0 0 1 1 1 1 I/O X X X 0 1 0 1 RDR X X X 0 0 1 1 PE 0 1 1 X X X X PS X 0 1 X X X X Function Input Input Input Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1 Pull Device Disabled Pull Up Pull Down Disabled Disabled Disabled Disabled NOTE: All bits of all registers in this module are completely synchronous to internal clocks during a register read. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Port Integration Module (PIM) Port T I/O Register (PTT) Address Offset: $00E0 Bit 7 Read: Write: ECT: Reset: PTT7 I/OC7 0 6 PTT6 I/OC6 0 5 PTT5 I/OC5 0 4 PTT4 I/OC4 0 3 PTT3 I/OC3 0 2 PTT2 I/OC2 0 1 PTT1 I/OC1 0 Bit 0 PTT0 I/OC0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. Port T Input Register (PTIT) Address Offset: $00E1 Bit 7 Read: Write: Reset: PTIT7 6 PTIT6 - 5 PTIT5 - 4 PTIT4 - 3 PTIT3 - 2 PTIT2 - 1 PTIT1 - Bit 0 PTIT0 - = Reserved or unimplemented Read: Anytime. Write: Never; writes to this register have no effect. This register always reads back the status of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Register Descriptions Port T Data Direction Register (DDRT) Address Offset: $00E2 Bit 7 Read: Write: Reset: DDRT7 0 6 DDRT6 0 5 DDRT5 0 4 DDRT4 0 3 DDRT3 0 2 DDRT2 0 1 DDRT1 0 Bit 0 DDRT0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output. The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In these cases the data direction bits will not change. The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. The timer input capture always monitors the state of the pin. DDRT[7:0] — Data Direction Port T 1 = Associated pin is configured as output. 0 = Associated pin is configured as input. Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Port T Reduced Drive Register (RDRT) Address Offset: $00E3 Bit 7 Read: Write: Reset: RDRT7 0 6 RDRT6 0 5 RDRT5 0 4 RDRT4 0 3 RDRT3 0 2 RDRT2 0 1 RDRT1 0 Bit 0 RDRT0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. RDRT[7:0] — Reduced Drive Port T 1 = Associated pin drives at about 1/3 of the full drive strength. 0 = Full drive strength at output. Port T Pull Device Enable Register (PERT) Address Offset: $00E4 Bit 7 Read: Write: Reset: PERT7 0 6 PERT6 0 5 PERT5 0 4 PERT4 0 3 PERT3 0 2 PERT2 0 1 PERT1 0 Bit 0 PERT0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. PERT[7:0] — Pull Device Enable Port T 1 = Either a pull-up or pull-down device is enabled. 0 = Pull-up or pull-down device is disabled. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Register Descriptions Port T Polarity Select Register (PPST) Address Offset: $00E5 Bit 7 Read: Write: Reset: PPST7 0 6 PPST6 0 5 PPST5 0 4 PPST4 0 3 PPST3 0 2 PPST2 0 1 PPST1 0 Bit 0 PPST0 0 = Reserved or unimplemented Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. PPST[7:0] — Pull Select Port T 1 = A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 0 = A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. Port S I/O Register (PTS) Address Offset: $00E8 Bit 7 Read: Write: SPI/SCI: Reset: PTS7 SS 0 6 PTS6 SCK 0 5 PTS5 MOSI 0 4 PTS4 MISO 0 3 PTS3 TxD1 0 2 PTS2 RxD1 0 1 PTS1 TxD0 0 Bit 0 PTS0 RxD0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) The SPI pins (PS[7:4]) configuration is determined by several status bits in the SPI module. See Serial Peripheral Interface (SPI) section on page 457 for details. The SCI pins associated with transmit pins 3 and 1 are configured as outputs if the transmitter is enabled. The SCI pins associated with receive pins 2 and 0 are configured as inputs if the receiver is enabled. See Serial Communications Interface (SCI) section on page 419 for details. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Port S Input Register (PTIS) Address Offset: $00E9 Bit 7 Read: Write: Reset: PTIS7 6 PTIS6 - 5 PTIS5 - 4 PTIS4 - 3 PTIS3 - 2 PTIS2 - 1 PTIS1 - Bit 0 PTIS0 - = Reserved or unimplemented Read: Anytime. Write: Never; writes to this register have no effect. This register always reads back the status of the associated pins. This also can be used to detect overload or short circuit conditions on output pins. Port S Data Direction Register (DDRS) Address Offset: $00EA Bit 7 Read: Write: Reset: DDRS7 0 6 DDRS6 0 5 DDRS5 0 4 DDRS4 0 3 DDRS3 0 2 DDRS2 0 1 DDRS1 0 Bit 0 DDRS0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Register Descriptions This register configures each port S pin as either input or output. If SPI is enabled, the SPI determines the pin direction. For details see Serial Peripheral Interface (SPI) section on page 457. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled. DDRS[7:0] — Data Direction Port S 1 = Associated pin is configured as output. 0 = Associated pin is configured as input. Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Port S Reduced Drive Register (RDRS) Address Offset: $00EB Bit 7 Read: Write: Reset: RDRS7 0 6 RDRS6 0 5 RDRS5 0 4 RDRS4 0 3 RDRS3 0 2 RDRS2 0 1 RDRS1 0 Bit 0 RDRS0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. RDRS[7:0] — Reduced Drive Port S 1 = Associated pin drives at about 1/3 of the full drive strength. 0 = Full drive strength at output. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Port S Pull Device Enable Register (PERS) Address Offset: $00EC Bit 7 Read: Write: Reset: PERS7 1 6 PERS6 1 5 PERS5 1 4 PERS4 1 3 PERS3 1 2 PERS2 1 1 PERS1 1 Bit 0 PERS0 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as output in wired-or (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. PERS[7:0] — Pull Device Enable Port S 1 = Either a pull-up or pull-down device is enabled. 0 = Pull-up or pull-down device is disabled. Port S Polarity Select Register (PPSS) Address Offset: $00ED Bit 7 Read: Write: Reset: PPSS7 0 6 PPSS6 0 5 PPSS5 0 4 PPSS4 0 3 PPSS3 0 2 PPSS2 0 1 PPSS1 0 Bit 0 PPSS0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Register Descriptions PPSS[7:0] — Pull Select Port S 1 = A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input. 0 = A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input or as wired-or output. Address Offset: $00EE Bit 7 Read: Write: Reset: WOMS7 0 6 WOMS6 0 5 WOMS5 0 4 WOMS4 0 3 WOMS3 0 2 WOMS2 0 1 WOMS1 0 Bit 0 WOMS0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A logic level of ‘1’ is not driven. It applies also to the SPI and SCI outputs and allows a multipoint connection of several serial modules. This bit has no influence on pins used as inputs. WOMS[7:0] — Wired-Or Mode Port S 1 = Output buffers operate as open-drain outputs. 0 = Output buffers operate as push-pull outputs. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Port S Wired-Or Mode Register (WOMS) Freescale Semiconductor, Inc. Port Integration Module (PIM) Port P I/O Register (PTP) Address Offset: $00F0 Bit 7 Read: Write: PWM: Reset: PTP7 PWM7 0 6 PTP6 PWM6 0 5 PTP5 PWM5 0 4 PTP4 PWM4 0 3 PTP3 PWM3 0 2 PTP2 PWM2 0 1 PTP1 PWM1 0 Bit 0 PTP0 PWM0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. The PWM function takes precedence over the general purpose I/O function if the associated PWM channel is enabled. While channels 6–0 are output only if the respective channel is enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. See Pulse Width Modulator (PWM8B8C) section on page 249 for details. Port P Input Register (PTIP) Address Offset: $00F1 Bit 7 Read: Write: Reset: PTIP7 6 PTIP6 - 5 PTIP5 - 4 PTIP4 - 3 PTIP3 - 2 PTIP2 - 1 PTIP1 - Bit 0 PTIP0 - = Reserved or unimplemented Read: Anytime. Write: Never; writes to this register have no effect. This register always reads back the status of the associated pins. This can be also used to detect overload or short circuit conditions on output pins. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Register Descriptions Port P Data Direction Register (DDRP) Address Offset: $00F2 Bit 7 Read: Write: Reset: DDRP7 0 6 DDRP6 0 5 DDRP5 0 4 DDRP4 0 3 DDRP3 0 2 DDRP2 0 1 DDRP1 0 Bit 0 DDRP0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. If the associated PWM channel is enabled this register has no effect on the pins. The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0 channel. Channel 7 can force the pin to input if the shutdown feature is enabled. The DDRP bits revert to controlling the I/O direction of a pin when the associated PWM channel is disabled. DDRP[7:0] — Data Direction Port P 1 = Associated pin is configured as output. 0 = Associated pin is configured as input. Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Port P Reduced Drive Register (RDRP) Address Offset: $00F3 Bit 7 Read: Write: Reset: RDRP7 0 6 RDRP6 0 5 RDRP5 0 4 RDRP4 0 3 RDRP3 0 2 RDRP2 0 1 RDRP1 0 Bit 0 RDRP0 0 = Reserved or unimplemented Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored. RDRP[7:0] — Reduced Drive Port P 1 = Associated pin drives at about 1/3 of the full drive strength. 0 = Full drive strength at output. Port P Pull Device Enable Register (PERP) Address Offset: $00F4 Bit 7 Read: Write: Reset: PERP7 0 6 PERP6 0 5 PERP5 0 4 PERP4 0 3 PERP3 0 2 PERP2 0 1 PERP1 0 Bit 0 PERP0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. PERP[7:0] — Pull Device Enable Port P 1 = Either a pull-up or pull-down device is enabled. 0 = Pull-up or pull-down device is disabled. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) Functional Description Port P Polarity Select Register (PPSP) Address Offset: $00F5 Bit 7 Read: Write: Reset: PPSP7 0 6 PPSP6 0 5 PPSP5 0 4 PPSP4 0 3 PPSP3 0 2 PPSP2 0 1 PPSP1 0 Bit 0 PPSP0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Reserved or unimplemented Freescale Semiconductor, Inc... Read: Anytime. Write: Anytime. This register selects a pull-up or a pull-down device if enabled. PPSP[7:0] — Polarity Select Port P 1 = A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 0 = A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. Functional Description General Each pin can act as general purpose I/O. In addition the pin can act as an output or as an input of a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however certain configurations might not become active. Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a push-pull output. I/O register This register holds the value driven out to the pin if the port is used as a general purpose I/O. Writing to this register has only an effect on the pin MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port Integration Module (PIM) if the port is used as general purpose output. When reading this address, the value of the pins is returned if the data direction register bits are set to 0. If the data direction register bits are set to 1, the contents of the I/O register is returned. This is independent of any other configuration. Input register Data direction register This is a read-only register and always returns the value of the pin. This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored. PTI 0 PT 1 I/O 0 1 DDR do obe mod_en 0 1 MOD PAD Figure 39 Illustration of I/O pin functionality Reduced drive register Pull device enable register Polarity select register If the port is used as an output the register allows the configuration of the drive strength. This register turns on a pull-up or pull-down device. It becomes only active if the pin is used as an input or as a wired-or output. This register selects either a pull-up or pull-down device if enabled. It becomes only active if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-or output. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Port Integration Module (PIM) Low Power Options Port T This port is associated with the Enhanced Capture Timer module. In all modes, port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the Enhanced Capture Timer. During reset, port T pins are configured as high-impedance inputs. Port S Port P This port is associated with the PWM module. In all modes, port P pins PP[7:0] can be used for either general purpose I/O or with the PWM subsystem. If the PWM is enabled the pins become PWM output channels with the exception of pin 7 which can be PWM input or output. During reset, port P pins are configured as high-impedance inputs. Low Power Options Run Mode No low power options exist for this module in run mode. Wait Mode No low power options exist for this module in wait mode. Stop Mode All clocks are stopped. Reset Initialization All registers including the data registers get set/reset asynchronously. MC9S12T64Revision 1.1.1 Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family This port is associated with the serial SCI and SPI modules. In all modes, port S pins PS[7:0] can be used either for general-purpose I/O, or with the SCI and SPI subsystems. During reset, port S pins are configured as inputs with pull-up. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... Port Integration Module (PIM) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Port Integration Module (PIM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Overview This specification describes the function of the Clocks and Reset Generator (CRG) and Oscillator (OSC) modules. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Features The main features of this block are: • Crystal (or ceramic resonator) oscillator (OSC) – User selectable Oscillator type: Colpitts (low power) or Pierce – Clock Monitor (CM) – Startup counter • Phase Locked Loop (PLL) frequency multiplier – Reference divider – Automatic bandwidth control mode for low-jitter operation – Automatic frequency lock detector – CPU interrupt on entry or exit from locked condition – Self clock mode in absence of reference clock • System Clock Generator (CGEN) – External clock mode – Clock switch for either Oscillator or PLL based system clocks – User selectable disabling of clocks during Wait Mode for reduced power consumption. • • Computer Operating Properly (COP) Watchdog Timer with time-out clear window. System Reset generation from the following possible sources – Power on reset – COP reset – Loss of clock reset – External pin reset • Real-Time Interrupt (RTI) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Modes of Operation Modes of Operation This subsection lists and briefly describes all CRG operating modes supported by the CRG. This is a high level description only, detailed descriptions of operating modes are contained in later sections. Run Mode Wait Mode Depending on the configuration of the individual bits in the CLKSEL register this mode allows to disable the system and core clocks. Stop Mode Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode (PSTP=0) and Pseudo Stop Mode (PSTP=1). • Full Stop Mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. • Pseudo Stop Mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set the COP and RTI will continue to run, else they remain frozen. Self Clock Mode Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Self Clock Mode Enable Bit (SCME) are both asserted and the clock monitor detects a loss of clock (external oscillator or crystal). As soon as Self Clock Mode is entered the CRG starts to perform a clock check. Self Clock Mode remains active until the clock check indicates the required quality of the incoming clock signal is met (frequency and amplitude). Self Clock Mode should be used for safety purposes only. It 1. COPCTL register is write once only MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... All functional parts of the CRG are running during Run Mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a non zero value1. Freescale Semiconductor, Inc... Clocks and Reset Generator (CRG) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Block Diagram Block Diagram The block diagram below shows a high level view of the CRG and OSC modules. Power on VREG / LVD Reset Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... CRG RESET Clock and Reset Control Reset Generator System Reset CM fail Clock Monitor XCLKS EXTAL XTAL Clock Quality Checker Bus Clock Core Clock OSC OSCCLK COP RTI Oscillator Clock XFC VDDPLL VSSPLL PLLCLK Registers PLL Figure 40 Block diagram of CRG MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) External Pin Descriptions Overview This section lists and describes the signals that connect off chip. Detailed Signal Descriptions VDDPLL, VSSPLL Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required VDDPLL and VSSPLL must be connected to properly. A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter to eliminate the VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. If PLL usage is not required the XFC pin must be tied to VDDPLL. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... XFC VDDPLL CS MCU RS XFC CP Figure 41 PLL Loop Filter Connections EXTAL, XTAL These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. All the MCU internal system clocks are derived from the EXTAL input frequency. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) External Pin Descriptions NOTE: Crystal circuit is changed from standard! EXTAL CDC * MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal . .Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family C1 Crystal or ceramic resonator Freescale Semiconductor, Inc... Figure 42 Colpitts Crystal Connections (XCLKS=1) EXTAL C1 MCU RS* RB Crystal or ceramic resonator C2 XTAL VSSPLL * Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer’s data. Figure 43 Pierce Oscillator Connections (XCLKS=0) MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) EXTAL MCU CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level) XTAL not connected RESET RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The XCLKS pin is sampled during reset with the rising edge of RESET. Table 50 lists the state coding of the sampled XCLKS signal. XCLKS Table 50 Clock Selection Based on XCLKS at reset XCLKS 1 0 Description Colpitts Oscillator selected Pierce Oscillator / External clock selected MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Figure 44 External Clock Connections (XCLKS=0) Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Map Register Map The register map for the CRG appears below. Register Name SYNR Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: = Reserved or unimplemented 0 LOCK TRACK SCM 0 0 Bit 7 0 6 0 5 SYN5 4 SYN4 3 SYN3 2 SYN2 1 SYN1 Bit 0 SYN0 Address offset $0034 REFDV REFDV3 REFDV2 REFDV1 REFDV0 $0035 Reserved for Factory Test Reads to this register return unpredictable values $0036 CRGFLG RTIF PORLVDRF LOCKIF SCMIF $0037 CRGINT RTIE 0 0 LOCKIE 0 0 SCMIE 0 $0038 CLKSEL PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI $0039 PLLCTL CME PLLON AUTO ACQ 0 PRE PCE SCME $003A RTICTL 0 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 $003B COPCTL WCOP RSBCK 0 0 0 CR2 CR1 CR0 $003C Reserved for Factory Test Reads to this register return unpredictable values $003D Figure 45 CRG Register Map MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 0 0 Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Name Reserved for Factory Test Read: Write: Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Address offset $003E Reads to this register return unpredictable values ARMCOP 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 $003F = Reserved or unimplemented Freescale Semiconductor, Inc... Figure 45 CRG Register Map (Continued) NOTE: Register Address = Base Address (INITRG) + Address Offset Register Descriptions NOTE: All bits of all registers in this module are completely synchronous to internal clocks during a register read. CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLLCLK from the reference frequency by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (fSCM). ( SYNR + 1 ) PLLCLK = 2xOSCCLKx ----------------------------( REFDV + 1 ) NOTE: If PLL is selected (PLLSEL=1)PLLCLK, Bus Clock =PLLCLK/2. Bus Clock must not exceed the maximum operating system frequency . Address Offset: $0034 Bit 7 Read: Write: Reset: 0 0 6 0 0 5 SYN5 0 4 SYN4 0 3 SYN3 0 2 SYN2 0 1 SYN1 0 0 SYN0 0 = Unimplemented or reserved MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions Read: anytime. Write: anytime except if PLLSEL = 1. NOTE: Write to this register initializes the lock detector bit and the track detector bit. Address Offset: $0035 Bit 7 Read: Write: Reset: 0 0 6 0 0 5 0 0 4 0 0 3 REFDV3 0 2 REFDV2 0 1 REFDV1 0 0 REFDV0 0 = Unimplemented or reserved Read: anytime. Write: anytime except when PLLSEL = 1. NOTE: Write to this register initializes the lock detector bit and the track detector bit. CRG Flags Register (CRGFLG) Address Offset: $0037 This register provides CRG status bits and flags. Bit 7 Read: Write: Reset: RTIF 0 6 PORLVDRF (1) 5 0 0 4 LOCKIF 0 3 LOCK 0 2 TRACK 0 1 SCMIF 0 0 SCM 0 = Unimplemented or reserved 1. PORLVDRF set to 1 when a power on reset or low-voltage detection reset occurs. Unaffected by non-POR resets. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... CRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV+1. Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Read: anytime. Write: refer to each bit for write conditions. RTIF — Real Time Interrupt Flag RTIF is set to 1 at the end of every RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 1 = RTI time-out has occurred. 0 = RTI time-out has not yet occurred. PORLVDRF — Power on Reset / Low-Voltage-Detector Reset Flag PORLVDRF is set to 1 when a power on reset or low-voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 1 = Power on reset or a low voltage reset has occurred 0 = Neither power on reset nor low voltage reset has occurred LOCKIF — PLL Lock Interrupt Flag LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request. 1 = LOCK bit has changed. 0 = No change in LOCK bit LOCK — Lock Status Bit LOCK reflects the current state of PLL lock condition. This bit is cleared in Self Clock Mode. Writes have no effect. 1 = PLL VCO is within the desired tolerance of the target frequency. 0 = PLL VCO is not within the desired tolerance of the target frequency. TRACK — Track Status Bit TRACK reflects the current state of PLL track condition. This bit is cleared in Self Clock Mode. Writes have no effect. See Acquisition and Tracking Modes in page 296 for more information. 1 = Tracking mode status. 0 = Acquisition mode status. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions SCMIF — Self-clock mode Interrupt Flag SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request. 1 = SCM condition has changed, either entered or exited self-clock mode. 0 = No change in SCM bit. SCM — Self-clock mode Status Bit Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SCM reflects the current clocking mode. Writes have no effect. 1 = MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency fSCM. See Table 118 in page 582 for the actual value of this parameter. 0 = MCU is operating normally with OSCCLK available. CRG Interrupt Enable Register (CRGINT) Address Offset: $0038 This register enables CRG interrupt requests. Bit 7 Read: Write: Reset: RTIE 0 6 0 0 5 0 0 4 LOCKIE 0 3 0 0 2 0 0 1 SCMIE 0 0 0 0 Read: anytime Write: anytime. RTIE — Real Time Interrupt Enable Bit 1 = Interrupt will be requested whenever RTIF is set. 0 = Interrupt requests from RTI are disabled. LOCKIE — Lock Interrupt Enable Bit 1 = Interrupt will be requested whenever LOCKIF is set. 0 = LOCK interrupt requests are disabled. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) SCMIE — Self-clock mode Interrupt Enable Bit 1 = Interrupt will be requested whenever SCMIF is set. 0 = SCM interrupt requests are disabled. CRG Clock Select Register (CLKSEL) Address Offset: $0039 This register controls CRG clock selection. Read: Write: Reset: PLLSEL 0 PSTP 0 SYSWAI 0 ROAWAI 0 PLLWAI 0 CWAI 0 RTIWAI 0 COPWAI 0 Read: anytime. Write: refer to each bit for individual write conditions. PLLSEL — PLL Select Bit Write: anytime Writing a one when LOCK=0 and AUTO=1, or TRACK=0 and AUTO=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set. 1 = SYSCLK is derived from PLLCLK. (Bus Clock=PLLCLK/2) 0 = SYSCLK is derived from OSCCLK. (Bus Clock=OSCCLK/2) PSTP — Pseudo Stop Bit Write: anytime This bit controls the functionality of the oscillator during Stop Mode. 1 = Oscillator continues to run in Stop Mode (Pseudo Stop). The oscillator amplitude is reduced. 0 = Oscillator is disabled in Stop Mode. NOTE: Pseudo-STOP allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Bit 7 6 5 4 3 2 1 0 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any Electro-Magnetic Susceptibility (EMS) tests. SYSWAI — System clocks stop in WAIT Mode Bit Write: anytime This bit controls the bus clock during Wait Mode. 1 = In Wait Mode, the system clocks stop. 0 = In Wait Mode, the system clocks continue to run. NOTE: RTI and COP are not affected by SYSWAI bit. ROAWAI — Reduced Oscillator Amplitude in WAIT Mode Bit Write: anytime This bit controls oscillator amplitude during Wait Mode. 1 = Reduced oscillator amplitude in Wait Mode. 0 = Normal oscillator amplitude in Wait Mode. NOTE: Lower oscillator amplitude exhibit lower power consumption but could have adverse effects during any Electro-Magnetic Susceptibility (EMS) tests. PLLWAI — PLL stops in WAIT Mode Bit Write: anytime If PLLWAI is set, the CRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit remains set during Wait Mode but the PLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set manually if PLL clock is required. While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting Wait Mode. 1 = PLL stops in Wait Mode. 0 = PLL keeps running in Wait Mode. CWAI — Core stops in WAIT Mode Bit Write: anytime This bit controls the core clock in Wait Mode. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) 1 = Core clock stops in Wait Mode. 0 = Core clock keeps running in Wait Mode. RTIWAI — RTI stops in WAIT Mode Bit Write: anytime 1 = RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode. 0 = RTI keeps running in Wait Mode. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family COPWAI — COP stops in WAIT Mode Bit Freescale Semiconductor, Inc... Write: once 1 = COP stops and initializes the COP dividers whenever the part goes into Wait Mode. 0 = COP keeps running in Wait Mode. CRG PLL Control Register (PLLCTL) Address Offset: $003A This register controls the PLL functionality. Bit 7 Read: Write: Reset: CME 1 6 PLLON 1 5 AUTO 1 4 ACQ 1 3 0 0 2 PRE 0 1 PCE 0 0 SCME 1 Read: anytime. Write: refer to each bit for individual write conditions. CME — Clock Monitor Enable Bit Write: anytime except when SCM = 1 CME enables the clock monitor. 1 = Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock Mode. 0 = Clock monitor is disabled. NOTE: Operating with CME=0 will not detect any loss of clock. In case of poor clock quality this could cause unpredictable operation of the MCU! MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions In Stop Mode (PSTP=0) the clock monitor is disabled independently of the CME bit setting and any loss of clock will not be detected. PLLON — Phase Lock Loop On Bit Write: anytime except when PLLSEL = 1. PLLON turns on the PLL circuitry. In Self Clock Mode, the PLL is turned on, but the PLLON bit reads the last latched value. 1 = PLL is turned on. If AUTO bit is set, the PLL will lock automatically. 0 = PLL is turned off. AUTO — Automatic Bandwidth Control Bit Write: anytime except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1 AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. 1 = Automatic Mode Control is enabled and ACQ bit has no effect. 0 = Automatic Mode Control is disabled and the PLL is under software control, using ACQ bit. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) ACQ — Acquisition Bit Write: anytime. If AUTO =1 this bit has no effect. 1 = High bandwidth filter is selected 0 = Low bandwidth filter is selected PRE — RTI Enable during Pseudo Stop Mode Bit PRE enables the RTI during Pseudo Stop Mode. 1 = RTI continues running during Pseudo Stop Mode. 0 = RTI stops during Pseudo Stop Mode. NOTE: If the PRE bit is cleared the RTI dividers will go static while Pseudo Stop Mode is active. The RTI dividers will not initialize like in Wait Mode with RTIWAI bit set. PCE — COP Enable during Pseudo Stop Mode Bit PCE enables the COP during Pseudo Stop Mode. 1 = COP continues running during Pseudo Stop Mode. 0 = COP stops during Pseudo Stop Mode. NOTE: If the PCE bit is cleared the COP dividers will go static while Pseudo Stop Mode is active. The COP dividers will not initialize like in Wait Mode with COPWAI bit set. SCME — Self-clock mode enable SCME can not be cleared while operating in Self Clock Mode (SCM=1). Write: once 1 = Detection of crystal clock failure forces the MCU in self-clock mode only. 0 = Detection of crystal clock failure causes clock monitor reset. CRG RTI Control Register (RTICTL) Address Offset: $003B This register selects the timeout period for the Real Time Interrupt. Bit 7 Read: Write: 0 6 RTR6 5 RTR5 4 RTR4 3 RTR3 2 RTR2 1 RTR1 0 RTR0 MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions Address Offset: $003B Bit 7 Reset: 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Read: anytime Write: anytime. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family NOTE: A write to this register will initialize the RTI counter. RTR[6:4] — Real Time Interrupt Prescale Rate Select Bits These bits select the prescale rate for the RTI. See Table 51. RTR[3:0] — Real Time Interrupt Modulus Counter Select These bits select the modulus counter target value to provide additional granularity. See Table 51. Table 51 shows all possible divide values selectable by the RTICTL register. The source clock for the RTI is OSCCLK. Table 51 RTI Frequency Divide Rates RTR[6:4] = Freescale Semiconductor, Inc... RTR[3:0] 0 (÷1) 1 (÷2) 2 (÷3) 3 (÷4) 4 (÷5) 5 (÷6) 6 (÷7) 7 (÷8) 8 (÷9) 9 (÷10) 10 (÷11) 11 (÷12) 12 (÷13) 000 (OFF) OFF (1)(2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) OFF (2) 001 (210) 210 2x210 3x210 4x210 5x210 6x210 7x210 8x210 9x210 10x210 11x210 12x210 13x210 010 (211) 211 2x211 3x211 4x211 5x211 6x211 7x211 8x211 9x211 10x211 11x211 12x211 13x211 011 (212) 212 2x212 3x212 4x212 5x212 6x212 7x212 8x212 9x212 10x212 11x212 12x212 13x212 100 (213) 213 2x213 3x213 4x213 5x213 6x213 7x213 8x213 9x213 10x213 11x213 12x213 13x213 101 (214) 214 2x214 3x214 4x214 5x214 6x214 7x214 8x214 9x214 10x214 11x214 12x214 13x214 110 (215) 215 2x215 3x215 4x215 5x215 6x215 7x215 8x215 9x215 10x215 11x215 12x215 13x215 111 (216) 216 2x216 3x216 4x216 5x216 6x216 7x216 8x216 9x216 10x216 11x216 12x216 13x216 MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 51 RTI Frequency Divide Rates (Continued) RTR[6:4] = RTR[3:0] 13 (÷14) 14 (÷15) 15 (÷16) 000 (OFF) OFF (2) OFF (2) OFF (2) 001 (210) 14x210 15x210 16x210 010 (211) 14x211 15x211 16x211 011 (212) 14x212 15x212 16x212 100 (213) 14x213 15x213 16x213 101 (214) 14x214 15x214 16x214 110 (215) 14x215 15x215 16x215 111 (216) 14x216 15x216 16x216 1. Denotes default value out of reset Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 2. These values should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions CRG COP Control Register (COPCTL) Address Offset: $003C This register controls the COP (Computer Operating Properly) watchdog. Bit 7 Read: Write: Reset: WCOP 0 6 RSBCK 1 5 0 0 4 0 0 3 0 0 2 CR2 0 1 CR1 1 0 CR0 1 Read: anytime. Write: once WCOP — Window COP mode Bit When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts and the user must wait until the next window before writing to ARMCOP. Table 52 shows the exact duration of this window for the seven available COP rates. 1 = Window COP operation 0 = Normal COP operation RSBCK — COP and RTI stop in Active BDM Bit 1 = Stops the COP and RTI counters whenever the part is in Active background debug mode. 0 = Allows the COP and RTI to keep running in Active background debug mode. CR[2:0] — COP Watchdog Timer Rate select These bits select the COP time-out rate (see Table 52). The COP time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) re-initializing the COP counter via the ARMCOP register. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 52 COP Watchdog Rates(1) CR2 0 0 0 0 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 Divide OSCCLK by OFF 2 14 2 16 2 18 2 22 2 23 2 24 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 1 1 1 1 2 20 1. Times are referenced from the previous COP time-out reset (writing $55/$AA to the ARMCOP register) CRG COP Timer Arm/Reset Register (ARMCOP) Address Offset: $003F This register is used to restart the COP time-out period. Bit 7 Read: Write: Reset: 0 Bit 7 0 6 0 Bit 6 0 5 0 Bit 5 0 4 0 Bit 4 0 3 0 Bit 3 0 2 0 Bit 2 0 1 0 Bit 1 0 0 0 Bit 0 0 Read: always reads $00. Write: anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period you must write $55 followed by a write of $AA. Other instructions may be executed between these writes but the sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of $55 writes or sequences of $AA writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description General This section provides a complete functional description of the CRG. It gives detailed informations on the internal operation of the design. Functional Blocks Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Oscillator (OSC) The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of Colpitts oscillator or Pierce Oscillator/External clock depends on the XCLKS signal which is sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback and can be buffered to drive other devices with same voltage amplitude. A buffered EXTAL signal, OSCCLK, becomes the internal reference clock. The oscillator is enabled based on the PSTP bit, and the STOP condition. The oscillator is disabled when the part is in STOP mode except when Pseudo-Stop mode is enabled. To improve noise immunity, the oscillator is powered by the VDDPLL and VSSPLL power supply pins. The Colpitts oscillator is equipped with a feedback system which does not waste current generating harmonics. Its configuration is “Colpitts oscillator with translated ground”. The transconductor used is driven by a current source under the control of a peak detector which will measure the amplitude of the AC signal appearing on EXTAL node in order to implement an Amplitude Limitation Control (ALC) loop. The ALC loop is in charge of reducing the quiescent current in the transconductor as a result of an increase in the oscillation amplitude. The Pierce Oscillator can be used for higher frequencies than possible with the Colpitts oscillator. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description Phase Locked Loop (PLL) The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6, ...,126,128 based on the SYNR register. [ SYNR + 1 ] PLLCLK = 2 × OSCCLK × ----------------------------[ REFDV + 1 ] NOTE: The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency fSCM. REFERENCE EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL OSCCLK REFDV FEEDBACK LOCK DETECTOR LOCK REFERENCE PROGRAMMABLE DIVIDER VDDPLL/VSSPLL PDET PHASE DETECTOR UP DOWN CPUMP VCO CLOCK MONITOR LOOP PROGRAMMABLE DIVIDER SYN VDDPLL LOOP FILTER XFC PIN PLLCLK supplied by: VDDPLL/VSSPLL VDD/VSS Figure 46 PLL Functional Diagram PLL Operation The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 16 (REFDV+1) to MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. If PLLSEL=1, Bus Clock = PLLCLK/2. Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) output the REFERENCE clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR +1)] to output the FEEDBACK clock. See Figure 46. The phase detector then compares the FEEDBACK clock, with the REFERENCE clock. Correction pulses are generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the next subsection. The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL. Acquisition and Tracking Modes The lock detector compares the frequencies of the FEEDBACK clock, and the REFERENCE clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison1. The PLL filter can be manually or automatically configured into one of two possible operating modes: • Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register. • Tracking mode 1. See Table 118 in page 582 for actual values of the parameters mentioned in this section. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as the source for the system and core clocks. If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO=1): • • • The TRACK bit is a read-only indicator of the mode of the filter. The LOCK bit is a read-only indicator of the locked state of the PLL. CPU interrupts can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in manual mode: MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode. After turning on the PLL by setting the PLLON bit software must wait a given time before entering tracking mode (ACQ = 0). After entering tracking mode software must wait a given time before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1). Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family • • Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description System Clocks Generator PLLSEL or SCM PHASE LOCK LOOP PLLCLK 1 0 SYSCLK WAIT(CWAI,SYSWAI), STOP Core Clock Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... WAIT(SYSWAI), STOP SCM ÷2 EXTAL OSCILLATOR OSCCLK 1 0 WAIT(RTIWAI), STOP(PSTP,PRE), RTI enable CLOCK PHASE GENERATOR Bus Clock RTI XTAL WAIT(COPWAI), STOP(PSTP,PCE), COP enable Clock Monitor COP WAIT(SYSWAI), STOP Oscillator Clock STOP(PSTP) Gating Condition = Clock Gate Oscillator * Clock (running during Pseudo Stop Mode * This clock is not used in the current MCU. Figure 47 Clock Generator The clock generator creates the clocks used in the MCU (see Figure 47). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the setting of the respective configuration bits. For example, a WAIT(SYSWAI) gating condition states that when the SYSWAI bit is set, the correspondent gate will be disabled during WAIT mode. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. The memory blocks use the Bus Clock. If the MCU enters Self Clock Mode (see Self Clock Mode in page 305) Oscillator clock source is switched to PLLCLK running at its minimum frequency fSCM. The Bus Clock is used to generate the clock visible at the ECLK pin. The Core Clock signal is the clock for the HCS12 core.The Core Clock is twice the Bus Clock as shown in Figure 48. But note that a CPU cycle corresponds to one Bus Clock. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. CORE CLOCK: BUS CLOCK / ECLK Figure 48 Core Clock and Bus Clock relationship Clock Monitor (CM) The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure which asserts self clock mode or generates a system reset depending on the state of SCME bit in the PLLCTL register (page 286). If the SCME bit is cleared, CRG generates a Clock Monitor Reset; otherwise, it enters Self Clock Mode. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function is enabled/disabled by the CME control bit. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description Clock Quality Checker Check window 1 VCO Clock 12345 OSCCLK 4095 OSCCLK OK . Figure 49 Check Window definition 4096 2 3 49999 50000 A clock quality check is triggered by any of the following events: • • • • Power-on Reset (POR) Low Voltage Detection Reset (LVDR) Wake-up from Full Stop Mode (Exit_Full_Stop) Clock Monitor fail indication (CM_Fail) 1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker provides a more accurate check in addition to the clock monitor. The clock quality checker expects a valid OSCLK to have 4096 rising OSCCLK edges within a time window of 50 000 VCO clock cycles1 (See Figure 49). This time window is called check window. If the requested number of 4096 rising OSCCLK edges occur within the check window, the quality of the OSCCLK is considered to be valid and the OSCCLK becomes the source for systems and core clocks. Note that if 4096 OSCCLK edges are counted within the check window, the check window is immediately terminated. Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) CLOCK OK POR | LVDR or Exit_Full_Stop num=0 CM_Fail Clock Monitor Reset Enter SCM yes no num=50 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SCM active? check window num=num+1 yes yes no OSCCLK OK? yes SCM active? no num X X No action, clock loss not detected. Clock failure --> 0 X CRG performs Clock Monitor Reset immediately MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 54 Outcome of Clock Loss in Wait Mode (Continued) CME SCME SCMIE CRG Actions Clock failure --> Scenario 1: OSCCLK recovers prior to exiting Wait Mode. - MCU remains in Wait Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag. Some time later OSCCLK recovers. - CM no longer indicates a failure, - 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., - SCM deactivated, - PLL disabled depending on PLLWAI, - VREG remains enabled (never gets disabled in Wait Mode). - MCU remains in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Wait Mode using OSCCLK as system clock (SYSCLK), - Continue normal operation. 1 1 0 or an External Reset is applied. - Exit Wait Mode using OSCCLK as system clock, - Start reset sequence. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Scenario 2: OSCCLK does not recover prior to exiting Wait Mode. - MCU remains in Wait Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag, - Keep performing Clock Quality Checks (could continue infinitely) while in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Start reset sequence, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Low Power Options Table 54 Outcome of Clock Loss in Wait Mode (Continued) CME SCME SCMIE CRG Actions Clock failure --> - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - SCMIF set. 1 1 SCMIF generates Self Clock Mode wakeup interrupt. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 1 Freescale Semiconductor, Inc... - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. CPU Stop Mode All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in Pseudo-Stop Mode. In addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual powersaving modes (if available). This is the main difference between Pseudo-Stop Mode and Wait Mode. After executing the STOP instruction the core requests the CRG to switch the MCU into Stop Mode. If the PLLSEL bit is still set when entering Stop-Mode, the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally disables the remaining system clocks. As soon as all clocks are switched off Stop-Mode is active. If Pseudo-Stop Mode (PSTP=1) is entered from Self-Clock Mode the CRG will continue to check the clock quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If Full-Stop Mode (PSTP=0) is entered from Self-Clock Mode an ongoing clock quality check will be stopped. A complete timeout window check will be started when Stop Mode is left again. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Wake-up from Stop-Mode also depends on the setting of the PSTP bit. Core req’s Stop Mode. Clear PLLSEL, Disable PLL Wait Mode left due to external reset Exit Wait w. ext.RESET Enter Stop Mode Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... no INT ? yes no PSTP=1 ? yes CME=1 ? yes no no INT ? yes no CLOCK OK ? CM fail ? yes no Exit Stop w. CMR no SCME=1 ? yes yes Exit Stop w. CMR no SCME=1 ? yes Exit Stop Mode SCMIE=1 ? Generate SCM Interrupt (Wakeup from Stop) yes Exit Stop Mode no Exit Stop Mode Exit Stop Mode no SCM=1 ? yes Enter SCM Enter SCM Enter SCM Continue w. normal OP Clocks OK ? Stands for a Clock Quality Check Figure 54 Stop Mode Entry/Exit Sequence MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Low Power Options Wake-up from Pseudo-Stop (PSTP=1) Wake-up from Pseudo-Stop is the same as wake-up from Wait-Mode. There are also five different scenarios for the CRG to restart the MCU from Pseudo-Stop Mode: • • • External Reset Clock Monitor Fail Wake-up Interrupt If the clock monitor is enabled (CME=1) the MCU is able to leave Pseudo-Stop Mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMR). The CRG’s behavior for CMR is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the interrupt the CRG enters Self-Clock Mode and starts the clock quality checker (see Clock Quality Checker in page 301). Then the MCU continues with normal operation. If the SCM interrupt is blocked by SCMIE=0, the SCMIF flag will be asserted but the CRG will not wake-up from Pseudo-Stop Mode. If any other interrupt source (e.g. RTI) triggers exit from Pseudo-Stop Mode, the MCU immediately continues with normal operation. Because the PLL has been powered-down during Stop-Mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving Stop-Mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 55 summarizes the outcome of a clock loss while in Pseudo-Stop Mode. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... If the MCU gets an external reset during Pseudo-Stop Mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Pseudo-Stop Mode is left and the MCU is in Run Mode again. Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 55 Outcome of Clock Loss in Pseudo-Stop Mode CME 0 1 SCME SCMIE CRG Actions Clock failure --> X X No action, clock loss not detected. Clock failure --> 0 X CRG performs Clock Monitor Reset immediately MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Low Power Options Table 55 Outcome of Clock Loss in Pseudo-Stop Mode (Continued) CME SCME SCMIE CRG Actions Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode. - MCU remains in Pseudo-Stop Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag. Some time later OSCCLK recovers. - CM no longer indicates a failure, - 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., - SCM deactivated, - PLL disabled, - VREG disabled. - MCU remains in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Pseudo-Stop Mode using OSCCLK as system clock (SYSCLK), - Continue normal operation. 1 1 0 or an External Reset is applied. - Exit Pseudo-Stop Mode using OSCCLK as system clock, - Start reset sequence. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Scenario 2: OSCCLK does not recover prior to exiting Pseudo-Stop Mode. - MCU remains in Pseudo-Stop Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag, - Keep performing Clock Quality Checks (could continue infinitely) while in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock - Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock - Start reset sequence, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 55 Outcome of Clock Loss in Pseudo-Stop Mode (Continued) CME SCME SCMIE CRG Actions Clock failure --> - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - SCMIF set. 1 1 SCMIF generates Self Clock Mode wakeup interrupt. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 1 Freescale Semiconductor, Inc... - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. Wake-up from Full Stop (PSTP=0) The MCU requires an external interrupt or an external reset in order to wake-up from Stop-Mode. If the MCU gets an external reset during Full Stop Mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check windows (see Clock Quality Checker in page 301). After completing the clock quality check the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Full Stop-Mode is left and the MCU is in Run Mode again. If the MCU is woken-up by an interrupt, the CRG will also perform a maximum of 50 clock check windows (see Clock Quality Checker in page 301). If the clock quality check is successful, the CRG will release all system and core clocks and will continue with normal operation. If all clock checks within the Timeout-Window are failing, the CRG will switch to Self-Clock Mode or generate a clock monitor reset (CMR) depending on the setting of the SCME bit in the PLLCTL register (page 286). If the SCME bit is cleared, CRG generates a Clock Monitor Reset; otherwise, it enters Self Clock Mode. Because the PLL has been powered-down during Stop-Mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving Stop-Mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... NOTE: Freescale Semiconductor, Inc. In Full Stop Mode the clock monitor is disabled and any loss of clock will not be detected. Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Clocks and Reset Generator (CRG) Low Power Options MC9S12T64Revision 1.1.1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Reset Description General This section describes how to reset the CRG and how the CRG itself controls the reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part of the CRG this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Register Descriptions in page 280. All reset sources are listed in Table 56. Refer to MCU specification for related vector addresses and priorities. Table 56 Reset Summary Vector Address Reset Source Power-on Reset $FFFE, $FFFF LVD Reset External Reset $FFFC, $FFFD $FFFA, $FFFB Clock Monitor Reset COP Watchdog Reset Local Enable None LVDCR (LVDE=1 and LVDRE=1) None PLLCTL (CME=1, SCME=0) COPCTL (CR[2:0] nonzero) Description of Reset Operation The reset sequence is initiated by any of the following events: • • • • • Low level is detected at the RESET pin (External Reset). Power-on is detected. (Power-on Reset - POR) Low voltage condition is detected. (Low Voltage Detection Reset LVDR) COP watchdog times out. (COP reset - COPR) Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0). (Clock Monitor Reset - CMR) Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see Figure 55). Since entry into reset is asynchronous it does not require a running SYSCLK. However, the internal reset circuit of the CRG cannot sequence out of current reset condition without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n=3 to 6 additional SYSCLK cycles MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Reset Description depending on the internal synchronization latency. After 128+n SYSCLK cycles the RESET pin is released. The reset generator circuit of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Table 57 shows which vector will be fetched. Table 57 Reset Vector Selection Sampled RESET pin (64 SYSCLK cycles after release) 1 1 1 Clock Monitor Reset pending COP Reset pending Vector fetch Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 0 1 0 0 X 1 POR / LVDR / External Reset Clock Monitor Reset COP Reset POR / LVDR / External Reset with rise of RESET pin 0 X X NOTE: External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 64 SYSCLK cycles after the low drive is released. The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is negated synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (External Reset), the internal reset remains asserted too. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) RESET )( )( RESET pin released CRG drives RESET pin low SYSCLK ) ( 128+n cycles ) ( 64 cycles ) ( Figure 55 RESET Timing Clock Monitor Reset The CRG generates a Clock Monitor Reset in case all of the following conditions are true: • • • Clock monitor is enabled (CME=1) Loss of clock is detected Self-Clock Mode is disabled (SCME=0). The reset event asynchronously forces the configuration registers to their default settings (see Register Descriptions in page 280). In detail the CME and the SCME are reset to logical “1” (which doesn’t change the state of the CME bit, because it has already been set). As a consequence the CRG immediately enters Self Clock Mode and starts its internal reset sequence. The clock quality check starts in parallel. As soon as the clock quality check indicates a valid OSCCLK, CRG switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running in parallel to the reset generator, the CRG may leave Self Clock Mode while still completing the internal reset sequence, e.g. when a high frequency OSCCLK is provided. When the reset sequence is finished the CRG checks the internally latched state of the clock monitor fail circuit. If a clock monitor fail is indicated processing begins by fetching the Clock Monitor Reset vector. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... eventually SYSCLK not running with n being min 3 / max 4 cycles depending on internal synchronization delay eventually RESET driven low externally Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Reset Description Computer Operating Properly Watchdog (COP) Reset When COP is enabled, the CRG expects sequential write of $55 and $AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than $55 or $AA is written, the CRG immediately generates a reset. In case window COP operation is enabled writes ($55 or $AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Low Voltage Detection Reset The CRG generates a Low Voltage Detection Reset in case all of the following conditions are true: • • VDDR voltage falls to VLVR level and remains at or below that level for 17 or more consecutive bus clock cycles. The LVD reset enable bit (LVDRE) in the LVDCR register is set. As showed in Figure 50, after a LVD reset occurs, the CRG will perform a maximum of 50 check windows before entering Self Clock Mode and executing the reset sequence. If OSCCLK is considered valid before 50 check windows are complete, the clock quality check is successfully terminated and reset sequence is executed. More details about the LVD module can be found in the section in page 185. Power-On Reset The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power on reset. As soon as a power on reset is triggered the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50 check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts using Self-Clock Mode. See Figure 50. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Figure 56 and Figure 57 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low. Note that the reset sequence only starts after a running SYSCLK is detected. RESET Clock Quality Check (no Self-Clock Mode) )( Freescale Semiconductor, Inc... Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 56 RESET pin tied to VDD (by a pull-up resistor) RESET Clock Quality Check (no Self Clock Mode) )( Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 57 RESET pin held low externally NOTE: NOTE: Proper function of the LVD module requires the voltage regulator to be enable during operation (VREGEN pin tied high). POR is only rearmed if the VDD voltage falls below the POR rearm level (VPOR 1). There are four possible combinations of PORLVDRF (CRGFLG register) and LVDF (LVDSR register) flags that can be obtained during operation. 1. See Table 116 in page 578 for the actual values of these parameters. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Reset Description These combinations are shown in Table 58 with the correspondent events that caused them to be set. PORLVDRF is set when a power-on or a low-voltage reset occurs, while LVDF is set when a low-voltage condition is detected. Table 58 Relation between PORLVDRF and LVDF PORLVDRF 0 LVDF 0 Event Neither POR nor LVDR occurred. No low-voltage condition detected(1) Neither POR nor LVDR occurred. Low-voltage condition detected but LVD reset not enabled (LVDRE=0)(1) POR occurred LVDR occurred 0 1 1 1 0 1 1. Considering that PORLVDRF and LVDF flags were cleared by the program after POR or LVDR. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Interrupts General This section describes all interrupts originated by the CRG. The interrupts/reset vectors requested by the CRG are listed in Table 59. Table 59 CRG Interrupt Vectors Vector Address $FFF0, $FFF1 $FFC6, $FFC7 $FFC4, $FFC5 Interrupt Source Real Time interrupt LOCK interrupt SCM interrupt CCR Mask I bit I bit I bit Local Enable CRGINT (RTIE) CRGINT (LOCKIE) CRGINT (SCMIE) Description of Interrupt Operation Real Time Interrupt The CRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from Pseudo Stop if the RTI interrupt is enabled. PLL Lock Interrupt The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit. MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Interrupts Self Clock Mode Interrupt The CRG generates a Self Clock Mode interrupt when the SCM condition of the system has changed, either entered or exited Self Clock Mode. SCM conditions can only change if the Self Clock Mode enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after Power-on-Reset (POR) or recovery from Full Stop Mode (PSTP=0) or Clock Monitor failure. For details on the clock quality check refer to Clock Quality Checker in page 301. If the clock monitor is enabled (CME=1) a loss of external clock will also cause a SCM condition (SCME=1). SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt flag (SCMIF) is set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Clocks and Reset Generator (CRG) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Overview The PWM_8B8C definition is based on the MC68HC11KD2 and the HC12 PWM definitions. This PWM_8B8C contains the basic features from the HC11 with some of the enhancements incorporated on the HC12. In addition, the module is now expanded to eight channels with independent control of left and center aligned outputs on each channel. In all basic functionality, it will behave similarly to the HC11 PWM with the additional HC12 PWM features of center aligned output mode and four available clock sources. The PWM_8B8C module contains eight channels. Each of these channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs. Features • • • • • Eight independent PWM channels with programmable period and duty cycle. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Dedicated counter for each PWM channel. Programmable PWM enable/disable for each channel. Software selection of PWM duty pulse polarity for each channel. Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches zero) or when the channel is disabled. Programmable center or left aligned outputs on individual channels. Eight 8-bit channel or four 16-bit channel PWM resolution. Four clock sources (A, B, SA and SB) provide for a wide range of frequencies. Programmable Clock Select Logic. Emergency shutdown. • • • • • Modes of Operation Normal Modes The PWM module behaves as described within this specification in all normal modes. Special Modes The PWM module behaves as described within this specification in all special modes. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Modes of Operation WARNING: While in special modes, do not access registers $0006, $0007, $000A and $000B. Writing to any of these registers can alter the PWM functionality. Freeze Mode The PWM module enters freeze mode when background debug mode (BDM) is active. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Emulation Modes Freescale Semiconductor, Inc... In Freeze Mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal program flow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Block Diagram PWM_8B8C PWM Channels Channel 7 Period and Duty Counter PWM7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Channel 6 PWM6 Counter Bus Clock Clock select PWM Clock Period and Duty Channel 5 Period and Duty Control Channel 4 Period and Duty Counter Counter PWM5 PWM4 Channel 3 Enable Period and Duty Counter PWM3 Polarity Channel 2 Period and Duty Counter PWM2 Alignment Channel 1 Period and Duty Channel 0 Period and Duty Counter Counter PWM1 PWM0 Figure 58 PWM8B8C Block Diagram MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) External Pin Descriptions External Pin Descriptions The PWM8B8C module has a total of 8 external pins. PWM7 (PP7) PWM8B8C Channel 7 - This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown feature. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PWM6 (PP6) PWM8B8C Channel 6 - This pin serves as waveform output of PWM channel 6. PWM5 (PP5) PWM8B8C Channel 5 - This pin serves as waveform output of PWM channel 5. PWM4 (PP4) PWM8B8C Channel 4 - This pin serves as waveform output of PWM channel 4. PWM3 (PP3) PWM8B8C Channel 3 - This pin serves as waveform output of PWM channel 3. PWM2 (PP2) PWM8B8C Channel 2 - This pin serves as waveform output of PWM channel 2. PWM1 (PP1) PWM8B8C Channel 1 - This pin serves as waveform output of PWM channel 1. PWM0 (PP0) PWM8B8C Channel 0 - This pin serves as waveform output of PWM channel 0. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Map This section describes the content of the registers in the PWM. The figure below shows the registers associated with the PWM and their relative offset from the base address. The register detail description follows the order they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shaded bits. Register Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL Reserved for Factory Test Reserved for Factory Test PWMSCLA PWMSCLB Reserved for Factory Test Reserved for Factory Test PWMCNT0 PWMCNT1 Bit 7 Read: PWME7 Write: Read: PPOL7 Write: Read: PCLK7 Write: Read: 0 Write: Read: CAE7 Write: Read: CON67 Write: Read: Write: Read: Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Write: Read: Write: Read: Bit 7 Write: 0 Read: Bit 7 Write: 0 Bit 6 PWME6 PPOL6 PCLKL6 PCKB2 CAE6 CON45 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ BIt 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 Address Offset $00A0 $00A1 $00A2 $00A3 $00A4 $00A5 $00A6 $00A7 Bit 0 Bit 0 $00A8 $00A9 $00AA $00AB Bit 0 0 Bit 0 0 $00AC $00AD Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Reads to this register return unpredictable values. Reads to this register return unpredictable values. 6 6 5 5 4 4 3 3 2 2 1 1 Reads to this register return unpredictable values. Reads to this register return unpredictable values. 6 0 6 0 5 0 5 0 4 0 4 0 3 0 3 0 2 0 2 0 1 0 1 0 = Unimplemented Figure 59 PWM Register Map MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Map Register Name PWMCNT2 PWMCNT3 PWMCNT4 PWMCNT5 PWMCNT6 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Bit 2 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BIt 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Address Offset $00AE $00AF $00B0 $00B1 $00B2 $00B3 $00B4 $00B5 $00B6 $00B7 $00B8 $00B9 $00BA $00BB $00BC $00BD $00BE $00BF $00C0 $00C1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PWMCNT7 PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 = Unimplemented Figure 59 PWM Register Map (Continued) MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Name PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: PWMIF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 PWMIE 0 0 0 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 0 0 0 0 Bit 2 2 2 PWM7IN 0 0 0 BIt 1 1 1 Bit 0 Bit 0 Bit 0 Address Offset $00C2 $00C3 $00C4 $00C5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 0 PWMLVL PWMRSTRT 0 0 0 0 0 0 PWM7INL PWM7ENA 0 0 0 0 0 0 $00C6 $00C7 Freescale Semiconductor, Inc... Reserved = Unimplemented Figure 59 PWM Register Map (Continued) NOTE: Register Address = Base Address (INITRG) + Address Offset Register Descriptions This section describes in detail all the registers and register bits in the PWM module. NOTE: All bits of all registers in this module are completely synchronous to internal clocks during a register read. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions PWM Enable Register (PWME) Address Offset: $00A0 Bit 7 Read: Write: Reset: PWME7 0 6 PWME6 0 5 PWME5 0 4 PWME4 0 3 PWME3 0 2 PWME2 0 1 PWME1 0 Bit 0 PWME0 0 The first PWM cycle after enabling the channel can be irregular. An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register) then enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all eight PWM channels are disabled PWMEx=0), the prescaler counter shuts off for power savings. Read: anytime Write: anytime PWME7 — Pulse Width Channel 7 Enable 1 = Pulse Width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit7 when its clock source begins its next cycle. 0 = Pulse Width channel 7 is disabled. PWME6 — Pulse Width Channel 6 Enable MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx=1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) 1 = Pulse Width channel 6 is enabled. The pulse modulated signal becomes available at port PWM output bit6 when its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output bit6 is disabled. 0 = Pulse Width channel 6 is disabled. PWME5 — Pulse Width Channel 5 Enable 1 = Pulse Width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when its clock source begins its next cycle. 0 = Pulse Width channel 5 is disabled. PWME4 — Pulse Width Channel 4 Enable 1 = Pulse Width channel 4 is enabled. The pulse modulated signal becomes available at PWM output bit 4 when its clock source begins its next cycle. If CON45=1, then bit has no effect and PWM output bit4 is disabled. 0 = Pulse Width channel 4 is disabled. PWME3 — Pulse Width Channel 3 Enable 1 = Pulse Width channel 3 is enabled. The pulse modulated signal becomes available at PWM output bit 3 when its clock source begins its next cycle. 0 = Pulse Width channel 3 is disabled. PWME2 — Pulse Width Channel 2 Enable 1 = Pulse Width channel 2 is enabled. The pulse modulated signal becomes available at PWM output bit 2 when its clock source begins its next cycle. If CON23=1, then bit has no effect and PWM output bit2 is disabled. 0 = Pulse Width channel 2 is disabled. PWME1 — Pulse Width Channel 1 Enable 1 = Pulse Width channel 1 is enabled. The pulse modulated signal becomes available at PWM output bit 1 when its clock source begins its next cycle. 0 = Pulse Width channel 1 is disabled. PWME0 — Pulse Width Channel 0 Enable MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions 1 = Pulse Width channel 0 is enabled. The pulse modulated signal becomes available at PWM, o/p bit 0 when its clock source begins its next cycle. If CON01=1, then bit has no effect and PWM output bit0 is disabled. 0 = Pulse Width channel 0 is disabled. PWM Polarity Register (PWMPOL) Address Offset: $00A1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Bit 7 Read: Write: Reset: PPOL7 0 6 PPOL6 0 5 PPOL5 0 4 PPOL4 0 3 PPOL3 0 2 PPOL2 0 1 PPOL1 0 Bit 0 PPOL0 0 The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. Read: anytime Write: anytime CAUTION: PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. PPOL7 — Pulse Width Channel 7 Polarity 1 = PWM channel 7 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 7 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL6 — Pulse Width Channel 6 Polarity MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) 1 = PWM channel 6 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 6 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL5 — Pulse Width Channel 5 Polarity 1 = PWM channel 5 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 5 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL4 — Pulse Width Channel 4 Polarity 1 = PWM channel 4 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 4 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL3 — Pulse Width Channel 3 Polarity 1 = PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL2 — Pulse Width Channel 2 Polarity 1 = PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL1 — Pulse Width Channel 1 Polarity 1 = PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL0 — Pulse Width Channel 0 Polarity 1 = PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions PWM Clock Select Register (PWMCLK) Address Offset: $00A2 Bit 7 Read: Write: Reset: PCLK7 0 6 PCLKL6 0 5 PCLK5 0 4 PCLK4 0 3 PCLK3 0 2 PCLK2 0 1 PCLK1 0 Bit 0 PCLK0 0 Read: anytime Write: anytime CAUTION: Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. PCLK7 — Pulse Width Channel 7 Clock Select 1 = Clock SB is the clock source for PWM channel 7. 0 = Clock B is the clock source for PWM channel 7. PCLK6 — Pulse Width Channel 6 Clock Select 1 = Clock SB is the clock source for PWM channel 6. 0 = Clock B is the clock source for PWM channel 6. PCLK5 — Pulse Width Channel 5 Clock Select 1 = Clock SA is the clock source for PWM channel 5. 0 = Clock A is the clock source for PWM channel 5. PCLK4 — Pulse Width Channel 4 Clock Select 1 = Clock SA is the clock source for PWM channel 4. 0 = Clock A is the clock source for PWM channel 4. PCLK3 — Pulse Width Channel 3 Clock Select 1 = Clock SB is the clock source for PWM channel 3. 0 = Clock B is the clock source for PWM channel 3. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below. Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) PCLK2 — Pulse Width Channel 2 Clock Select 1 = Clock SB is the clock source for PWM channel 2. 0 = Clock B is the clock source for PWM channel 2. PCLK1 — Pulse Width Channel 1 Clock Select 1 = Clock SA is the clock source for PWM channel 1. 0 = Clock A is the clock source for PWM channel 1. PCLK0 — Pulse Width Channel 0 Clock Select 1 = Clock SA is the clock source for PWM channel 0. 0 = Clock A is the clock source for PWM channel 0. PWM Prescale Clock Select Register (PWMPRCLK) Address Offset: $00A3 Bit 7 Read: Write: Reset: 0 0 6 PCKB2 0 5 PCKB1 0 4 PCKB0 0 3 0 0 2 PCKA2 0 1 PCKA1 0 Bit 0 PCKA0 0 = Reserved or unimplemented This register selects the prescale clock source for clocks A and B independently. Read: anytime Write: anytime CAUTION: PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. PCKB2–PCKB0 — Prescaler Select for Clock B Clock B is one of two clock sources which can be used for channels 2, 3, 6, or 7. These three bits determine the rate of clock B, as shown in the following table. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions Table 60 Clock B Prescaler Selects PCKB2 0 0 0 0 PCKB1 0 0 1 1 0 0 1 1 PCKB0 0 1 0 1 0 1 0 1 Value of Clock B Bus Clock Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 1 1 1 1 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 PCKA2–PCKA0 — Prescaler Select for Clock A Clock A is one of two clock sources which can be used for channels 0, 1, 4, or 5. These three bits determine the rate of clock A, as shown in the following table. Table 61 Clock A Prescaler Selects PCKA2 0 0 0 0 1 1 1 1 PCKA1 0 0 1 1 0 0 1 1 PCKA0 0 1 0 1 0 1 0 1 Value of Clock A Bus Clock Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) PWM Center Align Enable Register (PWMCAE) Address Offset: $00A4 Bit 7 Read: Write: Reset: CAE7 0 6 CAE6 0 5 CAE5 0 4 CAE4 0 3 CAE3 0 2 CAE2 0 1 CAE1 0 Bit 0 CAE0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference Left Aligned Outputs and Center Aligned Outputs for a more detailed description of the PWM output modes. Read: anytime Write: anytime CAUTION: Write these bits only when the corresponding channel is disabled. CAE7 — Center Aligned Output Mode on channel 7 1 = Channel 7 operates in Center Aligned Output Mode. 0 = Channel 7 operates in Left Aligned Output Mode. CAE6 — Center Aligned Output Mode on channel 6 1 = Channel 6 operates in Center Aligned Output Mode. 0 = Channel 6 operates in Left Aligned Output Mode. CAE5 — Center Aligned Output Mode on channel 5 1 = Channel 5 operates in Center Aligned Output Mode. 0 = Channel 5 operates in Left Aligned Output Mode. CAE4 — Center Aligned Output Mode on channel 4 1 = Channel 4 operates in Center Aligned Output Mode. 0 = Channel 4 operates in Left Aligned Output Mode. CAE3 — Center Aligned Output Mode on channel 3 1 = Channel 3 operates in Center Aligned Output Mode. 0 = Channel 3 operates in Left Aligned Output Mode. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions CAE2 — Center Aligned Output Mode on channel 2 1 = Channel 2 operates in Center Aligned Output Mode. 0 = Channel 2 operates in Left Aligned Output Mode. CAE1 — Center Aligned Output Mode on channel 1 1 = Channel 1 operates in Center Aligned Output Mode. 0 = Channel 1 operates in Left Aligned Output Mode. CAE0 — Center Aligned Output Mode on channel 0 1 = Channel 0 operates in Center Aligned Output Mode. 0 = Channel 0 operates in Left Aligned Output Mode. PWM Control Register (PWMCTL) Address Offset: $00A5 Bit 7 Read: Write: Reset: CON67 0 6 CON45 0 5 CON23 0 4 CON01 0 3 PSWAI 0 2 PFRZ 0 1 0 0 Bit 0 0 0 The PWMCTL register provides for various control of the PWM module. Read: anytime Write: anytime There are three control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel as shown in Figure 66. Similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. Reference PWM 16-Bit Functions for a more detailed description of the concatenation PWM Function. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) CAUTION: Change these bits only when both corresponding channels are disabled. CON67 — Concatenate channels 6 and 7 1 = Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. 0 = Channels 6 and 7 are separate 8-bit PWMs. CON45 — Concatenate channels 4 and 5 1 = Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. 0 = Channels 4 and 5 are separate 8-bit PWMs. CON23 — Concatenate channels 2 and 3 1 = Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. 0 = Channels 2 and 3 are separate 8-bit PWMs. CON01 — Concatenate channels 0 and 1 MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions 1 = Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. 0 = Channels 0 and 1 are separate 8-bit PWMs. PSWAI — PWM Stops in Wait Mode Enabling this bit allows for lower power consumption in Wait Mode by disabling the input clock to the prescaler. 1 = Stop the input clock to the prescaler whenever the MCU is in Wait Mode. 0 = Allow the clock to the prescaler to continue while in wait mode. PFRZ — PWM Counters Stop in Freeze Mode In Freeze Mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal program flow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. 1 = Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation. 0 = Allow PWM to continue while in freeze mode. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... NOTE: The PWM module enters freeze mode when background debug mode (BDM) is active. Refer to the Fast Background Debug Module (FBDM) section about the background debug mode. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) PWM Scale A Register (PWMSCLA) Address Offset: $00A8 Bit 7 Read: Write: Reset: Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE: When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Read: anytime Write: anytime (causes the scale counter to load the PWMSCLA value) PWM Scale B Register (PWMSCLB) Address Offset: $00A9 Bit 7 Read: Write: Reset: Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0 PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock B / (2 * PWMSCLB) MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions NOTE: When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Read: anytime Write: anytime (causes the scale counter to load the PWMSCLB value) Address Offset: $00AC, $00AD, $00AE,$00AF, $00B0, $00B1, $00B2, $00B3 Bit 7 Read: Write: Reset: Bit 7 0 0 6 6 0 0 5 5 0 0 4 4 0 0 3 3 0 0 2 2 0 0 1 1 0 0 Bit 0 Bit 0 0 0 Read: anytime Write: anytime (any value written causes PWM counter to be reset to $00) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register – 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is also cleared at the end of the effective period (see Sections Left Aligned Outputs and Center Aligned Outputs for more details). When the channel is disabled (PWMEx=0), the PWMCNTx register does not count. When a channel becomes enabled (PWMEx=1), the associated PWM counter starts at the count in MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PWM Channel Counter Registers (PWMCNTx) Where: x=0,1,2,3,4,5,6,7 Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) the PWMCNTx register. For more detailed information on the operation of the counters, reference PWM Timer Counters. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency CAUTION: Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PWM Channel Period Registers (PWMPERx) Where: x=0,1,2,3,4,5,6,7 Address Offset: $00B4, $00B5, $00B6,$00B7, $00B8, $00B9, $00BA, $00BB Bit 7 Read: Write: Reset: Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1 Read: anytime Write: anytime There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel. The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • • • The effective period ends The counter is written (counter resets to $00) The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions NOTE: Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. Reference PWM Period and Duty for more information. To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel: Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... • Left Aligned Output (CAEx=0) PWMx Period = Channel Clock Period * PWMPERx • Center Aligned Output (CAEx=1) PWMx Period = Channel Clock Period * (2 * PWMPERx) For Boundary Case programming values, please refer to PWM Boundary Cases. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) PWM Channel Duty Registers (PWMDTYx) Where: x=0,1,2,3,4,5,6,7 Address Offset: $00BC, $00BD, $00BE,$00BF, $00C0, $00C1, $00C2, $00C3 Bit 7 Read: Write: Reset: Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: anytime Write: anytime There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • • • The effective period ends The counter is written (counter resets to $00) The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE: Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. Reference PWM Period and Duty for more information. NOTE: Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Register Descriptions duty registers contain a count of the high time. If the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a% of period) for a particular channel: • Polarity = 0 (PPOLx=0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... • Polarity = 1 (PPOLx=1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% For Boundary Case programming values, please refer to PWM Boundary Cases. PWM Shutdown and Interrupt Control Register (PWMSDN) Address Offset: $00C4 Bit 7 Read: Write: Reset: PWMIF 0 6 PWMIE 0 5 0 PWMRSTRT 0 4 PWMLVL 0 3 0 0 2 PWM7IN 0 1 PWM7INL 0 Bit 0 PWM7ENA 0 = Reserved or unimplemented The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. Interruptions are enabled and monitored through this register. Read: anytime Write: anytime PWMIF — PWM Interrupt Flag Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a ‘1’ to it. Writing a ‘0’ has no effect. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) 1 = change on PWM7IN input 0 = No change on PWM7IN input. PWMIE — PWM Interrupt Enable If interrupt is enabled an interrupt to the CPU is asserted. 1 = PWM interrupt is enabled. 0 = PWM interrupt is disabled. PWMRSTRT — PWM Restart. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a ‘1’ to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes next ‘counter == 0’ phase. Also if the PWM7ENA bit is reset to 0, the PWM do not start before the counter passes $00. The bit is always read as ‘0’. PWMLVL — PWM shutdown output Level. If active level as defined by the PWM7IN input, gets asserted all enabled PWM channels are immediately driven to the level defined by PWMLVL. 1 = PWM outputs are forced to 1. 0 = PWM outputs are forced to 0 PWM7IN — PWM channel 7 input status. This reflects the current status of the PWM7 pin. PWM7INL — PWM shutdown active input level for ch. 7. If the emergency shutdown feature is enabled (PWM7ENA = 1), this bit determines the active level of the PWM7channel. 1 = Active level is high 0 = Active level is low PWM7ENA — PWM emergency shutdown Enable If this bit is ‘1’ the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled.All the other bits in this register are meaningful only if PWM7ENA = 1. 1 = PWM emergency feature is enabled. 0 = PWM emergency feature disabled. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description Functional Description PWM Clock Select There are four available clocks called clock A, clock B, clock SA (Scaled A), and clock SB (Scaled B). These four clocks are based on the Bus Clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the Bus Clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, Clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 60 shows the four different clocks and how the scaled clocks are created. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Clock A M U X PCLK0 Clock to PWM Ch 0 Clock A/2, A/4, A/6,....A/512 PCKA2 PCKA1 PCKA0 8-bit Down Counter Count=1 Load Clock SA M U X PCLK1 Clock to PWM Ch 1 PWMSCLA DIV 2 Freescale Semiconductor, Inc... M U X Clock to PWM Ch 2 PCLK2 M U X Clock to PWM Ch 3 PCLK3 Clock B M U X Clock to PWM Ch 4 Clock B/2, B/4, B/6,....B/512 M U X 8-bit Down Counter Count=1 Load Clock SB PCLK4 M U X Clock to PWM Ch 5 PWMSCLB DIV 2 PCLK5 M U X Clock to PWM Ch 6 PCLK6 PWME7-0 M U X Clock to PWM Ch 7 PCLK7 PRESCALE SCALE CLOCK SELECT Figure 60 PWM Clock Select Block Diagram MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family M U X Divide by Prescaler Taps: 2 4 8 16 32 64 128 Bus clock PFRZ fipg_freeze PCKB2 PCKB1 PCKB0 Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description Prescale The input clock to the PWM prescaler is the Bus Clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are disabled (PWMEx=0 in the PWME register; where x=0,1,...,7). This is useful for reducing power by disabling the prescale counter. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the Bus Clock. The value selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK register. Clock Scale The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, two things happen; a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals Clock A divided by two times the value in the PWMSCLA register. NOTE: Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Similarly, Clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals Clock B divided by two times the value in the PWMSCLB register. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) NOTE: Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be the Bus Clock divided by 4. A pulse will occur at a rate of once every 255x4 Bus Clock cycles. Passing this through the divide by two circuit produces a clock signal that is the Bus Clock divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register, when clock A is the Bus Clock divided by 4, will produce a clock that is the Bus Clock divided by 8 rate. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. CAUTION: Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs. Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. Clock Select CAUTION: PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown below in Figure 61 is the block diagram for the PWM timer MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description Clock Source 8-bit Counter GATE PWMCNTx (clock edge sync) From Port PWMP Data Register up/down reset 8-bit Compare = T PWMDTYx R Q Q 8-bit Compare = PWMPERx M U M U To Pin Driver Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PPOLx Q Q T CAEx R PWMEx Figure 61 PWM Timer Channel Block Diagram PWM Enable Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx=1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to PWM 16-Bit Functions for more detail. The first PWM cycle after enabling the channel can be irregular. On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com CAUTION: Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) edge. When the channel is disabled (PWMEx=0), the counter for the channel does not count. PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip flop in Figure 61. When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • • • The effective period ends The counter is written (counter resets to $00) The channel is disabled PWM Period and Duty In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect ‘immediately’ by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable it is possible to know where the count is with respect to the duty value and software can be used to make adjustments CAUTION: NOTE: When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description PWM Timer Counters Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx=0), the counter stops. When a channel becomes enabled (PWMEx=1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-enabled. When the channel is disabled, writing ‘0’ to the period register will cause the counter to reset on the next selected clock. NOTE: If the user wants to start a new ‘clean’ PWM waveform without any ‘history’ from the old waveform, the user must write to channel counter (PWMCNTx) prior to enabling the PWM channel (PWMEx=1). Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled except that the new period is started immediately with the output set according to the polarity bit. CAUTION: Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (reference PWM Clock Select for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 61. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 61 and described in Left Aligned Outputs and Center Aligned Outputs. Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) The counter is cleared at the end of the effective period (see Left Aligned Outputs and Center Aligned Outputs for more details). Table 62 PWM Timer Counter Conditions Counter Clears ($00) When PWMCNTx register written to any value Effective period ends Counter Counts When PWM channel is enabled (PWMEx=1). Counts from last value in PWMCNTx. Counter Stops When PWM channel is disabled (PWMEx=0) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Left Aligned Outputs The PWM timer provides the choice of two types of outputs, Left Aligned or Center Aligned outputs. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx=0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and a period register as shown in the block diagram in Figure 61. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop as shown in Figure 61 as well as performing a load from the double buffer period and duty register to the associated registers as described in PWM Period and Duty. The counter counts from 0 to the value in the period register – 1. NOTE: Changing the PWM output mode from Left Aligned Output to Center Aligned Output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description PPOLx=0 PPOLx=1 PWMDTYx Period = PWMPERx Figure 62 PWM Left Aligned Output Waveform To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel. • • PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx PWMx Duty Cycle (high time as a% of period): – Polarity = 0 (PPOLx=0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% – Polarity = 1 (PPOLx=1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock Source = Bus Clock, where Bus Clock=10MHz (100ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10MHz/4 = 2.5MHz PWMx Period = 400ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 63. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) E=100ns DUTY CYCLE = 75% PERIOD = 400ns Figure 63 PWM Left Aligned Output Example Waveform Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Center Aligned Outputs For Center Aligned Output Mode selection, set the CAEx bit (CAEx=1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 61. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed as described in PWM Period and Duty. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the effective period is PWMPERx*2. NOTE: Changing the PWM output mode from Left Aligned Output to Center Aligned Output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description PPOLx=0 PPOLx=1 PWMDTYx PWMPERx PWMPERx PWMDTYx Period = PWMPERx*2 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Figure 64 PWM Center Aligned Output Waveform To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel. • • PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx) PWMx Duty Cycle (high time as a% of period): – Polarity = 0 (PPOLx=0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% – Polarity = 1 (PPOLx=1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a center aligned output, consider the following case: Clock Source = Bus Clock, where Bus Clock =10MHz (100ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10MHz/8 = 1.25MHz PWMx Period = 800ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 65 MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) E=100ns DUTY CYCLE = 75% PERIOD = 800ns E=100ns Figure 65 PWM Center Aligned Output Example Waveform PWM 16-Bit Functions The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels. The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... CAUTION: Change these bits only when both corresponding channels are disabled. When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel as shown in Figure 66. Similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description Clock Source 7 High PWMCNT6 Low PWCNT7 Period/Duty Compare PWM7 Clock Source 5 Freescale Semiconductor, Inc... High PWMCNT4 Low PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High PWMCNT2 Low PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High PWMCNT0 Low PWCNT1 Period/Duty Compare PWM1 Figure 66 PWM 16-Bit Mode When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 66. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. Once concatenated mode is enabled (CONxx bits set in PWMCTL register) then enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. The table shown below is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 63 16-bit Concatenation Mode Summary CONxx CON67 CON45 CON23 CON01 PWMEx PWME7 PWME5 PWME3 PWME1 PPOLx PPOL7 PPOL5 PPOL3 PPOL1 PCLKx PCLK7 PCLK5 PCLK3 PCLK1 CAEx CAE7 CAE5 CAE3 CAE1 PWMx OUTPUT PWM7 PWM5 PWM3 PWM1 MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Functional Description PWM Boundary Cases The following table summarizes the boundary conditions for the PWM regardless of the output mode (Left Aligned or Center Aligned) and 8-bit (normal) or 16-bit (concatenation): Table 64 PWM Boundary Cases PWMDTYx $00 (indicates no duty) PWMPERx >$00 >$00 $00(1) (indicates no period) $001 (indicates no period) XX XX PPOLx 1 0 PWMx Output Always Low Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... $00 (indicates no duty) XX Always High 1 Always High XX 0 Always Low >= PWMPERx >= PWMPERx 1. Counter=$00 and does not count. 1 0 Always High Always Low MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Low Power Options This section summarizes the low power options available in the PWM module. Low power design practices are implemented where possible. Run Mode While in run mode, if all eight PWM channels are disabled (PWMEx=0 in the PWME register, where x=0,1,...,7), the prescaler counter shuts off for power savings (see Figure 60). Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Wait Mode The PWM will keep running in WAIT unless the PSWAI bit in the PWMCTL register is enabled. This allows for lower power consumption in WAIT mode by disabling the input clock to the prescaler. When in WAIT mode with this bit set, no activity in the PWM occurs and the PWM outputs go to a static state (high or low). Stop Mode In STOP mode, the PWM module is stopped since all the clocks from IP bus to the module are stopped. The PWM outputs go to a static state (high or low). Reset Initialization The reset state of each individual bit is listed within the Register Description section (see Register Descriptions) which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. • • The 8-bit up/down counter is configured as an up counter out of reset. All the channels are disabled and all the counters don’t count. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) Interrupts Interrupts The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE in the PWMSDN register) is set. The vector address for the PWM Emergency Shutdown interrupt is $FF8C,$FF8D. MC9S12T64Revision 1.1.1 Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... Pulse Width Modulator (PWM8B8C) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Pulse Width Modulator (PWM8B8C) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Overview The HC12 Enhanced Capture Timer module has the features of the HC12 Standard Timer module enhanced by additional features in order to enlarge the field of applications, in particular for automotive ABS applications. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Features • • 16-Bit Buffer Register for four Input Capture (IC) channels. Four 8-Bit Pulse Accumulators with 8-bit buffer registers associated with the four buffered IC channels. Configurable also as two 16-Bit Pulse Accumulators. 16-Bit Modulus Down-Counter with 4-bit Prescaler. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family • • Freescale Semiconductor, Inc... Four user selectable Delay Counters for input noise immunity increase. Support for only 16-bit access on the IP bus. • Modes of Operation STOP: FREEZE: Timer and modulus counter are off since clocks are stopped. The ECT module enters freeze mode when background debug mode (BDM) is active. In freeze mode, timer and modulus counter keep on running, unless TSFRZ in TSCR1 (see page 382) is set to one. Counters keep on running, unless TSWAI in TSCR1 is set to one. Timer and modulus counter keep on running, unless TEN in TSCR1 and MCEN in MCCTL (see page 396), respectively, are cleared. WAIT: NORMAL: Abbreviations Following abbreviations are used in the document. PACLK – 16-bit pulse accumulator A (PACA) clock MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Block Diagram Block Diagram Bus clock Prescaler 16-bit Counter Channel 0 Input capture Output compare Channel 1 Input capture Output compare Channel 2 Input capture Output compare Channel 3 Input capture Output compare IOC0 Freescale Semiconductor, Inc... Modulus counter Interrupt Timer overflow interrupt Timer channel 0 interrupt IOC1 16-bit Modulus Counter IOC2 IOC3 Registers Channel 4 Input capture Output compare Channel 5 Input capture Output compare IOC4 IOC5 Timer channel 7 interrupt PA overflow interrupt PA input interrupt PB overflow interrupt 16-bit Pulse accumulator A 16-bit Pulse accumulator B Channel 6 Input capture Output compare Channel 7 Input capture Output compare IOC6 IOC7 Figure 67 Timer Block Diagram MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) External Pin Descriptions IOC7 (PT7) Input capture and Output compare channel 7 - This pin serves as input capture or output compare for channel 7. IOC6 (PT6) Input capture and Output compare channel 6 - This pin serves as input capture or output compare for channel 6. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... IOC5 (PT5) Input capture and Output compare channel 5 - This pin serves as input capture or output compare for channel 5. IOC4 (PT4) Input capture and Output compare channel 4 - This pin serves as input capture or output compare for channel 4. IOC3 (PT3) Input capture and Output compare channel 3 - This pin serves as input capture or output compare for channel 3. IOC2 (PT2) Input capture and Output compare channel 2 - This pin serves as input capture or output compare for channel 2. IOC1 (PT1) Input capture and Output compare channel 1 - This pin serves as input capture or output compare for channel 1. IOC0 (PT0) Input capture and Output compare channel 0 - This pin serves as input capture or output compare for channel 0. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Map Register Map Register name TIOS CFORC Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0 14 6 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 C5F 0 13 5 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 C4F 0 12 4 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 0 TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0 11 3 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 10 2 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 9 1 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Address Offset $0040 $0041 (1) $0042 $0043 $0044 (2) $0045 (2) $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F $0050 (3) $0051 (3) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) = Unimplemented or reserved Figure 68 Enhanced Capture Timer Register Map MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register name TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 0 0 Bit 7 Bit 7 Bit 7 Bit 7 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 PAEN 0 6 6 6 6 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 PAMOD 0 5 5 5 5 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 PEDGE 0 4 4 4 4 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 CLK1 0 3 3 3 3 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 CLK0 0 2 2 2 2 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 PAOVI PAOVF 1 1 1 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Bit 0 Bit 0 Bit 0 Address Offset $0052 (3) $0053 (3) $0054 (3) $0055 (3) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family $0056 (3) $0057 (3) $0058 (3) $0059 (3) $005A (3) $005B (3) $005C (3) $005D (3) $005E (3) $005F (3) $0060 $0061 $0062 $0063 $0064 $0065 Freescale Semiconductor, Inc... TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACN3 (hi) PACN2 (lo) PACN1 (hi) PACN0 (lo) = Unimplemented or reserved Figure 68 Enhanced Capture Timer Register Map (Continued) MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Map Register name MCCTL MCFLG ICPAR DLYCT ICOVW Bit 7 Read: MCZI Write: Read: MCZF Write: Read: 0 Write: Read: 0 Write: Read: NOVW7 Write: Read: SH37 Write: Read: 0 Write: Read: Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: 6 MODMC 0 0 0 NOVW6 SH26 0 5 RDMCL 0 0 0 NOVW5 SH15 0 4 0 ICLAT 0 0 0 NOVW4 SH04 0 3 0 FLMC POLF3 PA3EN 0 NOVW3 TFMOD 0 2 MCEN POLF2 PA2EN 0 NOVW2 PACMX 0 1 MCPR1 POLF1 PA1EN DLY1 NOVW1 BUFEN 0 Bit 0 MCPR0 POLF0 PA0EN DLY0 NOVW0 LATQ 0 Address Offset $0066 $0067 $0068 $0069 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family $006A $006B (4) $006C $006D (2) Freescale Semiconductor, Inc... ICSYS Reserved Reserved for Factory Test Reserved Reserved PBCTL PBFLG PA3H PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) Reads to this register return unpredictable values 0 0 PBEN 0 6 6 6 6 14 6 14 6 0 0 0 0 5 5 5 5 13 5 13 5 0 0 0 0 4 4 4 4 12 4 12 4 0 0 0 0 3 3 3 3 11 3 11 3 0 0 0 0 2 2 2 2 10 2 10 2 0 0 PBOVI PBOVF 1 1 1 1 9 1 9 1 0 0 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 $006E $006F $0070 $0071 $0072 (5) $0073 (5) $0074 (5) $0075 (5) $0076 $0077 $0078 (5) $0079 (5) = Unimplemented or reserved Figure 68 Enhanced Capture Timer Register Map (Continued) MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register name TC1H (hi) TC1H (lo) TC2H (hi) TC2H (lo) TC3H (hi) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 6 14 6 14 6 14 6 5 13 5 13 5 13 5 4 12 4 12 4 12 4 3 11 3 11 3 11 3 2 10 2 10 2 10 2 1 9 1 9 1 9 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Address Offset $007A (5) $007B (5) $007C (5) $007D (5) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family $007E (5) $007F (5) Freescale Semiconductor, Inc... TC3H (lo) = Unimplemented or reserved Figure 68 Enhanced Capture Timer Register Map (Continued) 1. Always read $00. 2. Only writable in special modes. 3. Write to these registers have no meaning or effect during input capture. 4. May be written once in normal modes but writes are always permitted when special modes. 5. Write has no effect. NOTE: Register Address = Base Address (INITRG) + Address Offset Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Timer Input Capture/Output Compare Select (TIOS) Register offset: $0040 Bit 7 6 IOS6 0 5 IOS5 0 4 IOS4 0 3 IOS3 0 2 IOS2 0 1 IOS1 0 Bit 0 IOS0 0 Read: Write: Reset: IOS7 0 Read or write anytime. IOS[7:0] — Input Capture or Output Compare Channel Configuration 1 = The corresponding channel acts as an output compare. 0 = The corresponding channel acts as an input capture Timer Compare Force Register (CFORC) Register offset: $0041 Bit 7 6 0 FOC6 0 5 0 FOC5 0 4 0 FOC4 0 3 0 FOC3 0 2 0 FOC2 0 1 0 FOC1 0 Bit 0 0 FOC0 0 Read: Write: Reset: 0 FOC7 0 Read anytime but will always return $00 (1 state is transient). Write anytime. FOC[7:0] — Force Output Compare Action for Channel 7–0 A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare ‘n’ to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not get set NOTE: A successful channel 7 output compare overrides any channel 6:0 compares. If forced output compare on any channel occurs at the same MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) time as the successful output compare then forced output compare action will take precedence and interrupt flag won’t get set. Output Compare 7 Mask Register (OC7M) Freescale Semiconductor, Inc... Register offset: $0042 Bit 7 6 OC7M6 0 5 OC7M5 0 4 OC7M4 0 3 OC7M3 0 2 OC7M2 0 1 OC7M1 0 Bit 0 OC7M0 0 Read: Write: Reset: OC7M7 0 Read or write anytime. Setting the OC7Mn (n ranges from 0 to 6) will set the corresponding port to be an output port when the corresponding IOSn (TIOS register; n ranges from 0 to 6) bit is set to be an output compare. NOTE: A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Output Compare 7 Data Register (OC7D) Register offset: $0043 Bit 7 6 OC7D6 0 5 OC7D5 0 4 OC7D4 0 3 OC7D3 0 2 OC7D2 0 1 OC7D1 0 Bit 0 OC7D0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Reset: OC7D7 0 Freescale Semiconductor, Inc... Read or write anytime. A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. Timer Count Register (TCNT) Register offset: $0044–$0045 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 Read: Write: Bit 15 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Read: Write: Reset: Bit 7 0 0 0 0 0 0 0 0 = Reserved or unimplemented Read anytime. Write has no meaning or effect in the normal mode; only writable in special modes. The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. Timer System Control Register 1 (TSCR1) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Register offset: $0046 Freescale Semiconductor, Inc... Bit 7 6 TSWAI 0 5 TSFRZ 0 4 TFFCA 0 3 0 2 0 1 0 Bit 0 0 Read: Write: Reset: TEN 0 0 0 0 0 = Reserved or unimplemented Read or write anytime. TEN — Timer Enable 1 = Allows the timer to function normally. 0 = Disables the main timer, including the counter. Can be used for reducing power consumption. If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is generated by the timer prescaler. TSWAI — Timer Module Stops While in Wait 1 = Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. 0 = Allows the timer module to continue running during wait. TSWAI also affects pulse accumulators and modulus down counters. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions TSFRZ — Timer and Modulus Counter Stop While in Freeze Mode 1 = Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation. 0 = Allows the timer and modulus counter to continue running while in freeze mode. TSFRZ does not stop the pulse accumulator. NOTE: TFFCA — Timer Fast Flag Clear All 1 = For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. 0 = Allows the timer flag clearing to function normally. Timer Toggle On Overflow Register 1 (TTOV) Register offset: $0047 Bit 7 6 5 4 3 2 1 0 Read: Write: Reset: TOV7 0 TOV6 0 TOV5 0 TOV4 0 TOV3 0 TOV2 0 TOV1 0 TOV0 0 Read or write anytime. TOVx — Toggle On Overflow Bits MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The ECT module enters freeze mode when background debug mode (BDM) is active. Refer to the Fast Background Debug Module (FBDM) section about the background debug mode. Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 1 = Toggle output compare pin on overflow feature enabled 0 = Toggle output compare pin on overflow feature disabled MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Timer Control Registers 1and 2 (TCTL1, TCTL2) Register offset: $0048-$0049 Bit 7 6 OL7 6 OL3 0 5 OM6 5 OM2 0 4 OL6 4 OL2 0 3 OM5 3 OM1 0 2 OL5 2 OL1 0 1 OM4 1 OM0 0 Bit 0 OL4 Bit 0 OL0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Read: OM7 Bit 7 Freescale Semiconductor, Inc... Write: Reset: OM3 0 Read or write anytime. OMn — Output Mode OLn — Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn compare. When either OMn or OLn is one, the pin associated with OCn becomes an output tied to OCn. NOTE: To enable output action by OMn and OLn bits on timer port, the corresponding bit in OC7M should be cleared. Table 65 Compare Result Output Action OMn 0 0 1 1 OLn 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line to zero Set OCn output line to one To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Timer Control Registers 3 and 4 (TCTL3, TCTL4) Register offset: $004A-$004B Bit 7 6 EDG7A 6 EDG3A 0 5 EDG6B 5 EDG2B 0 4 EDG6A 4 EDG2A 0 3 EDG5B 3 EDG1B 0 2 EDG5A 2 EDG1A 0 1 EDG4B 1 EDG0B 0 Bit 0 EDG4A Bit 0 EDG0A 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Read: EDG7B Bit 7 Freescale Semiconductor, Inc... Write: Reset: EDG3B 0 Read or write anytime. EDGnB, EDGnA — Input Capture / Pulse Accumulator Edge Control These eight pairs of control bits configure the input capture edge detector circuits. The four pairs of control bits of TCTL4 also configure the 8 bit pulse accumulators PAC0–3. For 16-bit pulse accumulator PACB, EDG0B & EDG0A, control bits of TCTL4 will decide the active edge. Table 66 Edge Detector Circuit Configuration EDGnB 0 0 1 1 EDGnA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) NOTE: For the 16-bit pulse accumulator PACA, refer to the register PACTL for active edge control. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Timer Interrupt Enable Register (TIE) Register offset: $004C Bit 7 6 C6I 0 5 C5I 0 4 C4I 0 3 C3I 0 2 C2I 0 1 C1I 0 Bit 0 C0I 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Reset: C7I 0 Freescale Semiconductor, Inc... Read or write anytime. The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable Timer System Control Register 2 (TSCR2) Register offset: $004D Bit 7 6 0 5 0 4 0 3 TCRE 0 2 PR2 0 1 PR1 0 Bit 0 PR0 0 Read: Write: Reset: TOI 0 0 0 0 = Reserved or unimplemented Read or write anytime. TOI — Timer Overflow Interrupt Enable 1 = Hardware interrupt requested when TOF flag set 0 = Interrupt inhibited TCRE — Timer Counter Reset Enable This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) 1 = Counter reset by a successful output compare 7 0 = Counter reset inhibited and counter free runs If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF in TFLG2 (see page 389) will never be set when TCNT is reset from $FFFF to $0000. PR2, PR1, PR0 — Timer Prescaler Select These three bits specify the number of ÷2 stages that are to be inserted between the bus clock and the main timer counter. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Table 67 Prescaler Selection PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Prescale Factor 1 2 4 8 16 32 64 128 The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. Main Timer Interrupt Flag 1 (TFLG1) Register offset: $004E Bit 7 6 C6F 0 5 C5F 0 4 C4F 0 3 C3F 0 2 C2F 0 1 C1F 0 Bit 0 C0F 0 Read: Write: Reset: C7F 0 TFLG1 indicates when interrupt conditions have occurred. Read anytime. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Write used in the clearing mechanism. Writing one will cause the corresponding bits to be cleared. Writing a zero has no effect. Use of the TFMOD bit in the ICSYS register (see page 401) in conjunction with the use of the ICOVW (see page 400) register allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... When TFFCA bit in TSCR1 register (see page 382) is set, a read from an input capture or a write into an output compare channel will cause the corresponding channel flag CnF to be cleared. C7F–C0F — Input Capture/Output Compare Channel ‘n’ Flag. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be set by 8-bit pulse accumulators PAC3–PAC0. Main Timer Interrupt Flag 2 (TFLG2) Register offset: $004F Bit 7 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Read: Write: Reset: TOF 0 0 0 0 0 0 0 0 = Reserved or unimplemented TFLG2 indicates when interrupt conditions have occurred. Read anytime. Write used in the clearing mechanism. Writing one will cause the corresponding bits to be cleared. Writing a zero has no effect. Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR1 (see page 382) register is set. TOF — Timer Overflow Flag MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation in TSCR2 register page 387.) Register offset: $0050–$005F Bit 7 6 6 14 14 0 5 5 13 13 0 4 4 12 12 0 3 3 11 11 0 2 2 10 10 0 1 1 9 9 0 Bit 0 Bit 0 Bit 8 Bit 8 0 Read: Write: Read: Write: Reset: Bit 7 Bit 15 Bit 15 0 Read anytime. Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to $0000. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Timer Input Capture/Output Compare Registers 0–7 (TC0–TC7) Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions 16-Bit Pulse Accumulator A Control Register (PACTL) Register offset: $0060 Bit 7 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 CLK1 0 2 CLK0 0 1 PAOVI 0 Bit 0 PAI 0 Read: Write: Reset: 0 = Reserved or unimplemented Read or write any time. 16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit pulse accumulators PAC3 and PAC2. When PAEN is set, the PACA is enabled. The PACA shares the input pin with IC7. PAEN — Pulse Accumulator A System Enable 1 = Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA is enabled, the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR (see page 399) have no effect. Pulse Accumulator Input Edge Flag (PAIF) function is enabled. 0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled. PAEN is independent from TEN in TSCR1(see page 382). With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 0 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) PAMOD — Pulse Accumulator Mode This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). 1 = gated time accumulation mode 0 = event counter mode PEDGE — Pulse Accumulator Edge Control This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). Freescale Semiconductor, Inc... For PAMOD bit = 0 (event counter mode). 1 = rising edges on PT7 pin cause the count to be incremented 0 = falling edges on PT7 pin cause the count to be incremented For PAMOD bit = 1 (gated time accumulation mode). 1 = PT7 input pin low enables bus clock divided by 64 clock to Pulse Accumulator and the trailing rising edge on PT7 sets the PAIF flag 0 = PT7 input pin high enables bus clock divided by 64 clock to Pulse Accumulator and the trailing falling edge on PT7 sets the PAIF flag. Table 68 Pin Action PAMOD 0 0 1 1 PEDGE 0 1 0 1 Pin Action Falling edge Rising edge Div. by 64 clock enabled with pin high level Div. by 64 clock enabled with pin low level If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the timer prescaler. CLK1, CLK0 — Clock Select Bits Table 69 Clock Selection CLK1 0 0 1 1 CLK0 0 1 0 1 Clock Source Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency For the description of PACLK please refer to Figure 72 in page 412. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. PAOVI — Pulse Accumulator A Overflow Interrupt enable 1 = interrupt requested if PAOVF is set 0 = interrupt inhibited Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... PAI — Pulse Accumulator Input Interrupt enable 1 = interrupt requested if PAIF is set 0 = interrupt inhibited Pulse Accumulator A Flag Register (PAFLG) Register offset: $0061 Bit 7 6 0 5 0 4 0 3 0 2 0 1 PAOVF 0 Bit 0 PAIF 0 Read: Write: Reset: 0 0 0 0 0 0 0 = Reserved or unimplemented Read or write anytime. When the TFFCA bit in the TSCR1 register (see page 382) is set, any access to the PACNT register will clear all the flags in the PAFLG register. PAOVF — Pulse Accumulator A Overflow Flag Set when the 16-bit pulse accumulator A overflows from $FFFF to $0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF to $00. When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches $FF followed by an active edge on PT3. This bit is cleared automatically by a write to the PAFLG register with bit 1 set. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) PAIF — Pulse Accumulator Input edge Flag Set when the selected edge is detected at the PT7 input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set. Any access to the PACN3, PACN2 registers will clear all the flags in this register when TFFCA bit in register TSCR1 is set. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Pulse Accumulators Count Registers (PACN3, PACN2) Register offset: $0062–$0063 Bit 7 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0 Read: Write: Reset: BIt 7 0 Read or write any time. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1 in PACTL) the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in PAFLG is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. NOTE: The input capture edge circuits of 8-bit pulse accumulators are configured with control bits EDGnA and EDGnB in the TCTL4 register (see page 386). MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions NOTE: When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. Pulse Accumulators Count Registers (PACN1, PACN0) Register offset: $0064–$0065 Bit 7 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: Write: Reset: Bit 7 0 Read or write any time. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB is enabled, (PBEN=1 in PBCTL) the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in PBFLG (see page 405) is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. NOTE: The input capture edge circuits of 8-bit pulse accumulators are configured with control bits EDGnA EDGnB in the TCTL4 register (see page 386). When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. NOTE: MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) 16–Bit Modulus Down-Counter Control Register (MCCTL) Register offset: $0066 Bit 7 6 MODMC 0 5 RDMCL 0 4 0 ICLAT 0 3 0 FLMC 0 2 MCEN 0 1 MCPR1 0 Bit 0 MCPR0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Reset: MCZI 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read or write any time except for bit 4. MCZI — Modulus Counter Underflow Interrupt Enable 1 = Modulus counter interrupt is enabled. 0 = Modulus counter interrupt is disabled. MODMC — Modulus Mode Enable 1 = Modulus mode is enabled. When the counter reaches $0000, the counter is loaded with the latest value written to the modulus count register. 0 = The counter counts once from the value written to it and will stop at $0000. NOTE: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to $FFFF. RDMCL — Read Modulus Down-Counter Load 1 = Reads of the modulus count register will return the contents of the load register. 0 = Reads of the modulus count register will return the present value of the count register. ICLAT — Input Capture Force Latch Action When input capture latch mode is enabled - LATQ and BUFEN bit in ICSYS (see page 401) are set - a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3 and their MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse accumulators will be automatically cleared when the latch action occurs. Writing zero to this bit has no effect. Read of this bit will return always zero. FLMC — Force Load Register into the Modulus Counter Count Register This bit is active only when the modulus down-counter is enabled (MCEN=1). Freescale Semiconductor, Inc... A write one into this bit loads the load register into the modulus counter count register. This also resets the modulus counter prescaler. Write zero to this bit has no effect. When MODMC=0, counter starts counting and stops at $0000. Read of this bit will return always zero. MCEN — Modulus Down-Counter Enable 1 = Modulus counter is enabled. 0 = Modulus counter disabled. When MCEN=0, the counter is preset to $FFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. MCPR1, MCPR0 — Modulus Counter Prescaler select These two bits specify the division rate of the modulus counter prescaler. The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. Table 70 Modulus Counter Prescaler Select MCPR1 0 0 1 1 MCPR0 0 1 0 1 Prescaler division rate 1 4 8 16 MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) 16-Bit Modulus Down-Counter FLAG Register (MCFLG) Register offset: $0067 Bit 7 6 0 5 0 4 0 3 POLF3 2 POLF2 1 POLF1 Bit 0 POLF0 Read: Write: Reset: MCZF 0 = Reserved or unimplemented Read: any time Write: Only for clearing bit 7 MCZF — Modulus Counter Underflow Flag The flag is set when the modulus down-counter reaches $0000. A write one to this bit clears the flag. Write zero has no effect. Any access to the MCCNT register will clear the MCZF flag in this register when TFFCA bit in register TSCR1 (see page 382) is set. POLF3–POLF0 — First Input Capture Polarity Status This are read only bits. Write to these bits has no effect. Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read. Each POLFx corresponds to a timer PORTx input. 1 = The first input capture has been caused by a rising edge. 0 = The first input capture has been caused by a falling edge. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Input Control Pulse Accumulators Register (ICPAR) Register offset: $0068 Bit 7 6 0 5 0 4 0 3 PA3EN 0 2 PA2EN 0 1 PA1EN 0 Bit 0 PA0EN 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Reset: 0 0 0 0 0 = Reserved or unimplemented Freescale Semiconductor, Inc... The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN is set, PA3EN and PA2EN have no effect. The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN is set, PA1EN and PA0EN have no effect. Read or write any time. PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable 1 = 8-Bit Pulse Accumulator is enabled. 0 = 8-Bit Pulse Accumulator is disabled. NOTE: The input capture edge circuits of 8-bit pulse accumulators are configured with control bits EDGnA and EDGnB in the TCTL4 register (see page 386). Delay Counter Control Register (DLYCT) Register offset: $0069 Bit 7 6 0 5 0 4 0 3 0 2 0 1 DLY1 0 Bit 0 DLY0 0 Read: Write: Reset: 0 0 0 0 0 0 0 = Reserved or unimplemented MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Read or write any time. If enabled, after detection of a valid edge on input capture pin, the delay counter counts the pre-selected number of bus clock cycles, then it will generate a pulse on its output. The pulse is generated only if the level of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to narrow input pulses. After counting, the counter will be cleared automatically. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Delay between two active edges of the input signal period should be longer than the selected counter delay. DLYx — Delay Counter Select Table 71 Delay Counter Select DLY1 0 0 1 1 DLY0 0 1 0 1 Delay Disabled (bypassed) 256 bus clock cycles 512 bus clock cycles 1024 bus clock cycles Input Control Overwrite Register (ICOVW) Register offset: $006A Bit 7 6 NOVW6 0 5 NOVW5 0 4 NOVW4 0 3 NOVW3 0 2 NOVW2 0 1 NOVW1 0 Bit 0 NOVW0 0 Read: Write: Reset: NOVW7 0 Read or write any time. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions NOVWx — No Input Capture Overwrite 1 = The related capture register or holding register cannot be written by an event unless they are empty (see IC Channels). This will prevent the captured value to be overwritten until it is read or latched in the holding register. 0 = The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. NOTE: NOTE: A holding register is empty when it has been read. Input Control System Control Register (ICSYS) Register offset: $006B Bit 7 6 SH26 0 5 SH15 0 4 SH04 0 3 TFMOD 0 2 PACMX 0 1 BUFEN 0 Bit 0 LATQ 0 Read: Write: Reset: SH37 0 Read: any time Write: May be written once in normal modes. Writes are always permitted when special modes. SHxy — Share Input action of Input Capture Channels x and y 1 = The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge detector is used to be active on the channel ‘y’. 0 = Normal operation TFMOD — Timer Flag-setting Mode Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family An IC register is empty when it has been read or latched into the holding register. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) By setting TFMOD in queue mode, when NOVW bit is set and the corresponding capture and holding registers are emptied, an input capture event will first update the related input capture register with the main timer contents. At the next event the TCn data is transferred to the TCnH register, The TCn is updated and the CnF interrupt flag is set. See Figure 73 in page 413. In all other input capture cases the interrupt flag is set by a valid external event on PTn. 1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags C3F–C0F in TFLG1 are set only when a latch on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F–C0F are set the same way as for TFMOD=0. 0 = The timer flags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin occurs. PACMX — 8-Bit Pulse Accumulators Maximum Count 1 = When the 8-bit pulse accumulator has reached the value $FF, it will not be incremented further. The value $FF indicates a count of 255 or more. 0 = Normal operation. When the 8-bit pulse accumulator has reached the value $FF, with the next active edge, it will be incremented to $00. BUFEN — IC Buffer Enable 1 = Input Capture and pulse accumulator holding registers are enabled. The latching mode is defined by LATQ control bit. Write one into ICLAT bit in MCCTL (see page 396), when LATQ is set will produce latching of input capture and pulse accumulators registers into their holding registers. 0 = Input Capture and pulse accumulator holding registers are disabled. LATQ — Input Control Latch or Queue Mode Enable The BUFEN control bit should be set in order to enable the IC and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and pulse accumulators registers into their holding registers. 1 = Latch Mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is written into the count register MCCNT (see Buffered IC Channels). With a latching event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse accumulators are cleared. 0 = Queue Mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) 16-Bit Pulse Accumulator B Control Register (PBCTL) Register offset: $0070 Bit 7 6 PBEN 0 5 0 4 0 3 0 2 0 1 PBOVI 0 Bit 0 0 Read: Write: Reset: 0 = Reserved or unimplemented Read or write any time. 16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit pulse accumulators PAC1 and PAC0. When PBEN is set, the PACB is enabled. The PACB shares the input pin with IC0. PBEN — Pulse Accumulator B System Enable 1 = Pulse Accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. PA1EN and PA0EN control bits in ICPAR have no effect. 0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits in ICPAR are set. PBEN is independent from TEN in TSCR1 (see page 382). With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. PBOVI — Pulse Accumulator B Overflow Interrupt enable 1 = interrupt requested if PBOVF in PBFLG is set 0 = interrupt inhibited MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 0 0 0 0 0 0 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions NOTE: The input capture edge circuits of the 16-bit pulse accumulator PACB are configured with control bits EDG0B and EDG0A in the TCTL4 register (see page 386). Pulse Accumulator B Flag Register (PBFLG) Register offset: $0071 Bit 7 6 0 5 0 4 0 3 0 2 0 1 PBOVF 0 Bit 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: Write: Reset: 0 0 0 0 0 0 0 0 = Reserved or unimplemented Read or write any time. PBOVF — Pulse Accumulator B Overflow Flag This bit is set when the 16-bit pulse accumulator B overflows from $FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from $FF to $00. This bit is cleared by a write to the PBFLG register with bit 1 set. Any access to the PACN1 and PACN0 registers will clear the PBOVF flag in this register when TFFCA bit in register TSCR1 (see page 382) is set. When PACMX=1 in ICSYS (see page 401), PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches $FF and followed an active edge comes on PT1. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H) Register offset: $0072–$0075 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Read: Write: Reset: Bit 7 0 0 0 0 0 0 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... = Reserved or unimplemented Read: any time Write: has no effect. These registers are used to latch the value of the corresponding pulse accumulator when the related bits in register ICPAR are enabled (see Pulse Accumulators). Modulus Down-Counter Count Register (MCCNT) Register offset: $0076–$0077 Bit 15 14 14 6 6 1 13 13 5 5 1 12 12 4 4 1 11 11 3 3 1 10 10 2 2 1 9 9 1 1 1 8 Bit 8 Bit 0 Bit 0 1 Read: Write: Read: Write: Reset: Bit 15 Bit 7 Bit 7 1 = Reserved or unimplemented Read or write any time. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give different result than accessing them as a word. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions If the RDMCL bit in MCCTL register (see page 396) is cleared, reads of the MCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load register. If a $0000 is written into MCCNT and modulus counter while LATQ and BUFEN in ICSYS register are set, the input capture and pulse accumulator registers will be latched. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... With a $0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag in MCFLG register. If modulus mode is enabled (MODMC=1), a write to this address will update the load register with the value written to it. The count register will not be updated with the new value until the next counter underflow. The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an immediate load is desired. If modulus mode is not enabled (MODMC=0), a write to this address will clear the prescaler and will immediately update the counter register with the value written to it and down-counts once to $0000 Timer Input Capture Holding Registers 0–3 (TC0H–TC3H) Register offset: $0078–$007F Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 8 Bit 8 Read: Write: Bit 15 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Read: Write: Reset: Bit 7 0 0 0 0 0 0 0 0 = Reserved or unimplemented Read: any time Write: has no effect. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding IOSx bits in TIOS should be cleared (see IC Channels). Functional Description The Enhanced Capture Timer has 8 Input Capture, Output Compare (IC/OC) channels same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called Input Capture (IC) channels. Figures 69 (page 409) and 70 (page 410) show the Timer Block Diagram for Latch and Queue modes, respectively. Four IC channels are the same as on the standard timer with one capture register each which memorizes the timer value captured by an action on the associated input pin. Four other IC channels, in addition to the capture register, have also one buffer each called holding register. This permits to memorize two different timer values without generation of any interrupt. Four 8-bit pulse accumulators are associated with the four buffered IC channels. Each pulse accumulator has a holding register to memorize their value by an action on its external input. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. See Figures 71 (page 411) and 72 (page 412) for Block Diagrams of these accumulators. The 16-bit modulus down-counter can control the transfer of the IC registers contents and the pulse accumulators to the respective holding registers for a given period, every time the count reaches zero. The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Functional Description TIMCLK ÷ 1, 2,..., 128 Bus Clock Prescaler 16-bit Free-running 16 Bit MAIN TIMER main timer PCLK Bus Clock ÷ 1, 4, 8, 16 Prescaler 0 Comparator 16-bit load register 16-bit modulus down counter PT0 Pin logic Delay counter EDG0 TC0 capture/compare register TC0H hold register Comparator PAC0 PA0H hold register 0 RESET PT1 Pin logic Delay counter EDG1 TC1H hold register Comparator PT2 Pin logic Delay counter EDG2 TC2 capture/compare register TC2H hold register Comparator PT3 Pin logic Delay counter EDG3 TC3 capture/compare register TC3H hold register Comparator PT4 Pin logic EDG4 EDG0 SH04 Comparator PT5 Pin logic EDG5 EDG1 SH15 Comparator PT6 Pin logic EDG6 EDG2 SH26 Comparator PT7 Pin logic EDG7 EDG3 SH37 MUX TC7 capture/compare register MUX TC6 capture/compare register MUX TC5 capture/compare register MUX TC4 capture/compare register PA1H hold register 0 PAC2 PA2H hold register 0 PAC3 PA3H hold register RESET RESET ICLAT, LATQ, BUFEN (force latch) Write $0000 to modulus counter LATQ (MDC latch enable) Figure 69 Timer Block Diagram in Latch Mode MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family TC1 capture/compare register Freescale Semiconductor, Inc... PAC1 LATCH Underflow RESET Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) TIMCLK ÷1, 2,..., 128 Bus Clock PT0 Prescaler Pin logic 16-bit Free-running 16 Bit MAIN TIMER main timer Bus Clock PCLK ÷ 1, 4, 8, 16 Prescaler 0 Comparator 16-bit load register 16-bit modulus down counter RESET Delay counter EDG0 TC0 capture/compare register TC0H hold register Comparator PAC0 PA0H hold register 0 RESET LATCH0 Freescale Semiconductor, Inc... Delay counter EDG1 TC1 capture/compare register TC1H hold register Comparator PAC1 PA1H hold register 0 RESET LATCH1 PT2 Pin logic Delay counter EDG2 TC2 capture/compare register TC2H hold register Comparator PAC2 PA2H hold register 0 RESET LATCH2 PT3 Pin logic Delay counter EDG3 TC3 capture/compare register TC3H hold register Comparator PAC3 PA3H hold register LATCH3 PT4 Pin logic EDG4 EDG0 SH04 MUX TC4 capture/compare register LATQ, BUFEN (queue mode) Comparator PT5 Pin logic EDG5 EDG1 SH15 Comparator PT6 Pin logic EDG6 EDG2 SH26 Comparator PT7 Pin logic EDG7 EDG3 SH37 MUX TC7 capture/compare register MUX TC6 capture/compare register MUX TC5 capture/compare register Read TC3H hold register Read TC2H hold register Read TC1H hold register Read TC0H hold register Figure 70 Timer Block Diagram in Queue Mode MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family PT1 Pin logic Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Functional Description Load holding register and reset pulse accumulator 0 EDG0 PT0 Edge detector Delay counter 8-bit PAC0 (PACN0) PA0H holding register Freescale Semiconductor, Inc... Interrupt 0 EDG1 PT1 Edge detector Delay counter IP data bus 8-bit PAC1 (PACN1) PA1H holding register 0 EDG2 PT2 Edge detector Delay counter 8-bit PAC2 (PACN2) PA2H holding register Interrupt 0 EDG3 PT3 Edge detector Delay counter 8-bit PAC3 (PACN3) PA3H holding register Figure 71 8-Bit Pulse Accumulators Block Diagram MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) TIMCLK(Timer clock) CLK1 CLK0 PACLK / 65536 4:1 MUX Prescaled clock (PCLK) PACLK / 256 Clock select (PAMOD) PACLK Edge detector PT7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Interrupt 8-bit PAC3 (PACN3) PACA 8-bit PAC2 (PACN2) MUX Divide by 64 Intermodule Bus Bus Clock Interrupt 8-bit PAC1 (PACN1) PACB 8-bit PAC0 (PACN0) Delay counter Edge detector PT0 Figure 72 16-Bit Pulse Accumulators Block Diagram MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Functional Description 16-bit Main Timer PTn Edge detector Delay counter Set CnF Interrupt TCn Input Capture Reg. Freescale Semiconductor, Inc... TQ TCnH I.C. Holding Reg. BUFEN • LA • TFMOD Figure 73 Interrupt Flag Setting IC Channels The IC channels are composed of four standard IC registers and four buffered IC channels. An IC register is empty when it has been read or latched into the holding register. A holding register is empty when it has been read. Non-Buffered IC Channels The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding NOVWx bit of the ICOVW register (see page 400) is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written unless it is empty. This will prevent the captured value to be overwritten until it is read. Buffered IC Channels There are two modes of operations for the buffered IC channels. • IC Latch Mode: MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) When enabled (LATQ=1), the main timer value is memorized in the IC register by a valid input pin transition. The value of the buffered IC register is latched to its holding register by the Modulus counter for a given period when the count reaches zero, by a write $0000 to the modulus counter or by a write to ICLAT in the MCCTL register. See Figure 69 in page 409. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. In case of latching, the contents of its holding register are overwritten. If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see IC Channels). This will prevent the captured value to be overwritten until it is read or latched in the holding register. • IC queue mode: When enabled (LATQ=0), the main timer value is memorized in the IC register by a valid input pin transition. See Figure 70 in page 410. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see IC Channels). In queue mode, reads of holding register will latch the corresponding pulse accumulator value to its holding register. Pulse Accumulators There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC buffered channels. A pulse accumulator counts the number of active edges at the input of its channel. The active edge can be programmed through the TCTL4 register (for the 8-bit pulse accumulators and the 16-bit pulse accumulator PACB) and MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Functional Description the PEDGE bit in the PACTL register (for the 16-bit pulse accumulator PACA). The user can prevent 8-bit pulse accumulators counting further than $FF by PACMX control bit in ICSYS. In this case a value of $FF means that 255 counts or more have occurred. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... See Figures 71 (page 411) and 72 (page 412) for Block Diagrams of 8-bit and 16-bit accumulators. There are two modes of operation for the pulse accumulators. Pulse Accumulator latch mode The value of the pulse accumulator is transferred to its holding register when the modulus down-counter reaches zero, a write $0000 to the modulus counter or when the force latch control bit ICLAT is written. At the same time the pulse accumulator is cleared. Pulse Accumulator queue mode When queue mode is enabled, reads of an input capture holding register will transfer the contents of the associated pulse accumulator to its holding register. At the same time the pulse accumulator is cleared. Modulus Down-Counter The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used to latch the values of the IC registers and the pulse accumulators to their holding registers. The action of latching can be programmed to be periodic or only once. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Interrupts This section describes interrupts originated by the ECT block.The MCU must service the interrupt requests. Table 72 lists the interrupts generated by the ECT to communicate with the MCU. Table 72 ECT Interrupts $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFCA, $FFCB $FFC8, $FFC9 $FFDA, $FFDB $FFDC, $FFDD $FFDE, $FFDF Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Interrupt ECTCH0 ECTCH1 ECTCH2 ECTCH3 ECTCH4 ECTCH5 ECTCH6 ECTCH7 ECTMCUFI ECTPABO ECTPAAI ECTPAAO ECTOVI Vector Address Source Timer channel 0 Timer channel 1 Timer channel 2 Timer channel 3 Timer channel 4 Timer channel 5 Timer channel 6 Timer channel 7 Modulus down counter underflow Pulse Accumulator B overflow Pulse Accumulator A input edge Pulse Accumulator A overflow Timer overflow Description Active high timer channel interrupts 0 Active high timer channel interrupts 1 Active high timer channel interrupts 2 Active high timer channel interrupts 3 Active high timer channel interrupts 4 Active high timer channel interrupts 5 Active high timer channel interrupts 6 Active high timer channel interrupts 7 Active high modulus counter interrupt Active high pulse accumulator B interrupt Active high pulse accumulator A input interrupt Pulse accumulator overflow interrupt Timer Overflow interrupt Description of Interrupt Operation Channel [7:0] Interrupt (ECTCH(0-7)) The ECT only originates interrupt requests. The following is a description of how the ECT makes a request and how the MCU should acknowledge that request. This active high output will be asserted by the module to request a timer channel 7–0 interrupt to be serviced by the system controller. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Interrupts Modulus Down Counter Underflow Interrupt (ECTMCUFI) Pulse Accumulator B Overflow Interrupt (ECTPABO) Pulse Accumulator A Input Interrupt (ECTPAAI) Pulse Accumulator A Overflow Interrupt (ECTPAAO) Timer Overflow Interrupt (ECTOVI) This active high output will be asserted by the module to request a modulus counter underflow interrupt to be serviced by the system controller. This active high output will be asserted by the module to request a timer pulse accumulator B overflow interrupt to be serviced by the system controller. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... This active high output will be asserted by the module to request a timer pulse accumulator A input interrupt to be serviced by the system controller. This active high output will be asserted by the module to request a timer pulse accumulator A overflow interrupt to be serviced by the system controller. This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller. MC9S12T64Revision 1.1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Enhanced Capture Timer (ECT) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Overview The SCI allows asynchronous serial communications with peripheral devices and other CPUs. Features The SCI includes these distinctive features: • • • • • • Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 13-bit baud rate selection Programmable 8-bit or 9-bit data format Separately enabled transmitter and receiver Programmable transmitter output parity MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) • Two receiver wake-up methods: – Idle line wake-up – Address mark wake-up • Interrupt-driven operation with eight flags: – Transmitter empty – Transmission complete – Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • • • • Receiver framing error detection Hardware parity checking 10/13 bit software selectable break character length 1/16 bit-time noise detection Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. Run Mode Normal mode of operation. Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCIxCR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Block Diagram • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Stop Mode The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the bus clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. Block Diagram Figure 74 is a block diagram of the SCI. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCI Data Register IDLE RX Data In Receive Shift Register IRQ Generation IRQ RDRF/OR IRQ To CPU IRQ O R I N G Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Bus Clk Receive & Wake Up Control BAUD Generator ÷16 Data Format Control Transmit Control Transmit Shift Register SCI Data Register IRQ Generation TDRE IRQ TC IRQ TXData Out Figure 74 SCI Block Diagram External Pin Descriptions RXD (PS0, PS2) SCI receive pin. This pin serves as receive data input of SCI. When the SCI operates in single wire mode (LOOPS=1 in SCRxCR1 register), this channel is unused and corresponding MCU pins (PS0, PS2) can be used as general purpose I/O. TXD (PS1, PS3) SCI transmit pin. This pin serves as transmit data output of SCI. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Map Register Map Register name (1) Bit 7 0 6 0 5 0 4 3 2 1 Bit 0 Address offset SCI0 SCI1 Read: SCIxBDH Write: SCIxBDL Read: Write: SBR12 SBR11 SBR10 SBR9 SBR8 $00C8 $00D0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 $00C9 $00D1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SCIxCR1 Read: LOOPS SCISWAI Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: TIE TDRE TCIE TC RSRC M WAKE ILT PE PT $00CA $00D2 SCIxCR2 RIE RDRF ILIE IDLE TE OR RE NF RWU FE SBK PF $00CB $00D3 SCIxSR1 $00CC $00D4 SCIxSR2 0 0 0 0 0 BRK13 0 TXDIR 0 RAF $00CD $00D5 SCIxDRH R8 T8 R6 T6 0 0 0 0 $00CE $00D6 SCIxDRL R7 T7 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 $00CF $00D7 = Reserved or unimplemented Figure 75 SCI Register Quick Reference 1. Where: x = 0 for SCI0, or 1 for SCI1 NOTE: Register Address = Base Address (INITRG) + Address Offset MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register location do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SCI Baud Rate Registers (SCIxBDH/L) Bit 7 Read: Write: Reset: 0 0 Where: x = 0 for SCI0, or 1 for SCI1 Address Offset: $00C8 (SCI0BDH), $00D0 (SCI1BDH) 6 0 0 5 0 0 4 SBR12 0 3 SBR11 0 2 SBR10 0 1 SBR9 0 Bit 0 SBR8 0 = Unimplemented or Reserved Address Offset: $00C9 (SCI0BDL), $00D1 (SCI1BDL) Bit 7 Read: Write: Reset: SBR7 0 6 SBR6 0 5 SBR5 0 4 SBR4 0 3 SBR3 0 2 SBR2 1 1 SBR1 0 Bit 0 SBR0 0 Read: anytime. If only SCIxBDH is written to, a read will not return the correct data until SCIxBDL is written to as well, following a write to SCIxBDH. Write: anytime. Writing to SCIxBDH has no effect without writing to SCIxBDL, since writing to SCIxBDH puts the data in a temporary location until SCIxBDL is written to. The SCI Baud Rate Register is used by the counter to determine the baud rate of the SCI. The formula for calculating the baud rate is: SCI baud rate = Bus Clock / (16 x BR), MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions where BR is the content of the SCI baud rate registers, bits SBR12 through SBR0. The baud rate registers can contain a value from 1 to 8191. SBR12–SBR0 — SCI Baud Rate Bits The baud rate for the SCI is determined by these 13 bits. NOTE: SCI Control Register 1 (SCIxCR1) Where: x = 0 for SCI0, or 1 for SCI1 Address Offset: $00CA (SCI0CR1), $00D2 (SCI1CR1) Bit 7 Read: Write: Reset: LOOPS 0 6 SCISWAI 0 5 RSRC 0 4 M 0 3 WAKE 0 2 ILT 0 1 PE 0 Bit 0 PT 0 = Unimplemented or Reserved Read: anytime Write: anytime LOOPS — Loop Select Bit LOOPS enables loop operation. In loop operation, the RxD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 1 = Loop operation enabled 0 = Normal operation enabled The receiver input is determined by the RSRC bit. SCISWAI — SCI Stop in Wait Mode Bit SCISWAI disables the SCI in wait mode. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family The baud rate generator is disabled until TE or RE bits in SCIxCR2 are set for the first time after reset. The baud rate generator is disabled when BR = 0. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 1 = SCI disabled in wait mode 0 = SCI enabled in wait mode RSRC — Receiver Source Bit When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. 1 = Receiver input connected externally to transmitter 0 = Receiver input internally connected to transmitter output Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Table 73 Loop Functions LOOPS 0 1 1 RSRC x 0 1 Function Normal operation Loop mode with Rx input internally connected to Tx output Single-wire mode with Rx input connected to TXD M — Data Format Mode Bit MODE determines whether data characters are eight or nine bits long. 1 = One start bit, nine data bits, one stop bit 0 = One start bit, eight data bits, one stop bit WAKE — Wakeup Condition Bit WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD. 1 = Address mark wakeup 0 = Idle line wakeup ILT — Idle Line Type Bit ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions PE — Parity Enable Bit PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 1 = Parity function enabled 0 = Parity function disabled PT — Parity Type Bit PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 1 = Odd parity 0 = Even parity SCI Control Register 2 (SCIxCR2) Where: x = 0 for SCI0, or 1 for SCI1 Address Offset: $00CB (SCI0CR2), $00D3 (SCI1CR2) Bit 7 Read: Write: Reset: TIE 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0 = Unimplemented or Reserved Read: anytime Write: anytime TIE — Transmitter Interrupt Enable Bit TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 1 = TDRE interrupt requests enabled 0 = TDRE interrupt requests disabled MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TCIE — Transmission Complete Interrupt Enable Bit TCIE enables the transmission complete flag, TC, to generate interrupt requests. 1 = TC interrupt requests enabled 0 = TC interrupt requests disabled RIE — Receiver Full Interrupt Enable Bit RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 1 = RDRF and OR interrupt requests enabled 0 = RDRF and OR interrupt requests disabled ILIE — Idle Line Interrupt Enable Bit ILIE enables the idle line flag, IDLE, to generate interrupt requests. 1 = IDLE interrupt requests enabled 0 = IDLE interrupt requests disabled TE — Transmitter Enable Bit TE enables the SCI transmitter and configures the TxD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble. 1 = Transmitter enabled 0 = Transmitter disabled RE — Receiver Enable Bit RE enables the SCI receiver. 1 = Receiver enabled 0 = Receiver disabled RWU — Receiver Wakeup Bit Standby state 1 = RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. 0 = Normal operation. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions SBK — Send Break Bit Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11, respectively 13 or 14 bits). 1 = Transmit break characters 0 = No break characters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SCI Status Register 1 (SCIxSR1) Where: x = 0 for SCI0, or 1 for SCI1 The SCIxSR1 and SCIxSR2 register provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI Data Register. It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing. Address Offset: $00CC (SCI0SR1), $00D4 (SCI1SR1) Bit 7 Read: Write: Reset: 1 TDRE 6 TC 1 5 RDRF 0 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0 Bit 0 PF 0 = Unimplemented or Reserved Read: anytime Write: has no meaning or effect TDRE — Transmit Data Register Empty Flag TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIxDRH/L) is empty and can receive a new value to transmit. Clear TDRE by reading SCI status register 1 (SCIxSR1) with TDRE set and then writing to SCI data register low (SCIxDRL). MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 1 = Byte transferred to transmit shift register; transmit data register empty 0 = No byte transferred to transmit shift register TC — Transmit Complete Flag TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD out signal becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCIxSR1) with TC set and then writing to SCI data register low (SCIxDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete). 1 = No transmission in progress 0 = Transmission in progress RDRF — Receive Data Register Full Flag RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCIxSR1) with RDRF set and then reading SCI data register low (SCIxDRL). 1 = Received data available in SCI data register 0 = Data not available in SCI data register IDLE — Idle Line Flag IDLE is set when 10 consecutive logic 1s (if M=0) or 11 consecutive logic 1s (if M=1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCIxSR1) with IDLE set and then reading SCI data register low (SCIxDRL). 1 = Receiver input has become idle 0 = Receiver input is either active now or has never become active since the IDLE flag was last cleared NOTE: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions OR — Overrun Flag OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCIxSR1) with OR set and then reading SCI data register low (SCIxDRL). 1 = Overrun 0 = No overrun NF — Noise Flag NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1 (SCIxSR1) and then reading SCI data register low (SCIxDRL). 1 = Noise 0 = No noise FE — Framing Error Flag FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag, but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCIxSR1) with FE set and then reading the SCI data register low (SCIxDRL). 1 = Framing error 0 = No framing error PF — Parity Error Flag PF is set when the parity enable bit, PE, is set and the parity of the received data does not match its parity bit. Clear PF by reading SCI status register 1 (SCIxSR1), and then reading SCI data register low (SCIxDRL). 1 = Parity error 0 = No parity error MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCI Status Register 2 (SCIxSR2) Where: x = 0 for SCI0, or 1 for SCI1 Address Offset: $00CD (SCI0SR2), $00D5 (SCI1SR2) Bit 7 Read: Write: Reset: 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 BRK13 0 1 TXDIR 0 Bit 0 RAF 0 Read: anytime Write: anytime; writing accesses SCI status register 2; writing to any bits except TXDIR and BRK13 has no effect BRK13 — Break Transmit character length This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit. 1 = Break character is 13 or 14 bit long 0 = Break Character is 10 or 11 bit long TXDIR — Transmitter pin data direction in Single-Wire mode. This bit determines whether the TxD pin is going to be used as an input or output, in the Single-Wire mode of operation. This bit is only relevant in the Single-Wire mode of operation. 1 = TxD pin to be used as an output in Single-Wire mode 0 = TxD pin to be used as an input in Single-Wire mode RAF — Receiver Active Flag RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 1 = Reception in progress 0 = No reception in progress MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family = Unimplemented or Reserved Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions SCI Data Registers (SCIxDRH/L) Where: x = 0 for SCI0, or 1 for SCI1 Address Offset: $00CE (SCI0DRH), $00D6 (SCI1DRH) Bit7 Read: Write: Reset: 0 R8 6 T8 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... = Unimplemented or Reserved Address Offset: $OOCF (SCI0DRL), $00D7 (SCI1DRL) Bit 7 Read: Write: Reset: R7 T7 0 6 R6 T6 0 5 R5 T5 0 4 R4 T4 0 3 R3 T3 0 2 R2 T2 0 1 R1 T1 0 Bit 0 R0 T0 0 = Unimplemented or Reserved Read: anytime; reading accesses SCI receive data register Write: anytime; writing accesses SCI transmit data register; writing to R8 has no effect R8 — Received Bit 8 R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). T8 — Transmit Bit 8 T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). R7–R0 — Received bits seven through zero for 9-bit or 8-bit data formats T7–T0 — Transmit bits seven through zero for 9-bit or 8-bit formats NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten. The same value is transmitted until T8 is rewritten. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) NOTE: NOTE: In 8-bit data format, only SCI data register low (SCIxDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIxDRH), then SCIxDRL. Functional Description Freescale Semiconductor, Inc... This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 76 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, NRZ serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description SCI DATA REGISTER R8 RXD RECEIVE SHIFT REGISTER RE RECEIVE AND WAKEUP CONTROL RWU LOOPS RSRC M NF FE PF RAF IDLE RDRF BUS CLOCK BAUD RATE GENERATOR OR RIE WAKE DATA FORMAT CONTROL ILT PE PT TE ILIE IDLE INTERRUPT REQUEST RDRF/OR INTERRUPT REQUEST SBR12–SBR0 ÷16 TRANSMIT CONTROL LOOPS SBK RSRC TDRE TC TIE TDRE INTERRUPT REQUEST TC INTERRUPT REQUEST T8 TRANSMIT SHIFT REGISTER SCI DATA REGISTER TCIE TXD Figure 76 Detailed SCI Block Diagram Data Format The SCI uses the standard NRZ mark/space data format illustrated in Figure 77 below. 8-BIT DATA FORMAT BIT M IN SCIxCR1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY OR DATA BIT BIT 7 NEXT START STOP BIT BIT 9-BIT DATA FORMAT BIT M IN SCIxCR1 SET START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY OR DATA NEXT BIT START BIT 7 BIT 8 STOP BIT BIT Figure 77 SCI Data Formats MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits. Table 74 Example of 8-bit Data Formats Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Start Bit 1 1 1 Data Bits 8 7 7 Address Bits 0 0 1(1) Parity Bits 0 1 0 Stop Bit 1 1 1 1. The address bit identifies the frame as an address character. See section on Receiver Wakeup. When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIxDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 75 Example of 9-Bit Data Formats Start Bit 1 1 1 Data Bits 9 8 8 Address Bits 0 0 1(1) Parity Bits 0 1 0 Stop Bit 1 1 1 1. The address bit identifies the frame as an address character. See section on Receiver Wakeup. Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12–SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIxBDH and SCIxBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Baud rate generation is subject to two sources of error: • • Integer division of the bus clock may not give the exact target frequency. Synchronization with the bus clock can cause phase shift. Table 76 lists some examples of achieving target baud rates with a bus clock frequency of 16 MHz SCI baud rate = Bus Clock / (16 *SBR[12:0]) Table 76 Baud Rates (Example: Bus Clock = 16.0 MHz) Bits SBR[12-0] 13 26 52 104 208 417 833 1664 Receiver Clock (Hz) 1,230,769 615,385 307,692 153,846 76,923 38,369 19,207 9,598 Transmitter Clock (Hz) 76923 38,462 19,231 9615 4808 2398 1200 600 Target Baud Rate 76800 38,400 19,200 9600 4800 2400 1200 600 Error (%) 0.16 0.16 0.16 0.16 0.16 -0.08 0.04 -0.02 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... NOTE: The maximum divider rate is 8191. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Transmitter INTERNAL BUS MODULE CLOCK BAUD DIVIDER ÷ 16 SCI DATA REGISTERS STOP SBR12–SBR0 START 11-BIT TRANSMIT SHIFT REGISTER 8 MSB 7 6 5 4 3 2 1 0 M H L TX LOAD FROM SCIDR T8 LOOP CONTROL BREAK (ALL 0s) TO RECEIVER LOOPS RSRC PE PT PARITY GENERATION TRANSMITTER CONTROL TDRE INTERRUPT REQUEST TDRE TIE TC TCIE TE SBK BRK13 TC INTERRUPT REQUEST Figure 78 Transmitter Block Diagram Transmitter Character Length The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCIxCR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIxDRH) is the ninth bit (bit 8). To transmit data, the MCU writes the data bits to the SCI data registers (SCIxDRH/SCIxDRL), which in turn are transferred to the transmitter Character Transmission MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SHIFT ENABLE PREAMBLE (ALL ONES) Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description shift register. The transmit shift register then shifts a frame out through the TX output signal, after it has prefaced it with a start bit and appended it with a stop bit. The SCI data registers (SCIxDRH and SCIxDRL) are the write-only buffers between the internal data bus and the transmit shift register. The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIxDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIxDRH/SCIxDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 9. Configure the SCI: a. Select a baud rate. Write this value to the SCI baud registers (SCIxBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIxBDH has no effect without also writing to SCIxBDL. b. Write to SCIxCR1 to configure word length, parity, and other configuration bits (LOOPS, RSRC, M, WAKE, ILT, PE, PT). c. Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCIxCR2 register bits (TIE, TCIE, RIE, ILIE, TE, RE, RWU, SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 10. Transmit Procedure for Each Byte: a. Poll the TDRE flag by reading the SCIxSR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. b. If the TDRE flag is set, write the data to be transmitted to SCIxDRH/L, where the ninth bit is written to the T8 bit in SCIxDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 11. Repeat step 2 for each subsequent transmission. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) NOTE: The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIxDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (msb) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCIxSR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCIxCR2) is also set, the TDRE flag generates a transmitter interrupt request. When the transmit shift register is not transmitting a frame, the TX output signal goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCIxCR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles of minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIxDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description 4. Write the first byte of the second message to SCIxDRH/L. Break Characters Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCIxCR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCIxCR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: • • • • Sets the framing error flag, FE Sets the receive data register full flag, RDRF Clears the SCI data registers (SCIxDRH/L) May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see SCI Status Register 1 (SCIxSR1) and SCI Status Register 2 (SCIxSR2)) Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCIxCR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TX output signal becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TX output signal. Setting TE after the stop bit appears on TX output signal causes data previously written to the SCI data register to be lost. Toggle the TE bit MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. NOTE: If the TE bit is clear and the transmission is complete, the SCI is not the master of the TxD pin. Receiver INTERNAL BUS SBR12–SBR0 SCI DATA REGISTER STOP BAUD DIVIDER 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0 RXD LOOP CONTROL RE RAF LOOPS RSRC M WAKE ILT PE PT DATA RECOVERY ALL ONES H MSB FROM TXD FE NF WAKEUP LOGIC PE RWU PARITY CHECKING IDLE ILIE R8 IDLE INTERRUPT REQUEST RDRF RDRF/OR INTERRUPT REQUEST RIE OR Figure 79 SCI Receiver Block Diagram Receiver Character Length The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCIxCR1) determines the MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com START MODULE CLOCK L Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIxDRH) is the ninth bit (bit 8). Character Reception During an SCI reception, the receive shift register shifts a frame in from the RX input signal. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCIxSR1) becomes set, indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCIxCR2) is also set, the RDRF flag generates an RDRF interrupt request. Data Sampling The receiver samples the RX input signal at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 80) is re-synchronized: • • After every start bit After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) RX Input Signal SAMPLES 1 1 1 1 1 1 1 1 0 0 0 START BIT LSB 0 0 0 0 START BIT QUALIFICATION START BIT VERIFICATION DATA SAMPLING RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT CLOCK COUNT RT4 RESET RT CLOCK Figure 80 Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 77 summarizes the results of the start bit verification samples. Table 77 Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 78 summarizes the results of the data bit samples. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Table 78 Data Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0 NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 79 summarizes the results of the stop bit samples. Table 79 Stop Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 In Figure 81, the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) RX Input Signal SAMPLES 1 1 1 0 1 1 1 0 0 0 START BIT LSB 0 0 0 0 RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT CLOCK COUNT RT3 RESET RT CLOCK Figure 81 Start Bit Search Example 1 In Figure 82, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. PERCEIVED START BIT RX Input Signal SAMPLES 1 1 1 1 1 0 1 0 0 0 0 ACTUAL START BIT LSB 0 RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT CLOCK COUNT RESET RT CLOCK Figure 82 Start Bit Search Example 2 In Figure 83, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... RT8 RT9 RT1 RT2 RT3 RT4 RT5 RT6 RT7 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. PERCEIVED START BIT RX Input Signal SAMPLES 1 1 1 0 0 1 0 0 0 0 ACTUAL START BIT LSB RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT CLOCK COUNT RESET RT CLOCK Figure 83 Start Bit Search Example 3 Figure 84 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. RX Input Signal SAMPLES 1 1 1 1 1 1 1 1 1 0 PERCEIVED AND ACTUAL START BIT LSB 1 0 RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT CLOCK COUNT RESET RT CLOCK Figure 84 Start Bit Search Example 4 Figure 85 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT2 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT3 RT9 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. RX Input Signal SAMPLES 1 1 1 1 1 1 1 1 1 0 0 1 START BIT NO START BIT FOUND 1 0 0 0 0 0 0 0 0 LSB RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT CLOCK COUNT RESET RT CLOCK Figure 85 Start Bit Search Example 5 In Figure 86, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. RX Input Signal SAMPLES 1 1 1 1 1 1 1 1 1 0 0 0 START BIT LSB 0 1 0 1 RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT CLOCK COUNT RESET RT CLOCK Figure 86 Start Bit Search Example 6 MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... RT4 RT5 RT6 RT7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT3 RT1 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCIxSR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. Baud Rate Tolerance Slow Data Tolerance Figure 87 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 DATA SAMPLES Figure 87 Slow Data For an 8-bit data character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles +10 RT cycles =154 RT cycles. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) With the misaligned character shown in Figure 87, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((154 – 147) / 154) x 100 = 4.54% For a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 87, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((170 – 163) / 170) x 100 = 4.12% Fast Data Tolerance Figure 88 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. STOP IDLE OR NEXT FRAME RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 DATA SAMPLES Figure 88 Fast Data For an 8-bit data character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description With the misaligned character shown in Figure 88, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((154 – 160) / 154) x 100 = 3.90% For a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 88, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((170 – 176) / 170) x 100 = 3.53% Receiver Wakeup To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCIxCR2) puts the receiver into a standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIxDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCIxCR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. Idle input line wakeup (WAKE = 0) In this wakeup method, an idle condition on the RX input signal clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RX input signal. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCIxCR1). Address mark wakeup (WAKE = 1) In this wakeup method, a logic 1 in the most significant bit (msb) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the msb position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RX input signal. The logic 1 msb of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... NOTE: With the WAKE bit clear, setting the RWU bit after the RX input signal has been idle can cause the receiver to wake up immediately. Single-Wire Operation Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RxD pin is disconnected from the SCI. The SCI uses the TxD pin for both receiving and transmitting. MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description TRANSMITTER TXD Output Signal TXD Input Signal RECEIVER RxD Figure 89 Single-Wire Operation (LOOPS = 1, RSRC = 1) Freescale Semiconductor, Inc... Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCIxCR1). Setting the LOOPS bit disables the path from the RX input signal to the receiver. Setting the RSRC bit connects the receiver input to the output of the TxD pin driver. Both the transmitter and receiver must be enabled (TE=1 and RE=1).The TXDIR bit (SCIxSR2[1]) determines whether the TxD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. Loop Operation In loop operation the transmitter output goes to the receiver input. The RX input signal is disconnected from the SCI. TRANSMITTER TX Output Signal RECEIVER RxD Figure 90 Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCIxCR1). Setting the LOOPS bit disables the path from the RX input signal to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Interrupts Recovery from Wait Mode The SCI interrupt request can be used to bring the CPU out of wait mode. System Level Interrupt Sources Table 80 SCI Interrupt Sources Interrupt Vector Address SCI0 SCI1 Source Description Active high level detect. Indicates that a byte was transferred from SCIxDRH/L to the transmit shift register. Active high level detect. Indicates that a transmit is complete. Active high level detects. The RDRF interrupt indicates that received data is available in the SCI data register. Active high level detects. This interrupt indicates that an overrun condition has occurred. Active high level detect. Indicates that receiver input has become idle. TDRE TC RDRF $FFD6, $FFD7 $FFD4, $FFD5 SCIxSR1[7] SCIxSR1[6] SCIxSR1[5] OR IDLE SCIxSR1[3] SCIxSR1[4] The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The SCI only has a single interrupt line (SCI Interrupt signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. TDRE Description The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit shift register (SCIxDRH/L) is empty and that a new byte can be written to the SCIxDRH/L for transmission.Clear TDRE by MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 80 lists the five interrupt sources of the SCI. The local enables for the five SCI interrupt sources, are described in Table 80. Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Interrupts reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIxDRL). TC Description The TC interrupt is set by the SCI when a transmission has been completed. A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TxD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCIxSR1) with TC set and then writing to SCI data register low (SCIxDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCIxSR1) and then reading SCI data register low (SCIxDRL). The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCIxSR1) and then reading SCI data register low (SCIxDRL). The IDLE interrupt is set when 10 consecutive logic 1s (if M=0) or 11 consecutive logic 1s (if M=1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCIxSR1) with IDLE set and then reading SCI data register low (SCIxDRL). RDRF Description OR Description IDLE Description MC9S12T64Revision 1.1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... Serial Communications Interface (SCI) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Overview The Serial Peripheral Interface module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Features The Serial Peripheral Interface includes these distinctive features: • • • • Master mode and slave mode Bi-directional mode Slave select output Mode fault error flag with CPU interrupt capability Double-buffered operation Serial clock with programmable polarity and phase Control of SPI operation during wait mode Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... • • • Modes of Operation The SPI functions in three modes, run, wait, and stop. • Run Mode This is the basic mode of operation. • Wait Mode SPI operation in wait mode is a configurable low power mode. Depending on the state of internal bits, the SPI can operate normally when the CPU is in wait mode or the SPI clock generation can be turned off and the SPI module enters a power conservation state during wait mode. During wait mode, any master transmission in progress stops if the SPISWAI bit is set in the SPICR2 register. Reception and transmission of a byte as slave continues so that the slave is synchronized to the master. • Stop Mode The SPI is inactive in stop mode for reduced power consumption. The STOP instruction does not affect or depend on SPI register states. Again, reception and transmission of a byte as slave continues to stay synchronized with the master. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Block Diagram This is a high level description only, detailed descriptions of operating modes are contained in section Low Power Mode Options. Block Diagram Figure 91 is a block diagram of the Serial Peripheral Interface. BAUD RATE GENERATOR DIVIDER 2 4 8 16 32 64 128 256 8-BIT SHIFT REGISTER S M M S MISO SPI DATA REGISTER SELECT SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 MOSI PIN CONTROL LOGIC BAUD CLOCK MUXED CLOCK S M SS SPI BAUD RATE REGISTER CLOCK LOGIC SCK SPI CONTROL MSTR CPHA CPOL LSBFE SPC0 SPI STATUS REGISTER SPI CONTROL REGISTER 1 BIDIROE SPI CONTROL REGISTER 2 IPBUS Figure 91 SPI Block Diagram MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family BUS CLOCK Freescale Semiconductor, Inc... SPTEF SPI INTERRUPT REQUEST MODF SPIF Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) External Pin Descriptions MISO (PS4) Master In / Slave Out. This pin is used to transmit data out of the SPI module when it is configured as a Slave, and receive data when it is configured as Master MOSI (PS5) SCK (PS6) Serial Clock. This pin is used to output the clock with respect to which the SPI module tranfers and receives data. SS (PS7) Slave Select. This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Master Out/ Slave In. This pin is used to transmit data out of the SPI module when it is configured as a Master, and receive data when it is configured as Slave. Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Map Register Map Register Name SPICR1 Read: Write: Bit 7 SPIE 6 SPE 5 SPTIE 4 MSTR 3 CPOL 2 CPHA 1 SSOE Bit 0 LSBFE Address Offset $00D8 Freescale Semiconductor, Inc... Write: SPIBR Read: Write: 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 $00DA SPISR Read: Write: SPIF 0 SPTEF MODF 0 0 0 0 $00DB SPI Reserved Read: Write: 0 0 0 0 0 0 0 0 $00DC SPIDR Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 $00DD SPI Reserved Read: Write: 0 0 0 0 0 0 0 0 $00DE SPI Reserved Read: Write: 0 0 0 0 0 0 0 0 $00DF = Unimplemented or Reserved Figure 92 SPI Register Summary NOTE: Register Address = Base Address (INITRG) + Address Offset MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family SPICR2 Read: 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 $00D9 Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Address Offset: $00D8 Bit 7 Read: Write: Reset: SPIE 0 6 SPE 0 5 SPTIE 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SSOE 0 Bit 0 LSBFE 0 Read: anytime Write: anytime SPIE — SPI Interrupt Enable Bit This bit enables SPI interrupts each time the SPIF or MODF status flag is set. 1 = SPI interrupts enabled. 0 = SPI interrupts disabled. SPE — SPI System Enable Bit This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. 1 = SPI port pins are dedicated to SPI functions. 0 = SPI disabled. (lower power consumption) SPTIE — SPI Transmit Interrupt Enable This bit enables SPI interrupt generated each time the SPTEF flag is set. 1 = SPTEF interrupt enabled. 0 = SPTEF interrupt disabled. MSTR — SPI Master/Slave Mode Select Bit MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SPI Control Register 1 (SPICR1) Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions 1 = Master mode 0 = Slave mode CPOL — SPI Clock Polarity Bit This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. 1 = Active-low clocks selected; SCK idles high 0 = Active-high clocks selected; SCK idles low Freescale Semiconductor, Inc... CPHA — SPI Clock Phase Bit This bit is used to shift the SCK serial clock. 1 = The first SCK edge is issued at the beginning of the 8-cycle transfer operation 0 = The first SCK edge is issued one-half cycle into the 8-cycle transfer operation SSOE — Slave Select Output Enable The SS output feature is enabled only in the master mode by asserting the SSOE as shown in Table 81. Table 81 SS Input / Output Selection MOD SSOE Master Mode Slave Mode FEN 0 0 SS not used by SPI SS input 0 1 SS not used by SPI SS input 1 0 SS input with MODF feature SS input 1 1 SS output SS input LSBFE — SPI LSB-First Enable This bit does not affect the position of the msb and lsb in the data register. Reads and writes of the data register always have the msb in bit 7. 1 = Data is transferred least significant bit first. 0 = Data is transferred most significant bit first. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPI Control Register 2 (SPICR2) Address Offset: $00D9 Bit 7 Read: Write: Reset: 0 0 0 0 6 0 5 0 4 MODFEN 0 3 BIDIROE 0 2 0 0 1 SPISWAI 0 Bit 0 SPC0 0 = Unimplemented or Reserved Read: anytime Write: anytime; writes to unimplemented bits have no effect MODFEN — Mode Fault Enable Bit This bit when set allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as master and the MODFEN bit is low, then the SS pin is not used by the SPI. When the SPI is enabled as a slave, the SS is available only as an input regardless of the value of MODFEN. 1 = Enable setting the MODF error 0 = Disable the MODF error BIDIROE — Output enable in the Bidirectional mode of operation This bit along with the MSTR bit of SPCR1 is used to enable the output buffer when the SPI is configured in bidirectional mode. 1 = Output buffer enabled 0 = Output buffer disabled SPISWAI — SPI Stop in Wait Mode Bit This bit is used for power conservation while in wait mode. 1 = Stop SPI clock generation when in wait mode 0 = SPI clock operates normally in wait mode SPC0 — Serial Pin Control Bit 0 With the MSTR control bit, this bit enables bidirectional pin configurations as shown in Table 82. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions Table 82 Bidirectional Pin Configurations Pin Mode A Normal B C Bidirectional D SPC0 0 1 MSTR 0 1 0 1 MISO (1) MOSI (2) Slave Out Slave In Master In Master Out Slave I/O ----Master I/O SCK (3) SCK in SCK out SCK in SCK out SS (4) SS in SS I/O SS In SS I/O 1. Slave output is enabled if BIDIROE bit = 1, SS = 0, and MSTR = 0 (C) 2. Master output is enabled if BIDIROE bit = 1 and MSTR = 1 (D) Freescale Semiconductor, Inc... 3. SCK output is enabled if MSTR = 1 (B, D) 4. SS output is enabled if MODFEN bit = 1, SSOE = 1, and MSTR = 1 (B, D). SPI Baud Rate Register (SPIBR) Address Offset: $00DA Bit 7 Read: Write: Reset: 0 0 6 SPPR2 0 5 SPPR1 0 4 SPPR0 0 3 0 0 2 SPR2 0 1 SPR1 0 Bit 0 SPR0 0 = Unimplemented or Reserved Read: anytime Write: anytime; writes to unimplemented bits have no effect NOTE: Writing to this register during data transfers may cause spurious results SPPR2–SPPR0 — SPI Baud Rate Preselection Bits SPR2–SPR0 — SPI Baud Rate Selection Bits These bits are used in the determination of the SPI baud rates as shown in the Table 83. For details see SPI Baud Rate Generation in page 479. The bus clock divisor equation is as follows; ( SPR + 1 ) BusClockDivisor = ( SPPR + 1 ) • 2 MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) BusClock BaudRate = ------------------------------------------------BusClockDivisor Table 83 SPI Baud Rate Selection (16 MHz Bus Clock) SPPR2 0 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bus Clock Divisor 2 (1) 4 (1) Baud Rate 8 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 4 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 2.67 MHz 1.33 MHz 666.67 KHz 333.33 KHz 166.67 KHz 83.33 KHz 41.67 KHz 20.83 KHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 MHz 8 16 32 64 128 256 4 (1) 8 16 32 64 128 256 512 6 12 24 48 96 192 384 768 8 16 32 64 128 256 512 1024 MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions Table 83 SPI Baud Rate Selection (16 MHz Bus Clock) (Continued) SPPR2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bus Clock Divisor 10 20 40 80 160 320 640 1280 12 24 48 96 192 384 768 1536 14 28 56 112 224 448 896 1792 16 32 64 128 256 512 1024 2048 Baud Rate 1.6 MHz 800 KHz 400 KHz 200 KHz 100 KHz 50 KHz 25 KHz 12.5 KHz 1.33 MHz 666.67 KHz 333.33 KHz 166.67 KHz 83.33 KHz 41.67 KHz 20.83 KHz 10.42 KHz 1.14 MHz 571.43 KHz 285.71 KHz 142.86 KHz 71.43 KHz 35.71 KHz 17.86 KHz 8.93 KHz 1 MHz 500 MHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz 7.81 KHz 1. These Bus Clock Divisors are not supported in slave mode of SPI. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPI Status Register (SPISR) Address Offset: $00DB Bit 7 Read: Write: Reset: 0 0 1 0 0 0 0 0 SPIF 6 0 5 SPTEF 4 MODF 3 0 2 0 1 0 Bit 0 0 = Unimplemented or Reserved Read: anytime Write: has no meaning or effect SPIF — SPI Interrupt Flag This bit is set after the eighth SCK cycle in a data transfer and is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 1 = New data Copied to SPIDR 0 = Transfer not yet complete SPTEF — SPI Transmit Empty Interrupt Flag NOTE: There is an errata information about the SPTEF flag. See MC9S12T64 Errata Sheet for details. This bit is set when there is room in the transmit data buffer. It is cleared by reading SPISR with SPTEF set, followed by writing a data value to the transmit buffer at SPIDR. SPISR must be read with SPTEF=1 before writing data to SPIDR or the SPIDR write will be ignored. SPTEF generates an SPTEF CPU interrupt request if the SPTIE bit in the SPICR1 is also set. SPTEF is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift register and no transfer in progress), data written to SPIDR is transferred to the shifter almost immediately so SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 1 = SPI Data register empty 0 = SPI Data register not empty NOTE: Do not write to the SPI data register unless the SPTEF bit is high. Any such write to the SPI Data Register before reading SPTEF=1 is effectively ignored MODF — Mode Fault Flag Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... NOTE: There is an errata information about the mode fault behavior. See MC9S12T64 Errata Sheet for details. This bit is set if the SS input becomes low while the SPI is configured as a master. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. The MODF flag is set only if the MODFEN bit of SPICR2 register is set, Refer to MODFEN bit description in SPI Control Register 2 (SPICR2). 1 = Mode fault has occurred. 0 = Mode fault has not occurred. SPI Data Register (SPIDR) Address Offset: $00DD Bit 7 Read: Write: Reset: Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 2 0 Bit 0 Bit 0 0 Read: anytime; normally read only after SPIF is set Write: anytime; see SPTEF bit in SPISR register The SPI Data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) transmitted immediately after the previous transmission has completed. The SPI Transmitter empty flag in SPISR indicates when the SPI data register is ready to accept new data. NOTE: Do not write to the SPI data register unless the SPTEF bit is high. Reading the data can occur anytime from after the SPIF is set to before the end of the next transfer. If the SPIF is not serviced by the end of the successive transfers, those data bytes are lost and the data within the SPIDR retains the first byte until SPIF is serviced. NOTE: After reset the content of the SPI Shift Register is undefined until a data byte is stored into SPIDR. Functional Description The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • • • • Slave select (SS) Serial clock (SCK) Master out/slave in (MOSI) Master in/slave out (MISO) The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the SCK clock from the master; data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description A write to the SPI data register puts data into the transmit buffer if the previous transmission was complete. When a transfer is complete, received data is moved into a receive data register. Data may be read from this double-buffered system any time before the next transfer is complete. This 8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the shifter. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by shifting the clock by a half cycle or by not shifting the clock (see Transmission Formats). The SPI can be configured to operate as a master or as a slave. When MSTR in SPI control register1 is set, the master mode is selected; when the MSTR bit is clear, the slave mode is selected. Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock. The SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register control the baud rate generator and determine the speed of the shift register. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and MSTR control bits. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The SS pin is normally an input which should remain in the inactive high state. However, in the master mode, if both MODFEN bit and SSOE bit are set, then the SS pin is the slave select output. The SS output becomes low during each transmission and is high when the SPI is in the idling state. If the SS input becomes low while the SPI is configured as a master, it indicates a mode fault error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. In this case, the SPI immediately clears the output buffer enables associated with the MISO, MOSI (or MOMI), and SCK pins so that these pins become inputs. This mode fault error also clears the MSTR control bit and sets the mode fault (MODF) flag in the SPI status register. If the SPI interrupt enable bit (SPIE) is set when the MODF bit gets set, then an SPI interrupt sequence is also requested NOTE: There is an errata information about the mode fault behavior. See MC9S12T64 Errata Sheet for details. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Transmission Formats). Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register1 is clear. In slave mode, SCK is the SPI clock input from the master, and SS is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit in SPI control register 2 and the MSTR control bit. While in slave mode, the SS input controls the serial data output pin; if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register takes place. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE: When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB of the SPI shifter. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB of the SPI shifter. NOTE: In slave mode, the control bits CPHA and CPOL of the SPI should be configured only when SPI is disabled else it may lead to incorrect data transfer. If the SPI is disabled, e.g. for configuration purpose, the dedicated SPI pins become GPIO pins. Care must be taken to avoid driver collisions. As recommended action, GPIO pins should be configured as high impedance inputs, before disabling the SPI. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set. NOTE: There is an errata information about CPHA=1 transfer format in slave mode. See MC9S12T64 Errata Sheet for details. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. Freescale Semiconductor, Inc... MASTER SPI MISO MOSI SCK BAUD RATE GENERATOR SS MISO MOSI SCK SS SLAVE SPI SHIFT REGISTER SHIFT REGISTER VDD Figure 93 Master/Slave Transfer Block Diagram MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description Clock Phase and Polarity Controls Using two bits in the SPI control register1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE: It is recommended that software writes to the SPI control register to change CPHA, CPOL or MSTR bits only in the idle state of the SPI. If these bits are changed during the transmission, data transmission gets corrupted. The first edge on the SCK line is used to clock the first data bit of slave into the master and the first data bit of master into the slave. In some peripherals, the first bit of the slave's data is available at the slave data out pin as soon as the slave is selected. In this format, the first SCK edge is not issued until a half cycle into the 8-cycle transfer operation. The first edge of SCK is delayed a half cycle by clearing the CPHA bit. The SCK output from the master remains in the inactive state for a half SCK period before the first edge appears. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB of the shifter. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. CPHA = 0 Transfer Format MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family • Freescale Semiconductor, Inc... The SPIF flag in the SPI status register is set indicating that the transfer is complete. Figure 94 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description Transfer SCK (CPOL = 0) SCK (CPOL = 1) Begin End CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL tT Bit 1 Bit 6 tI tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. LSB Minimum 1/2 SCK for tT, tl, tL MSB Figure 94 SPI Clock Format 0 (CPHA = 0) The SS line should be deasserted at least for minimum idle time (half SCK cycle) between the successive transfers (SS should not be tied low all the times in this mode). If SS is not deasserted between the successive transmission then the new byte written to the data register would not be transmitted, instead the last received byte would be transmitted. CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin; the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family CHANGE O MOSI pin Freescale Semiconductor, Inc... If next transfer begins here SAMPLE I MOSI/MISO Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its most significant data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB of the SPI shifter. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pins on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered; data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th SCK edge: • Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. The SPIF flag bit in SPISR is set indicating that the transfer is complete. • Figure 95 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram since the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description Transfer SCK (CPOL = 0) SCK (CPOL = 1) Begin End CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL tT MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 tI tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): LSB Minimum 1/2 SCK for tT, tl, tL MSB tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. Figure 95 SPI Clock Format 1 (CPHA = 1) The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set after the last SCK edge in a data transfer operation to indicate that the transfer is complete though transfer is actually complete half SCK cycle later. SPI Baud Rate Generation Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the bus clock which results in the SPI baud rate. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family CHANGE O MOSI pin Freescale Semiconductor, Inc... If next transfer begins here SAMPLE I MOSI/MISO Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The bus clock divisor equation is shown in Figure 96. When all bits are clear (the default condition), the bus clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the bus clock divisor becomes 4. When the selection bits are 010, the bus clock divisor becomes 8, etc. Freescale Semiconductor, Inc... When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 83 for baud rate calculations for all bit conditions, based on a 16 MHz bus clock.The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. ( SPR + 1 ) BusClockDivisor = ( SPPR + 1 ) • 2 Figure 96 Bus Clock Divisor Equation Special Features SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 81. The mode fault feature is disabled while SS output is enabled. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description NOTE: Care must be taken when using the SS output feature in a multimaster system since the mode fault feature is not available for detecting system errors between masters. The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Normal Mode and Bidirectional Mode). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in the master mode and MOSI pin in the slave mode are not used by the SPI in Bidirectional Mode. Bidirectional Mode (MOMI or SISO) Table 84 Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0 Serial Out MOSI Serial In SPI MOSI Normal Mode SPC0 = 0 SPI Serial In MISO Serial Out MISO Serial Out MOMI BIDIROE Serial In BIDIROE SPI Serial Out SISO Bidirectional Mode SPC0 = 1 SPI Serial In . The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The bidirectional mode does not affect SCK and SS functions. Error Conditions The SPI has one error condition • Mode fault error Mode Fault Error In the special case where the MODFEN bit is cleared, the SS pin is a general purpose input/output pin for the SPI system configured in master mode. In this special case, the mode error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. When a mode fault error occurs, the MSTR bit in control register SPICR1 is cleared, MODF bit in the status register is set and the output enable for the SCK, MISO and MOSI pins are de-asserted. So SCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. NOTE: There is an errata information about the mode fault behavior. See MC9S12T64 Errata Sheet for details. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set but MISO (SISO) is not affected. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation; the MODF bit in the SPI status register is set automatically provided the MODFEN bit is set. Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Low Power Mode Options Low Power Mode Options SPI in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers can still be accessed, but clocks to the core of this module are disabled. Freescale Semiconductor, Inc... SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2. • • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. – If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the its operation mode at the start of wait mode (i.e. If the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE: Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. A SPIF flag and SPIDR copy is only generated if wait mode is entered or exited during a transmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur. SPI in Stop Mode The stop mode is equivalent to the wait mode with the SPISWAI bit set except that the stop mode is dependent on the system and cannot be controlled with the SPISWAI bit. Reset Initialization The reset values of registers and signals are described in Registers. All registers reset to a particular value. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit random data or the byte last received from the master before the reset. Reading from the SPIDR after reset will always read a byte of zeros. • Interrupts This section describes interrupts originated by the Serial Peripheral Interface. The MCU must service the interrupt requests. Table 85 lists the three sources of interrupts generated by the SPI module. The SPI module communicates with the MCU through one interrupt port. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Stop mode is dependent on the system. The SPI enters stop mode when the bus clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Interrupts Table 85 SPI Interrupt Signals Interrupt sources Mode Fault Transfer Complete SPI Transmitter Empty Vector Address Description Active high detect. MODF occurs when a logic zero occurs on the SS pin of a master SPI Active high detect. SPIF occurs after the last SCK cycle in a data transfer operation to indicate that the transfer is complete. Active high detect. SPTEF occurs when the SPI data register transfers a byte into the Transmit shift register. $FFD8, $FFD9 Description of Interrupt Operation MODF Description The Serial Peripheral Interface only originates interrupt requests. The following is a description of how the Serial Peripheral Interface makes a request and how the MCU should acknowledge that request. MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 81). Once MODF is set, the current transfer is halted and the following bit is changed: • MSTR=0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in SPI Status Register (SPISR). SPIF Description SPIF occurs when the SPI receives/transmits the last SCK edge in a data transfer operation. Once SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process which is described in SPI Status Register (SPISR). In the event that the SPIF is not serviced before the end of the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be ignored and no new data will be copied into the SPIDR. SPTEF occurs when the SPI Data register transfers a byte into the transmit buffer Once SPTEF is set, it does not clear until it is serviced. MC9S12T64Revision 1.1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com SPTEF Description Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... Serial Peripheral Interface (SPI) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. SPTEF has an automatic clearing process which is described in SPI Status Register (SPISR). Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Low Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 Overview The ATD module is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. The block is designed to be upwards compatible with the 68HC11 standard 8-bit A/D converter. In addition, there are new operating modes that are unique to the HC12 design. Features • • 8/10 Bit Resolution. 7 µsec, 10-Bit Single Conversion Time. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) • • • • • • • Sample Buffer Amplifier. Programmable Sample Time. Left/Right Justified, Signed/Unsigned Result Data. External Trigger Control. Conversion Completion Interrupt Generation. Analog Input Multiplexer for 8 Analog Input Channels. Analog/Digital Input Pin Multiplexing. 1 to 8 Conversion Sequence Lengths. Continuous Conversion Mode. Multiple Channel Scans. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... • • • Modes of Operation Conversion modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. The conversion modes for the ATD module are defined by the settings of three control bits and three control values. The control bits are ETRIGE in ATDCTL2, and MULT, SCAN in ATDCTL5. In brief, ETRIGE controls whether an external trigger is used to start a conversion sequence. MULT controls whether the sequence examines a single analog input channel or scans a number of different channels. SCAN determines if sequences are performed continuously. The control values are bits CC/CB/CA in ATDCTL5 which define the input channels to be examined; S8C/S4C/S2C/S1C in ATDCTL3 define the number of conversions in a sequence; SMP0/SMP1 in ATDCTL4 define the length of the sample time. MCU Operating Modes MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Modes of Operation Run Mode RUN mode for the ATD module is defined as the state where the ATD module is powered up and currently performing an A/D conversion. Complete assess to all control, status, and result registers is available. The module is consuming maximum power. Entering Wait Mode the ATD conversion either continues or aborts for low power depending on the logical value of the AWAIT bit in ATDCTL2 register. Entering Stop Mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This aborts any conversion sequence in progress. During recovery from Stop Mode, there must be a minimum delay for the Stop Recovery Time tSR before initiating a new ATD conversion sequence. The ATD module enters freeze mode when background debug mode (BDM) is active. In Freeze Mode the ATD module will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Wait Mode Freescale Semiconductor, Inc... Stop Mode Freeze Mode MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Block Diagram ATD Module Bus Clock Clock Prescaler ATD clock Results VRH VRL VDDA VSSA AN7 / ETRIG (PAD7) AN6 (PAD6) AN5 (PAD5) AN4 (PAD4) AN3 (PAD3) AN2 (PAD2) AN1 (PAD1) AN0 (PAD0) Successive Approximation Register (SAR) and DAC ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 + Sample & Hold 1 1 Comparator Analog MUX ATD Input Enable Register Port AD Data Register Figure 97 ATD Module Block Diagram MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Conversion Complete Interrupt Mode and Timing Control Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) External Pin Descriptions External Pin Descriptions The ATD module has a total of 12 external pins. AN7 / ETRIG (PAD7) This pin serves as the analog input Channel 7. It can be configured as an external trigger for the ATD conversion, or as general purpose digital input. AN5 (PAD5) This pin serves as the analog input Channel 5. It can be configured as general purpose digital input. AN4 (PAD4) This pin serves as the analog input Channel 4. It can be configured as general purpose digital input. AN3 (PAD3) This pin serves as the analog input Channel 3. It can be configured as general purpose digital input. AN2 (PAD2) This pin serves as the analog input Channel 2. It can be configured as general purpose digital input. AN1 (PAD1) This pin serves as the analog input Channel 1.It can be configured as general purpose digital input. AN0 (PAD0) This pin serves as the analog input Channel 0. It can also be configured as general purpose digital input. VRH, VRL VRH is the high reference voltage and VRL is the low reference voltage for ATD conversion. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... AN6 (PAD6) This pin serves as the analog input Channel 6. It can be configured as general purpose digital input. Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) VDDA, VSSA These pins are the power supplies for the analog circuitry of the ATD module block. Register Map ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Unimplemented Reserved for Factory Test ATDTEST1 Unimplemented ATDSTAT1 Unimplemented ATDDIEN Unimplemented Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write Reads to this register return unpredictable values. Reads to this register return unpredictable values. ADPU 0 SRES8 DJM SCF AFFC S8C SMP1 DSGN 0 AWAI S4C SMP0 SCAN ETORF $0080 $0081 ASCIF FRZ0 PRS0 CA CC0 ETRIGLE S2C PRS4 MULT FIFOR ETRIGP S1C PRS3 0 0 ETRIGE FIFO PRS2 CC CC2 ASCIE FRZ1 PRS1 CB CC1 $0082 $0083 $0084 $0085 $0086 $0087 $0088 Reads to this register return unpredictable values. Reads to this register return unpredictable values. Reads to these bits return unpredictable values. Reads to this register return unpredictable values. CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 SC $0089 $008A $008B $008C Reads to this register return unpredictable values. IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 $008D $008E Reads to this register return unpredictable values. = Unimplemented or Reserved Figure 98 ATD Register Map MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Register Name Reserved for Factory Test Reserved for Factory Test Bit 7 6 5 4 3 2 1 Bit 0 Address Offset Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Map Register Name PORTAD ATDDR0H ATDDR0L ATDDR1H ATDDR1L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 PTAD7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 6 PTAD6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 5 PTAD5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 4 PTAD4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 3 PTAD3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 2 PTAD2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 1 PTAD1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit 0 PTAD0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Address Offset $008F $0090 $0091 $0092 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F Freescale Semiconductor, Inc... ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L = Unimplemented or Reserved Figure 98 ATD Register Map (Continued) NOTE: NOTE: Register address: Base address (INITRG) + Address Offset Writing to Reserved Registers during special modes can alter functionality. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions The following subsections describe the bit-level arrangement and functionality of each register. ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Address Offset: $0082 Bit 15 14 AFFC 0 13 AWAI 0 12 ETRIGLE 0 11 ETRIGP 0 10 ETRIGE 0 9 ASCIE 0 Bit 8 ASCIF Read: Write: Reset: ADPU 0 0 READ: anytime WRITE: anytime (except for Bit 8 – ASCIF, READ: any time, WRITE: not allowed) ADPU — ATD Power Down This bit provides on/off control over the ATD module block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled. 1 = Normal ATD functionality 0 = Power down ATD AFFC — ATD Fast Flag Clear All 1 = Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. 0 = ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). AWAI — ATD Power Down in Wait Mode MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions When entering Wait Mode this bit provides on/off control over the ATD module block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode. 1 = Power down ATD during Wait mode 0 = ATD continues to run in Wait mode NOTE: ETRIGLE — External Trigger Level/Edge Control This bit controls the sensitivity of the external trigger signal. See Table 86 for details. ETRIGP — External Trigger Polarity This bit controls the polarity of the external trigger signal. See Table 86 for details. Table 86 External Trigger Configurations ETRIGLE 0 0 1 1 ETRIGP 0 1 0 1 External Trigger Sensitivity falling edge rising edge low level high level ETRIGE — External Trigger Mode Enable This bit enables the external trigger on ATD channel 7. The external trigger allows to synchronize sample and ATD conversions processes with external events. 1 = Enable external trigger 0 = Disable external trigger NOTE: The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled. ASCIE — ATD Sequence Complete Interrupt Enable MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Although a conversion that was interrupted prior to entering WAIT mode is restarted after WAIT mode wake-up, the results are not reliable and should not be used by the user application. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) 1 = ATD Interrupt will be requested whenever ASCIF=1 is set. 0 = ATD Sequence Complete interrupt requests are disabled. NOTE: There is an errata information about the ASCIF flag. See MC9S12 Errata Sheet for details. ASCIF — ATD Sequence Complete Interrupt Flag If ASCIE=1 the ASCIF flag equals the SCF flag (see register ATDSTAT0 - page 505), else ASCIF reads zero. Writes have no effect. 1 = ATD sequence complete interrupt pending 0 = No ATD interrupt occurred ATD Control Register 3 (ATDCTL3) Address Offset: $0083 Bit 7 This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. 6 S8C 0 5 S4C 1 4 S2C 0 3 S1C 0 2 FIFO 0 1 FRZ1 0 Bit 0 FRZ0 0 Read: Write: Reset: 0 0 Unimplemented or Reserved S8C/S4C/S2C/S1C — Conversion Sequence Length These bits control the number of conversions per sequence. Table 87 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 family. Table 87 Conversion Sequence Length Coding. S8C 0 0 0 0 0 S4C 0 0 0 0 1 S2C 0 0 1 1 0 S1C 0 1 0 1 0 Number of Conversions per Sequence 8 1 2 3 4 MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions Table 87 Conversion Sequence Length Coding. (Continued) S8C 0 0 0 1 S4C 1 1 1 X S2C 0 1 1 X S1C 1 0 1 X Number of Conversions per Sequence 5 6 7 8 FIFO — Result Register FIFO Mode If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion sequence; conversion results are placed in consecutive result registers between sequences. The result register counter wraps around when it reaches the end of the result register file. The conversion counter value in ATDSTAT0 can be used to determine where in the result register file, the current conversion result will be placed. Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 1 = Conversion results are placed in consecutive result registers (wrap around at end). 0 = Conversion results are placed in the corresponding result register up to the selected sequence length. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... FRZ1, FRZ0 — Background Debug Freeze Enable When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 88. Leakage onto the storage node and comparator MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. Table 88 ATD Behavior in Freeze Mode (Breakpoint) FRZ1 0 0 1 1 FRZ0 0 1 0 1 ATD RESPONSE Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... NOTE: The ATD module enters freeze mode when background debug mode (BDM) is active. Refer to the Fast Background Debug Module (FBDM) section about the background debug mode. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. Address Offset: $0084 Bit 7 6 SMP1 0 5 SMP0 0 4 PRS4 0 3 PRS3 0 2 PRS2 1 1 PRS1 0 Bit 0 PRS0 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Reset: SRES8 0 Freescale Semiconductor, Inc... Unimplemented or Reserved SRES8 — A/D Resolution Select 1 = 8-bit resolution selected. 0 = 10-bit resolution selected. This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. SMP0, SMP1 — Sample Time Select These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 89 lists the lengths available for the second sample phase. Table 89 Sample Time Select SMP1 0 0 1 1 SMP0 0 1 0 1 Length of Second Phase of Sample Time 2 A/D clock periods 4 A/D clock periods 8 A/D clock periods 16 A/D clock periods MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) PRS0, PRS1, PRS2, PRS3, PRS4 — ATD Clock Prescaler These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: [ BusClock ] ATDconversionclock = ------------------------------ × 0.5 [ PRS + 1 ] MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Note that the maximum ATD conversion clock frequency is half the Bus Clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is Bus Clock divided by 12. Table 90 illustrates the divide-by operation and the appropriate range of bus clock. Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions Table 90 Clock Prescaler Values Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Total Divisor Value divide by 2 divide by 4 divide by 6 divide by 8 divide by 10 divide by 12 divide by 14 divide by 16 divide by 18 divide by 20 divide by 22 divide by 24 divide by 26 divide by 28 divide by 30 divide by 32 divide by 34 divide by 36 divide by 38 divide by 40 divide by 42 divide by 44 divide by 46 divide by 48 divide by 50 divide by 52 divide by 54 divide by 56 divide by 58 divide by 60 divide by 62 divide by 64 Max Bus Clock(1) 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 36 MHz 40 MHz 44 MHz 48 MHz 52 MHz 56 MHz 60 MHz 64 MHz 68 MHz 72 MHz 76 MHz 80 MHz 84 MHz 88 MHz 92 MHz 96 MHz 100 MHz 104 MHz 108 MHz 112 MHz 116 MHz 120 MHz 124 MHz 128 MHz Min Bus Clock(2) 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz 1. Maximum ATD conversion clock frequency is 2MHz. The max. Bus clock frequency is computed from the max. ATD clock frequency times the indicated prescaler setting. 2. Minimum ATD clock frequency is 500KHz. The min. Bus clock frequency is computed from the min. ATD clock frequency times the indicated prescaler settling. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. Address Offset: $0085 Bit 7 6 DSGN 0 5 SCAN 0 4 MULT 0 3 0 2 CC 0 1 CB 0 Bit 0 CA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Read: Write: Reset: DJM 0 Freescale Semiconductor, Inc... 0 0 Unimplemented or Reserved Read: anytime Write: anytime DJM — Result Register Data Justification Mode 1 = Right justified mode. 0 = Left justified mode. This bit controls justification of conversion data in the result registers. See ATDDRx A/D Conversion Result Registers (ATDDR0–7) in page 510 for details. DSGN — Signed/Unsigned Result Data Mode 1 = Signed result register data select. 0 = Unsigned result register data select. This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2’s complement. See ATDDRx A/D Conversion Result Registers (ATDDR0–7) in page 510 for details. Table 91 summarizes the result data formats available and how they are set up using the control bits. Table 92 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions Table 91 Result Data Formats Available. SRES8 1 1 1 0 0 0 DJM 0 0 1 0 0 1 DSGN 0 1 X 0 1 X Result Data Formats Description and Bus Bit Mapping 8-bit/left justified/unsigned - bits 8-15 8-bit/ left justified/signed - bits 8-15 8-bit/right justified/unsigned - bits 0-7 10-bit/left justified/unsigned - bits 6-15 10-bit/left justified/signed - bits 6-15 10-bit/right justified/unsigned - bits 0-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Table 92 Left Justified, Signed and Unsigned ATD Output Codes. Input Signal Vrl = 0 Volts Vrh = 5.12 Volts 5.120 Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Signed 8-Bit Codes 7F 7F 7E 01 00 FF 81 80 Unsigned 8-Bit Codes FF FF FE 81 80 7F 01 00 Signed 10-Bit Codes 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 Unsigned 10-Bit Codes FFC0 FF00 FE00 8100 8000 7F00 0100 0000 SCAN — Continuous Conversion Sequence Mode 1 = Perform conversion sequences continuously. 0 = Perform a conversion sequence and return to idle mode. The scan mode bit controls whether or not conversion sequences are performed continuously or only once. MULT — Multi-Channel Sample Mode 1 = Sample across many channels. 0 = Sample only the specified channel. When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code. CC, CB, CA — Analog Input Channel Select Code Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 93 lists the coding used to select the various analog input channels. In the case of single channel scans (MULT=0), this selection code specifies the channel to be examined. In the case of multi-channel scans (MULT=1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing channel selection code; selection codes that reach the maximum value wrap around to the minimum value. Table 93 Analog Input Channel Select Coding CC 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions A/D Status Register (ATDSTAT0) This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Address Offset: $0086 Bit 7 6 0 5 ETORF 0 4 FIFOR 0 3 0 2 CC2 1 CC1 Bit 0 CC0 Read: Write: Reset: SCF 0 0 0 0 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Read: Anytime Write: Refer to each bit for individual write conditions NOTE: NOTE: There is an errata information about the flags SCF, ETORF and FIFOR. See MC9S12T64 Errata Sheet for details. There is an errata information about the SCF flag. See MC9S12T64 Errata Sheet for details. SCF — Sequence Complete Flag This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared when one of the following occurs: A) Write “1” to SCF B) Write to ATDCTL5 (a new conversion sequence is started) C) If AFFC=1 and read of a result register 1 = Conversion sequence has completed 0 = Conversion sequence not completed ETORF — External Trigger Overrun Flag While in edge trigger mode (ETRIGLE=0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the following occurs: A) Write “1” to ETORF B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) 1 = External trigger overrun error has occurred 0 = No External trigger overrun error has occurred FIFOR — FIFO Over Run Flag. This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e. the old data has been lost). This flag is cleared when one of the following occurs: A) Write “1” to FIFOR B) Write to ATDCTL5 (a new conversion sequence is started) 1 = An over run condition exists 0 = No over run has occurred CC2/CC1/CC0 — Conversion Counter These 3 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO=0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. ATD Test Register 1 (ATDTEST1) Address Offset: $0089 Bit 7 This register contains the SC bit used to enable special channel conversions. 6 5 4 3 2 1 Bit 0 SC Read: Write: Reset: 0 0 Reads to these bits return unpredictable values. 0 0 0 0 0 0 Unimplemented or Reserved MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions Read: anytime Write: anytime SC - Special Channel Conversion Bit If this bit is set, then special channel conversion can be selected using CC, CB, and CA of ATDCTL5 register. Table 94 lists the coding. 1 = Special channel conversions enabled 0 = Special channel conversions disabled Freescale Semiconductor, Inc... CAUTION: Always write remaining bits of ATDTEST1 (Bits 7 to 1) zero when writing the SC bit. Not doing so might result in unpredictable ATD behavior. Table 94 Special Channel Select Coding SC 1 1 1 1 1 CC 0 1 1 1 1 CB X 0 0 1 1 CA X 0 1 0 1 Analog Input Channel Reserved VRH VRL (VRL+VRH)/2 Reserved A/D Status Register (ATDSTAT1) Address Offset: $008B Bit 7 This read-only register contains the Conversion Complete Flags. 6 CCF6 5 CCF5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 Bit 0 CCF0 Read: Write: Reset: CCF7 0 0 0 0 0 0 0 0 Unimplemented or Reserved Read: anytime Write: only in special modes NOTE: There is an errata information about the CCF flags. See MC9S12T64 Errata Sheet for details. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) CCFx — Conversion Complete Flag x (x=7,6,5,4,3,2,1,0) A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A flag CCFx (x=7,6,5,4,3,2,1,0) is cleared when one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC=0 and read of ATDSTAT1 followed by read of result register ATDDRx C) If AFFC=1 and read of result register ATDDRx 1 = Conversion number x has completed, result ready in ATDDRx 0 = Conversion number x not completed ATD Input Enable Mask Register (ATDDIEN) Address Offset: $008D Bit 7 6 IEN 6 0 5 IEN 5 0 4 IEN 4 0 3 IEN 3 0 2 IEN 2 0 1 IEN 1 0 Bit 0 IEN 0 0 Read: Write: Reset: IEN 7 0 Read: anytime Write: anytime IENx— ATD Digital Input Enable on channel x (x=7,6,5,4,3,2,1,0) This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 1 = Enable digital input buffer to PTADx. 0 = Disable digital input buffer to PTADx NOTE: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Register Descriptions Port Data Register (PORTAD) Address Offset: $008F Bit 7 The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0. 6 PTAD6 5 PTAD5 4 PTAD4 3 PTAD3 2 PTAD2 1 PTAD1 Bit 0 PTAD0 Read: Write: Pin Function PTAD 7 AN7 AN6 1 AN5 1 AN4 1 AN3 1 AN2 1 AN1 1 AN0 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Reset: 1 Unimplemented or Reserved Freescale Semiconductor, Inc... Read: anytime. If the digital input buffers are disabled (IENx=0), read returns a 1. Write: anytime, no effect The A/D input channels may be used for general purpose digital input. PTADx — A/D Channel x (ANx) Digital Input (x= 7,6,5,4,3,2,1,0) If the digital input buffer on the ANx pin is enabled (IENx=1) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx=0), read returns a “1”. Reset sets all PORTAD bits to “1”. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) ATDDRx A/D Conversion Result Registers (ATDDR0–7) Where: x = 0, 1, 2, 3, 4, 5, 6, 7 Left Justified Result Data Address Offset: $0090, $0092, $0094, $0096, $0098, $009A, $009C, $009E ATDDRxH 10-bit data Read: Write: Read: Write: Reset Bit 15 Bit 9 MSB 14 8 13 7 12 6 11 5 10 4 9 3 Bit 8 Bit 2 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 8-bit data Bit 7 MSB 6 5 4 3 2 1 Bit 0 U U U U U U U U Address Offset: $0091, $0093, $0095, $0097, $0099, $009B, $009D, $009F ATDDRxL 10-bit data Read: Write: Read: Write: Reset Bit 7 Bit 1 6 Bit 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 8-bit data U U 0 0 0 0 0 0 U U U U U U U U Right Justified Result Data Address Offset: $0090, $0092, $0094, $0096, $0098, $009A, $009C, $009E ATDDRxH 10-bit data Read: Write: Read: Write: Reset Bit 15 0 14 0 13 0 12 0 11 0 10 0 9 Bit 9 MSB Bit 8 Bit 8 8-bit data 0 0 0 0 0 0 0 0 At reset the data format is left justified! Address Offset: $0091, $0093, $0095, $0097, $0099, $009B, $009D, $009F ATDDRxL 10-bit data Read: Write: Read: Write: Reset Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 8-bit data Bit 7 MSB 6 5 4 3 2 1 Bit 0 At reset the data format is left justified! Unimplemented or Reserved MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Functional Description Read: Anytime Write: Anytime, no effect. The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the result registers based on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. For 8-bit result data, the result data maps between the high (left justified) and low (right justified) order bytes of the result register. For 10-bit result data, the result data maps between bits 6–15 (left justified) and bits 0–9 (right justified) of the result register. Therefore for each bit in the SAR, there are 3 possible mappings of this bit into the result registers. Functional Description General The ATD module is structured in an analog and a digital sub-block. Analog Sub-block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. The Sample and Hold (S/H) Machine accepts analog signals from the external surroundings and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node. The second stage connects the input directly to the storage node to complete the sample for high accuracy. Sample and Hold Machine MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA. Analog Input Multiplexer Sample Buffer Amplifier Analog-to-Digital (A/D) Machine The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine. The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output codes. Digital Sub-block This subsection explains some of the digital features in more detail. See register descriptions for all details. The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The input signal (ATD channel 7) is programmable to be edge or level sensitive with polarity control. External Trigger Input (ETRIG) MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Functional Description Table 95 gives a brief description of the different combinations of control bits and their affect on the external trigger function. Table 95 External Trigger Control Bits ETRIGLE X ETRIGP X ETRIGE 0 SCAN 0 Description Ignores external trigger. Performs one conversion sequence and stops. Ignores external trigger. Performs continuous conversion sequences. Falling edge triggered. Performs one conversion sequence per trigger. Rising edge triggered. Performs one conversion sequence per trigger. Trigger active low. Performs continuous conversions while trigger is active. Trigger active high. Performs continuous conversions while trigger is active. 0 0 1 X 0 1 1 X 1 0 1 X 1 1 1 X During a conversion, if additional active edges are detected the overrun error flag ETORF is set. In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one Bus Clock cycle plus any skew or delay introduced by the trigger circuitry. NOTE: The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled. Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left asserted in MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family X X 0 1 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) level mode while a sequence is completing, another sequence will be triggered immediately. General Purpose Digital Input Port Operation The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port register PORTAD (input-only). Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog inputs of the ATD module. The input pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input. Low Power Modes The ATD module can be configured for lower MCU power consumption in 3 different ways: • • • Stop Mode Wait Mode with AWAI=1 Power down by writing ADPU=0 (Note that all ATD registers remain accessible.) Note that the reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state. Once the ATD module is configured for low power, it aborts any conversion sequence in progress. When ATD module powers up again (exit Stop Mode, exit Wait Mode with AWAI=1 or set ADPU=1), it requires a recovery time period. MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) Reset Initialization Reset Initialization The reset state of each individual bit is listed within the Register Description section (see Register Descriptions) which details the registers and their bit-fields. Interrupts The interrupt requested by the ATD module is listed in Table 96. Table 96 ATD module Interrupt Vectors Interrupt Source Sequence Complete Interrupt Vector Address $FFD2,$FFD3 CCR Mask I bit Local Enable ASCIE in ATDCTL2 MC9S12T64Revision 1.1.1 Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... Analog to Digital Converter (ATD) MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. Analog to Digital Converter (ATD) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 Overview The Fast Background Debug Mode (FBDM) module is a selectable single-wire or multi-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. This module is a super set of the BDM module and has added capability for selection of an SPI type interface in addition to the single-wire interface. This allows the interface to operate at a higher speed, through the use of three pins. Features • • Single-wire communication with host development system Active out of reset in special single-chip mode MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) • • • • • Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 15 firmware commands execute from on the standard BDM firmware lookup table Instruction tagging capability Software control of BDM operation during wait mode Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... • • • • • Software selectable clocks BDM disabled when secure feature is enabled. Selectable SPI type interface (matches Motorola standard SPI phase =1, polarity =1) In SPI mode, word reads are accelerated by sending next address while receiving data In SPI mode, the interface will always force a steal in order to make BDM instructions faster MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Modes of Operation Modes of Operation BDM is available in all operating modes but must be enabled before firmware commands are executed. Some on-chip peripherals have a control bit which allows suspending the peripheral function during background debug mode. In special single-chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. BDM is also active out of special peripheral mode reset and can be turned off by clearing the BDMACT bit in the BDM status (BDMSTS) register. This allows testing of the BDM memory space as well as the user’s memory space. NOTE: The BDM serial system should not be used in special peripheral mode since the CPU, which in other modes interfaces with the BDM to relinquish control of the bus during a free cycle or a steal operation, is not operating in this mode. Normal Operation BDM operates the same in all normal modes. Special Operation Special single-chip mode Special peripheral mode BDM is enabled and active immediately out of reset. This allows programming a system with blank memory. BDM is enabled and active immediately out of reset. BDM can be disabled by clearing the BDMACT bit in the BDM status (BDMSTS) register. The BDM serial system should not be used in special peripheral mode. Emulation Modes In emulation modes, the BDM operates as in all normal modes. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Block Diagram The block diagrams of the BDM are shown in Figure 99 and Figure 100 below. HOST SYSTEM MCU BDM MODULE BKGD Drive Control Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family BKGD BKGD Data Output 16-BIT SHIFT REGISTER BKGD Input SCKBDM / SPIMODE ENTAG BDMACT TRACE ADDRESS INSTRUCTION DECODE and EXECUTION BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS Freescale Semiconductor, Inc... SDV ENBDM STANDARD BDM FIRMWARE LOOKUP TABLE CLKSW Figure 99 Block Diagram of BDM in Single Wire Mode HOST SYSTEM MCU BDM MODULE BKGD_DOUT 16-BIT SHIFT REGISTER BKGD_IND SCKBDM SCK SPIMODE ADDRESS INSTRUCTION DECODE and EXECUTION BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS ENTAG BDMACT TRACE SDV ENBDM STANDARD BDM FIRMWARE LOOKUP TABLE CLKSW Figure 100 Block Diagram of BDM in SPI Mode MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) External Pin Descriptions External Pin Descriptions From a core standpoint there are five pins making up the FBDM interface. At the chip level these pins will likely be combined with other pins. • • BKGD / SI— Background interface pin, which becomes the SI (Serial data into the BDM) in SPI mode Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family TAGHI — High byte instruction tagging pin TAGLO — Low byte instruction tagging pin SCKBDM / SPIMODE — Selects SPI interface or single wire interface at rising edge the RESET pin, if SPI mode is select, then this pin becomes the serial clock input SO — Serial data out of the BDM for SPI mode Freescale Semiconductor, Inc... • • • Background Interface Pin (BKGD) Debugging control logic communicates with external devices serially via the single-wire background interface pin (BKGD). During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. The serial data from the host system to the FBDM uses this pin in SPI mode. High Byte Instruction Tagging Pin (TAGHI) This pin is used to tag the high byte of an instruction. When instruction tagging is on, a logic 0 at the falling edge of the external clock (ECLK) tags the high half of the instruction word being read into the instruction queue. Low Byte Instruction Tagging Pin (TAGLO) This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word being read into the instruction queue. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) FBDM Clock in SPI Mode (SCKBDM) and SPI Mode Select (SPIMODE) While the part is in reset, this pin selects whether the FBDM will operate as a single-wire interface (SPIMODE = 0) or multi-wire SPI type interface (SPIMODE = 1). When reset is released this mode is locked in and cannot be changed until the next reset. When the part is out of reset, if SPI mode has been selected, then this pin is the serial clock input (SCKBDM pin, SCK inside the module). The clock indicates when data should be shifted and sampled. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Serial Data Out of FBDM In SPI Mode (SO) The serial data from the FBDM to the host system uses this output pin in SPI mode. If single wire mode is selected during reset, this pin will hold a driven low state. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Register Map Register Map A summary of the registers associated with the BDM is shown in Figure 101 below. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow. Address $FF00 Register Name BDM reserved Read: Write: Bit 7 X 6 X 5 X 4 X 3 X 2 X 1 0 Bit 0 0 $FF01 BDMSTS Read: ENBDM BDMACT ENTAG Write: Read: Write: Read: Write: Read: Write: Read: Write: X X X SDV X TRACE CLKSW X X UNSEC 0 $FF02 BDM reserved X X $FF03 BDM reserved X X X X X X X X $FF04 BDM reserved X X X X X X X X $FF05 BDM reserved X X X X X X X X $FF06 BDMCCR Read: CCR7 Write: Read: Write: 0 CCR6 REG14 CCR5 REG13 CCR4 REG12 CCR3 REG11 CCR2 0 CCR1 0 CCR0 0 $FF07 BDMINR = Unimplemented X = Indeterminate Figure 101 BDM Register Map Summary MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Register Descriptions BDM Status Register (BDMSTS) Address: $FF01 Bit 7 Read: 6 5 ENTAG 4 SDV 3 TRACE 2 CLKSW 1 UNSEC Bit 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Write: Reset: Special single-chip mode: Special peripheral mode: All other modes: ENBDM BDMACT 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Read: All modes through BDM operation Write: All modes but subject to the following: – BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode. – CLKSW can only be written via BDM hardware or standard BDM firmware write commands. – All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution. – ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in Special Single Chip Mode). ENBDM — Enable BDM This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still allowed. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Register Descriptions 1 = BDM enabled 0 = BDM disabled NOTE: ENBDM is set by the firmware immediately out of reset in special single-chip mode. In secured mode this bit will not be set by the firmware until after the FLASH erase verify test is complete. BDMACT — BDM active status This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. 1 = BDM active 0 = BDM not active ENTAG — Tagging enable This bit indicates whether instruction tagging in enabled or disabled. It is set when the TAGGO command is executed and cleared when BDM is entered. The serial system is disabled and the tag function enabled 16 cycles after this bit is written. BDM cannot process serial commands while tagging is active. 1 = Tagging enabled 0 = Tagging not enabled, or BDM active SDV — Shift data valid This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a firmware read command or after data has been received as part of a firmware write command. It is cleared when the next BDM command has been received or background debug mode is exited. SDV is used by the standard BDM firmware to control program flow execution. 1 = Data phase of command is complete 0 = Data phase of command not complete MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) TRACE — TRACE1 BDM firmware command is being executed This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set as long as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized. 1 = TRACE1 command is being executed 0 = TRACE1 command is not being executed CLKSW — Clock switch Freescale Semiconductor, Inc... The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A WRITE_BD_BYTE command to address $FF01 changes the CLKSW bit. The 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active. The start of the next BDM command uses the new clock for timing subsequent BDM communications. This clock is referred as target clock in this document. 1 = BDM system operates with bus clock rate 0 = BDM system operates with oscillator clock divided by 2 when the PLLSEL bit is set, otherwise BDM system operates with bus clock rate. Table 97 Target Clock Selection Summary CLKSW 0 0 1 PLLSEL 0 1 — Target Clock Bus Clock Oscillator Clock / 2 Bus Clock UNSEC — Unsecure This bit is writable only in special single chip mode from the BDM secure firmware and always resets to 0. This bit is clear as secured mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map along with the standard BDM firmware lookup table. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Register Descriptions The secure BDM firmware lookup table verifies that the FLASH is erased. This being the case, UNSEC signal is set. The BDM program jumps to start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted. 1 = the part is in the unsecured mode 0 = the part is in the secured mode WARNING: BDM CCR Holding Register (BDMCCR) Address: $FF06 Bit 7 Read: Write: Reset: CCR7 0 6 CCR6 0 5 CCR5 0 4 CCR4 0 3 CCR3 0 2 CCR2 0 1 CCR1 0 Bit 0 CCR0 0 Read: All modes Write: All modes NOTE: When BDM is made active, the CPU stores the value of the CCR register in the BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to $D8 and not $D0 which is the reset value of the CCR register. CCR7–CCR0 — BDM CCR Holding Bits When entering background debug mode, the BDM CCR holding register is used to save the contents of the condition code register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written to modify the CCR value. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the system will be secured again when it is next taken out of reset. Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) BDM Internal Register Position Register (BDMINR) Address: $FF07 Bit 7 Read: Write: Reset: 0 0 6 REG14 0 5 REG13 0 4 REG12 0 3 REG11 0 2 0 0 1 0 0 Bit 0 0 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... = Unimplemented Read: All modes Write: Never REG14–REG11 — Internal register map position These four bits show the state of the upper bits of the base address for the system’s relocatable register block. BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the first 32K bytes of the 64K byte address space. If the register block size is 1K bytes, it will always occupy the first 1K bytes of the specified 2K byte space. Functional Description The BDM module receives and executes commands from a host via a single wire serial interface or via the BDM SPI interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode (see BDM Hardware Commands). Target system memory includes all memory that is accessible by the CPU. Firmware commands are used to read and write CPU resources and to exit from active background debug mode (see Standard BDM Firmware Commands). The CPU resources referred to are the accumulator (D), X MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description index register (X), Y index register (Y), stack pointer (SP), and program counter (PC). Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted in Modes of Operation below. Firmware commands can only be executed when the system is in active background debug mode (BDM). SPI Mode While in SPI mode, the delay time between an address and read data is shortened to always steal the next available cycle. On parts operating in single chip mode, this will be 8 target clock cycles (detailed explanation in Hardware Delay in SPI Mode). It will take 21 target clock cycles for parts with memory and / or peripherals on an external bus (to allow for misaligned, narrow bus and stretched accesses on the cycle before the steal and to allow for narrow bus and stretched accesses on the steal cycle). Also while in SPI mode, there is one hardware command with added functionality. The read word instruction will take in a new address while the data is being output. Then another address can be sent in while the data from the previous address is sent out (full duplex operation). When the user has completed the operation, an $FFFF needs to be sent in as the address. This will quit the read word instruction and the next input will be a new command. Note that this is the only instruction with this operation enhancement. Selecting SPI Mode The core has an input (SCKBDM / SPIMODE) which selects whether the BDM will use a single wire interface or the SPI type interface. This selection occurs at the release of reset and cannot be changed until the next reset. SPIMODE = 1 during reset for selecting the SPI type interface and SPIMODE = 0 during reset for selecting the single wire interface. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... An SPI mode option has been added to this module. When SPI mode is selected, the single wire interface becomes three wires: serial slave data in (SI), serial slave data out (SO) and serial slave clock in (SCK). As in the single wire mode, the external system still initiates and controls all transfers. The dedicated pins allow faster transfer rates, up to one quarter the bus frequency per bit. Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Secured Mode If the user resets into special single chip mode with the part secured, a secure BDM firmware lookup table is brought into the map along with the standard BDM firmware lookup table. The secure BDM firmware is higher priority than the standard BDM firmware. The secure BDM firmware verifies that the FLASH is erased. This being the case, the UNSEC bit is asserted (written to one). The BDM program jumps to start of the standard BDM firmware and the secure BDM firmware is turned off. If the FLASH do not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the software commands. This allows the BDM hardware commands to be used to erase the FLASH. Enabling and Activating BDM The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface or via the BDM SPI interface, using a hardware command such as WRITE_BD_BYTE. After being enabled, BDM is activated by one of the following1: • • • • Hardware BACKGROUND command BDM external instruction tagging mechanism CPU BGND instruction Breakpoint sub-block’s force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by the breakpoint sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. 1. BDM is enabled and active immediately out of special single-chip reset (see Special Operation). 2. This method is only available on systems that have a a Breakpoint sub-block. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description NOTE: If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses $FF00 to $FFFF. BDM registers are mapped to addresses $FF00 to $FF07. The BDM module uses these registers which are readable anytime by the BDM module, not user programs. NOTE: When the background debug mode is activated, the PWM, ECT and ATD modules enter freeze mode and control bits determine if the module is stopped during active BDM. See each module section about freeze mode. BDM Hardware Commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, EEPROM, Flash EEPROM, I/O and control registers, and all external memory. Hardware commands are executed with minimal or no CPU intervention and do not require the MCU to be in active BDM for execution, although, they can still be executed in this mode. When executing a hardware command in single wire mode, the BDM sub-block waits for a free CPU bus cycle so that the background access does not disturb the running application programs. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM module can steal a cycle. When the BDM module finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles, CPU clocks are frozen until the operation is complete, even though the BDM module found a free cycle. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) The BDM hardware commands are listed in Table 98. Table 98 Hardware Commands Command BACKGROUND READ_BD_BYTE Opcode (hex) 90 E4 Data None Description Enter background debug mode if firmware is enabled. Read from memory with standard BDM firmware lookup table 16-bit address in map. Odd address data on low byte; even address data on 16-bit data out high byte Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... READ_BD_WORD EC 16-bit address Read from memory with standard BDM firmware lookup table 16-bit data out in map. Must be aligned access. Read from memory with standard BDM firmware lookup table 16-bit address out of map. Odd address data on low byte; even address data 16-bit data out on high byte 16-bit address Read from memory with standard BDM firmware lookup table 16-bit data out out of map. Must be aligned access. Read from memory with standard BDM firmware lookup table 16-bit address out of map. Must be aligned access. SPI interface only: next 16-bit data out address must be sent in with data out, use address = $FFFF / next address to end read word operation. Write to memory with standard BDM firmware lookup table in 16-bit address map. Odd address data on low byte; even address data on 16-bit data in high byte 16-bit address Write to memory with standard BDM firmware lookup table in 16-bit data in map. Must be aligned access Write to memory with standard BDM firmware lookup table out 16-bit address of map. Odd address data on low byte; even address data on 16-bit data in high byte 16-bit address Write to memory with standard BDM firmware lookup table out 16-bit data in of map. Must be aligned access. READ_BYTE READ_WORD (single wire mode) READ_WORD (SPI mode) E0 E8 E8 WRITE_BD_BYTE C4 WRITE_BD_WORD CC WRITE_BYTE C0 WRITE_WORD C8 The READ_BD and WRITE_BD commands are used for reading the on standard BDM firmware lookup table locations and for reading and writing to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM system to access MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description BDM locations unobtrusively, even if the addresses conflict with the application memory map. Standard BDM Firmware Commands As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at $FF00-$FFFF, and the CPU begins executing the standard BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 99. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Firmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard BDM firmware commands (see Enabling and Activating BDM). Normal instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Table 99 Firmware Commands Command READ_NEXT READ_PC READ_D READ_X READ_Y Opcode (hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 10 18 Data 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in none none none Description Increment X by 2 (X = X + 2), then read word X points to. Read program counter. Read D accumulator. Read X index register. Read Y index register. Read stack pointer. Increment X by 2 (X=X+2), then write word to location pointed to by X. Write program counter. Write D accumulator. Write X index register. Write Y index register. Write stack pointer. Go to user program. Execute one user instruction then return to active BDM. Enable tagging and go to user program. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO TRACE1 TAGGO MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family NOTE: NOTE: Freescale Semiconductor, Inc... 16-bit misaligned reads and writes are not allowed. If attempted, the BDM module will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait 150 target clock cycles1 after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 target clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 target clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For hardware data read commands, the external host must wait the hardware delay after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait the hardware delay after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. Refer to Hardware Delay in SPI Mode in page 539. Hardware Commands in Single Wire Mode Hardware Commands in SPI Mode 1. Target clock cycles are cycles measured using the target system’s serial clock rate. See BDM Serial Interface and BDM Status Register (BDMSTS) for information on how serial clock rate is selected. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Firmware commands For firmware read commands, the external host must wait 32 target clock cycles after sending the command opcode before attempting to obtain the read data. If the access is external with a narrow bus access (+1 cycle) and / or a stretch (+1, 2 or 3 cycles), up to an additional 7 cycles could be needed if both occur (39 target clock cycles total). This allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. For firmware write commands, the external host must wait 32 target clock cycles after sending the data to be written, before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait 64 target clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. Figure 102 represents the BDM command structure in single wire mode. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The minimum time for an 8-bit command is 8 × 16 target clock cycles. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description 8 BITS AT ~16 TC/BIT HARDWARE READ COMMAND 16 BITS AT ~16 TC/BIT ADDRESS 150-TC DELAY 16 BITS AT ~16 TC/BIT DATA 150-TC DELAY NEXT COMMAND HARDWARE WRITE COMMAND 32-TC ** DELAY ADDRESS DATA NEXT COMMAND FIRMWARE READ COMMAND DATA 32-TC DELAY NEXT COMMAND Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... FIRMWARE WRITE COMMAND 64-TC DELAY DATA NEXT COMMAND GO, TRACE COMMAND NEXT COMMAND TC = TARGET CLOCK CYCLES ** allow 39 target clocks if read is external with stretch and / or narrow bus Figure 102 BDM Command Structure - Single Wire Mode Figure 103 represents the BDM command structure in SPI mode. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the SI and SO lines idle in the high state. The minimum time for an 8-bit command is 8 × 4 target clock cycles. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) 8 BITS SERIAL HARDWARE IN (SI) READ_WORD EXAMPLE 1 SERIAL OUT (SO) SERIAL HARDWARE IN (SI) READ_WORD EXAMPLE 2 SERIAL OUT (SO) COMMAND 16 BITS ADDRESS 1 HARDWARE DELAY 16 BITS ADDRESS 2 HARDWARE DELAY 16 BITS ADDRESS 3 DATA 1 DATA 2 COMMAND ADDRESS $FFFF NEXT COMMAND DATA NEXT COMMAND DATA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SERIAL HARDWARE IN (SI) READ (ALL OTHERS) SERIAL OUT (SO) COMMAND ADDRESS HARDWARE DELAY SERIAL HARDWARE IN (SI) WRITE SERIAL OUT (SO) COMMAND ADDRESS DATA NEXT COMMAND 32-TC ** DELAY SERIAL IN (SI) SERIAL OUT (SO) COMMAND NEXT COMMAND DATA FIRMWARE READ 32-TC DELAY FIRMWARE WRITE SERIAL IN (SI) SERIAL OUT (SO) 64-TC DELAY GO, TRACE, TAGGO SERIAL IN (SI) SERIAL OUT (SO) COMMAND NEXT COMMAND COMMAND DATA NEXT COMMAND TC = TARGET CLOCK CYCLES HARDWARE DELAY = 8-TC if no stretch and no narrow bus. = 21-TC stretch and or narrow bus can occur ** allow 39 target clocks if read is external with stretch and / or narrow bus Figure 103 BDM Command Structure - SPI Mode MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description Hardware Delay in SPI Mode A hardware delay is required between serial transfers when the BDM needs to access the bus to complete an operation. For example, on a hardware read a hardware delay is required after the address is sent so that the data can be accessed before it is returned. On a hardware write, a hardware delay is required after the write data is sent so that the write occurs before the next command is sent. In SPI mode, the hardware delay allows the BDM to synchronize to the incoming serial data, load up the appropriate registers for the bus access, synchronize with the CPU to steal the bus, complete the bus access and for a read, put the read data into the shifter to return it. The hardware delay takes into account the part of the operation that occurs between the rising edges of the serial clock. At the fastest transfer rate this is a total of eight target clocks. At the fastest rate, the user must wait eight target clocks which is the hardware delay. If SCKBDM was running slower, at 12 target clocks per bit, the hardware delay reduces to zero for single chip mode and to 13 for expanded mode (worst case). This can be determined with the equations: • • • For internal-only accesses Hardware Delay = 12TC – (SCKBDM PERIOD) For external accesses allowing for stretch and wide bus Hardware Delay = 21TC – (SCKBDM PERIOD) For external accesses allowing for stretch and narrow bus Hardware Delay = 25TC – (SCKBDM PERIOD) Where: If the hardware delay goes negative, it is zero. For example, if the SPI is running at 8 target clocks per bit, we get a 4 TC delay for internal accesses, a 13 TC delay for external accesses with a wide bus and stretch, and a 17 TC delay for external accesses with a narrow bus and stretch. BDM Serial Interface The BDM module communicates with external devices serially via the MCU mode control BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) After reset, this pin becomes the dedicated serial interface pin for the BDM module. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register (see BDM Status Register (BDMSTS)). This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pullup and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. Diagrams in Figure 104, Figure 105, and Figure 106 show timing of bit-time cases in single wire mode. Each case begins when the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the target MCU up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 104 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. CLOCK TARGET SYSTEM Freescale Semiconductor, Inc... HOST TRANSMIT 1 HOST TRANSMIT 0 PERCEIVED START OF BIT TIME SYNCHRONIZATION UNCERTAINTY TARGET SENSES BIT 10 CYCLES EARLIEST START OF NEXT BIT Figure 104 BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 105 shows the host receiving a logic 1 from the target MCU. Since the host is asynchronous to the target MCU, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target MCU drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) CLOCK TARGET SYSTEM HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE PERCEIVED START OF BIT TIME R-C RISE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 105 BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 106 shows the host receiving a logic 0 from the target MCU. Since the host is asynchronous to the target MCU, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target MCU finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... BKGD PIN Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description CLOCK TARGET SYS. HOST DRIVE TO BKGD PIN TARGET SYS. DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME HIGH-IMPEDANCE SPEEDUP PULSE 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 106 BDM Target-to-Host Serial Bit Timing (Logic 0) BDM Serial Interface in SPI mode An eight bit transfer in SPI mode is shown in the diagram (see Figure 107). The data is shifted (changes) on the falling edges of SCK and it is sampled (registered) on the rising edges of SCK. The SCK clock is always driven into the BDM and initiates a transfer. It’s idle state is one. Commands, addresses and write data are driven into the BDM on SI and read data is driven out of the BDM on SO. SCK SI SO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB DATA IS SHIFTED AT SCK FALLING EDGES AND SAMPLED AT SCK RISING EDGES Figure 107 8-Bit Data Transfer in SPI Mode Timing specifications for the SPI mode interface are described in the table (see Table 100). SCK must be no faster than 4 target clocks. When MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family BKGD PIN Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) running at the fastest rate, it is important that SCK be a 50% duty cycle because both edges of SCK are used (sampling and shifting). Table 100 SPI Mode Timing Characteristic SCK period SCK high time Minimum 4 target clocks 2 target clocks 2 target clocks 0.5 target clocks 2 target clocks 0.5 target clocks 2 target clocks Maximum 500 target clocks 250 target clocks 250 target clocks Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... SCK low time SI data valid before rising edge of SCK SI data hold after rising edge of SCK SO data valid before rising edge of SCK SO data hold after rising edge of SCK Instruction Tracing When a TRACE1 command is issued to the BDM module in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM module is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. Instruction Tagging The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a specific instruction, because execution already has begun by the time an operation is visible outside the system. A separate instruction tagging mechanism is provided for this purpose. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Functional Description The tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue, the CPU enters active BDM rather than executing the instruction. NOTE: Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active. Executing the BDM TAGGO command configures two MCU pins for tagging. On MCUs with an [Muxed] External Bus Interface (MEBI or EBI), the TAGLO signal shares a pin with the LSTRB signal, and the TAGHI signal shares a pin with the BKGD signal. On MCUs with a Development Tools Interface (DTI), TAGLO will generally be bonded out separately. WARNING: If tagging is used in SPI mode, the BKGD pin needs to be brought to a high level soon after the taggo command is sent. Since the BKGD pin is used for TAGHI, it must be high within 15 target cycles, or the next instruction may get tagged. Table 101 shows the functions of the two tagging pins. The pins operate independently, that is, the state of one pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall of the external clock (ECLK) performs the indicated function. High tagging is allowed in all modes. On MCUs with a [Muxed] External Bus Interface (MEBI or EBI), low tagging is allowed only when low strobe is enabled (LSTRB is allowed only in wide expanded modes and emulation expanded narrow mode). On MCUs with a Development Tools Interface (DTI), low tagging is allowed in all modes. Table 101 Tag Pin Function TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Fast Background Debug Module (FBDM) Low-Power Options Run Mode The BDM does not include disable controls that would conserve power during run mode. Wait Mode The BDM cannot be used in wait mode if the system disables the clocks to the BDM. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Stop Mode The BDM is completely shutdown in stop mode. Interrupts The BDM does not generate interrupt requests. MC9S12T64Revision 1.1.1 Fast Background Debug Module (FBDM) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Breakpoint Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Overview The Breakpoint sub-block of the Core provides for hardware breakpoints that are used to debug software on the CPU by comparing actual address and data values to predetermined data in setup registers. A successful comparison will place the CPU in Background Debug Mode or initiate a software interrupt (SWI). The Breakpoint Module contains two modes of operation: 1. Dual Address Mode, where a match on either of two addresses will cause the system to enter Background Debug Mode or initiate a Software Interrupt (SWI). 2. Full Breakpoint Mode, where a match on address and data will cause the system to enter Background Debug Mode or initiate a Software Interrupt (SWI). There are two types of breakpoints, forced and tagged. Forced breakpoints occur at the next instruction boundary if a match occurs and MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) tagged breakpoints allow for breaking just before a specific instruction executes. Tagged breakpoints will only occur on addresses. Tagging on data is not allowed; however, if this occurs, nothing will happen within the BKP. The BKP allows breaking within a 256 byte address range and/or within expanded memory. It allows matching of the data as well as address matching and to match 8 bit or 16 bit data. Forced breakpoints can match on a read or a write cycle. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Features • Full or Dual Breakpoint Mode – Compare on address and data (Full) – Compare on either of two addresses (Dual) • BDM or SWI Breakpoint – Enter BDM on breakpoint (BDM) – Execute SWI on breakpoint (SWI) • Tagged or Forced Breakpoint – Break just before a specific instruction will begin execution (TAG) – Break on the first instruction boundary after a match occurs (Force) • Single, Range, or Page address compares – Compare on address (Single) – Compare on address 256 byte (Range) – Compare on any 16K Page (Page) • • Compare address on read or write on forced breakpoints High and/or low byte data compares MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Modes of Operation Modes of Operation The Breakpoint can operate in Dual Address Mode or Full Breakpoint Mode. Each of these modes is discussed in the subsections below. Dual Address Mode The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is force or tag. The BKxMBH:L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion. The BKxRW and BKxRWE bits in the BKPCT1 register select whether the type of bus cycle to match is a read, write, or both when performing forced breakpoints. Full Breakpoint Mode Full Breakpoint Mode requires a match on address and data for a breakpoint to occur. Upon a successful match, the system will enter Background Debug Mode or initiate a software interrupt based upon the state of the BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. The BDM requests have a higher priority than the SWI requests. R/W matches are also allowed in this mode. The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is forced or tagged. If the BKTAG bit is set in BKPCT0, then only address is matched, data is ignored. The BK0MBH:L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly, is a range breakpoint, or is in page space. The BK1MBH:L bits in the BKPCT1 register select whether the data is matched on the high byte, low byte, or both bytes. The BK0RW and BK0RWE bits in the BKPCT1 register select whether the type of bus cycle to match is a read or a write MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... When Dual Address Mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter Background Debug Mode or to initiate a software interrupt based upon the state of the BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. BDM requests have a higher priority than the SWI requests. No data breakpoints are allowed in this mode. Freescale Semiconductor, Inc. Breakpoint (BKP) when performing forced breakpoints. BK1RW and BK1RWE bits in the BKPCT1 register are not used in Full Breakpoint Mode. Block Diagram Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... A block diagram of the Breakpoint sub-block is shown in Figure 108 below. The Breakpoint contains three main sub-blocks: the Register Block, the Compare Block and the Control Block. The Register Block consists of the eight registers that make up the Breakpoint register space. The Compare Block performs all required address and data signal comparisons. The Control Block generates the signals for the CPU for the tag high, tag low, force SWI and force BDM functions. In addition, it generates the register read and write signals and the comparator block enable signals. NOTE: There is a two cycle latency for address compares for forces, a two cycle latency for write data compares, and a three cycle latency for read data compares. MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Block Diagram Clocks and control signals CONTROL BLOCK BKP control signals Breakpoint Modes and generation of SWI, force BDM & tags read/write ctl control sigs results sigs control bits ...... EXPANSION ADDRESS ADDRESS WRITE DATA READ DATA REGISTER BLOCK BKPCT0 ...... BKPCT1 COMPARE BLOCK expansion addresses BKP Read Data Bus BKP0X Comparator address high Write Data Bus BKP0H Comparator address low BKP0L Comparator BKP1X Comparator expansion addresses data high address high data low BKP1H Comparator Data/Address High Mux BKP1L Comparator Data/Address Low Mux address low Comparator read data high Comparator read data low Figure 108 Breakpoint Block Diagram MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Breakpoint (BKP) External Pin Descriptions The BKP sub-block does not access any external pins. Register Map Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Register Name BKPCT0 Read: Write: Bit 7 BKEN 6 BKFULL 5 BKBDM 4 BKTAG 3 0 2 0 1 0 Bit 0 0 Address Offset $0028 BKPCT1 Read: BK0MBH Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: 0 BK0MBL 0 BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW $0029 BKP0X BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 $002A BKP0H Bit 15 14 13 12 11 10 9 Bit 8 $002B BKP0L Bit 7 0 6 0 5 4 3 2 1 Bit 0 $002C BKP1X BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 $002D BKP1H Bit 15 14 13 12 11 10 9 Bit 8 $002E BKP1L Bit 7 6 5 4 3 2 1 Bit 0 $002F = Unimplemented or reserved Figure 109 Breakpoint Register Map NOTE: Register Address = Base Address (INITRG) + Address Offset MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Register Descriptions Register Descriptions There are eight 8-bit registers in the BKP module. NOTE: All bits of all registers in this module are completely synchronous to internal clocks during a register read. Read and write: anytime. Address Offset Read: Write: Reset: $0028 Bit 7 BKEN 0 6 BKFULL 0 5 BKBDM 0 4 BKTAG 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 = Reserved or unimplemented BKEN — Breakpoint Enable This bit enables the module. 1 = Breakpoint module on. 0 = Breakpoint module off. BKFULL— Full Breakpoint Mode Enable This bit controls whether the breakpoint module is in Dual Address Mode or Full Breakpoint Mode 1 = Full Breakpoint Mode enabled. 0 = Dual Address Mode enabled. BKBDM — Breakpoint Background Debug Mode Enable This bit determines if the breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI) 1 = Go to BDM on a compare. 0 = Go to Software Interrupt on a compare. MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Breakpoint Control Register 0 (BKPCT0) This register is used to set the breakpoint modes. Freescale Semiconductor, Inc. Breakpoint (BKP) BKTAG — Breakpoint on Tag This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint 1 = On match, break if the match is an instruction that will be executed (tagged). 0 = On match, break at the next instruction boundary (force). Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Breakpoint Control Register 1 (BKPCT1) This register is used to control the breakpoint logic that resides within the Core. Read and write: anytime. Address Offset Read: Write: Reset: $0029 Bit 7 BK0MBH 0 6 BK0MBL 0 5 BK1MBH 0 4 BK1MBL 0 3 BK0RWE 0 2 BK0RW 0 1 BK1RWE 0 Bit 0 BK1RW 0 BK0MBH:BK0MBL — Breakpoint Mask High Byte and Low Byte for First Address In Dual Address or Full Breakpoint Mode, these bits may be used to mask (disable) the comparison of the high and low bytes of the first address breakpoint. The functionality is as given in Table 102 below. Table 102 Breakpoint Mask Bits for First Address BK0MBH:BK0MBL x:0 0:1 1:1 1. If page is selected. Address Compare Full Address Compare 256 byte Address Range 16K byte Address Range BKP0X Yes(1) Yes(1) Yes(1) BKP0H Yes Yes No BKP0L Yes No No MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Register Descriptions The x:0 case is for a Full Address Compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {BKP0X[5:0],BKP0H[5:0],BKP0L[7:0]}. When a program page is not selected the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {BKP0H[7:0],BKP0L[7:0]}. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BK0MBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will only occur if BKP0X compares. BK1MBH:BK1MBL — Breakpoint Mask High Byte and Low Byte of Data (Second Address) In Dual Address Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The functionality is as given in Table 103 below. Table 103 Breakpoint Mask Bits for Second Address (Dual Address Mode) BK1MBH:BK1MBL x:0 0:1 1:1 1. If page is selected. Address Compare Full Address Compare 256 byte Address Range 16K byte Address Range BKP1X Yes(1) Yes(1) Yes(1) BKP1H Yes Yes No BKP1L Yes No No The x:0 case is for a Full Address Compare. When a program page is selected the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {BKP1X[5:0],BKP1H[5:0],BKP1L[7:0]}. When a program page is not selected the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {BKP1H[7:0],BKP1L[7:0]}. MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Breakpoint (BKP) The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BK1MBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will only occur if BKP1X compares. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... In Full Breakpoint Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. The functionality is as given in Table 104 below. Table 104 Breakpoint Mask Bits for Data Breakpoints (Full Breakpoint Mode) BK1MBH:BK1MBL 0:0 0:1 1:0 1:1 Data Compare High and Low Byte Compare High Byte Low Byte No Compare BKP1X No(1) No(1) No(1) No(1) BKP1H Yes Yes No No BKP1L Yes No Yes No 1. Expansion addresses for breakpoint 1 are not available in this mode. BK0RWE — R/W Compare Enable Enables the comparison of the R/W signal for first address breakpoint. This bit is not useful in tagged breakpoints. 1 = R/W is used in comparisons. 0 = R/W is not used in the comparisons. BK0RW— R/W Compare Value When BK0RWE=1, this bit determines the type of bus cycle to match on first address breakpoint. When BK0RWE=0, this bit has no effect. 1 = Read cycle will be matched 0 = Write cycle will be matched. MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Register Descriptions BK1RWE — R/W Compare Enable In Dual Address Mode, this bit enables the comparison of the R/W signal to further specify what causes a match for the second address breakpoint. This bit is not useful on tagged breakpoints or in Full Breakpoint Mode and is therefore a don’t care. 1 = R/W is used in comparisons. 0 = R/W is not used in comparisons. BK1RW — R/W Compare Value Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... When BK1RWE=1, this bit determines the type of bus cycle to match on the second address breakpoint.When BK1RWE=0, this bit has no effect. 1 = Read cycle will be matched. 0 = Write cycle will be matched. MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Breakpoint First Address Expansion Register (BKP0X) Address Offset Read: Write: Reset: This register contains the data to be matched against expansion address lines for the first address breakpoint when a page is selected. Read and write: anytime. $002A Bit 7 0 0 6 0 0 5 BK0V5 0 4 BK0V4 0 3 BK0V3 0 2 BK0V2 0 1 BK0V1 0 Bit 0 BK0V0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 0 = Reserved or unimplemented BK0V[5:0] — First Address Breakpoint Expansion Address Value Breakpoint First Address High Byte Register (BKP0H) Address Offset Read: Write: Reset: This register is used to set the breakpoint when compared against the high byte of the address. Read and write: anytime $002B Bit 7 Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0 Breakpoint First Address Low Byte Register (BKP0L) Address Offset Read: Write: Reset: This register is used to set the breakpoint when compared against the low byte of the address. Read and write: anytime $002C Bit 7 Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0 MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Register Descriptions Breakpoint Second Address Expansion Register(BKP1X) In Dual Address Mode, this register contains the data to be matched against expansion address lines for the second address breakpoint when a page is selected. In Full Breakpoint Mode, this register is not used. Read and write: anytime Address Offset Read: $002D Bit 7 0 0 6 0 0 5 BK1V5 0 4 BK1V4 0 3 BK1V3 0 2 BK1V2 0 1 BK1V1 0 Bit 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Write: Reset: BK1V0 0 = Reserved or unimplemented BK1V[5:0] — Second Address Breakpoint Expansion Address Value Breakpoint Data (Second Address) High Byte Register (BKP1H) Address Offset Read: Write: Reset: In Dual Address Mode, this register is used to compare against the high order address lines. In Full Breakpoint Mode, this register is used to compare against the high order data lines. Read and write: anytime Bit 7 Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0 $002E Breakpoint Data (Second Address) Low Byte Register (BKP1L) Address Offset Read: Write: Reset: In Dual Address Mode, this register is used to compare against the low order address lines. In Full Breakpoint Mode, this register is used to compare against the low order data lines. Read and write: anytime $002F Bit 7 Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0 MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Breakpoint (BKP) Breakpoint Priority Breakpoint operation is first determined by the state of BDM. If BDM is already active, meaning the CPU is executing out of BDM firmware, Breakpoints are not allowed. In addition, while in BDM trace mode, tagging into BDM is not allowed. If BDM is not active, the Breakpoint will give priority to BDM requests over SWI requests. This condition applies to both forced and tagged breakpoints. Freescale Semiconductor, Inc... In all cases, BDM related breakpoints will have priority over those generated by the Breakpoint sub-block. This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the Breakpoint sub-block.enabled. NOTE: BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. Even if the ENABLE bit in the BDM is negated, the CPU actually executes the BDM ROM code. It checks the ENABLE and returns if enable is not set. If the BDM is not serviced by the monitor, then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. Reset Initialization The reset state of each individual bit is listed within the Register Description section, which details the registers and their bit-fields. All registers are reset by the system reset. Interrupts The BKP sub-block causes the CPU to generate SWI interrupts when BKBDM bit is equal to zero. MC9S12T64Revision 1.1.1 Breakpoint (BKP) For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Electrical Characteristics Contents Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 Flash EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Voltage Regulator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 577 Reset, Oscillator and PLL Characteristics. . . . . . . . . . . . . . . . . . . . . 578 SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 General NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. This section contains the most accurate electrical information for the MC9S12T64 microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc. Power Supply The MC9S12T64 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins. VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2. Pins 5V I/O pins There are four groups of functional pins. Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. This group is made up by the VRH and VRL pins. The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. This pin is used for production testing only. This pin is used to enable the on chip voltage regulator. Analog Reference Oscillator TEST VREGEN MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Characteristics General Current Injection Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table 105 Absolute Maximum Ratings(1) Num 1 2 3 4 Rating I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage(2) PLL Supply Voltage (2) Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins (3) Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL(4) Instantaneous Maximum Current Single pin limit for TEST(5) Storage Temperature Range Symbol VDD5 VDD VDDPLL ∆VDDX ∆VSSX VIN VRH, VRL VILV VTEST ID IDL IDT Tstg Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –25 –25 –0.25 –65 Max 6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +25 0 155 Unit V V V Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family V V V V V V mA mA mA ˚C Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 13 1. Functional operation beyond absolute maximum ratings might damage the device. 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL 5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications. Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics General For power dissipation calculations refer to the subsection Power Dissipation and Thermal Characteristics. Table 106 Operating Conditions Rating I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage(1) PLL Supply Voltage (2) Symbol VDD5 VDD VDDPLL ∆VDDX ∆VSSX fosc fbus (1/tbus) TA TJ TA TJ TA TJ Min 4.75 2.25 2.25 –0.1 –0.1 2 1 Typ 5 2.5 2.5 0 0 — — Max 5.25 2.75 2.75 0.1 0.1 16 16.0 Unit V V V V V MHz MHz Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Voltage Difference VDDX to VDDR and VDDA Freescale Semiconductor, Inc... Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC9S12T64C Operating Ambient Temperature Range (2) Operating Junction Temperature Range MC9S12T64V Operating Ambient Temperature Range (2) Operating Junction Temperature Range MC9S12T64M Operating Ambient Temperature Range (2) Operating Junction Temperature Range –40 –40 –40 –40 –40 –40 27 — 27 — 27 — 85 100 105 120 125 140 ˚C ˚C ˚C 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2. Please refer to the subsection Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ. Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in ˚C can be obtained from: T J = T A + ( P D • Θ JA ) T J = Junction Temperature, [ ° C ] T A = Ambient Temperature, [ ° C ] P D = Total Chip Power Dissipation, [W] MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Θ JA = Package Thermal Resistance, [ ° C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W] 1. Internal Voltage Regulator disabled P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA 2 P IO = R DSON ⋅ I IO i i ∑ PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL V DD5 – V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA IDDR is the current shown in Table 109 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON ⋅ I IO i i respectively ∑ PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Two cases with internal voltage regulator enabled and disabled must be considered: Freescale Semiconductor, Inc. Electrical Characteristics General Table 107 Thermal Package Characteristics(1) Num 1 Thermal Resistance Rating Symbol θJA Min — Typ — Max 51 Unit ˚C/W 1. The values for thermal resistance are achieved by package simulations Table 108 5V I/O Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 2 3 4 Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current (pins in high ohmic input mode)(1) Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) Partial Drive IOH = –1.25mA Full Drive IOH = –3mA Output Low Voltage (pins in output mode) Partial Drive IOL = +1.25mA Full Drive IOL = +3mA Internal Pull Up Device Current, tested at VIL Max. Internal Pull Up Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at VIL Max. Input Capacitance Injection current(2) 12 Single Pin limit Total Device Limit. Sum of all injected currents IICS IICP –2.5 –25 — 2.5 25 mA Rating Symbol VIH VIL VHYS Iin –2.5 Min 0.70*VDD5 VSS5 – 0.3 Typ — — 250 — 2.5 Max VDD5 + 0.3 0.30*VDD5 Unit V V mV µA 5 VOH VDD5 – 0.8 — — V 6 VOL IPUL IPUH IPDH IPDL Cin — — 0.8 V µA µA µA µA pF 7 8 9 10 11 — –10 — 10 — — — — 7 –130 — 130 — — MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... I/O Characteristics This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Freescale Semiconductor, Inc. Electrical Characteristics 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50˚C to 125˚C. 2. Refer to the subsection Current Injection (page 563), for more details Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 16MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Additional Remarks Table 109 Supply Current Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 Run supply currents Single Chip Mode Wait Supply current 2 Pseudo Stop Current (1) 3 4 1. PLL off Rating Symbol IDD5 IDDW Min Typ Max 30 25 10 Unit mA All modules enabled, PLL on Only RTI enabled, PLL off RTI and COP enabled RTI and COP disabled Stop Current mA IDDPS IDDS 500 250 60 7,000 6,500 6,000 µA µA MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Measurement Conditions Freescale Semiconductor, Inc. Electrical Characteristics ATD Characteristics ATD Characteristics This section describes the characteristics of the analog to digital converter. ATD Operating Characteristics The Table 110 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table 110 ATD Operating Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 2 3 4 Differential Reference Voltage(1) ATD Clock Frequency ATD 10-Bit Conversion Period Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK ATD 8-Bit Conversion Period 5 5 6 Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK Stop Recovery Time (VDDA=5.0 Volts) Reference Supply current NCONV8 TCONV8 tSR IREF 12 6 26 13 20 0.75 Cycles µs µs mA NCONV10 TCONV10 14 7 28 14 Cycles µs Rating Reference Potential Low High VRL VRH VRH–VRL fATDCLK VSSA VDDA/2 4.75 0.5 5.0 VDDA/2 VDDA 5.25 2.0 V V V MHz Symbol Min Typ Max Unit 1. Full accuracy is not guaranteed when differential voltage is less than 4.75V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. Factors Influencing Accuracy Two factors - source resistance and source capacitance - have an influence on the accuracy of the ATD. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Characteristics Source Resistance: Due to the input pin leakage current as specified in Table 108 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS– CINN). Table 111 ATD Electrical Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 2 3 Disruptive Analog Input Current Rating Max input Source Resistance Total Input Capacitance Non Sampling Sampling CINN CINS INA –2.5 10 15 2.5 pF mA Symbol RS Min — Typ — Max 1 Unit KΩ ATD accuracy Table 112 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Source Capacitance Freescale Semiconductor, Inc. Electrical Characteristics ATD Characteristics Table 112 ATD Conversion Performance Conditions are shown in Table 106 unless otherwise noted VREF = VRH – VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Num 1 2 3 10-Bit Resolution 10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error (1) Rating Symbol LSB DNL INL AE LSB DNL INL AE Min Typ 5 Max Unit mV –1 –2.5 –3 ±1.5 ±2.0 20 –0.5 –1.0 –1.5 ±0.5 ±1.0 1 2.5 3 Counts Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Counts Counts mV Freescale Semiconductor, Inc... 4 5 6 7 8 Error(1) 0.5 1.0 1.5 Counts Counts Counts 1. These values include quantization error which is inherently 1/2 count for any A/D converter. For the following definitions see also Figure 110. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. Vi – Vi – 1 DNL ( i ) = ----------------------- – 1 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ i=1 Vn – V0 DNL ( i ) = ------------------- – n 1LSB MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics DNL LSB Vi-1 $3FF $3FE $3FD 10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $FE $3F4 $3F3 $FD 9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50 Ideal Transfer Curve 2 10-Bit Transfer Curve 1 8-Bit Transfer Curve 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure 110 ATD Accuracy Definitions NOTE: Figure 110 shows only definitions, for specification values refer to Table 112. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family $3FC $FF Freescale Semiconductor, Inc... 10-Bit Resolution 8-Bit Resolution Freescale Semiconductor, Inc. Electrical Characteristics Flash EEPROM Characteristics Flash EEPROM Characteristics Flash EEPROM timing The time base for all Flash EEPROM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The Flash EEPROM module does not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the Flash EEPROM module at a lower frequency a full program or erase transition is not assured. The Flash EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV register. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table 113 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and minimum fbus. Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency f¨NVMOP and can be calculated according to the following formula. 1 1 t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f bus f NVMOP Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: 1 1 t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ---------f bus f NVMOP The time to program a whole row is: MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Characteristics t brpgm = t swpgm + 31 ⋅ t bwpgm Burst programming is more than 2 times faster than single word programming. Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes: 1 t era ≈ 4000 ⋅ --------------------f NVMOP The setup times can be ignored for this operation. Mass Erase Erasing a NVM block takes: Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 1 t mass ≈ 20000 ⋅ --------------------f NVMOP The setup times can be ignored for this operation. Blank Check The time it takes to perform a blank check on the Flash is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ≅ location ⋅ t bus + 10 ⋅ t bus MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Flash EEPROM Characteristics Table 113 NVM Timing Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 2 3 Rating External Oscillator Clock Bus Frequency for Programming or Erase Operations Operating Frequency Single Word Programming Time Flash Burst Programming Time for Consecutive Word Flash Burst Programming Time for 32 Words Sector Erase Time Mass Erase Time Blank Check Time per Block Symbol fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck Min 2 1 150 46 (2) Typ Max 16 (1) Unit MHz MHz 200 85 (3) kHz Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 4 5 6 7 8 9 µs µs µs ms ms tbus 20.4 (2) 678.4 (2) 20 (4) 100 (4) 35.7 (3) 1190.7 (3) 26.7 (3) 133 (3) 11(5) 32778(6) 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in subsections from Single Word Programming through Mass Erase for guidance. 4. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 5. Minimum time. If first word in the array is not blank. 6. Maximum time to complete check on erased block. NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE: All values shown in Table 114 are target values and subject to further extensive characterization. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Table 114 NVM Reliability Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 2 Rating Data Retention at an average junction temperature of TJavg = 65˚C Flash number of Program/Erase cycles Symbol tNVMRET nFLPE 10 100 Unit Years Cycles Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Voltage Regulator Characteristics Voltage Regulator Characteristics The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table 115 Voltage Regulator Recommended Load Capacitance Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Rating Symbol CLVDD CLVPLL Min Typ 220 220 Max Unit nF nF Freescale Semiconductor, Inc... Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Reset, Oscillator and PLL Characteristics This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). Startup Table 116 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clocks and Reset Generator (CRG) section in page 271. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Table 116 Startup Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 2 3 4 5 6 7 8 9 Rating Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, IRQ edge-sensitive mode Wait recovery startup time Low-voltage detector reset release level Low voltage detection level Low-voltage detector reset/recover hysteresis POR rearm level (1) Symbol PWRSTL nRST PWIRQ tWRS VLVRR VLVR VLVHYS VPOR RPOR Min 2 192 20 Typ Max Unit tosc 196 nosc ns tbus V V 14 4.75 3.9 200 0 100 0.035 mV mV V/ms POR rise time ramp rate (2) 1. Maximum is highest voltage that POR is guaranteed. 2. If minimum VDD is not reached before the internal POR reset is released, RESET must be driven low externally until minimum VDD is reached. POR and Low-voltage detector (LVD) Reset External Reset The release level VLVRR and the detection level VLVR are derived from the VDDR, while the rearm level VPOR is derived from the VDD. They are also valid if the device is powered externally. When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Reset, Oscillator and PLL Characteristics reset vector without doing a clock quality check, if there was an oscillation before reset. Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector. Oscillator The device features internal Colpitts and Pierce oscillators. By asserting the XCLKS input during reset the Colpitts oscillator can be bypassed allowing the input of a square wave or the Pierce oscillator. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, LVD reset, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR/LVDR or STOP if a proper oscillation is not detected. The fastest startup time possible is given by nuposc. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Clock Monitor Failure Assert Frequency fCMFA. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Pseudo Stop and Wait Recovery Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Characteristics Table 117 Oscillator Characteristics (1) Conditions are shown in Table 106 unless otherwise noted Num 1 2 3 4 Rating Crystal oscillator range (Colpitts) Startup Current Oscillator start-up time (2) Symbol fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS Min 2 100 Typ Max 16 Unit MHz µA 8 0.45 50 2 30 30 (3) 400 (4) ms s KHz MHz ns ns Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Clock Quality check time-out Clock Monitor Failure Assert Frequency External square wave input frequency(5) External square wave pulse width low External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance (EXTAL, XTAL inputs) DC Operating Bias in Colpitts Configuration on EXTAL Pin 2.5 100 200 32 Freescale Semiconductor, Inc... 5 6 7 8 9 10 11 12 1 1 9 1.1 ns ns pF V 1. When Colpitts Oscillator is selected during reset. 2. The oscillator start-up time is measured as the time necessary to detect a stable ECLK on pin PE4 after POR. 3. fosc = 4MHz, C = 22pF 4. Maximum value is for extreme cases using high Q, low frequency crystals 5. XCLKS =0 during reset MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Reset, Oscillator and PLL Characteristics Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. This section describes the selection of the XFC components to achieve a good filter characteristics. Motorola suggest the use of the following values R= 2.2 KΩ, Cs=33 nF, and Cp = 3.3 nF when fREF = 4MHz, fBUS = 16MHz, fVCO = 32MHz, REFDV = #$00, and SYNR = #$03. See Figure 111. These values are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. XFC Component Selection VDDPLL CS MCU RS XFC CP Figure 111 PLL Loop Filter Connections MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Characteristics Table 118 PLL Characteristics Conditions are shown in Table 106 unless otherwise noted Num 1 2 3 Rating Self Clock Mode frequency VCO locking range PLL Lock Time Jitter (2) (1) Symbol fSCM fVCO tlock Min Typ 3 Max Unit MHz 8 1 –0.26 –0.05 32 MHz ms Freescale Semiconductor, Inc... 4 Short term (5µs interval) Long term (500µs interval) jshort jlong 0.26 0.05 % 1. Lock time is defined as the time necessary for the PLL to have its LOCK bit asserted after its multiplication factor 2 ⋅ 〈 SYNR + 1〉 ⁄ 〈 REVDF + 1〉 was changed. 2. Jitter is defined as the average deviation from the programmed target frequency measured over an specific time interval (5 µs or 500 µs) at maximum fVCO. SPI Timing Master Mode Figure 112 and Figure 113 illustrate the master mode timing. Timing values are shown in Table 119. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Electrical Characteristics SPI Timing SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 6 MSB IN2 9 MOSI (OUTPUT) 1. If configured as output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. 1 4 4 11 3 12 Freescale Semiconductor, Inc... MISO (INPUT) BIT 6 . . . 1 9 LSB IN 10 LSB OUT MSB OUT2 BIT 6 . . . 1 Figure 112 SPI Master Timing (CPHA = 0) SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA 1. If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. 12 11 3 4 11 12 6 MSB IN2 BIT 6 . . . 1 10 LSB IN MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA Figure 113 SPI Master Timing (CPHA =1) MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Electrical Characteristics Table 119 SPI Master Mode Timing Characteristics(1) Conditions are shown in Table 106 unless otherwise noted, CLOAD = 200pF on all outputs Num 1 1 2 3 Rating Operating Frequency SCK Period tsck = 1/ fop Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid (after SCK Edge) Data Hold Time (Outputs) Rise Time Inputs and Outputs Fall Time Inputs and Outputs Symbol fop tsck tlead tlag twsck tsu thi tv tho tr tf Min DC 4 1/2 1/2 tbus − 30 25 0 Typ Max 1/4 2048 — Unit fbus tbus tsck Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family tsck 1024 tbus ns ns ns 25 ns ns 25 25 ns ns Freescale Semiconductor, Inc... 4 5 6 9 10 11 12 0 1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the Master and the Slave timing shown in Table 120. Slave Mode Figure 114 and Figure 115 illustrate the slave mode timing. Timing values are shown in Table 120. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics SPI Timing SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 7 9 MSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 4 4 11 12 8 10 10 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 12 11 3 Freescale Semiconductor, Inc... MISO (OUTPUT) SLAVE 5 SLAVE LSB OUT MOSI (INPUT) Figure 114 SPI Slave Timing (CPHA = 0) SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 11 3 10 BIT 6 . . . 1 SLAVE LSB OUT 8 Figure 115 SPI Slave Timing (CPHA =1) MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics Table 120 SPI Slave Mode Timing Characteristics Conditions are shown in Table 106 unless otherwise noted, CLOAD = 200pF on all outputs Num 1 1 2 3 Rating Operating Frequency SCK Period fsck = 1 / fop Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Data Hold Time (Outputs) Rise Time Inputs and Outputs Fall Time Inputs and Outputs Symbol fop tsck tlead tlag twsck tsu thi ta tdis tv tho tr tf 0 25 25 Min DC 4 1 1 tbus − 30 25 25 1 1 25 Typ Max 1/4 2048 Unit fbus tbus tbus ns ns ns tbus tbus ns ns ns ns Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family tbus Freescale Semiconductor, Inc... 4 5 6 7 8 9 10 11 12 MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics External Bus Timing External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure 116 with the actual timing values shown on table Table 121. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. Freescale Semiconductor, Inc... General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Electrical Characteristics 1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family 4 16 10 data 11 Freescale Semiconductor, Inc... 20 ECS PK7 21 22 23 24 R/W PE2 25 26 27 LSTRB PE3 28 29 30 NOACC PE7 31 32 33 IPIPE[1:0] PE[6:5] 34 35 36 Figure 116 General External Bus Timing MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Characteristics External Bus Timing Table 121 Expanded Bus Timing Characteristics – 16MHz Conditions are shown in Table 106 unless otherwise noted, CLOAD = 50pF Num 1 2 3 4 5 Rating Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high(1) Address delay time Address valid time to E rise (PWEL–tAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time(1) (PWEH–tDDW) Address access time(1) (tcyc–tAD–tDSR) E high access time(1) (PWEH–tDSR) Chip select delay time Chip select access time(1) (tcyc–tCSD–tDSR) Chip select hold time Chip select negated time Read/write delay time Read/write valid time to E rise (PWEL–tRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWEL–tLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWEL–tNOD) NOACC hold time ECLK Low to IPIPE[1:0] delay time IPIPE[1:0] valid time to E rise (PWEL–tP0D) Symbol fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V 15 –6 0 16 12 14 –5 14 14 –5 15 17 –5 11 15 –3 13 19 4 20 11 –5 9 –2 25 –5 16 Min 0 62.5 29 29 18 Typ Max 16.0 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Freescale Semiconductor, Inc. Electrical Characteristics Table 121 Expanded Bus Timing Characteristics – 16MHz (Continued) Conditions are shown in Table 106 unless otherwise noted, CLOAD = 50pF 35 36 ECLK High to IPIPE[1:0] delay time(1) (PWEH–tP1V) IPIPE[1:0] valid time to E fall tP1D tP1V 0 16 40 ns ns 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches. MC9S12T64Revision 1.1.1 Electrical Characteristics For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com MC9S12T64Revision 1.1.1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com MC9S12T64Revision 1.1.1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... MC9S12T64Revision 1.1.1 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc. Glossary A — See “accumulators (A and B or D).” accumulators (A and B or D) — Two 8-bit (A and B) or one 16-bit (D) general-purpose registers in the CPU. The CPU uses the accumulators to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation with large loop bandwidth. Also see “tracking mode”. address bus — The set of wires that the CPU or DMA uses to read and write memory locations. addressing mode — The way that the CPU determines the operand address for an instruction. The M68HC12 CPU has 15 addressing modes. ALU — See “arithmetic logic unit (ALU).” analogue-to-digital converter (ATD) — The ATD module is an 8-channel, multiplexed-input successive-approximation analog-to-digital converter. arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous — Refers to logic circuits and operations that are not synchronized by a common reference signal. ATD — See “analogue-to-digital converter”. B — See “accumulators (A and B or D).” baud rate — The total number of bits transmitted per unit of time. BCD — See “binary-coded decimal (BCD).” binary — Relating to the base 2 number system. binary number system — The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. For example, 234 (decimal) = 0010 0011 0100 (BCD) bit — A binary digit. A bit has a value of either logic 0 or logic 1. branch instruction — An instruction that causes the CPU to continue processing at a memory location other than the next sequential address. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... break module — The break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint — A number written into the break address registers of the break module. When a number appears on the internal address bus that is the same as the number in the break address registers, the CPU executes the software interrupt instruction (SWI). break interrupt — A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus — A set of wires that transfers logic signals. bus clock — See “CPU clock”. byte — A set of eight bits. CAN — See “Motorola scalable CAN.” CCR — See “condition code register.” central processor unit (CPU) — The primary functioning unit of any computer system. The CPU controls the execution of instructions. CGM — See “clock generator module (CGM).” clear — To change a bit from logic 1 to logic 0; the opposite of set. clock — A square wave signal used to synchronize events in a computer. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Glossary clock generator module (CGM) — The CGM module generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and/or phase-locked loop (PLL) circuit. comparator — A device that compares the magnitude of two inputs. A digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (COP) — A counter module that resets the MCU if allowed to overflow. condition code register (CCR) — An 8-bit register in the CPU that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit — One bit of a register manipulated by software to control the operation of the module. control unit — One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations. The control unit decodes instructions and generates the internal control signals that perform the requested operations. The outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, and bus interface. COP — See “computer operating properly module (COP).” CPU — See “central processor unit (CPU).” CPU12 — The CPU of the MC68HC12 Family. CPU clock — Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL) determine which clock drives SYSCLK for the main system, including the CPU and buses. When EXTALi drives the SYSCLK, the CPU or bus clock frequency (fo) is equal to the EXTALi frequency divided by 2. CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC12 are: • • A (8-bit accumulator) B (8-bit accumulator) – • D (16-bit accumulator formed by concatenation of accumulators A and B) IX (16-bit index register) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... • • • • IY (16-bit index register) SP (16-bit stack pointer) PC (16-bit program counter) CCR (8-bit condition code register) cycle time — The period of the operating frequency: tCYC = 1/fOP. D — See “accumulators (A and B or D).” decimal number system — Base 10 numbering system that uses the digits zero through nine. duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is usually represented by a percentage. ECT — See “enhanced capture timer.” EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of memory that can be electrically erased and reprogrammed. EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. enhanced capture timer (ECT) — The HC12 Enhanced Capture Timer module has the features of the HC12 Standard Timer module enhanced by additional features in order to enlarge the field of applications. exception — An event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program. fetch — To copy data from a memory location into the accumulator. firmware — Instructions and data programmed into nonvolatile memory. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Glossary flash EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of memory that can be electrically erased and reprogrammed. Does not support byte or word erase. free-running counter — A device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission — Communication on a channel in which data can be sent and received simultaneously. hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A through F. high byte — The most significant eight bits of a word. illegal address — An address not within the memory map illegal opcode — A nonexistent opcode. index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing modes, the CPU uses the contents of IX or IY to determine the effective address of the operand. IX and IY can also serve as a temporary data storage locations. input/output (I/O) — Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions — Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction. interrupt — A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine. I/O — See “input/output (I/0).” jitter — Short-term signal instability. latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency — The time lag between instruction completion and data movement. least significant bit (LSB) — The rightmost digit of a binary number. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary logic 1 — A voltage level approximately equal to the input power voltage (VDD). logic 0 — A voltage level approximately equal to the ground voltage (VSS). low byte — The least significant eight bits of a word. M68HC12 — A Motorola family of 16-bit MCUs. mark/space — The logic 1/logic 0 convention used in formatting data in serial communication. mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used in integrated circuit fabrication to transfer an image onto silicon. MCU — Microcontroller unit. See “microcontroller.” memory location — Each M68HC12 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal. In response to the read signal, the selected memory location places its data onto the data bus. memory map — A pictorial representation of all memory locations in a computer system. MI-Bus — See “Motorola interconnect bus”. microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU, memory, a clock oscillator, and input/output (I/O) on a single integrated circuit. modulo counter — A counter that can be programmed to count to any number from zero to its maximum possible modulus. most significant bit (MSB) — The leftmost digit of a binary number. Motorola interconnect bus (MI-Bus) — The Motorola Interconnect Bus (MI Bus) is a serial communications protocol which supports distributed real-time control efficiently and with a high degree of noise immunity. Motorola scalable CAN (msCAN) — The Motorola scalable controller area network is a serial communications protocol that efficiently supports distributed real-time control with a very high level of data integrity. msCAN — See “Motorola scalable CAN”. MSI — See “multiple serial interface”. multiple serial interface — A module consisting of multiple independent serial I/O sub-systems, e.g. two SCI and one SPI. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary multiplexer — A device that can select one of a number of inputs and pass the logic level of that input on to the output. nibble — A set of four bits (half of a byte). object code — The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode — A binary code that instructs the CPU to perform an operation. open-drain — An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand — Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator — A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that cannot be reprogrammed. overflow — A quantity that is too large to be contained in one byte or one word. page zero — The first 256 bytes of memory (addresses $0000–$00FF). parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts the number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. PC — See “program counter (PC).” peripheral — A circuit not under direct CPU control. phase-locked loop (PLL) — A clock generator circuit in which a voltage controlled oscillator produces an oscillation which is synchronized to a reference signal. PLL — See “phase-locked loop (PLL).” pointer — Pointer register. An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, VDD and VSS. polling — Periodically reading a status bit to monitor the condition of a peripheral device. port — A set of wires for communicating with off-chip devices. prescaler — A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program — A set of computer instructions that cause a computer to perform a desired operation or operations. program counter (PC) — A 16-bit register in the CPU. The PC register holds the address of the next instruction or operand that the CPU will use. pull — An instruction that copies into the accumulator the contents of a stack RAM location. The stack RAM address is in the stack pointer. pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width — The amount of time a signal is on as opposed to being in its off state. pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a signal with a constant frequency. push — An instruction that copies the contents of the accumulator to the stack RAM. The stack RAM address is in the stack pointer. PWM period — The time required for one complete cycle of a PWM waveform. RAM — Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off. RC circuit — A circuit consisting of capacitors and resistors having a defined time constant. read — To copy the contents of a memory location to the accumulator. register — A circuit that stores a group of bits. reserved memory location — Writing to a reserved location has no effect. Reading a reserved location always returns ZERO. reset — To force a device to a known condition. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary ROM — Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU. SCI — See “serial communication interface module (SCI).” serial — Pertaining to sequential transmission over a single line. serial communications interface module (SCI) — A module that supports asynchronous communication. serial peripheral interface module (SPI) — A module that supports synchronous communication. set — To change a bit from logic 0 to logic 1; opposite of clear. shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed — A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number. software — Instructions and data that control the operation of a microcontroller. software interrupt (SWI) — An instruction that causes an interrupt and its associated vector fetch. SPI — See “serial peripheral interface module (SPI).” stack — A portion of RAM reserved for storage of CPU register contents and subroutine return addresses. stack pointer (SP) — A 16-bit register in the CPU containing the address of the next available storage location on the stack. start bit — A bit that signals the beginning of an asynchronous serial transmission. status bit — A register bit that indicates the condition of a device. stop bit — A bit that signals the end of an asynchronous serial transmission. MC9S12T64Revision 1.1.1 Glossary For More Information On This Product, Go to: www.freescale.com Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX Product Family, DragonBall Product Family Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary subroutine — A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns to the main program where it left off. synchronous — Refers to logic circuits and operations that are synchronized by a common reference signal. timer — A module used to relate events in a system to a point in time. toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode — A mode of PLL operation with narrow loop bandwidth. Also see ‘acquisition mode.’ two’s complement — A means of performing binary subtraction using addition techniques. The most significant bit of a two’s complement number indicates the sign of the number (1 indicates negative). The two’s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered — Utilizes only one register for data; new data overwrites current data. unimplemented memory location — A memory location that is not used. Writing to an unimplemented location has no effect. Reading an unimplemented location returns an unpredictable value. variable — A value that changes during the course of program execution. VCO — See “voltage-controlled oscillator.” vector — A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform — A graphical representation in which the amplitude of a wave is plotted against time. wired-OR — Connection of circuit outputs so that if any output is high, the connection point is high. word — A set of two bytes (16 bits). write — The transfer of a byte of data from the CPU to a memory location. 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