MC9S12XHZ512
Data Sheet Covers MC9S12XHZ384, MC9S12XHZ256
HCS12X Microcontrollers
MC9S12XHZ512V1 Rev. 1.03 1/2007
freescale.com
MC9S12XHZ512 Data Sheet
MC9S12XHZ512V1 Rev. 1.03 1/2007
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document.
Revision History
Date January 5, 2006 April 20, 2006 July 28, 2006 January 8, 2007 Revision Level 01.00 01.01 01.02 01.03 New Book Updated block guide versions Made minor corrections Added MC9S12XHZ384 and MC9S12XHZ256 Description
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2007. All rights reserved. MC9S12XHZ512 Data Sheet, Rev. 1.03 4 Freescale Semiconductor
List of Chapters
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 Chapter 25 MC9S12XHZ Family Device Overview . . . . . . . . . . . . . . . . . . . 25 Port Integration Module (S12XHZPIMV1) . . . . . . . . . . . . . . . . . 61 512 Kbyte Flash Module (S12XFTX512K4V3). . . . . . . . . . . . . 135 4 Kbyte EEPROM Module (S12XEETX4KV2) . . . . . . . . . . . . . 177 XGATE (S12XGATEV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Security (S12X9SECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Clocks and Reset Generator (CRGV6) . . . . . . . . . . . . . . . . . . 345 Pierce Oscillator (S12XOSCLCPV1) . . . . . . . . . . . . . . . . . . . . 385 Analog-to-Digital Converter (ATD10B16CV4) . . . . . . . . . . . . 391 Liquid Crystal Display (LCD32F4BV1) . . . . . . . . . . . . . . . . . . 425 Motor Controller (MC10B12CV2). . . . . . . . . . . . . . . . . . . . . . . 443 Stepper Stall Detector (SSDV1). . . . . . . . . . . . . . . . . . . . . . . . 475 Inter-Integrated Circuit (IICV3) . . . . . . . . . . . . . . . . . . . . . . . . 493 Freescale’s Scalable Controller Area Network (MSCANV3) . 519 Serial Communication Interface (SCIV5) . . . . . . . . . . . . . . . . 577 Serial Peripheral Interface (SPIV4) . . . . . . . . . . . . . . . . . . . . . 615 Periodic Interrupt Timer (PIT24B4CV1) . . . . . . . . . . . . . . . . . 641 Pulse-Width Modulator (PWM8B8CV1). . . . . . . . . . . . . . . . . . 655 Enhanced Capture Timer (ECT16B8CV3). . . . . . . . . . . . . . . . 687 Voltage Regulator (VREG3V3V5) . . . . . . . . . . . . . . . . . . . . . . 741 Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . 755 S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . 781 External Bus Interface (S12XEBIV3) . . . . . . . . . . . . . . . . . . . . 823 Interrupt (S12XINTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 Memory Mapping Control (S12XMMCV3) . . . . . . . . . . . . . . . . 865
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Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 Appendix D Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 Appendix E Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
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Table of Contents
Chapter 1 MC9S12XHZ Family Device Overview
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.1.5 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.5.1 User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.5.2 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1.5.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.6.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.6.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.2
1.3 1.4 1.5
1.6
1.7 1.8
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.1 lntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.1 Port A and Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.2 Port C and Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.3.3 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3.4 Port K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.3.5 Miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.3.6 Port AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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2.2 2.3
2.4
2.5 2.6
2.3.7 Port L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.3.8 Port M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.3.9 Port P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.3.10 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.3.11 Port T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.3.12 Port U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.13 Port V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.3.14 Port W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.4.1 I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.4.2 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.4.3 Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 2.4.4 Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.4.5 Pull Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.4.6 Polarity Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.4.7 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 2.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 2.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 2.6.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 2.6.3 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.4.3 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
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3.2 3.3
3.4
3.5
3.6
3.7
3.8
Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.6.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 3.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 175 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 3.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.4.1 EEPROM Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.4.2 EEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.4.3 Illegal EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 EEPROM Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 208 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.7.1 EEPROM Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.7.2 Reset While EEPROM Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.8.1 Description of EEPROM Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
4.2 4.3
4.4
4.5
4.6 4.7
4.8
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Chapter 5 XGATE (S12XGATEV2)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 5.4.4 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.4.5 Software Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.5.1 Incoming Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.5.2 Outgoing Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.6.1 Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.6.2 Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 5.6.3 Leaving Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.8.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.8.2 Instruction Summary and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 5.8.3 Cycle Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.8.4 Thread Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.8.5 Instruction Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.8.6 Instruction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 5.9.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 5.9.2 Code Example (Transmit "Hello World!" on SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
5.2 5.3 5.4
5.5
5.6
5.7 5.8
5.9
Chapter 6 Security (S12X9SECV2)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 6.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 6.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
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6.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 6.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 6.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Chapter 7 Clocks and Reset Generator (CRGV6)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 7.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 348 7.2.2 XFC — External Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 7.2.3 RESET — Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 7.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 7.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 7.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 7.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 7.5.2 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 7.5.3 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 381 7.5.4 Power On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 7.6.1 Real Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 7.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 7.6.3 Self Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
7.2
7.3
7.4
7.5
7.6
Chapter 8 Pierce Oscillator (S12XOSCLCPV1)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 8.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 386 8.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 8.2.3 XCLKS — Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
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8.2
8.3
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 8.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 8.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 8.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 8.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 9.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins 393 9.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . . . . 393 9.2.3 VRH, VRL — High Reference Voltage Pin, Low Reference Voltage Pin . . . . . . . . . . . . 393 9.2.4 VDDA, VSSA — Analog Circuitry Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . 393 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 9.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 9.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 9.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
9.2
9.3
9.4
9.5 9.6
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.2.1 BP[3:0] — Analog Backplane Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.2.2 FP[31:0] — Analog Frontplane Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.2.3 VLCD — LCD Supply Voltage Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
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10.4.1 LCD Driver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 10.4.2 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.4.3 Operation in Pseudo Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.4.5 LCD Waveform Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Chapter 11 Motor Controller (MC10B12CV2)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 11.2.1 M0C0M/M0C0P/M0C1M/M0C1P — PWM Output Pins for Motor 0 . . . . . . . . . . . . 446 11.2.2 M1C0M/M1C0P/M1C1M/M1C1P — PWM Output Pins for Motor 1 . . . . . . . . . . . . 447 11.2.3 M2C0M/M2C0P/M2C1M/M2C1P — PWM Output Pins for Motor 2 . . . . . . . . . . . . 447 11.2.4 M3C0M/M3C0P/M3C1M/M3C1P — PWM Output Pins for Motor 3 . . . . . . . . . . . . 447 11.2.5 M4C0M/M4C0P/M4C1M/M4C1P — PWM Output Pins for Motor 4 . . . . . . . . . . . . 447 11.2.6 M5C0M/M5C0P/M5C1M/M5C1P — PWM Output Pins for Motor 5 . . . . . . . . . . . . 447 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 11.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 11.4.2 PWM Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 11.4.3 Motor Controller Counter Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 11.4.4 Output Switching Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 11.4.5 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.4.6 Operation in Stop and Pseudo-Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.6.1 Timer Counter Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 11.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 11.7.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
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Chapter 12 Stepper Stall Detector (SSDV1)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 12.1.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 12.2.1 COSxM/COSxP — Cosine Coil Pins for Motor x . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 12.2.2 SINxM/SINxP — Sine Coil Pins for Motor x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 12.4.1 Return to Zero Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 12.4.2 Full Step States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 12.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 12.4.4 Stall Detection Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Chapter 13 Inter-Integrated Circuit (IICV3)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 13.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 13.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 13.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 13.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
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Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 14.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 14.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 14.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 14.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 14.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 14.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 14.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 14.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 14.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 14.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 14.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 14.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Chapter 15 Serial Communication Interface (SCIV5)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 15.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 15.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 15.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 15.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 15.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
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15.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 15.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 15.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 15.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 15.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 15.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 15.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 15.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 15.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 15.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Chapter 16 Serial Peripheral Interface (SPIV4)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 16.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 16.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 16.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 16.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 16.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 16.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 16.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
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Chapter 17 Periodic Interrupt Timer (PIT24B4CV1)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 17.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 17.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 17.4.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 17.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 17.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Chapter 18 Pulse-Width Modulator (PWM8B8CV1)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 18.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 18.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 18.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 18.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
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Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.2 IOC6 — Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.3 IOC5 — Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.4 IOC4 — Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.5 IOC3 — Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.6 IOC2 — Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.7 IOC1 — Input Capture and Output Compare Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.2.8 IOC0 — Input Capture and Output Compare Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . 689 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 19.4.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 19.4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 19.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Chapter 20 Voltage Regulator (VREG3V3V5)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 20.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 20.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 743 20.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.2.5 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 20.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 20.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 20.4.3 Low-Voltage Detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
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20.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.5 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.6 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.7 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 20.4.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 20.4.9 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 20.4.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Chapter 21 Background Debug Module (S12XBDMV2)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 21.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 21.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 21.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 21.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 21.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 21.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 21.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 21.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 21.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 21.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 21.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 21.4.10Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 21.4.11Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
Chapter 22 S12X Debug (S12XDBGV3) Module
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 22.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 22.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 22.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 22.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 22.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 22.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
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22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 22.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 22.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 22.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 22.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 22.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 22.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Chapter 23 External Bus Interface (S12XEBIV3)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 23.1.1 Glossary or Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 23.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 23.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 23.4.1 Operating Modes and External Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 23.4.2 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 23.4.3 Accesses to Port Replacement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 23.4.4 Stretched External Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 23.4.5 Data Select and Data Direction Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 23.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 23.5.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 23.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Chapter 24 Interrupt (S12XINTV1)
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 24.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 24.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
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24.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 24.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 24.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 24.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 24.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 24.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 24.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 24.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 24.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 24.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 24.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 25.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 25.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 25.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 25.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 25.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 25.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 25.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886 25.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886 25.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 25.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899 25.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 25.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 25.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 25.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 25.5.2 Port Replacement Registers (PRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 25.5.3 On-Chip ROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 25.6 Internal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 25.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 25.6.2 S12X System behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 25.6.3 S12X_CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 25.6.4 S12X_BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 25.6.5 XGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 25.6.6 S12X_FLEXRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
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25.6.7 Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 25.6.8 XBUS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.9 XBUS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.10XBUS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.11XBUS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 25.6.12XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 25.7 Generic Labeling Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
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Appendix A Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 A.2 ATD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 A.3 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 A.3.1 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 A.3.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948 A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 A.5 Reset, Oscillator, and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 A.5.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 A.5.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 A.6 LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 A.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 A.8 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 A.8.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 A.8.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 A.9 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 A.9.1 Normal Expanded Mode (External Wait Feature Disabled). . . . . . . . . . . . . . . . . . . . . . 962 A.9.2 Normal Expanded Mode (External Wait Feature Enabled) . . . . . . . . . . . . . . . . . . . . . . 964 A.9.3 Emulation Single-Chip Mode (Without Wait States) . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 A.9.4 Emulation Expanded Mode (With Optional Access Stretching) . . . . . . . . . . . . . . . . . . 969 A.9.5 External Tag Trigger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 23
Appendix B Package Information
B.1 144-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 B.2 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Appendix C PCB Layout Guidelines Appendix D Ordering Information Appendix E Detailed Register Map
MC9S12XHZ512 Data Sheet, Rev. 1.03 24 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
1.1 Introduction
Targeted at automotive instrumentation applications, the MC912XHZ family of microcontrollers is a fully pin-compatible extension to the existing MC9S12HZ family. It offers not only a larger memory but also incorporates all the architectural benefits of the new S12X-based family to deliver significantly higher performance. The MC9S12XHZ family retains the low cost, power consumption, EMC and code-size efficiency advantages currently associated with the MC9S12 products. Based around S12X core, the MC912XHZ family runs 16-bit wide accesses without wait states for all peripherals and memories. The MC912XHZ family also features a new flexible interrupt handler, which allows multilevel nested interrupts. The MC912XHZ family features the performance boosting XGATE co-processor. The XGATE is programmable in “C” language and runs at twice the bus frequency of the S12. Its instruction set is optimized for data movement, logic and bit manipulation instructions. Any peripheral module can be serviced by the XGATE. The MC912XHZ family contains up to 512K bytes of Freescale Semiconductor’s industry leading, full automotive qualified Split-Gate Flash memory, with 4K bytes of additional integrated data EEPROM and up to 32K bytes of static RAM. The MC912XHZ family features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited to drive six stepper motors with stall detectors (SSD) to simultaneously calibrate the pointer reset position of each motor. It also features two MSCAN modules, each with a FIFO receiver buffer arrangement, and input filters optimized for Gateway applications handling numerous message identifiers. In addition, the MC912XHZ family is composed of standard on-chip peripherals including two asynchronous serial communications interfaces (SCI0 and SCI1), one serial peripheral interface (SPI), two IIC-bus interface (IIC0 and IIC1), an 8-channel 16-bit enhanced capture timer (ECT), a 16-channel, 10-bit analog-to-digital converter (ADC), and one 8-channel pulse width modulator (PWM). The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. The new fast-exit from STOP mode feature can further improve system power consumption. In addition to the I/O ports available in each module, 8 general-purpose I/O pins are available with interrupt and wake-up capability from stop or wait mode. The MC912XHZ family is available in 112-pin LQFP and 144-pin LQFP packages. The 144-pin LQFP package option provides a full 16-bit wide non-multiplexed external bus interface.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 25
Chapter 1 MC9S12XHZ Family Device Overview
1.1.1
•
Features
HCS12X Core — 16-bit HCS12X CPU – Upward compatible with MC9S12 instruction set – Interrupt stacking and programmer’s model identical to MC9S12 – Instruction queue – Enhanced indexed addressing – Enhanced instruction set — EBI (external bus interface) — MMC (module mapping control) — INT (interrupt controller) — DBG (debug module to monitor HCS12X CPU and XGATE bus activity) — BDM (background debug mode) XGATE (peripheral coprocessor) — Parallel processing module off loads the CPU by providing high-speed data processing and transfer — Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports Memory – 512K, 384K, 256K byte Flash EEPROM – 4K byte EEPROM – 32K, 28K, 16K byte RAM CRG (clock and reset generator) — Low noise/low power Pierce oscillator — PLL — COP watchdog — Real time interrupt — Clock monitor — Fast wake-up from stop mode Analog-to-digital converter — 16 channels, 10-bit resolution — External conversion trigger capability ECT (enhanced capture timer) — 16-bit main counter with 7-bit prescaler — 8 programmable input capture or output compare channels — Four 8-bit or two 16-bit pulse accumulators PIT (periodic interrupt timer) — Four timers with independent time-out periods — Time-out periods selectable between 1 and 224 bus clock cycles
•
•
•
•
•
•
MC9S12XHZ512 Data Sheet, Rev. 1.03 26 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
•
•
•
•
•
•
•
8 PWM (pulse-width modulator) channels — Programmable period and duty cycle — 8-bit 8-channel or 16-bit 4-channel — Separate control for each pulse width and duty cycle — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies — Fast emergency shutdown input Two 1-Mbps, CAN 2.0 A, B software compatible modules — Five receive and three transmit buffers — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit — Four separate interrupt channels for Rx, Tx, error, and wake-up — Low-pass filter wake-up function — Loop-back for self-test operation Two IIC (Inter-IC bus) Modules — Compatible with IIC bus standard — Multi-master operation — Broadcast mode Serial interfaces — Two asynchronous serial communication interfaces (SCI) with additional LIN support and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width — Synchronous Serial Peripheral Interface (SPI) Liquid crystal display (LCD) driver with variable input voltage — Configurable for up to 32 frontplanes and 4 backplanes or general-purpose input or output — 5 modes of operation allow for different display sizes to meet application requirements — Unused frontplane and backplane pins can be used as general-purpose I/O PWM motor controller (MC) with 24 high current drivers — Each PWM channel switchable between two drivers in an H-bridge configuration — Left, right and center aligned outputs — Support for sine and cosine drive — Dithering — Output slew rate control Six stepper stall detectors (SSD) — Full step control during return to zero — Voltage detector and integrator / sigma delta converter circuit — 16-bit accumulator register — 16-bit modulus down counter
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 27
Chapter 1 MC9S12XHZ Family Device Overview
•
•
• •
On-Chip Voltage Regulator — Two parallel, linear voltage regulators with bandgap reference — Low-voltage detect (LVD) with low-voltage interrupt (LVI) — Power-on reset (POR) circuit — 3.3-V–5.5-V operation — Low-voltage reset (LVR) — Ultra low-power wake-up timer 144-pin LQFP and 112-pin LQFP packages — I/O lines with 5-V input and drive capability — Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation — 5-V A/D converter inputs — 8 key wake up interrupts with digital filtering and programmable rising/falling edge trigger Operation at 80 MHz equivalent to 40-MHz bus speed Development support — Single-wire background debug™ mode (BDM) — Four on-chip hardware breakpoints
1.1.2
Modes of Operation
User modes: • Normal and emulation operating modes — Normal single-chip mode — Normal expanded mode — Emulation of single-chip mode — Emulation of expanded mode • Special Operating Modes — Special single-chip mode with active background debug mode — Special test mode (Freescale use only) Low-power modes: • System stop modes — Pseudo stop mode — Full stop mode • System wait mode
1.1.3
Block Diagram
Figure 1-1 shows a block diagram of the MC912XHZ family.
MC9S12XHZ512 Data Sheet, Rev. 1.03 28 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
512K, 384K, 256K Bytes Flash EEPROM 4k Bytes EEPROM
TEST BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 VDDR VDD1 VSS1,2
Pins and signals shown in BOLD are not available in the 112 QFP package
Peripheral Co-Processor
32K, 28K, 16K Bytes RAM Single-Wire Background CPU12X Debug Module Clock and Reset Generation Module
Periodic Interrupt COP Watchdog Clock Monitor Breakpoints FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 XIRQ IRQ RW/WE LSTRB/LDS/EROMCTL ECLK MODA/TAGLO/RE MODB/TAGHI XCLKS/ECLKX2 ADDR16/IQSTAT0 ADDR17/IQSTAT1 ADDR18/IQSTAT2 ADDR19/IQSTAT3 ADDR20/ACC0 ADDR21/ACC1 ADDR22/ACC2 EWAIT/ROMCTL DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 FP20 FP21
XGATE
4-Channel Programmable Interrupt Timer (PIT) for internal timebases VDDA VSSA VRH VRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 KWAD0 KWAD1 KWAD2 KWAD3 KWAD4 KWAD5 KWAD6 KWAD7 VDDA VSSA VRH VRL PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 PV0 PV1 PV2 PV3 PV4 PV5 PV6 PV7 PW0 PW1 PW2 PW3 PW4 PW5 PW6 PW7 VLCD PM1 CS1 PM2 PM3 PM4 PM5 PS0 PS1 PS2 CS3 PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 CS0 PP7 CS2
PLL
Enhanced Multilevel Interrupt Module AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
Analog to Digital Converter
AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
DDRAD DDRU DDRV DDRW DDRM DDRP
SSD0
DDRK
PTK
FP22 BP0 BP1 BP2 BP3
SSD1
M0COSM M0COSP M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP M2COSM M2COSP M2SINM M2SINP M3COSM M3COSP M3SINM M3SINP M4COSM M4COSP M4SINM M4SINP M5COSM M5COSP M5SINM M5SINP
DDRE
PWM0 PWM1 PWM2 PWM3 PWM4
M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P
PTE
SSD2
FP23
SSD3 LCD Driver
Non-Multiplexed External Bus Interface
SSD4
DDRA
PLL Supply 2.5V VDDPLL VSSPLL I/O Supply 5V VDDX1,2 VSSX1,2 Internal 2.5V VDD1 VSS1,2 Voltage Regulator 5V VDDR
SPI
PW0 PW1 Pulse PW2 Width Modulator PW3 PW4 PW5 PW6 PW7
Module-to-Port-Routing
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7
FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP24 FP25 FP26 FP27 SDA0 SCL0 SDA1 SCL1
DDRB
PTB
Motor Supplies VDDM1,2,3 VSSM1,2,3 A/D Converter & Voltage Regulator 5V VDDA VSSA
CAN0 TXCAN0 CAN1 TXCAN1 SCI0 SCI1
RXCAN1 RXD0 TXD0 RXD1 TXD1 MISO MOSI SCK SS
PTA
Enahanced Capture Timer
DDRT
PTT
IIC0 IIC1
SDA0 SCL0 SDA1 SCL1
Voltage Regulator
Figure 1-1. MC9S12XHZ Family Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 29
PTP
DDRS PTS
PTM
DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
DDRC
PTC
SSD5
VLCD
M2C0M M2C0P M2C1M PWM5 M2C1P M3C0M PWM6 M3C0P M3C1M PWM7 M3C1P M4C0M PWM8 M4C0P M4C1M PWM9 M4C1P M5C0M PWM10 M5C0P M5C1M PWM11 M5C1P
DDRD
PTD
RXCAN0
PTW
PTV
PTU
PTAD
DDRL
PTL
Chapter 1 MC9S12XHZ Family Device Overview
1.1.4
Device Memory Map
Table 1-1 shows the device memory map for the MC912XHZ family. Unimplemented register space shown in Table 1-1 is not allocated to any module. Writing to these locations have no effect. Read access to these locations returns zero.
Table 1-1. Device Register Memory Map
Address Offset 0x0000–0x0009 0x000A–0x000B 0x000C–0x000D 0x000E–0x000F 0x0010–0x0017 0x0018–0x0019 0x001A–0x001B 0x001C–0x001F 0x0020–0x002F 0x0030–0x0031 0x0032–0x0033 0x0034–0x003F 0x0040–0x007F 0x0080–0x00AF 0x00B0–0x00BF 0x00C0–0x00C7 0x00C8–0x00CF 0x00D0–0x00D7 0x00D8–0x00DF 0x00E0–0x00FF 0x0100–0x010F 0x0110–0x011B 0x011C–0x011F 0x0120–0x0137 0x0138–0x013F 0x0140–0x017F 0x0180–0x01BF 0x01C0–0x01FF 0x0200–0x027F 0x0280–0x0287 0x0288–0x028F 0x0290–0x0297 0x0298–0x029F PIM (port integration module) MMC (memory map control) PIM (port integration module) EBI (external bus interface) MMC (memory map control) Unimplemented Device ID register PIM (port integration module) DBG (debug module) MMC (memory map control) PIM (port integration module) CRG (clock and reset generator) ECT (enhanced capture timer 16-bit 8-channel) ATD (analog-to-digital converter 10-bit 16-channel) INT (interrupt module) IIC0 (inter IC bus) SCI0 (serial communications interface) SCI1 (serial communications interface) SPI (serial peripheral interface) Unimplemented Flash control registers EEPROM control registers MMC (memory map control) Liquid Crystal Display Driver 32x4 (LCD) IIC1 (inter IC bus) CAN0 (scalable CAN) CAN1 (scalable CAN) MC (motor controller) PIM (port integration module) SSD4 (stepper stall detector) SSD0 (stepper stall detector) SSD1 (stepper stall detector) SSD2 (stepper stall detector) Module Size (Bytes) 10 2 2 2 8 2 2 4 16 2 2 12 64 48 16 8 8 8 8 32 16 12 4 24 8 64 64 64 128 8 8 8 8
MC9S12XHZ512 Data Sheet, Rev. 1.03 30 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
Table 1-1. Device Register Memory Map
Address Offset 0x02A0–0x02A7 0x02A8–0x02AF 0x02B0–0x02EF 0x02F0–0x02F7 0x02F8–0x02FF 0x0300–0x0327 0x0328–0x033F 0x0340–0x0367 0x0368–0x037F 0x0380–0x03BF 0x03C0–0x03FF 0x0400–0x07FF SSD3 (stepper stall detector) SSD5 (stepper stall detector) Unimplemented Voltage regulator Unimplemented PWM (pulse-width modulator 8 channels) Unimplemented PIT (periodic interrupt timer) Unimplemented XGATE Unimplemented Unimplemented Module Size (Bytes) 8 8 64 8 8 40 24 40 24 64 64 1024
Figure 1-2 shows the CPU & BDM local address translation to the global memory map. It indicates also the location of the internal resources in the memory map.
Table 1-2. Device Internal Resources
Device MC9S12XHZ512 MC9S12XHZ384 MC9S12XHZ256 RAMSIZE / RAM_LOW 32K / 0x0F_8000 28K / 0x0F_9000 16K / 0x0F_C000 EEPROMSIZE / EEPROM_LOW 4K / 0x13_F000 4K / 0x13_F000 4K / 0x13_F000 FLASHSIZE0 / FLASH0_LOW 256K / 0x7B_FFFF 128K / 0x79_FFFF 128K / 0x79_FFFF FLASHSIZE1 / FLASH1_HIGH 256K / 0x7C_0000 256K / 0x7C_0000 128K / 0x7E_0000
Figure 1-3 shows XGATE local address translation to the global memory map. It indicates also the location of used internal resources in the memory map.
Table 1-3. XGATE Resources
Device MC9S12XHZ512 MC9S12XHZ384 MC9S12XHZ256
1
XGRAMSIZE / XGRAMLOW 32K / 0x0F_8000 28K / 0x0F_9000 16K / 0x0F_C000
XGFLASHSIZE / XGFLASH_HIGH 30K1 / 0x78_7FFF
This value is calculated by the following formula: (64K - 2K - XGRAMSIZE)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 31
Chapter 1 MC9S12XHZ Family Device Overview
CPU and BDM Local Memory Map
0x00_0000 0x00_07FF
Global Memory Map
2K REGISTERS
Unimplemented RAM
RAM_LOW RAM 2K REGISTERS 1K EEPROM window 1K EEPROM 4K RAM window 8K RAM 0x4000 0x13_FFFF Unpaged 16K FLASH 0x1F_FFFF 0x8000 External Space CS1 16K FLASH window PPAGE 0x3F_FFFF Unimplemented FLASH Unpaged 16K FLASH 0xFFFF
FLASHSIZE0
0x0000 0x0800 0x0C00 0x1000 0x2000
EPAGE
0x0F_FFFF Unimplemented EEPROM EEPROM_LOW EEPROM EEPROMSIZE
RAMSIZE
RPAGE
Reset Vectors
0x78_0000 FLASH0 FLASH0_LOW Unimplemented FLASH FLASH1_HIGH FLASH1 0x7F_FFFF
FLASHSIZE
Figure 1-2. MC9S12XHZ Family Global Memory Map
MC9S12XHZ512 Data Sheet, Rev. 1.03 32 Freescale Semiconductor
FLASHSIZE1
CS0
CS0
0xC000
CS2
CS2
CS3
Chapter 1 MC9S12XHZ Family Device Overview
XGATE Local Memory Map
0x00_0000 0x00_07FF
Global Memory Map
Registers
0x0000 Registers 0x0800 RAM 0x0F_FFFF XGRAMSIZE XGRAM_LOW RAMSIZE FLASHSIZE 33
FLASH
RAM
0x78_0800 FLASH XGFLASH_HIGH 0xFFFF
0x7F_FFFF
Figure 1-3. XGATE Global Address Mapping
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
1.1.5
Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0X001B). The read-only value is a unique part ID for each revision of the chip. Table 1-4 shows the assigned part ID number and mask set number.
Table 1-4. Assigned Part ID Numbers
Device MC9S12XHZ512 MC9S12XHZ384 MC9S12XHZ256
The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision including fab transfers Bit 3-0: Minor non-full mask set revision
1
Mask Set Number
Part ID
1
0M80F
0xE400
1.2
Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals.
1.2.1
Device Pinout
The MC912XHZ family is offered in the following package options: • 144-pin LQFP with an external bus interface (address/data bus) • 112-pin LQFP without an external bus interface Figure 1-4 and Figure 1-5 show the pin assignments.
MC9S12XHZ512 Data Sheet, Rev. 1.03 34 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
FP28/AN12/PL4 FP29AN13//PL5 FP30/AN14//PL6 FP31/AN15/PL7 M4C0M/M4COSM/PW0 M4C0P/M4COSP/PW1 M4C1M/M4SINM/PW2 M4C1P/M4SINP/PW3 VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 VDDM3 VSSM3 M5C0M/M5COSM/PW4 M5C0P/M5COSP/PW5 M5C1M/M5SINM/PW6 M5C1P/M5SINP/PW7 SCL0/PWM5/PP5 SDA0/PWM4/PP4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PT7/IOC7/SCL1 PT6/IOC6/SDA1 PT5/IOC5/SCL0 PT4/IOC4/SDA0 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 PC7/DAT15 PC6/DAT14 PC5/DAT13 PC4/DAT12 VSSX1 VDDX1 PK7/EWAIT/ROMCTL/FP23 PE7/ECLKX2/XCLKS/FP22 PE3/LSTRB/LDS/EROMCTL/FP21 PE2/RW/WE/FP20 PC3/DAT11 PC2/DAT10 PC1/DAT9 PC0/DAT8 PL3/AN11/FP19 PL2/AN10/FP18 PL1/AN9/FP17 PL0/AN8/FP16 PA7/ADDR15/FP15 PA6/ADDR14/FP14 PA5/ADDR13/FP13 PA4/ADDR12/FP12 PA3/ADDR11/FP11 PA2/ADDR10/FP10 PA1/ADDR9/FP9 PA0/ADDR8/FP8 PB7/ADDR7/FP7 PB6/ADDR6/FP6
MC9S12XHZ Family 144 LQFP
Pins shown in BOLD are not available in the 112 QFP package
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PB5/ADDR5/FP5 PB4/ADDR4/FP4 PB3/ADDR3/FP3 PB2/ADDR2/FP2 PB1/ADDR1/FP1 PB0/ADDR0/FP0 PK0/ADDR16/BP0 PK1/ADDR17/BP1 PK2/ADDR18/BP2 PK3/ADDR19/BP3 VLCD VSS1 VDD1 PD7/DATA7 PD6/DATA6 PD5/DATA5 PD4/DATA4 PD3/DATA3 PD2/DATA2 PD1/DATA1 PD0/DATA0 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/MODB/TAGHI
Freescale Semiconductor
PWM3/PP3 RXD1/PWM2/PP2 TXD1/PWM0/PP0 PWM1/PP1 CS0/SDA1/PWM6/PP6 CS2/SCL1/PWM7/PP7 ACC0/ADDR20/PK4 ACC1/ADDR21/PK5 RXD0/PS0 TXD0/PS1 CS3/RXD1/PS2 TXD1/PS3 VSS2 VDDR VDDX2 VSSX2 MODC/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST ACC2/ADDR22/PK6 CS1/PM1 RXCAN0/PM2 TXCAN0/PM3 RXCAN1/PM4 TXCAN1/PM5 TAGLO/RE/MODA/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
Figure 1-4. MC9S12XHZ Family 144 LQFP Pin Assignment
MC9S12XHZ512 Data Sheet, Rev. 1.03 35
Chapter 1 MC9S12XHZ Family Device Overview
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/FP23 PE7/XCLKS/FP22 PE3/FP21 PE2/FP20 PL3/AN11/FP19 PL2/AN10/FP18 PL1/AN9/FP17 PL0/AN8/FP16 PA7/FP15 PA6/FP14 PA5/FP13 PA4/FP12 PA3/FP11 PA2/FP10 PA1/FP9 PA0/FP8 PB7/FP7 PB6/FP6
PT7/IOC7/SCL1 PT6/IOC6/SDA1 PT5/IOC5/SCL0 PT4/IOC4/SDA0
FP28/AN12/PL4 FP29AN13//PL5 FP30/AN14//PL6 FP31/AN15/PL7 VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 VDDM3 VSSM3 SCL0/PWM5/PP5 SDA0/PWM4/PP4
PWM3/PP3 RXD1/PWM2/PP2 TXD1/PWM0/PP0 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2 MODC/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3
Figure 1-5. MC9S12XHZ Family 112 LQFP Pin Assignment
MC9S12XHZ512 Data Sheet, Rev. 1.03 36 Freescale Semiconductor
RXCAN1/PM4 TXCAN1/PM5
PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MC9S12XHZ Family 112 LQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PB5/FP5 PB4/FP4 PB3/FP3 PB2/FP2 PB1/FP1 PB0/FP0 PK0/BP0 PK1/BP1 PK2/BP2 PK3/BP3 VLCD VSS1 VDD1 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6
Chapter 1 MC9S12XHZ Family Device Overview
1.2.2
Signal Properties Summary
Table 1-5. Signal Properties
Table 1-5 summarizes all pin functions.
Pin Pin Name Name Function 1 Function 2 EXTAL XTAL RESET TEST XFC BKGD PAD[7:0] PA[7:0] PB[7:1] PB0 — — — — — MODC AN[7:0] FP[15:8] FP[7:1] FP0
Pin Name Function 3 — — — — — — KWAD[7:0] ADDR[15:8] ADDR[7:1] ADDR0
Pin Pin Powered Name Name by Function 4 Function 5 — — — — — — — IVD[15:8] IVD[7:1] IVD0 — — — — — — — — — UDS VDDPLL VDDPLL VDDX2 NA VDDPLL VDDX2 VDDA VDDX1 VDDX1 VDDX1
Internal Pull Up Resistor Description CTRL NA NA PULL UP NA NA Always on PERAD/ PPSAD PUCR PUCR PUCR NA NA Up Reset State NA NA External reset Test input - must be tied to VSS in all applications PLL loop Filter Background debug, mode input Oscillator pins
Disabled Port AD I/O, Analog inputs (ATD), interrupts Down Down Down Port A I/O, address bus, internal visibility data Port B I/O, address bus, internal visibility data Port B I/O, address bus, internal visibility data, upper data strobe
PC[7:0] PD[7:0] PE7
— — FP22
DATA[15:8] DATA[7:0] ECLKX2
— — XCLKS
— — —
VDDX1 VDDX1 VDDX1
PUCR PUCR PUCR
Disabled Port C I/O, data bus Disabled Port D I/O, data bus Down Port E I/O, LCD driver, system clock output, clock select Port E I/O, tag high, mode input Port E I/O, tag low, mode input, read enable Port E I/O, bus clock output Port E I/O, LCD driver, low byte strobe, EROMON control Port E I/O, read/write, write enable Port E input, maskable interrupt Port E input, non-maskable interrupt
PE6 PE5 PE4 PE3 PE2 PE1 PE0
TAGHI TAGLO ECLK FP21 FP20 IRQ XIRQ
MODB MODA — LSTRB R/W — —
— RE — LDS WE — —
— — — EROMCTL — — —
VDDX2 VDDX2 VDDX2 VDDX1 VDDX1 VDDX2 VDDX2
While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR PUCR Down Down Down
Up Up
PUCR
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 37
Chapter 1 MC9S12XHZ Family Device Overview
Table 1-5. Signal Properties
Pin Pin Name Name Function 1 Function 2 PK7 PK[6:4] PK[3:0] PL[7:4] PL[3:0] PM5 PM4 PM3 PM2 PM1 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 FP23 — BP[3:0] FP[31:28] FP[19:16] TXCAN1 RXCAN1 TXCAN0 RXCAN0 — PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SS SCK MOSI MISO TXD1 RXD1 TXD0 RXD0 Pin Name Function 3 ECS ADDR[22:20] Pin Pin Powered Name Name by Function 4 Function 5 ROMCTL ACC[2:0] ROMCTL — — — — — — — — — — — — — — — — — — — — — — — — — VDDX1 VDDX2 VDDX1 VDDA VDDX1 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 PERS/ PPSS PERP/ PPSP PERM/ PPSM PERL/ PPSL Down Internal Pull Up Resistor Description CTRL PUCR Reset State Down Port K I/O, emulation chip select, ROM on enable Port K I/O, extended address, access source Port K I/O, LCD driver, extended address, pipe status Port L I/O, LCD drivers, analog inputs (ATD) Port L I/O, LCD drivers, analog inputs (ATD) Disabled Port M I/O, TX of CAN1 Port M I/O, RX of CAN1 Port M I/O, TX of CAN0 Port M I/O, RX of CAN0 Port M I/O, chip select 1 Disabled Port P I/O, PWM channel, SCL of IIC1, chip select 2 Port P I/O, PWM channel, SDA of IIC1, chip select 0 Port P I/O, PWM channel, SCL of IIC0 Port P I/O, PWM channel, SDA of IIC0 Port P I/O, PWM channel Port P I/O, PWM channel, RXD of SCI1 Port P I/O, PWM channel Port P I/O, PWM channel, TXD of SCI1 Disabled Port S I/O, SS of SPI Port S I/O, SCK of SPI Port S I/O, MOSI of SPI Port S I/O, MISO of SPI Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1, chip select 3 Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0
ADDR[19:16] IQSTAT[3:0] AN[15:12] AN[11:8] — — — — — SCL1 SDA1 SCL0 SDA0 — RXD1 — TXD1 — — — — — — — — — — — — — — CS1 CS2 CS0 — — — — — — — — — — — CS3 — —
MC9S12XHZ512 Data Sheet, Rev. 1.03 38 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
Table 1-5. Signal Properties
Pin Pin Name Name Function 1 Function 2 PT7 PT6 PT5 PT4 PT[3:0] PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 PV7 PV6 PV5 PV4 PV3 PV2 PV1 PV0 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 IOC7 IOC6 IOC5 IOC4 IOC[3:0] M1C1P M1C1M M1C0P M1C0M M0C1P M0C1M M0C0P M0C0M M3C1P M3C1M M3C0P M3C0M M2C1P M2C1M M2C0P M2C0M M5C1P M5C1M M5C0P M5C0M M4C1P M4C1M M4C0P M4C0M Pin Name Function 3 SCL1 SDA1 SCL0 SDA0 FP[27:24] M1SINP M1SINM M1COSP M1COSM M0SINP M0SINM M0COSP M0COSM M3SINP M3SINM M3COSP M3COSM M2SINP M2SINM M2COSP M2COSM M5SINP M5SINM M5COSP M5COSM M4SINP M4SINM M4COSP M4COSM Pin Pin Powered Name Name by Function 4 Function 5 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VDDX1 VDDX1 VDDX1 VDDX1 VDDX1 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 Port W I/O, motor 4 coil nodes of MC or SSD4 PERW/ PPSW Disabled Port W I/O, motor 5 coil nodes of MC or SSD5 Port V I/O, motor 2 coil nodes of MC or SSD2 PERV/ PPSV Disabled Port V I/O, motor 3 coil nodes of MC or SSD3 Port U I/O, motor 0 coil nodes of MC or SSD0 PERT/ PPST PERU/ PPSU Down Internal Pull Up Resistor Description CTRL PERT/ PPST Reset State Disabled Port T I/O, Timer channels, SCL of IIC1 Port T I/O, Timer channels, SDA of IIC1 Port T I/O, Timer channels, SCL of IIC0 Port T I/O, Timer channels, SDA of IIC0 Port T I/O, Timer channels, LCD driver
Disabled Port U I/O, motor1 coil nodes of MC or SSD1
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 39
Chapter 1 MC9S12XHZ Family Device Overview
Table 1-6. Power and Ground
Mnemonic VLCD VDD1 VSS1 VSS2 VDDR VSSR VDDX1 VDDX2 VSSX1 VSSX2 VDDA VSSA VRH VRL VDDPLL VSSPLL VDDM1,2,3 VSSM1,2,3 Nominal Voltage 5.0 V 2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 2.5 V 0V 5.0 V 0V Operating voltage and ground for the analog-to-digital converter and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltage high for the ATD converter. Reference voltage low for the ATD converter. Provides operating voltage and ground for the phased-locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Provides operating voltage and ground for motor 0, 1, 2 and 3. External power and ground, supply to pin drivers. Voltage reference pin for the LCD driver. Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. External power and ground, supply to pin drivers and internal voltage regulator. Description
NOTE All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.
1.2.3
1.2.3.1
Detailed Signal Descriptions
EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
1.2.3.2
RESET — External Reset Pin
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.The RESET pin has an internal pullup device.
MC9S12XHZ512 Data Sheet, Rev. 1.03 40 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
1.2.3.3
TEST — Test Pin
NOTE The TEST pin must be tied to VSS in all applications.
This input only pin is reserved for test. This pin has a pulldown device.
1.2.3.4
XFC — PLL Loop Filter Pin
Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
VDDPLL CS MCU R0 CP VDDPLL
XFC
Figure 1-6. PLL Loop Filter Connections
1.2.3.5
BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pullup device.
1.2.3.6
PAD[7:0] / AN[7:0] / KWAD[7:0] — Port AD I/O Pins [7:0]
PAD7–PAD0 are general-purpose input or output pins and analog inputs for the analog-to-digital converter. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.2.3.7
PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins
PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data.
1.2.3.8
PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins
PB[7:1] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 41
Chapter 1 MC9S12XHZ Family Device Overview
1.2.3.9
PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin 0
PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation, this pin is used for external address bus ADDR0 and internal visibility read data IVD0.
1.2.3.10
PC[7:0] / DATA [15:8] — Port C I/O Pins
PC[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PC[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes.
1.2.3.11
PD[7:0] / DATA [7:0] — Port D I/O Pins
PD[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes.
1.2.3.12
PE7 / FP22 / ECLKX2 / XCLKS — Port E I/O Pin 7
PE7 is a general-purpose input or output pin. The pin can be configured as frontplane segment driver output FP22 of the LCD module or as the internal system clock ECLKX2. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing. This is the case for: • Power on reset or low-voltage reset • Clock monitor reset • Any reset while in self-clock mode or full stop mode The selected oscillator configuration is frozen with the rising edge of reset.
MC9S12XHZ512 Data Sheet, Rev. 1.03 42 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
EXTAL C1 MCU XTAL C2 VSSPLL Crystal or Ceramic Resonator
Figure 1-7. Loop Controlled Pierce Oscillator Connections (PE7 = 0)
EXTAL C1 MCU RS XTAL C2 VSSPLL RB Crystal or Ceramic Resonator
Figure 1-8. Full Swing Pierce Oscillator Connections (PE7 = 1)
EXTAL MCU XTAL
CMOS-Compatible External Oscillator
Not Connected
Figure 1-9. External Clock Connections (PE7 = 1)
1.2.3.13
PE6 / MODB / TAGHI — Port E I/O Pin 6
PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the instruction word being read into the instruction queue. The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE6 is configured to reduced levels out of reset in expanded and emulation modes.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 43
Chapter 1 MC9S12XHZ Family Device Overview
1.2.3.14
PE5 / MODA / TAGLO / RE — Port E I/O Pin 5
PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the read enable RE output. This pin is an input with a pull-down device which is only active when RESET is low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue. The input voltage threshold for PE5 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE5 is configured to reduced levels out of reset in expanded and emulation modes.
1.2.3.15
PE4 / ECLK — Port E I/O Pin 4
PE4 is a general-purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
1.2.3.16
PE3 / FP21 / LSTRB / LDS / EROMCTL— Port E I/O Pin 3
PE3 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP21 of the LCD module. In MCU expanded modes of operation, LSTRB or LDS can be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET the state of this pin is latched to the EROMON bit.
1.2.3.17
PE2 / FP20 / R/W / WE— Port E I/O Pin 2
PE2 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP20 of the LCD module. In MCU expanded modes of operations, this pin drives the read/write output signal or write enable output signal for the external bus. It indicates the direction of data on the external bus.
1.2.3.18
PE1 / IRQ — Port E Input Pin 1
PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.
1.2.3.19
PE0 / XIRQ — Port E Input Pin 0
PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.
1.2.3.20
PK7 / FP23 / EWAIT / ROMCTL — Port K I/O Pin 7
PK7 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP23 of the LCD module. During MCU emulation modes and normal expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal maintains the external bus access until the external device is ready to capture data (write) or provide data (read).
MC9S12XHZ512 Data Sheet, Rev. 1.03 44 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
The input voltage threshold for PK7 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PK7 is configured to reduced levels out of reset in expanded and emulation modes.
1.2.3.21
PK[6:4] / ADDR[22:20] / ACC[2:0] — Port K I/O Pin [6:4]
PK[6:4] are general-purpose input or output pins. During MCU expanded modes of operation, the ACC[2:0] signals are used to indicate the access source of the bus cycle. This pins also provide the expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is time multiplexed with the high addresses
1.2.3.22
PK[3:0] / BP[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0]
PK3-PK0 are general-purpose input or output pins. The pins can be configured as backplane segment driver outputs BP3–BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.
1.2.3.23
PL[7:4] / FP[31:28] / AN[15:12] — Port L I/O Pins [7:4]
PL7–PL4 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP31–FP28 of the LCD module or analog inputs for the analog-to-digital converter.
1.2.3.24
PL[3:0] / FP[19:16] / AN[11:8] — Port L I/O Pins [3:0]
PL3–PL0 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP19–FP16 of the LCD module or analog inputs for the analog-to-digital converter.
1.2.3.25
PM5 / TXCAN1 — Port M I/O Pin 5
PM5 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN1 of the scalable controller area network controller 1 (CAN1)
1.2.3.26
PM4 / RXCAN1 — Port M I/O Pin 4
PM4 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN1 of the scalable controller area network controller 1 (CAN1)
1.2.3.27
PM3 / TXCAN0 — Port M I/O Pin 3
PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the scalable controller area network controller 0 (CAN0)
1.2.3.28
PM2 / RXCAN0 — Port M I/O Pin 2
PM2 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN0 of the scalable controller area network controller 0 (CAN0).
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1.2.3.29
PM1 / CS1 — Port M I/O Pin 1
PM1 is a general-purpose input or output pin. It can be configured to provide a chip-select output.
1.2.3.30
PP7 / PWM7 / SCL1 / CS2 — Port P I/O Pin 7
PP7 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM7 or the serial clock pin SCL1 of the inter-IC bus interface 1 (IIC1). It can be configured to provide a chip-select output.
1.2.3.31
PP6 / PWM6 / SDA1 / CS0 — Port P I/O Pin 6
PP6 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM6 or the serial data pin SDA1 of the inter-IC bus interface 1 (IIC1). It can be configured to provide a chip-select output.
1.2.3.32
PP5 / PWM5 / SCL0 — Port P I/O Pin 5
PP5 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM5 or the serial clock pin SCL0 of the inter-IC bus interface 0 (IIC0).
1.2.3.33
PP4 / PWM4 / SDA0 — Port P I/O Pin 4
PP4 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM4 or the serial data pin SDA0 of the inter-IC bus interface 0 (IIC0).
1.2.3.34
PP3 / PWM3 — Port P I/O Pin 3
PP3 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM3.
1.2.3.35
PP2 / PWM2 / RXD1 — Port P I/O Pin 2
PP2 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM2 or the receive pin RXD1 of the serial communication interface 1 (SCI1).
1.2.3.36
PP1 / PWM1 — Port P I/O Pin 1
PP1 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM1.
1.2.3.37
PP0 / PWM0 / TXD1 — Port P I/O Pin 0
PP0 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM0 or the transmit pin TXD1 of the serial communication interface 1 (SCI1).
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1.2.3.38
PS7 / SS — Port S I/O Pin 7
PS7 is a general-purpose input or output pin. It can be configured as slave select pin SS of the serial peripheral interface (SPI).
1.2.3.39
PS6 / SCK — Port S I/O Pin 6
PS6 is a general-purpose input or output pin. It can be configured as serial clock pin SCK of the serial peripheral interface (SPI).
1.2.3.40
PS5 / MOSI — Port S I/O Pin 5
PS5 is a general-purpose input or output pin. It can be configured as the master output (during master mode) or slave input (during slave mode) pin MOSI of the serial peripheral interface (SPI).
1.2.3.41
PS4 / MISO — Port S I/O Pin 4
PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO for the serial peripheral interface (SPI).
1.2.3.42
PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general-purpose input or output pin. It can be configured as transmit pin TXD1 of the serial communication interface 1 (SCI1).
1.2.3.43
PS2 / RXD1 / CS2 — Port S I/O Pin 2
PS2 is a general-purpose input or output pin. It can be configured as receive pin RXD1 of the serial communication interface 1 (SCI1). It can be configured to provide a chip-select output.
1.2.3.44
PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general-purpose input or output pin. It can be configured as transmit pin TXD0 of the serial communication interface 0 (SCI0).
1.2.3.45
PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general-purpose input or output pin. It can be configured as receive pin RXD0 of the serial communication interface 0 (SCI0).
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1.2.3.46
PT7 / IOC7 / SCL1 — Port T I/O Pin 7
PT7 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC7 of the enhanced capture timer (ECT) or the serial clock pin SCL1 of the inter-IC bus interface 1 (IIC1).
1.2.3.47
PT6 / IOC6 / SDA1 — Port T I/O Pin 6
PT6 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC6 of the enhanced capture timer (ECT) or the serial data pin SDA1 of the inter-IC bus interface 1 (IIC1).
1.2.3.48
PT5 / IOC5 / SCL0 — Port T I/O Pin 5
PT5 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC5 of the enhanced capture timer (ECT) or the serial clock pin SCL0 of the inter-IC bus interface 0 (IIC0).
1.2.3.49
PT4 / IOC4 / SDA0 — Port T I/O Pin 4
PT4 is a general-purpose input or output pin. It can be configured as input capture or output compare pin IOC4 of the enhanced capture timer (ECT) or the serial data pin SDA0 of the inter-IC bus interface 0 (IIC0).
1.2.3.50
PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0]
PT3–PT0 are general-purpose input or output pins. They can be configured as input capture or output compare pins IOC3–IOC0 of the enhanced capture timer (ECT). They can be configured as frontplane segment driver outputs FP27–FP24 of the LCD module.
1.2.3.51
PU[7:4] / M1C1(SIN)P, M1C1(SIN)M, M1C0(COS)P, M1C0(COS)M — Port U I/O Pins [7:4]
PU7–PU4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 1.
1.2.3.52
PU[3:0] / M0C1(SIN)P, M0C1(SIN)M, M0C0(COS)P, M0C0(COS)M — Port U I/O Pins [3:0]
PU3–PU0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 0.
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1.2.3.53
PV[7:4] / M3C1(SIN)P, M3C1(SIN)M, M3C0(COS)P, M3C0(COS)M — Port V I/O Pins [7:4]
PV7–PV4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 3.
1.2.3.54
PV[3:0] / M2C1(SIN)P, M2C1(SIN)M, M2C0(COS)P, M2C0(COS)M — Port V I/O Pins [3:0]
PV3–PV0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 2.
1.2.3.55
PW[7:4] / M5C1(SIN)P, M5C1(SIN)M, M5C0(COS)P, M5C0(COS)M — Port W I/O Pins [7:4]
PW7–PW4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 5.
1.2.3.56
PW[3:0] / M4C1(SIN)P, M4C1(SIN)M, M4C0(COS)P, M4C0(COS)M — Port W I/O Pins [3:0]
PW3–PW0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 4.
1.2.4
Power Supply Pins
NOTE All VSS pins must be connected together in the application.
Power and ground pins are described below.
1.2.4.1
VDDR — External Power Pin
VDDR is the power supply pin for the internal voltage regulator.
1.2.4.2
VDDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. VDDX1 and VDDX2 as well as VSSX1 and VSSX2 are not internally connected.
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1.2.4.3
VDD1, VSS1, VSS2 — Internal Logic Power Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5-V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. VSS1 and VSS2 are internally connected.
1.2.4.4
VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground pins for the voltage regulator and the analog-to-digital converter.
1.2.4.5
VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the voltage reference pins for the analog-to-digital converter.
1.2.4.6
VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the oscillator and the phased-locked loop. This allows the supply voltage to the oscillator and PLL to be bypassed independently. This 2.5-V voltage is generated by the internal voltage regulator.
1.2.4.7
VDDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 3
VDDM1, VDDM2 and VDDM3 are the supply pins for the ports U, V and W. VDDM1, VDDM2 and VDDM3 are internally connected.
1.2.4.8
VSSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 3
VSSM1, VSSM2 and VSSM3 are the ground pins for the ports U, V and W. VSSM1, VSSM2 and VSSM3 are internally connected.
1.2.4.9
VLCD — Power Supply Reference Pin for LCD driver
VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the display contrast.
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1.3
System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-10 shows the clock connections from the CRG to all modules. Consult the CRG block description chapter for details on clock generation.
SSD0 . . SSD5
CAN0 & CAN1
IIC0 & IIC1
SCI0 & SCI1
MC
LCD
SPI
Bus Clock PIT EXTAL ECT CRG Oscillator Clock
XTAL Core Clock
PIM
RAM
S12X
XGATE
FLASH
EEPROM
Figure 1-10. Clock Connections
The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: • The on-chip phase locked loop (PLL) • the PLL self clocking • the oscillator The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure 1-10, this system clocks are used throughout the MCU to drive the core, the memories, and the peripherals.
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The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock.The oscillator clock is used as a time base to derive the program and erase times for the NVM’s. Consult the FTX512k4 and EETX4K block description chapters for more details on the operation of the NVM’s. The CAN modules may be configured to have their clock sources derived either from the bus clock or directly from the oscillator clock. This allows the user to select its clock based on the required jitter performance. Consult MSCAN block description for more details on the operation and configuration of the CAN blocks. In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more accurate check of the clock. The clock quality checker counts a predetermined number of clock edges within a defined time window to insure that the clock is running. The checker can be invoked following specific events such as on wake-up or clock monitor failure.
1.4
Chip Configuration Summary
The MCU can operate in six different modes. The different modes, the state of ROMCTL and EROMCTL signal on rising edge of RESET, and the security state of the MCU affects the following device characteristics: • External bus interface configuration • Flash in memory map, or not • Debug features enabled or disabled The operating mode out of reset is determined by the states of the MODC, MODB, and MODA signals during reset (see Table 1-7). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA signals are latched into these bits on the rising edge of RESET. In normal expanded mode and in emulation modes the ROMON bit and the EROMON bit in the MMCCTL1 register defines if the on chip flash memory is the memory map, or not. (See Table 1-7.) For a detailed description of the ROMON and EROMON bits refer to the S12X_MMC Bblock description chapter. The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MISC register on the rising edge of RESET.
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Table 1-7. Chip Modes and Data Sources
Chip Modes Normal single chip Special single chip Emulation single chip Normal expanded Emulation expanded BKGD = MODC 1 0 0 1 0 PE6 = MODB 0 0 0 0 1 PE5 = MODA 0 0 1 1 1 X X 0 1 0 1 1 Special test
1
PK7 = ROMCTL X
PE3 = EROMCTL X 0 1 X X X 0 1 X X
Data Source1 Internal Emulation memory Internal Flash External application Internal Flash External application Emulation memory Internal Flash External application Internal Flash
0
1
0
0 1
Internal means resources inside the MCU are read/written. Internal Flash means Flash resources inside the MCU are read/written. Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM, and register space are always considered internal). External application means resources residing outside the MCU are read/written.
The configuration of the oscillator can be selected using the XCLKS signal (see Table 1-8). For a detailed description please refer to the CRG block description chapter.
Table 1-8. Clock Selection Based on PE7
PE7 = XCLKS 0 1 Description Loop controlled Pierce oscillator selected Full swing Pierce oscillator or external clock source selected
1.5
1.5.1
1.5.1.1
Modes of Operation
User Modes
Normal Expanded Mode
Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus, and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the internal bus rate.
1.5.1.2
Normal Single-Chip Mode
There is no external bus in this mode. The processor program is executed from internal memory. Ports A, B,C,D, K, and most pins of port E are available as general-purpose I/O.
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1.5.1.3
Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external bus after reset in this mode.
1.5.1.4
Emulation of Expanded Mode
Developers use this mode for emulation systems in which the users target application is normal expanded mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.5
Emulation of Single-Chip Mode
Developers use this mode for emulation systems in which the user’s target application is normal single-chip mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.6
Special Test Mode
Freescale internal use only.
1.5.2
Low-Power Modes
The microcontroller features two main low-power modes. Consult the respective block description chapter for information on the module behavior in system stop, system pseudo stop, and system wait mode. An important source of information about the clock system is the Clock and Reset Generator (CRG) block description chapter.
1.5.2.1
System Stop Modes
The system stop modes are entered if the CPU executes the STOP instruction and the XGATE doesn’t execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to CRG block description chapter. Asserting RESET, XIRQ, IRQ or any other interrupt ends the system stop modes.
1.5.2.2
Pseudo Stop Mode
In this mode the clocks are stopped but the oscillator is still running and the real time interrupt (RTI) or watchdog (COP) submodule can stay active. Other peripherals are turned off. This mode consumes more current than the system stop mode, but the wake up time from this mode is significantly shorter.
1.5.2.3
Full Stop Mode
The oscillator is stopped in this mode. All clocks are switched off. All counters and dividers remain frozen.
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1.5.2.4
System Wait Mode
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in system wait mode. For further power consumption savings, the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that has not been masked ends system wait mode.
1.5.3
Freeze Mode
The enhanced capture timer, pulse width modulator, analog-to-digital converter, the periodic interrupt timer and the XGATE module provide a software programmable option to freeze the module status during the background debug module is active. This is useful when debugging application software. For detailed description of the behavior of the ATD, ECT, PWM, XGATE and PIT when the background debug module is active consult the corresponding module block description chapters.
1.6
Resets and Interrupts
Consult the S12XCPU block description chapter for information on exception processing.
1.6.1
Vectors
Table 1-9 lists all interrupt sources and vectors in the default order of priority. The interrupt module (S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each I-bit maskable service request is a configuration register. It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module.
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Table 1-9. Interrupt Vector Locations (Sheet 1 of 3)
Vector Address1 0xFFFE 0xFFFC 0xFFFA Vector base + 0xF8 Vector base+ 0xF6 Vector base+ 0xF4 Vector base+ 0xF2 Vector base+ 0xF0 Vector base+ 0xEE Vector base + 0xEC Vector base+ 0xEA Vector base+ 0xE8 Vector base+ 0xE6 Vector base+ 0xE4 Vector base + 0xE2 Vector base+ 0xE0 Vector base+ 0xDE Vector base+ 0xDC Vector base + 0xDA Vector base + 0xD8 Vector base+ 0xD6 Vector base + 0xD4 Vector base + 0xD2 Vector base + 0xD0 Vector base + 0xCE Vector base + 0xCC Vector base + 0xCA Vector base + 0xC8 Vector base + 0xC6 Vector base + 0xC4 Vector base + 0xC2 Vector base + 0xC0 Vector base + 0xBE XGATE Channel ID2 — — — — — — — 0x78 0x77 0x76 0x75 0x74 0x73 0x72 0x71 0x70 0x6F 0x6E 0x6D 0x6C 0x6B 0x6A 0x69 0x68 0x67 0x66 0x65 0x64 0x63 0x62 0x61 0x60 0x5F Interrupt Source System reset or illegal access reset Clock monitor reset COP watchdog reset Unimplemented instruction trap SWI XIRQ IRQ Real time interrupt Enhanced capture timer channel 0 Enhanced capture timer channel 1 Enhanced capture timer channel 2 Enhanced capture timer channel 3 Enhanced capture timer channel 4 Enhanced capture timer channel 5 Enhanced capture timer channel 6 Enhanced capture timer channel 7 Enhanced capture timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI SCI0 SCI1 ATD Reserved Port AD Reserved Modulus down counter underflow Pulse accumulator B overflow CRG PLL lock CRG self-clock mode Reserved IIC0 bus Reserved CCR Mask None None None None None X Bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit Local Enable None PLLCTL (CME, SCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSRC2 (TOF) PACTL (PAOVI) PACTL (PAI) SPCR1 (SPIE, SPTIE) SCI0CR2 (TIE, TCIE, RIE, ILIE) SCI1CR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) Reserved PIEAD (PIEAD7 - PIEAD0) Reserved MCCTL(MCZI) PBCTL(PBOVI) CRGINT(LOCKIE) CRGINT (SCMIE) Reserved IB0CR (IBIE) Reserved
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Table 1-9. Interrupt Vector Locations (Sheet 2 of 3)
Vector Address1 Vector base + 0xBC Vector base + 0xBA Vector base + 0xB8 Vector base + 0xB6 Vector base + 0xB4 Vector base + 0xB2 Vector base + 0xB0 Vector base + 0xAE Vector base + 0xAC Vector base + 0xAA Vector base + 0xA8 Vector base + 0xA6 Vector base + 0xA4 Vector base + 0xA2 Vector base + 0xA0 Vector base + 0x9E Vector base+ 0x9C Vector base+ 0x9A Vector base + 0x98 Vector base + 0x96 Vector base + 0x94 Vector base + 0x92 Vector base + 0x90 Vector base + 0x8E Vector base+ 0x8C Vector base + 0x8A Vector base + 0x88 Vector base + 0x86 Vector base + 0x84 Vector base + 0x82 Vector base + 0x80 Vector base + 0x7E Vector base + 0x7C Vector base + 0x7A XGATE Channel ID2 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57 0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D 0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D Interrupt Source Reserved EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit CAN1 wake-up CAN1 errors CAN1 receive CAN1 transmit Reserved Reserved SSD4 SSD0 SSD1 SSD2 SSD3 SSD5 Motor Control Timer Overflow Reserved Reserved Reserved Reserved PWM emergency shutdown Reserved Reserved Reserved Reserved IIC1 Bus Low-voltage interrupt (LVI) Autonomous periodical interrupt (API) Reserved Periodic interrupt timer channel 0 CCR Mask I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit Local Enable Reserved ECNFG (CCIE, CBEIE) FCNFG (CCIE, CBEIE) CAN0RIER (WUPIE) CAN0RIER (CSCIE, OVRIE) CAN0RIER (RXFIE) CAN0TIER (TXEIE[2:0]) CAN1RIER (WUPIE) CAN1RIER (CSCIE, OVRIE) CAN1RIER (RXFIE) CAN1TIER (TXEIE[2:0]) Reserved Reserved MDC4CTL (MCZIE, AOVIE) MDC0CTL (MCZIE, AOVIE) MDC1CTL (MCZIE, AOVIE) MDC2CTL (MCZIE, AOVIE) MDC3CTL (MCZIE, AOVIE) MDC5CTL (MCZIE, AOVIE) MCCTL1 (MCOCIE) Reserved Reserved Reserved Reserved PWMSDN (PWMIE) Reserved Reserved Reserved Reserved IB1CR (IBIE) VREGCTRL (LVIE) VREGAPICTRL (APIE) Reserved PITINTE (PINTE0)
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Table 1-9. Interrupt Vector Locations (Sheet 3 of 3)
Vector Address1 Vector base + 0x78 Vector base + 0x76 Vector base + 0x74 Vector base + 0x72 Vector base + 0x70 Vector base + 0x6E Vector base + 0x6C Vector base + 0x6A Vector base + 0x68 Vector base + 0x66 Vector base + 0x64 Vector base + 0x62 Vector base + 0x60 Vector base+ 0x12 to Vector base + 0x5E Vector base + 0x10
1 2
XGATE Channel ID2 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 — — — —
Interrupt Source Periodic interrupt timer channel 1 Periodic interrupt timer channel 2 Periodic interrupt timer channel 3 XGATE software trigger 0 XGATE software trigger 1 XGATE software trigger 2 XGATE software trigger 3 XGATE software trigger 4 XGATE software trigger 5 XGATE software trigger 6 XGATE software trigger 7 XGATE software error interrupt S12XCPU RAM access violation Reserved Spurious interrupt
CCR Mask I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit — —
Local Enable PITINTE (PINTE1) PITINTE (PINTE2) PITINTE (PINTE3) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) RAMWPC (AVIE) Reserved None
16 bits vector address based For detailed description of XGATE channel ID refer to XGATE block description chapter
1.6.2
Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module block description chapters for register reset states.
1.6.2.1
I/O Pins
Refer to the PIM block description chapter for reset configurations of all peripheral module ports.
1.6.2.2
Memory
The RAM array is not initialized out of reset.
1.7
COP Configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash control register FCTL (0x0107) located in the Flash EEPROM block. See Table 1-10 and Table 1-11 for coding. The FCTL register is loaded from the Flash configuration field byte at global address 0x7FFF0E during the reset sequence
MC9S12XHZ512 Data Sheet, Rev. 1.03 58 Freescale Semiconductor
Chapter 1 MC9S12XHZ Family Device Overview
NOTE If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP reset.
Table 1-10. Initial COP Rate Configuration
NV[2:0] in FCTL Register 000 001 010 011 100 101 110 111 CR[2:0] in COPCTL Register 111 110 101 100 011 010 001 000
Table 1-11. Initial WCOP Configuration
NV[3] in FCTL Register 1 0 WCOP in COPCTL Register 0 1
1.8
ATD External Trigger Input Connection
The ATD_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger feature allows the user to synchronize ATD conversion to external trigger events. Table 1-12 shows the connection of the external trigger inputs on MC9S12XHZ Family.
Table 1-12. ATD External Trigger Sources
External Trigger Input ETRIG0 ETRIG1 ETRIG2 ETRIG3 Connectivity Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger 0 Periodic interrupt timer hardware trigger 1
Consult the ATD_10B16C block description chapter for information about the analog-to-digital converter module.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 59
Chapter 1 MC9S12XHZ Family Device Overview
MC9S12XHZ512 Data Sheet, Rev. 1.03 60 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.1 lntroduction
The port integration module establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. This section covers: • Port A, B and K associated with S12X_EBI module and the LCD driver • Port C and D associated with S12X_EBI module • Port E associated with S12X_EBI module, the IRQ, XIRQ interrupt inputs, and the LCD driver • Port AD associated with ATD module (channels 7 through 0) and keyboard wake-up interrupts • Port L connected to the LCD driver and ATD (channels 15 through 8) modules • Port M connected to 2 CAN modules • Port P connected to 1 SCI, 2 IIC and PWM modules • Port S connected to 2 SCI and 1 SPI modules • Port T connected to 2 IIC, 1 ECT and LCD driver modules • Port U, V and W associated with PWM motor control and stepper stall detect modules Each I/O pin can be configured by several registers: input/output selection, drive strength reduction, enable and select of pull resistors, wired-or mode selection, interrupt enable, and/or status flags.
2.1.1
Features
A standard port has the following minimum features: • Input/output selection • 5-V output drive with two selectable drive strength (or slew rates) • 5-V digital and analog input • Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt input with glitch filtering
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 61
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.1.2
Block Diagram
Figure 2-1 is a block diagram of the S12XHZPIM
Port Integration Module
BKGD PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7
Single-Wire Background Debug Module
FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 XIRQ IRQ RW/WE LSTRB/LDS/EROMCTL ECLK MODA/TAGLO/RE MODB/TAGHI XCLKS/ECLKX2 ADDR16/IQSTAT0 ADDR17/IQSTAT1 ADDR18/IQSTAT2 ADDR19/IQSTAT3 ADDR20/ACC0 ADDR21/ACC1 ADDR22/ACC2 EWAIT/ROMCTL DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 FP20 FP21 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN8 AN9 Analog to AN10 Digital AN11 Converter AN12 AN13 AN14 AN15 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 KWAD0 KWAD1 KWAD2 KWAD3 KWAD4 KWAD5 KWAD6 KWAD7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 PV0 PV1 PV2 PV3 PV4 PV5 PV6 PV7 PW0 PW1 PW2 PW3 PW4 PW5 PW6 PW7 PM1 CS1 PM2 PM3 PM4 PM5 PS0 PS1 PS2 CS3 PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 CS0 PP7 CS2
DDRAD DDRU DDRV DDRW DDRM DDRP
SSD0
DDRK
PTK
FP22 BP0 BP1 BP2 BP3
SSD1
M0COSM M0COSP M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP M2COSM M2COSP M2SINM M2SINP M3COSM M3COSP M3SINM M3SINP M4COSM M4COSP M4SINM M4SINP M5COSM M5COSP M5SINM M5SINP
DDRE
PWM0 PWM1 PWM2 PWM3 PWM4
M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P
PTE
SSD2
FP23
SSD3 LCD Driver
Non-Multiplexed External Bus Interface
SSD4
DDRA
SPI
PW0 PW1 Pulse PW2 Width Modulator PW3 PW4 PW5 PW6 PW7
Module-to-Port-Routing
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7
FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP24 FP25 FP26 FP27 SDA0 SCL0 SDA1 SCL1
CAN0 TXCAN0 CAN1 TXCAN1 SCI0 SCI1
RXD0 TXD0 RXD1 TXD1 MISO MOSI SCK SS RXCAN1
DDRB
PTB
PTA
Enhanced Capture Timer
DDRT
PTT
IIC0 IIC1
SDA0 SCL0 SDA1 SCL1
Figure 2-1. S12XHZPIM Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 62 Freescale Semiconductor
PTP
DDRS PTS
PTM
DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
DDRC
PTC
SSD5
M2C0M M2C0P M2C1M PWM5 M2C1P M3C0M PWM6 M3C0P M3C1M PWM7 M3C1P M4C0M PWM8 M4C0P M4C1M PWM9 M4C1P M5C0M PWM10 M5C0P M5C1M PWM11 M5C1P
DDRD
PTD
RXCAN0
PTW
PTV
PTU
PTAD
DDRL
PTL
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.2
External Signal Description
This section lists and describes the signals that connect off chip. Table 2-1 shows all the pins and their functions that are controlled by the S12XHZPIM. The order in which the pin functions are listed represents the functions priority (top – highest priority, bottom – lowest priority).
Table 2-1. Detailed Signal Descriptions (Sheet 1 of 6)
Port — A Pin Name BKGD PA[7:0] Pin Function and Priority MODC BKGD ADDR[15:8] mux IVD[15:8] FP[15:8] GPIO ADDR[7:1] mux IVD[7:1] FP[7:1] GPIO ADDR0 mux IVD0 UDS FP[0] GPIO DATA[15:8] GPIO DATA[7:0] GPIO I/O I I/O O O I/O O O I/O O O O I/O I/O I/O I/O I/O Description MODC input during RESET S12X_BDM communication pin High-order external bus address output (multiplexed with IVIS data) LCD frontplane driver General-purpose I/O Low-order external bus address output (multiplexed with IVIS data) LCD frontplane driver General-purpose I/O Low-order external bus address output (multiplexed with IVIS data) Upper data strobe LCD frontplane driver General-purpose I/O High-order bidirectional data input/output Configurable for reduced input threshold General-purpose I/O Low-order bidirectional data input/output Configurable for reduced input threshold General-purpose I/O Pin Function after Reset BKGD Mode dependent
B
PB[7:1]
Mode dependent
PB[0]
C
PC[7:0]
Mode dependent
D
PD[7:0]
Mode dependent
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 63
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-1. Detailed Signal Descriptions (Sheet 2 of 6)
Port E Pin Name PE[7] Pin Function and Priority XCLKS ECLKX2 FP[22] GPIO MODB TAGHI GPIO MODA RE TAGLO GPIO ECLK GPIO EROMCTL LSTRB LDS FP[21] GPIO R/W WE FP[20] GPIO IRQ GPIO XIRQ GPIO ROMCTL EWAIT FP[23] GPIO ADDR[22:20] mux ACC[2:0] GPIO ADDR[19:16] mux IQSTAT[3:0] BP[3:0] GPIO AN[7:0] KWAD[7:0] GPIO I/O I O O I/O I I I/O I O I I/O O I/O I O O O I/O O O O I/O I I/O I I/O I I O I/O O I/O O O I/O I I I/O Description External clock selection input during RESET Free-running clock output at Core Clock rate (ECLK x 2) LCD frontplane driver General-purpose I/O MODB input during RESET Instruction tagging low pin Configurable for reduced input threshold General-purpose I/O MODA input during RESET Read enable signal Instruction tagging low pin Configurable for reduced input threshold General-purpose I/O Free-running clock output at the Bus Clock rate or programmable divided in normal modes General-purpose I/O EROMON bit control input during RESET Low strobe bar output Lower data strobe LCD frontplane driver General-purpose I/O Read/write output for external bus Write enable LCD frontplane driver General-purpose I/O Maskable level or falling edge-sensitive interrupt input General-purpose I/O Non-maskable level-sensitive interrupt input General-purpose I/O ROMON bit control input during RESET External Wait signal Configurable for reduced input threshold LCD frontplane driver General-purpose I/O Extended external bus address output (multiplexed with master access output) General-purpose I/O Extended external bus address output (multiplexed with instruction pipe status bits) LCD backplane driver General-purpose I/O Analog-to-digital converter input channel Keyboard wake-up interrupt General-purpose I/O Pin Function after Reset Mode dependent
PE[6]
PE[5]
PE[4]
PE[3]
PE[2]
PE[1] PE[0] K PK[7]
Mode dependent
PK[6:4]
PK[3:0]
AD
PAD[7:0]
GPIO
MC9S12XHZ512 Data Sheet, Rev. 1.03 64 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-1. Detailed Signal Descriptions (Sheet 3 of 6)
Port L Pin Name PL[7:4] Pin Function and Priority FP[31:28] AN[15:12] GPIO FP[19:16] AN[11:8] GPIO TXCAN1 GPIO RXCAN1 GPIO TXCAN0 GPIO RXCAN0 GPIO CS1 GPIO CS2 PWM7 SCL1 GPIO CS0 PWM6 SDA1 GPIO PWM5 SCL0 GPIO PWM4 SDA0 GPIO PWM3 GPIO PWM2 RXD1 GPIO PWM1 GPIO PWM0 TXD1 GPIO I/O O I I/O O I I/O O I/O I I/O O I/O I O O I/O O I/O I/O I/O O O I/O I/O I/O I/O I/O O I/O I/O O I/O O I I/O O I/O O O I/O Description LCD frontplane driver Analog-to-digital converter input channel General-purpose I/O LCD frontplane driver Analog-to-digital converter input channel General-purpose I/O MSCAN1 transmit pin General-purpose I/O MSCAN1 receive pin General-purpose I/O MSCAN0 transmit pin General-purpose I/O MSCAN0 receive pin General-purpose I/O Chip select 1 General-purpose I/O Chip select 2 Pulse-width modulator channel 7 and emergency shutdown input Inter-integrated circuit 1 serial clock line General-purpose I/O Chip select 0 Pulse-width modulator channel 6 Inter-integrated circuit 1 serial data line General-purpose I/O Pulse-width modulator channel 5 and emergency shutdown input Inter-integrated circuit 0 serial clock line General-purpose I/O Pulse-width modulator channel 4 Inter-integrated circuit 0 serial data line General-purpose I/O Pulse-width modulator channel 3 General-purpose I/O Pulse-width modulator channel 2 Serial communication interface 1 receive pin General-purpose I/O Pulse-width modulator channel 1 General-purpose I/O Pulse-width modulator channel 0 Serial communication interface 1 transmit pin General-purpose I/O Pin Function after Reset GPIO
PL[3:0]
M
PM[5] PM[4] PM[3] PM[2] PM[1]
GPIO
P
PP[7]
GPIO
PP[6]
PP[5]
PP[4]
PP[3] PP[2]
PP[1] PP[0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 65
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-1. Detailed Signal Descriptions (Sheet 4 of 6)
Port S Pin Name PS[7] Pin Function and Priority SS GPIO SCK GPIO MOSI GPIO MISO GPIO TXD1 GPIO CS3 RXD1 GPIO TXD0 GPIO RXD0 GPIO IOC7 SCL1 GPIO IOC7 SDA1 GPIO IOC5 SCL0 GPIO IOC4 SDA0 GPIO FP[27:24] IOC[3:0] GPIO I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O O I I/O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Serial peripheral interface slave select input/output in master mode, input in slave mode General-purpose I/O Serial peripheral interface serial clock pin General-purpose I/O Serial peripheral interface master out/slave in pin General-purpose I/O Serial peripheral interface master in/slave out pin General-purpose I/O Serial communication interface 1 transmit pin General-purpose I/O Chip select 3 Serial communication interface 1 receive pin General-purpose I/O Serial communication interface 0 transmit pin General-purpose I/O Serial communication interface 0 receive pin General-purpose I/O Timer channel Inter-integrated circuit 1 serial clock line General-purpose I/O Timer channel Inter-integrated circuit 1 serial data line General-purpose I/O Timer channel Inter-integrated circuit 0 serial clock line General-purpose I/O Timer channel Inter-integrated circuit 0 serial data line General-purpose I/O LCD frontplane driver Timer channel General-purpose I/O Pin Function after Reset GPIO
PS[6] PS[5] PS[4] PS[3] PS[2]
PS[1] PS[0] T PT[7]
GPIO
PT[6]
PT[5]
PT[4]
PT[3:0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 66 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-1. Detailed Signal Descriptions (Sheet 5 of 6)
Port U Pin Name PU[7] Pin Function and Priority M1SINP M1C1P GPIO M1SINM M1C1M GPIO M1COSP M1C0P GPIO M1COSM M1C0M GPIO M0SINP M0C1P GPIO M0SINM M0C1M GPIO M0COSP M0C0P GPIO M0COSM M0C0M GPIO M3SINP M3C1P GPIO M3SINM M3C1M GPIO M3COSP M3C0P GPIO M3COSM M3C0M GPIO M2SINP M2C1P GPIO M2SINM M2C1M GPIO M2COSP M2C0P GPIO M2COSM M2C0M GPIO I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O Description SSD1 Sine+ Node PWM motor controller channel 3 General-purpose I/O SSD1 Sine- Node PWM motor controller channel 3 General-purpose I/O SSD1 Cosine+ Node PWM motor controller channel 2 General-purpose I/O SSD1 Cosine- Node PWM motor controller channel 2 General-purpose I/O SSD0 Sine+ Node PWM motor controller channel 1 General-purpose I/O SSD0 Sine- Node PWM motor controller channel 1 General-purpose I/O SSD0 Cosine+ Node PWM motor controller channel 0 General-purpose I/O SSD0 Cosine- Node PWM motor controller channel 0 General-purpose I/O SSD3 sine+ node PWM motor controller channel 7 General-purpose I/O SSD3 sine- node PWM motor controller channel 7 General-purpose I/O SSD3 cosine+ node PWM motor controller channel 6 General-purpose I/O SSD3 cosine- node PWM motor controller channel 6 General-purpose I/O SSD2 sine+ node PWM motor controller channel 5 General-purpose I/O SSD2 sine- node PWM motor controller channel 5 General-purpose I/O SSD2 cosine+ node PWM motor controller channel 4 General-purpose I/O SSD2 cosine- node PWM motor controller channel 4 General-purpose I/O Pin Function after Reset GPIO
PU[6]
PU[5]
PU[4]
PU[3]
PU[2]
PU[1]
PU[0]
V
PV[7]
GPIO
PV[6]
PV[5]
PV[4]
PV[3]
PV[2]
PV[1]
PV[0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 67
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-1. Detailed Signal Descriptions (Sheet 6 of 6)
Port W Pin Name PW[7] Pin Function and Priority M5SINP M5C1P GPIO M5SINM M5C1M GPIO M5COSP M5C0P GPIO M5COSM M5C0M GPIO M4SINP M4C1P GPIO M4SINM M4C1M GPIO M4COSP M4C0P GPIO M4COSM M4C0M GPIO I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O O O I/O Description SSD5 sine+ node PWM motor controller channel 11 General-purpose I/O SSD5 sine- node PWM motor controller channel 11 General-purpose I/O SSD5 cosine+ node PWM motor controller channel 10 General-purpose I/O SSD5 cosine- node PWM motor controller channel 10 General-purpose I/O SSD4 sine+ node PWM motor controller channel 9 General-purpose I/O SSD4 sine- node PWM motor controller channel 9 General-purpose I/O SSD4 cosine+ node PWM motor controller channel 8 General-purpose I/O SSD4 cosine- node PWM motor controller channel 8 General-purpose I/O Pin Function after Reset GPIO
PW[6]
PW[5]
PW[4]
PW[3]
PW[2]
PW[1]
PW[0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 68 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3
Memory Map and Register Definition
This section provides a detailed description of all registers. Table 2-2 is a standard memory map of port integration module.
Table 2-2. S12XHZPIM Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A - 0x000B 0x000C 0x000D 0x000E - 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 - 0x0031 0x0032 0x0033 0x0034 - 0x01FF 0x0200 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 Port A I/O Register (PTA) Port B I/O Register (PTB) Port A Data Direction Register (DDRA) Port B Data Direction Register (DDRB) Port C I/O Register (PTC) Port D I/O Register (PTD) Port C Data Direction Register (DDRC) Port D Data Direction Register (DDRD) Port E I/O Register (PTE) Port E Data Direction Register (DDRE) Non-PIM address range Pull Up/Down Control Register (PUCR) Reduced Drive Register (RDRIV) Non-PIM address range ECLK Control Register (ECLKCR) Reserved IRQ Control Register (IRQCR) Slew Rate Control Register (SRCR) Non-PIM address range Port K I/O Register (PTK) Port K Data Direction Register (DDRK) Non-PIM address range Port T I/O Register (PTT) Port T Input Register (PTIT) Port T Data Direction Register (DDRT) Port T Reduced Drive Register (RDRT) Port T Pull Device Enable Register (PERT) Port T Polarity Select Register (PPST) Port T Wired-OR Mode Register (WOMT) Port T Slew Rate Register (SRRT) Use Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — R/W R/W — R/W — R/W R/W — R/W R/W — R/W R R/W R/W R/W R/W R/W R/W
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 69
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-2. S12XHZPIM Memory Map (continued)
Address Offset 0x0208 0x0209 0x020A 0x020B 0x020C 0x020D 0x020E 0x020F 0x0210 0x0211 0x0212 0x0213 0x0214 0x0215 0x0216 0x0217 0x0218 0x0219 0x021A 0x021B 0x021C 0x021D 0x021E 0x021F 0x0220 - 0x022F 0x0230 0x0231 0x0232 0x0233 0x0234 0x0235 0x0236 0x0237 0x0238 0x0239 0x023A 0x023B 0x023C 0x023D 0x023E - 0x023F Port S I/O Register (PTS) Port S Input Register (PTIS) Port S Data Direction Register (DDRS) Port S Reduced Drive Register (RDRS) Port S Pull Device Enable Register (PERS) Port S Polarity Select Register (PPSS) Port S Wired-OR Mode Register (WOMS) Port S Slew Rate Register (SRRS) Port M I/O Register (PTM) Port M Input Register (PTIM) Port M Data Direction Register (DDRM) Port M Reduced Drive Register (RDRM) Port M Pull Device Enable Register (PERM) Port M Polarity Select Register (PPSM) Port M Wired-OR Mode Register (WOMM) Port M Slew Rate Register (SRRM) Port P I/O Register (PTP) Port P Input Register (PTIP) Port P Data Direction Register (DDRP) Port P Reduced Drive Register (RDRP) Port P Pull Device Enable Register (PERP) Port P Polarity Select Register (PPSP) Port P Wired-OR Mode Register (WOMP) Port P Slew Rate Register (SRRP) Reserved Port L I/O Register (PTL) Port L Input Register (PTIL) Port L Data Direction Register (DDRL) Port L Reduced Drive Register (RDRL) Port L Pull Device Enable Register (PERL) Port L Polarity Select Register (PPSL) Reserved Port L Slew Rate Register (SRRL) Port U I/O Register (PTU) Port U Input Register (PTIU) Port U Data Direction Register (DDRU) Port U Slew Rate Register (SRRU) Port U Pull Device Enable Register (PERU) Port U Polarity Select Register (PPSU) Reserved MC9S12XHZ512 Data Sheet, Rev. 1.03 70 Freescale Semiconductor Use Access R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W — R/W R R/W R/W R/W R/W — R/W R/W R R/W R/W R/W R/W —
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-2. S12XHZPIM Memory Map (continued)
Address Offset 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 - 0x0247 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E - 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F 0x0260 - 0x027F Port V I/O Register (PTV) Port V Input Register (PTIV) Port V Data Direction Register (DDRV) Port V Slew Rate Register (SRRV) Port V Pull Device Enable Register (PERV) Port V Polarity Select Register (PPSV) Reserved Port W I/O Register (PTW) Port W Input Register (PTIW) Port W Data Direction Register (DDRW) Port W Slew Rate Register (SRRW) Port W Pull Device Enable Register (PERW) Port W Polarity Select Register (PPSW) Reserved Port AD I/O Register (PTAD) Reserved Port AD Input Register (PTIAD) Reserved Port AD Data Direction Register (DDRAD) Reserved Port AD Reduced Drive Register (RDRAD) Reserved Port AD Pull Device Enable Register (PERAD) Reserved Port AD Polarity Select Register (PPSAD) Reserved Port AD Interrupt Enable Register (PIEAD) Reserved Port AD Interrupt Flag Register (PIFAD) Reserved Use Access R/W R R/W R/W R/W R/W — R/W R R/W R/W R/W R/W — R/W — R — R/W — R/W — R/W — R/W — R/W — R/W —
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 71
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.1
Port A and Port B
Port A and port B are associated with the external address bus outputs ADDR15-ADDR0, the external read visibility IVD15-IVD0 and the liquid crystal display (LCD) driver. Each pin is assigned to these functions according to the following priority: LCD Driver > XEBI > general-purpose I/O. If the corresponding LCD frontplane drivers are enabled (and LCD module is enabled), the FP[15:0] outputs of the LCD module are available on port B and port A pins. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers.Refer to the S12X_EBI block description chapter for information on external bus. During reset, port A and port B pins are configured as inputs with pull down.
2.3.1.1
Port A I/O Register (PTA)
7 6 5 4 3 2 1 0
R PTA7 W XEBI: ADDR15 mux IVD15 FP15 0 ADDR14 mux IVD14 FP14 0 ADDR13 mux IVD13 FP13 0 ADDR12 mux IVD12 FP12 0 ADDR11 mux IVD11 FP11 0 ADDR10 mux IVD10 FP10 0 ADDR9 mux IVD9 FP9 0 ADDR8 mux IVD8 FP8 0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
LCD: Reset
Figure 2-2. Port A I/O Register (PTA)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRAx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRAx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTAx) reads “1”. If the associated data direction bit (DDRAx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 72 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.1.2
Port B I/O Register (PTB)
7 6 5 4 3 2 1 0
R PTB7 W XEBI: ADDR7 mux IVD7 FP7 0 ADDR6 mux IVD6 FP6 0 ADDR5 mux IVD5 FP5 0 ADDR4 mux IVD4 FP4 0 ADDR3 mux IVD3 FP3 0 ADDR2 mux IVD2 FP2 0 ADDR1 mux IVD1 FP1 0 ADDR0 mux IVD0 or UDS FP0 0 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
LCD: Reset
Figure 2-3. Port B I/O Register (PTB)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRBx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRBx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTBx) reads “1”. If the associated data direction bit (DDRBx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
2.3.1.3
Port A Data Direction Register (DDRA)
7 6 5 4 3 2 1 0
R DDRA7 W Reset 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Figure 2-4. Port A Data Direction Register (DDRA)
Read: Anytime. Write: Anytime. This register configures port pins PA[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-3. DDRA Field Descriptions
Field 7:0 DDRA[7:0] Data Direction Port A 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 73
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.1.4
Port B Data Direction Register (DDRB)
7 6 5 4 3 2 1 0
R DDRB7 W Reset 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Figure 2-5. Port B Data Direction Register (DDRB)
Read: Anytime. Write: Anytime. This register configures port pins PB[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-4. DDRB Field Descriptions
Field 7:0 DDRB[7:0] Data Direction Port B 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 74 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.2
Port C and Port D
Port C and port D pins can be used for either general-purpose I/O or the external data bus input/outputs DATA15-DATA0. Refer to the S12X_EBI block description chapter for information on external bus.
2.3.2.1
Port C I/O Register (PTC)
7 6 5 4 3 2 1 0
R PTC7 W XEBI: Reset DATA15 0 DATA14 0 DATA13 0 DATA12 0 DATA11 0 DATA10 0 DATA9 0 DATA8 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Figure 2-6. Port C I/O Register (PTC)
Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRCx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port C pin. If the data direction bit of the associated I/O pin (DDRCx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port C pin. If the associated data direction bit (DDRCx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRCx) is set to 0 (input), a read returns the value of the pin.
2.3.2.2
Port D I/O Register (PTD)
7 6 5 4 3 2 1 0
R PTD7 W XEBI: Reset DATA7 0 DATA6 0 DATA5 0 DATA4 0 DATA3 0 DATA2 0 DATA1 0 DATA0 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Figure 2-7. Port D I/O Register (PTD)
Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRDx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port D pin. If the data direction bit of the associated I/O pin (DDRDx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port D pin. If the associated data direction bit (DDRDx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRDx) is set to 0 (input), a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 75
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.2.3
Port C Data Direction Register (DDRC)
7 6 5 4 3 2 1 0
R DDRC7 W Reset 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Figure 2-8. Port C Data Direction Register (DDRC)
Read: Anytime. Write: Anytime. This register configures port pins PC[7:0] as either input or output.
Table 2-5. DDRC Field Descriptions
Field 7:0 DDRC[7:0] Data Direction Port C 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
2.3.2.4
Port D Data Direction Register (DDRD)
7 6 5 4 3 2 1 0
R DDRD7 W Reset 0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Figure 2-9. Port D Data Direction Register (DDRD)
Read: Anytime. Write: Anytime. This register configures port pins PD[7:0] as either input or output.
Table 2-6. DDRD Field Descriptions
Field 7:0 DDRD[7:0] Data Direction Port D 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 76 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.3
Port E
Port E pins can be used for either general-purpose I/O, or the liquid crystal display (LCD) driver, or the external bus control outputs R/W, WE, LSTRB, LDS and RE, the free running clock outputs ECLK and ECLKX2, or the inputs TAGHI, TAGLO, MODA, MODB, EROMCTL, XCLKS and interrupts IRQ and XIRQ. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to the S12X_EBI block description chapter for information on external bus. Port E pin PE[7] can be used for either general-purpose I/O, or as the free-running clock ECLKX2 output running at the core clock rate, or the frontplane driver FP22. The clock ECLKX2 output is always enabled in emulation modes. Port E pin PE[4] can be used for either general-purpose I/O or as the free-running clock ECLK output running at the bus clock rate or at the programmed divided clock rate. The clock output is always enabled in emulation modes. Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt inpu. IRQ will be enabled by setting the IRQEN configuration bit and clearing the I-bit in the CPU’s condition code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up.
2.3.3.1
Port E I/O Register (PTE)
7 6 5 4 3 2 1 0
R PTE7 W XEBI: XCLKS1 or ECLKX2 MODB1 or TAGHI MODA1 or TAGLO or RE EROMCTL1 or LSTRB or LDS FP21 0 0 0 0 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
ECLK
R/W or WE FP20 0
IRQ
XIRQ
LCD: Reset
FP22 0
—2
—2
Figure 2-10. Port E I/O Register (PTE)
1 2
Function active when RESET asserted. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values.
Read: Anytime. Write: Anytime. If the associated data direction bit (DDREx) is set to 1 (output), a read returns the value of the I/O register bit.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 77
Chapter 2 Port Integration Module (S12XHZPIMV1)
If the associated data direction bit (DDREx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTEx) reads “1”. If the associated data direction bit (DDREx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
2.3.3.2
Port E Data Direction Register (DDRE)
7 6 5 4 3 2 1 0
R DDRE7 W Reset 0 0 0 0 0 0 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2
0
0
0
0
= Reserved or Unimplemented
Figure 2-11. Port E Data Direction Register (DDRE)
Read: Anytime. Write: Anytime. This register configures port pins PE[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-7. DDRE Field Descriptions
Field 7:2 DDRE[7:2] Data Direction Port E 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 78 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.4
Port K
Port K pins can be used for either general-purpose I/O, or the liquid crystal display (LCD) driver, or the external address bus outputs ADDR22-ADDR16 muxed with master access output ACC2-ACC0 and instruction pipe signals IQSTAT3-IQSTAT0, or inputs EWAIT and ROMCTL. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to the S12X_EBI block description chapter for information on external bus.
2.3.4.1
Port K I/O Register (PTK)
7 6 5 4 3 2 1 0
R PTK7 W XEBI: ROMCTL1 or EWAIT FP23 0 0 0 0 ADDR22 or ACC2 ADDR21 or ACC1 ADDR20 or ACC0 ADDR19 or IQSTAT3 BP3 0 ADDR18 or IQSTAT2 BP2 0 ADDR17 or IQSTAT1 BP1 0 ADDR16 or IQSTAT0 BP0 0 PTK6 PTK5 PTK4 PTK3 PTK2 PTK1 PTK0
LCD: Reset
Figure 2-12. Port K I/O Register (PTK)
1
Function active when RESET asserted.
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRKx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRKx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTKx) reads “1”. If the associated data direction bit (DDRKx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
2.3.4.2
Port K Data Direction Register (DDRK)
7 6 5 4 3 2 1 0
R DDRK7 W Reset 0 0 0 0 0 0 0 0 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0
Figure 2-13. Port K Data Direction Register (DDRK)
Read: Anytime. Write: Anytime. This register configures port pins PK[7:0] as either input or output.If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 79
Chapter 2 Port Integration Module (S12XHZPIMV1)
Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-8. DDRK Field Descriptions
Field 7:0 DDRK[7:0] Data Direction Port K 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 80 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.5
2.3.5.1
Miscellaneous registers
Pull Up/Down Control Register (PUCR)
7 6 5 4 3 2 1 0
R PUPKE W Reset 1 1 BKGPE
0 PUPEE 0 1 PUPDE 0 PUPCE 0 PUPBE 1 PUPAE 1
Figure 2-14. Pull Up/Down Control Register (PUCR)
Read: Anytime. Write: Anytime except BKPUE which is writable in special test mode only. This register is used to enable pull up/down devices for the associated ports A, B, C, D, E and K. Pull up/down devices are assigned on a per-port basis and apply to any pin in the corresponding port currently configured as an input.
Table 2-9. PUCR Field Descriptions
Field 7 PUPKE 6 BKPUE 4 PUPEE Description Pull-down Port K Enable 0 Port K pull-down devices are disabled. 1 Enable pull-down devices for Port K input pins. BKGD Pin Pull-up Enable 0 BKGD pull-up device is disabled. 1 Enable pull-up device on BKGD pin. Pull Port E Enable 0 Port E pull-down devices on pins 7, 4–2 are disabled. Port E pull-up devices on pins 1–0 are disabled. 1 Enable pull-down devices for Port E input pins 7, 4–2. Enable pull-up devices for Port E input pins 1–0. Note: Bits 5 and 6 of Port E have pull-down devices which are only enabled during reset. This bit has no effect on these pins. Pull-up Port D Enable 0 Port D pull-up devices are disabled. 1 Enable pull-up devices for all Port D input pins. Pull-up Port C Enable 0 Port C pull-up devices are disabled. 1 Enable pull-up devices for all Port C. Pull-down Port B Enable 0 Port B pull-down devices are disabled. 1 Enable pull-down devices for all Port B input pins. Pull-down Port A Enable 0 Port A pull-down devices are disabled. 1 Enable pull-down devices for all Port A input pins.
3 PUPDE 2 PUPCE 1 PUPBE 0 PUPAE
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 81
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.5.2
Reduced Drive Register (RDRIV)
7 6 5 4 3 2 1 0
R RDPK W Reset 0
0
0 RDPE RDPD 0 RDPC 0 RDPB 0 RDPA 0
0
0
0
= Reserved or Unimplemented
Figure 2-15. Reduced Drive Register (RDRIV)
Read: Anytime. Write: Anytime. This register is used to select reduced drive for the pins associated with ports A, B, C, D, E, and K. If enabled, the pins drive at about 1/6 of the full drive strength. The reduced drive function is independent of which function is being used on a particular pin. The reduced drive functionality does not take effect on the pins in emulation modes.
Table 2-10. RDRIV Field Descriptions
Field 7 RDPK 4 RDPE 3 RDPD 2 RDPC 1 RDPB 0 RDPA Description Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. Reduced Drive of Port D 0 All port D output pins have full drive enabled. 1 All port D output pins have reduced drive enabled. Reduced Drive of Port C 0 All Port C output pins have full drive enabled. 1 All port C output pins have reduced drive enabled. Reduced Drive of Port B 0 All port B output pins have full drive enabled. 1 All port B output pins have reduced drive enabled. Reduced Drive of Port A 0 All Port A output pins have full drive enabled. 1 All port A output pins have reduced drive enabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 82 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.5.3
ECLK Control Register (ECLKCR)
7 6 5 4 3 2 1 0
R NECLK W Reset 01 1 NCLKX2
0
0
0
0 EDIV1 EDIV0 0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-16. ECLK Control Register (ECLKCR)
1
NECLK reset value is 1 in emulation single-chip and normal single-chip modes.
Read: Anytime. Write: Anytime. The ECLKCTL register is used to control the availability of the free-running clocks and the free-running clock divider.
Table 2-11. ECLKCTL Field Descriptions
Field 7 NECLK Description No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always active in emulation modes and if enabled in all other operating modes. 0 ECLK enabled 1 ECLK disabled No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other operating modes. 0 ECLKX2 is enabled 1 ECLKX2 is disabled Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pinr. The usage of the bits is shown in Table 2-12. Divider is always disabled in emulation modes and active as programmed in all other operating modes.
6 NCLKX2
1–0 EDIV[1:0]
Table 2-12. Free-Running ECLK Clock Rate
EDIV[1:0] 00 01 10 11 Rate of Free-Running ECLK ECLK = Bus clock rate ECLK = Bus clock rate divided by 2 ECLK = Bus clock rate divided by 3 ECLK = Bus clock rate divided by 4
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 83
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.5.4
IRQ Control Register (IRQCR)
7 6 5 4 3 2 1 0
R IRQE W Reset 0 1 IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-17. Port E Data Direction Register (DDRE)
Read: See individual bit descriptions below. Write: See individual bit descriptions below.
Table 2-13. IRQCR Field Descriptions
Field 7 IRQE Description IRQ Select Edge Sensitive Only Special modes: Read or write anytime. Normal and emulation modes: Read anytime, write once. 0 IRQ configured for low level recognition. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1. The edge detector is cleared only upon the servicing of the IRQ interrupt or a reset . External IRQ Enable Read or write anytime. 0 External IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic.
6 IRQEN
MC9S12XHZ512 Data Sheet, Rev. 1.03 84 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.5.5
Slew Rate Control Register (SRCR)
7 6 5 4 3 2 1 0
R SRRK W Reset 0
0
0 SRRE SRRD 0 SRRC 0 SRRB 0 SRRA 0
0
0
0
= Reserved or Unimplemented
Figure 2-18. Slew Rate Control Register (SRCR)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for the pins associated with ports A, B, C, D, E, and K.
Table 2-14. SRCR Field Descriptions
Field 7 SRRK 4 SRRE 3 SRRD 2 SRRC 1 SRRB 0 SRRA Description Slew Rate of Port K 0 Disables slew rate control and enables digital input buffer for all port K pins. 1 Enables slew rate control and disables digital input buffer for all port K pins. Slew Rate of Port E 0 Disables slew rate control and enables digital input buffer for all port E pins. 1 Enables slew rate control and disables digital input buffer for all port E pins. Slew Rate of Port D 0 Disables slew rate control and enables digital input buffer for all port D pins. 1 Enables slew rate control and disables digital input buffer for all port D pins. Slew Rate of Port C 0 Disables slew rate control and enables digital input buffer for all port C pins. 1 Enables slew rate control and disables digital input buffer for all port C pins. Slew Rate of Port B 0 Disables slew rate control and enables digital input buffer for all port B pins. 1 Enables slew rate control and disables digital input buffer for all port B pins. Slew Rate of Port A 0 Disables slew rate control and enables digital input buffer for all port A pins. 1 Enables slew rate control and disables digital input buffer for all port A pins.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 85
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.6
Port AD
Port AD is associated with the analog-to-digital converter (ATD) and keyboard wake-up (KWU) interrupts . Each pin is assigned to these modules according to the following priority: ATD > KWU > general-purpose I/O. For the pins of port AD to be used as inputs, the corresponding bits of the ATDDIEN1 register in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN1 register does not affect the port AD pins when they are configured as outputs. Refer to the ATD block description chapter for information on the ATDDIEN1 register. During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is disabled).
2.3.6.1
Port AD I/O Register (PTAD)
7 6 5 4 3 2 1 0
R PTAD7 W KWU: ATD: Reset KWAD7 AN7 0 KWAD6 AN6 0 KWAD5 AN55 0 KWAD4 AN4 0 KWAD3 AN3 0 KWAD2 AN2 0 KWAD1 AN1 0 KWAD0 AN0 0 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
Figure 2-19. Port AD I/O Register (PTAD)
Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port AD pin. If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads “1”. If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set to 1 (digital input buffer is enabled), a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 86 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.6.2
Port AD Input Register (PTIAD)
7 6 5 4 3 2 1 0
R W Reset
PTIAD7
PTIAD6
PTIAD5
PTIAD4
PTIAD3
PTIAD2
PTIAD1
PTIAD0
1
1
1
1
1
1
1
1
= Reserved or Unimplemented
Figure 2-20. Port AD Input Register (PTIAD)
Read: Anytime. Write: Never; writes to these registers have no effect. If the ATDDIEN1 bit of the associated I/O pin is set to 0 (digital input buffer is disabled), a read returns a 1. If the ATDDIEN1 bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin.
2.3.6.3
Port AD Data Direction Register (DDRAD)
7 6 5 4 3 2 1 0
R DDRAD7 W Reset 0 0 0 0 0 0 0 0 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0
Figure 2-21. Port AD Data Direction Register (DDRAD)
Read: Anytime. Write: Anytime. This register configures port pins PAD[7:0] as either input or output. If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated ATDDIEN1 bit. If the associated ATDDIEN1 bit is set to 1 (digital input buffer is enabled), a read on PTADx returns the value on port AD pin. If the associated ATDDIEN1 bit is set to 0 (digital input buffer is disabled), a read on PTADx returns a 1.
Table 2-15. DDRAD Field Descriptions
Field 7:0 Data Direction Port AD DDRAD[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 87
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.6.4
Port AD Reduced Drive Register (RDRAD)
7 6 5 4 3 2 1 0
R RDRAD7 W Reset 0 0 0 0 0 0 0 0 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
Figure 2-22. Port AD Reduced Drive Register (RDRAD)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-16. RDRAD Field Descriptions
Field Description
7:0 Reduced Drive Port A RDRAD[7:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.6.5
Port AD Pull Device Enable Register (PERAD)
7 6 5 4 3 2 1 0
R PERAD7 W Reset 0 0 0 0 0 0 0 0 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0
Figure 2-23. Port AD Pull Device Enable Register (PERAD)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-17. PERAD Field Descriptions
Field 7:0 Pull Device Enable Port AD PERAD[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 88 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.6.6
Port AD Polarity Select Register (PPSAD)
7 6 5 4 3 2 1 0
R PPSAD7 W Reset 0 0 0 0 0 0 0 0 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0
Figure 2-24. Port AD Polarity Select Register (PPSAD)
Read: Anytime. Write: Anytime. The Port AD Polarity Select Register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled (PERADx = 1). The Port AD Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input). In pull-down mode (PPSADx = 1), a rising edge on a port AD pin sets the corresponding PIFADx bit. In pull-up mode (PPSADx = 0), a falling edge on a port AD pin sets the corresponding PIFADx bit.
Table 2-18. PPSAD Field Descriptions
Field Description
7:0 Polarity Select Port AD PPSAD[7:0] 0 A pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation. 1 A pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt generation.
2.3.6.7
Port AD Interrupt Enable Register (PIEAD)
7 6 5 4 3 2 1 0
R PIEAD7 W Reset 0 0 0 0 0 0 0 0 PIEAD6 PIEAD5 PIEAD4 PIEAD3 PIEAD2 PIEAD1 PIEAD0
Figure 2-25. Port AD Interrupt Enable Register (PIEAD)
Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port AD.
Table 2-19. PIEAD Field Descriptions
Field 7:0 PIEAD[7:0] Interrupt Enable Port AD 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 89
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.6.8
Port AD Interrupt Flag Register (PIFAD)
7 6 5 4 3 2 1 0
R PIFAD7 W Reset 0 0 0 0 0 0 0 0 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 PIFAD0
Figure 2-26. Port AD Interrupt Flag Register (PIFAD)
Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. The active edge could be rising or falling based on the state of the corresponding PPSADx bit. To clear each flag, write “1” to the corresponding PIFADx bit. Writing a “0” has no effect. NOTE If the ATDDIEN1 bit of the associated pin is set to 0 (digital input buffer is disabled), active edges can not be detected.
Table 2-20. PIFAD Field Descriptions
Field 7:0 PIFAD[7:0] Description Interrupt Flags Port AD 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag.
MC9S12XHZ512 Data Sheet, Rev. 1.03 90 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.7
Port L
Port L is associated with the analog-to-digital converter (ATD) and the liquid crystal display (LCD) driver. If the ATD module is enabled, the AN[15:8] inputs of ATD module are available on port L pins PL[7:0]. If the corresponding LCD frontplane drivers are enabled, the FP[31:28] and FP[19:16] outputs of LCD module are available on port L pins PL[7:0] and the general purpose I/Os are disabled. For the pins of port L to be used as inputs, the corresponding LCD frontplane drivers must be disabled and the associated ATDDIEN0 register in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN0 register does not affect the port L pins when they are configured as outputs. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to the ATD block description chapter for information on the ATDDIEN0 register. During reset, port L pins are configured as inputs with pull down.
2.3.7.1
Port L I/O Register (PTL)
7 6 5 4 3 2 1 0
R PTL7 W ATD: LCD: Reset AN15 1 0 AN14 1 0 AN13 1 0 AN12 1 0 AN11 1 0 AN10 1 0 AN9 1 0 AN8 1 0 PTL6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0
Figure 2-27. Port L I/O Register (PTL)
Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRLx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port L pin. If the data direction bit of the associated I/O pin (DDRLx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port L pin. If the associated data direction bit (DDRLx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRLx) is set to 0 (input) and the associated ATDDIEN0 bits is set to 0 (digital input buffer is disabled), the associated I/O register bit (PTLx) reads “1”. If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTLx) reads “1”. If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 91
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.7.2
Port L Input Register (PTIL)
7 6 5 4 3 2 1 0
R W Reset
PTIL7
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
1
1
1
1
1
1
1
1
= Reserved or Unimplemented
Figure 2-28. Port L Input Register (PTIL)
Read: Anytime. Write: Never, writes to this register have no effect. If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled) or the associated ATDDIEN0 bit is set to 0 (digital input buffer is disabled), a read returns a 1. If the LCD frontplane driver of an associated I/O pin is disabled (or LCD module is disabled) and the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin.
2.3.7.3
Port L Data Direction Register (DDRL)
7 6 5 4 3 2 1 0
R DDRL7 W Reset 0 0 0 0 0 0 0 0 DDRL6 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0
Figure 2-29. Port L Data Direction Register (DDRL)
Read: Anytime. Write: Anytime. This register configures port pins PL[7:0] as either input or output. If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-21. DDRL Field Descriptions
Field 7:0 DDRL[7:0] Data Direction Port L 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 92 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.7.4
Port L Reduced Drive Register (RDRL)
7 6 5 4 3 2 1 0
R RDRL7 W Reset 0 0 0 0 0 0 0 0 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0
Figure 2-30. Port L Reduced Drive Register (RDRL)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-22. RDRL Field Descriptions
Field 7:0 RDRL[7:0] Description Reduced Drive Port L 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.7.5
Port L Pull Device Enable Register (PERL)
7 6 5 4 3 2 1 0
R PERL7 W Reset 1 1 1 1 1 1 1 1 PERL6 PERL5 PERL4 PERL3 PERL2 PERL1 PERL0
Figure 2-31. Port L Pull Device Enable Register (PERL)
Read:Anytime. Write:Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-23. PERL Field Descriptions
Field 7:0 PERL[7:0] Pull Device Enable Port L 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 93
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.7.6
Port L Polarity Select Register (PPSL)
7 6 5 4 3 2 1 0
R PPSL7 W Reset 1 1 1 1 1 1 1 1 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0
Figure 2-32. Port L Polarity Select Register (PPSL)
Read: Anytime. Write: Anytime. The Port L Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port L Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 2-24. PPSL Field Descriptions
Field 7:0 PPSL[7:0] Description Pull Select Port L 0 A pull-up device is connected to the associated port L pin. 1 A pull-down device is connected to the associated port L pin.
2.3.7.7
Port L Slew Rate Register (SRRL)
7 6 5 4 3 2 1 0
R SRRL7 W Reset 0 0 0 0 0 0 0 0 SRRL6 SRRL5 SRRL4 SRRL3 SRRL2 SRRL1 SRRL0
Figure 2-33. Port L Slew Rate Register (SRRL)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PL[7:0].
Table 2-25. SRRL Field Descriptions
Field 7:0 SRRL[7:0] Description Slew Rate Port L 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.03 94 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.8
Port M
Port M is associated with the chip select 1 and the Freescale’s scalable controller area network (CAN1 and CAN0) modules. Each pin is assigned to these modules according to the following priority: CS1/CAN1/CAN0 > general-purpose I/O. When the CAN1 module is enabled, PM[5:4] pins become TXCAN1 (transmitter) and RXCAN1 (receiver) pins for the CAN1 module. When the CAN0 module is enabled, PM[3:2] pins become TXCAN0 (transmitter) and RXCAN0 (receiver) pins for the CAN0 module. Refer to the MSCAN block description chapter for information on enabling and disabling the CAN module. During reset, port M pins are configured as high-impedance inputs.
2.3.8.1
Port M I/O Register (PTM)
7 6 5 4 3 2 1 0
R W CAN0/CAN1: Chip Select: Reset
0
0 PTM5 PTM4 PTM3 PTM2 PTM1
0
TXCAN1
RXCAN1
TXCAN0
RXCAN0 CS1
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-34. Port M I/O Register (PTM)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.
2.3.8.2
Port M Input Register (PTIM)
7 6 5 4 3 2 1 0
R W Reset
0
0
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
0
0
0
u
u
u
u
u
0
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-35. Port M Input Register (PTIM)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 95
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.8.3
Port M Data Direction Register (DDRM)
7 6 5 4 3 2 1 0
R W Reset
0
0 DDRM5 DDRM4 0 DDRM3 0 DDRM2 0 DDRM1 0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-36. Port M Data Direction Register (DDRM)
Read: Anytime. Write: Anytime. This register configures port pins PM[5:1] as either input or output. When a CAN module is enabled, the corresponding transmitter (TXCANx) pin becomes an output, the corresponding receiver (RXCANx) pin becomes an input, and the associated Data Direction Register bits have no effect. If a CAN module is disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-26. DDRM Field Descriptions
Field 5:1 DDRM[5:1] Data Direction Port M 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
2.3.8.4
Port M Reduced Drive Register (RDRM)
7 6 5 4 3 2 1 0
R W Reset
0
0 RDRM5 RDRM4 0 RDRM3 0 RDRM2 0 RDRM1 0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-37. Port M Reduced Drive Register (RDRM)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-27. RDRM Field Descriptions
Field 5:1 RDRM[5:1] Description Reduced Drive Port M 0 Full drive strength at output 1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12XHZ512 Data Sheet, Rev. 1.03 96 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.8.5
Port M Pull Device Enable Register (PERM)
7 6 5 4 3 2 1 0
R W Reset
0
0 PERM5 PERM4 0 PERM3 0 PERM2 0 PERM1 0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-38. Port M Pull Device Enable Register (PERM)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-28. PERM Field Descriptions
Field 5:1 PERM[5:1] Pull Device Enable Port M 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
2.3.8.6
Port M Polarity Select Register (PPSM)
7 6 5 4 3 2 1 0
R W Reset
0
0 PPSM5 PPSM4 0 PPSM3 0 PPSM2 0 PPSM1 0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-39. Port M Polarity Select Register (PPSM)
Read: Anytime. Write: Anytime. The Port M Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port M Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. If a CAN module is enabled, a pull-up device can be activated on the receiver pin, and on the transmitter pin if the corresponding wired-OR mode bit is set. Pull-down devices can not be activated on CAN pins.
Table 2-29. PPSM Field Descriptions
Field 5:1 PPSM[5:1] Description Pull Select Port M 0 A pull-up device is connected to the associated port M pin. 1 A pull-down device is connected to the associated port M pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 97
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.8.7
Port M Wired-OR Mode Register (WOMM)
7 6 5 4 3 2 1 0
R W Reset
0
0 WOMM5 WOMM4 0 WOMM3 0 WOMM2 0 WOMM1 0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-40. Port M Wired-OR Mode Register (WOMM)
Read: Anytime. Write: Anytime. This register selects whether a port M output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. These bits apply also to the CAN transmitter and allow a multipoint connection of several serial modules.
Table 2-30. WOMM Field Descriptions
Field 5:1 Wired-OR Mode Port M WOMM[5:1] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
2.3.8.8
Port M Slew Rate Register (SRRM)
7 6 5 4 3 2 1 0
R W Reset
0
0 SRRM5 SRRM4 0 SRRM3 0 SRRM2 0 SRRM1 0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-41. Port M Slew Rate Register (SRRM)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PM[5:1].
Table 2-31. SRRM Field Descriptions
Field 5:1 SRRM[5:1] Description Slew Rate Port M 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.03 98 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.9
Port P
Port P is associated with the chip selects 0 and 2, the Pulse Width Modulator (PWM), the serial communication interface (SCI1) and the Inter-IC bus (IIC0 and IIC1) modules. Each pin is assigned to these modules according to the following priority: CS0/CS2 > PWM > SCI1/IIC1/IIC0 > general-purpose I/O. When a PWM channel is enabled, the corresponding pin becomes a PWM output with the exception of PP[5] which can be PWM input or output. Refer to the PWM block description chapter for information on enabling and disabling the PWM channels. When the IIC1 module is enabled and MODRR1 is clear, PP[7:6] pins become SCL1 and SDA1 respectively as long as the corresponding PWM channels are disabled. When the IIC0 module is enabled and MODRR0 is clear, PP[5:4] pins become SCL0 and SDA0 respectively as long as the corresponding PWM channels are disabled. Refer to the IIC block description chapter for information on enabling and disabling the IIC bus. When the SCI1 receiver and transmitter are enabled and MODRR2 is clear, the PP[2] and PP[0] pins become RXD1 and TXD1 respectively as long as the corresponding PWM channels are disabled. Refer to the SCI block description chapter for information on enabling and disabling the SCI receiver and transmitter. During reset, port P pins are configured as high-impedance inputs.
2.3.9.1
Port P I/O Register (PTP)
7 6 5 4 3 2 1 0
R PTP7 W SCI1/ IIC1/IIC0: PWM: Chip Select: Reset PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
SCL1 PWM7 CS2
0
SDA1 PWM6 CS0
0
SCL0 PWM5
SDA0 PWM4 PWM3
RXD1 PWM2 PWM1
TXD1 PWM0
0
0
0
0
0
0
Figure 2-42. Port P I/O Register (PTP)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRPx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRPx) is set to 0 (input), a read returns the value of the pin. The PWM function takes precedence over the general-purpose I/O function if the associated PWM channel is enabled. The PWM channels 6-0 are outputs if the respective channels are enabled. PWM channel 7 can be an output, or an input if the shutdown feature is enabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 99
Chapter 2 Port Integration Module (S12XHZPIMV1)
The IIC function takes precedence over the general-purpose I/O function if the IIC bus is enabled and the corresponding PWM channels remain disabled. The SDA and SCL pins are bidirectional with outputs configured as open-drain. If enabled, the SCI1 transmitter takes precedence over the general-purpose I/O function, and the corresponding TXD1 pin is configured as an output. If enabled, the SCI1 receiver takes precedence over the general-purpose I/O function, and the corresponding RXD1 pin is configured as an input.
2.3.9.2
Port P Input Register (PTIP)
7 6 5 4 3 2 1 0
R W Reset
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-43. Port P I/O Register (PTP)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.
2.3.9.3
Port P Data Direction Register (DDRP)
7 6 5 4 3 2 1 0
R DDRP7 W Reset 0 0 0 0 0 0 0 0 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Figure 2-44. Port P Data Direction Register (DDRP)
Read: Anytime. Write: Anytime. This register configures port pins PP[7:0] as either input or output. If a PWM channel is enabled, the corresponding pin is forced to be an output and the associated Data Direction Register bit has no effect. Channel 5 can also force the corresponding pin to be an input if the shutdown feature is enabled. When an IIC bus is enabled, the corresponding pins become the SCL and SDA bidirectional pins respectively as long as the corresponding PWM channels are disabled. The associated Data Direction Register bits have no effect. When the SCI1 transmitter is enabled, the PP[0] pin becomes the TXD1 output pin and the associated Data Direction Register bit has no effect. When the SCI1 receiver is enabled, the PP[2] pin becomes the RXD1 input pin and the associated Data Direction Register bit has no effect.
MC9S12XHZ512 Data Sheet, Rev. 1.03 100 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
If the PWM, IIC0, IIC1 and SCI1 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-32. DDRP Field Descriptions
Field 7:0 DDRP[7:0] Data Direction Port P 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
2.3.9.4
Port P Reduced Drive Register (RDRP)
7 6 5 4 3 2 1 0
R RDRP7 W Reset 0 0 0 0 0 0 0 0 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Figure 2-45. Port P Reduced Drive Register (RDRP)
Read:Anytime. Write:Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-33. RDRP Field Descriptions
Field 7:0 RDRP[7:0] Description Reduced Drive Port P 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 101
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.9.5
Port P Pull Device Enable Register (PERP)
7 6 5 4 3 2 1 0
R PERP7 W Reset 0 0 0 0 0 0 0 0 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
Figure 2-46. Port P Pull Device Enable Register (PERP)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-34. PERP Field Descriptions
Field 7:0 PERP[7:0] Pull Device Enable Port P 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
2.3.9.6
Port P Polarity Select Register (PPSP)
7 6 5 4 3 2 1 0
R PPSP7 W Reset 0 0 0 0 0 0 0 0 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
Figure 2-47. Port P Polarity Select Register (PPSP)
Read: Anytime. Write: Anytime. The Port P Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port P Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. If an IIC module is enabled, a pull-up device can be activated on either the SCL or SDA pins. Pull-down devices can not be activated on IIC pins.
Table 2-35. PPSP Field Descriptions
Field 7:0 PPSP[7:0] Description Polarity Select Port P 0 A pull-up device is connected to the associated port P pin. 1 A pull-down device is connected to the associated port P pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 102 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.9.7
Port P Wired-OR Mode Register (WOMP)
7 6 5 4 3 2 1 0
R WOMP7 W Reset 0 0 0 0 WOMP6 WOMP5 WOMP4
0 WOMP2 0 0
0 WOMPO 0 0
= Reserved or Unimplemented
Figure 2-48. Port P Wired-OR Mode Register (WOMP)
Read: Anytime. Write: Anytime. This register selects whether a port P output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. If IIC is enabled and the corresponding PWM channels are disabled, the pins are configured as wired-or and the corresponding Wired-OR Mode Register bits have no effect.
Table 2-36. WOMP Field Descriptions
Field 7:4 Wired-OR Mode Port P WOMP[7:4] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 2 WOMP2 0 WOMP0 Wired-OR Mode Port P 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Wired-OR Mode Port P 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 103
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.9.8
Port P Slew Rate Register (SRRP)
7 6 5 4 3 2 1 0
R SRRP7 W Reset 0 0 0 0 0 0 0 0 SRRP6 SRRP5 SRRP4 SRRP3 SRRP2 SRRP1 SRRP0
Figure 2-49. Port P Slew Rate Register (SRRP)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PP[7:0].
Table 2-37. SRRP Field Descriptions
Field 7:0 SRRP[7:0] Description Slew Rate Port P 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.03 104 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10
Port S
Port S is associated with the chip select 3, the serial peripheral interface (SPI) and the serial communication interface (SCI0). Each pin is assigned to these modules according to the following priority: CS3 > SPI/SCI1/SCI0 > general-purpose I/O. When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the SPI block description chapter for information on enabling and disabling the SPI. When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and RXD0 respectively. When the SCI1 receiver and transmitter are enabled and MODRR2 is set, the PS[3:2] pins become TXD1 and RXD1 respectively. Refer to the SCI block description chapter for information on enabling and disabling the SCI receiver and transmitter. During reset, port S pins are configured as high-impedance inputs.
2.3.10.1
Port S I/O Register (PTS)
7 6 5 4 3 2 1 0
R PTS7 W SPI/ SCI1/SCI0: Chip Select: Reset 0 0 0 0 0 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
SS
SCK
MOSI
MISO
TXD1
RXD1 CS3
0
TXD0
RXD0
0
0
= Reserved or Unimplemented
Figure 2-50. Port S I/O Register (PTS)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin. The SPI function takes precedence over the general-purpose I/O function if the SPI is enabled. If enabled, the SCI0(1) transmitter takes precedence over the general-purpose I/O function, and the corresponding TXD0(1) pin is configured as an output. If enabled, the SCI0(1) receiver takes precedence over the general-purpose I/O function, and the corresponding RXD0(1) pin is configured as an input.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 105
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10.2
Port S Input Register (PTIS)
7 6 5 4 3 2 1 0
R W Reset
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-51. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.
2.3.10.3
Port S Data Direction Register (DDRS)
7 6 5 4 3 2 1 0
R DDRS7 W Reset 0 0 0 0 0 0 0 0 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
Figure 2-52. Port S Data Direction Register (DDRS)
Read: Anytime. Write: Anytime. This register configures port pins PS[7:0] as either input or output. When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data Direction Register bits have no effect. When the SCI1 transmitter is enabled, the PS[3] pin becomes the TXD1 output pin and the associated Data Direction Register bit has no effect. When the SCI1 receiver is enabled, the PS[2] pin becomes the RXD1 input pin and the associated Data Direction Register bit has no effect. When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0 input pin and the associated Data Direction Register bit has no effect. If the SPI, SCI1 and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-38. DDRS Field Descriptions
Field 7:0 DDRS[7:0] Data Direction Port S 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 106 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10.4
Port S Reduced Drive Register (RDRS)
7 6 5 4 3 2 1 0
R RDRS7 W Reset 0 0 0 0 0 0 0 0 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Figure 2-53. Port S Reduced Drive Register (RDRS)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-39. RDRS Field Descriptions
Field 7:0 RDRS[7:0] Description Reduced Drive Port S 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.10.5
Port S Pull Device Enable Register (PERS)
7 6 5 4 3 2 1 0
R PERS7 W Reset 0 0 0 0 0 0 0 0 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
Figure 2-54. Port S Pull Device Enable Register (PERS)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-40. PERS Field Descriptions
Field 7:0 PERS[7:0] Pull Device Enable Port S 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 107
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10.6
Port S Polarity Select Register (PPSS)
7 6 5 4 3 2 1 0
R PPSS7 W Reset 0 0 0 0 0 0 0 0 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
Figure 2-55. Port S Polarity Select Register (PPSS)
Read: Anytime. Write: Anytime. The Port S Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port S Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 2-41. PPSS Field Descriptions
Field 7:0 PPSS[7:0] Description Pull Select Port S 0 A pull-up device is connected to the associated port S pin. 1 A pull-down device is connected to the associated port S pin.
2.3.10.7
Port S Wired-OR Mode Register (WOMS)
7 6 5 4 3 2 1 0
R WOMS7 W Reset 0 0 0 0 0 0 0 0 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
Figure 2-56. Port S Wired-OR Mode Register (WOMS)
Read: Anytime. Write: Anytime. This register selects whether a port S output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input.
Table 2-42. WOMS Field Descriptions
Field 7:0 Wired-OR Mode Port S WOMS[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 108 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10.8
Port S Slew Rate Register (SRRS)
7 6 5 4 3 2 1 0
R SRRS7 W Reset 0 0 0 0 0 0 0 0 SRRS6 SRRS5 SRRS4 SRRS3 SRRS2 SRRS1 SRRS0
Figure 2-57. Port S Slew Rate Register (SRRS)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PS[7:0].
Table 2-43. SRRS Field Descriptions
Field 7:0 SRRS[7:0] Description Slew Rate Port S 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 109
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.11
Port T
Port T is associated with the 8-channel enhanced capture timer (ECT), the Inter-IC (IIC0 and IIC1) modules and the liquid crystal display (LCD) driver. Each pin is assigned to these modules according to the following priority: LCD Driver > IIC1/IIC0 > ECT > general-purpose I/O. When the IIC1 module is enabled and MODRR1 is set, PT[7:6] pins become SCL1 and SDA1 pins respectively. When the IIC0 module is enabled and MODRR0 is set, PT[5:4] pins become SCL0 and SDA0 respectively. Refer to the IIC block description chapter for information on enabling and disabling the IIC bus. If the corresponding LCD frontplane drivers are enabled (and LCD module is enabled), the FP[27:24] outputs of the LCD module are available on port T pins PT[3:0]. If the corresponding LCD frontplane drivers are disabled (or LCD module is disabled) and the ECT is enabled, the timer channels configured for output compare are available on port T pins PT[3:0]. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers.Refer to the ECT block description chapter for information on enabling and disabling the ECT module. During reset, port T pins are configured as inputs with pull down.
2.3.11.1
Port T I/O Register (PTT)
7 6 5 4 3 2 1 0
R PTT7 W ECT: IIC1/IIC0: LCD: Reset 0 0 0 0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
OC7 SCL1
OC6 SDA1
OC5 SCL0
OC4 SDA0
OC3
OC2
OC1
OC0
1
0
1
0
1
0
1
0
Figure 2-58. Port T I/O Register (PTT)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRTx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRTx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTTx) reads “1”. If the associated data direction bit (DDRTx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 110 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.11.2
Port T Input Register (PTIT)
7 6 5 4 3 2 1 0
R W Reset
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-59. Port T Input Register (PTIT)
Read: Anytime. Write: Never, writes to this register have no effect. If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled), a read returns a 1. If the LCD frontplane driver of the associated I/O pin is disabled (or LCD module is disabled), a read returns the status of the associated pin.
2.3.11.3
Port T Data Direction Register (DDRT)
7 6 5 4 3 2 1 0
R DDRT7 W Reset 0 0 0 0 0 0 0 0 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Figure 2-60. Port T Data Direction Register (DDRT)
Read: Anytime. Write: Anytime. This register configures port pins PT[7:0] as either input or output. If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. If the ECT module is enabled, each port pin configured for output compare is forced to be an output and the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. If the ECT module is enabled, each port pin configured as an input capture has the corresponding Data Direction Register bit controlling the I/O direction of the associated pin.
Table 2-44. DDRT Field Descriptions
Field 7:0 DDRT[7:0] Data Direction Port T 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 111
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.11.4
Port T Reduced Drive Register (RDRT)
7 6 5 4 3 2 1 0
R RDRT7 W Reset 0 0 0 0 0 0 0 0 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Figure 2-61. Port T Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-45. RDRT Field Descriptions
Field 7:0 RDRT[7:0] Description Reduced Drive Port T 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12XHZ512 Data Sheet, Rev. 1.03 112 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.11.5
Port T Pull Device Enable Register (PERT)
7 6 5 4 3 2 1 0
R PERT7 W Reset 0 0 0 0 1 1 1 1 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Figure 2-62. Port T Pull Device Enable Register (PERT)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. For port pins PT[7:4], a pull-up device can be activated on wired-or (open drain) output pins. If the pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-46. PERT Field Descriptions
Field 7:0 PERT[7:0] Pull Device Enable Port T 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
2.3.11.6
Port T Polarity Select Register (PPST)
7 6 5 4 3 2 1 0
R PPST7 W Reset 0 0 0 0 1 1 1 1 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Figure 2-63. Port T Polarity Select Register (PPST)
Read: Anytime. Write: Anytime. The Port T Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port T Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. If an IIC module is enabled, a pull-up device can be activated on either the SCL or SDA pins. Pull-down devices can not be activated on IIC pins.
Table 2-47. PPST Field Descriptions
Field 7:0 PPST[7:0] Description Pull Select Port T 0 A pull-up device is connected to the associated port T pin. 1 A pull-down device is connected to the associated port T pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 113
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.11.7
Port T Wired-OR Mode Register (WOMT)
7 6 5 4 3 2 1 0
R WOMT7 W Reset 0 0 0 0 WOMT6 WOMT5 WOMT4
0 MODRR2 0 0 MODRR1 0 MODRR0 0
= Reserved or Unimplemented
Figure 2-64. Port T Wired-OR Mode Register (WOMT)
Read: Anytime. Write: Anytime. This register selects whether a port T output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. If IIC is enabled, the pins are configured as wired-or and the corresponding Wired-OR Mode Register bits have no effect. This register also configures the re-routing of IIC0, IIC1 and SCI1 on alternative ports.
Table 2-48. WOMT Field Descriptions
Field 7:4 Wired-OR Mode Port T WOMT[7:4] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 2 MODRR2 1 MODRR1 0 MODRR0 SCI1 Routing Bit — See Table 2-49.. IIC1 Routing Bit — See Table 2-50.. IIC0 Routing Bit — See Table 2-51.. Description
Table 2-49. SCI1 Routing
MODRR[2] 0 1 TXD1 PP0 PS3 RXD1 PP2 PS2
Table 2-50. IIC1 Routing
MODRR[1] 0 1 SDA1 PP6 PT6 SCL1 PP7 PT7
MC9S12XHZ512 Data Sheet, Rev. 1.03 114 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-51. IIC0 Routing
MODRR[0] 0 1 SDA0 PP4 PT4 SCL0 PP5 PT5
2.3.11.8
Port T Slew Rate Register (SRRT)
7 6 5 4 3 2 1 0
R SRRT7 W Reset 0 0 0 0 0 0 0 0 SRRT6 SRRT5 SRRT4 SRRT3 SRRT2 SRRT1 SRRT0
Figure 2-65. Port T Slew Rate Register (SRRT)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PT[7:0].
Table 2-52. SRRT Field Descriptions
Field 7:0 SRRT[7:0] Description Slew Rate Port T 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 115
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.12
Port U
Port U is associated with the stepper stall detect (SSD1 and SSD0) and motor controller (MC1 and MC0) modules. Each pin is assigned to these modules according to the following priority: SSD1/SSD0 > MC1/MC0 > general-purpose I/O. If SSD1 module is enabled, the PU[7:4] pins are controlled by the SSD1 module. If SSD1 module is disabled, the PU[7:4] pins are controlled by the motor control PWM channels 3 and 2 (MC1). If SSD0 module is enabled, the PU[3:0] pins are controlled by the SSD0 module. If SSD0 module is disabled, the PU[3:0] pins are controlled by the motor control PWM channels 1 and 0 (MC0). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port U pins are configured as high-impedance inputs.
2.3.12.1
Port U I/O Register (PTU)
7 6 5 4 3 2 1 0
R PTU7 W MC: SSD1/ SSD0: Reset M1C1P M1SINP 0 M1C1M M1SINM 0 M1COP M1COSP 0 M1COM M1COSM 0 M0C1P M0SINP 0 M0C1M M0SINM 0 M0C0P M1COSP 0 M0C0M M0COSM 0 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0
Figure 2-66. Port U I/O Register (PTU)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTUx) reads “1”. If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 116 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.12.2
Port U Input Register (PTIU)
7 6 5 4 3 2 1 0
R W Reset
PTIU7
PTIU6
PTIU5
PTIU4
PTIU3
PTIU2
PTIU1
PTIU0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-67. Port U Input Register (PTIU)
Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.
2.3.12.3
Port U Data Direction Register (DDRU)
7 6 5 4 3 2 1 0
R DDRU7 W Reset 0 0 0 0 0 0 0 0 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0
Figure 2-68. Port U Data Direction Register (DDRU)
Read: Anytime. Write: Anytime. This register configures port pins PU[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Table 2-53. DDRU Field Descriptions
Field 7:0 DDRU[7:0] Data Direction Port U 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 117
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.12.4
Port U Slew Rate Register (SRRU)
7 6 5 4 3 2 1 0
R SRRU7 W Reset 0 0 0 0 0 0 0 0 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0
Figure 2-69. Port U Slew Rate Register (SRRU)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PU[7:0].
Table 2-54. SRRU Field Descriptions
Field 7:0 SRRU[7:0] Description Slew Rate Port U 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
2.3.12.5
Port U Pull Device Enable Register (PERU)
7 6 5 4 3 2 1 0
R PERU7 W Reset 0 0 0 0 0 0 0 0 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0
Figure 2-70. Port U Pull Device Enable Register (PERU)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-55. PERU Field Descriptions
Field 7:0 PERU[7:0] Pull Device Enable Port U 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 118 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.12.6
Port U Polarity Select Register (PPSU)
7 6 5 4 3 2 1 0
R PPSU7 W Reset 0 0 0 0 0 0 0 0 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0
Figure 2-71. Port U Polarity Select Register (PPSU)
Read: Anytime. Write: Anytime. The Port U Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port U Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 2-56. PPSU Field Descriptions
Field 7:0 PPSU[7:0] Description Pull Select Port U 0 A pull-up device is connected to the associated port U pin. 1 A pull-down device is connected to the associated port U pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 119
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.13
Port V
Port V is associated with the stepper stall detect (SSD3 and SSD2) and motor controller (MC3 and MC2) modules. Each pin is assigned to these modules according to the following priority: SSD3/SSD2 > MC3/MC2 > general-purpose I/O. If SSD3 module is enabled, the PV[7:4] pins are controlled by the SSD3 module. If SSD3 module is disabled, the PV[7:4] pins are controlled by the motor control PWM channels 7 and 6 (MC3). If SSD2 module is enabled, the PV[3:0] pins are controlled by the SSD2 module. If SSD2 module is disabled, the PV[3:0] pins are controlled by the motor control PWM channels 5 and 4 (MC2). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port V pins are configured as high-impedance inputs.
2.3.13.1
Port V I/O Register (PTV)
7 6 5 4 3 2 1 0
R PTV7 W MC: SSD3/ SSD2 Reset M3C1P M3SINP 0 M3C1M M3SINM 0 M3C0P M3COSP 0 M3C0M M3COSM 0 M2C1P M2SINP 0 M2C1M M2SINM 0 M2C0P M2COSP 0 M2C0M M2COSM 0 PTV6 PTV5 PTV4 PTV3 PTV2 PTV1 PTV0
Figure 2-72. Port V I/O Register (PTV)
Read: Anytime. Write: anytime. If the associated data direction bit (DDRVx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTVx) reads “1”. If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 120 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.13.2
Port V Input Register (PTIV)
7 6 5 4 3 2 1 0
R W Reset
PTIV7
PTIV6
PTIV5
PTIV4
PTIV3
PTIV2
PTIV1
PTIV0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-73. Port V Input Register (PTIV)
Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.
2.3.13.3
Port V Data Direction Register (DDRV)
7 6 5 4 3 2 1 0
R DDRV7 W Reset 0 0 0 0 0 0 0 0 DDRV6 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0
Figure 2-74. Port V Data Direction Register (DDRV)
Read: Anytime. Write: Anytime. This register configures port pins PV[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Table 2-57. DDRV Field Descriptions
Field 7:0 DDRV[7:0] Data Direction Port V 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 121
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.13.4
Port V Slew Rate Register (SRRV)
7 6 5 4 3 2 1 0
R SRRV7 W Reset 0 0 0 0 0 0 0 0 SRRV6 SRRV5 SRRV4 SRRV3 SRRV2 SRRV1 SRRV0
Figure 2-75. Port V Slew Rate Register (SRRV)
Read: anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PV[7:0].
Table 2-58. SRRV Field Descriptions
Field 7:0 SRRV[7:0] Description Slew Rate Port V 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
2.3.13.5
Port V Pull Device Enable Register (PERV)
7 6 5 4 3 2 1 0
R PERV7 W Reset 0 0 0 0 0 0 0 0 PERV6 PERV5 PERV4 PERV3 PERV2 PERV1 PERV0
Figure 2-76. Port V Pull Device Enable Register (PERV)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-59. PERV Field Descriptions
Field 7:0 PERV[7:0] Pull Device Enable Port V 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 122 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.13.6
Port V Polarity Select Register (PPSV)
7 6 5 4 3 2 1 0
R PPSV7 W Reset 0 0 0 0 0 0 0 0 PPSV6 PPSV5 PPSV4 PPSV3 PPSV2 PPSV1 PPSV0
Figure 2-77. Port V Polarity Select Register (PPSV)
Read: Anytime. Write: Anytime. The Port V Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port V Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 2-60. PPSV Field Descriptions
Field 7:0 PPSV[7:0] Description Pull Select Port V 0 A pull-up device is connected to the associated port V pin. 1 A pull-down device is connected to the associated port V pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 123
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.14
Port W
Port W is associated with the stepper stall detect (SSD5 and SSD4) and motor controller (MC5 and MC4) modules. Each pin is assigned to these modules according to the following priority: SSD5/SSD4 > MC5/MC4 > general-purpose I/O. If SSD5 module is enabled, the PW[7:4] pins are controlled by the SSD5 module. If SSD5 module is disabled, the PW[7:4] pins are controlled by the motor control PWM channels 11 and 10 (MC5). If SSD4 module is enabled, the PW[3:0] pins are controlled by the SSD4 module. If SSD4 module is disabled, the PW[3:0] pins are controlled by the motor control PWM channels 9 and 8 (MC4). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port W pins are configured as high-impedance inputs.
2.3.14.1
Port W I/O Register (PTW)
7 6 5 4 3 2 1 0
R PTW7 W MC: SSD5/ SSD4 Reset M5C1P M5SINP 0 M3C1M M3SINM 0 M5C0P M5COSP 0 M5C0M M5COSM 0 M4C1P M4SINP 0 M4C1M M4SINM 0 M4C0P M4COSP 0 M4C0M M4COSM 0 PTW6 PTW5 PTW4 PTW3 PTW2 PTW1 PTW0
Figure 2-78. Port W I/O Register (PTW)
Read: Anytime. Write: anytime. If the associated data direction bit (DDRWx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRWx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTWx) reads “1”. If the associated data direction bit (DDRWx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 124 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.14.2
Port W Input Register (PTIW)
7 6 5 4 3 2 1 0
R W Reset
PTIW7
PTIW6
PTIW5
PTIW4
PTIW3
PTIW2
PTIW1
PTIW0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-79. Port W Input Register (PTIW)
Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.
2.3.14.3
Port W Data Direction Register (DDRW)
7 6 5 4 3 2 1 0
R DDRW7 W Reset 0 0 0 0 0 0 0 0 DDRW6 DDRW5 DDRW4 DDRW3 DDRW2 DDRW1 DDRW0
Figure 2-80. Port W Data Direction Register (DDRW)
Read: Anytime. Write: Anytime. This register configures port pins PW[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Table 2-61. DDRW Field Descriptions
Field 7:0 DDRW[7:0] Data Direction Port W 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 125
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.14.4
Port W Slew Rate Register (SRRW)
7 6 5 4 3 2 1 0
R SRRW7 W Reset 0 0 0 0 0 0 0 0 SRRW6 SRRW5 SRRW4 SRRW3 SRRW2 SRRW1 SRRW0
Figure 2-81. Port W Slew Rate Register (SRRW)
Read: anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PW[7:0].
Table 2-62. SRRW Field Descriptions
Field 7:0 SRRW[7:0] Description Slew Rate Port W 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
2.3.14.5
Port W Pull Device Enable Register (PERW)
7 6 5 4 3 2 1 0
R PERW7 W Reset 0 0 0 0 0 0 0 0 PERW6 PERW5 PERW4 PERW3 PERW2 PERW1 PERW0
Figure 2-82. Port W Pull Device Enable Register (PERW)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-63. PERW Field Descriptions
Field 7:0 PERW[7:0] Pull Device Enable Port W 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 126 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.14.6
Port W Polarity Select Register (PPSW)
7 6 5 4 3 2 1 0
R PPSW7 W Reset 0 0 0 0 0 0 0 0 PPSW6 PPSW5 PPSW4 PPSW3 PPSW2 PPSW1 PPSW0
Figure 2-83. Port W Polarity Select Register (PPSW)
Read: Anytime. Write: Anytime. The Port W Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port W Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 2-64. PPSW Field Descriptions
Field 7:0 PPSW[7:0] Description Pull Select Port W 0 A pull-up device is connected to the associated port W pin. 1 A pull-down device is connected to the associated port W pin.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 127
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.4
Functional Description
Each pin except PE0, PE1, and BKGD can act as general-purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a push-pull output.
Table 2-65. Register Availability per Port1
Port A B C D E K AD L M P S T U V W
1
Data yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes
Data Direction yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes
Input — — — — — — yes yes yes yes yes yes yes yes yes
Reduced Drive yes
Pull Enable yes
Polarity Select — — — — — —
Wired-OR Interrupt Slew Rate Mode Enable — — — — — — — — yes yes yes yes — — — — yes yes yes yes yes yes yes yes yes — — — — — — yes — — — — — — — —
Interrupt Flag — — — — — — yes — — — — — — — —
yes yes yes yes yes yes — — —
yes yes yes yes yes yes yes yes yes
yes yes yes yes yes yes yes yes yes
Each cell represents one register with individual configuration bits
2.4.1
I/O Register
The I/O Register holds the value driven out to the pin if the port is used as a general-purpose I/O. Writing to the I/O Register only has an effect on the pin if the port is used as general-purpose output. When reading the I/O Register, the value of each pin is returned if the corresponding Data Direction Register bit is set to 0 (pin configured as input). If the data direction register bits is set to 1, the content of the I/O Register bit is returned. This is independent of any other configuration (Figure 2-84). Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the I/O Register when changing the data direction register.
2.4.2
Input Register
The Input Register is a read-only register and generally returns the value of the pin (Figure 2-84).It can be used to detect overload or short circuit conditions.
MC9S12XHZ512 Data Sheet, Rev. 1.03 128 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the Input Register when changing the Data Direction Register.
2.4.3
Data Direction Register
The Data Direction Register defines whether the pin is used as an input or an output. . A Data Direction Register bit set to 0 configures the pin as an input. A Data Direction Register bit set to 1 configures the pin as an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-84). PTIx
0 1
PTx
0 1
PAD
DDRx Digital Module
data out output enable
0 1
module enable
Figure 2-84. Illustration of I/O Pin Functionality
Figure 2-85 shows the state of digital inputs and outputs when an analog module drives the port. When the analog module is enabled all associated digital output ports are disabled and all associated digital input ports read “1”t. 1
Digital Input
1 0
Module Enable
Analog Module
Digital Output Analog Output
0 1
PAD
PIM Boundary
Figure 2-85. Digital Ports and Analog Module
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 129
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.4.4
Reduced Drive Register
If the port is used as an output the Reduced Drive Register allows the configuration of the drive strength.
2.4.5
Pull Device Enable Register
The Pull Device Enable Register turns on a pull-up or pull-down device. The pull device becomes active only if the pin is used as an input or as a wired-or output.
2.4.6
Polarity Select Register
The Polarity Select Register selects either a pull-up or pull-down device if enabled. The pull device becomes active only if the pin is used as an input or as a wired-or output.
2.4.7
Pin Configuration Summary
The following table summarizes the effect of various configuration in the Data Direction (DDR), Input/Output (I/O), reduced drive (RDR), Pull Enable (PE), Pull Select (PS) and Interrupt Enable (IE) register bits. The PS configuration bit is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is set to “1”.
Table 2-66. Pin Configuration Summary
DDR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 2
IO X X X X X X X 0 1 0 1 0 1 0 1
RDR X X X X X X X 0 0 1 1 0 0 1 1
PE 0 1 1 0 0 1 1 X X X X X X X X
PS X 0 1 0 1 0 1 X X X X 0 1 0 1
IE1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Function2 Input Input Input Input Input Input Input Output to 0, Full Drive Output to 1, Full Drive Output to 0, Reduced Drive Output to 1, Reduced Drive Output to 0, Full Drive Output to 1, Full Drive Output to 0, Reduced Drive Output to 1, Reduced Drive
Pull Device Disabled Pull Up Pull Down Disabled Disabled Pull Up Pull Down Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Interrupt Disabled Disabled Disabled Falling Edge Rising Edge Falling Edge Rising Edge Disabled Disabled Disabled Disabled Falling Edge Rising Edge Falling Edge Rising Edge
Applicable only on Port AD. Digital outputs are disabled and digital input logic is forced to “1” when an analog module associated with the port is enabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 130 Freescale Semiconductor
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.5
Resets
The reset values of all registers are given in the register description in Section 2.3, “Memory Map and Register Definition”. All ports start up as general-purpose inputs on reset.
2.5.1
Reset Initialization
All registers including the data registers get set/reset asynchronously. Table 2-67 summarizes the port properties after reset initialization.
P
Table 2-67. Port Reset State Summary
Reset States Port Data Direction Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Pull Mode Pull Down Pull Down Hi-z Hi-z Pull Down Hi-z Pull Down Hi-z Hi-z Hi-z Hi-z Pull Down Hi-z Hi-z Hi-z
1
Reduced Drive Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Slew Rate Disabled Disabled Disabled Disabled Disabled Disabled N/A Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Wired-OR Mode N/A N/A N/A N/A N/A N/A N/A N/A Disabled Disabled Disabled Disabled Disabled N/A N/A N/A
Interrupt N/A N/A N/A N/A N/A N/A Disabled N/A N/A N/A N/A N/A N/A N/A N/A N/A
A B C D E K AD L M P S T[7:4] T[3:0] U V W
1
Pull Down
PE[1:0] pins have pull-ups instead of pull-downs.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 131
Chapter 2 Port Integration Module (S12XHZPIMV1)
2.6
2.6.1
Interrupts
General
Port AD generates an edge sensitive interrupt if enabled. It offers eight I/O pins with edge triggered interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins configured as inputs (with the corresponding ATDDIEN1 bit set to 1)or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or wait mode. A digital filter on each pin prevents pulses (Figure 2-87) shorter than a specified time from generating an interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-86 and Table 2-68).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
tifmin tifmax Figure 2-86. Interrupt Glitch Filter on Port AD (PPS = 0)
Table 2-68. Pulse Detection Criteria
Mode Pulse STOP Unit Ignored Uncertain Valid
1
STOP1 Unit tpulse 0.15MHz ? no
yes END
yes
FDIV[5:0] > 4?
no ALL COMMANDS IMPOSSIBLE
Figure 3-24. Determination Procedure for PRDIV8 and FDIV Bits
MC9S12XHZ512 Data Sheet, Rev. 1.03 156 Freescale Semiconductor
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.4.1.2
Command Write Sequence
The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 3.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash memory. Addresses in multiple Flash blocks can be written to as long as the location is at the same relative address in each available Flash block. Multiple addresses must be written in Flash block order starting with the lower Flash block. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. If the CBEIF flag in the FSTAT register is clear when the first Flash array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the Flash command controller indicating that the command was successfully launched. For all command write sequences except data compress and sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For data compress and sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands.
3.4.2
Flash Commands
Table 3-20 summarizes the valid Flash commands along with the effects of the commands on the Flash block.
Table 3-20. Flash Command Description
FCMDB 0x05 NVM Command Erase Verify Function on Flash Memory Verify all memory bytes in the Flash block are erased. If the Flash block is erased, the BLANK flag in the FSTAT register will set upon command completion.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 157
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
Table 3-20. Flash Command Description
FCMDB 0x06 0x20 0x40 0x41 NVM Command Data Compress Program Sector Erase Mass Erase Sector Erase Abort Function on Flash Memory Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. Program a word (two bytes) in the Flash block. Erase all memory bytes in a sector of the Flash block. Erase all memory bytes in the Flash block. A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The Flash sector should not be considered erased if the ACCERR flag is set upon command completion.
0x47
CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed.
MC9S12XHZ512 Data Sheet, Rev. 1.03 158 Freescale Semiconductor
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.4.2.1
Erase Verify Command
The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 3-25. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored. Multiple Flash blocks can be simultaneously erase verified by writing to the same relative address in each Flash block. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the selected Flash blocks are verified to be erased. If any address in a selected Flash block is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify operation.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 159
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
START
Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset.
FDIVLD Set? yes
no
Write: FCLKDIV register Read: FSTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision
ACCERR/ PVIOL Set? no
yes
Write: FSTAT register Clear ACCERR/PVIOL 0x30
Write: Flash Block Address and Dummy Data Next Flash Block? yes
Decrement Global Address by 128K
2. 3.
no Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register
Bit Polling for Command Completion Check
CCIF Set? yes
no
Erase Verify Status
BLANK Set? yes
no
EXIT Flash Block Erased
EXIT
Flash Block Not Erased
Figure 3-25. Example Erase Verify Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 160 Freescale Semiconductor
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.4.2.2
Data Compress Command
The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 3-26. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command. The address written determines the starting address for the data compress operation and the data written determines the number of consecutive words to compress. If the data value written is 0x0000, 64K addresses or 128 Kbytes will be compressed. Multiple Flash blocks can be simultaneously compressed by writing to the same relative address in each Flash block. If more than one Flash block is written to in this step, the first data written will determine the number of consecutive words to compress in each selected Flash block. 2. Write the data compress command, 0x06, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the data compress command. After launching the data compress command, the CCIF flag in the FSTAT register will set after the data compress operation has completed. The number of bus cycles required to execute the data compress operation is equal to two times the number of consecutive words to compress plus the number of Flash blocks simultaneously compressed plus 18 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Once the CCIF flag is set, the signature generated by the data compress operation is available in the FDATA registers. The signature in the FDATA registers can be compared to the expected signature to determine the integrity of the selected data stored in the selected Flash memory. If the last address of a Flash block is reached during the data compress operation, data compression will continue with the starting address of the same Flash block. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the data compress operation. NOTE Since the FDATA registers (or data buffer) are written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress command write sequence. The CBEIF flag will not set after launching the data compress command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a data compress operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence should only be started after reading the signature stored in the FDATA registers. In order to take corrective action, it is recommended that the data compress command be executed on a Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid signature, the Flash sector should be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 161
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
START
Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset.
FDIVLD Set? yes
no
Write: FCLKDIV register Read: FSTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1.
ACCERR/ PVIOL Set? no
yes
Write: FSTAT register Clear ACCERR/PVIOL 0x30
Write: Flash Address to start compression and number of word addresses to compress NOTE: address used to select Flash block; data ignored.
Simultaneous Multiple Flash Block Decision
Next Flash Block?
yes
Decrement Global Address by 128K
2. 3.
no Write: FCMD register Data Compress Command 0x06 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register
Bit Polling for Command Completion Check
CCIF Set? yes
no
Read: FDATA registers Data Compress Signature no
Signature Valid? yes EXIT
Erase and Reprogram Flash Sector(s) Compressed
Figure 3-26. Example Data Compress Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 162 Freescale Semiconductor
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.4.2.2.1
Data Compress Operation
The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compression, then the signature from each Flash block is further compressed to generate a single 16-bit signature. The final 16-bit signature, found in the FDATA registers after the data compress operation has completed, is based on the following logic equation which is executed on every data compression cycle during the operation:
MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn. 3-1
where MISR is the content of the internal signature register associated with each Flash block and DATA is the data to be compressed as shown in Figure 3-27.
DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[15]
+
DQ M0 >
+
DQ M1 > +
+
DQ M2 > +
+
DQ M3 >
+
DQ M4 > +
+
DQ M5 >
...
+
DQ M15 >
+ = Exclusive-OR MISR[15:0] = Q[15:0]
Figure 3-27. 16-Bit MISR Diagram
During the data compress operation, the following steps are executed: 1. MISR for each Flash block is reset to 0xFFFF. 2. Initialized DATA equal to 0xFFFF is compressed into the MISR for each selected Flash block which results in the MISR containing 0x0001. 3. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses incrementing. 4. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses decrementing. 5. If Flash block 0 is selected for compression, DATA equal to the contents of the MISR for Flash block 0 is compressed into the MISR for Flash block 0. If data in Flash block 0 was not selected for compression, the MISR for Flash block 0 contains 0xFFFF. 6. If Flash block 1 is selected for compression, DATA equal to the contents of the MISR for Flash block 1 is compressed into the MISR for Flash block 0. 7. If Flash block 2 is selected for compression, DATA equal to the contents of the MISR for Flash block 2 is compressed into the MISR for Flash block 0. 8. If Flash block 3 is selected for compression, DATA equal to the contents of the MISR for Flash block 3 is compressed into the MISR for Flash block 0. 9. The contents of the MISR for Flash block 0 are written to the FDATA registers.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 163
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.4.2.3
Program Command
The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 3-28. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written. Multiple Flash blocks can be simultaneously programmed by writing to the same relative address in each Flash block. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation.
MC9S12XHZ512 Data Sheet, Rev. 1.03 164 Freescale Semiconductor
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
START
Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset.
FDIVLD Set? yes
no
Write: FCLKDIV register Read: FSTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision
ACCERR/ PVIOL Set? no Write: Flash Address and program Data Next Flash Block? no Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80
yes
Write: FSTAT register Clear ACCERR/PVIOL 0x30
yes
Decrement Global Address by 128K
2. 3.
Read: FSTAT register
Bit Polling for Buffer Empty Check
CBEIF Set? yes
no
Sequential Programming Decision
Next Word?
yes
no Read: FSTAT register
Bit Polling for Command Completion Check
CCIF Set? yes EXIT
no
Figure 3-28. Example Program Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 165
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.4.2.4
Sector Erase Command
The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 3-29. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while global address bits [9:0] and the data written are ignored. Multiple Flash sectors can be simultaneously erased by writing to the same relative address in each Flash block. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered.
MC9S12XHZ512 Data Sheet, Rev. 1.03 166 Freescale Semiconductor
Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
START
Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset.
FDIVLD Set? yes
no
Write: FCLKDIV register Read: FSTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision
ACCERR/ PVIOL Set? no
yes
Write: FSTAT register Clear ACCERR/PVIOL 0x30
Write: Flash Sector Address and Dummy Data Next Flash Block? yes
Decrement Global Address by 128K
2. 3.
no Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register
Bit Polling for Command Completion Check
CCIF Set? yes EXIT
no
Figure 3-29. Example Sector Erase Command Flow
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3.4.2.5
Mass Erase Command
The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 3-30. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored. Multiple Flash blocks can be simultaneously mass erased by writing to the same relative address in each Flash block. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered.
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Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
START
Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset.
FDIVLD Set? yes
no
Write: FCLKDIV register Read: FSTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision
ACCERR/ PVIOL Set? no
yes
Write: FSTAT register Clear ACCERR/PVIOL 0x30
Write: Flash Block Address and Dummy Data Next Flash Block? yes
Decrement Global Address by 128K
2. 3.
no Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register
Bit Polling for Command Completion Check
CCIF Set? yes EXIT
no
Figure 3-30. Example Mass Erase Command Flow
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3.4.2.6
Sector Erase Abort Command
The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 3-31. The sector erase abort command write sequence is as follows: 1. Write to any Flash block address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. Therefore, if the ACCERR flag is not set after the sector erase abort command has completed, a Flash sector being erased when the abort command was launched will be fully erased. The maximum number of cycles required to abort a sector erase operation is equal to four FCLK periods (see Section 3.4.1.1, “Writing the FCLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. If sectors in multiple Flash blocks are being simultaneously erased, the sector erase abort operation will be applied to all active Flash blocks without writing to each Flash block in the sector erase abort command write sequence. NOTE Since the ACCERR bit in the FSTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle.
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Execute Sector Erase Command Flow
Read: FSTAT register
Bit Polling for Command Completion Check
CCIF Set? yes
no
Erase Abort Needed? yes
no
Sector Erase Completed
EXIT 1. Write: Dummy Flash Address and Dummy Data Write: FCMD register Sector Erase Abort Cmd 0x47 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register
2.
3.
Bit Polling for Command Completion Check
CCIF Set? yes
no
Access Error Check
ACCERR Set? no
yes
Write: FSTAT register Clear ACCERR 0x10
Sector Erase Completed
EXIT
Sector Erase Aborted
EXIT
Figure 3-31. Example Sector Erase Abort Command Flow
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3.4.3
Illegal Flash Operations
The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4. Starting a command write sequence while a sector erase abort operation is active. 5. Writing a Flash address in step 1 of a command write sequence that is not the same relative address as the first one written in the same command write sequence. 6. Writing to any Flash register other than FCMD after writing to a Flash address. 7. Writing a second command to the FCMD register in the same command write sequence. 8. Writing an invalid command to the FCMD register. 9. When security is enabled, writing a command other than mass erase to the FCMD register when the write originates from a non-secure memory location or from the Background Debug Mode. 10. Writing to a Flash address after writing to the FCMD register. 11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register. 12. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see Section 3.4.2.6, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a program or erase operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 3.5.2, “Stop Mode”). If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 3.3.2.6, “Flash Status Register (FSTAT)”). The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if an address written in the command write sequence was in a protected area of the Flash memory 2. Writing the sector erase command if an address written in the command write sequence was in a protected area of the Flash memory 3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the block
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If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 3.3.2.6, “Flash Status Register (FSTAT)”).
3.5
3.5.1
Operating Modes
Wait Mode
If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 3.8, “Interrupts”).
3.5.2
Stop Mode
If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 3.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations.
3.5.3
Background Debug Mode
In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 3-20 can be executed. If the MCU is secured and is in special single chip mode, only mass erase can be executed.
3.6
Flash Module Security
The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 3.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security byte at 0x7F_FF0F in the Flash Configuration Field must be changed directly by programming 0x7F_FF0F when the MCU is unsecured and the higher address sector is unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize to a secure operating mode.
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3.6.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 3.3.2.2, “Flash Security Register (FSEC)”) and the KEYACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison between the written data and the backdoor key data stored in the Flash memory. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially starting with 0x7F_FF00–1 and ending with 0x7F_FF06–7. 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return invalid data. The user code stored in the Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 3.3.2.2, “Flash Security Register (FSEC)”), the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the Flash Configuration Register (FCNFG). 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0x7F_FF00. 3. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEYACC bit. 4. If all four 16-bit words match the backdoor keys stored in Flash addresses 0x7F_FF00–0x7F_FF07, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 1:0. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor keys programmed in the Flash array. 2. If the four 16-bit words are written in the wrong sequence. 3. If more than four 16-bit words are written. 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF. 5. If the KEYACC bit does not remain set while the four 16-bit words are written. 6. If any two of the four 16-bit words are written on successive MCU clock cycles. After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00–0x7F_FF07 in the Flash Configuration Field. The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the backdoor key access sequence to unsecure. The backdoor keys stored in addresses 0x7F_FF00–0x7F_FF07 are
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unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM).
3.6.2
Unsecuring the MCU in Special Single Chip Mode using BDM
The MCU can be unsecured in special single chip mode by erasing the Flash module by the following method: • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass erase command write sequence to erase the Flash memory. After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a word program sequence to program the Flash security byte to the unsecured state and reset the MCU.
3.7
3.7.1
Resets
Flash Reset Sequence
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash memory according to Table 3-1: • FPROT — Flash Protection Register (see Section 3.3.2.5). • FCTL - Flash Control Register (see Section 3.3.2.8). • FSEC — Flash Security Register (see Section 3.3.2.2).
3.7.2
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed.
3.8
Interrupts
The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data and command buffers are empty.
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Table 3-21. Flash Interrupt Sources
Interrupt Source Flash Address, Data and Command Buffers empty All Flash commands completed Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE (FCNFG register) CCIE (FCNFG register) Global (CCR) Mask I Bit I Bit
NOTE Vector addresses and their relative interrupt priority are determined at the MCU level.
3.8.1
Description of Flash Interrupt Operation
The logic used for generating interrupts is shown in Figure 3-32. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request.
CBEIF CBEIE
Flash Command Interrupt Request
CCIF CCIE
Figure 3-32. Flash Interrupt Implementation
For a detailed description of the register bits, refer to Section 3.3.2.4, “Flash Configuration Register (FCNFG)” and Section 3.3.2.6, “Flash Status Register (FSTAT)” .
MC9S12XHZ512 Data Sheet, Rev. 1.03 176 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.1 Introduction
This document describes the EETX4K module which includes a 4 Kbyte EEPROM (nonvolatile) memory. The EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The EEPROM memory is ideal for data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The EEPROM module supports both block erase (all memory bytes) and sector erase (4 memory bytes). An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the EEPROM memory is generated internally. It is not possible to read from the EEPROM block while it is being erased or programmed. CAUTION An EEPROM word (2 bytes) must be in the erased state before being programmed. Cumulative programming of bits within a word is not allowed.
4.1.1
Glossary
Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the EEPROM memory.
4.1.2
• • • • • • • •
Features
4 Kbytes of EEPROM memory divided into 1024 sectors of 4 bytes Automated program and erase algorithm Interrupts on EEPROM command completion and command buffer empty Fast sector erase and word program operation 2-stage command pipeline Sector erase abort feature for critical interrupt response Flexible protection scheme to prevent accidental program or erase Single power supply for all EEPROM operations including program and erase
4.1.3
Modes of Operation
Program, erase and erase verify operations (please refer to Section 4.4.1, “EEPROM Command Operations” for details).
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4.1.4
Block Diagram
A block diagram of the EEPROM module is shown in Figure 4-1.
EETX4K
EEPROM Interface
Command Pipeline
Command Interrupt Request
EEPROM
cmd2 addr2 data2 cmd1 addr1 data1
2K * 16 Bits
sector 0 sector 1
Registers
Protection sector 1023 Oscillator Clock
Clock Divider EECLK
Figure 4-1. EETX4K Block Diagram
4.2
External Signal Description
The EEPROM module contains no signals that connect off-chip.
4.3
Memory Map and Register Definition
This section describes the memory map and registers for the EEPROM module.
4.3.1
Module Memory Map
The EEPROM memory map is shown in Figure 4-2. The HCS12X architecture places the EEPROM memory addresses between global addresses 0x13_F000 and 0x13_FFFF. The EPROT register, described in Section 4.3.2.5, “EEPROM Protection Register (EPROT)”, can be set to protect the upper region in the EEPROM memory from accidental program or erase. The EEPROM addresses covered by this protectable
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region are shown in the EEPROM memory map. The default protection setting is stored in the EEPROM configuration field as described in Table 4-1.
Table 4-1. EEPROM Configuration Field
Global Address 0x13_FFFC 0x13_FFFD 0x13_FFFE – 0x13_FFFF Size (bytes) 1 1 2 Description Reserved EEPROM Protection byte Refer to Section 4.3.2.5, “EEPROM Protection Register (EPROT)” Reserved
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MODULE BASE+ 0x0000 EEPROM Registers 12 bytes MODULE BASE + 0x000B EEPROM START = 0x13_F000
EEPROM Memory 3584 bytes (up to 4032 bytes)
0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 0x13_FF40 0x13_FF80 0x13_FFC0 EEPROM END = 0x13_FFFF EEPROM Configuration Field 4 bytes (0x13_FFFC – 0x13_FFFF) EEPROM Memory Protected Region 64, 128, 192, 256, 320, 384, 448, 512 bytes
Figure 4-2. EEPROM Memory Map
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4.3.2
Register Descriptions
The EEPROM module also contains a set of 12 control and status registers located between EEPROM module base + 0x0000 and 0x000B. A summary of the EEPROM module registers is given in Figure 4-3. Detailed descriptions of each register bit are provided.
Register Name ECLKDIV R W RESERVED1 R W RESERVED2 R W ECNFG R W EPROT R W ESTAT R W ECMD R W RESERVED3 R W EADDRHI R W EADDRLO R W EDATAHI R W EDATALO R W = Unimplemented or Reserved EDLO EDHI EABLO 0 0 0 0 0 EABHI 0 0 0 0 CBEIE CCIE RNV6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 EDIVLD 6 PRDIV8 0 5 EDIV5 0 4 EDIV4 0 3 EDIV3 0 2 EDIV2 0 1 EDIV1 0 Bit 0 EDIV0 0
EPOPEN
RNV5
RNV4
EPDIS 0
EPS2 BLANK
EPS1 0
EPS0 0
CBEIF 0
CCIF
PVIOL
ACCERR
CMDB 0 0 0 0
Figure 4-3. EETX4K Register Summary
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4.3.2.1
EEPROM Clock Divider Register (ECLKDIV)
The ECLKDIV register is used to control timed events in program and erase algorithms.
7 6 5 4 3 2 1 0
R W Reset
EDIVLD PRDIV8 0 0 EDIV5 0 EDIV4 0 EDIV3 0 EDIV2 0 EDIV1 0 EDIV0 0
= Unimplemented or Reserved
Figure 4-4. EEPROM Clock Divider Register (ECLKDIV)
All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 4-2. ECLKDIV Field Descriptions
Field 7 EDIVLD 6 PRDIV8 5:0 EDIV[5:0] Description Clock Divider Loaded 0 Register has not been written. 1 Register has been written to since the last reset. Enable Prescalar by 8 0 The oscillator clock is directly fed into the ECLKDIV divider. 1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider. Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to Section 4.4.1.1, “Writing the ECLKDIV Register” for more information.
4.3.2.2
RESERVED1
This register is reserved for factory testing and is not accessible.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-5. RESERVED1
All bits read 0 and are not writable.
4.3.2.3
RESERVED2
This register is reserved for factory testing and is not accessible.
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7
6
5
4
3
2
1
0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-6. RESERVED2
All bits read 0 and are not writable.
4.3.2.4
EEPROM Configuration Register (ECNFG)
The ECNFG register enables the EEPROM interrupts.
7 6 5 4 3 2 1 0
R CBEIE W Reset 0 0 CCIE
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-7. EEPROM Configuration Register (ECNFG)
CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable.
Table 4-3. ECNFG Field Descriptions
Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the EEPROM module. 0 Command Buffer Empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”) is set. Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the EEPROM module. 0 Command Complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”) is set.
6 CCIE
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4.3.2.5
EEPROM Protection Register (EPROT)
The EPROT register defines which EEPROM sectors are protected against program or erase operations.
7 6 5 4 3 2 1 0
R EPOPEN W Reset F
RNV6
RNV5
RNV4 EPDIS EPS2 F EPS1 F EPS0 F
F
F
F
F
= Unimplemented or Reserved
Figure 4-8. EEPROM Protection Register (EPROT)
During the reset sequence, the EPROT register is loaded from the EEPROM Protection byte at address offset 0x0FFD (see Table 4-1).All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is irrelevant. To change the EEPROM protection that will be loaded during the reset sequence, the EEPROM memory must be unprotected, then the EEPROM Protection byte must be reprogrammed. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the PVIOL flag will be set in the ESTAT register. The mass erase of an EEPROM block is possible only when protection is fully disabled by setting the EPOPEN and EPDIS bits.
Table 4-4. EPROT Field Descriptions
Field 7 EPOPEN 6:4 RNV[6:4] 3 EPDIS Description Opens the EEPROM for Program or Erase 0 The entire EEPROM memory is protected from program and erase. 1 The EEPROM sectors not protected are enabled for program or erase. Reserved Nonvolatile Bits — The RNV[6:4] bits should remain in the erased state “1” for future enhancements. EEPROM Protection Address Range Disable — The EPDIS bit determines whether there is a protected area in a specific region of the EEPROM memory ending with address offset 0x0FFF. 0 Protection enabled. 1 Protection disabled. EEPROM Protection Address Size — The EPS[2:0] bits determine the size of the protected area as shown inTable 4-5. The EPS bits can only be written to while the EPDIS bit is set.
2:0 EPS[2:0]
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Table 4-5. EEPROM Protection Address Range
EPS[2:0] 000 001 010 011 100 101 110 111 Address Offset Range 0x0FC0 – 0x0FFF 0x0F80 – 0x0FFF 0x0F40 – 0x0FFF 0x0F00 – 0x0FFF 0x0EC0 – 0x0FFF 0x0E80 – 0x0FFF 0x0E40 – 0x0FFF 0x0E00 – 0x0FFF Protected Size 64 bytes 128 bytes 192 bytes 256 bytes 320 bytes 384 bytes 448 bytes 512 bytes
4.3.2.6
EEPROM Status Register (ESTAT)
The ESTAT register defines the operational status of the module.
7 6 5 4 3 2 1 0
R CBEIF W Reset 1
CCIF PVIOL 1 0 ACCERR 0
0
BLANK
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-9. EEPROM Status Register (ESTAT — Normal Mode)
7 6 5 4 3 2 1 0
R CBEIF W Reset 1
CCIF PVIOL 1 0 ACCERR 0
0
BLANK FAIL
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-10. EEPROM Status Register (ESTAT — Special Mode)
CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode.
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Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
Table 4-6. ESTAT Field Descriptions
Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data, and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the EEPROM address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the ECNFG register to generate an interrupt request (see Figure 4-24). 0 Buffers are full. 1 Buffers are ready to accept a new command. Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the ECNFG register to generate an interrupt request (see Figure 4-24). 0 Command in progress. 1 All commands are completed. Protection Violation Flag — The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the EEPROM memory during a command write sequence. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No failure. 1 A protection violation has occurred. Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the EEPROM memory caused by either a violation of the command write sequence (see Section 4.4.1.2, “Command Write Sequence”), issuing an illegal EEPROM command (see Table 4-8), launching the sector erase abort command terminating a sector erase operation early (see Section 4.4.2.5, “Sector Erase Abort Command”) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch a command or start a command write sequence. If ACCERR is set by an erase verify operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the EEPROM module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 EEPROM block verified as not erased. 1 EEPROM block verified as erased. Flag Indicating a Failed EEPROM Operation — The FAIL flag will set if the erase verify operation fails (EEPROM block verified as not erased). The FAIL flag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL flag has no effect on FAIL. 0 EEPROM operation completed without error. 1 EEPROM operation failed.
6 CCIF
5 PVIOL
4 ACCERR
2 BLANK
1 FAIL
MC9S12XHZ512 Data Sheet, Rev. 1.03 186 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.3.2.7
EEPROM Command Register (ECMD)
The ECMD register is the EEPROM command register.
7 6 5 4 3 2 1 0
R W Reset
0 CMDB 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 4-11. EEPROM Command Register (ECMD)
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable.
Table 4-7. ECMD Field Descriptions
Field 6:0 CMDB[6:0] Description EEPROM Command Bits — Valid EEPROM commands are shown in Table 4-8. Writing any command other than those listed in Table 4-8 sets the ACCERR flag in the ESTAT register.
Table 4-8. Valid EEPROM Command List
CMDB[6:0] 0x05 0x20 0x40 0x41 0x47 0x60 Command Erase Verify Word Program Sector Erase Mass Erase Sector Erase Abort Sector Modify
4.3.2.8
RESERVED3
This register is reserved for factory testing and is not accessible.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-12. RESERVED3
All bits read 0 and are not writable.
EEPROM Address Registers (EADDR)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 187
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
The EADDRHI and EADDRLO registers are the EEPROM address registers.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
EABHI
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-13. EEPROM Address High Register (EADDRHI)
7 6 5 4 3 2 1 0
R W Reset 0 0 0 0
EABLO
0
0
0
0
= Unimplemented or Reserved
Figure 4-14. EEPROM Address Low Register (EADDRLO)
All EABHI and EABLO bits read 0 and are not writable in normal modes. All EABHI and EABLO bits are readable and writable in special modes. The MCU address bit AB0 is not stored in the EADDR registers since the EEPROM block is not byte addressable.
4.3.2.9
EEPROM Data Registers (EDATA)
The EDATAHI and EDATALO registers are the EEPROM data registers.
7 6 5 4 3 2 1 0
R W Reset 0 0 0 0
EDHI
0
0
0
0
= Unimplemented or Reserved
Figure 4-15. EEPROM Data High Register (EDATAHI)
7 6 5 4 3 2 1 0
R W Reset 0 0 0 0
EDLO
0
0
0
0
= Unimplemented or Reserved
Figure 4-16. EEPROM Data Low Register (EDATALO)
All EDHI and EDLO bits read 0 and are not writable in normal modes.
MC9S12XHZ512 Data Sheet, Rev. 1.03 188 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
All EDHI and EDLO bits are readable and writable in special modes.
4.4
4.4.1
Functional Description
EEPROM Command Operations
Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector modify algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider. The command register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress. Buffer empty as well as command completion are signalled by flags in the EEPROM status register with interrupts generated, if enabled. The next sections describe: 1. How to write the ECLKDIV register 2. Command write sequences to program, erase, erase verify, sector erase abort, and sector modify operations on the EEPROM memory 3. Valid EEPROM commands 4. Effects resulting from illegal EEPROM command write sequences or aborting EEPROM operations
4.4.1.1
Writing the ECLKDIV Register
Prior to issuing any EEPROM command after a reset, the user is required to write the ECLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the ECLKDIV determination must take this information into account. If we define: • ECLK as the clock of the EEPROM timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323)=4) then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in Figure 4-17. For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz, ECLKDIV bits EDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting EECLK frequency is then 190 kHz. As a result, the EEPROM program and erase algorithm timings are increased over the optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting EECLK frequency is
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 189
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of EECLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPROM memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the EEPROM memory with EECLK < 150 kHz should be avoided. Setting ECLKDIV to a value such that EECLK < 150 kHz can destroy the EEPROM memory due to overstress. Setting ECLKDIV to a value such that (1/EECLK+Tbus) < 5 µs can result in incomplete programming or erasure of the EEPROM memory cells. If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR flag in the ESTAT register will set.
MC9S12XHZ512 Data Sheet, Rev. 1.03 190 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
START
Tbus < 1µs? yes PRDIV8 = 0 (reset)
no ALL COMMANDS IMPOSSIBLE
oscillator_clock >12.8 MHz? yes
no
PRDIV8 = 1 PRDCLK = oscillator_clock/8 PRDCLK = oscillator_clock
PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes
no
EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs]))
EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])–1
TRY TO DECREASE Tbus EECLK = (PRDCLK)/(1+EDIV[5:0])
1/EECLK[MHz] + Tbus[ms] > 5 AND EECLK > 0.15 MHz ? no
yes
END
yes
EDIV[5:0] > 4?
no ALL COMMANDS IMPOSSIBLE
Figure 4-17. Determination Procedure for PRDIV8 and EDIV Bits
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 191
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.1.2
Command Write Sequence
The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the EEPROM module not permitted between the steps. However, EEPROM register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to one address in the EEPROM memory. 2. Write a valid command to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the EADDR registers and the data will be stored in the EDATA registers. If the CBEIF flag in the ESTAT register is clear when the first EEPROM array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the EEPROM command controller indicating that the command was successfully launched. For all command write sequences except sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the ESTAT register. The CCIF flag will set upon completion of all active and buffered commands.
4.4.2
EEPROM Commands
Table 4-9 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block.
Table 4-9. EEPROM Command Description
ECMDB 0x05 0x20 0x40 Command Erase Verify Program Sector Erase Function on EEPROM Memory Verify all memory bytes in the EEPROM block are erased. If the EEPROM block is erased, the BLANK flag in the ESTAT register will set upon command completion. Program a word (two bytes) in the EEPROM block. Erase all four memory bytes in a sector of the EEPROM block.
MC9S12XHZ512 Data Sheet, Rev. 1.03 192 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
Table 4-9. EEPROM Command Description
ECMDB 0x41 Command Mass Erase Sector Erase Abort Sector Modify Function on EEPROM Memory Erase all memory bytes in the EEPROM block. A mass erase of the full EEPROM block is only possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The EEPROM sector should not be considered erased if the ACCERR flag is set upon command completion. Erase all four memory bytes in a sector of the EEPROM block and reprogram the addressed word.
0x47
0x60
CAUTION An EEPROM word (2 bytes) must be in the erased state before being programmed. Cumulative programming of bits within a word is not allowed.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 193
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.2.1
Erase Verify Command
The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown in Figure 4-18. The erase verify command write sequence is as follows: 1. Write to an EEPROM address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the ESTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of words in the EEPROM memory plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the ESTAT register will be set if all addresses in the EEPROM memory are verified to be erased. If any address in the EEPROM memory is not erased, the erase verify operation will terminate and the BLANK flag in the ESTAT register will remain clear.
MC9S12XHZ512 Data Sheet, Rev. 1.03 194 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
START
Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset.
EDIVLD Set? yes
no
Write: ECLKDIV register Read: ESTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. 2. 3.
ACCERR/ PVIOL Set? no Write: EEPROM Address and Dummy Data
yes
Write: ESTAT register Clear ACCERR/PVIOL 0x30
Write: ECMD register Erase Verify Command 0x05 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register
NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register.
Bit Polling for Command Completion Check
CCIF Set? yes
no
Erase Verify Status
BLANK Set? yes
no
EXIT EEPROM Memory Erased
EXIT
EEPROM Memory Not Erased
Figure 4-18. Example Erase Verify Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 195
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.2.2
Program Command
The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 4-19. The program command write sequence is as follows: 1. Write to an EEPROM block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2. Write the program command, 0x20, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the ESTAT register will set after the program operation has completed unless a new command write sequence has been buffered.
MC9S12XHZ512 Data Sheet, Rev. 1.03 196 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
START
Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset.
EDIVLD Set? yes
no
Write: ECLKDIV register Read: ESTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. 2. 3.
ACCERR/ PVIOL Set? no Write: EEPROM Address and program Data Write: ECMD register Program Command 0x20 Write: ESTAT register Clear CBEIF 0x80
yes
Write: ESTAT register Clear ACCERR/PVIOL 0x30
NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register.
Read: ESTAT register
Bit Polling for Buffer Empty Check
CBEIF Set? yes
no
Sequential Programming Decision
Next Word?
yes
no Read: ESTAT register
Bit Polling for Command Completion Check
CCIF Set? yes EXIT
no
Figure 4-19. Example Program Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 197
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.2.3
Sector Erase Command
The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 4-20. The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command. The EEPROM address written determines the sector to be erased while global address bits [1:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be erased is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the ESTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered.
MC9S12XHZ512 Data Sheet, Rev. 1.03 198 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
START
Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset.
EDIVLD Set? yes
no
Write: ECLKDIV register
Read: ESTAT register Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. 2. 3.
ACCERR/ PVIOL Set? no
yes
Write: ESTAT register Clear ACCERR/PVIOL 0x30
Write: EEPROM Sector Address and Dummy Data Write: ECMD register Sector Erase Command 0x40 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register.
Bit Polling for Command Completion Check
CCIF Set? yes EXIT
no
Figure 4-20. Example Sector Erase Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 199
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.2.4
Mass Erase Command
The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 4-21. The mass erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the mass erase command. If the EEPROM memory to be erased contains any protected area, the PVIOL flag in the ESTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the ESTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered.
MC9S12XHZ512 Data Sheet, Rev. 1.03 200 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
START
Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset.
EDIVLD Set? yes
no
Write: ECLKDIV register Read: ESTAT register
Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. 2. 3.
ACCERR/ PVIOL Set? no Write: EEPROM Address and Dummy Data
yes
Write: ESTAT register Clear ACCERR/PVIOL 0x30
Write: ECMD register Mass Erase Command 0x41 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register
NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register.
Bit Polling for Command Completion Check
CCIF Set? yes EXIT
no
Figure 4-21. Example Mass Erase Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 201
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.2.5
Sector Erase Abort Command
The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 4-22. The sector erase abort command write sequence is as follows: 1. Write to any EEPROM memory address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase or sector modify operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the EEPROM sector may not be fully erased and a new sector erase or sector modify command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase or sector modify operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. If the sector erase abort command is launched after the sector modify operation has completed the sector erase step, the program step will be allowed to complete. The maximum number of cycles required to abort a sector erase or sector modify operation is equal to four EECLK periods (see Section 4.4.1.1, “Writing the ECLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. NOTE Since the ACCERR bit in the ESTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the ESTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle.
MC9S12XHZ512 Data Sheet, Rev. 1.03 202 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
Execute Sector Erase/Modify Command Flow
Read: ESTAT register
Bit Polling for Command Completion Check
CCIF Set? yes
no
Erase Abort Needed? yes
no
Sector Erase Completed
EXIT 1. Write: Dummy EEPROM Address and Dummy Data Write: ECMD register Sector Erase Abort Cmd 0x47 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register
NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register.
2.
3.
Bit Polling for Command Completion Check
CCIF Set? yes
no
Access Error Check
ACCERR Set? no
yes
Write: ESTAT register Clear ACCERR 0x10
Sector Erase or Modify Completed
EXIT
Sector Erase or Modify Aborted
EXIT
Figure 4-22. Example Sector Erase Abort Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 203
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.2.6
Sector Modify Command
The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 4-23. The sector modify command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector modify command. The EEPROM address written determines the sector to be erased and word to be reprogrammed while byte address bit 0 is ignored. 2. Write the sector modify command, 0x60, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be modified is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector modify command will not launch. Once the sector modify command has successfully launched, the CCIF flag in the ESTAT register will set after the sector modify operation has completed unless a new command write sequence has been buffered.
MC9S12XHZ512 Data Sheet, Rev. 1.03 204 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
START
Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset.
EDIVLD Set? yes
no
Write: ECLKDIV register
Read: ESTAT register Address, Data, Command Buffer Empty Check
CBEIF Set? yes
no
Access Error and Protection Violation Check 1. 2. 3.
ACCERR/ PVIOL Set? no
yes
Write: ESTAT register Clear ACCERR/PVIOL 0x30
Write: EEPROM Word Address and program Data Write: ECMD register Sector Modify Command 0x60 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register.
Bit Polling for Command Completion Check
CCIF Set? yes EXIT
no
Figure 4-23. Example Sector Modify Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 205
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.4.3
Illegal EEPROM Operations
The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4. Writing to any EEPROM register other than ECMD after writing to an EEPROM address. 5. Writing a second command to the ECMD register in the same command write sequence. 6. Writing an invalid command to the ECMD register. 7. Writing to an EEPROM address after writing to the ECMD register. 8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the ECMD register. 9. Writing a 0 to the CBEIF flag in the ESTAT register to abort a command write sequence. The ACCERR flag will not be set if any EEPROM register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase or sector modify operation is active which results in the early termination of the sector erase or sector modify operation (see Section 4.4.2.5, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a command operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 4.5.2, “Stop Mode”). If the EEPROM memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the ESTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”). The PVIOL flag will be set after the command is written to the ECMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if the address written in the command write sequence was in a protected area of the EEPROM memory. 2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the EEPROM memory. 3. Writing the mass erase command to the EEPROM memory while any EEPROM protection is enabled. 4. Writing the sector modify command if the address written in the command write sequence was in a protected area of the EEPROM memory. If the PVIOL flag is set in the ESTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 4.3.2.6, “EEPROM Status Register (ESTAT)”).
MC9S12XHZ512 Data Sheet, Rev. 1.03 206 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.5
4.5.1
Operating Modes
Wait Mode
If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 4.8, “Interrupts”).
4.5.2
Stop Mode
If a command is active (CCIF = 0) when the MCU enters the stop mode, the operation will be aborted and, if the operation is program, sector erase, mass erase, or sector modify, the EEPROM array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the EEPROM memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 4.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program, sector erase, mass erase, or sector modify operations.
4.5.3
Background Debug Mode
In background debug mode (BDM), the EPROT register is writable. If the MCU is unsecured, then all EEPROM commands listed in Table 4-9 can be executed. If the MCU is secured and is in special single chip mode, the only command available to execute is mass erase.
4.6
EEPROM Module Security
The EEPROM module does not provide any security information to the MCU. After each reset, the security state of the MCU is a function of information provided by the Flash module (see the specific FTX Block Guide).
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 207
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.6.1
Unsecuring the MCU in Special Single Chip Mode using BDM
Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased using the following method : • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a mass erase command write sequence to erase the EEPROM memory. After the CCIF flag sets to indicate that the EEPROM mass operation has completed and assuming that the Flash memory has also been erased, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state.
4.7
4.7.1
Resets
EEPROM Reset Sequence
On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the EPROT register from the EEPROM memory according to Table 4-1.
4.7.2
Reset While EEPROM Command Active
If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted. The state of a word being programmed or the sector / block being erased is not guaranteed.
4.8
Interrupts
The EEPROM module can generate an interrupt when all EEPROM command operations have completed, when the EEPROM address, data, and command buffers are empty.
Table 4-10. EEPROM Interrupt Sources
Interrupt Source EEPROM address, data, and command buffers empty All EEPROM commands completed Interrupt Flag CBEIF (ESTAT register) CCIF (ESTAT register) Local Enable CBEIE (ECNFG register) CCIE (ECNFG register) Global (CCR) Mask I Bit I Bit
NOTE Vector addresses and their relative interrupt priority are determined at the MCU level.
MC9S12XHZ512 Data Sheet, Rev. 1.03 208 Freescale Semiconductor
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
4.8.1
Description of EEPROM Interrupt Operation
The logic used for generating interrupts is shown in Figure 4-24. The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request.
CBEIF CBEIE
EEPROM Command Interrupt Request
CCIF CCIE
Figure 4-24. EEPROM Interrupt Implementation
For a detailed description of the register bits, refer to Section 4.3.2.4, “EEPROM Configuration Register (ECNFG)” and Section 4.3.2.6, “EEPROM Status Register (ESTAT)” .
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 209
Chapter 4 4 Kbyte EEPROM Module (S12XEETX4KV2)
MC9S12XHZ512 Data Sheet, Rev. 1.03 210 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.1 Introduction
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform complex communication protocols. The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s interrupt load. Figure 5-1 gives an overview on the XGATE architecture. This document describes the functionality of the XGATE module, including: • XGATE registers (Section 5.3, “Memory Map and Register Definition”) • XGATE RISC core (Section 5.4.1, “XGATE RISC Core”) • Hardware semaphores (Section 5.4.4, “Semaphores”) • Interrupt handling (Section 5.5, “Interrupts”) • Debug features (Section 5.6, “Debug Mode”) • Security (Section 5.7, “Security”) • Instruction set (Section 5.8, “Instruction Set”)
5.1.1
Glossary of Terms
XGATE Request A service request from a peripheral module which is directed to the XGATE by the S12X_INT module (see Figure 5-1). XGATE Channel The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request Vector, Interrupt Flag) which are associated with a particular XGATE Request. XGATE Channel ID A 7-bit identifier associated with an XGATE channel. In S12X designs valid Channel IDs range from $78 to $09. XGATE Channel Interrupt An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module. XGATE Software Channel
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 211
Chapter 5 XGATE (S12XGATEV2)
Special XGATE channel that is not associated with any peripheral service request. A Software Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module. XGATE Semaphore A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE. (see 5.4.4/5-232) XGATE Thread A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request. XGATE Debug Mode A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables the XGATE’s debug features (see 5.6/5-234). XGATE Software Error The XGATE is able to detect a number of error conditions caused by erratic software (see 5.4.5/5-233). These error conditions will cause the XGATE to seize program execution and flag an Interrupt to the S12X_CPU. Word A 16 bit entity. Byte An 8 bit entity.
5.1.2
Features
The XGATE module includes these features: • Data movement between various targets (i.e Flash, RAM, and peripheral modules) • Data manipulation through built in RISC core • Provides up to 112 XGATE channels — 104 hardware triggered channels — 8 software triggered channels • Hardware semaphores which are shared between the S12X_CPU and the XGATE module • Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer • Software error detection to catch erratic application code
5.1.3
Modes of Operation
There are four run modes on S12X devices. • Run mode, wait mode, stop mode The XGATE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGATE module is idle. • Freeze mode (BDM active)
MC9S12XHZ512 Data Sheet, Rev. 1.03 212 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
In freeze mode all clocks of the XGATE module may be stopped, depending on the module configuration (see Section 5.3.1.1, “XGATE Control Register (XGMCTL)”).
5.1.4
Block Diagram
Figure Figure 5-1 shows a block diagram of the XGATE.
Peripheral Interrupts
S12X_INT
XGATE INTERRUPTS XGATE REQUESTS
XGATE
Interrupt Flags Semaphores
Software Triggers
RISC Core
Software Triggers
Data/Code
S12X_DBG
Peripherals
S12X_MMC
Figure 5-1. XGATE Block Diagram
5.2
External Signal Description
The XGATE module has no external pins.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 213
Chapter 5 XGATE (S12XGATEV2)
5.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the XGATE module. The memory map for the XGATE module is given below in Figure 5-2.The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved registers have no effect.
5.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Register Name 0x0000 XGMCTL R 15 0 14 0 13 0 12 0 11 0 10 0 9 0
XG SWEIFM
8 0 XGIEM
7
6
5
4
3 XG FACT
2 0
1
0
XG XG XG XGEM XGSSM W FRZM DBGM FACTM
XGE XGFRZ XGDBG XGSS
XG XGIE SWEIF
0x0002 R XGMCHID W 0x0003 R Reserved W 0x0004 R Reserved W 0x0005 R Reserved W 0x0006 XGVBR R W = Unimplemented or Reserved
0
XGCHID[6:0]
XGVBR[15:1]
0
Figure 5-2. XGATE Register Summary (Sheet 1 of 3)
MC9S12XHZ512 Data Sheet, Rev. 1.03 214 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
127 0x0008 XGIF R W 111 0x000A XGIF R W 0
126 0
125 0
124 0
123 0
122 0
121 0
120
119
118
117
116
115
114
113
112
XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60
95 0x000C XGIF R W
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50
79 0x000E XGIF Register Name 0x0010 XGIF R W R W
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30
47 0x0012 XGIF R W
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20
31 0x0014 XGIF R W
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10
15 0x0016 XGIF R W
14
13
12
11
10
9
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09
= Unimplemented or Reserved
Figure 5-2. XGATE Register Summary (Sheet 2 of 3)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 215
Chapter 5 XGATE (S12XGATEV2)
15 0x0018 R XGSWTM W 0x001A R XGSEMM W 0x001C R Reserved W 0x001D XGCCR 0x001E XGPC R W R W 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7
6
5
4
3
2
1
0
XGSWTM[7:0] 0 0 0 0 0 0 0 0
XGSWT[7:0]
XGSEMM[7:0]
XGSEM[7:0]
0
0
0
0
XGN XGZ
XGV XGC
XGPC
0x0020 R Reserved W 0x0021 R Reserved W 0x0022 XGR1 0x0024 XGR2 0x0026 XGR3 0x0028 XGR4 0x002A XGR5 0x002C XGR6 0x002E XGR7 R W R W R W R W R W R W R W = Unimplemented or Reserved XGR1
XGR2
XGR3
XGR4
XGR5
XGR6
XGR7
Figure 5-2. XGATE Register Summary (Sheet 3 of 3)
MC9S12XHZ512 Data Sheet, Rev. 1.03 216 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.3.1.1
XGATE Control Register (XGMCTL)
All module level switches and flags are located in the module control register Figure 5-3.
Module Base +0x00000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 XGEM 0
0
0
0 XG SSM 0
0 XG FACTM 0
0
0
0 XGE 0 XGFRZ XGDBG XGSS XGFACT 0 0 0 0
0
XG XG FRZM DBGM 0 0
XG XGIEM SWEIFM 0 0 0
XG SWEIF 0
XGIE 0
0
= Unimplemented or Reserved
Figure 5-3. XGATE Control Register (XGMCTL)
Read: Anytime Write: Anytime
Table 5-1. XGMCTL Field Descriptions (Sheet 1 of 3)
Field 15 XGEM Description XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is written to the XGEM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGE in the same bus cycle 1 Enable write access to the XGE in the same bus cycle XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared if a "1" is written to the XGFRZM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGFRZ in the same bus cycle 1 Enable write access to the XGFRZ in the same bus cycle XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared if a "1" is written to the XGDBGM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGDBG in the same bus cycle 1 Enable write access to the XGDBG in the same bus cycle XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a "1" is written to the XGSSM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGSS in the same bus cycle 1 Enable write access to the XGSS in the same bus cycle
14 XGFRZM
13 XGDBGM
12 XGSSM
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 217
Chapter 5 XGATE (S12XGATEV2)
Table 5-1. XGMCTL Field Descriptions (Sheet 2 of 3)
Field 11 XGFACTM Description XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or cleared if a "1" is written to the XGFACTM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGFACT in the same bus cycle 1 Enable write access to the XGFACT in the same bus cycle
9 XGSWEIF Mask — This bit controls the write access to the XGSWEIF bit. The XGSWEIF bit can only be cleared XGSWEIFM if a "1" is written to the XGSWEIFM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGSWEIF in the same bus cycle 1 Enable write access to the XGSWEIF in the same bus cycle 8 XGIEM XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1" is written to the XGIEM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGIE in the same bus cycle 1 Enable write access to the XGIE in the same bus cycle XGATE Module Enable — This bit enables the XGATE module. If the XGATE module is disabled, pending XGATE requests will be ignored. The thread that is executed by the RISC core while the XGE bit is cleared will continue to run. Read: 0 XGATE module is disabled 1 XGATE module is enabled Write: 0 Disable XGATE module 1 Enable XGATE module Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active). Read: 0 RISC core operates normally in Freeze (BDM active) 1 RISC core stops in Freeze Mode (BDM active) Write: 0 Don’t stop RISC core in Freeze Mode (BDM active) 1 Stop RISC core in Freeze Mode (BDM active) XGATE Debug Mode — This bit indicates that the XGATE is in Debug Mode (see Section 5.6, “Debug Mode”). Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see S12X_DBG Section), or by writing a "1" to this bit. Read: 0 RISC core is not in Debug Mode 1 RISC core is in Debug Mode Write: 0 Leave Debug Mode 1 Enter Debug Mode Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit.
7 XGE
6 XGFRZ
5 XGDBG
MC9S12XHZ512 Data Sheet, Rev. 1.03 218 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
Table 5-1. XGMCTL Field Descriptions (Sheet 3 of 3)
Field 4 XGSS Description XGATE Single Step — This bit forces the execution of a single instruction if the XGATE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared). Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Execute a single RISC instruction Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed. Fake XGATE Activity — This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE idle periods Read: 0 XGATE will only flag activity if it is not idle or in debug mode. 1 XGATE will always signal activity to the MCU. Write: 0 Only flag activity if not idle or in debug mode. 1 Always signal XGATE activity. XGATE Software Error Interrupt Flag — This bit signals a pending Software Error Interrupt. It is set if the RISC core detects an error condition (see Section 5.4.5, “Software Error Detection”). The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread and cause the XGATE to become idle. Read: 0 Software Error Interrupt is not pending 1 Software Error Interrupt is pending if XGIE is set Write: 0 No effect 1 Clears the XGSWEIF bit XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module Read: 0 All XGATE interrupts disabled 1 All XGATE interrupts enabled Write: 0 Disable all XGATE interrupts 1 Enable all XGATE interrupts
3 XGFACT
1 XGSWEIF
0 XGIE
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 219
Chapter 5 XGATE (S12XGATEV2)
5.3.1.2
XGATE Channel ID Register (XGCHID)
The XGATE channel ID register (Figure 5-4) shows the identifier of the XGATE channel that is currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register can be used to start and terminate threads (see Section 5.6.1, “Debug Features”).
Module Base +0x0002
7 6 5 4 3 2 1 0
R W Reset
0 0 0 0 0
XGCHID[6:0] 0 0 0 0
= Unimplemented or Reserved
Figure 5-4. XGATE Channel ID Register (XGCHID)
Read: Anytime Write: In Debug Mode
Table 5-2. XGCHID Field Descriptions
Field Description
6–0 Request Identifier — ID of the currently active channel XGCHID[6:0]
5.3.1.3
XGATE Vector Base Address Register (XGVBR)
The vector base address register (Figure 5-5 and Figure 5-6) determines the location of the XGATE vector block.
Module Base +0x0006
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
XGVBR[15:1] 0 0 0 0 0 0 0 0
0 0
= Unimplemented or Reserved
Figure 5-5. XGATE Vector Base Address Register (XGVBR)
Read: Anytime Write: Only if the module is disabled (XGE = 0) and idle (XGCHID = $00))
Table 5-3. XGVBR Field Descriptions
Field Description
15–1 Vector Base Address — The XGVBR register holds the start address of the vector block in the XGATE XBVBR[15:1] memory map.
MC9S12XHZ512 Data Sheet, Rev. 1.03 220 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.3.1.4
XGATE Channel Interrupt Flag Vector (XGIF)
The interrupt flag vector (Figure 5-6) provides access to the interrupt flags bits of each channel. Each flag may be cleared by writing a "1" to its bit location.
Module Base +0x0008
127 126 125 124 123 122 121 120
XGIF_78
119
XGF_77
118
117
116
115
114
113
112
R W Reset
0 0
111
0 0
110
0 0
109
0 0
108
0 0
107
0 0
106
0 0
105
XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70
0
104
0
103
XGF_67
0
102
0
101
0
100
0
99
0
98
0
97
0
96
R W Reset
XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68
XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60
0
95
0
94
0
93
0
92
0
91
0
90
0
89
0
88
0
87
XGF_57
0
86
0
85
0
84
0
83
0
82
0
81
0
80
R W Reset
XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58
XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50
0
79
0
78
0
77
0
76
0
75
0
74
0
73
0
72
0
71
0
70
0
69
0
68
0
67
0
66
0
65
0
64
R W Reset
XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40
0
63
0
62
0
61
0
60
0
59
0
58
0
57
0
56
0
55
0
54
0
53
0
52
0
51
0
50
0
49
0
48
R W Reset
XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30
0
47
0
46
0
45
0
44
0
43
0
42
0
41
0
40
0
39
0
38
0
37
0
36
0
35
0
34
0
33
0
32
R W Reset
XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20
0
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
R W Reset
XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R W Reset
XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. XGATE Channel Interrupt Flag Vector (XGIF)
Read: Anytime
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 221
Chapter 5 XGATE (S12XGATEV2)
Write: Anytime
Table 5-4. XGIV Field Descriptions
Field 127–9 XGIF[78:9] Description Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC core. Each flag can be cleared by writing a "1" to its bit location. Unimplemented interrupt flags will always read "0". Refer to Section “Interrupts” of the SoC Guide for a list of implemented Interrupts. Read: 0 Channel interrupt is not pending 1 Channel interrupt is pending if XGIE is set Write: 0 No effect 1 Clears the interrupt flag
NOTE Suggested Mnemonics for accessing the interrupt flag vector on a word basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[47:32]), XGIF_1F_10 (XGIF[31:16]), XGIF_0F_00 (XGIF[15:0])
MC9S12XHZ512 Data Sheet, Rev. 1.03 222 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.3.1.5
XGATE Software Trigger Register (XGSWT)
The eight software triggers of the XGATE module can be set and cleared through the XGATE software trigger register (Figure 5-7). The upper byte of this register, the software trigger mask, controls the write access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written to the associated mask in the same bus cycle.
Module Base +0x00018
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0
XGSWTM[7:0]
XGSWT[7:0] 0 0 0 0 0
Figure 5-7. XGATE Software Trigger Register (XGSWT)
Read: Anytime Write: Anytime
Table 5-5. XGSWT Field Descriptions
Field Description
15–8 Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only XGSWTM[7:0] be written if a "1" is written to the corresponding XGSWTM bit in the same access. Read: These bits will always read "0". Write: 0 Disable write access to the XGSWT in the same bus cycle 1 Enable write access to the corresponding XGSWT bit in the same bus cycle 7–0 XGSWT[7:0] Software Trigger Bits — These bits act as interrupt flags that are able to trigger XGATE software channels. They can only be set and cleared by software. Read: 0 No software trigger pending 1 Software trigger pending if the XGIE bit is set Write: 0 Clear Software Trigger 1 Set Software Trigger
NOTE The XGATE channel IDs that are associated with the eight software triggers are determined on chip integration level. (see Section “Interrupts” of the Soc Guide) XGATE software triggers work like any peripheral interrupt. They can be used as XGATE requests as well as S12X_CPU interrupts. The target of the software trigger must be selected in the S12X_INT module.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 223
Chapter 5 XGATE (S12XGATEV2)
5.3.1.6
XGATE Semaphore Register (XGSEM)
The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM instructions. The S12X_CPU has access to the semaphores through the XGATE semaphore register (Figure 5-8). Refer to section Section 5.4.4, “Semaphores” for details.
Module Base +0x0001A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0
XGSEMM[7:0]
XGSEM[7:0] 0 0 0 0 0
Figure 5-8. XGATE Semaphore Register (XGSEM)
Read: Anytime Write: Anytime (see Section 5.4.4, “Semaphores”)
Table 5-6. XGSEM Field Descriptions
Field Description
15–8 Semaphore Mask — These bits control the write access to the XGSEM bits. XGSEMM[7:0] Read: These bits will always read "0". Write: 0 Disable write access to the XGSEM in the same bus cycle 1 Enable write access to the XGSEM in the same bus cycle 7–0 XGSEM[7:0] Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access. Read: 0 Semaphore is unlocked or locked by the RISC core 1 Semaphore is locked by the S12X_CPU Write: 0 Clear semaphore if it was locked by the S12X_CPU 1 Attempt to lock semaphore by the S12X_CPU
MC9S12XHZ512 Data Sheet, Rev. 1.03 224 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.3.1.7
XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 5-9) provides access to the RISC core’s condition code register.
Module Base +0x001D
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
XGN 0
XGZ 0
XGV 0
XGC 0
= Unimplemented or Reserved
Figure 5-9. XGATE Condition Code Register (XGCCR)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-7. XGCCR Field Descriptions
Field 3 XGN 2 XGZ 1 XGV 0 XGC Sign Flag — The RISC core’s Sign flag Zero Flag — The RISC core’s Zero flag Overflow Flag — The RISC core’s Overflow flag Carry Flag — The RISC core’s Carry flag Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 225
Chapter 5 XGATE (S12XGATEV2)
5.3.1.8
XGATE Program Counter Register (XGPC)
The XGPC register (Figure 5-10) provides access to the RISC core’s program counter.
Module Base +0x0001E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
XGPC 0 0 0 0 0 0 0 0 0
Figure 5-10. XGATE Program Counter Register (XGPC) Figure 5-11.
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-8. XGPC Field Descriptions
Field 15–0 XGPC[15:0] Description Program Counter — The RISC core’s program counter
5.3.1.9
XGATE Register 1 (XGR1)
The XGR1 register (Figure 5-12) provides access to the RISC core’s register 1.
Module Base +0x00022
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR1 0 0 0 0 0 0 0 0
Figure 5-12. XGATE Register 1 (XGR1)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-9. XGR1 Field Descriptions
Field 15–0 XGR1[15:0] Description XGATE Register 1 — The RISC core’s register 1
MC9S12XHZ512 Data Sheet, Rev. 1.03 226 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.3.1.10
XGATE Register 2 (XGR2)
The XGR2 register (Figure 5-13) provides access to the RISC core’s register 2.
Module Base +0x00024
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR2 0 0 0 0 0 0 0 0
Figure 5-13. XGATE Register 2 (XGR2)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-10. XGR2 Field Descriptions
Field 15–0 XGR2[15:0] Description XGATE Register 2 — The RISC core’s register 2
5.3.1.11
XGATE Register 3 (XGR3)
The XGR3 register (Figure 5-14) provides access to the RISC core’s register 3.
Module Base +0x00026
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR3 0 0 0 0 0 0 0 0
Figure 5-14. XGATE Register 3 (XGR3)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-11. XGR3 Field Descriptions
Field 15–0 XGR3[15:0] Description XGATE Register 3 — The RISC core’s register 3
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 227
Chapter 5 XGATE (S12XGATEV2)
5.3.1.12
XGATE Register 4 (XGR4)
The XGR4 register (Figure 5-15) provides access to the RISC core’s register 4.
Module Base +0x00028
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR4 0 0 0 0 0 0 0 0
Figure 5-15. XGATE Register 4 (XGR4)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-12. XGR4 Field Descriptions
Field 15–0 XGR4[15:0] Description XGATE Register 4 — The RISC core’s register 4
5.3.1.13
XGATE Register 5 (XGR5)
The XGR5 register (Figure 5-16) provides access to the RISC core’s register 5.
Module Base +0x0002A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR5 0 0 0 0 0 0 0 0
Figure 5-16. XGATE Register 5 (XGR5)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-13. XGR5 Field Descriptions
Field 15–0 XGR5[15:0] Description XGATE Register 5 — The RISC core’s register 5
MC9S12XHZ512 Data Sheet, Rev. 1.03 228 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.3.1.14
XGATE Register 6 (XGR6)
The XGR6 register (Figure 5-17) provides access to the RISC core’s register 6.
Module Base +0x0002C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR6 0 0 0 0 0 0 0 0
Figure 5-17. XGATE Register 6 (XGR6)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-14. XGR6 Field Descriptions
Field 15–0 XGR6[15:0] Description XGATE Register 6 — The RISC core’s register 6
5.3.1.15
XGATE Register 7 (XGR7)
The XGR7 register (Figure 5-18) provides access to the RISC core’s register 7.
Module Base +0x0002E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR7 0 0 0 0 0 0 0 0
Figure 5-18. XGATE Register 7 (XGR7)
Read: In debug mode if unsecured Write: In debug mode if unsecured
Table 5-15. XGR7 Field Descriptions
Field 15–0 XGR7[15:0] Description XGATE Register 7 — The RISC core’s register 7
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 229
Chapter 5 XGATE (S12XGATEV2)
5.4
Functional Description
The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories and peripherals (see Figure 5-1). The RISC processor always remains in an idle state until it is triggered by an XGATE request. Then it executes a code sequence that is associated with the request and optionally triggers an interrupt to the S12X_CPU upon completion. Code sequences are not interruptible. A new XGATE request can only be serviced when the previous sequence is finished and the RISC core becomes idle. The XGATE module also provides a set of hardware semaphores which are necessary to ensure data consistency whenever RAM locations or peripherals are shared with the S12X_CPU. The following sections describe the components of the XGATE module in further detail.
5.4.1
XGATE RISC Core
The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit manipulations, and simple arithmetic operations (see Section 5.8, “Instruction Set”). It is able to access the MCU’s internal memories and peripherals without blocking these resources from the S12X_CPU1. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core will be stalled until the resource becomes available again1. The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC core can perform up to two RAM accesses per S12X_CPU bus cycle. Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU cycle can not be exceeded. The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral modules or by software.
5.4.2
Programmer’s Model
Register Block
15 15 15 15 15 15 15 15
Program Counter
0 0 0 0 0 0 0 0 15
R7 R6 R5 R4 R3 R2
PC
0
Condition Code Register NZVC 3210
R1(Variable Pointer) R0 = 0
Figure 5-19. Programmer’s Model
1. With the exception of PRR registers (see Section “S12X_MMC”). MC9S12XHZ512 Data Sheet, Rev. 1.03 230 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
The programmer’s model of the XGATE RISC core is shown in Figure 5-19. The processor offers a set of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional eighth register (R0) is tied to the value “$0000”. Register R1 has an additional functionality. It is preloaded with the initial variable pointer of the channel’s service request vector (see Figure 5-20). The initial content of the remaining general purpose registers is undefined. The 16 bit program counter allows the addressing of a 64 kbyte address space. The condition code register contains four bits: the sign bit (S), the zero flag (Z), the overflow flag (V), and the carry bit (C). The initial content of the condition code register is undefined.
5.4.3
Memory Map
The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed information. The XGATE vector block assigns a start address and a variable pointer to each XGATE channel. Its position in the XGATE memory map can be adjusted through the XGVBR register (see Section 5.3.1.3, “XGATE Vector Base Address Register (XGVBR)”). Figure 5-20 shows the layout of the vector block. Each vector consists of two 16 bit words. The first contains the start address of the service routine. This value will be loaded into the program counter before a service routine is executed. The second word is a pointer to the service routine’s variable space. This value will be loaded into register R1 before a service routine is executed.
XGVBR
+$0000 unused
Code
+$0024 Channel $09 Initial Program Counter Channel $09 Initial Variable Pointer +$0028 Channel $0A Initial Program Counter Channel $0A Initial Variable Pointer +$002C Channel $0B Initial Program Counter Channel $0B Initial Variable Pointer +$0030 Channel $0C Initial Program Counter Channel $0C Initial Variable Pointer
Variables
Code
+$01E0
Channel $78 Initial Program Counter Channel $78 Initial Variable Pointer
Variables
Figure 5-20. XGATE Vector Block
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 231
Chapter 5 XGATE (S12XGATEV2)
5.4.4
Semaphores
The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism to protect system resources that are shared between two concurrent threads of program execution; one thread running on the S12X_CPU and one running on the XGATE RISC core. Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore register (XGSEM, see Section 5.3.1.6, “XGATE Semaphore Register (XGSEM)”). The RISC core does this through its SSEM and CSEM instructions. Figure 5-21 illustrates the valid state transitions.
%1 ⇒ XGSEM SSEM Instruction CSEM Instruction %1 ⇒ XGSEM %0 ⇒ XGSEM SSEM Instruction
LOCKED BY S12X_CPU
LOCKED BY XGATE
M SE XG M ⇒ SE 0 . % EM str XG r ⇒ o GS In XM 1 % ⇒E 1 SS % nd a
UNLOCKED
%0 ⇒ XGSEM CSEM Instruction Figure 5-21. Semaphore State Transitions
MC9S12XHZ512 Data Sheet, Rev. 1.03 232 Freescale Semiconductor
In CS st E ru M ct In SS io st E n ru M ct io n
Chapter 5 XGATE (S12XGATEV2)
Figure 5-22 gives an example of the typical usage of the XGATE hardware semaphores. Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core. They both have a critical section of code that accesses the same system resource. To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown.
S12X_CPU
......... %1 ⇒ XGSEMx XGSEM ≡ %1?
XGATE
......... SSEM
BCC?
critical code sequence
critical code sequence
XGSEM ⇒ %0 .........
CSEM .........
Figure 5-22. Algorithm for Locking and Releasing Semaphores
5.4.5
Software Error Detection
The XGATE module will immediately terminate program execution after detecting an error condition caused by erratic application code. There are three error conditions: • Execution of an illegal opcode • Illegal vector or opcode fetches • Illegal load or store accesses All opcodes which are not listed in section Section 5.8, “Instruction Set” are illegal opcodes. Illegal vector and opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the S12X_MMC Section for a detailed information.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 233
Chapter 5 XGATE (S12XGATEV2)
5.5
5.5.1
Interrupts
Incoming Interrupt Requests
XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the SoC Guide.
5.5.2
Outgoing Interrupt Requests
There are three types of interrupt requests which can be triggered by the XGATE module: 5. Channel interrupts For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector (XGIF, see Section 5.3.1.4, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to the S12X_CPU when the XGATE has completed one of its tasks. 6. Software triggers Software triggers are interrupt flags, which can be set and cleared by software (see Section 5.3.1.5, “XGATE Software Trigger Register (XGSWT)”). They are typically used to trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software. 7. Software error interrupt The software error interrupt signals to the S12X_CPU the detection of an error condition in the XGATE application code (see Section 5.4.5, “Software Error Detection”). All XGATE interrupts can be disabled by the XGIE bit in the XGATE module control register (XGMCTL, see Section 5.3.1.1, “XGATE Control Register (XGMCTL)”).
5.6
Debug Mode
The XGATE debug mode is a feature to allow debugging of application code.
5.6.1
Debug Features
In debug mode the RISC core will be halted and the following debug features will be enabled: • Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)1 All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue program execution with the modified register values.
1. Only possible if MCU is unsecured
MC9S12XHZ512 Data Sheet, Rev. 1.03 234 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
•
•
Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly. Write accesses to the XGCHID register Three operations can be performed by writing to the XGCHID register: – Change of channel ID If a non-zero value is written to the XGCHID while a thread is active (XGCHID ≠ $00), then the current channel ID will be changed without any influence on the program counter or the other RISC core registers. – Start of a thread If a non-zero value is written to the XGCHID while the XGATE is idle (XGCHID = $00), then the thread that is associated with the new channel ID will be executed upon leaving debug mode. – Termination of a thread If zero is written to the XGCHID while a thread is active (XGCHID ≠ $00), then the current thread will be terminated and the XGATE will become idle.
5.6.2
Entering Debug Mode
Debug mode can be entered in four ways: 1. Setting XGDBG to "1" Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter debug mode upon completion of the current instruction. NOTE After writing to the XGDBG bit the XGATE will not immediately enter debug mode. Depending on the instruction that is executed at this time there may be a delay of several clock cycles. The XGDBG will read "0" until debug mode is entered. 2. Software breakpoints XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A software breakpoint is set by replacing an instruction of the program code with the "BRK" instruction. As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode. Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the "BRK" instruction. The other RISC core registers will hold the result of the previous instruction. To resume program execution, the "BRK" instruction must be replaced by the original instruction before leaving debug mode.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 235
Chapter 5 XGATE (S12XGATEV2)
3. Tagged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the tagged instruction. The other RISC core registers will hold the result of the previous instruction. 4. Forced Breakpoints Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion of the current instruction.
5.6.3
Leaving Debug Mode
Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been cleared in debug mode), program execution will resume at the value of XGPC.
5.7
Security
In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug features have been made. These are: • Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device • Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device • Single stepping is not possible on a secured device
5.8
5.8.1
Instruction Set
Addressing Modes
For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all operations must have one of the eight general purpose registers R0 … R7 as their source as well their destination. All word accesses must work with a word aligned address, that is A[0] = 0!
MC9S12XHZ512 Data Sheet, Rev. 1.03 236 Freescale Semiconductor
Chapter 5 XGATE (S12XGATEV2)
5.8.1.1
Naming Conventions
Destination register, allowed range is R0–R7 Low byte of the destination register, bits [7:0] High byte of the destination register, bits [15:8] Source register, allowed range is R0–R7 Low byte of the source register, bits [7:0] High byte of the source register, bits[15:8] Base register for indexed addressing modes, allowed range is R0–R7 Offset register for indexed addressing modes with register offset, allowed range is R0–R7 Offset register for indexed addressing modes with register offset and post-increment, Allowed range is R0–R7 (R0+ is equivalent to R0) Offset register for indexed addressing modes with register offset and pre-decrement, Allowed range is R0–R7 (–R0 is equivalent to R0)
RD RD.L RD.H RS, RS1, RS2 RS.L, RS1.L, RS2.L RS.H, RS1.H, RS2.H RB RI RI+
–RI
NOTE Even though register R1 is intended to be used as a pointer to the variable segment, it may be used as a general purpose data register as well. Selecting R0 as destination register will discard the result of the instruction. Only the condition code register will be updated
5.8.1.2
Inherent Addressing Mode (INH)
Instructions that use this addressing mode either have no operands or all operands are in internal XGATE registers:. Examples
BRK RTS
5.8.1.3
Immediate 3-Bit Wide (IMM3)
Operands for immediate mode instructions are included in the instruction stream and are fetched into the instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an immediate addressing mode operand. This address mode is used for semaphore instructions. Examples:
CSEM SSEM #1 #3 ; Unlock semaphore 1 ; Lock Semaphore 3
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 237
Chapter 5 XGATE (S12XGATEV2)
5.8.1.4
Immediate 4 Bit Wide (IMM4)
The 4 bit wide immediate addressing mode is supported by all shift instructions. RD = RD ∗ imm4 Examples:
LSL LSR R4,#1 R4,#3 ; R4 = R4 > 3; shift register R4 by 3 bits to the right
5.8.1.5
Immediate 8 Bit Wide (IMM8)
The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP). RD = RD ∗ imm8 Examples:
ADDL SUBL LDH CMPL R1,#1 R2,#2 R3,#3 R4,#4 ; ; ; ; adds an 8 bit value to register R1 subtracts an 8 bit value from register R2 loads an 8 bit immediate into the high byte of Register R3 compares the low byte of register R4 with an immediate value
5.8.1.6
Immediate 16 Bit Wide (IMM16)
The 16 bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode. RD = RD ∗ imm16 Examples:
LDW ADD R4,#$1234 R4,#$5678 ; translated to LDL R4,#$34; LDH R4,#$12 ; translated to ADDL R4,#$78; ADDH R4,#$56
5.8.1.7
Monadic Addressing (MON)
In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)), the target (RD = f()), or both source and target of the operation (RD = f(RD)). Examples:
JAL SIF R1 R2 ; PC = R1, R1 = PC+2 ; Trigger IRQ associated with the channel number in R2.L
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5.8.1.8
Dyadic Addressing (DYA)
In this mode the result of an operation between two registers is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register, only the condition code flags are updated. This addressing mode is used only for shift operations with a variable shift value Examples:
LSL LSR R4,R5 R4,R5 ; R4 = R4 > R5
5.8.1.9
Triadic Addressing (TRI)
In this mode the result of an operation between two or three registers is stored into a third one. RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code flags are updated. This addressing mode is used for all arithmetic and logical operations. Examples:
ADC SUB R5,R6,R7 R5,R6,R7 ; R5 = R6 + R7 + Carry ; R5 = R6 - R7
5.8.1.10
Relative Addressing 9-Bit Wide (REL9)
A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for conditional branch instructions. Examples:
BCC BEQ REL9 REL9 ; PC = PC + 2 + (REL9 R2;arithmetic shift register R4 right by the amount ; of bits contained in R2[3:0].
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5.8.2.5
Bit Field Operations
This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions are very useful to extract, insert, clear, set or toggle portions of a 16 bit word.
15
W4 O4 5 2 W4=3, O4=2
RS2 0 RS1 Bit Field Extract
Bit Field Insert 15 3 0 RD
Figure 5-23. Bit Field Addressing
BFEXT R3,R4,R5 ; R5: W4 bits offset O4, will be extracted from R4 into R3
5.8.2.6
Special Instructions for DMA Usage
The XGATE offers a number of additional instructions for flag manipulation, program flow control and debugging: 1. SIF: Set a channel interrupt flag 2. SSEM: Test and set a hardware semaphore 3. CSEM: Clear a hardware semaphore 4. BRK: Software breakpoint 5. NOP: No Operation 6. RTS: Terminate the current thread
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5.8.3
Cycle Notation
Table 5-16 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.
Table 5-16. Access Detail Notation V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle r — 8 bit data read: lasts for at least one RISC core cycle R — 16 bit data read: lasts for at least one RISC core cycle w — 8 bit data write: lasts for at least one RISC core cycle W — 16 bit data write: lasts for at least one RISC core cycle A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles f — Free cycle: no read or write, lasts for one RISC core cycles Special Cases PP/P — Branch: PP if branch taken, P if not
5.8.4
Thread Execution
When the RISC core is triggered by an interrupt request (see Figure 5-1) it first executes a vector fetch sequence which performs three bus accesses: 1. A V-cycle to fetch the initial content of the program counter. 2. A V-cycle to fetch the initial content of the data segment pointer (R1). 3. A P-cycle to load the initial opcode. Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If further interrupt requests are pending after a thread has been terminated, a new vector fetch will be performed. Otherwise the RISC core will idle until a new interrupt request is received. A thread can not be interrupted by an interrupt request.
5.8.5
Instruction Glossary
This section describes the XGATE instruction set in alphabetical order.
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ADC
Operation RS1 + RS2 + C ⇒ RD
Add with Carry
ADC
Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions. Example:
ADC ADC BCC R6,R2,R2 R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2 ; conditional branch on 32 bit addition
CCR Effects
N ∆ N: Z: V: C: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000 and Z was set before this operation; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new
Code and CPU Cycles
Source Form ADC RD, RS1, RS2 Address Mode TRI 0 0 0 1 1 Machine Code RD RS1 RS2 1 1 Cycles P
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ADD
Operation
Add without Carry
ADD
RS1 + RS2 ⇒ RD RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8]) Performs a 16 bit addition and stores the result in the destination register RD. CCR Effects
N ∆ N: Z: V: Z ∆ V ∆ C ∆
C:
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations. Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations.
Code and CPU Cycles
Source Form ADD RD, RS1, RS2 ADD RD, #IMM16 Address Mode TRI IMM8 IMM8 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 Machine Code RD RD RD RS1 RS2 IMM16[7:0] IMM16[15:8] 1 0 Cycles P P P
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ADDH
Operation RD + IMM8:$00 ⇒ RD
Add Immediate 8 bit Constant (High Byte)
ADDH
Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for a 16 bit immediate addition. Example:
ADDL ADDH R2,#LOWBYTE R2,#HIGHBYTE ; R2 = R2 + 16 bit immediate
CCR Effects
N ∆ N: Z: V: C: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old & IMM8[7] & RD[15]new | RD[15]old & IMM8[7] & RD[15]new Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & IMM8[7] | RD[15]old & RD[15]new | IMM8[7] & RD[15]new
Code and CPU Cycles
Source Form ADDH RD, #IMM8 Address Mode IMM8 1 1 1 0 1 Machine Code RD IMM8 Cycles P
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ADDL
Operation RD + $00:IMM8 ⇒ RD
Add Immediate 8 bit Constant (Low Byte)
ADDL
Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition in conjunction with the ADDH instruction. CCR Effects
N ∆ N: Z: V: C: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise. RD[15]old & RD[15]new Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & RD[15]new
Code and CPU Cycles
Source Form ADDL RD, #IMM8 Address Mode IMM8 1 1 1 0 0 Machine Code RD IMM8 Cycles P
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AND
Operation
Logical AND
AND
RS1 & RS2 ⇒ RD RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD. Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result. CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Refer to ANDH instruction for #IMM16 operations. 0; cleared. Not affected.
Code and CPU Cycles
Source Form AND RD, RS1, RS2 AND RD, #IMM16 Address Mode TRI IMM8 IMM8 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 Machine Code RD RD RD RS1 RS2 IMM16[7:0] IMM16[15:8] 0 0 Cycles P P P
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ANDH
Operation RD.H & IMM8 ⇒ RD.H
Logical AND Immediate 8 bit Constant (High Byte)
ANDH
Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form ANDH RD, #IMM8 Address Mode IMM8 1 0 0 0 1 Machine Code RD IMM8 Cycles P
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ANDL
Operation RD.L & IMM8 ⇒ RD.L
Logical AND Immediate 8 bit Constant (Low Byte)
ANDL
Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form ANDL RD, #IMM8 Address Mode IMM8 1 0 0 0 0 Machine Code RD IMM8 Cycles P
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ASR
Operation
b15
Arithmetic Shift Right
ASR
C
n
RD
n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS is greater than 15. CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form ASR RD, #IMM4 ASR RD, RS Address Mode IMM4 DYA 0 0 0 0 0 0 0 0 1 1 Machine Code RD RD IMM4 RS 1 1 0 0 0 0 0 1 1 Cycles P P
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BCC
Operation
Branch if Carry Cleared (Same as BHS)
BCC
If C = 0, then PC + $0002 + (REL9 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to set bits.
15 7 W4 15 3 4 3 O4 0 RS1 Inverted Bit Field Insert 15 5 2 0 RD 0 RS2
W4=3, O4=2
CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form BFINSI RD, RS1, RS2 Address Mode TRI 0 1 1 1 0 Machine Code RD RS1 RS2 1 1 Cycles P
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BFINSX
Operation
Bit Field Insert and XNOR
BFINSX
!(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back io RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to toggle bits.
15 7 W4 15 3 4 3 O4 0 RS1 Bit Field Insert XNOR 15 5 2 0 RD 0 RS2
W4=3, O4=2
CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form BFINSX RD, RS1, RS2 Address Mode TRI 0 1 1 1 1 Machine Code RD RS1 RS2 1 1 Cycles P
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BGE
Operation Branch if RS1 ≥ RS2:
SUB BGE
Branch if Greater than or Equal to Zero
BGE
If N ^ V = 0, then PC + $0002 + (REL9 RS2:
SUB BGE R0,RS1,RS2 REL9
Branch if Greater than Zero
BGT
If Z | (N ^ V) = 0, then PC + $0002 + (REL9 RS2:
SUB BHI R0,RS1,RS2 REL9
Branch if Higher
BHI
If C | Z = 0, then PC + $0002 + (REL9 1) $C000
INIT_SCI
INIT_INT
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INIT_XGATE INIT_XGATE_BUSY_LOOP
;########################################### ;# INITIALIZE XGATE # ;########################################### MOVW #XGMCTL_CLEAR , XGMCTL;clear all XGMCTL bits TST BNE LDX LDD STD STD STD STD STD STD STD STD XGCHID ;wait until current thread is finished INIT_XGATE_BUSY_LOOP #XGIF #$FFFF 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ ;clear all channel interrupt flags
MOVW #XGATE_VECTORS_XG, XGVBR;set vector base register MOVW #$FF00, XGSWT ;clear all software triggers
INIT_XGATE_VECTAB_LOOP
;########################################### ;# INITIALIZE XGATE VECTOR TABLE # ;########################################### LDAA #128 ;build XGATE vector table LDY #XGATE_VECTORS MOVW #XGATE_DUMMY_ISR_XG, 4,Y+ DBNE A, INIT_XGATE_VECTAB_LOOP MOVW #XGATE_CODE_XG, RAM_START+(2*SCI_VEC) MOVW #XGATE_DATA_XG, RAM_START+(2*SCI_VEC)+2 ;########################################### ;# COPY XGATE CODE # ;########################################### LDX #XGATE_DATA_FLASH MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ CPX #XGATE_CODE_FLASH_END BLS COPY_XGATE_CODE_LOOP ;########################################### ;# START XGATE # ;########################################### MOVW #XGMCTL_ENABLE, XGMCTL;enable XGATE BRA * ;########################################### ;# DUMMY INTERRUPT SERVICE ROUTINE # ;########################################### RTI CPU XGATE
COPY_XGATE_CODE COPY_XGATE_CODE_LOOP
START_XGATE
DUMMY_ISR
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XGATE_DATA_FLASH XGATE_DATA_SCI XGATE_DATA_IDX XGATE_DATA_MSG
;########################################### ;# XGATE DATA # ;########################################### ALIGN 1 EQU * EQU *-XGATE_DATA_FLASH DW SCI_REGS ;pointer to SCI register space EQU *-XGATE_DATA_FLASH DB XGATE_DATA_MSG ;string pointer EQU *-XGATE_DATA_FLASH FCC "Hello World! ;ASCII string DB $0D ;CR ;########################################### ;# XGATE CODE # ;########################################### ALIGN 1 LDW R2,(R1,#XGATE_DATA_SCI);SCI -> R2 LDB R3,(R1,#XGATE_DATA_IDX);msg -> R3 LDB R4,(R1,R3+) ;curr. char -> R4 STB R3,(R1,#XGATE_DATA_IDX);R3 -> idx LDB R0,(R2,#(SCISR1-SCI_REGS));initiate SCI transmit STB R4,(R2,#(SCIDRL-SCI_REGS));initiate SCI transmit CMPL R4,#$0D BEQ XGATE_CODE_DONE RTS LDL R4,#$00 ;disable SCI interrupts STB R4,(R2,#(SCICR2-SCI_REGS)) LDL R3,#XGATE_DATA_MSG;reset R3 STB R3,(R1,#XGATE_DATA_IDX) RTS EQU (XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
XGATE_CODE_FLASH
XGATE_CODE_DONE
XGATE_CODE_FLASH_END XGATE_DUMMY_ISR_XG
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Chapter 6 Security (S12X9SECV2)
6.1 Introduction
This specification describes the function of the security mechanism in the S12X chip family (S12X9SECV2).
6.1.1
Features
The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access to a programming routine that updates parameters stored in another section of the Flash memory. The security features of the S12X chip family (in secure mode) are: • Protect the contents of non-volatile memories (Flash, EEPROM) • Execution of NVM commands is restricted • Disable access to internal memory via background debug module (BDM) • Disable access to internal Flash/EEPROM in expanded modes • Disable debugging features for CPU and XGATE Table 6-1 gives an overview over availability of security relevant features in unsecure and secure modes.
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Table 6-1. Features Availability in Unsecure and Secure Modes
Unsecure Mode NS Flash Array Access EEPROM Array Access NVM Commands BDM DBG Module Trace XGATE Debugging External Bus Interface Internal status visible multiplexed on external bus Internal accesses visible on external bus
1
Secure Mode ST ✔1 ✔ ✔ ✔ ✔ ✔ ✔ — NS ✔ ✔ ✔2 — — — — — SS ✔ ✔ ✔2 ✔3 — — — — NX — — ✔2 — — — ✔ — ES — — ✔2 — — — ✔ ✔ EX — — ✔2 — — — ✔ ✔ ST — — ✔2 — — — ✔ —
SS ✔ ✔ ✔ ✔ ✔ ✔ — —
NX ✔1 ✔ ✔2 ✔ ✔ ✔ ✔ —
ES ✔1 ✔ ✔2 ✔ ✔ ✔ ✔ ✔
EX ✔1 ✔ ✔2 ✔ ✔ ✔ ✔ ✔
✔ ✔ ✔2 ✔ ✔ ✔ — —
—
—
—
—
—
✔
—
—
—
—
—
✔
Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of the ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for detailed information. 2 Restricted NVM command set only. Please refer to the FTX/EETX block guides for detailed information. 3 BDM hardware commands restricted to peripheral registers only.
6.1.2 6.1.3
Modes of Operation Securing the Microcontroller
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down. The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence.
7 6 5 4 3 2 1 0
0xFF0F
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
Figure 6-1. Flash Options/Security Byte
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Chapter 6 Security (S12X9SECV2)
The meaning of the bits KEYEN[1:0] is shown in Table 6-2. Please refer to Section 6.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information.
Table 6-2. Backdoor Key Access Enable Bits
KEYEN[1:0] 00 01 10 11 Backdoor Key Access Enabled 0 (disabled) 0 (disabled) 1 (enabled) 0 (disabled)
The meaning of the security bits SEC[1:0] is shown in Table 6-3. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
Table 6-3. Security Bits
SEC[1:0] 00 01 10 11 Security State 1 (secured) 1 (secured) 0 (unsecured) 1 (secured)
NOTE Please refer to the Flash block guide (FTX) for actual security configuration (in section “Flash Module Security”).
6.1.4
Operation of the Secured Microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. Secured operation has the following effects on the microcontroller:
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6.1.4.1
• • • •
Normal Single Chip Mode (NS)
Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled.
6.1.4.2
• • • • •
Special Single Chip Mode (SS)
BDM firmware commands are disabled. BDM hardware commands are restricted to the register space. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled.
Special single chip mode means BDM is active after reset. The availability of BDM firmware commands depends on the security state of the device. The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked.
6.1.4.3
• • • • • •
Expanded Modes (NX, ES, EX, and ST)
BDM operation is completely disabled. Internal Flash memory and EEPROM are disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 340 Freescale Semiconductor
Chapter 6 Security (S12X9SECV2)
6.1.5
Unsecuring the Microcontroller
Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes)
6.1.5.1
Unsecuring the MCU Using the Backdoor Key Access
In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that: • The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been programmed to a valid value. • The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. • In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). It is not possible to download the backdoor keys using background debug mode. The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF.
6.1.5.2
Backdoor Key Access Sequence
These are the necessary steps for a successful backdoor key access sequence: 1. Set the KEYACC bit in the Flash configuration register FCNFG. 2. Write the first 16-bit word of the backdoor key to 0xFF00 (0x7F_FF00). 3. Write the second 16-bit word of the backdoor key to 0xFF02 (0x7F_FF02). 4. Write the third 16-bit word of the backdoor key to 0xFF04 (0x7F_FF04). 5. Write the fourth 16-bit word of the backdoor key to 0xFF06 (0x7F_FF06). 6. Clear the KEYACC bit in the Flash Configuration register FCNFG. NOTE Flash cannot be read while KEYACC is set. Therefore the code for the backdoor key access sequence must execute from RAM.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 341
Chapter 6 Security (S12X9SECV2)
If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will be forced to the unsecured state (‘10’). The contents of the Flash options/security byte are not changed by this procedure, and so the microcontroller will revert to the secure state after the next reset unless further action is taken as detailed below. If any of the four 16-bit words does not match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will remain secured.
6.1.6
Reprogramming the Security Bits
In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that: • The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte. • The Flash sector containing the Flash options/security byte is not protected.
6.1.7
Complete Memory Erase (Special Modes)
The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks. When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset.
MC9S12XHZ512 Data Sheet, Rev. 1.03 342 Freescale Semiconductor
Chapter 6 Security (S12X9SECV2)
Special single chip erase and unsecure sequence: 1. Reset into special single chip mode. 2. Write an appropriate value to the ECLKDIV register for correct timing. 3. Write 0xFF to the EPROT register to disable protection. 4. Write 0x30 to the ESTAT register to clear the PVIOL and ACCERR bits. 5. Write 0x0000 to the EDATA register (0x011A–0x011B). 6. Write 0x0000 to the EADDR register (0x0118–0x0119). 7. Write 0x41 (mass erase) to the ECMD register. 8. Write 0x80 to the ESTAT register to clear CBEIF. 9. Write an appropriate value to the FCLKDIV register for correct timing. 10. Write 0x00 to the FCNFG register to select Flash block 0. 11. Write 0x10 to the FTSTMOD register (0x0102) to set the WRALL bit, so the following writes affect all Flash blocks. 12. Write 0xFF to the FPROT register to disable protection. 13. Write 0x30 to the FSTAT register to clear the PVIOL and ACCERR bits. 14. Write 0x0000 to the FDATA register (0x010A–0x010B). 15. Write 0x0000 to the FADDR register (0x0108–0x0109). 16. Write 0x41 (mass erase) to the FCMD register. 17. Write 0x80 to the FSTAT register to clear CBEIF. 18. Wait until all CCIF flags are set. 19. Reset back into special single chip mode. 20. Write an appropriate value to the FCLKDIV register for correct timing. 21. Write 0x00 to the FCNFG register to select Flash block 0. 22. Write 0xFF to the FPROT register to disable protection. 23. Write 0xFFBE to Flash address 0xFF0E. 24. Write 0x20 (program) to the FCMD register. 25. Write 0x80 to the FSTAT register to clear CBEIF. 26. Wait until the CCIF flag in FSTAT is are set. 27. Reset into any mode.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 343
Chapter 6 Security (S12X9SECV2)
MC9S12XHZ512 Data Sheet, Rev. 1.03 344 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.1 Introduction
This specification describes the function of the clocks and reset generator (CRG).
7.1.1
Features
The main features of this block are: • Phase locked loop (PLL) frequency multiplier — Reference divider — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Interrupt request on entry or exit from locked condition — Self clock mode in absence of reference clock • System clock generator — Clock quality check — User selectable fast wake-up from Stop in self-clock mode for power saving and immediate program execution — Clock switch for either oscillator or PLL based system clocks • Computer operating properly (COP) watchdog timer with time-out clear window • System reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 345
Chapter 7 Clocks and Reset Generator (CRGV6)
7.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required, the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value. • Wait mode In this mode, the PLL can be disabled automatically depending on the PLLSEL bit in the CLKSEL register. • Stop mode Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode (PSTP = 0) and pseudo stop mode (PSTP = 1). — Full stop mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. — Pseudo stop mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set, the COP and RTI will continue to run, or else they remain frozen. • Self clock mode Self clock mode will be entered if the clock monitor enable bit (CME) and the self clock mode enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of clock. As soon as self clock mode is entered, the CRG starts to perform a clock quality check. Self clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). Self clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions.
MC9S12XHZ512 Data Sheet, Rev. 1.03 346 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.1.3
Block Diagram
Figure 7-1 shows a block diagram of the CRG.
Illegal Address Reset Power on Reset Low Voltage Reset
S12X_MMC Voltage Regulator
CRG
RESET Clock Monitor CM fail COP Timeout
Reset Generator Clock Quality Checker COP RTI
System Reset
XCLKS EXTAL XTAL
OSCCLK
Oscillator
Bus Clock Core Clock Oscillator Clock
Registers
XFC VDDPLL VSSPLL PLLCLK
PLL
Clock and Reset Control
Real Time Interrupt PLL Lock Interrupt Self Clock Mode Interrupt
Figure 7-1. CRG Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 347
Chapter 7 Clocks and Reset Generator (CRGV6)
7.2
External Signal Description
This section lists and describes the signals that connect off chip.
7.2.1
VDDPLL and VSSPLL — Operating and Ground Voltage Pins
These pins provide operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, VDDPLL and VSSPLL must be connected to properly.
7.2.2
XFC — External Loop Filter Pin
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter that eliminates the VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. Refer to the device specification for calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied to VDDPLL.
VDDPLL
CS MCU RS XFC
CP
Figure 7-2. PLL Loop Filter Connections
7.2.3
RESET — Reset Pin
RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has been triggered.
7.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the CRG.
MC9S12XHZ512 Data Sheet, Rev. 1.03 348 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.1
Module Memory Map
Table 7-1. CRG Memory Map
Address Offset 0x_00 0x_01 0x_02 0x_03 0x_04 0x_05 0x_06 0x_07 0x_08 0x_09 0x_0A 0x_0B
1 2
Table 7-1 gives an overview on all CRG registers.
Use CRG Synthesizer Register (SYNR) CRG Reference Divider Register (REFDV) CRG Test Flags Register (CTFLG) CRG Flags Register (CRGFLG) CRG Interrupt Enable Register (CRGINT) CRG Clock Select Register (CLKSEL) CRG PLL Control Register (PLLCTL) CRG RTI Control Register (RTICTL) CRG COP Control Register (COPCTL) CRG Force and Bypass Test Register CRG Test Control Register (FORBYP)2
1
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(CTCTL)3
CRG COP Arm/Timer Reset (ARMCOP)
CTFLG is intended for factory test purposes only. FORBYP is intended for factory test purposes only. 3 CTCTL is intended for factory test purposes only.
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 349
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2
Register Descriptions
This section describes in address order all the CRG registers and their individual bits.
Register Name SYNR R W REFDV R W CTFLG R W CRGFLG R W CRGINT R W CLKSEL R W PLLCTL R W RTICTL R W COPCTL R W FORBYP R W CTCTL R W ARMCOP R W 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 1 0 0 0 0 0 0 0 RTIF PORF LVRF 0 LOCKIF LOCK TRACK SCMIF SCM 0 0 0 0 Bit 7 0 6 0 5 SYN5 4 SYN4 3 SYN3 2 SYN2 1 SYN1 Bit 0 SYN0
REFDV5 0
REFDV4 0
REFDV3 0
REFDV2 0
REFDV1 0
REFDV0 0
RTIE
ILAF
LOCKIE 0
0
0
SCMIE
0
PLLSEL
PSTP
0
PLLWAI
0
RTIWAI
COPWAI
CME
PLLON
AUTO
ACQ
FSTWKP
PRE
PCE
SCME
RTDEC
RTR6
RTR5 0 WRTMASK 0
RTR4 0
RTR3 0
RTR2
RTR1
RTR0
WCOP 0
RSBCK 0
CR2 0
CR1 0
CR0 0
0
0
= Unimplemented or Reserved
Figure 7-3. S12CRGV6 Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.03 350 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.1
CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (fSCM).
( SYNR + 1 ) PLLCLK = 2xOSCCLKx ----------------------------------( REFDV + 1 )
NOTE If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2 Bus Clock must not exceed the maximum operating system frequency.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
SYN5 0
SYN4 0
SYN3 0
SYN2 0
SYN1 0
SYN0 0
= Unimplemented or Reserved
Figure 7-4. CRG Synthesizer Register (SYNR)
Read: Anytime Write: Anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit.
7.3.2.2
CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
REFDV5 0
REFDV4 0
REFDV3 0
REFDV2 0
REFDV1 0
REFDV0 0
= Unimplemented or Reserved
Figure 7-5. CRG Reference Divider Register (REFDV)
Read: Anytime Write: Anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 351
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.3
Reserved Register (CTFLG)
This register is reserved for factory testing of the CRG module and is not available in normal modes.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 7-6. Reserved Register (CTFLG)
Read: Always reads 0x_00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRG fucntionality.
7.3.2.4
CRG Flags Register (CRGFLG)
This register provides CRG status bits and flags.
7 6 5 4 3 2 1 0
R W Reset
RTIF 0
PORF
1
LVRF
2
LOCKIF 0
LOCK 0
TRACK 0
SCMIF 0
SCM 0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved
Figure 7-7. CRG Flags Register (CRGFLG)
Read: Anytime Write: Refer to each bit for individual write conditions
Table 7-2. CRGFLG Field Descriptions
Field 7 RTIF Description Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power on reset has not occurred. 1 Power on reset has occurred.
6 PORF
MC9S12XHZ512 Data Sheet, Rev. 1.03 352 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-2. CRGFLG Field Descriptions (continued)
Field 5 LVRF Description Low Voltage Reset Flag — If low voltage reset feature is not available (see device specification) LVRF always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self clock mode. Writes have no effect. 0 PLL VCO is not within the desired tolerance of the target frequency. 1 PLL VCO is within the desired tolerance of the target frequency. Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self clock mode. Writes have no effect. 0 Acquisition mode status. 1Tracking mode status. Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE = 1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect. 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency fSCM.
4 LOCKIF
3 LOCK
2 TRACK
1 SCMIF
0 SCM
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 353
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.5
CRG Interrupt Enable Register (CRGINT)
This register enables CRG interrupt requests.
7 6 5 4 3 2 1 0
R W Reset
RTIE 0
ILAF
1
0 0
LOCKIE 0
0 0
0 0
SCMIE 0
0 0
1. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset. = Unimplemented or Reserved
Figure 7-8. CRG Interrupt Enable Register (CRGINT)
Read: Anytime Write: Anytime
Table 7-3. CRGINT Field Descriptions
Field 7 RTIE 6 ILAF Description Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Illegal address reset has not occurred. 1 Illegal address reset has occurred. Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Self ClockMmode Interrupt Enable Bit 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set.
4 LOCKIE 1 SCMIE
MC9S12XHZ512 Data Sheet, Rev. 1.03 354 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.6
CRG Clock Select Register (CLKSEL)
This register controls CRG clock selection. Refer to Figure 7-17 for more details on the effect of each bit.
7 6 5 4 3 2 1 0
R W Reset
PLLSEL 0
PSTP 0
0 0
0 0
PLLWAI 0
0 0
RTIWAI 0
COPWAI 0
= Unimplemented or Reserved
Figure 7-9. CRG Clock Select Register (CLKSEL)
Read: Anytime Write: Refer to each bit for individual write conditions
Table 7-4. CLKSEL Field Descriptions
Field 7 PLLSEL Description PLL Select Bit — Write anytime. Writing a1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has no effect This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters self clock mode, Stop mode or wait mode with PLLWAI bit set. 0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2). 1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2). Pseudo Stop Bit Write: Anytime This bit controls the functionality of the oscillator during stop mode. 0 Oscillator is disabled in stop mode. 1 Oscillator continues to run in stop mode (pseudo stop). Note: Pseudo stop mode allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption. PLL Stops in Wait Mode Bit Write: Anytime If PLLWAI is set, the CRG will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during wait mode, but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be set manually if PLL clock is required. While the PLLWAI bit is set, the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting wait mode. 0 PLL keeps running in wait mode. 1 PLL stops in wait mode. RTI Stops in Wait Mode Bit Write: Anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode. COP Stops in Wait Mode Bit Normal modes: Write once Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP counter whenever the part goes into wait mode.
6 PSTP
3 PLLWAI
1 RTIWAI
0 COPWAI
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 355
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.7
CRG PLL Control Register (PLLCTL)
This register controls the PLL functionality.
7 6 5 4 3 2 1 0
R W Reset
CME 1
PLLON 1
AUTO 1
ACQ 1
FSTWKP 0
PRE 0
PCE 0
SCME 1
Figure 7-10. CRG PLL Control Register (PLLCTL)
Read: Anytime Write: Refer to each bit for individual write conditions
Table 7-5. PLLCTL Field Descriptions
Field 7 CME Description Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self clock mode. Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality, this could cause unpredictable operation of the MCU! Note: In stop mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss of external clock will not be detected. Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor is disabled independently of the CME bit setting and any loss of external clock will not be detected. Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self clock mode, the PLL is turned on, but the PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1. 0 PLL is turned off. 1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically. Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI = 1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. Acquisition Bit Write anytime. If AUTO=1 this bit has no effect. 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If self-clock mode is disabled (SCME = 0) this bit has no effect. 0 Fast wake-up from full stop mode is disabled. 1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately resume operation i self-clock mode (see Section 7.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set. The system will remain in self-clock mode with oscillator and clock monitor disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to OSCCLK. The SCMIF flag will be set. See application examples in Figure 7-23 and Figure 7-24.
6 PLLON
5 AUTO
4 ACQ
3 FSTWKP
MC9S12XHZ512 Data Sheet, Rev. 1.03 356 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-5. PLLCTL Field Descriptions (continued)
Field 2 PRE Description RTI Enable during Pseudo Stop Bit — PRE enables the RTI during pseudo stop mode. Write anytime. 0 RTI stops running during pseudo stop mode. 1 RTI continues running during pseudo stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set. COP Enable during Pseudo Stop Bit — PCE enables the COP during pseudo stop mode. Write anytime. 0 COP stops running during pseudo stop mode 1 COP continues running during pseudo stop mode Note: If the PCE bit is cleared, the COP dividers will go static while pseudo stop mode is active. The COP dividers will not initialize like in wait mode with COPWAI bit set. Self Clock Mode Enable Bit Normal modes: Write once Special modes: Write anytime SCME can not be cleared while operating in self clock mode (SCM = 1). 0 Detection of crystal clock failure causes clock monitor reset (see Section 7.5.2, “Clock Monitor Reset”). 1 Detection of crystal clock failure forces the MCU in self clock mode (see Section 7.4.2.2, “Self Clock Mode”).
1 PCE
0 SCME
7.3.2.8
CRG RTI Control Register (RTICTL)
This register selects the timeout period for the real time interrupt.
7 6 5 4 3 2 1 0
R W Reset
RTDEC 0
RTR6 0
RTR5 0
RTR4 0
RTR3 0
RTR2 0
RTR1 0
RTR0 0
Figure 7-11. CRG RTI Control Register (RTICTL)
Read: Anytime Write: Anytime NOTE A write to this register initializes the RTI counter.
Table 7-6. RTICTL Field Descriptions
Field 7 RTDEC 6–4 RTR[6:4] 3–0 RTR[3:0] Description Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values. 0 Binary based divider value. See Table 7-7 1 Decimal based divider value. See Table 7-8 Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 7-7 and Table 7-8. Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity.Table 7-7 and Table 7-8 show all possible divide values selectable by the RTICTL register. The source clock for the RTI is OSCCLK.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 357
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-7. RTI Frequency Divide Rates for RTDEC = 0
RTR[6:4] = RTR[3:0] 000 (OFF) OFF* OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 001 (210) 210 2x210 3x210 4x210 5x210 6x210 7x210 8x210 9x210 10x210 11x210 12x210 13x210 14x210 15x210 16x210 010 (211) 211 2x211 3x211 4x211 5x211 6x211 7x211 8x211 9x211 10x211 11x211 12x211 13x211 14x211 15x211 16x211 011 (212) 212 2x212 3x212 4x212 5x212 6x212 7x212 8x212 9x212 10x212 11x212 12x212 13x212 14x212 15x212 16x212 100 (213) 213 2x213 3x213 4x213 5x213 6x213 7x213 8x213 9x213 10x213 11x213 12x213 13x213 14x213 15x213 16x213 101 (214) 214 2x214 3x214 4x214 5x214 6x214 7x214 8x214 9x214 10x214 11x214 12x214 13x214 14x214 15x214 16x214 110 (215) 215 2x215 3x215 4x215 5x215 6x215 7x215 8x215 9x215 10x215 11x215 12x215 13x215 14x215 15x215 16x215 111 (216) 216 2x216 3x216 4x216 5x216 6x216 7x216 8x216 9x216 10x216 11x216 12x216 13x216 14x216 15x216 16x216
0000 (÷1) 0001 (÷2) 0010 (÷3) 0011 (÷4) 0100 (÷5) 0101 (÷6) 0110 (÷7) 0111 (÷8) 1000 (÷9) 1001 (÷10) 1010 (÷11) 1011 (÷12) 1100 (÷13) 1101 (÷14) 1110 (÷15) 1111 (÷16)
* Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
MC9S12XHZ512 Data Sheet, Rev. 1.03 358 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-8. RTI Frequency Divide Rates for RTDEC = 1
RTR[6:4] = RTR[3:0] 000 (1x103) 1x103 2x103 3x103 4x103 5x103 6x103 7x103 8x103 9x103 10 x103 11 x103 12x103 13x103 14x103 15x103 16x103 001 (2x103) 2x103 4x103 6x103 8x103 10x103 12x103 14x103 16x103 18x103 20x103 22x103 24x103 26x103 28x103 30x103 32x103 010 (5x103) 5x103 10x103 15x103 20x103 25x103 30x103 35x103 40x103 45x103 50x103 55x103 60x103 65x103 70x103 75x103 80x103 011 (10x103) 10x103 20x103 30x103 40x103 50x103 60x103 70x103 80x103 90x103 100x103 110x103 120x103 130x103 140x103 150x103 160x103 100 (20x103) 20x103 40x103 60x103 80x103 100x103 120x103 140x103 160x103 180x103 200x103 220x103 240x103 260x103 280x103 300x103 320x103 101 (50x103) 50x103 100x103 150x103 200x103 250x103 300x103 350x103 400x103 450x103 500x103 550x103 600x103 650x103 700x103 750x103 800x103 110 (100x103) 100x103 200x103 300x103 400x103 500x103 600x103 700x103 800x103 900x103 1x106 1.1x106 1.2x106 1.3x106 1.4x106 1.5x106 1.6x106 111 (200x103) 200x103 400x103 600x103 800x103 1x106 1.2x106 1.4x106 1.6x106 1.8x106 2x106 2.2x106 2.4x106 2.6x106 2.8x106 3x106 3.2x106
0000 (÷1) 0001 (÷2) 0010 (÷3) 0011 (÷4) 0100 (÷5) 0101 (÷6) 0110 (÷7) 0111 (÷8) 1000 (÷9) 1001 (÷10) 1010 (÷11) 1011 (÷12) 1100 (÷13) 1101 (÷14) 1110 (÷15) 1111 (÷16)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 359
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.9
CRG COP Control Register (COPCTL)
This register controls the COP (computer operating properly) watchdog.
7 6 5 4 3 2 1 0
R W Reset1
WCOP
RSBCK 0
0 WRTMASK 0
0 0
0 0
CR2
CR1
CR0
1. Refer to Device User Guide (Section: CRG) for reset values of WCOP, CR2, CR1, and CR0. = Unimplemented or Reserved
Figure 7-12. CRG COP Control Register (COPCTL)
Read: Anytime Write: 1. RSBCK: Anytime in special modes; write to “1” but not to “0” in all other modes 2. WCOP, CR2, CR1, CR0: — Anytime in special modes — Write once in all other modes Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. Writing WCOP to “0” has no effect, but counts for the “write once” condition. The COP time-out period is restarted if one these two conditions is true: 1. Writing a nonzero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0. or 2. Changing RSBCK bit from “0” to “1”.
Table 7-9. COPCTL Field Descriptions
Field 7 WCOP Description Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, 0x_55 can be written as often as desired. Once 0x_AA is written after the 0x_55, the time-out logic restarts and the user must wait until the next window before writing to ARMCOP. Table 7-10 shows the duration of this window for the seven available COP rates. 0 Normal COP operation 1 Window COP operation COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode.
6 RSBCK
MC9S12XHZ512 Data Sheet, Rev. 1.03 360 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-9. COPCTL Field Descriptions (continued)
Field 5 WRTMASK Description Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of WCOP and CR[2:0]. 0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL 1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL. (Does not count for “write once”.) COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 7-10). The COP time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register. While all of the following three conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest time-out period (2 24 cycles) in normal COP mode (Window COP mode disabled): 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in emulation or special modes
2–0 CR[1:0]
Table 7-10. COP Watchdog Rates1
CR2 0 0 0 0 1 1 1 1
1
CR1 0 0 1 1 0 0 1 1
CR0 0 1 0 1 0 1 0 1
OSCCLK Cycles to Time-out COP disabled 214 216 218 220 222 223 224
OSCCLK cycles are referenced from the previous COP time-out reset (writing 0x_55/0x_AA to the ARMCOP register)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 361
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.10
Reserved Register (FORBYP)
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 7-13. Reserved Register (FORBYP)
Read: Always read 0x_00 except in special modes Write: Only in special modes
7.3.2.11
Reserved Register (CTCTL)
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special test modes can alter the CRG’s functionality.
7 6 5 4 3 2 1 0
R W Reset
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 7-14. Reserved Register (CTCTL)
Read: always read 0x_80 except in special modes Write: only in special modes
MC9S12XHZ512 Data Sheet, Rev. 1.03 362 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.3.2.12
CRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
7 6 5 4 3 2 1 0
R W Reset
0 Bit 7 0
0 Bit 6 0
0 Bit 5 0
0 Bit 4 0
0 Bit 3 0
0 Bit 2 0
0 Bit 1 0
0 Bit 0 0
Figure 7-15. ARMCOP Register Diagram
Read: Always reads 0x_00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than 0x_55 or 0x_AA causes a COP reset. To restart the COP time-out period you must write 0x_55 followed by a write of 0x_AA. Other instructions may be executed between these writes but the sequence (0x_55, 0x_AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of 0x_55 writes or sequences of 0x_AA writes are allowed. When the WCOP bit is set, 0x_55 and 0x_AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 363
Chapter 7 Clocks and Reset Generator (CRGV6)
7.4
7.4.1
7.4.1.1
Functional Description
Functional Blocks
Phase Locked Loop (PLL)
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register.
[ SYNR + 1 ] PLLCLK = 2 × OSCCLK × ----------------------------------[ REFDV + 1 ]
CAUTION Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. If (PLLSEL = 1), Bus Clock = PLLCLK / 2 The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency fSCM.
REFERENCE EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL OSCCLK REFDV FEEDBACK LOCK DETECTOR LOCK
REFERENCE PROGRAMMABLE DIVIDER
VDDPLL/VSSPLL PDET PHASE DETECTOR UP DOWN CPUMP VCO
CRYSTAL MONITOR
LOOP PROGRAMMABLE DIVIDER SYN
VDDPLL LOOP FILTER XFC PIN PLLCLK
supplied by:
VDDPLL/VSSPLL VDD/VSS
Figure 7-16. PLL Functional Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 364 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.4.1.1.1
PLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 64 (REFDV + 1) to output the REFERENCE clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR + 1)] to output the FEEDBACK clock. Figure 7-16. The phase detector then compares the FEEDBACK clock, with the REFERENCE clock. Correction pulses are generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the next subsection. The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL. The minimum VCO frequency is reached with the XFC pin forced to VDDPLL. This is the self clock mode frequency. 7.4.1.1.2 Acquisition and Tracking Modes
The lock detector compares the frequencies of the FEEDBACK clock, and the REFERENCE clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. The PLL filter can be manually or automatically configured into one of two possible operating modes: • Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register. • Tracking mode In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as the source for the system and core clocks. If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 365
Chapter 7 Clocks and Reset Generator (CRGV6)
The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1): • The TRACK bit is a read-only indicator of the mode of the filter. • The TRACK bit is set when the VCO frequency is within a certain tolerance, ∆trk, and is clear when the VCO frequency is out of a certain tolerance, ∆unt. • The LOCK bit is a read-only indicator of the locked state of the PLL. • The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared when the VCO frequency is out of a certain tolerance, ∆unl. • Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode. • After turning on the PLL by setting the PLLON bit software must wait a given time (tacq) before entering tracking mode (ACQ = 0). • After entering tracking mode software must wait a given time (tal) before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1).
7.4.1.2
System Clocks Generator
PLLSEL or SCM
PHASE LOCK LOOP
PLLCLK
1 0
STOP
SYSCLK CORE CLOCK
SCM
÷2
EXTAL OSCILLATOR OSCCLK
1 0
WAIT(RTIWAI), STOP(PSTP,PRE), RTI ENABLE
CLOCK PHASE GENERATOR
BUS CLOCK
RTI
XTAL
WAIT(COPWAI), STOP(PSTP,PCE), COP ENABLE
COP
CLOCK MONITOR GATING CONDITION = CLOCK GATE
STOP
OSCILLATOR CLOCK
Figure 7-17. System Clocks Generator
MC9S12XHZ512 Data Sheet, Rev. 1.03 366 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
The clock generator creates the clocks used in the MCU (see Figure 7-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self clock mode (see Section 7.4.2.2, “Self Clock Mode”) oscillator clock source is switched to PLLCLK running at its minimum frequency fSCM. The bus clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU. The core clock is twice the bus clock as shown in Figure 7-18. But note that a CPU cycle corresponds to one bus clock. PLL clock mode is selected with PLLSEL bit in the CLKSEL registerr. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases.
CORE CLOCK
BUS CLOCK / ECLK
Figure 7-18. Core Clock and Bus Clock Relationship
7.4.1.3
Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The CRG then asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME control bit.
7.4.1.4
Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker provides a more accurate check in addition to the clock monitor. A clock quality check is triggered by any of the following events: • Power on reset (POR) • Low voltage reset (LVR) • Wake-up from full stop mode (exit full stop) • Clock monitor fail indication (CM fail) A time window of 50,000 VCO clock cycles1 is called check window.
1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM. MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 367
Chapter 7 Clocks and Reset Generator (CRGV6)
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See Figure 7-19 as an example.
check window 1 VCO Clock 1 OSCCLK 4095 osc ok 2 3 4 5 4096 2 3 49999 50000
Figure 7-19. Check Window Example
The sequence for clock quality check is shown in Figure 7-20.
Clock OK CM fail exit full stop POR LVR SCME = 1 & FSTWKP = 1 ? no Clock Monitor Reset yes num = 0 Enter SCM no
FSTWKP = 0 ? yes
num = 50
Enter SCM yes
no SCM active?
num = 0
check window
num=num–1 yes yes no SCME=1 ? no
osc ok ? yes SCM active? no
no
num > 0 ?
yes
Switch to OSCCLK
Exit SCM
Figure 7-20. Sequence for Clock Quality Check
MC9S12XHZ512 Data Sheet, Rev. 1.03 368 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
NOTE Remember that in parallel to additional actions caused by self clock mode or clock monitor reset1 handling the clock quality checker continues to check the OSCCLK signal. The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo stop mode or wait mode.
7.4.1.5
Computer Operating Properly Watchdog (COP)
The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 7.4.1.5, “Computer Operating Properly Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register allow selection of seven COP time-out periods. When COP is enabled, the program must write 0x_55 and 0x_AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, the part will reset. Also, if any value other than 0x_55 or 0x_AA is written, the part is immediately reset. Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part. If PCE bit is set, the COP will continue to run in pseudo stop mode.
7.4.1.6
Real Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE = 1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated OSCCLK. At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period starts immediately. A write to the RTICTL register restarts the RTI time-out period. If the PRE bit is set, the RTI will continue to run in pseudo stop mode.
7.4.2
7.4.2.1
Operating Modes
Normal Mode
The CRG block behaves as described within this specification in all normal modes.
1. A Clock Monitor Reset will always set the SCME bit to logical 1.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 369
Chapter 7 Clocks and Reset Generator (CRGV6)
7.4.2.2
Self Clock Mode
The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO running at minimum operating frequency; this mode of operation is called self clock mode. This requires CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self clock mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. Section 7.4.1.4, “Clock Quality Checker” for more information on entering and leaving self clock mode. NOTE In order to detect a potential clock loss the CME bit should be always enabled (CME = 1)! If CME bit is disabled and the MCU is configured to run on PLL clock (PLLCLK), a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards the VCO’s minimum frequency fSCM. As soon as the external clock is available again the system clock ramps up to its PLL target frequency. If the MCU is running on external clock any loss of clock will cause the system to go static.
7.4.3
Low Power Options
This section summarizes the low power options available in the CRG.
7.4.3.1
Run Mode
The RTI can be stopped by setting the associated rate select bits to 0. The COP can be stopped by setting the associated rate select bits to 0.
7.4.3.2
Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed. This provides enhanced granularity in reducing the level of power consumption during wait mode. Table 7-11 lists the individual configuration bits and the parts of the MCU that are affected in wait mode
.
Table 7-11. MCU Configuration During Wait Mode
PLLWAI PLL RTI COP Stopped — — RTIWAI — Stopped — COPWAI — — Stopped
After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG then checks whether the PLLWAI bit is asserted (Figure 7-21). Depending on the configuration, the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the PLL. As soon as all clocks are switched off wait mode is active.
MC9S12XHZ512 Data Sheet, Rev. 1.03 370 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
CPU Req’s Wait Mode.
PLLWAI=1 ? Yes
No
Clear PLLSEL, Disable PLL No Enter Wait Mode Wait Mode left due to external reset CME=1 ? Yes No INT ? Yes
Exit Wait w. ext.RESET
CM Fail ? Yes
No
Exit Wait w. CMRESET
No
SCME=1 ? Yes Exit Wait Mode
SCMIE=1 ? Generate SCM Interrupt (Wakeup from Wait) Yes Exit Wait Mode
No
SCM=1 ? Yes
No
Enter SCM
Enter SCM
Continue w. Normal OP
Figure 7-21. Wait Mode Entry/Exit Sequence
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 371
Chapter 7 Clocks and Reset Generator (CRGV6)
There are four different scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Any interrupt If the MCU gets an external reset or COP reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector. Wait mode is left and the MCU is in run mode again. If the clock monitor is enabled (CME = 1) the MCU is able to leave wait mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 7.4.1.4, “Clock Quality Checker”). Then the MCU continues with normal operation.If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted and clock quality checks will be performed but the MCU will not wake-up from wait-mode. If any other interrupt source (e.g., RTI) triggers exit from wait mode, the MCU immediately continues with normal operation. If the PLL has been powered-down during wait mode, the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving wait mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. If wait mode is entered from self-clock mode the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 7-12 summarizes the outcome of a clock loss while in wait mode.
7.4.3.3
System Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE, and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo stop mode. In addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g., voltage-regulator) to enter their individual power saving modes (if available). This is the main difference between pseudo stop mode and wait mode. If the PLLSEL bit is still set when entering stop mode, the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active. If pseudo stop mode (PSTP = 1) is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If full stop mode (PSTP = 0) is entered from self-clock mode, an ongoing clock quality check will be stopped. A complete timeout window check will be started when stop mode is left again. Wake-up from stop mode also depends on the setting of the PSTP bit.
MC9S12XHZ512 Data Sheet, Rev. 1.03 372 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-12. Outcome of Clock Loss in Wait Mode
CME 0 1 SCME X 0 SCMIE X X Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock failure --> Scenario 1: OSCCLK recovers prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later clock quality check indicates clock o.k., – SCM deactivated, – PLL disabled depending on PLLWAI, – VREG remains enabled (never gets disabled in wait mode). – MCU remains in wait mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit wait mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit wait mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag, – Keep performing clock quality checks (could continue infinitely) while in wait mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit wait mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform additional clock quality checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit wait mode in SCM using PLL clock (fSCM) as system clock, – Start reset sequence, – Continue to perform additional clock quality checks until OSCCLKis o.k.again. Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – SCMIF set. SCMIF generates self clock mode wakeup interrupt. – Exit wait mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional clock quality checks until OSCCLK is o.k. again. CRG Actions
1
1
0
1
1
1
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 373
Chapter 7 Clocks and Reset Generator (CRGV6)
Core req’s Stop Mode.
Clear PLLSEL, Disable PLL Stop Mode left due to external reset
Exit Stop w. ext.RESET
Enter Stop Mode
No INT ? Yes
No
PSTP=1 ?
Yes
CME=1 ? Yes
No
No INT ? Yes
SCME=1 & FSTWKP=1 ? No
Yes CM fail ? Yes No
No
Clock OK ? Yes Exit Stop Mode
Exit Stop w. CMRESET
no
SCME=1 ? Yes Exit Stop Mode
Exit Stop w. CMRESET
No
SCME=1 ? Yes
SCMIE=1 ? Yes Exit Stop Mode
No
Exit Stop Mode
Exit Stop Mode
Generate SCM Interrupt (Wakeup from Stop)
No SCM=1 ? Yes
Enter SCM
Enter SCM SCMIF not set!
Enter SCM
Enter SCM
Continue w. normal OP
Figure 7-22. Stop Mode Entry/Exit Sequence
MC9S12XHZ512 Data Sheet, Rev. 1.03 374 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.4.3.3.1
Wake-up from Pseudo Stop Mode (PSTP=1)
Wake-up from pseudo stop mode is the same as wake-up from wait mode. There are also four different scenarios for the CRG to restart the MCU from pseudo stop mode: • External reset • Clock monitor fail • COP reset • Wake-up interrupt If the MCU gets an external reset or COP reset during pseudo stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector. pseudo stop mode is left and the MCU is in run mode again. If the clock monitor is enabled (CME = 1), the MCU is able to leave pseudo stop mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 7.4.1.4, “Clock Quality Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by SCMIE=0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo stop mode. If any other interrupt source (e.g., RTI) triggers exit from pseudo stop mode, the MCU immediately continues with normal operation. Because the PLL has been powered-down during stop mode, the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 7-13 summarizes the outcome of a clock loss while in pseudo stop mode.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 375
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-13. Outcome of Clock Loss in Pseudo Stop Mode
CME 0 1 SCME X 0 SCMIE X X Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later clock quality check indicates clock o.k., – SCM deactivated, – PLL disabled, – VREG disabled. – MCU remains in pseudo stop mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit pseudo stop mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit pseudo stop mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag, – Keep performing clock quality checks (could continue infinitely) while in pseudo stop mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit pseudo stop mode in SCM using PLL clock (fSCM) as system clock – Continue to perform additional clock quality checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit pseudo stop mode in SCM using PLL clock (fSCM) as system clock – Start reset sequence, – Continue to perform additional clock quality checks until OSCCLK is o.k.again. Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – SCMIF set. SCMIF generates self clock mode wakeup interrupt. – Exit pseudo stop mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional clock quality checks until OSCCLK is o.k. again. CRG Actions
1
1
0
1
1
1
MC9S12XHZ512 Data Sheet, Rev. 1.03 376 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.4.3.3.2
Wake-up from Full Stop (PSTP = 0)
The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 7.4.1.4, “Clock Quality Checker”). After completing the clock quality check the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Full stop-mode is left and the MCU is in run mode again. If the MCU is woken-up by an interrupt and the fast wake-up feature is disabled (FSTWKP = 0 or SCME = 0), the CRG will also perform a maximum of 50 clock check_windows (see Section 7.4.1.4, “Clock Quality Checker”). If the clock quality check is successful, the CRG will release all system and core clocks and will continue with normal operation. If all clock checks within the Timeout-Window are failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending on the setting of the SCME bit. If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will immediately resume operation in self-clock mode (see Section 7.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set. The system will remain in self-clock mode with oscillator disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to oscillator clock. The SCMIF flag will be set. See application examples in Figure 7-23 and Figure 7-24. Because the PLL has been powered-down during stop-mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop-mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. NOTE In full stop mode or self-clock mode caused by the fast wake-up feature, the clock monitor and the oscillator are disabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 377
Chapter 7 Clocks and Reset Generator (CRGV6)
CPU resumes program execution immediately
Instruction
FSTWKP=1 SCME=1 STOP IRQ Service STOP Interrupt IRQ Service STOP Interrupt IRQ Service Interrupt
Power Saving
Oscillator Clock
Oscillator Disabled
PLL Clock
Core Clock
Self-Clock Mode
Figure 7-23. Fast Wake-up from Full Stop Mode: Example 1
.
CPU resumes program execution immediately
Instruction
FSTWKP=1 SCME=1 STOP IRQ Service FSTWKP=0 IRQ Interrupt SCMIE=1 Freq. Uncritical Instructions Freq. Critical Instr. Possible SCM Interrupt Clock Quality Check Oscillator Disabled OSC Startup
Oscillator Clock
PLL Clock
Self-Clock Mode
Core Clock
Figure 7-24. Fast Wake-up from Full Stop Mode: Example 2
MC9S12XHZ512 Data Sheet, Rev. 1.03 378 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.5
Resets
This section describes how to reset the CRG, and how the CRG itself controls the reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 7.3, “Memory Map and Register Definition”. All reset sources are listed in Table 7-14. Refer to MCU specification for related vector addresses and priorities.
Table 7-14. Reset Summary
Reset Source Power on Reset Low Voltage Reset External Reset Illegal Address Reset Clock Monitor Reset COP Watchdog Reset Local Enable None None None None PLLCTL (CME = 1, SCME = 0) COPCTL (CR[2:0] nonzero)
7.5.1
Description of Reset Operation
The reset sequence is initiated by any of the following events: • Low level is detected at the RESET pin (external reset) • Power on is detected • Low voltage is detected • Illegal Address Reset is detected (see S12XMMC Block Guide for details) • COP watchdog times out • Clock monitor failure is detected and self-clock mode was disabled (SCME=0) Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see Figure 7-25). Since entry into reset is asynchronous, it does not require a running SYSCLK. However, the internal reset circuit of the CRG cannot sequence out of current reset condition without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency. After 128 + n SYSCLK cycles the RESET pin is released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Table 7-15 shows which vector will be fetched.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 379
Chapter 7 Clocks and Reset Generator (CRGV6)
Table 7-15. Reset Vector Selection
Sampled RESET Pin (64 cycles after release) 1 1 1 0 Clock Monitor Reset Pending 0 1 0 X COP Reset Pending 0 X 1 X Vector Fetch POR / LVR / Illegal Address Reset / External Reset Clock Monitor Reset COP Reset POR / LVR / Illegal Address Reset / External Reset with rise of RESET pin
NOTE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
RESET
)(
)(
RESET pin released
CRG drives RESET pin low
SYSCLK
) (
128 + n cycles Possibly SYSCLK not running With n being min 3 / max 6 cycles depending on internal synchronization delay
) (
64 cycles
) (
Possibly RESET driven low externally
Figure 7-25. RESET Timing
MC9S12XHZ512 Data Sheet, Rev. 1.03 380 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.5.2
Clock Monitor Reset
The CRG generates a clock monitor reset in case all of the following conditions are true: • Clock monitor is enabled (CME = 1) • Loss of clock is detected • Self-clock mode is disabled (SCME = 0). The reset event asynchronously forces the configuration registers to their default settings (see Section 7.3, “Memory Map and Register Definition”). In detail the CME and the SCME are reset to logical ‘1’ (which doesn’t change the state of the CME bit, because it has already been set). As a consequence the CRG immediately enters self clock mode and starts its internal reset sequence. In parallel the clock quality check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and leaves self clock mode. Since the clock quality checker is running in parallel to the reset generator, the CRG may leave self clock mode while still completing the internal reset sequence. When the reset sequence is finished, the CRG checks the internally latched state of the clock monitor fail circuit. If a clock monitor fail is indicated, processing begins by fetching the clock monitor reset vector.
7.5.3
Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the CRG expects sequential write of 0x_55 and 0x_AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x_55 or 0x_AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled writes (0x_55 or 0x_AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector.
7.5.4
Power On Reset, Low Voltage Reset
The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid oscillator clock signal, the reset sequence starts using the oscillator clock. If after 50 check windows the clock quality check indicated a non-valid oscillator clock, the reset sequence starts using self-clock mode. Figure 7-26 and Figure 7-27 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 381
Chapter 7 Clocks and Reset Generator (CRGV6)
RESET
Clock Quality Check (no Self-Clock Mode) )(
Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK
Figure 7-26. RESET Pin Tied to VDD (by a pull-up resistor)
RESET
Clock Quality Check (no Self Clock Mode) )(
Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK
Figure 7-27. RESET Pin Held Low Externally
7.6
Interrupts
The interrupts/reset vectors requested by the CRG are listed in Table 7-16. Refer to MCU specification for related vector addresses and priorities.
Table 7-16. CRG Interrupt Vectors
Interrupt Source Real time interrupt LOCK interrupt SCM interrupt CCR Mask I bit I bit I bit Local Enable CRGINT (RTIE) CRGINT (LOCKIE) CRGINT (SCMIE)
7.6.1
Real Time Interrupt
The CRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to 0. The real time interrupt flag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during pseudo stop mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from pseudo stop if the RTI interrupt is enabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 382 Freescale Semiconductor
Chapter 7 Clocks and Reset Generator (CRGV6)
7.6.2
PLL Lock Interrupt
The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
7.6.3
Self Clock Mode Interrupt
The CRG generates a self clock mode interrupt when the SCM condition of the system has changed, either entered or exited self clock mode. SCM conditions can only change if the self clock mode enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power on reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details on the clock quality check refer to Section 7.4.1.4, “Clock Quality Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1). SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 383
Chapter 7 Clocks and Reset Generator (CRGV6)
MC9S12XHZ512 Data Sheet, Rev. 1.03 384 Freescale Semiconductor
Chapter 8 Pierce Oscillator (S12XOSCLCPV1)
8.1 Introduction
The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (2.5 V nominal) and require the minimum number of external components. It is designed for optimal start-up margin with typical crystal oscillators.
8.1.1
Features
The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. • High noise immunity due to input hysteresis • Low RF emissions with peak-to-peak swing limited dynamically • Transconductance (gm) sized for optimum start-up margin for typical oscillators • Dynamic gain control eliminates the need for external current limiting resistor • Integrated resistor eliminates the need for external bias resistor • Low power consumption: — Operates from 2.5 V (nominal) supply — Amplitude control limits power • Clock monitor
8.1.2
Modes of Operation
Two modes of operation exist: 1. Loop controlled Pierce oscillator 2. External square wave mode featuring also full swing Pierce without internal feedback resistor
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 385
Chapter 8 Pierce Oscillator (S12XOSCLCPV1)
8.1.3
Block Diagram
Figure 8-1 shows a block diagram of the XOSC.
Monitor_Failure Clock Monitor
OSCCLK
Peak Detector
Gain Control VDDPLL = 2.5 V
Rf
EXTAL
XTAL
Figure 8-1. XOSC Block Diagram
8.2
External Signal Description
This section lists and describes the signals that connect off chip
8.2.1
VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This allows the supply voltage to the XOSC to be independently bypassed.
8.2.2
EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived from the
MC9S12XHZ512 Data Sheet, Rev. 1.03 386 Freescale Semiconductor
Chapter 8 Pierce Oscillator (S12XOSCLCPV1)
EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals.
EXTAL C1 MCU XTAL C2 VSSPLL Crystal or Ceramic Resonator
Figure 8-2. Loop Controlled Pierce Oscillator Connections (XCLKS = 0)
NOTE Full swing Pierce circuit is not suited for overtone resonators and crystals without a careful component selection.
EXTAL C1 MCU RS* XTAL C2 VSSPLL * Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer’s data. RB Crystal or Ceramic Resonator
Figure 8-3. Full Swing Pierce Oscillator Connections (XCLKS = 1)
EXTAL MCU XTAL
CMOS Compatible External Oscillator (VDDPLL Level)
Not Connected
Figure 8-4. External Clock Connections (XCLKS = 1)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 387
Chapter 8 Pierce Oscillator (S12XOSCLCPV1)
8.2.3
XCLKS — Input Signal
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS pin. Table 8-1 lists the state coding of the sampled XCLKS signal.
.
Table 8-1. Clock Selection Based on XCLKS
XCLKS 0 1 Description Loop controlled Pierce oscillator selected Full swing Pierce oscillator/external clock selected
8.3
Memory Map and Register Definition
The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.
8.4
Functional Description
The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback. A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is powered by the VDDPLL and VSSPLL power supply pins.
8.4.1
Gain Control
A closed loop control system will be utilized whereby the amplifier is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer. Electrical specification details are provided in the Electrical Characteristics appendix.
8.4.2
Clock Monitor
The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function is enabled/disabled by the CME control bit, described in the CRG block description chapter.
MC9S12XHZ512 Data Sheet, Rev. 1.03 388 Freescale Semiconductor
Chapter 8 Pierce Oscillator (S12XOSCLCPV1)
8.4.3
Wait Mode Operation
During wait mode, XOSC is not impacted.
8.4.4
Stop Mode Operation
XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 389
Chapter 8 Pierce Oscillator (S12XOSCLCPV1)
MC9S12XHZ512 Data Sheet, Rev. 1.03 390 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.1 Introduction
The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy.
9.1.1
• • • • • • • • • • • • •
Features
8-/10-bit resolution 7 µs, 10-bit single conversion time Sample buffer amplifier Programmable sample time Left/right justified, signed/unsigned result data External trigger control Conversion completion interrupt generation Analog input multiplexer for 16 analog input channels Analog/digital input pin multiplexing 1 to 16 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity Configurable location for channel wrap around (when converting multiple channels in a sequence)
•
9.1.2
Modes of Operation
There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.
9.1.3
Block Diagram
Refer to Figure 9-1 for a block diagram of the ATD0B16C block.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 391
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Bus Clock
Clock Prescaler Trigger Mux
ATD clock
ATD10B16C
ETRIG0 ETRIG1 ETRIG2 ETRIG3 (see Device Overview chapter for availability and connectivity) ATDCTL1
Mode and Timing Control
Sequence Complete Interrupt
ATDDIEN
VDDA VSSA VRH VRL AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 Analog MUX
PORTAD Successive Approximation Register (SAR) and DAC
Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15
+ Sample & Hold 1 1 Comparator
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
Figure 9-1. ATD10B16C Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 392 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.2
External Signal Description
This section lists all inputs to the ATD10B16C block.
9.2.1
ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins
This pin serves as the analog input channel x. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion.
9.2.2
ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins
These inputs can be configured to serve as an external trigger for the ATD conversion. Refer to the Device Overview chapter for availability and connectivity of these inputs.
9.2.3
VRH, VRL — High Reference Voltage Pin, Low Reference Voltage Pin
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
9.2.4
VDDA, VSSA — Analog Circuitry Power Supply Pins
These pins are the power supplies for the analog circuitry of the ATD10B16CV4 block.
9.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ATD10B16C.
9.3.1
Module Memory Map
Table 9-1 gives an overview of all ATD10B16C registers
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 393
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
.
Table 9-1. ATD10B16CV4 Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010, 0x0011 0x0012, 0x0013 0x0014, 0x0015 0x0016, 0x0017 0x0018, 0x0019 0x001A, 0x001B 0x001C, 0x001D 0x001E, 0x001F 0x0020, 0x0021 0x0022, 0x0023 0x0024, 0x0025 0x0026, 0x0027 0x0028, 0x0029 0x002A, 0x002B 0x002C, 0x002D 0x002E, 0x002F
1
Use ATD Control Register 0 (ATDCTL0) ATD Control Register 1 (ATDCTL1) ATD Control Register 2 (ATDCTL2) ATD Control Register 3 (ATDCTL3) ATD Control Register 4 (ATDCTL4) ATD Control Register 5 (ATDCTL5) ATD Status Register 0 (ATDSTAT0) Unimplemented ATD Test Register 0 (ATDTEST0)1 ATD Test Register 1 (ATDTEST1) ATD Status Register 2 (ATDSTAT2) ATD Status Register 1 (ATDSTAT1) ATD Input Enable Register 0 (ATDDIEN0) ATD Input Enable Register 1 (ATDDIEN1) Port Data Register 0 (PORTAD0) Port Data Register 1 (PORTAD1) ATD Result Register 0 (ATDDR0H, ATDDR0L) ATD Result Register 1 (ATDDR1H, ATDDR1L) ATD Result Register 2 (ATDDR2H, ATDDR2L) ATD Result Register 3 (ATDDR3H, ATDDR3L) ATD Result Register 4 (ATDDR4H, ATDDR4L) ATD Result Register 5 (ATDDR5H, ATDDR5L) ATD Result Register 6 (ATDDR6H, ATDDR6L) ATD Result Register 7 (ATDDR7H, ATDDR7L) ATD Result Register 8 (ATDDR8H, ATDDR8L) ATD Result Register 9 (ATDDR9H, ATDDR9L) ATD Result Register 10 (ATDDR10H, ATDDR10L) ATD Result Register 11 (ATDDR11H, ATDDR11L) ATD Result Register 12 (ATDDR12H, ATDDR12L) ATD Result Register 13 (ATDDR13H, ATDDR13L) ATD Result Register 14 (ATDDR14H, ATDDR14L) ATD Result Register 15 (ATDDR15H, ATDDR15L)
Access R/W R/W R/W R/W R/W R/W R/W R R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ATDTEST0 is intended for factory test purposes only.
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
MC9S12XHZ512 Data Sheet, Rev. 1.03 394 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2
Register Descriptions
This section describes in address order all the ATD10B16C registers and their individual bits.
Register Name 0x0000 ATDCTL0 R W R W R W R W R W R W R W R W R W R W R W R W R W IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 Unimplemented SC CCF8 Unimplemented SRES8 0 0 0 Bit 7 0 6 0 5 0 4 0 3 2 1 Bit 0
WRAP3
WRAP2
WRAP1
WRAP0
0x0001 ATDCTL1 0x0002 ATDCTL2 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemented 0x0008 ATDTEST0 0x0009 ATDTEST1 0x000A ATDSTAT2 0x000B ATDSTAT1 0x000C ATDDIEN0
ETRIGSEL
ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 ASCIF
ADPU 0
AFFC
AWAI
ETRIGLE
ETRIGP
ETRIGE
ASCIE
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
DJM
DSGN 0
SCAN
MULT
CD CC3
CC CC2
CB CC1
CA CC0
SCF
ETORF
FIFOR
= Unimplemented or Reserved
u = Unaffected
Figure 9-2. ATD Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 395
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Register Name 0x000D ATDDIEN1 0x000E PORTAD0 0x000F PORTAD1 R W R W R W
Bit 7 IEN7 PTAD15
6 IEN6 PTAD14
5 IEN5 PTAD13
4 IEN4 PTAD12
3 IEN3 PTAD11
2 IEN2 PTAD10
1 IEN1 PTAD9
Bit 0 IEN0 PTAD8
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
R BIT 9 MSB BIT 7 MSB 0x0010–0x002F W ATDDRxH– ATDDRxL R W
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
BIT 1 u
BIT 0 u
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
u = Unaffected
Figure 9-2. ATD Register Summary (continued)
9.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0 WRAP3 WRAP2 1 WRAP1 1 WRAP0 1
0
0
0
0
1
= Unimplemented or Reserved
Figure 9-3. ATD Control Register 0 (ATDCTL0)
Read: Anytime Write: Anytime
Table 9-2. ATDCTL0 Field Descriptions
Field 3:0 WRAP[3:0] Description Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 9-3.
MC9S12XHZ512 Data Sheet, Rev. 1.03 396 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-3. Multi-Channel Wrap Around Coding
WRAP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WRAP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WRAP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WRAP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting Reserved AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
9.3.2.2
ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R ETRIGSEL W Reset 0
0
0
0 ETRIGCH3 ETRIGCH2 1 ETRIGCH1 1 ETRIGCH0 1
0
0
0
1
= Unimplemented or Reserved
Figure 9-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime Write: Anytime
Table 9-4. ATDCTL1 Field Descriptions
Field 7 ETRIGSEL Description External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG[3:0] inputs. See device specification for availability and connectivity of ETRIG[3:0] inputs. If ETRIG[3:0] input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, that means one of the AD channels (selected by ETRIGCH[3:0]) remains the source for external trigger. The coding is summarized in Table 9-5.
3:0 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG[3:0] inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 9-5.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 397
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-5. External Trigger Channel Select Coding
ETRIGSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
1
ETRIGCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1
ETRIGCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 X
ETRIGCH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X
ETRIGCH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X
External Trigger Source AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ETRIG01 ETRIG11 ETRIG21 ETRIG31 Reserved Reserved
Only if ETRIG[3:0] input option is available (see device specification), else ETRISEL is ignored, that means external trigger source remains on one of the AD channels selected by ETRIGCH[3:0]
9.3.2.3
ATD Control Register 2 (ATDCTL2)
This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence.
MC9S12XHZ512 Data Sheet, Rev. 1.03 398 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
7
6
5
4
3
2
1
0
R ADPU W Reset 0 0 0 0 0 0 0 AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE
ASCIF
0
= Unimplemented or Reserved
Figure 9-5. ATD Control Register 2 (ATDCTL2)
Read: Anytime Write: Anytime
Table 9-6. ATDCTL2 Field Descriptions
Field 7 ADPU Description ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled. 0 Power down ATD 1 Normal ATD functionality ATD Fast Flag Clear All 0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). 1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode. 0 ATD continues to run in Wait mode 1 Halt conversion and power down ATD during Wait mode After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this conversion should be ignored. External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 9-7 for details. External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 9-7 for details. External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the ETRIG[3:0] inputs as described in Table 9-5. If external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events. 0 Disable external trigger 1 Enable external trigger ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 9.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect. 0 No ATD interrupt occurred 1 ATD sequence complete interrupt pending
6 AFFC
5 AWAI
4 ETRIGLE 3 ETRIGP 2 ETRIGE
1 ASCIE 0 ASCIF
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 399
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-7. External Trigger Configurations
ETRIGLE 0 0 1 1 ETRIGP 0 1 0 1 External Trigger Sensitivity Falling Edge Ring Edge Low Level High Level
MC9S12XHZ512 Data Sheet, Rev. 1.03 400 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.4
ATD Control Register 3 (ATDCTL3)
This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R W Reset
0 S8C 0 0 S4C 1 S2C 0 S1C 0 FIFO 0 FRZ1 0 FRZ0 0
= Unimplemented or Reserved
Figure 9-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime Write: Anytime
Table 9-8. ATDCTL3 Field Descriptions
Field 6 S8C 5 S4C 4 S2C 3 S1C Description Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 401
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-8. ATDCTL3 Field Descriptions (continued)
Field 2 FIFO Description Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register file, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 9-10. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
1:0 FRZ[1:0]
Table 9-9. Conversion Sequence Length Coding
S8C 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S4C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S2C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S1C 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Number of Conversions per Sequence 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MC9S12XHZ512 Data Sheet, Rev. 1.03 402 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-10. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1 0 0 1 1 FRZ0 0 1 0 1 Behavior in Freeze Mode Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 403
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.5
ATD Control Register 4 (ATDCTL4)
This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R SRES8 W Reset 0 0 0 0 0 1 0 1 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Figure 9-7. ATD Control Register 4 (ATDCTL4)
Read: Anytime Write: Anytime
Table 9-11. ATDCTL4 Field Descriptions
Field 7 SRES8 Description A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10 bit resolution 1 8 bit resolution Sample Time Select —These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 9-12 lists the lengths available for the second sample phase. ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: [ BusClock ] ATDclock = ------------------------------- × 0.5 [ PRS + 1 ] Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12. Table 9-13 illustrates the divide-by operation and the appropriate range of the bus clock.
6:5 SMP[1:0]
4:0 PRS[4:0]
Table 9-12. Sample Time Select
SMP1 0 0 1 1 SMP0 0 1 0 1 Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 16 A/D conversion clock periods
MC9S12XHZ512 Data Sheet, Rev. 1.03 404 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-13. Clock Prescaler Values
Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
1
Total Divisor Value Divide by 2 Divide by 4 Divide by 6 Divide by 8 Divide by 10 Divide by 12 Divide by 14 Divide by 16 Divide by 18 Divide by 20 Divide by 22 Divide by 24 Divide by 26 Divide by 28 Divide by 30 Divide by 32 Divide by 34 Divide by 36 Divide by 38 Divide by 40 Divide by 42 Divide by 44 Divide by 46 Divide by 48 Divide by 50 Divide by 52 Divide by 54 Divide by 56 Divide by 58 Divide by 60 Divide by 62 Divide by 64
Max. Bus Clock1 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 36 MHz 40 MHz 44 MHz 48 MHz 52 MHz 56 MHz 60 MHz 64 MHz 68 MHz 72 MHz 76 MHz 80 MHz 84 MHz 88 MHz 92 MHz 96 MHz 100 MHz 104 MHz 108 MHz 112 MHz 116 MHz 120 MHz 124 MHz 128 MHz
Min. Bus Clock2 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz
Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2 Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 405
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.6
ATD Control Register 5 (ATDCTL5)
This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase.
7 6 5 4 3 2 1 0
R DJM W Reset 0 0 0 0 0 0 0 0 DSGN SCAN MULT CD CC CB CA
Figure 9-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime Write: Anytime
Table 9-14. ATDCTL5 Field Descriptions
Field 7 DJM Description Result Register Data Justification — This bit controls justification of conversion data in the result registers. See Section 9.3.2.16, “ATD Conversion Result Registers (ATDDRx)” for details. 0 Left justified data in the result registers. 1 Right justified data in the result registers. Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed data is not available in right justification. See 9.3.2.16 ATD Conversion Result Registers (ATDDRx) for details. 0 Unsigned data representation in the result registers. 1 Signed data representation in the result registers. Table 9-15 summarizes the result data formats available and how they are set up using the control bits. Table 9-16 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means each trigger event starts a single conversion sequence. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0. 0 Sample only one channel 1 Sample across several channels
6 DSGN
5 SCAN
4 MULT
MC9S12XHZ512 Data Sheet, Rev. 1.03 406 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-14. ATDCTL5 Field Descriptions (continued)
Field 3:0 C[D:A} Description Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 9-17 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined. In the case of multiple channel conversions (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP[3:0] in ATDCTL0). In case starting with a channel number higher than the one defined by WRAP[3:0] the first wrap around will be AN15 to AN0.
Table 9-15. Available Result Data Formats.
SRES8 1 1 1 0 0 0 DJM 0 0 1 0 0 1 DSGN 0 1 X 0 1 X Result Data Formats Description and Bus Bit Mapping 8-bit / left justified / unsigned — bits 15:8 8-bit / left justified / signed — bits 15:8 8-bit / right justified / unsigned — bits 7:0 10-bit / left justified / unsigned — bits 15:6 10-bit / left justified / signed -— bits 15:6 10-bit / right justified / unsigned — bits 9:0
Table 9-16. Left Justified, Signed and Unsigned ATD Output Codes.
Input Signal VRL = 0 Volts VRH = 5.12 Volts 5.120 Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Signed 8-Bit Codes 7F 7F 7E 01 00 FF 81 80 Unsigned 8-Bit Codes FF FF FE 81 80 7F 01 00 Signed 10-Bit Codes 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 Unsigned 10-Bit Codes FFC0 FF00 FE00 8100 8000 7F00 0100 0000
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 407
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-17. Analog Input Channel Select Coding
CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
MC9S12XHZ512 Data Sheet, Rev. 1.03 408 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.7
ATD Status Register 0 (ATDSTAT0)
This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter.
7 6 5 4 3 2 1 0
R SCF W Reset 0
0 ETORF 0 0 FIFOR 0
CC3
CC2
CC1
CC0
0
0
0
0
= Unimplemented or Reserved
Figure 9-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime Write: Anytime (No effect on CC[3:0])
Table 9-18. ATDSTAT0 Field Descriptions
Field 7 SCF Description Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is cleared when one of the following occurs: • Write “1” to SCF • Write to ATDCTL5 (a new conversion sequence is started) • If AFFC = 1 and read of a result register 0 Conversion sequence not completed 1 Conversion sequence has completed External Trigger Overrun Flag —While in edge trigger mode (ETRIGLE = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the following occurs: • Write “1” to ETORF • Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted) • Write to ATDCTL5 (a new conversion sequence is started) 0 No External trigger over run error has occurred 1 External trigger over run error has occurred
5 ETORF
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 409
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-18. ATDSTAT0 Field Descriptions (continued)
Field 4 FIFOR Description FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). This flag is cleared when one of the following occurs: • Write “1” to FIFOR • Start a new conversion sequence (write to ATDCTL5 or external trigger) 0 No over run has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag remained set) Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0, CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1.
3:0 CC[3:0}
MC9S12XHZ512 Data Sheet, Rev. 1.03 410 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.8
Reserved Register 0 (ATDTEST0)
7 6 5 4 3 2 1 0
R W Reset
u
u
u
u
u
u
u
u
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 9-10. Reserved Register 0 (ATDTEST0)
Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality.
9.3.2.9
ATD Test Register 1 (ATDTEST1)
This register contains the SC bit used to enable special channel conversions.
7 6 5 4 3 2 1 0
R W Reset
u
u
u
u
u
u
u SC
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 9-11. Reserved Register 1 (ATDTEST1)
Read: Anytime, returns unpredictable values for bit 7 and bit 6 Write: Anytime NOTE Writing to this register when in special modes can alter functionality.
Table 9-19. ATDTEST1 Field Descriptions
Field 0 SC Description Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC, CB, and CA of ATDCTL5. Table 9-20 lists the coding. 0 Special channel conversions disabled 1 Special channel conversions enabled
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 411
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
Table 9-20. Special Channel Select Coding
SC 1 1 1 1 1 1 CD 0 0 0 0 0 1 CC 0 1 1 1 1 X CB X 0 0 1 1 X CA X 0 1 0 1 X Analog Input Channel Reserved VRH VRL (VRH+VRL) / 2 Reserved Reserved
9.3.2.10
ATD Status Register 2 (ATDSTAT2)
This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
7 6 5 4 3 2 1 0
R W Reset
CCF15
CCF14
CCF13
CCF12
CCF11
CCF10
CCF9
CCF8
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-12. ATD Status Register 2 (ATDSTAT2)
Read: Anytime Write: Anytime, no effect
Table 9-21. ATDSTAT2 Field Descriptions
Field 7:0 CCF[15:8] Description Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF8 is set when the ninth conversion in a sequence is complete and the result is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and the result is available in ATDDR9, and so forth. A flag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when one of the following occurs: • Write to ATDCTL5 (a new conversion sequence is started) • If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx • If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx
MC9S12XHZ512 Data Sheet, Rev. 1.03 412 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.11
ATD Status Register 1 (ATDSTAT1)
This read-only register contains the Conversion Complete Flags CCF7 to CCF0
7 6 5 4 3 2 1 0
R W Reset
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-13. ATD Status Register 1 (ATDSTAT1)
Read: Anytime Write: Anytime, no effect
Table 9-22. ATDSTAT1 Field Descriptions
Field 7:0 CCF[7:0] Description Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A CCF flag is cleared when one of the following occurs: • Write to ATDCTL5 (a new conversion sequence is started) • If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx • If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. Conversion number x not completed Conversion number x has completed, result ready in ATDDRx
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 413
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9.3.2.12
ATD Input Enable Register 0 (ATDDIEN0)
7 6 5 4 3 2 1 0
R IEN15 W Reset 0 0 0 0 0 0 0 0 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8
Figure 9-14. ATD Input Enable Register 0 (ATDDIEN0)
Read: Anytime Write: anytime
Table 9-23. ATDDIEN0 Field Descriptions
Field 7:0 IEN[15:8] Description ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.
9.3.2.13
ATD Input Enable Register 1 (ATDDIEN1)
7 6 5 4 3 2 1 0
R IEN7 W Reset 0 0 0 0 0 0 0 0 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0
Figure 9-15. ATD Input Enable Register 1 (ATDDIEN1)
Read: Anytime Write: Anytime
Table 9-24. ATDDIEN1 Field Descriptions
Field 7:0 IEN[7:0] Description ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.
MC9S12XHZ512 Data Sheet, Rev. 1.03 414 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.14
Port Data Register 0 (PORTAD0)
The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8].
7 6 5 4 3 2 1 0
R W Reset Pin Function
PTAD15
PTAD14
PTAD13
PTAD12
PTAD11
PTAD10
PTAD9
PTAD8
1 AN15
1 AN14
1 AN13
1 AN12
1 AN11
1 AN10
1 AN9
1 AN8
= Unimplemented or Reserved
Figure 9-16. Port Data Register 0 (PORTAD0)
Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input.
Table 9-25. PORTAD0 Field Descriptions
Field 7:0 PTAD[15:8] Description A/D Channel x (ANx) Digital Input Bits— If the digital input buffer on the ANx pin is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD0 bits to “1”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 415
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9.3.2.15
Port Data Register 1 (PORTAD1)
The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0.
7 6 5 4 3 2 1 0
R W Reset Pin Function
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
1 AN 7
1 AN6
1 AN5
1 AN4
1 AN3
1 AN2
1 AN1
1 AN0
= Unimplemented or Reserved
Figure 9-17. Port Data Register 1 (PORTAD1)
Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input.
Table 9-26. PORTAD1 Field Descriptions
Field 7:0 PTAD[7:8] Description A/D Channel x (ANx) Digital Input Bits — If the digital input buffer on the ANx pin is enabled (IENx=1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD1 bits to “1”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 416 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.16
ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes 9.3.2.16.1 Left Justified Result Data
7 6 5 4 3 2 1 0
R (10-BIT) BIT 9 MSB R (8-BIT) BIT 7 MSB W Reset 0
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
7 6 5 4 3 2 1 0
R (10-BIT) R (8-BIT) W Reset
BIT 1 u
BIT 0 u
0 0
0 0
0 0
0 0
0 0
0 0
0
0
0
0
0
0 u = Unaffected
0
0
= Unimplemented or Reserved
Figure 9-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 417
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.3.2.16.2
Right Justified Result Data
7 6 5 4 3 2 1 0
R (10-BIT) R (8-BIT) W Reset
0 0
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-20. Right Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
7 6 5 4 3 2 1 0
R (10-BIT) BIT 7 R (8-BIT) BIT 7 MSB W Reset 0
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-21. Right Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
9.4
Functional Description
The ATD10B16C is structured in an analog and a digital sub-block.
9.4.1
Analog Sub-block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.
9.4.1.1
Sample and Hold Machine
The sample and hold (S/H) machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node.The second stage connects the input directly to the storage node to complete the sample for high accuracy. When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA.
MC9S12XHZ512 Data Sheet, Rev. 1.03 418 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.4.1.2
Analog Input Multiplexer
The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine.
9.4.1.3
Sample Buffer Amplifier
The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential.
9.4.1.4
Analog-to-Digital (A/D) Machine
The A/D machine performs analog to digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics continue drawing quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output codes.
9.4.2
Digital Sub-Block
This subsection explains some of the digital features in more detail. See register descriptions for all details.
9.4.2.1
External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 9-27 gives a brief description of the different combinations of control bits and their effect on the external trigger function.
Table 9-27. External Trigger Control Bits
ETRIGLE X X 0 0 1 1 ETRIGP X X 0 1 0 1 ETRIGE 0 0 1 1 1 1 SCAN 0 1 X X X X Description Ignores external trigger. Performs one conversion sequence and stops. Ignores external trigger. Performs continuous conversion sequences. Falling edge triggered. Performs one conversion sequence per trigger. Rising edge triggered. Performs one conversion sequence per trigger. Trigger active low. Performs continuous conversions while trigger is active. Trigger active high. Performs continuous conversions while trigger is active.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 419
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In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger remains asserted in level mode while a sequence is completing, another sequence will be triggered immediately.
9.4.2.2
General-Purpose Digital Input Port Operation
The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port registers (PORTAD0 & PORTAD1) (input-only). The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog inputs of the ATD10B16C. The input pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN0 & ATDDIEN1 register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input.
9.4.3
Operation in Low Power Modes
The ATD10B16C can be configured for lower MCU power consumption in three different ways: • Stop Mode Stop Mode: This halts A/D conversion. Exit from Stop mode will resume A/D conversion, But due to the recovery time the result of this conversion should be ignored. Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This halts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time tSR before initiating a new ATD conversion sequence. • Wait Mode Wait Mode with AWAI = 1: This halts A/D conversion. Exit from Wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. Entering wait mode, the ATD conversion either continues or halts for low power depending on the logical value of the AWAIT bit. • Freeze Mode Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. NOTE The reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state.
MC9S12XHZ512 Data Sheet, Rev. 1.03 420 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
9.5
Resets
At reset the ATD10B16C is in a power down state. The reset state of each individual bit is listed within Section 9.3, “Memory Map and Register Definition,” which details the registers and their bit fields.
9.6
Interrupts
The interrupt requested by the ATD10B16C is listed in Table 9-28. Refer to MCU specification for related vector address and priority.
Table 9-28. ATD Interrupt Vectors
Interrupt Source Sequence Complete Interrupt CCR Mask I bit Local Enable ASCIE in ATDCTL2
See Section 9.3.2, “Register Descriptions,” for further details.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 421
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MC9S12XHZ512 Data Sheet, Rev. 1.03 422 Freescale Semiconductor
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 423
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4)
MC9S12XHZ512 Data Sheet, Rev. 1.03 424 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.1 Introduction
The LCD32F4BV1 driver module has 32 frontplane drivers and 4 backplane drivers so that a maximum of 128 LCD segments are controllable. Each segment is controlled by a corresponding bit in the LCD RAM. Four multiplex modes (1/1, 1/2, 1/3, 1/4 duty), and three bias (1/1, 1/2, 1/3) methods are available. The V0 voltage is the lowest level of the output waveform and V3 becomes the highest level. All frontplane and backplane pins can be multiplexed with other port functions. The LCD32F4BV1 driver system consists of five major sub-modules: • Timing and Control – consists of registers and control logic for frame clock generation, bias voltage level select, frame duty select, backplane select, and frontplane select/enable to produce the required frame frequency and voltage waveforms. • LCD RAM – contains the data to be displayed on the LCD. Data can be read from or written to the display RAM at any time. • Frontplane Drivers – consists of 32 frontplane drivers. • Backplane Drivers – consists of 4 backplane drivers. • Voltage Generator – Based on voltage applied to VLCD, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms.
10.1.1
Features
The LCD32F4BV1 includes these distinctive features: • Supports five LCD operation modes • 32 frontplane drivers • 4 backplane drivers — Each frontplane has an enable bit respectively • Programmable frame clock generator • Programmable bias voltage level selector • On-chip generation of 4 different output voltage levels
10.1.2
Modes of Operation
The LCD32F4BV1 module supports five operation modes with different numbers of backplanes and different biasing levels. During pseudo stop mode and wait mode the LCD operation can be suspended
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 425
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
under software control. Depending on the state of internal bits, the LCD can operate normally or the LCD clock generation can be turned off and the LCD32F4BV1 module enters a power conservation state. This is a high level description only, detailed descriptions of operating modes are contained in Section 10.4.2, “Operation in Wait Mode”, Section 10.4.3, “Operation in Pseudo Stop Mode”, and Section 10.4.4, “Operation in Stop Mode”.
10.1.3
Block Diagram
Figure 10-1 is a block diagram of the LCD32F4BV1 module.
Internal Address/Data/Clocks
OSCCLK
LCD RAM 16 bytes
Timing and Control Logic
Prescaler
LCD Clock
V3 V2 Frontplane Drivers V1 V0 Voltage Generator
V3 V2 V1 V0 Backplane Drivers
FP[31:0]
VLCD
BP[3:0]
Figure 10-1. LCD32F4BV1 Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 426 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.2
External Signal Description
The LCD32F4BV1 module has a total of 37 external pins.
Table 10-1. Signal Properties
Name 4 backplane waveforms 32 frontplane waveforms LCD voltage Port BP[3:0] Function Backplane waveform signals that connect directly to the pads Reset State High impedance High impedance —
FP[31:0] Frontplane waveform signals that connect directly to the pads VLCD LCD supply voltage
10.2.1
BP[3:0] — Analog Backplane Pins
This output signal vector represents the analog backplane waveforms of the LCD32F4BV1 module and is connected directly to the corresponding pads.
10.2.2
FP[31:0] — Analog Frontplane Pins
This output signal vector represents the analog frontplane waveforms of the LCD32F4BV1 module and is connected directly to the corresponding pads.
10.2.3
VLCD — LCD Supply Voltage Pin
Positive supply voltage for the LCD waveform generation.
10.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
10.3.1
Module Memory Map
The memory map for the LCD32F4BV1 module is given in Table 10-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the LCD32F4BV1 module and the address offset for each register.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 427
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
Table 10-2. LCD32F4BV1 Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 Use LCD Control Register 0 (LCDCR0) LCD Control Register 1 (LCDCR1) LCD Frontplane Enable Register 0 (FPENR0) LCD Frontplane Enable Register 1 (FPENR1) LCD Frontplane Enable Register 2 (FPENR2) LCD Frontplane Enable Register 3 (FPENR3) Unimplemented Unimplemented LCDRAM (Location 0) LCDRAM (Location 1) LCDRAM (Location 2) LCDRAM (Location 3) LCDRAM (Location 4) LCDRAM (Location 5) LCDRAM (Location 6) LCDRAM (Location 7) LCDRAM (Location 8) LCDRAM (Location 9) LCDRAM (Location 10) LCDRAM (Location 11) LCDRAM (Location 12) LCDRAM (Location 13) LCDRAM (Location 14) LCDRAM (Location 15) Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
MC9S12XHZ512 Data Sheet, Rev. 1.03 428 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.3.2
Register Descriptions
This section consists of register descriptions. Each description includes a standard register diagram. Details of register bit and field function follow the register diagrams, in bit order.
10.3.2.1
LCD Control Register 0 (LCDCR0)
7 6 0 LCDEN LCLK2 0 0 LCLK1 0 LCLK0 0 BIAS 0 DUTY1 0 DUTY0 0 5 4 3 2 1 0
R W Reset 0
= Unimplemented or Reserved
Figure 10-2. LCD Control Register 0 (LCDCR0)
Read: anytime Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty select bits must not be changed when the LCD is enabled.
Table 10-3. LCDCR0 Field Descriptions
Field 7 LCDEN Description LCD32F4BV1 Driver System Enable — The LCDEN bit starts the LCD waveform generator. 0 All frontplane and backplane pins are disabled. In addition, the LCD32F4BV1 system is disabled and all LCD waveform generation clocks are stopped. 1 LCD driver system is enabled. All FP[31:0] pins with FP[31:0]EN set, will output an LCD driver waveform The BP[3:0] pins will output an LCD32F4BV1 driver waveform based on the settings of DUTY0 and DUTY1. LCD Clock Prescaler — The LCD clock prescaler bits determine the OSCCLK divider value to produce the LCD clock frequency. For detailed description of the correlation between LCD clock prescaler bits and the divider value please refer to Table 10-7. BIAS Voltage Level Select — This bit selects the bias voltage levels during various LCD operating modes, as shown in Table 10-8. LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD32F4BV1 driver system, as shown in Table 10-8.
5:3 LCLK[2:0] 2 BIAS 1:0 DUTY[1:0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 429
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.3.2.2
LCD Control Register 1 (LCDCR1)
7 6 0 5 0 4 0 3 0 2 0 LCDSWAI LCDRPSTP 0 1 0
R W Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 10-3. LCD Control Register 1 (LCDCR1)
Read: anytime Write: anytime
Table 10-4. LCDCR1 Field Descriptions
Field 1 LCDSWAI Description LCD Stop in Wait Mode — This bit controls the LCD operation while in wait mode. 0 LCD operates normally in wait mode. 1 Stop LCD32F4BV1 driver system when in wait mode.
0 LCD Run in Pseudo Stop Mode — This bit controls the LCD operation while in pseudo stop mode. LCDRPSTP 0 Stop LCD32F4BV1 driver system when in pseudo stop mode. 1 LCD operates normally in pseudo stop mode.
10.3.2.3
LCD Frontplane Enable Register 0–3 (FPENR0–FPENR3)
7 6 FP6EN 0 5 FP5EN 0 4 FP4EN 0 3 FP3EN 0 2 FP2EN 0 1 FP1EN 0 0 FP0EN 0
R FP7EN W Reset 0
Figure 10-4. LCD Frontplane Enable Register 0 (FPENR0)
7 R FP15EN W Reset 0 0 0 0 0 0 0 0 FP14EN FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN 6 5 4 3 2 1 0
Figure 10-5. LCD Frontplane Enable Register 1 (FPENR1)
7 R FP23EN W Reset 0 0 0 0 0 0 0 0 FP22EN FP21EN FP20EN FP19EN FP18EN FP17EN FP16EN 6 5 4 3 2 1 0
Figure 10-6. LCD Frontplane Enable Register 2 (FPENR2)
MC9S12XHZ512 Data Sheet, Rev. 1.03 430 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
7 R FP31EN W Reset 0
6 FP30EN 0
5 FP29EN 0
4 FP28EN 0
3 FP27EN 0
2 FP26EN 0
1 FP25EN 0
0 FP24EN 0
Figure 10-7. LCD Frontplane Enable Register 3 (FPENR3)
These bits enable the frontplane output waveform on the corresponding frontplane pin when LCDEN = 1. Read: anytime Write: anytime
Table 10-5. FPENR0–FPENR3 Field Descriptions
Field Description
31:0 Frontplane Output Enable — The FP[31:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these FP[31:0]EN bits have no effect on the state of the I/O pins. It is recommended to set FP[31:0]EN bits before LCDEN is set. 0 Frontplane driver output disabled on FP[31:0]. 1 Frontplane driver output enabled on FP[31:0].
10.3.2.4
LCD RAM (LCDRAM)
The LCD RAM consists of 16 bytes. After reset the LCD RAM contents will be indeterminate (I), as indicated by Figure 10-8.
7 R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset I = Value is indeterminate FP1BP3 I FP3BP3 I FP5BP3 I FP7BP3 I FP9BP3 I FP11BP3 I 6 FP1BP2 I FP3BP2 I FP5BP2 I FP7BP2 I FP9BP2 I FP11BP2 I 5 FP1BP1 I FP3BP1 I FP5BP1 I FP7BP1 I FP9BP1 I FP11BP1 I 4 FP1BP0 I FP3BP0 I FP5BP0 I FP7BP0 I FP9BP0 I FP11BP0 I 3 FP0BP3 I FP2BP3 I FP4BP3 I FP6BP3 I FP8BP3 I FP10BP3 I 2 FP0BP2 I FP2BP2 I FP4BP2 I FP6BP2 I FP8BP2 I FP10BP2 I 1 FP0BP1 I FP2BP1 I FP4BP1 I FP6BP1 I FP8BP1 I FP10BP1 I 0 FP0BP0 I FP2BP0 I FP4BP0 I FP6BP0 I FP8BP0 I FP10BP0 I
Figure 10-8. LCD RAM (LCDRAM)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 431
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset
FP13BP3 I FP15BP3 I FP17BP3 I FP19BP3 I FP21BP3 I FP23BP3 I FP25BP3 I FP27BP3 I FP29BP3 I FP31BP3 I
FP13BP2 I FP15BP2 I FP17BP2 I FP19BP2 I FP21BP2 I FP23BP2 I FP25BP2 I FP27BP2 I FP29BP2 I FP31BP2 I
FP13BP1 I FP15BP1 I FP17BP1 I FP19BP1 I FP21BP1 I FP23BP1 I FP25BP1 I FP27BP1 I FP29BP1 I FP31BP1 I
FP13BP0 I FP15BP0 I FP17BP0 I FP19BP0 I FP21BP0 I FP23BP0 I FP25BP0 I FP27BP0 I FP29BP0 I FP31BP0 I
FP12BP3 I FP14BP3 I FP16BP3 I FP18BP3 I FP20BP3 I FP22BP3 I FP24BP3 I FP26BP3 I FP28BP3 I FP30BP3 I
FP12BP2 I FP14BP2 I FP16BP2 I FP18BP2 I FP20BP2 I FP22BP2 I FP24BP2 I FP26BP2 I FP28BP2 I FP30BP2 I
FP12BP1 I FP14BP1 I FP16BP1 I FP18BP1 I FP20BP1 I FP22BP1 I FP24BP1 I FP26BP1 I FP28BP1 I FP30BP1 I
FP12BP0 I FP14BP0 I FP16BP0 I FP18BP0 I FP20BP0 I FP22BP0 I FP24BP0 I FP26BP0 I FP28BP0 I FP30BP0 I
I = Value is indeterminate
Figure 10-8. LCD RAM (LCDRAM) (continued)
Read: anytime Write: anytime
Table 10-6. LCD RAM Field Descriptions
Field 31:0 3:0 FP[31:0] BP[3:0] Description LCD Segment ON — The FP[31:0]BP[3:0] bit displays (turns on) the LCD segment connected between FP[31:0] and BP[3:0]. 0 LCD segment OFF 1 LCD segment ON
MC9S12XHZ512 Data Sheet, Rev. 1.03 432 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.4
Functional Description
This section provides a complete functional description of the LCD32F4BV1 block, detailing the operation of the design from the end user perspective in a number of subsections.
10.4.1
10.4.1.1
LCD Driver Description
Frontplane, Backplane, and LCD System During Reset
During a reset the following conditions exist: • The LCD32F4BV1 system is configured in the default mode, 1/4 duty and 1/3 bias, that means all backplanes are used. • All frontplane enable bits, FP[31:0]EN are cleared and the ON/OFF control for the display, the LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
10.4.1.2
LCD Clock and Frame Frequency
The frequency of the oscillator clock (OSCCLK) and divider determine the LCD clock frequency. The divider is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0). Table 10-7 shows the LCD clock and frame frequency for some multiplexed mode at OSCCLK = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, and 0.5 MHz.
Table 10-7. LCD Clock and Frame Frequency
Oscillator Frequency in MHz OSCCLK = 0.5 OSCCLK = 1.0 OSCCLK = 2.0 OSCCLK = 4.0 OSCCLK = 8.0 OSCCLK = 16.0 LCD Clock Prescaler Divider LCLK2 0 0 0 0 0 0 0 1 1 1 1 1 LCLK1 0 0 0 1 1 1 1 0 0 0 1 1 LCLK0 0 1 1 0 0 1 1 0 0 1 0 1 1024 2048 2048 4096 4096 8192 8192 16384 16384 32768 65536 131072 LCD Clock Frequency [Hz] 488 244 488 244 488 244 488 244 488 244 244 122 Frame Frequency [Hz] 1/1 Duty 488 244 488 244 488 244 488 244 488 244 244 122 1/2 Duty 244 122 244 122 244 122 244 122 244 122 122 61 1/3 Duty 163 81 163 81 163 81 163 81 163 81 81 40 1/4 Duty 122 61 122 61 122 61 122 61 122 61 61 31
For other combinations of OSCCLK and divider not shown in Table 10-7, the following formula may be used to calculate the LCD frame frequency for each multiplex mode: OSCCLK (Hz) LCD Frame Frequency (Hz) = ----------------------------------- ⋅ Duty Divider The possible divider values are shown in Table 10-7.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 433
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.4.1.3
LCD RAM
For a segment on the LCD to be displayed, data must be written to the LCD RAM which is shown in Section 10.3, “Memory Map and Register Definition”. The 128 bits in the LCD RAM correspond to the 128 segments that are driven by the frontplane and backplane drivers. Writing a 1 to a given location will result in the corresponding display segment being driven with a differential RMS voltage necessary to turn the segment ON when the LCDEN bit is set and the corresponding FP[31:0]EN bit is set. Writing a 0 to a given location will result in the corresponding display segment being driven with a differential RMS voltage necessary to turn the segment OFF. The LCD RAM is a dual port RAM that interfaces with the internal address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling purposes. When LCDEN = 0, the LCD RAM can be used as on-chip RAM. Writing or reading of the LCDEN bit does not change the contents of the LCD RAM. After a reset, the LCD RAM contents will be indeterminate.
10.4.1.4
LCD Driver System Enable and Frontplane Enable Sequencing
If LCDEN = 0 (LCD32F4BV1 driver system disabled) and the frontplane enable bit, FP[31:0]EN, is set, the frontplane driver waveform will not appear on the output until LCDEN is set. If LCDEN = 1 (LCD32F4BV1 driver system enabled), the frontplane driver waveform will appear on the output as soon as the corresponding frontplane enable bit, FP[31:0]EN, in the registers FPENR0–FPENR3 is set.
10.4.1.5
LCD Bias and Modes of Operation
The LCD32F4BV1 driver has five modes of operation: • 1/1 duty (1 backplane), 1/1 bias (2 voltage levels) • 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels) • 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) • 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) • 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) The voltage levels required for the different operating modes are generated internally based on VLCD. Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states, thereby setting the display contrast. The backplane waveforms are continuous and repetitive every frame. They are fixed within each operating mode and are not affected by the data in the LCD RAM. The frontplane waveforms generated are dependent on the state (ON or OFF) of the LCD segments as defined in the LCD RAM. The LCD32F4BV1 driver hardware uses the data in the LCD RAM to construct the frontplane waveform to create a differential RMS voltage necessary to turn the segment ON or OFF. The LCD duty is decided by the DUTY1 and DUTY0 bits in the LCD control register 0 (LCDCR0). The number of bias voltage levels is determined by the BIAS bit in LCDCR0. Table 10-8 summarizes the multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty). The backplane pins have their corresponding backplane waveform output BP[3:0] in high impedance state when in the OFF state as indicated in Table 10-8. In the OFF state the corresponding pins BP[3:0]can be used for other functionality, for example as general purpose I/O ports.
MC9S12XHZ512 Data Sheet, Rev. 1.03 434 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
Table 10-8. LCD Duty and Bias
LCDCR0 Register Duty DUTY1 1/1 1/2 1/3 1/4 0 1 1 0 DUTY0 1 0 1 0 BP3 OFF OFF OFF BP3 BP2 OFF OFF BP2 BP2 BP1 OFF BP1 BP1 BP1 BP0 BP0 BP0 BP0 BP0 1/1 YES NA NA NA 1/2 NA YES NA NA 1/3 NA NA YES YES 1/1 YES NA NA NA 1/2 NA NA NA NA 1/3 NA YES YES YES Backplanes Bias (BIAS = 0) Bias (BIAS = 1)
10.4.2
Operation in Wait Mode
The LCD32F4BV1 driver system operation during wait mode is controlled by the LCD stop in wait (LCDSWAI) bit in the LCD control register 1 (LCDCR1). If LCDSWAI is reset, the LCD32F4BV1 driver system continues to operate during wait mode. If LCDSWAI is set, the LCD32F4BV1 driver system is turned off during wait mode. In this case, the LCD waveform generation clocks are stopped and the LCD32F4BV1 drivers pull down to VSSX those frontplane and backplane pins that were enabled before entering wait mode. The contents of the LCD RAM and the LCD registers retain the values they had prior to entering wait mode.
10.4.3
Operation in Pseudo Stop Mode
The LCD32F4BV1 driver system operation during pseudo stop mode is controlled by the LCD run in pseudo stop (LCDRPSTP) bit in the LCD control register 1 (LCDCR1). If LCDRPSTP is reset, the LCD32F4BV1 driver system is turned off during pseudo stop mode. In this case, the LCD waveform generation clocks are stopped and the LCD32F4BV1 drivers pull down to VSSX those frontplane and backplane pins that were enabled before entering pseudo stop mode. If LCDRPSTP is set, the LCD32F4BV1 driver system continues to operate during pseudo stop mode. The contents of the LCD RAM and the LCD registers retain the values they had prior to entering pseudo stop mode.
10.4.4
Operation in Stop Mode
All LCD32F4BV1 driver system clocks are stopped, the LCD32F4BV1 driver system pulls down to VSSX those frontplane and backplane pins that were enabled before entering stop mode. Also, during stop mode, the contents of the LCD RAM and the LCD registers retain the values they had prior to entering stop mode. As a result, after exiting from stop mode, the LCD32F4BV1 driver system clocks will run (if LCDEN = 1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode.
10.4.5
LCD Waveform Examples
Figure 10-9 through Figure 10-13 show the timing examples of the LCD output waveforms for the available modes of operation.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 435
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.4.5.1
1/1 Duty Multiplexed with 1/1 Bias Mode
Duty = 1/1:DUTY1 = 0, DUTY0 = 1 Bias = 1/1:BIAS = 0 or BIAS = 1 V0 = V1 = VSSX, V2 = V3 = VLCD - BP1, BP2, and BP3 are not used, a maximum of 32 segments are displayed.
1 Frame VLCD BP0 VSSX VLCD FPx (xxx0) VSSX VLCD FPy (xxx1) VSSX +VLCD BP0-FPx (OFF) 0 -VLCD +VLCD BP0-FPy (ON) 0 -VLCD
Figure 10-9. 1/1 Duty and 1/1 Bias
MC9S12XHZ512 Data Sheet, Rev. 1.03 436 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.4.5.2
1/2 Duty Multiplexed with 1/2 Bias Mode
Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/2:BIAS = 0 V0 = VSSX, V1 = V2 = VLCD * 1/2, V3 = VLCD - BP2 and BP3 are not used, a maximum of 64 segments are displayed.
1 Frame VLCD VLCD × 1/2 VSSX VLCD VLCD × 1/2 VSSX VLCD VLCD × 1/2 VSSX VLCD VLCD × 1/2 VSSX VLCD VLCD × 1/2 VSSX +VLCD +VLCD × 1/2 0 -VLCD × 1/2 -VLCD +VLCD +VLCD × 1/2 0 -VLCD × 1/2 -VLCD +VLCD +VLCD × 1/2 0 -VLCD × 1/2 -VLCD +VLCD +VLCD × 1/2 0 -VLCD × 1/2 -VLCD
BP0
BP1
FPx (xx10)
FPy (xx00)
FPz (xx11)
BP0-FPx (OFF)
BP1-FPx (ON)
BP0-FPy (OFF)
BP0-FPz (ON)
Figure 10-10. 1/2 Duty and 1/2 Bias
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 437
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.4.5.3
1/2 Duty Multiplexed with 1/3 Bias Mode
Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/3:BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - BP2 and BP3 are not used, a maximum of 64 segments are displayed.
1 Frame VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD
BP0
BP1
FPx (xx10)
FPy (xx00)
FPz (xx11)
BP0-FPx (OFF)
BP1-FPx (ON)
BP0-FPy (OFF)
BP0-FPz (ON)
Figure 10-11. 1/2 Duty and 1/3 Bias
MC9S12XHZ512 Data Sheet, Rev. 1.03 438 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.4.5.4
1/3 Duty Multiplexed with 1/3 Bias Mode
Duty = 1/3:DUTY1 = 1, DUTY0 = 1 Bias = 1/3:BIAS = 0 or BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - BP3 is not used, a maximum of 96 segments are displayed.
1 Frame VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD
BP0
BP1
BP2
FPx (x010)
BP0-FPx (OFF)
BP1-FPx (ON)
Figure 10-12. 1/3 Duty and 1/3 Bias
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 439
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.4.5.5
1/4 Duty Multiplexed with 1/3 Bias Mode
Duty = 1/4:DUTY1 = 0, DUTY0 = 0 Bias = 1/3:BIAS = 0 or BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - A maximum of 128 segments are displayed.
1 Frame VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX VLCD VLCD × 2/3 VLCD × 1/3 VSSX +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD +VLCD +VLCD × 2/3 +VLCD × 1/3 0 -VLCD × 1/3 -VLCD × 2/3 -VLCD
BP0
BP1
BP2
BP3
FPx (1001)
BP0-FPx (ON)
BP1-FPx (OFF)
Figure 10-13. 1/4 Duty and 1/3 Bias
MC9S12XHZ512 Data Sheet, Rev. 1.03 440 Freescale Semiconductor
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
10.5
Resets
The reset values of registers and signals are described in Section 10.3, “Memory Map and Register Definition”. The behavior of the LCD32F4BV1 system during reset is described in Section 10.4.1, “LCD Driver Description”.
10.6
Interrupts
This module does not generate any interrupts.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 441
Chapter 10 Liquid Crystal Display (LCD32F4BV1)
MC9S12XHZ512 Data Sheet, Rev. 1.03 442 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.1 Introduction
The block MC10B12C is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring a PWM signal. The motor controller has twelve PWM channels associated with two pins each (24 pins in total).
11.1.1
Features
The MC_10B12C includes the following features: • 10/11-bit PWM counter • 11-bit resolution with selectable PWM dithering function • 7-bit resolution mode (fast mode): duty cycle can be changed by accessing only 1 byte/output • Left, right, or center aligned PWM • Output slew rate control • This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive capabilities of the module.
11.1.2
11.1.2.1
11.1.2.1.1
Modes of Operation
Functional Modes
PWM Resolution
The motor controller can be configured to either 11- or 7-bits resolution mode by clearing or setting the FAST bit. This bit influences all PWM channels. For details, please refer to Section 11.3.2.5, “Motor Controller Duty Cycle Registers”. 11.1.2.1.2 Dither Function
Dither function can be selected or deselected by setting or clearing the DITH bit. This bit influences all PWM channels. For details, please refer to Section 11.4.1.3.5, “Dither Bit (DITH)”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 443
Chapter 11 Motor Controller (MC10B12CV2)
11.1.2.2
PWM Channel Configuration Modes
The twelve PWM channels can operate in three functional modes. Those modes are, with some restrictions, selectable for each channel independently. 11.1.2.2.1 Dual Full H-Bridge Mode
This mode is suitable to drive a stepper motor or a 360o air gauge instrument. For details, please refer to Section 11.4.1.1.1, “Dual Full H-Bridge Mode (MCOM = 11)”. In this mode two adjacent PWM channels are combined, and two PWM channels drive four pins. 11.1.2.2.2 Full H-Bridge Mode
This mode is suitable to drive any load requiring a PWM signal in a H-bridge configuration using two pins. For details please refer to Section 11.4.1.1.2, “Full H-Bridge Mode (MCOM = 10)”. 11.1.2.2.3 Half H-Bridge Mode
This mode is suitable to drive a 90o instrument driven by one pin. For details, please refer to Section 11.4.1.1.3, “Half H-Bridge Mode (MCOM = 00 or 01)”.
11.1.2.3
PWM Alignment Modes
Each PWM channel can operate independently in three different alignment modes. For details, please refer to Section 11.4.1.3.1, “PWM Alignment Modes”.
11.1.2.4
Low-Power Modes
The behavior of the motor controller in low-power modes is programmable. For details, please refer to Section 11.4.5, “Operation in Wait Mode” and Section 11.4.6, “Operation in Stop and Pseudo-Stop Modes”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 444 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.1.3
Block Diagram
Control Registers FAST DITH
Period Register
11-Bit Timer/Counter 11
PWM Channel Pair PWM Channel M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P M4C0M M4C0P M4C1M M4C1P M5C0M M5C0P M5C1M M5C1P
Duty Register 0 Duty Register 1 Duty Register 2 Duty Register 3 Duty Register 4 Duty Register 5 Duty Register 6 Duty Register 7 Duty Register 8 Duty Register 9 Duty Register 10 Duty Register 11
Comparator Comparator Comparator Comparator Comparator Comparator Comparator Comparator Comparator Comparator Comparator Comparator
Figure 11-1. MC10B12C Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 445
Chapter 11 Motor Controller (MC10B12CV2)
11.2
External Signal Description
The motor controller is associated with 24 pins. Table 11-1 lists the relationship between the PWM channels and signal pins as well as PWM channel pair (motor number), coils, and nodes they are supposed to drive if all channels are set to dual full H-bridge configuration.
Table 11-1. PWM Channel and Pin Assignment
Pin Name M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P M4C0M M4C0P M4C1M M4C1P M5C0M M5C0P M5C1M M5C1P
1
PWM Channel 0 1 2 3 4 5 6 7 8 9 10 11
PWM Channel Pair1 0
Coil 0 1
Node Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus
1
0 1
2
0 1
3
0 1
4
0 1
5
0 1
A PWM Channel Pair always consists of PWM channel x and PWM channel x+1 (x = 2⋅n). The term “PWM Channel Pair” is equivalent to the term “Motor”. E.g. Channel Pair 0 is equivalent to Motor 0
11.2.1
M0C0M/M0C0P/M0C1M/M0C1P — PWM Output Pins for Motor 0
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 0. PWM output on M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high state.
MC9S12XHZ512 Data Sheet, Rev. 1.03 446 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.2.2
M1C0M/M1C0P/M1C1M/M1C1P — PWM Output Pins for Motor 1
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 1. PWM output on M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high state.
11.2.3
M2C0M/M2C0P/M2C1M/M2C1P — PWM Output Pins for Motor 2
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. PWM output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high state.
11.2.4
M3C0M/M3C0P/M3C1M/M3C1P — PWM Output Pins for Motor 3
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 3. PWM output on M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high state.
11.2.5
M4C0M/M4C0P/M4C1M/M4C1P — PWM Output Pins for Motor 4
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 4. PWM output on M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. PWM output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high state.
11.2.6
M5C0M/M5C0P/M5C1M/M5C1P — PWM Output Pins for Motor 5
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 5. PWM output on M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. PWM output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high state.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 447
Chapter 11 Motor Controller (MC10B12CV2)
11.3
Memory Map and Register Definition
This section provides a detailed description of all registers of the 10-bit 12-channel motor controller module.
11.3.1
Module Memory Map
Table 11-2. MC10B12C - Memory Map Address offset
$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 $22
Table 11-2 shows the memory map of the 10-bit 12-channel motor controller module.
Use
MCCTL0 MCCTL1 MCPER (high byte) MCPER (low byte) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MCCC0 MCCC1 MCCC2 MCCC3 MCCC4 MCCC5 MCCC6 MCCC7 MCCC8 MCCC9 MCCC10 MCCC11 Reserved Reserved Reserved Reserved MCDC0 (high byte) MCDC0 (low byte) MCDC1 (high byte) MC9S12XHZ512 Data Sheet, Rev. 1.03 448 Freescale Semiconductor
Access
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Chapter 11 Motor Controller (MC10B12CV2)
Table 11-2. MC10B12C - Memory Map
$23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F MCDC1 (low byte) MCDC2 (high byte) MCDC2 (low byte) MCDC3 (high byte) MCDC3 (low byte) MCDC4 (high byte) MCDC4 (low byte) MCDC5 (high byte) MCDC5 (low byte) MCDC6 (high byte) MCDC6 (low byte) MCDC7 (high byte) MCDC7 (low byte) MCDC8 (high byte) MCDC8 (low byte) MCDC9 (high byte) MCDC9 (low byte) MCDC10 (high byte) MCDC10 (low byte) MCDC11 (high byte) MCDC11 (low byte) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW -
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 449
Chapter 11 Motor Controller (MC10B12CV2)
11.3.2
11.3.2.1
Register Descriptions
Motor Controller Control Register 0
This register controls the operating mode of the motor controller module.
7 R W Reset 0 0 0 0 0 0 0 0 0 MCPRE[1:0] MCSWAI FAST DITH 6 5 4 3 2 1 0 MCTOIF 0
= Unimplemented or Reserved
Figure 11-3. Motor Controller Control Register 0 (MCCTL0) Table 11-3. MCCTL0 Field Descriptions
Field 6:5 MCPRE[1:0] Description Motor Controller Prescaler Select — MCPRE1 and MCPRE0 determine the prescaler value that sets the motor controller timer counter clock frequency (fTC). The clock source for the prescaler is the peripheral bus clock (fBUS) as shown in Figure 11-22. Writes to MCPRE1 or MCPRE0 will not affect the timer counter clock frequency fTC until the start of the next PWM period. Table 11-4 shows the prescaler values that result from the possible combinations of MCPRE1 and MCPRE0 Motor Controller Module Stop in Wait Mode 0 Entering wait mode has no effect on the motor controller module and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode. 1 Entering wait mode will stop the clock of the module and debias the analog circuitry. The module will release the pins. Motor Controller PWM Resolution Mode 0 PWM operates in 11-bit resolution mode, duty cycle registers of all channels are switched to word mode. 1 PWM operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode. Motor Control/Driver Dither Feature Enable (refer to Section 11.4.1.3.5, “Dither Bit (DITH)”) 0 Dither feature is disabled. 1 Dither feature is enabled. Motor Controller Timer Counter Overflow Interrupt Flag — This bit is set when a motor controller timer counter overflow occurs. The bit is cleared by writing a 1 to the bit. 0 A motor controller timer counter overflow has not occurred since the last reset or since the bit was cleared. 1 A motor controller timer counter overflow has occurred.
4 MCSWAI
3 FAST 2 DITH 0 MCTOIF
.
Table 11-4. Prescaler Values
MCPRE[1:0] 00 01 10 11 fTC fBus fBus/2 fBus/4 fBus/8
MC9S12XHZ512 Data Sheet, Rev. 1.03 450 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.3.2.2
Motor Controller Control Register 1
This register controls the behavior of the analog section of the motor controller as well as the interrupt enables.
7 R RECIRC W Reset 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 MCTOIE 0
= Unimplemented or Reserved
Figure 11-4. Motor Controller Control Register 1 (MCCTL1) Table 11-5. MCCTL1 Field Descriptions
Field 7 RECIRC Description Recirculation in (Dual) Full H-Bridge Mode (refer to Section 11.4.1.3.3, “RECIRC Bit”)— RECIRC only affects the outputs in (dual) full H-bridge modes. In half H-bridge mode, the PWM output is always active low. RECIRC = 1 will also invert the effect of the S bits (refer to Section 11.4.1.3.2, “Sign Bit (S)”) in (dual) full H-bridge modes. RECIRC must be changed only while no PWM channel is operating in (dual) full H-bridge mode; otherwise, erroneous output pattern may occur. 0 Recirculation on the high side transistors. Active state for PWM output is logic low, the static channel will output logic high. 1 Recirculation on the low side transistors. Active state for PWM output is logic high, the static channel will output logic low. Motor Controller Timer Counter Overflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the motor controller timer counter overflow interrupt flag (MCTOIF) is set.
0 MCTOIE
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 451
Chapter 11 Motor Controller (MC10B12CV2)
11.3.2.3
Motor Controller Period Register
The period register defines PER, the number of motor controller timer counter clocks a PWM period lasts. The motor controller timer counter is clocked with the frequency fTC. If dither mode is enabled (DITH = 1, refer to Section 11.4.1.3.5, “Dither Bit (DITH)”), P0 is ignored and reads as a 0. In this case PER = 2 * D[10:1].
15 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 13 0 12 0 11 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 10 9 8 7 6 5 4 3 2 1 0
= Unimplemented or Reserved
Figure 11-5. Motor Controller Period Register (MCPER) with DITH = 0
15 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 13 0 12 0 11 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 10 9 8 7 6 5 4 3 2 1 0 0
= Unimplemented or Reserved
Figure 11-6. Motor Controller Period Register (MCPER) with DITH = 1
For example, programming MCPER to 0x0022 (PER = 34 decimal) will result in 34 counts for each complete PWM period. Setting MCPER to 0 will shut off all PWM channels as if MCAM[1:0] is set to 0 in all channel control registers after the next period timer counter overflow. In this case, the motor controller releases all pins. NOTE Programming MCPER to 0x0001 and setting the DITH bit will be managed as if MCPER is programmed to 0x0000. All PWM channels will be shut off after the next period timer counter overflow.
MC9S12XHZ512 Data Sheet, Rev. 1.03 452 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.3.2.4
Motor Controller Channel Control Registers
Each PWM channel has one associated control register to control output delay, PWM alignment, and output mode. The registers are named MCCC0... MCCC11. In the following, MCCC0 is described as a reference for all twelve registers.
7 R MCOM1 W Reset 0 0 0 0 0 0 0 0 MCOM0 MCAM1 MCAM0 6 5 4 3 0 2 0 CD1 CD0 1 0
= Unimplemented or Reserved
Figure 11-7. Motor Controller Control Register Channel0
.. 11 (MCCC0 .. MCCC11)
Table 11-6. MCCC0–MCCC11 Field Descriptions
Field Description
7:6 Output Mode — MCOM1, MCOM0 control the PWM channel’s output mode. See Table 11-7. MCOM[1:0] 5:4 MCAM[1:0] PWM Channel Alignment Mode — MCAM1, MCAM0 control the PWM channel’s PWM alignment mode and operation. See Table 11-8. MCAM[1:0] and MCOM[1:0] are double buffered. The values used for the generation of the output waveform will be copied to the working registers either at once (if all PWM channels are disabled or MCPER is set to 0) or if a timer counter overflow occurs. Reads of the register return the most recent written value, which are not necessarily the currently active values. 1:0 CD[1:0] PWM Channel Delay — Each PWM channel can be individually delayed by a programmable number of PWM timer counter clocks. The delay will be n/fTC. See Table 11-9.
Table 11-7. Output Mode
MCOM[1:0] 00 01 10 11 Output Mode Half H-bridge mode, PWM on MnCxM, MnCxP is released Half H-bridge mode, PWM on MnCxP, MnCxM is released Full H-bridge mode Dual full H-bridge mode
Table 11-8. PWM Alignment Mode
MCAM[1:0] 00 01 10 11 PWM Alignment Mode Channel disabled Left aligned Right aligned Center aligned
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 453
Chapter 11 Motor Controller (MC10B12CV2)
Table 11-9. Channel Delay
CD[1:0] 00 01 10 11 n [# of PWM Clocks] 0 1 2 3
NOTE The PWM motor controller will release the pins after the next PWM timer counter overflow without accommodating any channel delay if a single channel has been disabled or if the period register has been cleared or all channels have been disabled. Program one or more inactive PWM frames (duty cycle = 0) before writing a configuration that disables a single channel or the entire PWM motor controller.
11.3.2.5
Motor Controller Duty Cycle Registers
Each duty cycle register sets the sign and duty functionality for the respective PWM channel. The contents of the duty cycle registers define DUTY, the number of motor controller timer counter clocks the corresponding output is driven low (RECIRC = 0) or is driven high (RECIRC = 1). Setting all bits to 0 will give a static high output in case of RECIRC = 0; otherwise, a static low output. Values greater than or equal to the contents of the period register will generate a static low output in case of RECIRC = 0, or a static high output if RECIRC = 1. The layout of the duty cycle registers differ dependent upon the state of the FAST bit in the control register 0.
15 R S W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 S 13 S 12 S 11 S D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 10 9 8 7 6 5 4 3 2 1 0
= Unimplemented or Reserved
Figure 11-8. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 0
15 R S W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 14 13 12 11 10 9 8 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 11-9. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 1
MC9S12XHZ512 Data Sheet, Rev. 1.03 454 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
Table 11-10. MCDCx Field Descriptions
Field 0 S Description SIGN — The SIGN bit is used to define which output will drive the PWM signal in (dual) full-H-bridge modes. The SIGN bit has no effect in half-bridge modes. See Section 11.4.1.3.2, “Sign Bit (S)”, and table Table 11-12 for detailed information about the impact of RECIRC and SIGN bit on the PWM output.
Whenever FAST = 1, the bits D10, D9, D1, and D0 will be set to 0 if the duty cycle register is written. For example setting MCDCx = 0x0158 with FAST = 0 gives the same output waveform as setting MCDCx = 0x5600 with FAST = 1 (with FAST = 1, the low byte of MCDCx needs not to be written). The state of the FAST bit has impact only during write and read operations. A change of the FAST bit (set or clear) without writing a new value does not impact the internal interpretation of the duty cycle values. To prevent the output from inconsistent signals, the duty cycle registers are double buffered. The motor controller module will use working registers to generate the output signals. The working registers are copied from the bus accessible registers at the following conditions: • MCPER is set to 0 (all channels are disabled in this case) • MCAM[1:0] of the respective channel is set to 0 (channel is disabled) • A PWM timer counter overflow occurs while in half H-bridge or full H-bridge mode • A PWM channel pair is configured to work in Dual Full H-Bridge mode and a PWM timer counter overflow occurs after the odd1 duty cycle register of the channel pair has been written. In this way, the output of the PWM will always be either the old PWM waveform or the new PWM waveform, not some variation in between. Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active sign, duty cycle, and dither functionality due to the double buffering scheme.
1. Odd duty cycle register: MCDCx+1, x = 2⋅n MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 455
Chapter 11 Motor Controller (MC10B12CV2)
11.4
11.4.1
Functional Description
Modes of Operation
PWM Output Modes
11.4.1.1
The motor controller is configurable between three output modes. • Dual full H-bridge mode can be used to control either a stepper motor or a 360° air core instrument. In this case two PWM channels are combined. • In full H-bridge mode, each PWM channel is updated independently. • In half H-bridge mode, one pin of the PWM channel can generate a PWM signal to control a 90° air core instrument (or other load requiring a PWM signal) and the other pin is unused. The mode of operation for each PWM channel is determined by the corresponding MCOM[1:0] bits in channel control registers. After a reset occurs, each PWM channel will be disabled, the corresponding pins are released. Each PWM channel consists of two pins. One output pin will generate a PWM signal. The other will operate as logic high or low output depending on the state of the RECIRC bit (refer to Section 11.4.1.3.3, “RECIRC Bit”), while in (dual) full H-bridge mode, or will be released, while in half H-bridge mode. The state of the S bit in the duty cycle register determines the pin where the PWM signal is driven in full H-bridge mode. While in half H-bridge mode, the state of the released pin is determined by other modules associated with this pin. Associated with each PWM channel pair n are two PWM channels, x and x + 1, where x = 2 * n and n (0,1,2... 5) is the PWM channel pair number. Duty cycle register x controls the sign of the PWM signal (which pin drives the PWM signal) and the duty cycle of the PWM signal for motor controller channel x. The pins associated with PWM channel x are MnC0P and MnC0M. Similarly, duty cycle register x + 1 controls the sign of the PWM signal and the duty cycle of the PWM signal for channel x + 1. The pins associated with PWM channel x + 1 are MnC1P and MnC1M. This is summarized in Table 11-11.
Table 11-11. Corresponding Registers and Pin Names for each PWM Channel Pair
PWM Channel Pair Number PWM Channel Control Register MCMCx n MCMCx+1 MCMC0 0 MCMC1 MCDC1 PWM Channel 1 MCDCx+1 MCDC0 Duty Cycle Register Channel Number Pin Names
MCDCx
PWM Channel x, x = 2⋅n PWM Channel x+1, x = 2⋅n PWM Channel 0
MnC0M MnC0P MnC1M MnC1P M0C0M M0C0P M0C1M M0C1P
MC9S12XHZ512 Data Sheet, Rev. 1.03 456 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
Table 11-11. Corresponding Registers and Pin Names for each PWM Channel Pair
PWM Channel Pair Number PWM Channel Control Register MCMC2 1 MCMC3 MCMC4 2 MCMC5 MCMC6 3 MCMC7 MCMC8 4 MCMC9 MCMC10 5 MCMC11 MCDC11 PWM Channel 11 MCDC9 MCDC10 PWM Channel 9 PWM Channel 10 MCDC7 MCDC8 PWM Channel 7 PWM Channel 8 MCDC5 MCDC6 PWM Channel 5 PWM Channel 6 MCDC3 MCDC4 PWM Channel 3 PWM Channel 4 Duty Cycle Register Channel Number Pin Names
M1C0M MCDC2 PWM Channel 2 M1C0P M1C1M M1C1P M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P M4C0M M4C0P M4C1M M4C1P M5C0M M5C0P M5C1M M5C1P
11.4.1.1.1
Dual Full H-Bridge Mode (MCOM = 11)
PWM channel pairs x and x + 1 operate in dual full H-bridge mode if both channels have been enabled (MCAM[1:0]=01, 10, or 11) and both of the corresponding output mode bits MCOM[1:0] in both PWM channel control registers are set. A typical configuration in dual full H-bridge mode is shown in Figure 11-10. PWM channel x drives the PWM output signal on either MnC0P or MnC0M. If MnC0P drives the PWM signal, MnC0M will be output either high or low depending on the RECIRC bit. If MnC0M drives the PWM signal, MnC0P will be an output high or low. PWM channel x + 1 drives the PWM output signal on either MnC1P or MnC1M. If MnC1P drives the PWM signal, MnC1M will be an output high or low. If MnC1M drives the PWM signal, MnC1P will be an output high or low. This results in motor recirculation currents on the high side drivers (RECIRC = 0) while the PWM signal is at a logic high level, or motor recirculation currents on the low side drivers (RECIRC = 1) while the PWM signal is at a logic low level. The pin driving the PWM signal is determined by the S (sign) bit in the corresponding duty cycle register and the state of the RECIRC bit. The value of the PWM duty cycle is determined by the value of the D[10:0] or D[8:2] bits respectively in the duty cycle register depending on the state of the FAST bit.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 457
Chapter 11 Motor Controller (MC10B12CV2)
PWM Channel x
MnC0P MnC0M
Motor n, Coil 0 Motor n, Coil 1
PWM Channel x + 1
MnC1P MnC1M
Figure 11-10. Typical Dual Full H-Bridge Mode Configuration
Whenever FAST = 0 only 16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses can lead to unpredictable duty cycles. While fast mode is enabled (FAST = 1), 8-bit write accesses to the high byte of the duty cycle registers are allowed, because only the high byte of the duty cycle register is used to determine the duty cycle. The following sequence should be used to update the current magnitude and direction for coil 0 and coil 1 of the motor to achieve consistent PWM output: 1. Write to duty cycle register x 2. Write to duty cycle register x + 1. At the next timer counter overflow, the duty cycle registers will be copied to the working duty cycle registers. Sequential writes to the duty cycle register x will result in the previous data being overwritten. 11.4.1.1.2 Full H-Bridge Mode (MCOM = 10)
In full H-bridge mode, the PWM channels x and x + 1 operate independently. The duty cycle working registers are updated whenever a timer counter overflow occurs. 11.4.1.1.3 Half H-Bridge Mode (MCOM = 00 or 01)
In half H-bridge mode, the PWM channels x and x + 1 operate independently. In this mode, each PWM channel can be configured such that one pin is released and the other pin is a PWM output. Figure 11-11 shows a typical configuration in half H-bridge mode. The two pins associated with each channel are switchable between released mode and PWM output dependent upon the state of the MCOM[1:0] bits in the MCCCx (channel control) register. See register description in Section 11.3.2.4, “Motor Controller Channel Control Registers”. In half H-bridge mode, the state of the S bit has no effect.
MC9S12XHZ512 Data Sheet, Rev. 1.03 458 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
VDDM
Released PWM Channel x MnC0P MnC0M PWM Output VDDM VSSM Released PWM Channel x + 1 MnC1P MnC1M PWM Output
VSSM
Figure 11-11. Typical Quad Half H-Bridge Mode Configuration
11.4.1.2
Relationship Between PWM Mode and PWM Channel Enable
The pair of motor controller channels cannot be placed into dual full H-bridge mode unless both motor controller channels have been enabled (MCAM[1:0] not equal to 00) and dual full H-bridge mode is selected for both PWM channels (MCOM[1:0] = 11). If only one channel is set to dual full H-bridge mode, this channel will operate in full H-bridge mode, the other as programmed.
11.4.1.3
11.4.1.3.1
Relationship Between Sign, Duty, Dither, RECIRC, Period, and PWM Mode Functions
PWM Alignment Modes
Each PWM channel can be programmed individually to three different alignment modes. The mode is determined by the MCAM[1:0] bits in the corresponding channel control register. Left aligned (MCAM[1:0] = 01): The output will start active (low if RECIRC = 0 or high if RECIRC = 1) and will turn inactive (high if RECIRC = 0 or low if RECIRC = 1) after the number of counts specified by the corresponding duty cycle register.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 459
Chapter 11 Motor Controller (MC10B12CV2)
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 1 Period 100 Counts 15 99 0 15 99 0
DITH = 0, MCAM[1:0] = 01, MCDCx = 15, MCPER = 100, RECIRC = 0
Right aligned (MCAM[1:0] = 10): The output will start inactive (high if RECIRC = 0 and low if RECIRC = 1) and will turn active after the number of counts specified by the difference of the contents of period register and the corresponding duty cycle register.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 1 Period 100 Counts 85 99 0 85 99 0
DITH = 0, MCAM[1:0] = 10, MCDCx = 15, MCPER = 100, RECIRC = 0
Center aligned (MCAM[1:0] = 11): Even periods will be output left aligned, odd periods will be output right aligned. PWM operation starts with the even period after the channel has been enabled. PWM operation in center aligned mode might start with the odd period if the channel has not been disabled before changing the alignment mode to center aligned.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 1 Period 100 Counts 15 99 0 85 99 0
DITH = 0, MCAM[1:0] = 11, MCDCx = 15, MCPER = 100, RECIRC = 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 460 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.4.1.3.2
Sign Bit (S)
Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding channel is cleared, MnC0P (if the PWM channel number is even, n = 0, 1, 2...5, see Table 11-11) or MnC1P (if the PWM channel number is odd, ,n = 0, 1, 2...5 see Table 11-11), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is generated on MnC0M (if the PWM channel number is even, n = 0, 1, 2...5, see Table 11-11) or MnC1M (if the PWM channel number is odd, n = 0, 1, 2...5). Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding channel is set, MnC0M (if the PWM channel number is even, n = 0, 1, 2...5, see Table 11-11) or MnC1M (if the PWM channel number is odd, n = 0, 1, 2...5, see Table 11-11), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is generated on MnC0P (if the PWM channel number is even, n = 0, 1, 2...5, see Table 11-11) or MnC1P (if the PWM channel number is odd, n = 0, 1, 2...5). Setting RECIRC = 1 will also invert the effect of the S bit such that while S = 0, MnC0P or MnC1P will generate the PWM signal and MnC0M or MnC1M will be a static low output. While S = 1, MnC0M or MnC1M will generate the PWM signal and MnC0P or MnC1P will be a static low output. In this case the active state of the PWM signal will be high. See Table 11-12 for detailed information about the impact of SIGN and RECIRC bit on the PWM output.
Table 11-12. Impact of RECIRC and SIGN Bit on the PWM Output
Output Mode (Dual) Full H-Bridge (Dual) Full H-Bridge (Dual) Full H-Bridge (Dual) Full H-Bridge Half H-Bridge: PWM on MnCyM Half H-Bridge: PWM on MnCyP
1
RECIRC 0 0 1 1 Don’t care Don’t care
SIGN 0 1 0 1 Don’t care Don’t care
MnCyM PWM1 1 0 PWM PWM —
MnCyP 1 PWM PWM2 1 —3 PWM
PWM: The PWM signal is low active. e.g., the waveform starts with 0 in left aligned mode. Output M generates the PWM signal. Output P is static high. 2 PWM: The PWM signal is high active. e.g., the waveform starts with 1 in left aligned mode. output P generates the PWM signal. Output M is static low. 3 The state of the output transistors is not controlled by the motor controller.
11.4.1.3.3
RECIRC Bit
The RECIRC bit controls the flow of the recirculation current of the load. Setting RECIRC = 0 will cause recirculation current to flow through the high side transistors, and RECIRC = 1 will cause the recirculation current to flow through the low side transistors. The RECIRC bit is only active in (dual) full H-bridge modes. Effectively, RECIRC = 0 will cause a static high output on the output terminal not driven by the PWM, RECIRC = 1 will cause a static low output on the output terminals not driven by the PWM. To achieve the same current direction, the S bit behavior is inverted if RECIRC = 1. Figure 11-12, Figure 11-13, Figure 11-14, and Figure 11-15 illustrate the effect of the RECIRC bit in (dual) full H-bridge modes.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 461
Chapter 11 Motor Controller (MC10B12CV2)
RECIRC bit must be changed only while no PWM channel is operated in (dual) full H-bridge mode.
VDDM
Static 0
PWM 1
MnC0P Static 0
MnC0M PWM 1
VSSM
Figure 11-12. PWM Active Phase, RECIRC = 0, S = 0
VDDM
Static 0
PWM 0
MnC0P Static 0
MnC0M PWM 0
VSSM
Figure 11-13. PWM Passive Phase, RECIRC = 0, S = 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 462 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
VDDM
PWM 0
Static 1
MnC0P PWM 0 VSSM
MnC0M Static 1
Figure 11-14. PWM Active Phase, RECIRC = 1, S = 0
VDDM
PWM 1
Static 1
MnC0P PWM 1
MnC0M Static 1
VSSM
Figure 11-15. PWM Passive Phase, RECIRC = 1, S = 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 463
Chapter 11 Motor Controller (MC10B12CV2)
11.4.1.3.4
Relationship Between RECIRC Bit, S Bit, MCOM Bits, PWM State, and Output Transistors
Please refer to Figure 11-16 for the output transistor assignment.
VDDM
T1
T3
MnCyP T2
MnCyM T4
VSSM
Figure 11-16. Output Transistor Assignment
Table 11-13 illustrates the state of the output transistors in different states of the PWM motor controller module. ‘—’ means that the state of the output transistor is not controlled by the motor controller.
Table 11-13. State of Output Transistors in Various Modes
Mode Off Half H-Bridge Half H-Bridge Half H-Bridge Half H-Bridge (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full MCOM[1:0] Don’t care 00 00 01 01 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 PWM Duty — Active Passive Active Passive Active Passive Active Passive Active Passive Active Passive RECIRC Don’t care Don’t care Don’t care Don’t care Don’t care 0 0 0 0 1 1 1 1 S Don’t care Don’t care Don’t care Don’t care Don’t care 0 0 1 1 0 0 1 1 T1 — — — OFF ON ON ON OFF ON ON OFF OFF OFF T2 — — — ON OFF OFF OFF ON OFF OFF ON ON ON T3 — OFF ON — — OFF ON ON ON OFF OFF ON OFF T4 — ON OFF — — ON OFF OFF OFF ON ON OFF ON
MC9S12XHZ512 Data Sheet, Rev. 1.03 464 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.4.1.3.5
Dither Bit (DITH)
The purpose of the dither mode is to increase the minimum length of output pulses without decreasing the PWM resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. If dither mode is selected the output pattern will repeat after two timer counter overflows. For the same output frequency, the shortest output pulse will have twice the length while dither feature is selected. To achieve the same output frame frequency, the prescaler of the MC10B12C module has to be set to twice the division rate if dither mode is selected; e.g., with the same prescaler division rate the repeat rate of the output pattern is the same as well as the shortest output pulse with or without dither mode selected. The DITH bit in control register 0 enables or disables the dither function. DITH = 0: dither function is disabled. When DITH is cleared and assuming left aligned operation and RECIRC = 0, the PWM output will start at a logic low level at the beginning of the PWM period (motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 11-bit PWM duty cycle value, DUTY, contained in D[10:0] in MCDCx. When a match (output compare between motor controller timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the contents of MCPER – 1). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This completes one PWM period. The PWM period repeats every P counts (as defined by the bits P[10:0] in the motor controller period register) of the motor controller timer counter. If DUTY >= P, the output will be static low. If DUTY = 0x0000, the output will be continuously at a logic high level. The relationship between the motor controller timer counter clock, motor controller timer counter value, and PWM output while DITH = 0 is shown in Figure 11-17.
Motor Controller Timer Counter Clock Motor Controller Timer Counter
0
100
199 0
100
199 0
PWM Output 1 Period 200 Counts 1 Period 200 Counts
Figure 11-17. PWM Output: DITH = 0, MCAM[1:0] = 01, MCDC = 100, MCPER = 200, RECIRC = 0
DITH = 1: dither function is enabled Please note if DITH = 1, the bit P0 in the motor controller period register will be internally forced to 0 and read always as 0. When DITH is set and assuming left aligned operation and RECIRC = 0, the PWM output will start at a logic low level at the beginning of the PWM period (when the motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 10-bit PWM duty cycle
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 465
Chapter 11 Motor Controller (MC10B12CV2)
value, DUTY, contained in D[10:1] in MCDCx. When a match (output compare between motor controller timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This completes the first half of the PWM period. During the second half of the PWM period, the PWM output will remain at a logic low level until either the motor controller timer counter matches the 10-bit PWM duty cycle value, DUTY, contained in D[10:1] in MCDCx if D0 = 0, or the motor controller timer counter matches the 10-bit PWM duty cycle value + 1 (the value of D[10:1] in MCDCx is increment by 1 and is compared with the motor controller timer counter value) if D0 = 1 in the corresponding duty cycle register. When a match occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This process will repeat every number of counts of the motor controller timer counter defined by the period register contents (P[10:0]). If the output is neither set to 0% nor to 100% there will be four edges on the PWM output per PWM period in this case. Therefore, the PWM output compare function will alternate between DUTY and DUTY + 1 every half PWM period if D0 in the corresponding duty cycle register is set to 1. The relationship between the motor controller timer counter clock (fTC), motor controller timer counter value, and left aligned PWM output if DITH = 1 is shown in Figure 11-18 and Figure 11-19. Figure 11-20 and Figure 11-21 show right aligned and center aligned PWM operation respectively, with dither feature enabled and D0 = 1. Please note: In the following examples, the MCPER value is defined by the bits P[10:0], which is, if DITH = 1, always an even number. NOTE The DITH bit must be changed only if the motor controller is disabled (all channels disabled or period register cleared) to avoid erroneous waveforms.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 100 Counts 15 16 99 0 15 16 99 0
Figure 11-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 466 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
Motor Controller Timer Counter Clock Motor Controller Timer Counter PWM Output 1 Period 100 Counts 100 Counts 0 15 16 99 0 15 16 99 0
Figure 11-19. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 30, MCPER = 200, RECIRC = 0
.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 100 Counts 84 85 99 0 84 85 99 0
Figure 11-20. PWM Output: DITH = 1, MCAM[1:0] = 10, MCDC = 31, MCPER = 200, RECIRC = 0
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 100 Counts 15 99 0 84 99 0
Figure 11-21. PWM Output: DITH = 1, MCAM[1:0] = 11, MCDC = 31, MCPER = 200, RECIRC = 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 467
Chapter 11 Motor Controller (MC10B12CV2)
11.4.2
PWM Duty Cycle
The PWM duty cycle for the motor controller channel x can be determined by dividing the decimal representation of bits D[10:0] in MCDCx by the decimal representation of the bits P[10:0] in MCPER and multiplying the result by 100% as shown in the equation below: DUTY Effective PWM Channel X % Duty Cycle = --------------------- ⋅ 100% MCPER NOTE x = PWM Channel Number = 0, 1, 2, 3 ... 11. This equation is only valid if DUTY = P[10:0], a constant low level (RECIRC = 0) or high level (RECIRC = 1) will be output.
11.4.3
Motor Controller Counter Clock Source
Figure 11-22 shows how the PWM motor controller timer counter clock source is selected.
Clock Generator CLK Peripheral Bus Clock fBUS Clocks and Reset Generator Module
Motor Controller Timer Counter Clock Prescaler Select MPPRE0, MPPRE1
1 1/2 1/4 1/8
Motor Controller Timer Counter Clock fTC
11-Bit Motor Controller Timer Counter
Motor Controller Timer Counter Prescaler
Figure 11-22. Motor Controller Counter Clock Selection
The peripheral bus clock is the source for the motor controller counter prescaler. The motor controller counter clock rate, fTC, is set by selecting the appropriate prescaler value. The prescaler is selected with the MCPRE[1:0] bits in motor controller control register 0 (MCCTL0). The motor controller channel frequency of operation can be calculated using the following formula if DITH = 0: fTC Motor Channel Frequency (Hz) = -----------------------------MCPER ⋅ M
MC9S12XHZ512 Data Sheet, Rev. 1.03 468 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
The motor controller channel frequency of operation can be calculated using the following formula if DITH = 1: fTC Motor Channel Frequency (Hz) = ------------------------------------MCPER ⋅ M ⁄ 2 NOTE Both equations are only valid if MCPER is not equal to 0. M = 1 for left or right aligned mode, M = 2 for center aligned mode. Table 11-14 shows examples of the motor controller channel frequencies that can be generated based on different peripheral bus clock frequencies and the prescaler value.
Table 11-14. Motor Controller Channel Frequencies (Hz), MCPER = 256, DITH = 0, MCAM = 10, 01
Peripheral Bus Clock Frequency Prescaler 1 1/2 1/4 1/8 16 MHz 62500 31250 15625 7813 10 MHz 39063 19531 9766 4883 8 MHz 31250 15625 7813 3906 5 MHz 19531 9766 4883 2441 4 MHz 15625 7813 3906 1953
NOTE Due to the selectable slew rate control of the outputs, clipping may occur on short output pulses.
11.4.4
Output Switching Delay
In order to prevent large peak current draw from the motor power supply, selectable delays can be used to stagger the high logic level to low logic level transitions on the motor controller outputs. The timing delay, td, is determined by the CD[1:0] bits in the corresponding channel control register (MCMCx) and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. NOTE A PWM channel gets disabled at the next timer counter overflow without notice of the switching delay.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 469
Chapter 11 Motor Controller (MC10B12CV2)
11.4.5
Operation in Wait Mode
During wait mode, the operation of the motor controller pins are selectable between the following two options: 1. MCSWAI = 1: All module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the RECIRC bit during wait mode. The motor controller module registers stay the same as they were prior to entering wait mode. Therefore, after exiting from wait mode, the associated port pins will resume to the same functionality they had prior to entering wait mode. 2. MCSWAI = 0: The PWM clocks continue to run and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode.
11.4.6
Operation in Stop and Pseudo-Stop Modes
All module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the RECIRC bit. The motor controller module registers stay the same as they were prior to entering stop or pseudo-stop modes. Therefore, after exiting from stop or pseudo-stop modes, the associated port pins will resume to the same functionality they had prior to entering stop or pseudo-stop modes.
11.5
Reset
The motor controller is reset by system reset. All associated ports are released, all registers of the motor controller module will switch to their reset state as defined in Section 11.3.2, “Register Descriptions”.
11.6
Interrupts
The motor controller has one interrupt source.
11.6.1
Timer Counter Overflow Interrupt
An interrupt will be requested when the MCTOIE bit in the motor controller control register 1 is set and the running PWM frame is finished. The interrupt is cleared by either setting the MCTOIE bit to 0 or to write a 1 to the MCTOIF bit in the motor controller control register 0.
MC9S12XHZ512 Data Sheet, Rev. 1.03 470 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
11.7
Initialization/Application Information
This section provides an example of how the PWM motor controller can be initialized and used by application software. The configuration parameters (e.g., timer settings, duty cycle values, etc.) are not guaranteed to be adequate for any real application. The example software is implemented in assembly language.
11.7.1
Code Example
One way to use the motor controller is: 1. Perform global initialization a) Set the motor controller control registers MCCTL0 and MCCTL1 to appropriate values. i) Prescaler disabled (MCPRE1 = 0, MCPRE0 = 0). ii) Fast mode and dither disabled (FAST = 0, DITH = 0). iii) Recirculation feature in dual full H-bridge mode disabled (RECIRC = 0). All other bits in MCCTL0 and MCCTL1 are set to 0. b) Configure the channel control registers for the desired mode. i) Dual full H-bridge mode (MCOM[1:0] = 11). ii) Left aligned PWM (MCAM[1:0] = 01). iii) No channel delay (MCCD[1:0] = 00). 2. Perform the startup phase a) Clear the duty cycle registers MCDC0 and MCDC1 b) Initialize the period register MCPER, which is equivalent to enabling the motor controller. c) Enable the timer which generates the timebase for the updates of the duty cycle registers. 3. Main program a) Check if pin PB0 is set to “1” and execute the sub program if a timer interrupt is pending. b) Initiate the shutdown procedure if pin PB0 is set to “0”. 4. Sub program a) Update the duty cycle registers Load the duty cycle registers MCDC0 and MCDC1 with new values from the table and clear the timer interrupt flag. The sub program will initiate the shutdown procedure if pin PB0 is set to “0”. b) Shutdown procedure The timer is disabled and the duty cycle registers are cleared to drive an inactive value on the PWM output as long as the motor controller is enabled. The period register is cleared after a certain time, which disables the motor controller. The table address is restored and the timer interrupt flag is cleared.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 471
Chapter 11 Motor Controller (MC10B12CV2)
;-----------------------------------------------------------------------------------------; Motor Controller (MC10B8C) setup example ;-----------------------------------------------------------------------------------------; Timer defines ;-----------------------------------------------------------------------------------------T_START EQU $0040 TSCR1 EQU T_START+$06 TFLG2 EQU T_START+$0F ;-----------------------------------------------------------------------------------------; Motor Controller defines ;-----------------------------------------------------------------------------------------MC_START EQU $0200 MCCTL0 EQU MC_START+$00 MCCTL1 EQU MC_START+$01 MCPER_HI EQU MC_START+$02 MCPER_LO EQU MC_START+$03 MCCC0 EQU MC_START+$10 MCCC1 EQU MC_START+$11 MCCC2 EQU MC_START+$12 MCCC3 EQU MC_START+$13 MCDC0_HI EQU MC_START+$20 MCDC0_LO EQU MC_START+$21 MCDC1_HI EQU MC_START+$22 MCDC1_LO EQU MC_START+$23 MCDC2_HI EQU MC_START+$24 MCDC2_LO EQU MC_START+$25 MCDC3_HI EQU MC_START+$26 MCDC3_LO EQU MC_START+$27 ;-----------------------------------------------------------------------------------------; Port defines ;-----------------------------------------------------------------------------------------DDRB EQU $0003 PORTB EQU $0001 ;-----------------------------------------------------------------------------------------; Flash defines ;-----------------------------------------------------------------------------------------FLASH_START EQU $0100 FCMD EQU FLASH_START+$06 FCLKDIV EQU FLASH_START+$00 FSTAT EQU FLASH_START+$05 FTSTMOD EQU FLASH_START+$02 ; Variables CODE_START EQU $1000 ; start of program code DTYDAT EQU $1500 ; start of motor controller duty cycle data TEMP_X EQU $1700 ; save location for IX reg in ISR TABLESIZE EQU $1704 ; number of config entries in the table MCPERIOD EQU $0250 ; motor controller period ;-----------------------------------------------------------------------------------------;-----------------------------------------------------------------------------------------ORG CODE_START ; start of code LDS #$1FFF ; set stack pointer MOVW #$000A,TABLESIZE ; number of configurations in the table MOVW TABLESIZE,TEMP_X
MC9S12XHZ512 Data Sheet, Rev. 1.03 472 Freescale Semiconductor
Chapter 11 Motor Controller (MC10B12CV2)
;-----------------------------------------------------------------------------------------;global motor controller init ;-----------------------------------------------------------------------------------------GLB_INIT: MOVB #$0000,MCCTL0 ; fMC = fBUS, FAST=0, DITH=0 MOVB #$0000,MCCTL1 ; RECIRC=0, MCTOIE=0 MOVW #$D0D0,MCCC0 ; dual full h-bridge mode, left aligned, ; no channel delay MOVW #$0000,MCPER_HI ; disable motor controller ;-----------------------------------------------------------------------------------------;motor controller startup ;-----------------------------------------------------------------------------------------STARTUP: MOVW #$0000,MCDC0_HI ; define startup duty cycles MOVW #$0000,MCDC1_HI MOVW #MCPERIOD,MCPER_HI ; define PWM period MOVB #$80,TSCR1 ; enable timer MAIN: LDAA PORTB ; if PB=0, activate shutdown ANDA #$01 BEQ MN0 JSR TIM_SR MN0: TST TFLG2 ; poll for timer counter overflow flag BEQ MAIN ; TOF set? JSR TIM_SR ; yes, go to TIM_SR BRA MAIN TIM_SR: LDX TEMP_X ; restore index register X LDAA PORTB ; if PB=0, enter shutdown routine ANDA #$01 BNE SHUTDOWN LDX TEMP_X ; restore index register X BEQ NEW_SEQ ; all mc configurations done? NEW_CFG: LDD DTYDAT,X ; load new config’s STD MCDC0_HI DEX DEX LDD DTYDAT,X STD MCDC1_HI BRA END_SR ; leave sub-routine SHUTDOWN: MOVB #$00,TSCR1 ; disable timer MOVW #$0000,MCDC0_HI ; define startup duty cycle MOVW #$0000,MCDC1_HI ; define startup duty cycle LDAA #$0000 ; ensure that duty cycle registers are ; cleared for some time before disabling ; the motor controller LOOP DECA BNE LOOP MOVW #$0000,MCPER_HI ; define pwm period NEW_SEQ: MOVW TABLESIZE,TEMP_X ; start new tx loop LDX TEMP_X END_SR: STX TEMP_X ; save byte counter MOVB #$80,TFLG2 ; clear TOF RTS ; wait for new timer overflow
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 473
Chapter 11 Motor Controller (MC10B12CV2)
;-----------------------------------------------------------------------------------------; motor controller duty cycles ;-----------------------------------------------------------------------------------------org DTYDAT DC.B $02, $FF1; MCDC1_HI, MCDC1_LO DC.B $02, $D0 ; MCDC0_HI, MCDC0_LO DC.B $02, $A0 ; MCDC1_HI, MCDC1_LO DC.B $02, $90 ; MCDC0_HI, MCDC0_LO DC.B $02, $60 ; MCDC1_HI, MCDC1_LO DC.B $02, $25 ; MCDC0_HI, MCDC0_LO
1. The values for the duty cycle table have to be defined for the needs of the target application. MC9S12XHZ512 Data Sheet, Rev. 1.03 474 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
12.1 Introduction
The stepper stall detector (SSD) block provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ). During the RTZ event, the pointer is returned to zero using full steps in either clockwise or counter clockwise direction, where only one coil is driven at any point in time. The back electromotive force (EMF) signal present on the non-driven coil is integrated after a blanking time, and its results stored in a 16-bit accumulator. The 16-bit modulus down counter can be used to monitor the blanking time and the integration time. The value in the accumulator represents the change in linked flux (magnetic flux times the number of turns in the coil) and can be compared to a stored threshold. Values above the threshold indicate a moving motor, in which case the pointer can be advanced another full step in the same direction and integration be repeated. Values below the threshold indicate a stalled motor, thereby marking the cessation of the RTZ event. The SSD is capable of multiplexing two stepper motors.
12.1.1
•
Modes of Operation
•
Return to zero modes — Blanking with no drive — Blanking with drive — Conversion — Integration Low-power modes
12.1.2
• • • • • •
Features
Programmable full step state Programmable integration polarity Blanking (recirculation) state 16-bit integration accumulator register 16-bit modulus down counter with interrupt Multiplex two stepper motors
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 475
Chapter 12 Stepper Stall Detector (SSDV1)
12.1.3
Block Diagram
Coil COSx x = A or B Coil SINx
VDDM
VDDM
VDDM
VDDM
T1
COSxP COSxM
T3
T5
SINxP SINxM
T7
P A D
T2
S1 S2
S3 S4 T4
P A D
P A D
T6
S5 S6
S7 S8 T8
P A D
VSSM
VSSM
VSSM
VSSM
reference integrator
DAC C1
R1
– +
VDDM
–
DFF
+
16-bit accumulator register 16-bit load register 16-bit modulus down counter
R2
R2
sigma-delta converter (analog)
VSSM
4:1 MUX
2:1 MUX
Bus Clock
1/32
1/2
1/2
1/2
1/2
Figure 12-1. SSD Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 476 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
12.2
External Signal Description
Each SSD signal is the output pin of a half bridge, designed to source or sink current. The H-bridge pins drive the sine and cosine coils of a stepper motor to provide four-quadrant operation. The SSD is capable of multiplexing between stepper motor A and stepper motor B if two motors are connected.
Table 12-1. Pin Table1
Pin Name COSxM COSxP SINxM SINxP
1
Node Minus Plus Minus Plus
Coil COSx
SINx
x = A or B indicating motor A or motor B
12.2.1
COSxM/COSxP — Cosine Coil Pins for Motor x
These pins interface to the cosine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position.
12.2.2
SINxM/SINxP — Sine Coil Pins for Motor x
These pins interface to the sine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 477
Chapter 12 Stepper Stall Detector (SSDV1)
12.3
Memory Map and Register Definition
This section provides a detailed description of all registers of the stepper stall detector (SSD) block.
12.3.1
Module Memory Map
Table 12-2 gives an overview of all registers in the SSDV1 memory map. The SSDV1 occupies eight bytes in the memory space. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and is given in the Device Overview chapter. The address offset is defined at the block level and is given here.
Table 12-2. SSDV1 Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 RTZCTL MDCCTL SSDCTL SSDFLG MDCCNT (High) MDCCNT (Low) ITGACC (High) ITGACC (Low) Use Access R/W R/W R/W R/W R/W R/W R R
12.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the SSDV1 block. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
MC9S12XHZ512 Data Sheet, Rev. 1.03 478 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
12.3.2.1
Return-to-Zero Control Register (RTZCTL)
7 6 5 4 3 2 1 0
R ITG W Reset 0 0 0 0 DCOIL RCIR POL
0 SMS 0 0 0 STEP 0
= Unimplemented or Reserved
Figure 12-2. Return-to-Zero Control Register (RTZCTL)
Read: anytime Write: anytime
Table 12-3. RTZCTL Field Descriptions
Field 7 ITG Description Integration — During return to zero (RTZE = 1), one of the coils must be recirculated or non-driven determined by the STEP field. If the ITG bit is set, the coil is non-driven, and if the ITG bit is clear, the coil is being recirculated. Table 12-4 shows the condition state of each transistor from Figure 12-1 based on the STEP, ITG, DCOIL and RCIR bits. Regardless of the RTZE bit value, if the ITG bit is set, one end of the non-driven coil connects to the (non-zero) reference input and the other end connects to the integrator input of the sigma-delta converter. Regardless of the RTZE bit value, if the ITG bit is clear, the non-driven coil is in a blanking state, the converter is in a reset state, and the accumulator is initialized to zero. Table 12-5 shows the condition state of each switch from Figure 12-1 based on the ITG, STEP and POL bits. 0 Blanking 1 Integration Drive Coil — During return to zero (RTZE=1), one of the coils must be driven determined by the STEP field. If the DCOIL bit is set, this coil is driven. If the DCOIL bit is clear, this coil is disconnected or drivers turned off. Table 12-4 shows the condition state of each transistor from Figure 12-1 based on the STEP, ITG, DCOIL and RCIR bits. 0 Disconnect Coil 1 Drive Coil Recirculation in Blanking Mode — During return to zero (RTZE = 1), one of the coils is recirculated prior to integration during the blanking period. This bit determines if the coil is recirculated via VDDM or via VSSM. Table 12-4 shows the condition state of each transistor from Figure 12-1 based on the STEP, ITG, DCOIL and RCIR bits. 0 Recirculation on the high side transistors 1 Recirculation on the low side transistors Polarity — This bit determines which end of the non-driven coil is routed to the sigma-delta converter during conversion or integration mode. Table 12-5 shows the condition state of each switch from Figure 12-1 based on the ITG, STEP and POL bits. Stepper Motor Select — This bit selects one of two possible stepper motors to be used for stall detection. See top level chip description for the stepper motor assignments to the SSD. 0 Stepper Motor A is selected for stall detection 1 Stepper Motor B is selected for stall detection Full Step State — This field indicates one of the four possible full step states. Step 0 is considered the east pole or 0° angle, step 1 is the north Pole or 90° angle, step 2 is the west pole or 180° angle, and step 3 is the south pole or 270° angle. For each full step state, Table 12-6 shows the current through each of the two coils, and the coil nodes that are multiplexed to the sigma-delta converter during conversion or integration mode.
6 DCOIL
5 RCIR
4 POL 2 SMS
1:0 STEP
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 479
Chapter 12 Stepper Stall Detector (SSDV1)
Table 12-4. Transistor Condition States (RTZE = 1)
STEP xx 00 00 00 00 00 01 01 01 01 01 10 10 10 10 10 11 11 11 11 11 ITG 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 DCOIL 0 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 RCIR x 0 1 0 1 x 0 1 0 1 x 0 1 0 1 x 0 1 0 1 x T1 OFF OFF OFF ON ON ON ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF T2 OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON ON ON OFF ON OFF ON OFF T3 OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF OFF ON ON ON ON OFF ON OFF OFF T4 OFF OFF OFF ON ON ON OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF T5 OFF ON OFF ON OFF OFF OFF OFF ON ON ON ON OFF ON OFF OFF OFF OFF OFF OFF OFF T6 OFF OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON ON ON T7 OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF OFF ON ON ON T8 OFF OFF ON OFF ON OFF OFF OFF ON ON ON OFF ON OFF ON OFF OFF OFF OFF OFF OFF
Table 12-5. Switch Condition States (RTZE = 1 or 0)
ITG 0 1 1 1 1 1 1 1 1 STEP xx 00 00 01 01 10 10 11 11 POL x 0 1 0 1 0 1 0 1 S1 Open Open Open Open Close Open Open Close Open S2 Open Open Open Close Open Open Open Open Close S3 Open Open Open Close Open Open Open Open Close S4 Open Open Open Open Close Open Open Close Open S5 Open Close Open Open Open Open Close Open Open S6 Open Open Close Open Open Close Open Open Open S7 Open Open Close Open Open Close Open Open Open S8 Open Close Open Open Open Open Close Open Open
MC9S12XHZ512 Data Sheet, Rev. 1.03 480 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
Table 12-6. Full Step States
COSINE Coil Current STEP Pole Angle DCOIL = 0 DCOIL = 1 DCOIL = 0 DCOIL = 1 0 1 2 3 East North West South 0° 90° 180° 270° 0 0 0 0 + I max 0 – I max 0 0 0 0 0 0 + I max 0 – I max SINE Coil Current Coil Node to Integrator input (Close Switch) ITG = 1 POL = 0 SINxM (S8) ITG = 1 POL = 1 SINxP (S6) Coil Node to Reference input (Close Switch) ITG = 1 POL = 0 SINxP (S5) ITG = 1 POL = 1 SINxM (S7)
COSxP (S2) COSxM (S4) COSxM (S3) COSxP (S1) SINxP (S6) SINxM (S8) SINxM (S7) SINxP (S5)
COSxM (S4) COSxP (S2) COSxP (S1) COSxM (S3)
12.3.2.2
Modulus Down Counter Control Register (MDCCTL)
7 6 5 4 3 2 1 0
R MCZIE W Reset 0 0 0 0 MODMC RDMCL PRE
0 MCEN FLMC 0 0
0 AOVIE 0 0
= Unimplemented or Reserved
Figure 12-3. Modulus Down Counter Control Register (MDCCTL)
Read: anytime Write: anytime.
l
Table 12-7. MDCCTL Field Descriptions
Field 7 MCZIE Description Modulus Counter Underflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the modulus counter underflow interrupt flag (MCZIF) is set. Modulus Mode Enable 0 The modulus counter counts down from the value in the counter register and will stop at 0x0000. 1 Modulus mode is enabled. When the counter reaches 0x0000, the counter is loaded with the latest value written to the modulus counter register. Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to 0xFFFF. Read Modulus Down-Counter Load 0 Reads of the modulus count register (MDCCNT) will return the present value of the count register. 1 Reads of the modulus count register (MDCCNT) will return the contents of the load register. Prescaler 0 The modulus down counter clock frequency is the bus frequency divided by 64. 1 The modulus down counter clock frequency is the bus frequency divided by 512. Note: A change in the prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs.
6 MODMC
5 RDMCL 4 PRE
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 481
Chapter 12 Stepper Stall Detector (SSDV1)
Table 12-7. MDCCTL Field Descriptions (continued)
Field 3 FLMC 2 MCEN Description Force Load Register into the Modulus Counter Count Register — This bit always reads zero. 0 Write zero to this bit has no effect. 1 Write one into this bit loads the load register into the modulus counter count register. Modulus Down-Counter Enable 0 Modulus down-counter is disabled. The modulus counter (MDCCNT) is preset to 0xFFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. 1 Modulus down-counter is enabled. Accumulator Overflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the accumulator overflow interrupt flag (AOVIF) is set.
0 AOVIE
12.3.2.3
Stepper Stall Detector Control Register (SSDCTL)
7 6 5 4 3 2 1 0
R RTZE W Reset 0 0 0 0 SDCPU SSDWAI FTST
0
0 ACLKS
0
0
0
0
= Unimplemented or Reserved
Figure 12-4. Stepper Stall Detector Control Register (SSDCTL)
Read: anytime Write: anytime
l
Table 12-8. SSDCTL Field Descriptions
Field 7 RTZE Description Return to Zero Enable — If this bit is set, the coils are controlled by the SSD and are configured into one of the four full step states as shown in Table 12-6. If this bit is cleared, the coils are not controlled by the SSD. 0 RTZ is disabled. 1 RTZ is enabled. Sigma-Delta Converter Power Up — This bit provides on/off control for the sigma-delta converter allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after it is powered up. 0 Sigma-delta converter is powered down. 1 Sigma-delta converter is powered up. SSD Disabled during Wait Mode — When entering Wait Mode, this bit provides on/off control over the SSD allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after exit from Wait Mode. 0 SSD continues to run in WAIT mode. 1 Entering WAIT mode freezes the clock to the prescaler divider, powers down the sigma-delta converter, and if RTZE bit is set, the sine and cosine coils are recirculated via VSSM.
6 SDCPU
5 SSDWAI
MC9S12XHZ512 Data Sheet, Rev. 1.03 482 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
Table 12-8. SSDCTL Field Descriptions (continued)
Field 4 FTST 1:0 ACLKS Description Factory Test — This bit is reserved for factory test and reads zero in user mode. Accumulator Sample Frequency Select — This field sets the accumulator sample frequency by pre-scaling the bus frequency by a factor of 8, 16, 32, or 64. A faster sample frequency can provide more accurate results but cause the accumulator to overflow. Best results are achieved with a frequency between 500 kHz and 2 MHz. Accumulator Sample Frequency = fBUS / (8 x 2ACLKS)
Table 12-9. Accumulator Sample Frequency
ACLKS 0 1 2 3 Frequency fBUS / 8 fBUS / 16 fBUS / 32 fBUS / 64 fBUS = 40 MHz 5.00 MHz 2.50 MHz 1.25 MHz 625 kHz fBUS = 25 MHz 3.12 MHz 1.56 MHz 781 kHz 391 kHz fBUS = 16 MHz 2.00 MHz 1.00 MHz 500 kHz 250 kHz
NOTE
A change in the accumulator sample frequency will not be effective until the ITG bit is cleared.
12.3.2.4
Stepper Stall Detector Flag Register (SSDFLG)
7 6 5 4 3 2 1 0
R MCZIF W Reset 0
0
0
0
0
0
0 AOVIF
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-5. Stepper Stall Detector Flag Register (SSDFLG)
Read: anytime Write: anytime.
l
Table 12-10. SSDFLG Field Descriptions
Field 7 MCZIF 0 AOVIF Description Modulus Counter Underflow Interrupt Flag — This flag is set when the modulus down-counter reaches 0x0000. If not masked (MCZIE = 1), a modulus counter underflow interrupt is pending while this flag is set. This flag is cleared by writing a ‘1’ to the bit. A write of ‘0’ has no effect. Accumulator Overflow Interrupt Flag — This flag is set when the Integration Accumulator has a positive or negative overflow. If not masked (AOVIE = 1), an accumulator overflow interrupt is pending while this flag is set. This flag is cleared by writing a ‘1’ to the bit. A write of ‘0’ has no effect.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 483
Chapter 12 Stepper Stall Detector (SSDV1)
12.3.2.5
Modulus Down-Counter Count Register (MDCCNT)
15 14 13 12 11 10 9 8
R MDCCNT W Reset 1 1 1 1 1 1 1 1
Figure 12-6. Modulus Down-Counter Count Register High (MDCCNT)
7 6 5 4 3 2 1 0
R MDCCNT W Reset 1 1 1 1 1 1 1 1
Figure 12-7. Modulus Down-Counter Count Register Low (MDCCNT)
Read: anytime Write: anytime.
NOTE
A separate read/write for high byte and low byte gives a different result than accessing the register as a word. If the RDMCL bit in the MDCCTL register is cleared, reads of the MDCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MDCCNT register will return the contents of the load register. With a 0x0000 write to the MDCCNT register, the modulus counter stays at zero and does not set the MCZIF flag in the SSDFLG register. If modulus mode is not enabled (MODMC = 0), a write to the MDCCNT register immediately updates the load register and the counter register with the value written to it. The modulus counter will count down from this value and will stop at 0x0000. If modulus mode is enabled (MODMC = 1), a write to the MDCCNT register updates the load register with the value written to it. The count register will not be updated with the new value until the next counter underflow. The FLMC bit in the MDCCTL register can be used to immediately update the count register with the new value if an immediate load is desired. The modulus down counter clock frequency is the bus frequency divided by 64 or 512.
MC9S12XHZ512 Data Sheet, Rev. 1.03 484 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
12.3.2.6
Integration Accumulator Register (ITGACC)
15 14 13 12 11 10 9 8
R W Reset 0 0 0 0
ITGACC
0
0
0
0
Figure 12-8. Integration Accumulator Register High (ITGACC)
7 6 5 4 3 2 1 0
R W Reset 0 0 0 0
ITGACC
0
0
0
0
Figure 12-9. Integration Accumulator Register Low (ITGACC)
Read: anytime. Write: Never.
NOTE
A separate read for high byte and low byte gives a different result than accessing the register as a word. This 16-bit field is signed and is represented in two’s complement. It indicates the change in flux while integrating the back EMF present in the non-driven coil during a return to zero event. When ITG is zero, the accumulator is initialized to 0x0000 and the sigma-delta converter is in a reset state. When ITG is one, the accumulator increments or decrements depending on the sigma-delta conversion sample. The accumulator sample frequency is determined by the ACLKS field. The accumulator freezes at 0x7FFF on a positive overflow and freezes at 0x8000 on a negative overflow.
12.4
Functional Description
The stepper stall detector (SSD) has a simple control block to configure the H-bridge drivers of a stepper motor in four different full step states with four available modes during a return to zero event. The SSD has a detect circuit using a sigma-delta converter to measure and integrate changes in flux of the de-energized winding in the stepping motor and the conversion result is accumulated in a 16-bit signed register. The SSD also has a 16-bit modulus down counter to monitor blanking and integration times. DC offset compensation is implemented when using the modulus down counter to monitor integration times.
12.4.1
Return to Zero Modes
Table 12-11. Return to Zero Modes
ITG DCOIL Mode
There are four return to zero modes as shown in Table 12-11.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 485
Chapter 12 Stepper Stall Detector (SSDV1)
Table 12-11. Return to Zero Modes
0 0 1 1 0 1 0 1 Blanking with no drive Blanking with drive Conversion Integration
12.4.1.1
Blanking with No Drive
In blanking mode with no drive, one of the coils is masked from the sigma-delta converter, and if RTZ is enabled (RTZE = 1), it is set up to recirculate its current. If RTZ is enabled (RTZE = 1), the other coil is disconnected to prevent any loss of flux change that would occur when the motor starts moving before the end of recirculation and start of integration. In blanking mode with no drive, the accumulator is initialized to 0x0000 and the converter is in a reset state.
12.4.1.2
Blanking with Drive
In blanking mode with drive, one of the coils is masked from the sigma-delta converter, and if RTZ is enabled (RTZE = 1), it is set up to recirculate its current. If RTZ is enabled (RTZE = 1), the other coil is driven. In blanking mode with drive, the accumulator is initialized to 0x0000 and the converter is in a reset state.
12.4.1.3
Conversion
In conversion mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. If RTZ is enabled (RTZE=1), both coils are disconnected. This mode is not useful for stall detection.
12.4.1.4
Integration
In integration mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. If RTZ is enabled (RTZE = 1), the other coil is driven. This mode is used to rectify and integrate the back EMF produced by the coils to detect stepped rotary motion. DC offset compensation is implemented when using the modulus down counter to monitor integration time.
12.4.2
Full Step States
During a return to zero (RTZ) event, the stepper motor pointer requires a 90° full motor electrical step with full amplitude pulses applied to each phase in turn. For counter clockwise rotation (CCW), the STEP value is incremented 0, 1, 2, 3, 0 and so on, and for a clockwise rotation the STEP value is decremented 3, 2, 1, 0 and so on. Figure 12-10 shows the current level through each coil for each full step in CCW rotation when DCOIL is set.
MC9S12XHZ512 Data Sheet, Rev. 1.03 486 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
+ Imax SINE COIL CURRENT 0 _ Imax
Recirculation + Imax COSINE COIL CURRENT 0 _ Imax 0 1 2 3
Figure 12-10. Full Steps (CCW)
Figure 12-11 shows the current flow in the SINx and COSx H-bridges when STEP = 0, DCOIL = 1, ITG = 0 and RCIR = 0.
VDDM VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 12-11. Current Flow when STEP = 0, DCOIL = 1, ITG = 0, RCIR = 0
Figure 12-12 shows the current flow in the SINx and COSx H-bridges when STEP = 1, DCOIL = 1, ITG = 0 and RCIR = 1.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 487
Chapter 12 Stepper Stall Detector (SSDV1)
VDDM
VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 12-12. Current Flow when STEP = 1, DCOIL = 1, ITG = 0, RCIR = 1
Figure 12-13 shows the current flow in the SINx and COSx H-bridges when STEP = 2, DCOIL = 1 and ITG = 1.
VDDM VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 12-13. Current flow when STEP = 2, DCOIL = 1, ITG = 1
Figure 12-14 shows the current flow in the SINx and COSx H-bridges when STEP = 3, DCOIL = 1 and ITG = 1.
MC9S12XHZ512 Data Sheet, Rev. 1.03 488 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
VDDM
VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 12-14. Current flow when STEP = 3, DCOIL = 1, ITG = 1
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 489
Chapter 12 Stepper Stall Detector (SSDV1)
12.4.3
Operation in Low Power Modes
The SSD block can be configured for lower MCU power consumption in three different ways. • Stop mode powers down the sigma-delta converter and halts clock to the modulus counter. Exit from Stop enables the sigma-delta converter and the clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. • Wait mode with SSDWAI bit set powers down the sigma-delta converter and halts the clock to the modulus counter. Exit from Wait enables the sigma-delta converter and clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. • Clearing SDCPU bit powers down the sigma-delta converter.
12.4.4
Stall Detection Flow
Figure 12-15 shows a flowchart and software setup for stall detection of a stepper motor. To control a second stepper motor, the SMS bit must be toggled during the SSD initialization.
MC9S12XHZ512 Data Sheet, Rev. 1.03 490 Freescale Semiconductor
Chapter 12 Stepper Stall Detector (SSDV1)
Advance Pointer
Using Motor Control module, drive pointer to within 3 full steps of calibrated zero position.
Initialize SSD
1. Clear (or set) RCIR; clear (or set) POL; clear (or set) SMS; 2. Set MCZIE; clear MODMC; clear (or set) PRE; set MCEN. 3. Set RTZE; set SDCPU; write ACLKS (select sample frequency). 4. Store threshold value in RAM.
Start Blanking
1. Clear MCZIF. 2. Write MDCCNT with blanking time value. 3. Clear ITG; clear (or set) DCOIL; increment (or decrement) STEP for CCW (or CW) motion.
End of Blanking? Yes Start Integration
MDCCNT = 0x0000? or MCZIF = 1? No
1. Clear MCZIF. 2. Write MDCCNT with integration time value. 3. Set ITG; set DCOIL.
End of Integration? Yes
MDCCNT = 0x0000? or MCZIF = 1? No
No
Stall Detection? Yes Disable SSD
ITGACC < Threshold (RAM value)?
1. Clear MCZIF. 2. Clear MCEN. 3. Clear ITG. 4. Clear RTZE; clear SDCPU.
Figure 12-15. Return-to-Zero Flowchart
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 491
Chapter 12 Stepper Stall Detector (SSDV1)
MC9S12XHZ512 Data Sheet, Rev. 1.03 492 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
13.1 Introduction
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for further expansion and system development. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
13.1.1
Features
The IIC module has the following key features: • Compatible with I2C bus standard • Multi-master operation • Software programmable for one of 256 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection • General Call Address detection • Compliant to ten-bit address
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 493
Chapter 13 Inter-Integrated Circuit (IICV3)
13.1.2
Modes of Operation
The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes.
13.1.3
Block Diagram
The block diagram of the IIC module is shown in Figure 13-1.
IIC Start Stop Arbitration Control
Registers
Interrupt Clock Control
bus_clock
In/Out Data Shift Register
SCL
SDA
Address Compare
Figure 13-1. IIC Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 494 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
13.2
External Signal Description
The IICV3 module has two external pins.
13.2.1
IIC_SCL — Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
13.2.2
IIC_SDA — Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
13.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the IIC module.
13.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Register Name IBAD R W IBFD R W IBCR R W IBSR R W IBDR R W IBCR2 R W D7 D6 D5 0 Bit 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2 0
IBC1 0
IBC0
IBEN TCF
IBIE IAAS
MS/SL IBB
Tx/Rx
TXAK 0
RSTA
SRW IBIF
IBSWAI RXAK
IBAL
D4 0
D3 0
D2
D1
D0
GCEN
ADTYPE
AD10
AD9
AD8
= Unimplemented or Reserved
Figure 13-2. IIC Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 495
Chapter 13 Inter-Integrated Circuit (IICV3)
13.3.1.1
IIC Address Register (IBAD)
7 6 5 4 3 2 1 0
R AD7 W Reset 0 0 0 0 0 0 0 AD6 AD5 AD4 AD3 AD2 AD1
0
0
= Unimplemented or Reserved
Figure 13-3. IIC Bus Address Register (IBAD)
Read and write anytime This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer.
Table 13-1. IBAD Field Descriptions
Field 7:1 AD[7:1] 0 Reserved Description Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
13.3.1.2
IIC Frequency Divider Register (IBFD)
7 6 5 4 3 2 1 0
R IBC7 W Reset 0 0 0 0 0 0 0 0 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
= Unimplemented or Reserved
Figure 13-4. IIC Bus Frequency Divider Register (IBFD)
Read and write anytime
Table 13-2. IBFD Field Descriptions
Field 7:0 IBC[7:0] Description I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown in Table 13-3.
MC9S12XHZ512 Data Sheet, Rev. 1.03 496 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-3. I-Bus Tap and Prescale Values
IBC2-0 (bin) 000 001 010 011 100 101 110 111 IBC5-3 (bin) 000 001 010 011 100 101 110 111 scl2start (clocks) 2 2 2 6 14 30 62 126 SCL Tap (clocks) 5 6 7 8 9 10 12 15 scl2stop (clocks) 7 7 9 9 17 33 65 129 SDA Tap (clocks) 1 1 2 2 3 3 4 4 scl2tap (clocks) 4 4 6 6 14 30 62 126 tap2tap (clocks) 1 2 4 8 16 32 64 128
Table 13-4. Multiplier Factor
IBC7-6 00 01 10 11 MUL 01 02 04 RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 13-3, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 13-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time. IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 13-4.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 497
Chapter 13 Inter-Integrated Circuit (IICV3)
SCL Divider
SCL
SDA
SDA Hold
SDA
SCL Hold(start)
SCL Hold(stop)
SCL
START condition
STOP condition
Figure 13-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 13-5. The equation used to generate the SDA Hold value from the IBFD bits is: SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3} The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
Table 13-5. IIC Divider and Hold Values (Sheet 1 of 6)
IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
MUL=1
MC9S12XHZ512 Data Sheet, Rev. 1.03 498 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-5. IIC Divider and Hold Values (Sheet 2 of 6)
IBC[7:0] (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C SCL Divider (clocks) 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 160 192 224 256 288 320 384 480 320 384 448 512 576 SDA Hold (clocks) 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 17 17 33 33 49 49 65 65 33 33 65 65 97 SCL Hold (start) 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 78 94 110 126 142 158 190 238 158 190 222 254 286 SCL Hold (stop) 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 81 97 113 129 145 161 193 241 161 193 225 257 289
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 499
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-5. IIC Divider and Hold Values (Sheet 3 of 6)
IBC[7:0] (hex) 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F SCL Divider (clocks) 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 40 44 48 52 56 60 68 80 56 64 72 80 88 96 112 136 96 112 128 144 160 176 208 256 160 SDA Hold (clocks) 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 14 14 16 16 18 18 20 20 14 14 18 18 22 22 26 26 18 18 26 26 34 34 42 42 18 SCL Hold (start) 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 12 14 16 18 20 22 26 32 20 24 28 32 36 40 48 60 36 44 52 60 68 76 92 116 76 SCL Hold (stop) 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921 22 24 26 28 30 32 36 42 30 34 38 42 46 50 58 70 50 58 66 74 82 90 106 130 82
MUL=2
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58
MC9S12XHZ512 Data Sheet, Rev. 1.03 500 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-5. IIC Divider and Hold Values (Sheet 4 of 6)
IBC[7:0] (hex) 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F SCL Divider (clocks) 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 4608 5120 6144 7680 80 88 96 104 112 SDA Hold (clocks) 18 34 34 50 50 66 66 34 34 66 66 98 98 130 130 66 66 130 130 194 194 258 258 130 130 258 258 386 386 514 514 258 258 514 514 770 770 1026 1026 28 28 32 32 36 SCL Hold (start) 92 108 124 140 156 188 236 156 188 220 252 284 316 380 476 316 380 444 508 572 636 764 956 636 764 892 1020 1148 1276 1532 1916 1276 1532 1788 2044 2300 2556 3068 3836 24 28 32 36 40 SCL Hold (stop) 98 114 130 146 162 194 242 162 194 226 258 290 322 386 482 322 386 450 514 578 642 770 962 642 770 898 1026 1154 1282 1538 1922 1282 1538 1794 2050 2306 2562 3074 3842 44 48 52 56 60
MUL=4
80 81 82 83 84
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 501
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-5. IIC Divider and Hold Values (Sheet 5 of 6)
IBC[7:0] (hex) 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 SCL Divider (clocks) 120 136 160 112 128 144 160 176 192 224 272 192 224 256 288 320 352 416 512 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 SDA Hold (clocks) 36 40 40 28 28 36 36 44 44 52 52 36 36 52 52 68 68 84 84 36 36 68 68 100 100 132 132 68 68 132 132 196 196 260 260 132 132 260 260 388 388 516 516 260 260 SCL Hold (start) 44 52 64 40 48 56 64 72 80 96 120 72 88 104 120 136 152 184 232 152 184 216 248 280 312 376 472 312 376 440 504 568 632 760 952 632 760 888 1016 1144 1272 1528 1912 1272 1528 SCL Hold (stop) 64 72 84 60 68 76 84 92 100 116 140 100 116 132 148 164 180 212 260 164 196 228 260 292 324 388 484 324 388 452 516 580 644 772 964 644 772 900 1028 1156 1284 1540 1924 1284 1540
MC9S12XHZ512 Data Sheet, Rev. 1.03 502 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-5. IIC Divider and Hold Values (Sheet 6 of 6)
IBC[7:0] (hex) B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF SCL Divider (clocks) 3584 4096 4608 5120 6144 7680 5120 6144 7168 8192 9216 10240 12288 15360 SDA Hold (clocks) 516 516 772 772 1028 1028 516 516 1028 1028 1540 1540 2052 2052 SCL Hold (start) 1784 2040 2296 2552 3064 3832 2552 3064 3576 4088 4600 5112 6136 7672 SCL Hold (stop) 1796 2052 2308 2564 3076 3844 2564 3076 3588 4100 4612 5124 6148 7684
13.3.1.3
IIC Control Register (IBCR)
7 6 5 4 3 2 1 0
R IBEN W Reset 0 0 0 0 0 IBIE MS/SL Tx/Rx TXAK
0
0 IBSWAI
RSTA
0 0 0
= Unimplemented or Reserved
Figure 13-6. IIC Bus Control Register (IBCR)
Read and write anytime
Table 13-6. IBCR Field Descriptions
Field 7 IBEN Description I-Bus Enable — This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing arbitration, after which bus operation would return to normal. I-Bus Interrupt Enable 0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt condition 1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status register is also set.
6 IBIE
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 503
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-6. IBCR Field Descriptions (continued)
Field 5 MS/SL Description Master/Slave Mode Select Bit — Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave.A STOP signal should only be generated if the IBIF flag is set. MS/SL is cleared without generating a STOP signal when the master loses arbitration. 0 Slave Mode 1 Master Mode Transmit/Receive Mode Select Bit — This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. 0 Receive 1 Transmit Transmit Acknowledge Enable — This bit specifies the value driven onto SDA during data acknowledge cycles for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a receiver, not a transmitter. 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 Generate repeat start cycle
4 Tx/Rx
3 TXAK
2 RSTA
1 Reserved — Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0. RESERVED 0 IBSWAI I Bus Interface Stop in Wait Mode 0 IIC bus module clock operates normally 1 Halt IIC bus module clock generation in wait mode
Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway. It is also possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.
MC9S12XHZ512 Data Sheet, Rev. 1.03 504 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
13.3.1.4
IIC Status Register (IBSR)
7 6 5 4 3 2 1 0
R W Reset
TCF
IAAS
IBB IBAL
0
SRW IBIF
RXAK
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-7. IIC Bus Status Register (IBSR)
This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software clearable.
Table 13-7. IBSR Field Descriptions
Field 7 TCF Description Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module. 0 Transfer in progress 1 Transfer complete Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling address or it receives the general call address with GCEN== 1,this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit. 0 Not addressed 1 Addressed as a slave Bus Busy Bit 0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: 1. SDA sampled low when the master drives a high during an address or data transmit cycle. 2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3. A start cycle is attempted when the bus is busy. 4. A repeated start cycle is requested in slave mode. 5. A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.
6 IAAS
5 IBB
4 IBAL
3 Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. RESERVED 2 SRW Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 505
Chapter 13 Inter-Integrated Circuit (IICV3)
Table 13-7. IBSR Field Descriptions (continued)
Field 1 IBIF Description I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs: — Arbitration lost (IBAL bit set) — Byte transfer complete (TCF bit set) — Addressed as slave (IAAS bit set) It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one to it. A write of 0 has no effect on this bit. Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock. 0 Acknowledge received 1 No acknowledge received
0 RXAK
13.3.1.5
IIC Data I/O Register (IBDR)
7 6 5 4 3 2 1 0
R D7 W Reset 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
Figure 13-8. IIC Bus Data I/O Register (IBDR)
In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. Reading the IBDR will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0).
MC9S12XHZ512 Data Sheet, Rev. 1.03 506 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
13.3.1.6
IIC Control Register 2(IBCR2)
7
6
5
4
3
2
1
0
R GCEN W Reset 0 0 ADTYPE
0
0
0 AD10 AD9 0 AD8 0
0
0
0
0
Figure 13-9. IIC Bus Control Register 2(IBCR2)
This register contains the variables used in general call and in ten-bit address. Read and write anytime
Table 13-8. IBCR2 Field Descriptions
Field 7 GCEN Description General Call Enable. 0 General call is disabled. The module dont receive any general call data and address. 1 enable general call. It indicates that the module can receive address and any data. Address Type— This bit selects the address length. The variable must be configured correctly before IIC enters slave mode. 0 7-bit address 1 10-bit address
6 ADTYPE
5,4,3 Reserved — Bit 5,4 and 3 of the IBCR2 are reserved for future compatibility. These bits will always read 0. RESERVED 2:0 AD[10:8] Slave Address [10:8] —These 3 bits represent the MSB of the 10-bit address when address type is asserted (ADTYPE = 1).
13.4
Functional Description
This section provides a complete functional description of the IICV3.
13.4.1
I-Bus Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 13-10.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 507
Chapter 13 Inter-Integrated Circuit (IICV3)
MSB SCL 1 2 3 4 5 6 7
LSB 8 9
MSB 1 2 3 4 5 6 7
LSB 8 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Start Signal
Calling Address
Read/ Write
Ack Bit
Data Byte
No Stop Ack Signal Bit LSB
MSB SCL 1 2 3 4 5 6 7
LSB 8 9
MSB 1 2 3 4 5 6 7
8
9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start Signal
Calling Address
Read/ Write
Ack Bit
Repeated Start Signal
New Calling Address
Read/ Write
No Stop Ack Signal Bit
Figure 13-10. IIC-Bus Transmission Signals
13.4.1.1
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal.As shown in Figure 13-10, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states.
SDA
SCL
START Condition
STOP Condition
Figure 13-11. Start and Stop Conditions
MC9S12XHZ512 Data Sheet, Rev. 1.03 508 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
13.4.1.2
Slave Address Transmission
The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. If the calling address is 10-bit, another byte is followed by the first byte.Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 13-10). No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an address that is equal to its own slave address. The IIC bus cannot be master and slave at the same time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate correctly even if it is being addressed by another master.
13.4.1.3
Data Transfer
As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 13-10. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal.
13.4.1.4
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 13-10). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus.
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Chapter 13 Inter-Integrated Circuit (IICV3)
13.4.1.5
Repeated START Signal
As shown in Figure 13-10, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
13.4.1.6
Arbitration Procedure
The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
13.4.1.7
Clock Synchronization
Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus. The devices start counting their low period and as soon as a device's clock has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 13-11). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods.The first device to complete its high period pulls the SCL line low again.
WAIT SCL1 Start Counting High Period
SCL2
SCL
Internal Counter Reset
Figure 13-12. IIC-Bus Clock Synchronization
MC9S12XHZ512 Data Sheet, Rev. 1.03 510 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
13.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line.
13.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it.If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched.
13.4.1.10 Ten-bit Address
A ten-bit address is indicated if the first 5 bits of the first address byte are 0x11110. The following rules apply to the first address byte.
SLAVE ADDRESS 0000000 0000010 0000011 11111XX 11110XX R/W BIT 0 x x x x DESCRIPTION General call address Reserved for different bus format Reserved for future purposes Reserved for future purposes 10-bit slave addressing
Figure 13-13. Definition
of bits in the first byte.
The address type is identified by ADTYPE. When ADTYPE is 0, 7-bit address is applied. Reversely, the address is 10-bit address.Generally, there are two cases of 10-bit address.See the Fig.1-14 and 1-15.
Slave Add1st 7bits 11110+AD10+AD9 R/W 0 Slave Add 2nd byte A2 AD[8:1]
S
A1
Data
A3
Figure 13-14. A master-transmitter addresses a slave-receiver with a 10-bit address S Slave Add1st 7bits 11110+AD10+AD9 R/W 0 A1 Slave Add 2nd byte A2 AD[8:1] Sr Slave Add 1st 7bits R/W A3 Data 11110+AD10+AD9 1 A4
Figure 13-15. A master-receiver addresses a slave-transmitter with a 10-bit address.
In the figure 1-15,the first two bytes are the similar to figure1-14.After the repeated START(Sr),the first slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 511
Chapter 13 Inter-Integrated Circuit (IICV3)
13.4.1.11 General Call Address
If some device want to generate a broadcast, it must first generate general call address($00), then after receiving acknowledge, it should generate data. In the communication, as slave device, provided its GCEN is asserted, it would acknowledge the broadcast and receive data until the GCEN is disabled or the master device release the bus or generate a new transfer.In the broadcast, slaves always act as receivers. Note in general call, IAAS is also used to indicate the address match.In order to distinguish whether the address match is the normal address match or the general call address match, IBDR should be read after it’s addressed. If the data is “00”,we can conclude the match is general call address match. The meaning of the general call address is always specified in the first data byte. But IIC don’t interpret it. It must be dealt with by S/W. When one byte transfer is done, user can get the data by reading IBDR. Generally, user can control the procedure by enabling or disabling GCEN.
13.4.2
Operation in Run Mode
This is the basic mode of operation.
13.4.3
Operation in Wait Mode
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry.
13.4.4
Operation in Stop Mode
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC register states.
13.5
Resets
The reset state of each individual bit is listed in Section 13.3, “Memory Map and Register Definition,” which details the registers and their bit-fields.
13.6
Interrupts
Table 13-9. Interrupt Summary
Interrupt IIC Interrupt Offset — Vector — Priority — Source Description
IICV3 uses only one interrupt vector.
IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set bits in IBSR may cause an interrupt based on arbitration register lost, transfer complete or address detect conditions
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt type by reading the status register.
MC9S12XHZ512 Data Sheet, Rev. 1.03 512 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine.
13.7
13.7.1
Application Information
IIC Programming Examples
Initialization Sequence
13.7.1.1
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2. Update the ADTYPE of IBCR2 to define the address length, 7 bits or 10 bits. 3. Update the IIC bus address register (IBAD) to define its slave address. If 10-bit address is applied IBCR2 should be updated to define the rest bits of address. 4. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system. 5. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive mode and interrupt enable or not. 6. If supported general call, the GCEN in IBCR2 should be asserted.
13.7.1.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data written to the data register comprises the slave calling address and the LSB set to indicate the direction of transfer required from the slave. The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below:
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 513
Chapter 13 Inter-Integrated Circuit (IICV3)
CHFLAG TXSTART IBFREE
BRSET BSET MOVB BRCLR
IBSR,#$20,* IBCR,#$30 CALLING,IBDR IBSR,#$20,*
;WAIT FOR IBB FLAG TO CLEAR ;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION ;TRANSMIT THE CALLING ADDRESS, D0=R/W ;WAIT FOR IBB FLAG TO SET
13.7.1.3
Post-Transfer Software Response
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register (IBDR) in receive mode or writing to IBDR in transmit mode. Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation is different when arbitration is lost. Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage. During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly.For slave mode data cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine the direction of the current transfer. The following is an example of a software response by a 'master transmitter' in the interrupt routine.
ISR BCLR BRCLR BRCLR BRSET MOVB IBSR,#$02 IBCR,#$20,SLAVE IBCR,#$10,RECEIVE IBSR,#$01,END DATABUF,IBDR ;CLEAR THE IBIF FLAG ;BRANCH IF IN SLAVE MODE ;BRANCH IF IN RECEIVE MODE ;IF NO ACK, END OF TRANSMISSION ;TRANSMIT NEXT BYTE OF DATA
TRANSMIT
13.7.1.4
Generation of STOP
A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter.
MASTX TST BEQ BRSET MOVB DEC BRA BCLR RTI TXCNT END IBSR,#$01,END DATABUF,IBDR TXCNT EMASTX IBCR,#$20 ;GET VALUE FROM THE TRANSMITING COUNTER ;END IF NO MORE DATA ;END IF NO ACK ;TRANSMIT NEXT BYTE OF DATA ;DECREASE THE TXCNT ;EXIT ;GENERATE A STOP CONDITION ;RETURN FROM INTERRUPT
END EMASTX
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK)
MC9S12XHZ512 Data Sheet, Rev. 1.03 514 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver.
MASR DEC BEQ MOVB DEC BNE BSET BRA BCLR MOVB RTI RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 NXMAR IBCR,#$20 IBDR,RXBUF ;DECREASE THE RXCNT ;LAST BYTE TO BE READ ;CHECK SECOND LAST BYTE ;TO BE READ ;NOT LAST OR SECOND LAST ;SECOND LAST, DISABLE ACK ;TRANSMITTING ;LAST ONE, GENERATE ‘STOP’ SIGNAL ;READ DATA AND STORE
LAMAR
ENMASR NXMAR
13.7.1.5
Generation of Repeated START
At the end of data transfer, if the master continues to want to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown.
RESTART BSET MOVB IBCR,#$04 CALLING,IBDR ;ANOTHER START (RESTART) ;TRANSMIT THE CALLING ADDRESS;D0=R/W
13.7.1.6
Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in the required mode. In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal.
13.7.1.7
Arbitration Lost
If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the
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Chapter 13 Inter-Integrated Circuit (IICV3)
attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set.
MC9S12XHZ512 Data Sheet, Rev. 1.03 516 Freescale Semiconductor
Chapter 13 Inter-Integrated Circuit (IICV3)
Clear IBIF
Y
Master Mode ?
N
TX
Tx/Rx ?
RX
Y
Arbitration Lost ? N
Last Byte Transmitted ? N
Y
Clear IBAL
RXAK=0 ? Y End Of Addr Cycle (Master Rx) ? N
N
Last Byte To Be Read ? N
Y
N
IAAS=1 ? Y
Y
IAAS=1 ? N
Address Transfer Y Y 2nd Last Byte To Be Read ? N Y (Read) SRW=1 ? N (Write) Y
Data Transfer TX/RX ? TX ACK From Receiver ? N Read Data From IBDR And Store RX
Write Next Byte To IBDR
Set TXAK =1
Generate Stop Signal
Set TX Mode
Write Data To IBDR
Tx Next Byte
Switch To Rx Mode
Set RX Mode
Switch To Rx Mode
Dummy Read From IBDR
Generate Stop Signal
Read Data From IBDR And Store
Dummy Read From IBDR
Dummy Read From IBDR
RTI
Figure 13-16. Flow-Chart of Typical IIC Interrupt Routine
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Chapter 13 Inter-Integrated Circuit (IICV3)
MC9S12XHZ512 Data Sheet, Rev. 1.03 518 Freescale Semiconductor
Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
14.1 Introduction
Freescale’s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software.
14.1.1
Glossary
ACK: Acknowledge of CAN message CAN: Controller Area Network CRC: Cyclic Redundancy Code EOF: End of Frame FIFO: First-In-First-Out Memory IFS: Inter-Frame Sequence SOF: Start of Frame CPU bus: CPU related read/write data bus CAN bus: CAN protocol related serial bus oscillator clock: Direct clock from external oscillator bus clock: CPU bus realated clock CAN clock: CAN protocol related clock
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 519
Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
14.1.2
Block Diagram MSCAN
Oscillator Clock Bus Clock
CANCLK
MUX
Presc.
Tq Clk
Receive/ Transmit Engine
RXCAN TXCAN
Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Wake-Up Interrupt Req.
Control and Status
Message Filtering and Buffering
Configuration Registers
Wake-Up
Low Pass Filter
Figure 14-1. MSCAN Block Diagram
14.1.3
Features
The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mbps1 — Support for remote frames • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization using a “local priority” concept • Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters • Programmable wakeup functionality with integrated low-pass filter • Programmable loopback mode supports self-test operation • Programmable listen-only mode for monitoring of CAN bus • Programmable bus-off recovery functionality • Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) • Programmable MSCAN clock source either bus clock or oscillator clock • Internal timer for time-stamping of received and transmitted messages
1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12XHZ512 Data Sheet, Rev. 1.03 520 Freescale Semiconductor
Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
• •
Three low-power modes: sleep, power down, and MSCAN enable Global initialization of configuration registers
14.1.4
Modes of Operation
The following modes of operation are specific to the MSCAN. See Section 14.4, “Functional Description,” for details. • Listen-Only Mode • MSCAN Sleep Mode • MSCAN Initialization Mode • MSCAN Power Down Mode
14.2
External Signal Description
The MSCAN uses two external pins:
14.2.1
RXCAN — CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
14.2.2
TXCAN — CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state
14.2.3
CAN System
A typical CAN system with MSCAN is shown in Figure 14-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations.
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CAN node 1 MCU CAN Controller (MSCAN)
CAN node 2
CAN node n
TXCAN
RXCAN
Transceiver CAN_H CAN_L CAN Bus
Figure 14-2. CAN System
14.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
14.3.1
Module Memory Map
Figure 14-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The detailed register descriptions follow in the order they appear in the register map.
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Register Name 0x0000 CANCTL0 0x0001 CANCTL1 0x0002 CANBTR0 0x0003 CANBTR1 0x0004 CANRFLG 0x0005 CANRIER 0x0006 CANTFLG 0x0007 CANTIER 0x0008 CANTARQ 0x0009 CANTAAK 0x000A CANTBSEL 0x000B CANIDAC 0x000C Reserved 0x000D CANMISC 0x000E CANRXERR R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
6 RXACT
5
4 SYNCH
3
2
1
Bit 0
RXFRM
CSWAI
TIME
WUPE
SLPRQ SLPAK
INITRQ INITAK
CANE
CLKSRC
LOOPB
LISTEN
BORM
WUPM
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
SAMP
TSEG22
TSEG21 RSTAT1
TSEG20 RSTAT0
TSEG13 TSTAT1
TSEG12 TSTAT0
TSEG11
TSEG10
WUPIF
CSCIF
OVRIF
RXF
WUPIE 0
CSCIE 0
RSTATE1 0
RSTATE0 0
TSTATE1 0
TSTATE0
OVRIE
RXFIE
TXE2
TXE1
TXE0
0
0
0
0
0
TXEIE2
TXEIE1
TXEIE0
0
0
0
0
0
ABTRQ2 ABTAK2
ABTRQ1 ABTAK1
ABTRQ0 ABTAK0
0
0
0
0
0
0
0
0
0
0
TX2 IDHIT2
TX1 IDHIT1
TX0 IDHIT0
0
0
IDAM1 0
IDAM0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BOHOLD RXERR0
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
= Unimplemented or Reserved
u = Unaffected
Figure 14-3. MSCAN Register Summary
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Register Name 0x000F CANTXERR 0x0010–0x0013 CANIDAR0–3 0x0014–0x0017 CANIDMRx 0x0018–0x001B CANIDAR4–7 0x001C–0x001F CANIDMR4–7 0x0020–0x002F CANRXFG 0x0030–0x003F CANTXFG R W R W R W R W R W R W R W
Bit 7 TXERR7
6 TXERR6
5 TXERR5
4 TXERR4
3 TXERR3
2 TXERR2
1 TXERR1
Bit 0 TXERR0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
See Section 14.3.3, “Programmer’s Model of Message Storage”
See Section 14.3.3, “Programmer’s Model of Message Storage” = Unimplemented or Reserved u = Unaffected
Figure 14-3. MSCAN Register Summary (continued)
14.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read.
14.3.2.1
MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Module Base + 0x0000
7 6 5 4 3 2 1 0
R RXFRM W Reset: 0
RXACT CSWAI 0 = Unimplemented 0
SYNCH TIME 0 0 WUPE 0 SLPRQ 0 INITRQ 1
Figure 14-4. MSCAN Control Register 0 (CANCTL0)
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Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode).
Table 14-1. CANCTL0 Register Field Descriptions
Field 7 RXFRM1 Description Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this flag 1 A valid message was received since last clearing of this flag Receiver Active Status — This read-only flag indicates the MSCAN is receiving a message. The flag is controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle2 1 MSCAN is receiving a message (including when arbitration is lost)2 CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode Synchronized Status — This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 14.3.3, “Programmer’s Model of Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode when traffic on CAN is detected (see Section 14.4.5.4, “MSCAN Sleep Mode”). This bit must be configured before sleep mode entry for the selected function to take effect. 0 Wake-up disabled — The MSCAN ignores traffic on CAN 1 Wake-up enabled — The MSCAN is able to restart
6 RXACT
5 CSWAI3
4 SYNCH
3 TIME
2 WUPE4
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Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
Table 14-1. CANCTL0 Register Field Descriptions (continued)
Field 1 SLPRQ5 Description Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 14.4.5.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ cannot be set while the WUPIF flag is set (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running — The MSCAN functions normally 1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see Section 14.4.5.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9, CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0. 0 Normal operation 1 MSCAN in initialization mode
0 INITRQ6,7
1 2
The MSCAN must be in normal mode for this bit to become set. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states. 3 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the CPU enters wait (CSWAI = 1) or stop mode (see Section 14.4.5.2, “Operation in Wait Mode” and Section 14.4.5.3, “Operation in Stop Mode”). 4 The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 5 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 6 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 7 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 8 Not including WUPE, INITRQ, and SLPRQ. 9 TSTAT1 and TSTAT0 are not affected by initialization mode. 10 RSTAT1 and RSTAT0 are not affected by initialization mode.
14.3.2.2
MSCAN Control Register 1 (CANCTL1)
The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below.
MC9S12XHZ512 Data Sheet, Rev. 1.03 526 Freescale Semiconductor
Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
Module Base 0x0001 +
7 6 5 4 3 2 1 0
R CANE W Reset: 0 0 = Unimplemented 0 1 0 0 CLKSRC LOOPB LISTEN BORM WUPM
SLPAK
INITAK
0
1
Figure 14-5. MSCAN Control Register 1 (CANCTL1)
Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1).
Table 14-2. CANCTL1 Register Field Descriptions
Field 7 CANE 6 CLKSRC MSCAN Enable 0 MSCAN module is disabled 1 MSCAN module is enabled MSCAN Clock Source — This bit defines the clock source for the MSCAN module (only for systems with a clock generation module; Section 14.4.3.2, “Clock System,” and Section Figure 14-43., “MSCAN Clocking Scheme,”). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. 0 Loopback self test disabled 1 Loopback self test enabled Listen Only Mode — This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section 14.4.4.4, “Listen-Only Mode”). In addition, the error counters are frozen. Listen only mode supports applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated Bus-Off Recovery Mode — This bits configures the bus-off state recovery mode of the MSCAN. Refer to Section 14.5.2, “Bus-Off Recovery,” for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification) 1 Bus-off recovery upon user request Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 14.4.5.4, “MSCAN Sleep Mode”). 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup Description
5 LOOPB
4 LISTEN
3 BORM
2 WUPM
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Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
Table 14-2. CANCTL1 Register Field Descriptions (continued)
Field 1 SLPAK Description Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 14.4.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the flag if it detects activity on the CAN bus while in sleep mode. 0 Running — The MSCAN operates normally 1 Sleep mode active — The MSCAN has entered sleep mode Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode (see Section 14.4.5.5, “MSCAN Initialization Mode”). It is used as a handshake flag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running — The MSCAN operates normally 1 Initialization mode active — The MSCAN has entered initialization mode
0 INITAK
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14.3.2.3
MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Module Base + 0x0002
7 6 5 4 3 2 1 0
R SJW1 W Reset: 0 0 0 0 0 0 0 0 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Figure 14-6. MSCAN Bus Timing Register 0 (CANBTR0)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 14-3. CANBTR0 Register Field Descriptions
Field 7:6 SJW[1:0] 5:0 BRP[5:0] Description Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 14-4). Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 14-5).
Table 14-4. Synchronization Jump Width
SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles
Table 14-5. Baud Rate Prescaler
BRP5 0 0 0 0 : 1 BRP4 0 0 0 0 : 1 BRP3 0 0 0 0 : 1 BRP2 0 0 0 0 : 1 BRP1 0 0 1 1 : 1 BRP0 0 1 0 1 : 1 Prescaler value (P) 1 2 3 4 : 64
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14.3.2.4
MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Module Base + 0x0003
7 6 5 4 3 2 1 0
R SAMP W Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Figure 14-7. MSCAN Bus Timing Register 1 (CANBTR1)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 14-6. CANBTR1 Register Field Descriptions
Field 7 SAMP Description Sampling — This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit. 1 Three samples per bit1. If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
6:4 Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG2[2:0] of the sample point (see Figure 14-44). Time segment 2 (TSEG2) values are programmable as shown in Table 14-7. 3:0 Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 14-44). Time segment 1 (TSEG1) values are programmable as shown in Table 14-8.
1
In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
Table 14-7. Time Segment 2 Values
TSEG22 0 0 : 1 1
1
TSEG21 0 0 : 1 1
TSEG20 0 1 : 0 1
Time Segment 2 1 Tq clock cycle1 2 Tq clock cycles : 7 Tq clock cycles 8 Tq clock cycles
This setting is not valid. Please refer to Table 14-35 for valid settings.
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Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
Table 14-8. Time Segment 1 Values
TSEG13 0 0 0 0 : 1 1
1
TSEG12 0 0 0 0 : 1 1
TSEG11 0 0 1 1 : 1 1
TSEG10 0 1 0 1 : 0 1
Time segment 1 1 Tq clock cycle1 2 Tq clock cycles1 3 Tq clock cycles1 4 Tq clock cycles : 15 Tq clock cycles 16 Tq clock cycles
This setting is not valid. Please refer to Table 14-35 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 14-7 and Table 14-8).
Eqn. 14-1
( Prescaler value ) Bit Time = ----------------------------------------------------- • ( 1 + TimeSegment1 + TimeSegment2 ) f CANCLK
14.3.2.5
MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register.
Module Base + 0x0004
7 6 5 4 3 2 1 0
R WUPIF W Reset: 0 0 CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0 OVRIF RXF 0
0
0
0
0
0
= Unimplemented
Figure 14-8. MSCAN Receiver Flag Register (CANRFLG)
NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored.
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 531
Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
Table 14-9. CANRFLG Register Field Descriptions
Field 7 WUPIF Description Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 14.4.5.4, “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status
6 CSCIF
5:4 Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As RSTAT[1:0] soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is: 00 RxOK: 0 ≤ receive error counter ≤ 96 01 RxWRN: 96 < receive error counter ≤ 127 10 RxERR: 127 < receive error counter 11 Bus-off1: transmit error counter > 255 3:2 Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. TSTAT[1:0] As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK: 0 ≤ transmit error counter ≤ 96 01 TxWRN: 96 < transmit error counter ≤ 127 10 TxERR: 127 < transmit error counter ≤ 255 11 Bus-Off: transmit error counter > 255 1 OVRIF Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this flag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG
0 RXF2
1
Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2 To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
MC9S12XHZ512 Data Sheet, Rev. 1.03 532 Freescale Semiconductor
Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
14.3.2.6
MSCAN Receiver Interrupt Enable Register (CANRIER)
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
Module Base + 0x0005
7 6 5 4 3 2 1 0
R WUPIE W Reset: 0 0 0 0 0 0 0 0 CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Figure 14-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode
Table 14-10. CANRIER Register Field Descriptions
Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
5:4 Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state RSTATE[1:0] changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”2 state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 3:2 Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes.
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Table 14-10. CANRIER Register Field Descriptions (continued)
Field 1 OVRIE 0 RXFIE
1
Description Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
WUPIE and WUPE (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery mechanism from stop or wait is required. 2 Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).
14.3.2.7
MSCAN Transmitter Flag Register (CANTFLG)
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
Module Base + 0x0006
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TXE2 TXE1 1 TXE0 1
0
0
0
0
0
1
= Unimplemented
Figure 14-10. MSCAN Transmitter Flag Register (CANTFLG)
NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored
MC9S12XHZ512 Data Sheet, Rev. 1.03 534 Freescale Semiconductor
Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
Table 14-11. CANTFLG Register Field Descriptions
Field 2:0 TXE[2:0] Description Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 14.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). When listen-mode is active (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx flags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled)
14.3.2.8
MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Module Base + 0x0007
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TXEIE2 TXEIE1 0 TXEIE0 0
0
0
0
0
0
0
= Unimplemented
Figure 14-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 14-12. CANTIER Register Field Descriptions
Field 2:0 TXEIE[2:0] Description Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request.
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14.3.2.9
MSCAN Transmitter Message Abort Request Register (CANTARQ)
The CANTARQ register allows abort request of queued messages as described below.
Module Base + 0x0008
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 ABTRQ2 ABTRQ1 0 ABTRQ0 0
0
0
0
0
0
0
= Unimplemented
Figure 14-12. MSCAN Transmitter Message Abort Request Register (CANTARQ)
NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 14-13. CANTARQ Register Field Descriptions
Field Description
2:0 Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge flags (ABTAK, see Section 14.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE flag is set. 0 No abort request 1 Abort request pending
MC9S12XHZ512 Data Sheet, Rev. 1.03 536 Freescale Semiconductor
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14.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register.
Module Base + 0x0009
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0
ABTAK2
ABTAK1
ABTAK0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). Read: Anytime Write: Unimplemented for ABTAKx flags
Table 14-14. CANTAAK Register Field Descriptions
Field Description
2:0 Abort Acknowledge — This flag acknowledges that a message was aborted due to a pending abort request ABTAK[2:0] from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted.
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14.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)
The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space.
Module Base + 0x000A
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TX2 TX1 0 TX0 0
0
0
0
0
0
0
= Unimplemented
Figure 14-14. MSCAN Transmit Buffer Selection Register (CANTBSEL)
NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode
Table 14-15. CANTBSEL Register Field Descriptions
Field 2:0 TX[2:0] Description Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit
The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. • LDD CANTFLG; value read is 0b0000_0110 • STD CANTBSEL; value written is 0b0000_0110 • LDD CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.
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14.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC)
The CANIDAC register is used for identifier acceptance control as described below.
Module Base + 0x000B
7 6 5 4 3 2 1 0
R W Reset:
0
0 IDAM1 IDAM0 0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-15. MSCAN Identifier Acceptance Control Register (CANIDAC)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only
Table 14-16. CANIDAC Register Field Descriptions
Field 5:4 IDAM[1:0] 2:0 IDHIT[2:0] Description Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 14.4.3, “Identifier Acceptance Filter”). Table 14-17 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded. Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see Section 14.4.3, “Identifier Acceptance Filter”). Table 14-18 summarizes the different settings.
Table 14-17. Identifier Acceptance Mode Settings
IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Two 32-bit acceptance filters Four 16-bit acceptance filters Eight 8-bit acceptance filters Filter closed
Table 14-18. Identifier Acceptance Hit Indication
IDHIT2 0 0 0 0 1 1 1 1 IDHIT1 0 0 1 1 0 0 1 1 IDHIT0 0 1 0 1 0 1 0 1 Identifier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit
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The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
14.3.2.13 MSCAN Reserved Register
This register is reserved for factory testing of the MSCAN module and is not available in normal system operation modes.
Module Base + 0x000C
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-16. MSCAN Reserved Register
Read: Always read 0x0000 in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality.
14.3.2.14 MSCAN Miscellaneous Register (CANMISC)
This register provides additional features.
Module Base + 0x000D
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0
0
0 BOHOLD
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-17. MSCAN Miscellaneous Register (CANMISC)
Read: Anytime Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored
MC9S12XHZ512 Data Sheet, Rev. 1.03 540 Freescale Semiconductor
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Table 14-19. CANMISC Register Field Descriptions
Field 0 BOHOLD Description Bus-off State Hold Until User Request — If BORM is set in Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer to Section 14.5.2, “Bus-Off Recovery,” for details. 0 Module is not bus-off or recovery has been requested by user in bus-off state 1 Module is bus-off and holds this state until user request
14.3.2.15 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
Module Base + 0x000E
7 6 5 4 3 2 1 0
R W Reset:
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-18. MSCAN Receive Error Counter (CANRXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
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Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
14.3.2.16 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Module Base + 0x000F
7 6 5 4 3 2 1 0
R W Reset:
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-19. MSCAN Transmit Error Counter (CANTXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
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14.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 14.3.3.1, “Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 14.4.3, “Identifier Acceptance Filter”). For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 (CANIDAR0) 0x0011 (CANIDAR1) 0x0012 (CANIDAR2) 0x0013 (CANIDAR3)
7 6 5 4 3 2 1 0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 14-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 14-20. CANIDAR0–CANIDAR3 Register Field Descriptions
Field 7:0 AC[7:0] Description Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
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Module Base + 0x0018 (CANIDAR4) 0x0019 (CANIDAR5) 0x001A (CANIDAR6) 0x001B (CANIDAR7)
7 6 5 4 3 2 1 0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 14-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 14-21. CANIDAR4–CANIDAR7 Register Field Descriptions
Field 7:0 AC[7:0] Description Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
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Chapter 14 Freescale’s Scalable Controller Area Network (MSCANV3)
14.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.” To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Module Base + 0x0014 (CANIDMR0) 0x0015 (CANIDMR1) 0x0016 (CANIDMR2) 0x0017 (CANIDMR3)
7 6 5 4 3 2 1 0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 14-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 14-22. CANIDMR0–CANIDMR3 Register Field Descriptions
Field 7:0 AM[7:0] Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit
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Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7)
7 6 5 4 3 2 1 0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 14-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 14-23. CANIDMR4–CANIDMR7 Register Field Descriptions
Field 7:0 AM[7:0] Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit
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14.3.3
Programmer’s Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers.
Table 14-24. Message Buffer Organization
Offset Address 0x00X0 0x00X1 0x00X2 0x00X3 0x00X4 0x00X5 0x00X6 0x00X7 0x00X8 0x00X9 0x00XA 0x00XB 0x00XC 0x00XD 0x00XE 0x00XF
1 2
Register Identifier Register 0 Identifier Register 1 Identifier Register 2 Identifier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Transmit Buffer Priority Register1 Time Stamp Register (High Byte)2 Time Stamp Register (Low Byte)3
Access
Not applicable for receive buffers Read-only for CPU 3 Read-only for CPU
Figure 14-24 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 14-25. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit priority registers are 0 out of reset. MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 547
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Register Name 0x00X0 IDR0 0x00X1 IDR1 0x00X2 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLR R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 ID28
6 ID27
5 ID26
4 ID25
3 ID24
2 ID23
1 ID22
Bit0 ID21
ID20
ID19
ID18
SRR (=1)
IDE (=1)
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
= Unused, always read ‘x’
Figure 14-24. Receive/Transmit Message Buffer — Extended Identifier Mapping
Read: For transmit buffers, anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only when RXF flag is set (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).
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Write: For transmit buffers, anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for receive buffers. Reset: Undefined (0x00XX) because of RAM-based implementation
Register Name IDR0 0x00X0 IDR1 0x00X1 IDR2 0x00X2 IDR3 0x00X3 R W R W R W R W Bit 7 ID10 6 ID9 5 ID8 4 ID7 3 ID6 2 ID5 1 ID4 Bit 0 ID3
ID2
ID1
ID0
RTR
IDE (=0)
= Unused, always read ‘x’
Figure 14-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
14.3.3.1
Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE, and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0], RTR, and IDE bits. 14.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping
Module Base + 0x00X1
7 6 5 4 3 2 1 0
R ID28 W Reset: x x x x x x x x ID27 ID26 ID25 ID24 ID23 ID22 ID21
Figure 14-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping Table 14-25. IDR0 Register Field Descriptions — Extended
Field 7:0 ID[28:21] Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
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Module Base + 0x00X1
7 6 5 4 3 2 1 0
R ID20 W Reset: x x x x x x x x ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15
Figure 14-27. Identifier Register 1 (IDR1) — Extended Identifier Mapping Table 14-26. IDR1 Register Field Descriptions — Extended
Field 7:5 ID[20:18] 4 SRR 3 IDE Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Substitute Remote Request — This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
2:0 ID[17:15]
Module Base + 0x00X2
7 6 5 4 3 2 1 0
R ID14 W Reset: x x x x x x x x ID13 ID12 ID11 ID10 ID9 ID8 ID7
Figure 14-28. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 14-27. IDR2 Register Field Descriptions — Extended
Field 7:0 ID[14:7] Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
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Module Base + 0x00X3
7 6 5 4 3 2 1 0
R ID6 W Reset: x x x x x x x x ID5 ID4 ID3 ID2 ID1 ID0 RTR
Figure 14-29. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 14-28. IDR3 Register Field Descriptions — Extended
Field 7:1 ID[6:0] 0 RTR Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Remote Transmission Request — This flag reflects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame
14.3.3.1.2
IDR0–IDR3 for Standard Identifier Mapping
Module Base + 0x00X0
7 6 5 4 3 2 1 0
R ID10 W Reset: x x x x x x x x ID9 ID8 ID7 ID6 ID5 ID4 ID3
Figure 14-30. Identifier Register 0 — Standard Mapping Table 14-29. IDR0 Register Field Descriptions — Standard
Field 7:0 ID[10:3] Description Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 14-30.
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Module Base + 0x00X1
7 6 5 4 3 2 1 0
R ID2 W Reset: x x x x x x x x ID1 ID0 RTR IDE (=0)
= Unused; always read ‘x’
Figure 14-31. Identifier Register 1 — Standard Mapping Table 14-30. IDR1 Register Field Descriptions
Field 7:5 ID[2:0] 4 RTR Description Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 14-29. Remote Transmission Request — This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit)
3 IDE
Module Base + 0x00X2
7 6 5 4 3 2 1 0
R W Reset: x x x x x x x x
= Unused; always read ‘x’
Figure 14-32. Identifier Register 2 — Standard Mapping
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Module Base + 0x00X3
7 6 5 4 3 2 1 0
R W Reset: x x x x x x x x
= Unused; always read ‘x’
Figure 14-33. Identifier Register 3 — Standard Mapping
14.3.3.2
Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register.
Module Base + 0x0004 (DSR0) 0x0005 (DSR1) 0x0006 (DSR2) 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7)
7 6 5 4 3 2 1 0
R DB7 W Reset: x x x x x x x x DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 14-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
Table 14-31. DSR0–DSR7 Register Field Descriptions
Field 7:0 DB[7:0] Data bits 7:0 Description
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14.3.3.3
Data Length Register (DLR)
This register keeps the data length field of the CAN frame.
Module Base + 0x00XB
7 6 5 4 3 2 1 0
R DLC3 W Reset: x x x x x x x x DLC2 DLC1 DLC0
= Unused; always read “x”
Figure 14-35. Data Length Register (DLR) — Extended Identifier Mapping
Table 14-32. DLR Register Field Descriptions
Field 3:0 DLC[3:0] Description Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 14-33 shows the effect of setting the DLC bits.
Table 14-33. Data Length Codes
Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8
14.3.3.4
Transmit Buffer Priority Register (TBPR)
This register defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: • All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. • The transmission buffer with the lowest local priority field wins the prioritization.
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In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.
Module Base + 0xXXXD
7 6 5 4 3 2 1 0
R PRIO7 W Reset: 0 0 0 0 0 0 0 0 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Figure 14-36. Transmit Buffer Priority Register (TBPR)
Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
14.3.3.5
Time Stamp Register (TSRH–TSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers.
Module Base + 0xXXXE
7 6 5 4 3 2 1 0
R W Reset:
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
x
x
x
x
x
x
x
x
Figure 14-37. Time Stamp Register — High Byte (TSRH)
Module Base + 0xXXXF
7 6 5 4 3 2 1 0
R W Reset:
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
x
x
x
x
x
x
x
x
Figure 14-38. Time Stamp Register — Low Byte (TSRL)
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Read: Anytime when TXEx flag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented
14.4
14.4.1
Functional Description
General
This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction.
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14.4.2
Message Storage
CAN Receive / Transmit Engine CPU12 Memory Mapped I/O
Rx0
Rx1 Rx2 Rx3 Rx4
RXF
RxBG
MSCAN
Receiver
Tx0
RxFG
CPU bus
TXE0
TxBG
Tx1
PRIO
TXE1
TxFG
MSCAN
CPU bus
PRIO
Tx2
TXE2
Transmitter
TxBG
PRIO
Figure 14-39. User Model for Message Buffer Organization
MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
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14.4.2.1
Message Transmit Background
Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. • The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the “local priority” concept described in Section 14.4.2.2, “Transmit Structures.”
14.4.2.2
Transmit Structures
The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 14-39. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 14.3.3, “Programmer’s Model of Message Storage”). An additional Section 14.3.3.4, “Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (see Section 14.3.3.4, “Transmit Buffer Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a message, if required (see Section 14.3.3.5, “Time Stamp Register (TSRH–TSRL)”). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section 14.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
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The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 14.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”.) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
14.4.2.3
Receive Structures
The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (see Figure 14-39). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 14-39). This scheme simplifies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (see Section 14.3.3, “Programmer’s Model of Message Storage”). The receiver full flag (RXF) (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”) signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identifier, this flag is set. On reception, each message is checked to see whether it passes the filter (see Section 14.4.3, “Identifier Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO2, sets the RXF flag, and generates a receive interrupt (see Section 14.4.7.3, “Receive Interrupt”) to the CPU3. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF flag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 559
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field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers and another message is correctly received from the CAN bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 14.4.7.5, “Error Interrupt”). The MSCAN remains able to transmit messages while the receiver FIFO being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted.
14.4.3
Identifier Acceptance Filter
The MSCAN identifier acceptance registers (see Section 14.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”) define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identifier mask registers (see Section 14.3.2.18, “MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)”). A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits in the CANIDAC register (see Section 14.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more filters match), the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes (see Bosch CAN 2.0A/B protocol specification): • Two identifier acceptance filters, each to be applied to: — The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame: – Remote transmission request (RTR) – Identifier extension (IDE) – Substitute remote request (SRR) — The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages1. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Figure 14-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit.
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•
•
•
Four identifier acceptance filters, each to be applied to — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 14-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits. Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier. Figure 14-42 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 4 to 7 hits. Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set.
IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3
CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
ID Accepted (Filter 0 Hit)
Figure 14-40. 32-bit Maskable Identifier Acceptance Filter
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CAN 2.0B Extended Identifier CAN 2.0A/B Standard Identifier
ID28 ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
ID Accepted (Filter 0 Hit)
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
ID Accepted (Filter 1 Hit)
Figure 14-41. 16-bit Maskable Identifier Acceptance Filters
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CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0
AC7
CIDAR0
AC0
ID Accepted (Filter 0 Hit)
AM7
CIDMR1
AM0
AC7
CIDAR1
AC0
ID Accepted (Filter 1 Hit)
AM7
CIDMR2
AM0
AC7
CIDAR2
AC0
ID Accepted (Filter 2 Hit)
AM7
CIDMR3
AM0
AC7
CIDAR3
AC0
ID Accepted (Filter 3 Hit)
Figure 14-42. 8-bit Maskable Identifier Acceptance Filters
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14.4.3.1
Protocol Violation Protection
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) serve as a lock to protect the following registers: — MSCAN control 1 register (CANCTL1) — MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) — MSCAN identifier acceptance control register (CANIDAC) — MSCAN identifier acceptance registers (CANIDAR0–CANIDAR7) — MSCAN identifier mask registers (CANIDMR0–CANIDMR7) • The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 14.4.5.6, “MSCAN Power Down Mode,” and Section 14.4.5.5, “MSCAN Initialization Mode”). • The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN.
14.4.3.2
Clock System
Figure 14-43 shows the structure of the MSCAN clock generation circuitry.
MSCAN
Bus Clock
CANCLK CLKSRC
Prescaler (1 .. 64)
Time quanta clock (Tq)
CLKSRC Oscillator Clock
Figure 14-43. MSCAN Clocking Scheme
The clock source bit (CLKSRC) in the CANCTL1 register (14.3.2.2/14-526) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required.
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If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN.
Eqn. 14-2
f CANCLK = ----------------------------------------------------Tq ( Prescaler value ) A bit time is subdivided into three segments as described in the Bosch CAN specification. (see Figure 14-44): • SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. • Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. • Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
Eqn. 14-3
f Tq Bit Rate = -------------------------------------------------------------------------------( number of Time Quanta )
NRZ Signal
SYNC_SEG
Time Segment 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8 ... 25 Time Quanta = 1 Bit Time
Time Segment 2 (PHASE_SEG2) 2 ... 8
1
Transmit Point
Sample Point (single or triple sampling)
Figure 14-44. Segments within the Bit Time
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Table 14-34. Time Segment Syntax
Syntax SYNC_SEG Transmit Point Description System expects transitions to occur on the CAN bus during this period. A node in transmit mode transfers a new value to the CAN bus at this point. A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
Sample Point
The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (see Section 14.3.2.3, “MSCAN Bus Timing Register 0 (CANBTR0)” and Section 14.3.2.4, “MSCAN Bus Timing Register 1 (CANBTR1)”). Table 14-35 gives an overview of the CAN compliant segment settings and the related parameter values. NOTE It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard.
Table 14-35. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchronization Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3
14.4.4
14.4.4.1
Modes of Operation
Normal Modes
The MSCAN module behaves as described within this specification in all normal system operation modes.
14.4.4.2
Special Modes
The MSCAN module behaves as described within this specification in all special system operation modes.
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14.4.4.3
Emulation Modes
In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification.
14.4.4.4
Listen-Only Mode
In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmision. If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although the CAN bus may remain in recessive state externally.
14.4.4.5
Security Modes
The MSCAN module has no security features.
14.4.5
Low-Power Options
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 14-36 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
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Table 14-36. CPU vs. MSCAN Operating Modes
MSCAN Mode CPU Mode Normal Sleep CSWAI = X1 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X Power Down Reduced Power Consumption Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X
RUN
WAIT
STOP
1
‘X’ means don’t care.
14.4.5.1
Operation in Run Mode
As shown in Table 14-36, only MSCAN sleep mode is available as low power option when the CPU is in run mode.
14.4.5.2
Operation in Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts its internal controllers and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the low-power modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 14-36.
14.4.5.3
Operation in Stop Mode
The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits (Table 14-36).
14.4.5.4
MSCAN Sleep Mode
The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity:
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•
• •
If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.
Bus Clock Domain
CAN Clock Domain SLPRQ Flag
SLPRQ CPU Sleep Request
SYNC
sync. SLPRQ
SLPAK Flag
sync.
SLPAK
SYNC
SLPAK MSCAN in Sleep Mode
Figure 14-45. Sleep Request / Acknowledge Cycle
NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 14-45). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect. The MSCAN is able to leave sleep mode (wake up) only when: • CAN bus activity occurs and WUPE = 1
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•
or the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active.
After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits.
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14.4.5.5
MSCAN Initialization Mode
In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. See Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode.
Bus Clock Domain
CAN Clock Domain INIT Flag
INITRQ CPU Init Request
SYNC
sync. INITRQ
INITAK Flag
sync.
INITAK
SYNC
INITAK
Figure 14-46. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Section Figure 14-46., “Initialization Request/Acknowledge Cycle”). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active.
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14.4.5.6
MSCAN Power Down Mode
The MSCAN is in power down mode (Table 14-36) when • CPU is in stop mode or • CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again.
14.4.5.7
Programmable Wake-Up Function
The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see control bit WUPE in Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The sensitivity to existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line while in sleep mode (see control bit WUPM in Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from—for example—electromagnetic interference within noisy environments.
14.4.6
Reset Initialization
The reset state of each individual bit is listed in Section 14.3.2, “Register Descriptions,” which details all the registers and their bit-fields.
14.4.7
Interrupts
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated flags. Each interrupt is listed and described separately.
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14.4.7.1
Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see Table 14-37), any of which can be individually masked (for details see sections from Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER),” to Section 14.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter.
Table 14-37. Interrupt Vectors
Interrupt Source Wake-Up Interrupt (WUPIF) Error Interrupts Interrupt (CSCIF, OVRIF) Receive Interrupt (RXF) Transmit Interrupts (TXE[2:0]) CCR Mask I bit I bit I bit I bit Local Enable CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0])
14.4.7.2
Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set.
14.4.7.3
Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer.
14.4.7.4
Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN internal sleep mode. WUPE (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must be enabled.
14.4.7.5
Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: • Overrun — An overrun condition of the receiver FIFO as described in Section 14.4.2.3, “Receive Structures,” occurred. • CAN Status Change — The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
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Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” and Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”).
14.4.7.6
Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in either the Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” or the Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG).” Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine.
14.4.7.7
Recovery from Stop or Wait
The MSCAN can recover from stop or wait via the wake-up interrupt. This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
14.5
14.5.1
Initialization/Application Information
MSCAN initialization
The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode and enter normal mode If the configuration of registers which are writable in initialization mode needs to be changed only when the MSCAN module is in normal mode: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode
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14.5.2
Bus-Off Recovery
The bus-off recovery is user configurable. The bus-off state can either be left automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (See the Bosch CAN specification for details). If the MSCAN is configured for user request (BORM set in Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”), the recovery from bus-off starts after both independent events have become true: • 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in Section 14.3.2.14, “MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order.
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Chapter 15 Serial Communication Interface (SCIV5)
15.1 Introduction
This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs.
15.1.1
Glossary
IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin
15.1.2
Features
The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 13-bit baud rate selection • Programmable 8-bit or 9-bit data format • Separately enabled transmitter and receiver • Programmable polarity for transmitter and receiver
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• •
•
• • •
Programmable transmitter output parity Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection
15.1.3
Modes of Operation
The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode
15.1.4
Block Diagram
Figure 15-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks.
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SCI Data Register RXD Data In Infrared Decoder
Receive Shift Register IDLE Receive RDRF/OR Interrupt Generation BRKD RXEDG BERR Transmit TDRE Interrupt Generation TC
Receive & Wakeup Control
SCI Interrupt Request
Bus Clock
Baud Rate Generator
Data Format Control
1/16
Transmit Control
Transmit Shift Register
Infrared Encoder
Data Out TXD
SCI Data Register
Figure 15-1. SCI Block Diagram
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15.2
External Signal Description
The SCI module has a total of two external pins.
15.2.1
TXD — Transmit Pin
The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled.
15.2.2
RXD — Receive Pin
The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage.
15.3
Memory Map and Register Definition
This section provides a detailed description of all the SCI registers.
15.3.1
Module Memory Map and Register Definition
The memory map for the SCI module is given below in Figure 15-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.
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15.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.
Register Name SCIBDH1 R W SCIBDL1 R W SCICR11 R W SCIASR12 R W SCIACR12 R W SCIACR22 R W SCICR2 R W SCISR1 R W SCISR2 R W SCIDRH R W SCIDRL R W R7 T7 AMAP R8 0 0 TXPOL 0 RXPOL 0 BRK13 0 TXDIR 0 RAF TIE TDRE TCIE TC RIE RDRF ILIE IDLE TE OR Bit 7 IREN 6 TNP1 5 TNP0 4 SBR12 3 SBR11 2 SBR10 1 SBR9 Bit 0 SBR8
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
LOOPS
SCISWAI 0
RSRC 0
M 0
WAKE 0
ILT
PE
PT
RXEDGIF
BERRV 0
BERRIF
BKDIF
RXEDGIE 0
0
0
0
0
BERRIE
BKDIE
0
0
0
0
BERRM1
BERRM0
BKDFE
RE NF
RWU FE
SBK PF
T8 R6 T6
0
0
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved
Figure 15-2. SCI Register Summary
1 2
Those registers are accessible if the AMAP bit in the SCISR2 register is set to zero Those registers are accessible if the AMAP bit in the SCISR2 register is set to one
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15.3.2.1
R W Reset
SCI Baud Rate Registers (SCIBDH, SCIBDL)
7 6 5 4 3 2 1 0
IREN 0
TNP1 0
TNP0 0
SBR12 0
SBR11 0
SBR10 0
SBR9 0
SBR8 0
Figure 15-3. SCI Baud Rate Register (SCIBDH)
7 6 5 4 3 2 1 0
R W Reset
SBR7 0
SBR6 0
SBR5 0
SBR4 0
SBR3 0
SBR2 0
SBR1 0
SBR0 0
Figure 15-4. SCI Baud Rate Register (SCIBDL)
Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: Anytime, if AMAP = 0. NOTE Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule.
Table 15-1. SCIBDH and SCIBDL Field Descriptions
Field 7 IREN 6:5 TNP[1:0] 4:0 7:0 SBR[12:0] Description Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule. 0 IR disabled 1 IR enabled Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. See Table 15-2. SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI bus clock / (16 x SBR[12:0]) When IREN = 1 then, SCI baud rate = SCI bus clock / (32 x SBR[12:1]) Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the first time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and IREN = 1). Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in a temporary location until SCIBDL is written to.
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Table 15-2. IRSCI Transmit Pulse Width
TNP[1:0] 11 10 01 00 Narrow Pulse Width 1/4 1/32 1/16 3/16
15.3.2.2
R W Reset
SCI Control Register 1 (SCICR1)
7 6 5 4 3 2 1 0
LOOPS 0
SCISWAI 0
RSRC 0
M 0
WAKE 0
ILT 0
PE 0
PT 0
Figure 15-5. SCI Control Register 1 (SCICR1)
Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition).
Table 15-3. SCICR1 Field Descriptions
Field 7 LOOPS Description Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit. SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode. 0 SCI enabled in wait mode 1 SCI disabled in wait mode Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. See Table 15-4. 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long. 0 One start bit, eight data bits, one stop bit 1 One start bit, nine data bits, one stop bit Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD pin. 0 Idle line wakeup 1 Address mark wakeup
6 SCISWAI 5 RSRC
4 M 3 WAKE
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 583
Chapter 15 Serial Communication Interface (SCIV5)
Table 15-3. SCICR1 Field Descriptions (continued)
Field 2 ILT Description Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled 1 Parity function enabled Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 1 Even parity 1 Odd parity
1 PE
0 PT
Table 15-4. Loop Functions
LOOPS 0 1 1 RSRC x 0 1 Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input Function
MC9S12XHZ512 Data Sheet, Rev. 1.03 584 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.3.2.3
R W Reset
SCI Alternative Status Register 1 (SCIASR1)
7 6 5 4 3 2 1 0
RXEDGIF 0
0 0
0 0
0 0
0 0
BERRV 0
BERRIF 0
BKDIF 0
= Unimplemented or Reserved
Figure 15-6. SCI Alternative Status Register 1 (SCIASR1)
Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1
Table 15-5. SCIASR1 Field Descriptions
Field 7 RXEDGIF Description Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it. 0 No active receive on the receive input has occurred 1 An active edge on the receive input has occurred Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1. 0 A low input was sampled, when a high was expected 1 A high input reassembled, when a low was expected Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it. 0 No mismatch detected 1 A mismatch has occurred Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received
2 BERRV
1 BERRIF
0 BKDIF
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 585
Chapter 15 Serial Communication Interface (SCIV5)
15.3.2.4
R W Reset
SCI Alternative Control Register 1 (SCIACR1)
7 6 5 4 3 2 1 0
RXEDGIE 0
0 0
0 0
0 0
0 0
0 0
BERRIE 0
BKDIE 0
= Unimplemented or Reserved
Figure 15-7. SCI Alternative Control Register 1 (SCIACR1)
Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1
Table 15-6. SCIACR1 Field Descriptions
Field 7 RSEDGIE Description Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag, RXEDGIF, to generate interrupt requests. 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt requests enabled Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt requests. 0 BERRIF interrupt requests disabled 1 BERRIF interrupt requests enabled Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled
1 BERRIE
0 BKDIE
MC9S12XHZ512 Data Sheet, Rev. 1.03 586 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.3.2.5
R W Reset
SCI Alternative Control Register 2 (SCIACR2)
7 6 5 4 3 2 1 0
0 0
0 0
0 0
0 0
0 0
BERRM1 0
BERRM0 0
BKDFE 0
= Unimplemented or Reserved
Figure 15-8. SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1
Table 15-7. SCIACR2 Field Descriptions
Field Description
2:1 Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 15-8. BERRM[1:0] 0 BKDFE Break Detect Feature Enable — BKDFE enables the break detect circuitry. 0 Break detect circuit disabled 1 Break detect circuit enabled
Table 15-8. Bit Error Mode Coding
BERRM1 0 0 1 1 BERRM0 0 1 0 1 Bit error detect circuit is disabled Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 15-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 15-19) Reserved Function
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 587
Chapter 15 Serial Communication Interface (SCIV5)
15.3.2.6
R W Reset
SCI Control Register 2 (SCICR2)
7 6 5 4 3 2 1 0
TIE 0
TCIE 0
RIE 0
ILIE 0
TE 0
RE 0
RWU 0
SBK 0
Figure 15-9. SCI Control Register 2 (SCICR2)
Read: Anytime Write: Anytime
Table 15-9. SCICR2 Field Descriptions
Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 0 TDRE interrupt requests disabled 1 TDRE interrupt requests enabled Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate interrupt requests. 0 TC interrupt requests disabled 1 TC interrupt requests enabled Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests. 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit — RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters
6 TCIE
5 RIE
4 ILIE 3 TE
2 RE 1 RWU
0 SBK
MC9S12XHZ512 Data Sheet, Rev. 1.03 588 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.3.2.7
SCI Status Register 1 (SCISR1)
The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing.
7 6 5 4 3 2 1 0
R W Reset
TDRE 1
TC 1
RDRF 0
IDLE 0
OR 0
NF 0
FE 0
PF 0
= Unimplemented or Reserved
Figure 15-10. SCI Status Register 1 (SCISR1)
Read: Anytime Write: Has no meaning or effect
Table 15-10. SCISR1 Field Descriptions
Field 7 TDRE Description Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL). 0 No byte transferred to transmit shift register 1 Byte transferred to transmit shift register; transmit data register empty Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete). 0 Transmission in progress 1 No transmission in progress Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL). 0 Data not available in SCI data register 1 Received data available in SCI data register Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag.
6 TC
5 RDRF
4 IDLE
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 589
Chapter 15 Serial Communication Interface (SCIV5)
Table 15-10. SCISR1 Field Descriptions (continued)
Field 3 OR Description Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL). 0 No overrun 1 Overrun Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received. Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL). 0 No framing error 1 Framing error Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error
2 NF
1 FE
0 PF
MC9S12XHZ512 Data Sheet, Rev. 1.03 590 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.3.2.8
R W Reset
SCI Status Register 2 (SCISR2)
7 6 5 4 3 2 1 0
AMAP 0
0 0
0 0
TXPOL 0
RXPOL 0
BRK13 0
TXDIR 0
RAF 0
= Unimplemented or Reserved
Figure 15-11. SCI Status Register 2 (SCISR2)
Read: Anytime Write: Anytime
Table 15-11. SCISR2 Field Descriptions
Field 7 AMAP Description Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and status registers and hides the baud rate and SCI control Register 1. 0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible 1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 Normal polarity 1 Inverted polarity Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 Normal polarity 1 Inverted polarity Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit. 0 Break character is 10 or 11 bit long 1 Break character is 13 or 14 bit long Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire mode of operation. 0 TXD pin to be used as an input in single-wire mode 1 TXD pin to be used as an output in single-wire mode Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress
4 TXPOL
3 RXPOL
2 BRK13
1 TXDIR
0 RAF
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 591
Chapter 15 Serial Communication Interface (SCIV5)
15.3.2.9
R W Reset
SCI Data Registers (SCIDRH, SCIDRL)
7 6 5 4 3 2 1 0
R8 0
T8 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 15-12. SCI Data Registers (SCIDRH)
7 6 5 4 3 2 1 0
R W Reset
R7 T7 0
R6 T6 0
R5 T5 0
R4 T4 0
R3 T3 0
R2 T2 0
R1 T1 0
R0 T0 0
Figure 15-13. SCI Data Registers (SCIDRL)
Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
Table 15-12. SCIDRH and SCIDRL Field Descriptions
Field SCIDRH 7 R8 SCIDRH 6 T8 SCIDRL 7:0 R[7:0] T[7:0] Description Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats
NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL.
MC9S12XHZ512 Data Sheet, Rev. 1.03 592 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.4
Functional Description
This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 15-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
IREN SCI Data Register RXD Infrared Receive Decoder Ir_RXD SCRXD Receive Shift Register RE R16XCLK Receive and Wakeup Control RWU LOOPS RSRC M Baud Rate Generator WAKE Data Format Control ILT PE SBR12:SBR0 PT TCIE TE ÷16 Transmit Control LOOPS SBK RSRC T8 Transmit Shift Register SCI Data Register RXEDGIE Active Edge Detect Break Detect BKDIE TC TDRE TC TDRE SCI Interrupt Request R8 NF FE PF RAF IDLE RDRF OR RIE TIE RDRF/OR RXEDGIF BKDIF RXD BERRIE Infrared Transmit Encoder R32XCLK TNP[1:0] IREN BERRM[1:0] Ir_TXD TXD ILIE IDLE
Bus Clock
BKDFE
SCTXD R16XCLK
LIN Transmit BERRIF Collision Detect
Figure 15-14. Detailed SCI Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 593
Chapter 15 Serial Communication Interface (SCIV5)
15.4.1
Infrared Interface Submodule
This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s. The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low pulses. The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK, which are configured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock.
15.4.1.1
Infrared Transmit Encoder
The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set.
15.4.1.2
Infrared Receive Decoder
The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when RXPOL is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification.
15.4.2
LIN Support
This module provides some basic support for the LIN protocol. At first this is a break detect circuitry making it easier for the LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.
MC9S12XHZ512 Data Sheet, Rev. 1.03 594 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.4.3
Data Format
The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 15-15 below.
8-Bit Data Format (Bit M in SCICR1 Clear) Start Bit Possible Parity Bit Bit 6 Bit 7 STOP Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Next Start Bit
Standard SCI Data
Infrared SCI Data
9-Bit Data Format (Bit M in SCICR1 Set) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
POSSIBLE PARITY Bit Bit 8 STOP Bit
NEXT START Bit
Standard SCI Data Infrared SCI Data
Figure 15-15. SCI Data Formats
Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits.
Table 15-13. Example of 8-Bit Data Formats
Start Bit 1 1 1
1
Data Bits 8 7 7
Address Bits 0 0 1
1
Parity Bits 0 1 0
Stop Bit 1 1 1
The address bit identifies the frame as an address character. See Section 15.4.6.6, “Receiver Wakeup”.
When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits.
Table 15-14. Example of 9-Bit Data Formats
Start Bit 1 1 1 Data Bits 9 8 8 Address Bits 0 0 1
1
Parity Bits 0 1 0
Stop Bit 1 1 1
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 595
Chapter 15 Serial Communication Interface (SCIV5)
1
The address bit identifies the frame as an address character. See Section 15.4.6.6, “Receiver Wakeup”.
15.4.4
Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error: • Integer division of the bus clock may not give the exact target frequency. Table 15-15 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz. When IREN = 0 then, SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])
Table 15-15. Baud Rates (Example: Bus Clock = 25 MHz)
Bits SBR[12:0] 41 81 163 326 651 1302 2604 5208 Receiver Clock (Hz) 609,756.1 308,642.0 153,374.2 76,687.1 38,402.5 19,201.2 9600.6 4800.0 Transmitter Clock (Hz) 38,109.8 19,290.1 9585.9 4792.9 2400.2 1200.1 600.0 300.0 Target Baud Rate 38,400 19,200 9,600 4,800 2,400 1,200 600 300 Error (%) .76 .47 .16 .15 .01 .01 .00 .00
MC9S12XHZ512 Data Sheet, Rev. 1.03 596 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.4.5
Transmitter
Internal Bus
Bus Clock
Baud Divider
÷ 16
SCI Data Registers
SBR12:SBR0 Start Stop 11-Bit Transmit Register 8 MSB 7 6 5 4 3 2 1 0 TXPOL SCTXD
M
H
L
T8 Load from SCIDR Preamble (All 1s) Break (All 0s)
LOOP CONTROL
To Receiver
PT TDRE IRQ
Parity Generation TIE TDRE
Shift Enable
PE
LOOPS RSRC
Transmitter Control TC IRQ TC TCIE TE SBK BERRM[1:0]
BERRIF BER IRQ TCIE
Transmit Collision Detect
SCTXD SCRXD (From Receiver)
Figure 15-16. Transmitter Block Diagram
15.4.5.1
Transmitter Character Length
The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
15.4.5.2
Character Transmission
To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 597
Chapter 15 Serial Communication Interface (SCIV5)
The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word length, parity, and other configuration bits (LOOPS,RSRC,M,WAKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for each byte: a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request.
MC9S12XHZ512 Data Sheet, Rev. 1.03 598 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L.
15.4.5.3
Break Characters
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received. Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI registers. If the break detect feature is disabled (BKDFE = 0): • Sets the framing error flag, FE • Sets the receive data register full flag, RDRF • Clears the SCI data registers (SCIDRH/L) • May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see 3.4.4 and 3.4.5 SCI Status Register 1 and 2) If the break detect feature is enabled (BKDFE = 1) there are two scenarios1 The break is detected right from a start bit or is detected during a byte reception. • Sets the break detect interrupt flag, BLDIF • Does not change the data register full flag, RDRF or overrun flag OR • Does not change the framing error flag FE, parity error flag PE. • Does not clear the SCI data registers (SCIDRH/L) • May set noise flag NF, or receiver active flag RAF.
1. A Break character in this context are either 10 or 11 consecutive zero received bits
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 599
Chapter 15 Serial Communication Interface (SCIV5)
Figure 15-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission. At the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate a parity error will be set. Once the break is detected the BRKDIF flag will be set.
Start Bit Position Stop Bit Position BRKDIF = 1 RXD_1 Zero Bit Counter 1 2 3 4 5 6 7 8 9 10 . . . FE = 1 RXD_2 BRKDIF = 1
Zero Bit Counter
1
2
3
4
5
6
7
8
9
10
...
Figure 15-17. Break Detection if BRKDFE = 1 (M = 0)
15.4.5.4
Idle Characters
An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin
MC9S12XHZ512 Data Sheet, Rev. 1.03 600 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.4.5.5
LIN Transmit Collision Detection
LIN Physical Interface
This module allows to check for collisions on the LIN bus.
Synchronizer Stage Receive Shift Register Compare Bit Error Bus Clock
RXD Pin LIN Bus
Sample Point Transmit Shift Register TXD Pin
Figure 15-18. Collision Detect Principle
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received data is detected the following happens: • The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1) • The transmission is aborted and the byte in transmit buffer is discarded. • the transmit data register empty and the transmission complete flag will be set • The bit error interrupt flag, BERRIF, will be set. • No further transmissions will take place until the BERRIF is cleared.
0 1 2 3 4 5 6 7 8 Sampling Begin 9 Sampling End 10 11 12 Sampling Begin 13 Sampling End 14 15 0
Output Transmit Shift Register Input Receive Shift Register
BERRM[1:0] = 0:1
BERRM[1:0] = 1:1
Compare Sample Points
Figure 15-19. Timing Diagram Bit Error Detection
If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 601
Chapter 15 Serial Communication Interface (SCIV5)
15.4.6
Receiver
Internal Bus
SBR12:SBR0
SCI Data Register
11-Bit Receive Shift Register 8 7 6 All 1s 5 4 3 2 1 0
RXPOL SCRXD From TXD Pin or Transmitter Loop Control
Data Recovery
H
RE RAF
MSB
LOOPS RSRC
FE M WAKE ILT PE PT Wakeup Logic NF PE RWU
Parity Checking
R8 IDLE ILIE Idle IRQ
Start L RDRF/OR IRQ
BRKDFE
Stop
Bus Clock
Baud Divider
RDRF OR RIE Break IRQ
Break Detect Logic
BRKDIF BRKDIE
Active Edge Detect Logic
RXEDGIF RXEDGIE RX Active Edge IRQ
Figure 15-20. SCI Receiver Block Diagram
15.4.6.1
Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
15.4.6.2
Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
MC9S12XHZ512 Data Sheet, Rev. 1.03 602 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
15.4.6.3
Data Sampling
The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 15-21) is re-synchronized: • After every start bit • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Start Bit RXD Samples 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 LSB
Start Bit Qualification
Start Bit Verification
Data Sampling
RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT10 RT11 RT12 RT13 RT14 RT15 RT CLock Count Reset RT Clock RT16 RT4
Figure 15-21. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Figure 15-16 summarizes the results of the start bit verification samples.
Table 15-16. Start Bit Verification
RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 603
Chapter 15 Serial Communication Interface (SCIV5)
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-17 summarizes the results of the data bit samples.
Table 15-17. Data Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0
NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-18 summarizes the results of the stop bit samples.
Table 15-18. Stop Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 604 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
In Figure 15-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
Start Bit RXD Samples 1 1 1 0 1 1 1 0 0 0 0 0 0 0 LSB
RT Clock RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 LSB RT6 RT Clock Count Reset RT Clock RT3 RT7
Figure 15-22. Start Bit Search Example 1
In Figure 15-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Perceived Start Bit Actual Start Bit RXD Samples 1 1 1 1 1 0 1 0 0 0 0 0
RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT10 RT11 RT12 RT13 RT14 RT15 RT Clock Count Reset RT Clock RT16 RT5
Figure 15-23. Start Bit Search Example 2
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 605
Chapter 15 Serial Communication Interface (SCIV5)
In Figure 15-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Perceived Start Bit Actual Start Bit RXD Samples 1 1 1 0 0 1 0 0 0 0 LSB
RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 LSB RT2 RT10 RT11 RT12 RT13 RT14 RT15 RT Clock Count Reset RT Clock RT16 RT9 RT3
Figure 15-24. Start Bit Search Example 3
Figure 15-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag.
Perceived and Actual Start Bit RXD Samples 1 1 1 1 1 1 1 1 1 0 1 0
RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT Clock Count Reset RT Clock
Figure 15-25. Start Bit Search Example 4
MC9S12XHZ512 Data Sheet, Rev. 1.03 606 Freescale Semiconductor
RT16
RT1
Chapter 15 Serial Communication Interface (SCIV5)
Figure 15-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
Start Bit RXD Samples 1 1 1 1 1 1 1 1 1 0 0 1 1 0 No Start Bit Found 0 0 0 0 0 0 0 LSB
RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 LSB RT2 RT Clock Count Reset RT Clock RT1 RT3
Figure 15-26. Start Bit Search Example 5
In Figure 15-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored.
Start Bit RXD Samples 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1
RT Clock RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT Clock Count Reset RT Clock RT1
Figure 15-27. Start Bit Search Example 6
15.4.6.4
Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 607
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15.4.6.5
Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 15.4.6.5.1 Slow Data Tolerance
Figure 15-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB Stop
Receiver RT Clock RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
Data Samples
Figure 15-28. Slow Data
Let’s take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 15-28, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 – 144) / 151) x 100 = 4.63% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 15-28, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19%
MC9S12XHZ512 Data Sheet, Rev. 1.03 608 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
15.4.6.5.2
Fast Data Tolerance
Figure 15-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
Stop Idle or Next Frame
Receiver RT Clock RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
Data Samples
Figure 15-29. Fast Data
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 15-29, the receiver counts 154 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 – 154) / 160) x 100 = 3.75% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 15-29, the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 – 170) /176) x 100 = 3.40%
15.4.6.6
Receiver Wakeup
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 609
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15.4.6.6.1
Idle Input line Wakeup (WAKE = 0)
In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1). 15.4.6.6.2 Address Mark Wakeup (WAKE = 1)
In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately.
15.4.7
Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting.
Transmitter TXD
Receiver
RXD
Figure 15-30. Single-Wire Operation (LOOPS = 1, RSRC = 1)
MC9S12XHZ512 Data Sheet, Rev. 1.03 610 Freescale Semiconductor
Chapter 15 Serial Communication Interface (SCIV5)
Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. NOTE In single-wire operation data from the TXD pin is inverted if RXPOL is set.
15.4.8
Loop Operation
In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI.
Transmitter TXD
Receiver
RXD
Figure 15-31. Loop Operation (LOOPS = 1, RSRC = 0)
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same.
15.5
15.5.1
Initialization/Application Information
Reset Initialization
See Section 15.3.2, “Register Descriptions”.
15.5.2
15.5.2.1
Modes of Operation
Run Mode
Normal mode of operation. To initialize a SCI transmission, see Section 15.4.5.2, “Character Transmission”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 611
Chapter 15 Serial Communication Interface (SCIV5)
15.5.2.2
Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI.
15.5.2.3
Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input can be used to bring the CPU out of stop mode.
15.5.3
Interrupt Operation
This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 15-19 lists the eight interrupt sources of the SCI.
Table 15-19. SCI Interrupt Sources
Interrupt TDRE TC RDRF OR IDLE Source SCISR1[7] SCISR1[6] SCISR1[5] SCISR1[3] SCISR1[4] ILIE RXEDGIE BERRIE BRKDIE Local Enable TIE TCIE RIE Description Active high level. Indicates that a byte was transferred from SCIDRH/L to the transmit shift register. Active high level. Indicates that a transmit is complete. Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. Active high level. This interrupt indicates that an overrun condition has occurred. Active high level. Indicates that receiver input has become idle. Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected. Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. Active high level. Indicates that a break character has been received.
RXEDGIF SCIASR1[7] BERRIF BKDIF SCIASR1[1] SCIASR1[0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 612 Freescale Semiconductor
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15.5.3.1
Description of Interrupt Operation
The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 15.5.3.1.1 TDRE Description
The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL). 15.5.3.1.2 TC Description
The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providing there is no more data queued for transmission) when the break character has been shifted out. A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent. 15.5.3.1.3 RDRF Description
The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 15.5.3.1.4 OR Description
The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 15.5.3.1.5 IDLE Description
The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).
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Chapter 15 Serial Communication Interface (SCIV5)
15.5.3.1.6
RXEDGIF Description
The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 15.5.3.1.7 BERRIF Description
The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if the bit error detect feature is disabled. 15.5.3.1.8 BKDIF Description
The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled.
15.5.4
Recovery from Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode.
15.5.5
Recovery from Stop Mode
An active edge on the receive input can be used to bring the CPU out of stop mode.
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Chapter 16 Serial Peripheral Interface (SPIV4)
16.1 Introduction
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
16.1.1
Glossary of Terms
SPI SS SCK MOSI MISO MOMI SISO
Serial Peripheral Interface Slave Select Serial Clock Master Output, Slave Input Master Input, Slave Output Master Output, Master Input Slave Input, Slave Output
16.1.2
Features
The SPI includes these distinctive features: • Master mode and slave mode • Bidirectional mode • Slave select output • Mode fault error flag with CPU interrupt capability • Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode
16.1.3
Modes of Operation
The SPI functions in three modes: run, wait, and stop. • Run mode This is the basic mode of operation. • Wait mode
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•
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master.
This is a high level description only, detailed descriptions of operating modes are contained in Section 16.4.7, “Low Power Mode Options”.
16.1.4
Block Diagram
Figure 16-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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Chapter 16 Serial Peripheral Interface (SPIV4)
SPI 2 SPI Control Register 1 BIDIROE 2 SPI Control Register 2 SPC0 SPI Status Register SPIF MODF SPTEF Interrupt Control SPI Interrupt Request Baud Rate Generator Counter Bus Clock Prescaler Clock Select SPPR 3 SPR 3 Shifter SPI Baud Rate Register LSBFE=1 8 SPI Data Register 8 LSBFE=0 MSB LSBFE=0 LSBFE=1 LSBFE=0 LSB LSBFE=1 Data Out Data In Baud Rate Shift Clock Sample Clock Slave Control
CPOL
CPHA
MOSI
Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Master Control
Port Control Logic
SCK
SS
Figure 16-1. SPI Block Diagram
16.2
External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPI module has a total of four external pins.
16.2.1
MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave.
16.2.2
MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master.
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16.2.3
SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave.
16.2.4
SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
16.3
16.3.1
Memory Map and Register Definition
Module Memory Map
This section provides a detailed description of address space and registers used by the SPI.
The memory map for the SPI is given in Figure 16-2. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect.
Register Name SPICR1 R W R W R W R W R W R W R W R W
Bit 7 SPIE 0
6 SPE 0
5 SPTIE 0
4 MSTR
3 CPOL
2 CPHA 0
1 SSOE
Bit 0 LSBFE
SPICR2
MODFEN
BIDIROE 0
SPISWAI
SPC0
SPIBR
0
SPPR2 0
SPPR1 SPTEF
SPPR0 MODF
SPR2 0
SPR1 0
SPR0 0
SPISR
SPIF
0
Reserved
SPIDR
Bit 7
6
5
4
3
2
1
Bit 0
Reserved
Reserved
= Unimplemented or Reserved
Figure 16-2. SPI Register Summary
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Chapter 16 Serial Peripheral Interface (SPIV4)
16.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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16.3.2.1
R W Reset
SPI Control Register 1 (SPICR1)
7 6 5 4 3 2 1 0
SPIE 0
SPE 0
SPTIE 0
MSTR 0
CPOL 0
CPHA 1
SSOE 0
LSBFE 0
Figure 16-3. SPI Control Register 1 (SPICR1)
Read: Anytime Write: Anytime
Table 16-1. SPICR1 Field Descriptions
Field 7 SPIE 6 SPE Description SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock. Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 16-2. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first.
5 SPTIE 4 MSTR
3 CPOL
2 CPHA
1 SSOE 0 LSBFE
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Table 16-2. SS Input / Output Selection
MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode SS not used by SPI SS not used by SPI SS input with MODF feature SS is slave select output Slave Mode SS input SS input SS input SS input
16.3.2.2
R W Reset
SPI Control Register 2 (SPICR2)
7 6 5 4 3 2 1 0
0 0
0 0
0 0
MODFEN 0
BIDIROE 0
0 0
SPISWAI 0
SPC0 0
= Unimplemented or Reserved
Figure 16-4. SPI Control Register 2 (SPICR2)
Read: Anytime Write: Anytime; writes to the reserved bits have no effect
Table 16-3. SPICR2 Field Descriptions
Field 4 MODFEN Description Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration, refer to Table 16-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 SS port pin is not used by the SPI. 1 SS port pin with MODF feature. Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled. 1 Output buffer enabled. SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 16-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
3 BIDIROE
1 SPISWAI 0 SPC0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 621
Chapter 16 Serial Peripheral Interface (SPIV4)
Table 16-4. Bidirectional Pin Configurations
Pin Mode SPC0 BIDIROE MISO MOSI
Master Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Out Slave In Slave I/O Slave In MOSI not used by SPI Master In MISO not used by SPI Master Out Master In Master I/O
16.3.2.3
R W Reset
SPI Baud Rate Register (SPIBR)
7 6 5 4 3 2 1 0
0 0
SPPR2 0
SPPR1 0
SPPR0 0
0 0
SPR2 0
SPR1 0
SPR0 0
= Unimplemented or Reserved
Figure 16-5. SPI Baud Rate Register (SPIBR)
Read: Anytime Write: Anytime; writes to the reserved bits have no effect
Table 16-5. SPIBR Field Descriptions
Field 6–4 SPPR[2:0] 2–0 SPR[2:0] Description SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 16-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 16-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 16-1
The baud rate can be calculated with the following equation:
Baud Rate = BusClock / BaudRateDivisor Eqn. 16-2
NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet.
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Table 16-6. Example SPI Baud Rate Selection (25 MHz Bus Clock)
SPPR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPPR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 SPR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 SPR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Baud Rate Divisor 2 4 8 16 32 64 128 256 4 8 16 32 64 128 256 512 6 12 24 48 96 192 384 768 8 16 32 64 128 256 512 1024 10 20 40 80 160 320 640 Baud Rate 12.5 MHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 4.16667 MHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.13 kHz 39.06 kHz
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Table 16-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued)
SPPR2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Baud Rate Divisor 1280 12 24 48 96 192 384 768 1536 14 28 56 112 224 448 896 1792 16 32 64 128 256 512 1024 2048 Baud Rate 19.53 kHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 16.28 kHz 1.78571 MHz 892.86 kHz 446.43 kHz 223.21 kHz 111.61 kHz 55.80 kHz 27.90 kHz 13.95 kHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 12.21 kHz
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Chapter 16 Serial Peripheral Interface (SPIV4)
16.3.2.4
R W Reset
SPI Status Register (SPISR)
7 6 5 4 3 2 1 0
SPIF 0
0 0
SPTEF 1
MODF 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 16-6. SPI Status Register (SPISR)
Read: Anytime Write: Has no effect
Table 16-7. SPISR Field Descriptions
Field 7 SPIF Description SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 0 Transfer not yet complete. 1 New data copied to SPIDR. SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI data register without reading SPTEF = 1, is effectively ignored. 0 SPI data register not empty. 1 SPI data register empty. Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 16.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred.
5 SPTEF
4 MODF
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16.3.2.5
R W Reset
SPI Data Register (SPIDR)
7 6 5 4 3 2 1 0
Bit 7 0
6 0
5 0
4 0
3 0
2 0
2 0
Bit 0 0
Figure 16-7. SPI Data Register (SPIDR)
Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. If SPIF is cleared and a byte has been received, the received byte is transferred from the receive shift register to the SPIDR and SPIF is set. If SPIF is set and not serviced, and a second byte has been received, the second received byte is kept as valid byte in the receive shift register until the start of another transmission. The byte in the SPIDR does not change. If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 16-8). If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of a third transmission, the byte in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 16-9).
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Data A Received
Data B Received
Data C Received SPIF Serviced
Receive Shift Register
Data A
Data B
Data C
SPIF
SPI Data Register
Data A
Data B
Data C
= Unspecified
= Reception in progress
Figure 16-8. Reception with SPIF Serviced in Time
Data A Received
Data B Received
Data C Received Data B Lost SPIF Serviced
Receive Shift Register
Data A
Data B
Data C
SPIF
SPI Data Register
Data A
Data C
= Unspecified
= Reception in progress
Figure 16-9. Reception with SPIF Serviced too Late
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 627
Chapter 16 Serial Peripheral Interface (SPIV4)
16.4
Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This 8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 16.4.3, “Transmission Formats”). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided.
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Chapter 16 Serial Peripheral Interface (SPIV4)
16.4.1
Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock. • Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. • MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. • SS pin If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 16.4.3, “Transmission Formats”). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state.
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16.4.2
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear. • Serial clock In slave mode, SCK is the SPI clock input from the master. • MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2. • SS pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided.
MC9S12XHZ512 Data Sheet, Rev. 1.03 630 Freescale Semiconductor
Chapter 16 Serial Peripheral Interface (SPIV4)
16.4.3
Transmission Formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention.
MASTER SPI MISO MOSI SCK BAUD RATE GENERATOR SS MISO MOSI SCK SS SLAVE SPI
SHIFT REGISTER
SHIFT REGISTER
VDD
Figure 16-10. Master/Slave Transfer Block Diagram
16.4.3.1
Clock Phase and Polarity Controls
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
16.4.3.2
CPHA = 0 Transfer Format
The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 631
Chapter 16 Serial Peripheral Interface (SPIV4)
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master. • The SPIF flag in the SPI status register is set, indicating that the transfer is complete. Figure 16-11 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
End of Idle State SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) 1 2 Begin 3 4 5 6 Transfer 7 8 9 10 11 12 End 13 14 15 16 Begin of Idle State
CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I)
tL
tT Bit 1 Bit 6
tI
tL
MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode.
LSB Minimum 1/2 SCK for tT, tl, tL MSB
Figure 16-11. SPI Clock Format 0 (CPHA = 0)
MC9S12XHZ512 Data Sheet, Rev. 1.03 632 Freescale Semiconductor
If next transfer begins here
SAMPLE I MOSI/MISO
Chapter 16 Serial Peripheral Interface (SPIV4)
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI data register is not transmitted; instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted. In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time.
16.4.3.3
CPHA = 1 Transfer Format
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th SCK edge: • Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. • The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 16-12 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 633
Chapter 16 Serial Peripheral Interface (SPIV4)
End of Idle State SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) 1 2 3
Begin 4 5 6 7
Transfer 8 9 10 11 12
End 13 14 15 16
Begin of Idle State
CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I)
tL
tT
tI
tL
MSB first (LSBFE = 0): LSB first (LSBFE = 1):
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
Figure 16-12. SPI Clock Format 1 (CPHA = 1)
The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. • Back-to-back transfers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI data register, this byte is sent out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge.
MC9S12XHZ512 Data Sheet, Rev. 1.03 634 Freescale Semiconductor
If next transfer begins here
SAMPLE I MOSI/MISO
Chapter 16 Serial Peripheral Interface (SPIV4)
16.4.4
SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 16-3.
BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 16-3
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 16-6 for baud rate calculations for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet.
16.4.5
16.4.5.1
Special Features
SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 16-2. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 635
Chapter 16 Serial Peripheral Interface (SPIV4)
16.4.5.2
Bidirectional Mode (MOMI or SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 16-8). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.
Table 16-8. Normal Mode and Bidirectional Mode
When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0
Serial Out
MOSI
Serial In SPI
MOSI
Normal Mode SPC0 = 0
SPI Serial In MISO
Serial Out
MISO
Serial Out
MOMI BIDIROE
Serial In BIDIROE SPI Serial Out SISO
Bidirectional Mode SPC0 = 1
SPI Serial In
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. • The SCK is output for the master mode and input for the slave mode. • The SS is the input or output for the master mode, and it is always the input for the slave mode. • The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case MISO becomes occupied by the SPI and MOSI is not used. This must be considered, if the MISO pin is used for another purpose.
MC9S12XHZ512 Data Sheet, Rev. 1.03 636 Freescale Semiconductor
Chapter 16 Serial Peripheral Interface (SPIV4)
16.4.6
Error Conditions
The SPI has one error condition: • Mode fault error
16.4.6.1
Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. NOTE If a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost.
16.4.7
16.4.7.1
Low Power Mode Options
SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 637
Chapter 16 Serial Peripheral Interface (SPIV4)
16.4.7.2
SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.
–
16.4.7.3
SPI in Stop Mode
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit.
MC9S12XHZ512 Data Sheet, Rev. 1.03 638 Freescale Semiconductor
Chapter 16 Serial Peripheral Interface (SPIV4)
16.4.7.4
Reset
The reset values of registers and signals are described in Section 16.3, “Memory Map and Register Definition”, which details the registers and their bit fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. • Reading from the SPIDR after reset will always read a byte of zeros.
16.4.7.5
Interrupts
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request. 16.4.7.5.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 16-2). After MODF is set, the current transfer is aborted and the following bit is changed: • MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”. 16.4.7.5.2 SPIF
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”. 16.4.7.5.3 SPTEF
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 639
Chapter 16 Serial Peripheral Interface (SPIV4)
MC9S12XHZ512 Data Sheet, Rev. 1.03 640 Freescale Semiconductor
Chapter 17 Periodic Interrupt Timer (PIT24B4CV1)
17.1 Introduction
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 17-1 for a simplified block diagram.
17.1.1
Glossary
Acronyms and Abbreviations PIT ISR CCR SoC
Periodic Interrupt Timer Interrupt Service Routine Condition Code Register System on Chip clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit modulus down-counters.
micro time bases
17.1.2
Features
The PIT includes these features: • Four timers implemented as modulus down-counters with independent time-out periods. • Time-out periods selectable between 1 and 224 bus clock cycles. Time-out equals m*n bus clock cycles with 1 $00 $001 (indicates no period) $001 (indicates no period) XX XX
PPOLx 1 0 1 0 1 0
PWMx Output Always low Always high Always high Always low Always high Always low
Counter = $00 and does not count.
18.5
Resets
The reset state of each individual bit is listed within the Section 18.3.2, “Register Descriptions” which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured as an up counter out of reset. • All the channels are disabled and all the counters do not count.
MC9S12XHZ512 Data Sheet, Rev. 1.03 684 Freescale Semiconductor
Chapter 18 Pulse-Width Modulator (PWM8B8CV1)
18.6
Interrupts
The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active. In stop mode or wait mode (with the PSWAI bit set), the emergency shutdown feature will drive the PWM outputs to their shutdown output levels but the PWMIF flag will not be set. A description of the registers involved and affected due to this interrupt is explained in Section 18.3.2.15, “PWM Shutdown Register (PWMSDN)”. The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM interrupt signal.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 685
Chapter 18 Pulse-Width Modulator (PWM8B8CV1)
MC9S12XHZ512 Data Sheet, Rev. 1.03 686 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.1 Introduction
The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module enhanced by additional features in order to enlarge the field of applications, in particular for automotive ABS applications. This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. A full access for the counter registers or the input capture/output compare registers will take place in one clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same result as accessing them in one word.
19.1.1
• • • •
Features
16-bit buffer register for four input capture (IC) channels. Four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered IC channels. Configurable also as two 16-bit pulse accumulators. 16-bit modulus down-counter with 8-bit prescaler. Four user-selectable delay counters for input noise immunity increase.
19.1.2
• • • •
Modes of Operation
Stop — Timer and modulus counter are off since clocks are stopped. Freeze — Timer and modulus counter keep on running, unless the TSFRZ bit in the TSCR1 register is set to one. Wait — Counters keep on running, unless the TSWAI bit in the TSCR1 register is set to one. Normal — Timer and modulus counter keep on running, unless the TEN bit in the TSCR1 register or the MCEN bit in the MCCTL register are cleared.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 687
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.1.3
Block Diagram
Bus Clock Prescaler 16-bit Counter Channel 0 Input Capture Output Compare Channel 1 Input Capture IOC0
Modulus Counter Interrupt Timer Overflow Interrupt Timer Channel 0 Interrupt
16-Bit Modulus Counter
Output Compare Channel 2 Input Capture Output Compare Channel 3 Input Capture Output Compare
IOC1
IOC2
IOC3
Registers
Channel 4 Input Capture Output Compare Channel 5 Input Capture Output Compare
IOC4
IOC5
Timer Channel 7 Interrupt PA Overflow Interrupt PA Input Interrupt PB Overflow Interrupt 16-Bit Pulse Accumulator A 16-Bit Pulse Accumulator B
Channel 6 Input Capture Output Compare Channel 7 Input Capture Output Compare
IOC6
IOC7
Figure 19-1. ECT Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 688 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.2
External Signal Description
The ECT module has a total of eight external pins.
19.2.1
IOC7 — Input Capture and Output Compare Channel 7
This pin serves as input capture or output compare for channel 7.
19.2.2
IOC6 — Input Capture and Output Compare Channel 6
This pin serves as input capture or output compare for channel 6.
19.2.3
IOC5 — Input Capture and Output Compare Channel 5
This pin serves as input capture or output compare for channel 5.
19.2.4
IOC4 — Input Capture and Output Compare Channel 4
This pin serves as input capture or output compare for channel 4.
19.2.5
IOC3 — Input Capture and Output Compare Channel 3
This pin serves as input capture or output compare for channel 3.
19.2.6
IOC2 — Input Capture and Output Compare Channel 2
This pin serves as input capture or output compare for channel 2.
19.2.7
IOC1 — Input Capture and Output Compare Channel 1
This pin serves as input capture or output compare for channel 1.
19.2.8
IOC0 — Input Capture and Output Compare Channel 0
NOTE For the description of interrupts see Section 19.4.3, “Interrupts”.
This pin serves as input capture or output compare for channel 0.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 689
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
19.3.1
Module Memory Map
The memory map for the ECT module is given below in Table 19-1. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the ECT module and the address offset for each register.
Table 19-1. ECT Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D Register Timer Input Capture/Output Compare Select (TIOS) Timer Compare Force Register (CFORC) Output Compare 7 Mask Register (OC7M) Output Compare 7 Data Register (OC7D) Timer Count Register High (TCNT) Timer Count Register Low (TCNT) Timer System Control Register 1 (TSCR1) Timer Toggle Overflow Register (TTOV) Timer Control Register 1 (TCTL1) Timer Control Register 2 (TCTL2) Timer Control Register 3 (TCTL3) Timer Control Register 4 (TCTL4) Timer Interrupt Enable Register (TIE) Timer System Control Register 2 (TSCR2) Main Timer Interrupt Flag 1 (TFLG1) Main Timer Interrupt Flag 2 (TFLG2) Timer Input Capture/Output Compare Register 0 High (TC0) Timer Input Capture/Output Compare Register 0 Low (TC0) Timer Input Capture/Output Compare Register 1 High (TC1) Timer Input Capture/Output Compare Register 1 Low (TC1) Timer Input Capture/Output Compare Register 2 High (TC2) Timer Input Capture/Output Compare Register 2 Low (TC2) Timer Input Capture/Output Compare Register 3 High (TC3) Timer Input Capture/Output Compare Register 3 Low (TC3) Timer Input Capture/Output Compare Register 4 High (TC4) Timer Input Capture/Output Compare Register 4 Low (TC4) Timer Input Capture/Output Compare Register 5 High (TC5) Timer Input Capture/Output Compare Register 5 Low (TC5) Timer Input Capture/Output Compare Register 6 High (TC6) Timer Input Capture/Output Compare Register 6 Low (TC6) Access R/W R/W1 R/W R/W R/W2 R/W2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3
MC9S12XHZ512 Data Sheet, Rev. 1.03 690 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-1. ECT Memory Map (continued)
Address Offset 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F
1 2
Register Timer Input Capture/Output Compare Register 7 High (TC7) Timer Input Capture/Output Compare Register 7 Low (TC7) 16-Bit Pulse Accumulator A Control Register (PACTL) Pulse Accumulator A Flag Register (PAFLG) Pulse Accumulator Count Register 3 (PACN3) Pulse Accumulator Count Register 2 (PACN2) Pulse Accumulator Count Register 1 (PACN1) Pulse Accumulator Count Register 0 (PACN0) 16-Bit Modulus Down Counter Register (MCCTL) 16-Bit Modulus Down Counter Flag Register (MCFLG) Input Control Pulse Accumulator Register (ICPAR) Delay Counter Control Register (DLYCT) Input Control Overwrite Register (ICOVW) Input Control System Control Register (ICSYS) Output Compare Pin Disconnect Register(OCPD) Timer Test Register (TIMTST) Precision Timer Prescaler Select Register (PTPSR) Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) 16-Bit Pulse Accumulator B Control Register (PBCTL) 16-Bit Pulse Accumulator B Flag Register (PBFLG) 8-Bit Pulse Accumulator Holding Register 3 (PA3H) 8-Bit Pulse Accumulator Holding Register 2 (PA2H) 8-Bit Pulse Accumulator Holding Register 1 (PA1H) 8-Bit Pulse Accumulator Holding Register 0 (PA0H) Modulus Down-Counter Count Register High (MCCNT) Modulus Down-Counter Count Register Low (MCCNT) Timer Input Capture Holding Register 0 High (TC0H) Timer Input Capture Holding Register 0 Low (TC0H) Timer Input Capture Holding Register 1 High(TC1H) Timer Input Capture Holding Register 1 Low (TC1H) Timer Input Capture Holding Register 2 High (TC2H) Timer Input Capture Holding Register 2 Low (TC2H) Timer Input Capture Holding Register 3 High (TC3H) Timer Input Capture Holding Register 3 Low (TC3H)
Access R/W3 R/W3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W4 R/W R/W2 R/W R/W R/W R/W R/W5 R/W5 R/W5 R/W5 R/W R/W R/W5 R/W5 R/W5 R/W5 R/W5 R/W5 R/W5 R/W5
Always read 0x0000. Only writable in special modes (test_mode = 1). 3 Writes to these registers have no meaning or effect during input capture. 4 May be written once when not in test00mode but writes are always permitted when test00mode is enabled. 5 Writes have no effect.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 691
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Register Name 0x0000 TIOS 0x0001 CFORC 0x0002 OC7M 0x0003 OC7D R W R W R W R W Bit 7 IOS7 0 FOC7 OC7M7 6 IOS6 0 FOC6 OC7M6 5 IOS5 0 FOC5 OC7M5 4 IOS4 0 FOC4 OC7M4 3 IOS3 0 FOC3 OC7M3 2 IOS2 0 FOC2 OC7M2 1 IOS1 0 FOC1 OC7M1 Bit 0 IOS0 0 FOC0 OC7M0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
0x0004 R TCNT (High) W 0x0005 R TCNT (Low) W 0x0006 TSCR1 0x0007 TTOF 0x0008 TCTL1 0x0009 TCTL2 0x000A TCTL3 0x000B TCTL4 0x000C TIE R W R W R W R W R W R W R W
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2 0
TCNT1 0
TCNT0 0
TEN
TSWAI
TSFRZ
TFFCA
PRNT
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
= Unimplemented or Reserved
Figure 19-2. ECT Register Summary (Sheet 1 of 5)
MC9S12XHZ512 Data Sheet, Rev. 1.03 692 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Register Name 0x000D TSCR2 0x000E TFLG1 0x000F TFLG2 R W R W R W
Bit 7 TOI
6 0
5 0
4 0
3 TCRE
2 PR2
1 PR1
Bit 0 PR0
C7F
C6F 0
C5F 0
C4F 0
C3F 0
C2F 0
C1F 0
C0F 0
TOF
0x0010 R TC0 (High) W 0x0011 TC0 (Low) R W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0012 R TC1 (High) W 0x0013 TC1 (Low) R W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0014 R TC2 (High) W 0x0015 TC2 (Low) R W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0016 R TC3 (High) W 0x0017 TC3 (Low) R W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0018 R TC4 (High) W 0x0019 TC4 (Low) R W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x001A R TC5 (High) W 0x001B TC5 (Low) R W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
= Unimplemented or Reserved
Figure 19-2. ECT Register Summary (Sheet 2 of 5)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 693
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Register Name 0x001C R TC6 (High) W 0x001D TC6 (Low) R W
Bit 7 Bit 15
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
Bit 0 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x001E R TC7 (High) W 0x001F TC7 (Low) 0x0020 PACTL 0x0021 PAFLG 0x0022 PACN3 0x0023 PACN2 0x0024 PACN1 0x0025 PACN0 0x0026 MCCTL 0x0027 MCFLG 0x0028 ICPAR 0x0029 DLYCT 0x002A ICOVW R W R W R W R W R W R W R W R W R W R W R W R W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAEN 0
PAMOD 0
PEDGE 0
CLK1 0
CLK0 0
PA0VI
PAI
0
PA0VF
PAIF
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)
PACNT7
PACNT6
PACNT5
PACNT4 0 ICLAT 0
PACNT3 0 FLMC POLF3
PACNT2
PACNT1
PACNT0
MCZI
MODMC 0
RDMCL 0
MCEN POLF2
MCPR1 POLF1
MCPR0 POLF0
MCZF 0
0
0
0
PA3EN
PA2EN
PA1EN
PA0EN
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
NOVW7
NOVW6
NOVW5
NOVW4
NOVW3
NOVW2
NOVW1
NOVW0
= Unimplemented or Reserved
Figure 19-2. ECT Register Summary (Sheet 3 of 5)
MC9S12XHZ512 Data Sheet, Rev. 1.03 694 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Register Name 0x002B ICSYS 0x002C OCPD 0x002D TIMTST 0x002E PTPSR R W R W R W R W
Bit 7 SH37
6 SH26
5 SH15
4 SH04
3 TFMOD
2 PACMX
1 BUFEN
Bit 0 LATQ
OCPD7
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
Timer Test Register
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
0x002F R PTMCPSR W 0x0030 PBCTL 0x0031 PBFLG 0x0032 PA3H 0x0033 PA2H 0x0034 PA1H 0x0035 PA0H 0x0036 MCCNT (High) 0x0037 MCCNT (Low) R W R W R W R W R W R W R
PTMPS7 0
PTMPS6
PTMPS5 0
PTMPS4 0
PTMPS3 0
PTMPS2 0
PTMPS1
PTMPS0 0
PBEN 0
PBOVI
0
0
0
0
0
PBOVF PA3H1
0
PA3H7
PA3H6
PA3H5
PA3H4
PA3H3
PA3H2
PA3H0
PA2H7
PA2H6
PA2H5
PA2H4
PA2H3
PA2H2
PA2H1
PA2H0
PA1H7
PA1H6
PA1H5
PA1H4
PA1H3
PA1H2
PA1H1
PA1H0
PA0H7
PA0H6
PA0H5
PA0H4
PA0H3
PA0H2
PA0H1
PA0H0
W MCCNT15 R W MCCNT7
MCCNT14
MCCNT13
MCCNT12
MCCNT11
MCCNT10
MCCNT9
MCCNT8
MCCNT6
MCCNT5
MCCNT4
MCCNT3
MCCNT2
MCCNT1
MCCNT9
R 0x0038 TC0H (High) W 0x0039 R TC0H (Low)
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
= Unimplemented or Reserved
Figure 19-2. ECT Register Summary (Sheet 4 of 5)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 695
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Register Name 0x003A R TC1H (High) W 0x003B R TC1H (Low) W 0x003C R TC2H (High) W 0x003D R TC2H (Low) W 0x003E R TC3H (High) W 0x003F R TC3H (Low) W
Bit 7 TC15
6 TC14
5 TC13
4 TC12
3 TC11
2 TC10
1 TC9
Bit 0 TC8
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
= Unimplemented or Reserved
Figure 19-2. ECT Register Summary (Sheet 5 of 5)
19.3.2.1
Timer Input Capture/Output Compare Select Register (TIOS)
Module Base + 0x0000
7 6 5 4 3 2 1 0
R W Reset
IOS7 0
IOS6 0
IOS5 0
IOS4 0
IOS3 0
IOS2 0
IOS1 0
IOS0 0
Figure 19-3. Timer Input Capture/Output Compare Register (TIOS)
Read or write: Anytime All bits reset to zero.
Table 19-2. TIOS Field Descriptions
Field 7:0 IOS[7:0] Description Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture. 1 The corresponding channel acts as an output compare.
MC9S12XHZ512 Data Sheet, Rev. 1.03 696 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.2
Timer Compare Force Register (CFORC)
Module Base + 0x0001
7 6 5 4 3 2 1 0
R W Reset
0 FOC7 0
0 FOC6 0
0 FOC5 0
0 FOC4 0
0 FOC3 0
0 FOC2 0
0 FOC1 0
0 FOC0 0
Figure 19-4. Timer Compare Force Register (CFORC)
Read or write: Anytime but reads will always return 0x0000 (1 state is transient). All bits reset to zero.
Table 19-3. CFORC Field Descriptions
Field 7:0 FOC[7:0] Description Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. Note: A successful channel 7 output compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the same time as the successful output compare, then the forced output compare action will take precedence and the interrupt flag will not get set.
19.3.2.3
Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
7 6 5 4 3 2 1 0
R W Reset
OC7M7 0
OC7M6 0
OC7M5 0
OC7M4 0
OC7M3 0
OC7M2 0
OC7M1 0
OC7M0 0
Figure 19-5. Output Compare 7 Mask Register (OC7M)
Read or write: Anytime All bits reset to zero.
Table 19-4. OC7M Field Descriptions
Field 7:0 OC7M[7:0] Description Output Compare Mask Action for Channel 7:0 0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on a successful channel 7 output compare, even if the corresponding pin is setup for output compare. 1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a successful channel 7 output compare. Note: The corresponding channel must also be setup for output compare (IOSx = 1) for data to be transferred from the output compare 7 data register to the timer port.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 697
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.4
Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
7 6 5 4 3 2 1 0
R W Reset
OC7D7 0
OC7D6 0
OC7D5 0
OC7D4 0
OC7D3 0
OC7D2 0
OC7D1 0
OC7D0 0
Figure 19-6. Output Compare 7 Data Register (OC7D)
Read or write: Anytime All bits reset to zero.
Table 19-5. OC7D Field Descriptions
Field 7:0 OC7D[7:0] Description Output Compare 7 Data Bits — A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register.
MC9S12XHZ512 Data Sheet, Rev. 1.03 698 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.5
Timer Count Register (TCNT)
Module Base + 0x0004
15 14 13 12 11 10 9 8
R W Reset
TCNT15 0
TCNT14 0
TCNT13 0
TCNT12 0
TCNT11 0
TCNT10 0
TCNT9 0
TCNT8 0
Figure 19-7. Timer Count Register High (TCNT)
Module Base + 0x0005
7 6 5 4 3 2 1 0
R W Reset
TCNT7 0
TCNT6 0
TCNT5 0
TCNT4 0
TCNT3 0
TCNT2 0
TCNT1 0
TCNT0 0
Figure 19-8. Timer Count Register Low (TCNT)
Read: Anytime Write: Has no meaning or effect All bits reset to zero.
Table 19-6. TCNT Field Descriptions
Field Description
15:0 Timer Counter Bits — The 16-bit main timer is an up counter. A read to this register will return the current value TCNT[15:0] of the counter. Access to the counter register will take place in one clock cycle. Note: A separate read/write for high byte and low byte in test mode will give a different result than accessing them as a word. The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 699
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.6
Timer System Control Register 1 (TSCR1)
Module Base + 0x0006
7 6 5 4 3 2 1 0
R W Reset
TEN 0
TSWAI 0
TSFRZ 0
TFFCA 0
PRNT 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 19-9. Timer System Control Register 1 (TSCR1)
Read or write: Anytime except PRNT bit is write once All bits reset to zero.
Table 19-7. TSCR1 Field Descriptions
Field 7 TEN Description Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. Note: If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is generated by the timer prescaler. Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode. Timer interrupts cannot be used to get the MCU out of wait. Timer and Modulus Counter Stop While in Freeze Mode 0 Allows the timer and modulus counter to continue running while in freeze mode. 1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation. The pulse accumulators do not stop in freeze mode. Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 A read from an input capture or a write to the output compare channel registers causes the corresponding channel flag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF flag in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. Any access to the MCCNT register clears the MCZF flag in the MCFLG register. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. Note: The flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag) when TFFCA = 1. Precision Timer 0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection. 1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits of PTMCPSR register are used for the prescaler Precision Timer Modulus Counter Prescaler selection.
6 TSWAI
5 TSFRZ
4 TFFCA
3 PRNT
MC9S12XHZ512 Data Sheet, Rev. 1.03 700 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.7
Timer Toggle On Overflow Register 1 (TTOV)
Module Base + 0x0007
7 6 5 4 3 2 1 0
R W Reset
TOV7 0
TOV6 0
TOV5 0
TOV4 0
TOV3 0
TOV2 0
TOV1 0
TOV0 0
Figure 19-10. Timer Toggle On Overflow Register 1 (TTOV)
Read or write: Anytime All bits reset to zero.
Table 19-8. TTOV Field Descriptions
Field 7:0 TOV[7:0] Description Toggle On Overflow Bits — TOV97:0] toggles output compare pin on timer counter overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 701
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.8
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Module Base + 0x0008
7 6 5 4 3 2 1 0
R W Reset
OM7 0
OL7 0
OM6 0
OL6 0
OM5 0
OL5 0
OM4 0
OL4 0
Figure 19-11. Timer Control Register 1 (TCTL1)
Module Base + 0x0009
7 6 5 4 3 2 1 0
R W Reset
OM3 0
OL3 0
OM2 0
OL2 0
OM1 0
OL1 0
OM0 0
OL0 0
Figure 19-12. Timer Control Register 2 (TCTL2)
Read or write: Anytime All bits reset to zero.
Table 19-9. TCTL1/TCTL2 Field Descriptions
Field OM[7:0] 7, 5, 3, 1 OL[7:0] 6, 4, 2, 0 Description OMx — Output Mode OLx — Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx. See Table 19-10.
Table 19-10. Compare Result Output Action
OMx 0 0 1 1 OLx 0 1 0 1 Action No output compare action on the timer output signal Toggle OCx output line Clear OCx output line to zero Set OCx output line to one
NOTE To enable output action by OMx and OLx bits on timer port, the corresponding bit in OC7M should be cleared.
MC9S12XHZ512 Data Sheet, Rev. 1.03 702 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.9
Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Module Base + 0x000A
7 6 5 4 3 2 1 0
R W Reset
EDG7B 0
EDG7A 0
EDG6B 0
EDG6A 0
EDG5B 0
EDG5A 0
EDG4B 0
EDG4A 0
Figure 19-13. Timer Control Register 3 (TCTL3)
Module Base + 0x000B
7 6 5 4 3 2 1 0
R W Reset
EDG3B 0
EDG3A 0
EDG2B 0
EDG2A 0
EDG1B 0
EDG1A 0
EDG0B 0
EDG0A 0
Figure 19-14. Timer Control Register 4 (TCTL4)
Read or write: Anytime All bits reset to zero.
Table 19-11. TCTL3/TCTL4 Field Descriptions
Field EDG[7:0]B 7, 5, 3, 1 EDG[7:0]A 6, 4, 2, 0 Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the active edge for the 16-bit pulse accumulator PACB. See Table 19-12.
Table 19-12. Edge Detector Circuit Configuration
EDGxB 0 0 1 1 EDGxA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 703
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7 6 5 4 3 2 1 0
R W Reset
C7I 0
C6I 0
C5I 0
C4I 0
C3I 0
C2I 0
C1I 0
C0I 0
Figure 19-15. Timer Interrupt Enable Register (TIE)
Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register.
Table 19-13. TIE Field Descriptions
Field 7:0 C[7:0]I Description Input Capture/Output Compare “x” Interrupt Enable 0 The corresponding flag is disabled from causing a hardware interrupt. 1 The corresponding flag is enabled to cause an interrupt.
MC9S12XHZ512 Data Sheet, Rev. 1.03 704 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7 6 5 4 3 2 1 0
R W Reset
TOI 0
0 0
0 0
0 0
TCRE 0
PR2 0
PR1 0
PR0 0
= Unimplemented or Reserved
Figure 19-16. Timer System Control Register 2 (TSCR2)
Read or write: Anytime All bits reset to zero.
Table 19-14. TSCR2 Field Descriptions
Field 7 TOI 3 TCRE Description Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled. 1 Hardware interrupt requested when TOF flag set. Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output compare. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset disabled and counter free runs. 1 Counter reset by a successful output compare on channel 7. Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000. Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. See Table 19-15.
2:0 PR[2:0]
Table 19-15. Prescaler Selection
PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Prescale Factor 1 2 4 8 16 32 64 128
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 705
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7 6 5 4 3 2 1 0
R W Reset
C7F 0
C6F 0
C5F 0
C4F 0
C3F 0
C2F 0
C1F 0
C0F 0
Figure 19-17. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”). Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a timer interrupt to be generated after capturing two values in the capture and holding registers, instead of generating an interrupt for every capture.
Table 19-16. TFLG1 Field Descriptions
Field 7:0 C[7:0]F Description Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be set by 8-bit pulse accumulators PAC3–PAC0. If the delay counter is enabled, the CxF flag will not be set until after the delay.
MC9S12XHZ512 Data Sheet, Rev. 1.03 706 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7 6 5 4 3 2 1 0
R W Reset
TOF 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 19-18. Main Timer Interrupt Flag 2 (TFLG2)
Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 19-17. TFLG2 Field Descriptions
Field 7 TOF Description Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 707
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.14 Timer Input Capture/Output Compare Registers 0–7
Module Base + 0x0010
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-19. Timer Input Capture/Output Compare Register 0 High (TC0)
Module Base + 0x0011
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-20. Timer Input Capture/Output Compare Register 0 Low (TC0)
Module Base + 0x0012
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-21. Timer Input Capture/Output Compare Register 1 High (TC1)
Module Base + 0x0013
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-22. Timer Input Capture/Output Compare Register 1 Low (TC1)
Module Base + 0x0014
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-23. Timer Input Capture/Output Compare Register 2 High (TC2)
Module Base + 0x0015
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-24. Timer Input Capture/Output Compare Register 2 Low (TC2)
MC9S12XHZ512 Data Sheet, Rev. 1.03 708 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x0016
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-25. Timer Input Capture/Output Compare Register 3 High (TC3)
Module Base + 0x0017
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-26. Timer Input Capture/Output Compare Register 3 Low (TC3)
Module Base + 0x0018
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-27. Timer Input Capture/Output Compare Register 4 High (TC4)
Module Base + 0x0019
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-28. Timer Input Capture/Output Compare Register 4 Low (TC4)
Module Base + 0x001A
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-29. Timer Input Capture/Output Compare Register 5 High (TC5)
Module Base + 0x001B
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-30. Timer Input Capture/Output Compare Register 5 Low (TC5)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 709
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x001C
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-31. Timer Input Capture/Output Compare Register 6 High (TC6)
Module Base + 0x001D
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-32. Timer Input Capture/Output Compare Register 6 Low (TC6)
Module Base + 0x001E
15 14 13 12 11 10 9 8
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 19-33. Timer Input Capture/Output Compare Register 7 High (TC7)
Module Base + 0x001F
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 19-34. Timer Input Capture/Output Compare Register 7 Low (TC7)
Read: Anytime Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All bits reset to zero. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare.
MC9S12XHZ512 Data Sheet, Rev. 1.03 710 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)
Module Base + 0x0020
7 6 5 4 3 2 1 0
R W Reset
0 0
PAEN 0
PAMOD 0
PEDGE 0
CLK1 0
CLK0 0
PAOVI 0
PAI 0
= Unimplemented or Reserved
Figure 19-35. 16-Bit Pulse Accumulator Control Register (PACTL)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-18. PACTL Field Descriptions
Field 6 PAEN Description Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled. 1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect. Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7. Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). 0 Event counter mode 1 Gated time accumulation mode Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). Refer to Table 19-19. For PAMOD bit = 0 (event counter mode). 0 Falling edges on PT7 pin cause the count to be incremented 1 Rising edges on PT7 pin cause the count to be incremented For PAMOD bit = 1 (gated time accumulation mode). 0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7 sets the PAIF flag. 1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7 sets the PAIF flag. If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the timer prescaler. 3:2 CLK[1:0] Clock Select Bits — For the description of PACLK please refer to Figure 19-71. If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. Refer to Table 19-20. Pulse Accumulator A Overflow Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PAOVF is set
5 PAMOD 4 PEDGE
2 PAOVI
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 711
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-18. PACTL Field Descriptions (continued)
Field 0 PAI Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PAIF is set Description
.
Table 19-19. Pin Action
PAMOD 0 0 1 1 PEDGE 0 1 0 1 Falling edge Rising edge Divide by 64 clock enabled with pin high level Divide by 64 clock enabled with pin low level Pin Action
Table 19-20. Clock Selection
CLK1 0 0 1 1 CLK0 0 1 0 1 Clock Source Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency
19.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Module Base + 0x0021
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
PAOVF 0
PAIF 0
= Unimplemented or Reserved
Figure 19-36. Pulse Accumulator A Flag Register (PAFLG)
Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero.
MC9S12XHZ512 Data Sheet, Rev. 1.03 712 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 19-21. PAFLG Field Descriptions
Field 1 PAOVF Description Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to 0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000. When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by an active edge on PT3. 0 PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF.
19.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)
Module Base + 0x0022
7 6 5 4 3 2 1 0
R W Reset
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) 0 0 0 0 0 0
PACNT1(9) 0
PACNT0(8) 0
Figure 19-37. Pulse Accumulators Count Register 3 (PACN3)
Module Base + 0x0023
7 6 5 4 3 2 1 0
R W Reset
PACNT7 0
PACNT6 0
PACNT5 0
PACNT4 0
PACNT3 0
PACNT2 0
PACNT1 0
PACNT0 0
Figure 19-38. Pulse Accumulators Count Register 2 (PACN2)
Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set. Full count register access will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give a different result than accessing them as a word.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 713
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented.
19.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)
Module Base + 0x0024
7 6 5 4 3 2 1 0
R W Reset
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) 0 0 0 0 0 0
PACNT1(9) 0
PACNT0(8) 0
Figure 19-39. Pulse Accumulators Count Register 1 (PACN1)
Module Base + 0x0025
7 6 5 4 3 2 1 0
R W Reset
PACNT7 0
PACNT6 0
PACNT5 0
PACNT4 0
PACNT3 0
PACNT2 0
PACNT1 0
PACNT0 0
Figure 19-40. Pulse Accumulators Count Register 0 (PACN0)
Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. When PACN1 overflows from 0x00FF to 0x0000, the interrupt flag PBOVF in PBFLG is set. Full count register access will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give a different result than accessing them as a word. When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented.
MC9S12XHZ512 Data Sheet, Rev. 1.03 714 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL)
Module Base + 0x0026
7 6 5 4 3 2 1 0
R W Reset
MCZI 0
MODMC 0
RDMCL 0
0 ICLAT 0
0 FLMC 0
MCEN 0
MCPR1 0
MCPR0 0
Figure 19-41. 16-Bit Modulus Down-Counter Control Register (MCCTL)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-22. MCCTL Field Descriptions
Field 7 MCZI 6 MODMC Modulus Counter Underflow Interrupt Enable 0 Modulus counter interrupt is disabled. 1 Modulus counter interrupt is enabled. Modulus Mode Enable 0 The modulus counter counts down from the value written to it and will stop at 0x0000. 1 Modulus mode is enabled. When the modulus counter reaches 0x0000, the counter is loaded with the latest value written to the modulus count register. Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to 0xFFFF. Read Modulus Down-Counter Load 0 Reads of the modulus count register (MCCNT) will return the present value of the count register. 1 Reads of the modulus count register (MCCNT) will return the contents of the load register. Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3 and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse accumulators will be automatically cleared when the latch action occurs. Writing zero to this bit has no effect. Read of this bit will always return zero. 3 FLMC Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus down-counter is enabled (MCEN = 1). A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets the modulus counter prescaler. Write zero to this bit has no effect. Read of this bit will return always zero. 2 MCEN Modulus Down-Counter Enable 0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. 1 Modulus counter is enabled. Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. Description
5 RDMCL 4 ICLAT
1:0 MCPR[1:0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 715
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-23. Modulus Counter Prescaler Select
MCPR1 0 0 1 1 MCPR0 0 1 0 1 Prescaler Division 1 4 8 16
19.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Module Base + 0x0027
7 6 5 4 3 2 1 0
R W Reset
MCZF 0
0 0
0 0
0 0
POLF3 0
POLF2 0
POLF1 0
POLF0 0
= Unimplemented or Reserved
Figure 19-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero.
Table 19-24. MCFLG Field Descriptions
Field 7 MCZF Description Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000. The flag indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”). First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect. Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read. Each POLFx corresponds to a timer PORTx input. 0 The first input capture has been caused by a falling edge. 1 The first input capture has been caused by a rising edge.
3:0 POLF[3:0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 716 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR)
Module Base + 0x0028
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
PA3EN 0
PA2EN 0
PA1EN 0
PA0EN 0
= Unimplemented or Reserved
Figure 19-43. Input Control Pulse Accumulators Register (ICPAR)
Read: Anytime Write: Anytime. All bits reset to zero. The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN is set, PA3EN and PA2EN have no effect. The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN is set, PA1EN and PA0EN have no effect.
Table 19-25. ICPAR Field Descriptions
Field 3:0 PA[3:0]EN 8-Bit Pulse Accumulator ‘x’ Enable 0 8-Bit Pulse Accumulator is disabled. 1 8-Bit Pulse Accumulator is enabled. Description
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 717
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.22 Delay Counter Control Register (DLYCT)
Module Base + 0x0029
7 6 5 4 3 2 1 0
R W Reset
DLY7 0
DLY6 0
DLY5 0
DLY4 0
DLY3 0
DLY2 0
DLY1 0
DLY0 0
Figure 19-44. Delay Counter Control Register (DLYCT)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-26. DLYCT Field Descriptions
Field 7:0 DLY[7:0] Description Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to calculate the delay.Table 19-27 shows the delay settings in this case. When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay. Table 19-28 shows the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to narrow input pulses. Delay between two active edges of the input signal period should be longer than the selected counter delay. Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register TSCR1.
Table 19-27. Delay Counter Select when PRNT = 0
DLY1 0 0 1 1 DLY0 0 1 0 1 Delay Disabled 256 bus clock cycles 512 bus clock cycles 1024 bus clock cycles
Table 19-28. Delay Counter Select Examples when PRNT = 1
DLY7 0 0 0 0 0 0 0 0 0 0 0 0 DLY6 0 0 0 0 0 0 0 0 0 0 0 1 DLY5 0 0 0 0 0 0 0 0 0 0 1 1 DLY4 0 0 0 0 0 0 0 0 0 1 1 1 DLY3 0 0 0 0 0 0 0 0 1 1 1 1 DLY2 0 0 0 0 1 1 1 1 1 1 1 1 DLY1 0 0 1 1 0 0 1 1 1 1 1 1 DLY0 0 1 0 1 0 1 0 1 1 1 1 1 Delay Disabled (bypassed) 8 bus clock cycles 12 bus clock cycles 16 bus clock cycles 20 bus clock cycles 24 bus clock cycles 28 bus clock cycles 32 bus clock cycles 64 bus clock cycles 128 bus clock cycles 256 bus clock cycles 512 bus clock cycles
MC9S12XHZ512 Data Sheet, Rev. 1.03 718 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-28. Delay Counter Select Examples when PRNT = 1
DLY7 1 DLY6 1 DLY5 1 DLY4 1 DLY3 1 DLY2 1 DLY1 1 DLY0 1 Delay 1024 bus clock cycles
19.3.2.23 Input Control Overwrite Register (ICOVW)
Module Base + 0x002A
7 6 5 4 3 2 1 0
R W Reset
NOVW7 0
NOVW6 0
NOVW5 0
NOVW4 0
NOVW3 0
NOVW2 0
NOVW1 0
NOVW0 0
Figure 19-45. Input Control Overwrite Register (ICOVW)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-29. ICOVW Field Descriptions
Field 7:0 NOVW[7:0] Description No Input Capture Overwrite 0 The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. 1 The related capture register or holding register cannot be written by an event unless they are empty (see Section 19.4.1.1, “IC Channels”). This will prevent the captured value being overwritten until it is read or latched in the holding register.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 719
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.24 Input Control System Control Register (ICSYS)
Module Base + 0x002B
7 6 5 4 3 2 1 0
R W Reset
SH37 0
SH26 0
SH15 0
SH04 0
TFMOD 0
PACMX 0
BUFEN 0
LATQ 0
Figure 19-46. Input Control System Register (ICSYS)
Read: Anytime Write: Once in normal modes All bits reset to zero.
Table 19-30. ICSYS Field Descriptions
Field 7:4 SHxy Description Share Input action of Input Capture Channels x and y 0 Normal operation 1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge detector is used to be active on the channel ‘y’. Timer Flag Setting Mode — Use of the TFMOD bit in conjunction with the use of the ICOVW register allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. By setting TFMOD in queue mode, when NOVWx bit is set and the corresponding capture and holding registers are emptied, an input capture event will first update the related input capture register with the main timer contents. At the next event, the TCx data is transferred to the TCxH register, the TCx is updated and the CxF interrupt flag is set. In all other input capture cases the interrupt flag is set by a valid external event on PTx. 0 The timer flags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin occurs. 1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F–C0F in TFLG1 are set only when a latch on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F–C0F are set the same way as for TFMOD = 0. 8-Bit Pulse Accumulators Maximum Count 0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge, it will be incremented to 0x0000. 1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value 0x00FF indicates a count of 255 or more. IC Buffer Enable 0 Input capture and pulse accumulator holding registers are disabled. 1 Input capture and pulse accumulator holding registers are enabled. The latching mode is defined by LATQ control bit.
3 TFMOD
2 PACMX
1 BUFFEN
MC9S12XHZ512 Data Sheet, Rev. 1.03 720 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-30. ICSYS Field Descriptions (continued)
Field 0 LATQ Description Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled. Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and pulse accumulators registers into their holding registers. 0 Queue mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. 1 Latch mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is written into the count register MCCNT (see Section 19.4.1.1.2, “Buffered IC Channels”). With a latching event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse accumulators are cleared.
19.3.2.25 Output Compare Pin Disconnect Register (OCPD)
Module Base + 0x002C
7 6 5 4 3 2 1 0
R W Reset
OCPD7 0
OCPD6 0
OCPD5 0
OCPD4 0
OCPD3 0
OCPD2 0
OCPD1 0
OCPD0 0
Figure 19-47. Output Compare Pin Disconnect Register (OCPD)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-31. OCPD Field Descriptions
Field 7:0 OCPD[7:0] Description Output Compare Pin Disconnect Bits 0 Enables the timer channel IO port. Output Compare actions will occur on the channel pin. These bits do not affect the input capture or pulse accumulator functions. 1 Disables the timer channel IO port. Output Compare actions will not affect on the channel pin; the output
compare flag will still be set on an Output Compare event.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 721
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.26 Precision Timer Prescaler Select Register (PTPSR)
Module Base + 0x002E
7 6 5 4 3 2 1 0
R W Reset
PTPS7 0
PTPS6 0
PTPS5 0
PTPS4 0
PTPS3 0
PTPS2 0
PTPS1 0
PTPS0 0
Figure 19-48. Precision Timer Prescaler Select Register (PTPSR)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-32. PTPSR Field Descriptions
Field 7:0 PTPS[7:0] Description Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 19-33 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
Table 19-33. Precision Timer Prescaler Selection Examples when PRNT = 1
PTPS7 0 0 0 0 0 0 0 0 0 0 0 0 1 PTPS6 0 0 0 0 0 0 0 0 0 0 0 1 1 PTPS5 0 0 0 0 0 0 0 0 0 0 1 1 1 PTPS4 0 0 0 0 0 0 0 0 0 1 1 1 1 PTPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 PTPS2 0 0 0 0 1 1 1 1 1 1 1 1 1 PTPS1 0 0 1 1 0 0 1 1 1 1 1 1 1 PTPS0 0 1 0 1 0 1 0 1 1 1 1 1 1 Prescale Factor 1 2 3 4 5 6 7 8 16 32 64 128 256
MC9S12XHZ512 Data Sheet, Rev. 1.03 722 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.27 Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)
Module Base + 0x002F
7 6 5 4 3 2 1 0
R W Reset
PTMPS7 0
PTMPS6 0
PTMPS5 0
PTMPS4 0
PTMPS3 0
PTMPS2 0
PTMPS1 0
PTMPS0 0
Figure 19-49. Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-34. PTMCPSR Field Descriptions
Field Description
7:0 Precision Timer Modulus Counter Prescaler Select Bits — These eight bits specify the division rate of the PTMPS[7:0] modulus counter prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 19-35 shows some possible division rates. The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs.
Table 19-35. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1
PTMPS7 0 0 0 0 0 0 0 0 0 0 0 0 1 PTMPS6 0 0 0 0 0 0 0 0 0 0 0 1 1 PTMPS5 0 0 0 0 0 0 0 0 0 0 1 1 1 PTMPS4 0 0 0 0 0 0 0 0 0 1 1 1 1 PTMPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 PTMPS2 0 0 0 0 1 1 1 1 1 1 1 1 1 PTMPS1 0 0 1 1 0 0 1 1 1 1 1 1 1 PTMPS0 0 1 0 1 0 1 0 1 1 1 1 1 1 Prescaler Division Rate 1 2 3 4 5 6 7 8 16 32 64 128 256
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 723
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.28 16-Bit Pulse Accumulator B Control Register (PBCTL)
Module Base + 0x0030
7 6 5 4 3 2 1 0
R W Reset
0 0
PBEN 0
0 0
0 0
0 0
0 0
PBOVI 0
0 0
= Unimplemented or Reserved
Figure 19-50. 16-Bit Pulse Accumulator B Control Register (PBCTL)
Read: Anytime Write: Anytime All bits reset to zero.
Table 19-36. PBCTL Field Descriptions
Field 6 PBEN Description Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits in ICPAR are set. 1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. PA1EN and PA0EN control bits in ICPAR have no effect. The PACB shares the input pin with IC0. Pulse Accumulator B Overflow Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PBOVF is set
1 PBOVI
MC9S12XHZ512 Data Sheet, Rev. 1.03 724 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.29 Pulse Accumulator B Flag Register (PBFLG)
Module Base + 0x0031
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
PBOVF 0
0 0
= Unimplemented or Reserved
Figure 19-51. Pulse Accumulator B Flag Register (PBFLG)
Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. PBFLG indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 19-37. PBFLG Field Descriptions
Field 1 PBOVF Description Pulse Accumulator B Overflow Flag — This bit is set when the 16-bit pulse accumulator B overflows from 0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000. When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active edge follows on PT1.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 725
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.30 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H)
Module Base + 0x0032
7 6 5 4 3 2 1 0
R W Reset
PA3H7 0
PA3H6 0
PA3H5 0
PA3H4 0
PA3H3 0
PA3H2 0
PA3H1 0
PA3H0 0
= Unimplemented or Reserved
Figure 19-52. 8-Bit Pulse Accumulators Holding Register 3 (PA3H)
Module Base + 0x0033
7 6 5 4 3 2 1 0
R W Reset
PA2H7 0
PA2H6 0
PA2H5 0
PA2H4 0
PA2H3 0
PA2H2 0
PA2H1 0
PA2H0 0
= Unimplemented or Reserved
Figure 19-53. 8-Bit Pulse Accumulators Holding Register 2 (PA2H)
Module Base + 0x0034
7 6 5 4 3 2 1 0
R W Reset
PA1H7 0
PA1H6 0
PA1H5 0
PA1H4 0
PA1H3 0
PA1H2 0
PA1H1 0
PA1H0 0
= Unimplemented or Reserved
Figure 19-54. 8-Bit Pulse Accumulators Holding Register 1 (PA1H)
Module Base + 0x0035
7 6 5 4 3 2 1 0
R W Reset
PA0H7 0
PA0H6 0
PA0H5 0
PA0H4 0
PA0H3 0
PA0H2 0
PA0H1 0
PA0H0 0
= Unimplemented or Reserved
Figure 19-55. 8-Bit Pulse Accumulators Holding Register 0 (PA0H)
Read: Anytime. Write: Has no effect. All bits reset to zero. These registers are used to latch the value of the corresponding pulse accumulator when the related bits in register ICPAR are enabled (see Section 19.4.1.3, “Pulse Accumulators”).
MC9S12XHZ512 Data Sheet, Rev. 1.03 726 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.31 Modulus Down-Counter Count Register (MCCNT)
Module Base + 0x0036
15 14 13 12 11 10 9 8
R W Reset
MCCNT15 1
MCCNT14 1
MCCNT13 1
MCCNT12 1
MCCNT11 1
MCCNT10 1
MCCNT9 1
MCCNT8 1
Figure 19-56. Modulus Down-Counter Count Register High (MCCNT)
Module Base + 0x0037
7 6 5 4 3 2 1 0
R W Reset
MCCNT7 1
MCCNT6 1
MCCNT5 1
MCCNT4 1
MCCNT3 1
MCCNT2 1
MCCNT1 1
MCCNT9 1
Figure 19-57. Modulus Down-Counter Count Register Low (MCCNT)
Read: Anytime Write: Anytime. All bits reset to one. A full access for the counter register will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give different results than accessing them as a word. If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load register. If a 0x0000 is written into MCCNT when LATQ and BUFEN in ICSYS register are set, the input capture and pulse accumulator registers will be latched. With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag in MCFLG register. If the modulus down counter is enabled (MCEN = 1) and modulus mode is enabled (MODMC = 1), a write to MCCNT will update the load register with the value written to it. The count register will not be updated with the new value until the next counter underflow. If modulus mode is not enabled (MODMC = 0), a write to MCCNT will clear the modulus prescaler and will immediately update the counter register with the value written to it and down-counts to 0x0000 and stops. The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an immediate load is desired.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 727
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.32 Timer Input Capture Holding Registers 0–3 (TCxH)
Module Base + 0x0038
15 14 13 12 11 10 9 8
R W Reset
TC15 0
TC14 0
TC13 0
TC12 0
TC11 0
TC10 0
TC9 0
TC8 0
= Unimplemented or Reserved
Figure 19-58. Timer Input Capture Holding Register 0 High (TC0H)
Module Base + 0x0039
7 6 5 4 3 2 1 0
R W Reset
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 19-59. Timer Input Capture Holding Register 0 Low (TC0H)
Module Base + 0x003A
15 14 13 12 11 10 9 8
R W Reset
TC15 0
TC14 0
TC13 0
TC12 0
TC11 0
TC10 0
TC9 0
TC8 0
= Unimplemented or Reserved
Figure 19-60. Timer Input Capture Holding Register 1 High (TC1H)
Module Base + 0x003B
7 6 5 4 3 2 1 0
R W Reset
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 19-61. Timer Input Capture Holding Register 1 Low (TC1H)
Module Base + 0x003C
15 14 13 12 11 10 9 8
R W Reset
TC15 0
TC14 0
TC13 0
TC12 0
TC11 0
TC10 0
TC9 0
TC8 0
= Unimplemented or Reserved
Figure 19-62. Timer Input Capture Holding Register 2 High (TC2H)
MC9S12XHZ512 Data Sheet, Rev. 1.03 728 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x003D
7 6 5 4 3 2 1 0
R W Reset
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 19-63. Timer Input Capture Holding Register 2 Low (TC2H)
Module Base + 0x003E
15 14 13 12 11 10 9 8
R W Reset
TC15 0
TC14 0
TC13 0
TC12 0
TC11 0
TC10 0
TC9 0
TC8 0
= Unimplemented or Reserved
Figure 19-64. Timer Input Capture Holding Register 3 High (TC3H)
Module Base + 0x003F
7 6 5 4 3 2 1 0
R W Reset
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 19-65. Timer Input Capture Holding Register 3 Low (TC3H)
Read: Anytime Write: Has no effect. All bits reset to zero. These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding IOSx bits in TIOS should be cleared (see Section 19.4.1.1, “IC Channels”).
19.4
Functional Description
This section provides a complete functional description of the ECT block, detailing the operation of the design from the end user perspective in a number of subsections.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 729
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
÷ 1, 2, ..., 128 Bus Clock Timer Prescaler
16-Bit Free-Running 16 BIT MAIN TIMER Main Timer Bus Clock
÷ 1, 4, 8, 16 Modulus Prescaler
16-Bit Load Register 16-Bit Modulus Down Counter 0 RESET Underflow RESET RESET RESET LATCH
P0
Pin Logic
Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0
TC0H Hold Reg.
PA0H Hold Reg. 0
P1
Pin Logic
Comparator Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1
TC1H Hold Reg.
PA1H Hold Reg. 0
P2
Pin Logic
Comparator Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2
TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg.
PA2H Hold Reg. 0
P3
Pin Logic
PAC3
TC3H Hold Reg.
PA3H Hold Reg.
P4
Pin Logic
Comparator EDG4 EDG0 SH04 Comparator EDG5 EDG1 SH15 Comparator EDG6 EDG2 SH26 Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. MUX TC6 Capture/Compare Reg. MUX TC5 Capture/Compare Reg. Write 0x0000 to Modulus Counter MUX TC4 Capture/Compare Reg. ICLAT, LATQ, BUFEN (Force Latch)
P5
Pin Logic
P6
Pin Logic
LATQ (MDC Latch Enable)
P7
Pin Logic
Figure 19-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 730 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
÷ 1, 2,3, ..., 256 Bus Clock Timer Prescaler
16-Bit Free-Running 16 BITMain Timer MAIN TIMER Bus Clock
÷ 1, 2,3, ..., 256 Modulus Prescaler
16-Bit Load Register 16-Bit Modulus Down Counter 0 RESET Underflow RESET RESET RESET LATCH
P0
Pin Logic
Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0
8, 12, 16, ..., 1024 TC0H Hold Reg. PA0H Hold Reg. 0 P1 Pin Logic Comparator Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1
8, 12, 16, ..., 1024 TC1H Hold Reg. PA1H Hold Reg. 0 P2 Pin Logic Comparator Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2
8, 12, 16, ..., 1024 TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg. PAC3 PA2H Hold Reg. 0 P3 Pin Logic
8, 12, 16, ..., 1024 TC3H Hold Reg. PA3H Hold Reg.
P4
Pin Logic
Comparator EDG4 EDG0 SH04 Comparator EDG5 EDG1 SH15 Comparator EDG6 EDG2 SH26 Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. MUX TC6 Capture/Compare Reg. MUX TC5 Capture/Compare Reg. Write 0x0000 to Modulus Counter MUX TC4 Capture/Compare Reg. ICLAT, LATQ, BUFEN (Force Latch)
P5
Pin Logic
P6
Pin Logic
LATQ (MDC Latch Enable)
P7
Pin Logic
Figure 19-67. Detailed Timer Block Diagram in Latch Mode when PRNT = 1
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 731
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Bus Clock
÷1, 2, ..., 128 Timer Prescaler
16-Bit Free-Running 16 BIT MAIN TIMER Main Timer Bus Clock
÷ 1, 4, 8, 16 Modulus Prescaler
16-Bit Load Register 16-Bit Modulus Down Counter 0 RESET
P0
Pin Logic
Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 LATCH0 LATCH3 LATCH2 LATCH1
TC0H Hold Reg. Comparator Delay Counter EDG1 TC1 Capture/Compare Reg.
PA0H Hold Reg. 0 RESET
P1
Pin Logic
PAC1
TC1H Hold Reg. Comparator Delay Counter EDG2 TC2 Capture/Compare Reg.
PA1H Hold Reg. 0 RESET
P2
Pin Logic
PAC2
TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg.
PA2H Hold Reg. 0 RESET
P3
Pin Logic
PAC3
TC3H Hold Reg. Comparator EDG4 EDG0 MUX SH04 P5 Pin Logic Comparator EDG5 EDG1 MUX SH15 P6 Pin Logic Comparator EDG6 EDG2 MUX SH26 P7 Pin Logic Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. TC6 Capture/Compare Reg. TC5 Capture/Compare Reg. TC4 Capture/Compare Reg.
PA3H Hold Reg.
P4
Pin Logic
LATQ, BUFEN (Queue Mode)
Read TC3H Hold Reg.
Read TC2H Hold Reg.
Read TC1H Hold Reg.
Read TC0H Hold Reg.
Figure 19-68. Detailed Timer Block Diagram in Queue Mode when PRNT = 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 732 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
÷1, 2, 3, ... 256 Bus Clock Timer Prescaler 16-Bit Free-Running 16 BIT MAIN TIMER Main Timer Bus Clock ÷ 1, 2, 3, ... 256 Modulus Prescaler 0 P0 Pin Logic Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 LATCH0 LATCH3 LATCH2 LATCH1 16-Bit Load Register 16-Bit Modulus Down Counter RESET
8, 12, 16, ... 1024 TC0H Hold Reg. Comparator Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 PA0H Hold Reg. 0 P1 Pin Logic RESET
8, 12, 16, ... 1024 TC1H Hold Reg. Comparator Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 PA1H Hold Reg. 0 P2 Pin Logic RESET
8, 12, 16, ... 1024 TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg. PAC3 PA2H Hold Reg. 0 P3 Pin Logic RESET
8, 12, 16, ... 1024 TC3H Hold Reg. Comparator EDG4 EDG0 MUX SH04 P5 Pin Logic Comparator EDG5 EDG1 MUX SH15 P6 Pin Logic Comparator EDG6 EDG2 MUX SH26 P7 Pin Logic Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. Read TC0H Hold Reg. TC6 Capture/Compare Reg. Read TC1H Hold Reg. Read TC2H Hold Reg. TC5 Capture/Compare Reg. TC4 Capture/Compare Reg. PA3H Hold Reg.
P4
Pin Logic
LATQ, BUFEN (Queue Mode)
Read TC3H Hold Reg.
Figure 19-69. Detailed Timer Block Diagram in Queue Mode when PRNT = 1
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 733
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Load Holding Register and Reset Pulse Accumulator 0 EDG0 P0 Edge Detector Delay Counter 8-Bit PAC0 (PACN0)
8, 12,16, ..., 1024
PA0H Holding Register Interrupt 8, 12,16, ..., 1024 EDG1 P1 Edge Detector Delay Counter 0 8-Bit PAC1 (PACN1)
PA1H Holding Register
8, 12,16, ..., 1024 EDG2 P2 Edge Detector Delay Counter
0 8-Bit PAC2 (PACN2)
PA2H Holding Register Interrupt 8, 12,16, ..., 1024 P3 Edge Detector Delay Counter 0 EDG3 8-Bit PAC3 (PACN3)
PA3H Holding Register
Figure 19-70. 8-Bit Pulse Accumulators Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 734 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
TIMCLK (Timer Clock)
CLK1 CLK0
4:1 MUX
PACLK / 65536
PACLK / 256
Prescaled Clock (PCLK)
Clock Select (PAMOD) PACLK
Edge Detector
P7
Interrupt
8-Bit PAC3 (PACN3) PACA
8-Bit PAC2 (PACN2)
MUX
Divide by 64
Bus Clock
Interrupt
8-Bit PAC1 (PACN1) PACB
8-Bit PAC0 (PACN0)
Delay Counter
Edge Detector
P0
Figure 19-71. 16-Bit Pulse Accumulators Block Diagram
16-Bit Main Timer
Px
Edge Detector
Delay Counter TCx Input Capture Register Set CxF Interrupt
TCxH I.C. Holding Register
BUFEN • LATQ • TFMOD
Figure 19-72. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 735
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.4.1
Enhanced Capture Timer Modes of Operation
The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called input capture (IC) channels. Four IC channels (channels 7–4) are the same as on the standard timer with one capture register each that memorizes the timer value captured by an action on the associated input pin. Four other IC channels (channels 3–0), in addition to the capture register, also have one buffer each called a holding register. This allows two different timer values to be saved without generating any interrupts. Four 8-bit pulse accumulators are associated with the four buffered IC channels (channels 3–0). Each pulse accumulator has a holding register to memorize their value by an action on its external input. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. The 16-bit modulus down-counter can control the transfer of the IC registers and the pulse accumulators contents to the respective holding registers for a given period, every time the count reaches zero. The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability.
19.4.1.1
IC Channels
The IC channels are composed of four standard IC registers and four buffered IC channels. • An IC register is empty when it has been read or latched into the holding register. • A holding register is empty when it has been read. 19.4.1.1.1 Non-Buffered IC Channels
The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written unless it is empty. This will prevent the captured value from being overwritten until it is read. 19.4.1.1.2 Buffered IC Channels
There are two modes of operations for the buffered IC channels: 1. IC latch mode (LATQ = 1) The main timer value is memorized in the IC register by a valid input pin transition (see Figure 19-66 and Figure 19-67). The value of the buffered IC register is latched to its holding register by the modulus counter for a given period when the count reaches zero, by a write 0x0000 to the modulus counter or by a write to ICLAT in the MCCTL register. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. In case of latching, the contents of its holding register are overwritten.
MC9S12XHZ512 Data Sheet, Rev. 1.03 736 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 19.4.1.1, “IC Channels”). This will prevent the captured value from being overwritten until it is read or latched in the holding register. 2. IC Queue Mode (LATQ = 0) The main timer value is memorized in the IC register by a valid input pin transition (see Figure 19-68 and Figure 19-69). If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 19.4.1.1, “IC Channels”). In queue mode, reads of the holding register will latch the corresponding pulse accumulator value to its holding register. 19.4.1.1.3 Delayed IC Channels
There are four delay counters in this module associated with IC channels 0–3. The use of this feature is explained in the diagram and notes below.
BUS CLOCK
DLY_CNT INPUT ON CH0–3 INPUT ON CH0–3 INPUT ON CH0–3 INPUT ON CH0–3
0
1
2
3
253
254
255
256
Rejected 255 Cycles Rejected
255.5 Cycles
255.5 Cycles
Accepted
256 Cycles
Accepted
Figure 19-73. Channel Input Validity with Delay Counter Feature
In Figure 19-73 a delay counter value of 256 bus cycles is considered. 1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected. 2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points. 3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points. 4. Input pulses with a duration of DLY_CNT or longer are accepted.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 737
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.4.1.2
OC Channel Initialization
An internal compare channel whose output drives OCx may be programmed before the timer drives the output compare state (OCx). The required output of the compare logic can be disconnected from the pin, leaving it driven by the GP IO port, by setting the appropriate OCPDx bit before enabling the output compare channel (by default the OPCD bits are cleared which would enable the output compare logic to drive the pin as soon as the time output compare channel is enabled). The desired initial state can then be configured in the internal output compare logic by forcing a compare action with the logic disconnected from the IO (by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one). Clearing the output compare disconnect bit (OCPDx) will then allow the internal compare logic to drive the programmed state to OCx. This allows a glitch free switch over of the port from general purpose I/O to timer output.
19.4.1.3
Pulse Accumulators
There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC buffered channels 3–0. A pulse accumulator counts the number of active edges at the input of its channel. The minimum pulse width for the PAI input is greater than two bus clocks.The maximum input frequency on the pulse accumulator channel is one half the bus frequency or Eclk. The user can prevent the 8-bit pulse accumulators from counting further than 0x00FF by utilizing the PACMX control bit in the ICSYS register. In this case, a value of 0x00FF means that 255 counts or more have occurred. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator (see Figure 19-71). To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output compare 7 and 0 respectively, the user must set the corresponding bits: IOSx = 1, OMx = 0, and OLx = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared. There are two modes of operation for the pulse accumulators: • Pulse accumulator latch mode The value of the pulse accumulator is transferred to its holding register when the modulus down-counter reaches zero, a write 0x0000 to the modulus counter or when the force latch control bit ICLAT is written. At the same time the pulse accumulator is cleared. • Pulse accumulator queue mode When queue mode is enabled, reads of an input capture holding register will transfer the contents of the associated pulse accumulator to its holding register. At the same time the pulse accumulator is cleared.
19.4.1.4
Modulus Down-Counter
The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used to latch the values of the IC registers and the pulse accumulators to their holding registers. The action of latching can be programmed to be periodic or only once.
MC9S12XHZ512 Data Sheet, Rev. 1.03 738 Freescale Semiconductor
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.4.1.5
Precision Timer
By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter and enhance delay counter settings compared to the settings in the present ECT timer.
19.4.1.6
Flag Clearing Mechanisms
The flags in the ECT can be cleared one of two ways: 1. Normal flag clearing mechanism (TFFCA = 0) Any of the ECT flags can be cleared by writing a one to the flag. 2. Fast flag clearing mechanism (TFFCA = 1) With the timer fast flag clear all (TFFCA) enabled, the ECT flags can only be cleared by accessing the various registers associated with the ECT modes of operation as described below. The flags cannot be cleared via the normal flag clearing mechanism. This fast flag clearing mechanism has the advantage of eliminating the software overhead required by a separate clear sequence. Extra care must be taken to avoid accidental flag clearing due to unintended accesses. — Input capture A read from an input capture channel register causes the corresponding channel flag, CxF, to be cleared in the TFLG1 register. — Output compare A write to the output compare channel register causes the corresponding channel flag, CxF, to be cleared in the TFLG1 register. — Timer counter Any access to the TCNT register clears the TOF flag in the TFLG2 register. — Pulse accumulator A Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. — Pulse accumulator B Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. — Modulus down counter Any access to the MCCNT register clears the MCZF flag in the MCFLG register.
19.4.2
Reset
The reset state of each individual bit is listed within the register description section (Section 19.3, “Memory Map and Register Definition”) which details the registers and their bit-fields.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 739
Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.4.3
Interrupts
This section describes interrupts originated by the ECT block. The MCU must service the interrupt requests. Table 19-38 lists the interrupts generated by the ECT to communicate with the MCU.
Table 19-38. ECT Interrupts
Interrupt Source Timer channel 7–0 Modulus counter underflow Pulse accumulator B overflow Pulse accumulator A input Pulse accumulator A overflow Timer overflow Description Active high timer channel interrupts 7–0 Active high modulus counter interrupt Active high pulse accumulator B interrupt Active high pulse accumulator A input interrupt Pulse accumulator overflow interrupt Timer 0verflow interrupt
The ECT only originates interrupt requests. The following is a description of how the module makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
19.4.3.1
Channel [7:0] Interrupt
This active high output will be asserted by the module to request a timer channel 7–0 interrupt to be serviced by the system controller.
19.4.3.2
Modulus Counter Interrupt
This active high output will be asserted by the module to request a modulus counter underflow interrupt to be serviced by the system controller.
19.4.3.3
Pulse Accumulator B Overflow Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator B overflow interrupt to be serviced by the system controller.
19.4.3.4
Pulse Accumulator A Input Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator A input interrupt to be serviced by the system controller.
19.4.3.5
Pulse Accumulator A Overflow Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator A overflow interrupt to be serviced by the system controller.
19.4.3.6
Timer Overflow Interrupt
This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller.
MC9S12XHZ512 Data Sheet, Rev. 1.03 740 Freescale Semiconductor
Chapter 20 Voltage Regulator (VREG3V3V5)
20.1 Introduction
Module VREG_3V3 is a dual output voltage regulator that provides two separate 2.5V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3V up to 5V (typical).
20.1.1
Features
Module VREG_3V3 includes these distinctive features: • Two parallel, linear voltage regulators — Bandgap reference • Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) • Low-voltage reset (LVR) • Autonomous periodical interrupt (API)
20.1.2
Modes of Operation
There are three modes VREG_3V3 can operate in: 1. Full performance mode (FPM) (MCU is not in stop mode) The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR (power-on reset) are available. The API is available. 2. Reduced power mode (RPM) (MCU is in stop mode) The purpose is to reduce power consumption of the device. The output voltage may degrade to a lower value than in full performance mode, additionally the current sourcing capability is substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled. The API is available. 3. Shutdown mode Controlled by VREGEN (see device level specification for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a high-impedance state, only the POR feature is available, LVD and LVR are disabled. The API internal RC oscillator clock is not available. This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the VREG_3V3 to use external supplies.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 741
Chapter 20 Voltage Regulator (VREG3V3V5)
20.1.3
Block Diagram
Figure 20-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.
REG2 VDDR REG VBG REG1 VDDA
VDDPLL VSSPLL
VDD
LVD
LVR
LVR
POR
POR
VSSA
VSS
VREGEN
CTRL LVI API Rate Select API API
Bus Clock
LVD: Low-Voltage Detect LVR: Low-Voltage Reset POR: Power-On Reset
REG: Regulator Core CTRL: Regulator Control API: Auto. Periodical Interrupt PIN
Figure 20-1. VREG_3V3 Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 742 Freescale Semiconductor
Chapter 20 Voltage Regulator (VREG3V3V5)
20.2
External Signal Description
Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. Table 20-1 shows all signals of VREG_3V3 associated with pins.
Table 20-1. Signal Properties
Name VDDR VDDA VSSA VDD VSS VDDPLL VSSPLL VREGEN (optional) Function Power input (positive supply) Quiet input (positive supply) Quiet input (ground) Primary output (positive supply) Primary output (ground) Secondary output (positive supply) Secondary output (ground) Optional Regulator Enable Reset State — — — — — — — — Pull Up — — — — — — — —
NOTE Check device level specification for connectivity of the signals.
20.2.1
VDDR — Regulator Power Input Pins
Signal VDDR is the power input of VREG_3V3. All currents sourced into the regulator loads flow through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR (if VSSR is not available VSS) can smooth ripple on VDDR. For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without VREGEN pin.
20.2.2
VDDA, VSSA — Regulator Reference Supply Pins
Signals VDDA/VSSA, which are supposed to be relatively quiet, are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply.
20.2.3
VDD, VSS — Regulator Output1 (Core Logic) Pins
Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 743
Chapter 20 Voltage Regulator (VREG3V3V5)
20.2.4
VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins
Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator.
20.2.5
VREGEN — Optional Regulator Enable Pin
This optional signal is used to shutdown VREG_3V3. In that case, VDD/VSS and VDDPLL/VSSPLL must be provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high, the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode. For the connectivity of VREGEN, see device specification. NOTE Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa is not supported while MCU is powered.
20.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in VREG_3V3. If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within it’s memory slice.
20.3.1
Module Memory Map
Table 20-2. Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 Use HT Control Register (VREGHTCL) Control Register (VREGCTRL) Autonomous Periodical Interrupt Control Register (VREGAPICL) Autonomous Periodical Interrupt Trimming Register (VREGAPITR) Autonomous Periodical Interrupt Period High (VREGAPIRH) Autonomous Periodical Interrupt Period Low (VREGAPIRL) Reserved 06 Reserved 07 Access — R/W R/W R/W R/W R/W — —
Table 20-2 provides an overview of all used registers.
MC9S12XHZ512 Data Sheet, Rev. 1.03 744 Freescale Semiconductor
Chapter 20 Voltage Regulator (VREG3V3V5)
20.3.2
Register Descriptions
This section describes all the VREG_3V3 registers and their individual bits.
20.3.2.1
HT Control Register (VREGHTCL)
The VREGHTCL is reserved for test purposes. This register should not be written.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 20-2. HT Control Register (VREGHTCL)
20.3.2.2
Control Register (VREGCTRL)
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
LVDS 0
LVIE 0
LVIF 0
= Unimplemented or Reserved
Figure 20-3. Control Register (VREGCTRL) Table 20-3. VREGCTRL Field Descriptions
Field 2 LVDS 1 LVIE 0 LVIF Description Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect. 0 Input voltage VDDA is above level VLVID or RPM or shutdown mode. 1 Input voltage VDDA is below level VLVIA and FPM. Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set. Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 745
Chapter 20 Voltage Regulator (VREG3V3V5)
20.3.2.3
Autonomous Periodical Interrupt Control Register (VREGAPICL)
The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt features.
7 6 5 4 3 2 1 0
R W Reset
APICLK 0
0 0
0 0
0 0
0 0
APIFE 0
APIE 0
APIF 0
= Unimplemented or Reserved
Figure 20-4. Autonomous Periodical Interrupt Control Register (VREGAPICL) Table 20-4. VREGAPICL Field Descriptions
Field 7 APICLK Description Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation. 0 Autonomous periodical interrupt clock used as source. 1 Bus clock used as source. Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer when set. 0 Autonomous periodical interrupt is disabled. 1 Autonomous periodical interrupt is enabled and timer starts running. Autonomous Periodical Interrupt Enable Bit 0 API interrupt request is disabled. 1 API interrupt will be requested whenever APIF is set. Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed. This flag can only be cleared by writing a 1 to it. Clearing of the flag has precedence over setting. Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API timeout has not yet occurred. 1 API timeout has occurred.
2 APIFE
1 APIE 0 APIF
MC9S12XHZ512 Data Sheet, Rev. 1.03 746 Freescale Semiconductor
Chapter 20 Voltage Regulator (VREG3V3V5)
20.3.2.4
Autonomous Periodical Interrupt Trimming Register (VREGAPITR)
The VREGAPITR register allows to trim the API timeout period.
7 6 5 4 3 2 1 0
R W Reset
APITR5 01
APITR4 01
APITR3 01
APITR2 01
APITR1 01
APITR0 01
0 0
0 0
1. Reset value is either 0 or preset by factory. See Device User Guide for details. = Unimplemented or Reserved
Figure 20-5. Autonomous Periodical Interrupt Trimming Register (VREGAPITR) Table 20-5. VREGAPITR Field Descriptions
Field 7–2 APITR[5:0] Description Autonomous Periodical Interrupt Period Trimming Bits — See Table 20-6 for trimming effects.
Table 20-6. Trimming Effect of APIT
Bit APITR[5] APITR[4] APITR[3] APITR[2] APITR[1] APITR[0] Increases period Decreases period less than APITR[5] increased it Decreases period less than APITR[4] Decreases period less than APITR[3] Decreases period less than APITR[2] Decreases period less than APITR[1] Trimming Effect
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 747
Chapter 20 Voltage Regulator (VREG3V3V5)
20.3.2.5
Autonomous Periodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL)
The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous periodical interrupt rate.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
APIR11 0
APIR10 0
APIR9 0
APIR8 0
= Unimplemented or Reserved
Figure 20-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)
7
6
5
4
3
2
1
0
R W Reset
APIR7 0
APIR6 0
APIR5 0
APIR4 0
APIR3 0
APIR2 0
APIR1 0
APIR0 0
Figure 20-7. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL) Table 20-7. VREGAPIRH / VREGAPIRL Field Descriptions
Field 11-0 APIR[11:0] Description Autonomous Periodical Interrupt Rate Bits — These bits define the timeout period of the API. See Table 20-8 for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of VREGAPICL register.
MC9S12XHZ512 Data Sheet, Rev. 1.03 748 Freescale Semiconductor
Chapter 20 Voltage Regulator (VREG3V3V5)
Table 20-8. Selectable Autonomous Periodical Interrupt Periods
APICLK 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
1
APIR[11:0] 000 001 002 003 004 005 ..... FFD FFE FFF 000 001 002 003 004 005 ..... FFD FFE FFF
Selected Period 0.2 ms1 0.4 ms1 0.6 ms1 0.8 ms1 1.0 ms1 1.2 ms1 ..... 818.8 ms1 819 ms1 819.2 ms1 2 * bus clock period 4 * bus clock period 6 * bus clock period 8 * bus clock period 10 * bus clock period 12 * bus clock period ..... 8188 * bus clock period 8190 * bus clock period 8192 * bus clock period
When trimmed within specified accuracy. See electrical specifications for details.
You can calculate the selected period depending of APICLK as: Period = 2*(APIR[11:0] + 1) * 0.1 ms or period = 2*(APIR[11:0] + 1) * bus clock period
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 749
Chapter 20 Voltage Regulator (VREG3V3V5)
20.3.2.6
Reserved 06
The Reserved 06 is reserved for test purposes.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 20-8. Reserved 06
20.3.2.7
Reserved 07
The Reserved 07 is reserved for test purposes.
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 20-9. Reserved 07
20.4
20.4.1
Functional Description
General
Module VREG_3V3 is a voltage regulator, as depicted in Figure 20-1. The regulator functional elements are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on reset module (POR), and a low-voltage reset module (LVR).
20.4.2
Regulator Core (REG)
Respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ only in the amount of current that can be delivered. The regulator is a linear regulator with a bandgap reference when operated in Full Performance Mode. It acts as a voltage clamp in Reduced Power Mode. All load currents flow from input VDDR to VSS or VSSPLL. The reference circuits are supplied by VDDA and VSSA.
20.4.2.1
Full Performance Mode
In Full Performance Mode, the output voltage is compared with a reference voltage by an operational amplifier. The amplified input voltage difference drives the gate of an output transistor.
MC9S12XHZ512 Data Sheet, Rev. 1.03 750 Freescale Semiconductor
Chapter 20 Voltage Regulator (VREG3V3V5)
20.4.2.2
Reduced Power Mode
In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to reduce power consumption.
20.4.3
Low-Voltage Detect (LVD)
Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input voltage (VDDA–VSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode or Shutdown Mode.
20.4.4
Power-On Reset (POR)
This functional block monitors VDD. If VDD is below VPORD, POR is asserted; if VDD exceeds VPORD, the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-on sequence.
20.4.5
Low-Voltage Reset (LVR)
Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal, LVR asserts; if VDD rises above the deassertion level (VLVRD) signal, LVR deasserts. The LVR function is available only in Full Performance Mode.
20.4.6
Regulator Control (CTRL)
This part contains the register block of VREG_3V3 and further digital functionality needed to control the operating modes. CTRL also represents the interface to the digital core logic.
20.4.7
Autonomous Periodical Interrupt (API)
Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable the timer, the bit APIFE needs to be set. The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation will freeze when MCU clock source is selected and bus clock is turned off. See CRG specification for details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is not set. The APIR[11:0] bits determine the interrupt period. APIR[11:0] can only be written when APIFE is cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[11:0] bits. When the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF. The procedure to change APICLK or APIR[11:0] is first to clear APIFE, then write to APICLK or APIR[11:0], and afterwards set APIFE.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 751
Chapter 20 Voltage Regulator (VREG3V3V5)
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See Table 20-6 for the trimming effect of APITR. NOTE The first period after enabling the counter by APIFE might be reduced. The API internal RC oscillator clock is not available if VREG_3V3 is in Shutdown Mode.
20.4.8
Resets
This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and signals are provided in Section 20.3, “Memory Map and Register Definition”. Possible reset sources are listed in Table 20-9.
Table 20-9. Reset Sources
Reset Source Power-on reset Low-voltage reset Local Enable Always active Available only in Full Performance Mode
20.4.9
20.4.9.1
Description of Reset Operation
Power-On Reset (POR)
During chip power-up the digital core may not work if its supply voltage VDD is below the POR deassertion level (VPORD). Therefore, signal POR, which forces the other blocks of the device into reset, is kept high until VDD exceeds VPORD. The MCU will run the start-up sequence after POR deassertion. The power-on reset is active in all operation modes of VREG_3V3.
20.4.9.2
Low-Voltage Reset (LVR)
For details on low-voltage reset, see Section 20.4.5, “Low-Voltage Reset (LVR)”.
20.4.10 Interrupts
This section describes all interrupts originated by VREG_3V3. The interrupt vectors requested by VREG_3V3 are listed in Table 20-10. Vector addresses and interrupt priorities are defined at MCU level.
Table 20-10. Interrupt Vectors
Interrupt Source Low-voltage interrupt (LVI) Local Enable LVIE = 1; available only in Full Performance Mode
MC9S12XHZ512 Data Sheet, Rev. 1.03 752 Freescale Semiconductor
Chapter 20 Voltage Regulator (VREG3V3V5)
Table 20-10. Interrupt Vectors
Interrupt Source Autonomous periodical interrupt (API) Local Enable APIE = 1
20.4.10.1 Low-Voltage Interrupt (LVI)
In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1. NOTE On entering the Reduced Power Mode, the LVIF is not cleared by the VREG_3V3.
20.4.10.2 Autonomous Periodical Interrupt (API)
As soon as the configured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated by flag APIF = 1, is triggered if interrupt enable bit APIE = 1.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 753
Chapter 20 Voltage Regulator (VREG3V3V5)
MC9S12XHZ512 Data Sheet, Rev. 1.03 754 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
21.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12X core platform. The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. The BDM has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible to the BDM of the S12 family with the following exceptions: • TAGGO command no longer supported by BDM • External instruction tagging feature now part of DBG module • BDM register map and register content extended/modified • Global page access functionality • Enabled but not active out of reset in emulation modes • CLKSW bit set out of reset in emulation mode. • Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices is 0xC1)
21.1.1
Features
The BDM includes these distinctive features: • Single-wire communication with host development system • Enhanced capability for allowing more flexibility in clock rates • SYNC command to determine communication rate • GO_UNTIL command • Hardware handshake protocol to increase the performance of the serial communication • Active out of reset in special single chip mode • Nine hardware commands using free cycles, if available, for minimal CPU intervention • Hardware commands not requiring active BDM • 14 firmware commands execute from the standard BDM firmware lookup table
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 755
Chapter 21 Background Debug Module (S12XBDMV2)
• • • • • • • •
Software control of BDM operation during wait mode Software selectable clocks Global page access functionality Enabled but not active out of reset in emulation modes CLKSW bit set out of reset in emulation mode. When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash and EEPROM erase tests fail. Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices is 0xC1) BDM hardware commands are operational until system stop mode is entered (all bus masters are in stop mode)
21.1.2
Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed. Some systems may have a control bit that allows suspending thefunction during background debug mode.
21.1.2.1
Regular Run Modes
All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power during run mode. • Normal modes General operation of the BDM is available and operates the same in all normal modes. • Special single chip mode In special single chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. • Emulation modes In emulation mode, background operation is enabled but not active out of reset. This allows debugging and programming a system in this mode more easily.
21.1.2.2
Secure Mode Operation
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to Flash or EEPROM other than allowing erasure. For more information please see Section 21.4.1, “Security”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 756 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
21.1.2.3
Low-Power Modes
The BDM can be used until all bus masters (e.g., CPU or XGATE) are in stop mode. When CPU is in a low power mode (wait or stop mode) all BDM firmware commands as well as the hardware BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter a low power mode during BDM active mode. If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM is now ready to receive a new command.
21.1.3
Block Diagram
A block diagram of the BDM is shown in Figure 21-1.
Host System Serial Interface Data Control Register Block Address TRACE BDMACT Instruction Code and Execution Bus Interface and Control Logic Data Control Clocks 16-Bit Shift Register
BKGD
ENBDM SDV Standard BDM Firmware LOOKUP TABLE Secured BDM Firmware LOOKUP TABLE
UNSEC CLKSW BDMSTS Register
Figure 21-1. BDM Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 757
Chapter 21 Background Debug Module (S12XBDMV2)
21.2
External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode.
21.3
21.3.1
Memory Map and Register Definition
Module Memory Map
Table 21-1 shows the BDM memory map when BDM is active.
Table 21-1. BDM Memory Map
Global Address 0x7FFF00–0x7FFF0B 0x7FFF0C–0x7FFF0E 0x7FFF0F 0x7FFF10–0x7FFFFF Module BDM registers BDM firmware ROM Family ID (part of BDM firmware ROM) BDM firmware ROM Size (Bytes) 12 3 1 240
MC9S12XHZ512 Data Sheet, Rev. 1.03 758 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
21.3.2
Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 21-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global Address 0x7FFF00
Register Name Reserved R W
Bit 7 X
6 X
5 X
4 X
3 X
2 X
1 0
Bit 0 0
0x7FFF01
BDMSTS
R W
ENBDM X
BDMACT
0
SDV
TRACE
CLKSW X
UNSEC
0
0x7FFF02
Reserved
R W
X
X
X
X
X
X
0x7FFF03
Reserved
R W
X
X
X
X
X
X
X
X
0x7FFF04
Reserved
R W
X
X
X
X
X
X
X
X
0x7FFF05
Reserved
R W
X
X
X
X
X
X
X
X
0x7FFF06
BDMCCRL R W
CCR7 0
CCR6 0
CCR5 0
CCR4 0
CCR3 0
CCR2
CCR1
CCR0
0x7FFF07
BDMCCRH R W
CCR10
CCR9
CCR8
0x7FFF08
BDMGPR
R W
BGAE 0
BGP6 0
BGP5 0
BGP4 0
BGP3 0
BGP2 0
BGP1 0
BGP0 0
0x7FFF09
Reserved
R W
0x7FFF0A
Reserved
R W
0
0
0
0
0
0
0
0
0x7FFF0B
Reserved
R W
0
0
0
0
0
0
0
0
= Unimplemented, Reserved X = Indeterminate 0
= Implemented (do not alter) = Always read zero
Figure 21-2. BDM Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 759
Chapter 21 Background Debug Module (S12XBDMV2)
21.3.2.1
BDM Status Register (BDMSTS)
7 6 5 4 3 2 1 0
Register Global Address 0x7FFF01
R W Reset Special Single-Chip Mode Emulation Modes All Other Modes
ENBDM
BDMACT
0
SDV
TRACE
CLKSW
UNSEC
0
01 1 0
1 0 0
0 0 0
0 0 0
0 0 0
0 12 0
03 0 0
0 0 0
= Unimplemented, Reserved 0
1
= Implemented (do not alter)
= Always read zero
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased (Flash and EEPROM). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed. 2 CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when secured. 3 UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description).
Figure 21-3. BDM Status Register (BDMSTS)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured, but subject to the following: — ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single chip and emulation modes). — BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode. — CLKSW can only be written via BDM hardware WRITE_BD commands. — All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution.
Table 21-2. BDMSTS Field Descriptions
Field 7 ENBDM Description Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still allowed. 0 BDM disabled 1 BDM enabled Note: ENBDM is set by the firmware out of reset in special single chip mode and by hardware in emulation modes. In special single chip mode with the device secured, this bit will not be set by the firmware until after the EEPROM and Flash erase verify tests are complete. In emulation modes with the device secured, the BDM operations are blocked.
MC9S12XHZ512 Data Sheet, Rev. 1.03 760 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
Table 21-2. BDMSTS Field Descriptions (continued)
Field 6 BDMACT Description BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. 0 BDM not active 1 BDM active Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a firmware or hardware read command or after data has been received as part of a firmware or hardware write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow execution. 0 Data phase of command not complete 1 Data phase of command is complete TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set until BDM firmware is exited by one of the following BDM commands: GO or GO_UNTIL. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send. The delay should be obtained no matter which bit is modified to effectively change the clock source (either PLLSEL bit or CLKSW bit). This guarantees that the start of the next BDM command uses the new clock for timing subsequent BDM communications. Table 21-3 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (PLL select in the CRG module, the bit is part of the CLKSEL register) bits. Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency restriction on the alternate clock which was required on previous versions. Refer to the device specification to determine which clock connects to the alternate clock source input. Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new rate for the write command which changes it. Note: In emulation mode, the CLKSW bit will be set out of RESET. Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure firmware. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map overlapping the standard BDM firmware lookup table. The secure BDM firmware lookup table verifies that the on-chip EEPROM and Flash EEPROM are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted. 0 System is in a secured mode. 1 System is in a unsecured mode. Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect when the security byte in the Flash EEPROM is configured for unsecure mode.
4 SDV
3 TRACE
2 CLKSW
1 UNSEC
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 761
Chapter 21 Background Debug Module (S12XBDMV2)
Table 21-3. BDM Clock Sources
PLLSEL 0 0 1 1 CLKSW 0 1 0 1 Bus clock dependent on oscillator Bus clock dependent on oscillator Alternate clock (refer to the device specification to determine the alternate clock source) Bus clock dependent on the PLL BDMCLK
21.3.2.2
BDM CCR LOW Holding Register (BDMCCRL)
7 6 5 4 3 2 1 0
Register Global Address 0x7FFF06
R W Reset Special Single-Chip Mode All Other Modes
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
1 0
1 0
0 0
0 0
1 0
0 0
0 0
0 0
Figure 21-4. BDM CCR LOW Holding Register (BDMCCRL)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured NOTE When BDM is made active, the CPU stores the content of its CCRL register in the BDMCCRL register. However, out of special single-chip reset, the BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the CCRL register in this CPU mode. Out of reset in all other modes the BDMCCRL register is read zero. When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte of the condition code register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
MC9S12XHZ512 Data Sheet, Rev. 1.03 762 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
21.3.2.3
BDM CCR HIGH Holding Register (BDMCCRH)
7 6 5 4 3 2 1 0
Register Global Address 0x7FFF07
R W Reset
0 0
0 0
0 0
0 0
0 0
CCR10 0
CCR9 0
CCR8 0
= Unimplemented or Reserved
Figure 21-5. BDM CCR HIGH Holding Register (BDMCCRH)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured When entering background debug mode, the BDM CCR HIGH holding register is used to save the high byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be written to modify the CCR value.
21.3.2.4
BDM Global Page Index Register (BDMGPR)
7 6 BGP6 0 5 BGP5 0 4 BGP4 0 3 BGP3 0 2 BGP2 0 1 BGP1 0 0 BGP0 0
Register Global Address 0x7FFF08
R W Reset
BGAE 0
Figure 21-6. BDM Global Page Register (BDMGPR)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured
Table 21-4. BDMGPR Field Descriptions
Field 7 BGAE Description BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and firmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and WRITE_BD_) can not be used for global accesses even if the BGAE bit is set. 0 BDM Global Access disabled 1 BDM Global Access enabled BDM Global Page Index Bits 6–0 — These bits define the extended address bits from 22 to 16. For more detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.
6–0 BGP[6:0]
21.3.3
Family ID Assignment
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x7FFF0F). The read-only value is a unique family ID which is 0xC1 for S12X devices.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 763
Chapter 21 Background Debug Module (S12XBDMV2)
21.4
Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 21.4.3, “BDM Hardware Commands”. Target system memory includes all memory that is accessible by the CPU. Firmware commands are used to read and write CPU resources and to exit from active background debug mode, see Section 21.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC). Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see Section 21.4.3, “BDM Hardware Commands”) and in secure mode (see Section 21.4.1, “Security”). Firmware commands can only be executed when the system is not secure and is in active background debug mode (BDM).
21.4.1
Security
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip EEPROM and Flash EEPROM are erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the EEPROM or Flash do not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the firmware commands. This allows the BDM hardware to be used to erase the EEPROM and Flash. BDM operation is not possible in any other mode than special single chip mode when the device is secured. The device can only be unsecured via BDM serial interface in special single chip mode. For more information regarding security, please see the S12X_9SEC Block Guide.
21.4.2
Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE.
MC9S12XHZ512 Data Sheet, Rev. 1.03 764 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
After being enabled, BDM is activated by one of the following1: • Hardware BACKGROUND command • CPU BGND instruction • External instruction tagging mechanism2 • Breakpoint force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs.
21.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, EEPROM, Flash EEPROM, I/O and control registers, and all external memory. Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. The BDM hardware commands are listed in Table 21-5. The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is provided by the S12X_DBG module.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 765
Chapter 21 Background Debug Module (S12XBDMV2)
Table 21-5. Hardware Commands
Command BACKGROUND ACK_ENABLE ACK_DISABLE READ_BD_BYTE READ_BD_WORD READ_BYTE READ_WORD WRITE_BD_BYTE WRITE_BD_WORD WRITE_BYTE WRITE_WORD Opcode (hex) 90 D5 D6 E4 EC E0 E8 C4 CC C0 C8 Data None None None Description Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. Enable Handshake. Issues an ACK pulse after the command is executed. Disable Handshake. This command does not issue an ACK pulse.
16-bit address Read from memory with standard BDM firmware lookup table in map. 16-bit data out Odd address data on low byte; even address data on high byte. 16-bit address Read from memory with standard BDM firmware lookup table in map. 16-bit data out Must be aligned access. 16-bit address Read from memory with standard BDM firmware lookup table out of map. 16-bit data out Odd address data on low byte; even address data on high byte. 16-bit address Read from memory with standard BDM firmware lookup table out of map. 16-bit data out Must be aligned access. 16-bit address Write to memory with standard BDM firmware lookup table in map. 16-bit data in Odd address data on low byte; even address data on high byte. 16-bit address Write to memory with standard BDM firmware lookup table in map. 16-bit data in Must be aligned access. 16-bit address Write to memory with standard BDM firmware lookup table out of map. 16-bit data in Odd address data on low byte; even address data on high byte. 16-bit address Write to memory with standard BDM firmware lookup table out of map. 16-bit data in Must be aligned access.
NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands.
21.4.4
Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard BDM firmware commands, see Section 21.4.2, “Enabling and Activating BDM”. Normal instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 21-6.
MC9S12XHZ512 Data Sheet, Rev. 1.03 766 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
Table 21-6. Firmware Commands
Command1 READ_NEXT2 READ_PC READ_D READ_X READ_Y READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO GO_UNTIL3 TRACE1 TAGGO -> GO Opcode (hex) 62 63 64 65 66 67 42 Data Description
16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. 16-bit data out Read program counter. 16-bit data out Read D accumulator. 16-bit data out Read X index register. 16-bit data out Read Y index register. 16-bit data out Read stack pointer. 16-bit data in Increment X index register by 2 (X = X + 2), then write word to location pointed to by X. Write program counter. Write D accumulator. Write X index register. Write Y index register. Write stack pointer. Go to user program. If enabled, ACK will occur when leaving active background mode. Go to user program. If enabled, ACK will occur upon returning to active background mode. Execute one user instruction then return to active BDM. If enabled, ACK will occur upon returning to active background mode. (Previous enable tagging and go to user program.) This command will be deprecated and should not be used anymore. Opcode will be executed as a GO command.
43 44 45 46 47 08 0C 10 18
16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in none none none none
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 2 When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources are accessed rather than user code. Writing BDM firmware is not possible. 3 System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode). The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL” condition (BDM active again) is reached (see Section 21.4.7, “Serial Interface Hardware Handshake Protocol” last Note).
1
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 767
Chapter 21 Background Debug Module (S12XBDMV2)
21.4.5
BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. The following cycle count information is only valid when the external wait function is not used (see wait bit of EBI sub-block). During an external wait the BDM can not steal a cycle. Hence be careful with the external wait function if the BDM serial interface is much faster than the bus, because of the BDM soft-reset after time-out (see Section 21.4.11, “Serial Communication Time Out”). For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. This includes the potential of extra cycles when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the PRU (port replacement unit) in emulation mode. The 48 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. NOTE This timing has increased from previous BDM modules due to the new capability in which the BDM serial interface can potentially run faster than the bus. On previous BDM modules this extra time could be hidden within the serial time. For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed.
MC9S12XHZ512 Data Sheet, Rev. 1.03 768 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing or the external wait function is used, it is recommended that the ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 21-7 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.1
8 Bits AT ~16 TC/Bit Hardware Read Command 16 Bits AT ~16 TC/Bit Address 150-BC Delay 16 Bits AT ~16 TC/Bit Data 150-BC Delay Hardware Write Command 48-BC DELAY Firmware Read Command Data 36-BC DELAY Firmware Write Command 76-BC Delay GO, TRACE Command Next Command BC = Bus Clock Cycles TC = Target Clock Cycles Data Next Command Next Command Address Data Next Command Next Command
Figure 21-7. BDM Command Structure
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 21.4.6, “BDM Serial Interface” and Section 21.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 769
Chapter 21 Background Debug Module (S12XBDMV2)
21.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see Section 21.3.2.1, “BDM Status Register (BDMSTS)”. This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 21-8 and that of target-to-host in Figure 21-9 and Figure 21-10. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 21-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
MC9S12XHZ512 Data Sheet, Rev. 1.03 770 Freescale Semiconductor
Chapter 21 Background Debug Module (S12XBDMV2)
BDM Clock (Target MCU)
Host Transmit 1
Host Transmit 0 Perceived Start of Bit Time 10 Cycles Synchronization Uncertainty Target Senses Bit Earliest Start of Next Bit
Figure 21-8. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 21-9 shows the host receiving a logic 1 from the target system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse Perceived Start of Bit Time R-C Rise BKGD Pin
High-Impedance
High-Impedance
High-Impedance
10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit
Figure 21-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
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Chapter 21 Background Debug Module (S12XBDMV2)
Figure 21-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.
BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Drive and Speedup Pulse Perceived Start of Bit Time BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit
High-Impedance Speedup Pulse
Figure 21-10. BDM Target-to-Host Serial Bit Timing (Logic 0)
21.4.7
Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 21-11). This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends upon the CPU bus frequency, which in some cases could be very slow
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Chapter 21 Background Debug Module (S12XBDMV2)
compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication.
BDM Clock (Target MCU)
16 Cycles Target Transmits ACK Pulse High-Impedance 32 Cycles Speedup Pulse Minimum Delay From the BDM Command BKGD Pin Earliest Start of Next Bit High-Impedance
16th Tick of the Last Command Bit
Figure 21-11. Target Acknowledge Pulse (ACK)
NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. Figure 21-12 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even.
Target BKGD Pin READ_BYTE Host Byte Address Target Host New BDM Command Host BDM Issues the ACK Pulse (out of scale) BDM Executes the READ_BYTE Command Target
(2) Bytes are Retrieved
BDM Decodes the Command
Figure 21-12. Handshake Protocol at Command Level
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Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 21-11 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin. NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). Other “highs” are pulled rather than driven. However, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. NOTE The ACK pulse does not provide a time out. This means for the GO_UNTIL command that it can not be distinguished if a stop or wait has been executed (command discarded and ACK not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command. See the handshake abort procedure described in Section 21.4.8, “Hardware Handshake Abort Procedure”.
21.4.8
Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 21.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it can not be guaranteed that the pending command is aborted when issuing a SYNC before the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware READ or WRITE command that is issued and if the serial interface is running on a different clock rate than the bus. When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or
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GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 21.4.9, “SYNC — Request Timed Reference Pulse”. Figure 21-13 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer.
READ_BYTE CMD is Aborted by the SYNC Request (Out of Scale) BKGD Pin READ_BYTE Host Memory Address Target SYNC Response From the Target (Out of Scale) READ_STATUS Host Target New BDM Command Host Target
BDM Decode and Starts to Execute the READ_BYTE Command
New BDM Command
Figure 21-13. ACK Abort Procedure at the Command Level
NOTE Figure 21-13 does not represent the signals in a true timing scale
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Figure 21-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conflict from happening.
At Least 128 Cycles BDM Clock (Target MCU) ACK Pulse Target MCU Drives to BKGD Pin Host Drives SYNC To BKGD Pin Host and Target Drive to BKGD Pin Host SYNC Request Pulse BKGD Pin 16 Cycles High-Impedance Electrical Conflict Speedup Pulse
Figure 21-14. ACK Pulse and SYNC Request Conflict
NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could eventually occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. The commands are described as follows: • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. • ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 21.4.3, “BDM Hardware Commands” and Section 21.4.4, “Standard BDM Firmware Commands” for more information on the BDM commands.
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Chapter 21 Background Debug Module (S12XBDMV2)
The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command.
21.4.9
SYNC — Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by CLKSW.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic one. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed
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within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued.
21.4.10 Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist. Do not trace the CPU instruction BGND used for soft breakpoints. Tracing the BGND instruction will result in a return address pointing to BDM firmware address space. When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving the low power mode. This is the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM hardware commands except the BACKGROUND command are operational after tracing a stop or wait instruction and still being in stop or wait mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational. As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the corresponding interrupt service routine. In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system
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stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command.
21.4.11 Serial Communication Time Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any time-out limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDM is running in a frequency much greater than the CPU frequency. In this case, the command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.1 Introduction
The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The S12XDBG module is optimized for the HCS12X 16-bit architecture and allows debugging of both S12XCPU and XGATE module operations. Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user configures the S12XDBG module for a debugging session over the BDM interface. Once configured the S12XDBG module is armed and the device leaves BDM Mode returning control to the user program, which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured over a serial interface using SWI routines.
22.1.1
Glossary Of Terms
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt. BDM : Background Debug Mode DUG: Device User Guide, describing the features of the device into which the DBG is integrated. WORD: 16 bit data entity Data Line : 64 bit data entity XGATE : S12X family programmable Direct Memory Access Module CPU : S12X_CPU module Tag : Tags can be attached to XGATE or CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs.
22.1.2
Overview
The comparators monitor the bus activity of the S12XCPU and XGATE modules. When a match occurs the control logic can trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated. Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered by the external TAGHI and TAGLO signals, by an XGATE module S/W breakpoint request or an immediate trigger, instigated by writing to the TRIG control bit.
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The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
22.1.3
•
Features
•
•
•
•
•
•
Four comparators (A, B, C, and D) — Comparators A and C compare the full address bus and full 16-bit data bus — Comparators A and C feature a data bus mask register — Comparators B and D compare the full address bus only — Each comparator can be configured to monitor either S12XCPU or XGATE buses — Each comparator features selection of read or write access cycles — Comparators B and D allow selection of byte or word access cycles — Comparisons can be used as triggers for the state sequencer Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin ≤ Address ≤ Addmax — Outside address range match mode, Address < Addmin or Address > Addmax Two types of triggers — Tagged — This triggers just before a specific instruction begins execution — Force — This triggers on the first instruction boundary after a match occurs. Three types of breakpoints — S12XCPU breakpoint entering BDM on breakpoint (BDM) — S12XCPU breakpoint executing SWI on breakpoint (SWI) — XGATE breakpoint Three trigger modes independent of comparators — External instruction tagging (associated with S12XCPU instructions only) — XGATE S/W breakpoint request — TRIG Immediate software trigger Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 22.4.5.2.1) for change of flow definition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Pure PC: All program counter addresses are stored. 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin, End, and Mid alignment of tracing to trigger
22.1.4
Modes of Operation
The S12XDBG module can be used in all MCU functional modes.
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Chapter 22 S12X Debug (S12XDBGV2) Module
During BDM hardware accesses and whilst the BDM module is active, S12XCPU monitoring is disabled. Thus breakpoints, comparators, and bus tracing mapped to the S12XCPU are disabled but XGATE bus monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE module. When the S12XCPU enters active BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed. The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be generated if the MCU is secure.
Table 22-1. Mode Dependent Restriction Summary
BDM Enable x 0 0 1 1 BDM Active x 0 1 0 1 MCU Secure 1 0 0 0 0 Yes XGATE only Comparator Matches Enabled Yes Yes Breakpoints Possible Yes Only SWI Yes XGATE only Tagging Possible Yes Yes Yes XGATE only Tracing Possible No Yes Yes XGATE only
Active BDM not possible when not enabled
22.1.5
Block Diagram
TAGS BREAKPOINT REQUESTS S12XCPU & XGATE
TAGHITS EXTERNAL TAGHI / TAGLO XGATE S/W BREAKPOINT REQUEST SECURE COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D MATCH0 COMPARATOR MATCH CONTROL MATCH1 MATCH2 MATCH3 TAG & TRIGGER CONTROL LOGIC
TRIGGER STATE STATE SEQUENCER STATE
S12XCPU BUS
XGATE BUS
BUS INTERFACE
TRACE CONTROL TRIGGER
TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS)
Figure 22-1. Debug Module Block Diagram
22.2
External Signal Description
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation modes only.
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Table 22-2. External System Pins Associated With S12XDBG
Pin Name TAGHI (See DUG) TAGLO (See DUG) TAGLO (See DUG) Pin Functions TAGHI TAGLO Unconditional Tagging Enable Description When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. When instruction tagging is on, tags the low half of the instruction word being read into the instruction queue. In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the end of reset enables the Unconditional Tagging function.
22.3
22.3.1
Memory Map and Registers
Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 22-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
Address 0x0020 Name DBGC1 R W R W R W R W R W R W R W R W R W Bit 7 ARM TBF 6 0 TRIG EXTF 5 XGSBPE 0 4 BDM 0 0 3 DBGBRK SSF2 2 1 Bit 0 COMRV SSF1 SSF0
0x0021
DBGSR
0x0022
DBGTCR
TSOURCE 0 0 0
TRANGE 0
TRCMOD
TALIGN
0x0023
DBGC2
CDCM Bit 11 Bit 10 Bit 9
ABCM Bit 8
0x0024
DBGTBH
Bit 15
Bit 14
Bit 13
Bit 12
0x0025
DBGTBL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0026
DBGCNT
0
CNT
0x0027 0x0027 0x00281 0x00282
DBGSCRX DBGMFR
0 0
0 0
0 0
0 0
SC3 MC3
SC2 MC2
SC1 MC1
SC0 MC0
DBGXCTL R (COMPA/C) W DBGXCTL R (COMPB/D) W DBGXAH R W
0
NDB SZ
TAG TAG
BRK BRK
RW RW
RWE RWE
SRC SRC
COMPE COMPE
SZE 0
0x0029
Bit 22
21
20
19
18
17
Bit 16
Figure 22-2. Quick Reference to S12XDBG Registers
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Chapter 22 S12X Debug (S12XDBGV2) Module
Address 0x002A
Name DBGXAM R W R W R W R W R W
Bit 7 Bit 15
6 14
5 13
4 12
3 11
2 10
1 9
Bit 0 Bit 8
0x002B
DBGXAL
Bit 7
6
5
4
3
2
1
Bit 0
0x002C
DBGXDH
Bit 15
14
13
12
11
10
9
Bit 8
0x002D
DBGXDL
Bit 7
6
5
4
3
2
1
Bit 0
0x002E
DBGXDHM
Bit 15
14
13
12
11
10
9
Bit 8
R Bit 7 6 5 4 3 2 W 1 This represents the contents if the Comparator A or C control register is blended into this address. 2 This represents the contents if the Comparator B or D control register is blended into this address 0x002F DBGXDLM
1
Bit 0
Figure 22-2. Quick Reference to S12XDBG Registers
22.3.2
Register Descriptions
This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
22.3.2.1
Debug Control Register 1 (DBGC1)
Address: 0x0020
7 6 5 4 3 2 1 0
R W Reset
ARM 0
0 TRIG 0
XGSBPE 0
BDM 0 0
DBGBRK 0 0
COMRV 0
Figure 22-3. Debug Control Register (DBGC1)
Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 5:2 anytime S12XDBG is not armed. NOTE When disarming the S12XDBG by clearing ARM with software, the contents of bits[5:2] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 785
Chapter 22 S12X Debug (S12XDBGV2) Module
Table 22-3. DBGC1 Field Descriptions
Field 7 ARM Description Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. 0 Debugger disarmed 1 Debugger armed Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of comparator or external tag signal status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If both TSOURCE bits are clear no tracing is carried out. If tracing has already commenced using BEGINor MID trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit settings, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit has no effect. 0 Do not trigger until the state sequencer enters the Final State. 1 Enter Final State immediately and issue forced breakpoint request when tracing is completed. XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is passed to the S12XCPU. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can request an S12XCPU breakpoint depending on the state of this bit. 0 XGATE S/W breakpoint request is disabled 1 XGATE S/W breakpoint request is enabled Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint to either S12XCPU or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please refer to Section 22.4.7 for further details. XGATE software breakpoints are independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the S12XCPU independent of the DBGBRK bit field configuration. See Table 22-4. Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register is visible at the address 0x0027. See Table 22-5.
6 TRIG
5 XGSBPE
4 BDM
3–2 DBGBRK
1–0 COMRV
Table 22-4. DBGBRK Encoding
DBGBRK 00 01 10 11 Resource Halted by Breakpoint No breakpoint generated XGATE breakpoint generated S12XCPU breakpoint generated Breakpoints generated for S12XCPU and XGATE
Table 22-5. COMRV Encoding
COMRV 00 01 Visible Comparator Comparator A Comparator B Visible Register at 0x0027 DBGSCR1 DBGSCR2
MC9S12XHZ512 Data Sheet, Rev. 1.03 786 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
Table 22-5. COMRV Encoding
COMRV 10 11 Visible Comparator Comparator C Comparator D Visible Register at 0x0027 DBGSCR3 DBGMFR
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 787
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.2
Debug Status Register (DBGSR)
Address: 0x0021
7 6 5 4 3 2 1 0
R W Reset POR
TBF — 0
EXTF 0 0
0 0 0
0 0 0
0 0 0
SSF2 0 0
SSF1 0 0
SSF0 0 0
= Unimplemented or Reserved
Figure 22-4. Debug Status Register (DBGSR)
Read: Anytime Write: Never
Table 22-6. DBGSR Field Descriptions
Field 7 TBF Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0]. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was met since arming. This bit is cleared when ARM in DBGC1 is written to a one. 0 External tag hit has not occurred 1 External tag hit has occurred State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 22-7.
6 EXTF
2–0 SSF[2:0]
Table 22-7. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0] 000 001 010 011 100 101,110,111 Current State State0 (disarmed) State1 State2 State3 Final State Reserved
MC9S12XHZ512 Data Sheet, Rev. 1.03 788 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.3
Debug Trace Control Register (DBGTCR)
Address: 0x0022
7 6 5 4 3 2 1 0
R W Reset 0
TSOURCE 0 0
TRANGE 0 0
TRCMOD 0 0
TALIGN 0
Figure 22-5. Debug Trace Control Register (DBGTCR)
Read: Anytime Write: Bits 7:6 only when S12XDBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed.
Table 22-8. DBGTCR Field Descriptions
Field 7–6 TSOURCE 5–4 TRANGE Description Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU system is secured, these bits cannot be set and tracing is inhibited. See Table 22-9. Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when tracing from the S12XCPU in Detail Mode. The XGATE tracing range cannot be narrowed using these bits. To use a comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state sequence triggers. If the corresponding SRC bit is set the comparator is mapped to the XGATE buses, the TRANGE bits have no effect on the valid address range, memory accesses within the whole memory map are traced. See Table 22-10. Trace Mode Bits — See Section 22.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See Table 22-11. Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a tracing session. See Table 22-12.
3–2 TRCMOD
1–0 TALIGN
Table 22-9. TSOURCE — Trace Source Bit Encoding
TSOURCE 00 01 10 11
1 2 1 1,2
Tracing Source No tracing requested S12XCPU XGATE Both S12XCPU and XGATE
No range limitations are allowed. Thus tracing operates as if TRANGE = 00. No Detail Mode tracing supported. If TRCMOD = 10, no information is stored.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 789
Chapter 22 S12X Debug (S12XDBGV2) Module
Table 22-10. TRANGE Trace Range Encoding
TRANGE 00 01 10 11 Tracing Range Trace from all addresses (No filter) Trace only in address range from $00000 to Comparator D Trace only in address range from Comparator C to $7FFFFF Trace only in range from Comparator C to Comparator D
Table 22-11. TRCMOD Trace Mode Bit Encoding
TRCMOD 00 01 10 11 Description Normal Loop1 Detail Pure PC
Table 22-12. TALIGN Trace Alignment Encoding
TALIGN 00 01 10 11 Description Trigger at end of stored data Trigger before storing data Trace buffer entries before and after trigger Reserved
MC9S12XHZ512 Data Sheet, Rev. 1.03 790 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.4
Debug Control Register2 (DBGC2)
Address: 0x0023
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0 0
CDCM 0 0
ABCM 0
= Unimplemented or Reserved
Figure 22-6. Debug Control Register2 (DBGC2)
Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching.
Table 22-13. DBGC2 Field Descriptions
Field 3–2 CDCM[1:0] 1–0 ABCM[1:0] Description C and D Comparator Match Control — These bits determine the C and D comparator match mapping as described in Table 22-14. A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 22-15.
Table 22-14. CDCM Encoding
CDCM 00 01 10 11
1
Description Match2 mapped to comparator C match....... Match3 mapped to comparator D match. Match2 mapped to comparator C/D inside range....... Match3 disabled. Match2 mapped to comparator C/D outside range....... Match3 disabled. Reserved1
Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D
Table 22-15. ABCM Encoding
ABCM 00 01 10 11
1
Description Match0 mapped to comparator A match....... Match1 mapped to comparator B match. Match 0 mapped to comparator A/B inside range....... Match1 disabled. Match 0 mapped to comparator A/B outside range....... Match1 disabled. Reserved1
Currently defaults to Match0 mapped to comparator A : Match1 mapped to comparator B
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 791
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.5
Debug Trace Buffer Register (DBGTBH:DBGTBL)
Address: 0x0024, 0x0025
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W POR Other Resets
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 X — X — X — X — X — X — X —
Bit 8 X —
Bit 7 X —
Bit 6 X —
Bit 5 X —
Bit 4 X —
Bit 3 X —
Bit 2 X —
Bit 1 X —
Bit 0 X —
Figure 22-7. Debug Trace Buffer Register (DBGTB)
Read: Anytime when unlocked and not secured and not armed. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents.
Table 22-16. DBGTB Field Descriptions
Field 15–0 Bit[15:0] Description Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 64-bit wide data lines of the Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed. The POR state is undefined Other resets do not affect the trace buffer contents. .
MC9S12XHZ512 Data Sheet, Rev. 1.03 792 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.6
Debug Count Register (DBGCNT)
Address: 0x0026
7 6 5 4 3 2 1 0
R W Reset POR
0 0 0 — 0 — 0 — 0
CNT — 0 — 0 — 0 — 0
= Unimplemented or Reserved
Figure 22-8. Debug Count Register (DBGCNT)
Read: Anytime Write: Never
Table 22-17. DBGCNT Field Descriptions
Field 6–0 CNT[6:0] Description Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer. Table 22-18 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer.
Table 22-18. CNT Decoding Table
TBF (DBGSR) 0 0 0 CNT[6:0] 0000000 0000001 0000010 0000100 0000110 .. 1111100 1111110 0000000 0000010 .. .. 1111110 Description No data valid 32 bits of one line valid1 1 line valid 2 lines valid 3 lines valid .. 62 lines valid 63 lines valid 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 64 lines valid, oldest data has been overwritten by most recent data
0 1 1
1
This applies to Normal/Loop1 Modes when tracing from either S12XCPU or XGATE only.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 793
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.7
Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR).
Table 22-19. State Control Register Access Encoding
COMRV 00 01 10 11 Visible State Control Register DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR
MC9S12XHZ512 Data Sheet, Rev. 1.03 794 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.7.1
Address: 0x0027
7
Debug State Control Register 1 (DBGSCR1)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
SC3 0
SC2 0
SC1 0
SC0 0
= Unimplemented or Reserved
Figure 22-9. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and S12XDBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the match channels of the comparator match control logic as depicted in Figure 22-1 and described in Section 22.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Table 22-20. DBGSCR1 Field Descriptions
Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State1, based upon the match event.
Table 22-21. State1 Sequencer Next State Selection
SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state2 Any match triggers to state3 Any match triggers to Final State Match2 triggers to State2....... Other matches have no effect Match2 triggers to State3....... Other matches have no effect Match2 triggers to Final State....... Other matches have no effect Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2 Reserved Reserved Reserved
The trigger priorities described in Table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 795
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.7.2
Address: 0x0027
7
Debug State Control Register 2 (DBGSCR2)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
SC3 0
SC2 0
SC1 0
SC0 0
= Unimplemented or Reserved
Figure 22-10. Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01 Write: If COMRV[1:0] = 01 and S12XDBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2. The matches refer to the match channels of the comparator match control logic as depicted in Figure 22-1 and described in Section 22.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Table 22-22. DBGSCR2 Field Descriptions
Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State2, based upon the match event.
Table 22-23. State2 —Sequencer Next State Selection
SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state1 Any match triggers to state3 Any match triggers to Final State Match3 triggers to State1....... Other matches have no effect Match3 triggers to State3....... Other matches have no effect Match3 triggers to Final State....... Other matches have no effect Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect Match2 triggers to State1..... Match3 trigger to Final State Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State Reserved Reserved
The trigger priorities described in Table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches.
MC9S12XHZ512 Data Sheet, Rev. 1.03 796 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.7.3
Address: 0x0027
7
Debug State Control Register 3 (DBGSCR3)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
SC3 0
SC2 0
SC1 0
SC0 0
= Unimplemented or Reserved
Figure 22-11. Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10 Write: If COMRV[1:0] = 10 and S12XDBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3. The matches refer to the match channels of the comparator match control logic as depicted in Figure 22-1 and described in Section 22.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Table 22-24. DBGSCR3 Field Descriptions
Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State3, based upon the match event.
Table 22-25. State3 — Sequencer Next State Selection
SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state1 Any match triggers to state2 Any match triggers to Final State Match0 triggers to State1....... Other matches have no effect Match0 triggers to State2....... Other matches have no effect Match0 triggers to Final State.......Match1 triggers to State1 Match1 triggers to State1....... Other matches have no effect Match1 triggers to State2....... Other matches have no effect Match1 triggers to Final State....... Other matches have no effect Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect Match2 triggers to Final State....... Other matches have no effect Match3 triggers to Final State....... Other matches have no effect Reserved Reserved
The trigger priorities described in Table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 797
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.7.4
Address: 0x0027
7
Debug Match Flag Register (DBGMFR)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
MC3 0
MC2 0
MC1 0
MC0 0
= Unimplemented or Reserved
Figure 22-12. Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11 Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly to a channel. Should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag is set, further triggers on the same channel have no affect.
22.3.2.8
Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparators B and D consist of four register bytes (three address bus compare registers and a control register). Each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for comparators B and D differ from those of comparators A and C.
Table 22-26. Comparator Register Layout
0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F CONTROL ADDRESS HIGH ADDRESS MEDIUM ADDRESS LOW DATA HIGH COMPARATOR DATA LOW COMPARATOR DATA HIGH MASK DATA LOW MASK Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Comparators A,B,C,D Comparators A,B,C,D Comparators A,B,C,D Comparators A,B,C,D Comparator A and C only Comparator A and C only Comparator A and C only Comparator A and C only
MC9S12XHZ512 Data Sheet, Rev. 1.03 798 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.8.1
Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map.
Address: 0x0028
7 6 5 4 3 2 1 0
R W Reset
0 0
NDB 0
TAG 0
BRK 0
RW 0
RWE 0
SRC 0
COMPE 0
= Unimplemented or Reserved
Figure 22-13. Debug Comparator Control Register (Comparators A and C)
Address: 0x0028
7 6 5 4 3 2 1 0
R W Reset
SZE 0
SZ 0
TAG 0
BRK 0
RW 0
RWE 0
SRC 0
COMPE 0
Figure 22-14. Debug Comparator Control Register (Comparators B and D)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding. The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 22-27.
Table 22-27. Comparator Address Register Visibility
COMRV 00 01 10 11 Visible Comparator DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM DBGBCTL, DBGBAH, DBGBAM, DBGBAL DBGCCTL, DBGCAH, DBGCAM, DBGCAL, DBGCDH, DBGCDL, DBGCDHM, DBGCDLM DBDACTL, DBGDAH, DBGDAM, DBGDAL
Table 22-28. DBGXCTL Field Descriptions
Field 7 SZE (Comparators B nd D) 6 NDB (Comparators A and C Description Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator. This bit is ignored if the TAG bit in the same register is set. 0 Word/Byte access size is not used in comparison 1 Word/Byte access size is used in comparison Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. Furthermore data bus bits can be individually masked using the comparator data mask registers. This bit is only available for comparators A and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for comparators B and D. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 799
Chapter 22 S12X Debug (S12XDBGV2) Module
Table 22-28. DBGXCTL Field Descriptions (continued)
Field 6 SZ (Comparators B and D) 5 TAG Description Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. This bit position has NDB functionality for comparators A and C 0 Word access size will be compared 1 Byte access size will be compared Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 Trigger immediately on match 1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated Break — This bit controls whether a channel match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bits DBGBRK[1:0]. 0 The debug session termination is dependent upon the state sequencer and trigger conditions. 1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is not used if RWE = 0. 0 Write cycle will be matched 1 Read cycle will be matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Determines mapping of comparator to S12XCPU or XGATE 0 The comparator is mapped to S12XCPU buses 1 The comparator is mapped to XGATE address and data buses Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled for state sequence triggers or tag generation
4 BRK
3 RW
2 RWE
1 SRC 0 COMPE
Table 22-29 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. Thus these bits are ignored if tagged triggering is selected.
Table 22-29. Read or Write Comparison Logic Table
RWE Bit 0 0 1 1 1 1 RW Bit x x 0 0 1 1 RW Signal 0 1 0 1 0 1 Comment RW not used in comparison RW not used in comparison Write data bus No match No match Read data bus
MC9S12XHZ512 Data Sheet, Rev. 1.03 800 Freescale Semiconductor
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.8.2
Address: 0x0029
7
Debug Comparator Address High Register (DBGXAH)
6
5
4
3
2
1
0
R W Reset
0 0
Bit 22 0
Bit 21 0
Bit 20 0
Bit 19 0
Bit 18 0
Bit 17 0
Bit 16 0
= Unimplemented or Reserved
Figure 22-15. Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding.
Table 22-30. DBGXAH Field Descriptions
Field 6–0 Bit[22:16] Description Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. This register byte is ignored for XGATE compares. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
22.3.2.8.3
Address: 0x002A
7
Debug Comparator Address Mid Register (DBGXAM)
6
5
4
3
2
1
0
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 22-16. Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding.
Table 22-31. DBGXAM Field Descriptions
Field 7–0 Bit[15:8] Description Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the selected comparator will compare the address bus bits [15:8] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.8.4
Address: 0x002B
7
Debug Comparator Address Low Register (DBGXAL)
6
5
4
3
2
1
0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 22-17. Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding.
Table 22-32. DBGXAL Field Descriptions
Field 7–0 Bits[7:0] Description Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator will compare the address bus bits [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
22.3.2.8.5
Address: 0x002C
7
Debug Comparator Data High Register (DBGXDH)
6
5
4
3
2
1
0
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 22-18. Debug Comparator Data High Register (DBGXDH)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding.
Table 22-33. DBGXAH Field Descriptions
Field 7–0 Bits[15:8] Description Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.8.6
Address: 0x002D
7
Debug Comparator Data Low Register (DBGXDL)
6
5
4
3
2
1
0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 22-19. Debug Comparator Data Low Register (DBGXDL)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding.
Table 22-34. DBGXDL Field Descriptions
Field 7–0 Bits[7:0] Description Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one
22.3.2.8.7
Address: 0x002E
7
Debug Comparator Data High Mask Register (DBGXDHM)
6
5
4
3
2
1
0
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 22-20. Debug Comparator Data High Mask Register (DBGXDHM)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding.
Table 22-35. DBGXDHM Field Descriptions
Field 7–0 Bits[15:8] Description Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. This register is available only for comparators A and C. 0 Do not compare corresponding data bit 1 Compare corresponding data bit
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 803
Chapter 22 S12X Debug (S12XDBGV2) Module
22.3.2.8.8
Address: 0x002F
7
Debug Comparator Data Low Mask Register (DBGXDLM)
6
5
4
3
2
1
0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 22-21. Debug Comparator Data Low Mask Register (DBGXDLM)
Read: Anytime. See Table 22-27 for visible register encoding. Write: If DBG not armed. See Table 22-27 for visible register encoding.
Table 22-36. DBGXDLM Field Descriptions
Field 7–0 Bits[7:0] Description Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register is available only for comparators A and C. 0 Do not compare corresponding data bit 1 Compare corresponding data bit
22.4
Functional Description
This section provides a complete functional description of the S12XDBG module. If the part is in secure mode, the S12XDBG module can generate breakpoints but tracing is not possible.
22.4.1
S12XDBG Operation
Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the S12XCPU or the XGATE module. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the S12XCPU and XGATE modules. Comparators can be configured to monitor address and databus. Comparators can also be configured to mask out individual data bus bits during a compare and to use R/W and word/byte access qualification in the comparison. When a match with a comparator register value occurs the associated control logic can trigger the state sequencer to another state (see Figure 22-23). Either forced or tagged triggers are possible. Using a forced trigger, the trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated. Tracing of both S12XCPU and/or XGATE bus activity is possible. Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals, by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register.
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Chapter 22 S12X Debug (S12XDBGV2) Module
The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads.
TAGHITS EXTERNAL TAGHI / TAGLO XGATE S/W BREAKPOINT REQUEST SECURE COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D MATCH0 COMPARATOR MATCH CONTROL MATCH1 MATCH2 MATCH3 TRACE CONTROL TRIGGER TAG & TRIGGER CONTROL LOGIC TAGS BREAKPOINT REQUESTS S12XCPU & XGATE
TRIGGER STATE STATE SEQUENCER STATE
S12XCPU BUS
XGATE BUS
BUS INTERFACE
TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS)
Figure 22-22. S12XDBG Overview
22.4.2
Comparator Modes
The S12XDBG contains four comparators, A, B, C, and D. Each comparator can be configured to monitor either S12XCPU or XGATE buses using the SRC bit in the corresponding comparator control register. Each comparator compares the selected address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparators A and C also compare the data buses to the data stored in DBGXDH, DBGXDL and allow masking of individual data bus bits. All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (see Figure 22-22) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. On a match a trigger can initiate a transition to another state sequencer state (see Section 22.4.3”). The comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare. Only comparators B and D feature SZE and SZ. The TAG bit in each comparator control register is used to determine the triggering condition. By setting TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs
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Chapter 22 S12X Debug (S12XDBGV2) Module
before the tagged instruction executes (tagged-type trigger). Whilst tagging the RW, RWE, SZE, and SZ bits are ignored and the comparator register must be loaded with the exact opcode address. If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data value when a subsequent match occurs. Comparators C and D can also be used to select an address range to trace from. This is determined by the TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 22-10. If the TRANGE bits select a range definition using comparator D, then comparator D is configured for trace range definition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range definition using comparator C, then comparator C is configured for trace range definition and cannot be used for address bus comparisons. Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see Section 22.3.2.4”). Comparator priority rules are described in the trigger priority section (Section 22.4.3.6”).
22.4.2.1
Exact Address Comparator Match (Comparators A and C)
With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the comparator address/data registers. Further qualification of the type of access (R/W, word/byte) is possible. Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. The exact address is compared, thus with the comparator address register loaded with address (n) a misaligned word access of address (n–1) also accesses (n) but does not cause a match. Table 22-38 lists access considerations without data bus compare. Table 22-37 lists access considerations with data bus comparison. To compare byte accesses DBGXDH must be loaded with the data byte. The low byte must be masked out using the DBGXDLM mask register. On word accesses the data byte of the lower address is mapped to DBGXDH.
Table 22-37. Comparator A and C Data Bus Considerations
Access Word Byte Word Word Address ADDR[n] ADDR[n] ADDR[n] ADDR[n] DBGxDH Data[n] Data[n] Data[n] x DBGxDL Data[n+1] x x Data[n+1] DBGxDHM $FF $FF $FF $00 DBGxDLM $FF $00 $00 $FF Example Valid Match MOVW #$WORD ADDR[n] MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] MOVW #$WORD ADDR[n]
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Chapter 22 S12X Debug (S12XDBGV2) Module
Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents.
22.4.2.2
Exact Address Comparator Match (Comparators B and D)
Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the same as for comparators A and C. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified type of access causes a match. Thus if configured for a byte access of a particular address, a word access covering the same address does not lead to match.
Table 22-38. Comparator Access Size Considerations
Comparator Comparators A and C Comparators B and D Comparators B and D Comparators B and D
1
Address ADDR[n]
SZE —
SZ8 —
Condition For Valid Match Word and byte accesses of ADDR[n]1 MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word and byte accesses of ADDR[n]1 MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word accesses of ADDR[n]1 MOVW #$WORD ADDR[n] Byte accesses of ADDR[n] MOVB #$BYTE ADDR[n]
ADDR[n]
0
X
ADDR[n] ADDR[n]
1 1
0 1
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address used in the code.
22.4.2.3
Range Comparisons
When using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data and data mask registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. Similarly when using the CD comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator C data and data mask registers. Furthermore the DBGCCTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access if tagging is not selected. The corresponding DBGDCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A and C TAG bits are used to tag range comparisons for the AB and CD ranges respectively. The comparator B and D TAG bits are ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. Similarly for a range CD comparison, both COMPEC and COMPED must be set. If a range mode is selected SRCA and SRCC select the source (S12X or XGATE), SRCB and SRCD are ignored. The comparator A and C BRK bits are used for the AB and CD ranges respectively, the comparator B and D BRK bits are ignored in range mode. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.2.3.1
Inside Range (CompAC_Addr ≤ address ≤ CompBD_Addr)
In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. This configuration depends upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is inside the range. 22.4.2.3.2 Outside Range (address < CompAC_Addr or address > CompBD_Addr)
In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are from an unexpected range. In forced trigger modes the outside range trigger would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $7FFFFF or lower range limit to $000000 respectively. When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR register and hence vector address can be modified.
22.4.3
Trigger Modes
Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in the following sections.
22.4.3.1
Forced Trigger On Comparator Match
If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state for each trigger. Forced triggers are generated as soon as the matching address appears on the address bus, which in the case of opcode fetches occurs several cycles before the opcode execution. For this reason a forced trigger of an opcode address precedes a tagged trigger at the same address by several cycles.
22.4.3.2
Trigger On Comparator Related Taghit
If either a S12XCPU or XGATE taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the S12XDBG must first generate tags based on comparator matches. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the S12XCPU/XGATE. The state control register for the current state determines the next state for each trigger.
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.3.3
External Tagging Trigger
In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device emulation modes.
22.4.3.4
Trigger On XGATE S/W Breakpoint Request
The XGATE S/W breakpoint request issues a forced breakpoint request to the S12XCPU immediately independent of S12XDBG settings and triggers the state sequencer into the disarmed state. Active tracing sessions are terminated immediately, thus if tracing has not yet begun, no trace information is stored. XGATE generated breakpoints are independent of the DBGBRK bits. The XGSBPE bit in DBGC1 determines if the XGATE S/W breakpoint function is enabled. The BDM bit in DBGC1 determines if the XGATE requested breakpoint causes the system to enter BDM Mode or initiate a software interrupt (SWI).
22.4.3.5
Immediate Trigger
Independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. This triggers the state sequencer into the Final State and issues a forced breakpoint request to both S12XCPU and XGATE.
22.4.3.6
Trigger Priorities
In case of simultaneous triggers, the priority is resolved according to Table 22-39. The lower priority trigger is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger of a higher priority. The trigger priorities described in Table 22-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches independent of current state sequencer state. When configured for range modes a simultaneous match of comparators A and C generates an active match0 whilst match2 is suppressed.
Table 22-39. Trigger Priorities
Priority Highest Source XGATE TRIG External TAGHI/TAGLO Match0 (force or tag hit) Match1 (force or tag hit) Match2 (force or tag hit) Lowest Match3 (force or tag hit) Action Immediate forced breakpoint......(Tracing terminated immediately). Enter Final State Enter State0 Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.4
State Sequence Control
ARM = 0 State 0 (Disarmed) ARM = 1 State1 ARM = 0 Session Complete (Disarm) Final State ARM = 0 State3 State2
Figure 22-23. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. From Final State the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, the Final State is entered and tracing starts immediately if the TSOURCE bits are configured for tracing. A tag hit through TAGHI/TAGLO brings the state sequencer immediately into state0, causes a breakpoint, if breakpoints are enabled, and ends tracing immediately independent of the trigger alignment bits TALIGN[1:0]. Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. An XGATE S/W breakpoint request, if enabled causes a transition to the State0 and generates a breakpoint request to the S12XCPU immediately.
22.4.4.1
Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field (see Section 22.3.2.3”). If the TSOURCE bits in the trace control register DBGTCR are cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM
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Chapter 22 S12X Debug (S12XDBGV2) Module
bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed.
22.4.5
Trace Buffer Operation
The trace buffer is a 64 lines deep by 64-bits wide RAM array. The S12XDBG module stores trace information in the RAM array in a circular buffer format. The S12XCPU accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace buffer line is read via the S12XCPU, an internal pointer into the RAM is incremented so that the next read will receive fresh information. Data is stored in the format shown in Table 22-40. After each store the counter register bits DBGCNT[6:0] are incremented. Tracing of S12XCPU activity is disabled when the BDM is active but tracing of XGATE activity is still possible. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented.
22.4.5.1
Trace Trigger Alignment
Using the TALIGN bits (see Section 22.3.2.3”) it is possible to align the trigger with the end, the middle, or the beginning of a tracing session. If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered. The transition to Final State if End is selected signals the end of the tracing session. The transition to Final State if Mid is selected signals that another 32 lines will be traced before ending the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. 22.4.5.1.1 Storing with Begin-Trigger
Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the S12XDBG module will remain armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger will be stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 22.4.5.1.2 Storing with Mid-Trigger
Storing with Mid-Trigger, data is stored in the Trace Buffer as soon as the S12XDBG module is armed. When the trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the S12XDBG module is disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction the trigger event is not stored in the Trace Buffer. Using Mid-trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.5.1.3
Storing with End-Trigger
Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.
22.4.5.2
Trace Modes
The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in the DBGTCR register. In each mode tracing of XGATE or S12XCPU information is possible. The source for the trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the following subsections. The trace buffer organization is shown in Table 22-40. 22.4.5.2.1 Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored. COF addresses are defined as follows for the S12XCPU: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR, and CALL instruction. • Destination address of RTI, RTS, and RTC instructions • Vector address of interrupts, except for SWI and BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. COF addresses are defined as follows for the XGATE: • Source address of taken conditional branches • Destination address of indexed JAL instructions. • First XGATE code address in a thread Change-of-flow addresses stored include the full 23-bit address bus in the case of S12XCPU, the 16-bit address bus for the XGATE module and an information byte, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. 22.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the S12XDBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches.
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Chapter 22 S12X Debug (S12XDBGV2) Module
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the S12XDBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the background comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below:
LOOP INX BRCLR CMPTMP,#$0c, LOOP ; 1-byte instruction fetched by 1st P-cycle of BRCLR ; the BRCLR instruction also will be fetched by 1st ; P-cycle of BRCLR ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE
LOOP2
BRN NOP DBNE
* A,LOOP2
22.4.5.2.3
Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. In the case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information byte storage to the trace buffer, for each address byte storage. The information byte indicates the size of access (word or byte), the type of access (read or write). When tracing S12XCPU activity in Detail Mode, all cycles are traced except those when the S12XCPU is either in a free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide a snapshot of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity occurring at the time of the trace buffer entry. When tracing S12XCPU activity alone in Detail Mode, the address range can be limited to a range specified by the TRANGE bits in DBGTCR. This function uses comparators C and D to define an address range inside which S12XCPU activity should be traced (see Table 22-40). Thus the traced S12XCPU activity can be restricted to register range accesses. When tracing XGATE activity in Detail Mode, all load and store cycles are traced. Additionally the S12XCPU program counter is stored at the time of the XGATE trace buffer entry to provide a snapshot of S12XCPU activity. 22.4.5.2.4 Pure PC Mode
In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes are stored. In Pure PC Mode, tracing from the XGATE the PC addresses of all executed opcodes are stored.
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.5.3
Trace Buffer Organization
The buffer can be used to trace either from S12XCPU, from XGATE or from both sources. An X prefix denotes information from the XGATE module, a C prefix denotes information from the S12XCPU. ADRH, ADRM, ADRL denote address high, middle and low byte respectively. INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format for Loop1 Mode is the same as that of Normal Mode. Whilst tracing from XGATE or S12XCPU only, in Normal or Loop1 modes each array line contains data from entries made at two separate times, thus in this case the DBGCNT[0] is incremented after each separate entry. In all other modes DBGCNT[0] remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry. XGATE and S12XCPU COFs occur independently of each other and the profile of COFs for the two sources is totally different. When both sources are being traced in Normal or Loop1 mode, for each COF from one source, there may be many COFs from the other source, depending on user code. COF events could occur far from each other in the time domain, on consecutive cycles or simultaneously. When a COF occurs in either source (S12X or XGATE) a trace buffer entry is made and the corresponding CDV or XDV bit is set. The current PC of the other source is simultaneously stored to the trace buffer even if no COF has occurred, in which case CDV/XDV remains cleared indicating the address is not associated with a COF, but is simply a snapshot of the PC contents at the time of the COF from the other source. Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte3 and the byte at the higher address is stored to byte2
Table 22-40. Trace Buffer Organization
Mode 8-Byte Wide Word Buffer 7 CXINF1 CXINF2 CXINF1 CXINF2 XINF0 XINF1 XINF1 XINF3 CINF1 CINF3 CPCH1 CPCH3 6 CADRH1 CADRH2 CADRH1 CADRH2 5 CADRM1 CADRM2 CADRM1 CADRM2 XPCM0 XPCM1 XPCM1 XPCM3 CPCM1 CPCM3 4 CADRL1 CADRL2 CADRL1 CADRL2 XPCL0 XPCL1 XPCL1 XPCL3 CPCL1 CPCL3 3 XDATAH1 XDATAH2 CDATAH1 CDATAH2 CINF0 CINF1 XINF0 XINF2 CINF0 CINF2 CPCH0 CPCH2 2 XDATAL1 XDATAL2 CDATAL1 CDATAL2 CPCH0 CPCH1 1 XADRM1 XADRM2 XADRM1 XADRM2 CPCM0 CPCM1 XPCM0 XPCM2 CPCM0 CPCM2 0 XADRL1 XADRL2 XADRL1 XADRL2 CPCL0 CPCL1 XPCL0 XPCL2 CPCL0 CPCL2
XGATE Detail S12XCPU Detail Both Other Modes XGATE Other Modes S12XCPU Other Modes
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.5.3.1
Information Byte Organization
The format of the control information byte for both S12XCPU and XGATE modules is dependent upon the active trace mode and tracing source as described below. In Normal, Loop1, or Pure PC modes tracing of XGATE activity, XINF is used to store control information. In Normal, Loop1, or Pure PC modes tracing of S12XCPU activity, CINF is used to store control information. In Detail Mode, CXINF contains the control information XGATE Information Byte
Bit 7 XSD Bit 6 XSOT Bit 5 XCOT Bit 4 XDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Figure 22-24. XGATE Information Byte XINF Table 22-41. XINF Field Descriptions
Field 7 XSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing. 0 Source address 1 Destination address or Start of Thread or Continuation of Thread Source Of Thread Indicator — This bit indicates that the corresponding stored address is a start of thread address. This is only used in Normal and Loop1 mode tracing. NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels. 0 Stored address not from a start of thread 1 Stored address from a start of thread Continuation Of Thread Indicator — This bit indicates that the corresponding stored address is the first address following a return from a higher priority thread. This is only used in Normal and Loop1 mode tracing. NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels. 0 Stored address not from a continuation of thread 1 Stored address from a continuation of thread Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in Normal, Loop1 and Pure PC modes, to indicate that the XGATE trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid
6 XSOT
5 XCOT
4 XDV
X12X_CPU Information Byte
Bit 7 CSD Bit 6 CVA Bit 5 0 Bit 4 CDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Figure 22-25. S12XCPU Information Byte CINF
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Chapter 22 S12X Debug (S12XDBGV2) Module
Table 22-42. CINF Field Descriptions
Field 7 CSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing. 0 Source address 1 Destination address Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. This is only used in Normal and Loop1 mode tracing. 0 Indexed jump destination address 1 Vector destination address Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in Normal, Loop1 and Pure PC modes, to indicate that the S12XCPU trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid
6 CVA
4 CDV
CXINF Information Byte
Bit 7 CFREE Bit 6 CSZ Bit 5 CRW Bit 4 COCF Bit 3 XACK Bit 2 XSZ Bit 1 XRW Bit 0 XOCF
Figure 22-26. Information Byte CXINF
This describes the format of the information byte used only when tracing from S12XCPU or XGATE in Detail Mode. When tracing from the S12XCPU in Detail Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made by the S12XCPU, whilst the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free cycle (no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in Detail Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The S12XCPU entry stored on the same line is a snapshot of the S12XCPU program counter. In this case the XSZ and XRW bits indicate the type of access being made by the XGATE, whilst the CFREE and COCF bits indicate if the simultaneous S12XCPU cycle is a free cycle or opcode fetch cycle.
Table 22-43. CXINF Field Descriptions
Field 7 CFREE Description S12XCPU Free Cycle Indicator — This bit indicates if the stored S12XCPU address corresponds to a free cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains valid information when tracing S12XCPU activity in Detail Mode. 0 Word Access 1 Byte Access
6 CSZ
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Chapter 22 S12X Debug (S12XDBGV2) Module
Table 22-43. CXINF Field Descriptions (continued)
Field 5 CRW Description Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing S12XCPU activity in Detail Mode. 0 Write Access 1 Read Access S12XCPU Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle XGATE Access Indicator — This bit indicates if the stored XGATE address corresponds to a free cycle. This bit only contains valid information when tracing the S12XCPU accesses in Detail Mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle Access Type Indicator — This bit indicates if the access was a byte or word size access. This bit only contains valid information when tracing XGATE activity in Detail Mode. 0 Word Access 1 Byte Access Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing XGATE activity in Detail Mode. 0 Write Access 1 Read Access XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle.This bit only contains valid information when tracing the S12XCPU accesses in Detail Mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle
4 COCF
3 XACK
2 XSZ
1 XRW
0 XOCF
22.4.5.4
Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read using either the background debug module (BDM) module or the S12XCPU provided the S12XDBG module is not armed, is configured for tracing (at least one TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by an aligned word write to DBGTB when the module is disarmed. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid 64-bit lines can be determined. DBGCNT will not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1 and 0 of Table 22-40. The bytes containing invalid information (shaded in Table 22-40) are also read out.
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Chapter 22 S12X Debug (S12XDBGV2) Module
Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of the RAM pointer will occur.
22.4.5.5
Trace Buffer Reset State
The Trace Buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session. Generally debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer.
22.4.6
Tagging
A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. Each comparator control register features a TAG bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. Both S12XCPU and XGATE opcodes can be tagged with the comparator register TAG bits. Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Similarly using Mid trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated. Using End trigger, when the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring is not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. Similarly access size (SZ) monitoring and data bus monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the size of access. Thus these bits are ignored if tagged triggering is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. S12X tagging is disabled when the BDM becomes active. XGATE tagging is possible when the BDM is active.
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.6.1
External Tagging using TAGHI and TAGLO
External tagging using the external TAGHI and TAGLO pins can only be used to tag S12XCPU opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into state0 when the tagged opcode reaches the execution stage of the instruction queue. The pins operate independently, thus the state of one pin does not affect the function of the other. External tagging is possible in emulation modes only. The presence of logic level 0 on either pin at the rising edge of the external clock (ECLK) performs the function indicated in the Table 22-44. It is possible to tag both bytes of an instruction word. If a taghit occurs, a breakpoint can be generated as defined by the DBGBRK and BDM bits in DBGC1. Each time TAGHI or TAGLO are low on the rising edge of ECLK, the old tag is replaced by a new one.
Table 22-44. Tag Pin Function
TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes
22.4.6.2
Unconditional Tagging Function
In emulation modes a low assertion of PE5/TAGLO/MODA in the 7th or 8th bus cycle after reset enables the unconditional tagging function, allowing immediate tagging via TAGHI/TAGLO with breakpoint to BDM independent of the ARM, BDM and DBGBRK bits. Conversely these bits are not affected by unconditional tagging. The unconditional tagging function remains enabled until the next reset. This function allows an immediate entry to BDM in emulation modes before user code execution. The TAGLO assertion must be in the 7th or 8th bus cycle following the end of reset, whereby the prior RESET pin assertion lasts the full 192 bus cycles.
22.4.7
Breakpoints
There are several ways to generate breakpoints to the XGATE and S12XCPU modules • Through XGATE software breakpoint requests. • From comparator channel triggers to final state. • Using software to write to the TRIG bit in the DBGC1 register. • From taghits generated using the external TAGHI and TAGLO pins.
22.4.7.1
XGATE Software Breakpoints
The XGATE software breakpoint instruction BRK can request an S12XCPU breakpoint, via the S12XDBG module. In this case, if the XGSBPE bit is set, the S12XDBG module immediately generates a forced breakpoint request to the S12XCPU, the state sequencer is returned to state0 and tracing, if active, is terminated. If configured for BEGIN trigger and tracing has not yet been triggered from another source, the trace buffer contains no information. Breakpoint requests from the XGATE module do not depend upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE
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Chapter 22 S12X Debug (S12XDBGV2) Module
and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to generate breakpoints in the S12XCPU program flow, but it is necessary to set XGSBPE. Furthermore, if a breakpoint to BDM is required, the BDM bit must also be set. When the XGATE requests an S12XCPU breakpoint, the XGATE program flow stops by default, independent of the S12XDBG module.
22.4.7.2
Breakpoints From Internal Comparator Channel Final State Triggers
Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 22-45). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment.
Table 22-45. Breakpoint Setup For Both XGATE and S12XCPU Breakpoints
BRK 0 0 0 0 0 0 1 1 x TALIGN 00 00 01 01 10 10 00,01,10 00,01,10 11 DBGBRK[n] 0 1 0 1 0 1 1 0 x Breakpoint Alignment Fill Trace Buffer until trigger (no breakpoints — keep running) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints — keep running) Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full Store a further 32 Trace Buffer line entries after trigger (no breakpoints — keep running) Store a further 32 Trace Buffer line entries after trigger Request breakpoint after the 32 further Trace Buffer entries Terminate tracing and generate breakpoint immediately on trigger Terminate tracing immediately on trigger Reserved
22.4.7.3
Breakpoints Generated Via The TRIG Bit
If a TRIG triggers occur, the Final State is entered. Tracing trigger alignment is defined by the TALIGN bits. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 22-45). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if the S12XDBG module is disarmed.
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Chapter 22 S12X Debug (S12XDBGV2) Module
22.4.7.4
Breakpoints Via TAGHI Or TAGLO Pin Taghits
Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is always end aligned, independent of internal channel trigger alignment configuration.
22.4.7.5
S12XDBG Breakpoint Priorities
XGATE software breakpoints have the highest priority. Active tracing sessions are terminated immediately. If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a comparator channel, it has no effect, since tracing has already started. If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer enters state0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of the tracing trigger alignment bits TALIGN[1:0]. If a forced and tagged breakpoint coincide, the forced breakpoint occurs too late to prevent the tagged instruction being loaded into the execution unit. Conversely the taghit is too late to prevent the breakpoint request in the DBG module. Thus the S12XCPU suppresses the taghit although the tagged instruction is executed. Considering the code example below the forced breakpoint is requested when the location COUNTER is accessed. This is signalled to the S12XCPU when the next (tagged) instruction (NOP) is already in the execution stage, thus the tagged instruction is carried out but the tagged breakpoint is suppressed. Reading the PC with BDM READ_PC returns $C008
c000 c003 c004 c007 00 [BDM c008 cf ff 00 a7 72 70 08 a7 START LDS NOP INC NOP BGND BRA #$FF00 COUNTER ; Forced breakpoint location = COUNTER ; Tagged opcode location = MARK
MARK
firmware commands] 20 01
END ; 1st instruction on return from BDM
22.4.7.5.1
S12XDBG Breakpoint Priorities And BDM Interfacing
Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is active, the S12XCPU is executing out of BDM firmware and S12X breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests if the breakpoint happens to coincide with a SWI instruction in the user’s code. On returning from BDM, the SWI from user code gets executed.
Table 22-46. Breakpoint Mapping Summary
DBGBRK[1] (DBGC1[3]) 0 1 1 BDM Bit (DBGC1[4]) X 0 0 BDM Enabled X X X BDM Active X 0 1 S12X Breakpoint Mapping No Breakpoint Breakpoint to SWI No Breakpoint
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Chapter 22 S12X Debug (S12XDBGV2) Module
Table 22-46. Breakpoint Mapping Summary
1 1 1 1 1 1 0 1 1 X 0 1 Breakpoint to SWI Breakpoint to BDM No Breakpoint
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the S12XCPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal S12XCPU flow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code and DBG breakpoint could occur simultaneously. The S12XCPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re triggering a breakpoint. NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint. To avoid re triggering a breakpoint at the same location reconfigure the S12XDBG module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program flow past the tagged instruction. An XGATE software breakpoint is forced immediately, the tracing session terminated and the XGATE module execution stops. The user can thus determine if an XGATE breakpoint has occurred by reading out the XGATE program counter over the BDM interface.
MC9S12XHZ512 Data Sheet, Rev. 1.03 822 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
23.1 Introduction
This document describes the functionality of the XEBI block controlling the external bus interface. The XEBI controls the functionality of a non-multiplexed external bus (a.k.a. ‘expansion bus’) in relationship with the chip operation modes. Dependent on the mode, the external bus can be used for data exchange with external memory, peripherals or PRU, and provide visibility to the internal bus externally in combination with an emulator.
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Chapter 23 External Bus Interface (S12XEBIV3)
23.1.1
Glossary or Terms
bus clock expanded modes System Clock. Refer to CRG Block Guide. Normal Expanded Mode Emulation Single-Chip Mode Emulation Expanded Mode Special Test Mode Normal Single-Chip Mode Special Single-Chip Mode Emulation Single-Chip Mode Emulation Expanded Mode Normal Single-Chip Mode Normal Expanded Mode Special Single-Chip Mode Special Test Mode Normal Single-Chip Mode Special Single-Chip Mode Normal Expanded Mode Emulation Single-Chip Mode Emulation Expanded Mode Special Test Mode Addresses outside MCU Port Replacement Registers Port Replacement Unit External emulation memory CPU or BDM or XGATE
single-chip modes emulation modes normal modes special modes NS SS NX ES EX ST external resource PRR PRU EMULMEM access source
23.1.2
Features
The XEBI includes the following features: • Output of up to 23-bit address bus and control signals to be used with a non-muxed external bus • Bidirectional 16-bit external data bus with option to disable upper half • Visibility of internal bus activity
23.1.3
• •
Modes of Operation
•
Single-chip modes The external bus interface is not available in these modes. Expanded modes Address, data, and control signals are activated on the external bus in normal expanded mode and special test mode. Emulation modes The external bus is activated to interface to an external tool for emulation of normal expanded mode or normal single-chip mode applications.
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Chapter 23 External Bus Interface (S12XEBIV3)
Refer to the S12X_MMC section for a detailed description of the MCU operating modes.
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Chapter 23 External Bus Interface (S12XEBIV3)
23.1.4
Block Diagram
Figure 23-1 is a block diagram of the XEBI with all related I/O signals.
ADDR[22:0] DATA[15:0] IVD[15:0] LSTRB RW EWAIT XEBI UDS LDS RE WE ACC[2:0] IQSTAT[3:0]
Figure 23-1. XEBI Block Diagram
23.2
External Signal Description
NOTE The following external bus related signals are described in other sections: CS2, CS1, CS0 (chip selects) — S12X_MMC section ECLK, ECLKX2 (free-running clocks) — PIM section TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section
The user is advised to refer to the SoC section for port configuration and location of external bus signals.
Table 23-1 outlines the pin names and gives a brief description of their function. Refer to the SoC section and PIM section for reset states of these pins and associated pull-ups or pull-downs.
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Chapter 23 External Bus Interface (S12XEBIV3)
Table 23-1. External System Signals Associated with XEBI
EBI Signal Multiplex (T)ime2 (F)unction3 — T — — — T — — T — — T F Available in Modes Description NS Read Enable, indicates external read access External address Access source External address Instruction Queue Status External address Internal visibility read data (IVIS = 1) External address Internal visibility read data (IVIS = 1) — — — — — — — — — — — F F Upper Data Select, indicates external access to the high byte DATA[15:8] Low Strobe, indicates valid data on DATA[7:0] Lower Data Select, indicates external access to the low byte DATA[7:0] Read/Write, indicates the direction of internal data transfers Write Enable, indicates external write access Bidirectional data (even address) Bidirectional data (odd address) External control for external bus access stretches (adding wait states) No No No No No No No No No No No No No No No No No SS No No No No No No No No No No No No No No No No No NX Yes Yes No Yes No Yes No No No Yes No Yes No Yes Yes Yes Yes ES No Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes No EX No Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes Yes ST No Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes No
Signal
I /O
1
RE ADDR[22:20] ACC[2:0] ADDR[19:16] IQSTAT[3:0] ADDR[15:1] IVD[15:1] ADDR0 IVD0 UDS LSTRB LDS RW WE DATA[15:8] DATA[7:0] EWAIT
1 2
O O O O O O O O O O O O O O I/O I/O I
All inputs are capable of reducing input threshold level Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated time slot (in modes where applicable). 3 Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin depending on configuration and reset state.
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Chapter 23 External Bus Interface (S12XEBIV3)
23.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XEBI.
23.3.1
Module Memory Map
The registers associated with the XEBI block are shown in Figure 23-2.
Register Name 0x0E EBICTL0 0x0F EBICTL1 R W R W Bit 7 ITHRS 6 0 5 HDBE 0 4 ASIZ4 0 3 ASIZ3 0 2 ASIZ2 1 ASIZ1 Bit 0 ASIZ0
EWAITE
0
EXSTR2
EXSTR1
EXSTR0
= Unimplemented or Reserved
Figure 23-2. XEBI Register Summary
23.3.2
Register Descriptions
The following sub-sections provide a detailed description of each register and the individual register bits. All control bits can be written anytime, but this may have no effect on the related function in certain operating modes. This allows specific configurations to be set up before changing into the target operating mode. NOTE Depending on the operating mode an available function may be enabled, disabled or depend on the control register bit. Reading the register bits will reflect the status of related function only if the current operating mode allows user control. Please refer the individual bit descriptions.
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Chapter 23 External Bus Interface (S12XEBIV3)
23.3.2.1
External Bus Interface Control Register 0 (EBICTL0)
Module Base +0x000E (PRR)
7 6 5 4 3 2 1 0
R W Reset
ITHRS 0
0 0
HDBE 1
ASIZ4 1
ASIZ3 1
ASIZ2 1
ASIZ1 1
ASIZ0 1
= Unimplemented or Reserved
Figure 23-3. External Bus Interface Control Register 0 (EBICTL0)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes, the data is read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. This register controls input pin threshold level and determines the external address and data bus sizes in normal expanded mode. If not in use with the external bus interface, the related pins can be used for alternative functions. External bus is available as programmed in normal expanded mode and always full-sized in emulation modes and special test mode; function not available in single-chip modes.
Table 23-2. EBICTL0 Field Descriptions
Field 7 ITHRS Description Reduced Input Threshold — This bit selects reduced input threshold on external data bus pins and specific control input signals which are in use with the external bus interface in order to adapt to external devices with a 3.3 V, 5 V tolerant I/O. The reduced input threshold level takes effect depending on ITHRS, the operating mode and the related enable signals of the EBI pin function as summarized in Table 23-3. 0 Input threshold is at standard level on all pins 1 Reduced input threshold level enabled on pins in use with the external bus interface High Data Byte Enable — This bit enables the higher half of the 16-bit data bus. If disabled, only the lower 8-bit data bus can be used with the external bus interface. In this case the unused data pins and the data select signals (UDS and LDS) are free to be used for alternative functions. 0 DATA[15:8], UDS, and LDS disabled 1 DATA[15:8], UDS, and LDS enabled External Address Bus Size — These bits allow scalability of the external address bus. The programmed value corresponds to the number of available low-aligned address lines (refer to Table 23-4). All address lines ADDR[22:0] start up as outputs after reset in expanded modes. This needs to be taken into consideration when using alternative functions on relevant pins in applications which utilize a reduced external address bus.
5 HDBE
4–0 ASIZ[4:0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 829
Chapter 23 External Bus Interface (S12XEBIV3)
Table 23-3. Input Threshold Levels on External Signals
ITHRS External Signal DATA[15:8] TAGHI, TAGLO 0 DATA[7:0] EWAIT DATA[15:8] TAGHI, TAGLO 1 DATA[7:0] EWAIT Standard Standard Reduced if HDBE = 1 Reduced Reduced if EWAITE = 1 Standard Reduced if EWAITE = 1 Standard Standard Standard Standard NS SS NX ES Reduced Standard Reduced EX Reduced Standard Reduced Reduced ST
Standard
Table 23-4. External Address Bus Size
ASIZ[4:0] 00000 00001 00010 00011 : 10110 10111 : 11111 Available External Address Lines None UDS ADDR1, UDS ADDR[2:1], UDS : ADDR[21:1], UDS ADDR[22:1], UDS
MC9S12XHZ512 Data Sheet, Rev. 1.03 830 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
23.3.2.2
External Bus Interface Control Register 1 (EBICTL1)
Module Base +0x000F (PRR)
7 6 5 4 3 2 1 0
R W Reset
EWAITE 0
0 0
0 0
0 0
0 0
EXSTR2 1
EXSTR1 1
EXSTR0 1
= Unimplemented or Reserved
Figure 23-4. External Bus Interface Control Register 1 (EBICTL1)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data is read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. This register is used to configure the external access stretch (wait) function.
Table 23-5. EBICTL1 Field Descriptions
Field 7 EWAITE Description External Wait Enable — This bit enables the external access stretch function using the external EWAIT input pin. Enabling this feature may have effect on the minimum number of additional stretch cycles (refer to Table 23-6). External wait feature is only active if enabled in normal expanded mode and emulation expanded mode; function not available in all other operating modes. 0 External wait is disabled 1 External wait is enabled External Access Stretch Bits 2, 1, 0 — This three bit field determines the amount of additional clock stretch cycles on every access to the external address space as shown in Table 23-6. The minimum number of stretch cycles depends on the EWAITE setting. Stretch cycles are added as programmed in normal expanded mode and emulation expanded mode; function not available in all other operating modes.
2–0 EXSTR[2:0]
Table 23-6. External Access Stretch Bit Definition
Number of Stretch Cycles EXSTR[2:0] EWAITE = 0 000 001 010 011 100 101 110 111 1 cycle 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles EWAITE = 1 >= 2 cycles >= 2 cycles >= 3 cycles >= 4 cycles >= 5 cycles >= 6 cycles >= 7 cycles >= 8 cycles
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 831
Chapter 23 External Bus Interface (S12XEBIV3)
23.4
Functional Description
This section describes the functions of the external bus interface. The availability of external signals and functions in relation to the operating mode is initially summarized and described in more detail in separate sub-sections.
23.4.1
Operating Modes and External Bus Properties
Table 23-7. Summary of Functions
Single-Chip Modes Expanded Modes Normal Expanded Emulation Single-Chip Emulation Expanded Special Test
A summary of the external bus interface functions for each operating mode is shown in Table 23-7.
Properties (if Enabled)
Normal Single-Chip
Special Single-Chip
Timing Properties PRR access1 2 cycles read internal write internal — — 2 cycles read internal write internal — — 2 cycles read internal write internal — Max. of 2 to 9 programmed cycles or n cycles of ext. wait3 — Signal Properties Bus signals — — ADDR[22:1] DATA[15:0] ADDR[22:20]/A ADDR[22:20]/A CC[2:0] CC[2:0] ADDR[19:16]/ ADDR[19:16]/ IQSTAT[3:0] IQSTAT[3:0] ADDR[15:0]/ ADDR[15:0]/ IVD[15:0] IVD[15:0] DATA[15:0] DATA[15:0] ADDR0 LSTRB RW — ADDR0 LSTRB RW CS0 CS1 CS2 CS3 EWAIT DATA[15:0] EWAIT ADDR[22:0] DATA[15:0] 2 cycles read external write int & ext 1 cycle 1 cycle 2 cycles read external write int & ext 1 cycle Max. of 2 to 9 programmed cycles or n cycles of ext. wait3 1 cycle 2 cycles read internal write internal 1 cycle 1 cycle
Internal access visible externally External address access and unimplemented area access2 Flash area address access4
—
—
1 cycle
1 cycle
Data select signals (if 16-bit data bus) Data direction signals
— — —
— — —
UDS LDS RE WE CS0 CS1 CS2 CS3 EWAIT Refer to Table 23-3
ADDR0 LSTRB RW CS0 CS1 CS2 CS3 — Refer to Table 23-3
Chip Selects
External wait feature Reduced input threshold enabled on
1
— —
— —
— DATA[15:0] EWAIT
Incl. S12X_EBI registers
MC9S12XHZ512 Data Sheet, Rev. 1.03 832 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
2 3
Refer to S12X_MMC section. If EWAITE = 1, the minimum number of external bus cycles is 3. 4 Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
23.4.2
Internal Visibility
Internal visibility allows the observation of the internal CPU address and data bus as well as the determination of the access source and the CPU pipe (queue) status through the external bus interface. Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware instructions. Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see Table 23-10 to Table 23-12), internal writes on ADDRx and DATAx (see Table 23-13 to Table 23-15). RW and LSTRB show the type of access. External read data are also visible on IVDx. During ‘no access’ cycles RW is held in read position while LSTRB is undetermined. All accesses which make use of the external bus interface are considered external accesses.
23.4.2.1
Access Source Signals (ACC)
The access source can be determined from the external bus control signals ACC[2:0] as shown in Table 23-8.
Table 23-8. Determining Access Source from Control Signals
ACC[2:0] 000 001 010 011 100 101 110, 111
1
Access Description Repetition of previous access cycle CPU access BDM external access XGATE PRR access No access1 CPU access error Reserved
Denotes also CPU accesses to BDM firmware and BDM registers (IQSTATx are ‘XXXX’ and RW = 1 in these cases)
23.4.2.2
Instruction Queue Status Signals (IQSTAT)
The CPU instruction queue status (execution-start and data-movement information) is brought out as IQSTAT[3:0] signals. For decoding of the IQSTAT values, refer to the S12X_CPU section.
23.4.2.3
Internal Visibility Data (IVD)
Depending on the access size and alignment, either a word of read data is made visible on the address lines or only the related data byte will be presented in the ECLK low phase. For details refer to Table 23-9.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 833
Chapter 23 External Bus Interface (S12XEBIV3)
Invalid IVD are brought out in case of non-CPU read accesses.
Table 23-9. IVD Read Data Output
Access Word read of data at an even and even+1 address Word read of data at an odd and odd+1 internal RAM address (misaligned) Byte read of data at an even address Byte read of data at an odd address IVD[15:8] ivd(even) ivd(odd+1) ivd(even) addr[15:8] (rep.) IVD[7:0] ivd(even+1) ivd(odd) addr[7:0] (rep.) ivd(odd)
23.4.2.4
Emulation Modes Timing
A bus access lasts 1 ECLK cycle. In case of a stretched external access (emulation expanded mode), up to an infinite amount of ECLK cycles may be added. ADDRx values will only be shown in ECLK high phases, while ACCx, IQSTATx, and IVDx values will only be presented in ECLK low phases. Based on this multiplex timing, ACCx are only shown in the current (first) access cycle. IQSTATx and (for read accesses) IVDx follow in the next cycle. If the access takes more than one bus cycle, ACCx display NULL (0x000) in the second and all following cycles of the access. IQSTATx display NULL (0x0000) from the third until one cycle after the access to indicate continuation. The resulting timing pattern of the external bus signals is outlined in the following tables for read, write and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus cycles. Non-shaded bold entries denote all values related to Access #0.
MC9S12XHZ512 Data Sheet, Rev. 1.03 834 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
The following terminology is used: ‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins ‘x’ — Undefined output pin values ‘z’ — Tristate pins ‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’ 23.4.2.4.1 Read Access Timing
Table 23-10. Read Access (1 Cycle) Access #0 Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) RW ... ... ... addr 0 ? ? 1 ... ... ... ... high
Access #1 2 3
low acc 1 iqstat 0 ivd 0 z z 1 high addr 2 z data 1 1 low acc 2 iqstat 1 ivd 1 z z 1 ... ... ... ... ... ... ... ...
1
low acc 0 iqstat -1 ? z z 1 z data 0 1 addr 1 high
ADDR[19:16] / IQSTAT[3:0] ...
Table 23-11. Read Access (2 Cycles) Access #0 Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) RW ... ... ... addr 0 ? ? 1 ... ... ... ... high
Access #1 2 3
low 000 iqstat 0 x z z 1 high addr 1 z data 0 1 low acc 1 0000 ivd 0 z z 1 ... ... ... ... ... ... ... ...
1
low acc 0 iqstat-1 ? z z 1 z z 1 addr 0 high
ADDR[19:16] / IQSTAT[3:0] ...
Table 23-12. Read Access (n–1 Cycles) Access #0 Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) RW ... ... ... addr 0 ? ? 1 ... ... ... ... high
Access #1 3
... low 000 addr 0 z z 1 0000 x z z 1 ... ... ... ... ... ... ... z data 0 1 addr 1 high
1
low acc 0 iqstat-1 ? z z 1 z z 1 addr 0 high
2
low 000 iqstat 0 x z z 1 high
n
low acc 1 0000 ivd 0 z z 1
... ... ... ... ... ... ... ...
ADDR[19:16] / IQSTAT[3:0] ...
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 835
Chapter 23 External Bus Interface (S12XEBIV3)
23.4.2.4.2
Write Access Timing
Table 23-13. Write Access (1 Cycle) Access #0 Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (write) RW ... ... ... addr 0 ? 0 0 ... ... ... high
Access #1 2
high addr 1 low acc 1 iqstat 0 x data 0 1 1 data 1
Access #2 3
high addr 2 low acc 2 iqstat 1 x data 2 1 1 ... ... ... ... ... ... ...
1
low acc 0 iqstat -1 ?
ADDR[19:16] / IQSTAT[3:0] ...
Table 23-14. Write Access (2 Cycles) Access #0 Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (write) RW ... ... ... addr 0 ? 0 0 0 ... ... ... high
Access #1 2 3
low 000 iqstat 0 x data 0 0 1 high addr 1 low acc 1 0000 x x 1 ... ... ... ... ... ... ...
1
low acc 0 iqstat-1 ? addr 0 high
ADDR[19:16] / IQSTAT[3:0] ...
Table 23-15. Write Access (n–1 Cycles) Access #0 Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (write) RW ... ... ... addr 0 ? 0 0 0 0 ... ... ... high
Access #1 3
... low 000 addr 0 0000 x data 0 0 0 ... 1 ... ... ... ... addr 1 high
1
low acc 0 iqstat-1 ? addr 0 high
2
low 000 iqstat 0 x high
n
low acc 1 0000 x x 1
... ... ... ... ... ... ...
ADDR[19:16] / IQSTAT[3:0] ...
MC9S12XHZ512 Data Sheet, Rev. 1.03 836 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
23.4.2.4.3
Read-Write-Read Access Timing
Table 23-16. Interleaved Read-Write-Read Accesses (1 Cycle) Access #0 Access #1 2
low acc 0 addr 0 ? ? 1 iqstat -1 ? z z 1 z data 0 0 addr 1 high low acc 1 iqstat 0 ivd 0 (write) data 1 (write) data 1 0 1 addr 2 high
Access #2 3
low acc 2 iqstat 1 x z z 1 ... ... ... ... ... ... ... ...
Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) RW
... ... ... ... ... ... ... high
1
ADDR[19:16] / IQSTAT[3:0] ...
23.4.3
Accesses to Port Replacement Registers
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode. If writing to these addresses in emulation modes, the access is directed to both, the internal register and the external resource while reads will be treated external. The XEBI control registers also belong to this category.
23.4.4
Stretched External Bus Accesses
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI supports stretched external bus accesses (wait states). This feature is available in normal expanded mode and emulation expanded mode for accesses to all external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2 cycles, respectively.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 837
Chapter 23 External Bus Interface (S12XEBIV3)
Stretched accesses are controlled by: 1. EXSTR[2:0] bits in the EBICTL1 register configuring fixed amount of stretch cycles 2. Activation of the external wait feature by EWAITE in EBICTL1 register 3. Assertion of the external EWAIT signal when EWAITE = 1 The EXSTR[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2. An arbitrary amount of stretch cycles can be added using the EWAIT input. EWAIT needs to be asserted at least for a minimal specified time window within an external access cycle for the internal logic to detect it and add a cycle (refer to electrical characteristics). Holding it for additional cycles will cause the external bus access to be stretched accordingly. Write accesses are stretched by holding the initiator in its current state for additional cycles as programmed and controlled by external wait after the data have been driven out on the external bus. This results in an extension of time the bus signals and the related control signals are valid externally. Read data are not captured by the system in normal expanded mode until the specified setup time before the RE rising edge. Read data are not captured in emulation expanded mode until the specified setup time before the falling edge of ECLK. In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is not supported. In case the internal flash is taken out of the map in user applications, accesses are stretched as programmed and controlled by external wait.
23.4.5
Data Select and Data Direction Signals
The S12X_EBI supports byte and word accesses at any valid external address. The big endian system of the MCU is extended to the external bus; however, word accesses are restricted to even aligned addresses. The only exception is the visibility of misaligned word accesses to addresses in the internal RAM as this module exclusively supports these kind of accesses in a single cycle. With the above restriction, a fixed relationship is implied between the address parity and the dedicated bus halves where the data are accessed: DATA[15:8] is related to even addresses and DATA[7:0] is related to odd addresses. In expanded modes the data access type is externally determined by a set of control signals, i.e., data select and data direction signals, as described below. The data select signals are not available if using the external bus interface with an 8-bit data bus.
23.4.5.1
Normal Expanded Mode
In normal expanded mode, the external signals RE, WE, UDS, LDS indicate the access type (read/write), data size and alignment of an external bus access (Table 23-17).
MC9S12XHZ512 Data Sheet, Rev. 1.03 838 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
Table 23-17. Access in Normal Expanded Mode
DATA[15:8] Access Word write of data on DATA[15:0] at an even and even+1 address Byte write of data on DATA[7:0] at an odd address Byte write of data on DATA[15:8] at an even address Word read of data on DATA[15:0] at an even and even+1 address Byte read of data on DATA[7:0] at an odd address Byte read of data on DATA[15:8] at an even address Indicates No Access Unimplemented RE WE UDS LDS I/O data(addr) I/O data(addr) 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 Out data(even) Out In In In In In In In x data(even) x data(even) x x x Out In In In In In In In Out data(even) data(odd) data(odd) x data(odd) data(odd) x x x x DATA[7:0]
23.4.5.2
Emulation Modes and Special Test Mode
In emulation modes and special test mode, the external signals LSTRB, RW, and ADDR0 indicate the access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 23-18.
Table 23-18. Access in Emulation Modes and Special Test Mode
DATA[15:8] Access Word write of data on DATA[15:0] at an even and even+1 address Byte write of data on DATA[7:0] at an odd address Byte write of data on DATA[15:8] at an even address Word write at an odd and odd+1 internal RAM address (misaligned — only in emulation modes) Word read of data on DATA[15:0] at an even and even+1 address Byte read of data on DATA[7:0] at an odd address Byte read of data on DATA[15:8] at an even address Word read at an odd and odd+1 internal RAM address (misaligned - only in emulation modes) RW LSTRB ADDR0 I/O 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Out In Out data(addr) data(even) x data(odd) I/O Out Out In data(addr) data(odd) data(odd) x data(odd) data(even+1) data(odd) x data(odd) DATA[7:0]
Out data(odd+1) Out In In In In data(even) x data(even) data(odd+1) In In In In
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 839
Chapter 23 External Bus Interface (S12XEBIV3)
23.4.6
Low-Power Options
The XEBI does not support any user-controlled options for reducing power consumption.
23.4.6.1
Run Mode
The XEBI does not support any options for reducing power in run mode. Power consumption is reduced in single-chip modes due to the absence of the external bus interface. Operation in expanded modes results in a higher power consumption, however any unnecessary toggling of external bus signals is reduced to the lowest indispensable activity by holding the previous states between external accesses.
23.4.6.2
Wait Mode
The XEBI does not support any options for reducing power in wait mode.
23.4.6.3
Stop Mode
The XEBI will cease to function in stop mode.
23.5
Initialization/Application Information
This section describes the external bus interface usage and timing. Typical customer operating modes are normal expanded mode and emulation modes, specifically to be used in emulator applications. Taking the availability of the external wait feature into account the use cases are divided into four scenarios: • Normal expanded mode — External wait feature disabled – External wait feature enabled • Emulation modes – Emulation single-chip mode (without wait states) – Emulation expanded mode (with optional access stretching) Normal single-chip mode and special single-chip mode do not have an external bus. Special test mode is used for factory test only. Therefore, these modes are omitted here. All timing diagrams referred to throughout this section are available in the Electrical Characteristics appendix of the SoC section.
MC9S12XHZ512 Data Sheet, Rev. 1.03 840 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
23.5.1
Normal Expanded Mode
This mode allows interfacing to external memories or peripherals which are available in the commercial market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each external access.
23.5.1.1
Example 1a: External Wait Feature Disabled
The first example of bus timing of an external read and write access with the external wait feature disabled is shown in • Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’ The associated supply voltage dependent timing are numbers given in • Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAITE = 0)’ • Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAITE = 0)’ Systems designed this way rely on the internal programmable access stretching. These systems have predictable external memory access times. The additional stretch time can be programmed up to 8 cycles to provide longer access times.
23.5.1.2
Example 1b: External Wait Feature Enabled
The external wait operation is shown in this example. It can be used to exceed the amount of stretch cycles over the programmed number in EXSTR[2:0]. The feature must be enabled by writing EWAITE = 1. If the EWAIT signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. If EWAIT is asserted within the predefined time window during the access it will be strobed active and another stretch cycle is added. If strobed inactive, the next cycle will be the last cycle before the access is finished. EWAIT can be held asserted as long as desired to stretch the access. An access with 1 cycle stretch by EWAIT assertion is shown in • Figure ‘Example 1b: Normal Expanded Mode — Stretched Read Access’ • Figure ‘Example 1b: Normal Expanded Mode — Stretched Write Access’ The associated timing numbers for both operations are given in • Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAITE = 1)’ • Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAITE = 1)’ It is recommended to use the free-running clock (ECLK) at the fastest rate (bus clock rate) to synchronize the EWAIT input signal.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 841
Chapter 23 External Bus Interface (S12XEBIV3)
23.5.2
Emulation Modes
In emulation mode applications, the development systems use a custom PRU device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator. Accesses to a set of registers controlling the related ports in normal modes (refer to SoC section) are directed to the external bus in emulation modes which are substituted by PRR as part of the PRU. Accesses to these registers take a constant time of 2 cycles. Depending on the setting of ROMON and EROMON (refer to S12X_MMC section), the program code can be executed from internal memory or an optional external emulation memory (EMULMEM). No wait state operation (stretching) of the external bus access is done in emulation modes when accessing internal memory or emulation memory addresses. In both modes observation of the internal operation is supported through the external bus (internal visibility).
MC9S12XHZ512 Data Sheet, Rev. 1.03 842 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
23.5.2.1
Example 2a: Emulation Single-Chip Mode
This mode is used for emulation systems in which the target application is operating in normal single-chip mode. Figure 23-5 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM Emulator
PRU PRR Ports
LSTRB RW
ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] ECLK ECLKX2
Figure 23-5. Application in Emulation Single-Chip Mode
The timing diagram for this operation is shown in: • Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’ The associated timing numbers are given in: • Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAITE = 0)’ Timing considerations: • Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing. • LSTRB has the same timing as RW. • ECLKX2 rising edges have the same timing as ECLK edges. • The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 843
Chapter 23 External Bus Interface (S12XEBIV3)
23.5.2.2
Example 2b: Emulation Expanded Mode
This mode is used for emulation systems in which the target application is operating in normal expanded mode. If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals UDS, LDS, RE, and WE from the ADDR0, LSTRB, and RW signals. Figure 23-6 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM Emulator
PRU PRR Ports
LSTRB RW
UDS LDS RE WE
ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] EWAIT ECLK ECLKX2 CS[2:0]
Figure 23-6. Application in Emulation Expanded Mode
The timings of accesses with 1 stretch cycle are shown in • Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’ • Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’ The associated timing numbers are given in • Table ‘Example 2b: Emulation Expanded Mode Timing VDD5 = 5.0 V (EWAITE = 0)’ (this also includes examples for alternative settings of 2 and 3 additional stretch cycles) Timing considerations: • If no stretch cycle is added, the timing is the same as in Emulation Single-Chip Mode.
MC9S12XHZ512 Data Sheet, Rev. 1.03 844 Freescale Semiconductor
Chapter 23 External Bus Interface (S12XEBIV3)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 845
Chapter 23 External Bus Interface (S12XEBIV3)
MC9S12XHZ512 Data Sheet, Rev. 1.03 846 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
24.1 Introduction
The XINT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to either the CPU or the XGATE module. The XINT module supports: • I bit and X bit maskable interrupt requests • A non-maskable unimplemented opcode trap • A non-maskable software interrupt (SWI) or background debug mode request • A spurious interrupt vector request • Three system reset vector requests Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be handled by the XGATE module cannot be nested because the XGATE module cannot be interrupted while processing. NOTE The HPRIO register and functionality of the XINT module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 847
Chapter 24 Interrupt (S12XINTV1)
24.1.1
Glossary
The following terms and abbreviations are used in the document.
Table 24-1. Terminology Term CCR DMA INT IPL ISR MCU XGATE IRQ XIRQ Meaning
Condition Code Register (in the S12X CPU) Direct Memory Access Interrupt Interrupt Processing Level Interrupt Service Routine Micro-Controller Unit please refer to the "XGATE Block Guide" refers to the interrupt request associated with the IRQ pin refers to the interrupt request associated with the XIRQ pin
24.1.2
• • • • • • • • • • • •
Features
Interrupt vector base register (IVBR) One spurious interrupt vector (at address vector base1 + 0x0010). 2–113 I bit maskable interrupt vector requests (at addresses vector base + 0x0012–0x00F2). Each I bit maskable interrupt request has a configurable priority level and can be configured to be handled by either the CPU or the XGATE module2. I bit maskable interrupts can be nested, depending on their priority levels. One X bit maskable interrupt vector request (at address vector base + 0x00F4). One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base + 0x00F6). One non-maskable unimplemented opcode trap (TRAP) vector (at address vector base + 0x00F8). Three system reset vectors (at addresses 0xFFFA–0xFFFE). Determines the highest priority DMA and interrupt vector requests, drives the vector to the XGATE module or to the bus on CPU request, respectively. Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever XIRQ is asserted, even if X interrupt is masked. XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
24.1.3
•
Modes of Operation
Run mode This is the basic mode of operation.
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). 2. The IRQ interrupt can only be handled by the CPU MC9S12XHZ512 Data Sheet, Rev. 1.03 848 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
•
•
•
Wait mode In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 24.5.3, “Wake Up from Stop or Wait Mode” for details. Stop Mode In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 24.5.3, “Wake Up from Stop or Wait Mode” for details. Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 24.3.1.1, “Interrupt Vector Base Register (IVBR)” for details.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 849
Chapter 24 Interrupt (S12XINTV1)
24.1.4
Block Diagram
Figure 24-1 shows a block diagram of the XINT module.
Peripheral Interrupt Requests Wake Up CPU
Non I Bit Maskable Channels Vector Address Priority Decoder
IRQ Channel
IVBR New IPL Current IPL
Interrupt Requests PRIOLVL2 PRIOLVL1 PRIOLVL0
RQST One Set Per Channel (Up to 112 Channels)
INT_XGPRIO XGATE Requests Priority Decoder Wake up XGATE Vector ID XGATE Interrupts RQST DMA Request Route, PRIOLVLn Priority Level = bits from the channel configuration in the associated configuration register INT_XGPRIO = XGATE Interrupt Priority IVBR = Interrupt Vector Base IPL = Interrupt Processing Level
To XGATE Module
Figure 24-1. XINT Block Diagram
MC9S12XHZ512 Data Sheet, Rev. 1.03 850 Freescale Semiconductor
To CPU
Chapter 24 Interrupt (S12XINTV1)
24.2
External Signal Description
The XINT module has no external signals.
24.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XINT.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 851
Chapter 24 Interrupt (S12XINTV1)
24.3.1
Register Descriptions
This section describes in address order all the XINT registers and their individual bits.
Offset Address 0x1 Register Name IVBR R W 0x6 INT_XGPRIO R W 0x7 INT_CFADDR R W 0x8 INT_CFDATA0 R W 0x9 INT_CFDATA1 R W 0xA INT_CFDATA2 R W 0xB INT_CFDATA3 R W 0xC INT_CFDATA4 R W 0xD INT_CFDATA5 R W 0xE INT_CFDATA6 R W 0xF INT_CFDATA7 R W RQST INT_CFADDR[7:4] 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0
IVB_ADDR[7:0] 0 0
XILVL[2:0] 0 0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
= Unimplemented or Reserved
Figure 24-2. XINT Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.03 852 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
24.3.1.1
Interrupt Vector Base Register (IVBR)
Offset Address: 0x1
7 6 5 4 3 2 1 0
R W Reset 1 1 1
IVB_ADDR[7:0] 1 1 1 1 1
Figure 24-3. Interrupt Vector Base Register (IVBR)
Read: Anytime Write: Anytime
Table 24-2. IVBR Field Descriptions
Field Description
7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to HCS12. Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset vectors (0xFFFA–0xFFFE). Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 853
Chapter 24 Interrupt (S12XINTV1)
24.3.1.2
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Offset Address: 0x6
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0
XILVL[2:0] 0 1
= Unimplemented or Reserved
Figure 24-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime Write: Anytime
Table 24-3. INT_XGPRIO Field Descriptions
Field 2–0 XILVL[2:0] Description XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the DMA interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Table 24-4. XGATE Interrupt Priority Levels
Priority XILVL2 0 low 0 0 0 1 1 1 high 1 XILVL1 0 0 1 1 0 0 1 1 XILVL0 0 1 0 1 0 1 0 1 Meaning Interrupt request is disabled Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7
MC9S12XHZ512 Data Sheet, Rev. 1.03 854 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
24.3.1.3
Interrupt Request Configuration Address Register (INT_CFADDR)
Offset Address: 0x7
7 6 5 4 3 2 1 0
R W Reset 0
INT_CFADDR[7:4] 0 0 1
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 24-5. Interrupt Configuration Address Register (INT_CFADDR)
Read: Anytime Write: Anytime
Table 24-5. INT_CFADDR Field Descriptions
Field Description
7–4 Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128 INT_CFADDR[7:4] configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal value written to this register corresponds to the upper nibble of the lower byte of the interrupt vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector requests starting with vector (vector base + 0x00E0) to be accessible as INT_CFDATA0–7. Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to INT_CFDATA0–7 will be ignored and read accesses will return all 0.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 855
Chapter 24 Interrupt (S12XINTV1)
24.3.1.4
Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt configuration data register of the vector with the highest address, respectively.
Offset Address: 0x8
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Offset Address: 0x9
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-7. Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Offset Address: 0xA
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-8. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Offset Address: 0xB
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-9. Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
MC9S12XHZ512 Data Sheet, Rev. 1.03 856 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
Offset Address: 0xC
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Offset Address: 0xD
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-11. Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Offset Address: 0xE
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-12. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Offset Address: 0xF
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 24-13. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Read: Anytime Write: Anytime
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 857
Chapter 24 Interrupt (S12XINTV1)
Table 24-6. INT_CFDATA0–7 Field Descriptions
Field 7 RQST Description XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by the XGATE module. 0 Interrupt request is handled by the CPU 1 Interrupt request is handled by the XGATE module Note: The IRQ interrupt cannot be handled by the XGATE module. For this reason, the configuration register for vector (vector base + 0x00F2) = IRQ vector address) does not contain a RQST bit. Writing a 1 to the location of the RQST bit in this register will be ignored and a read access will return 0.
2–0 Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of PRIOLVL[2:0] the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”) to provide backwards compatibility with previous HCS12 interrupt controllers. Please also refer to Table 24-7 for available interrupt request priority levels. Note: Write accesses to configuration data registers of unused interrupt channels will be ignored and read accesses will return all 0. For information about what interrupt channels are used in a specific MCU, please refer to the Device User Guide of that MCU. Note: When vectors (vector base + 0x00F0–0x00FE) are selected by writing 0xF0 to INT_CFADDR, writes to INT_CFDATA2–7 (0x00F4–0x00FE) will be ignored and read accesses will return all 0s. The corresponding vectors do not have configuration data registers associated with them. Note: Write accesses to the configuration register for the spurious interrupt vector request (vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the CPU, PRIOLVL = 7).
Table 24-7. Interrupt Priority Levels
Priority PRIOLVL2 0 low 0 0 0 1 1 1 high 1 PRIOLVL1 0 0 1 1 0 0 1 1 PRIOLVL0 0 1 0 1 0 1 0 1 Meaning Interrupt request is disabled Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7
MC9S12XHZ512 Data Sheet, Rev. 1.03 858 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
24.4
Functional Description
The XINT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.
24.4.1
S12X Exception Requests
The CPU handles both reset requests and interrupt requests. The XINT contains registers to configure the priority level of each I bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the priority of a pending interrupt request.
24.4.2
Interrupt Prioritization
After system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00F2) are enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. The exception to this rule is the spurious interrupt vector request at (vector base + 0x0010) which cannot be disabled, is always handled by the CPU and has a fixed priority level of 7. A priority level of 0 effectively disables the associated interrupt request. If more than one interrupt request is configured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization. The following conditions must be met for an I bit maskable interrupt request to be processed. 1. The local interrupt enabled bit in the peripheral module must be set. 2. The setup in the configuration register associated with the interrupt request channel must meet the following conditions: a) The XGATE request enable bit must be 0 to have the CPU handle the interrupt request. b) The priority level must be set to non zero. c) The priority level must be greater than the current interrupt processing level in the condition code register (CCR) of the CPU (PRIOLVL[2:0] > IPL[2:0]). 3. The I bit in the condition code register (CCR) of the CPU must be cleared. 4. There is no SWI, TRAP, or XIRQ request pending. NOTE All non I bit maskable interrupt requests always have higher priority than I bit maskable interrupt requests. If an I bit maskable interrupt request is interrupted by a non I bit maskable interrupt request, the currently active interrupt processing level (IPL) remains unaffected. It is possible to nest non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 859
Chapter 24 Interrupt (S12XINTV1)
24.4.2.1
Interrupt Priority Stack
The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.
24.4.3
XGATE Requests
The XINT module processes all exception requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed in the subsections below.
24.4.3.1
XGATE Request Prioritization
An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the associated configuration register is set to 1 (please refer to Section 24.3.1.4, “Interrupt Request Configuration Data Registers (INT_CFDATA0–7)”). The priority level setting (PRIOLVL) for this channel becomes the DMA priority which will be used to determine the highest priority DMA request to be serviced next by the XGATE module. Additionally, DMA interrupts may be raised by the XGATE module by setting one or more of the XGATE channel interrupt flags (using the SIF instruction). This will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST bits are set. The shared interrupt priority for the DMA interrupt requests is taken from the XGATE interrupt priority configuration register (please refer to Section 24.3.1.2, “XGATE Interrupt Priority Configuration Register (INT_XGPRIO)”). If more than one DMA interrupt request channel becomes active at the same time, the channel with the highest vector address wins the prioritization.
24.4.4
Priority Decoders
The XINT module contains priority decoders to determine the priority for all interrupt requests pending for the respective target. There are two priority decoders, one for each interrupt request target (CPU, XGATE module). The function of both priority decoders is basically the same with one exception: the priority decoder for the XGATE module does not take the current interrupt processing level into account because XGATE requests cannot be nested. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception instead of the original request.
MC9S12XHZ512 Data Sheet, Rev. 1.03 860 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector. NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)).
24.4.5
Reset Exception Requests
The XINT supports three system reset exception request types (please refer to CRG for details): 1. Pin reset, power-on reset, low-voltage reset, or illegal address reset 2. Clock monitor reset request 3. COP watchdog reset request
24.4.6
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the XINT upon request by the CPU is shown in Table 24-8.
Table 24-8. Exception Vector Map and Priority
Vector Address1 0xFFFE 0xFFFC 0xFFFA (Vector base + 0x00F8) (Vector base + 0x00F6) (Vector base + 0x00F4) (Vector base + 0x00F2) Source Pin reset, power-on reset, low-voltage reset, illegal address reset Clock monitor reset COP watchdog reset Unimplemented opcode trap Software interrupt instruction (SWI) or BDM vector request XIRQ interrupt request IRQ interrupt request
(Vector base + 0x00F0–0x0012) Device specific I bit maskable interrupt sources (priority determined by the associated configuration registers, in descending order) (Vector base + 0x0010)
1
Spurious interrupt
16 bits vector address based
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 861
Chapter 24 Interrupt (S12XINTV1)
24.5
24.5.1
Initialization/Application Information
Initialization
After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests. • If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and configure the XGATE module (please refer the XGATE Block Guide for details). • Enable I maskable interrupts by clearing the I bit in the CCR. • Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
24.5.2
Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the I bit maskable interrupt requests handled by the CPU. • I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to Figure 24-14 for an example using up to three nested interrupt requests). I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can interrupt the current ISR. An ISR of an interruptible I bit maskable interrupt request could basically look like this: • Service interrupt, e.g., clear interrupt flags, copy data, etc. • Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI
MC9S12XHZ512 Data Sheet, Rev. 1.03 862 Freescale Semiconductor
Chapter 24 Interrupt (S12XINTV1)
0 Stacked IPL 0 4 0 0 0
IPL in CCR 7 6 5 4 Processing Levels 3 2 1 0
0
4
7
4
3
1
0
L7
RTI
RTI L3 (Pending) L4 L1 (Pending) Reset RTI RTI
Figure 24-14. Interrupt Processing Example
24.5.3
24.5.3.1
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode: • If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU. • An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the current IPL in CCR. • I bit maskable interrupt requests which are configured to be handled by the XGATE are not capable of waking up the CPU. An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set.
24.5.3.2
XGATE Wake Up from Stop or Wait Mode
Interrupt request channels which are configured to be handled by the XGATE are capable of waking up the XGATE. Interrupt request channels handled by the XGATE do not affect the state of the CPU.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 863
Chapter 24 Interrupt (S12XINTV1)
MC9S12XHZ512 Data Sheet, Rev. 1.03 864 Freescale Semiconductor
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is shown in Figure 25-1. The MMC module controls the multi-master priority accesses, the selection of internal resources and external space. Internal buses, including internal memories and peripherals, are controlled in this module. The local address space for each master is translated to a global memory space.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 865
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.1.1
Terminology
Table 25-1. Acronyms and Abbreviations
Logic level “1” Logic level “0” 0x x byte word local address global address Aligned address Voltage that corresponds to Boolean true state Voltage that corresponds to Boolean false state Represents hexadecimal number Represents logic level ’don’t care’ 8-bit data 16-bit data based on the 64 KBytes Memory Space (16-bit address) based on the 8 MBytes Memory Space (23-bit address) Address on even boundary Address on odd boundary System Clock. Refer to CRG Block Guide. Normal Expanded Mode Emulation Single-Chip Mode Emulation Expanded Mode Special Test Mode Normal Single-Chip Mode Special Single-Chip Mode Emulation Single-Chip Mode Emulation Expanded Mode Normal Single-Chip Mode Normal Expanded Mode Special Single-Chip Mode Special Test Mode Normal Single-Chip Mode Special Single-Chip Mode Normal Expanded Mode Emulation Single-Chip Mode Emulation Expanded Mode Special Test Mode Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented Area which is accessible in the global address range 14_0000 to 3F_FFFF Resources (Emulator, Application) connected to the MCU via the external bus on expanded modes (Unimplemented areas and External Space) Port Replacement Registers Port Replacement Unit located on the emulator side MicroController Unit Non-volatile Memory; Flash EEPROM or ROM FlexRay IP Integration module
Mis-aligned address Bus Clock expanded modes
single-chip modes emulation modes normal modes special modes NS SS NX ES EX ST Unimplemented areas External Space external resource PRR PRU MCU NVM FLEXRAY
25.1.2
Features
The main features of this block are: • Paging capability to support a global 8 Mbytes memory address space • Bus arbitration between the masters CPU, BDM, FLEXRAY and XGATE
MC9S12XHZ512 Data Sheet, Rev. 1.03 866 Freescale Semiconductor
Chapter 25 Memory Mapping Control (S12XMMCV3)
• • • • • • • • •
Simultaneous accesses to different resources1 (internal, external, and peripherals) (see Figure 25-1) Resolution of target bus access collision Access restriction control from masters to some targets (e.g., RAM write access protection for user specified areas) MCU operation mode control MCU security control Separate memory map schemes for each master CPU, BDM, FLEXRAY and XGATE ROM control bits to enable the on-chip FLASH or ROM selection Port replacement registers access control Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes
25.1.3
S12X Memory Mapping
The S12X architecture implements a number of memory mapping schemes including • a CPU 8 MByte global map, defined using a global page (GPAGE) register and dedicated 23-bit address load/store instructions. • a BDM 8 MByte global map, defined using a global page (BDMGPR) register and dedicated 23-bit address load/store instructions. • FLEXRAY 8 MByte global map. • a (CPU or BDM) 64 KByte local map, defined using specific resource page (RPAGE, EPAGE and PPAGE) registers and the default instruction set. The 64 KBytes visible at any instant can be considered as the local map accessed by the 16-bit (CPU or BDM) address. • The XGATE 64 Kbyte local map. The MMC module performs translation of the different memory mapping schemes to the specific global (physical) memory implementation.
25.1.4
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the MMC.
25.1.4.1
• • •
Power Saving Modes
Run mode MMC is functional during normal run mode. Wait mode MMC is functional during wait mode. Stop mode MMC is inactive during stop mode.
1. Resources are also called targets.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 867
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.1.4.2
• •
Functional Modes
•
Single chip modes In normal and special single chip mode the internal memory is used. External bus is not active. Expanded modes Address, data, and control signals are activated in normal expanded and special test modes when accessing the external bus. Access to internal resources will not cause activity on the external bus. Emulation modes External bus is active to emulate, via an external tool, the normal expanded or the normal single chip mode.
25.1.5
Block Diagram
Figure 25-11 shows a block diagram of the MMC.
BDM EEPROM MMC FLASH
CPU
XGATE
FLEXRAY
Address Decoder & Priority
DBG
Target Bus Controller
EBI
RAM
Peripherals
Figure 25-1. MMC Block Diagram
25.2
External Signal Description
The user is advised to refer to the SoC Guide for port configuration and location of external bus signals. Some pins may not be bonded out in all implementations. Table 25-2 and Table 25-3 outline the pin names and functions. It also provides a brief description of their operation.
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities. MC9S12XHZ512 Data Sheet, Rev. 1.03 868 Freescale Semiconductor
Chapter 25 Memory Mapping Control (S12XMMCV3)
Table 25-2. External Input Signals Associated with the MMC
Signal MODC MODB MODA EROMCTL ROMCTL I/O I I I I I Description Mode input Mode input Mode input EROM control input ROM control input Availability Latched after RESET (active low) Latched after RESET (active low) Latched after RESET (active low) Latched after RESET (active low) Latched after RESET (active low)
Table 25-3. External Output Signals Associated with the MMC
Available in Modes Signal CS0 CS1 CS2 CS3 I/O O O O O Description NS Chip select line 0 Chip select line 1 Chip select line 2 Chip select line 3 SS NX ES EX ST (see Table 25-4)
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 869
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.3
25.3.1
Memory Map and Registers
Module Memory Map
A summary of the registers associated with the MMC block is shown in Figure 25-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
Address 0x000A Register Name MMCCTL0 R W 0x000B MODE R W 0x0010 GPAGE R W 0x0011 DIRECT R W 0x0012 Reserved R W 0x0013 MMCCTL1 R W 0x0014 Reserved R W 0x0015 Reserved R W 0x0016 RPAGE R W 0x0017 EPAGE R W 0x0018 RAMFRL R W 0x0019 RAMFRU R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 0 6 0 5 0 4 0 3 CS3E 0 2 CS2E 0 1 CS1E 0 Bit 0 CS0E 0
MODC 0
MODB
MODA
GP6
GP5
GP4
GP3
GP2
GP1
GP0
DP15 0
DP14 0
DP13 0
DP12 0
DP11 0
DP10 0
DP9 0
DP8 0
EROMON 0
ROMHM 0
ROMON 0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
FRL7
FRL6
FRL5
FRL4
FRL3
FRL2
FRL1
FRL0
FRU7
FRU6
FRU5
FRU4
FRU3
FRU2
FRU1
FRU0
= Unimplemented or Reserved
Figure 25-2. MMC Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.03 870 Freescale Semiconductor
Chapter 25 Memory Mapping Control (S12XMMCV3)
Address 0x0030
Register Name PPAGE R W
Bit 7 PIX7 0
6 PIX6 0
5 PIX5 0
4 PIX4 0
3 PIX3 0
2 PIX2 0
1 PIX1 0
Bit 0 PIX0 0
0x0031
Reserved
R W
0x011C
RAMWPC
R W
RPWE 1
0
0
0
FRCPU
FRXG
AVIE
AVIF
0x011D
RAMXGU
R W
XGU6
XGU5
XGU4
XGU3
XGU2
XGU1
XGU0
0x011E
RAMSHL
R W
1
SHL6
SHL5
SHL4
SHL3
SHL2
SHL1
SHL0
0x011F
RAMSHU
R W
1
SHU6
SHU5
SHU4
SHU3
SHU2
SHU1
SHU0
= Unimplemented or Reserved
Figure 25-2. MMC Register Summary
25.3.2
25.3.2.1
Register Descriptions
MMC Control Register (MMCCTL0)
Address: 0x000A PRR
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
CS3E 0
CS2E 0
CS1E 0
CS0E ROMON1
1. ROMON is bit[0] of the register MMCTL1 (see Figure 25-10) = Unimplemented or Reserved
Figure 25-3. MMC Control Register (MMCCTL0)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other modes the data is read from this register. Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Table 25-4. Chip Selects Function Activity
Chip Modes Register Bit NS CS3E, CS2E, CS1E, CS0E Disabled1 SS Disabled NX Enabled2 ES Disabled EX Enabled ST Enabled
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 871
Chapter 25 Memory Mapping Control (S12XMMCV3)
1 2
Disabled: feature always inactive. Enabled: activity is controlled by the appropriate register bit value.
The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results.
Table 25-5. MMCCTL0 Field Descriptions
Field 3–0 CS[3:0]E Description Chip Select Enables — Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0 outputs which are asserted during accesses to specific external addresses. The associated global address ranges are shown in Table 25-6 and Table 25-24 and Figure 25-23. Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test mode. The function disabled in all other operating modes. 0 Chip select is disabled 1 Chip select is enabled
Table 25-6. Chip Select Signals
Global Address Range 0x00_0800–0x0F_FFFF 0x10_0000–0x1F_FFFF 0x20_0000–0x3F_FFFF 0x40_0000–0x7F_FFFF
1
Asserted Signal CS3 CS2 CS1 CS01
When the internal NVM is enabled (see ROMON in Section 25.3.2.5, “MMC Control Register (MMCCTL1)) the CS0 is not asserted in the space occupied by this on-chip memory block.
MC9S12XHZ512 Data Sheet, Rev. 1.03 872 Freescale Semiconductor
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.3.2.2
Mode Register (MODE)
Address: 0x000B PRR
7 6 5 4 3 2 1 0
R W Reset
MODC MODC1
MODB MODB1
MODA MODA1
0 0
0 0
0 0
0 0
0 0
1. External signal (see Table 25-2). = Unimplemented or Reserved
Figure 25-4. Mode Register (MODE)
Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all other modes the data are read from this register.
Write: Only if a transition is allowed (see Figure 25-5). In emulation modes write operations will be also directed to the external bus.
The MODE bits of the MODE register are used to establish the MCU operating mode. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results.
Table 25-7. MODE Field Descriptions
Field 7–5 MODC, MODB, MODA Description Mode Select Bits — These bits control the current operating mode during RESET high (inactive). The external mode pins MODC, MODB, and MODA determine the operating mode during RESET low (active). The state of the pins is latched into the respective register bits after the RESET signal goes inactive (see Figure 25-5). Write restrictions exist to disallow transitions between certain modes. Figure 25-5 illustrates all allowed mode changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to these register bits except in special modes. Both transitions from normal single-chip mode to normal expanded mode and from emulation single-chip to emulation expanded mode are only executed by writing a value of 3’b101 (write once). Writing any other value will not change the MODE bits, but will block further writes to these register bits. Changes of operating modes are not allowed when the device is secured, but it will block further writes to these register bits except in special modes. In emulation modes reading this address returns data from the external bus which has to be driven by the emulator. It is therefore responsibility of the emulator hardware to provide the expected value (i.e. a value corresponding to normal single chip mode while the device is in emulation single-chip mode or a value corresponding to normal expanded mode while the device is in emulation expanded mode).
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 873
Chapter 25 Memory Mapping Control (S12XMMCV3)
RESET
010 Special Test (ST) 010
10
10
0
1
1
01
00
1
Normal Expanded (NX) 101 010 000
RESET
100 110 111
Normal Single-Chip (NS) 100
101
101 RESET
001 RESET
10
1
Emulation Single-Chip (ES) 001
101
Emulation Expanded (EX) 011
011 RESET
10 0
Special Single-Chip (SS) 000 000
RESET
Transition done by external pins (MODC, MODB, MODA)
RESET
Transition done by write access to the MODE register 110 111 Illegal (MODC, MODB, MODA) pin values. Do not use. (Reserved for future use).
Figure 25-5. Mode Transition Diagram when MCU is Unsecured
MC9S12XHZ512 Data Sheet, Rev. 1.03 874 Freescale Semiconductor
01
00 1
1
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.3.2.3
Global Page Index Register (GPAGE)
Address: 0x0010
7 6 5 4 3 2 1 0
R W Reset
0 0
GP6 0
GP5 0
GP4 0
GP3 0
GP2 0
GP1 0
GP0 0
= Unimplemented or Reserved
Figure 25-6. Global Page Index Register (GPAGE)
Read: Anytime Write: Anytime The global page index register is used to construct a 23 bit address in the global map format. It is only used when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see Figure 25-7). CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results.
Global Address [22:0]
Bit22
Bit16 Bit15
Bit 0
GPAGE Register [6:0]
CPU Address [15:0]
Figure 25-7. GPAGE Address Mapping Table 25-8. GPAGE Field Descriptions
Field 6–0 GP[6:0] Description Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is to be accessed.
Example 25-1. This example demonstrates usage of the GPAGE register
LDX MOVB GLDAA #0x5000 #0x14, GPAGE X ;Set GPAGE offset to the value of 0x5000 ;Initialize GPAGE register with the value of 0x14 ;Load Accu A from the global address 0x14_5000
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 875
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.3.2.4
Direct Page Register (DIRECT)
Address: 0x0011
7 6 5 4 3 2 1 0
R W Reset
DP15 0
DP14 0
DP13 0
DP12 0
DP11 0
DP10 0
DP9 0
DP8 0
Figure 25-8. Direct Register (DIRECT)
Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme.
Table 25-9. DIRECT Field Descriptions
Field 7–0 DP[15:8] Description Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. The bits from this register form bits [15:8] of the address (see Figure 25-9).
CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results.
Global Address [22:0]
Bit22
Bit16 Bit15
Bit8
Bit7
Bit0
DP [15:8] CPU Address [15:0]
Figure 25-9. DIRECT Address Mapping
Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global instruction in direct addressing mode or by the appropriate local address to the global address expansion (refer to Section 25.4.2.1.1, “Expansion of the Local Address Map).
Example 25-2. This example demonstrates usage of the Direct Addressing Mode
MOVB #0x80,DIRECT ;Set DIRECT register to 0x80. Write once only. ;Global data accesses to the range 0xXX_80XX can be direct. ;Logical data accesses to the range 0x80XX are direct. ;Load the Y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are “direct page aware” and can MC9S12XHZ512 Data Sheet, Rev. 1.03 876 Freescale Semiconductor
LDY
0x0F_RAMFRU_FF System Reaction flexray_ill_access = 1 and s12x_vaddr_flexray = 1
In the case of illegal S12X_FLEXRAY access to protected memory areas, no targets receive a request. This transaction will be acknowledged (s12x_vaddr_flexray = 1) but not performed.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 923
Chapter 25 Memory Mapping Control (S12XMMCV3)
25.6.7
Priority Scheme
Table 25-39. Priority scheme applied to each target bus
XBUS0 (FTX0, EETX, BDM) available ✘ available ✘ available ✘ ✘ available XBUS1 (FTX1) XBUS2 (IPBI). XBUS3 (S12X_EBI). XRAM (XSRAM)
Table 25-39 describes the target priority scheme starting from higher to lower priority.
Priority Level
Target busy FLEXRAY (High priority) BDM (High priority) XGATE (PRR) CPU XGATE FLEXRAY BDM
available ✘ ✘ ✘ ✘ available ✘ ✘
available ✘ available available available available ✘ available
available ✘ available available available ✘ ✘ available
available available for read available for read ✘ available for read available available for read available for read
Table 25-40 describes the RAM target priority scheme starting from higher to lower priority in case of
Table 25-40. Priority scheme applied to RAM
Priority Level Target busy FLEXRAY (High priority) BDM (High priority) XGATE (PRR) CPU FLEXRAY BDM XGATE XRAM (XSRAM) available available for write available for write ✘ available for write available for write available for write available
S12X mastere write accesses.
MC9S12XHZ512 Data Sheet, Rev. 1.03 924 Freescale Semiconductor
Chapter 25 Memory Mapping Control (S12XMMCV3)
Some masters do have access limitation to some targets; all authorized target accesses to a specific master are noted by “available”. All restricted target accesses are noted by “✘: not available”. The winner of the priority scheme is granted to access the target. This access preforms if no protection error set. In case of protection error, no other master can access this target.
25.6.8
XBUS0
The XBUS0 is an XBUS protocol type Short (default) connected to the targets (FTX,EETX and S12X_BDM). The access types of the XBUS0 are bytes or aligned words. FTX, EETX are accessible only when the device is not secured “in expanded modes”. S12X_BDM resources are accessible only in case of firmware or hardware accesses. FTX, EETX and S12X_BDM select-lines (xbus0_sel_ftx, xbus0_sel_eetx, xbus0_sel_bdm) are “mutually exclusive”.
25.6.9
XBUS1
The XBUS1 is an XBUS protocol type Short (default) connected to the targets FTX for the BLKX (see Section , “MCU_XGATE_FTX_ACC). The access types of the XBUS1 are aligned words. XBUS1 is a read only bus. XBUS0 access to the BLKX FLASH address range (xbus0_sel_ftx = 1) has high priority than XBUS1 access to the same address range (xbus1_sel_ftx = 0).
25.6.10 XBUS2
The XBUS2 is an XBUS protocol type Short (default) connected to the target IPBI. The access types of the XBUS2 are bytes or aligned words. XBUS2 is busy (xbus2_sel_ipbi = 0) during the cycle the xbus2_data_wait = 1.
25.6.11 XBUS3
The XBUS3 is an XBUS protocol type Long connected to the target S12X_EBI, which has to keep resources in the whole T2 period (due to the external bus timing). This bus supports two types of selects: 1. xbus3_sel_long_ebi: is set when an external access occurs. 2. xbus3_vis_ebi: is set when S12X_CPU is doing a transaction to a specific target even external (see Section 25.6.3.4, “Internal Visibility). when xbus3_sel_long_ebi = 1, the allowed access types are bytes or aligned words. when xbus3_vis_ebi = 1, the access types are bytes, aligned word, misaligned word (in case of XSRAM accesses). Two signals are sent to S12X_EBI to be used by the “system stretch mechanism logic”.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 925
Chapter 25 Memory Mapping Control (S12XMMCV3)
• •
mmc_acc_emul_mem: This signal is set when the external access to the emulated memory needs to be processed always in one cycle (stretch 0 cycle). mmc_acc_prr: This signal is set when the access to PRRs is performed in emulation mode. It informs S12X_EBI to do this access for two cycles (stretch 1 cycle).
One signal is sent to S12X_EBI to provide the actual master access information to the external bus.
Table 25-41. MASTER ACCESS to External Bus Interface
mmc_ebi_acc(2) 0 0 mmc_ebi_acc(1) 0 0 mmc_ebi_acc(0) 0 1 Description Repetition of the previous access only if xbus3_acc_wait = 1 except the first cycle. CPU address shown to the external bus address only if (xbus3_sel_vis = 1) only during the first cycle BDM address shown to the external bus address only if (xbus3_sel_long_ebi = 1) only during the first cycle XGATE address shown to the external bus address only if (xbus3_sel_long_ebi = 1) only during the first cycle Noacc (xbus3_sel_long_ebi = 0) and (xbus3_sel_vis = 0)
0
1
0
0
1
1
1 1
0 0
0 1
CPU access Error CPU address shown to the external bus address only if (xbus3_sel_vis = 1) only during the first cycle The remaining cases are not implemented
-
-
-
25.6.12 XRAM
The XRAM is an XGATE bus protocol connected to the target XSRAM. The access types to the XRAM bus are: • Bytes, aligned words and misaligned words (in case of (MCU_FMTS = 1)). • Bytes, aligned words (in case of (MCU_FMTS = 0)).
25.7
Generic Labeling Scheme
s12x_mmc_.... labelling scheme for the generic S12X platform. Table 25-42 shows the sub-set of parameters to be used for different labelling scheme. The default S12X platform uses the default parameters in the column “default” (Refer to Figure 25-42) In the default case, the should be empty which means and the s12x_mmc applies the following label : s12x_mmc....
MC9S12XHZ512 Data Sheet, Rev. 1.03 926 Freescale Semiconductor
Chapter 25 Memory Mapping Control (S12XMMCV3)
Table 25-42. Generic architecture parameters for label
Configuration MCU_XGATE MCU_XGATE_FTX_ACC2 MCU_FLEXRAY MCU_EBI MCU_FMTS MCU_IPBI_XFR_WAIT
1
Default 1’b1 1’b1 1’b0 1’b1 1’b1 1’b0
Tag1 xg0 xfa0 flx1 ebi0 fmt0 xfr1
Tags are used for label scripting to distinguish between different configurable architectures. 2 This parameter is valid only when MCU_XGATE = 1’b1.
If these parameters change the default values, the tag will appear on the field like it’s defined in the tag column in Table 25-42 Example: Eagleray will have the following parameter changes: MCU_FLEXRAY = 1. s12x_mmc applies the following label: s12x_mmc_flx1.... Bonito will have the following parameter changes: MCU_XGATE_FTX_ACC = 0 MCU_EBI = 0 s12x_mmc applies the following label: s12x_mmc_xfa0ebi0....
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 927
Chapter 25 Memory Mapping Control (S12XMMCV3)
MC9S12XHZ512 Data Sheet, Rev. 1.03 928 Freescale Semiconductor
Appendix A Electrical Characteristics
Appendix A Electrical Characteristics
A.1 General
NOTE The electrical characteristics given in this section should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. This supplement contains the most accurate electrical information for the MC9S12XHZ family of microcontrollers available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE This classification is shown in the column labeled “C” in the parameter tables where appropriate. P: C: T: Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
D:
A.1.2
Power Supply
The MC9S12XHZ family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and parts of the internal voltage regulator. The VDDX1/VSSX1 and VDDX2/VSSX2 pairs supply the I/O pins except PU, PV and PW. VDDR supplies the internal voltage regulator. VDDM1/VSSM1, VDDM2/VSSM2 and VDDM3/VSSM3 pairs supply the ports PU, PV and PW.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 929
Appendix A Electrical Characteristics
VDD1, VSS1 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX1, VDDX2, VDDM as well as VSSA, VSSX1, VSSX2 and VSSM are connected by anti-parallel diodes for ESD protection. NOTE In the following context VDD5 is used for either VDDA, VDDM, VDDR and VDDX1/2; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX1/2, VDDM and VDDR pins. VDD is used for VDD1 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDDPLL.
A.1.3
Pins
There are four groups of functional pins.
A.1.3.1
I/O Pins
Those I/O pins have a nominal level of 5 V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical; however, some of the functionality may be disabled. For example, for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently.
A.1.3.2
Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3
Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5 V level. They are supplied by VDDPLL.
A.1.3.4
TEST
This pin is used for production testing only.
A.1.4
Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
MC9S12XHZ512 Data Sheet, Rev. 1.03 930 Freescale Semiconductor
Appendix A Electrical Characteristics
greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1. Absolute Maximum Ratings1
Num 1 2 3 4 5 6 7 8 9 10 10 11 12 13
1 2 3 4 5 6
Rating I/O, regulator and analog supply voltage Digital logic supply voltage PLL supply voltage
2 2
Symbol VDD5 VDD VDDPLL ∆VDDX ∆VSSX VIN VRH, VRL VILV VTEST I
D
Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –25 –55 –25 –0.25 –65
Max 6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +55 +25 0 155
Unit V V V V V V V V V mA mA mA mA °C
Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O input voltage Analog reference XFC, EXTAL, XTAL inputs TEST input Instantaneous maximum current Single pin limit for all digital I/O pins except Port U, V and W3 Instantaneous maximum current Single pin limit for Port U, V and W4 Instantaneous maximum current Single pin limit for XFC, EXTAL, XTAL5 Instantaneous maximum current Single pin limit for TEST 6 Storage temperature range
ID I I
DL
DT
Tstg
Beyond absolute maximum ratings device might be damaged. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. All digital I/O pins are internally clamped to VSSX1/2 and VDDX1/2 or VSSA and VDDA. Ports U, V and W are internally clamped to VSSM1/2/3 and VDDM1/2/3. Those pins are internally clamped to VSSPLL and VDDPLL. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 931
Appendix A Electrical Characteristics
A.1.6
ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
Table A-2. ESD and Latch-up Test Conditions
Model Human Body Series resistance Storage capacitance Number of pulse per pin Positive Negative Latch-up Minimum input voltage limit Maximum input voltage limit Description Symbol R1 C — — Value 1500 100 3 3 –2.5 7.5 V V Unit Ohm pF
Table A-3. ESD and Latch-Up Protection Characteristics
Num 1 2 3 C C C C Rating Human Body Model (HBM) Charge Device Model (CDM) Latch-up current at TA = 125°C Positive Negative Latch-up current at TA = 27°C Positive Negative Symbol VHBM VCDM ILAT +100 –100 ILAT +200 –200 — — — — mA Min 2000 500 Max — — Unit V V mA
4
C
MC9S12XHZ512 Data Sheet, Rev. 1.03 932 Freescale Semiconductor
Appendix A Electrical Characteristics
A.1.7
Operating Conditions
This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”.
Table A-4. Operating Conditions
Rating I/O, regulator and analog supply voltage Digital logic supply voltage1 PLL supply voltage2 Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Oscillator Bus frequency MC9S12XHZ512C Operating junction temperature range Operating ambient temperature range2 MC9S12XHZ512V Operating junction temperature range Operating ambient temperature range2 MC9S12XHZ512M Operating junction temperature range Operating ambient temperature range2
1
Symbol VDD5 VDD VDDPLL ∆VDDX ∆VSSX fosc fbus TJ TA TJ TA TJ TA
Min 4.5 2.35 2.35 –0.1 –0.1 0.5 0.5 –40 –40 –40 –40 –40 –40
Typ 5 2.5 2.5 0 0 — — — 27 — 27 — 27
Max 5.5 2.75 2.75 0.1 0.1 16 40 100 85
Unit V V V V V MHz MHz °C
°C 120 105 °C 140 125
The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2 Please refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more details about the relation between ambient temperature TA and device junction temperature TJ.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 933
Appendix A Electrical Characteristics
A.1.8
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from:
T T T J A D = Junction Temperature, [ ° C ] = Ambient Temperature, [ ° C ] = Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ ° C/W] J = T + (P • Θ ) A D JA
P
Θ
JA
The total power dissipation can be calculated from:
P P INT = Chip Internal Power Dissipation, [W] D =P INT +P IO
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal voltage regulator disabled
P INT =I DD ⋅V DD IO +I = DDPLL ⋅V DDPLL +I DDA ⋅V DDA
P
∑ RDSON ⋅ IIOi2 i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid:
R V OL = ----------- ;for outputs driven low DSON I OL
respectively
R V –V DD5 OH = ----------------------------------- ;for outputs driven high DSON I OH
2. Internal voltage regulator enabled
P INT =I DDR ⋅V DDR +I DDA ⋅V DDA
IDDR is the current shown in Table A-9 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high.
P IO =
∑ RDSON ⋅ IIOi2 i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
MC9S12XHZ512 Data Sheet, Rev. 1.03 934 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-5. Thermal Package Characteristics1
Num C Rating LQFP144 1 2 3 4 5 T T Thermal resistance LQFP144, single sided PCB2 Thermal resistance LQFP144, double sided PCB with 2 internal planes3 Junction to Board LQFP 144 Junction to Case LQFP 1444 Junction to Package Top LQFP1445 LQFP112 6 7 8 9 10
1 2
Symbol
Min
Typ
Max
Unit
θJA θJA θJB θJC ΨJT θJA θJA θJB θJC
— — — — —
— — — — —
41 32 22 7.4 3
°C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
T T
Thermal resistance LQFP112, single sided PCB2 Thermal resistance LQFP112, double sided PCB with 2 internal planes3 Junction to Board LQFP112 Junction to Case LQFP1124 Junction to Package Top LQFP112
5
— — — — —
— — — — —
43 32 22 7 3
ΨJT
The values for thermal resistance are achieved by package simulations Junction to ambient thermal resistance, θJA was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. 3 Junction to ambient thermal resistance, θ was simulated to be equivalent to the JEDEC specification JESD51-7 in a JA horizontal configuration in natural convection.
A.1.9
I/O Characteristics
This section describes the characteristics of all I/O pins except EXTAL, XTAL,XFC,TEST and supply pins.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 935
Appendix A Electrical Characteristics
Table A-6. I/O Characteristics
Conditions are 4.5 V < VDD5 < 5.5 V temperature from –40°C to +140°C, unless otherwise noted Num C 1 P Input high voltage T 2 P Input low voltage T 3 4 C Input hysteresis P Input leakage current (input mode) Vin = VDD5 or VSS5 All I/O pins except Port U, V, W Port U , V and W C P P 6 C P 7 Output high voltage (output mode) Partial drive: IOH = –2 mA Full drive: IOH = –10 mA Port U, V, W: IOH = –20 mA Output low voltage (output mode) Partial drive: IOL = +2 mA Full drive: IOL = +10 mA Port U, V, W: IOH = +20 mA
1
Rating
Symbol V
IH
Min 0.65*VDD5 —
Typ — — — — 250
Max — VDD5 + 0.3 0.35*VDD5 — —
Unit V V V V mV
VIL
— VSS5 – 0.3
VHYS
I V
in
–1 –2.5
— —
1 2.5 — — — 0.8 0.8 0.32
µA µA V V V V V V
5
OH
VDD5 – 0.8 — VDD5 – 0.8 — VDD5 – 0.32 VDD5 – 0.2 — — — — — 0.2
VOL
C Output Rise Time ( slew enabled) VDD5=5V, Rload=1KΩ, 10% to 90% of VOH Partial drive Full drive Port U, V, W C Output Fall Time ( slew enabled) VDD5=5V, Rload=1KΩ, 10% to 90% of VOH Partial drive Full drive Port U, V, W P Internal pull up device current, tested at VIL max C Internal pull up device current, tested at VIH min P Internal pull down device current, tested at VIH min C Internal pull down device current, tested at VIL max D Input capacitance T Injection current2 Single pin limit Total device Limit, sum of all injected currents P Port AD interrupt input pulse filtered3 passed3
tr 50 25 50 tf 50 25 50 IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE — 10 — — 3 — — –10 — 10 — –2.5 –25 75 35 100 — — — — 6 — 2.5 25 µs µs 100 50 150 –130 — 130 — — ns ns ns µA µA µA µA pF mA 75 35 100 100 50 150 ns ns ns
8
9 10 11 12 13 14
15
Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temper ture range from 50°C to 125°C. a 2 Refer to Section A.1.4, “Current Injection” for more details 3 Parameter only applies in stop or pseudo stop mode.
1
MC9S12XHZ512 Data Sheet, Rev. 1.03 936 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-7. I/O Characteristics for Port C, D, PE5, PE6, and PE7 for Reduced Input Voltage Thresholds
Conditions are 4.5 V < VDD5 < 5.5 V Temperature from –40°C to +140°C, unless otherwise noted Num C 1 2 3 P Input high voltage P Input low voltage C Input hysteresis Rating Symbol VIH VIL VHYS Min 1.75 — — Typ — — 100 Max — 0.75 — Unit V V mV
A.1.10
Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements.
A.1.10.1
Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode and the CPU and XGATE code is executed from RAM, VDD5=5.5V, internal voltage regulator is enabled and the bus frequency is 40MHz using a 4-MHz oscillator in loop controlled Pierce mode. Production testing is performed using a square wave signal at the EXTAL input.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 937
Appendix A Electrical Characteristics
Table A-8. shows the configuration of the peripherals for run current measurement.
Table A-8. Peripheral Configurations for Run Supply Current Measurements
Peripheral MSCAN SPI Configuration configured to loop-back mode using a bit rate of 1Mbit/s configured to master mode, continously transmit data (0x55 or 0xAA) at 1Mbit/s configured into loop mode, continously transmit data (0x55) at speed of 57600 baud operate in master mode and continously transmit data (0x55 or 0xAA) at the bit rate of 100Kbit/s configured to toggle its pins at the rate of 40kHz the peripheral shall be configured to output compare mode, Pulse accumulator and modulus counter enabled. the peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on all input channels in sequence. XGATE fetches code from RAM, XGATE runs in an infinite loop , it reads the Status and Flag registers of CAN’s, SPI’s, SCI’s in sequence and does some bit manipulation on the data COP Warchdog Rate 224 enabled, RTI Control Register (RTICTL) set to $FF the module is configured to run from the RC oscillator clock source. PIT is enabled, Micro-timer register 0 and 1 loaded with $0F and timer registers 0 to 3 are loaded with $03/07/0F/1F. the module is enabled and the comparators are configured to trigger in outside range. The range covers all the code executed by the core.
SCI
IIC
PWM ECT
ATD
XGATE
COP RTI API PIT
DBG
MC9S12XHZ512 Data Sheet, Rev. 1.03 938 Freescale Semiconductor
Appendix A Electrical Characteristics
A.1.10.2
Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data, and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take single chip currents and add the currents due to the external loads.
Table A-9. Run and Wait Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C
1
Rating
Symbol
Min
Typ
Max
Unit
Run supply current (Peripheral Configuration see Table A-8.) 1 2 C T T 3 T T T 4 T T T 5 T T T 6 T T T 7 T T T 8 9 T T 10
1 2 3 4 5 6
P
Peripheral Set fosc=4MHz, fbus=40MHz Peripheral Set1 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set2 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set3 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set4 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set5 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set6 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz
IDD5
110
mA
90 45 18 70 35 15 60 30 13 56 28 12 53 26 11 50 25 10 Wait supply current IDDW 95 mA
P
Peripheral Set ,PLL on XGATE executing code from RAM Peripheral Set2 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=8MHz All modules disabled, RTI enabled, PLL off
1
50 10 10
P
The following peripherals are on: ATD/ECT/IIC0/PWM/SPI/SCI0-SCI1/CAN0-CAN1/XGATE The following peripherals are on: ATD/ECT/IIC0/PWM/SPI/SCI0-SCI1/CAN0-CAN1 The following peripherals are on: ATD/ECT/IIC0/PWM/SPI/SCI0-SCI1 The following peripherals are on: ATD/ECT/IIC0/PWM/SPI The following peripherals are on: ATD/ECT/IIC0/PWM The following peripherals are on: ATD/ECT/IIC0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 939
Appendix A Electrical Characteristics
Table A-10. Pseudo Stop and Full Stop Current
Conditions are shown in Table A-4 unless otherwise noted Num C Rating –40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C –40°C 27°C 70°C 85°C 105°C 125°C 140°C Stop Current 12 C P C C P C P C P –40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C IDDS — — — — — — — — — 20 30 100 200 250 400 500 600 1000 — 100 — — 2000 — 3000 — 7000 µA Symbol Min Typ Max Unit µA
Pseudo stop current (API, RTI, and COP disabled) PLL off 10 C P C C P C P C P C C C C C C C IDDPS — — — — — — — — — — — — — — — — 200 300 400 500 600 800 1000 1200 1500 500 750 850 1000 1200 1500 2000 — 500 — — 2500 — 3500 — 7000 — — — — — — —
Pseudo stop current (API, RTI, and COP enabled) PLL off 11 IDDPS µA
MC9S12XHZ512 Data Sheet, Rev. 1.03 940 Freescale Semiconductor
Appendix A Electrical Characteristics
A.2
ATD
This section describes the characteristics of the analog-to-digital converter.
A.2.1
ATD Operating Characteristics
The Table A-11 and Table A-13 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-11. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted, supply voltage 4.5 V < VDDA < 5.5 V Num C 1 D Reference potential Low High C Differential reference voltage1 D ATD clock frequency D ATD 10-bit conversion period Clock cycles2 Conv, time at 2.0 MHz ATD clock fATDCLK D ATD 8-Bit conversion period Clock cycles2 Conv, time at 2.0 MHz ATD clock fATDCLK D Recovery time (VDDA = 5.0 Volts) P Reference supply current Rating Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV8 TCONV8 tREC IREF Min VSSA VDDA/2 4.50 0.5 14 7 12 6 — — — — — — — — Typ — — 5.00 Max VDDA/2 VDDA 5.5 2.0 28 14 26 13 20 0.375 Unit V V V MHz Cycles µs Cycles µs µs mA
2 3 4
5
6 7
1 2
Full accuracy is not guaranteed when differential voltage is less than 4.50 V The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
A.2.2
Factors Influencing Accuracy
Three factors — source resistance, source capacitance and current injection — have an influence on the accuracy of the ATD.
A.2.2.1
Source Resistance
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 941
Appendix A Electrical Characteristics
A.2.2.2
Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS–CINN).
A.2.2.3
Current Injection
There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as: VERR = K * RS * IINJ with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel.
Table A-12. ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol RS CINN CINS INA Kp Kn Min — — — –2.5 — — Typ — — — — — — Max 1 10 22 2.5 10-4 10-2 mA A/A A/A Unit KΩ pF
C Max input source resistance T Total input capacitance Non sampling Sampling C Disruptive analog input current C Coupling ratio positive current injection C Coupling ratio negative current injection
3 4 5
MC9S12XHZ512 Data Sheet, Rev. 1.03 942 Freescale Semiconductor
Appendix A Electrical Characteristics
A.2.3
ATD Accuracy
Table A-13 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance, and source resistance.
Table A-13. ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH–VRL = 5.12 V. Resulting to one 8-bit count = 20 mV and one 10-bit count = 5 mV fATDCLK = 2.0 MHz Num C 1 2 3 4 5 6 7 8 9 9
1
Rating
Symbol LSB DNL INL
Min — –1 –2.5 –3 –4 — –0.5 –1.0 –1.5 –2.0
Typ 5 — ±1.5 ±2.0 ±3.0 20 — ±0.5 ±1.0 ±1.5
Max — 1 2.5 3 4 — 0.5 1.0 1.5 2.0
Unit mV Counts Counts Counts Counts mV Counts Counts Counts Counts
P 10-bit resolution P 10-bit differential nonlinearity P 10-bit integral nonlinearity P 10-bit absolute error (Port AD) P 10-bit absolute error (Port P 8-bit resolution P 8-bit differential nonlinearity P 8-bit integral nonlinearity P 8-bit absolute error (Port AD) P 8-bit absolute error (Port L)1
1 1
AE AE LSB DNL INL AE AE
L)1
These values include the quantization error which is inherently 1/2 count for any A/D converter.
A.2.3.1
ATD Accuracy Definitions
For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps.
V –V i i–1 DNL ( i ) = -------------------------- – 1 1LSB
The integral non-linearity (INL) is defined as the sum of all DNLs:
INL ( n ) =
i=1
∑
n
V –V n 0 DNL ( i ) = -------------------- – n 1LSB
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 943
Appendix A Electrical Characteristics
DNL
Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 10-Bit Resolution $3F3
LSB
10-Bit Absolute Error Boundary Vi
8-Bit Absolute Error Boundary
$FF
$FE
$FD 8-Bit Resolution
Vin mV
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50
Ideal Transfer Curve 2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
50555060506550705075508050855090509551005105511051155120
Figure A-1. ATD Accuracy Definitions
NOTE Figure A-1 shows only definitions, for specification values refer to Table A-13.
MC9S12XHZ512 Data Sheet, Rev. 1.03 944 Freescale Semiconductor
Appendix A Electrical Characteristics
A.3
NVM, Flash, and EEPROM
NOTE Unless otherwise noted the abbreviation NVM (nonvolatile memory) is used for both Flash and EEPROM.
A.3.1
NVM Timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-14 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2 MHz.
A.3.1.1
Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
t swpgm 1 1 = 9 ⋅ ------------------------ + 25 ⋅ ----------f f NVMOP bus
A.3.1.2
Burst Programming
This applies only to the Flash where up to 64 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
t bwpgm 1 1 = 4 ⋅ ------------------------ + 9 ⋅ ----------f f NVMOP bus
The time to program a whole row is:
t brpgm =t swpgm + 63 ⋅ t bwpgm
Burst programming is more than 2 times faster than single word programming.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 945
Appendix A Electrical Characteristics
A.3.1.3
Sector Erase
Erasing a 1024-byte Flash sector or a 4-byte EEPROM sector takes:
t era 1 ≈ 4000 ⋅ -----------------------f NVMOP
The setup time can be ignored for this operation.
A.3.1.4
Mass Erase
Erasing a NVM block takes:
t mass 1 ≈ 20000 ⋅ -----------------------f NVMOP
The setup time can be ignored for this operation.
A.3.1.5
Blank Check
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command.
t check ≈ location ⋅ t cyc + 10 ⋅ t cyc
MC9S12XHZ512 Data Sheet, Rev. 1.03 946 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-14. NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7
Rating
Symbol fNVMOSC fNVMBUS fNVMOP tswpgm
4
Min 0.5 1 150 462 20.4
2 2
Typ — — — — — — — — — —
Max 801 — 200 74.53 31
3 3
Unit MHz MHz kHz µs µs µs ms ms tcyc tcyc
D External oscillator clock D Bus frequency for programming or erase operations D Operating frequency P Single word programming time D Flash burst programming consecutive word D Flash burst programming time for 64 words P Sector erase time P Mass erase time D Blank check time Flash per block D Blank check time EEPROM per block
tbwpgm tbrpgm tera tmass tcheck tcheck
4
1331.2 205 1005 116 116
2027.5 26.73 1333
655467 20587
Restrictions for oscillator in crystal mode apply. Minimum programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. Maximum erase and programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.3.1.1, “Single Word Programming” – Section A.3.1.4, “Mass Erase” for guidance. Burst programming operations are not applicable to EEPROM Minimum erase times are achieved under maximum NVM operating frequency, fNVMOP. Minimum time, if first word in the array is not blank Maximum time to complete check on an erased block
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 947
Appendix A Electrical Characteristics
A.3.2
NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed
Table A-15. NVM Reliability Characteristics1
Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Flash Reliability Characteristics 1 2 3 4 C Data retention after 10,000 program/erase cycles at an average junction temperature of TJavg ≤ 85°C C Data retention with =100 nF >=100 nF >=100 nF >=100 nF >=100 nF >=100 nF >=100 nF 100 nF .. 220 nF
See CRG block description chapter
MC9S12XHZ512 Data Sheet, Rev. 1.03 976 Freescale Semiconductor
Appendix C PCB Layout Guidelines
C8 VDDX1
VSSX1
VDDM1 C7 VSSM1 VSS1 C1 VDD1
VDDM2 C6 VSSM2
VDDA
VDDM3 C2 C5 VSSM3 VSSA
C3
C4
VDDR/
C9
VDDX2
C14
C10 Q1
C11
Figure C-1. LQFP144 Recommended PCB Layout
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 977
C12 R1
C13 VSSPLL VDDPLL
Appendix C PCB Layout Guidelines
C8
VSSX1
VDDX1
VDDM1 C7 VSSM1 VSS1 C1 VDDM2 C6 VSSM2 VDD1
VDDA
VDDM3 C2 C5 VSSM3 VSSA
C3
C4
VDDR/
C14
C9
C10
C11
VDDX2
Q1 C12 R1 C13 VSSPLL VDDPLL
Figure C-2. LQFP112 Recommended PCB Layout
MC9S12XHZ512 Data Sheet, Rev. 1.03 978 Freescale Semiconductor
Appendix D Ordering Information
Appendix D Ordering Information
The following figure provides an ordering number example for the MC9S12XHZ512.
MC9S12X HZ512
C AL
Temperature Options C = -40˚C to 85˚C Package Option Temperature Option V = -40˚C to 105˚C M = -40˚C to 125˚C Device Title Package Options Controller Family AL = 112 LQFP AG = 144 LQFP
Figure D-1. Order Part Number Example
Customers who place orders using the generic MC partnumbers which are constructed using the above rules will automatically receive our preferred maskset (ie preferred revision of silicon). If the product is updated in the future and a newer maskset is put into production, then the newer maskset may automatically ship against these generic MC partnumbers. If required, a customer can specify a particular maskset when ordering product. To do this, the customer must order the corresponding "SC" partnumber from the below table. Orders placed against these SC partnumbers will only ever receive one specific maskset. If a new maskset is made available, customers will be notified by PCN (Process Change Notification) but will have to order against a different SC part number in order to receive the new maskset. The marking on the device will be as per the left hand column in the below table independently of whether the MC or the SC partnumber is ordered.
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 979
Appendix E Detailed Register Map
Appendix E Detailed Register Map
The following tables show the detailed register map of the MC9S12XHZ family. 0x0000–0x0009 Port Integration Module (PIM) Map 1 of 5
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 Name PORTA PORTB DDRA DDRB PORTC PORTD DDRC DDRD PORTE DDRE R W R W R W R W R W R W R W R W R W R W Bit 7 PA7 PB7 DDRA7 DDRB7 PC7 PD7 DDRC7 DDRD7 PE7 DDRE7 Bit 6 PA6 PB6 DDRA6 DDRB6 PC6 PD6 DDRC6 DDRD6 PE6 DDRE6 Bit 5 PA5 PB5 DDRA5 DDRB5 PC5 PD5 DDRC5 DDRD5 PE5 DDRE5 Bit 4 PA4 PB4 DDRA4 DDRB4 PC4 PD4 DDRC4 DDRD4 PE4 DDRE4 Bit 3 PA3 PB3 DDRA3 DDRB3 PC3 PD3 DDRC3 DDRD3 PE3 DDRE3 Bit 2 PA2 PB2 DDRA2 DDRB2 PC2 PD2 DDRC2 DDRD2 PE2 DDRE2 Bit 1 PA1 PB1 DDRA1 DDRB1 PC1 PD1 DDRC1 DDRD1 PE1 0 Bit 0 PA 0 PB0 DDRA0 DDRB0 PC0 PD0 DDRC0 DDRD0 PE0 0
0x000A–0x000B Module Mapping Control (S12XMMC) Map 1 of 4
Address 0x000A 0x000B Name MMCCTL0 MODE R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 0 Bit 3 0 0 Bit 2 CS2E 0 Bit 1 CS1E 0 Bit 0 CS0E 0
MODC
MODB
MODA
0x000C–0x000D Port Integration Module (PIM) Map 2 of 5
Address 0x000C 0x000D Name PUCR RDRIV R W R W Bit 7 PUPKE RDPK Bit 6 BKGPE 0 Bit 5 0 0 Bit 4 PUPEE RDPE Bit 3 PUPDE RDPD Bit 2 PUPCE RDPC Bit 1 PUPBE RDPB Bit 0 PUPAE RDPA
MC9S12XHZ512 Data Sheet, Rev. 1.03 980 Freescale Semiconductor
Appendix E Detailed Register Map
0x000E–0x000F External Bus Interface (S12XEBI) Map
Address 0x000E 0x000F Name EBICTL0 EBICTL1 Bit 7 R ITHRS W R EWAITE W Bit 6 0 0 Bit 5 HDBE 0 Bit 4 ASIZ4 0 Bit 3 ASIZ3 0 Bit 2 ASIZ2 EXSTR2 Bit 1 ASIZ1 EXSTR1 Bit 0 ASIZ0 EXSTR0
0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 4
Address 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 Name GPAGE DIRECT Reserved MMCCTL1 Reserved Reserved RPAGE EPAGE R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 GP6 DP14 0 0 0 0 Bit 5 GP5 DP13 0 0 0 0 Bit 4 GP4 DP12 0 0 0 0 Bit 3 GP3 DP11 0 0 0 0 Bit 2 GP2 DP10 0 Bit 1 GP1 DP9 0 Bit 0 GP0 DP8 0
DP15 0 0 0 0
EROMON 0 0
ROMHM 0 0
ROMON 0 0
RP7 EP7
RP6 EP6
RP5 EP5
RP4 EP4
RP3 EP3
RP2 EP2
RP1 EP1
RP0 EP0
0x0018–0x001B Miscellaneous Peripheral
Address 0x0018 0x0019 0x001A 0x001B Name Reserved Reserved PARTIDH PARTIDL R W R W R W R W Bit 7 0 0 1 0 Bit 6 0 0 1 0 Bit 5 0 0 1 0 Bit 4 0 0 0 0 Bit 3 0 0 0 0 Bit 2 0 0 1 0 Bit 1 0 0 0 0 Bit 0 0 0 0 0
0x001C–0x001F Port Integration Module (PIM) Map 3 of 5
Address 0x001C Name ECLKCTL R W Bit 7 NECLK Bit 6 NCLKX2 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 EDIV1 Bit 0 EDIV0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 981
Appendix E Detailed Register Map
0x001C–0x001F Port Integration Module (PIM) Map 3 of 5
Address 0x001D Name Reserved R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0
0x001E 0x001F
IRQCR SRCR
IRQE SRRK
IRQEN 0
SRRE
SRRD
SRRC
SRRB
SRRA
0x0020–0x0027 Debug Module (S12XDBG) Map
Address 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x00281 0x00282 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F
1 2
Name DBGC1 DBGSR DBGTCR DBGC2 DBGTBH DBGTBL DBGCNT DBGSCRX DBGXCTL (COMPA/C) DBGXCTL (COMPB/D) DBGXAH DBGXAM DBGXAL DBGXDH DBGXDL DBGXDHM DBGXDLM R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 ARM TBF
Bit 6 0 TRIG EXTF
Bit 5 XGSBPE 0
Bit 4 BDM 0
Bit 3
Bit 2
Bit 1
Bit 0
DBGBRK 0 SSF2
COMRV SSF1 SSF0
TSOURCE 0 Bit 15 Bit 7 0 0 0 0 0 0 Bit 14 Bit 6 0
TRANGE 0 Bit 12 Bit 4
TRCMOD CDCM Bit 11 Bit 3 CNT 0 Bit 10 Bit 2
TALIGN ABCM Bit 9 Bit 1 Bit 8 Bit 0
Bit 13 Bit 5
SC3 RW RW 19 11 3 11 3 11 3
SC2 RWE RWE 18 10 2 10 2 10 2
SC1 SRC SRC 17 9 1 9 1 9 1
SC0 COMPE COMPE Bit 16 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
NDB SZ Bit 22 14 6 14 6 14 6
TAG TAG 21 13 5 13 5 13 5
BRK BRK 20 12 4 12 4 12 4
SZE 0
Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7
This represents the contents if the Comparator A or C control register is blended into this address This represents the contents if the Comparator B or D control register is blended into this address
MC9S12XHZ512 Data Sheet, Rev. 1.03 982 Freescale Semiconductor
Appendix E Detailed Register Map
0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4
Address 0x0030 0x0031 Name PPAGE Reserved R W R W Bit 7 PIX7 0 Bit 6 PIX6 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5
Address 0x0032 0x0033 Name PORTK DDRK R W R W Bit 7 PK7 DDRK7 Bit 6 PK6 DDRK6 Bit 5 PK5 DDRK5 Bit 4 PK4 DDRK4 Bit 3 PK3 DDRK3 Bit 2 PK2 DDRK2 Bit 1 PK1 DDRK1 Bit 0 PK0 DDRK0
0x0034–0x003F Clock and Reset Generator (CRG) Map
Address 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F Name SYNR REFDV CTFLG CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP CTCTL ARMCOP Bit 7 R 0 W 0 R W R 0 W R RTIF W R RTIE W R PLLSEL W R CME W R RTDEC W R WCOP W R 0 W R 0 W R 0 W Bit 7 Bit 6 0 0 0 Bit 5 SYN5 REFDV5 0 Bit 4 SYN4 REFDV4 Bit 3 SYN3 REFDV3 Bit 2 SYN2 REFDV2 Bit 1 SYN1 REFDV1 0 Bit 0 SYN0 REFDV0 0 SCM 0
PORF ILAF PSTP PLLON RTR6 RSBCK 0 0 0 6
LVRF 0 0
0 0 0 Reserved For Factory Test LOCK TRACK LOCKIF LOCKIE 0 0 0 0
SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1
PLLWAI FSTWKP RTR3 0
COPWAI SCME RTR0 CR0 0 0 0 Bit 0
AUTO RTR5 0 0 0 0 5
ACQ RTR4 0
PRE RTR2 CR2 0 0 0 2
0 0 Reserved For Factory Test 0 Reserved For Factory Test 0 0 4 3
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 983
Appendix E Detailed Register Map
0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3)
Address 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0
TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7
TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0
TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0
TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0
PRNT TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0
TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0
TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0
TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0
C6F 0
C5F 0
C4F 0
14 6 14 6 14 6
13 5 13 5 13 5
12 4 12 4 12 4
11 3 11 3 11 3
10 2 10 2 10 2
9 1 9 1 9 1
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 984 Freescale Semiconductor
Appendix E Detailed Register Map
0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 2 of 3)
Address 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C Name TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACN3 (hi) PACN2 (lo) PACN1 (hi) PACN0 (lo) MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS OCPD Bit 7 R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R 0 W R 0 W R Bit 7 W R Bit 7 W R Bit 7 W R Bit 7 W R MCZI W R MCZF W R 0 W R DLY7 W R NOVW7 W R SH37 W R OCPD7 W Bit 6 14 6 14 6 14 6 14 6 14 6 PAEN 0 Bit 5 13 5 13 5 13 5 13 5 13 5 PAMOD 0 Bit 4 12 4 12 4 12 4 12 4 12 4 PEDGE 0 Bit 3 11 3 11 3 11 3 11 3 11 3 CLK1 0 Bit 2 10 2 10 2 10 2 10 2 10 2 CLK0 0 Bit 1 9 1 9 1 9 1 9 1 9 1 PAOVI PAOVF 1 1 1 1 MCPR1 POLF1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Bit 0 Bit 0 Bit 0 MCPR0 POLF0
6 6 6 6 MODMC 0 0
5 5 5 5 RDMCL 0 0
4 4 4 4 0 ICLAT 0 0
3 3 3 3 0 FLMC POLF3
2 2 2 2 MCEN POLF2
PA3EN DLY3 NOVW3 TFMOD OCPD3
PA2EN DLY2 NOVW2 PACMX OCPD2
PA1EN DLY1 NOVW1 BUFEN OCPD1
PA0EN DLY0 NOVW0 LATQ OCPD0
DLY6 NOVW6 SH26 OCPD6
DLY5 NOVW5 SH15 OCPD5
DLY4 NOVW4 SH04 OCPD4
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 985
Appendix E Detailed Register Map
0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 3 of 3)
Address 0x006D 0x006E 0x006F 0x0070 0x0071 0x0072 0x0073 0x0074 0x0075 0x0076 0x0077 0x0078 0x0079 0x007A 0x007B 0x007C 0x007D 0x007E 0x007F Name TIMTST PTPSR PTMCPSR PBCTL PBFLG PA3H PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) TC1H (hi) TC1H (lo) TC2H (hi) TC2H (lo) TC3H (hi) TC3H (lo) Bit 7 R 0 W R PTPS7 W R PTMPS7 W R 0 W R 0 W R PA3H7 W R PA2H7 W R PA1H7 W R PA0H7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 0 Bit 1 0 Bit 0 0 0 0 Reserved For Factory Test PTPS4 PTMPS4 0 0 PA3H4 PA2H4 PA1H4 PA0H4 PTPS3 PTMPS3 0 0 PA3H3 PA2H3 PA1H3 PA0H3
PTPS6 PTMPS6 PBEN 0 PA3H6 PA2H6 PA1H6 PA0H6
PTPS5 PTMPS5 0 0 PA3H5 PA2H5 PA1H5 PA0H5
PTPS2 PTMPS2 0 0 PA3H2 PA2H2 PA1H2 PA0H2
PTPS1 PTMPS1 PBOVI PBOVF PA3H1 PA2H1 PA1H1 PA0H1
PTPS0 PTMPS0 0 0 PA3H0 PA2H0 PA1H 0 PA0H0
14 6 14 6 14 6 14 6 14 6
13 5 13 5 13 5 13 5 13 5
12 4 12 4 12 4 12 4 12 4
11 3 11 3 11 3 11 3 11 3
10 2 10 2 10 2 10 2 10 2
9 1 9 1 9 1 9 1 9 1
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 986 Freescale Semiconductor
Appendix E Detailed Register Map
0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD) Map (Sheet 1 of 3)
Address 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x0090 0x0091 0x0092 0x0093 0x0094 0x0095 0x0096 Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 ATDSTAT2 ATDSTAT1 ATDDIEN0 ATDDIEN ATDPTAD0 ATDPTAD1 ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H Bit 7 R 0 W R ETRIG SEL W R ADPU W R 0 W R SRES8 W R DJM W R SCF W R 0 W R U W R 0 W R CCF15 W R CCF7 W R IEN15 W R IEN7 W R PTAD15 W R PTAD7 W R Bit15 W R Bit7 W R Bit15 W R Bit7 W R Bit15 W R Bit7 W R Bit15 W Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 WRAP3 ETRIG CH3 ETRIGP S1C PRS3 CD CC3 0 Bit 2 WRAP2 ETRIG CH2 ETRIGE FIFO PRS2 CC CC2 0 Bit 1 WRAP1 ETRIG CH1 ASCIE FRZ1 PRS1 CB CC1 0 U 0 CCF9 CCF1 Bit 0 WRAP0 ETRIG CH0 ASCIF
AFFC S8C SMP1 DSGN 0 0 U 0 CCF14 CCF6
AWAI S4C SMP0 SCAN ETORF 0 U
ETRIGLE S2C PRS4 MULT FIFOR 0
FRZ0 PRS0 CA CC0 0 U
U U U Reserved For Factory Test 0 0 0 0 Reserved For Factory Test CCF13 CCF12 CCF11 CCF10 CCF5 CCF4 CCF3 CCF2
SC CCF8 CCF0
IEN14 IEN6 PTAD14 PTAD6 14 Bit6 14 Bit6 14 Bit6 14
IEN13 IEN5 PTAD13 PTAD5 13 0 13 0 13 0 13
IEN12 IEN4 PTAD12 PTAD4 12 0 12 0 12 0 12
IEN11 IEN3 PTAD11 PTAD3 11 0 11 0 11 0 11
IEN10 IEN2 PTAD10 PTAD2 10 0 10 0 10 0 10
IEN9 IEN1 PTAD9 PTAD1 9 0 9 0 9 0 9
IEN8 IEN0 PTAD8 PTAD0 Bit8 0 Bit8 0 Bit8 0 Bit8
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 987
Appendix E Detailed Register Map
0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD) Map (Sheet 2 of 3)
Address 0x0097 0x0098 0x0099 0x009A 0x009B 0x009C 0x009D 0x009E 0x009F 0x00A0 0x00A1 0x00A2 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 0x00AA 0x00AB 0x00AC Name ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L ATDDR8H ATDDR8L ATDDR9H ATDDR9L ATDDR10H ATDDR10L ATDDR11H ATDDR11L ATDDR12H ATDDR12L ATDDR13H ATDDR13L ATDDR14H R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 Bit 4 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 Bit 3 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 Bit 2 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 Bit 1 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 Bit 0 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
MC9S12XHZ512 Data Sheet, Rev. 1.03 988 Freescale Semiconductor
Appendix E Detailed Register Map
0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD) Map (Sheet 3 of 3)
Address 0x00AD 0x00AE 0x00AF Name ATDDR14L ATDDR15H ATDDR15L R W R W R W Bit 7 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 Bit 5 0 13 0 Bit 4 0 12 0 Bit 3 0 11 0 Bit 2 0 10 0 Bit 1 0 9 0 Bit 0 0 Bit8 0
0x00B0–0x00BF Interrupt Module (S12XINT) Map
Address 0x00B0 0x00B1 0x00B2 0x00B3 0x00B4 0x00B5 0x00B6 0x00B7 Name Reserved IVBR Reserved Reserved Reserved Reserved INT_XGPRIO INT_CFADDR R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
IVB_ADDR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
XILVL[2:0] 0 0
INT_CFADDR[7:4] RQST RQST RQST RQST RQST RQST RQST RQST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x00B8 INT_CFDATA0 0x00B8 INT_CFDATA1 0x00B9 INT_CFDATA2 0x00BA INT_CFDATA3 0x00BB INT_CFDATA4 0x00BC INT_CFDATA5 0x00BE INT_CFDATA6 0x00BF INT_CFDATA7
PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 989
Appendix E Detailed Register Map
0x00C0–0x00C7 Inter IC Bus (IIC0) Map
Address 0x00C0 0x00C1 0x00C2 0x00C3 0x00C4 0x00C5 0x00C6 0x00C7 Name IB0AD IB0FD IB0CR IB0SR IB0DR IB0CR2 Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 ADR7 IBC7 IBEN TCF Bit 6 ADR6 IBC6 IBIE IAAS Bit 5 ADR5 IBC5 MS/SL IBB Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 Bit 2 ADR2 IBC2 0 RSTA SRW Bit 1 ADR1 IBC1 0 Bit 0 0
IBC0 IBSWAI RXAK
IBIF D1 ADR9 0 0
D7 GCEN 0 0
D6 ADTYPE 0 0
D5 0 0 0
D3 0 0 0
D2 ADR10 0 0
D0 ADR8 0 0
0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map
Address 0x00C8 0x00C9 0x00CA 0x00C8 0x00C9 0x00CA 0x00CB 0x00CC 0x00CD 0x00CE 0x00CF
1 2
Name SCI0BDH1 SCI0BDL1 SCI0CR11 SCI0ASR12 SCI0ACR12 SCI0ACR22 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL
Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7
Bit 6 TNP1 SBR6 SCISWAI 0 0 0
Bit 5 TNP0 SBR5 RSRC 0 0 0
Bit 4 SBR12 SBR4 M 0 0 0
Bit 3 SBR11 SBR3 WAKE 0 0 0
Bit 2 SBR10 SBR2 ILT BERRV 0
Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE
Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0
BERRM1 RE NF
TCIE TC 0
RIE RDRF 0 0 R5 T5
ILIE IDLE
TE OR
TXPOL 0 R4 T4
RXPOL 0 R3 T3
BRK13 0 R2 T2
TXDIR 0 R1 T1
T8 R6 T6
Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one
MC9S12XHZ512 Data Sheet, Rev. 1.03 990 Freescale Semiconductor
Appendix E Detailed Register Map
0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map
Address 0x00D0 0x00D1 0x00D2 0x00D0 0x00D1 0x00D2 0x00D3 0x00D4 0x00D5 0x00D6 0x00D7
1 2
Name SCI1BDH1 SCI1BDL1 SCI1CR11 SCI1ASR12 SCI1ACR12 SCI1ACR22 SCI1CR2 SCI1SR1 SCI1SR2 SCI1DRH SCI1DRL
Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7
Bit 6 TNP1 SBR6 SCISWAI 0 0 0
Bit 5 TNP0 SBR5 RSRC 0 0 0
Bit 4 SBR12 SBR4 M 0 0 0
Bit 3 SBR11 SBR3 WAKE 0 0 0
Bit 2 SBR10 SBR2 ILT BERRV 0
Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE
Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0
BERRM1 RE NF
TCIE TC 0
RIE RDRF 0 0 R5 T5
ILIE IDLE
TE OR
TXPOL 0 R4 T4
RXPOL 0 R3 T3
BRK13 0 R2 T2
TXDIR 0 R1 T1
T8 R6 T6
Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one
0x00D8–0x00DF Serial Peripheral Interface (SPI) Map
Address 0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE 0x00DF Name SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 SPIE 0 0 SPIF 0 Bit 6 SPE 0 Bit 5 SPTIE 0 Bit 4 MSTR MODFEN SPPR0 MODF 0 Bit 3 CPOL BIDIROE 0 0 0 Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0
SPPR2 0 0
SPPR1 SPTEF 0
SPR2 0 0
Bit7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit0 0 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 991
Appendix E Detailed Register Map
0x00E0–0x00FF Reserved
Address 0x00E0– 0x00FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0100–0x010F Flash Control Register (FTX512K4) Map
Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010A 0x010B 0x010C 0x010D 0x010E 0x010F Name FCLKDIV FSEC FTSTMOD FCNFG FPROT FSTAT FCMD FCTL FADDRHI FADDRLO FDATAHI FDATALO Reserved Reserved Reserved Reserved Bit 7 R FDIVLD W R KEYEN1 W R 0 W R CBEIE W R FPOPEN W R CBEIF W R 0 W R NV7 W R W R W R W R W R 0 W R 0 W R 0 W R 0 W Bit 6 PRDIV8 KEYEN0 Bit 5 FDIV5 RNV5 Bit 4 FDIV4 RNV4 Bit 3 FDIV3 RNV3 0 0 Bit 2 FDIV2 RNV2 0 0 Bit 1 FDIV1 SEC1 0 0 Bit 0 FDIV0 SEC0 0 0
MRDS CCIE RNV6 CCIF KEYACC FPHDIS PVIOL
WRALL 0
FPHS1 ACCERR
FPHS0 0
FPLDIS BLANK
FPLS1 0
FPLS0 0
CMDB[6:0] NV6 NV5 NV4 NV3 NV2 NV1 NV0
FADDRHI FADDRLO FDATAHI FDATALO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 992 Freescale Semiconductor
Appendix E Detailed Register Map
0x0110–0x011B EEPROM Control Register (EETX4K) Map
Address 0x0110 0x0111 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118 0x0119 0x011A 0x011B Name ECLKDIV Reserved Reserved ECNFG EPROT ESTAT ECMD Reserved EADDRHI EADDRLO EDATAHI EDATALO Bit 7 R EDIVLD W R 0 W R 0 W R CBEIE W R EPOPEN W R CBEIF W R 0 W R 0 W R 0 W R W R W R W Bit 6 PRDIV8 0 0 Bit 5 EDIV5 0 0 0 RNV5 Bit 4 EDIV4 0 0 0 RNV4 Bit 3 EDIV3 0 0 0 Bit 2 EDIV2 0 0 0 Bit 1 EDIV1 0 0 0 Bit 0 EDIV0 0 0 0
CCIE RNV6 CCIF
EPDIS 0
EPS2 BLANK
EPS1 0
EPS0 0
PVIOL
ACCERR
CMDB[6:0] 0 0 0 0 0 0 EABLO EDHI EDLO 0 0 0 0 EABHI 0
0x011C–0x011F Memory Map Control (S12XMMC) Map 4 of 4
Address 0x011C 0x011D 0x011E 0x011F Name RAMWPC RAMXGU RAMSHL RAMSHU R W R W R W R W Bit 7 RPWE 1 1 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 AVIE XGU1 SHL1 SHU1 Bit 0 AVIF XGU0 SHL0 SHU0
XGU6 SHL6 SHU6
XGU5 SHL5 SHU5
XGU4 SHL4 SHU4
XGU3 SHL3 SHU3
XGU2 SHL2 SHU2
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 993
Appendix E Detailed Register Map
0x0120–0x0137 Liquid Crystal Display 32x4 (LCD) Map
Address 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 0x0128 0x0129 0x012A 0x012B 0x012C 0x012D 0x012E 0x012F 0x0130 0x0131 0x0132 0x0133 0x0134 Name LCDCR0 LCDCR1 FPENR0 FPENR1 FPENR2 FPENR3 Reserved Reserved LCDRAM0 LCDRAM1 LCDRAM2 LCDRAM3 LCDRAM4 LCDRAM5 LCDRAM6 LCDRAM7 LCDRAM8 LCDRAM9 LCDRAM10 LCDRAM11 LCDRAM12 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 LCDEN 0 Bit 6 0 0 Bit 5 LCLK2 0 Bit 4 LCLK1 0 Bit 3 LCLK0 0 Bit 2 BIAS 0 Bit 1 DUTY1 LCDSWAI FP1EN FP9EN FP17EN FP25EN 0 0 Bit 0 DUTY0 LCDRPST P FP0EN FP8EN FP16EN FP24EN 0 0
FP7EN FP15EN FP23EN FP31EN 0 0
FP6EN FP14EN FP22EN FP30EN 0 0
FP5EN FP13EN FP21EN FP29EN 0 0
FP4EN FP12EN FP20EN FP28EN 0 0
FP3EN FP11EN FP19EN19 FP27EN 0 0
FP2EN FP10EN FP18EN FP26EN 0 0
FP1BP3 FP3BP3 FP5BP3 FP7BP3 FP9BP3 FP11BP3 FP13BP3 FP15BP3 FP17BP3 FP19BP3 FP21BP3 FP23BP3 FP25BP3
FP1BP2 FP3BP2 FP5BP2 FP7BP2 FP9BP2 FP11BP2 FP13BP2 FP15BP2 FP17BP2 FP19BP2 FP21BP2 FP23BP2 FP25BP2
FP1BP1 FP3BP1 FP5BP1 FP7BP1 FP9BP1 FP11BP1 FP13BP1 FP15BP1 FP17BP1 FP19BP1 FP21BP1 FP23BP1 FP25BP1
FP1BP0 FP3BP0 FP5BP0 FP7BP0 FP9BP0 FP11BP0 FP13BP0 FP15BP0 FP17BP0 FP19BP0 FP21BP0 FP23BP0 FP25BP0
FP0BP3 FP2BP3 FP4BP3 FP6BP3 FP8BP3 FP10BP3 FP12BP3 FP14BP3 FP16BP3 FP18BP3 FP20BP3 FP22BP3 FP24BP3
FP0BP2 FP2BP2 FP4BP2 FP6BP2 FP8BP2 FP10BP2 FP12BP2 FP14BP2 FP16BP2 FP18BP2 FP20BP2 FP22BP2 FP24BP2
FP0BP1 FP2BP1 FP4BP1 FP6BP1 FP8BP1 FP10BP1 FP12BP1 FP14BP1 FP16BP1 FP18BP1 FP20BP1 FP22BP1 FP24BP1
FP0BP0 FP2BP0 FP4BP0 FP6BP0 FP8BP0 FP10BP0 FP12BP0 FP14BP0 FP16BP0 FP18BP0 FP20BP0 FP22BP0 FP24BP0
MC9S12XHZ512 Data Sheet, Rev. 1.03 994 Freescale Semiconductor
Appendix E Detailed Register Map
0x0120–0x0137 Liquid Crystal Display 32x4 (LCD) Map
Address 0x0135 0x0136 0x0137 Name LCDRAM13 LCDRAM14 LCDRAM15 Bit 7 R FP27BP3 W R FP29BP3 W R FP31BP3 W Bit 6 FP27BP2 FP29BP2 FP31BP2 Bit 5 FP27BP1 FP29BP1 FP31BP1 Bit 4 FP27BP0 FP29BP0 FP31BP0 Bit 3 FP26BP3 FP28BP3 FP30BP3 Bit 2 FP26BP2 FP28BP2 FP30BP2 Bit 1 FP26BP1 FP28BP1 FP30BP1 Bit 0 FP26BP0 FP28BP0 FP30BP0
0x0138–0x013F Inter IC Bus (IIC1) Map
Address 0x0138 0x0139 0x013A 0x013B 0x013C 0x013D 0x013E 0x013F Name IB1AD IB1FD IB1CR IB1SR IB1DR IB1CR2 Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 ADR7 IBC7 IBEN TCF Bit 6 ADR6 IBC6 IBIE IAAS Bit 5 ADR5 IBC5 MS/SL IBB Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 Bit 2 ADR2 IBC2 0 RSTA SRW Bit 1 ADR1 IBC1 0 Bit 0 0
IBC0 IBSWAI RXAK
IBIF D1 ADR9 0 0
D7 GCEN 0 0
D6 ADTYPE 0 0
D5 0 0 0
D3 0 0 0
D2 ADR10 0 0
D0 ADR8 0 0
0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map
Address 0x0140 0x0141 0x0142 0x0143 0x0144 0x0145 0x0146 0x0147 Name CAN0CTL0 CAN0CTL1 CAN0BTR0 CAN0BTR1 CAN0RFLG CAN0RIER CAN0TFLG CAN0TIER Bit 7 R RXFRM W R CANE W R SJW1 W R SAMP W R WUPIF W R WUPIE W R 0 W R 0 W Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME BORM BRP3 TSEG13 TSTAT1 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK
CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0
LISTEN BRP4 TSEG20 RSTAT0
BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1
BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0
RSTATE1 0 0
RSTATE0 0 0
TSTATE1 0 0
TSTATE0 TXE2 TXEIE2
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 995
Appendix E Detailed Register Map
0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map (continued)
Address 0x0148 0x0149 0x014A 0x014B 0x014C 0x014D 0x014E 0x014F Name CAN0TARQ CAN0TAAK CAN0TBSEL CAN0IDAC Reserved CAN0MISC CAN0RXERR CAN0TXERR Bit 7 R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AM7 W R AC7 W R AM7 W R CAN0RXFG W R W Bit 6 0 0 0 0 0 0 RXERR6 TXERR6 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 0 0 0 RXERR3 TXERR3 Bit 2 ABTRQ2 ABTAK2 Bit 1 ABTRQ1 ABTAK1 Bit 0 ABTRQ0 ABTAK0
TX2 IDHIT2 0 0 RXERR2 TXERR2
TX1 IDHIT1 0 0 RXERR1 TXERR1
TX0 IDHIT0 0
IDAM1 0 0 RXERR5 TXERR5
IDAM0 0 0 RXERR4 TXERR4
BOHOLD RXERR0 TXERR0
0x0150– CAN0IDAR0– 0x0153 CAN0IDAR3 0x0154– CAN0IDMR0– 0x0157 CAN0IDMR3 0x0158– CAN0IDAR4– 0x015B CAN0IDAR7 0x015C CAN0IDMR4– – CAN0IDMR7 0x015F 0x0160– 0x016F 0x0170– 0x017F
AC6 AM6 AC6 AM6
AC5 AM5 AC5 AM5
AC4 AM4 AC4 AM4
AC3 AM3 AC3 AM3
AC2 AM2 AC2 AM2
AC1 AM1 AC1 AM1
AC0 AM0 AC0 AM0
FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)
CAN0TXFG
Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address 0xXXX0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 R R W R R W R R W R R W Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
0xXXX1
ID9
ID8
ID7
0xXXX2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
0xXXX3
MC9S12XHZ512 Data Sheet, Rev. 1.03 996 Freescale Semiconductor
Appendix E Detailed Register Map
Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address Name Bit 7 DB7 Bit 6 DB6 Bit 5 DB5 Bit 4 DB4 Bit 3 DB3 Bit 2 DB2 Bit 1 DB1 Bit 0 DB0 0xXXX4 R CANxRDSR0– – W CANxRDSR7 0xXXXB R 0xXXXC CANRxDLR W R 0xXXXD Reserved W R 0xXXXE CANxRTSRH W R 0xXXXF CANxRTSRL W Extended ID R CANxTIDR0 W 0xXX10 Standard ID R W Extended ID R 0xXX0x CANxTIDR1 W XX10 Standard ID R W Extended ID R CANxTIDR2 W 0xXX12 Standard ID R W Extended ID R CANxTIDR3 W 0xXX13 Standard ID R W 0xXX14 R CANxTDSR0– – W CANxTDSR7 0xXX1B R 0xXX1C CANxTDLR W R 0xXX1D CANxTTBPR W R 0xXX1E CANxTTSRH W R 0xXX1F CANxTTSRL W
DLC3
DLC2
DLC1
DLC0
TSR15 TSR7
TSR14 TSR6
TSR13 TSR5
TSR12 TSR4
TSR11 TSR3
TSR10 TSR2
TSR9 TSR1
TSR8 TSR0
ID28 ID10 ID20 ID2 ID14
ID27 ID9 ID19 ID1 ID13
ID26 ID8 ID18 ID0 ID12
ID25 ID7 SRR=1 RTR ID11
ID24 ID6 IDE=1 IDE=0 ID10
ID23 ID5 ID17
ID22 ID4 ID16
ID21 ID3 ID15
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 997
Appendix E Detailed Register Map
0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 1 of 2)
Address 0x0180 0x0181 0x0182 0x0183 0x0184 0x0185 0x0186 0x0187 0x0188 0x0189 0x018A 0x018B 0x018C 0x018D 0x018E 0x018F 0x0190 0x0191 0x0192 0x0193 0x0194 0x0195 Name CAN1CTL0 CAN1CTL1 CAN1BTR0 CAN1BTR1 CAN1RFLG CAN1RIER CAN1TFLG CAN1TIER CAN1TARQ CAN1TAAK CAN1TBSEL CAN1IDAC Reserved CAN1MISC CAN1RXERR CAN1TXERR CAN1IDAR0 CAN1IDAR1 CAN1IDAR2 CAN1IDAR3 CAN1IDMR0 CAN1IDMR1 Bit 7 R RXFRM W R CANE W R SJW1 W R SAMP W R WUPIF W R WUPIE W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AC7 W R AC7 W R AC7 W R AM7 W R AM7 W Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME BORM BRP3 TSEG13 TSTAT1 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK
CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6
LISTEN BRP4 TSEG20 RSTAT0
BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1
BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0
RSTATE1 0 0 0 0 0
RSTATE0 0 0 0 0 0
TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3
TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2
TX2 IDHIT2 0 0 RXERR2 TXERR2
TX1 IDHIT1 0 0 RXERR1 TXERR1
TX0 IDHIT0 0
IDAM1 0 0 RXERR5 TXERR5
IDAM0 0 0 RXERR4 TXERR4
BOHOLD RXERR0 TXERR0
AC6 AC6 AC6 AC6 AM6 AM6
AC5 AC5 AC5 AC5 AM5 AM5
AC4 AC4 AC4 AC4 AM4 AM4
AC3 AC3 AC3 AC3 AM3 AM3
AC2 AC2 AC2 AC2 AM2 AM2
AC1 AC1 AC1 AC1 AM1 AM1
AC0 AC0 AC0 AC0 AM0 AM0
MC9S12XHZ512 Data Sheet, Rev. 1.03 998 Freescale Semiconductor
Appendix E Detailed Register Map
0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 2 of 2)
Address 0x0196 0x0197 0x0198 0x0199 0x019A 0x019B 0x019C 0x019D 0x019E 0x019F 0x01A0– 0x01AF 0x01B0– 0x01BF Name CAN1IDMR2 CAN1IDMR3 CAN1IDAR4 CAN1IDAR5 CAN1IDAR6 CAN1IDAR7 CAN1IDMR4 CAN1IDMR5 CAN1IDMR6 CAN1IDMR7 R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 AM7 AM7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 Bit 6 AM6 AM6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 Bit 5 AM5 AM5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 Bit 4 AM4 AM4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 Bit 3 AM3 AM3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 Bit 2 AM2 AM2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 Bit 1 AM1 AM1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 Bit 0 AM0 AM0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0
CAN1RXFG
FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)
CAN1TXFG
0x01C0–0x01FF Motor Controller 10-bit 12-Channels (MC) Map
Address 0x01C0 0x01C1 0x01C2 0x01C3 0x01C4– 0x01CF 0x01D0 0x01D1 0x01D2 Name MCCTL0 MCCTL1 MCPER (hi) MCPER (lo) Reserved MCCC0 MCCC1 MCCC2 Bit 7 R 0 W R RECIRC W R 0 W R P7 W R 0 W R OM1 W R OM1 W R OM1 W Bit 6 MCPRE1 0 0 Bit 5 MCPRE0 0 0 Bit 4 MCSWAI 0 0 Bit 3 FAST 0 0 Bit 2 DITH 0 Bit 1 0 0 Bit 0 MCTOIF MCTOIE P8 P0 0
P10 P2 0 0 0 0
P9 P1 0
P6 0
P5 0
P4 0
P3 0 0 0 0
OM0 OM0 OM0
AM1 AM1 AM1
AM0 AM0 AM0
CD1 CD1 CD1
CD0 CD0 CD0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 999
Appendix E Detailed Register Map
0x01C0–0x01FF Motor Controller 10-bit 12-Channels (MC) Map (continued)
Address 0x01D3 0x01D4 0x01D5 0x01D6 0x01D7 0x01D8 0x01D9 0x01DA 0x01DB 0x01DC– 0x01DF 0x01E0 0x01E1 0x01E2 0x01E3 0x01E4 0x01E5 0x01E6 0x01E7 0x01E8 0x01E9 0x01EA 0x01EB 0x01EC Name MCCC3 MCCC4 MCCC5 MCCC6 MCCC7 MCCC8 MCCC9 MCCC10 MCCC11 Reserved MCDC0 (hi) MCDC0 (lo) MCDC1 (hi) MCDC1 (lo) MCDC2 (hi) MCDC2 (lo) MCDC3 (hi) MCDC3 (lo) MCDC4 (hi) MCDC4 (lo) MCDC5 (hi) MCDC5 (lo) MCDC6 (hi) R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 OM1 OM1 OM1 OM1 OM1 OM1 OM1 OM1 OM1 0 Bit 6 OM0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 OM0 0 S Bit 5 AM1 AM1 AM1 AM1 AM1 AM1 AM1 AM1 AM1 0 S Bit 4 AM0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 AM0 0 S Bit 3 0 0 0 0 0 0 0 0 0 0 S Bit 2 0 0 0 0 0 0 0 0 0 0 Bit 1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 CD1 0 Bit 0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 CD0 0
S D7 S D7 S D7 S D7 S D7 S D7 S
D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10
D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9
D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
MC9S12XHZ512 Data Sheet, Rev. 1.03 1000 Freescale Semiconductor
Appendix E Detailed Register Map
0x01C0–0x01FF Motor Controller 10-bit 12-Channels (MC) Map (continued)
Address 0x01ED 0x01EE 0x01EF 0x01F0 0x01F1 0x01F2 0x01F3 0x01F4 0x01F5 0x01F6 0x01F7 0x01F8– 0x01FF Name MCDC6 (lo) MCDC7 (hi) MCDC7 (lo) MCDC8 (hi) MCDC8 (lo) MCDC9 (hi) MCDC9 (lo) MCDC10 (hi) MCDC10 (lo) MCDC11 (hi) MCDC11 (lo) Reserved R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 D7 S D7 S D7 S D7 S D7 S D7 0 Bit 6 D6 S Bit 5 D5 S Bit 4 D4 S Bit 3 D3 S Bit 2 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 0 Bit 1 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 0 Bit 0 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 0
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 0
D5 0
D4 0
D3 0
0x0200–0x027F Port Integration Module (PIM) Map 5 of 5
Address 0x0200 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 Name PTT PTIT DDRT RDRT PERT PPST WOMT SRRT Bit 7 R PTT7 W R PTIT7 W R DDRT7 W R RDRT7 W R PERT7 W R PPST7 W R WOMT7 W R SRRT7 W Bit 6 PTT6 PTIT6 Bit 5 PTT5 PTIT5 Bit 4 PTT4 PTIT4 Bit 3 PTT3 PTIT3 Bit 2 PTT2 PTIT2 Bit 1 PTT1 PTIT1 Bit 0 PTT0 PTIT0
DDRT6 RDRT6 PERT6 PPST6 WOMT6 SRRT6
DDRT5 RDRT5 PERT5 PPST5 WOMT5 SRRT5
DDRT4 RDRT4 PERT4 PPST4 WOMT4 SRRT4
DDRT3 RDRT3 PERT3 PPST3 0
DDRT2 RDRT2 PERT2 PPST2 MODRR2 SRRT2
DDRT1 RDRT1 PERT1 PPST1 MODRR1 SRRT1
DDRT0 RDRT0 PERT0 PPST0 MODRR0 SRRT0
SRRT3
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 1001
Appendix E Detailed Register Map
0x0200–0x027F Port Integration Module (PIM) Map 5 of 5
Address 0x0208 0x0209 0x020A 0x020B 0x020C 0x020D 0x020E 0x020F 0x0210 0x0211 0x0212 0x0213 0x0214 0x0215 0x0216 0x0217 0x0218 0x0219 0x021A 0x021B 0x021C 0x021D 0x021E Name PTS PTIS DDRS RDRS PERS PPSS WOMS SRRS PTM PTIM DDRM RDRM PERM PPSM WOMM SRRM PTP PTIP DDRP RDRP PERP PPSP WOMP Bit 7 R PTS7 W R PTIS7 W R DDRS7 W R RDRS7 W R PERS7 W R PPSS7 W R WOMS7 W R SRRS7 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R PTP7 W R PTIP7 W R DDRP7 W R RDRP7 W R PERP7 W R PPSP7 W R WOMP7 W Bit 6 PTS6 PTIS6 Bit 5 PTS5 PTIS5 Bit 4 PTS4 PTIS4 Bit 3 PTS3 PTIS3 Bit 2 PTS2 PTIS2 Bit 1 PTS1 PTIS1 Bit 0 PTS0 PTIS0
DDRS7 RDRS6 PERS6 PPSS6 WOMS6 SRRS6 0 0 0 0 0 0 0 0
DDRS5 RDRS5 PERS5 PPSS5 WOMS5 SRRS5 PTM5 PTIM5
DDRS4 RDRS4 PERS4 PPSS4 WOMS4 SRRS4 PTM4 PTIM4
DDRS3 RDRS3 PERS3 PPSS3 WOMS3 SRRS3 PTM3 PTIM3
DDRS2 RDRS2 PERS2 PPSS2 WOMS2 SRRS2 PTM2 PTIM2
DDRS1 RDRS1 PERS1 PPSS1 WOMS1 SRRS1 PTM1 PTIM1
DDRS0 RDRS0 PERS0 PPSS0 WOMS0 SRRS0 0 0 0 0 0 0 0 0
DDRM5 RDRM5 PERM5 PPSM5 WOMM5 SRRM5 PTP5 PTIP5
DDRM4 RDRM4 PERM4 PPSM4 WOMM4 SRRM4 PTP4 PTIP4
DDRM3 RDRM3 PERM3 PPSM3 WOMM3 SRRM3 PTP3 PTIP3
DDRM2 RDRM2 PERM2 PPSM2 WOMM2 SRRM2 PTP2 PTIP2
DDRM1 RDRM1 PERM1 PPSM1 WOMM1 SRRM1 PTP1 PTIP1
PTP6 PTIP6
PTP0 PTIP0
DDRP7 RDRP6 PERP6 PPSP6 WOMP6
DDRP5 RDRP5 PERP5 PPSP5 WOMP5
DDRP4 RDRP4 PERP4 PPSP4 WOMP4
DDRP3 RDRP3 PERP3 PPSP3 0
DDRP2 RDRP2 PERP2 PPSP2 WOMP2
DDRP1 RDRP1 PERP1 PPSP1 0
DDRP0 RDRP0 PERP0 PPSS0 WOMP0
MC9S12XHZ512 Data Sheet, Rev. 1.03 1002 Freescale Semiconductor
Appendix E Detailed Register Map
0x0200–0x027F Port Integration Module (PIM) Map 5 of 5
Address 0x021F 0x0220– 0x022F 0x0230 0x0231 0x0232 0x0233 0x0234 0x0235 0x0236 0x0237 0x0238 0x0239 0x023A 0x023B 0x023C 0x023D 0x023E 0x023F 0x0240 0x0241 0x0242 0x0243 0x0244 Name SRRP Reserved PTL PTIL DDRL RDRL PERL PPSL Reserved SRRL PTU PTIU DDRU SRRU PERU PPSU Reserved Reserved PTV PTIV DDRV SRRV PERV R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 SRRP7 0 Bit 6 SRRP6 0 Bit 5 SRRP5 0 Bit 4 SRRP4 0 Bit 3 SRRP3 0 Bit 2 SRRP2 0 Bit 1 SRRP1 0 Bit 0 SRRP0 0
PTL7 PTIL7
PTL6 PTIL6
PTL5 PTIL5
PTL4 PTIL4
PTL3 PTIL3
PTL2 PTIL2
PTL1 PTIL1
PTL0 PTIL0
DDRL7 RDRL7 PERL7 PPSL7 0
DDRL6 RDRL6 PERL6 PPSL6 0
DDRL5 RDRL5 PERL5 PPSL5 0
DDRL4 RDRL4 PERL4 PPSL4 0
DDRL3 RDRL3 PERL3 PPSL3 0
DDRL2 RDRL2 PERL2 PPSL2 0
DDRL1 RDRL1 PERL1 PPSL1 0
DDRL0 RDRL0 PERL0 PPSL0 0
SRRL7 PTU7 PTIU7
SRRL6 PTU6 PTIU6
SRRL5 PTU5 PTIU5
SRRL4 PTU4 PTIU4
SRRL3 PTU3 PTIU3
SRRL2 PTU2 PTIU2
SRRL1 PTU1 PTIU1
SRRL0 PTU0 PTIU0
DDRU7 SRRU7 PERU7 PPSU7 0 0
DDRU7 SRRU6 PERU6 PPSU6 0 0
DDRU SRRU5 PERU5 PPSU5 0 0
DDRU4 SRRU4 PERU4 PPSU4 0 0
DDRU3 SRRU3 PERU3 PPSU3 0 0
DDRU2 SRRU2 PERU2 PPSU2 0 0
DDRU1 SRRU1 PERU1 PPSU1 0 0
DDRU0 SRRU0 PERU0 PPSU0 0 0
PTV7 PTIV7
PTV6 PTIV6
PTV5 PTIV5
PTV4 PTIV4
PTV3 PTIV3
PTV2 PTIV2
PTV1 PTIV1
PTV0 PTIV0
DDRV7 SRRV7 PERV7
DDRV7 SRRV6 PERV6
DDRV SRRV5 PERV5
DDRV4 SRRV4 PERV4
DDRV3 SRRV3 PERV3
DDRV2 SRRV2 PERV2
DDRV1 SRRV1 PERV1
DDRV0 SRRV0 PERV0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 1003
Appendix E Detailed Register Map
0x0200–0x027F Port Integration Module (PIM) Map 5 of 5
Address 0x0245 0x0246 0x0247 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B Name PPSV Reserved Reserved PTW PTIW DDRW SRRW PERW PPSW Reserved Reserved Reserved PTAD Reserved PTIAD Reserved DDRAD Reserved RDRAD Reserved PERAD Reserved PPSAD R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PPSV7 0 0 Bit 6 PPSV6 0 0 Bit 5 PPSV5 0 0 Bit 4 PPSV4 0 0 Bit 3 PPSV3 0 0 Bit 2 PPSV2 0 0 Bit 1 PPSV1 0 0 Bit 0 PPSV0 0 0
PTW7 PTIW7
PTW6 PTIW6
PTW5 PTIW5
PTW4 PTIW4
PTW3 PTIW3
PTW2 PTIW2
PTW1 PTIW1
PTW0 PTIW0
DDRW7 SRRW7 PERW7 PPSW7 0 0 0
DDRW7 SRRW6 PERW6 PPSW6 0 0 0
DDRW SRRW5 PERW5 PPSW5 0 0 0
DDRW4 SRRW4 PERW4 PPSW4 0 0 0
DDRW3 SRRW3 PERW3 PPSW3 0 0 0
DDRW2 SRRW2 PERW2 PPSW2 0 0 0
DDRW1 SRRW1 PERW1 PPSW1 0 0 0
DDRW0 SRRW0 PERW0 PPSW0 0 0 0
PTAD7 0
PTAD6 0
PTAD5 0
PTAD4 0
PTAD3 0
PTAD2 0
PTAD1 0
PTAD0 0
PTIAD7 0
PTIAD6 0
PTIAD5 0
PTIAD4 0
PTIAD3 0
PTIAD2 0
PTIAD1 0
PTIAD0 0
DDRAD7 0
DDRAD6 0
DDRAD5 0
DDRAD4 0
DDRAD3 0
DDRAD2 0
DDRAD1 0
DDRAD0 0
RD1AD7 0
RDRAD6 0
RDRAD5 0
RDRAD4 0
RDRAD3 0
RDRAD2 0
RDRAD1 0
RDRAD0 0
PERAD7 0
PERAD6 0
PERAD5 0
PERAD4 0
PERAD3 0
PERAD2 0
PERAD1 0
PERAD0 0
PPSAD7
PPSAD6
PPSAD5
PPSAD4
PPSAD3
PPSAD2
PPSAD1
PPSAD0
MC9S12XHZ512 Data Sheet, Rev. 1.03 1004 Freescale Semiconductor
Appendix E Detailed Register Map
0x0200–0x027F Port Integration Module (PIM) Map 5 of 5
Address 0x025C 0x025D 0x025E 0x025F 0x0260– 0x027F Name Reserved PIEAD Reserved PIFAD Reserved Bit 7 R 0 W R PIEAD7 W R 0 W R PIFAD7 W R 0 W Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
PIEAD6 0
PIEAD5 0
PIEAD4 0
PIEAD3 0
PIEAD2 0
PIEAD1 0
PIEAD0 0
PIFAD6 0
PIFAD5 0
PIFAD4 0
PIFAD3 0
PIFAD2 0
PIFAD1 0
PIFAD0 0
0x0280–0x0287 Stepper Stall Detector (SSD4) Map
Address 0x0280 0x0281 0x0282 0x0283 0x0284 0x0285 0x0286 0x0287 Name RTZ4CTL MDC4CTL SSD4CTL SSD4FLG MDC4CNT(hi) MDC4CNT(lo) ITG4ACC(hi) ITG4ACC(lo) R W R W R W R W R W R W R W R W Bit 7 ITG MCZIE RTZE MCZIF Bit 6 DCOIL MODMC SDCPU 0 Bit 5 RCIR RDMCL SSDWAI 0 Bit 4 POL PRE FTST 0 Bit 3 0 0 FLMC 0 0 Bit 2 0 0 Bit 1 STEP AOVIE ACLKS 0 AOVIF Bit 0
MCEN 0 0
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x0288–0x028F Stepper Stall Detector (SSD0) Map
Address 0x0288 Name RTZ0CTL Bit 7 ITG MCZIE RTZE MCZIF Bit 6 DCOIL MODMC SDCPU 0 Bit 5 RCIR RDMCL SSDWAI 0 Bit 4 POL PRE FTST 0 Bit 3 0 0 FLMC 0 0 Bit 2 0 0 Bit 1 STEP AOVIE ACLKS 0 AOVIF Bit 0 R W R 0x0289 MDC0CTL W R 0x028A SSD0CTL W R 0x028B SSD0FLG W R 0x028C MDC0CNT(hi) W
MCEN 0 0
MDCCNT[15:8]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 1005
Appendix E Detailed Register Map
0x0288–0x028F Stepper Stall Detector (SSD0) Map (continued)
Address Name R W R ITG0ACC(hi) W R ITG0ACC(lo) W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x028D MDC0CNT(lo) 0x028E 0x028F
MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x0290–0x0297 Stepper Stall Detector (SSD1) Map
Address 0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297 Name RTZ1CTL MDC1CTL SSD1CTL SSD1FLG MDC1CNT(hi) MDC1CNT(lo) ITG1ACC(hi) ITG1ACC(lo) R W R W R W R W R W R W R W R W Bit 7 ITG MCZIE RTZE MCZIF Bit 6 DCOIL MODMC SDCPU 0 Bit 5 RCIR RDMCL SSDWAI 0 Bit 4 POL PRE FTST 0 Bit 3 0 0 FLMC 0 0 Bit 2 0 0 Bit 1 STEP AOVIE ACLKS 0 AOVIF Bit 0
MCEN 0 0
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x0298–0x029F Stepper Stall Detector (SSD2) Map
Address 0x0298 0x0299 0x029A 0x029B Name RTZ2CTL MDC2CTL SSD2CTL SSD2FLG R W R W R W R W R W R W R W R W Bit 7 ITG MCZIE RTZE MCZIF Bit 6 DCOIL MODMC SDCPU 0 Bit 5 RCIR RDMCL SSDWAI 0 Bit 4 POL PRE FTST 0 Bit 3 0 0 FLMC 0 0 Bit 2 0 0 Bit 1 STEP AOVIE ACLKS 0 AOVIF Bit 0
MCEN 0 0
0x029C MDC2CNT(hi) 0x029D MDC2CNT(lo) 0x029E 0x029F ITG2ACC(hi) ITG2ACC(lo)
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
MC9S12XHZ512 Data Sheet, Rev. 1.03 1006 Freescale Semiconductor
Appendix E Detailed Register Map
0x02A0–0x02A7 Stepper Stall Detector (SSD3) Map
Address 0x02A0 0x02A1 0x02A2 0x02A3 Name RTZ3CTL MDC3CTL SSD3CTL SSD3FLG R W R W R W R W R W R W R W R W Bit 7 ITG MCZIE RTZE MCZIF Bit 6 DCOIL MODMC SDCPU 0 Bit 5 RCIR RDMCL SSDWAI 0 Bit 4 POL PRE FTST 0 Bit 3 0 0 FLMC 0 0 Bit 2 0 0 Bit 1 STEP AOVIE ACLKS 0 AOVIF Bit 0
MCEN 0 0
0x02A4 MDC3CNT(hi) 0x02A5 MDC3CNT(lo) 0x02A6 0x02A7 ITG3ACC(hi) ITG3ACC(lo)
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x02A8–0x02AF Stepper Stall Detector (SSD5) Map
Address 0x02A8 0x02A9 0x02AA 0x02AB Name RTZ5CTL MDC5CTL SSD5CTL SSD5FLG R W R W R W R W R W R W R W R W Bit 7 ITG MCZIE RTZE MCZIF Bit 6 DCOIL MODMC SDCPU 0 Bit 5 RCIR RDMCL SSDWAI 0 Bit 4 POL PRE FTST 0 Bit 3 0 0 FLMC 0 0 Bit 2 0 0 Bit 1 STEP AOVIE ACLKS 0 AOVIF Bit 0
MCEN 0 0
0x02AC MDC5CNT(hi) 0x02AD MDC5CNT(lo) 0x02AE 0x02AF ITG5ACC(hi) ITG5ACC(lo)
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x02B0–0x02EF Reserved
Address 0x02B0– 0x02EF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 1007
Appendix E Detailed Register Map
0x02F0–0x02F7 Voltage Regulator (VREG_3V3) Map
Address 0x02F0 0x02F1 0x02F2 0x02F3 0x02F4 0x02F5 0x02F6 0x02F7 Name VREGHTCL VREGCTRL VREGAPICL VREGAPITR VREGAPIRH VREGAPIRL Reserved Reserved Bit 7 R W R 0 W R APICLK W R APITR5 W R 0 W R APIR7 W R 0 W R 0 W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved for Factory Test 0 0 0 0 0 0 0 0 LVDS LVIE APIE 0 LVIF APIF 0
APIFE APITR0 APIR10 APIR2 0 0
APITR4 0
APITR3 0
APITR2 0
APITR1 APIR11 APIR3 0 0
APIR9 APIR1 0 0
APIR8 APIR0 0 0
APIR6 0 0
APIR5 0 0
APIR4 0 0
0x02F8–0x02FF Reserved
Address 0x02F8– 0x02FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map
Address 0x0300 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 Name PWME Bit 7 Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 Bit 3 PWME3 PPOL3 PCLK3 0 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 R PWME7 W R PWMPOL PPOL7 W R PWMCLK PCLK7 W R 0 PWMPRCLK W R PWMCAE CAE7 W R PWMCTL CON67 W R 0 PWMTST Test Only W R 0 PWMPRSC W R PWMSCLA Bit 7 W R PWMSCLB Bit 7 W
CAE3 PSWAI 0 0
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 1008 Freescale Semiconductor
Appendix E Detailed Register Map
0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map
Address 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 0x0314 0x0315 0x0316 0x0317 0x0318 0x0319 0x031A 0x031B 0x031C 0x031D 0x031E 0x031F 0x0320 Name R W R PWMSCNTB W R PWMCNT0 W R PWMCNT1 W R PWMCNT2 W R PWMCNT3 W R PWMCNT4 W R PWMCNT5 W R PWMCNT6 W R PWMCNT7 W R PWMPER0 W R PWMPER1 W R PWMPER2 W R PWMPER3 W R PWMPER4 W R PWMPER5 W R PWMPER6 W R PWMPER7 W R PWMDTY0 W R PWMDTY1 W R PWMDTY2 W R PWMDTY3 W R PWMDTY4 W PWMSCNTA Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 6 Bit 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 Bit 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 Bit 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 1009
Appendix E Detailed Register Map
0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map
Address 0x0321 0x0322 0x0323 Name PWMDTY5 PWMDTY6 PWMDTY7 R W R W R W R W R W R W R W Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 6 6 6 Bit 5 5 5 5 0 PWM RSTRT 0 0 0 Bit 4 4 4 4 Bit 3 3 3 3 0 PWMLVL 0 0 0 0 0 0 0 0 0 Bit 2 2 2 2 PWM7IN PWM7INL 0 0 0 Bit 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 PWM7 ENA 0 0 0
0x0324
PWMSDN
PWMIF 0 0 0
PWMIE 0 0 0
0x0325 0x0326 0x0327
Reserved Reserved Reserved
0x0328–0x033F Reserved
Address 0x0328– 0x033F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0340–0x0367 Periodic Interrupt Timer (PIT) Map
Address 0x0340 0x0341 0x0342 0x0343 0x0344 0x0345 0x0346 0x0347 0x0348 0x0349 Name PITCFLMT PITFLT PITCE PITMUX PITINTE PITTF PITMTLD0 PITMTLD1 PITLD0 (hi) PITLD0 (lo) Bit 7 R PITE W R 0 W R 0 W R 0 W R 0 W R 0 W R PMTLD7 W R PMTLD7 W R PLD15 W R PLD7 W Bit 6 PITSWAI 0 0 0 0 0 Bit 5 PITFRZ 0 0 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 PFLT3 PCE3 PMUX3 PINTE3 PTF3 PMTLD3 PMTLD3 PLD11 PLD3 Bit 2 0 0 PFLT2 PCE2 PMUX2 PINTE2 PTF2 PMTLD2 PMTLD2 PLD10 PLD2 Bit 1 0 PFLMT1 0 PFLT1 PCE1 PMUX1 PINTE1 PTF1 PMTLD1 PMTLD1 PLD9 PLD1 Bit 0 0 PFLMT0 0 PFLT0 PCE0 PMUX0 PINTE0 PTF0 PMTLD0 PMTLD0 PLD8 PLD0
PMTLD6 PMTLD6 PLD14 PLD6
PMTLD5 PMTLD5 PLD13 PLD5
PMTLD4 PMTLD4 PLD12 PLD4
MC9S12XHZ512 Data Sheet, Rev. 1.03 1010 Freescale Semiconductor
Appendix E Detailed Register Map
0x0340–0x0367 Periodic Interrupt Timer (PIT) Map (continued)
Address 0x034A 0x034B 0x034C 0x034D 0x034E 0x034F 0x0350 0x0351 0x0352 0x0353 0x0354 0x0355 0x0356 0x0357 0x0358– 0x0367 Name PITCNT0 (hi) PITCNT0 (lo) PITLD1 (hi) PITLD1 (lo) PITCNT1 (hi) PITCNT1 (lo) PITLD2 (hi) PITLD2 (lo) PITCNT2 (hi) PITCNT2 (lo) PITLD3 (hi) PITLD3 (lo) PITCNT3 (hi) PITCNT3 (lo) Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PCNT15 PCNT7 PLD15 PLD7 PCNT15 PCNT7 PLD15 PLD7 PCNT15 PCNT7 PLD15 PLD7 PCNT15 PCNT7 0 Bit 6 PCNT14 PCNT6 PLD14 PLD6 PCNT14 PCNT6 PLD14 PLD6 PCNT14 PCNT6 PLD14 PLD6 PCNT14 PCNT6 0 Bit 5 PCNT13 PCNT5 PLD13 PLD5 PCNT13 PCNT5 PLD13 PLD5 PCNT13 PCNT5 PLD13 PLD5 PCNT13 PCNT5 0 Bit 4 PCNT12 PCNT4 PLD12 PLD4 PCNT12 PCNT4 PLD12 PLD4 PCNT12 PCNT4 PLD12 PLD4 PCNT12 PCNT4 0 Bit 3 PCNT11 PCNT3 PLD11 PLD3 PCNT11 PCNT3 PLD11 PLD3 PCNT11 PCNT3 PLD11 PLD3 PCNT11 PCNT3 0 Bit 2 PCNT10 PCNT2 PLD10 PLD2 PCNT10 PCNT2 PLD10 PLD2 PCNT10 PCNT2 PLD10 PLD2 PCNT10 PCNT2 0 Bit 1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 0 Bit 0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 0
0x0368–0x037F Reserved
Address 0x0368– 0x037F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 1011
Appendix E Detailed Register Map
0x0380–0x03BF XGATE Map (Sheet 1 of 3)
Address 0x0380 Name XGMCTL R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 XGEM XGE 0 Bit 6 0 XGFRZM XGFRZ Bit 5 0 XGDBGM XGDBG Bit 4 0 XGSSM XGSS Bit 3 0 XGFACTM XGFACT XGCHID[6:0] 0 Bit 2 0 Bit 1 0 XGS WEIFM XGSWEIF Bit 0 XGIEM
0x0381 0x0382 0x0383 0x0384 0x0385 0x0386 0x0387 0x0388 0x0389 0x038A 0x023B 0x023C 0x038D 0x038E 0x038F 0x0390 0x0391 0x0392 0x0393 0x0394 0x0395
XGMCTL XGCHID Reserved Reserved Reserved XGVBR XGVBR XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF
XGIE
XGVBR[15:8] XGVBR[7:1] 0 0 0 0 0 0 0 0
XGIF_78 XGIF_70 XGIF_68 XGIF_60 XGIF_58 XGIF_50 XGIF_48 XGIF_40 XGIF_38 XGIF_30 XGIF_28 XGIF_20 XGIF_18 XGIF_10
XGIF_77 XGIF_6F XGIF_67 XGIF_5F XGIF_57 XGIF_4F XGIF_47 XGIF_3F XGIF_37 XGIF_2F XGIF_27 XGIF_1F XGIF_17
XGIF_76 XGIF_6E XGIF_66 XGIF_5E XGIF_56 XGIF_4E XGIF_46 XGIF_3E XGIF_36 XGIF_2E XGIF_26 XGIF_1E XGIF_16
XGIF_75 XGIF_6D XGIF_65 XGIF_5D XGIF_55 XGIF_4D XGIF_45 XGIF_3D XGIF_35 XGIF_2D XGIF_25 XGIF_1D XGIF_15
XGIF_74 XGIF_6C XGIF_64 XGIF_5C XGIF_54 XGIF_4C XGIF_44 XGIF_3C XGIF_34 XGIF_2C XGIF_24 XGIF_1C XGIF_14
XGIF_73 XGIF_6B XGIF_63 XGIF_5B XGIF_53 XGIF_4B XGIF_43 XGIF_3B XGIF_33 XGIF_2B XGIF_23 XGIF_1B XGIF_13
XGIF_72 XGIF_6A XGIF_62 XGIF_5A XGIF_52 XGIF_4A XGIF_42 XGIF_3A XGIF_32 XGIF_2A XGIF_22 XGIF_1A XGIF_12
XGIF_71 XGIF_69 XGIF_61 XGIF_59 XGIF_51 XGIF_49 XGIF_41 XGIF_39 XGIF_31 XGIF_29 XGIF_21 XGIF_19 XGIF_11
MC9S12XHZ512 Data Sheet, Rev. 1.03 1012 Freescale Semiconductor
Appendix E Detailed Register Map
0x0380–0x03BF XGATE Map (Sheet 2 of 3)
Address 0x0396 0x0397 0x0398 0x0399 0x039A 0x039B 0x039C 0x039D 0x039E 0x039F 0x03A0 0x03A1 0x03A2 0x03A3 0x03A4 0x03A5 0x03A6 0x03A7 0x03A8 0x03A9 0x03AA 0x03AB 0x03AC Name XGIF XGIF XGSWT (hi) XGSWT (lo) XGSEM (hi) XGSEM (lo) Reserved XGCCR XGPC (hi) XGPC (lo) Reserved Reserved XGR1 (hi) XGR1 (lo) XGR2 (hi) XGR2 (lo) XGR3 (hi) XGR3 (lo) XGR4 (hi) XGR4 (lo) XGR5 (hi) XGR5(lo) XGR6 (hi) Bit 7 R XGIF_0F W R 0 W R 0 W R W R 0 W R W R 0 W R 0 W R W R W R 0 W R 0 W R W R W R W R W R W R W R W R W R W R W R W Bit 6 XGIF_0E 0 0 Bit 5 XGIF_0D 0 0 Bit 4 XGIF_0C 0 Bit 3 XGIF_0B 0 Bit 2 XGIF_0A 0 0 Bit 1 XGIF_09 0 0 Bit 0 0 0 0
0 0 XGSWTM[7:0] XGSWT[7:0]
0
0
0 0 XGSEMM[7:0] XGSEM[7:0]
0
0
0
0 0
0 0
0 0
0
0
0
0
XGN
XGZ
XGV
XGC
XGPC[15:8] XGPC[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0
XGR1[15:8] XGR1[7:0] XGR2[15:8] XGR2[7:0] XGR3[15:8] XGR3[7:0] XGR4[15:8] XGR4[7:0] XGR5[15:8] XGR5[7:0] XGR6[15:8]
MC9S12XHZ512 Data Sheet, Rev. 1.03 Freescale Semiconductor 1013
Appendix E Detailed Register Map
0x0380–0x03BF XGATE Map (Sheet 3 of 3)
Address 0x03AD 0x03AE 0x03AF 0x03B0– 0x03BF Name XGR6 (lo) XGR7 (hi) XGR7 (lo) Reserved R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
XGR6[7:0] XGR7[15:8] XGR7[7:0] 0 0 0 0 0 0 0 0
0x03C0–0x07FF Reserved
Address 0x03C0 –0x07FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
MC9S12XHZ512 Data Sheet, Rev. 1.03 1014 Freescale Semiconductor
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