MCF51CN128

Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF51CN128 Rev. 4, 5/2009 MCF51CN128 MCF51CN128 ColdFire Microcontroller Cover: MCF51CN128 The MCF51CN128 device is a low-cost, low-power, high-performance 32-bit ColdFire V1 microcontroller (MCU) featuring 10/100 BASE-T/TX fast ethernet controller (FEC), media independent interface (MII) to connect an external physical transceiver (PHY), and multi-function external bus interface. MCF51CN128 also has multiple communication interfaces for various ethernet gateway applications. MCF51CN128 is the first ColdFire V1 device to incorporate ethernet and external bus interface along with new features to minimize power consumption and increase functionality in low-power modes. The MCF51CN128 features the following functional units: • 32-bit ColdFire V1 Central Processing Unit (CPU) – Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz CPU from 2.1 V to 1.8 V across temperature range of –40 °C to 85 °C – Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM (0.76 DMIPS/MHz from flash) – ColdFire Instruction Set Revision C (ISA_C) – Support for up to 45 peripheral interrupt requests and 7 software interrupts • On-Chip Memory – 128 KB Flash, 24 KB RAM – Flash read/program/erase over full operating voltage and temperature – On-chip memory aliased to create a contiguous memory space with off-chip memory – Security circuitry to prevent unauthorized access to Peripherals, RAM, and flash contents • Ethernet – FEC—10/100 BASE-T/TX, bus-mastering fast ethernet controller with direct memory access (DMA); supports half or full duplex; operation is limited to 3.0 V to 3.6 V 80 LQFP 14 mm × 14 mm 64 LQFP 10 mm × 10 mm 48 QFN 7 mm × 7 mm – MII—media independent interface to connect ethernet controller to external PHY; includes output clock for external PHY • External Bus – Mini-FlexBus—Multi-function external bus interface; supports up to 1 MB memories, gate-array logic, simple slave device or glueless interfaces to standard chip-selected asynchronous memories – Programmable options: access time per chip select, burst and burst-inhibited transfers per chip select, transfer direction, and address setup and hold times • Power-Saving Modes – Two low-power stop modes, one of which allows limited use of some peripherals (ADC, KBI, RTC) – Reduced-power wait mode shuts off CPU and allows full use of all peripherals; FEC can remain active and conduct DMA transfers to RAM and assert an interrupt to wake up the CPU upon completion – Low-power run and wait modes allow peripherals to run while the voltage regulator is in standby – Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents – Low-power external oscillator that can be used in stop3 mode to provide accurate clock source to active peripherals – Low-power real-time counter for use in run, wait, and stop modes with internal and external clock sources – 6 μs typical wake-up time from stop3 mode – Pins and clocks to peripherals not available in smaller packages are automatically disabled for reduced current consumption; no user interaction is needed • Clock Source Options – Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 25 MHz – Multi-Purpose Clock Generator (MCG) — Flexible clock source module with either frequency-locked-loop (FLL) or phase-lock loop (PLL) clock options. FLL can be controlled by internal or external reference and Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009. All rights reserved. • • • • includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and voltage. PLL derives a higher accuracy clock source derived by an external reference System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode and illegal address detection with programmable reset or exception response – Flash block protection Development Support – Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and 9S12x families debug modules – 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response – 64-entry processor status and debug data trace buffer with programmable start/stop conditions Peripherals – ADC—Up to 12 channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V – SCI—Three modules with optional 13-bit break – SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting – IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing – TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base, time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up without external components; runs in all MCU modes – MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler Input/Output – Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions – 16 keyboard interrupt (KBI) pins with selectable polarity – Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on all output pins – 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF) MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 2 Freescale Semiconductor Table of Contents 1 2 3 MCF51CN128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18 3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20 3.9 Multipurpose Clock Generator (MCG) Specifications . .21 3.10 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .23 3.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . .24 3.11.1 Receive Signal Timing Specifications . . . . . . . .24 3.11.2 Transmit Signal Timing Specifications . . . . . . . .25 3.11.3 Asynchronous Input Signal Timing Specifications25 3.11.4 MII Serial Management Timing Specifications .26 3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.12.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .28 3.12.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.12.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .32 3.12.5 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .35 3.13 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .36 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36 6.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 6.3 48-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Table 13..Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14..Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 15..MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 25 Table 16..MII Serial Management Channel Signal Timing . . . . . 26 Table 17..Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 18..TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 19..SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 20..12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 32 Table 21..12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 22..Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 23..Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 24..Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 25..Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 List of Figures Figure 1..MCF51CN128 Series Block Diagram . . . . . . . . . . . . . . 5 Figure 2..Pin Assignments in 80-Pin LQFP Package. . . . . . . . . . 6 Figure 3..Pin Assignments in 64-Pin LQFP Package. . . . . . . . . . 7 Figure 4..Pin Assignments in 48-Pin QFN Package. . . . . . . . . . . 8 Figure 5..Pull-up and Pull-down Typical Resistor Values . . . . . . 16 Figure 6..Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7..Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8..Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9..Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10..Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled) . . . . . . . . . . . . . 19 Figure 11..Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12..Typical Crystal or Resonator Circuit: Low Range/Low Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13..Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 23 Figure 14..Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 24 Figure 15..MII Receive Signal Timing Diagram . . . . . . . . . . . . . 25 Figure 16..MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 25 Figure 17..MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 25 Figure 18..MII Serial Management Channel TIming Diagram . . 26 Figure 19..Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 20..IRQ/KBIPx Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 21..Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 22..Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 28 Figure 23..SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 30 Figure 24..SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . 30 Figure 25..SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 31 Figure 26..SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 31 Figure 27..ADC Input Impedance Equivalency Diagram . . . . . . 33 4 5 6 7 List of Tables Table 1.. MCF51CN128 Series Device Comparison . . . . . . . . . . .4 Table 2.. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .8 Table 3.. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .12 Table 4.. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12 Table 5.. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13 Table 6.. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .14 Table 7.. ESD and Latch-Up Protection Characteristics . . . . . . .14 Table 8.. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 9.. Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18 Table 10..XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 11..MCG Frequency Specifications (Temperature Range = –40 to 125 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 12..Mini-FlexBus AC Timing Specifications . . . . . . . . . . . .23 MCF51CN128 ColdFire Microcontroller Advance Information Data Sheet, Rev. 4 3 Freescale Semiconductor MCF51CN128 Series Comparison 1 1.1 MCF51CN128 Series Comparison Device Comparison Table 1. MCF51CN128 Series Device Comparison MCF51CN128 Feature 80-pin Flash memory size (KB) RAM size (KB) V1 ColdFire core equiped with BDM (background debug module) and 2X3 Crossbar switch ADC (analog-to-digital converter) channels (12-bit) FEC (Fast Ethernet Controller with MII Interface) COP (computer operating properly) IIC1 (inter-integrated circuit) IIC2 IRQ (interrupt request input) KBI (keyboard interrupts) LVD (low-voltage detector) MCG (multipurpose clock generator) Port I/O 1 The following table compares the various device derivatives available within the MCF51CN128 series. 64-pin 128 24 Yes 12 Yes Yes Yes Yes Yes 48-pin 16 12 Yes Yes 6 70 16 54 16 Yes Yes Yes 38 8 RGPIO (rapid general-purpose I/O) RTC (real-time counter) SCI1, SCI2 & SCI3 (serial communications interface) SPI1 & SPI2 (serial peripheral interface) TPM1 (Timer/PWM Module) channels TPM2 channels MTIM1 & MTIM2 External Timer Clocks Mini-FlexBus XOSC (crystal oscillator) 1 2 3 3 3 3 Yes2 3 3 2 Yes 1 0 Yes 1 0 All GPIO are muxed with other functions TMRCLK2 is not available on the 48 pin package, although MTIM2 can be used as an internal timebase using on-chip clock sources. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 4 Freescale Semiconductor MCF51CN128 Series Comparison 1.2 Block Diagram The following figure shows the connections between the MCF51CN128 series pins and modules. ADC BDM Port D: BKGD/MS BKGD/MS/PTD6/RGPIO6 DBG INTC IIC2 Port C/G: SDA2 SCL2 Port E: KBI2P7 KBI2P6 KBI2P5 KBI2P4 KBI2P3 KBI2P2 KBI2P1 KBI2P0 Port G/I: KBI1P7 KBI1P6 KBI1P5 KBI1P4 KBI1P3 KBI1P2 KBI1P1 KBI1P0 Port D: ColdFire V1 core Port E: TPM1CH2 TPM1CH1 TPM1CH0 Port B, F or H* : TPM1CLK TPM1 RESET/PTC3 Port F/H: TPM2CH2 TPM2CH1 TPM2CH0 Port B, F or H* : TPM2CLK TPM2 SIM Port F: RGPIO15 RGPIO14 RGPIO13 RGPIO12 RGPIO11 RGPIO10 RGPIO9 RGPIO8 Port C KBI Port B Port A VDDA/ VREFH VSSA/ VREFL VDDA VREFH VSSA VREFL Port C: ADP3ADP0 Port D: ADP8ADP4 Port E: ADP11ADP9 Port C/G: SDA1 IIC1 SCL1 PTA7/MII_RX_DV/MOSI2 PTA6/MII_RXD0/MISO2 PTA5/MII_RXD1/SPSCK2 PTA4/MII_RXD2/RXD3 PTA3/MII_RXD3/TXD3 PTA2/MII_MDC/SCL2 PTA1/MII_MDIO/SDA2 PTA0/PHYCLK PTB7/MII_TXD2/TPM2CH1 PTB6/MII_TXD1/TPM2CH0 PTB5/MII_TXD0/SPSCK1 PTB4/MII_TX_EN/MISO1 PTB3/MII_TX_CLK/MOSI1 PTB2/MII_TX_ER/SS1 PTB1/MII_RX_ER/TMRCLK1 PTB0/MII_RX_CLK/SS2 PTC7/SDA2/SPSCK1/ADP8 PTC6/SCL2/MISO1/ADP9 PTC5/MOSI1/ADP10 PTC4/IRQ/SS1/ADP11 PTC2/MII_CRS/SDA1 PTC1/MII_COL/SCL1 PTC0/MII_TXD3/TPM2CH2 PTD7/RGPIO7/SPSCK2/ADP3 BKGD/MS/PTD6/RGPIO6 PTD5/RGPIO5/XTAL PTD4/RGPIO4/EXTAL PTD3/RGPIO3/RXD2/ADP4 PTD2/RGPIO2/TXD2/ADP5 PTD1/RGPIO1/RXD1/ADP6 PTD0/RGPIO0/TXD1/ADP7 PTE7/KBI2P7/FB_CS0/RXD3 PTE6/KBI2P6/FB_D0/TXD3 PTE5/KBI2P5/IRQ/TPM1CH2 PTE4/KBI2P4/CLKOUT/TPM1CH1 PTE3/KBI2P3/TPM1CH0 PTE2/KBI2P2/SS2/ADP0 PTE1/KBI2P1/MOSI2/ADP1 PTE0/KBI2P0/MISO2/ADP2 PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2 PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1 PTF5/RGPIO13/FB_D4/TPM2CH0 PTF4/RGPIO12/FB_D5/TMRCLK2 PTF3/RGPIO11/FB_A16/FB_AD16 PTF2/RGPIO10/FB_A17/FB_AD17 PTF1/RGPIO9/FB_A18/FB_AD18 PTF0/RGPIO8/FB_A19/FB_AD19 PTG7/KBI1P7/FB_D1 PTG6/KBI1P6/FB_D2 PTG5/KBI1P5/FB_D3 PTG4/KBI1P4/FB_RW PTG3/KBI1P3/FB_A5/FB_AD5/SDA1 PTG2/KBI1P2/FB_A6/FB_AD6/SCL1 PTG1/KBI1P1/FB_A7/FB_AD7/SDA2 PTG0/KBI1P0/FB_A8/FB_AD8/SCL2 PTH7/FB_A9/FB_AD9/TPM2CH2 PTH6/FB_A10/FB_AD10/TPM2CH1 PTH5/FB_A11/FB_AD11 PTH4/FB_A12/FB_AD12 PTH3/FB_D6/TPM2CH0 PTH2/FB_D7/TMRCLK1 PTH1/FB_OE PTH0/FB_A15/FB_AD15 PTJ5/FB_A0/FB_AD0 PTJ4/FB_A1/FB_AD1 PTJ3/FB_A2/FB_AD2 PTJ2/FB_A3/FB_AD3 PTJ1/FB_A4/FB_AD4 PTJ0/FB_ALE/FB_CS1 COP LVD FLASH 128 KB MCG XOSC EXTAL XTAL Port A: CLKOUT Port E Port D: RXD1 TXD1 Port D: RXD2 TXD2 Port E: RXD3 TXD3 Port C: SS1 SPSCK1 MOSI1 MISO1 Port H Port J Port G Port F RAM 24 KB Port A: MII_TX_CLK MII_RX_CLK MII_TX_EN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 Port B: MII_TX_ER MII_RX_DV MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3 MII_RX_ER MII_CRS Port C: MII_COL MII_MDC MII_MDIO RGPIO Port D: RGPIO7 RGPIO6 RGPIO5 RGPIO4 RGPIO3 RGPIO2 RGPIO1 RGPIO0 RTC MTIM1 Port B, F or H* : MTIM1CLK Port B, F or H* : MTIM2CLK MTIM2 MII Port F: FB_D7-FB_D0 Port H: FB_A19-FB_A16 FB_A11-FB_A8 Port G: FB_CS1 FB_CS0 OE Mini-FlexBus FB_RW FB_A5-FB_A2 Port I: FB_A15-FB_A12 FB_A7-FB_A6 Port E: FB_A1-FB_A0 SCI1 SCI2 SCI3 FEC VDD1 VSS1 VDD2 VSS2 VDD3 VSS3 VDD4 VSS4 SPI1 VREG Port C: External Interrupt IRQ Port D/E: SS2 SPI2 SPSCK2 MOSI2 MISO2 * TPMx and MTIMx external clocks each have the choice of being assigned to either TMRCLK1 or TMRCLK2. Figure 1. MCF51CN128 Series Block Diagram MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 5 Port D Pin Assignments 2 Pin Assignments PTJ5/FB_A0/FB_AD0 PTJ4/FB_A1/FB_AD1 PTJ3/FB_A2/FB_AD2 PTJ2/FB_A3/FB_AD3 PTJ1/FB_A4/FB_AD4 PTJ0/FB_ALE/FB_CS1 PTE7/KBI2P7/FB_CS0/RXD3 PTE6/KBI2P6/FB_D0/TXD3 PTE5/KBI2P5/IRQ/TPM1CH2 PTE4/KBI2P4/CLKOUT/TPM1CH1 PTE3/KBI2P3/TPM1CH0 PTE2/KBI2P2/SS2/ADP0 PTE1/KBI2P1/MOSI2/ADP1 PTE0/KBI2P0/MISO2/ADP2 PTD7/RGPIO7/SPSCK2/ADP3 BKGD/MS/PTD6/RGPIO6 PTD5/RGPIO5/XTAL PTD4/RGPIO4/EXTAL VSS4 VDD4 This section describes the pin assignments for the available packages. See for pin availability by package pin-count. VDD1 VSS1 PTA0/PHYCLK PTA1/MII_MDIO/SDA2 PTA2/MII_MDC/SCL2 PTA3/MII_RXD3/TXD3 PTA4/MII_RXD2/RXD3 PTA5/MII_RXD1/SPSCK2 PTA6/MII_RXD0/MISO2 PTA7/MII_RX_DV/MOSI2 PTB0/MII_RX_CLK/SS2 PTB1/MII_RX_ER/TMRCLK1 PTF0/RGPIO8/FB_A19/FB_AD19 PTF1/RGPIO9/FB_A18/FB_AD18 PTF2/RGPIO10/FB_A17/FB_AD17 PTF3/RGPIO11/FB_A16/FB_AD16 PTH0/FB_A15/FB_AD15 PTH1/FB_OE PTH2/FB_D7/TMRCLK1 PTH3/FB_D6/TPM2CH0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 80-Pin LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTG7/KBI1P7/FB_D1 PTG6/KBI1P6/FB_D2 PTG5/KBI1P5/FB_D3 PTG4/KBI1P4/FB_RW PTG3/KBI1P3/FB_A5/FB_AD5/SDA1 PTG2/KBI1P2/FB_A6/FB_AD6/SCL1 PTG1/KBI1P1/FB_A7/FB_AD7/SDA2 PTG0/KBI1P0/FB_A8/FB_AD8/SCL2 PTD3/RGPIO3/RXD2/ADP4 PTD2/RGPIO2/TXD2/ADP5 PTD1/RGPIO1/RXD1/ADP6 PTD0/RGPIO0/TXD1/ADP7 PTC7/SDA2/SPSCK1/ADP8 PTC6/SCL2/MISO1/ADP9 PTC5/MOSI1/ADP10 PTC4/IRQ/SS1/ADP11 VSSA VDDA VSS3 VDD3 Figure 2. Pin Assignments in 80-Pin LQFP Package MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 6 Freescale Semiconductor VDD2 VSS2 PTB2/MII_TX_ER/SS1 PTB3/MII_TX_CLK/MOSI1 PTB4/MII_TX_EN/MISO1 PTB5/MII_TXD0/SPSCK1 PTB6/MII_TXD1/TPM2CH0 PTB7/MII_TXD2/TPM2CH1 PTC0/MII_TXD3/TPM2CH2 PTC1/MII_COL/SCL1 PTC2/MII_CRS/SDA1 RESET/PTC3 PTF4/RGPIO12/FB_D5/TMRCLK2 PTF5/RGPIO13/FB_D4/TPM2CH0 PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1 PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2 PTH4/FB_A12/FB_AD12 PTH5/FB_A11/FB_AD11 PTH6/FB_A10/FB_AD10/TPM2CH1 PTH7/FB_A9/FB_AD9/TPM2CH2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Assignments 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTJ1/FB_A4/FB_AD4 PTJ0/FB_ALE/FB_CS1 PTE7/KBI2P7/FB_CS0/RXD3 PTE6/KBI2P6/FB_D0/TXD3 PTE5/KBI2P5/IRQ/TPM1CH2 PTE4/KBI2P4/CLKOUT/TPM1CH1 PTE3/KBI2P3/TPM1CH0 PTE2/KBI2P2/SS2/ADP0 PTE1/KBI2P1/MOSI2/ADP1 PTE0/KBI2P0/MISO2/ADP2 PTD7/RGPIO7/SPSCK2/ADP3 BKGD/MS/PTD6/RGPIO6 PTD5/RGPIO5/XTAL PTD4/RGPIO4/EXTAL VSS4 VDD4 VDD1 VSS1 PTA0/PHYCLK PTA1/MII_MDIO/SDA2 PTA2/MII_MDC/SCL2 PTA3/MII_RXD3/TXD3 PTA4/MII_RXD2/RXD3 PTA5/MII_RXD1/SPSCK2 PTA6/MII_RXD0/MISO2 PTA7/MII_RX_DV/MOSI2 PTB0/MII_RX_CLK/SS2 PTB1/MII_RX_ER/TMRCLK1 PTF0/RGPIO8/FB_A19/FB_AD19 PTF1/RGPIO9/FB_A18/FB_AD18 PTF2/RGPIO10/FB_A17/FB_AD17 PTF3/RGPIO11/FB_A16/FB_AD16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTG3/KBI1P3/FB_A5/FB_AD5/SDA1 PTG2/KBI1P2/FB_A6/FB_AD6/SCL1 PTG1/KBI1P1/FB_A7/FB_AD7/SDA2 PTG0/KBI1P0/FB_A8/FB_AD8/SCL2 PTD3/RGPIO3/RXD2/ADP4 PTD2/RGPIO2/TXD2/ADP5 PTD1/RGPIO1/RXD1/ADP6 PTD0/RGPIO0/TXD1/ADP7 PTC7/SDA2/SPSCK1/ADP8 PTC6/SCL2/MISO1/ADP9 PTC5/MOSI1/ADP10 PTC4/IRQ/SS1/ADP11 VSSA VDDA VSS3 VDD3 Figure 3. Pin Assignments in 64-Pin LQFP Package MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 7 VDD2 VSS2 PTB2/MII_TX_ER/SS1 PTB3/MII_TX_CLK/MOSI1 PTB4/MII_TX_EN/MISO1 PTB5/MII_TXD0/SPSCK1 PTB6/MII_TXD1/TPM2CH0 PTB7/MII_TXD2/TPM2CH1 PTC0/MII_TXD3/TPM2CH2 PTC1/MII_COL/SCL1 PTC2/MII_CRS/SDA1 RESET/PTC3 PTF4/RGPIO12/FB_D5/TMRCLK2 PTF5/RGPIO13/FB_D4/TPM2CH0 PTF6/RGPIO14/FB_A14/FB_AD14/TPM2CH1 PTF7/RGPIO15/FB_A13/FB_AD13/TPM2CH2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Assignments 47 PTE4/KBI2P4/CLKOUT/TPM1CH1 48 PTE5/KBI2P5/IRQ/TPM1CH2 44 PTE1/KBI2P1/MOSI2/ADP1 PTD7/RGPIO7/SPSCK2/ADP3 PTE0/KBI2P0/MISO2/ADP2 45 PTE2/KBI2P2/SS2/ADP0 46 PTE3/KBI2P3/TPM1CH0 BKGD/MS/PTD6/RGPIO6 PTD4/RGPIO4/EXTAL PTD5/RGPIO5/XTAL 43 42 41 40 39 38 VDD1 1 VSS1 PTA0/PHYCLK PTA1/MII_MDIO/SDA2 PTA2/MII_MDC/SCL2 PTA3/MII_RXD3/TXD3 PTA4/MII_RXD2/RXD3 PTA5/MII_RXD1/SPSCK2 PTA6/MII_RXD0/MISO2 PTA7/MII_RX_DV/MOSI2 PTB0/MII_RX_CLK/SS2 PTB1/MII_RX_ER/TMRCLK1 2 3 4 5 6 7 8 9 10 11 12 VDD2 13 VSS2 14 PTB2/MII_TX_ER/SS1 15 PTB3/MII_TX_CLK/MOSI1 16 PTB3/MII_TX_CLK/MOSI1 17 PTB5/MII_TXD0/SPSCK1 18 PTB6/MII_TXD1/TPM2CH0 19 PTB7/MII_TXD2/TPM2CH1 20 PTC0/MII_TXD3/TPM2CH2 21 PTC1/MII_COL/SCL1 22 PTC2/MII_CRS/SDA1 23 RESET/PTC3 24 48-Pin QFN Figure 4. Pin Assignments in 48-Pin QFN Package NOTE There is no electrical connection to the flag for 48-pin QFN packages. Table 2. Package Pin Assignments 80-Pin 1 2 3 64-Pin 1 2 3 48-Pin 1 2 3 Default Function VDD1 VSS1 PTA0 Alt 1 — — PHYCLK Alt 2 — — — Alt 3 — — — Comment — — — MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 8 Freescale Semiconductor 37 VDD4 36 PTD3/RGPIO3/RXD2/ADP4 35 PTD2/RGPIO2/TXD2/ADP5 34 PTD1/RGPIO1/RXD1/ADP6 33 PTD0/RGPIO0/TXD1/ADP7 32 PTC7/SDA2/SPSCK1/ADP8 31 PTC6/SCL2/MISO1/ADP9 30 PTC5/MOSI1/ADP10 29 PTC4/IRQ/SS1/ADP11 28 VSSA 27 VDDA 26 VSS3 25 VDD3 VSS4 Pin Assignments Table 2. Package Pin Assignments (continued) 80-Pin 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64-Pin 4 5 6 7 8 9 10 11 12 13 14 15 16 — — — — 17 18 19 20 21 22 23 24 25 26 27 48-Pin 4 5 6 7 8 9 10 11 12 — — — — — — — — 13 14 15 16 17 18 19 20 21 22 23 Default Function PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTA7 PTB0 PTB1 PTF0/RGPIO8 PTF1/RGPIO9 PTF2/RGPIO10 PTF3/RGPIO11 PTH0 PTH1 PTH2 PTH3 VDD2 VSS2 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTC0 PTC1 PTC2 Alt 1 MII_MDIO MII_MDC MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RX_DV MII_RX_CLK MII_RX_ER — — — — — — — — — — MII_TX_ER MII_TX_CLK MII_TX_EN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_COL MII_CRS Alt 2 — — TXD3 RXD3 SPSCK2 MISO2 MOSI2 SS2 — FB_A19/FB_AD19 FB_A18/FB_AD18 FB_A17/FB_AD17 FB_A16/FB_AD16 FB_A15/FB_AD15 FB_OE FB_D7 FB_D6 — — SS1 MOSI1 MISO1 SPSCK1 — — — — — Alt 3 SDA2 SCL2 — — — — — — TMRCLK1 — — — — — — TMRCLK1 TPM2CH0 — — — — — — TPM2CH0 TPM2CH1 TPM2CH2 SCL1 SDA1 — — — — — — — — — — — — — — — Comment — — — — — — — — — RGPIO_ENB selects between standard GPIO and RGPIO MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 9 Pin Assignments Table 2. Package Pin Assignments (continued) 80-Pin 32 64-Pin 28 48-Pin 24 Default Function RESET Alt 1 PTC3 Alt 2 — Alt 3 — Comment This pin is a bi-directional open drain pin and has an internal pullup. There is no clamp diode to VDD. DSE and SRE port controls for this bit have no effect. RGPIO_ENB selects between standard GPIO and RGPIO 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 29 30 31 32 — — — — 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 — — — — — — — — — — — 25 26 27 28 29 30 31 32 33 34 35 36 — — — — — — — PTF4/RGPIO12 PTF5/RGPIO13 PTF6/RGPIO14 PTF7/RGPIO15 PTH4 PTH5 PTH6 PTH7 VDD3 VSS3 VDDA VSSA PTC4 PTC5 PTC6 PTC7 PTD0/RGPIO0 PTD1/RGPIO1 PTD2/RGPIO2 PTD3/RGPIO3 PTG0 PTG1 PTG2 PTG3 PTG4 PTG5 PTG6 — — — — — — — — — — — — IRQ — SCL2 SDA2 — — — — KBI1P0 KBI1P1 KBI1P2 KBI1P3 KBI1P4 KBI1P5 KBI1P6 FB_D5 FB_D4 FB_A14/FB_AD14 FB_A13/FB_AD13 FB_A12/FB_AD12 FB_A11/FB_AD11 FB_A10/FB_AD10 FB_A9/FB_AD9 — — — — SS1 MOSI1 MISO1 SPSCK1 TXD1 RXD1 TXD2 RXD2 FB_A8/FB_AD8 FB_A7/FB_AD7 FB_A6/FB_AD6 FB_A5/FB_AD5 FB_RW FB_D3 FB_D2 TMRCLK2 TPM2CH0 TPM2CH1 TPM2CH2 — — TPM2CH1 TPM2CH2 — — — — ADP11 ADP10 ADP9 ADP8 ADP7 ADP6 ADP5 ADP4 SCL2 SDA2 SCL1 SDA1 — — — — — — — — — — — — — — — RGPIO_ENB selects between standard GPIO and RGPIO — — — — — — — MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 10 Freescale Semiconductor Electrical Characteristics Table 2. Package Pin Assignments (continued) 80-Pin 60 61 62 63 64 65 64-Pin — 49 50 51 52 53 48-Pin — 37 38 39 40 41 Default Function PTG7 VDD4 VSS4 PTD4/RGPIO4 PTD5/RGPIO5 BKGD/MS Alt 1 KBI1P7 — — — — PTD6/RGPIO6 Alt 2 FB_D1 — — — — — Alt 3 — — — EXTAL XTAL — Comment — — — RGPIO_ENB selects between standard GPIO and RGPIO This pin has an internal pullup. PTD6/RGPIO6 can only be programmed as an output.1 RGPIO_ENB selects between standard GPIO and RGPIO — — — — — — — — — — — — — — 66 54 42 PTD7RGPIO7 — SPSCK2 ADP3 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 55 56 57 58 59 60 61 62 63 64 — — — — 43 44 45 46 47 48 — — — — — — — — PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 PTE6 PTE7 PTJ0 PTJ1 PTJ2 PTJ3 PTJ4 PTJ5 KBI2P0 KBI2P1 KBI2P2 KBI2P3 KBI2P4 KBI2P5 KBI2P6 KBI2P7 FB_ALE — — — — — MISO2 MOSI2 SS2 — CLKOUT IRQ FB_D0 FB_CS0 FB_CS1 FB_A4/FB_AD4 FB_A3/FB_AD3 FB_A2/FB_AD2 FB_A1/FB_AD1 FB_A0/FB_AD0 ADP2 ADP1 ADP0 TPM1CH0 TPM1CH1 TPM1CH2 TXD3 RXD3 — — — — — — RGPIO_ENB selects between standard GPIO and RGPIO. When PTD6 is set as RGPIO output, and "1" is driven to PTD6 via RGPIO function, a read of register RGPIODATA6 always returns a "0" because V1 RGPIO design looks for IO enable when the return value of RGPIO function reads data. As PTD6 is set to RGPIO output only, it returns "0" always to RGPIODATA6, athough PTD6 pin is driven to high. 3 3.1 Electrical Characteristics Introduction This section contains electrical and timing specifications for the MCF51CN128 series of microcontrollers available at the time of publication. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 11 Electrical Characteristics 3.2 Parameter Classification Table 3. Parameter Classifications P C T D These parameters are guaranteed during production testing on each individual device. These parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. These parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. These parameters are derived mainly from simulations. The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 4. Absolute Maximum Ratings Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range 1 Symbol VDD IDD VIn ID Tstg Value –0.3 to +3.8 120 –0.3 to VDD + 0.3 ± 25 –55 to 150 Unit V mA V mA °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 12 Freescale Semiconductor Electrical Characteristics 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 48-pin QFN 64-pin LQFP 80-pin LQFP Thermal resistance Four-layer board 48-pin QFN 64-pin LQFP 80-pin LQFP 1 Symbol TA TJM Value TL to TH (–40 to 85 or 0 to 70)1 95 Unit °C °C 81 θJA 69 60 °C/W 26 θJA 50 47 °C/W Depending on device. The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 2.7 V VDD > 1.8 V VDD > 2.7 V VDD >1.8 V — VIn = VDD or VSS VIn = VDD or VSS — mA 6 P Input high voltage C P Input low voltage V 0.35 x VDD 0.30 x VDD — 1 1 52.5 0.2 5 8 1.79 — 2.45 2.49 mV μA μA kΩ mA mA pF V μs V all digital inputs VIL all digital inputs all input only pins (Per pin) all input/output (per pin) all digital inputs, when enabled Single pin limit Total MCU limit, includes sum of all stressed pins IIC CIn VPOR tPOR VLVDH9 Vhys |IIn| |IOZ| RP 7 C 8 9 10 11 C Input hysteresis P P P Input leakage current Hi-Z (off-state) leakage current Pull resistors 12 DC injection 4, 5, 6 D current VIN < VSS, VIN > VDD –5 — 0.9 10 13 14 15 16 C Input Capacitance, all pins C POR re-arm voltage7 D POR re-arm time P Low-voltage detection threshold — high range8 VDD falling VDD rising 2.15 2.24 MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 15 Electrical Characteristics Table 8. DC Characteristics (continued) Num C 17 18 19 20 1 2 Characteristic Low-voltage detection threshold — low range8 Low-voltage warning threshold — high range8 Low-voltage warning threshold — low range8 Symbol VLVDL VLVWH VLVWL VBG Condition VDD falling VDD rising VDD falling VDD rising VDD falling VDD rising — Min 1.70 1.80 2.50 2.50 2.25 2.29 1.15 Typ1 1.83 1.89 2.62 2.62 2.32 2.39 1.17 Max 1.95 2.00 2.70 2.70 2.45 2.49 1.18 Unit V V V V P P P P Bandgap Voltage Reference10 Typical values are measured at 25 °C. Characterized, not tested As an exception, the Fast Ethernet Controller (FEC) is only operational above the operating voltage of 3 V. 3 As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. 4 All functional non-supply pins are internally clamped to VSS and VDD. 5 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 7 Maximum is highest voltage that POR is guaranteed. 8 Low voltage detection and warning limits measured at 1 MHz bus frequency. 9 Run at 1 MHz bus frequency 10 Factory trimmed at V DD = 3.3 V, Temp = 25 °C PULL-DOWN RESISTANCE (kΩ) 40 PULL-UP RESISTOR (kΩ) 35 30 25 20 1.8 PULL-UP RESISTOR TYPICALS 85°C 25°C –40°C PULL-DOWN RESISTOR TYPICALS 85°C 25°C –40°C 40 35 30 25 20 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 3.6 2.3 2.8 VDD (V) 3.3 3.6 Figure 5. Pull-up and Pull-down Typical Resistor Values MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 16 Freescale Semiconductor Electrical Characteristics TYPICAL VOL VS IOL AT VDD = 3.3 V 85°C 25°C –40°C 1.2 1 0.8 VOL (V) 0.2 0.15 VOL (V) 0.1 0.05 0 TYPICAL VOL VS VDD 0.6 0.4 0.2 0 0 5 10 IOL (mA) 15 20 85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA 1 2 VDD (V) 3 4 Figure 6. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VOL VS IOL AT VDD = 3.3 V 85°C 25°C –40°C 1 0.8 VOL (V) 0.6 0.4 0.2 0 0 TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 IOL = 6 mA IOL = 3 mA 1 2 VDD (V) 3 4 85°C 25°C –40°C IOL = 10 mA 10 IOL (mA) 20 30 Figure 7. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1) TYPICAL VDD – VOH VS IOH AT VDD = 3.3 V VDD – VOH (V) 85°C 25°C –40°C 1.2 VDD – VOH (V) 1 0.8 0.6 0.4 0.2 0 0 0.25 0.2 0.15 0.1 0.05 0 TYPICAL VDD – VOH VS VDD AT SPEC IOH 85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA –5 –10 IOH (mA)) –15 –20 1 2 VDD (V) 3 4 Figure 8. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 17 Electrical Characteristics TYPICAL VDD – VOH VS VDD AT SPEC IOH 85°C 25° C –40°C 0.4 0.8 0.6 0.4 0.2 0 0 –5 –10 –15 –20 IOH (mA) –25 –30 TYPICAL VDD – VOH VS IOH AT VDD = 3.3 V VDD – VOH (V) 85°C 25° C –40°C VDD – VOH (V) 0.3 0.2 0.1 0 1 IOH = –10 mA IOH = –6 mA IOH = –3 mA 2 VDD (V) 3 4 Figure 9. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1) 3.7 Supply Current Characteristics Table 9. Supply Current Characteristics This section includes information about power supply current in various operating modes. Num C P T Parameter Run supply current FEI mode, all modules on Symbol Bus Freq 25 MHz 20 MHz VDD (V) Typ1 60 49 Max 75 — Unit Temp (°C) 1 T T C T 2 T T T 3 T Run supply current LPRS=1, all modules off, running from Flash Wait mode supply current FEI mode, all modules off Run supply current LPRS=0, all modules off Run supply current FEI mode, all modules off RIDD 3.3 8 MHz 1 MHz 25 MHz 20 MHz 21 4.6 44 36 3.3 8 MHz 1 MHz 16 kHz FBILP 15.5 3.9 203 3.3 16 kHz FBELP 16 kHz FBELP 25 MHz 20 MHz 3.3 154 — — — — — — 47 — mA –40 to 85 °C RIDD mA –40 to 85 °C RIDD μA –40 to 85 °C 4 T C T RIDD 50 11 4.57 — 13.7 — — — 11 μA –40 to 85 °C 5 T T C P 6 C C Stop2 mode supply current WIDD 3.3 8 MHz 1 MHz 3.3 2 0.73 0.35 45 μA –-40 to 85 °C 0 to 70 °C μA –40 to 85 °C 0 to 70 °C –40 to 85 °C S2IDD n/a 12 1.8 0.35 16.2 MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 18 Freescale Semiconductor Electrical Characteristics Table 9. Supply Current Characteristics (continued) Num C C P 7 C C 8 9 10 11 12 13 14 1 Parameter Stop3 mode supply current No clocks active Symbol Bus Freq VDD (V) 3.3 Typ1 Max 14 Unit Temp (°C) 0 to 70 °C 0.52 55 μA 15 –40 to 85 °C 0 to 70 °C –40 to 85 °C S3IDD n/a 1.8 0.52 32.4 500 70 12 3.3 15 200 1 100 — — — — — — — T T T T T T T Low power mode adders: EREFSTEN=1 IREFSTEN=1 TPM PWM SCI, SPI, or IIC RTC using LPO RTC using ICSERCLK LVD — 32 kHz 32 kHz 100 Hz 300 bps 1 kHz 32 kHz n/a nA μA μA μA nA μA μA –40 to 85 °C –40 to 85 °C –40 to 85 °C –40 to 85 °C –40 to 85 °C –40 to 85 °C –40 to 85 °C Data in Typical column was characterized at 3.3 V, 25 °C or is typical recommended value. Figure 10. Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled) MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 19 Electrical Characteristics 3.8 External Oscillator (XOSC) Characteristics Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) Reference Figure 11 and Figure 12 for crystal or resonator circuits. Num C Characteristic Symbol flo fhi fhi C1,C2 Min Typ1 Max Unit 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) D Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings 32 1 1 — — — 38.4 25 8 kHz MHz MHz 2 See Note2 See Note3 3 Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, High Gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high power C High range, low power High range, high power D Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) External with FLL / PLL enabled (FEE / PEE) External with bypass (FBE.FBELP,PBE, PBELP) RF — — — — — — — — — — 10 1 — 0 100 0 0 0 200 400 5 15 — — — — — — — — 0 10 20 — — — — 50.33 50.33 MΩ Ω 4 RS ΚΩ t CSTL t CSTH 5 — — — — 0.03125 0 ms 6 1 2 fextal MHz MHz Data in Typical column was characterized at 3.3 V, 25 °C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 20 Freescale Semiconductor Electrical Characteristics XOSC EXTAL XTAL RS RF C1 Crystal or Resonator C2 Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSC EXTAL XTAL Crystal or Resonator Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Gain 3.9 Num C Multipurpose Clock Generator (MCG) Specifications Table 11. MCG Frequency Specifications (Temperature Range = –40 to 125 °C Ambient) Rating Symbol fint_ft Min Typical Max Unit 1 Internal reference frequency - factory P trimmed at VDD = and temperature = 25 °C P P Average internal reference frequency untrimmed 1 Average internal reference frequency user trimmed — 32.768 — kHz 2 3 4 fint_ut fint_t tirefst 25 31.25 — — — 60 41.66 39.06 100 kHz kHz us D Internal reference startup time DCO output frequency range untrimmed 1 — value provided for reference: fdco_ut = 1024 X fint_ut P DCO output frequency range - trimmed Resolution of trimmed DCO output C frequency at fixed voltage and temperature (using FTRIM) 5 fdco_ut 25.6 33.48 42.66 MHz 6 7 fdco_t Δfdco_res_t 32 — — ± 0.1 40 ± 0.2 MHz %fdco MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 21 Electrical Characteristics Table 11. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125 °C Ambient) Num C 8 Rating Symbol Δfdco_res_t Min — Typical ± 0.2 Max ± 0.4 Unit %fdco Resolution of trimmed DCO output C frequency at fixed voltage and temperature (not using FTRIM) Total deviation of trimmed DCO output P frequency over voltage and temperature Total deviation of trimmed DCO output C frequency over fixed voltage and temperature range of 0 - 70 °C C FLL acquisition time 2 D PLL acquisition time 3 C Long term Jitter of DCO output clock (averaged over 2ms interval) 4 9 Δfdco_t — + 0.5 -1.0 ±2 %fdco 10 11 12 13 14 15 16 17 Δfdco_t tfll_acquire tpll_acquire CJitter fvco Dlock Dunl tfll_lock — — — — 7.0 ± 1.49 ± 4.47 — ± 0.5 — — 0.02 — — — — ±1 1 1 0.2 55.0 ± 2.98 ± 5.97 tfll_acquire+ 1075(1/fint_t ) %fdco ms ms %fdco MHz % % s D VCO operating frequency D Lock entry frequency tolerance5 D Lock exit frequency tolerance6 D Lock time - FLL 18 D Lock time - PLL Loss of external clock minimum D frequency - RANGE = 0 tpll_lock — — tpll_acquire+ 1075(1/fpll_r ef) s 19 1 2 floc_low (3/5) x fint — — kHz TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 5 Below D lock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG does not enter lock. But if the MCG is already in lock, then the MCG may stay in lock. 6 Below Dunl minimum, the MCG does not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 22 Freescale Semiconductor Electrical Characteristics 3.10 Mini-FlexBus Timing Specifications A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values. Table 12. Mini-FlexBus AC Timing Specifications Num — MB1 MB2 MB3 MB4 MB5 1 2 C — D P D P D Characteristic Frequency of Operation Clock Period Output Valid Output Hold Input Setup Input Hold Min — 39.73 — 1.0 22 10 Max 25.1666 — 20 — — — Unit MHz ns ns ns ns ns Notes — — 1 1 2 2 Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE. Specification is valid for all MB_D[7:0]. S0 S1 S2 S3 S0 FB_CLK MB1 MB3 ADDR[19:0] MB2 MB5 DATA[7:0] MB4 FB_A[19:16] 8-bit Non-Mux’d Bus FB_D[7:0] ADDR[31:24] FB_AD[19:16] 16-bit Mux’d Bus FB_AD[15:0] ADDR[15:0] ADDR[19:16] DATA[15:0] FB_R/W FB_ALE FB_CSn, FB_OE Figure 13. Mini-FlexBus Read Timing MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 23 Electrical Characteristics S0 S1 S2 S3 S0 FB_CLK MB1 MB3 ADDR[19:8] MB2 FB_AD[19:8] 8-bit Non-Mux’d Bus FB_AD[7:0] FB_AD[19:16] 16-bit Mux’d Bus FB_AD[15:0] FB_R/W FB_ALE FB_CSn FB_OE ADDR[15:0] ADDR[7:0] DATA[7:0] ADDR[19:16] DATA[15:0] Figure 14. Mini-FlexBus Write Timing 3.11 Fast Ethernet Timing Specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 3.11.1 Receive Signal Timing Specifications Table 13. Receive Signal Timing MII Mode The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. Num — E1 E2 E3 E4 C — P D D D RXCLK frequency Characteristic Min — 5 5 35% 35% Max 25 — — 65% 65% Unit MHz ns ns RXCLK period RXCLK period RXD[3:0], RXDV, RXER to RXCLK setup RXCLK to RXD[3:0], RXDV, RXER hold RXCLK pulse width high RXCLK pulse width low MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 24 Freescale Semiconductor Electrical Characteristics RXCLK (Input) E4 E3 E1 E2 RXD[n:0] RXDV, RXER Valid Data Figure 15. MII Receive Signal Timing Diagram 3.11.2 Transmit Signal Timing Specifications Table 14. Transmit Signal Timing MII Mode Num — E5 E6 E7 E8 C — D P D D TXCLK frequency Characteristic Min — 5 — 35% 35% Max 25 — 25 65% 65% Unit MHz ns ns tTXCLK tTXCLK TXCLK to TXD[3:0], TXEN, TXER invalid TXCLK to TXD[3:0], TXEN, TXER valid TXCLK pulse width high TXCLK pulse width low TXCLK (Input) E6 E8 E7 E5 TXD[n:0] TXEN, TXER Valid Data Figure 16. MII Transmit Signal Timing Diagram 3.11.3 Num E9 Asynchronous Input Signal Timing Specifications Table 15. MII Transmit Signal Timing C D Characteristic CRS, COL minimum pulse width Min 1.5 Max — Unit TXCLK period CRS, COL E9 Figure 17. MII Async Inputs Timing Diagram MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 25 Electrical Characteristics 3.11.4 Num E10 E11 E12 E13 E14 E15 MII Serial Management Timing Specifications Table 16. MII Serial Management Channel Signal Timing C D D D D D D MDC cycle time MDC pulse width MDC to MDIO output valid MDC to MDIO output invalid MDIO input to MDC setup MDIO input to MDC hold E10 E11 Characteristic Symbol tMDC — — — — — Min 400 40 — 30 5 15 Max — 60 375 — — — Unit ns % tMDC ns ns ns ns MDC (Output) E11 E12 E13 MDIO (Output) Valid Data E14 E15 MDIO (Input) Valid Data Figure 18. MII Serial Management Channel TIming Diagram 3.12 AC Characteristics This section describes timing characteristics for each peripheral system. 3.12.1 Num C Control Timing Table 17. Control Timing Rating Bus frequency (tcyc = 1/fBus) VDD > 2.7 V 2.7 V > VDD > 2.1 V 2.1 V > VDD > 1.8 V Internal low power oscillator period External reset pulse Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes width2 Symbol Min dc dc dc 700 100 34 x tcyc 500 Typ1 — — — — — — — Max 50.33 40 20 1300 — — — Unit 1 D fBus MHz 2 3 4 5 D D D D tLPO textrst trstdrv tMSSU μs ns ns ns MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 26 Freescale Semiconductor Electrical Characteristics Table 17. Control Timing (continued) Num 6 C D Rating BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 9 C Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 10 1 2 Symbol tMSH Min 100 Typ1 — Max — Unit μs 7 D tILIH, tIHIL 100 2 x tcyc 100 2 x tcyc — — — — — — — — ns 8 D tILIH, tIHIL ns tRise, tFall — — 16 23 — — ns tRise, tFall — — — 5 9 6 — — 10 ns C Stop3 recovery time, from interrupt event to vector fetch tSTPREC μs Typical values are based on characterization data at VDD = 3.3 V, 25 °C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt request until it is explicitly negated by the interrupt service routine. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40 °C to 85 °C. textrst RESET PIN Figure 19. Reset Timing tIHIL KBIPx IRQ/KBIPx tILIH Figure 20. IRQ/KBIPx Timing MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 27 Electrical Characteristics 3.12.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 18. TPM Input Timing No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW tTCLK tclkh Min 0 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit Hz tcyc tcyc tcyc tcyc TCLK tclkl Figure 21. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 22. Timer Input Capture Pulse MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 28 Freescale Semiconductor Electrical Characteristics 3.12.3 SPI Timing Table 19. SPI Timing Table 19 and Figure 23 through Figure 26 describe the timing requirements for the SPI system. No. — C D Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol fop Min fBus/2048 0 Max fBus/2 fBus/4 2048 — — — — — 1024 tcyc — — — — — 1 1 25 25 — — tcyc – 25 25 tcyc – 25 25 Unit Hz Hz tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc ns ns ns ns ns ns ns ns tSPSCK 2 4 tLead 1/2 1 1/2 1 tcyc – 30 tcyc – 30 tSU 15 15 tHI 0 25 ta tdis tv — — tHO 0 0 tRI tRO tFI tFO — — — — — — 1 D 2 D tLag 3 D tWSPSCK 4 D 5 D 6 7 8 9 D D D D 10 D 11 D 12 D MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 29 Electrical Characteristics SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 6 MSB IN2 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 11 3 12 NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 23. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT(2) 6 MSB IN(2) BIT 6 . . . 1 10 12 11 3 4 11 12 LSB IN BIT 6 . . . 1 MASTER LSB OUT PORT DATA NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 24. SPI Master Timing (CPHA =1) MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 30 Freescale Semiconductor Electrical Characteristics SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT) NOTE: 12 11 3 4 4 11 12 8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 10 10 SLAVE LSB OUT SEE NOTE 1. Not defined but normally MSB of character just received Figure 25. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 3 11 10 8 SLAVE LSB OUT BIT 6 . . . 1 NOTE: 1. Not defined but normally LSB of character just received Figure 26. SPI Slave Timing (CPHA = 1) MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 31 Electrical Characteristics 3.12.4 C D D D D D C C ADC Characteristics Table 20. 12-bit ADC Operating Conditions Conditions Absolute Delta to VDD (VDD-VDDAD) 2 Characteristic Supply voltage Symb VDDAD ΔVDDAD ΔVSSAD VREFH VREFL VADIN CADIN RADIN Min 1.8 -100 -100 1.8 VSSAD VREFL — — — — — — — Typ1 — 0 0 VDDAD VSSAD — 4.5 5 — — — — — — — Max 3.6 +100 +100 VDDAD VSSAD VREFH 5.5 7 2 5 Unit V mV mV V V V pF kΩ Comment Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance Analog Source Resistance Delta to VSS (VSS-VSSAD)2 12 bit mode fADCK > 4MHz fADCK < 4MHz 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) RAS External to MCU C kΩ 5 10 10 8.0 MHz 0.4 4.0 D 1 ADC Conversion High Speed (ADLPC=0) Clock Freq. Low Power (ADLPC=1) fADCK 0.4 Typical values assume VDDAD = 3.3 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 32 Freescale Semiconductor Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + – + – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 27. ADC Input Impedance Equivalency Diagram Table 21. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 Supply Current ADC Asynchronous Clock Source Stop, Reset, Module Off High Speed (ADLPC=0) Low Power (ADLPC=1) Conditions C T Symb IDDAD Min — Typ1 120 Max — μA Unit Comment T IDDAD — 202 — μA T IDDAD — 288 — μA T IDDAD — 0.532 1 mA D P C IDDAD fADACK — 2 1.25 0.007 3.3 2 0.8 5 3.3 μA tADACK = 1/fADACK MHz MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 33 Electrical Characteristics Table 21. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) Characteristic Conditions C P C P C T P T T P T T P T T P T T P T D EQ EFS EZS INL DNL ETUE tADS Symb tADC Min — — — — — — — — — — — — — — — — — — — — — — D EIL — — — D m — — D VTEMP25 — Typ1 20 40 3.5 23.5 ±3.0 ±1 ±0.5 ±1.75 ±0.5 ±0.3 ±1.5 ±0.5 ±0.3 ±1.5 ±0.5 ±0.5 ±1.0 ±0.5 ±0.5 -1 to 0 — — ±2 ±0.2 ±0.1 1.646 1.769 701.2 Max — — — — — ±2.5 ±1.0 — ±1.0 ±0.5 — ±1.0 ±0.5 — ±1.5 ±0.5 — ±1 ±0.5 — ±0.5 ±0.5 — ±4 ±1.2 — — — mV mV/°C LSB2 Pad leakage4 * RAS{test=pad leakage test} Unit ADCK cycles ADCK cycles LSB2 Comment See the ADC chapter in the MCF51CN128 Reference Manual for conversion time variances Includes Quantization Conversion Time Short Sample (ADLSMP=0) (Including Long Sample (ADLSMP=1) sample time) Sample Time Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Total Unadjusted 12 bit mode Error 10 bit mode 8 bit mode Differential Non-Linearity 12 bit mode 10 bit mode3 8 bit mode3 Integral Non-Linearity 12 bit mode 10 bit mode 8 bit mode Zero-Scale Error 12 bit mode 10 bit mode 8 bit mode Full-Scale Error 12 bit mode 10 bit mode 8 bit mode Quantization Error 12 bit mode 10 bit mode 8 bit mode Input Leakage Error 12 bit mode 10 bit mode 8 bit mode Temp Sensor Slope Temp Sensor Voltage 1 LSB2 LSB2 LSB2 VADIN = VSSAD LSB2 VADIN = VDDAD LSB2 -40°C to 25°C 25°C to 85°C 25°C Typical values assume VDDAD = 3.3 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 34 Freescale Semiconductor Electrical Characteristics 3.12.5 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section of the MCF51CN128 Reference Manual. Table 22. Flash Characteristics C D D D D P P P P D D C C 1 2 Characteristic Supply voltage for program/erase -40 °C to 85 °C Supply voltage for read operation Internal FCLK frequency1 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE mode)(2) Min 1.8 1.8 150 5 Typical — — — — 9 4 4000 20,000 Max 3.6 3.6 200 6.67 Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc Internal FCLK period (1/FCLK) Longword program time (random location)(2) Longword program time (burst Page erase Mass erase time2 time(2) Longword program current3 Page erase current 3 — — 10,000 — 9.7 7.6 — 100,000 100 — — — — — mA mA cycles years Program/erase TL to TH = –40°C to + 85°C T = 25°C Data retention5 tD_ret endurance4 15 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.3 V, bus frequency = 8.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 3.13 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 35 Ordering Information 3.13.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. 4 Ordering Information Table 23. Ordering Information Freescale Part Number1 Flash MCF51CN128CLK MCF51CN128CLH MCF51CN128CGT 128K 128K 128K Memory RAM 24K 24K 24K Temperature Range (°C) –40 to +85 –40 to +85 –40 to +85 Package2 80-pin LQFP 64-pin LQFP 48-pin QFN This section contains ordering information for MCF51CN128 devices. 1 See the MCF51CN128 Reference Manual (document MCF51CN128RM), for a complete description of modules included on each device. 2 See Table 24 for package information. 5 80 64 48 Package Information Table 24. Package Descriptions Pin Count Package Type Low Quad Flat Package Low Quad Flat Package Quad Flat No-Leads Abbreviation LQFP LQFP QFN Designator LK LH GT Case No. 917A 840F 1314 Document No. 98ASS23237W 98ASS23234W 98ARH99048A 6 Mechanical Outline Drawings The following pages are mechanical drawings for the packages described in Table 24. For the latest available drawings, visit freescale web site (http://www.freescale.com) and enter the package’s document number into the keyword search box. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 36 Freescale Semiconductor Mechanical Outline Drawings 6.1 80-pin LQFP MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 37 Mechanical Outline Drawings MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 38 Freescale Semiconductor Mechanical Outline Drawings MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 39 Mechanical Outline Drawings 6.2 64-pin LQFP MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 40 Freescale Semiconductor Mechanical Outline Drawings MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 41 Mechanical Outline Drawings MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 42 Freescale Semiconductor Mechanical Outline Drawings 6.3 48-pin QFN MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 43 Mechanical Outline Drawings MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 44 Freescale Semiconductor Mechanical Outline Drawings MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 45 Mechanical Outline Drawings MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 46 Freescale Semiconductor Revision History 7 Revision History Table 25. Revision History Revision Number 1 2 3 4 Date August 2008 January 2009 January 2009 May 2009 Description of Changes Alpha Customer Release. Pre-Launch Release. Launch Release. • Changed LVDH trip and recovery values in Table 8. • Fixed Mini-FlexBus maximum frequency to 25.1666 MHz in Section 3.10, “Mini-FlexBus Timing Specifications.” • Updated FEC feature list to describe ethernet operation between 3.0 V to 3.6 V. • In Table 8, added a footnote to the operating voltage. It describes an exception to the Fast Ethernet Controller (FEC), because it is only operational above the operating voltage of 3 V. • Corrected Freescale part numbers in Table 23. • In Table 21, changed IDDAD classification to T. This section lists the changes between versions of MCF51CN128 Data Sheet document. MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 47 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. 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