MCF51JM128

Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF51JM128 Rev. 2, 09/2008 MCF51JM128 80 LQFP 14 mm × 14 mm 64 LQFP 10 mm × 10 mm MCF51JM128 ColdFire Microcontroller The MCF51JM128 is a member of the ColdFire® family of 32-bit reduced instruction set computing (RISC) microprocessors. This document provides an overview of the MCF51JM128 series, focusing on its highly integrated and diverse feature set. The MCF51JM128 series is based on the V1 ColdFire core and operates at processor core speeds up to 50.33 MHz. As part of Freescale’s Controller Continuum®, it is an ideal upgrade for designs based on the MC9S08JM60 series of 8-bit microcontrollers. The MCF51JM128 features the following functional units: • • • • • • • • • • • • • • • • • • • V1 ColdFire core with background debug module Up to 128 KBytes of flash memory Up to 16 Kbytes of static RAM (SRAM) Multipurpose clock generator (MCG) Dual-role Universal Serial Bus On-The-Go device (USBOTG) Controller-area network (MSCAN) Cryptographic acceleration unit (CAU) Random number generator accelerator (RNGA) Analog comparators (ACMP) Analog-to-digital converter (ADC) with up to 12 channels Two Inter-integrated circuit (IIC) modules Two serial peripheral interfaces (SPI) Two serial communications interfaces (SCI) Carrier modulation timer (CMT) Eight-channel timer/pulse-width modulators (TPM) Real-time counter (RTC) 66 general-purpose input/output (GPIO) modules plus Interrupt request input Eight keyboard interrupts (KBI) 16-bit Rapid GPIO 44 LQFP 10 mm × 10 mm 64 QFP 14 mm × 14 mm This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. Table of Contents 1 MCF51JM128 Family Configurations . . . . . . . . . . . . . . . . . . . .3 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.5 Pinouts and Packaging . . . . . . . . . . . . . . . . . . . . . . . . .10 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .15 2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .16 2.4 Electrostatic Discharge (ESD) Protection Characteristics 17 2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .22 2.7 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .23 2.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.9 External Oscillator (XOSC) Characteristics . . . . . . . . .27 2.10 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.2 Timer/PWM (TPM) Module Timing . . . . . . . . . .30 2.11.3 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.15 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.15.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .36 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .37 3.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.3 64-pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.4 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Figure 6. Typical Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0). . . . . . . . . . Figure 7. Typical High-side Drive (source) characteristics – High Drive (PTxDSn = 1) . . . . . . . . . Figure 8. Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0). . . . . . . . . . Figure 9. ADC Input Impedance Equivalency Diagram . . . . . . . Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . Figure 14.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . Figure 15.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . Figure 16.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . Figure 17.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 21 21 22 24 30 30 31 31 33 33 34 34 2 List of Tables Table 1. MCF51JM128 Series Device Comparison . . . . . . . . . . 3 Table 2. MCF51JM128 Series Functional Units . . . . . . . . . . . . . 6 Table 3. Orderable Part Number Summary. . . . . . . . . . . . . . . . . 9 Table 4. Pin Assignments by Package and Pin Sharing Priority 12 Table 5. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16 Table 7. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 17 Table 9. ESD and Latch-Up Protection Characteristics. . . . . . . 18 Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 22 Table 12.Analog Comparator Electrical Specifications. . . . . . . . 23 Table 13.5 Volt 12-bit ADC Operating Conditions . . . . . . . . . . . 23 Table 14.5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 25 Table 15.Oscillator Electrical Specifications (Temperature Range = –40 to 105×C Ambient) . . . . . 27 Table 16.MCG Frequency Specifications (Temperature Range = –40 to 125×C Ambient) . . . . . 28 Table 17.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 18.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 19.MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . 31 Table 20.SPI Electrical Characteristic . . . . . . . . . . . . . . . . . . . . 32 Table 21.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 22.Internal USB 3.3V Voltage Regulator Characteristics . 36 3 4 List of Figures Figure 1. MCF51JM128 Block Diagram . . . . . . . . . . . . . . . . . . . . 5 Figure 2. 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. 64-pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1) . . . . . . . . . 21 MCF51JM128 ColdFire Microcontroller, Rev. 2 2 Freescale Semiconductor MCF51JM128 Family Configurations 1 1.1 MCF51JM128 Family Configurations Device Comparison Table 1. MCF51JM128 Series Device Comparison MCF51JM128 Feature 80-pin 64-pin 128 16 44-pin 80-pin 64-pin 64 16 Yes Yes 12 Yes Yes No 8 No No Yes 12 Yes No Yes Yes Yes Yes No Yes Yes 8 8 6 8 8 Yes Yes 66 16 51 6 33 0 66 16 51 6 Yes Yes Yes Yes Yes Yes 33 0 66 16 51 6 33 0 6 8 8 6 No Yes No 8 No No Yes 12 Yes No 8 No No 44-pin 80-pin 64-pin 32 16 44-pin MCF51JM64 MCF51JM32 The MCF51JM128 series consists of the devices compared in Table 1. Flash memory size (Kbytes) RAM size (Kbytes) V1 ColdFire core with BDM (background debug module) ACMP (analog comparator) ADC (analog-to-digital converter) channels (12-bit) CAN (controller area network) CAU (cryptographic acceleration unit) CMT (carrier modulator timer) COP (computer operating properly) IIC1 (inter-integrated circuit) IIC2 IRQ (interrupt request input) KBI (keyboard interrupts) LVD (low-voltage detector) MCG (multipurpose clock generator) Port I/O 1 RGPIO (rapid general-purpose I/O) RNGA (random number generator accelerator) RTC (real-time counter) SCI1 (serial communications interface) SCI2 SPI1 (serial peripheral interface) SPI2 MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 3 MCF51JM128 Family Configurations Table 1. MCF51JM128 Series Device Comparison (continued) MCF51JM128 Feature 80-pin TPM1 (timer/pulse-width modulator) channels TPM2 channels USBOTG (USB On-The-Go dual-role controller) XOSC (crystal oscillator) 1 MCF51JM64 80-pin 6 64-pin 6 2 Yes Yes 44-pin 4 MCF51JM32 80-pin 6 64-pin 6 44-pin 4 64-pin 6 44-pin 4 6 Up to 16 pins on Ports A, H, and J are shared with the ColdFire Rapid GPIO module. 1.2 Block Diagram Figure 1 shows the connections between the MCF51JM128 series pins and modules. MCF51JM128 ColdFire Microcontroller, Rev. 2 4 Freescale Semiconductor MCF51JM128 Family Configurations BKGD/MS BDM CAU DBG ADC CMT Port C: IRO Port C: SDA1 SCL1 Port H: SCL2 SDA2 Port B: KBIP5 KBIP4 Port D: KBIP3 KBIP2 Port G: KBIP7 KBIP6 KBIP1 KBIP0 Port G: Port A VREFH VREFL VDDAD VSSAD VREFH VREFL VDDAD VSSAD RESET IRQ/TPMCLK TPMCLK SYSCTL TPM1 COP LVD IRQ TPMCLK Port F: TPM1CH5 TPM1CH4 TPM1CH3 TPM1CH2 Port E: TPM1CH1 TPM1CH0 Port F: TPM2CH1 TPM2CH0 IIC2 Port B V1 ColdFire core Port B: ADP7 ADP6 ADP5 ADP4 ADP3 ADP2 ADP1 ADP0 Port D: ADP11 ADP10 ADP9 ADP8 Port D: ACMPO ACMP ACMP– ACMP+ PTA7/RGPIO7 PTA6/RGPIO6 PTA5/RGPIO5 PTA4/RGPIO4 PTA3/RGPIO3 PTA2/RGPIO2 PTA1/RGPIO1 PTA0/RGPIO0 PTB7/ADP7 PTB6/ADP6 PTB5/KBIP5/ADP5 PTB4/KBIP4/ADP4 PTB3/SS2/ADP3 PTB2/SPSCK2/ADP2 PTB1/MOSI2/ADP1 PTB0/MISO2/ADP0 PTC7 PTC6/RXCAN PTC5/RXD2 PTC4 PTC3/TXD2 PTC2/IRO PTC1/SDA1 PTC0/SCL1 PTD7 PTD6 PTD5 PTD4/ADP11 PTD3/KBIP3/ADP10 PTD2/KBIP2/ACMPO PTD1/ACMP–/ADP9 PTD0/ACMP+/ADP8 PTE7/SS1 PTE6/SPSCK1 PTE5/MOSI1 PTE4/MISO1 PTE3/TPM1CH1 PTE2/TPM1CH0 PTE1/RXD1 PTE0/TXD1 PTF7/TXCAN PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG7 PTG6 PTG5/EXTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 PTH4/RGPIO10 PTH3/RGPIO9 PTH2/RGPIO8 PTH1/SCL2 PTH0/SDA2 PTJ4/RGPIO15 PTJ3/RGPIO14 PTJ2/RGPIO13 PTJ1/RGPIO12 PTJ0/RGPIO11 IIC1 KBI TPM2 FLASH 128 or 64 Kbytes RAM 16 or 8 Kbytes Port J: RGPIO15 RGPIO14 RGPIO13 RGPIO12 RGPIO11 Port H: RGPIO10 RGPIO9 RGPIO RGPIO8 Port A: RGPIO7 RGPIO6 RGPIO5 RGPIO4 RGPIO3 RGPIO2 RGPIO1 RGPIO0 VDD VDD VSS VSS MCG XOSC EXTAL XTAL Port C: RXCAN Port F: TXCAN SCI1 Port E: RXD1 TXD1 Port C: RXD2 TXD2 Port E: SS1 SPSCK1 MOSI1 MISO1 Port B: SS2 SPSCK2 MOSI2 MISO2 Port G Port J Port H VREG SCI2 INTC SPI1 RNGA USBDN USBDP VUSB33 SPI2 USB RTC Figure 1. MCF51JM128 Block Diagram MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 5 Port F Port E CAN Port D Port C MCF51JM128 Family Configurations 1.3 Features Table 2. MCF51JM128 Series Functional Units Unit Function Executes programs and interrupt handlers Provides a single-pin debugging interface (part of the V1 ColdFire core) Provides debugging and emulation capabilities (part of the V1 ColdFire core) Provides LVD, COP, external interrupt request, and so on Provides storage for program code and constants Provides storage for program code, constants, and variables Allows I/O port access at CPU clock speeds Controls power management throughout the device Supports the USB On-The-Go dual-role controller Measures analog voltages at up to 12 bits of resolution Provide a variety of timing-based features Controls and prioritizes all device interrupts Co-processor support for DES, 3DES, AES, MD5, and SHA-1 32-bit random number generator that complies with FIPS-140 Provides a constant-time base with optional interrupt Compares two analog inputs Infrared output used for the Remote Controller Supports the standard IIC communications protocol Provides pin interrupt capabilities Provides clocking options for the device, including a phase-locked loop (PLL) and frequency-locked loop (FLL) for multiplying slower reference clock sources Supports low/high range crystals Supports standard CAN communications protocol Serial communications UARTs that can support RS-232 and LIN protocols Provide a 4-pin synchronous serial interface Table 2 describes the functional units of the MCF51JM128 series. CF1CORE (V1 ColdFire core) BDM (background debug module) DBG (debug) SYSCTL (system control) FLASH (flash memory) RAM (random-access memory) RGPIO (rapid general-purpose input/output) VREG (voltage regulator) USBOTG (USB On-The-Go) ADC (analog-to-digital converter) TPM1, TPM2 (timer/pulse-width modulators) CF1_INTC (interrupt controller) CAU (cryptographic acceleration unit) RNGA (random number generator accelerator) RTC (real-time counter) ACMP (analog comparator) CMT (carrier modulator timer) IIC1, IIC2 (inter-integrated circuits) KBI (keyboard interrupt) MCG (multipurpose clock generator) XOSC (crystal oscillator) CAN (controller area network) SCI1, SCI2 (serial communications interfaces) SPI1, SPI2 (serial peripheral interfaces) MCF51JM128 ColdFire Microcontroller, Rev. 2 6 Freescale Semiconductor MCF51JM128 Family Configurations 1.3.1 • Feature List 32-Bit Version 1 ColdFire® Central Processor Unit (CPU) — Up to 50.33 MHz at 2.7 V – 5.5 V — Performance (Dhrystone 2.1): – 0.94 Dhrystone 2.1 MIPS per MHz when running from internal RAM – 0.76 Dhrystone 2.1 MIPS per MHz when running from flash — Implements Instruction Set Revision C (ISA_C) — Supports up to 30 peripheral interrupt requests and seven software interrupts On-chip memory — Up to 128 KBytes Flash memory with read/program/erase over full operating voltage and temperature range — Up to 16 KBytes static random access memory (RAM) — Security circuitry to prevent unauthorized access to RAM and flash contents Power-saving modes — Two low-power stop plus wait modes — Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents; this behavior allows clocks to remain enabled to specific perhipherals in Stop3 mode — Very lower power real-time counter for use in run, wait, and stop modes with internal and external clock sources Four Clock Source Options — Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz — FLL/PLL controlled by internal or external reference — Trimmable internal reference allows 0.2% resolution and 2% deviation System protection features — Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock — Low-voltage detection with reset or interrupt; selectable trip points — Illegal opcode and illegal address detection with programmable reset or exception response — Flash block protection Debug support — Single-wire Background debug interface — 4 Program Counters plus two address (optional data) breakpoint registers with programmable 1- or 2-level trigger response — 64-entry processor status and debug data trace buffer with programmable start/stop conditions Universal Serial Bus (USB) On-The-Go dual-role controller — Full-speed USB device controller – Fully compliant with USB specification 1.1 and 2.0 – 16 bidirectional endpoints, with double buffering to provide the maximum throughput – Supports control, bulk, interrupt, and isochronous endpoints – Supports bus-powered capability with low-power consumption — Full-speed / low-speed host controller – Host mode allows control, bulk, interrupt, and isochronous transfers — OTG protocol logic — On-chip USB transceiver — On-chip 3.3 V USB regulator and pull-up resistors save system cost • • • • • • MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 7 MCF51JM128 Family Configurations • • • • • • • • • Controller area network (MSCAN) — Implementation of the CAN protocol — Version 2.0A/B — Five receive buffers with FIFO storage scheme — Three transmit buffers with internal prioritization using a “local priority” concept — Flexible maskable identifier filter programmable as 2x32-bit, 4x16-bit, or 8x8-bit — Programmable wakeup functionality with integrated low-pass filter — Programmable loopback mode supports self-test operation — Programmable bus-off recovery functionality — Internal timer for time-stamping of received and transmitted messages Cryptographic acceleration unit (CAU) — Co-processor support of DES, 3DES, AES, MD5, and SHA-1 Random number generator accelerator (RNGA) — 32-bit random number generator that complies with FIPS-140 Analog-to-digital converter (ADC) — 12-channel, 12-bit resolution — Output formatted in 12-, 10-, or 8-bit right-justified format — Single or continuous conversion, and selectable asynchronous hardware conversion trigger — Operation in Stop3 mode — Automatic compare function — Internal temperature sensor Analog comparators (ACMP) — Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output — Option to compare to fixed internal bandgap reference voltage — Option to route output to TPM module — Operation in Stop3 mode Inter-integrated circuit (IIC) — Up to 100 kbps with maximum bus loading — Multi-master operation — Programmable slave address — Supports broadcast mode and 10-bit address extension Serial communications interfaces (SCI) — Two SCIs with full-duplex, non-return-to-zero (NRZ) format — LIN master extended break generation — LIN slave extended break detection — Programmable 8-bit or 9-bit character length — Wake up on active edge Serial peripheral interfaces (SPI) — Two serial peripheral interfaces with full-duplex or single-wire bidirectional — Double-buffered transmit and receive — Programmable transmit bit rate, phase, polarity, and Slave Select output — MSB-first or LSB-first shifting Timer/pulse width modulator (TPM) — 16-bit free-running or modulo up/down count operation — Up to eight channels, where each channel can be an input capture, output compare, or edge-aligned PWM — One interrupt per channel plus terminal count interrupt MCF51JM128 ColdFire Microcontroller, Rev. 2 8 Freescale Semiconductor MCF51JM128 Family Configurations • • • RTC — 8-bit modulus counter with binary- or decimal-based prescaler — External clock source for precise time base, time-of-day, calendar or task scheduling functions — Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components Carrier modulator timer (CMT) — carrier generator, modulator, and transmitter drive the infrared out (IRO) pin — operation in independent high/low time control, baseband, FSK, and direct IRO control modes Input/Output — 66 GPIOs — Eight keyboard interrupt pins with selectable polarity — Hysteresis and configurable pull-up device on all input pins; configurable slew rate and drive strength on all output pins — 16 bits of Rapid GPIO connected to the processor’s local 32-bit platform bus with set, clear, and faster toggle functionality 1.4 Part Numbers Table 3. Orderable Part Number Summary Description MCF51JM128 ColdFire Microcontroller with CAU Enabled MCF51JM128 ColdFire Microcontroller MCF51JM128 ColdFire Microcontroller MCF51JM128 ColdFire Microcontroller MCF51JM128 ColdFire Microcontroller MCF51JM64 ColdFire Microcontroller with CAU enabled MCF51JM64 ColdFire Microcontroller MCF51JM64 ColdFire Microcontroller MCF51JM64 ColdFire Microcontroller MCF51JM64 ColdFire Microcontroller MCF51JM32 ColdFire Microcontroller with CAU enabled MCF51JM32 ColdFire Microcontroller MCF51JM32 ColdFire Microcontroller MCF51JM32 ColdFire Microcontroller MCF51JM32 ColdFire Microcontroller Flash / SRAM (Kbytes) 128 / 16 128 / 16 128 / 16 128 / 16 128 / 16 64 / 16 64 / 16 64 / 16 64 / 16 64 / 16 32 / 16 32 / 16 32 / 16 32 / 16 32 / 16 Package 80 LQFP 80 LQFP 64 LQFP 64 QFP 44 LQFP 80 LQFP 80 LQFP 64 LQFP 64 QFP 44 LQFP 80 LQFP 80 LQFP 64 LQFP 64 QFP 44 LQFP Temperature –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C –40 to +105 °C Freescale Part Number MCF51JM128EVLK MCF51JM128VLK MCF51JM128VLH MCF51JM128VQH MCF51JM128VLD MCF51JM64EVLK MCF51JM64VLK MCF51JM64VLH MCF51JM64VQH MCF51JM64VLD MCF51JM32EVLK MCF51JM32VLK MCF51JM32VLH MCF51JM32VQH MCF51JM32VLD MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 9 MCF51JM128 Family Configurations 1.5 Pinouts and Packaging PTC5 / RXD2 PTC3 / TXD2 PTC2 / IRO PTC1 / SDA1 PTC0 / SCL1 PTG7 PTG6 VDD VSS PTG5 / EXTAL PTG4 / XTAL BKGD/MS PTG3 / KBIP7 PTG2 / KBIP6 PTD7 PTD6 PTD5 PTD4 / ADP11 PTD3 / KBIP3 / ADP10 PTJ4 / RGPIO15 PTC4 IRQ / TPMCLK RESET PTF0 / TPM1CH2 PTF1 / TPM1CH3 PTF2 / TPM1CH4 PTF3 / TPM1CH5 PTF4 / TPM2CH0 PTC6 / RXCAN PTF7 / TXCAN PTF5 / TPM2CH1 PTF6 PTE0 / TXD1 PTE1 / RXD1 PTE2 / TPM1CH0 PTE3 / TPM1CH1 PTC7 PTH0 / SDA2 PTH1 / SCL2 PTH2 / RGPIO8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Figure 2 shows the pinout of the 80-pin LQFP. PTJ3 / RGPIO14 PTJ2 / RGPIO13 PTJ1 / RGPIO12 PTJ0 / RGPIO11 PTD2 / KBIP2 / ACMPO VSSAD VREFL VREFH VDDAD PTD1 / ADP9 / ACMP– PTD0 / ADP8 / ACMP+ PTB7 / ADP7 PTB6 / ADP6 PTB5 / KBIP5 / ADP5 PTB4 / KBIP4 / ADP4 PTB3 / SS2 / ADP3 PTB2 / SPSCK2 / ADP2 PTB1 / MOSI2 / ADP1 PTB0 / MISO2 / ADP0 PTA7 / RGPIO7 10 PTH3 / RGPIO9 PTH4 / RGPIO10 PTE4 / MISO1 PTE5 / MOSI1 PTE6 / SPSCK1 PTE7 / SS1 VDD VSS USBDN USBDP VUSB33 PTG0 / KBIP0 PTG1 / KBIP1 PTA0 / RGPIO0 PTA1 / RGPIO1 PTA2 / RGPIO2 PTA3 / RGPIO3 PTA4 / RGPIO4 PTA5 / RGPIO5 PTA6 / RGPIO6 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 2. 80-pin LQFP MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor MCF51JM128 Family Configurations Figure 3 shows the pinout of the 64-pin LQFP and QFP. PTC5 / RXD2 PTC3 / TXD2 PTC2 / IRO PTC1 / SDA1 PTC0 / SCL1 VSS PTG5 / EXTAL PTG4 / XTAL BKGD/MS PTG3 / KBIP7 PTG2 / KBIP6 PTD7 PTD6 PTD5 PTD4 / ADP11 PTD3 / KBIP3 / ADP10 PTC4 IRQ / TPMCLK RESET PTF0 / TPM1CH2 PTF1 / TPM1CH3 PTF2 / TPM1CH4 PTF3 / TPM1CH5 PTF4 / TPM2CH0 PTC6 / RXCAN PTF7 / TXCAN PTF5 / TPM2CH1 PTF6 PTE0 / TXD1 PTE1 / RXD1 PTE2 / TPM1CH0 PTE3 / TPM1CH1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTD2 / KBIP2 / ACMPO VSSAD VREFL VREFH VDDAD PTD1 / ADP9 / ACMP– PTD0 / ADP8 / ACMP+ PTB7 / ADP7 PTB6 / ADP6 PTB5 / KBIP5 / ADP5 PTB4 / KBIP4 / ADP4 PTB3 / SS2 / ADP3 PTB2 / SPSCK2 / ADP2 PTB1 / MOSI2 / ADP1 PTB0 / MISO2 / ADP0 PTA5 / RGPIO5 MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 11 PTE4 / MISO1 PTE5 / MOSI1 PTE6 / SPSCK1 PTE7 / SS1 VDD VSS USBDN USBDP VUSB33 PTG0 / KBIP0 PTG1 / KBIP1 PTA0 / RGPIO0 PTA1 / RGPIO1 PTA2 / RGPIO2 PTA3 / RGPIO3 PTA4 / RGPIO4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. 64-pin QFP and LQFP MCF51JM128 Family Configurations Figure 4 shows the pinout of the 44-pin LQFP. PTC5 / RXD2 PTC3 / TXD2 PTC2 / IRO PTC1 / SDA1 PTC0 / SCL1 VSS PTG5 / EXTAL PTG4 / XTAL BKGD / MS PTG3 / KBIP7 PTG2 / KBIP6 PTC4 IRQ / TPMCLK RESET PTF0 / TPM1CH2 PTF1 / TPM1CH3 PTF4 / TPM2CH0 PTF5 / TPM2CH1 PTE0 / TXD1 PTE1 / RXD1 PTE2 / TPM1CH0 PTE3 / TPM1CH1 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Table 4 shows the package pin assignments. Table 4. Pin Assignments by Package and Pin Sharing Priority Pin Number 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 44 1 2 3 4 5 — — 6 — — 7 — 8 9 10 Highest Alt 1 Alt 2 — TPMCLK — — — — — BUSCLK_OUT — — — — — — — MCF51JM128 ColdFire Microcontroller, Rev. 2 12 Freescale Semiconductor PTE4 / MISO1 PTE5 / MOSI1 PTE6 / SPSCK1 PTE7 / SS1 VDD VSS USBDN USBDP VUSB33 PTG0 / KBIP0 PTG1 / KBIP1 12 13 14 15 16 17 18 19 20 21 22 PTD2 / KBIP2 / ACMPO VSSAD / VREFL VDDAD / VREFH PTD1 / ADP9 / ACMP– PTD0 / ADP8 / ACMP+ PTB5 / KBIP5 / ADP5 PTB4 / KBIP4 / ADP4 PTB3 / SS2 / ADP3 PTB2 / SPSCK2 / ADP2 PTB1 / MOSI2 / ADP1 PTB0 / MISO2 / ADP0 Figure 4. 44-pin LQFP MCF51JM128 Family Configurations Table 4. Pin Assignments by Package and Pin Sharing Priority (continued) Pin Number 80 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 16 — — — — — — 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 — — 34 35 36 37 38 39 40 44 11 — — — — — — 12 13 14 15 16 17 18 19 20 21 22 — — — — — — — — 23 24 25 26 27 28 — Highest Alt 1 TPM1CH1 — SDA2 SCL2 RGPIO8 RGPIO9 RGPIO10 MISO1 MOSI1 SPSCK1 SS1 — — — — — KBIP0 KBIP1 RGPIO0 RGPIO1 RGPIO2 RGPIO3 RGPIO4 RGPIO5 RGPIO6 RGPIO7 MISO2 MOSI2 SPSCK2 SS2 KBIP4 KBIP5 ADP6 Alt 2 — — — — — — — — — — — VDD VSS USBDN USBDP VUSB33 USB_ALT_CLK — USB_SESSVLD USB_SESSEND USB_VBUSVLD USB_PULLUP(D+) USB_DM_DOWN USB_DP_DOWN USB_ID — ADP0 ADP1 ADP2 ADP3 ADP4 ADP5 — MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 13 MCF51JM128 Family Configurations Table 4. Pin Assignments by Package and Pin Sharing Priority (continued) Pin Number 80 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 41 42 43 44 45 46 47 48 — — — — — 49 50 51 52 53 54 55 56 57 58 59 — — — 60 61 62 63 64 33 — — — — — — — — — — 34 35 36 37 38 39 — — — 40 41 42 43 44 32 44 — 29 30 31 Highest Alt 1 ADP7 ADP8 ADP9 — — — — KBIP2 RGPIO11 RGPIO12 RGPIO13 RGPIO14 RGPIO15 KBIP3 ADP11 — — — KBIP6 KBIP7 BKGD XTAL EXTAL — — — — SCL1 SDA1 IRO TXD2 RXD2 VSS VDD — — — — — — — Alt 2 — ACMP+ ACMP– VDDAD VREFH VREFL VSSAD ACMPO — — — — — ADP10 — — — — — — MS MCF51JM128 ColdFire Microcontroller, Rev. 2 14 Freescale Semiconductor Preliminary Electrical Characteristics 2 Preliminary Electrical Characteristics This section contains electrical specification tables and reference timing diagrams for the MCF51JM128 microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this data sheet supersede any values found in the module specifications. 2.1 Parameter Classification Table 5. Parameter Classifications P C The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled C in the parameter tables where appropriate. T D 2.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 6 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, VSS or VDD). MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 15 Preliminary Electrical Characteristics Table 6. Absolute Maximum Ratings Rating Supply voltage Input voltage Instantaneous maximum current (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature Maximum junction temperature 1 Symbol VDD VIn Single pin limit ID IDD Tstg TJ Value –0.3 to + 5.8 – 0.3 to VDD + 0.3 ± 25 120 –55 to +150 150 Unit V V mA mA °C °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load shunt current is greater than maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples: if no system clock is present or if the clock rate is low, which would reduce overall power consumption. 2.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD is small. Table 7. Thermal Characteristics Rating Operating temperature range (packaged) Thermal resistance 80-pin LQFP 1,2,3,4 Symbol TA Value –40 to +105 Unit °C 1s 2s2p 64-pin LQFP 1s 2s2p 64-pin QFP 1s 2s2p 44-pin LQFP 1s 2s2p 1 52 40 θJA 65 47 54 40 69 48 °C/W Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection MCF51JM128 ColdFire Microcontroller, Rev. 2 16 Freescale Semiconductor Preliminary Electrical Characteristics 3 4 1s - Single Layer Board, one signal layer 2s2p - Four Layer Board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) where: TA = Ambient temperature, °CθJA = Package thermal resistance, junction-to-ambient, °C/WPD = Pint + PI/OPint = IDD × VDD, Watts — chip internal powerPI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 4MHz fADCK < 4MHz 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) ADC Conversion High Speed (ADLPC=0) Clock Freq. Low Power (ADLPC=1) 1 Conditions Symb RADIN RAS Min — — — — — — Typ1 3 — — — — — — — Max 5 2 5 5 10 10 8.0 4.0 Unit kΩ kΩ Comment External to MCU fADCK 0.4 0.4 MHz Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + – + – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 9. ADC Input Impedance Equivalency Diagram MCF51JM128 ColdFire Microcontroller, Rev. 2 24 Freescale Semiconductor Preliminary Electrical Characteristics Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Supply CurrentADLPC= 1ADLSMP=1AD CO=1 Supply CurrentADLPC= 1ADLSMP=0AD CO=1 Supply CurrentADLPC= 0ADLSMP=1AD CO=1 Supply CurrentADLPC= 0ADLSMP=0AD CO=1 Supply Current ADC Asynchronous Clock Source Stop, Reset, Module Off High Speed (ADLPC=0) Low Power (ADLPC=1) T tADC T Conditions C T Symb IDDAD Min — Typ1 133 Max — Unit μA Comment T IDDAD — 218 — μA T IDDAD — 327 — μA P IDDAD — 0.582 1 mA IDDAD fADACK — 2 1.25 — — 0.011 3.3 2 20 40 3.5 23.5 ±3.0 ±1 ±0.5 ±1.75 ±0.5 ±0.3 ±1.5 ±0.5 ±0.3 ±1.5 ±0.5 ±0.5 ±1 ±0.5 ±0.5 1 5 3.3 — — — — — ±2.5 ±1.0 — ±1.0 ±0.5 — ±1.0 ±0.5 — ±1.5 ±0.5 — ±1 ±0.5 μA MHz tADACK = 1/fADACK See Table 9 for conversion time variances Conversion Time Short Sample (ADLSMP=0) (Including Long Sample (ADLSMP=1) sample time) Sample Time Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Total Unadjusted 12 bit mode Error 10 bit mode 8 bit mode Differential Non-Linearity 12 bit mode 10 bit mode3 8 bit Integral Non-Linearity mode3 ADCK cycles ADCK cycles LSB2 T tADS — — T P T T P T T T T T P T T T T ETUE — — — Includes quantization DNL — — — LSB2 12 bit mode 10 bit mode 8 bit mode INL — — — LSB2 Zero-Scale Error 12 bit mode 10 bit mode 8 bit mode Full-Scale Error 12 bit mode 10 bit mode 8 bit mode EZS — — — LSB2 VADIN = VSSAD EFS — — — LSB2 VADIN = VDDAD MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 25 Preliminary Electrical Characteristics Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) Characteristic Quantization Error Conditions 12 bit mode 10 bit mode 8 bit mode Input Leakage Error 12 bit mode 10 bit mode 8 bit mode 1 C D Symb EQ Min — — — Typ1 -1 to 0 — — ±1 ±0.2 ±0.1 Max — ±0.5 ±0.5 — ±2.5 ±1 Unit LSB2 Comment D EIL — — — LSB2 Pad leakage4 * RAS Typical values assume VDDAD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. MCF51JM128 ColdFire Microcontroller, Rev. 2 26 Freescale Semiconductor Preliminary Electrical Characteristics 2.9 Num C External Oscillator (XOSC) Characteristics Table 15. Oscillator Electrical Specifications (Temperature Range = –40 to 105°C Ambient) Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) • Low range (RANGE = 0) • High range (RANGE = 1) FEE or FBE mode 2 • High range (RANGE = 1) PEE or PBE mode 3 • High range (RANGE = 1, HGO = 1) BLPE mode • High range (RANGE = 1, HGO = 0) BLPE mode Load capacitors Feedback resistor • Low range (32 kHz to 38.4 kHz) • High range (1 MHz to 16 MHz) Series resistor • Low range, low gain (RANGE = 0, HGO = 0) • Low range, high gain (RANGE = 0, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz • High range, low gain (RANGE = 1, HGO = 0) • High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz — — — 0 100 0 — — — Symbol flo fhi-fll fhi-pll fhi-hgo fhi-lp C1 C2 RF Min Typ1 Max Unit 1 32 1 1 1 1 — — — — — 38.4 5 16 16 8 kHz MHz MHz MHz MHz 2 See crystal or resonator manufacturer’s recommendation. MΩ MΩ 3 10 1 4 — RS kΩ — — — 0 0 0 0 10 20 5 Crystal start-up time 4 • Low range, low gain (RANGE = 0, HGO = 0) T • Low range, high gain (RANGE = 0, HGO = 1) • High range, low gain (RANGE = 1, HG0 = 0)5 • High range, high gain (RANGE = 1, HG0 = 1)5 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) • FEE or FBE mode 2 T • PEE or PBE mode 3 • BLPE mode t CSTL-LP t CSTL-HGO t CSTH-LP t CSTH-HGO — — — — 200 400 5 15 — — — — ms 6 fextal 0.03125 1 0 — — — 5 16 40 MHz MHz MHz Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz. 4 This parameter is characterized and not tested on each device. Proper PC board-layout procedures must be followed to achieve specifications. 5 4 MHz crystal 1 2 MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 27 Preliminary Electrical Characteristics 2.10 Num C MCG Specifications Table 16. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) Rating Symbol fint_ft Min Typical Max Unit 1 Internal reference frequency - factory P trimmed at VDD = 5 V and temperature = 25 °C P P Average internal reference frequency untrimmed 1 Average internal reference frequency user trimmed — 31.25 — kHz 2 3 4 fint_ut fint_t tirefst 25 31.25 — 32.7 — 60 41.66 39.0625 100 kHz kHz us D Internal reference startup time DCO output frequency range untrimmed 1 — value provided for reference: fdco_ut = 1024 X fint_ut P DCO output frequency range - trimmed Resolution of trimmed DCO output C frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output C frequency at fixed voltage and temperature (not using FTRIM) Total deviation of trimmed DCO output P frequency over voltage and temperature Total deviation of trimmed DCO output C frequency over fixed voltage and temperature range of 0 - 70 °C C FLL acquisition time 2 D PLL acquisition time 3 C Long term Jitter of DCO output clock (averaged over 2ms interval) 4 5 fdco_ut 25.6 33.48 42.66 MHz 6 7 fdco_t Δfdco_res_t 32 — — ± 0.1 40 ± 0.2 MHz %fdco 8 Δfdco_res_t — ± 0.2 ± 0.4 %fdco 9 Δfdco_t — + 0.5 -1.0 ±2 %fdco 10 11 12 13 14 17 18 Δfdco_t tfll_acquire tpll_acquire CJitter fvco fpll_jitter_625ns Dlock — — — — 7.0 — ± 1.49 ± 0.5 — — 0.02 — 0.5665 — ±1 1 1 0.2 55.0 — ± 2.98 %fdco ms ms %fdco MHz %fpll % D VCO operating frequency T Jitter of PLL output clock measured over 625 ns5 D Lock entry frequency tolerance 6 MCF51JM128 ColdFire Microcontroller, Rev. 2 28 Freescale Semiconductor Preliminary Electrical Characteristics Table 16. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125°C Ambient) Num C 19 20 Rating Symbol Dunl tfll_lock Min ± 4.47 — Typical — — Max ± 5.97 tfll_acquire+ D Lock time - FLL 1075(1/fint_t ) Unit % s D Lock exit frequency tolerance 7 21 D Lock time - PLL Loss of external clock minimum D frequency - RANGE = 0 tpll_lock — — tpll_acquire+ 1075(1/fpll_r ef) s 22 1 2 floc_low (3/5) x fint — — kHz 3 4 5 6 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG does not enter lock. But if the MCG is already in lock, then the MCG may stay in lock. Below Dunl minimum, the MCG does not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock. 7 2.11 AC Characteristics This section describes ac timing characteristics for each peripheral system. 2.11.1 Num 1 2 3 C Control Timing Table 17. Control Timing Parameter Bus frequency (tcyc = 1/fBus) Internal low-power oscillator period External reset pulse width2 (tcyc = 1/fSelf_reset) Reset low drive Active background debug mode latch setup time Symbol fBus tLPO textrst trstdrv tMSSU Min dc 700 100 66 x tcyc 500 Typ1 — Max 24 1300 — — — Unit MHz μs ns ns ns 4 5 MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 29 Preliminary Electrical Characteristics Table 17. Control Timing Num 6 7 C Parameter Active background debug mode latch hold time IRQ pulse width Asynchronous path2 Synchronous path3 KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Symbol tMSH tILIH, tIHIL Min 100 100 1.5 x tcyc 100 1.5 x tcyc — — Typ1 Max — Unit ns ns — — 8 tILIH, tIHIL — — ns 9 1 2 tRise, tFall 3 30 ns Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. This is the shortest pulse guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 105°C. textrst RESET PIN Figure 10. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 11. IRQ/KBIPx Timing 2.11.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. MCF51JM128 ColdFire Microcontroller, Rev. 2 30 Freescale Semiconductor Preliminary Electrical Characteristics Table 18. TPM Input Timing NUM 1 2 3 4 5 C — — D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTPMext tTPMext tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit MHz tcyc tcyc tcyc tcyc tTPMext tclkh TPMxCLK tclkl Figure 12. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure 13. Timer Input Capture Pulse 2.11.3 Num 1 2 1 MSCAN Table 19. MSCAN Wake-up Pulse Characteristics C D D Parameter MSCAN Wake-up dominant pulse filtered MSCAN Wake-up dominant pulse pass Symbol tWUP tWUP 5 Min Typ1 Max 2 5 Unit μs μs Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 31 Preliminary Electrical Characteristics 2.12 SPI Characteristics Table 20. SPI Electrical Characteristic Num1 1 C D Characteristic2 Operating frequency Master Slave 2 D Cycle time Master Slave 3 D Enable lead time Master Slave 4 D Enable lag time Master Slave 5 6 7 D D D Clock (SPSCK) high time Master and Slave Clock (SPSCK) low time Master and Slave Data setup time (inputs) Master Slave 8 D Data hold time (inputs) Master Slave 9 10 11 D D D Access time, slave3 Disable time, slave4 Data setup time (outputs) Master Slave 12 D Data hold time (outputs) Master Slave 1 2 Table 20 and Figure 14 through Figure 17 describe the timing requirements for the SPI system. Symbol Min Max Unit Hz fop fop tSCK tSCK fBus/2048dc fBus/2 fBus/4 2048 2 4 — 1/2 — 1/2 — 1/2 — tcyc tcyc tLead tLead tLag tLag tSCKH tSCKL tSI(M) tSI(S) tHI(M) tHI(S) tA tdis tSO tSO tHO tHO tSCKtS CK — 1/2 tSCKtS CK 1/2 tSCK – 25 1/2 tSCK – 25 30 30 — — — — ns ns ns ns 30 30 0 — 25 25 — — 40 40 — — ns ns ns ns ns ns –10 –10 — — ns ns Refer to Figure 14 through Figure 17. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. MCF51JM128 ColdFire Microcontroller, Rev. 2 32 Freescale Semiconductor Preliminary Electrical Characteristics SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 10 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 10 BIT 6 . . . 1 LSB OUT LSB IN 11 1 5 4 3 5 4 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 14. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 10 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 3 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 15. SPI Master Timing (CPHA = 1) MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 33 Preliminary Electrical Characteristics SS (INPUT) 2 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) NOTE: 3 5 4 5 4 11 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 12 SLAVE LSB OUT SEE NOTE 9 1. Not defined but normally MSB of character received Figure 16. SPI Slave Timing (CPHA = 0) SS (INPUT) 2 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 11 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 12 BIT 6 . . . 1 SLAVE LSB OUT 9 3 NOTE: 1. Not defined but normally LSB of character received Figure 17. SPI Slave Timing (CPHA = 1) MCF51JM128 ColdFire Microcontroller, Rev. 2 34 Freescale Semiconductor Preliminary Electrical Characteristics 2.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. Table 21. Flash Characteristics Num 1 2 3 4 5 C Characteristic Supply voltage for program/erase Supply voltage for read operation Internal FCLK frequency2 Internal FCLK period (1/FCLK) Byte program time (random location)(2) Byte program time (burst mode)(2) Page erase time3 Mass erase time(2) Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass Min 2.7 2.7 150 5 Typ1 Max 5.5 5.5 200 6.67 Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc 9 4 4000 20,000 6 7 8 9 C Program/erase endurance4 TL to TH = –40°C to + 105°C T = 25°C Data retention5 tD_ret 10,000 — 15 — 100,000 100 — — — cycles 10 1 years 2 Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated. The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 2.14 USB Electricals The USB electricals for the USBOTG module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. If the Freescale USBOTG implementation requires additional or deviant electrical characteristics, this space would be used to communicate that information. MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 35 Preliminary Electrical Characteristics Table 22. Internal USB 3.3V Voltage Regulator Characteristics Symbol Regulator operating voltage Vreg output Vusb33 input with internal Vreg disabled VREG Quiescent Current Vregin Vregout Vusb33in IVRQ Unit V V V Min 3.9 3 3 Typ — 3.3 3.3 Max 5.5 3.6 3.6 mA — 0.5 — 2.15 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 2.15.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. MCF51JM128 ColdFire Microcontroller, Rev. 2 36 Freescale Semiconductor Mechanical Outline Drawings 3 3.1 Mechanical Outline Drawings 80-pin LQFP MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 37 Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 38 Freescale Semiconductor Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 39 Mechanical Outline Drawings 3.2 64-pin LQFP MCF51JM128 ColdFire Microcontroller, Rev. 2 40 Freescale Semiconductor Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 41 Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 42 Freescale Semiconductor Mechanical Outline Drawings 3.3 64-pin QFP MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 43 Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 44 Freescale Semiconductor Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 45 Mechanical Outline Drawings 3.4 44-pin LQFP MCF51JM128 ColdFire Microcontroller, Rev. 2 46 Freescale Semiconductor Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 47 Mechanical Outline Drawings MCF51JM128 ColdFire Microcontroller, Rev. 2 48 Freescale Semiconductor Revision History 4 Revision History Table 23. Changes Between Revisions Revision 1 Description Updated features list Updated the figures Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1), Typical Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0), and Typical High-side Drive (source) characteristics – High Drive (PTxDSn = 1) Added the figure Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0) Updated the Supply Current Characteristics table Updated the Oscillator Electrical Specifications (Temperature Range = –40 to 105×C Ambient) table Updated the SPI Electrical Characteristic table Updated the DC Characteristics table Updated the table Orderable Part Number Summary, DC Characteristics, and Supply Current Characteristics This section lists major changes between versions of the MCF51JM128 Data Sheet document. 2 MCF51JM128 ColdFire Microcontroller, Rev. 2 Freescale Semiconductor 49 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008. All rights reserved. D ocument Number: MCF51JM128 Rev. 2 09/2008