Freescale Semiconductor Data Sheet: Technical Data
Document Number: MCF51QE128 Rev. 7, 10/2008
MCF51QE128 Series
Covers: MCF51QE128, MCF51QE32 MCF51QE96, MCF51QE64,
MCF51QE128
80-LQFP Case 917A 14 mm2 64-LQFP Case 840F 10 mm2
• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU) – Up to 50.33-MHz ColdFire V1 CPU above 2.4V, 40-MHz CPU above 2.1V, and 20-MHz CPU above 1.8V, across temperature range – Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM (0.76 DMIPS/MHz from flash) – Implements Instruction Set Revision C (ISA_C) – Support for up to 30 peripheral interrupt requests and seven software interrupts • On-Chip Memory – Flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two low power stop modes; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode – Very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals – Very low power real time counter for use in run, wait, and stop modes with internal and external clock sources – 6 μs typical wake up time from stop modes • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — FLL controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode and illegal address detection with programmable reset or exception response – Flash block protection
• Development Support – Single-wire background debug interface – 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response – 64-entry processor status and debug data trace buffer with programmable start/stop conditions • ADC — 24-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V • ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 • SCIx — Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge • SPIx— Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting • IICx — Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing • TPMx — One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel • RTC — 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components • Input/Output – 70 GPIOs and 1 input-only and 1 output-only pin – 16 KBI interrupts with selectable polarity – Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all output pins. – SET/CLR registers on 16 pins (PTC and PTE) – 16 bits of Rapid GPIO connected to the CPU’s high-speed local bus with set, clear, and toggle functionality
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 2 3 MCF51QE128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18 3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .19 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . . 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 23 24 27 27 30 31 31 31 36 36
4 5 6 7
MCF51QE128 Series Data Sheet, Rev. 7 2 Freescale Semiconductor
TPM1CH2-0 RESET
V1 ColdFire CORE
BKGD/MS CPU
MODULE (TPM1) ANALOG COMPARATOR (ACMP1)
TPM1CLK ACMP1O ACMP1+ ACMP1EXTAL XTAL 3
BDC / Debug
IP Bus Bridge INTERNAL CLOCK SOURCE (ICS) OSCILLATOR (XOSC)
PORT A
3-CHANNEL TIMER/PWM
PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6 PTB1/KBI1P5/TxD1/ADP5 PTB0/KBI1P4/RxD1/ADP4 PTC7/RGPIO15/TxD2/ACMP2PTC6/RGPIO14/RxD2/ACMP2+ PTC5/RGPIO13/TPM3CH5/ACMP2O PTC4/RGPIO12/TPM3CH4/RSTO PTC3/RGPIO11/TPM3CH3 PTC2/RGPIO10/TPM3CH2 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0 PTD7/KBI2P7 PTD6/KBI2P6 PTD5/KBI2P5 PTD4/KBI2P4 PTD3/KBI2P3/SS2 PTD2/KBI2P2/MISO2 PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTE7/RGPIO7/TPM3CLK PTE6/RGPIO6 PTE5/RGPIO5 PTE4/RGPIO4 PTE3/RGPIO3/SS1 PTE2/RGPIO2/MISO1 PTE1/RGPIO1/MOSI1 PTE0/RGPIO0/TPM2CLK/SPSCK1 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTF3/ADP13 PTF2/ADP12 PTF1/ADP11 PTF0/ADP10 PTG7/ADP23 PTG6/ADP22 PTG5/ADP21 PTG4/ADP20 PTG3/ADP19 PTG2/ADP18 PTG1 PTG0
SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ COP INTC LVD -
TPM2CH2-0 3-CHANNEL TIMER/PWM MODULE (TPM2) TPM2CLK SCL1 SDA1 ACMP2+ ACMP2O ACMP2TPM3CH5-0 6-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CLK 16 SERIAL COMMUNICATIONS INTERFACE (SCI1) TxD1 RxD1 SS2 MISO2 MOSI2 SPSCK2 TxD2 RxD2
IIC MODULE (IIC1) ANALOG COMPARATOR (ACMP2)
USER FLASH 128K / 64K
USER RAM 8K / 6K / 4K
Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2)
REAL TIME COUNTER (RTC) VDD VDD VSS VSS PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 VREFH VREFL VDDA VSSA PTH7/SDA2 PTH6/SCL2 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 SDA2 SCL2
VOLTAGE REGULATOR
SERIAL COMMUNICATIONS INTERFACE (SCI2)
PORT J
SERIAL PERIPHERAL INTERFACE MODULE (SPI1)
SS1 MISO1 MOSI1 SPSCK1
IIC MODULE (IIC2)
PORT H
Figure 1. MCF51QE128 Series Block Diagram
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 3
PORT G
PORT F
24-CHANNEL,12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
PORT E
PORT D
PORT C
PORT B
MCF51QE128 Series Comparison
1
MCF51QE128 Series Comparison
Table 1. MCF51QE128 Series Features by MCU and Package
Feature Flash size (bytes) RAM size (bytes) Pin quantity Version 1 ColdFire core ACMP1 ACMP2 ADC channels DBG ICS IIC1 IIC2 KBI Port I/O1, 2 Rapid GPIO RTC SCI1 SCI2 SPI1 SPI2 External IRQ TPM1 channels TPM2 channels TPM3 channels XOSC
1
The following table compares the various device derivatives available within the MCF51QE128 series.
MCF51QE128 131072 8192 80 64
MCF51QE96 98304 8192 80 64 yes yes yes
MCF51QE64 65536 8192 64
MCF51QE32 32768 8192 64
24
20
24
20 yes yes yes yes 16
20
20
70
54
70
54 yes yes yes yes yes yes yes 3 3 6 yes
54
54
Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the output-only PTA4/ACMP1O/BKGD/MS. 2 16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO module.
MCF51QE128 Series Data Sheet, Rev. 7 4 Freescale Semiconductor
Pin Assignments
2
Pin Assignments
PTC7/RGPIO15 /TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA5/IRQ/TPM1CLK/RESET PTC4/RGPIO12/TPM3CH4/RSTO PTC5/RGPIO13/TPM3CH5/ACMP2O
This section describes the pin assignments for the available packages. See Table 1 for pin availability by package pin-count.
PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTH5 PTH4 PTE7/RGPIO7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTH3 PTH2 PTH1 PTH0 PTE6/RGPIO6
PTE5/RGPIO5 PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTC3/RGPIO11/TPM3CH3 PTC2/RGPIO10/TPM3CH2 PTD7/KBI2P7 PTD6/KBI2P6
Pins in bold are added from the next smaller package.
Figure 2. Pin Assignments in 80-Pin LQFP
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 5
PTD5/KBI2P5 PTJ7 PTJ6 PTJ5 PTJ4 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PTE0/RGPIO0/TPM2CLK/SPSCK1 PTE1/RGPIO1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/RGPIO2/MISO1 PTE3/RGPIO3/SS1 PTG4/ADP20 PTG5/ADP21 PTG6/ADP22 PTG7/ADP23 PTC6/RGPIO14/RxD2/ACMP2+
PTA4/ACMP1O/BKGD/MS
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PTA2/KBI1P2/SDA1/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 PTJ0 PTJ1 PTF0/ADP10 PTF1/ADP11 VSS VDD PTE4/RGPIO4 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTF2/ADP12 PTF3/ADP13 PTJ2 PTJ3 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5
6
PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTE7/RGPIO7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTE6/RGPIO6 PTH1 PTH0
Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PTA4/ACMP1O/BKGD/MS PTA5/IRQ/TPM1CLK/RESET PTC4/RGPIO12/TPM3CH4/RSTO PTC5/RGPIO13/TPM3CH5/ACMP2O PTE0/RGPIO0/TPM2CLK/SPSCK1 PTE1/RGPIO1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/RGPIO2/MISO1 PTE3/RGPIO3/SS1
PTE5/RGPIO5 PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTC3/RGPIO11/TPM3CH3 PTC2/RGPIO10/TPM3CH2 PTD7/KBI2P7 PTD6/KBI2P6
PTC6/RGPIO14/RxD2/ACMP2+
PTC7/RGPIO15/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
Figure 3. Pin Assignments in 64-Pin LQFP Package
PTD5/KBI2P5 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6
MCF51QE128 Series Data Sheet, Rev. 7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD PTE4/RGPIO4 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTF2/ADP12 PTF3/ADP13 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PTA2/KBI1P2/SDA11/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 PTF0/ADP10 PTF1/ADP11 VSS
Freescale Semiconductor
Pin Assignments
Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority
Pin Number 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 1 2 3 4 — — 5 6 7 8 9 10 11 12 13 — — 14 15 16 17 18 19 20 21 22 23 24 — — — — 25 26 27 28 29 30 31 32 PTB7 PTB6 PTH3 PTH2 PTH1 PTH0 PTE6 PTE5 PTB5 PTB4 PTC3 PTC2 PTD7 PTD6 PTD5 PTJ7 PTJ6 PTJ5 PTJ4 PTC1 PTC0 PTF7 PTF6 PTF5 PTF4 PTB3 PTB2 KBI1P7 KBI1P6 MOSI11 SPSCK1 RGPIO9 RGPIO8 TPM3CH1 TPM3CH0 ADP17 ADP16 ADP15 ADP14 ADP7 ADP6 RGPIO6 RGPIO5 TPM1CH1 TPM2CH1 RGPIO11 RGPIO10 KBI2P7 KBI2P6 KBI2P5 SS1 MISO1 TPM3CH3 TPM3CH2 SCL1 SDA1 Lowest Port Pin PTD1 PTD0 PTH7 PTH6 PTH5 PTH4 PTE7 RGPIO7 TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS EXTAL XTAL ←⎯ Alt 1 KBI2P1 KBI2P0 SDA2 SCL2 Priority Alt 2 MOSI2 SPSCK2 ⎯→ Alt 3 Highest Alt 4
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 7
Pin Assignments
Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority (continued)
Pin Number 80 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 33 34 — — 35 36 37 38 39 40 41 42 43 — — 44 45 46 47 48 49 50 51 52 — — — — 53 54 55 56 57 58 59 60 61 62 63 64 PTF1 PTF0 PTJ1 PTJ0 PTD4 PTD3 PTD2 PTA3 PTA2 PTA1 PTA0 PTC7 PTC6 PTG7 PTG6 PTG5 PTG4 PTE3 PTE2 PTG3 PTG2 PTG1 PTG0 PTE1 PTE0 PTC5 PTC4 PTA5 PTA43 RGPIO1 RGPIO0 RGPIO13 RGPIO12 IRQ ACMP1O MOSI1 TPM2CLK TPM3CH5 TPM3CH4 TPM1CLK BKGD RSTO RESET MS SPSCK1 ACMP2O RGPIO3 RGPIO2 SS1 MISO1 ADP19 ADP18 KBI2P4 KBI2P3 KBI2P2 KBI1P3 KBI1P2 KBI1P1 KBI1P0 RGPIO15 RGPIO14 SS2 MISO2 SCL12 SDA1 TPM2CH0 TPM1CH0 TxD2 RxD2 ADP1 ADP0 ADP3 ADP2 ACMP1ACMP1+ ACMP2ACMP2+ ADP23 ADP22 ADP21 ADP20 Lowest Port Pin PTB1 PTB0 PTJ3 PTJ2 PTF3 PTF2 PTA7 PTA6 PTE4 TPM2CH2 TPM1CH2 RGPIO4 VDD VSS ADP11 ADP10 ADP13 ADP12 ADP9 ADP8 ←⎯ Alt 1 KBI1P5 KBI1P4 Priority Alt 2 TxD1 RxD1 ⎯→ Alt 3 Highest Alt 4 ADP5 ADP4
MCF51QE128 Series Data Sheet, Rev. 7 8 Freescale Semiconductor
Electrical Characteristics
1
SPI1 pins (SS1, MISO1, MOSI1, and SPSCK2) can be repositioned using SPI1PS in SOPT2. Default locations are PTB5, PTB4, PTB3, and PTB2. 2 IIC1 pins (SCL1 and SDA1) can be repositioned using IIC1PS in SOPT2. Default locations are PTA3 and PTA2, respectively. 3 The PTA4/ACMP1O/BKGD/MS is limited to output only for the port I/O function.
3
3.1
Electrical Characteristics
Introduction
This section contains electrical and timing specifications for the MCF51QE128 series of microcontrollers available at the time of publication.
3.2
Parameter Classification
Table 3. Parameter Classifications P C T D
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
NOTE
The classification is shown in the column labeled “C” in the parameter tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 9
Electrical Characteristics
Table 4. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value –0.3 to +3.8 120 –0.3 to VDD + 0.3 ± 25 –55 to 150
Unit V mA V mA °C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics
Rating Operating temperature range (packaged): MCF51QE64, MCF51QE96, and MCF51QE128: MCF51QE32: Maximum junction temperature Thermal resistance Single-layer board 64-pin LQFP 80-pin LQFP Thermal resistance Four-layer board 64-pin LQFP 80-pin LQFP θJA 50 47 °C/W θJA 69 60 °C/W –40 to 85 TA 0 to 70 95 °C Symbol Value Unit
TJM
°C
MCF51QE128 Series Data Sheet, Rev. 7 10 Freescale Semiconductor
Electrical Characteristics
The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 2.7 V VDD > 1.8 V VDD > 2.7 V VDD >1.8 V 0.70 x VDD 0.85 x VDD — — 0.06 x VDD VIn = VDD or VSS VIn = VDD or VSS — —
Max total IOH for all ports All I/O pins, low-drive strength All I/O pins, high-drive strength
IOHT
VOL
2.7 V, ILoad = 10 mA 2.3 V, ILoad = 6 mA 1.8 V, ILoad = 3 mA
Max total IOL for all ports all digital inputs
IOLT VIH
6
P Input high voltage C P Input low voltage
all digital inputs VIL all digital inputs all input only pins (Per pin) all input/output (per pin) all digital inputs, when enabled Vhys |IIn| |IOZ| RPU
7 C 8 9 10 C Input hysteresis P P Input leakage current Hi-Z (off-state) leakage current Pull-up resistors 11 P
17.5
—
52.5
MCF51QE128 Series Data Sheet, Rev. 7 12 Freescale Semiconductor
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C DC injection 3, 4, 5 D current Characteristic Single pin limit Total MCU limit, includes sum of all stressed pins IIC CIn VRAM VPOR tPOR VLVDH8 VLVDL VLVWH VLVWL Vhys VBG VDD falling VDD rising VDD falling VDD rising VDD falling VDD rising VDD falling VDD rising VIN < VSS, VIN > VDD Symbol Condition Min –0.2 –5 — — 0.9 10 2.11 2.16 1.80 1.86 2.36 2.36 2.11 2.16 — 1.15 Typ1 — — — 0.6 1.4 — 2.16 2.21 1.82 1.90 2.46 2.46 2.16 2.21 50 1.17 Max 0.2 5 8 1.0 1.79 — 2.22 2.27 1.91 1.99 2.56 2.56 2.22 2.27 — 1.18 Unit mA mA pF V V μs V V V V mV V
12
13 14 15 16 17 18 19 20 21 22
1 2 3 4 5
C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage6 D POR re-arm time P P P P C Low-voltage detection threshold — high range7 Low-voltage detection threshold — low range7 Low-voltage warning threshold — high range7 Low-voltage warning threshold — low range7 Low-voltage inhibit reset/recover hysteresis7
P Bandgap Voltage Reference9
6 7 8 9
Typical values are measured at 25°C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed.
Low voltage detection and warning limits measured at 1 MHz bus frequency.
Run at 1 MHz bus frequency Factory trimmed at VDD = 3.0 V, Temp = 25°C
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 13
Electrical Characteristics
PULL-DOWN RESISTANCE (kΩ) PULL-UP RESISTOR TYPICALS 85°C 25°C –40°C
40 PULL-UP RESISTOR (kΩ) 35 30 25 20 1.8
40 35 30 25 20 1.8
PULL-DOWN RESISTOR TYPICALS 85°C 25°C –40°C
2
2.2
2.4
2.6 2.8 VDD (V)
3
3.2
3.4
3.6
2.3
2.8 VDD (V)
3.3
3.6
Figure 4. Pull-up and Pull-down Typical Resistor Values
TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 1 0.8 VOL (V) VOL (V) 0.6 0.4 0.2 0 0 5 10 IOL (mA) 15 20 0 1 2 VDD (V) 3 4
85°C 25°C –40°C
0.2 0.15 0.1 0.05
TYPICAL VOL VS VDD
85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA
Figure 5. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS IOL AT VDD = 3.0 V 1 0.8 VOL (V) 0.6 0.4 0.2 0 0 10 IOL (mA) 20 30
85°C 25°C –40°C
TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 1 2 VDD (V) 3 4 IOL = 6 mA IOL = 3 mA
85°C 25°C –40°C
IOL = 10 mA
Figure 6. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
MCF51QE128 Series Data Sheet, Rev. 7 14 Freescale Semiconductor
Electrical Characteristics
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 1.2 VDD – VOH (V) 1 0.8 0.6 0.4 0.2 0 0 –5 –10 IOH (mA)) –15 –20 VDD – VOH (V)
85°C 25°C –40°C
TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.25 0.2 0.15 0.1 0.05 0 1 2 VDD (V) 3 4
85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA
Figure 7. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.4
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
VDD – VOH (V)
0.6 0.4 0.2 0 0
85°C 25° C –40°C
VDD – VOH (V)
0.8
0.3 0.2 0.1 0
85°C 25° C –40°C
IOH = –10 mA IOH = –6 mA IOH = –3 mA 1 2 VDD (V) 3 4
–5
–10
–15 –20 IOH (mA)
–25
–30
Figure 8. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
Table 9. Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Num
C P P
Parameter Run supply current FEI mode, all modules on
Symbol
Bus Freq 25.165 MHz
VDD (V)
Typ1 32 32
Max 35 35 — — — 29.6 —
Unit
Temp (°C) –40 to 25 85
1
T T T C T Run supply current FEI mode, all modules off
RIDD
20 MHz 8 MHz 1 MHz 25.165 MHz 20 MHz
3
28.0 13.2 2.4 28.1 22.9
mA –40 to 85
2 T T
RIDD
3 8 MHz 1 MHz 11.3 2.0 — —
mA
–40 to 85
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 15
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
Num C T 3 T Run supply current LPS=1, all modules off, running from Flash Wait mode supply current FEI mode, all modules off WIDD Parameter Run supply current LPS=0, all modules off RIDD Symbol Bus Freq 16 kHz FBILP 3 16 kHz FBELP 16 kHz FBELP 25.165 MHz 20 MHz 3 8 MHz 1 MHz Stop2 mode supply current 3 S2IDD n/a 0.6 2 2.5 6.0 Stop3 mode supply current No clocks active 0.8 3 S3IDD n/a 0.8 2 5.0 12.0 1.3 16 20 6.0 18.0 0.8 10 12 1.3 18 28 μA 2 0.73 0.6 3.0 8.0 — — 0.8 11 20 μA -40 to 25 70 85 -40 to 25 70 85 -40 to 25 70 85 -40 to 25 70 85 3 154 — VDD (V) Typ1 203 Max — μA –40 to 85 Unit Temp (°C)
4
T C T
RIDD
50 11 4.57
— 13.7 —
μA
–40 to 85
5 T T P C P 6 C C C P C P 7 C C C
1
mA
–-40 to 85
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Table 10. Stop Mode Adders
Temperature (°C) Num 1 2 3 4 5 6 7 C T T T T T T T Parameter LPO ERREFSTEN IREFSTEN1 RTC LVD1 ACMP ADC
1 1
Condition -40 50 RANGE = HGO = 0 1000 63 does not include clock source current LVDSE = 1 not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 not using the bandgap (BGBE = 0) 50 90 18 95 25 75 1000 70 75 100 20 106 70 100 1100 77 100 110 22 114 85 150 1500 81 150 115 23 120
Units nA nA uA nA uA uA uA
MCF51QE128 Series Data Sheet, Rev. 7 16 Freescale Semiconductor
Electrical Characteristics
1
Not available in stop2 mode.
35
30
25
FEI: 24 MHz 20 IDD (mA) FBELP: 24 MHz FEI: 8 MHz FBELP: 8 MHz 15 FEI: 1 MHz FBELP: 1 MHz
10
5
0 1.8 2 2.2 2.4 VDD (V) 2.6 2.8 3
Figure 9. Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled)
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 17
Electrical Characteristics
3.8
External Oscillator (XOSC) Characteristics
Table 11. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Reference Figure 10 and Figure 11 for crystal or resonator circuits.
Num
C
Characteristic
Symbol flo fhi fhi C1,C2
Min
Typ1
Max
Unit
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) D Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings
32 1 1
— — —
38.4 16 8
kHz MHz MHz
2
See Note2 See Note3
3
Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, High Gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high power C High range, low power High range, high power D Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode FBELP mode
RF
— — — — — — — — —
— 10 1 — 0 100 0 0 0 200 400 5 15 — —
— — — — — — 0 10 20 — — — — 40.0 50.33
MΩ
4
RS
kΩ
t CSTL t CSTH
5
— — — — 0.03125 0
ms
6
1 2
fextal
MHz MHz
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications.
MCF51QE128 Series Data Sheet, Rev. 7 18 Freescale Semiconductor
Electrical Characteristics
XOSC EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 10. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSC EXTAL XTAL
Crystal or Resonator
Figure 11. Typical Crystal or Resonator Circuit: Low Range/Low Gain
3.9
Num 1 2 3 C P P T P 4 P P P 5 P P 6 7 C C
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Characteristic Average internal reference frequency — factory trimmed at VDD = 3.6 V and temperature = 25°C Internal reference frequency — user trimmed Internal reference start-up time Low range (DRS=00) DCO output frequency range — trimmed 2 DCO output frequency 2 Reference = 32768 Hz and DMX32 = 1 Mid range (DRS=01) High range (DRS=10) Low range (DRS=00) Mid range (DRS=01) High range (DRS=10) Δfdco_res_t Δfdco_res_t fdco_DMX32 fdco_u Symbol fint_ft fint_ut tIRST Min — 31.25 — 16 32 48 — — — — — Typ1 32.768 — 60 — — — 19.92 39.85 59.77 ± 0.1 ± 0.2 Max — 39.06 100 20 40 60 — — — ± 0.2 ± 0.4 %fdco %fdco MHz MHz Unit kHz kHz μs
Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM)
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 19
Electrical Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Num 8 9 10 11
1 2
C C C
Characteristic Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0°C to 70 °C
Symbol Δfdco_t Δfdco_t tAcquire CJitter
Min — — — —
Typ1 + 0.5 -1.0 ± 0.5 — 0.02
Max ±2 ±1 1 0.2
Unit %fdco %fdco ms %fdco
C FLL acquisition time 3 C Long term jitter of DCO output clock (averaged over 2-ms interval) 4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
0.60%
0.40%
0.20%
0.00% -40
% deviation
-20
0
20
40
60
80
100
120
-0.20%
-0.40%
-0.60%
-0.80%
-1.00% VDD
Figure 12. Deviation of DCO Output Across Temperature at VDD = 3.0 V
MCF51QE128 Series Data Sheet, Rev. 7 20 Freescale Semiconductor
Electrical Characteristics
0.50%
0.40%
0.30%
0.20%
0.10%
% deviation
0.00% 2.1V -0.10%
2.4V
2.7V
3.0V
3.3V
3.6V
-0.20%
-0.30%
-0.40%
-0.50% VDD
Figure 13. Deviation of DCO Output Across VDD at 25°C
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Num C
Control Timing
Table 13. Control Timing
Rating Bus frequency (tcyc = 1/fBus) VDD ≥ 1.8V VDD > 2.1V VDD > 2.4V Internal low power oscillator period External reset pulse Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 width2 Symbol Min Typ1 — — — — — — — — Max 10 20 25.165 1300 — — — — Unit
1
D
fBus
dc
MHz
2 3 4 5 6
D D D D D
tLPO textrst trstdrv tMSSU tMSH
700 100 34 x tcyc 500 100
μs ns ns ns μs
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 21
Electrical Characteristics
Table 13. Control Timing (continued)
Num 7 C D IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 9 C Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
10
1 2
Rating
Symbol tILIH, tIHIL
Min 100 2 x tcyc 100 2 x tcyc
Typ1 — — — —
Max — — — —
Unit
ns
8
D
tILIH, tIHIL
ns
tRise, tFall
— —
8 31
— —
ns
tRise, tFall
— — —
7 24 4
— — —
ns
Voltage regulator recovery time
tVRR
μs
Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt request until it is explicitly negated by the interrupt service routine. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst RESET PIN
Figure 14. Reset Timing
tIHIL KBIPx
IRQ/KBIPx tILIH
Figure 15. IRQ/KBIPx Timing
MCF51QE128 Series Data Sheet, Rev. 7 22 Freescale Semiconductor
Electrical Characteristics
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TPM Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW
tTCLK tclkh
Min 0 4 1.5 1.5 1.5
Max fBus/4 — — — —
Unit Hz tcyc tcyc tcyc tcyc
TCLK tclkl
Figure 16. Timer External Clock
tICPW TPMCHn
TPMCHn tICPW
Figure 17. Timer Input Capture Pulse
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 23
Electrical Characteristics
3.10.3
SPI Timing
Table 15. SPI Timing
Table 15 and Figure 18 through Figure 21 describe the timing requirements for the SPI system.
No. —
C D
Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output
Symbol fop
Min fBus/2048 0
Max fBus/2 fBus/4 2048 — — — — — 1024 tcyc — — — — — 1 1 25 25 — — tcyc – 25 25 tcyc – 25 25
Unit Hz Hz tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc ns ns ns ns ns ns ns ns
tSPSCK 2 4 tLead 1/2 1 1/2 1 tcyc – 30 tcyc – 30 tSU 15 15 tHI 0 25 ta tdis tv — — tHO 0 0 tRI tRO tFI tFO — — — — — —
1
D
2
D
tLag
3
D
tWSPSCK
4
D
5
D
6 7 8 9
D D D D
10
D
11
D
12
D
MCF51QE128 Series Data Sheet, Rev. 7 24 Freescale Semiconductor
Electrical Characteristics
SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 6 MSB IN2 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN
10
1 4 4
11
3
12
NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA = 0)
SS(1) (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT(2) 6 MSB IN(2) BIT 6 . . . 1
10 12 11
3
4
11
12
LSB IN
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI Master Timing (CPHA =1)
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 25
Electrical Characteristics
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT)
NOTE:
12
11
3
4
4
11
12
8 9 MSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1
10 10
SLAVE LSB OUT
SEE NOTE
1. Not defined but normally MSB of character just received
Figure 20. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4
11 12 12
3
11
10
8 SLAVE LSB OUT
BIT 6 . . . 1
NOTE: 1. Not defined but normally LSB of character just received
Figure 21. SPI Slave Timing (CPHA = 1)
MCF51QE128 Series Data Sheet, Rev. 7 26 Freescale Semiconductor
Electrical Characteristics
3.11
C D C D C C P C
Analog Comparator (ACMP) Electricals
Table 16. Analog Comparator Electrical Specifications
Characteristic Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT 3.0 — — Min 1.80 — VSS – 0.3 Typical — 20 — 20 9.0 — — Max 3.6 35 VDD 40 15.0 1.0 1.0 Unit V μA V mV mV μA μs
3.12
C D D D D D C C
ADC Characteristics
Table 17. 12-bit ADC Operating Conditions
Characteristic Conditions Absolute Delta to VDD (VDD-VDDAD)2 Symb VDDAD ΔVDDAD ΔVSSAD VREFH VREFL VADIN CADIN RADIN 12 bit mode fADCK > 4MHz fADCK < 4MHz 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) RAS — — — — — fADCK 0.4 0.4 — — — — — — — 2 5 kΩ 5 10 10 8.0 MHz 4.0 VSS (VSS-VSSAD)2 Min 1.8 -100 -100 1.8 VSSAD VREFL — — Typ1 — 0 0 VDDAD VSSAD — 4.5 5 Max 3.6 +100 +100 VDDAD VSSAD VREFH 5.5 7 Unit V mV mV V V V pF kΩ External to MCU Comment
Supply voltage
Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance Analog Source Resistance
Delta to
C
D
1
ADC Conversion High Speed (ADLPC=0) Clock Freq. Low Power (ADLPC=1)
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 27
Electrical Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT ZAS RAS Pad leakage due to input protection SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+
VADIN VAS
+ –
CAS
–
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 22. ADC Input Impedance Equivalency Diagram Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 Supply Current ADC Asynchronous Clock Source Stop, Reset, Module Off High Speed (ADLPC=0) Low Power (ADLPC=1) Conditions C T Symb IDDAD Min — Typ1 120 Max — μA Unit Comment
T
IDDAD
—
202
— μA
T
IDDAD
—
288
— μA
D
IDDAD
—
0.532
1 mA
T P P
IDDAD fADACK
— 2 1.25
0.007 3.3 2
0.8 5 3.3
μA tADACK = 1/fADACK MHz
MCF51QE128 Series Data Sheet, Rev. 7 28 Freescale Semiconductor
Electrical Characteristics
Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic Conditions C P C P C T P T T P T T T T T P T T P T D EQ EFS EZS INL DNL ETUE tADS Symb tADC Min — — — — — — — — — — — — — — — — — — — — — — D EIL — — — D m — — D VTEMP25 — Typ1 20 40 3.5 23.5 ±3.0 ±1 ±0.5 ±1.75 ±0.5 ±0.3 ±1.5 ±0.5 ±0.3 ±1.5 ±0.5 ±0.5 ±1.0 ±0.5 ±0.5 -1 to 0 — — ±2 ±0.2 ±0.1 1.646 1.769 701.2 Max — — — — — ±2.5 ±1.0 — ±1.0 ±0.5 — ±1.0 ±0.5 — ±1.5 ±0.5 — ±1 ±0.5 — ±0.5 ±0.5 — ±4 ±1.2 — — — mV mV/°C LSB2 Pad leakage4 * RAS LSB2 LSB2 VADIN = VDDAD LSB2 VADIN = VSSAD LSB2 LSB2 Unit ADCK cycles ADCK cycles LSB2 Comment See the ADC chapter in the MCF51QE128 Reference Manual for conversion time variances Includes Quantization
Conversion Time Short Sample (ADLSMP=0) (Including Long Sample (ADLSMP=1) sample time) Sample Time Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Total Unadjusted 12 bit mode Error 10 bit mode 8 bit mode Differential Non-Linearity 12 bit mode 10 bit mode3 8 bit mode3 Integral Non-Linearity 12 bit mode 10 bit mode 8 bit mode Zero-Scale Error 12 bit mode 10 bit mode 8 bit mode Full-Scale Error 12 bit mode 10 bit mode 8 bit mode Quantization Error 12 bit mode 10 bit mode 8 bit mode Input Leakage Error 12 bit mode 10 bit mode 8 bit mode Temp Sensor Slope Temp Sensor Voltage
1
-40°C to 25°C 25°C to 85°C 25°C
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals.
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 29
Electrical Characteristics
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section of the MCF51QE128 Reference Manual. Table 19. Flash Characteristics
C D D D D P P P P Characteristic Supply voltage for program/erase -40°C to 85°C Supply voltage for read operation Internal FCLK frequency1 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE — — 10,000 — tD_ret 15
3
Min 1.8 1.8 150 5
Typical
Max 3.6 3.6 200 6.67
Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc
Internal FCLK period (1/FCLK) Longword program time (random location)(2) Longword program time (burst Page erase Mass erase time2 time(2) mode)(2)
9 4 4000 20,000 9.7 7.6 — 100,000 100 — — — — —
Longword program current3 Page erase current C C
1 2
mA mA cycles years
Program/erase TL to TH = –40°C to + 85°C T = 25°C Data retention5
endurance4
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
MCF51QE128 Series Data Sheet, Rev. 7 30 Freescale Semiconductor
Ordering Information
4
Ordering Information
Table 20. Ordering Information
Freescale Part Number1 Flash MCF51QE128CLK MCF51QE128CLH MCF51QE96CLK MCF51QE96CLH MCF51QE64CLH MCF51QE32CLH MCF51QE32LH 128K 128K 96K 64K 32K 32K Memory RAM 8K 8K 8K 8K 8K 8K -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 80 LQFP 64 LQFP 80 LQFP 64 LQFP 64 LQFP 64 LQFP 64 LQFP Temperature range (°C) Package2
This section contains ordering information for MCF51QE128MCF51QE96, and MCF51QE64 devices.
1 2
See the reference manual, MCF51QE128RM, for a complete description of modules included on each device. See Table 21 for package information.
5
Package Information
Table 21. Package Descriptions
Pin Count 80 64 Package Type Low Quad Flat Package Low Quad Flat Package Abbreviation LQFP LQFP Designator LK LH Case No. 917A 840F Document No. 98ASS23237W 98ASS23234W
The below table details the various packages available.
5.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 21. For the latest available drawings please visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 31
Package Information
4X
4X 20 TIPS
–X–
X= L, M, N
0.20 (0.008) H L–M N
80 1 61 60
0.20 (0.008) T L–M N C L AB AB –M– VIEW Y B V J
PLATING
P
G
–L–
3X
VIEW Y B1
F
V1
BASE METAL
20 21 40
41
–N– A1 S1 A S
0.13 (0.005)
SECTION AB–AB
ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K P R1 S S1 U V V1 W Z 0 01 02 MILLIMETERS MIN MAX 14.00 BSC 7.00 BSC 14.00 BSC 7.00 BSC ––– 1.60 0.04 0.24 1.30 1.50 0.22 0.38 0.40 0.75 0.17 0.33 0.65 BSC 0.09 0.27 0.50 REF 0.325 BSC 0.10 0.20 16.00 BSC 8.00 BSC 0.09 0.16 16.00 BSC 8.00 BSC 0.20 REF 1.00 REF 0 10 0 ––– 9 14 INCHES MIN MAX 0.551 BSC 0.276 BSC 0.551 BSC 0.276 BSC ––– 0.063 0.002 0.009 0.051 0.059 0.009 0.015 0.016 0.030 0.007 0.013 0.026 BSC 0.004 0.011 0.020 REF 0.013 REF 0.004 0.008 0.630 BSC 0.315 BSC 0.004 0.006 0.630 BSC 0.315 BSC 0.008 REF 0.039 REF 0 10 0 ––– 9 14
C –H– –T–
SEATING PLANE
8X
2
0.10 (0.004) T
VIEW AA (W) C2 0.05 (0.002)
S
1
2X R R1
0.25 (0.010)
GAGE PLANE
(K) C1 E (Z)
VIEW AA
DATE 09/21/95
CASE 917A-02 ISSUE C
Figure 23. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)
MCF51QE128 Series Data Sheet, Rev. 7 32 Freescale Semiconductor
ÍÇÍÇ Í ÍÇÇÍ ÍÇÇ ÍÍ
D U
M
T L–M
S
N
S
Package Information
Figure 24. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 33
Package Information
Figure 25. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 2 of 3
MCF51QE128 Series Data Sheet, Rev. 7 34 Freescale Semiconductor
Package Information
Figure 26. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 3 of 3
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 35
Product Documentation
6
Product Documentation
Reference Manual (MCF51QE128RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
Find the most current versions of all documents at: http://www.freescale.com
7
Revision History
http://www.freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. Table 22. Revision History
Revision Date Description of Changes Table 8: Changed Condition entires in specs #6 (VIH) and #7 (VIL) from VDD ≥ 1.8V to VDD > 2.7V and VDD ≤ 1.8V to VDD > 1.8V. Table 8: Changed VDD rising and VDD falling min/typ/max specs in row #19 (Low-voltage warning threshold—high range) from 2.35, 2.40, and 2.50 to 2.36, 2.46, and 2.56 respectively. Added information about the MCF51QE32 device. Changed the SRAM size for the MCF51QE64 device (was 4 Kbytes, is 8 Kbytes). Corrected the number of ADC channels for the MCF51QE64 device (was 22, is 20). Corrected the number of ADC channels for the 64-pin package of the MCF51QE64 device (was 22, is 20). Changed ACMP electricals, VAIO specification’s test category from P to C. Updated the tables Thermal Characteristics, DC Characteristics, Supply Current Characteristics, XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient), ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient), Control Timing, and Analog Comparator Electrical Specifications, 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ACMP and ADC off, All Other Modules Enabled), Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V), and Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25°C) Updated the table Thermal Characteristics Updated the row corresponding to Num 18 in the table DC Characteristics Updated the tables MCF51QE128 Series Features by MCU and Package, DC Characteristics, Supply Current Characteristics, Thermal Characteristics, Control Timing, and Ordering Information Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled), Deviation of DCO Output Across Temperature at VDD = 3.0 V, and Deviation of DCO Output Across VDD at 25×C Updated the Stop2 and Stop3 mode supply current in the Supply Current Characteristics table. Replaced the stop mode adders section from the Supply Current Characteristics with its own Stop Mode Adders table with new specifications.
3
25 Jun 2007
4
17 Sep 2007
5
28 May 2008
6
24 Jun 2008
7
14 Oct 2008
MCF51QE128 Series Data Sheet, Rev. 7 36 Freescale Semiconductor
Revision History
MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 37
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Rev. 7 10/2008
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