MCF5213_07

Freescale Semiconductor Data Sheet Document Number: MCF5213EC Rev. 3, 05/2007 MCF5213 MCF5213 ColdFire Microcontroller Supports MCF5213, MCF5212, & MCF5211 The MCF5213 is a member of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This document provides an overview of the 32-bit MCF5213 microcontroller, focusing on its highly integrated and diverse feature set. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 256 Kbytes of flash memory and 32 Kbytes of static random access memory (SRAM). On-chip modules include: • V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at 80 MHz running from internal flash memory with Multiply Accumulate (MAC) Unit and hardware divider • FlexCAN controller area network (CAN) module • Three universal asynchronous/synchronous receiver/transmitters (UARTs) • Inter-integrated circuit (I2C™) bus controller • Queued serial peripheral interface (QSPI) module • Eight-channel 12-bit fast analog-to-digital converter (ADC) • Four-channel direct memory access (DMA) controller • Four 32-bit input capture/output compare timers with DMA support (DTIM) • Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), and pulse accumulation • Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer • Two 16-bit periodic interrupt timers (PITs) • Programmable software watchdog timer • Interrupt controller capable of handling 57 sources • Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL) • Test access/debug port (JTAG, BDM) LQFP–64 10 mm x 10 mm QFN–64 9 mm x 9 mm MAPBGA–81 10 mm x 10 mm LQFP–100 14 mm x 14 mm This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. Table of Contents 1 MCF5213 Family Configurations . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .21 1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .21 1.8 I2C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.9 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.10 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.11 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.12 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .23 1.13 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .23 1.14 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .23 1.15 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .24 1.16 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .25 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28 2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .30 2.5 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .31 2.7 Clock Source Electrical Specifications . . . . . . . . . . . . .32 2.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .33 2.9 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.10 I2C Input/Output Timing Specifications . . . . . . . . . . . . .35 2.11 Analog-to-Digital Converter (ADC) Parameters . . . . . .36 2.12 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . . .37 2.13 DMA Timers Timing Specifications . . . . . . . . . . . . . . . .38 2.14 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .38 2.15 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . .39 2.16 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .41 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .43 3.1 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .43 3.2 64 QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.3 81 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . .50 3.4 100-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .52 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Figure 8. Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . . Figure 9. QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . Figure 11.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . Figure 12.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . Figure 13.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . . Figure 15.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 37 38 39 40 40 40 41 42 List of Tables Table 1. MCF5213 Family Configurations . . . . . . . . . . . . . . . . . . 3 Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 12 Table 3. Pin Functions by Primary and Alternate Purpose . . . . 16 Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Mode Selection Signals . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 21 Table 9. Queued Serial Peripheral Interface (QSPI) Signals. . . 21 Table 10.I2C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 15.PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 24 Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 25 Table 19.Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 26 Table 20.Current Consumption in Low-Power Mode, . . . . . . . . . 27 Table 21.Typical Active Current Consumption Specifications. . . 28 Table 22.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 28 Table 23.SGFM Flash Program and Erase Characteristics . . . . 30 Table 24.SGFM Flash Module Life Characteristics . . . . . . . . . . 30 Table 25.ESD Protection Characteristics, . . . . . . . . . . . . . . . . . 31 Table 26.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 31 Table 27.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32 Table 28.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 29.Reset and Configuration Override Timing . . . . . . . . . . 34 Table 30.I2C Input Timing Specifications between I2C_SCL and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 31.I2C Output Timing Specifications between I2C_SCL and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 32.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 33.Timer Module AC Timing Specifications . . . . . . . . . . . 38 Table 34.QSPI Modules AC Timing Specifications. . . . . . . . . . . 38 Table 35.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 39 Table 36.Debug AC Timing Specification . . . . . . . . . . . . . . . . . . 41 Table 37.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2 3 4 List of Figures Figure 1. MCF5213 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. 100 LQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . 13 Figure 3. 81 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . . 14 Figure 4. 64 LQFP and 64 QFN Pin Assignments . . . . . . . . . . . 15 Figure 5. GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6. RSTI and Configuration Override Timing . . . . . . . . . . 34 Figure 7. I2C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 36 MCF5213 ColdFire Microcontroller, Rev. 3 2 Freescale Semiconductor MCF5213 Family Configurations 1 MCF5213 Family Configurations Table 1. MCF5213 Family Configurations Module ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit) System Clock Performance (Dhrystone 2.1 MIPS) Flash / Static RAM (SRAM) Interrupt Controller (INTC) Fast Analog-to-Digital Converter (ADC) FlexCAN 2.0B Module Four-channel Direct-Memory Access (DMA) Watchdog Timer Module (WDT) Programmable Interval Timer Module (PIT) Four-Channel General-Purpose Timer 32-bit DMA Timers QSPI UARTs I 2C 5211 5212 5213 • • 66, 80 MHz • 63 128/16 Kbytes up to 76 256/32 Kbytes • • See note1 • • — • • • • • 2 3 4 • • 2 3 4 • • 2 3 4 • 3 • 3 • 3 • 8 • 8 • 8 PWM General Purpose I/O Module (GPIO) Chip Configuration and Reset Controller Module Background Debug Mode (BDM) JTAG - IEEE 1149.1 Test Access Port2 Package • • • • 64 LQFP 64 QFN 81 MAPBGA • • • • 64 LQFP 81 MAPBGA • • • • 81 MAPBGA 100 LQFP 1 2 FlexCAN is available on the MCF5211 only in the 64 QFN package. The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller packages. Figure 1 shows a top-level block diagram of the MCF5213. Package options for this family are described later in this document. MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 3 MCF5213 Family Configurations EzPD EzPQ EzPCK EzPort EzPCS GPTn Interrupt Controller PADI – Pin Muxing QSPI_DIN, QSPI_DOUT QSPI_CLK, QSPI_CSn Arbiter 4 CH DMA UART 0 UART 1 UART 2 IC 2 QSPI UTXDn URXDn URTSn UCTSn DTINn/DTOUTn CANRX CANTX PWMn To/From PADI SWT DTIM 0 DTIM 1 DTIM 2 DTIM 3 JTAG_EN MUX V2 ColdFire CPU JTAG TAP IFP OEP MAC PMM AN[7:0] ADC 32 Kbytes SRAM (4K×16)×4 VSTBY 256 Kbytes Flash (32K×16)×4 PORTS (GPIO) CIM RSTI RSTO VRH VRL FlexCAN Edge Port PLL OCO CLKGEN PIT0 PIT1 GPT PWM EXTAL XTAL CLKOUT CLKMOD0 CLKMOD1 To/From Interrupt Controller Figure 1. MCF5213 Block Diagram 1.1 Features This document contains information on a new product under development. Freescale reserves the right to change or discontinue this product without notice. Specifications and information herein are subject to change without notice. 1.1.1 Feature Overview The MCF5213 family includes the following features: MCF5213 ColdFire Microcontroller, Rev. 3 4 Freescale Semiconductor MCF5213 Family Configurations • • • • • • Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data paths on-chip — Up to 80 MHz processor core frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+) — Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 → 32 or 32×32 → 32 operations — Illegal instruction decode that allows for 68-Kbyte emulation support System debug support — Real-time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging (DEBUG_B+) — Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or 2-level trigger On-chip memories — 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support — 256 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses Power management — Fully static operation with processor sleep and whole chip stop modes — Rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used FlexCAN 2.0B module — Based on and includes all existing features of the Freescale TouCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard data and remote frames (up to 109 bits long) – Extended data and remote frames (up to 127 bits long) – Zero to eight bytes data length – Programmable bit rate up to 1 Mbit/sec — Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages — Unused MB space can be used as general purpose RAM space — Listen-only mode capability — Content-related addressing — No read/write semaphores — Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15 — Programmable transmit-first scheme: lowest ID or lowest buffer number — Time stamp based on 16-bit free-running timer — Global network time, synchronized by a specific message — Maskable interrupts Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic with maskable interrupts — DMA support — Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity — Up to two stop bits in 1/16 increments MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 5 MCF5213 Family Configurations • • • • • • — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers I2C module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers Fast analog-to-digital converter (ADC) — Eight analog input channels — 12-bit resolution — Minimum 1.125 μs conversion time — Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit — Unused analog channels can be used as digital I/O Four 32-bit timers with DMA support — 12.5 ns resolution at 80 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input capture capability with programmable trigger edge on input pin — Output compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or output compare — DMA trigger capability on input capture or output compare Four-channel general purpose timer — 16-bit architecture — Programmable prescaler — Output pulse-widths variable from microseconds to seconds — Single 16-bit input pulse accumulator — Toggle-on-overflow feature for pulse-width modulator (PWM) generation — One dual-mode pulse accumulation channel Pulse-width modulation timer — Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution — Programmable period and duty cycle — Programmable enable/disable for each channel — Software selectable polarity for each channel — Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached (PWM counter reaches zero) or when the channel is disabled. MCF5213 ColdFire Microcontroller, Rev. 3 6 Freescale Semiconductor MCF5213 Family Configurations • • • • • • • — Programmable center or left aligned outputs on individual channels — Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies — Emergency shutdown Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down Software watchdog timer — 32-bit counter — Low-power mode support Clock generation features — One to 48 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference options — Trimmed relaxation oscillator — Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable from 1 to 8 — System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator — Low power modes supported — 2n (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation Interrupt controller — Uniquely programmable vectors for all interrupt sources — Fully programmable level and priority for all peripheral interrupt sources — Seven external interrupt signals with fixed level and priority — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low-power modes DMA controller — Four fully programmable channels — Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4×32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4) Reset — Separate reset in and reset out signals — Seven sources of reset: – Power-on reset (POR) – External – Software – Watchdog – Loss of clock – Loss of lock – Low-voltage detection (LVD) — Status flag indication of source of last reset Chip integration module (CIM) MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 7 MCF5213 Family Configurations • • — System configuration during reset — Selects one of six clock modes — Configures output pad drive strength — Unique part identification number and part revision number General purpose I/O interface — Up to 56 bits of general purpose I/O — Bit manipulation supported via set/clear functions — Programmable drive strengths — Unused peripheral pins may be used as extra GPIO JTAG support for system level board testing 1.1.2 V2 Core Overview The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF5213 core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16×16 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The MAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost. 1.1.3 Integrated Debug Module The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided on 100-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF5213 implements revision B+ of the ColdFire Debug Architecture. The MCF5213’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging. To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF5213 includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111). The full debug/trace interface is available only on the 100-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal. MCF5213 ColdFire Microcontroller, Rev. 3 8 Freescale Semiconductor MCF5213 Family Configurations 1.1.4 JTAG The MCF5213 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The MCF5213 implementation can: • • • • • Perform boundary-scan operations to test circuit board electrical continuity Sample MCF5213 system pins during operation and transparently shift out the result in the boundary scan register Bypass the MCF5213 for a given circuit board test by effectively reducing the boundary-scan register to a single bit Disable the output drive to pins during circuit-board testing Drive output pins to stable levels 1.1.5 1.1.5.1 On-Chip Memories SRAM The dual-ported SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. 1.1.5.2 Flash Memory The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local bus. The CFM is constructed with four banks of 32-Kbyte×16-bit flash memory arrays to generate 256 Kbytes of 32-bit flash memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips. 1.1.6 Power Management The MCF5213 incorporates several low-power modes of operation entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip falls below the standby battery voltage. MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 9 MCF5213 Family Configurations 1.1.7 FlexCAN The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers. 1.1.8 UARTs The MCF5213 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions. 1.1.9 I2C Bus The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. 1.1.10 QSPI The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers. 1.1.11 Fast ADC The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing. The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly until manually stopped. The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled. During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously. Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions. 1.1.12 DMA Timers (DTIM0–DTIM3) There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the MCF5213. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers. MCF5213 ColdFire Microcontroller, Rev. 3 10 Freescale Semiconductor MCF5213 Family Configurations 1.1.13 General Purpose Timer (GPT) The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, channel three, can be configured as a pulse accumulator. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator. 1.1.14 Periodic Interrupt Timers (PIT0 and PIT1) The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running down-counter. 1.1.15 Pulse-Width Modulation (PWM) Timers The MCF5213 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels. 1.1.16 Software Watchdog Timer The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. 1.1.17 Phase-Locked Loop (PLL) The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS. 1.1.18 Interrupt Controller (INTC) The MCF5213 has a single interrupt controller that supports up to 63 interrupt sources. There are 56 programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for software interrupt requests. 1.1.19 DMA Controller The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events. MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 11 MCF5213 Family Configurations 1.1.20 Reset The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset: • • • • • • • External reset input Power-on reset (POR) Watchdog timer Phase locked-loop (PLL) loss of lock PLL loss of clock Software Low-voltage detector (LVD) Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin. 1.1.21 GPIO Nearly all pins on the MCF5213 have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins. 1.1.22 Part Numbers and Packaging This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office for up-to-date RoHS information. Table 2. Orderable Part Number Summary Freescale Part Number MCF5211CAE66 MCF5211CEP66 MCF5211LCEP66 MCF5211LCVM66 MCF5211LCVM80 MCF5212CAE66 MCF5212LCVM66 MCF5212LCVM80 MCF5213CAF66 MCF5213CAF80 MCF5213LCVM66 MCF5213LCVM80 Description MCF5211 ColdFire Microcontroller MCF5211 ColdFire Microcontroller, FlexCAN MCF5211 ColdFire Microcontroller MCF5211 ColdFire Microcontroller MCF5211 ColdFire Microcontroller MCF5212 ColdFire Microcontroller MCF5212 ColdFire Microcontroller MCF5212 ColdFire Microcontroller MCF5213 ColdFire Microcontroller, FlexCAN MCF5213 ColdFire Microcontroller, FlexCAN MCF5213 ColdFire Microcontroller, FlexCAN MCF5213 ColdFire Microcontroller, FlexCAN Speed 66 MHz 66 MHz 66 MHz 66 MHz 80 MHz 66 MHz 66 MHz 80 MHz 66 MHz 80 MHz 66 MHz 80 MHz Package 64 LQFP 64 QFN 64 QFN 81 MAPBGA 81 MAPBGA 64 LQFP 81 MAPBGA 81 MAPBGA 100 LQFP 100 LQFP 81 MAPBGA 81 MAPBGA Temperature -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C MCF5213 ColdFire Microcontroller, Rev. 3 12 Freescale Semiconductor MCF5213 Family Configurations Figure 2 shows the pinout configuration for the 100 LQFP. URXD1 UTXD1 UCTS1 RSTO RSTI IRQ7 IRQ6 VDD VSS IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 ALLPST DSCLK DDATA3 DDATA2 VSS VDD DSO DSI DDATA1 DDATA0 BKPT VDD VDD VSS URTS1 TEST UCTS0 URXD0 UTXD0 URTS0 SCL SDA QSPI_CS3 QSPI_CS2 VDD VSS QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS1 QSPI_CS0 RCON VDD VDD VSS VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS VDDPLL EXTAL XTAL VSSPLL PST3 PST2 VDD VSS PST1 PST0 PSTCLK PWM7 GPT3 GPT2 PWM5 GPT1 GPT0 VDD VSS VSTBY AN4 AN5 AN6 AN7 Freescale Semiconductor JTAG_EN UCTS2 URXD2 UTXD2 URTS2 DTIN2 DTIN3 PWM3 VDD VSS DTIN0 DTIN1 PWM1 CLKMOD1 CLKMOD0 VDD VSS AN0 AN1 AN2 AN3 VSSA VRL VRH VDDA 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 2. 100 LQFP Pin Assignments MCF5213 ColdFire Microcontroller, Rev. 3 13 MCF5213 Family Configurations Figure 3 shows the pinout configuration for the 81 MAPBGA. 1 A VSS 2 UTXD1 3 RSTI 4 IRQ5 5 IRQ3 6 ALLPST 7 TDO 8 TMS 9 VSS B URTS1 URXD1 RSTO IRQ6 IRQ2 TRST TDI VDDPLL EXTAL C UCTS0 TEST UCTS1 IRQ7 IRQ4 IRQ1 TCLK VSSPLL XTAL D URXD0 UTXD0 URTS0 VSS VDD VSS PWM7 GPT3 GPT2 E SCL SDA VDD VDD VDD VDD VDD PWM5 GPT1 F QSPI_CS3 QSPI_CS2 QSPI_DIN VSS VDD VSS GPT0 VSTBY AN4 G QSPI_DOUT QSPI_CLK RCON DTIN1 CLKMOD0 AN2 AN3 AN5 AN6 H QSPI_CS0 QSPI_CS1 DTIN3 DTIN0 CLKMOD1 AN1 VSSA VDDA AN7 J VSS JTAG_EN DTIN2 PWM3 PWM1 AN0 VRL VRH VSSA Figure 3. 81 MAPBGA Pin Assignments MCF5213 ColdFire Microcontroller, Rev. 3 14 Freescale Semiconductor MCF5213 Family Configurations Figure 4 shows the pinout configuration for the 64 LQFP and 64 QFN. VSS URXD1 UTXD1 UCTS1 RSTO RSTI IRQ7 IRQ4 IRQ1 ALLPST DSCLK VSS VDD DSO DSI BKPT VDD URTS1 TEST UCTS0 URXD0 UTXD0 URTS0 SCL SDA VDD VSS QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS0 RCON 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin Packages 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDPLL EXTAL XTAL VSSPLL PSTCLK GPT3 GPT2 GPT1 GPT0 VDD VSS VSTBY AN4 AN5 AN6 AN7 Figure 4. 64 LQFP and 64 QFN Pin Assignments Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin. MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 15 JTAG_EN DTIN2 DTIN3 VDD VSS DTIN0 DTIN1 CLKMOD0 AN0 AN1 AN2 AN3 VSSA VRL VRH VDDA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MCF5213 Family Configurations 16 Pin Group ADC Primary Function AN7 AN6 AN5 AN4 AN3 AN2 MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor AN1 AN0 SYNCA SYNCB VDDA VSSA VRH VRL Clock Generation EXTAL XTAL VDDPLL VSSPLL Debug Data ALLPST DDATA[3:0] PST[3:0] I 2C 3 3 Table 3. Pin Functions by Primary and Alternate Purpose Secondary Function — — — — — — — — — — — — — — — — — — — — — CANTX4 CANRX3 Tertiary Function — — — — — — — — — — — — — — — — — — — — — UTXD2 URXD2 Quaternary Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO — — — — — — — — — — — GPIO GPIO GPIO GPIO Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 1 Control Low Low Low Low Low Low Low Low N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A High High High PDSR[0] PDSR[0] FAST FAST FAST FAST FAST FAST FAST FAST N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FAST FAST FAST PSRR[0] PSRR[0] — — — — — — — — — — — — — — — — — — — — — pull-up5 pull-up5 Pin on 100 LQFP 51 52 53 54 46 45 44 43 — — 50 47 49 48 73 72 74 71 86 84,83,78,77 70,69,66,65 10 11 Pin on 81 MAPBGA H9 G9 G8 F9 G7 G6 H6 J6 — — H8 H7, J9 J8 J7 B9 C9 B8 C8 A6 — — E1 E2 Pin on 64 LQFP/QFN 33 34 35 36 28 27 26 25 — — 32 29 31 30 47 46 48 45 55 — — 8 9 SCL SDA Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group Interrupts Primary Function IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 MCF5213 ColdFire Microcontroller, Rev. 3 IRQ1 JTAG/BDM JTAG_EN TCLK/ PSTCLK TDI/DSI TDO/DSO TMS /BKPT TRST /DSCLK Mode Selection7 CLKMOD0 CLKMOD1 RCON/ EZPCS PWM PWM7 PWM5 PWM3 PWM1 Secondary Function — — — — — — SYNCA — CLKOUT — — — — — — — — — — — Tertiary Function — — — — — — PWM1 — — — — — — — — — — — — — Quaternary Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO — — — — — — — — — GPIO GPIO GPIO GPIO Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 Low Low Low Low Low Low High N/A High N/A High N/A N/A N/A N/A N/A PDSR[31] PDSR[30] PDSR[29] PDSR[28] FAST FAST FAST FAST FAST FAST FAST N/A FAST N/A FAST N/A N/A N/A N/A N/A PSRR[31] PSRR[30] PSRR[29] PSRR[28] pull-up pull-up pull-up pull-up pull-up pull-up pull-up5 pull-down pull-up6 pull-up6 — pull-up6 pull-up6 pull-down7 pull-down7 pull-up — — — — Pin on 100 LQFP 95 94 91 90 89 88 87 26 64 79 80 76 85 40 39 21 63 60 33 38 Pin on 81 MAPBGA C4 B4 A4 C5 A5 B5 C6 J2 C7 B7 A7 A8 B6 G5 H5 G3 D7 E8 J4 J5 Pin on 64 LQFP/QFN 58 — — 57 — — 56 17 44 50 51 49 54 24 — 16 MCF5213 Family Configurations — — — — Freescale Semiconductor 17 Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group QSPI Primary Function QSPI_DIN/ EZPD QSPI_DOUT/ EZPQ QSPI_CLK/ EZPCK QSPI_CS3 QSPI_CS2 QSPI_CS1 QSPI_CS0 Reset 9 MCF5213 Family Configurations 18 MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor RSTI RSTO Test Timers, 16-bit TEST GPT3 GPT2 GPT1 GPT0 Timers, 32-bit DTIN3 DTIN2 DTIN1 DTIN0 UART 0 UCTS0 URTS0 URXD0 UTXD0 Secondary Function CANRX4 CANTX4 SCL SYNCA — — SDA — — — — — — — DTOUT3 DTOUT2 DTOUT1 DTOUT0 CANRX CANTX — — Tertiary Function URXD1 UTXD1 URTS1 SYNCB — — UCTS1 — — — PWM7 PWM5 PWM3 PWM1 PWM6 PWM4 PWM2 PWM0 — — — — Quaternary Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO — — — GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 PDSR[2] PDSR[1] PDSR[3] PDSR[7] PDSR[6] PDSR[5] PDSR[4] N/A high N/A PDSR[23] PDSR[22] PDSR[21] PDSR[20] PDSR[19] PDSR[18] PDSR[17] PDSR[16] PDSR[11] PDSR[10] PDSR[9] PDSR[8] PSRR[2] PSRR[1] PSRR[3] PSRR[7] PSRR[6] PSRR[5] PSRR[4] N/A FAST N/A PSRR[23] PSRR[22] PSRR[21] PSRR[20] PSRR[19] PSRR[18] PSRR[17] PSRR[16] PSRR[11] PSRR[10] PSRR[9] PSRR[8] — — pull-up8 — — — pull-up8 pull-up9 — pull-down pull-up 10 Pin on 100 LQFP 16 17 18 12 13 19 20 96 97 5 62 61 59 58 32 31 37 36 6 9 7 8 Pin on 81 MAPBGA F3 G1 G2 F1 F2 H2 H1 A3 B3 C2 D8 D9 E9 F7 H3 J3 G4 H4 C1 D3 D1 D2 Pin on 64 LQFP/QFN 12 13 14 — — — 15 59 60 3 43 42 41 40 19 18 23 22 4 7 5 6 pull-up10 pull-up10 pull-up — — — — — — — — 10 Table 3. Pin Functions by Primary and Alternate Purpose (continued) Pin Group UART 1 Primary Function UCTS1 URTS1 URXD1 UTXD1 UART 2 UCTS2 URTS2 MCF5213 ColdFire Microcontroller, Rev. 3 URXD2 UTXD2 FlexCAN CANRX 4,11 Freescale Semiconductor 1 Secondary Function SYNCA SYNCB — — — — — — Tertiary Function URXD2 UTXD2 — — — — — — Quaternary Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 PDSR[15] PDSR[14] PDSR[13] PDSR[12] PDSR[27] PDSR[26] PDSR[25] PDSR[24] N/A N/A PSRR[15] PSRR[14] PSRR[13] PSRR[12] PSRR[27] PSRR[26] PSRR[25] PSRR[24] N/A N/A N/A N/A — — — — — — — — — — — — Pin on 100 LQFP 98 4 100 99 27 30 28 29 — — 55 1,2,14,22, 23,34,41, 57,68,81,93 Pin on 81 MAPBGA C3 B1 B2 A2 — — — — — — F8 Pin on 64 LQFP/QFN 61 2 63 62 — — — — — — 37 CANTX4,11 VSTBY VDD VSTBY VDD — — — — — — N/A N/A D5,E3–E7, 1,10,20,39,5 F5 2 11,21,38, 53,64 VSS VSS — — — N/A N/A — 3,15,24,25,3 A1,A9,D4,D 5,42,56, 6,F4,F6,J1 67,75,82,92 The PDSR and PSSR registers are described in the General Purpose I/O chapter. All programmable signals default to 2 mA drive and FAST slew rate in normal (single-chip) mode. 2 All signals have a pull-up in GPIO mode. 3 These signals are multiplexed on other pins. 4 The multiplexed CANTX and CANRX signals are not available on the MCF5211 or MCF5212. 5 For primary and GPIO functions only. 6 Only when JTAG mode is enabled. 7 CLKMOD0 and CLKMOD1 have internal pull-down resistors; however, the use of external resistors is very strongly recommended. 8 For secondary and GPIO functions only. 9 RSTI has an internal pull-up resistor; however, the use of an external resistor is very strongly recommended. 10 For GPIO function. Primary Function has pull-up control within the GPT module. 11 CANTX and CANRX are secondary functions only. MCF5213 Family Configurations 19 MCF5213 Family Configurations 1.2 Reset Signals Table 4. Reset Signals Signal Name Reset In Reset Out Abbreviation RSTI RSTO Function Primary reset input to the device. Asserting RSTI for at least 8 CPU clock cycles immediately resets the CPU and peripherals. Driven low for 1024 CPU clocks after the reset source has deasserted. I/O I O Table 4 describes signals used to reset the chip or as a reset indication. 1.3 PLL and Clock Signals Table 5. PLL and Clock Signals Signal Name External Clock In Crystal Clock Out Abbreviation EXTAL XTAL CLKOUT Function Crystal oscillator or external clock input except when the on-chip relaxation oscillator is used. Crystal oscillator output except when CLKMOD1=1, then sampled as part of the clock mode selection mechanism. This output signal reflects the internal system clock. I/O I O O Table 5 describes signals used to support the on-chip clock generation circuitry. 1.4 Mode Selection Table 6. Mode Selection Signals Signal Name Clock Mode Selection Reset Configuration Abbreviation Function I/O I Table 6 describes signals used in mode selection; Table 7 describes the particular clocking modes. CLKMOD[1:0] Selects the clock boot mode. RCON The Serial Flash Programming mode is entered by asserting the RCON pin (with the TEST pin negated) as the chip comes out of reset. During this mode, the EzPort has access to the flash memory which can be programmed from an external device. Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions. Test TEST I Table 7. Clocking Modes CLKMOD[1:0] 00 00 01 10 10 11 XTAL 0 1 N/A 0 1 N/A Configure the clock mode. PLL disabled, clock driven by external oscillator PLL disabled, clock driven by on-chip oscillator PLL disabled, clock driven by crystal PLL in normal mode, clock driven by external oscillator PLL in normal mode, clock driven by on-chip oscillator PLL in normal mode, clock driven by crystal MCF5213 ColdFire Microcontroller, Rev. 3 20 Freescale Semiconductor MCF5213 Family Configurations 1.5 External Interrupt Signals Table 8. External Interrupt Signals Signal Name External Interrupts Abbreviation IRQ[7:1] External interrupt sources. Function I/O I Table 8 describes the external interrupt signals. 1.6 Queued Serial Peripheral Interface (QSPI) Table 9. Queued Serial Peripheral Interface (QSPI) Signals Signal Name QSPI Synchronous Serial Output QSPI Synchronous Serial Data Input QSPI Serial Clock Abbreviation Function I/O O I O O Table 9 describes the QSPI signals. QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be driven on the rising or falling edge of QSPI_CLK. QSPI_DIN QSPI_CLK Provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPI_CLK. Provides the serial clock from the QSPI. The polarity and phase of QSPI_CLK are programmable. Synchronous Peripheral QSPI_CS[3:0] QSPI peripheral chip select; can be programmed to be active high or Chip Selects low. 1.7 I2C I/O Signals Table 10. I2C I/O Signals Signal Name Serial Clock Abbreviation SCL Function Open-drain clock signal for the for the I2C interface. When the bus is In master mode, this clock is driven by the I2C module; when the bus is in slave mode, this clock becomes the clock input. Open-drain signal that serves as the data input/output for the I2C interface. I/O I/O Table 10 describes the I2C serial interface module signals. Serial Data SDA I/O MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 21 MCF5213 Family Configurations 1.8 UART Module Signals Table 11. UART Module Signals Signal Name Transmit Serial Data Output Abbreviation UTXDn Function Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, LSB first, on this pin at the falling edge of the serial clock source. Receiver serial data inputs for the UART modules. Data is received on this pin LSB first. When the UART clock is stopped for power-down mode, any transition on this pin restarts the clock. Indication to the UART modules that they can begin data transmission. Automatic request-to-send outputs from the UART modules. This signal can also be configured to be asserted and negated as a function of the RxFIFO level. I/O O Table 11 describes the UART module signals. Receive Serial Data Input Clear-to-Send Request-to-Send URXDn I UCTSn URTSn I O 1.9 DMA Timer Signals Table 12. DMA Timer Signals Signal Name DMA Timer Input DMA Timer Output Abbreviation DTIN DTOUT Function Event input to the DMA timer modules. Programmable output from the DMA timer modules. I/O I O Table 12 describes the signals of the four DMA timer modules. 1.10 ADC Signals Table 13. ADC Signals Signal Name Analog Inputs Analog Reference Abbreviation AN[7:0] VRH VRL Analog Supply VDDA VSSA ADC Sync Inputs SYNCA / SYNCB These signals can initiate an analog-to-digital conversion process. Isolate the ADC circuitry from power supply noise. Function Inputs to the analog-to-digital converter. Reference voltage high and low inputs. I/O I I I — — I Table 13 describes the signals of the Analog-to-Digital Converter. MCF5213 ColdFire Microcontroller, Rev. 3 22 Freescale Semiconductor MCF5213 Family Configurations 1.11 General Purpose Timer Signals Table 14. GPT Signals Table 14 describes the general purpose timer signals. Signal Name General Purpose Timer Input/Output Abbreviation GPT[3:0] Function Inputs to or outputs from the general purpose timer module. I/O I/O 1.12 Pulse Width Modulator Signals Table 15. PWM Signals Signal Name Abbreviation PWM[7:0] Function Pulse width modulated output for PWM channels. I/O O Table 15 describes the PWM signals. PWM Output Channels 1.13 Debug Support Signals Table 16. Debug Support Signals Signal Name JTAG Enable Test Reset Test Clock Test Mode Select Test Data Input Test Data Output Abbreviation JTAG_EN TRST TCLK TMS TDI TDO Function Select between debug module and JTAG signals at reset. This active-low signal is used to initialize the JTAG logic asynchronously. Used to synchronize the JTAG logic. Used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCLK. Serial input for test instructions and data. TDI is sampled on the rising edge of TCLK. Serial output for test instructions and data. TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK. Development Serial Clock - Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state. Breakpoint - Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. I/O I I I I I O These signals are used as the interface to the on-chip JTAG controller and the BDM logic. Development Serial Clock DSCLK I Breakpoint BKPT I MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 23 MCF5213 Family Configurations Table 16. Debug Support Signals (continued) Signal Name Development Serial Input Development Serial Output Debug Data Abbreviation DSI Function Development Serial Input - Internally synchronized input that provides data input for the serial communication port to the debug module, after the DSCLK has been seen as high (logic 1). Development Serial Output - Provides serial output communication for debug module responses. DSO is registered internally. The output is delayed from the validation of DSCLK high. Display captured processor data and breakpoint status. The CLKOUT signal can be used by the development system to know when to sample DDATA[3:0]. Processor Status Clock - Delayed version of the processor clock. Its rising edge appears in the center of valid PST and DDATA output. PSTCLK indicates when the development system should sample PST and DDATA values. If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and PST and DDATA outputs from toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing CSR[PCD], although the external development systems must resynchronize with the PST and DDATA outputs. PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during system reset exception processing. Indicate core status. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. The CLKOUT signal can be used by the development system to know when to sample PST[3:0]. Logical AND of PST[3:0]. The CLKOUT signal can be used by the development system to know when to sample ALLPST. I/O I DSO O DDATA[3:0] O Processor Status Clock PSTCLK O Processor Status Outputs PST[3:0] O All Processor Status Outputs ALLPST O 1.14 EzPort Signal Descriptions Table 17. EzPort Signal Descriptions Signal Name EzPort Clock EzPort Chip Select EzPort Serial Data In EzPort Serial Data Out Abbreviation EZPCK EZPCS EZPD EZPQ Function Shift clock for EzPort transfers. Chip select for signalling the start and end of serial transfers. EZPD is sampled on the rising edge of EZPCK. EZPQ transitions on the falling edge of EZPCK. I/O I I I O Table contains a list of EzPort external signals. MCF5213 ColdFire Microcontroller, Rev. 3 24 Freescale Semiconductor Electrical Characteristics 1.15 Power and Ground Pins Table 18. Power and Ground Pins Signal Name PLL Analog Supply Abbreviation VDDPLL, VSSPLL VDD VSS Function Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply. These pins supply positive power to the core logic. This pin is the negative supply (ground) to the chip. The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. Positive Supply Ground 2 Electrical Characteristics NOTE The parameters specified in this data sheet supersede any values found in the module specifications. This section contains electrical specification tables and reference timing diagrams for the MCF5213 microcontroller unit, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 25 Electrical Characteristics 2.1 Maximum Ratings Table 19. Absolute Maximum Ratings1, 2 Rating Supply voltage Clock synthesizer supply voltage RAM standby supply voltage Digital input voltage 3 EXTAL pin voltage XTAL pin voltage Instantaneous maximum current Single pin limit (applies to all pins)4, 5 Operating temperature range (packaged) Storage temperature range 1 Symbol VDD VDDPLL VSTBY VIN VEXTAL VXTAL IDD TA (TL - TH) Tstg Value –0.3 to +4.0 –0.3 to +4.0 –0.3 to +4.0 –0.3 to +4.0 0 to 3.3 0 to 3.3 25 –40 to 85 –65 to 150 Unit V V V V V V mA °C °C 2 3 4 5 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or VDD). Input must be current limited to the IDD value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and VDD. The power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in the external power supply going out of regulation. Ensure that the external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power (e.g., no clock). MCF5213 ColdFire Microcontroller, Rev. 3 26 Freescale Semiconductor Electrical Characteristics 2.2 Current Consumption Table 20. Current Consumption in Low-Power Mode1,2 Mode Stop mode 3 (Stop 11)4 Stop mode 2 (Stop 10) Stop mode 1 (Stop 01) 4 8MHz (Typ)3 16MHz (Typ)2 64MHz (Typ)2 80MHz (Typ)2 0.13 2.29 2.80 2.80 11.12 12.40 3.08 3.08 20.23 22.74 4.76 4.76 30.17 39.92 5.38 5.39 33.36 45.47 Units mA 4,5 Stop mode 0 (Stop 00)4 Wait / Doze Run 1 2 All values are measured with a 3.30 V power supply Refer to the Power Management chapter in the MCF5213 Reference Manual for more information on low-power modes. 3 CLKOUT and all peripheral clocks except UART0 and CFM off before entering low power mode. CLKOUT is disabled. All code executed from flash memory. Code run from SRAM reduces power consumption further. Tests performed at room temperature. 4 See the description of the Low-Power Control Register (LPCR) in the MCF5213 Reference Manual for more information on stop modes 0–3. 5 Results are identical to STOP 00 for typical values because they only differ by CLKOUT power consumption. CLKOUT is already disabled in this instance prior to entering low power mode. 50.00 45.00 40.00 35.00 mA @ 3.3V 30.00 25.00 20.00 15.00 10.00 5.00 0.00 0 8 16 24 32 40 48 56 64 72 80 System Clock (MHz) Stop 0 - Flash Stop 1 - Flash Stop 2 - Flash Stop 3 - Flash Wait/Doze - Flash Run - Flash Typical Current Consumption in Low-Power Modes MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 27 Electrical Characteristics Table 21. Typical Active Current Consumption Specifications Characteristic 1 MHz core & I/O 8 MHz core & I/O 16 MHz core & I/O 64 MHz core & I/O 80 MHz core & I/O RAM standby supply current • Normal operation: VDD > VSTBY - 0.3 V • Transient condition: VSTBY - 0.3 V > VDD > VSS + 0.5 V • Standby operation: VDD < VSS + 0.5 V Analog supply current • Normal operation • Low-power stop 1 Symbol IDD Typical1 Active (SRAM) — 7.28 12.08 40.14 49.2 Typical1 Active (Flash) 3.48 13.37 25.08 54.62 64.09 N/A3 N/A3 N/A3 Peak2 — 19.02 35.66 85.01 100.03 N/A3 N/A3 N/A3 Unit mA ISTBY μA mA μA mA μA IDDA — — — — 16 50 Tested at room temperature with CPU polling a status register. All clocks were off except the UART and CFM (when running from flash memory). 2 Peak current measured with all modules active, and default drive strength with matching load. 3 Due to the errata “Non-functional RAM Standby Supply” in the MCF5213 Device Errata, VSTBY should be connected directly to VDD and cannot be used for RAM standby operation. 2.3 Thermal Characteristics Table 22. Thermal Characteristics Characteristic Symbol Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection — θJA θJA θJMA θJMA θJB θJC Ψjt Tj Value 531,2 391,3 42 1,3 Table 22 lists thermal resistance values. Unit °C / W °C / W °C / W °C / W °C / W °C / W °C / W oC 100 LQFP Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 331,3 254 95 26 105 MCF5213 ColdFire Microcontroller, Rev. 3 28 Freescale Semiconductor Electrical Characteristics Table 22. Thermal Characteristics (continued) Characteristic 81 MAPBGA Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 64 LQFP Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 64 QFN Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to ambient (@200 ft/min) Junction to board Junction to case (bottom) Junction to top of package Maximum operating junction temperature 1 Symbol Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection — Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection — Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection — θJA θJA θJMA θJMA θJB θJC Ψjt Tj θJA θJA θJMA θJMA θJB θJC Ψjt Tj θJA θJA θJMA θJMA θJB θJC Ψjt Tj Value 611,2 352,3 50 2,3 Unit °C / W °C / W °C / W °C / W °C / W °C / W °C / W o 312,3 20 12 2 4 5 6 105 62 1,2 C °C / W °C / W °C / W °C / W °C / W °C / W °C / W oC 431,3 501,3 361,3 264 95 26 105 681,2 241,3 551,3 191,3 84 0.65 36 105 °C / W °C / W °C / W °C / W °C / W °C / W °C / W oC 2 3 4 5 6 θJA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board JESD51-7) horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 29 Electrical Characteristics The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D × Θ JMA ) (1) Where: TA ΘJA PD PINT PI/O = ambient temperature, °C = package thermal resistance, junction-to-ambient, °C/W = PINT + PI/O = chip internal power, IDD × VDD, watts = power dissipation on input and output pins — user determined, watts For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K ÷ ( T J + 273 ° C ) Solving equations 1 and 2 for K gives: K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2) 2.4 Flash Memory Characteristics Table 23. SGFM Flash Program and Erase Characteristics (VDDF = 2.7 to 3.6 V) Parameter Symbol fsys(R) fsys(P/E) Min 0 0.15 Typ — — Max 66.67 or 801 66.67 or 801 Unit MHz MHz The flash memory characteristics are shown in Table 23 and Table 24. System clock (read only) System clock (program/erase)2 1 2 Depending on packaging; see Table 2. Refer to the flash memory section for more information Table 24. SGFM Flash Module Life Characteristics (VDDF = 2.7 to 3.6 V) Parameter Maximum number of guaranteed program/erase cycles1 before failure Data retention at average operating temperature of 85°C 1 2 Symbol P/E Retention Value 10,0002 10 Unit Cycles Years A program/erase cycle is defined as switching the bits from 1 → 0 → 1. Reprogramming of a flash memory array block prior to erase is not required. MCF5213 ColdFire Microcontroller, Rev. 3 30 Freescale Semiconductor Electrical Characteristics 2.5 ESD Protection Table 25. ESD Protection Characteristics1, 2 Characteristics ESD target for Human Body Model ESD target for Machine Model HBM circuit description Symbol HBM MM Rseries C MM circuit description Rseries C Number of pulses per pin (HBM) • Positive pulses • Negative pulses Number of pulses per pin (MM) • Positive pulses • Negative pulses Interval of pulses 1 Value 2000 200 1500 100 0 200 1 1 Units V V Ω pF Ω pF — — — — — — — 3 3 1 sec All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 2.6 DC Electrical Specifications Table 26. DC Electrical Specifications 1 Characteristic Symbol VDD VSTBY VIH VIL VHYS VLVD VLVDHYS Iin VOH VOL Min 3.0 3.0 0.7 × VDD VSS – 0.3 0.06 × VDD 2.15 60 –1.0 VDD – 0.5 — Max 3.6 3.6 4.0 0.35 × VDD — 2.3 120 1.0 — 0.5 Unit V V V V mV V mV μA V V Supply voltage Standby voltage Input high voltage Input low voltage Input hysteresis Low-voltage detect trip voltage (VDD falling) Low-voltage detect hysteresis (VDD rising) Input leakage current Vin = VDD or VSS, digital pins Output high voltage (all input/output and all output pins) IOH = –2.0 mA Output low voltage (all input/output and all output pins) IOL = 2.0mA MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 31 Electrical Characteristics Table 26. DC Electrical Specifications (continued)1 Characteristic Output high voltage (high drive) IOH = -5 mA Output low voltage (high drive) IOL = 5 mA Output high voltage (low drive) IOH = -2 mA Output low voltage (low drive) IOL = 2 mA Weak internal pull Up device current, tested at VIL Max.2 Input Capacitance 3 • All input-only pins • All input/output (three-state) pins 1 2 Symbol VOH VOL VOH VOL IAPU Cin Min VDD – 0.5 — VDD - 0.5 — –10 — — Max — 0.5 — 0.5 –130 7 7 Unit V V V V μA pF Refer to Table 27 for additional PLL specifications. Refer to Table 3 for pins having internal pull-up devices. 3 This parameter is characterized before qualification rather than 100% tested. 2.7 Clock Source Electrical Specifications Table 27. PLL Electrical Specifications (VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Symbol Min Max Unit MHz fref_crystal fref_ext fsys 0 fref / 32 fLOR fSCM tcst VIHEXT 2.0 VILEXT VSS tlpll tdc — 40 0.8 500 60 μs % fref VDD V 100 1 — 2 2 10.0 10.0 MHz 66.67 or 802 66.67 or 802 1000 5 10 kHz MHz ms V PLL reference frequency range • Crystal reference • External reference System frequency 1 • External clock mode • On-chip PLL frequency Loss of reference frequency 3, 5 Self clocked mode frequency Crystal start-up time 5, 6 EXTAL input high voltage • External reference EXTAL input low voltage • External reference PLL lock time4,7 Duty cycle of reference 4 4 MCF5213 ColdFire Microcontroller, Rev. 3 32 Freescale Semiconductor Electrical Characteristics Table 27. PLL Electrical Specifications (continued) (VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Frequency un-LOCK range Frequency LOCK range CLKOUT period jitter , measured at fSYS Max • Peak-to-peak (clock edge to clock edge) • Long term (averaged over 2 ms interval) On-chip oscillator frequency 1 2 3 4 5 6 7 8 4, 5, 8 ,9 Symbol fUL fLCK Cjitter Min –1.5 –0.75 — — Max 1.5 0.75 10 .01 8.16 Unit % fref % fref % fsys MHz foco 7.84 9 All internal registers retain data at 0 Hz. Depending on packaging; see Table 2. Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode. Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below fLOR with default MFD/RFD settings. This parameter is characterized before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. Based on slow system clock of 40 MHz measured at fsys max. 2.8 General Purpose I/O Timing GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, and Interrupt interfaces. When in GPIO mode, the timing specification for these pins is given in Table 28 and Figure 5. The GPIO timing is met under the following load test conditions: • • 50 pF / 50 Ω for high drive 25 pF / 25 Ω for low drive Table 28. GPIO Timing NUM G1 G2 G3 G4 Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min — 1.5 9 1.5 Max 10 — — — Unit ns ns ns ns MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 33 Electrical Characteristics CLKOUT G1 G2 GPIO Outputs G3 G4 GPIO Inputs Figure 5. GPIO Timing 2.9 Reset Timing Table 29. Reset and Configuration Override Timing (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1 NUM R1 R2 R3 R4 1 2 Characteristic RSTI input valid to CLKOUT High CLKOUT High to RSTI Input invalid RSTI input valid time 2 Symbol tRVCH tCHRI tRIVT tCHROV Min 9 1.5 5 — Max — — — 10 Unit ns ns tCYC ns CLKOUT High to RSTO Valid All AC timing is shown with respect to 50% VDD levels unless otherwise noted. During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the system. Thus, RSTI must be held a minimum of 100 ns. CLKOUT 1R1 R2 R3 R4 R4 RSTI RSTO Figure 6. RSTI and Configuration Override Timing MCF5213 ColdFire Microcontroller, Rev. 3 34 Freescale Semiconductor Electrical Characteristics 2.10 I2C Input/Output Timing Specifications Table 30. I2C Input Timing Specifications between I2C_SCL and I2C_SDA Num 11 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 × tCYC 8 × tCYC — 0 — 4 × tCYC 0 2 × tCYC 2 × tCYC Max — — 1 — 1 — — — — Units ns ns ms ns ms ns ns ns ns Table 30 lists specifications for the I2C input timing parameters shown in Figure 7. Table 31 lists specifications for the I2C output timing parameters shown in Figure 7. Table 31. I2C Output Timing Specifications between I2C_SCL and I2C_SDA Num 111 I21 I32 I41 I5 3 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 6 × tCYC 10 × tCYC — 7 × tCYC — 10 × tCYC 2 × tCYC 20 × tCYC 10 × tCYC Max — — — — 3 — — — — Units ns ns µs ns ns ns ns ns ns I61 I7 1 I81 I91 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 31. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 31 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. MCF5213 ColdFire Microcontroller, Rev. 3 Freescale Semiconductor 35 Electrical Characteristics Figure 7 shows timing for the values in Table 30 and Table 31. I2 I6 I5 SCL I1 I4 I7 I8 I3 I9 SDA Figure 7. I2C Input/Output Timings 2.11 Analog-to-Digital Converter (ADC) Parameters Table 32. ADC Parameters1 Table 32 lists specifications for the analog-to-digital converter. Name VREFL VREFH VDDA VADIN RES INL INL DNL Characteristic Low reference voltage High reference voltage ADC analog supply voltage Input voltages Resolution Integral non-linearity (full input signal range)2 Min VSS VREFL 3.0 VREFL 12 — — — Typical — — 3.3 — — ±2.5 ±2.5 –1 < DNL < +1 Max VREFH VDDA 3.6 VREFH 12 ±3 ±3