Freescale Semiconductor Data Sheet: Advance Information
Document Number: MCF52259 Rev. 0, 12/2008
MCF52259
LQFP–144 mm x mm
MCF52259 ColdFire Microcontroller
The MCF52259 is a member of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This document provides an overview of the 32-bit MCF52259 microcontroller, focusing on its highly integrated and diverse feature set. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 512 Kbytes of flash memory and 64 Kbytes of static random access memory (SRAM). On-chip modules include: • V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at 80 MHz running from internal flash memory with Enhanced Multiply Accumulate (MAC) Unit and hardware divider • Cryptography Acceleration Unit (CAU) • Fast Ethernet controller (FEC) • Mini-FlexBus external bus interface available on 144 pin packages • Universal Serial Bus On-The-Go (USBOTG) • USB Transceiver • FlexCAN controller area network (CAN) module • Three universal asynchronous/synchronous receiver/transmitters (UARTs) • Two inter-integrated circuit (I2C™) bus interface modules • Queued serial peripheral interface (QSPI) module • Eight-channel 12-bit fast analog-to-digital converter (ADC) with simultaneous sampling • Four-channel direct memory access (DMA) controller • Four 32-bit input capture/output compare timers with DMA support (DTIM) • Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM), and pulse accumulation • Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer • • • • • •
MAPBGA–144 mm x mm
LQFP–100 14 mm x 14 mm
Two 16-bit periodic interrupt timers (PITs) Real-time clock (RTC) module with 32 kHz crystal Programmable software watchdog timer Secondary watchdog timer with independent clock Interrupt controller capable of handling 57 sources Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL) • Test access/debug port (JTAG, BDM)
This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 2 Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21 2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .23 2.5 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .24 2.7 Clock Source Electrical Specifications . . . . . . . . . . . . .25 2.8 USB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.9 Mini-FlexBus External Interface Specifications . . . . . . .26 2.10 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 2.11 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 2.12 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13 I2C Input/Output Timing Specifications . . . . . . . . . . . . 2.14 Analog-to-Digital Converter (ADC) Parameters. . . . . . 2.15 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . . 2.16 DMA Timers Timing Specifications . . . . . . . . . . . . . . . 2.17 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 2.18 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 2.19 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . 3.1 100-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 28 29 30 31 32 33 33 34 36 37 38 40
3 4
MCF52259 ColdFire Microcontroller, Rev. 0 2 Freescale Semiconductor
Family Configurations
1
Family Configurations
Table 1. MCF52259 Family Configurations
Module 52252 • 52254 • 52255 • up to 80 MHz1 52256 • 52258 • 52259 • up to 80 MHz1
Version 2 ColdFire Core with eMAC (Enhanced multiply-accumulate unit) and CAU (Cryptographic acceleration unit) System Clock Performance (Dhrystone 2.1 MIPS) Flash Static RAM (SRAM) Two Interrupt Controllers (INTC) Fast Analog-to-Digital Converter (ADC) USB On-The-Go (USB OTG) Mini-FlexBus external bus interface Fast Ethernet Controller (FEC) Random Number Generator and Cryptographic Acceleration Unit (CAU) FlexCAN 2.0B Module Four-channel Direct-Memory Access (DMA) Software Watchdog Timer (WDT) Secondary Watchdog Timer Two-channel Periodic Interrupt Timer (PIT) Four-Channel General Purpose Timer (GPT) 32-bit DMA Timers QSPI UART(s) I
2C
up to 66 or 80 MHz1
up to 66 or 80 MHz1
up to 63 or 76 256 KB 32 KB • • • — • — Varies • • • 2 • 4 • 3 2 • • • • • 512 KB 64 KB • • • — • — Varies • • • 2 • 4 • 3 2 • • • • • 100 LQFP 512 KB 64 KB • • • — • • • • • • 2 • 4 • 3 2 • • • • • 256 KB 32 / 64 KB • • • • • — Varies • • • 2 • 4 • 3 2 • • • • • 512 KB 64 KB • • • • • — Varies • • • 2 • 4 • 3 2 • • • • • 512 KB 64 KB • • • • • • • • • • 2 • 4 • 3 2 • • • • •
Eight/Four-channel 8/16-bit PWM Timer General Purpose I/O Module (GPIO) Chip Configuration and Reset Controller Module Background Debug Mode (BDM) JTAG - IEEE 1149.1 Test Access Port Package
1
144 LQFP or 144 MAPBGA
66 MHz = 63 MIPS; 80 MHz = 76 MIPS
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 3
Family Configurations
1.1
Block Diagram
Slave Mode Access (CIM_IBO/EzPort)
Figure 1 shows a top-level block diagram of the device. Package options for this family are described later in this document.
AN QSPI SDAn SCLn UTXDn PADI – Pin Muxing URXDn URTSn UCTSn PWMn DTINn/DTOUTn GPT RCON_B ALLPST PST DDATA
Arbiter M2 M0 TMS TDI TDO TRST TCLK
M1
Interrupt Controller
BDM PORT UART 0 JTAG TAP UART 1 UART 2 I2C 0 QSPI Watch Dog
JTAG_EN
DTIM 0
DTIM 1
DTIM 2
DTIM 3
RTC
I2C 1
4 CH DMA
V2 ColdFire CPU
MAC
DIV PMM
IPS Bus Gasket AN[7:0] CIM_IBO ADC Backup Watchdog
16 Kbytes SRAM
CFM 128 Kbytes flash memory (16K×16)×4 VPP
CLKMOD PORTS CIM_IBO RSTI RSTO
VSTBY
TIM
Edge Port EXTAL IRQ[7:1]
PLL OCO CLKGEN XTAL CLKOUT
PIT0
PIT1
PWM
GPT[3:0]
MCF52259 ColdFire Microcontroller, Rev. 0 4 Freescale Semiconductor
Family Configurations EzPD EzPQ EzPCK EzPCS Mini-FlexBus To/From PADI Arbiter USB Interrupt Controllers PADI – Pin Muxing USB Mini-FlexBus AN[7:0] I2Cs QSPI UARTs GPTn IRQn FEC DTINn/DTOUTn CANRX CANTX PWMn EzPort JTAG/BDM
EzPort
To/From PADI
FEC 4 ch DMA To/From PADI
UARTs 0–2
PITs 0–1
I2C 0–1
QSPI
DTIMs 0–3
FlexCAN
Edge Port
RTC
JTAG_EN
MUX V2 ColdFire CPU JTAG TAP IFP OEP CAU EMAC PMM
To/From PADI
ADC
up to 64 Kbytes SRAM (4K×16)×4
up to 512Kbytes Flash (64K×16)×4
PORTS (GPIO)
CCM, Reset
RSTIN RSTOUT
VRH
VRL
PLL CLKGEN
Watchdog Timer
RNGA
GPT
PWM
EXTAL
XTAL CLKOUT
Figure 1. Block Diagram
1.2
Features
This document contains information on a new product under development. Freescale reserves the right to change or discontinue this product without notice. Specifications and information herein are subject to change without notice.
1.2.1
•
Feature Overview
Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data paths on-chip — Up to 80 MHz processor core frequency
The MCF52259 family includes the following features:
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 5
Family Configurations
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— 40 MHz or 33 MHz off-platform bus frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+) — Enhanced Multiply-Accumulate (EMAC) unit with four 32-bit accumulators to support 16×16 → 32 or 32×32 → 32 operations — Cryptographic Acceleration Unit (CAU) – Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions – Support for DES, 3DES, AES, MD5, and SHA-1 algorithms System debug support — Real-time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging (DEBUG_B+) — Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or 2-level trigger On-chip memories — Up to 64-Kbyte dual-ported SRAM on CPU internal bus, supporting core, DMA, and USB access with standby power supply support for the first 16 Kbytes — Up to 512 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses Power management — Fully static operation with processor sleep and whole chip stop modes — Rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used (except backup watchdog timer) — Software controlled disable of external clock output for low-power consumption FlexCAN 2.0B module — Based on and includes all existing features of the Freescale TouCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard data and remote frames (up to 109 bits long) – Extended data and remote frames (up to 127 bits long) – Zero to eight bytes data length – Programmable bit rate up to 1 Mbit/sec — Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages — Unused MB space can be used as general purpose RAM space — Listen-only mode capability — Content-related addressing — No read/write semaphores — Three programmable mask registers: global for MBs 0–13, special for MB14, and special for MB15 — Programmable transmit-first scheme: lowest ID or lowest buffer number — Time stamp based on 16-bit free-running timer — Global network time, synchronized by a specific message — Maskable interrupts Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller — Full-speed / low-speed host controller — USB 1.1 and 2.0 compliant full-speed / low speed device controller — 16 bidirectional end points — DMA or FIFO data stream interfaces
MCF52259 ColdFire Microcontroller, Rev. 0
6
Freescale Semiconductor
Family Configurations
•
— Low power consumption — OTG protocol logic Fast Ethernet controller (FEC) — 10/100 BaseT/TX capability, half duplex or full duplex — On-chip transmit and receive FIFOs — Built-in dedicated DMA controller — Memory-based flexible descriptor rings
•
•
•
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•
Mini-FlexBus — External bus interface available on 144 pin packages — Supports glueless interface with 8-bit ROM/flash/SRAM/simple slave peripherals. Can address up to 2 Mbytes of addresses — 2 chip selects (FB_CS[1:0]) — Non-multiplexed mode: 8-bit dedicated data bus, 20-bit address bus — Multiplexed mode: 16-bit data and 20-bit address bus — FB_CLK output to support synchronous memories — Programmable base address, size, and wait states to support slow peripherals — Operates at up to 40 MHz (bus clock) in 1:2 mode or up to 80 MHz (core clock) in 1:1 mode Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic with maskable interrupts — DMA support — Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity — Up to two stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers Two I2C modules — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to three chip selects available — Master mode operation only — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers Fast analog-to-digital converter (ADC) — Eight analog input channels — 12-bit resolution — Minimum 1.125 μs conversion time — Simultaneous sampling of two channels for motor control applications — Single-scan or continuous operation — Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit — Unused analog channels can be used as digital I/O
MCF52259 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
7
Family Configurations
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•
•
•
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Four 32-bit timers with DMA support — 12.5 ns resolution at 80 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input capture capability with programmable trigger edge on input pin — Output compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or output compare — DMA trigger capability on input capture or output compare Four-channel general purpose timer — 16-bit architecture — Programmable prescaler — Output pulse-widths variable from microseconds to seconds — Single 16-bit input pulse accumulator — Toggle-on-overflow feature for pulse-width modulator (PWM) generation — One dual-mode pulse accumulation channel Pulse-width modulation timer — Support for PCM mode (resulting in superior signal quality compared to conventional PWM) — Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution — Programmable period and duty cycle — Programmable enable/disable for each channel — Software selectable polarity for each channel — Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached (PWM counter reaches zero) or when the channel is disabled. — Programmable center or left aligned outputs on individual channels — Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies — Emergency shutdown Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down Real-Time Clock (RTC) — Maintains system time-of-day clock — Provides stopwatch and alarm interrupt functions Software watchdog timer — 32-bit counter — Low-power mode support Backup watchdog timer (BWT) — Independent timer that can be used to help software recover from runaway code — 16-bit counter — Low-power mode support Clock generation features — Twelve to 48 MHz crystal, 8 MHz on-chip trimmed relaxation oscillator, or external oscillator reference options — Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable from 1 to 8 — System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator — Low power modes supported
MCF52259 ColdFire Microcontroller, Rev. 0 8 Freescale Semiconductor
Family Configurations
•
•
•
•
•
•
— 2n (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation Interrupt controller — Uniquely programmable vectors for all interrupt sources — Fully programmable level and priority for all peripheral interrupt sources — Seven external interrupt signals with fixed level and priority — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low-power modes DMA controller — Four fully programmable channels — Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4×32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle-steal support — Software-programmable DMA requests for the UARTs (3) and 32-bit timers (4) — Channel linking support Reset — Separate reset in and reset out signals — Seven sources of reset: – Power-on reset (POR) – External – Software – Watchdog – Loss of clock / loss of lock – Low-voltage detection (LVD) – JTAG — Status flag indication of source of last reset Chip configuration module (CCM) — System configuration during reset — Selects one of six clock modes — Configures output pad drive strength — Unique part identification number and part revision number General purpose I/O interface — Up to 56 bits of general purpose I/O on 100-pin package — Up to 96 bits of general purpose I/O on 144-pin package — Bit manipulation supported via set/clear functions — Programmable drive strengths — Unused peripheral pins may be used as extra GPIO JTAG support for system level board testing
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 9
Family Configurations
1.2.2
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the core includes the enhanced multiply-accumulate (EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized for 32x32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
1.2.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided on 144-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. This device implements revision B+ of the ColdFire Debug Architecture. The processor’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging. To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111). The full debug/trace interface is available only on the 144-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.4
JTAG
The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The device implementation can: • • • • • Perform boundary-scan operations to test circuit board electrical continuity Sample system pins during operation and transparently shift out the result in the boundary scan register Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit Disable the output drive to pins during circuit-board testing Drive output pins to stable levels
MCF52259 ColdFire Microcontroller, Rev. 0 10 Freescale Semiconductor
Family Configurations
1.2.5
1.2.5.1
On-Chip Memories
SRAM
The dual-ported SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. The SRAM module is also accessible by the DMA, FEC, and USB. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance.
1.2.5.2
Flash Memory
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local bus. The CFM is constructed with four banks of 64-Kbyte×16-bit flash memory arrays to generate 512 Kbytes of 32-bit flash memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips.
1.2.6
Cryptographic Acceleration Unit
The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.
1.2.7
Power Management
The device incorporates several low-power modes of operation entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip falls below the standby battery voltage.
1.2.8
FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers.
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 11
Family Configurations
1.2.9
Mini-FlexBus
A multi-function external bus interface called the Mini-FlexBus is provided on the device with basic functionality of interfacing to slave-only devices with a maximum slave bus frequency up to 40 MHz in 1:2 mode and 80 MHz in 1:1 mode. It can be directly connected to the following asynchronous or synchronous devices with little or no additional circuitry: • • • • External ROMs Flash memories Gate-array logic Other simple target (slave) devices
The Mini-FlexBus is a subset of the FlexBus module found on higher-end ColdFire microprocessors. The Mini-FlexBus minimizes package pin-outs while maintaining a high level of configurability and functionality.
1.2.10
USB On-The-Go Controller
The device includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller. USB is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs. The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly to each other without the need for a PC. The dual-mode controller on the device can act as a USB OTG host and as a USB device. It also supports full-speed and low-speed modes.
1.2.11
Fast Ethernet Controller (FEC)
The Ethernet media access controller (MAC) supports 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FECs supports the 10/100 Mbps MII, and the 10 Mbps-only 7-wire interface.
1.2.12
UARTs
The device has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions.
1.2.13
I2C Bus
The processor includes two I2C modules. The I2C bus is an industry-standard, two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices.
1.2.14
QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.
1.2.15
Fast ADC
The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing. Signals on the SYNCA and SYNCB pins initiate an ADC conversion.
MCF52259 ColdFire Microcontroller, Rev. 0 12 Freescale Semiconductor
Family Configurations
The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly until manually stopped. The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled. During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously. Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.16
DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the device. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers.
1.2.17
General Purpose Timer (GPT)
The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, channel three, can be configured as a pulse accumulator. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.
1.2.18
Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running down-counter.
1.2.19
Real-Time Clock (RTC)
The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions along with an alarm interrupt.
1.2.20
Pulse-Width Modulation (PWM) Timers
The device has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The timer supports PCM mode, which results in superior signal quality when compared to that of a conventional PWM. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 13
Family Configurations
higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.
1.2.21
Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
1.2.22
Backup Watchdog Timer
The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from runaway code. This timer is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system clock.
1.2.23
Phase-Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.
1.2.24
Interrupt Controllers (INTCn)
The device has two interrupt controllers that supports up to 128 interrupt sources. There are 56 programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for software interrupt requests.
1.2.25
DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.
1.2.26
• • • • • • •
Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset: External reset input Power-on reset (POR) Watchdog timer Phase locked-loop (PLL) loss of lock / loss of clock Software Low-voltage detector (LVD) JTAG
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin.
MCF52259 ColdFire Microcontroller, Rev. 0 14 Freescale Semiconductor
Family Configurations
1.2.27
GPIO
Nearly all pins on the device have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pin.
1.2.28
Part Numbers and Packaging
This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office for up-to-date RoHS information. Table 2. Orderable Part Number Summary
Freescale Part Number MCF52221CAE66 MCF52221CVM66 MCF52221CAF66 MCF52221CVM80 MCF52221CAF80 MCF52223CVM66 MCF52223CAF66 MCF52223CVM80 MCF52223CAF80 Description MCF52221 Microcontroller MCF52221 Microcontroller MCF52221 Microcontroller MCF52221 Microcontroller MCF52221 Microcontroller MCF52223 Microcontroller MCF52223 Microcontroller MCF52223 Microcontroller MCF52223 Microcontroller Speed Flash/SRAM (MHz) (Kbytes) 66 66 66 80 80 66 66 80 80 128/16 128/16 128/16 128/16 128/16 128/16 128/16 128/16 128/16 Package 64 LQFP 81 MAPBGA 100 LQFP 81 MAPBGA 100 LQFP 81 MAPBGA 100 LQFP 81 MAPBGA 100 LQFP Temp range (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85
Table 3. Orderable Part Number Summary
Freescale Part Number MCF52252AF80 MCF52252CAF66 MCF52254AF80 MCF52254CAF66 MCF52255CAF80 MCF52256AG80 MCF52256CAG66 MCF52256CVN66 MCF52256VN80 FlexCAN — • — • • — • • — Encryption — — — — • — — — — Speed (MHz) 80 256 66 80 512 66 80 80 66 256 66 80 64 144 MAPBGA 32 0 to +70 -40 to +85 512 64 32 144 LQFP 64 -40 to +85 100 LQFP 64 100 LQFP -40 to +85 -40 to +85 0 to +70 32 100 LQFP -40 to +85 0 to +70 Flash (Kbytes) SRAM (Kbytes) Package Temp range (°C) 0 to +70
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 15
Family Configurations
Table 3. Orderable Part Number Summary (continued)
Freescale Part Number MCF52258AG80 MCF52258CAG66 MCF52258CVN66 MCF52258VN80 MCF52259CAG80 MCF52259CVN80 FlexCAN — • • — • • Encryption — — — — • • 80 512 64 144 MAPBGA -40 to +85 Speed (MHz) 80 144 LQFP 66 512 66 144 MAPBGA 80 144 LQFP 0 to +70 -40 to +85 64 -40 to +85 -40 to +85 Flash (Kbytes) SRAM (Kbytes) Package Temp range (°C) 0 to +70
Figure 2 shows the pinout configuration for the 144 LQFP.
FEC_RXCLK FEC_TXCLK FEC_RXER FEC_RXDV FEC_TXER FEC_TXEN FEC_RXD3 FEC_RXD2 FEC_RXD1 FEC_RXD0 FEC_TXD0 FEC_TXD1 FEC_TXD2 FEC_TXD3 110 CLKMOD1 CLKMOD0 FEC_COL 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 TRST TDI FB_RW FB_D3 FB_D2 FB_D1 FB_D0 FB_A4 FB_A3 FB_A2 FB_A1 FB_A0 UTXD1 ALLPST UCTS1 URTS1 ICOC3 AN0 AN1 AN2 AN3 FB_CS0 URXD1 JTAG_EN TIN2 TDO VRL VDD FB_ALE VDD VSSA TCLK VRH TMS VSS VSS 72 RSTOUT FB_A15 FB_A16 FB_A17 FB_A18 FB_A19 FB_OE FB_D5 FB_D6 FB_D7 RSTIN
IRQ3
IRQ5
VDD
VDD
VDD 115
VSS
VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
114
113
112
FB_D4 FB_A14 FB_A13 FB_A12 FB_A11 FB_A10 VDD VSS TEST RCON TIN0 TIN1 RCC_EXTAL RTC_XTAL UCTS0 UTXD0 URXD0 URTS0 TIN3 VDD VSS PCS3 PCS2 QSDI QSD0 SCK PCS0 SCL SDA VDD VSS FB_A9 FB_A8 FB_A7 FB_A6 FB_A5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
111
•
VSS
FEC_CRS VDDPLL EXTAL XTAL VSSPLL IRQ1 URXD2 UTXD2 VDD VSS URTS2 UCTS2 IRQ7 ICOC2 ICOC1 ICOC0 VDD VSS PST0 PST1 PST2 PST3 DDATA3 DDATA2 DDATA1 DDATA0 VSSUSB USB_DP USB_DM VDDUSB VSTBY AN4 AN5 AN6 AN7 VDDA
Figure 2. 144 LQFP Pin Assignment
MCF52259 ColdFire Microcontroller, Rev. 0 16 Freescale Semiconductor
Family Configurations
Figure 3 shows the pinout configuration for the 100 LQFP.
CLKMOD1 CLKMOD0 RSTOUT RSTIN IRQ3 IRQ5 FEC_RXD3 FEC_RXD2 VDD VSS FEC_RXD1 FEC_RXD0 FEC_RXDV FEC_RXCLK FEC_RXER FEC_TXER FEC_TXCLK FEC_TXEN VDD VSS FEC_TXD0 FEC_TXD1 FEC_TXD2 FEC_TXD3 FEC_COL VDD VSS TEST RCON TIN0 TIN1 RTC_EXTAL RTC_XTAL UCTS0 UTXD0 URXD0 URTS0 TIN3 VDD VSS PCS3 PCS2 QSDI QSDO SCK PCS0 SCL SDA VDD VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 LQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
FEC_CRS VDDPLL EXTAL XTAL VSSPLL IRQ1 URXD2 UTXD2 VDD VSS URTS2 UCTS2 IRQ7 ICOC2 ICOC1 ICOC0 VSSUSB USB_DP USB_DM VDDUSB VSTBY AN4 AN5 AN6 AN7
Freescale Semiconductor
TMS TRST TDI TDO ALLPST TCLK JTAG_EN VDD VSS ICOC3 VDD VSS UCTS1 UTXD1 URXD1 URTS1 TIN2 AN0 AN1 AN2 AN3 VSSA VRL VRH VDDA
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 3. 100 LQFP Pin Assignments
MCF52259 ColdFire Microcontroller, Rev. 0 17
Family Configurations
Figure 4 shows the pinout configuration for the 144 MAPBGA.
1 A VSS 2 RSTOUT 3 RSTIN 4 FB_D6 5 FB_D7 6 IRQ3 7 IRQ5 8 FEC_ RXD0 FEC_ RXCLK FEC_ RXDV FEC_ TXER 9 FEC_ RXER FEC_ TXCLK FEC_ TXD1 FEC_ TXD0 10 FEC_ TXEN FEC_ TXD2 11 FEC_ TXD3 12 VSS A
B
TEST
FB_A14
FB_D4
FB_D5
FB_OE
FB_A19
FEC_ RXD1 FEC_ RXD2 FEC_ RXD3
FEC_COL FEC_CRS B
C
TIN1
FB_A12
FB_A13
FB_A15
FB_A16
FB_A18
URXD2
VDDPLL
EXTAL
C
D
RTC_ EXTAL RTC_ XTAL
TIN0
FB_A11
CLKMOD1 CLKMOD0
FB_A17
UTXD2
VSSPLL
XTAL
D
E
UCTS0
FB_A10
RCON
VDD
VDD
VDD
VDD
IRQ1
URTS2
UCTS2
IRQ7
E
F
UTXD0
URXD0
URTS0
TIN3
VDD
VSS
VSS
VSS
PST3
DDATA0
DDATA1
ICOC0
F
G
QSDO
QSDI
PCS2
PCS3
VDD
VSS
VSS
VSS
DDATA3
PST2
PST1
PST0
G
H
SCL
SDA
SCK
PCS0
VDD
VDD
VDD
VSS
VSSUSB
DDATA2
USB_DM
USB_DP
H
J
FB_A6
FB_A7
FB_A9
FB_A8
FB_D0
FB_A3
VDD
TIN2
VDDUSB
ICOC2
ICOC1
VSTBY
J
K
TMS
TRST
FB_ALE
FB_A5
FB_D2
FB_A4
UCTS1
UTXD1
AN3
AN6
AN4
AN5
K
L
TDI
TDO
ALLPST
FB_D3
FB_D1
FB_A1
FB_A0
URXD1
AN2
VRH
VDDA
AN7
L
M
VSS 1
JTAG_ EN 2
TCLK 3
FB_RW 4
FB_CS0 5
FB_A2 6
ICOC3 7
URTS1 8
AN0 9
AN1 10
VRL 11
VSSA 12
M
Figure 4. Pinout Top View (144 MAPBGA)
MCF52259 ColdFire Microcontroller, Rev. 0 18 Freescale Semiconductor
Table 4 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin. Table 4. Pin Functions by Primary and Alternate Purpose
Pin Group ADC Primary Function AN7 AN6 AN5 AN4 AN3 MCF52259 ColdFire Microcontroller, Rev. 0 AN2 AN1 AN0 SYNCA3 SYNCB VDDA VSSA VRH VRL Clock Generation EXTAL XTAL VDDPLL VSSPLL Debug Data ALLPST DDATA[3:0] PST[3:0] I
2C 3
Freescale Semiconductor 19
Secondary Function — — — — — — — — — — — — — — — — — — — — —
Tertiary Function — — — — — — — — — — — — — — — — — — — — — UTXD2 URXD2
Quaternary Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO — — — — — — — — — — — GPIO GPIO GPIO GPIO
Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 1 Control Low Low Low Low Low Low Low Low N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A High High High PDSR[0] PDSR[0] FAST FAST FAST FAST FAST FAST FAST FAST N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FAST FAST FAST PSRR[0] PSRR[0] — — — — — — — — — — — — — — — — — — — — — pull-up4 pull-up
4
Pin on 100 LQFP 51 52 53 54 46 45 44 43 — — 50 47 49 48 73 72 74 71 86 84,83,78,77 70,69,66,65 10 11
Pin on 81 MAPBGA H9 G9 G8 F9 G7 G6 H6 J6 — — H8 H7, J9 J8 J7 B9 C9 B8 C8 A6 — — E1 E2
Pin on 64 LQFP/QFN 33 34 35 36 28 27 26 25 — — 32 29 31 30 47 46 48 45 55 — — 8 9 Family Configurations
SCL SDA
Table 4. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group Interrupts Primary Function IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 MCF52259 ColdFire Microcontroller, Rev. 0 IRQ1 JTAG/BDM JTAG_EN TCLK/ PSTCLK TDI/DSI TDO/DSO TMS /BKPT TRST /DSCLK Mode Selection6 CLKMOD0 CLKMOD1 RCON/ EZPCS Secondary Function — — — — — — SYNCA — CLKOUT — — — — — — — — — — — — — — — — Tertiary Function — — — — — — Quaternary Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO — — — — — — — — — Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 Low Low Low Low Low Low High N/A High N/A High N/A N/A N/A N/A N/A FAST FAST FAST FAST FAST FAST FAST N/A FAST N/A FAST N/A N/A N/A N/A N/A pull-up4 pull-down pull-up5 pull-up5 — pull-up5 pull-up5 pull-down6 pull-down6 pull-up Pin on 100 LQFP 95 94 91 90 89 88 87 26 64 79 80 76 85 40 39 21 Pin on 81 MAPBGA C4 B4 A4 C5 A5 B5 C6 J2 C7 B7 A7 A8 B6 G5 H5 G3 Pin on 64 LQFP/QFN 58 — — 57 — — 56 17 44 50 51 49 54 24 — 16
Family Configurations
20 Freescale Semiconductor
Table 4. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group QSPI Primary Function QSPI_DIN/ EZPD QSPI_DOUT/ EZPQ QSPI_CLK/ EZPCK QSPI_CS3 MCF52259 ColdFire Microcontroller, Rev. 0 QSPI_CS2 QSPI_CS1 QSPI_CS0 Reset
8
Freescale Semiconductor 21
Secondary Function
Tertiary Function URXD1 UTXD1
Quaternary Function GPIO GPIO GPIO GPIO
Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 PDSR[2] PDSR[1] PDSR[3] PDSR[7] PDSR[6] PDSR[5] PDSR[4] N/A high N/A PDSR[23] PDSR[22] PDSR[21] PDSR[20] PDSR[19] PDSR[18] PDSR[17] PDSR[16] PDSR[11] PDSR[10] PDSR[9] PDSR[8] PSRR[2] PSRR[1] PSRR[3] PSRR[7] PSRR[6] PSRR[5] PSRR[4] N/A FAST N/A PSRR[23] PSRR[22] PSRR[21] PSRR[20] PSRR[19] PSRR[18] PSRR[17] PSRR[16] PSRR[11] PSRR[10] PSRR[9] PSRR[8] — pull-up7 pull-up8 — pull-down pull-up
9
Pin on 100 LQFP 16 17 18 12 13 19 20 96 97 5
Pin on 81 MAPBGA F3 G1 G2 F1 F2 H2 H1 A3 B3 C2
Pin on 64 LQFP/QFN 12 13 14 — — — 15 59 60 3
— — pull-up7
SCL SYNCA
URTS1
— — SDA — — — — — — — DTOUT3 DTOUT2 DTOUT1 DTOUT0 — UCTS1 — — — PWM7 PWM5 PWM3 PWM1 PWM6 PWM4 PWM2 PWM0 — — — —
GPIO GPIO GPIO — — — GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
RSTI RSTO
Test Timers, 16-bit
TEST GPT3 GPT2 GPT1 GPT0
pull-up9 pull-up9 pull-up9 — — — — — — — — 32 31 37 36 6 9 7 8 H3 J3 G4 H4 C1 D3 D1 D2 19 18 23 22 4 7 5 6 Family Configurations
Timers, 32-bit
DTIN3 DTIN2 DTIN1 DTIN0
UART 0
UCTS0 URTS0 URXD0 UTXD0
Table 4. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group UART 1 Primary Function UCTS1 URTS1 URXD1 UTXD1 UART 2 MCF52259 ColdFire Microcontroller, Rev. 0 UCTS2 URTS2 URXD2 UTXD2 VSTBY VDD VSTBY VDD — — — — Secondary Function SYNCA SYNCB Tertiary Function URXD2 UTXD2 — — — — — — — — Quaternary Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO — — Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 PDSR[15] PDSR[14] PDSR[13] PDSR[12] PDSR[27] PDSR[26] PDSR[25] PDSR[24] N/A N/A PSRR[15] PSRR[14] PSRR[13] PSRR[12] PSRR[27] PSRR[26] PSRR[25] PSRR[24] N/A N/A — — — — — — — — — — Pin on 100 LQFP 98 4 100 99 27 30 28 29 55 1,2,14,22, 23,34,41, 57,68,81,93 Pin on 81 MAPBGA C3 B1 B2 A2 — — — — F8 Pin on 64 LQFP/QFN 61 2 63 62 — — — — 37
Family Configurations
22 VSS VSS
1 2 3 4 5 6 7 8 9
D5,E3–E7, 1,10,20,39,5 F5 2 11,21,38, 53,64
—
—
—
N/A
N/A
—
3,15,24,25,3 A1,A9,D4,D 5,42,56, 6,F4,F6,J1 67,75,82,92
The PDSR and PSSR registers are described in the General Purpose I/O chapter. All programmable signals default to 2 mA drive and FAST slew rate in normal (single-chip) mode. All signals have a pull-up in GPIO mode. These signals are multiplexed on other pins. For primary and GPIO functions only. Only when JTAG mode is enabled. CLKMOD0 and CLKMOD1 have internal pull-down resistors; however, the use of external resistors is very strongly recommended. For secondary and GPIO functions only. RSTI has an internal pull-up resistor; however, the use of an external resistor is very strongly recommended. For GPIO function. Primary Function has pull-up control within the GPT module.
Freescale Semiconductor
Freescale Semiconductor MCF52259 ColdFire Microcontroller, Rev. 0 23
Table 5. Pin Functions by Primary and Alternate Purpose
Pin Group ADC Primary Function AN[7:0] VDDA VSSA VRH VRL Clock Generation EXTAL XTAL VDDPLL VSSPLL RTC RTC_EXTAL RTC_XTAL Debug Data ALLPST DDATA[3:0] PST[3:0] FEC FEC_COL FEC_CRS FEC_RXCLK FEC_RXD[0:3] FEC_RXDV FEC_RXER FEC_TXCLK FEC_TXD[0:3] SecondaryF unction — — — — — — — — — — — — — — — — — — — — — — Tertiary Function — — — — — — — — — — — — — — — — — — — — — — Drive Quaternary Strength/ Function Control1 PAN[7:0] — — — — — — — — — — — PDD[7:4] PDD[3:0] PTI0 PTI1 PTI2 PTI[3:6] PTI7 PTJ0 PTJ1 PTJ[2:5] N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A High High High Low Low Low Low Low Low Low Low Wired OR Control — N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A — — — Pull-up/ Pin on Pull-down2 144 MAPBGA — — — — — — — — — — — — — — K9–K12; L9, L12; M9–M10 L11 M12 L10 M11 C12 D12 C11 D11 D1 E1 L3 F10–F11; G9; H10 F9; G10–G12 B11 B12 B8 A8; B7; C7; D7 C8 A9 B9 A11; B10; C9; D9 Pin on 144 LQFP 74–77; 66–69 73 70 72 71 106 105 107 104 33 34 42 83–86 87–90 109 108 120 122–123; 126–127 121 119 117 113–110 Pin on 100 LQFP 43–46; 51–54 50 47 49 48 73 72 74 71 7 8 30 — — 76 75 87 89–90; 93–94 88 86 84 77–80 Family Configurations
Table 5. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group FEC Primary Function FEC_TXEN FEC_TXER I2C03 I2C_SCL0 I2C_SDA0 Interrupts MCF52259 ColdFire Microcontroller, Rev. 0 IRQ7 IRQ5 IRQ3 IRQ1 JTAG/BDM JTAG_EN TCLK/ PSTCLK TDI/DSI TDO/DSO TMS/BKPT TRST/DSCLK Mode Selection QSPI RCON/EZPCS CLKMOD[1:0] QSPI_CS3 QSPI_CS2 QSPI_CS0 QSPI_CLK/ EZPCK QSPI QSPI_DIN/ EZPD QSPI_DOUT/E ZPQ SecondaryF unction — — — — — FEC_MDC FEC_MDIO — — CLKOUT — — — — — — SYNCA SYNCB I2C_SDA0 I2C_SCL0 I2C_SDA1 I2C_SCL1 Tertiary Function — — UTXD2 URXD2 — — — USB_ALTCLK — FB_CLK — — — — — — USB_DP_ PDOWN USB_DM_ PDOWN UCTS1 URTS1 URXD1 UTXD1 Drive Quaternary Strength/ Function Control1 PTJ6 PTJ7 PAS0 PAS1 PNQ7 PNQ5 PNQ3 PNQ1 — — — — — — — — PQS6 PQS5 PQS3 PQS2 PQS1 PQS0 Low Low PDSR[0] PDSR[0] Low Low Low Low N/A High N/A High N/A N/A N/A N/A PDSR[7] PDSR[6] PDSR[4] PDSR[3] PDSR[2] PDSR[1] — — — — — — N/A — N/A N/A N/A N/A N/A6 N/A — — PWOR[7] PWOR[6]
6
Freescale Semiconductor 24
Wired OR Control
Pull-up/ Pin on Pull-down2 144 MAPBGA A10 D8 Pull-Up4 Pull-Up
4 4
Pin on 144 LQFP 116 118 28 29 96 128 129 103 44 43 40 41 38 39 10 143–144 22 23 27 26 24 25
Pin on 100 LQFP 83 85 22 23 63 95 96 70 32 31 28 29 26 27 4 99–100 16 17 21 20 18 19
H1 H2 E12 A7 A6 E9 M2 M3 L1 L2 K1 K2 E4 D4–D5
Pull-Up
Pull-Up4 Pull-Up
4 4
Pull-Up
Pull-Down Pull-Up5 Pull-Up5 — Pull-Up5 Pull-Up Pull-Up
— — Pull-Up7 Pull-Up7 — —
G4 G3 H4 H3 G2 G1
Family Configurations
PWOR[4]6 PWOR[5]6
Table 5. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group Reset8 Primary Function RSTI RSTO Test Timer 3, 16-bit Timer 2, 16-bit MCF52259 ColdFire Microcontroller, Rev. 0 Timer 1, 16-bit Timer 0, 16-bit Timer 3, 32-bit Timer 2, 32-bit Timer 1, 32-bit Timer 0, 32-bit UART 0 TEST GPT3 GPT2 GPT1 GPT0 DTIN3 DTIN2 DTIN1 DTIN0 UCTS0 URTS0 URXD0 UTXD0 UART 1 UCTS1 URTS1 URXD1 UTXD1 SecondaryF unction — — — — — — — DTOUT3 DTOUT2 DTOUT1 DTOUT0 — — — — SYNCA SYNCB I2C_SDA1 I2C_SCL1 Tertiary Function — — — PWM7 PWM5 PWM3 PWM1 PWM6 PWM4 PWM2 PWM0 USB_VBUSE USB_VBUSD — — URXD2 UTXD2 — — Drive Quaternary Strength/ Function Control1 — — — PTA3 PTA2 PTA1 PTA0 PTC3 PTC2 PTC1 PTC0 PUA3 PUA2 PUA1 PUA0 PUB3 PUB2 PUB1 PUB0 N/A High N/A N/A N/A N/A N/A PDSR[19] PDSR[18] PDSR[17] PDSR[16] PDSR[11] PDSR[10] PDSR[9] PDSR[8] PDSR[15] PDSR[14] PDSR[13] PDSR[12] Wired OR Control N/A — N/A — — — — — — — — — — PWOR[0] PWOR[1] — — PWOR[2] PWOR[3] Pull-up/ Pin on Pull-down2 144 MAPBGA Pull-Up8 — Pull-Down Pull-Up
9
Freescale Semiconductor 25
Pin on 144 LQFP 141 142 9 58 95 94 93 19 65 12 11 15 18 17 16 61 64 63 62
Pin on 100 LQFP 97 98 3 35 62 61 60 13 42 6 5 9 12 11 10 38 41 40 39 Family Configurations
A3 A2 B1 M7 J10 J11 F12 F4 J8 C1 D2 E2 F3 F2 F1 K7 M8 L8 K8
Pull-Up9 Pull-Up9 Pull-Up9 — — — — — — — — — — — —
Table 5. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group UART 2 Primary Function UCTS2 URTS2 URXD2 UTXD2 USB OTG MCF52259 ColdFire Microcontroller, Rev. 0 USB_DM USB_DP USB_VDD USB_VSS MiniFlexBus10 FB_ALE FB_AD[7:0] FB_AD[15:8] FB_AD[19:16] FB_CS0 FB_R/W FB_OE FB_D7 FB_D6 FB_D5 FB_D4 FB_D3 SecondaryF unction I2C_SCL1 I2C_SDA1 CANRX CANTX — — — — FB_CS1 — — — — — — CANRX CANTX I2C_SCL1 I2C_SDA1 USB_ VBUSD Tertiary Function USB_ VBUSCHG USB_ VBUSDIS — — — — — — — — — — — — — — — — — — Drive Quaternary Strength/ Function Control1 PUC3 PUC2 PUC1 PUC0 — — — — PAS2 PTE[7:0] PTF[7:0] PTG[3:0] PTG5 PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PDSR[27] PDSR[26] PDSR[25] PDSR[24] N/A N/A N/A N/A Low Low Low Low Low Low Low Low Low Low Low Low Wired OR Control — — — — Pull-up/ Pin on Pull-down2 144 MAPBGA — — — — E11 E10 C10 D10 H11 H12 J9 H9 K3 J1–J2; J6; K4; K6; L6; L7; M6 Pin on 144 LQFP 97 98 102 101 80 81 79 82 37 34–36; 53–57 Pin on 100 LQFP 64 65 69 68 57 58 56 59 — — — — — — — — — — — —
Family Configurations
26 Freescale Semiconductor
B2; C2–C4; 32–33; 2–6; D3; E3; J3–J4 136 B6; C5–C6; D6 M5 M4 B5 A5 A4 B4 B3 L4 130–133 52 45 137 138 139 140 1 46
Table 5. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group MiniFlexBus11 Primary Function FB_D2 FB_D1 FB_D0 Standby Voltage VDD12 MCF52259 ColdFire Microcontroller, Rev. 0 VSTBY VDD SecondaryF unction USB_ VBUSE SYNCA SYNCB — — Tertiary Function — — — — — Drive Quaternary Strength/ Function Control1 PTH0 PTG6 PTG7 — — Low Low Low N/A N/A N/A N/A — — Wired OR Control Pull-up/ Pin on Pull-down2 144 MAPBGA K5 L5 J5 J12 E5–E8; F5; G5; H5–7; J7 Pin on 144 LQFP 47 50 51 78 7; 20; 30; 48; 59; 92; 100; 115; 125; 135 8; 21; 31; 49; 60; 91; 99; 114; 124; 134 Pin on 100 LQFP — — — 55 1; 14; 24; 33; 36; 67; 82; 92 2; 15; 25; 34; 37; 66; 81; 91
Freescale Semiconductor 27
VSS
VSS
—
—
—
N/A
N/A
—
A1; A12; F6–8; G6–8; H8; M1; M2
1 2
The PDSR and PSSR registers are part of the GPIO module. All programmable signals default to 2mA drive in normal (single-chip) mode. All signals have a pull-up in GPIO mode. 3 I2C1 is multiplexed with specific pins of the QSPI, UART1, UART2, and Mini-FlexBus pin groups. 4 For primary and GPIO functions only. 5 Only when JTAG mode is enabled. 6 Has high drive strength in EZPort mode. 7 For secondary and GPIO functions only. 8 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended. 9 For GPIO functions, the Primary Function has pull-up control within the GPT module. 10 Available on 144-pin packages only. 11 Available on 144-pin packages only. 12 This list for power and ground does not include those dedicated power/ground pins included elsewhere, such as in the ADC. Family Configurations
Electrical Characteristics
2
Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the microcontroller unit, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module specifications.
2.1
Maximum Ratings
Table 6. Absolute Maximum Ratings1, 2
Rating Supply voltage Clock synthesizer supply voltage RAM standby supply voltage USB standby supply voltage Digital input voltage EXTAL pin voltage XTAL pin voltage Instantaneous maximum current Single pin limit (applies to all pins)4, 5 Operating temperature range (packaged) Storage temperature range
1 3
Symbol VDD VDDPLL VSTBY VDDUSB VIN VEXTAL VXTAL IDD TA (TL - TH) Tstg
Value –0.3 to +4.0 –0.3 to +4.0 +1.8 to 3.5 –0.3 to +4.0 –0.3 to +4.0 0 to 3.3 0 to 3.3 25 –40 to 85 or 0 to 706 –65 to 150
Unit V V V V V V V mA °C °C
2
3
4 5
6
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or VDD). Input must be current limited to the IDD value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and VDD. The power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in the external power supply going out of regulation. Ensure that the external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power (e.g., no clock). Depending on the packaging; see the orderable part number summary.
MCF52259 ColdFire Microcontroller, Rev. 0 28 Freescale Semiconductor
Electrical Characteristics
2.2
Current Consumption
Table 7. Typical Active Current Consumption Specifications
Characteristic Symbol IDD Typical1 Active (SRAM) 22 31 84 102 ISTBY — — 23 — — Typical1 Active (Flash) 30 45 100 118 Peak2 (Flash) 36 60 155 185 5 20 15 2 6
4
Unit mA
PLL @ 8 MHz PLL @ 16 MHz PLL @ 64 MHz PLL @ 80 MHz RAM standby supply current • Normal operation: VDD > VSTBY - 0.3 V • Standby operation: VDD < VSS + 0.5 V Analog supply current • Normal operation USB supply current PLL supply current
1
μA μA mA mA mA
IDDA IDDUSB IDDPLL
Tested at room temperature with CPU polling a status register. All clocks were off except the UART and CFM (when running from flash memory). 2 Peak current measured with all modules active, CPU polling a status register, and default drive strength with matching load. 3 Tested using Auto Power Down (APD), which powers down the ADC between conversions; ADC running at 4 MHz in Once Parallel mode with a sample rate of 3 kHz. 4 Tested with the PLL MFD set to 7 (max value). Setting the MFD to a lower value results in lower current consumption.
Table 8. Current Consumption in Low-Power Mode, Code From Flash Memory1,2,3
Mode Stop mode 3 (Stop 11)4 Stop mode 2 (Stop 10)4 9 9 21 23 10 10 32 36 8 MHz (Typ) 16 MHz (Typ) 64 MHz (Typ) 80 MHz (Typ) Unit Symbol
0.150 7.0 15 15 56 70 17 17 65 81 mA IDD
Stop mode 1 (Stop 01)4,5 Stop mode 0 (Stop Wait / Doze Run
1 2
00)5
All values are measured with a 3.30V power supply. Tests performed at room temperature. Refer to the Power Management chapter in the MCF52259 Reference Manual for more information on low-power modes. 3 CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 and CFM off before entering low-power mode. CLKOUT is disabled. 4 See the description of the Low-Power Control Register (LPCR) in the MCF52259 Reference Manual for more information on stop modes 0–3. 5 Results are identical to STOP 00 for typical values because they only differ by CLKOUT power consumption. CLKOUT is already disabled in this instance prior to entering low-power mode.
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 29
Electrical Characteristics
Table 9. Current Consumption in Low-Power Mode, Code From SRAM1,2,3
Mode Stop mode 3 (Stop 11)
4
8 MHz (Typ)
16 MHz (Typ)
64 MHz (Typ)
80 MHz (Typ)
Unit
Symbol
0.090 7 9 9 13 16 10 10 18 21 15 15 42 55 17 17 50 65 mA IDD
Stop mode 2 (Stop 10)4 Stop mode 1 (Stop 01) Stop mode 0 (Stop 00) Wait / Doze Run
1 2 4,5 5
All values are measured with a 3.30V power supply. Tests performed at room temperature. Refer to the Power Management chapter in the MCF52259 Reference Manual for more information on low-power modes. 3 CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 off before entering low-power mode. CLKOUT is disabled. Code executed from SRAM with flash memory shut off by writing 0x0 to the FLASHBAR register. 4 See the description of the Low-Power Control Register (LPCR) in the MCF52259 Reference Manual for more information on stop modes 0–3. 5 Results are identical to STOP 00 for typical values because they only differ by CLKOUT power consumption. CLKOUT is already disabled in this instance prior to entering low-power mode.
2.3
Thermal Characteristics
Table 10. Thermal Characteristics
Characteristic Symbol Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection — Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection — θJA θJA θJMA θJMA θJB θJC Ψjt Tj θJA θJA θJMA θJMA θJB θJC Ψjt Tj Value 531,2 301,3 431,3 261,3 164 95 26 105 447,8 351,9 351,3 29
1,3
Table 10 lists thermal resistance values.
Unit °C / W °C / W °C / W °C / W °C / W °C / W °C / W
oC
144 MAPBGA Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 144 LQFP Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
°C / W °C / W °C / W °C / W °C / W °C / W °C / W
oC
2310 711 2
12
105
MCF52259 ColdFire Microcontroller, Rev. 0 30 Freescale Semiconductor
Electrical Characteristics
Table 10. Thermal Characteristics (continued)
Characteristic 100 LQFP Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient, (@200 ft/min) Junction to ambient, (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
1
Symbol Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection — θJA θJA θJMA θJMA θJB θJC Ψjt Tj
Value 5313,14 391,15 42
1,3
Unit °C / W °C / W °C / W °C / W °C / W °C / W °C / W
o
331,3 25 9 2
16
17 18
105
C
θJA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 3 Per JEDEC JESD51-6 with the board JESD51-7) horizontal. 4 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 7θ JA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 8 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 9 Per JEDEC JESD51-6 with the board JESD51-7) horizontal. 10 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 11 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 12 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 13 θJA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 14 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 15 Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 31
Electrical Characteristics
16
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 17 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 18 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D × Θ JMA ) (1) Where: TA ΘJA PD PINT PI/O = ambient temperature, °C = package thermal resistance, junction-to-ambient, °C/W = PINT + PI/O = chip internal power, IDD × VDD, watts = power dissipation on input and output pins — user determined, watts
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K ÷ ( T J + 273 ° C ) Solving equations 1 and 2 for K gives: K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2)
2.4
Flash Memory Characteristics
Table 11. SGFM Flash Program and Erase Characteristics
(VDDF = 2.7 to 3.6 V) Parameter Symbol fsys(R)
2
The flash memory characteristics are shown in Table 11 and Table 12.
Min 0 0.15
Typ — —
Max 66.67 or 801 66.67 or 801
Unit MHz MHz
System clock (read only) System clock (program/erase)
1 2
fsys(P/E)
Depending on packaging; see Table 12. Refer to the flash memory section for more information
Table 12. SGFM Flash Module Life Characteristics
(VDDF = 2.7 to 3.6 V) Parameter Maximum number of guaranteed program/erase cycles1 before failure Symbol P/E Retention Value 10,000 10
2
Unit Cycles Years
Data retention at average operating temperature of 85°C
1 2
A program/erase cycle is defined as switching the bits from 1 → 0 → 1. Reprogramming of a flash memory array block prior to erase is not required.
MCF52259 ColdFire Microcontroller, Rev. 0 32 Freescale Semiconductor
Electrical Characteristics
2.5
ESD Protection
Table 13. ESD Protection Characteristics1, 2
Characteristics ESD target for Human Body Model ESD target for Machine Model HBM circuit description Symbol HBM MM Rseries C MM circuit description Rseries C Number of pulses per pin (HBM) • Positive pulses • Negative pulses Number of pulses per pin (MM) • Positive pulses • Negative pulses Interval of pulses
1
Value 2000 200 1500 100 0 200 1 1
Units V V Ω pF Ω pF —
— — — — —
— 3 3 1 sec
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
2.6
DC Electrical Specifications
Table 14. DC Electrical Specifications 1
Characteristic Symbol VDD VSTBY VIH VIL VHYS VLVD VLVDHYS Iin VOH VOL Min 3.0 3.0 0.7 × VDD VSS – 0.3 0.06 × VDD 2.15 60 –1.0 VDD – 0.5 — Max 3.6 3.5 4.0 0.35 × VDD — 2.3 120 1.0 — 0.5 Unit V V V V mV V mV μA V V
Supply voltage Standby voltage Input high voltage Input low voltage Input hysteresis Low-voltage detect trip voltage (VDD falling) Low-voltage detect hysteresis (VDD rising) Input leakage current Vin = VDD or VSS, digital pins Output high voltage (all input/output and all output pins) IOH = –2.0 mA Output low voltage (all input/output and all output pins) IOL = 2.0mA
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 33
Electrical Characteristics
Table 14. DC Electrical Specifications (continued)1
Characteristic Output high voltage (high drive) IOH = -5 mA Output low voltage (high drive) IOL = 5 mA Output high voltage (low drive) IOH = -2 mA Output low voltage (low drive) IOL = 2 mA Weak internal pull Up device current, tested at VIL Max.2 Input Capacitance 3 • All input-only pins • All input/output (three-state) pins
1 2
Symbol VOH VOL VOH VOL IAPU Cin
Min VDD – 0.5 — VDD - 0.5 — –10 — —
Max — 0.5 — 0.5 –130 7 7
Unit V V V V μA pF
Refer to Table 15 for additional PLL specifications. Refer to Table 4 for pins having internal pull-up devices. 3 This parameter is characterized before qualification rather than 100% tested.
2.7
Clock Source Electrical Specifications
Table 15. Oscillator and PLL Specifications
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Symbol fcrystal fext fref_pll fsys Min 0.5 0 2 0 fref / 32 100 1 — 2.0 VSS — 40 Max 48.0 50.0 or 60.0 10.0 66.67 or 803 66.67 or 803 1000 5 0.1 VDD V 0.8 500 60 μs % fref MHz MHz Unit MHz
Clock Source Frequency Range of EXTAL Frequency Range • Crystal • External1 PLL reference frequency range System frequency • External clock mode • On-chip PLL frequency Loss of reference frequency 4, 6 Self clocked mode frequency 5 Crystal start-up time
6, 7 2
fLOR fSCM tcst VIHEXT VILEXT tlpll tdc
kHz MHz ms V
EXTAL input high voltage • External reference EXTAL input low voltage • External reference PLL lock time4,8 Duty cycle of reference 4
MCF52259 ColdFire Microcontroller, Rev. 0 34 Freescale Semiconductor
Electrical Characteristics
Table 15. Oscillator and PLL Specifications (continued)
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Frequency un-LOCK range Frequency LOCK range CLKOUT period jitter , measured at fSYS Max • Peak-to-peak (clock edge to clock edge) • Long term (averaged over 2 ms interval) On-chip oscillator frequency
1 2 4, 5, 9 ,10
Symbol fUL fLCK Cjitter
Min –1.5 –0.75 — — 7.84
Max 1.5 0.75 10 .01 8.16
Unit % fref % fref % fsys MHz
foco
In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL. All internal registers retain data at 0 Hz. 3 Depending on packaging; see Table 12. 4 Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode. 5 Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f LOR with default MFD/RFD settings. 6 This parameter is characterized before qualification rather than 100% tested. 7 Proper PC board layout procedures must be followed to achieve specifications. 8 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. 10 Based on slow system clock of 40 MHz measured at f sys max.
2.8
USB Operation
Table 16. USB Operation Specifications
Characteristic Minimum core speed for USB operation Symbol fsys_USB_min Value 16 Unit MHz
2.9
Mini-FlexBus External Interface Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 35
Electrical Characteristics
Table 17. Mini-FlexBus AC Timing Specifications
Num Characteristic Frequency of Operation MB1 MB2 MB3 MB4 MB5
1 2
Min — 12.5 — 2 6 0
Max 80 — 8 — — —
Unit MHz ns ns ns ns ns
Notes
Clock Period Output Valid Output Hold Input Setup Input Hold
1 1 2 2
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE. Specification is valid for all MB_D[7:0].
MB_CLK
MB1 MB3
MB_A[19:X]
MB2
A[19:X]
MB5
MB_D[7:0] / MB_A[15:0] MB_R/W
ADDRESS
D[Y:0]
MB4
MB3
MB2
MB_ALE
MB_CSn
MB2 MB3
MB_OE
Figure 5. Mini-FlexBus Read Timing
MCF52259 ColdFire Microcontroller, Rev. 0 36 Freescale Semiconductor
Electrical Characteristics
MB_CLK
MB1 MB3
MB_A[19:X]
MB2
A[19:X]
MB_D[7:0] / MB_A[15:0]
ADDRESS
DATA[Y:0]
MB_R/W
MB3 MB2
MB_ALE
MB_CSn
MB2 MB3
MB_OE
Figure 6. Mini-FlexBus Write Timing
2.10
Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface.
2.10.1
Receive Signal Timing Specifications
Table 18. Receive Signal Timing
MII Mode
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
Num — E1 E2 E3 E4
1
Characteristic Min RXCLK frequency RXD[n:0], RXDV, RXER to RXCLK setup1 RXCLK to RXD[n:0], RXDV, RXER hold RXCLK pulse width high RXCLK pulse width low
1
Unit Max 25 — — 65% 65% MHz ns ns RXCLK period RXCLK period — 5 5 35% 35%
In MII mode, n = 3
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 37
Electrical Characteristics
RXCLK (Input)
E4
E3
E1
E2
RXD[n:0] RXDV, RXER
Valid Data
Figure 7. MII Receive Signal Timing Diagram
2.10.2
Transmit Signal Timing Specifications
Table 19. Transmit Signal Timing
MII Mode Num — E5 E6 E7 E8 TXCLK frequency TXCLK to TXD[n:0], TXEN, TXER invalid1 TXCLK to TXD[n:0], TXEN, TXER TXCLK pulse width high TXCLK pulse width low valid1 Characteristic Min — 5 — 35% 35% Max 25 — 25 65% 65% MHz ns ns tTXCLK tTXCLK Unit
1
In MII mode, n = 3
TXCLK (Input)
E6
E8
E7 E5
TXD[n:0] TXEN, TXER
Valid Data
Figure 8. MII Transmit Signal Timing Diagram
2.10.3
Num E9
Asynchronous Input Signal Timing Specifications
Table 20. MII Transmit Signal Timing
Characteristic CRS, COL minimum pulse width Min 1.5 Max — Unit TXCLK period
CRS, COL
E9
Figure 9. MII Async Inputs Timing Diagram
MCF52259 ColdFire Microcontroller, Rev. 0 38 Freescale Semiconductor
Electrical Characteristics
2.10.4
MII Serial Management Timing Specifications
Table 21. MII Serial Management Channel Signal Timing
Characteristic MDC cycle time MDC pulse width MDC to MDIO output valid MDC to MDIO output invalid MDIO input to MDC setup MDIO input to MDC hold
E10 E11
Num E10 E11 E12 E13 E14 E15
Symbol tMDC
Min 400 40 — 25 10 0
Max — 60 375 — — —
Unit ns % tMDC ns ns ns ns
MDC (Output)
E11 E12 E13
MDIO (Output)
Valid Data
E14
E15
MDIO (Input)
Valid Data
Figure 10. MII Serial Management Channel TIming Diagram
2.11
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, Interrupt and USB interfaces. When in GPIO mode, the timing specification for these pins is given in Table 22 and Figure 11. The GPIO timing is met under the following load test conditions: • • 50 pF / 50 Ω for high drive 25 pF / 25 Ω for low drive Table 22. GPIO Timing
NUM G1 G2 G3 G4 Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min — 1.5 9 1.5 Max 10 — — — Unit ns ns ns ns
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 39
Electrical Characteristics
CLKOUT
G1 G2
GPIO Outputs
G3
G4
GPIO Inputs
Figure 11. GPIO Timing
2.12
Reset Timing
Table 23. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM R1 R2 R3 R4
1 2
Characteristic RSTI input valid to CLKOUT High CLKOUT High to RSTI Input invalid RSTI input valid time
2
Symbol tRVCH tCHRI tRIVT tCHROV
Min 9 1.5 5 —
Max — — — 10
Unit ns ns tCYC ns
CLKOUT High to RSTO Valid
All AC timing is shown with respect to 50% VDD levels unless otherwise noted. During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the system. Thus, RSTI must be held a minimum of 100 ns.
CLKOUT
1R1 R2 R3 R4 R4
RSTI
RSTO
Figure 12. RSTI and Configuration Override Timing
2.13
I2C Input/Output Timing Specifications
Table 24 lists specifications for the I2C input timing parameters shown in Figure 13.
MCF52259 ColdFire Microcontroller, Rev. 0 40 Freescale Semiconductor
Electrical Characteristics
Table 24. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num 11 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 × tCYC 8 × tCYC — 0 — 4 × tCYC 0 2 × tCYC 2 × tCYC Max — — 1 — 1 — — — — Units ns ns ms ns ms ns ns ns ns
Table 25 lists specifications for the I2C output timing parameters shown in Figure 13. Table 25. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num 111 I2
1
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 × tCYC 10 × tCYC — 7 × tCYC — 10 × tCYC 2 × tCYC 20 × tCYC 10 × tCYC
Max — — — — 3 — — — —
Units ns ns μs ns ns ns ns ns ns
I32 I41 I53 I61 I71 I8
1
I91
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 25. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 25 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
MCF52259 ColdFire Microcontroller, Rev. 0 Freescale Semiconductor 41
Electrical Characteristics
Figure 13 shows timing for the values in Table 24 and Table 25.
I2 SCL I6 I5
I1
I4
I7
I8
I3
I9
SDA
Figure 13. I2C Input/Output Timings
2.14
Analog-to-Digital Converter (ADC) Parameters
Table 26. ADC Parameters1
Table 26 lists specifications for the analog-to-digital converter.
Name VREFL VREFH VDDA VADIN RES INL INL DNL
Characteristic Low reference voltage High reference voltage ADC analog supply voltage Input voltages Resolution Integral non-linearity (full input signal range)2 Integral non-linearity (10% to 90% input signal range)4 Differential non-linearity Monotonicity
Min VSSA VDDA - 50 mV 3.1 VREFL 12 — — —
Typical — — 3.3 — — ±2.5 ±2.5 –1 < DNL < +1
Max VSSA + 50 mV VDDA 3.6 VREFH 12 ±3 ±3
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