MCF5483

Freescale Semiconductor Data Sheet Document Number: MCF5485EC Rev. 4, 12/2007 MCF548x ColdFire® Microprocessor Supports MCF5480, MCF5481, MCF5482, MCF5483, MCF5484, and MCF5485 Features list: • ColdFire V4e Core – Limited superscalar V4 ColdFire processor core – Up to 200MHz peak internal core frequency (308 MIPS [Dhrystone 2.1] @ 200 MHz) – Harvard architecture – 32-Kbyte instruction cache – 32-Kbyte data cache – Memory Management Unit (MMU) – Separate, 32-entry, fully-associative instruction and data translation lookahead buffers – Floating point unit (FPU) – Double-precision conforms to IEE-754 standard – Eight floating point registers • Internal master bus (XLB) arbiter – High performance split address and data transactions – Support for various parking modes • 32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller – 66–133 MHz operation – Supports DDR and SDR DRAM – Built-in initialization and refresh – Up to four chip selects enabling up to one GB of external memory • Version 2.2 peripheral component interconnect (PCI) bus – 32-bit target and initiator operation – Support for up to five external PCI masters – 33–66 MHz operation with PCI bus to XLB divider ratios of 1:1, 1:2, and 1:4 • Flexible multi-function external bus (FlexBus) – Provides a glueless interface to boot flash/ROM, SRAM, and peripheral devices – Up to six chip selects – 33 – 66 MHz operation • Communications I/O subsystem – Intelligent 16 channel DMA controller – Up to two 10/100 Mbps fast Ethernet controllers (FECs) each with separate 2-Kbyte receive and transmit FIFOs – Universal serial bus (USB) version 2.0 device controller – Support for one control and six programmable MCF548x TEPBGA–388 27 mm x 27 mm • • • • • • • endpoints, interrupt, bulk, or isochronous – 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM – Integrated physical layer interface – Up to four programmable serial controllers (PSCs) each with separate 512-byte receive and transmit FIFOs for UART, USART, modem, codec, and IrDA 1.1 interfaces – I2C peripheral interface – Two FlexCAN controller area network 2.0B controllers each with 16 message buffers – DMA Serial Peripheral Interface (DSPI) Optional Cryptography accelerator module – Execution units for: – DES/3DES block cipher – AES block cipher – RC4 stream cipher – MD5/SHA-1/SHA-256/HMAC hashing – Random Number Generator 32-Kbyte system SRAM – Arbitration mechanism shares bandwidth between internal bus masters System integration unit (SIU) – Interrupt controller – Watchdog timer – Two 32-bit slice timers alarm and interrupt generation – Up to four 32-bit general-purpose timers, compare, and PWM capability – GPIO ports multiplexed with peripheral pins Debug and test features – ColdFire background debug mode (BDM) port – JTAG/ IEEE 1149.1 test access port PLL and clock generator – 30 to 66.67 MHz input frequency range Operating Voltages – 1.5V internal logic – 2.5V DDR SDRAM bus I/O – 3.3V PCI, FlexBus, and all other I/O Estimated power consumption – Less than 1.5W (388 PBGA) © Freescale Semiconductor, Inc., 2007. All rights reserved. Table of Contents 1 2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4 2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .6 4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.2 Supply Voltage Sequencing and Separation Cautions . .6 4.3 General USB Layout Guidelines . . . . . . . . . . . . . . . . . . .8 4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10 PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12 FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 9.1 SDR SDRAM AC Timing Characteristics . . . . . . . . . . .15 9.2 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18 PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . .22 11.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .22 11.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .23 11.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24 11.4 MII Serial Management Channel Timing (MDIO,MDC).24 General Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . .25 I2C Input/Output Timing Specifications. . . . . . . . . . . . . . . . . .25 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . .26 DSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .29 Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . .29 Case Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 15.DDR Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . Figure 16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18.PCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19.MII Receive Signal Timing Diagram. . . . . . . . . . . . . . Figure 20.MII Transmit Signal Timing Diagram . . . . . . . . . . . . . Figure 21.MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . Figure 22.MII Serial Management Channel TIming Diagram. . . Figure 23.I2C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . Figure 24.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . Figure 25.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . Figure 26.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . Figure 27.TRST Timing Debug AC Timing Specifications . . . . . Figure 28.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . . Figure 29.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . Figure 30.DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 31.388-pin BGA Case Outline. . . . . . . . . . . . . . . . . . . . . 18 20 21 22 23 23 24 24 26 27 27 27 27 28 28 29 31 3 4 5 6 7 8 9 10 11 List of Tables Table 1. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 3. Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 4. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . 5 Table 5. USB Filter Circuit Values . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. I/O Driver Capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Clock Timing Specifications. . . . . . . . . . . . . . . . . . . . . 11 Table 8. MCF548x Divide Ratio Encodings. . . . . . . . . . . . . . . . 11 Table 9. Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . 12 Table 10.FlexBus AC Timing Specifications. . . . . . . . . . . . . . . . 13 Table 11.SDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 16 Table 12.DDR Clock Crossover Specifications . . . . . . . . . . . . . 18 Table 13.DDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 18 Table 14.PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 21 Table 15.MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . 23 Table 16.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 23 Table 17.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 24 Table 18.MII Serial Management Channel Signal Timing . . . . . 24 Table 19.General AC Timing Specifications . . . . . . . . . . . . . . . . 25 Table 20.I2C Input Timing Specifications between SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 21. I2C Output Timing Specifications between SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 22.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 26 Table 23.Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 28 Table 24.DSPI Modules AC Timing Specifications. . . . . . . . . . . 29 Table 25.Timer Module AC Timing Specifications . . . . . . . . . . . 29 12 13 14 15 16 17 18 List of Figures Figure 1. MCF548X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. System PLL VDD Power Filter . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Supply Voltage Sequencing and Separation Cautions . 7 Figure 4. Preferred VBUS Connections . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Alternate VBUS Connections . . . . . . . . . . . . . . . . . . . . 8 Figure 6. USB VDD Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. USBRBIAS Connection. . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 11 Figure 9. CLKIN, Internal Bus, and Core Clock Ratios . . . . . . . 11 Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14.SDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MCF548x ColdFire® Microprocessor, Rev. 4 2 Freescale Semiconductor ColdFire V4e Core FPU, MMU EMAC 32K D-cache 32K I-Cache PLL DDR SDRAM Interface FlexBus Interface XL Bus Arbiter XL Bus Master/Slave Interface Cryptography Accelerator*** Crypto R/W Memory Controller FlexBus Controller Interrupt Controller Watchdog Timer Slice Timers x 2 GP PCI 2.2 Controller Perpheral I/O Interface & Ports Slave Timers x 4 Bus 32K System SRAM Read Write DMA DMA XL Bus Read/Write FlexCAN x2 Multi-Channel DMA Master Bus Interface & FIFOs CommBus PCI Interface & FIFOs DSPI I2C PSC x 4 FEC1 FEC2** USB 2.0 DEVICE* Perpheral Communications I/O Interface & Ports USB 2.0 PHY* Figure 1. MCF548X Block Diagram MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 3 PCI I/O Interface & Ports Communications I/O Subsystem System Integration Unit Maximum Ratings 1 Maximum Ratings Table 1. Absolute Maximum Ratings Rating External (I/O pads) supply voltage (3.3-V power pins) Internal logic supply voltage Memory (I/O pads) supply voltage (2.5-V power pins) PLL supply voltage Internal logic supply voltage, input voltage level Storage temperature range Symbol EVDD IVDD SD VDD PLL VDD Vin Tstg Value –0.3 to +4.0 –0.5 to +2.0 –0.3 to +4.0 SDR Memory –0.3 to +2.8 DDR Memory –0.5 to +2.0 –0.5 to +3.6 –55 to +150 Units V V V V V oC Table 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of these ranges may cause erratic behavior or damage to the processor. 2 2.1 Thermal Characteristics Operating Temperatures Table 2. Operating Temperatures Characteristic Maximum operating junction temperature Maximum operating ambient temperature Minimum operating ambient temperature 1 Table 2 lists junction and ambient operating temperatures. Symbol Tj TAmax TAmin Value 105 DQS) Relative to DQS (DDR Write Mode) (tQS) Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS (DDR Write Mode) (tQH) Input Data Skew Relative to DQS (Input Setup) (tIS) Input Data Hold Relative to DQS (tIH) DQS falling edge to SDCLK rising (output setup time) (tDSS) DQS falling edge from SDCLK rising (output hold time) (tDSH) 0.25 × SDCLK + 0.5ns 0.5 0.5 Min 501 7.52 0.45 0.45 — 2.0 — 1.0 1.0 Max 133 12 0.55 0.55 0.5 × SDCLK + 1.0 ns — 1.25 — — 1 — — — Unit MHz ns SDCLK SDCLK ns ns SDCLK ns ns ns ns ns ns 7 8 9 Notes 2 3 4 5 6 10 11 MCF548x ColdFire® Microprocessor, Rev. 4 18 Freescale Semiconductor SDRAM Bus Table 13. DDR Timing Specifications (continued) Symbol DD13 DD14 DD15 DD16 1 2 Characteristic DQS input read preamble width (tRPRE) DQS input read postamble width (tRPST) DQS output write preamble width (tWPRE) DQS output write postamble width (tWPST) Min 0.9 0.4 0.25 0.4 Max 1.1 0.6 — 0.6 Unit SDCLK SDCLK SDCLK SDCLK Notes DDR memories typically have a minimum speed specification of 83 MHz. Check memory component specifications to verify. The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x Reference Manual. 3 SDCLK is one memory clock in (ns). 4 Pulse width high plus pulse width low cannot exceed max clock period. 5 Pulse width high plus pulse width low cannot exceed max clock period. 6 Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process, temperature, and voltage variations. 7 This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 8 The first data beat is valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data beats is valid for each subsequent SDDQS edge. 9 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 10 Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 11 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid. MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 19 SDRAM Bus DD1 SDCLK0 DD3 SDCLK1 DD2 SDCLK0 SDCLK1 DD5 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] ROW COL DD7 SDDM DD8 SDDQS DD7 SDDATA WD1 WD2 WD3 WD4 DD8 CMD DD6 Figure 16. DDR Write Timing MCF548x ColdFire® Microprocessor, Rev. 4 20 Freescale Semiconductor PCI Bus DD1 SDCLK0 DD3 SDCLK1 DD2 SDCLK0 SDCLK1 DD5 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] ROW COL DQS Read Preamble DD10 SDDATA WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble WD1 WD2 WD3 WD4 SDDATA DD9 DQS Read Postamble CMD CL=2.5 CL=2 SDDQS SDDQS Figure 17. DDR Read Timing 10 PCI Bus Table 14. PCI Timing Specifications Num Frequency of Operation P1 P2 P3 P4 P5 P6 Clock Period (tCK) Address, Data, and Command (33< PCI ≤ 50 Mhz)—Input Setup (tIS) Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (tIS) Address, Data, and Command (33–50 Mhz)—Output Valid (tDV) Address, Data, and Command (0–33 Mhz) - Output Valid (tDV) PCI signals (0–50 Mhz) - Output Hold (tDH) Characteristic Min 25 20 3.0 7.0 — — 0 Max 50 40 — — 6.0 11.0 — Unit MHz ns ns ns ns ns ns 4 3 The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis. Notes 1 2 MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 21 Fast Ethernet AC Timing Specifications Table 14. PCI Timing Specifications (continued) Num P7 P8 P9 P10 P11 P12 1 Characteristic PCI signals (0–50 Mhz) - Input Hold (tIH) PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Output valid (tDV) PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (tDV) PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Input Setup (tIS) PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (tIS) PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (tIS) Min 0 — — — 12 10 Max — 6 12 5 — — Unit ns ns ns ns ns ns Notes 5 6 2 3 4 5 6 Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x Reference Manual. Also specific guidelines may need to be followed when operating the system PLL below certain frequencies. Max cycle rate is determined by CLKIN and how the user has the system PLL configured. All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals. PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it is not required or guaranteed. PCI 2.2 spec requires zero input hold. These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec. P1 CLKIN P4 Output Valid/Hold P6 Output Valid P2 Input Setup/Hold Input Valid P7 Figure 18. PCI Timing 11 11.1 Fast Ethernet AC Timing Specifications MII/7-WIRE Interface Timing Specs The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the EMAC_10_100 I/O signals. The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver. MCF548x ColdFire® Microprocessor, Rev. 4 22 Freescale Semiconductor Fast Ethernet AC Timing Specifications Table 15. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic RXD[3:0], RXDV, RXER to RXCLK setup RXCLK to RXD[3:0], RXDV, RXER hold RXCLK pulse width high RXCLK pulse width low Min 5 5 35% 35% Max — — 65% 65% Unit ns ns RXCLK period RXCLK period M3 RXCLK (Input) M1 RXD[3:0] (Inputs) RXDV, RXER M2 M4 Figure 19. MII Receive Signal Timing Diagram 11.2 MII Transmit Signal Timing Table 16. MII Transmit Signal Timing Num M5 M6 M7 M8 Characteristic TXCLK to TXD[3:0], TXEN, TXER invalid TXCLK to TXD[3:0], TXEN, TXER valid TXCLK pulse width high TXCLK pulse width low Min 0 — 35% 35% Max — 25 65% 65% Unit ns ns TXCLK period TXCLK period M7 TXCLK (Input) M5 TXD[3:0] (Outputs) TXEN, TXER M6 M8 Figure 20. MII Transmit Signal Timing Diagram MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 23 Fast Ethernet AC Timing Specifications 11.3 MII Async Inputs Signal Timing (CRS, COL) Table 17. MII Transmit Signal Timing Num M9 Characteristic CRS, COL minimum pulse width Min 1.5 Max — Unit TX_CLK period CRS, COL M9 Figure 21. MII Async Inputs Timing Diagram 11.4 MII Serial Management Channel Timing (MDIO,MDC) Table 18. MII Serial Management Channel Signal Timing Num M10 M11 M12 M13 M14 M15 Characteristic MDC falling edge to MDIO output invalid (min prop delay) MDC falling edge to MDIO output valid (max prop delay) MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width high MDC pulse width low Min 0 — 10 0 40% 40% Max — 25 — — 60% 60% Unit ns ns ns ns MDC period MDC period M14 MDC (Output) M10 MDIO (Output) M12 MDIO (Input) M13 M15 M11 Figure 22. MII Serial Management Channel TIming Diagram MCF548x ColdFire® Microprocessor, Rev. 4 24 Freescale Semiconductor General Timing Specifications 12 General Timing Specifications Table 19. General AC Timing Specifications Table 19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts. Name G1 G2 G3 Characteristic CLKIN high to signal output valid CLKIN high to signal invalid (output hold) Signal input pulse width Min — 0 2 Max 2 — — Unit PSTCLK ns PSTCLK 13 I2C Input/Output Timing Specifications Table 20. I2C Input Timing Specifications between SCL and SDA Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 — 0 — 4 0 2 2 Max — — 1 — 1 — — — — Units Bus clocks Bus clocks mS ns mS Bus clocks ns Bus clocks Bus clocks Table 20 lists specifications for the I2C input timing parameters shown in Figure 23. Table 21 lists specifications for the I2C output timing parameters shown in Figure 23. Table 21. I2C Output Timing Specifications between SCL and SDA Num I1 1 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 6 10 — 7 — 10 2 20 10 Max — — — — 3 — — — — Units Bus clocks Bus clocks µS Bus clocks ns Bus clocks Bus clocks Bus clocks Bus clocks I2 1 I3 2 I4 1 I5 3 I6 1 I7 1 I8 1 I9 1 MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 25 JTAG and Boundary Scan Timing 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 21. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 21 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 23 shows timing for the values in Table 20 and Table 21. I2 I6 SCL I1 I4 SDA I7 I8 I3 I9 I5 Figure 23. I2C Input/Output Timings 14 Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 1 JTAG and Boundary Scan Timing Table 22. JTAG and Boundary Scan Timing Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 2 15.15 0.0 5.0 24.0 0.0 0.0 5.0 10.0 0.0 0.0 100.0 10.0 Max 10 — — 3.0 — — 15.0 15.0 — — 20.0 15.0 — — Unit MHz tCK ns ns ns ns ns ns ns ns ns ns ns ns MTMOD is expected to be a static signal. Hence, it is not associated with any timing MCF548x ColdFire® Microprocessor, Rev. 4 26 Freescale Semiconductor JTAG and Boundary Scan Timing J2 J3 TCLK (Input) VIH VIL J4 J4 J3 Figure 24. Test Clock Input Timing TCLK VIH 5 Data Inputs 7 Data Outputs 8 Data Outputs 7 Data Outputs Output Data Valid Output Data Valid 6 VIL Input Data Valid Figure 25. Boundary Scan (JTAG) Timing TCLK VIH 9 TDI, TMS, BKPT 11 TDO 12 TDO 11 TDO Output Data Valid Output Data Valid 10 VIL Input Data Valid Figure 26. Test Access Port Timing TCLK 14 TRST 13 Figure 27. TRST Timing Debug AC Timing Specifications MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 27 JTAG and Boundary Scan Timing Table 23 lists specifications for the debug AC timing parameters shown in Figure 29. Table 23. Debug AC Timing Specifications 50 MHz Num D1 D2 D3 D4 1 Characteristic Min PSTDDATA to PSTCLK setup PSTCLK to PSTDDATA hold DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time 4.5 4.5 1 4 5 Max — — — — — Units ns ns PSTCLKs PSTCLKs PSTCLKs D5 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. Figure 28 shows real-time trace timing for the values in Table 23. PSTCLK D1 PSTDDATA[7:0] D2 Figure 28. Real-Time Trace AC Timing Figure 29 shows BDM serial port AC timing for the values in Table 23. D5 DSCLK D3 DSI Current D4 DSO Past Current Next Figure 29. BDM Serial Port AC Timing MCF548x ColdFire® Microprocessor, Rev. 4 28 Freescale Semiconductor DSPI Electrical Specifications 15 DSPI Electrical Specifications Table 24. DSPI Modules AC Timing Specifications Table 24 lists DSPI timings. Name DS1 DS2 DS3 DS4 DS5 DSPI_CS[3:0] to DSPI_CLK Characteristic Min 1 × tck — 2 10 10 Max 510 × tck 12 — — — Unit ns ns ns ns ns DSPI_CLK high to DSPI_DOUT valid. DSPI_CLK high to DSPI_DOUT invalid. (Output hold) DSPI_DIN to DSPI_CLK (Input setup) DSPI_DIN to DSPI_CLK (Input hold) The values in Table 24 correspond to Figure 30. DSPI_CS[3:0] DS1 DSPI_CLK DS2 DSPI_DOUT DS3 DSPI_DIN DS4 DS5 Figure 30. DSPI Timing 16 Timer Module AC Timing Specifications Table 25. Timer Module AC Timing Specifications 0–50 MHz Name T1 T2 Characteristic Min TIN0 / TIN1 / TIN2 / TIN3 cycle time TIN0 / TIN1 / TIN2 / TIN3 pulse width 3 1 Max — — PSTCLK PSTCLK Unit Table 25 lists timer module AC timings. MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 29 Case Drawing 17 Case Drawing MCF548x ColdFire® Microprocessor, Rev. 4 30 Freescale Semiconductor Case Drawing Figure 31. 388-pin BGA Case Outline MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 31 Revision History 18 Revision History Revision Number 2.2 2.3 2.4 Date August 29, 2005 August 30, 2005 December 14, 2005 Substantive Changes Table 7: Changed C1 minimum spec from 15.15 ns to 20 ns and maximum spec from 33.3 ns to 40 ns. Table 22: Changed J11 maximum from 15 ns to 20 ns. Table 9: Changed heading maximum from 66 MHz to 50 MHz. Table 10: Changed frequency of operation maximum from 66 MHz to 50 MHz and corresponding FB1 minimum from 15.15 ns to 20 ns. Table 10: Changed FB1 maximum from 33.33 ns to 40 ns. Table 14: Changed frequency of operation maximum from 66 MHz to 50 MHz and corresponding FB1 minimum from 15.15 ns to 20 ns. Table 14: Changed FB1 maximum from 33.33 ns to 40 ns. Table 14: Changed various entry descriptions from “(33 < PCI ≤ 66 Mhz)” to (33< PCI ≤ 50 Mhz) Table 23: Changed heading maximum from 66 MHz to 50 MHz. Table 25: Changed heading maximum from 66 MHz to 50 MHz. Table 4: Updated DC electrical specifications, VIL and VIH. Table 6: Changed FlexBus output load from 20pF to 30pF. Added Section 4.3, “General USB Layout Guidelines.” Figure 2: Changed resistor value from 10W to 10Ω Figure 3: Changed note 1 in from “IVDD should not exceed EVDD, SD VDD or PLL VDD by more than 0.4V...” to “IVDD should not exceed EVDD or SD VDD by more than 0.4V...” Table 3: Updated thermal information for θJMA, θJB, and θJC Table 4: Added input leakage current spec. Table 6: Added footnote regarding pads having balanced source & sink current. Table 9: Added RSTI pulse duration spec. Added features list, pinout drawing, block diagram, and case outline. 3 February 20, 2007 4 December 4, 2007 MCF548x ColdFire® Microprocessor, Rev. 4 32 Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 33 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. All rights reserved. D ocument Number: MCF5485EC Rev. 4 12/2007