MCF548X

Freescale Semiconductor Data Sheet MCF5485EC Rev. 2.4, 12/2005 MCF548x Integrated Microprocessor Electrical Characteristics Applies to the MCF5480, MCF5481, MCF5482, MCF5483, MCF5484, and MCF5485 This chapter contains electrical specification tables and reference timing diagrams for the MCF548x microprocessor. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF548x. NOTE The parameters specified in this MPU document supersede any values found in the module specifications. Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Maximum Ratings................................................1 Thermal Characteristics ......................................2 DC Electrical Specifications ................................3 Supply Voltage Sequencing and Separation Cautions ..............................................................5 Output Driver Capability and Loading .................6 PLL Timing Specifications ...................................7 Reset Timing Specifications ................................8 FlexBus................................................................8 SDRAM Bus ......................................................11 PCI Bus .............................................................17 Fast Ethernet AC Timing Specifications ............18 General Timing Specifications...........................21 I2C Input/Output Timing Specifications .............21 JTAG and Boundary Scan Timing .....................22 DSPI Electrical Specifications ...........................25 Timer Module AC Timing Specifications............25 Revision History ................................................26 1 Maximum Ratings Table 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of these ranges may cause erratic behavior or damage to the processor. © Freescale Semiconductor, Inc., 2004. All rights reserved. Thermal Characteristics Table 1. Absolute Maximum Ratings Rating External (I/O pads) supply voltage (3.3-V power pins) Internal logic supply voltage Memory (I/O pads) supply voltage (2.5-V power pins) PLL supply voltage Internal logic supply voltage, input voltage level Storage temperature range Symbol EVDD IVDD SD VDD PLL VDD Vin Tstg Value –0.3 to +4.0 –0.5 to +2.0 –0.3 to +4.0 SDR Memory –0.3 to +2.8 DDR Memory –0.5 to +2.0 –0.5 to +3.6 –55 to +150 Units V V V V V o C 2 2.1 Thermal Characteristics Operating Temperatures Table 2. Operating Temperatures Characteristic Maximum operating junction temperature Maximum operating ambient temperature Minimum operating ambient temperature Symbol Tj TAmax TAmin Value 105 DQS) Relative to DQS (DDR Write Mode) (tQS) Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS (DDR Write Mode) (tQH) Input Data Skew Relative to DQS (Input Setup) (tIS) Input Data Hold Relative to DQS (tIH) DQS falling edge to SDCLK rising (output setup time) (tDSS) DQS falling edge from SDCLK rising (output hold time) (tDSH) DQS input read preamble width (tRPRE) DQS input read postamble width (tRPST) DQS output write preamble width (tWPRE) DQS output write postamble width (tWPST) 0.25 × SDCLK + 0.5ns 0.5 0.5 0.9 0.4 0.25 0.4 Min 501 7.52 0.45 0.45 — 2.0 — 1.0 1.0 Max 133 12 0.55 0.55 0.5 × SDCLK + 1.0 ns — 1.25 — — 1 — — — 1.1 0.6 — 0.6 Unit MHz ns SDCLK SDCLK ns ns SDCLK ns ns ns ns ns ns SDCLK SDCLK SDCLK SDCLK 7 8 9 Notes 2 3 4 5 6 10 11 NOTES: 1 Note that DDR memories typically have a minimum speed specification of 83 MHz. Check with memory component specifications to verify. 2 The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x Reference Manual. 3 SDCLK is one memory clock in (ns). 4 Pulse width high plus pulse width low cannot exceed max clock period. 5 Pulse width high plus pulse width low cannot exceed max clock period. 6 Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process, temperature, and voltage variations. 7 This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 15 SDRAM Bus 8 The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data beats will be valid for each subsequent SDDQS edge. 9 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 10 Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 11 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid. DD1 SDCLK0 DD2 DD3 SDCLK1 SDCLK0 SDCLK1 DD5 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] CMD DD6 ROW COL DD7 SDDM DD8 SDDQS DD7 SDDATA WD1 WD2 WD3 WD4 DD8 Figure 12. DDR Write Timing MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 16 Freescale Semiconductor PCI Bus DD1 SDCLK0 DD2 DD3 SDCLK1 SDCLK0 SDCLK1 DD5 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] CL=2 CMD CL=2.5 ROW COL DQS Read Preamble DD10 DD9 SDDQS DQS Read Postamble SDDATA SDDQS WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble WD1 WD2 WD3 WD4 SDDATA Figure 13. DDR Read Timing 10 PCI Bus Table 14. PCI Timing Specifications Num Frequency of Operation P1 P2 P3 P4 P5 Clock Period (tCK) Address, Data, and Command (33< PCI ≤ 50 Mhz)—Input Setup (tIS) Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (tIS) Address, Data, and Command (33–50 Mhz)—Output Valid (tDV) Address, Data, and Command (0–33 Mhz) - Output Valid (tDV) Characteristic Min 25 20 3.0 7.0 — — Max 50 40 — — 6.0 11.0 Unit MHz ns ns ns ns ns 3 The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis. Notes 1 2 MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 17 Fast Ethernet AC Timing Specifications Table 14. PCI Timing Specifications (continued) Num P6 P7 P8 P9 P10 P11 P12 1 Characteristic PCI signals (0–50 Mhz) - Output Hold (tDH) PCI signals (0–50 Mhz) - Input Hold (tIH) PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Output valid (tDV) PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (tDV) PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Input Setup (tIS) PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (tIS) PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (tIS) Min 0 0 — — — 12 10 Max — — 6 12 5 — — Unit ns ns ns ns ns ns ns Notes 4 5 6 NOTES: Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x Reference Manual. Also specific guidelines may need to be followed when operating the system PLL below certain frequencies. 2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured. 3 All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals. 4 PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it is not required or guaranteed. 5 PCI 2.2 spec requires zero input hold. 6 These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec. P1 CLKIN P4 P6 Output Valid/Hold Output Valid P2 Input Setup/Hold Input Valid P7 Figure 14. PCI Timing 11 Fast Ethernet AC Timing Specifications 11.1 MII/7-WIRE Interface Timing Specs The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the EMAC_10_100 I/O signals. MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 18 Freescale Semiconductor Fast Ethernet AC Timing Specifications The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver. Table 15. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic RXD[3:0], RXDV, RXER to RXCLK setup RXCLK to RXD[3:0], RXDV, RXER hold RXCLK pulse width high RXCLK pulse width low Min 5 5 35% 35% Max — — 65% 65% Unit ns ns RXCLK period RXCLK period M3 RXCLK (Input) M1 RXD[3:0] (Inputs) RXDV, RXER M2 M4 Figure 15. MII Receive Signal Timing Diagram 11.2 MII Transmit Signal Timing Table 16. MII Transmit Signal Timing Num M5 M6 M7 M8 Characteristic TXCLK to TXD[3:0], TXEN, TXER invalid TXCLK to TXD[3:0], TXEN, TXER valid TXCLK pulse width high TXCLK pulse width low Min 0 — 35% 35% Max — 25 65% 65% Unit ns ns TXCLK period TXCLK period M7 TXCLK (Input) M5 TXD[3:0] (Outputs) TXEN, TXER M6 M8 Figure 16. MII Transmit Signal Timing Diagram MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 19 Fast Ethernet AC Timing Specifications 11.3 MII Async Inputs Signal Timing (CRS, COL) Table 17. MII Transmit Signal Timing Num M9 Characteristic CRS, COL minimum pulse width Min 1.5 Max — Unit TX_CLK period CRS, COL M9 Figure 17. MII Async Inputs Timing Diagram 11.4 MII Serial Management Channel Timing (MDIO,MDC) Table 18. MII Serial Management Channel Signal Timing Num M10 M11 M12 M13 M14 M15 Characteristic MDC falling edge to MDIO output invalid (min prop delay) MDC falling edge to MDIO output valid (max prop delay) MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width high MDC pulse width low Min 0 — 10 0 40% 40% Max — 25 — — 60% 60% Unit ns ns ns ns MDC period MDC period M14 MDC (Output) M10 MDIO (Output) M12 MDIO (Input) M13 M15 M11 Figure 18. MII Serial Management Channel TIming Diagram MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 20 Freescale Semiconductor General Timing Specifications 12 General Timing Specifications Table 19. General AC Timing Specifications Table 19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts. Name G1 G2 G3 Characteristic CLKIN high to signal output valid CLKIN high to signal invalid (output hold) Signal input pulse width Min — 0 2 Max 2 — — Unit PSTCLK ns PSTCLK 13 I2C Input/Output Timing Specifications Table 20. I2C Input Timing Specifications between SCL and SDA Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 — 0 — 4 0 2 2 Max — — 1 — 1 — — — — Units Bus clocks Bus clocks mS ns mS Bus clocks ns Bus clocks Bus clocks Table 20 lists specifications for the I2C input timing parameters shown in Figure 19. Table 21 lists specifications for the I2C output timing parameters shown in Figure 19. Table 21. I2C Output Timing Specifications between SCL and SDA Num I11 I2 1 I3 I4 I5 I6 I7 I8 2 1 3 1 1 1 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 6 10 — 7 — 10 2 20 10 Max — — — — 3 — — — — Units Bus clocks Bus clocks µS Bus clocks ns Bus clocks Bus clocks Bus clocks Bus clocks I9 1 MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 21 JTAG and Boundary Scan Timing NOTES: 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 21. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 21 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 19 shows timing for the values in Table 20 and Table 21. I2 I6 SCL I1 I4 SDA I7 I8 I3 I9 I5 Figure 19. I2C Input/Output Timings 14 Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 JTAG and Boundary Scan Timing Table 22. JTAG and Boundary Scan Timing Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 2 15.15 0.0 5.0 24.0 0.0 0.0 5.0 10.0 0.0 0.0 100.0 10.0 Max 10 — — 3.0 — — 15.0 15.0 — — 20.0 15.0 — — Unit MHz tCK ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1 MTMOD is expected to be a static signal. Hence, it is not associated with any timing MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 22 Freescale Semiconductor JTAG and Boundary Scan Timing J2 J3 TCLK (Input) VIH VIL J4 J4 J3 Figure 20. Test Clock Input Timing TCLK VIL 5 VIH 6 Data Inputs 7 Data Outputs 8 Data Outputs 7 Data Outputs Input Data Valid Output Data Valid Output Data Valid Figure 21. Boundary Scan (JTAG) Timing TCLK VIL 9 VIH 10 TDI, TMS, BKPT 11 TDO 12 TDO 11 TDO Input Data Valid Output Data Valid Output Data Valid Figure 22. Test Access Port Timing MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 23 JTAG and Boundary Scan Timing TCLK 14 TRST 13 Figure 23. TRST Timing Debug AC Timing Specifications Table 23 lists specifications for the debug AC timing parameters shown in Figure 25. Table 23. Debug AC Timing Specification 50 MHz Num D1 D2 D3 D4 1 D5 Characteristic Min PSTDDATA to PSTCLK setup PSTCLK to PSTDDATA hold DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time 4.5 4.5 1 4 5 Max — — — — — ns ns PSTCLKs PSTCLKs PSTCLKs Units NOTES: 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. Figure 24 shows real-time trace timing for the values in Table 23. PSTCLK D1 PSTDDATA[7:0] D2 Figure 24. Real-Time Trace AC Timing Figure 25 shows BDM serial port AC timing for the values in Table 23. D5 DSCLK D3 DSI Current D4 DSO Past Current Next Figure 25. BDM Serial Port AC Timing MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 24 Freescale Semiconductor DSPI Electrical Specifications 15 DSPI Electrical Specifications Table 24. DSPI Modules AC Timing Specifications Table 24 lists DSPI timings. Name DS1 DS2 DS3 DS4 DS5 DSPI_CS[3:0] to DSPI_CLK Characteristic Min 1 × tck — 2 10 10 Max 510 × tck 12 — — — Unit ns ns ns ns ns DSPI_CLK high to DSPI_DOUT valid. DSPI_CLK high to DSPI_DOUT invalid. (Output hold) DSPI_DIN to DSPI_CLK (Input setup) DSPI_DIN to DSPI_CLK (Input hold) The values in Table 24 correspond to Figure 26. DSPI_CS[3:0] DS1 DSPI_CLK DS2 DSPI_DOUT DS3 DSPI_DIN DS4 DS5 Figure 26. DSPI Timing 16 Timer Module AC Timing Specifications Table 25. Timer Module AC Timing Specifications 0–50 MHz Name T1 T2 Characteristic Min TIN0 / TIN1 / TIN2 / TIN3 cycle time TIN0 / TIN1 / TIN2 / TIN3 pulse width 3 1 Max — — PSTCLK PSTCLK Unit Table 25 lists timer module AC timings. MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 25 Revision History 17 Revision History Revision Number 2.2 2.3 2.4 Date August 29, 2005 August 30, 2005 December 14, 2005 Substantive Changes Table 7: Changed C1 minimum spec from 15.15 ns to 20 ns and maximum spec from 33.3 ns to 40 ns. Table 22: Changed J11 maximum from 15 ns to 20 ns. Table 9: Changed heading maximum from 66 MHz to 50 MHz. Table 10: Changed frequency of operation maximum from 66 MHz to 50 MHz and corresponding FB1 minimum from 15.15 ns to 20 ns. Table 10: Changed FB1 maximum from 33.33 ns to 40 ns. Table 14: Changed frequency of operation maximum from 66 MHz to 50 MHz and corresponding FB1 minimum from 15.15 ns to 20 ns. Table 14: Changed FB1 maximum from 33.33 ns to 40 ns. Table 14: Changed various entry descriptions from “(33 < PCI ≤ 66 Mhz)” to (33< PCI ≤ 50 Mhz) Table 23: Changed heading maximum from 66 MHz to 50 MHz. Table 25: Changed heading maximum from 66 MHz to 50 MHz. MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 26 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.4 Freescale Semiconductor 27 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2004. All rights reserved. MCF5475EC Rev. 2.4 12/2005