MCIMX27

MCIMX27 Multimedia Applications Processor Reference Manual MCIMX27RM Rev. 0.2 9/2007 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. All rights reserved. For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Contents Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx Chapter 1 Introduction to the i.MX27 Multimedia Applications Processor 1.1 i.MX27 Applications Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Summary of Core and Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1 ARM9™ Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.2 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.3 Standard System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.4 Power Management and Backup Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.5 System Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.6 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.2.7 Wireline Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.2.8 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.9 Memory Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.2.10 Video Codec and enhanced Multimedia Accelerator Lite (eMMA_lt) . . . . . . . . . . . . . . . 1-17 1.2.11 MultiMedia Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.2.12 Human Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.2.13 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Chapter 2 System Memory and Register Map 2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Detailed Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-1 2-7 Chapter 3 Clocks, Power Management, and Reset Control 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Clock Controller Architecture Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 High Frequency Clock Source and Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Output Frequency Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 PLL Operation at Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 PLL Operation at Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor iii 3-1 3-1 3-4 3-5 3-5 3-5 3-5 3.3.3 i.MX27 Processor Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.4 SDRAM Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.5 Power Management in the PLL Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.6 Power Management Using Frequency Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.2 Clock Source Control Register (CSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3 MPLL Control Register 0 (MPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4.4 MCU and System PLL Control Register 1 (MPCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.4.5 Programming the Serial Peripheral PLL (SPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.6 SPLL Control Register 0 (SPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.7 SPLL Control Register 1 (SPCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.4.8 Oscillator 26M Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.4.9 Peripheral Clock Divider Register 0 (PCDR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.4.10 Peripheral Clock Divider Register 1 (PCDR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.4.11 Peripheral Clock Control Register 0 (PCCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.4.12 Peripheral Clock Control Register 1 (PCCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.4.13 Clock Control Status Register (CCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.4.14 Wakeup Guard Mode Control Register (WKGDCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.5 Functional Description of the Reset Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.5.1 Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.5.2 ARM9 Platform Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 Chapter 4 System Control 4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.1 Chip ID Register (CID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 Function Multiplexing Control Register (FMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.3 Global Peripheral Control Register (GPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.4 Well Bias System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.5 Well Bias Control Register (WBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.6 Drive Strength Control Register 1 (DSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.7 Drive Strength Control Register 2 (DSCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.8 Drive Strength Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.2.9 Drive Strength Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.2.10 Drive Strength Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.2.11 Drive Strength Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.2.12 Drive Strength Control Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.2.13 Drive Strength Control Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 4.2.14 Drive Strength Control Register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4.2.15 Drive Strength Control Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 4.2.16 Drive Strength Control Register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.2.17 Drive Strength Control Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 iv Freescale Semiconductor 4.2.18 Drive Strength Control Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.19 Pull Strength Control Register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.20 Priority Control and Select Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.21 Power Management Control Register (PMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.22 DPTC Comparator Value Register 0 (DCVR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.23 DPTC Comparator Value Register 1 (DCVR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.24 DPTC Comparator Value Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.25 DPTC Comparator Value Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.26 PMIC Pad Control Register (PPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 System Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4-38 4-40 4-41 4-43 4-43 4-44 4-45 4-45 4-46 Chapter 5 Signal Descriptions and Pin Assignments 5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 I/O Power Supply and Signal Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.1 Pull/Pull Strength/Open Drain Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.2 GPIO Default and Pull-Up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.3 I/O Mode and Supply Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 Chapter 6 General-Purpose I/O (GPIO) 6.1 6.2 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 6.6.10 6.6.11 6.6.12 6.6.13 6.6.14 6.6.15 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 GPIO Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 External Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Data Direction Register (PTn_DDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Output Configuration Register 1 (OCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Output Configuration Register 2 (OCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Input Configuration Register A1 (ICONFA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Input Configuration Register A2 (ICONFA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Input Configuration Register B1 (ICONFB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Input Configuration Register B2 (ICONFB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Data Register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 GPIO IN USE Registers (GIUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 GPIO IN USE Register Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Sample Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Interrupt Configuration Register 1 (ICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Interrupt Configuration Register 2 (ICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor v 6.6.16 6.6.17 6.6.18 6.6.19 6.6.20 Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Register (GPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset Register (SWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull-Up Enable Register (PUEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Interrupt Mask Register (PMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6-27 6-28 6-29 6-30 Chapter 7 JTAG Controller (JTAGC) 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.7 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.8.6 7.8.7 7.9 7.9.1 7.9.2 7.9.3 7.10 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Controller Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARM926 Platform mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i.MX27 JTAG Controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMPLE/PRELOAD Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ENABLE_ExtraDebug Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS Sequence to Check ID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS Sequence to Write to ExtraDebug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS Sequence to Read ExtraDebug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i.MX27 JTAG Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-2 7-2 7-3 7-3 7-3 7-3 7-4 7-4 7-4 7-5 7-5 7-5 7-6 7-6 7-6 7-6 7-7 7-8 7-8 Chapter 8 Bootstrap Mode Operation 8.1 8.2 8.3 8.4 8.4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART/USB Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enter Bootstrap Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Protocol and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8-1 8-1 8-2 8-3 Chapter 9 ARM9 Platform 9.1 9.1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Design Methodology Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 vi Freescale Semiconductor 9.1.2 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2.10 9.2.11 9.3 9.4 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.7 9.7.1 9.7.2 9.8 9.8.1 9.8.2 9.8.3 9.8.4 9.9 9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.9.6 9.9.7 9.10 9.11 9.12 9.13 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 ARM9 Platform Sub-Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 ARM926EJ-S Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 ARM9 Embedded Trace Macrocell and Embedded Trace Buffer . . . . . . . . . . . . . . . . . . . . 9-6 The 6 x 3 Multi-Layer AHB Crossbar Switch (MAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 ARM Interrupt Controller (AITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Memory Controller and BIST Engine (MCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 AHB IP Bus Interface (AIPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 PAHBMUX–Primary AHB Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 ROMPATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Clock Control Module (CLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 JAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Test Wrapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 ARM9 Platform Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 ARM9 Platform Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 External Peripheral Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 External Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 Memory Map Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 Platform Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 ARM926EJ-S Clock Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 ARM926EJ-S JTAG Port Clocking Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 External Alternate Bus Master Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 External Secondary AHB Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 Platform Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 HRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 POR and JTAG_TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 Register Level Clock Gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 Block Level Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 External Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 Well Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 Platform AHB Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 Definition of AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 Alternate Bus Master Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 Single Master Seamless Connection to ABM Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 Multiple External Masters Connection to ABM Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 Alternate Bus Master Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 MAX AHB Slave Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 Endian Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 Preliminary Size Estimate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 ARM9 Platform I/O Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor vii 9.13.1 9.13.2 9.13.3 9.13.4 9.13.5 9.13.6 9.13.7 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Well Bias Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clk and jtag_tck Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Bus Master (ABM) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary AHB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM and ROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9-40 9-41 9-41 9-42 9-44 9-46 Chapter 10 ARM926EJ-S Interrupt Controller (AITC) 10.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2.2 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.3 Interrupt Control Register (INTCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.2.4 Normal Interrupt Mask Register (NIMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.2.5 Interrupt Enable Number Register (INTENNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.2.6 Interrupt Disable Number Register (INTDISNUM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.2.7 Interrupt Enable Register High (INTENABLEH) and Low (INTENABLEL) . . . . . . . . 10-12 10.2.8 Interrupt Type Register High (INTTYPEH) and Low (INTTYPEL). . . . . . . . . . . . . . . . 10-13 10.2.9 Normal Interrupt Priority Level Registers (NIPRIORITYn) . . . . . . . . . . . . . . . . . . . . . . 10-14 10.2.10 Normal Interrupt Vector and Status Register (NIVECSR). . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.2.11 Fast Interrupt Vector and Status Register (FIVECSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.2.12 Interrupt Source Register High (INTSRCH) and Low (INTSRCL). . . . . . . . . . . . . . . . . 10-24 10.2.13 Interrupt Force Register High (INTFRCH) and Low (INTFRCL). . . . . . . . . . . . . . . . . . 10-27 10.2.14 Normal Interrupt Pending Register High (NIPNDH) and Low (NIPNDL) . . . . . . . . . . . 10-28 10.2.15 Fast Interrupt Pending Register High (FIPNDH) and Low (FIPNDL) . . . . . . . . . . . . . . 10-29 10.3 ARM926EJ-S Interrupt Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.1 ARM926EJ-S Prioritization of Exception Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.2 AITC Prioritization of Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.3 Assigning and Enabling Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.3.4 Enabling Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.3.5 Typical Interrupt Entry Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.3.6 Writing Reentrant Normal Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.3.7 AHB Interface of AITC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 Chapter 11 Security Controller (SCC) 11.1 11.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 viii Freescale Semiconductor Chapter 12 Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) 12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Chapter 13 Run-Time Integrity Checker (RTIC) 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 System Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-2 13-2 13-2 Chapter 14 IC Identification (IIM) 14.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 Chapter 15 External Memory Interface (EMI) 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.4 15.4.1 15.5 15.6 15.6.1 15.7 15.7.1 15.7.2 15.8 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 PCMCIA Host Adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 Card Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 TrueIDE Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 NAND Flash Controller (NFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 Enhanced SDRAM Controller (ESDRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 M3IF AHB MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Overview of EMI AHB MUX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 M3IF I/O MUX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Overview of EMI I/O MUX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 EMI Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 Chapter 16 Multi-Master Memory Interface (M3IF) 16.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1.1 M3IF Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor ix 16-1 16-1 16-3 16-4 16-4 16-6 16.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3.2 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.4.1 Master Port Gasket (MPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.4.2 Master Port Gasket 64 (MPG64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.4.3 M3IF Arbitration (M3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 16.4.4 Master Arbitration and Buffering (MAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36 16.4.5 Snooping Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39 16.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40 16.5.1 M3IF in a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40 Chapter 17 Wireless External Interface Module (WEIM) 17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.4 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.5 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.5.2 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.5.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.6.1 Configurable Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.6.2 WEIM Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.6.3 Burst Mode Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.6.4 Burst Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.6.5 Burst Clock Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.6.6 Page Mode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.6.7 PSRAM Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.6.8 Multiplexed Address/Data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.6.9 Mixed AHB/Memory Burst Modes Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.6.10 AHB Bus Cycles Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.6.11 DTACK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.6.12 Internal Input Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.6.13 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.8 External Bus Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.8.1 Asynchronous Memory Accesses Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17.8.2 Page Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-50 17.8.3 DTACK Mode Memory Accesses Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-51 17.8.4 Burst Memory Accesses Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-54 17.8.5 Synchronous Accesses Timing Diagrams with PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . 17-65 17.8.6 Multiplexed A/D Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-68 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 x Freescale Semiconductor Chapter 18 Enhanced SDRAM Controller (ESDRAMC) 18.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.1 SDRAM Command Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.2 Bank Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.3 Decoder and Address MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.4 ESDRAMC Control and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.5 Refresh Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.6 Command Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.7 Size Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.8 Mobile/Low Power DDR (LPDDR) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.1.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.3.2 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 18.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36 18.4.1 Enhanced SDRAM Controller Optimization Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37 18.4.2 Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 18.4.3 Multiplexed Address Bus—During “Special” Mode (SMODE 1 or 3) . . . . . . . . . . . . . . 18-47 18.4.4 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47 18.4.5 Low Power Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49 18.4.6 SDRAM (SDR and LPDDR) Command Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60 18.4.7 Normal READ/WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 18.4.8 Precharge Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-91 18.4.9 Auto-Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-93 18.4.10 Manual Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-94 18.4.11 Set Mode Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-94 18.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 18.5.1 Memory Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 18.5.2 Configuring Controller for SDRAM Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 18.5.3 CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 18.5.4 SDRAM/LPDDR Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-97 Chapter 19 NAND Flash Controller (NFC) 19.1 19.2 19.3 19.4 19.4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xi 19-1 19-2 19-2 19-3 19-3 19.4.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.5 NFC Buffer Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.5.1 Main and Spare Area Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.6 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.6.2 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.7.1 Internal SRAM SIZE (NFC_BUFSIZE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.7.2 Buffer Number for Page Data Transfer (RAM_BUFFER_ADDRESS) . . . . . . . . . . . . . 19-10 19.7.3 NAND Flash Address (NAND_FLASH_ADD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.7.4 NAND Flash Command (NAND_FLASH_CMD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.7.5 NFC Internal Buffer Lock Control (NFC_CONFIGURATION) . . . . . . . . . . . . . . . . . . . 19-11 19.7.6 Controller Status and Result of Flash Operation (ECC_STATUS_RESULT). . . . . . . . . 19-12 19.7.7 ECC Error Position of Main Area Data Error x8 (ECC_RSLT_MAIN_AREA). . . . . . . 19-12 19.7.8 ECC Error Position of Main Area Data Error x16 (ECC_RSLT_MAIN_AREA). . . . . . 19-13 19.7.9 ECC Error Position of Spare Area Data Error x8 (ECC_RSLT_SPARE_AREA) . . . . . 19-14 19.7.10 ECC Error Position of Spare Area Data Error x16 (ECC_RSLT_SPARE_AREA) . . . . 19-14 19.7.11 NAND Flash Write Protection (NF_WR_PROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.7.12 Address to Unlock in Write Protection Mode—Start (UNLOCK_START_BLK_ADD) 19-15 19.7.13 Address to Unlock in Write Protection Mode—End (UNLOCK_END_BLK_ADD). . . 19-16 19.7.14 NAND Flash Write Protection Status (NAND_FLASH_WR_PR_ST) . . . . . . . . . . . . . . 19-16 19.7.15 NAND Flash Operation Configuration (NAND_FLASH_CONFIG1) . . . . . . . . . . . . . . 19-17 19.7.16 NAND Flash Operation Configuration 2 (NAND_FLASH_CONFIG2) . . . . . . . . . . . . . 19-18 19.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.8.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.8.2 Booting From a NAND Flash Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 19.8.3 NAND Flash Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21 19.8.4 Error Code Correction (ECC) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.8.5 Address Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.8.6 RAM Buffer (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.7 Registers (Command, Address, Status, and Others.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.8 Read and Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.9 Data Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.10 Host Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.11 AHB BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.8.12 I/O Pins Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.9 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.9.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.9.2 ECC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34 19.9.3 Write Protection Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35 19.9.4 Memory Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xii Freescale Semiconductor Chapter 20 Personal Computer Memory Card International Association (PCMCIA) Controller 20.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.2 Windowing Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.3 WAIT Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.5.5 Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.6 Reset and Three-Score Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.7 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 20.5.8 16-Bit/8-Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25 20.5.9 Data and Control Signals Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25 20.5.10 True IDE Mode Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.5.11 Card Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.5.12 TrueIDE Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 20.5.13 Endianness Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 Chapter 21 1-Wire Interface (1-Wire) 21.1 21.2 21.3 21.4 21.5 21.5.1 21.5.2 21.5.3 21.5.4 21.5.5 21.6 21.6.1 21.6.2 21.6.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Enable and AIPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sequence with Reset Pulse Presence Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write 1 and Read Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Divider Register (TIME_DIVIDER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21-2 21-2 21-3 21-3 21-3 21-3 21-4 21-4 21-5 21-5 21-5 21-7 21-9 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xiii Chapter 22 Advanced Technology Attachment (ATA) 22.1 22.2 22.3 22.4 22.4.1 22.5 22.5.1 22.6 22.6.1 22.6.2 22.6.3 22.7 22.8 22.8.1 22.8.2 22.8.3 22.8.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 PIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 DMA Mode (Multi-Word DMA and Ultra DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 Resetting ATA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 Access to ATA Bus in PIO Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 Using DMA Mode to Receive Data from ATA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 Using DMA Mode to Transmit Data to ATA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25 Chapter 23 Configurable Serial Peripheral Interface (CSPI) 23.1 23.1.1 23.2 23.3 23.3.1 23.3.2 23.3.3 23.3.4 23.3.5 23.4 23.4.1 23.5 23.5.1 23.5.2 23.5.3 23.6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 External Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 Module Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 Software Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 Chapter 24 Inter-Integrated Circuit (I2C) 24.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xiv Freescale Semiconductor 24.2 24.2.1 24.3 24.3.1 24.3.2 24.3.3 24.4 24.4.1 24.4.2 24.4.3 24.4.4 24.4.5 24.4.6 24.4.7 24.4.8 24.5 24.5.1 24.5.2 24.5.3 24.5.4 24.5.5 24.5.6 24.5.7 24.5.8 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 Detailed External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 I2C Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 I2C System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 IP Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Generation of Transfer Error on IP Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Generation of START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 Generation of Repeated START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 Arbitration Lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 Timing Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18 Chapter 25 Keypad Port (KPP) 25.1 25.1.1 25.1.2 25.2 25.2.1 25.3 25.3.1 25.3.2 25.3.3 25.4 25.4.1 25.4.2 25.4.3 25.4.4 25.4.5 25.4.6 25.4.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 KPP Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 Keypad Matrix Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 Keypad Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 Keypad Matrix Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 Keypad Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 Glitch Suppression on Keypad Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 Multiple Key Closures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 3-Point Contact Keys Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xv 25.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.5.1 Typical Keypad Configuration and Scanning Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 25.5.2 Key Press Interrupt Scanning Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.5.3 Additional Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25-15 25-15 25-16 Chapter 26 Memory Stick Host Controller (MSHC) 26.1 26.1.1 26.1.2 26.2 26.2.1 26.3 26.3.1 26.4 26.4.1 26.4.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sony Memory Stick Controller (SMSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSHC Gasket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26-2 26-2 26-2 26-2 26-3 26-4 26-7 26-7 26-7 Chapter 27 Secured Digital Host Controller (SDHC) 27.1 27.1.1 27.2 27.3 27.3.1 27.3.2 27.3.3 27.4 27.4.1 27.4.2 27.4.3 27.4.4 27.4.5 27.4.6 27.4.7 27.4.8 27.4.9 27.5 27.5.1 27.5.2 27.5.3 27.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30 Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-34 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-35 SDIO Card Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-36 Card Insertion and Removal Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-38 Power Management and Wake-Up Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-39 Command/Data Interpreter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-40 System Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-42 DAT/CMD Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-43 Initialization/Application of SDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-43 Command Submit—Response Receive Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . 27-44 Card Identification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-45 Card Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-50 Commands for MMC/SD/SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xvi Freescale Semiconductor Chapter 28 Universal Asynchronous Receiver/Transmitters (UART) 28.1 28.1.1 28.1.2 28.2 28.2.1 28.3 28.3.1 28.3.2 28.3.3 28.3.4 28.4 28.4.1 28.4.2 28.4.3 28.4.4 28.4.5 28.4.6 28.4.7 28.4.8 28.4.9 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 Memory Map and Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 Interrupts and DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 Clocking Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28 General UART Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31 Sub-Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 Binary Rate Multiplier (BRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-40 Baud Rate Automatic Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42 Escape Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-44 UART Operation in Low-Power System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-48 UART Operation in System Debug State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-49 Chapter 29 Fast Ethernet Controller (FEC) 29.1 29.2 29.2.1 29.3 29.3.1 29.3.2 29.3.3 29.3.4 29.4 29.5 29.5.1 29.5.2 29.5.3 29.5.4 29.5.5 29.5.6 29.5.7 29.5.8 29.5.9 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 Full and Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 Interface Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 Address Recognition Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 FEC Top-Level Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 User Initialization (Prior to Asserting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . . . . . . . . 29-5 Microcontroller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 User Initialization (After Asserting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 Network Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 FEC Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 FEC Frame Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8 Ethernet Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 Hash Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xvii 29.5.10 Full Duplex Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.5.11 Inter-Packet Gap (IPG) Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.5.12 Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.5.13 Internal and External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.5.14 Ethernet Error-Handling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.6 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.6.1 High-Level Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.6.2 Detailed Memory Map (Control/Status Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.6.3 MIB Block Counters Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.6.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.6.5 Buffer Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14 29-15 29-15 29-15 29-16 29-17 29-17 29-18 29-19 29-21 29-37 Chapter 30 High-Speed USB On-The-Go (HS USB-OTG) 30.1 30.2 30.3 30.3.1 30.4 30.4.1 30.4.2 30.5 30.5.1 30.6 30.6.1 30.6.2 30.6.3 30.6.4 30.6.5 30.6.6 30.6.7 30.6.8 30.7 30.7.1 30.7.2 30.8 30.8.1 30.8.2 30.8.3 30.8.4 30.8.5 30.8.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 USB HOST Controller 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 USB Host Controller 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12 USB OTG Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13 USB Power Control Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15 TLL Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 USB Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 ULPI/Serial MUX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 Software Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 Summary of Register Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-27 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-30 Host Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-76 Host Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-101 EHCI Deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-182 Device Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-188 Device Operational Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-194 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xviii Freescale Semiconductor Chapter 31 General Purpose Timer (GPT) 31.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.2.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.2 Operation During Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.3 Capture Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.4 Compare Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3.1 GPT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.3.2 GPT Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.3.3 GPT Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.3.4 GPT Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10 31.3.5 GPT Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.3.6 GPT Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 Chapter 32 Pulse-Width Modulator (PWM) 32.1 32.2 32.2.1 32.3 32.3.1 32.3.2 32.4 32.4.1 32.5 32.5.1 32.5.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 PWM Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14 PWM Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15 ipg_enable_clk Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16 Chapter 33 Real Time Clock (RTC) 33.1 33.2 33.2.1 33.2.2 33.3 33.3.1 33.4 33.4.1 33.4.2 33.4.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xix 33-1 33-2 33-2 33-2 33-3 33-3 33-3 33-3 33-3 33-6 33.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.5.1 Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.5.2 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.5.3 Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.5.4 Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.6.1 Flowchart of RTC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33.6.2 Code Example of ARM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-17 33-17 33-18 33-18 33-19 33-19 33-19 33-20 Chapter 34 Watchdog Timer (WDOG) 34.1 34.1.1 34.2 34.2.1 34.2.2 34.3 34.3.1 34.3.2 34.4 34.4.1 34.4.2 34.5 34.5.1 34.5.2 34.5.3 34.5.4 34.5.5 34.5.6 34.5.7 34.6 34.6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 Detailed External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 Internal Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 Watchdog Timer Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 Watchdog Control Register (WCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 Watchdog Service Register (WSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 Watchdog During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 Watchdog After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 Generation of Transfer Error on the IP Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9 Low-Power and DEBUG Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9 Watchdog Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 WDOG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 Chapter 35 AHB-Lite IP Interface (AIPI) Module 35.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.1.1 Peripheral Size Registers[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.1.2 Peripheral Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.2 AIPI1 and AIPI2 Peripheral Widths and PSR Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.3.1 Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.3.2 Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.3.3 Aborted Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2 35-3 35-4 35-4 35-6 35-6 35-6 35-6 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xx Freescale Semiconductor Chapter 36 Multi-Layer AHB Crossbar Switch (MAX) 36.1 36.2 36.3 36.4 36.4.1 36.4.2 36.4.3 36.4.4 36.4.5 36.4.6 36.4.7 36.4.8 36.5 36.5.1 36.5.2 36.5.3 36.5.4 36.6 36.7 36.7.1 36.7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 General Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 MAX Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6 Master Priority Registers (MPR0–MPR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6 Alternate Master Priority Register for Slave Port 0–2 (AMPR0–2). . . . . . . . . . . . . . . . . . 36-7 General Purpose Control Register for Slave Port 0–2 (SGPCR0–2) . . . . . . . . . . . . . . . . . 36-9 Alternate SGPCR for Slave Port 0–2 (ASGPCR0–2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-14 Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-14 Priority Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15 Master Port Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-16 Slave Port Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-25 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 Master Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 Slave Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 Chapter 37 Direct Memory Access Controller (DMAC) 37.1 37.2 37.2.1 37.2.2 37.3 37.4 37.4.1 37.4.2 37.4.3 37.4.4 37.4.5 37.5 37.6 37.6.1 37.6.2 37.7 37.7.1 37.7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1 DMA Request and Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 External DMA Request and Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-2 DMA Request Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5 DMAC Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-5 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-6 General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-10 2D Memory Registers (A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-16 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-19 DMA Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-29 Special Cases of Burst Length and Access Size Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-30 Memory Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-30 Memory Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 Special Cases When CCNR and CNTR Values Differ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 CNTR Not A Multiple of Destination Access Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 BL is Not a Multiple of Destination Access Size, CNTR Is. . . . . . . . . . . . . . . . . . . . . . . 37-32 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xxi 37.8 Application Note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-32 37.9 DMA Burst Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-32 37.10 Glossary of Terms Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-33 Chapter 38 Digital Audio MUX (AUDMUX) 38.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.3 Internal Network Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4 38.4 Tx/Rx Switch and External Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4 38.5 Frame Sync and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5 38.6 Synchronous Mode (4-Wire Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6 38.7 Asynchronous Mode (6-Wire Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7 38.8 SSI to Peripheral Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7 38.9 SSI to SAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.10 Peripheral Port to Peripheral Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.11 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 38.11.1 AUDMUX Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 38.11.2 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 38.11.3 Host Port Configuration Register (HPCR1–2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-16 38.11.4 Peripheral Port Configuration Registers (PPCR1–2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-18 38.12 Peripheral Connectivity Through AUDMUX Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 38-20 38.12.1 Generic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-20 38.12.2 AUDMUX Configuration with SSI1 and SAP as Master. . . . . . . . . . . . . . . . . . . . . . . . . 38-22 38.12.3 Tx-Rx Switch Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-23 38.12.4 Internal/External Network Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-24 Chapter 39 CMOS Sensor Interface (CSI) 39.1 39.2 39.2.1 39.3 39.3.1 39.3.2 39.3.3 39.3.4 39.3.5 39.4 39.4.1 39.4.2 39.4.3 39.4.4 39.4.5 CSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSI Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals from CSI to eMMA Pre-Processor Block (PrP). . . . . . . . . . . . . . . . . . . . . . . . . . . Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gated Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Gated Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCIR656 Interlace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCIR656 Progressive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Correction for CCIR656 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start Of Frame Interrupt (SOF_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . End Of Frame Interrupt (EOF_INT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Change Of Field Interrupt (COF_INT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCIR Error Interrupt (ECC_INT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Packing Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xxii Freescale Semiconductor 39-1 39-2 39-3 39-3 39-4 39-4 39-4 39-6 39-7 39-7 39-7 39-8 39-8 39-8 39-8 39.4.6 RX FIFO Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-9 39.4.7 STAT FIFO Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-10 39.5 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11 39.5.1 CSI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11 39.5.2 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11 39.5.3 CSI Control Register 1 (CSICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-14 39.5.4 CSI Control Register 2 (CSICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-17 39.5.5 CSI Control Register 3 (CSICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-19 39.5.6 CSI Status Register (CSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-20 39.5.7 CSI STATFIFO Register (CSISTATFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-22 39.5.8 CSI RxFIFO Register (CSIRFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-22 39.5.9 CSI RX Count Register (CSIRXCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-23 Chapter 40 Video Codec (Video_Codec) 40.1 40.2 40.3 40.3.1 40.3.2 40.4 40.4.1 40.4.2 40.4.3 40.5 40.5.1 40.5.2 40.6 40.7 40.7.1 40.7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 Clock Domain and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-12 Video Codec Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-14 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-15 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-15 Video Codec Processing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-15 Application Using Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-24 Chapter 41 enhanced Multimedia Accelerator Light (eMMA_lt) 41.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.2 eMMA_lt Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 41.2.1 Pre-Processor (PrP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.2.2 Post-Processor (PP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.2.3 64-Bit Gasket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.3 Post-Processor (PP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.3.1 Color Space Conversion (CSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 41.3.2 Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-9 41.3.3 Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-10 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xxiii 41.3.4 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3.5 Relationship of Register Fields Related to the Input Frame . . . . . . . . . . . . . . . . . . . . . . . 41.3.6 Relationship of Register Fields Related to Output Frame . . . . . . . . . . . . . . . . . . . . . . . . 41.4 Post Processor (PP) Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.1 PP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.2 PP Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.3 PP Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.4 PP Source Y Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.5 PP Source Cb Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.6 PP Source Cr Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.7 PP Destination RGB Frame Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.8 PP Quantizer Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.9 PP Process Frame Parameter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.10 PP Source Frame Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.11 PP Destination Display Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.12 PP Destination Image Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.13 PP Destination Frame Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.14 PP Resize Table Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.15 PP CSC COEF 123 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.16 PP CSC COEF_4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4.17 PP Resize Coefficient Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5 Pre-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.2 Input Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.3 Resize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.4 Color Space Conversion (CSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.5 RGB to YUV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.6 Frame Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.7 LOOP Mode (LEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.8 Channel-1 and Channel-2 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.9 Channel-2 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.10 Line Buffer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.11 Relationship of Register Fields Related to the Input Frame . . . . . . . . . . . . . . . . . . . . . . . 41.5.12 Relationship of Register Fields Related to Channel-1 Output Frame . . . . . . . . . . . . . . . 41.5.13 CSI Frame Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5.14 CSI-PrP Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6 Pre-Processor (PrP) Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.1 PrP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.2 PrP Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.3 PrP Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.4 PrP Source Y Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.5 PrP Source Cb Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.6 PrP Source Cr Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.7 PrP Destination RGB1 Frame Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6.8 PrP Destination RGB2 Frame Start Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xxiv 41-11 41-11 41-12 41-13 41-14 41-15 41-16 41-17 41-18 41-19 41-19 41-20 41-21 41-21 41-22 41-23 41-24 41-25 41-26 41-27 41-28 41-30 41-31 41-31 41-32 41-35 41-35 41-36 41-37 41-37 41-38 41-38 41-38 41-39 41-40 41-41 41-43 41-44 41-47 41-49 41-50 41-51 41-51 41-52 41-53 Freescale Semiconductor 41.6.9 41.6.10 41.6.11 41.6.12 41.6.13 41.6.14 41.6.15 41.6.16 41.6.17 41.6.18 41.6.19 41.6.20 41.6.21 41.6.22 41.6.23 41.6.24 41.6.25 41.6.26 41.6.27 41.6.28 41.6.29 41.6.30 41.6.31 41.6.32 41.6.33 PrP Destination Y Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Destination Cb Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Destination Cr Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Source Frame Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Destination Channel-1 Line Stride Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Source Pixel Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel-1 Pixel Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Destination Channel-1 Output Image Size Register . . . . . . . . . . . . . . . . . . . . . . . . . PrP Destination Channel-2 Output Image Size Register . . . . . . . . . . . . . . . . . . . . . . . . . PrP Source Line Stride Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP CSC Coefficient 012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP CSC Coefficient 345 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP CSC Coefficient 678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel 1 Horizontal Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel1 Horizontal Resize Coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel 1 Horizontal Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel1 Vertical Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel 1 Vertical Resize Coefficient 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel 1 Vertical Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel-2 Horizontal Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel-2 Horizontal Resize Coefficient-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel-2 Horizontal Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel2 Vertical Resize Coefficient-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel 2 Vertical Resize Coefficient 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PrP Channel 2 Vertical Resize Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-53 41-54 41-55 41-55 41-56 41-57 41-59 41-61 41-61 41-62 41-63 41-64 41-65 41-67 41-68 41-69 41-70 41-71 41-72 41-73 41-74 41-75 41-76 41-78 41-79 Chapter 42 Synchronous Serial Interface (SSI) 42.1 42.1.1 42.1.2 42.2 42.2.1 42.2.2 42.2.3 42.3 42.3.1 42.3.2 42.3.3 42.4 42.4.1 42.4.2 42.4.3 42.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-20 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-20 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-20 Internal I/O Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-25 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-27 R/WSSI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-27 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-28 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-32 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-64 SSI Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-64 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-64 Receive Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-69 Transmit Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-69 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xxv 42.4.5 IP Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-70 42.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-70 Chapter 43 Liquid Crystal Display Controller (LCDC) 43.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1 43.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.2.1 LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.2.2 Graphic Window on Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4 43.2.3 Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5 43.2.4 Display Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5 43.2.5 Black-and-White Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7 43.2.6 Gray-Scale Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7 43.2.7 Color Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8 43.2.8 Frame Rate Modulation Control (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-10 43.2.9 Panel Interface Signals and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-11 43.2.10 8 bpp Mode Color STN Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-14 43.3 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-19 43.3.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-20 43.3.2 LCDC Screen Start Address Register (LSSAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-24 43.3.3 LCDC Size Register (LSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-24 43.3.4 LCDC Virtual Page Width Register (LVPWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-25 43.3.5 LCDC Cursor Position Register (LCPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-26 43.3.6 LCDC Cursor Width Height and Blink Register (LCWHB) . . . . . . . . . . . . . . . . . . . . . . 43-27 43.3.7 LCDC Color Cursor Mapping Register (LCCMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-28 43.3.8 LCDC Panel Configuration Register (LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-29 43.3.9 LCDC Horizontal Configuration Register (LHCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-31 43.3.10 LCDC Vertical Configuration Register (LVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-32 43.3.11 LCDC Panning Offset Register (LPOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-33 43.3.12 LCDC Sharp Configuration Register (LSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-34 43.3.13 LCDC PWM Contrast Control Register (LPCCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-36 43.3.14 LCDC DMA Control Register (LDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-37 43.3.15 LCDC Refresh Mode Control Register (LRMCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-38 43.3.16 LCDC Interrupt Configuration Register (LICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-39 43.3.17 LCDC Interrupt Enable Register (LIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-40 43.3.18 LCDC Interrupt Status Register (LISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-41 43.3.19 LCDC Graphic Window Start Address Register (LGWSAR) . . . . . . . . . . . . . . . . . . . . . 43-43 43.3.20 LCDC Graphic Window Size Register (LGWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-43 43.3.21 LCDC Graphic Window Virtual Page Width Register (LGWVPWR) . . . . . . . . . . . . . . 43-44 43.3.22 LCDC Graphic Window Panning Offset Register (LGWPOR) . . . . . . . . . . . . . . . . . . . . 43-44 43.3.23 LCDC Graphic Window Position Register (LGWPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-45 43.3.24 LCDC Graphic Window Control Register (LGWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-46 43.3.25 LCDC Graphic Window DMA Control Register (LGWDCR) . . . . . . . . . . . . . . . . . . . . 43-47 43.3.26 LCDC AUS Mode Control Register (LAUSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-48 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xxvi Freescale Semiconductor 43.3.27 43.3.28 LCDC AUS Mode Cursor Control Register (LAUSCCR) . . . . . . . . . . . . . . . . . . . . . . . . 43-49 BGLUT and GWLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-50 Chapter 44 Smart Liquid Crystal Display Controller (SLCDC) 44.1 SLCDC Module Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-2 44.2.1 Word Size Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.2.2 Image Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.2.3 Accessing the LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.2.4 Aborting SLCDC Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-14 44.2.5 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-14 44.2.6 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-14 44.2.7 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-15 44.2.8 SLDC Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-16 44.2.9 Data Buffer Base Address Register (DATABASEADR). . . . . . . . . . . . . . . . . . . . . . . . . 44-18 44.2.10 Data Buffer Size Register (DATABUFSIZE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-18 44.2.11 Command Buffer Base Address Register (COMBASEADR) . . . . . . . . . . . . . . . . . . . . . 44-19 44.2.12 Command Buffer Size Register (COMBUFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-19 44.2.13 Command String Size Register (COMSTRINGSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-20 44.2.14 FIFO Configuration Register (FIFOCONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-21 44.2.15 LCD Controller Configuration Register (LCDCONFIG). . . . . . . . . . . . . . . . . . . . . . . . . 44-21 44.2.16 LCD Transfer Configuration Register (LCDTRANSCONFIG) . . . . . . . . . . . . . . . . . . . 44-22 44.2.17 SLCDC Control/Status Register (SLCDCCONTROL/STATUS) . . . . . . . . . . . . . . . . . . 44-23 44.2.18 LCD Clock Configuration Register (LCDCLOCKCONFIG) . . . . . . . . . . . . . . . . . . . . . 44-26 44.2.19 LCD Write Data Register (LCDWRITEDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-26 44.3 LCD Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-27 44.3.1 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-27 44.3.2 Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-29 44.4 LCD Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-30 44.5 R-AHB Interface and SLCDC FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-31 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xxvii MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xxviii Freescale Semiconductor About This Book The MCIMX27 Multimedia Applications Processor Reference Manual describes the features and operation of the i.MX27 microprocessor, the seventh generation of the DragonBall family of products. It provides the details of how to initialize, configure, and program the i.MX27 device. The manual presumes basic knowledge of ARM926EJ-S™ architecture. Audience The MCIMX27 Multimedia Applications Processor Reference Manual is intended to provide a design engineer with the necessary data to successfully integrate the i.MX27 processor into a wide variety of applications. It is assumed that the reader has a good working knowledge of the ARM926EJ-S processor. For programming information about the ARM926EJ-S processor, see the documents listed in the Suggested Reading section of this preface. Organization This reference manual is organized into two books: 1. Book I contains chapters that detail integration information, including the signals, clocks, power management, muxing tables, and JTAG/Boot operation of the IC. 2. Book II is divided into parts that consist of chapters that cover the operation and programming of the i.MX27 device. Document Revision History Since the last revision, Rev. 0.1, base addresses and memory addresses for some modules were updated for easier reader access. Suggested Reading The following documents are recommended for a complete description of the i.MX27 Multimedia Applications Processor, and enable proper design with the i.MX27 device. Especially for those not familiar with the ARM926EJ-S processor or previous DragonBall products, the following documents will be helpful when used in conjunction with this manual. • AMBA AHB specifications, (ARM Ltd.) • ARM926EJ-S Platform specifications (also named ARM926 Platform) • Hip7a KiloBit Single Port HP SRAM Compiler, MEMCTC (May 8, 2002) • Hip7A SAMI ROM Compiler, MEMCTC (November 16, 2001) • Hip7A KiloBit HD VIA ROM Compiler, MEMCTC (June 28, 2002) • ARM926EJ-S Platform Test Guide (ARM Ltd.) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xxix • • • • • ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029) ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) MC9328MX1 i.MX Integrated Portable System Processor Reference Manual (order number MC9328MX1RM) MCIMX27 Multimedia Application Processor Data Sheet—(order number MCIMX27)) These manuals can be found at the ARM Ltd. World Wide Web site at http://www.arm.com and Freescale Semiconductors World Wide Web site at http://www.freescale.com/imx. These documents can be downloaded directly from the World Wide Web site, or printed versions may be ordered. The World Wide Web site may also have useful application notes. Conventions This reference uses the following conventions: • OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. • Logic level one is a voltage that corresponds to Boolean true (1) state. • Logic level zero is a voltage that corresponds to Boolean false (0) state. • To set a bit or bits means to establish logic level one. • To clear a bit or bits means to establish logic level zero. • A signal is an electronic construct whose state conveys or changes in state convey information. • A pin is an external physical connection. The same pin can be used to connect a number of signals. • Asserted means that a discrete signal is in active logic state. — Active low signals change from logic level one to logic level zero. — Active high signals change from logic level zero to logic level one. • Negated means that an asserted discrete signal changes logic state. — Active low signals change from logic level zero to logic level one. — Active high signals change from logic level one to logic level zero. • LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. • Numbers preceded by a percent sign (%) are binary. Numbers preceded by a 0x are hexadecimal. Definitions, Acronyms, and Abbreviations The following list defines acronyms and abbreviations used in this document. ADC analog-to-digital converter AFE analog front end API application programming interface BCD binary coded decimal BER bit error ratio CGM clock generation module MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xxx Freescale Semiconductor CMOS CRC CSIC DAC DDR RAM DMA DRAM DSP FEC FIFO FIRI GPIO I/O ICE IrDa JTAG MAP MAPBGA MIPS MMC PLL PWM RTC SD SDRAM SPI SRAM TQFP UART USB USB OTG XTAL BE/LE CCM LV complimentary metal-oxide semiconductor cyclic redundancy check complex instruction set computer digital-to-analog converter double data rate RAM direct memory access dynamic random access memory digital signal processor forward error correction first in first out fast IR interface general purpose input/output Input/Output in-circuit emulation infrared data association joint test action group mold array process mold array process ball grid array million instructions per second multimedia card phase locked loop pulse-width modulator real-time clock secure digital synchronous dynamic random access memory serial peripheral interface static random access memory thin quad flat pack universal asynchronous receiver/transmitter universal serial bus USB On-The-Go crystal big endian/little endian clock control module, also called “clkctl” module low voltage MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor xxxi LWB MCTL RAM ROM R-AHB bus SRAM ARM API Fabrication Path Flash Path GPCR HW iRAM iROM NFC NAND Flash ROM Bootstrap RAM Path SIDR Sync Flash TBD UART USB V-Sync Flash Word TYPE UID WTLS late-write buffer memory controller random access memory read only memory reduced advanced high-performance bus (AHB), related to ARM bus architecture static RAM Advanced RISC Machines processor architecture Application Programming Interface Path within ROM Bootstrap for fabrication test execution Path within ROM Bootstrap leading towards executing a Flash application. Global Peripheral Control Registry of the i.MX27. Hardware Processor-internal RAM Processor-internal ROM NAND Flash Controller A Flash ROM Technology Internal boot code encompassing main boot flow as well as exception vectors, USB/UART Bootloader blocks. Path within ROM Bootstrap leading towards downloading and executing a RAM application Silicon ID Register of the i.MX27 A Flash ROM Technology To Be Determined Universal Asynchronous Receiver/Transmitter Universal Serial Bus A Flash ROM Technology 32 bits Identifier that distinguishes a production or engineering device. Unique ID; a field in the processor and CSF identifying a device or group of devices Wireless Transport layer Security, a part of the Wireless Application Protocol MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 xxxii Freescale Semiconductor Book I: i.MX27 Applications Processor Integration and Description Introduction Book I comprises detailed descriptions and information on the integration of the i.MX27 Multimedia Applications Processor. Book I includes the following chapters. Device Introduction and Memory Map Chapter 1, “Introduction to the i.MX27 Multimedia Applications Processor,” on page 1-1 Chapter 2, “System Memory and Register Map,” on page 2-1 Clocks, Power Management and Reset Chapter 3, “Clocks, Power Management, and Reset Control,” on page 3-1 Pins Chapter 4, “System Control,” on page 4-1 Chapter 5, “Signal Descriptions and Pin Assignments,” on page 5-1 Chapter 6, “General-Purpose I/O (GPIO),” on page 6-1 Debug Chapter 7, “JTAG Controller (JTAGC),” on page 7-1 Boot Chapter 8, “Bootstrap Mode Operation,” on page 8-1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Chapter 1 Introduction to the i.MX27 Multimedia Applications Processor As part of the i.MX growing family of multimedia-focused products, the i.MX27 Multimedia Applications Processor takes the Mobile Multimedia Experience to another level. Whether you are designing mobile entertainment, a smartphone, wireless PDA, or any other portable device, the i.MX27 processor offers a high degree of integration to significantly reduce your design time while providing low-power consumption with performance to spare, and the flexibility necessary for today’s competitive marketplace. The i.MX27 processor is packaged in a 404-pin MAPBGA. Differentiating features of the i.MX27 device include: • Advanced and power-efficient implementation of the ARM926EJ-S™ core, operating at speeds up to 400 MHz • enhanced Multimedia Accelerator Lite (eMMA_lt)—MPEG-4 and H.264 hardware encode or decode up to D1 resolution at 30 fps or encode and decode up to VGA resolution at 24 fps. • High-Speed USB On-The-Go controller, host or client • Smart Speed Crossbar Switch—Multi-layer AMBA-compliant bus allows any one of the six bus masters to talk to any of the three slaves without interfering with the other bus master/slave transactions to provide system level parallelism. • PCMCIA/Compact Flash Interface—Supports hot-insertion, card insert, and removal detection • Security—Software and hardware combined security solution allows secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. • Smart Power Management—Includes Run, Doze, and Sleep modes, frequency scaling, active well biasing and clock gating • LCD panels—Supports both smart and standard LCD panels • Fast Ethernet—Supports 10/100 baseT Ethernet MAC 1.1 i.MX27 Applications Processor Block Diagram Figure 1-1 is a simplified functional block diagram of the i.MX27 processor. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-1 Introduction to the i.MX27 Multimedia Applications Processor Connectivity CSPI (3) SSI (2) I2C (2) CPU Complex Wireline UART (6) USB 2.0 Internal Control 1-WIRE FEC ATA System Control JTAG/ETM9 i.MX27 Bootstrap CRM System Security SCC SAHARA2 RTIC ARM926EJ-S I-Cache MAX (Smart Speed Switch) D-Cache MMU IIM Bus Control Memory Control Multimedia Accelerator External Memory Interface M3IF Std System Resource GPT (6) PWM WDOG SRTC GPIO SDMA Video Codec eMMA Lite Multimedia Interface CSI Human Interface LCDC and SLCDC Keypad Control Expansion SDHC (3) MSHC SDRAMC EIM NFC PCMCIA/CF Figure 1-1. i.MX27 Processor Functional Block Diagram 1.2 Summary of Core and Modules This section describes the ARM926EJ-S as it applies to the i.MX27 processor and the function of the modules within the i.MX27 device. 1.2.1 ARM9™ Platform The ARM9™ Platform consists of the ARM926EJ-S core, operating at speeds up to 400 MHz at 1.6 V, and 266 MHz at 1.2 V. The ARM926EJ-S core includes a 16-Kbyte level 1 (L1) cache system, a 6 × 3 multi-layer AHB crossbar switch, and a 16 channel DMA. The ARM926EJ-S is a member of the ARM9 family of general-purpose microprocessors targeted at multi-tasking applications. The ARM9 Platform provides the following features: • ARM926EJ-S microprocessor core — 16K instruction cache and 16K data cache — High-performance ARM® 32-bit RISC engine — Thumb® 16-bit compressed instruction set for a leading level of code density MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-2 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor • • • • • • • Efficient execution of Java byte codes EmbeddedICE™ JTAG software debug 100% user code binary compatibility with ARM7TDMI™ Advanced Microcontroller Bus Architecture (AMBA™) system-on-chip multi-master bus interface — Support for mixed loads of real-time and user applications via cache locking facilities — Virtual Memory Management Unit (VMMU) Support for Little Endian only CPU and System speed — ARM926EJ-S core: up to 400 MHz — System Clock: up to 133 MHz — External memory interface: same clock source as system, up to 133 MHz at 1.8 V supply — System clock is derived from the CPU clock through an integer divider ARM Interrupt Controller (AITC) — The AITC is connected to the primary AHB as a slave device and provides support for up to 64 interrupt sources. It generates normal and fast interrupts to the processor core. The AITC supports a hardware-assisted vectoring mode for automatic vectoring to reduce interrupt latency. Clock Control Module (CLKCTL)—The CLKCTL performs block level clock gating, ARM926EJ-S JTAG synchronization requirements, as well as other miscellaneous clock control for the platform. AHB to IP bus interfaces (AIPIs)—Provide a communication interface between the high-speed AHB to a lower-speed IP bus for slave peripherals The Multi-Layer 6 × 3 AHB Crossbar Switch (MAX)—The crossbar switch allows for concurrent transactions to proceed from any input port (bus master) to any output port (bus slave): That is, it is possible for all three output ports to be active at the same time as a result of three independent input or output requests. Well Bias Charge Pump (WBCP)—With the exception of the memories, the entire ARM9 Platform supports two active well biasing to reduce leakage current to minimum levels. The well bias enable inputs (wt_en and wt_en_dnw) are driven by the external Well Bias Charge Pump (WBCP) to the ARM9 Platform. — — — — MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-3 Introduction to the i.MX27 Multimedia Applications Processor 1.2.2 System Control To ensure optimum power use and clock signal stability, the i.MX27 processor uses the following modules to generate, control, and distribute clock and control signals throughout the i.MX27 processor and to external devices. 1.2.2.1 Clock Controller Module (CCM) The CCM generates clock and reset signals used throughout the i.MX27 device and for external peripherals. It also enables system software to control, customize, or read the status of the following functions: • Chip ID • Multiplexing of I/O signals • I/O driving strength • I/O pull enable control • Well bias control • System boot mode selection • DPTC control 1.2.2.2 JTAG Controller (JTAGC) The JTAGC provides debug access to the ARM926EJ-S core and boundary scan test control. The i.MX27 processor offers designers and programers with full-debug capabilities through industry-standard JTAG interface and the ability to bootload using either a serial or USB interface. • UART Bootstrap mode function: — Allows system initialization and program or data download to system memory via USB or UART1 — Accepts execution command to run program stored in system memory — Supports memory/register read/write operation of selectable data size of byte, half-word, or word — Provides a 16-byte instruction buffer for ARM instruction storage and execution • USB Bootstrap mode function — Supports bootstrapping through USB OTG port • JTAG port to support generic ARM debug tools 1.2.3 Standard System Resources The i.MX27 processor contains various timers and resource features to optimize the control and security of both the internal modules and external devices. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-4 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor 1.2.3.1 General Purpose Timer (GPT) The six General-Purpose Timer (GPT) modules contain identical general-purpose 32-bit timers with programmable prescalers and compare and capture registers with the following features: • Automatic interrupt generation • Programmable timer input/output pins • Input capture channels capability with programmable trigger edge for each GPT • Output compare channels with programmable mode for each GPT 1.2.3.2 Pulse-Width Modulator (PWM) The Pulse-Width Modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It also generate tones. The following features characterize the PWM module: • • • 4 × 16 FIFO to minimize interrupt overhead 16-bit resolution Sound and melody generation 1.2.3.3 Real Time Clock (RTC) The Real-Time Clock (RTC) module maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features: • 32.768 kHz and 32 kHz input operation • Full clock features: seconds, minutes, hours, days • Capable of counting up to 512 days • Minute countdown timer with interrupt • Programmable daily alarm with interrupt • Sampling timer with interrupt • Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts • Interrupt generation for digitizer sampling or keyboard debouncing • Independent power supply 1.2.3.4 Watchdog Timer Module (WDOG) The Watchdog Timer module (WDOG Timer) module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. The WDOG timer module also generates a system reset using a software write to the Watchdog Control Register (WCR), a detection of a clock monitor event, an external reset, an external JTAG reset signal, or an occurrence of a power-on reset. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-5 Introduction to the i.MX27 Multimedia Applications Processor The WDOG Timer provides the following: • Programmable time out of 0.5 s to 64 s • Resolution of 0.5 s 1.2.3.5 General-Purpose I/O Ports (GPIO) The GPIO module provides six general purpose I/O ports. Each single GPIO port is a 32-bit port that may be multiplexed with one or more dedicated functions. The GPIO features are: • Supports level or edge trigger interrupt and is system wake-up capable • Most I/O signals are multiplexed with dedicated functions for pin efficiency. 1.2.3.6 Direct Memory Access Controller (DMAC) The Direct Memory Access Controller (DMAC) provides 16 channels to support linear memory, 2D memory, FIFO, and end-of-burst enable FIFO transfers to support a wide variety of DMA operations. Features include the following: • Supports 16 channels linear memory, 2D memory, and FIFO for both source and destination • Supports 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer • DMA burst length is configurable up to maximum of 16 words, 32 half-words, or 64 bytes for each channel • Bus utilization control for a channel that is not triggered by DMA request • Interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error • DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a programmed timing period • Dedicated external DMA request and grant signal • Supports increment, decrement, and no increment for source and destination addressing • Supports DMA chaining 1.2.4 Power Management and Backup Modes The i.MX27 processor’s power management features are as follows: • SupportS 3 power modes of operation: Run, Doze, and Stop • Aggressive clock gating within modules to minimize CMOS switching power • Active well biasing technique to reduce standby mode current consumption • Voltage/frequency scalable capability • Dynamic process temperature compensation 1.2.4.1 SCC, RTC, and Oscillator Power Supply The i.MX27 processor has a separate power domain from the main power domain for the SCC, RTC, and the 32 kHz oscillator (OSC32K) power supply, so that when the main power domain shuts down, the SCC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-6 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor internal memory data and status is maintained. Also, the RTC and OSC32K works as normal using the backup power supply that is provided by power management. 1.2.4.2 Enter/Exit Mode Power management provides the power_cut to indicate the main power cut: 1—main power_cut; 0—main power_on. • Mode Enter—When power_cut is set to 1 by the power management chip, then the main power can shut down. • Mode Exit—power_cut must be set to 1 when the main power is not on; after main power_on is restored (after the main power reset ends), power_cut should be set to 0. • Power On Initial—In the initial process, power_cut must be set to 0, and POR must give a valid 0 slot for the SCC, RTC power_on reset. 1.2.4.3 Reset Strategy The POR is active to the RTC and SCC. When power_cut is set to 1 (in the backed power mode), then the reset from the chip system will be gated, preventing any chip reset sources from resetting SCC and RTC. When power_cut is set to 0 (not in the backed power mode), then the reset from the chip system will be active to SCC and RTC, which means all chip reset sources can reset the SCC and RTC. 1.2.5 System Security To address the need for secure wireless communication, the i.MX27 processor provides confidentiality, authentication, integrity, and legitimacy within its architecture. This section describes the modules that provide these types of security—the Security Controller, SAHARA2, Run-Time Integrity Checker, and the IC Identification Module—whose built-in features support a broad range of security-enabled products. 1.2.5.1 Security Controller Module (SCC) The SCC is a hardware component composed of two blocks—the Secure RAM module and the Security Monitor. The Secure RAM securely stores sensitive information. The Security Monitor implements the security policy, checking algorithm sequencing, and controlling the Secure State. There is also a unique encryption key accessible only to secure RAM. 1.2.5.2 Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) SAHARA2 is a security co-processor within the i.MX27 processor used to implement block encryption algorithms, hashing algorithms, stream cipher algorithms, and hardware random number generation. SAHARA2 accelerates the following security protocols and their features: • AES encryption/decryption — ECB, CBC, CTR, and CCM modes — 128 bit key • DES/3DES MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-7 Introduction to the i.MX27 Multimedia Applications Processor • • • — EBC, CBC, and CTR modes — 56 key with parity (DES) — 112 bit or 168 bit key parity (3DES) AR4 (RC4 compatible cipher) — 5–16 byte key — Host accessible S-box MD5, SHA-1, SHA-224 and SHA-256 hashing algorithms — Message lengths are multiples of bytes — Auto padding supported — HMAC (support for IPAD and OPAD via descriptors) — Up to 4-Gbyte message length Random number generator (NIST approved PRNG – FIPS 186-2) — Entropy is generated via an independent free running ring oscillator 1.2.5.3 Run-Time Integrity Checkers (RTIC) The RTIC ensures the integrity of the contents of the peripheral memory and assists with boot authentication. The RTIC offers the following features: • SHA-1 message authentication • Input DMA (AMBA-AHB Lite1 bus master) interface • Segmented data gathering to support non-contiguous data blocks in memory (up to two segments per block) • Works with High Assurance Boot (HAB) process • Secure-scan DFT security • Support for up to four independent memory blocks • Programmable DMA bus duty cycle timer and watchdog timer • Power-saving clock gating logic • Hardware configurable Big/Little-Endian data format • Full word memory reads (word-aligned addresses, multiple of 32-bit lengths) 1.2.5.4 IC Identification Module (IIM) The IC Identification Module (IIM) provides an interface for reading, and in some cases, programming, and for overriding identification and control information stored in on-chip fuse elements. 1. AHB-Lite interface provides support for request/grant bus arbitration MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-8 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor 1.2.6 Connectivity This section describes how the modules within the i.MX27 processor interface with each other, and provides a high-level overview on how the architecture of the buses are configured and multiplexed. Bluetooth Audio SSI Voice SSI IIM I2C RS-232 IrDA IrDA GPS Bluetooth IrDA IrDA I2C AUDMUX CSPI1 CSPI2 SAHARA2 RTIC UART1 UART2 UART3 UART4 UART5 UART6 SSI1 SSI2 SECURITY MEMORY EXPANSION SCC INTERNAL CONNECTIVITY SD MSHC Secure Digital Memory Stick Pro i.MX27 MEMORY CPU ROMPATCH ETM EXTERNAL CONNECTIVITY OTG USB External Memory Interface (EMI) ESDRAM M3IF EIM Host 1 USB USB NFC PCMCIA/CF CRM MAX ETB JTAGC Host 2 Serial EEPROM EtherNet 1-Wire FEC DMAC Linear FIFO 2D MULTIMEDIA Video Codec eMMA_lt CSI HUMAN INTERFACE SLCDC LCDC KPP ATA ATAPI IDE Hard Drive MPEG-4 H.264 CCIR656 Camera Smart Displays Dumb Display KeyPad Figure 1-2. i.MX27 Connectivity Example 1.2.6.1 Configurable Serial Peripheral Interfaces (CSPI) The i.MX27 processor has three Configurable Serial Peripheral Interface (CSPI) modules that allow rapid data communication with fewer software interrupts than conventional serial communications. Each CSPI is equipped with data FIFO and is a master/slave configurable serial peripheral interface module, enabling the i.MX27 processor to interface with external SPI master or slave devices. • Master/slave configurable • Two chip-selects each for master mode operation MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-9 Introduction to the i.MX27 Multimedia Applications Processor • • Up to 16-bit programmable data transfer 8 × 16 FIFO for both transmit and receive data 1.2.6.2 Inter-IC Connectivity (I2C) Bus Module The two I2C modules are two-wire, bidirectional serial buses that provide a simple, efficient method of data exchange, minimizing the interconnection between devices. These buses are suitable for applications requiring occasional communications over a short distance between several devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development. The I2C features include: • Multiple-master operation • Software-programmable for 1 of 64 different serial clock frequencies • Interrupt-driven, byte-by-byte data transfer • Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation and detection • Repeated START signal generation • Acknowledge bit generation and detection • Bus-busy detection 1.2.6.3 Synchronous Serial Interface (SSI) The two synchronous serial interfaces are full-duplex, serial ports that enable the i.MX27 device to communicate with a variety of serial devices, such as standard codecs, digital signal processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard. Features include the following: • Supports generic SSI interface for timeslot based communication with synchronous voice codecs • Timeslot mode supports up to four channels for communication among devices, Bluetooth™ voice port, voice codecs, and baseband audio ports. • Supports Philips standard Inter-IC Sound (I2S) bus for external digital audio chip interface at 44.1 kHz and 48 kHz • AC97 Host Controller mode with support for two audio channels supporting fixed and variable rate transfers • Used together with the Digital Audio Mux (AUDMUX) module to provide flexible audio and voice routing options 1.2.6.4 Bus Control The six modules that control the bus in the MX27 are listed here. This section provides a brief description for each. • AHB-Lite IP Interface Module (AIPI) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-10 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor • • • ARM926EJ-S Interrupt Controller (AITC) Intellectual Property Bus Multiplexer (IPMUX) Multi-layer AHB Crossbar Switch (MAX) AHB-Lite IP Interface Module (AIPI) 1.2.6.4.1 The AIPI acts as an interface between the ARM Advanced High-performance Bus Lite. (AHB-Lite) and lower bandwidth peripherals that conform to the IP Bus Specification, Rev 2.0. 1.2.6.4.2 ARM926EJ-S Interrupt Controller (AITC) AITC is connected to the primary AHB as a slave device. It generates the normal and fast interrupts to the ARM926EJ-S processor. 1.2.6.4.3 Intellectual Property Bus Multiplexer (IPMUX) The Intellectual Property Bus Multiplexer (IPMUX) is used to select the read data, transfer wait, and transfer error signals from the various modules and pass it to the AIPI in the ARM9 Platform. 1.2.6.4.4 Multi-Layer AHB Crossbar Switch (MAX) The ARM926EJ-S core’s instruction and data buses and all alternate bus master interfaces arbitrate for resources via a 6 × 3 Multi-Layer AHB Crossbar Switch (MAX)—also known as a Smart Speed Switch. There are six fully functional master ports (M0–M5) and three fully functional slave ports (S0–S2). The MAX is uni-directional. All master and slave ports are AHB-Lite compliant. 1.2.7 Wireline Connectivity The i.MX27 device provides a variety of external wireline connectivity. This section describes the modules for this support. 1.2.7.1 Universal Asynchronous Receiver/Transmitter (UART) The i.MX27 processor includes six Universal Asynchronous Receiver/Transmitter (UART) modules that provide serial communication with external devices through either an RS-232 cable or by using IrDA-compatible infrared. Each of the six UARTs features the following: • Supports serial data transmit/receive operation: 7 or 8 data bits, 1 or 2 stop bits, programmable parity (even, odd, or none) • Programmable baud rates up to 1.875 MHz • Automatic baud rate detection • 32-bytes FIFO for transmit and 32 half-words FIFO for receive data • IrDA Serial Infra-Red (SIR) mode support MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-11 Introduction to the i.MX27 Multimedia Applications Processor 1.2.7.2 High Speed USB 2.0 Interface (USB) The i.MX27 processor supports three independent USB 2.0 ports, two of which support high speed (HS) operation: • OTG—High speed (480 Mbps) • Host 1—High speed (480 Mbps) • Host 2—Full speed (12 Mbps) The USB connectivity of the i.MX27 processor provides extremely fast synchronization with a PC or between two devices. Any of the USB ports may be used for transceiver-free connection or for external transceiver-based connection. The USB OTG port can connect to a PC as either a device or as a host to any of the following peripherals: keyboard, printer, mouse, speakers, storage device, digital camera, and so on. It supports 16 endpoints for each host and device. USB Host 1 is typically connected to dedicated ICs that support WLAN, Bluetooth™ wireless technology, and GPS. Host 1 supports 16 endpoints. USB Host 2 is typically used to connect to ICs for baseband or WLAN, Bluetooth wireless technology, or GPS. Host 2 supports four endpoints. 1.2.7.3 1-Wire Interface (1-Wire) The 1-Wire® module provides bi-directional communication between the ARM926EJ-S and the Add-Only-Memory EPROM (DS2502). The 1-Kbit EPROM is used to hold information about the battery and to communicate with the ARM9 Platform using the IP interface. 1.2.7.4 Advanced Technology Attachment (ATA) The Advanced Technology Attachment (ATA) block of the i.MX27 processor is an AT attachment host interface and is used to interface with IDE hard disk drives and ATAPI optical disk drives. This feature allows designers to attach storage devices at low costs per unit, which is a critical selling point in the portable digital player market. The ATA controller interfaces with ATA devices using the industry-standard ATA-6 specification. The ATA interface is compliant to the ATA-6 standard, and supports following protocols: • PIO mode 0, 1, 2, 3, and 4 • Multiword DMA mode 0, 1, and 2 • Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher • Ultra DMA modes 5 with bus clock of 80 MHz or higher 1.2.7.5 Fast Ethernet Controller (FEC) The Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. The FEC supports connection and functionality for the 10/100 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-12 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor Mbps 802.3 Media Independent Interface (MII). It requires an external transceiver (PHY) to complete the interface to the media. The FEC provides the following features: • Supports three different Ethernet physical interfaces: — 100 Mbps IEEE 802.3 MII — 10 Mbps IEEE 802.3 MII — 10 Mbps 7-wire interface (industry standard) • IEEE 802.3 full-duplex flow control • Programmable maximum frame length supports IEEE 802.1 VLAN tags and priority • Supports full-duplex operation (200 Mbps throughput) with a minimum system clock rate of 50 MHz • Supports half-duplex operation (100 Mbps throughput) with a minimum system clock rate of 25 MHz • Retransmission from transmit FIFO following a collision (no processor bus utilization) • Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization) • Address recognition — Frames with broadcast address may be always accepted or always rejected — Exact match for single 48-bit individual (unicast) address — Hash (64-bit hash) check of individual (unicast) addresses — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode 1.2.8 External Memory Interface The External Memory Interface (EMI) of the i.MX27 processor consists of the SDRAM controller (SDRAMC), the PCMCIA controller, the NAND Flash controller (NFC), and the External Interface module (EIM), using the Multi-Master Memory Interface (M3IF) as the controller through the external memory ports. The individual features of these controllers are provided in this section. To allow the maximum number of potential designs, the EMI supports the following memory types: • SDRAM—133 MHz, 32/16-bit • DDR—266 MHz, 32/16-bit • NAND Flash—dedicated 8-bit, shared 16-bit • PSRAM 1.2.8.1 Multi-Master Memory Interface (M3IF) The Multi-Master Memory Interface (M3IF) controls memory accesses from one or more masters through different port interfaces to the external memory controllers SDRAM, PCMCIA, NAND Flash, and EIM. The M3IF includes these distinctive features: • Supports multiple requests from masters through input port interfaces MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-13 Introduction to the i.MX27 Multimedia Applications Processor • • • • • • Arbitrates requests to the different memory controllers Multiple requests capabilities to SDRAMC through a dedicated arbitration mechanism Flexible round robin access arbitration, with a programmable priority scheme to selective masters Programmable master that controls (locks) accesses to SDRAM/DDR, and a programmable master that controls (locks) accesses to other memories (NFC, EIM) Multi-endianness support for all memory controllers Supports memory “snooping”—that is, monitors a region in external memory for write accesses 1.2.8.2 SDRAM Controller (SDRAMC) The SDRAM Controller (SDRAMC) provides an interface and control for synchronous DRAM memories for the system. The SDRAMC supports the following: • Optimization of consecutive memory accesses using memory command anticipation (latency hiding) — Hiding latency (or “command anticipation”) by optimizing the commands to both connected chip-selects — Monitoring open memory pages — Bank-wise memory address mapping — SDRAM burst length configuration of 41 or 8 bursts or full-page mode — MDDR burst length configuration of 8 bursts — Support of different internal burst length (1/4/8 words) by using burst truncate commands — ARM/AMBA/AHB-Lite compliant — Shared address and command bus to SDRAM/MDDR • Supports 64, 128, 256, 512 Mbit, 1 Gbit, and 2 Gbit, 4 bank, single data rate, synchronous SDRAM, and MDDR — Two independent chip-selects — Up to 128 Mbytes per chip-select — Up to four banks active simultaneously per chip-select — JEDEC standard pinout/operation • Supports mobile DDR266 devices (both 16-bit and 32-bit) • PC133 compliant interface — 133-MHz system clock achievable with “–7” option PC133 compliant memories — Single fixed-length (4/8-word) burst or full page access — Access time of 9-1-1-1-1-1-1-1 at 133 MHz (for read access when the memory bus is available, the row is open and CAS latency configured to three cycles). The access time includes the M3IF delay (assuming there is no arbitration penalty). • Software configurable for different system and memory devices requirements — 16-bit or 32-bit memory data bus width 1. For 16-bit memory burst length 4 is not supported. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-14 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor • • — Many row and column addresses — Row cycle delay (tRC) — Row precharge delay (tRP) — Row-to-column delay (tRCD) — Column-to-data delay (CAS latency) — Load mode register to active command (tMRD) — Write to precharge (tWR) — Write to read (tWTR) for MDDR memories only — MDDR exit power down to next valid command delay (tXS) — Active to precharge (tRAS) — Active to active (tRRD) Built-in auto-refresh timer and state machine Hardware and software supported self-refresh entry and exit — Keeps data valid during system reset and low-power modes — Auto Power Down timer (one per chip-select) — Auto Precharge timer (one per bank in each chip-select) 1.2.8.3 NAND Flash Controller (NFC) The NAND Flash controller (NFC) interfaces standard NAND Flash memory devices to the i.MX27 processor and hides the complexities of accessing NAND Flash. The NFC features include: • Contains hardware boot loader for automatic boot up from NAND Flash devices • Supports all 8-bit/16-bit NAND Flash devices regardless of density and organization • Supports 512-byte and 2-Kbyte page sizes • Internal 2 Kbytes of buffer RAM used as boot RAM during cold startup and as read/write page buffers to relieve CPU intervention • Automatic ECC detection and selectable correction • Data protection for RAM buffer and NAND Flash pages 1.2.8.4 Personal Computer Memory Card International Association (PCMCIA) The PCMCIA host adapter module provides the control logic for PCMCIA socket interfaces, and requires some additional external analog power switching logic and buffering. The PCMCIA controller provides the following features: • A host adapter interface fully compliant with the PCMCIA standard release 2.1 (PC Card -16) — Supports one PCMCIA socket — Supports hot-insertion — Supports card detection MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-15 Introduction to the i.MX27 Multimedia Applications Processor • • — Mappings to common memory space, attribute memory space, and I/O space. Each space is up to 64 Mbytes in size. — Supports five memory windows — Generates a single interrupt to the CPU — PC card access timing is fully programmable — Handles interrupts from the card The pcmcia_if signal is part of the EMI complex and shares pins with the EIM, SDRAMC, and NFC controller. Supports ATA disk emulation 1.2.8.5 External Interface Module (EIM) The External Interface Module (EIM) interfaces to devices external to the chip, including generation of chip-selects, clock and control for external peripherals, and memory. The EIM provides asynchronous and synchronous access to devices with an SRAM-like interface. The EIM includes the following features: • Six chip-selects for external devices, with CS [0] and CS [1] each covering a range of 128 Mbytes, and CS [2] – CS [5], each covering a range of 32 Mbytes • CS [0] range can be increased to 256 Mbytes when collapsed with CS [1] • Selectable protection for each chip-select • Programmable data port size for each chip-select • Asynchronous accesses with programmable setup and hold times for control signals • Synchronous Memory Burst Read Mode support for AMD, Intel, and Micron burst flash memory • Synchronous Memory Burst Write Mode support for PSRAM (CellularRAMTM from Micron, Infineon, and Cypress) • Support for multiplexed address/data bus operation • External cycle termination/postpone with DTACK signal • Programmable wait-state generator for each chip-select • Support for Big Endian and Little Endian modes of operation per access • ARM AHB slave interface 1.2.9 Memory Expansion The i.MX27 processor offers memory expansion options for SD, Memory Stick Pro®, and ATA-6. Each expansion port reflects the latest version of the respective specification for that interface. Brief descriptions of each expansion port follow. 1.2.9.1 Memory Stick Host Controller (MSHC) The i.MX27 processor’s Memory Stick Host Controller supports one Memory Stick Pro slot. The MSHC conforms to Memory Stick Standard Format Specifications, ver.1.4-00 and Memory Stick Standard MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-16 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor Memory Stick PRO Format Specification, ver.1.00-01. The MSHC communication is based on an advanced 7-pin serial bus designed to operate in a low-voltage range. In addition to multimedia cards, the module can be used to communicate to high-bit rate communication devices, such as WLAN 802.11 a/b, and Bluetooth wireless technology, among others. The MSHC is placed between the AIPI and the customer memory stick to support data transfer from the i.MX27 device to the customer memory stick. 1.2.9.2 Secured Digital Host Controller (SDHC) The three Secured Digital Host Controllers (SDHC) in the i.MX27 device control the Secure Digital memory cards and I/O functions by sending commands to the cards and performing data accesses to and from the cards. SDHC features include: • Fully compatible with the SD Memory Card Specification 1.0 and SD I/O Specification 1.0 with 1 and 4 channel(s) • Supports hot swappable operation • Data rates from 25 Mbps to 100 Mbps • Dedicated power pin 1.2.10 Video Codec and enhanced Multimedia Accelerator Lite (eMMA_lt) The i.MX27 processor uses a Video Codec and an enhanced Multimedia Accelerator Lite (eMMA_lt) to provide H.264, MPEG-4 and H.263 hardware acceleration with pre- and post-processing. 1.2.10.1 Video Codec The Video Codec module supports full-duplex video codec with MPEG-4 and H.264 hardware encode or decode up to D1 resolution at 30 fps or encode and decode up to VGA resolution at 24 fps, and integrates multiple video processing standards, such as H.264 BP, MPEG-4 SP, and H.263 P3. The Video Codec architecture is shown in the Figure 1-3. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-17 Introduction to the i.MX27 Multimedia Applications Processor CRM Clock and Reset ahb64_sel Video Processing IP 32bit AXI AXI to AHB bus Read Channel 1 and 2 Logic 64bit Memories Block Write Channel Logic 32to64 Gasket 64bit EMI 64bit Memory Bist Engine APB to IP Bus 32 bit Test Signal Internal SRAM AIPI Interrupt Signal Figure 1-3. Video Codec Architecture Diagram The Video Codec provides the following capabilities: • Multi-standard video codec — MPEG-4 part-II Simple Profile (SP) encoding/decoding — H.264/AVC Baseline Profile (BP) encoding/decoding — H.263 P3 encoding/decoding — Multi-party call: One stream encoding and two streams decoding simultaneously — Multi-format: Encodes MPEG-4 bitstream, and decodes H.264 bitstream simultaneously • Coding tools — High-performance motion estimation (single reference frame for both MPEG-4 and H.264 encoding) – Quarter-pel and half-pel accuracy motion estimation – [±16, ±16] search range — All variable block sizes are supported. (In case of encoding, 8 × 4, 4 × 8, and 4 × 4 block sizes are not supported.) — Unrestricted motion vector — MPEG-4 AC/DC prediction and intra-prediction (H.264) — H.264/AVC intra-prediction MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-18 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor • • • — H.263 Annex I, J, K, and T are supported — Error resilience tools – MPEG-4 resync. marker and data-partitioning with RVLC (fixed number of bits/macroblocks between macroblocks) – H.264/AVC FMO and ASO – H.263 slice structured mode – Bit-rate control (CBR and VBR) Pre/post rotation/mirroring — 8 rotation/mirroring modes for image to be encoded — 8 rotation/mirroring modes for image to be displayed Programmability — Embeds C and M proprietary 16-bit DSP processor that is dedicated to processing bitstream and driving the codec hardware — General purpose registers and interrupt for communication between internal host processor and Video Codec IP Performance — Up to full-duplex VGA 24 fps encoding/decoding — Up to half-duplex SD 30 fps encoding/decoding 1.2.10.2 enhanced Multimedia Accelerator Lite (eMMA_lt) The i.MX27 processor comes with an enhanced Multimedia Accelerator Lite (eMMA_lt), which comprises independent pre-processing and post-processing stages that provide exceptional image and video quality. The eMMA_lt represents a major breakthrough to solve the problem of high MIPS required for video encode and decode operations in mobile and wireless applications. Tight integration and memory pipelining coupled with AHB master mode operation ensure minimal system loading. To further offload the CPU, live video stream data enters the eMMA_lt module directly through an internal private data interface. The i.MX27 processor’s eMMA_lt features the following: • Enables simultaneous MPEG-4 Simple Profile (SP) video encoding and decoding • Supports real-time video decode in any of the following advanced formats: — MPEG-4 Simple Profile (SP) — H.264 • Provides video and image data pre/post-processing (resizing, color conversion, filtering) that is fully hardware accelerated The eMMA_lt architecture is shown in Figure 1-4. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-19 Introduction to the i.MX27 Multimedia Applications Processor IP bus IP bus Interface Post Processing PreProcessing Sensor data From CSI Bus Arbitration AHB bus Figure 1-4. eMMA_lt Architecture 1.2.10.2.1 Image Pre-Processor (PrP) The image Pre-Processor block performs color space conversion and image resizing for the viewfinder display, and data formatting for the video encoder. It also performs color space conversions of the still image for input to either a hardware- or software-based video encoder or image compressor. The Pre-Processor has two media input and output paths and can accept input from system memory or from a private data bus connected to the CMOS Sensor Interface (CSI) module. The Pre-Processor can apply frame rate control on the live video stream from the CSI module to adjust for different processing load conditions. The Pre-Processor’s two output channels are used to output RGB data for display of the local camera view and to output image data for compression by the hardware encoder or a software encoder (still image or video encode). Figure 1-5 shows the image Pre-Processor. CMOS Sensor Interface Main Resize Color Space Conversion Second Frame Buffer (RGB/YUV) Pre-Processor Optional data paths using dumb CMOS sensors Resize System Memory YUV 4:2:2,4:2:0, 4:4:4 RGB Display Buffer Viewfinder Compression or video encode Figure 1-5. Pre-Processor Data Flow Pre-Processor features: • Data input: — System memory — Private DMA between CMOS Sensor Interface module and Pre-Processor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-20 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor • • • • • Data input formats: — Arbitrarily unpacked RGB input — YUV 4:2:2 (Interleaved) — YUV 4:2:0 (Planar) Input image size: 2044 × 2044 Image scaling: — Main resize ratio: 8:1–1:1 in integral steps, Horizontal 9:8/vertical 6:5 and Horizontal 9:8/Vertical 1:1 — Secondary resize ratio for viewfinder: 8:1–1:1 in integral steps Output data format: — RGB565 — YUV 4:2:2 (Interleaved) — YUV 4:2:0 (Planar) RGB data and one YUV data format can be generated concurrently Post-Processor (PP) 1.2.10.2.2 The Post-Processor performs Deblock, Dering, Image Resize, and Color Space Conversion (CSC) functions on the input image data. These functions provide flexibility to meet various RGB formats and YUV formats for display. In addition to working in tandem with the decoder sub-block in the eMMA_lt, the Post-Processor can also be used by software decoders (other than MPEG-4) to touch up the final output before display. The sub-blocks that perform Deblock, Dering, Resize, and CSC operations can be selectively bypassed through software configuration. Figure 1-6 shows the flow for video postprocessing. MPEG-4 Decoder Current/ Ref Frame Deblock Current/ Ref Frame Dering Image Resize Color Conversion RGB Display Buffer Post-Processor Figure 1-6. Post-Processor Post-Processor features: • Input data: — From system memory • Input format: — YUV 4:2:0 (Planar) • Output format: — YUV422 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-21 Introduction to the i.MX27 Multimedia Applications Processor • • — RGB444 — RGB565 — RGB666 — RGB888 (unpacked) Input Size: Maximum size of 2044 × 2044 Image Resize: — Upscaling ratios ranging from 1:1 to 1:4 in fractional steps — Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1 — Ratios provide scaling between QCIF, CIF, QVGA (320 × 240) and QVGA (240 × 320) 1.2.10.3 Digital Audio Multiplexer (AUDMUX) The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnect fabric for voice, audio, and synchronous data routing between the i.MX27 processor’s SSI modules and external SSI, audio, and voice codecs. The AUDMUX is designed so that resource configurations do not need to be hard-wired, but instead, can be shared in many different configurations. The AUDMUX interconnections allow multiple simultaneous separate audio/voice/data flows between the ports in a point-to-point or point-to-multipoint configuration(s). In a typical scenario, the AUDMUX and two SSI/I2S modules provide interfaces to the Serial Audio Port of the cellular baseband (BB), narrowband (NB), and wideband (WB) audio ports of the external audio AD/DA, and to the audio port of the Bluetooth wireless technology on-board peripheral. See Figure 1-7. Power Management IC Voice Codec Stereo DAC Blue tooth Alert Tone i.MX27 i.MX31/i.MX31L WB SSI1 MP3 MP3 i.MX27 i.MX31/i.MX31L NB Voice Notes Voice Notes Port 1 Port Port 4 4 Port 4 (External) (External) (External) BluetoothTM IC Voice ADC/DAC Audio ADC/DAC Voice AUDMUX SSI2 Port 2 Port Port 6 6 Port 6 (External) (External) (External) Baseband IC Voice BB SAP Port 3 Port Port 7 7 Port 7 (External) (External) (External) IO MUX Port Port 5 5 Port 5 (External) (External) (External) Option Voice Call Figure 1-7. Typical AUDMUX Application MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-22 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor 1.2.11 MultiMedia Interface The CMOS Sensor Interface (CSI) provides multimedia interfacing. 1.2.11.1 CMOS Sensor Interface (CSI) The CMOS Sensor Interface (CSI) is a logic interface that enables the i.MX27 device to connect directly to external CMOS sensors and a CCIR656 video source. The sensor port provides a connection to either one or two image sensors, of which only one sensor can be active at any given time. The sensor port supports a direct parallel interface to either CMOS or CCD sensor controllers using a parallel interface with widths of 12 bits, 10 bits, 8 bits, or 4 bits at data bus rates up to 60 MHz. The sensor port may be configured to perform outputs of a still image to a non-contiguous memory buffer, enabling efficient memory use under an open OS. The capabilities of the CSI include: • Configurable interface logic to support common available CMOS sensors in the market • Support traditional sensor timing interface • Support CCIR656 video interface, progressive mode for smart sensor, interlace mode for PAL and NTSC input • 8-bit input port for YCC, YUV, Bayer, or RGB data • 32 × 32 FIFO storing image data supporting core data read and DMA data burst transfer to system memory • Full control of 8-bit and 16-bit data to 32-bit FIFO packing • Direct interface to the eMMA_lt Pre-Processing block (PrP) • Single interrupt source to the interrupt controller from maskable sensor interrupt sources: Start of Frame, End of Frame, Change of Field, FIFO full • Configurable master clock frequency output to sensor • Asynchronous input logic design. Sensor master clock can be driven by either the i.MX27 processor or by an external clock source. • Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the camera (for Bayer data only) 1.2.12 Human Interface The i.MX27 processor can connect to a wide variety of popular display devices, such as: • RAM-less LCD panels—up to 40 Mpix/s (for example, SVGA @ 80 fps), 262k colors. Results are dependent on end application. • LCD panels with integrated frame buffer—up to 1024 × 1024, 14M colors. Results are dependent on end application. • Graphics accelerators • TV encoders MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-23 Introduction to the i.MX27 Multimedia Applications Processor The i.MX27 processor’s display ports enable simultaneous connectivity of up to two displays—an LCD without memory and a TV encoder—as well as provides connectivity to three interface types: • Synchronous parallel (18-bit) • Asynchronous parallel (18-bit) • Asynchronous Serial (SPI-like) at a bus rate of up to 100 MHz 1.2.12.1 Liquid Crystal Display Controller (LCDC) The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD panels. The LCDC features include the following: • Software programmable screen size (up to 800 × 600) to support single (non-split) monochrome, color STN panels, and color TFT panels • Support for color depth for CSTN panels: 4- or 8-bit mapping from 256 × 18 table, 12-bit true color • Support for color depth for TFT panels: 4- or 8-bit mapping from 256 × 18 table, 16-bit/18-bit/24-bit true color • Up to 16 grey levels out of 16 palettes • Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp, Hitachi, and Toshiba • Support for data bus width of 16-bit or 18-bit TFT panels • Support for the AUO panel in 16 bpp and 24 bpp pixel modes • Support for data bus widths of 8-bit, 4-bit, 2-bit, and 1-bit monochrome LCD panels • Direct interface to Sharp® 320 × 240 and 240 × 320 HR-TFT panels and other generic panels • Support for logical operation between color hardware cursor and background • LCD contrast control using 8-bit PWM • Support for self-refresh LCD modules • Hardware panning (soft horizontal scrolling) • Windowing support for one graphic or text overlay 1.2.12.2 Smart Liquid Crystal Display Controller (SLCDC) The Smart Liquid Crystal Display Controller (SLCDC) transparently and efficiently transfers image data from system memory to an external LCD controller. The SLCDC module contains a DMA controller that transfers image and control data from system memory to the SLCDC FIFO, where it is formatted and sent out to the external LCD controller. The SLCDC can be configured to write image data to an external LCD controller via a 4-line serial, 3-line serial, or 8- or 16-bit parallel interface. The SLCDC has two FIFOs where command and display data are loaded via DMA. The display data is tagged with commands that are used by the SLCDC to communicate display information and data to the Smart LCD panel. The command tagged data format of the SLCDC provides flexibility and ease of connection to existing and new smart LCD panels. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-24 Freescale Semiconductor Introduction to the i.MX27 Multimedia Applications Processor 1.2.12.3 Keypad Port (KPP) The Keypad Port (KPP) is used for key pad matrix scanning or as a general purpose I/O. This peripheral simplifies the software task of scanning a keypad matrix. Features include: • Up to 8 × 8 external key pad matrix support • Open drain design • Glitch suppression circuit prevents erroneous key detection • Multiple keys detection • Standby key press detection 1.2.13 Packaging Information The i.MX27 processor is offered in the 404 MAPBGA package option. This package brings out all the new interfaces, and supplies more flexible multiplexing. • • • Type: 0.65 mm pitch Dimensions: 17 mm × 17 mm Balls: 404 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1-25 Introduction to the i.MX27 Multimedia Applications Processor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 1-26 Freescale Semiconductor Chapter 2 System Memory and Register Map 2.1 Introduction This chapter provides the i.MX27 Multimedia Applications Processor’s memory maps and chip configuration registers. 2.2 Memory Space The i.MX27 Multimedia Applications Processor, with a 32-bit address bus, is capable of addressing a 4-Gbyte physical address space. This space is divided into sections of 512-Mbyte regions within which various memories and peripherals are mapped. Table 2-1 shows a simplified breakdown of the eight 512-Mbyte regions decoded within the 4-Gbyte address space. Table 2-1. 4 Gbyte Memory Map Breakdown Address Size Usage ROM, Primary AHB Slaves, and Peripherals Reserved Reserved Reserved Secondary AHB Slave Port 1 Secondary AHB Slave Port 2 Primary AHB (RAM) 0x0000_0000 512 Mbyte 0x2000_0000 512 Mbyte 0x4000_0000 512 Mbyte 0x6000_0000 512 Mbyte 0x8000_0000 512 Mbyte 0xA000_0000 1 Gbyte 0xE000_0000 512 Mbyte 2.2.1 Detailed Memory Map Figure 2-2 shows the memory space breakout view for the i.MX27 processor. The left-most column shows the eight 512-Mbyte regions. The middle column shows the breakout of primary and secondary AHB slaves, and the right-most column shows the breakout of the AIPI1 and AIPI2 address spaces. Table 2-2 through Table 2-5 show the detailed breakdown of the complete memory map according to the 512-Mbyte regions. Table 2-6 and Table 2-7 show the detailed breakdown of the AIPI1 and AIPI2 modules and the different IP peripherals accessed over the AIPI1 and AIPI2. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-1 System Memory and Register Map WB Audio Voice BT CE Battery Ctl MU MU MU MU IPMUX IPMUX AUDMUX SSI 1 2 10 [16] IIM SLID [22] RAM [12,13] SCC OSC32K SSI 2 [17] OWIRE IP Bus 2 CSPI 1 [14] CSPI 2 [15] CSPI 3 [23] [9] WDOG Interrupt IP Bus 1 [2] WDOG [21] [8] MPLL SPLL [7] [7] ETM ARM926EJ-S IP bus GPIO KPP PWM I2C1 GPIO 8x8 Keypad Pulse Width Mod. In/Out MU MU OSC26M CRM RTC SAHARA2 [6] eMMA_lt [1] DMA [10] RTIC ARM926 PLATFORM CLKCTL JTAG SYNC MU AITC ETB MCTL AIPI 1 AIPI 2 Primary AHB IP bus [6] [18] ETM9 JAM IP bus PAHBMUX 6x3 MAX Camera CSI ABCD [5] D-$ D-AHB I-$ I-AHB ROMPATCH I-AHB Patch D-AHB Patch m0 S0 m1 S1 m2 S2 m3 m4 m5 To CRM ATA [24] Hard Drive Memory Stick MS/Pro MMC/SD Card MMC/SD Card MMC/SD Card MU TMAX TMAX MU ARM926EJ-S Platform MSHC [19] [20] [30] MCU M2 Internal 45 Kbyte 24 Kbyte ROM Memory RAM SROUTER 64-bit TMAX SDHC1 SDHC2 SDHC3 LCD Display 1 LCD Display 2 10/100baseT PHY [2] SLCDC [1] LCDC TCU JTAGC TMAX FEC [11] [3] EMI 0 1 2 3 4 5 6 7 PCMCIA NFC WEIM ESDCTL Video Codec USB2.0 IrDA/WLAN BB + RF IrDA IrDA IrDA MU [4] [10] PCMCIA/CF NAND Flash NOR-Flash SDRAM (SDR and DDR) M3IF UART1 UART2 SCC, CRM, SAHARA2 [11] [12] i.MX27 [27] UART 5 MU IrDA IIM [8] [29] UART3 [13] UART4 I2C2 USB ctl MU [28] UART 6 MU [3] GPT 1 MU [4] GPT 2 MU [5] GPT 3 MU [25] GPT 4 MU [26] GPT 5 MU [31] GPT 6 MU IPC MCU MemoryMapped Module Other Modules like test, PLLs or memories (all sizes in KByte) Module without DMA Module with internal DMA COLOR LEGEND DMA LEGEND PAD-MUX LEGEND MUX Functional pad muxing with other peripherals in some modes Module with DMA-req to DMA Module with internal DMA and DMA-req to DMA Figure 2-1. Detailed Block Diagram for the i.MX27 Processor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-2 Freescale Semiconductor System Memory and Register Map NOTE Accesses to locations defined as Reserved (other than aliased RAM space) result in an AHB error response. Accesses to unimplemented locations within the AITC register spaces will be terminated, write accesses will have no effect, and read accesses will return all zeros. Table 2-2 shows the memory map of the Primary AHB address space in the first 512-Mbyte region. Table 2-2. Primary AHB Memory Map (Lower) Address 0x0000_0000–0x0000_3FFF 0x0000_4000–0x0040_3FFF 0x0040_4000–0x0040_5FFF 0x0040_6000– 0x007F_FFFF 0x0080_0000–0x0FFF_FFFF 0x1000_0000–0x1001_FFFF 0x1002_0000–0x1003_FFFF 0x1004_0000–0x1004_0FFF 0x1004_1000– 0x1004_1FFF 0x1004_2000–0x7FFF_FFFF Secondary AHB Slave Port 1 BROM Reserved BROM BROM (Hole) Reserved AIPI1 AIPI2 AITC ROM Patch Reserved Size 16 Kbyte 4 Mbyte 8 Kbyte 3 Mbyte + 1000 Kbyte 248 Mbyte 128 Kbyte 128 Kbyte 4 Kbyte 4 Kbyte 255 Mbyte + 752 Kbyte Table 2-3 shows the memory map of the CSI and ATA modules when connected to the Secondary AHB Ports 1 via the ABCD. The BROM (hole) is split into two sections of 16 Kbytes and 8 Kbytes. The BROM (Hole) indicates that there is no BROM code present in this region. The AIPI1 and AIPI2 address space contains AIPI control registers and the IP slave registers. The AIPI1 and AIPI2 maps are shown in Table 2-6 and Table 2-7, respectively. Table 2-3. Secondary AHB Port 1 Memory Map Address 0x8000_0000–0x8000_0FFF 0x8000_1000–0x8000_1FFF 0x8000_2000–0x9FFF_FFFF Secondary AHB Port 1 CSI ATA Reserved Size 4 Kbyte 4 Kbyte 512 Mbyte–8 Kbyte Figure 2-2 shows the i.MX27 processor’s physical memory map (4 Gbytes). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-3 System Memory and Register Map Base Address 16 Kbyte 0x0000 0000 0x1000 0000 0x1002 0000 0x1002 0FFF 0x1002 1000 0x1002 1FFF 0x1002 2000 0x1002 2FFF 0x1002 3000 0x1002 3FFF 0x1002 4000 0x1002 4FFF 0x1002 5000 0x1002 5FFF 0x1002 6000 0x1002 6FFF 0x1002 7000 0x1002 7FFF 0x1002 8000 0x1002 8FFF 0x1002 9000 0x1002 9FFF 0x1002 A000 0x1002 AFFF BROM 0x0000 3FFF 0x0000 4000 4 Mbyte 0x1000 0000 128 Kbyte 0x1000 0FFF 0x1000 1000 0x1000 1FFF 0x1000 2000 AIPI1 DMA WDOG GPT1 GPT2 GPT3 PWM RTC KPP OWIRE UART1 UART2 UART3 UART4 CSPI1 CSPI2 SSI1 SSI2 I2C1 SDHC1 SDHC2 GPIO AIPI2 LCDC SLCDC H.264 USB2.0 SAHARA2 eMMA_lt CRM IIM Reserved RTIC FEC SCC SCC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AIPI1 0x1001 FFFF 0x1002 0000 128 Kbyte Reserved 0x0040 3FFF 0x0040 4000 4 Mbyte 16 Kbyte 0x1000 2FFF 0x1000 3000 0x1000 3FFF 0x1000 4000 BROM 0x007F FFFF 0x0080 0000 248 Mbyte 0x1003 1FFF 0x1004 0000 0x1004 0FFF 0x1004 1000 0x1004 1FFF 72 K byte AIPI2 Reserved 36 K 20 K byte AITC ROM Patch 4 Kbyte 0x1000 4FFF 0x1000 5000 4 Kbyte 0x1000 5FFF 0x1000 6000 0x1000 6FFF 0x1000 7000 Reserved 0x0FFF FFFF 0x1000 0000 264 Kbyte 0x1000 7FFF 0x1000 8000 Internal Registers 0x1004 1FFF 0x1004 2000 256 Mbyte - 0x1000 8FFF 0x1000 9000 0x1000 9FFF 0x1000 A000 0x1002 B000 0x1002 BFFF 0x1002 C000 0x1002 CFFF 0x1002 D000 0x1002 DFFF 0x1002 E000 0x1002 EFFF 0x1002 F000 0x1002 FFFF 0x1003 0000 0x1003 0FFF 0x1003 1000 0x1003 1FFF 0x1003 2000 0x1003 2FFF 0x1003 3000 0x1003 3FFF 0x1003 4000 0x1003 4FFF 0x1003 5000 0x1003 5FFF 0x1003 6000 0x1003 6FFF 0x1003 7000 Reserved 280 Kbyte 0xA000 0000 256 Mbyte 0x1000 AFFF 0x1000 B000 0x1000 BFFF 0x1000 C000 CSD0 (SDRAM) active low 0xAFFF FFFF 0xB000 0000 256 Mbyte 0x1FFF FFFF 0x2000 0000 0x1000 CFFF 0x1000 D000 0x1000 DFFF 0x1000 E000 CSD1 (SDRAM) active low 0xBFFF FFFF 0xC000 0000 128 Mbyte 0x1000 EFFF 0x1000 F000 CS0 (Flash) active low 1536 MB 0x1000 FFFF 0x1001 0000 128 Mbyte 0x1001 0FFF 0x1001 1000 0x1001 1FFF 0x1001 2000 32 Mbyte 0x1001 2FFF 0x1001 3000 Reserved 0xC7FF FFFF 0xC800 0000 CS1 (Flash) active low 0xCFFF FFFF 0xD000 0000 CS2 (Ext SRAM) active low 0xD1FF FFFF 0xD200 0000 0x7FFF FFFF 0x8000 0000 512 Mbyte 32 Mbyte 0x1001 3FFF 0x1001 4000 0x1001 4FFF 0x1001 5000 CSI (4KB) ATA(4KB) Reserved External CS3 (Spare) active low 0xD3FF FFFF 0xD400 0000 32 Mbyte 0x1001 5FFF 0x1001 6000 0x1001 6FFF 0x1001 7000 AUDMUX Reserved CSPI3 MSHC GPT4 GPT5 UART5 UART6 Reserved Reserved Reserved Reserved ETB Regs ETB RAM 0x1003 7FFF 0x1003 8000 0x1003 8FFF 0x1003 9000 0x1003 9FFF 0x1003 A000 0x1003 AFFF 0x1003 B000 0x1003 BFFF 0x1003 C000 0x1003 CFFF 0x1003 D000 0x1003 DFFF 0x1003 E000 0x9FFF FFFF 0xA000 0000 Memory (960 Mbyte) Reserved EMI (20 Kbyte) 1 Gbyte 0xD5FF FFFF 0xD600 0000 CS4 (Spare) active low 32 Mbyte 0x1001 7FFF 0x1001 8000 0x1001 8FFF 0x1001 9000 0xDFFF FFFF 0xE000 0000 Reserved 511 Mbyte CS5 (Spare) active low 0xD7FF FFFF 0xD800 0000 64 Mbyte 0x1001 9FFF 0x1001 A000 0x1001 AFFF 0x1001 B000 0x1001 BFFF 0x1001 C000 64 Mbyte 0x1001 CFFF 0x1001 D000 EMI Modules 5X4 KByte Reserved Reserved 979 Kbyte 0xFFEF FFFF 0xFFF0 0000 0xFFFF 4BFF 0xFFFF 4C00 0xFFFF FFFF 0xDBFF FFFF 0xDC00 0000 Reserved VRAM (45 Kbyte) 45 Kbyte PCMCIA/CF 0xDFFF FFFF 0x1001 DFFF 0x1001 E000 0x1001 EFFF 0x1001 F000 0x1001 FFFF I2C2 CS5 ETB RAM (Spare) active JAM SDHC3 low GPT6 MAX 0x1003 EFFF 0x1003 F000 0x1003 FFFF Figure 2-2. i.MX27 Processor’s Physical Memory Map (4 Gbytes) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-4 Freescale Semiconductor System Memory and Register Map Table 2-4 shows the memory map breakdown for the Secondary AHB Port 3. The SDRAMC, WEIM, PCMCIA, and NFC module control registers and external memory are addressed via this region. The external memory regions (memory or external peripherals) are accessed via the respective chip selects. CSD1 and CSD0 are SDRAMC chip selects, and CS5 to CS0 are WEIM chip selects. CSD1 and CS0 chip select spaces are available for external boot. 0xBC000 0000 to 0xDFFF_FFFF is allocated for PCMCIA IO and memory space. Table 2-4. Secondary AHB Port 2 Memory Map Address 0xA000_0000–0xAFFF_FFFF 0xB000_0000–0xBFFF_FFFF 0xC000_0000–0xC7FF_FFFF 0xC800_0000–0xCFFF_FFFF 0xD000_0000–0xD1FF_FFFF 0xD200_0000–0xD3FF_FFFF 0xD400_0000–0xD5FF_FFFF 0xD600_0000–0xD7FF_FFFF 0xD800_0000–0xD800_0FFF 0xD800_1000–0xD800_1FFF 0xD800_2000–0xD800_2FFF 0xD800_3000–0xD800_3FFF 0xD800_4000–0xD800_4FFF 0xD800_5000–0xDBFF_FFFF 0xDC00_0000–0xDFFF_FFFF Secondary AHB Port 3 External SDRAM/MDDR (CSD0) External SDRAM/MDDR (CSD1) WEIM External Memory (CS0) WEIM External Memory (CS1) WEIM External Memory (CS2) WEIM External Memory (CS3) WEIM External Memory (CS4) WEIM External Memory (CS5) NFC registers and internal RAM SDRAMC registers WEIM registers M3IF registers PCMCIA registers Reserved PCMCIA Memory Space Size 256 Mbyte 256 Mbyte 128 Mbyte 128 Mbyte 32 Mbyte 32 Mbyte 32 Mbyte 32 Mbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 64 Mbyte–20 Kbyte 64 Mbyte Table 2-5 shows the last region of address space that is part of the Primary AHB Memory Map. The Vector-RAM is mapped into this region and the i.MX27 device uses the high memory (0xFFFF FF00–0xFFFF FFFF) to store the interrupt vector table (64 words). This region is aliased on a 128-Kbyte boundary. Table 2-5. Primary AHB Memory Map (Upper) Address 0xE000_0000–0xFFEF_FFFF 0xFFF0_0000–0xFFFF_4BFF 0xFFFF_4C00–0xFFFF_FFFF Primary AHB Reserved (aliased) VRAM Space Not Use 45 Kbyte VRAM Size 511 Mbyte 979 Kbyte 45 Kbyte Table 2-6 and Table 2-7 show the detailed breakdown of the address space controlled by AIPI1 and AIPI2. More details on the AIPI can be found in Chapter 35, “AHB-Lite IP Interface (AIPI) Module.” MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-5 System Memory and Register Map Table 2-6. AIPI1 Memory Map Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x1000_0000–0x1000_0FFF 0x1000_1000–0x1000_1FFF 0x1000_2000–0x1000_2FFF 0x1000_3000–0x1000_3FFF 0x1000_4000–0x1000_4FFF 0x1000_5000–0x1000_5FFF 0x1000_6000–0x1000_6FFF 0x1000_7000–0x1000_7FFF 0x1000_8000–0x1000_8FFF 0x1000_9000–0x1000_9FFF 0x1000_A000–0x1000_AFFF 0x1000_B000–0x1000_BFFF 0x1000_C000–0x1000_CFFF 0x1000_D000–0x1000_DFFF 0x1000_E000–0x1000_EFFF 0x1000_F000–0x1000_FFFF 0x1001_0000–0x1001_0FFF 0x1001_1000–0x1001_1FFF 0x1001_2000–0x1001_2FFF 0x1001_3000–0x1001_3FFF 0x1001_4000–0x1001_4FFF 0x1001_5000–0x1001_5FFF 0x1001_6000–0x1001_6FFF 0x1001_7000–0x1001_7FFF 0x1001_8000–0x1001_8FFF 0x1001_9000–0x1001_9FFF 0x1001_A000–0x1001_AFFF 0x1001_B000–0x1001_BFFF 0x1001_C000–0x1001_CFFF 0x1001_D000–0x1001_DFFF 0x1001_E000–0x1001_EFFF 0x1001_F000–0x1001_FFFF AIPI1 Memory Map AIPI1 (slot 0) DMA WDOG GPT1 GPT2 GPT3 PWM RTC KPP OWIRE UART1 UART2 UART3 UART4 CSPI1 CSPI2 SSI1 SSI2 I2C1 SDHC1 SDHC2 GPIO AUDMUX CSPI3 MSHC GPT4 GPT5 UART5 UART6 I2C2 SDHC3 GPT6 Size 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-6 Freescale Semiconductor System Memory and Register Map Table 2-7. AIPI2 Memory Map Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14–26 27 28 29 30 31 0x1002_0000–0x1002_0FFF 0x1002_1000–0x1002_1FFF 0x1002_2000–0x1002_2FFF 0x1002_3000–0x1002_3FFF 0x1002_4000–0x1002_4FFF 0x1002_5000–0x1002_5FFF 0x1002_6000–0x1002_6FFF 0x1002_7000–0x1002_7FFF 0x1002_8000–0x1002_8FFF 0x1002_9000–0x1002_9FFF 0x1002_A000–0x1002_AFFF 0x1002_B000–0x1002_BFFF 0x1002_C000–0x1002_CFFF 0x1002_D000–0x1002_DFFF 0x1002_E000–0x1003_AFFF 0x1003_B000–0x1003_BFFF 0x1003_C000–0x1003_CFFF 0x1003_D000–0x1003_DFFF 0x1003_E000–0x1003_EFFF 0x1003_F000–0x1003_FFFF AIPI2 Memory Map AIPI2 (Slot 0) LCDC SLCDC Reserved USB2.0 SAHARA2 eMMA_lt CRM IIM Reserved RTIC FEC SCC SCC Reserved (slots 14–26) ETB Regs ETB RAM ETB RAM JAM MAX Size 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 52 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 2.3 Register Map Table 2-8. Register Map The internal registers in the i.MX27 processor are listed in Table 2-8. Module Name AIPI1 AIPI1 AIPI1 AIPI1 DMAC DMAC DMAC Address 0x1000_0000 0x1000_0004 0x1000_0008 0x1000_000C 0x1000_1000 0x1000_1004 0x1000_1008 Register Name PSR0 PSR1 PAR AAOR DCR DISR DIMR Description Peripheral Size Register 0 Peripheral Size Register 1 Peripheral Access Register Atomic Access Only Register DMA Control Register DMA Interrupt Status Register DMA Interrupt Mask Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-7 System Memory and Register Map Table 2-8. Register Map (continued) Module Name DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Address 0x1000_100C 0x1000_1010 0x1000_1014 0x1000_1018 0x1000_101C 0x1000_1040 0x1000_1044 0x1000_1048 0x1000_104C 0x1000_1050 0x1000_1054 0x1000_1080 0x1000_1084 0x1000_1088 0x1000_108C 0x1000_1090 0x1000_1094 0x1000_1098 0x1000_109C 0x1000_10C0 0x1000_10C4 0x1000_10C8 0x1000_10CC 0x1000_10D0 0x1000_10D4 0x1000_10D8 0x1000_10DC 0x1000_1100 0x1000_1104 0x1000_1108 0x1000_110C Register Name DBTOSR DRTOSR DSESR DBOSR DBTOCR WSRA XSRA YSRA WSRB XSRB YSRB SAR0 DAR0 CNTR0 CCR0 RSSR0 BLR0 RTOR0 BUCR0 CCNR0 SAR1 DAR1 CNTR1 CCR1 RSSR1 BLR1 RTOR1 BUCR1 CCNR1 SAR2 DAR2 CNTR2 CCR2 Description DMA Burst Time-Out Status Register DMA Request Time-Out Status Register DMA Transfer Error Status Register DMA Buffer Overflow Status Register DMA Burst Time-Out Control Register W-Size Register A X-Size Register A Y-Size Register A W-Size Register B X-Size Register B Y-Size Register B Channel 0 Source Address Register Channel 0 Destination Address Register Channel 0 Count Register Channel 0 Control Register Channel 0 Request Source Select Register Channel 0 Burst Length Register Channel 0 Request Time-Out Register Channel 0 Bus Utilization Control Register Channel 0 Channel Counter Register Channel 1 Source Address Register Channel 1 Destination Address Register Channel 1 Count Register Channel 1 Control Register Channel 1 Request Source Select Register Channel 1 Burst Length Register Channel 1 Request Time-Out Register Channel 1 Bus Utilization Control Register Channel 1 Channel Counter Register Channel 2 Source Address Register Channel 2 Destination Address Register Channel 2 Count Register Channel 2 Control Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-8 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Address 0x1000 1110 0x1000 1114 0x1000 1118 0x1000 111C 0x1000 1140 0x1000 1144 0x1000 1148 0x1000 114C 0x1000 1150 0x1000 1154 0x1000 1158 0x1000 115C 0x1000 1180 0x1000 1184 0x1000 1188 0x1000 118C 0x1000 1190 0x1000 1194 0x1000 1198 0x1000 119C 0x1000 11C0 0x1000 11C4 0x1000 11C8 0x1000 11CC 0x1000 11D0 0x1000 11D4 0x1000 11D8 0x1000 11DC 0x1000 1200 0x1000 1204 Register Name RSSR2 BLR2 RTOR2 BUCR2 CCNR2 SAR3 DAR3 CNTR3 CCR3 RSSR3 BLR3 RTOR3 BUCR3 CCNR3 SAR4 DAR4 CNTR4 CCR4 RSSR4 BLR4 RTOR4 BUCR4 CCNR 4 SAR5 DAR5 CNTR5 CCR5 RSSR5 BLR5 RTOR5 BUCR5 CCNR5 SAR6 DAR6 Description Channel 2 Request Source Select Register Channel 2 Burst Length Register Channel 2 Request Time-Out Register Channel 2 Bus Utilization Control Register Channel 2 Channel Counter Register Channel 3 Source Address Register Channel 3 Destination Address Register Channel 3 Count Register Channel 3 Control Register Channel 3 Request Source Select Register Channel 3 Burst Length Register Channel 3 Request Time-Out Register Channel 3 Bus Utilization Control Register Channel 3 Channel Counter Register Channel 4 Source Address Register Channel 4 Destination Address Register Channel 4 Count Register Channel 4 Control Register Channel 4 Request Source Select Register Channel 4 Burst Length Register Channel 4 Request Time-Out Register Channel 4 Bus Utilization Control Register Channel 4 Channel Counter Register Channel 5 Source Address Register Channel 5 Destination Address Register Channel 5 Count Register Channel 5 Control Register Channel 5 Request Source Select Register Channel 5 Burst Length Register Channel 5 Request Time-Out Register Channel 5 Bus Utilization Control Register Channel 5 Channel Counter Register Channel 6 Source Address Register Channel 6 Destination Address Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-9 System Memory and Register Map Table 2-8. Register Map (continued) Module Name DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Address 0x1000 1208 0x1000 120C 0x1000 1210 0x1000 1214 0x1000 1218 0x1000 121C 0x1000 1240 0x1000 1244 0x1000 1248 0x1000 124C 0x1000 1250 0x1000 1254 0x1000 1258 0x1000 125C 0x1000 1280 0x1000 1284 0x1000 1288 0x1000 128C 0x1000 1290 0x1000 1294 0x1000 1298 0x1000 129C 0x1000 12C0 0x1000 12C4 0x1000 12C8 0x1000 12CC 0x1000 12D0 0x1000 12D4 0x1000 12D8 0x1000 12DC Register Name CNTR6 CCR6 RSSR6 BLR6 RTOR6 BUCR6 CCNR6 SAR7 DAR7 CNTR7 CCR7 RSSR7 BLR7 RTOR7 BUCR7 CCNR7 SAR8 DAR8 CNTR8 CCR8 RSSR8 BLR8 RTOR8 BUCR8 CCNR8 SAR9 DAR9 CNTR9 CCR9 RSSR9 BLR9 RTOR9 BUCR9 CCNR9 Description Channel 6 Count Register Channel 6 Control Register Channel 6 Request Source Select Register Channel 6 Burst Length Register Channel 6 Request Time-Out Register Channel 6 Bus Utilization Control Register Channel 6 Channel Counter Register Channel 7 Source Address Register Channel 7 Destination Address Register Channel 7 Count Register Channel 7 Control Register Channel 7 Request Source Select Register Channel 7 Burst Length Register Channel 7 Request Time-Out Register Channel 7 Bus Utilization Control Register Channel 7 Channel Counter Register Channel 8 Source Address Register Channel 8 Destination Address Register Channel 8 Count Register Channel 8 Control Register Channel 8 Request Source Select Register Channel 8 Burst Length Register Channel 8 Request Time-Out Register Channel 8 Bus Utilization Control Register Channel 8 Channel Counter Register Channel 9 Source Address Register Channel 9 Destination Address Register Channel 9 Count Register Channel 9 Control Register Channel 9 Request Source Select Register Channel 9 Burst Length Register Channel 9 Request Time-Out Register Channel 9 Bus Utilization Control Register Channel 9 Channel Counter Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-10 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Address 0x1000 1300 0x1000 1304 0x1000 1308 0x1000 130C 0x1000 1310 0x1000 1314 0x1000 1318 0x1000 131C 0x1000 1340 0x1000 1344 0x1000 1348 0x1000 134C 0x1000 1350 0x1000 1354 0x1000 1358 0x1000 135C 0x1000 1380 0x1000 1384 0x1000 1388 0x1000 138C 0x1000 1390 0x1000 1394 0x1000 1398 0x1000 139C 0x1000 13C0 0x1000 13C4 0x1000 13C8 0x1000 13CC 0x1000 13D0 0x1000 13D4 Register Name SAR10 DAR10 CNTR10 CCR10 RSSR10 BLR10 RTOR10 BUCR10 CCNR10 SAR11 DAR11 CNTR11 CCR11 RSSR11 BLR11 RTOR11 BUCR11 CCNR11 SAR12 DAR12 CNTR12 CCR12 RSSR12 BLR12 RTOR12 BUCR12 CCNR12 SAR13 DAR13 CNTR13 CCR13 RSSR13 BLR13 Description Channel 10 Source Address Register Channel 10 Destination Address Register Channel 10 Count Register Channel 10 Control Register Channel 10 Request Source Select Register Channel 10 Burst Length Register Channel 10 Request Time-Out Register Channel 10 Bus Utilization Control Register Channel 10 Channel Counter Register Channel 11 Source Address Register Channel 11 Destination Address Register Channel 11 Count Register Channel 11 Control Register Channel 11 Request Source Select Register Channel 11 Burst Length Register Channel 11 Request Time-Out Register Channel 11 Bus Utilization Control Register Channel 11 Channel Counter Register Channel 12 Source Address Register Channel 12 Destination Address Register Channel 12 Count Register Channel 12 Control Register Channel 12 Request Source Select Register Channel 12 Burst Length Register Channel 12 Request Time-Out Register Channel 12 Bus Utilization Control Register Channel 14 Channel Counter Register Channel 13 Source Address Register Channel 13 Destination Address Register Channel 13 Count Register Channel 13 Control Register Channel 13 Request Source Select Register Channel 13 Burst Length Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-11 System Memory and Register Map Table 2-8. Register Map (continued) Module Name DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC WDOG WDOG WDOG GPT1 GPT1 GPT1 GPT1 Address 0x1000 13D8 0x1000 13DC 0x1000 1400 0x1000 1404 0x1000 1408 0x1000 140C 0x1000 1410 0x1000 1414 0x1000 1418 0x1000 141C 0x1000 1440 0x1000 1444 0x1000 1448 0x1000 144C 0x1000 1450 0x1000 1454 0x1000 1458 0x1000 145C 0x1000 1480 0x1000 1484 0x1000 148C 0x1000 1490 0x1000 1498 0x1000 149C 0x1000 2000 0x1000 2002 0x1000 2004 0x1000 3000 0x1000 3004 0x1000 3008 0x1000 300C Register Name RTOR13 BUCR13 CCNR13 SAR14 DAR14 CNTR14 CCR14 RSSR14 BLR14 RTOR14 BUCR14 CCNR14 SAR15 DAR15 CNTR15 CCR15 RSSR15 BLR15 RTOR15 BUCR15 CCNR15 TCR TFIFOAR TDIPR TFIFOBR TDRR_L TDRR_H WCR WSR WRSR TCTL1 TPRER1 TCMP1 TCR1 Description Channel 13 Request Time-Out Register Channel 13 Bus Utilization Control Register Channel 13 Channel Counter Register Channel 14 Source Address Register Channel 14 Destination Address Register Channel 14 Count Register Channel 14 Control Register Channel 14 Request Source Select Register Channel 14 Burst Length Register Channel 14 Request Time-Out Register Channel 14 Bus Utilization Control Register Channel 14 Channel Counter Register Channel 15 Source Address Register Channel 15 Destination Address Register Channel 15 Count Register Channel 15 Control Register Channel 15 Request Source Select Register Channel 15 Burst Length Register Channel 15 Request Time-Out Register Channel 15 Bus Utilization Control Register Channel 15 Channel Counter Register Test Control Register Test FIFO A Register Test DMA In Progress Register Test FIFO B Register Low 32 DMA Request Register High 32 DMA Request Register Watchdog Control Register Watchdog Service Register Watchdog Reset Status Register GPT Control Register 1 GPT Prescaler Register 1 GPT Compare Register 1 GPT Capture Register 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-12 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name GPT1 GPT1 GPT2 GPT2 GPT2 GPT2 GPT2 GPT2 GPT3 GPT3 GPT3 GPT3 GPT3 GPT3 PWM PWM PWM PWM PWM PWM RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC KPP KPP KPP Address 0x1000 3010 0x1000 3014 0x1000 4000 0x1000 4004 0x1000 4008 0x1000 400C 0x1000 4010 0x1000 4014 0x1000 5000 0x1000 5004 0x1000 5008 0x1000 500C 0x1000 5010 0x1000 5014 0x1000 6000 0x1000 6004 0x1000 6008 0x1000 600C 0x1000 6010 0x1000 6014 0x1000 7000 0x1000 7004 0x1000 7008 0x1000 700C 0x1000 7010 0x1000 7014 0x1000 7018 0x1000 701C 0x1000 7020 0x1000 7024 0x1000_8000 0x1000_8002 0x1000_8004 Register Name TCN1 TSTAT1 TCTL2 TPRER2 TCMP2 TCR2 TCN2 TSTAT2 TCTL3 TPRER3 TCMP3 TCR3 TCN3 TSTAT3 PWMCR PWMSR PWMIR PWMSAR PWMPR PWMCNR HOURMIN SECONDS ALRM_HM ALRM_SEC RCCTL RTCISR RTCIENR STPWCH DAYR DAYALARM KPCR KPSR KDDR Description GPT Counter Register 1 GPT Status Register 1 GPT Control Register 2 GPT Prescaler Register 2 GPT Compare Register 2 GPT Capture Register 2 GPT Counter Register 2 GPT Status Register 2 GPT Control Register 3 GPT Prescaler Register 3 GPT Compare Register 3 GPT Capture Register 3 GPT Counter Register 3 GPT Status Register 3 PWM Control Register PWM Status Register PWM Interrupt Register PWM Sample Register PWM Period Register PWM Counter Register RTC Hours and Minutes Counter Register RTC Seconds Counter Register RTC Hours and Minutes Alarm Register RTC Seconds Alarm Register RTC Control Register RTC Interrupt Status Register RTC Interrupt Enable Register Stopwatch Minutes Register RTC Days Counter Register RTC Day Alarm Register Keypad Control Register Keypad Status Register Keypad Data Direction Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-13 System Memory and Register Map Table 2-8. Register Map (continued) Module Name KPP O-Wire O-Wire O-Wire UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART1 UART2 UART2 UART2 UART2 UART2 UART2 UART2 UART2 UART2 UART2 UART2 UART2 UART2 Address 0x1000_8006 0x1000 9000 0x1000 9002 0x1000 9004 0x1000_A000 0x1000_A040 0x1000_A080 0x1000_A084 0x1000_A088 0x1000_A08C 0x1000_A090 0x1000_A094 0x1000_A098 0x1000_A09C 0x1000_A0A0 0x1000_A0A4 0x1000_A0A8 0x1000_A0AC 0x1000_A0B0 0x1000_A0B4 0x1000_B000 0x1000_B040 0x1000_B080 0x1000_B084 0x1000_B088 0x1000_B08C 0x1000_B090 0x1000_B094 0x1000_B098 0x1000_B09C 0x1000_B0A0 0x1000_B0A4 0x1000_B0A8 Register Name KPDR CONTROL TIME_DIVIDER RESET UXRD_1 UTXD_1 UCR1_1 UCR2_1 UCR3_1 UCR4_1 UFCR_1 USR1_1 USR2_1 UESC_1 UTIM_1 UBIR_1 UBMR_1 UBRC_1 ONEMS_1 UTS_1 UXRD_2 UTXD_2 UCR1_2 UCR2_2 UCR3_2 UCR4_2 UFCR_2 USR1_2 USR2_2 UESC_2 UTIM_2 UBIR_2 UBMR_2 Description Keypad Data Register 1-Wire Control Register 1-Wire Time Divider Register 1-Wire Reset Register UART1 Receiver Register UART1 Transmitter Register UART1 Control Register UART1 Control Register 2 UART1 Control Register 3 UART1 Control Register 4 UART1 FIFO Control Register UART1 Status Register 1 UART1 Status Register 2 UART1 Escape Character Register UART1 Escape Timer Register UART1 BRM Incremental Register UART1 BRM Modulator Register UART1 Baud Rate Count Register UART1 One Millisecond Register UART1 Test Register 1 UART2 Receiver Register UART2 Transmitter Register UART2 Control Register UART2 Control Register 2 UART2 Control Register 3 UART2 Control Register 4 UART2 FIFO Control Register UART2 Status Register 1 UART2 Status Register 2 UART2 Escape Character Register UART2 Escape Timer Register UART2 BRM Incremental Register UART2 BRM Modulator Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-14 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name UART2 UART2 UART2 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART3 UART4 UART4 UART4 UART4 UART4 UART4 UART4 UART4 UART4 UART4 UART4 UART4 UART4 UART4 Address 0x1000_B0AC 0x1000_B0B0 0x1000_B0B4 0x1000_C000 0x1000_C040 0x1000_C080 0x1000_C084 0x1000_C088 0x1000_C08C 0x1000_C090 0x1000_C094 0x1000_C098 0x1000_C09C 0x1000_C0A0 0x1000_C0A4 0x1000_C0A8 0x1000_C0AC 0x1000_C0B0 0x1000_C0B4 0x1000_D000 0x1000_D040 0x1000_D080 0x1000_D084 0x1000_D088 0x1000_D08C 0x1000_D090 0x1000_D094 0x1000_D098 0x1000_D09C 0x1000_D0A0 0x1000_D0A4 0x1000_D0A8 0x1000_D0AC Register Name UBRC_2 ONEMS_2 UTS_2 UXRD_3 UTXD_3 UCR1_3 UCR2_3 UCR3_3 UCR4_3 UFCR_3 USR1_3 USR2_3 UESC_3 UTIM_3 UBIR_3 UBMR_3 UBRC_3 ONEMS_3 UTS_3 UXRD_4 UTXD_4 UCR1_4 UCR2_4 UCR3_4 UCR4_4 UFCR_4 USR1_4 USR2_4 UESC_4 UTIM_4 UBIR_4 UBMR_4 UBRC_4 Description UART2 Baud Rate Count Register UART2 One Millisecond Register UART2 Test Register 1 UART3 Receiver Register UART3 Transmitter Register UART3 Control Register UART3 Control Register 2 UART3 Control Register 3 UART3 Control Register 4 UART3 FIFO Control Register UART3 Status Register 1 UART3 Status Register 2 UART3 Escape Character Register UART3 Escape Timer Register UART3 BRM Incremental Register UART3 BRM Modulator Register UART3 Baud Rate Count Register UART3 One Millisecond Register UART3 Test Register 1 UART4 Receiver Register UART4 Transmitter Register UART4 Control Register UART4 Control Register 2 UART4 Control Register 3 UART4 Control Register 4 UART4 FIFO Control Register UART4 Status Register 1 UART4 Status Register 2 UART4 Escape Character Register UART4 Escape Timer Register UART4 BRM Incremental Register UART4 BRM Modulator Register UART4 Baud Rate Count Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-15 System Memory and Register Map Table 2-8. Register Map (continued) Module Name UART4 UART4 CSPI1 CSPI1 CSPI1 CSPI1 CSPI1 CSPI1 CSPI1 CSPI1 CSPI2 CSPI2 CSPI2 CSPI2 CSPI2 CSPI2 CSPI2 CSPI2 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 Address 0x1000_D0B0 0x1000_D0B4 0x1000 E000 0x1000 E004 0x1000 E008 0x1000 E00C 0x1000 E010 0x1000 E014 0x1000 E018 0x1000 E01C 0x1000 F000 0x1000 F004 0x1000 F008 0x1000 F00C 0x1000 F010 0x1000 F014 0x1000 F018 0x1000 F01C 0x1001 0000 0x1001 0004 0x1001 0008 0x1001 000C 0x1001 0010 0x1001 0014 0x1001 0018 0x1001 001C 0x1001 0020 0x1001 0024 0x1001 0028 0x1001 002C 0x1001 0030 0x1001 0034 0x1001 0038 Register Name ONEMS_4 UTS_4 RXDATA1 TXDATA1 CONTROL_REG1 INT_REG1 TEST_REG PERIOD1 CSPI_DMA1 CSPI_RESET1 RXDATA2 TXDATA2 CONTROL_REG2 INT_REG2 TEST_REG 2 PERIOD2 CSPI_DMA2 CSPI_RESET2 STX0 STX1 SRX0 SRX1 SCR SISR SIER STCR SRCR STCCR SRCCR SFCSR STR SOR SACNT Description UART4 One Millisecond Register UART4 Test Register 1 Receive Data Register 1 Transmit Data Register 1 CSPI Control Register 1 Interrupt Control/Status Register 1 CSPI Test Register 1 CSPI Sample Period Control Register 1 CSPI DMA Register 1 CSPI 1 Soft Reset Register Receive Data Register 2 Transmit Data Register 2 CSPI Control Register 2 Interrupt Control/Status Register 2 CSPI Test Register 2 CSPI Sample Period Control Register 2 CSPI DMA Register 2 CSPI 2 Soft Reset Register SSI Transmit Data Register 0 SSI Transmit Data Register 1 SSI Receive Data Register 0 SSI Receive Data Register 1 SSI Control Register SSI Interrupt Status Register SSI Interrupt Enable Register SSI Transmit Configuration Register SSI Receive Configuration Register SSI Transmit Clock Control Register SSI Receive Clock Control Register SSI FIFO Control/Status Register SSI Test Register SSI Option Register SSI AC97 Control Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-16 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 1 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 SSI 2 I2C 1 I2C 1 Address 0x1001 003C 0x1001 0040 0x1001 0044 0x1001 0048 0x1001 004C 0x1001 0050 0x1001 0054 0x1001 0058 0x1001 1000 0x1001 1004 0x1001 1008 0x1001 100C 0x1001 1010 0x1001 1014 0x1001 1018 0x1001 101C 0x1001 1020 0x1001 1024 0x1001 1028 0x1001 102C 0x1001 1030 0x1001 1034 0x1001 1038 0x1001 103C 0x1001 1040 0x1001 1044 0x1001 1048 0x1001 104C 0x1001 1050 0x1001 1054 0x1001 1058 0x1001 2000 0x1001 2004 Register Name SACADD SACDAT SATAG STMSK SRMSK SACCST SACCEN SACCDIS STX0 STX1 SRX0 SRX1 SCR SISR SIER STCR SRCR STCCR SRCCR SFCSR STR SOR SACNT SACADD SACDAT SATAG STMSK SRMSK SACCST SACCEN SACCDIS IADR IFDR Description SSI AC97 Command Address Register SSI AC97 Command Data Register SSI AC97 Tag Register SSI Transmit Time Slot Mask Register SSI Receive Time Slot Mask Register SSI AC97 Channel Status Register SSI AC97 Channel Enable Register SSI AC97 Channel Disable Register SSI Transmit Data Register 0 SSI Transmit Data Register 1 SSI Receive Data Register 0 SSI Receive Data Register 1 SSI Control Register SSI Interrupt Status Register SSI Interrupt Enable Register SSI Transmit Configuration Register SSI Receive Configuration Register SSI Transmit Clock Control Register SSI Receive Clock Control Register SSI FIFO Control/Status Register SSI Test Register SSI Option Register SSI AC97 Control Register SSI AC97 Command Address Register SSI AC97 Command Data Register SSI AC97 Tag Register SSI Transmit Time Slot Mask Register SSI Receive Time Slot Mask Register SSI AC97 Channel Status Register SSI AC97 Channel Enable Register SSI AC97 Channel Disable Register I2C Address Register I2C Frequency Divider Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-17 System Memory and Register Map Table 2-8. Register Map (continued) Module Name I2C 1 I2C 1 I2C 1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC1 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 SDHC2 Address 0x1001 2008 0x1001 200C 0x1001 2010 0x1001 3000 0x1001 3004 0x1001 3008 0x1001 300C 0x1001 3010 0x1001 3014 0x1001 3018 0x1001 301C 0x1001 3020 0x1001 3024 0x1001 3028 0x1001 302C 0x1001 3030 0x1001 3034 0x1001 3038 0x1001 4000 0x1001 4004 0x1001 4008 0x1001 400C 0x1001 4010 0x1001 4014 0x1001 4018 0x1001 401C 0x1001 4020 0x1001 4024 0x1001 4028 0x1001 402C 0x1001 4030 0x1001 4034 0x1001 4038 Register Name I2CR I2SR I2DR STR_STP_CLK STATUS (Read Only) CLK_RATE CMD_DAT_CONT RESPONSE_TO READ_TO BLK_LEN NOB REV_NO INT_CNTL CMD ARGH ARGL RES_FIFO (Read Only) BUFFER_ACCESS STR_STP_CLK STATUS (Read Only) CLK_RATE CMD_DAT_CONT RESPONSE_TO READ_TO BLK_LEN NOB REV_NO INT_CNTL CMD ARGH ARGL RES_FIFO (Read Only) BUFFER_ACCESS Description I2C Control Register I2C Status Register I2C Data I/O Register MMC/SD1 Clock Control Register MMC/SD1 Status Register MMC/SD1 Clock Rate Register MMC/SD1 Command and Data Control Register MMC/SD1 Response Time Out Register MMC/SD1 Read Time Out Register MMC/SD1 Block Length Register MMC/SD1 Number of Block Register MMC/SD1 Revision Number Register MMC/SD1 Interrupt Control Register MMC/SD1 Command Number Register MMC/SD1 Higher Argument Register MMC/SD1 Lower Argument Register MMC/SD1 Response FIFO Register MMC/SD1 Buffer Access Register MMC/SD2 Clock Control Register MMC/SD2 Status Register MMC/SD2 Clock Rate Register MMC/SD2 Command and Data Control Register MMC/SD2 Response Time Out Register MMC/SD2 Read Time Out Register MMC/SD2 Block Length Register MMC/SD2 Number of Block Register MMC/SD2 Revision Number Register MMC/SD2 Interrupt Control Register MMC/SD2 Command Number Register MMC/SD2 Higher Argument Register MMC/SD2 Lower Argument Register MMC/SD2 Response FIFO Register MMC/SD2 Buffer Access Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-18 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Address 0x1001 5000 0x1001 5004 0x1001 5008 0x1001 500C 0x1001 5010 0x1001 5014 0x1001 5018 0x1001 501c 0x1001 5020 0x1001 5024 0x1001 5028 0x1001 502C 0x1001 5030 0x1001 5034 0x1001 5038 0x1001 503c 0x1001 5040 0x1001_5100 0x1001 5104 0x1001 5108 0x1001 510c 0x1001 5110 0x1001 5114 0x1001 5118 0x1001 511c 0x1001 5120 0x1001 5124 0x1001 5128 0x1001 512C 0x1001 5130 0x1001 5134 0x1001 5138 0x1001 513c Register Name PTA_DDIR PTA_OCR1 PTA_OCR2 PTA_ICONFA1 PTA_ICONFA2 PTA_ICONFB1 PTA_ICONFB2 PTA_DR PTA_GIUS PTA_SSR PTA_ICR1 PTA_ICR2 PTA_IMR PTA_ISR PTA_GPR PTA_SWR PTA_PUEN PTB_DDIR PTB_OCR1 PTB_OCR2 PTB_ICONFA1 PTB_ICONFA2 PTB_ICONFB1 PTB_ICONFB2 PTB_DR PTB_GIUS PTB_SSR PTB_ICR1 PTB_ICR2 PTB_IMR PTB_ISR PTB_GPR PTB_SWR Description Data Direction Register, Port A Output Configuration Register 1 (OCR1), Port A Output Configuration Register 2 (OCR2), Port A Input Configuration Register A1 (ICONFA1), Port A Input Configuration Register A1 (ICONFA2), Port A Input Configuration Register B1 (ICONFB1), Port A Input Configuration Register B2 (ICONFB2), Port A Data Register, Port A GPIO In Use Register, Port A Sample Status Register, Port A Interrupt Configuration Register 1, Port A Interrupt Configuration Register 2, Port A Interrupt Mask Register, Port A Interrupt Status Register, Port A General Purpose Register, Port A Software Reset Register, Port A Pull_up Enable Register, Port A Data Direction Register, Port B Output Configuration Register 1 (OCR1), Port B Output Configuration Register 2 (OCR2), Port B Input Configuration Register A1 (ICONFA1), Port B Input Configuration Register A1 (ICONFA2), Port B Input Configuration Register B1 (ICONFB1), Port B Input Configuration Register B2 (ICONFB2), Port B Data Register, Port B GPIO In Use Register, Port B Sample Status Register, Port B Interrupt Configuration Register 1, Port B Interrupt Configuration Register 2, Port B Interrupt Mask Register, Port B Interrupt Status Register, Port B General Purpose Register, Port B Software Reset Register, Port B MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-19 System Memory and Register Map Table 2-8. Register Map (continued) Module Name GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Address 0x1001 5140 0x1001_5200 0x1001 5204 0x1001 5208 0x1001 520c 0x1001 5210 0x1001 5214 0x1001 5218 0x1001 521C 0x1001 5220 0x1001 5224 0x1001 5228 0x1001 522C 0x1001 5230 0x1001 5234 0x1001 5238 0x1001 523c 0x1001 5240 0x1001 5300 0x1001 5304 0x1001 5308 0x1001 530c 0x1001 5310 0x1001 5314 0x1001 5318 0x1001 531c 0x1001 5320 0x1001 5324 0x1001 5328 0x1001 532C 0x1001 5330 0x1001 5334 0x1001 5338 Register Name PTB_PUEN PTC_DDIR PTC_OCR1 PTC_OCR2 PTC_ICONFA1 PTC_ICONFA2 PTC_ICONFB1 PTC_ICONFB2 PTC_DR PTC_GIUS PTC_SSR PTC_ICR1 PTC_ICR2 PTC_IMR PTC_ISR PTC_GPR PTC_SWR PTC_PUEN PTD_DDIR PTD_OCR1 PTD_OCR2 PTD_ICONFA1 PTD_ICONFA2 PTD_ICONFB1 PTD_ICONFB2 PTD_DR PTD_GIUS PTD_SSR PTD_ICR1 PTD_ICR2 PTD_IMR PTD_ISR PTD_GPR Description Pull_up Enable Register, Port B Data Direction Register, Port C Output Configuration Register 1 (OCR1), Port C Output Configuration Register 2 (OCR2), Port C Input Configuration Register A1 (ICONFA1), Port C Input Configuration Register A1 (ICONFA2), Port C Input Configuration Register B1 (ICONFB1), Port C Input Configuration Register B2 (ICONFB2), Port C Data Register, Port C GPIO In Use Register, Port C Sample Status Register, Port C Interrupt Configuration Register 1, Port C Interrupt Configuration Register 2, Port C Interrupt Mask Register, Port C Interrupt Status Register, Port C General Purpose Register, Port C Software Reset Register, Port C Pull_up Enable Register, Port C Data Direction Register, Port D Output Configuration Register 1 (OCR1), Port D Output Configuration Register 2 (OCR2), Port D Input Configuration Register A1 (ICONFA1), Port D Input Configuration Register A1 (ICONFA2), Port D Input Configuration Register B1 (ICONFB1), Port D Input Configuration Register B2 (ICONFB2), Port D Data Register, Port D GPIO In Use Register, Port D Sample Status Register, Port D Interrupt Configuration Register 1, Port D Interrupt Configuration Register 2, Port D Interrupt Mask Register, Port D Interrupt Status Register, Port D General Purpose Register, Port D MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-20 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Address 0x1001 533c 0x1001 5340 0x1001 5400 0x1001 5404 0x1001 5408 0x1001 540c 0x1001 5410 0x1001 5414 0x1001 5418 0x1001 541c 0x1001 5420 0x1001 5424 0x1001 5428 0x1001 542C 0x1001 5430 0x1001 5434 0x1001 5438 0x1001 543c 0x1001 5440 0x1001 5500 0x1001 5504 0x1001 5508 0x1001 550C 0x1001 5510 0x1001 5514 0x1001 5518 0x1001 551c 0x1001 5520 0x1001 5524 0x1001 5528 0x1001 552C 0x1001 5530 0x1001 5534 Register Name PTD_SWR PTD_PUEN PTE_DDIR PTE_OCR1 PTE_OCR2 PTE_ICONFA1 PTE_ICONFA2 PTE_ICONFB1 PTE_ICONFB2 PTE_DR PTE_GIUS PTE_SSR PTE_ICR1 PTE_ICR2 PTE_IMR PTE_ISR PTE_GPR PTE_SWR PTE_PUEN PTF_DDIR PTF_OCR1 PTF_OCR2 PTF_ICONFA1 PTF_ICONFA2 PTF_ICONFB1 PTF_ICONFB2 PTF_DR PTF_GIUS PTF_SSR PTF_ICR1 PTF_ICR2 PTF_IMR PTF_ISR Description Software Reset Register, Port D Pull_up Enable Register, Port D Data Direction Register, Port E Output Configuration Register 1 (OCR1), Port E Output Configuration Register 2 (OCR2), Port E Input Configuration Register A1 (ICONFA1), Port E Input Configuration Register A1 (ICONFA2), Port E Input Configuration Register B1 (ICONFB1), Port E Input Configuration Register B2 (ICONFB2), Port E Data Register, Port E GPIO In Use Register, Port E Sample Status Register, Port E Interrupt Configuration Register 1, Port E Interrupt Configuration Register 2, Port E Interrupt Mask Register, Port E Interrupt Status Register, Port E General Purpose Register, Port E Software Reset Register, Port E Pull_up Enable Register, Port E Data Direction Register, Port F Output Configuration Register 1 (OCR1), Port F Output Configuration Register 2 (OCR2), Port F Input Configuration Register A1 (ICONFA1), Port F Input Configuration Register A1 (ICONFA2), Port F Input Configuration Register B1 (ICONFB1), Port F Input Configuration Register B2 (ICONFB2), Port F Data Register, Port F GPIO In Use Register, Port F Sample Status Register, Port F Interrupt Configuration Register 1, Port F Interrupt Configuration Register 2, Port F Interrupt Mask Register, Port F Interrupt Status Register, Port F MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-21 System Memory and Register Map Table 2-8. Register Map (continued) Module Name GPIO GPIO GPIO GPIO AUDMUX AUDMUX AUDMUX AUDMUX AUDMUX AUDMUX CSPI3 CSPI3 CSPI3 CSPI3 CSPI3 CSPI3 CSPI3 CSPI3 MSHC MSHC MSHC MSHC GPT4 GPT4 GPT4 GPT4 GPT4 GPT4 GPT5 GPT5 GPT5 GPT5 GPT5 Address 0x1001 5538 0x1001 553c 0x1001 5540 0x1001 5600 0x1001 6000 0x1001 6004 0x1001 6008 0x1001 6010 0x1001 6014 0x1001 601C 0x1001 7000 0x1001 7004 0x1001 7008 0x1001 700C 0x1001 7010 0x1001 7014 0x1001 7018 0x1001 701C 0x1001 8000 0x1001 8008 0x1001 8010 0x1001 8018 0x1001 9000 0x1001 9004 0x1001 9008 0x1001 900C 0x1001 9010 0x1001 9014 0x1001 A000 0x1001 A004 0x1001 A008 0x1001 A00C 0x1001 A010 Register Name PTF_GPR PTF_SWR PTF_PUEN PMASK HPCR1 HPCR2 HPCR3 PPCR1 PPCR2 PPCR3 RXDATA3 TXDATA3 CONTROL_REG3 INT_REG3 TEST_REG3 PERIOD3 CSPI_DMA3 CSPI_RESET3 COMMAND_REG DATA_REG STATUS_REG SYSTEM_REG TCTL4 TPRER4 TCMP4 TCR4 TCN4 TSTAT4 TCTL5 TPRER5 TCMP5 TCR5 TCN5 Description General Purpose Register, Port F Software Reset Register, Port F Pull_up Enable Register, Port F GPIO Port Interrupt Mask Host Port Configuration Register 1 Host Port Configuration Register 2 Host Port Configuration Register 3 Peripheral Port Configuration Register 1 Peripheral Port Configuration Register 2 Peripheral Port Configuration Register 3 Receive Data Register 3 Transmit Data Register 3 CSPI Control Register 3 Interrupt Control/Status Register 3 CSPI Test Register 3 CSPI Sample Period Control Register 3 CSPI DMA Register 3 CSPI Soft Reset Register 3 MSHC Command Register MSHC Data Register MSHC Status Register MSHC System Register GPT Control Register 4 GPT Prescaler Register 4 GPT Compare Register 4 GPT Capture Register 4 GPT Counter Register 4 GPT Status Register 4 GPT Control Register 5 GPT Prescaler Register 5 GPT Compare Register 5 GPT Capture Register 5 GPT Counter Register 5 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-22 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name GPT5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART5 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 UART6 Address 0x1001 A014 0x1001_B000 0x1001_B040 0x1001_B080 0x1001_B084 0x1001_B088 0x1001_B08C 0x1001_B090 0x1001_B094 0x1001_B098 0x1001_B09C 0x1001_B0A0 0x1001_B0A4 0x1001_B0A8 0x1001_B0AC 0x1001_B0B0 0x1001_B0B4 0x1001_C000 0x1001_C040 0x1001_C080 0x1001_C084 0x1001_C088 0x1001_C08C 0x1001_C090 0x1001_C094 0x1001_C098 0x1001_C09C 0x1001_C0A0 0x1001_C0A4 0x1001_C0A8 0x1001_C0AC 0x1001_C0B0 0x1001_C0B4 Register Name TSTAT5 UXRD_5 UTXD_5 UCR1_5 UCR2_5 UCR3_5 UCR4_5 UFCR_5 USR1_5 USR2_5 UESC_5 UTIM_5 UBIR_5 UBMR_5 UBRC_5 ONEMS_5 UTS_5 UXRD_6 UTXD_6 UCR1_6 UCR2_6 UCR3_6 UCR4_6 UFCR_6 USR1_6 USR2_6 UESC_6 UTIM_6 UBIR_6 UBMR_6 UBRC_6 ONEMS_6 UTS_6 Description GPT Status Register 5 UART5 Receiver Register UART5 Transmitter Register UART5 Control Register UART5 Control Register 2 UART5 Control Register 3 UART5 Control Register 4 UART5 FIFO Control Register UART5 Status Register 1 UART5 Status Register 2 UART5 Escape Character Register UART5 Escape Timer Register UART5 BRM Incremental Register UART5 BRM Modulator Register UART5 Baud Rate Count Register UART5 One Millisecond Register UART5 Test Register 1 UART6 Receiver Register UART6 Transmitter Register UART6 Control Register UART6 Control Register 2 UART6 Control Register 3 UART6 Control Register 4 UART6 FIFO Control Register UART6 Status Register 1 UART6 Status Register 2 UART6 Escape Character Register UART6 Escape Timer Register UART6 BRM Incremental Register UART6 BRM Modulator Register UART6 Baud Rate Count Register UART6 One Millisecond Register UART6 Test Register 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-23 System Memory and Register Map Table 2-8. Register Map (continued) Module Name I2C 2 I2C 2 I2C 2 I2C 2 I2C 2 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 SDHC3 GPT6 GPT6 GPT6 GPT6 GPT6 GPT6 AIPI2 AIPI2 AIPI2 AIPI2 LCDC LCDC LCDC Address 0x1001 D000 0x1001 D004 0x1001 D008 0x1001 D00C 0x1001 D010 0x1001 E000 0x1001 E004 0x1001 E008 0x1001 E00C 0x1001 E010 0x1001 E014 0x1001 E018 0x1001 E01C 0x1001 E020 0x1001 E024 0x1001 E028 0x1001 E02C 0x1001 E030 0x1001 E034 0x1001 E038 0x1001 F000 0x1001 F004 0x1001 F008 0x1001 F00C 0x1001 F010 0x1001 F014 0x1002 0000 0x1002 0004 0x1002 0008 0x1002 000C 0x1002 1000 0x1002 1004 0x1002 1008 Register Name IADR IFDR I2CR I2SR I2DR STR_STP_CLK STATUS (Read Only) CLK_RATE CMD_DAT_CONT RESPONSE_TO READ_TO BLK_LEN NOB REV_NO INT_CNTL CMD ARGH ARGL RES_FIFO (Read Only) BUFFER_ACCESS TCTL6 TPRER6 TCMP6 TCR6 TCN6 TSTAT6 PSR0 PSR1 PAR AAOR LSSAR LSR LVPWR Description I2C Address Register I2C Frequency Divider Register I2C Control Register I2C Status Register I2C Data I/O Register MMC/SD2 Clock Control Register MMC/SD2 Status Register MMC/SD2 Clock Rate Register MMC/SD2 Command and Data Control Register MMC/SD2 Response Time Out Register MMC/SD2 Read Time Out Register MMC/SD2 Block Length Register MMC/SD2 Number of Block Register MMC/SD2 Revision Number Register MMC/SD2 Interrupt Control Register MMC/SD2 Command Number Register MMC/SD2 Higher Argument Register MMC/SD2 Lower Argument Register MMC/SD2 Response FIFO Register MMC/SD2 Buffer Access Register GPT Control Register 6 GPT Prescaler Register 6 GPT Compare Register 6 GPT Capture Register 6 GPT Counter Register 6 GPT Status Register 6 Peripheral Size Register0 Peripheral Size Register1 Peripheral Access Register Atomic Access Only Register LCDC Screen Start Address Register LCDC Size Register LCDC Virtual Page Width Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-24 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC SLCDC SLCDC SLCDC SLCDC SLCDC SLCDC SLCDC SLCDC SLCDC SLCDC Address 0x1002 100C 0x1002 1010 0x1002 1014 0x1002 1018 0x1002 101C 0x1002 1020 0x1002 1024 0x1002 1028 0x1002 102C 0x1002 1030 0x1002 1034 0x1002 1038 0x1002 103C 0x1002 1040 0x1002 1050 0x1002 1054 0x1002 1058 0x1002 105C 0x1002 1060 0x1002 1064 0x1002 1068 0x1002 1080 0x1002 1084 0x1002 2000 0x1002 2004 0x1002 2008 0x1002 200C 0x1002 2010 0x1002 2014 0x1002 2018 0x1002 201C 0x1002 2020 0x1002 2024 Register Name LCPR LCWHBR LCCMR LPCR LHCR LVCR LPOR LSCR LPCCR LDCR LRMCR LICR LIER LISR LGWSAR LGWSR LGWVPWR LGWPOR LGWPR LGWCR LGWDCR LAUSCR LAUSCCR DATA_BASE_ADDR DATA_BUFF_SIZE CMD_BASE_ADDR CMD_BUFF_SIZE CMD_STR_SIZE FIFO_CONFIG LCD_CONFIG LCD_XFER_CONFIG DMA_CTRL_STAT LCD_CLK_CONFIG Description LCDC Cursor Position Register LCDC Cursor Width Height and Blink Register LCDC Color Cursor Mapping Register LCDC Panel Configuration Register LCDC Horizontal Configuration Register LCDC Vertical Configuration Register LCDC Panning Offset Register LCDC Sharp Configuration Register LCDC PWM Contrast Control Register LCDC DMA Control Register LCDC Refresh Mode Control Register LCDC Interrupt Configuration Register LCDC Interrupt Enable Register LCDC Interrupt Status Register LCDC Graphic Window Start Address Register LCDC Graphic Window Size Register LCDC Graphic Window Virtual Page Width Register LCDC Graphic Window Panning Offset Register LCDC Graphic Window Position Register LCDC Graphic Window Control Register LCDC Graphic Window DMA Control Register LCDC Aus mode Control Register LCDC Aus mode Cursor Control Register SLCD Data Base Address Register SLCD Data Buffer Size Register SLCD Command Buffer Base Address Register SLCD Command Buffer Size Register SLCD Command String Size Register SLCD FIFO Configuration Register SLCD Configuration Register SLCD Transfer Configuration Register SLCD DMA Control/Status Register SLCD Clock Configuration Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-25 System Memory and Register Map Table 2-8. Register Map (continued) Module Name SLCDC Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Address 0x1002 2028 0x1002 3000 0x1002 3004 0x1002 3008 0x1002 300C 0x1002 3010 0x1002 3100 0x1002 3104 0x1002 3108 0x1002 310C 0x1002 3110 0x1002 3114 0x1002 3140 0x1002 3144 0x1002 3148 0x1002 3160 0x1002 3164 0x1002 3168 0x1002 316C 0x1002 3180 0x1002 3184 0x1002 3188 0x1002 318C 0x1002 3190 0x1002 3194 0x1002 3198 0x1002 319C Register Name LCD_WRITE_DATA CodeRun CodeDownLoad HostIntReq BitIntClear BitIntSts WorkBufAddr CodeBufAddr BitStreamCtrl FrameMemCtrl SramAddr SramSize BitStreamRdPtr BitStreamWrPtr FrameNum BusyFlag RunCommand RunIndex RunCodStd BitBufAddr BitBufSize FrameIntAddrY FrameIntAddrCb FrameIntAddrCr EncCodStd EncSrcFormat EncMp4Para Description SLCD Write Data Register BIT run start Code Download Data Register Host Interrupt Request to BI BIT Interrupt Clear BIT Interrupt Status Working Buffer Address in External Memory Code Table Size in External Memory Bit Stream Control Frame Memory Control Internal SRAM Base Address Internal SRAM Size Bit Stream Buffer Read Address Bit Stream Buffer Write Address Encoded/Decoded Frame Number Processing Busy Flag Start/Stop Codec Run Command Run Process Index Run Codec Standard Parameter Registers in sequence initialization. Bitstream Buffer Address Parameter Registers in sequence initialization. Bitstream Buffer Size Parameter Registers in sequence initialization. Temporal Frame Y Address Parameter Registers in sequence initialization. Temporal Frame Cb Address Parameter Registers in sequence initialization. Temporal Frame Cr Address Parameter Registers in sequence initialization. Encode Coding Standard Parameter Registers in sequence initialization. Encode Source Frame Format Parameter Registers in sequence initialization. Encode MPEG4 Parameter MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-26 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec Video Codec USBOTG USBOTG USBOTG USBOTG USBOTG Address 0x1002 31A0 0x1002 31A4 0x1002 31A8 0x1002 31AC 0x1002 31B0 0x1002 31C0 0x1002 31C4 0x1002 31C8 0x1002 31CC 0x1002 31D0 0x1002 3180 0x1002 3184 0x1002 3188 0x1002 318C 0x1002 3190 0x1002 3194 0x1002 31C0 0x1002 4000 0x1002 4004 0x1002 4008 0x1002 400C 0x1002 4010 Register Name Enc263Para Enc264Para EncSliceMode EncGopNum EncPictureQs RetStatus RetSrcFormat RetMp4Info Ret263Info Ret264Info FrameSrcAddrY FrameSrcAddrCb FrameSrcAddrCr FrameDecAddrY FrameDecAddrCb FrameDecAddrCr RetStatus UOG_ID UOG_HWGENERAL UOG_HWHOST UOG_HWDEVICE UOG_HWTXBUF Description Parameter Registers in sequence initialization. Encode H.263 Parameter Parameter Registers in sequence initialization. Encode H.264 Parameter Parameter Registers in sequence initialization. Encode Slice Mode Parameter Registers in sequence initialization. Encode GOP Number Parameter Registers in sequence initialization. Encode Picture Quantize Step Parameter Registers in sequence initialization. Command Executing Result Status Parameter Registers in sequence initialization. Decoded Source Format Parameter Registers in sequence initialization. Decoded MPEG4 Sequence Information Parameter Registers in sequence initialization. Decoded H.263 Sequence Information Parameter Registers in sequence initialization. Decoded H.264 Sequence Information Parameter Register in Processing Running. Source Frame Y Address Parameter Register in Processing Running. Source Frame Cb Address Parameter Register in Processing Running. Source Frame Cr Address Parameter Register in Processing Running. Decode Frame Y Address Parameter Register in Processing Running. Decode Frame Cb Address Parameter Register in Processing Running. Decode Frame Cr Address Parameter Register in Processing Running. Command Executing Result Status ID (UOG_ID) Hardware General (UOG_HWGENERAL) Host Hardware Parameters (UOG_HWHOST) Device Hardware Parameters (UOG_HWDEVICE) TX Buffer Hardware Parameters (UOG_HWTXBUF) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-27 System Memory and Register Map Table 2-8. Register Map (continued) Module Name USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG Address 0x1002 4014 0x1002 4080 0x1002 4084 0x1002 4088 0x1002 408C 0x1002 4100 0x1002 4102 0x1002 4104 0x1002 4108 0x1002 4120 0x1002 4124 0x1002 4140 0x1002 4144 0x1002 4148 0x1002 414C 0x1002 4154 0x1002 4158 0x1002 4160 0x1002 4164 0x1002 4170 0x1002 4180 0x1002 4184 0x1002 41A4 0x1002 41A8 0x1002 41AC 0x1002 41B0 0x1002 41B4 0x1002 41B8 Register Name UOG_HWRXBUF GPTIMER0LD GPTIMER0CTRL GPTIMER0LD GPTIMER0CTRL UOG_CAPLENGTH UOG_HCIVERSION UOG_HCSPARAMS UOG_HCCPARAMS UOG_DCIVERSION UOG_DCCPARAMS UOG_USBCMD UOG_USBSTS UOG_USBINTR UOG_FRINDEX UOG_PERIODICLISTBASE UOG_ASYNCLISTADDR UOG_BURSTSIZE UOG_TXFILLTUNING ULPIVIEW UOG_CFGFLAG UOG_PORTSC1 UOG_OTGSC UOG_USBMODE UOG_ENDPTSETUPSTAT UOG_ENDPTPRIME UOG_ENDPTFLUSH UOG_ENDPTSTAT Description RX Buffer Hardware Parameters (UOG_HWRXBUF) General Purpose Timer #0 Load (GPTIMER0LD) General Purpose Timer #0 Controller (GPTIMER0CTRL) General Purpose Timer #1 Load (GPTIMER0LD) General Purpose Timer #1 Controller (GPTIMER0CTRL) Capability Register Length (UOG_CAPLENGTH) Host Interface Version (UOG_HCIVERSION) Host Control Structural Parameters (UOG_HCSPARAMS) Control Capability Parameters (UOG_HCCPARAMS) Device Interface Version (UOG_DCIVERSION) Device Controller Capability Parameters (UOG_DCCPARAMS) USB Command Register (UOG_USBCMD) USB Status Register (UOG_USBSTS) Interrupt Enable Register (UOG_USBINTR) USB Frame Index (UOG_FRINDEX) Host Controller Frame List Base Address (UOG_PERIODICLISTBASE) Host Controller Next Asynch. Address (UOG_ASYNCLISTADDR) Host Controller Embedded TT Asynch. Buffer Status (UOG_BURSTSIZE) TX FIFO Fill Tuning (UOG_TXFILLTUNING) ULPI Viewport (ULPIVIEW) Config Flag (UOG_CFGFLAG) Port Status and Control (UOG_PORTSC1) On-The-Go Status and control (UOG_OTGSC) USB Device Mode (UOG_USBMODE) Endpoint Setup Status (UOG_ENDPTSETUPSTAT) Endpoint Initialization (UOG_ENDPTPRIME) Endpoint De-Initialize (UOG_ENDPTFLUSH) Endpoint Status (UOG_ENDPTSTAT) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-28 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USB OTG USB OTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG Address 0x1002 41BC 0x1002 41C0 0x1002 41C4 0x1002 41C8 0x1002 41CC 0x1002 41D0 0x1002 41D4 0x1002 41D8 0x1002 41DC 0x1002 4200 0x1002 4204 0x1002 4208 0x1002 4210 0x1002 4214 0x1002 4280 0x1002 4284 0x1002 4288 0x1002 428C 0x1002 4300 0x1002 4302 0x1002 4304 0x1002 4308 0x1002 4340 0x1002 4344 0x1002 4348 0x1002 434C 0x1002 4354 0x1002 4358 0x1002 4360 Register Name UOG_ENDPTCOMPLETE ENDPTCTRL0 ENDPTCTRL1 ENDPTCTRL2 ENDPTCTRL3 ENDPTCTRL4 ENDPTCTRL5 ENDPTCTRL6 ENDPTCTRL7 UH1_ID UH1_HWGENERAL UH1_HWHOST UH1_HWTXBUF UH1_HWRXBUF GPTIMER0LD GPTIMER0CTRL GPTIMER0LD GPTIMER0CTRL UH1_CAPLENGTH UH1_HCIVERSION UH1_HCSPARAMS UH1_HCCPARAMS UH1_USBCMD UH1_USBSTS UH1_USBINTR UH1_FRINDEX UH1_PERIODICLISTBASE UH1_ASYNCLISTADDR UH1_BURSTSIZE Description Endpoint Complete (UOG_ENDPTCOMPLETE) Endpoint Control 0 (ENDPTCTRL0) Endpoint Control 1 (ENDPTCTRL1) Endpoint Control 2 (ENDPTCTRL2) Endpoint Control 3 (ENDPTCTRL3) Endpoint Control 4 (ENDPTCTRL4) Endpoint Control 5 (ENDPTCTRL5) Endpoint Control 6 (ENDPTCTRL6) Endpoint Control 7 (ENDPTCTRL7) Host 1 ID (UH1_ID) Hardware General (UH1_HWGENERAL) Host Hardware Parameters (UH1_HWHOST) TX Buffer Hardware Parameters (UH1_HWTXBUF) RX Buffer Hardware Parameters (UH1_HWRXBUF) General Purpose Timer #0 Load (GPTIMER0LD) General Purpose Timer #0 Controller (GPTIMER0CTRL) General Purpose Timer #1 Load (GPTIMER0LD) General Purpose Timer #1 Controller (GPTIMER0CTRL) Capability Register Length (UH1_CAPLENGTH) Host Interface Version (UH1_HCIVERSION) Host Control Structural Parameters (UH1_HCSPARAMS) Control Capability Parameters (UH1_HCCPARAMS) USB Command Register (UH1_USBCMD) USB Status Register (UH1_USBSTS) Interrupt Enable Register (UH1_USBINTR) USB Frame Index (UH1_FRINDEX) Host Controller Frame List Base Address (UH1_PERIODICLISTBASE) Host Controller Next Asynch. Address (UH1_ASYNCLISTADDR) Host Controller Embedded TT Asynch. Buffer Status (UH1_BURSTSIZE) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-29 System Memory and Register Map Table 2-8. Register Map (continued) Module Name USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG USBOTG Address 0x1002 4364 0x1002 4380 0x1002 4838 0x1002 4384 0x1002 483C 0x1002 43A8 0x1002 4400 0x1002 4404 0x1002 4408 0x1002 4410 0x1002 4414 0x1002 4480 0x1002 4484 0x1002 4488 0x1002 448C 0x1002 4500 0x1002 4502 0x1002 4504 0x1002 4508 0x1002 4540 0x1002 4544 0x1002 4548 0x1002 454C 0x1002 4554 0x1002 4558 0x1002 4560 0x1002 4564 0x1002 4570 0x1002 4580 Reserved UH1_PORTSC1 Reserved UH1_USBMODE UH2_ID UH2_HWGENERAL UH2_HWHOST UH2_HWTXBUF UH2_HWRXBUF GPTIMER0LD GPTIMER0CTRL GPTIMER0LD GPTIMER0CTRL UH2_CAPLENGTH UH2_HCIVERSION UH2_HCSPARAMS UH2_HCCPARAMS UH2_USBCMD UH2_USBSTS UH2_USBINTR UH2_FRINDEX UH2_PERIODICLISTBASE UH2_ASYNCLISTADDR UH2_BURSTSIZE UH2_TXFILLTUNING ULPIVIEW Register Name UH1_TXFILLTUNING Description TX FIFO Fill Tuning (UH1_TXFILLTUNING) Reserved Port Status and Control (UH1_PORTSC1) Port Status and Control (UH1_PORTSC1) Reserved USB Device Mode (UH1_USBMODE) ID (UH2_ID) Hardware General (UH2_HWGENERAL) Host Hardware Parameters (UH2_HWHOST) TX Buffer Hardware Parameters (UH2_HWTXBUF) RX Buffer Hardware Parameters (UH2_HWRXBUF) General Purpose Timer #0 Load (GPTIMER0LD) General Purpose Timer #0 Controller (GPTIMER0CTRL) General Purpose Timer #1 Load (GPTIMER0LD) General Purpose Timer #1 Controller (GPTIMER0CTRL) Capability Register Length (UH2_CAPLENGTH) Host Interface Version (UH2_HCIVERSION) Host Control Structural Parameters (UH2_HCSPARAMS) Control Capability Parameters (UH2_HCCPARAMS) USB Command Register (UH2_USBCMD) USB Status Register (UH2_USBSTS) Interrupt Enable Register (UH2_USBINTR) USB Frame Index (UH2_FRINDEX) Host Controller Frame List Base Address (UH2_PERIODICLISTBASE) Host Controller Next Asynch. Address (UH2_ASYNCLISTADDR) Host Controller Embedded TT Asynch. Buffer Status (UH2_BURSTSIZE) TX FIFO Fill Tuning (UH2_TXFILLTUNING) ULPI Viewport (ULPIVIEW) Reserved MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-30 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name USBOTG USBOTG USBOTG USBOTG SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 Address 0x1002 4584 0x1002 45A8 0x1002 4600 0x1002 4604 0x1002 5000 0x1002 5004 0x1002 5008 0x1002 500C 0x1002 5010 0x1002 5014 0x1002 5018 0x1002 501C 0x1002 5020 0x1002 5024 0x1002 5080 0x1002 5084 0x1002 5088 0x1002 508C 0x1002 5090 0x1002 5094 0x1002 50A0 0x1002 50A4 0x1002 50A8 0x1002 50B0 0x1002 50B4 0x1002 50B8 0x1002 50C0 0x1002 5100 0x1002 5104 0x1002 5108 0x1002 510C 0x1002 5110 Register Name UH2_PORTSC1 UH2_USBMODE USB_CTRL USB_OTG_MIRROR VER_ID DSC_ADR CONTROL COMMAND STAT ERR_STAT FAULT_ADR C_DSC_ADR I_DSC_ADR BUFF_LVL DSC_A DSC_B DSC_C DSC_D DSC_E DSC_F LNK_1_A LNK_1_B LNK_1_C LNK_2_A LNK_2_B LNK_2_C FLOW_CTRL SKHA_MODE SKHA_KEY_SIZE SKHA_DATA_SIZE SKHA_STAT SKHA_ERR_STAT Description Port Status and Control (UH2_PORTSC1) USB Device Mode (UH2_USBMODE) USB Control Register (USB_CTRL) USB OTG Mirror Register (USB_OTG_MIRROR) SAHARA2 Version ID Register SAHARA2 Descriptor Address Register SAHARA2 Control Register SAHARA2 Command Register SAHARA2 Status Register SAHARA2 Error Status Register SAHARA2 Fault Address Register SAHARA2 Current Descriptor Address Register SAHARA2 Initial Descriptor Address Register SAHARA2 Buffer Level Register Location to Store Descriptor Location to Store Descriptor Location to Store Descriptor Location to Store Descriptor Location to Store Descriptor Location to Store Descriptor Location to Store Link Data Location to Store Link Data Location to Store Link Data Location to Store Link Data Location to Store Link Data Location to Store Link Data SAHARA2 Internal Buffer and Data-Paths Control Register SKHA Mode Register SKHA Key Size Register SKHA Data Size Register SKHA Status Register SKHA Error Status Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-31 System Memory and Register Map Table 2-8. Register Map (continued) Module Name SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 SAHARA2 eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt Address 0x1002 5114 0x1002 5140– 0x1002 517F 0x1002 5180– 0x1002 51FF 0x1002 5200 0x1002 5204 0x1002 5208 0x1002 520C 0x1002 5210 0x1002 5214 0x1002 5240– 0x1002 5254 0x1002 5280– 0x1002 52FF 0x1002 5300 0x1002 5308 0x1002 530C 0x1002 5310 0x1002 5314 0x1002 5340– 0x1002 537F 0x1002 5380 0x1002 5400– 0x1002 54FF 0x1002 5500– 0x1002 55FF 0x1002 5600– 0x1002 57FF 0x1002 6000 0x1002 6004 0x1002 6008 0x1002 600C 0x1002 6010 0x1002 6014 0x1002 6018 Register Name SKHA_End-of-Message SKHA_CXT SKHA Key MDHA_MODE MDHA_KEY_SIZE MDHA_DATA_SIZE MDHA_STAT MDHA_ERR_STAT MDHA_End-of-Message MDHA_Digest and Length MDHA_Key RNG_Mode RNG_Data_SIZE RNG_STAT RNG_ERROR_STAT RNG_End-of-Message RNG_VERIFICATION RNG_ENTROPY Data Input Buffer Data Output Buffer SBOX CONTEXT PP_CNTL PP_INTRCNTL PP_INTRSTATUS PP_SOURCE_Y_PTR PP_SOURCE_CB_PTR PP_SOURCE_CR_PTR PP_DEST_RGB_PTR Description SKHA End-of-Message Register SKHA Context Register SKHA Key Register MDHA Mode Register MDHA Key Size Register MDHA Data Size Register MDHA Status Register MDHA Error Status Register MDHA End-of-Message Register MDHA Message Digest and Length Register MDHA Keys RNG Mode Register RNG Data Size Register RNG Status Register RNG Error Status Register RNG End-of-Message Register RNG Verification Register RNG Entropy Register Data Input Buffers Data Output Buffers SBOX Context PP Control Register PP Interrupt Control Register PP interrupt Status Register PP Source “Y” FramE Data Pointer Register PP Source “CB” Frame Data Pointer Register PP Source “CR” Frame Data Pointer Register PP Destination “RGB” Frame Start Address Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-32 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt Address 0x1002 601C 0x1002 6020 0x1002 6024 0x1002 6028 0x1002 602C 0x1002 6030 0x1002 6034 0x1002 6038 0x1002 603C 0x1002 6100– 0x1002 617C 0x1002 6400 0x1002 6404 0x1002 6408 0x1002 640C 0x1002 6410 0x1002 6414 0x1002 6418 0x1002 641C 0x1002 6420 0x1002 6424 0x1002 6428 0x1002 642C 0x1002 6430 0x1002 6434 0x1002 6438 0x1002 643C 0x1002 6440 0x1002 6444 0x1002 6448 0x1002 644C Register Name PP_QUANTIZER_PTR PP_PROCESS_FRAME_PARA PP_SOURCE_FRAME_WIDTH PP_DEST_DISPLAY_WIDTH PP_DEST_IMAGE_SIZE PP_DEST_FRAME_FMT_CNTL PP Resize Table index Reg PP_CSC_COEFF_012 PP_CSC_COEFF_34 PP_RESIZE_COEF_TBL PrP_CNTL PrP_INTRCNTL PrP_INTRSTATUS PrP_SOURCE_Y_PTR PrP_SOURCE_CB_PTR PrP_SOURCE_CR_PTR PrP_DEST_RGB1_PTR PrP_DEST_RGB2_PTR PrP_DEST_Y_PTR PrP_DEST_CB_PTR PrP_DEST_CR_PTR PrP_SOURCE_FRAME_SIZE PrP_CH1_LINE_STRIDE Description PP Quantizer Start Address Register PP Process Frame Parameter, Width And Height Register PP Source Frame Width Register PP Destination Display Width Register PP Destination Image Size Register PP Destination Frame Format Control Register PP Resize Table Index Register PP CSC Coefficient 0, 1, and 2 Register PP CSC Coefficient 3 and 4 Register PP Resize Coefficient Table Register PrP Control Register PrP Interrupt Control Register PrP interrupt Status Register PrP Source “Y” Frame Start Address Register PrP Source “CB” Frame Start Address Register PrP Source “CR” Frame Start Address Register PrP Destination “RGB” Frame-1 Start Address Register PrP Destination “RGB” Frame-2 Start Address Register PrP Destination “Y” Frame Start Address Register PrP Destination “CB” Frame Start Address Register PrP Destination “CR” Frame Start Address Register PrP Source Frame Size Register PrP Channel-1 Line stride Register PrP_SRC_PIXEL_FORMAT_CNTL PrP Source Pixel Format Control Register PrP_CH1_PIXEL_FORMAT_CNTL PrP CH1 Pixel Format Control Register PrP_CH1_OUT_IMAGE_SIZE PrP_CH2_OUT_IMAGE_SIZE PrP_SOURCE_LINE_STRIDE PrP_CSC_COEFF_012 PrP_CSC_COEFF_345 PrP CH1 Output Image Size Register PrP CH2 Output Image Size Register PrP Source Line Stride Register PrP CSC Coefficients 0, 1, and 2 Register PrP CSC Coefficients 3, 4, and 5 Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-33 System Memory and Register Map Table 2-8. Register Map (continued) Module Name eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt eMMA_lt PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL Address 0x1002 6450 0x1002 6454 0x1002 6458 0x1002 645C 0x1002 6460 0x1002 6464 0x1002 6468 0x1002 646C 0x1002 6470 0x1002 6474 0x1002 6478 0x1002 647C 0x1002 6480 0x1002 7000 0x1002 7004 0x10027008 0x1002700C 0x10027010 0x10027014 0x10027018 0x1002701C 0x10027020 0x10027024 0x10027028 0x1002702C 0x10027030 0x10027034 0x10027800 0x10027814 0x10027818 0x1002781C 0x10027820 0x10027824 Register Name PrP_CSC_COEFF_678 PrP_CH1_HRESIZE_COEFF1 PrP_CH1_HRESIZE_COEFF2 PrP_CH1_HRESIZE_VALID PrP_CH1_VRESIZE_COEFF1 PrP_CH1_VRESIZE_COEFF2 PrP_CH1_VRESIZE_VALID PrP_CH2_HRESIZE_COEFF1 PrP_CH2_HRESIZE_COEFF2 PrP_CH2_HRESIZE_VALID PrP_CH2_VRESIZE_COEFF1 PrP_CH2_VRESIZE_COEFF2 PrP_CH2_VRESIZE_VALID CSCR MPCTL0 MPCTL1 SPCTL0 SPCTL1 OSC26MCTL PCDR0 PCDR1 PCCR0 PCCR1 CCSR PMCTL PMCOUNT WKGDCTL CID FMCR GPCR WBCR DSCR1 DSCR2 Description PrP CSC Coefficients 6, 7, and 8 Register PrP CH1 Horizontal Resize Coefficients Register PrP CH1 Horizontal Resize Coefficients Register PrP CH1 Horizontal Resize Valid Register PrP CH1 Vertical Resize Coefficients Register PrP CH1 Vertical Resize Coefficients Register PrP CH1 Vertical Resize Valid Register PrP CH2 Horizontal Resize Coefficients Register PrP CH2 Horizontal Resize Coefficients Register PrP CH2 Horizontal Resize Valid Register PrP CH2 Vertical Resize Coefficients Register PrP CH2 Vertical Resize Coefficients Register PrP CH2 Vertical Resize Valid Register Clock Source Control Register MPLL Control Register 0 MPLL Control Register 1 SPLL Control Register 0 SPLL Control Register 1 Oscillator 26M Register Peripheral Clock Divider Register 0 Peripheral Clock Divider Register 1 Peripheral Clock Control Register 0 Peripheral Clock Control Register 1 Clock Control Status Register PMOS Switch Control Register PMOS Switch Counter Register Wakeup Guard Mode Control Register Chip ID Register Function Multiplexing Control Register Global Peripheral Control Register Well Bias Control Register Driving Strength Control Register 1 Driving Strength Control Register 2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-34 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL SYSCTRL IIM IIM IIM IIM IIM IIM IIM IIM IIM IIM IIM IIM IIM IIM IIM Address 0x10027828 0x1002782C 0x10027830 0x10027834 0x10027838 0x1002783C 0x10027840 0x1002 7844 0x1002 7848 0x1002 784C 0x1002 7850 0x1002 7854 0x1002 7858 0x1002 7860 0x1002 7864 0x1002 7868 0x1002 786C 0x1002 7870 0x1002_8000 0x1002_8004 0x1002_8008 0x1002_800C 0x1002_8010 0x1002_8014 0x1002_8018 0x1002_801C 0x1002_8020 0x1002_8024 0x1002_8028 0x1002_802C 0x1002_8030 0x1002_8034 0x1002_8038 Register Name DSCR3 DSCR4 DSCR5 DSCR6 DSCR7 DSCR8 DSCR9 DSCR10 DSCR11 DSCR12 DSCR13 PSCR PCSR PMCR DCVR0 DCVR‘ DCVR2 DCVR3 STAT STATM ERR EMASK FCTL UA LA SDAT PREV SREV PROG_P SCS0 SCS1 SCS2 SCS3 Description Driving Strength Control Register 3 Driving Strength Control Register 4 Driving Strength Control Register 5 Driving Strength Control Register 6 Driving Strength Control Register 7 Driving Strength Control Register 8 Driving Strength Control Register 9 Driving Strength Control Register 10 Driving Strength Control Register 11 Driving Strength Control Register 12 Driving Strength Control Register 13 Pull Strength Control Register Priority Control and Select Register Power Management Control Register DPTC Comparator Value Register 0 DPTC Comparator Value Register 1 DPTC Comparator Value Register 2 DPTC Comparator Value Register 3 Status Register Status IRQ Mask Register Module Errors Register Error IRQ Mask Register Fuse Control Register Upper Address Register Lower Address Register Explicit Sense Data Register Product Revision Register Silicon Revision Register Program Protection Register Software_Controllable Signals Register 0 Software_Controllable Volatile Hardware—Visible Signals Register (1–3) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-35 System Memory and Register Map Table 2-8. Register Map (continued) Module Name IIM IIM IIM IIM IIM IIM IIM IIM IIM IIM RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC Address 0x1002_803C 0x1002_8804 0x1002_8808 0x1002_880C 0x1002_8810 0x1002_8814– 0x1002_8828 0x1002_882C– 0x1002_887C 0x1002_8C00 0x1002_8C04– 0x1002_8C18 0x1002_8C1C– 0x1002_8C7C 0x1002 A000 0x1002 A004 0x1002 A008 0x1002 A00C 0x1002 A010 0x1002 A014 0x1002 A0018 0x1002 A01C 0x1002 A030 0x1002 A034 0x1002 A038 0x1002 A003C 0x1002 A050 0x1002 A054 0x1002 A058 0x1002 A05C 0x1002 A070 0x1002 A074 0x1002 A078 0x1002 A07C Register Name FBAC0 WORD1_BANK0 WORD2_BANK0 WORD3_BANK0 WORD4_BANK0 SUID SCC_KEY FBAC1 MAC_ADDR RESERVED RTICSR RTICCMDR RTICCNTLR RTICTR RTICAMSAR1 RTICAMLR1 RTICAMSAR2 RTICAMLR2 RTICBMSAR1 RTICBMLR1 RTICBMSAR2 RTICBMLR2 RTICCMSAR1 RTICCMLR1 RTICCMSAR2 RTICCMLR2 RTICDMSAR1 RTICDMLR1 RTICDMSAR2 RTICDMLR2 Description Fuse Bank 0 Access Protection Register Word 1 of Fusebank 0 Word 2 of Fusebank 0 Word 3 of Fusebank 0 Word 4 of Fusebank 0 Silicon_Unique_ID[47:0] SCC_KEY[167:0] Fuse Bank 0 Access Protection register MAC Address of Ethernet Reserved for future use RTIC Status Register RTIC Command Register RTIC Control Register RTIC Throttle Register RTIC Memory A Start Address Register 1 RTIC Memory A Len Register 1 RTIC Memory A Start Address Register 2 RTIC Memory A Len Register 2 RTIC Memory B Start Address Register 1 RTIC Memory B Len Register 1 RTIC Memory B Start Address Register 2 RTIC Memory B Len Register 2 RTIC Memory C Start Address Register 1 RTIC Memory C Len Register 1 RTIC Memory C Start Address Register 2 RTIC Memory C Len Register 2 RTIC Memory D Start Address Register 1 RTIC Memory D Len Register 1 RTIC Memory D Start Address Register 2 RTIC Memory D Len Register 2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-36 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC RTIC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC Address 0x1002 A090 0x1002 A094 0x1002 A0A0 0x1002 A0A4 0x1002 A0A8 0x1002 A0AC 0x1002 A0B0 0x1002 A0C0 0x1002 A0C4 0x1002 A0C8 0x1002 A0CC 0x1002 A0D0 0x1002 A0E0 0x1002 A0E4 0x1002 A0E8 0x1002 A0EC 0x1002 A0F0 0x1002 A100 0x1002 A104 0x1002 A108 0x1002 A10C 0x1002 A110 0x1002_B004 0x1002_B008 0x1002_B010 0x1002_B014 0x1002_B024 0x1002_B040 0x1002_B044 0x1002_B064 0x1002_B084 0x1002_B0C4 0x1002_B0E4 Register Name RTICFAR RTICWR RTICAMHR1 RTICAMHR2 RTICAMHR3 RTICAMHR4 RTICAMHR5 RTICBMHR1 RTICBMHR2 RTICBMHR3 RTICBMHR4 RTICBMHR5 RTICCMHR1 RTICCMHR2 RTICCMHR3 RTICCMHR4 RTICCMHR5 RTICDMHR1 RTICDMHR2 RTICDMHR3 RTICDMHR4 RTICDMHR5 EIR EIMR RDAR TDAR ECR MMFR MSCR MIBC RCR TCR PALR Description RTIC Fault Address Register RTIC Watchdog Register RTIC Memory A Hash Result [159:128] RTIC Memory A Hash Result [127:96] RTIC Memory A Hash Result [95:64] RTIC Memory A Hash Result [63:32] RTIC Memory A Hash Result [31:0] RTIC Memory B Hash Result [159:128] RTIC Memory B Hash Result [127:96] RTIC Memory B Hash Result [95:64] RTIC Memory B Hash Result [63:32 RTIC Memory B Hash Result [31:0] RTIC Memory C Hash Result [159:128] RTIC Memory C Hash Result [127:96] RTIC Memory C Hash Result [95:64] RTIC Memory C Hash Result [63:32] RTIC Memory C Hash Result [31:0] RTIC Memory D Hash Result [159:128] RTIC Memory D Hash Result [127:96] RTIC Memory D Hash Result [95:64] RTIC Memory D Hash Result [63:32] RTIC Memory D Hash Result [31:0] Interrupt Event Register Interrupt Mask Register Receive Descriptor Active Register Transmit Descriptor Active Register Ethernet Control Register MII Management Frame Register MII Speed Control Register MIB Control/Status Register Receive Control Register Transmit Control Register Physical Address Low Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-37 System Memory and Register Map Table 2-8. Register Map (continued) Module Name FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC Address 0x1002_B0E8 0x1002_B0EC 0x1002_B118 0x1002_B11C 0x1002_B120 0x1002_B124 0x1002_B144 0x1002_B14C 0x1002_B150 0x1002_B180 0x1002_B184 0x1002_B188 0x1002_B200 0x1002_B204 0x1002_B208 0x1002_B20C 0x1002_B210 0x1002_B214 0x1002_B218 0x1002_B21C 0x1002_B220 0x1002_B224 0x1002_B228 0x1002_ 22C 0x1002_B230 0x1002_B234 0x1002_B238 0x1002_B23C 0x1002_B240 0x1002_B244 0x1002_B248 0x1002_B24C 0x1002_B250 Register Name PAUR OPD IAUR IALR GAUR GALR TFWR FRBR FRSR ERDSR ETDSR EMRBR RMON_T_DROP RMON_T_PACKETS RMON_T_BC_PKT RMON_T_MC_PKT RMON_T_CRC_ALIGN RMON_T_UNDERSIZE RMON_T_OVERSIZE RMON_T_FRAG RMON_T_JAB RMON_T_COL RMON_T_P64 RMON_T_P65TO127 RMON_T_P128TO255 RMON_T_P256TO511 RMON_T_P512TO1023 RMON_T_P1024TO2047 RMON_T_P_GTE2048 RMON_T_OCTETS IEEE_T_DROP IEEE_T_FRAME_OK IEEE_T_1COL Description Physical Address High+ Type Field Opcode + Pause Duration Upper 32 bits of Individual Hash Table Lower 32 Bits of Individual Hash Table Upper 32 bits of Group Hash Table Lower 32 bits of Group Hash Table Transmit FIFO Watermark FIFO Receive Bound Register FIFO Receive FIFO Start Registers Pointer to Receive Descriptor Ring Pointer to Transmit Descriptor Ring Maximum Receive Buffer Size Count of frames not counted correctly RMON Tx packet count RMON Tx Broadcast Packets RMON Tx Multicast Packets RMON Tx Packets w CRC/Align error RMON Tx Packets < 64 bytes, good crc RMON Tx Packets > MAX_FL bytes, good crc RMON Tx Packets < 64 bytes, bad crc RMON Tx Packets > MAX_FL bytes, bad crc RMON Tx collision count RMON Tx 64 byte packets RMON Tx 65 to 127 byte packets RMON Tx 128 to 255 byte packets RMON Tx 256 to 511 byte packets RMON Tx 512 to 1023 byte packets RMON Tx 1024 to 2047 byte packets RMON Tx packets w > 2048 bytes RMON Tx Octets Count of frames not counted correctly Frames Transmitted OK Frames Transmitted with Single Collision MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-38 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC FEC Address 0x1002_B254 0x1002_B258 0x1002_B25C 0x1002_B260 0x1002_B264 0x1002_B268 0x1002_B26C 0x1002_B270 0x1002_B274 0x1002_B284 0x1002_B288 0x1002_B28C 0x1002_B290 0x1002_B294 0x1002_B298 0x1002_B29C 0x1002_B2A0 0x1002_B2A4 0x1002_B2A8 0x1002_B2AC 0x1002_B2B0 0x1002_B2B4 0x1002_B2B8 0x1002_B2BC 0x1002_B2C0 0x1002_B2C4 0x1002_B2C8 0x1002_B2CC 0x1002_B2D0 0x1002_B2D4 0x1002_B2D8 0x1002_B2DC 0x1002_B2E0 Register Name IEEE_T_MCOL IEEE_T_DEF IEEE_T_LCOL IEEE_T_EXCOL IEEE_T_MACERR IEEE_T_CSERR IEEE_T_SQE IEEE_T_FDXFC IEEE_T_OCTETS_OK RMON_R_PACKETS RMON_R_BC_PKT RMON_R_MC_PKT RMON_R_CRC_ALIGN RMON_R_UNDERSIZE RMON_R_OVERSIZE RMON_R_FRAG RMON_R_JAB RMON_R_RESVD_0 RMON_R_P64 RMON_R_P65TO127 RMON_R_P128TO255 RMON_R_P256TO511 RMON_R_P512TO1023 RMON_R_P1024TO2047 RMON_R_P_GTE2048 RMON_R_OCTETS IEEE_R_DROP IEEE_R_FRAME_OK IEEE_R_CRC IEEE_R_ALIGN IEEE_R_MACERR IEEE_R_FDXFC IEEE_R_OCTETS_OK Description Frames Transmitted with Multiple Collisions Frames Transmitted after Deferral Delay Frames Transmitted with Late Collision Frames Transmitted with Excessive Collisions Frames Transmitted with Tx FIFO Underrun Frames Transmitted with Carrier Sense Error Frames Transmitted with SQE Error Flow Control Pause frames transmitted Octet count for Frames Transmitted w/o Error RMON Rx packet count RMON Rx Broadcast Packets RMON Rx Multicast Packets RMON Rx Packets w CRC/Align error RMON Rx Packets < 64 bytes, good crc RMON Rx Packets > MAX_FL bytes, good crc RMON Rx Packets < 64 bytes, bad crc RMON Rx Packets > MAX_FL bytes, bad crc Reserved RMON Rx 64 byte packets RMON Rx 65 to 127 byte packets RMON Rx 128 to 255 byte packets RMON Rx 256 to 511 byte packets RMON Rx 512 to 1023 byte packets RMON Rx 1024 to 2047 byte packets RMON Rx packets w > 2048 bytes RMON Rx Octets Count of frames not counted correctly Frames Received OK Frames Received with CRC Error Frames Received with Alignment Error Receive Fifo Overflow count Flow Control Pause frames received Octet count for Frames Rcvd w/o Error MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-39 System Memory and Register Map Table 2-8. Register Map (continued) Module Name SCC SCC SCC SCC SCC SCC SCC SCC SCC SCC Address 0x1002_C000 0x1002_C004 0x1002_C008 0x1002_C010 0x1002_C014 0x1002_C018 0x1002_C01C 0x1002_C020 0x1002_C024 0x1002_C400 – 0x1002_C7FF 0x1002_C800 – 0x1002_CBFF 0x1002_D000 0x1002_D004 0x1002_D008 0x1002_D00C 0x1002_D010 0x1002_D014 0x1002_D018 0x1002_D01C 0x1002_D020 0x1002_D024 0x1002_D028 0x1002_D02C 0x1002_D030 0x1002_D034 0x1002_D038 0x1003_B000 0x1003_B004 0x1003_B008 0x1003_B00C Register Name RED_START BLACK_START LENGTH SCM_STAT SCM_ERROR INTERRUPT_CONTROL CONFIGURATION INIT_VECTOR 0 INIT_VECTOR1 SCM_RED_MEM Description SCM Red Memory Start Addr Register SCM Black Memory Start Addr Register SCM Encrypt/Decrypt Data Length Register SCM Status Register SCC Error Status Register SCC Interrupt Control Register SCC Configuration Register Initial Vector 0 Register Initial Vector 1 Register SCM Red Memory SCC SCM_BLACK_MEM SCM Black Memory SCC SCC SCC SCC SCC SCC SCC SCC SCC SCC SCC SCC SCC SCC SCC ETB REG ETB REG ETB REG ETB REG SMN_STAT SMN_COMMAND SEQ_START SEQ_END SEQ_CHECK BIT_COUNT BIT_BANK_INC_SIZE BIT_BANK_DEC CMP_SIZE PLAINTEXT_CHECK CIPHER CHECK TIMER IV TIMER CONTROL DEBUG DETECTOR STATUS TIMER ETB_ID ETB_RAM_DEPTH ETB_RAM_WIDTH ETB_STATUS SMN Status Register SMN Command Register Sequence Start Value Register Sequence End Value Register Sequence Check Register Bit Count Register Bit Bank Increment Size Register Bit Bank Decrement Compare Size Register Plaintext Check Register Ciphertext Check Register Timer Initial Vector Register Timer Control Register Debug Port Detection Status Register Timer Register ETB Identify Register ETB RAM depth Register ETB RAM width Register ETB Status Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-40 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name ETB REG ETB REG ETB REG ETB REG ETB REG JAM JAM MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX AITC AITC AITC AITC AITC AITC AITC AITC Address 0x1003_B010 0x1003_B014 0x1003_B018 0x1003_B01C 0x1003_B020 0x1003_E000 0x1003_E010 0x1003_F000 0x1003_F100 0x1003_F200 0x1003_F004 0x1003_F104 0x1003_F204 0x1003_F010 0x1003_F110 0x1003_F210 0x1003_F014 0x1003_F114 0x1003_F214 0x1003_F800 0x1003_F900 0x1003_FA00 0x1003_FB00 0x1003_FC00 0x1003_FD00 0x1004_0000 0x1004_0004 0x1004_0008 0x1004_000C 0x1004_0010 0x1004_0014 0x1004_0018 0x1004_001C Register Name ETB_DATA ETB_READ_POINTER ETB_WRITE_POINTER ETB_TRIGGER_COUNTER ETB_CONTROL JAM_ARM9P_GPR0 JAM_ARM9P_GPR4 MPR0 MPR1 MPR2 AMPR0 AMPR1 AMPR2 SGPCR0 SGPCR1 SGPCR2 ASGPCR0 ASGPCR1 ASGPCR2 MGPCR0 MGPCR1 MGPCR2 MGPCR3 MGPCR4 MGPCR5 INTCNTL NIMASK INTENNUM INTDISNUM INTENABLEH INTENABLEL INTTYPEH INTTYPEL ETB Data Register ETB Read Pointer Register ETB Write Pointer Register ETB Trigger Counter Register ETB Control Register JAM ARM9P General Purpose Register 0 JAM ARM9P General Purpose Register 4 Master Priority Register for Slave Port 0 Master Priority Register for Slave Port 1 Master Priority Register for Slave Port 2 Alternate Master Priority Register for Slave Port 0 Alternate Master Priority Register for Slave Port 1 Alternate Master Priority Register for Slave Port 2 General Purpose Control Register for Slave Port 0 General Purpose Control Register for Slave Port 1 General Purpose Control Register for Slave Port 2 Alternate SGPCR for Slave Port 0 Alternate SGPCR for Slave Port 1 Alternate SGPCR for Slave Port 2 General Purpose Control Register for Master Port 0 General Purpose Control Register for Master Port 1 General Purpose Control Register for Master Port 2 General Purpose Control Register for Master Port 3 General Purpose Control Register for Master Port 4 General Purpose Control Register for Master Port 5 Interrupt Control Register Normal Interrupt Mask Register Interrupt Enable Number Register Interrupt Disable Number Register Interrupt Enable Register High Interrupt Enable Register Low Interrupt Type Register High Interrupt Type Register Low Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-41 System Memory and Register Map Table 2-8. Register Map (continued) Module Name AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC AITC CSI CSI CSI CSI CSI CSI CSI CSI ATA ATA ATA ATA ATA ATA ATA Address 0x1004_0020 0x1004_0024 0x1004_0028 0x1004_002C 0x1004_0030 0x1004_0034 0x1004_0038 0x1004_003C 0x1004_0040 0x1004_0044 0x1004_0048 0x1004_004C 0x1004_0050 0x1004_0054 0x1004_0058 0x1004_005C 0x1004_0060 0x1004_0064 0x8000_0000 0x8000_0004 0x8000_0008 0x8000_000C 0x8000_0010 0x8000_0014 0x8000_0018 0x8000_001C 0x8000_1000 0x8000_1004 0x8000_1008 0x8000_100C 0x8000_1010 0x8000_1014 0x8000_1018 Register Name NIPRIORITY7 NIPRIORITY6 NIPRIORITY5 NIPRIORITY4 NIPRIORITY3 NIPRIORITY2 NIPRIORITY1 NIPRIORITY0 NIVECSR FIVECSR INTSRCH INTSRCL INTFRCH INTFRCL NIPNDH NIPNDL FIPNDH FIPNDL CSICR1 CSICR2 CSISR CSISTATR CSIRXR CSIRXCNT CSIDEBUG CSICR3 TIME_CONFIG0 TIME_CONFIG1 TIME_CONFIG2 TIME_CONFIG3 TIME_CONFIG4 TIME_CONFIG5 FIFO_DATA_32 Description Normal Interrupt Priority Level Register 7 Normal Interrupt Priority Level Register 6 Normal Interrupt Priority Level Register 5 Normal Interrupt Priority Level Register 4 Normal Interrupt Priority Level Register 3 Normal Interrupt Priority Level Register 2 Normal Interrupt Priority Level Register 1 Normal Interrupt Priority Level Register 0 Normal Interrupt Vector and Status Register Fast Interrupt Vector and Status Register Interrupt Source Register High Interrupt Source Register Low Interrupt Force Register High Interrupt Force Register Low Normal Interrupt Pending Register High Normal Interrupt Pending Register Low Fast Interrupt Pending Register High Fast Interrupt Pending Register Low CSI Control Register 1 CSI Control Register 2 CSI Status Register CSI Statistic FIFO Register CSI RxFIFO Register CSI RX Count Register CSI Debug Register CSI Control Register 3 ATA timing parameter 0. ATA timing parameter 1. ATA timing parameter 2. ATA timing parameter 3. ATA timing parameter 4. ATA timing parameter 5. 32-bit wide data port to/from FIFO MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-42 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name ATA ATA ATA ATA ATA ATA ATA ATA ATA ATA ATA ATA ATA ATA ATA ATA NFC NFC NFC NFC NFC NFC NFC NFC NFC NFC NFC NFC NFC NFC NFC Address 0x8000_101C 0x8000_1020 0x8000_1024 0x8000_1028 0x8000_102c 0x8000_1030 0x8000_1034 0x8000_10A0 0x8000_10A4 0x8000_10A8 0x8000_10AC 0x8000_10B0 0x8000_10B4 0x8000_10B8 0x8000_10BC 0x8000_10D8 0xD800_0E00 0xD800_0E02 0xD800_0E04 0xD800_0E06 0xD800_0E08 0xD800_0E0A 0xD800_0E0C 0xD800_0E0E 0xD800_0E10 0xD800_0E12 0xD800_0E14 0xD800_0E16 0xD800_0E18 0xD800_0E1A 0xD800_0E1C Register Name FIFO_DATA_16 FIFO_FILL ATA_CONTROL INT_PENDING INT_ENABLE INT_CLEAR FIFO_ALARM DCTR DDTR DFTR DSCR DSNR DCLR DCHR DDHR DCDR NFC_BUFSIZE Reserved RAM_BUFFER_ADDRESS NAND_FLASH_ADD NAND_FLASH_CMD NFC_CONFIGURATION ECC_STATUS_RESULT ECC_RSLT_MAIN_AREA ECC_RSLT_SPARE_AREA NF_WR_PROT UNLOCK_START_BLK_ADD UNLOCK_END_BLK_ADD NAND_FLASH_WR_PR_ST NAND_FLASH_CONFIG1 NAND_FLASH_CONFIG2 Description 16-bit wide data port to/from FIFO FIFO Filling in Halfwords ATA Interface Control Register Interrupt Pending Register Interrupt Enable Register Interrupt Clear Register FIFO Alarm Threshold Drive Data Register Drive Features Register Drive Sector Count Register Drive Sector Number Register Drive Cylinder Low Register Drive Cylinder High Register Drive Device Head Register Drive Command Register (W)/ Drive Status Register (R) Drive Alternate Status Register (W)/ Drive Control Register (R) Internal SRAM Size Reserved Buffer Number for Page Data Transfer To/ From Flash Memory NAND Flash Address NAND Flash Command NFC Internal Buffer Lock Control Controller Status/Result of Flash Operation ECC Error Position of Main Area Data Error ECC Error Position of Spare Area Data Error Nand Flash Write Protection Start Address for Write Protection Unlock End Address for Write Protection Unlock Current Nand Flash Write Protection Status Nand Flash Operation Configuration 1 Nand Flash Operation Configuration 2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-43 System Memory and Register Map Table 2-8. Register Map (continued) Module Name ESDCTL ESDCTL ESDCTL ESDCTL ESDCTL WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM WEIM M3IF M3IF M3IF M3IF M3IF M3IF M3IF M3IF M3IF Address 0xD800_1000 0xD800_1004 0xD800_1008 0xD800_100C 0xD800_1010 0xD800_2000 0xD800_2004 0xD800_2008 0xD800 2010 0xD800_2014 0xD800_2018 0xD800_2020 0xD800_2024 0xD800_2028 0xD800_2030 0xD800_2034 0xD800_2038 0xD800_2040 0xD800_2044 0xD800_2048 0xD800_2050 0xD800_2054 0xD800_2058 0xD800_2060 0xD800_3000 0xD800_3028 0xD800_302C 0xD800_3030 0xD800_3034 0xD800_3038 0xD800_3040 0xD800_3044 0xD800_3048 Register Name ESD_ESDCTL0 ESD_ESDCFG0 ESD_ESDCTL1 ESD_ESDCFG1 ESD_ESDMISC CS0U CS0L CS0A CS1U CS1L CS1A CS2U CS2L CS2A CS3U CS3L CS3A CS4U CS4L CS4A CS5U CS5L CS5A EIM M3IF_CTL M3IF_SCFG0 M3IF_SCFG1 M3IF_SCFG2 M3IF_SSR0 M3IF_SSR1 M3IFMLWE0 M3IFMLWE1 M3IFMLWE2 Description SDRAM/MDDR 0 Control Register SDRAM/MDDR 0 Timing Config Register SDRAM/MDDR 1 Control Register SDRAM/MDDR 1 Timing Config Register SDRAM/MDDR Miscellaneous Register Chip Select 0 Upper Control Register Chip Select 0 Lower Control Register Chip Select 0 Addition Control Register Chip Select 1 Upper Control Register Chip Select 1 Lower Control Register Chip Select 1 Addition Control Register Chip Select 2 Upper Control Register Chip Select 2 Lower Control Register Chip Select 2 Addition Control Register Chip Select 3 Upper Control Register Chip Select 3 Lower Control Register Chip Select 3 Addition Control Register Chip Select 4 Upper Control Register Chip Select 4 Lower Control Register Chip Select 4 Addition Control Register Chip Select 5 Upper Control Register Chip Select 5 Lower Control Register Chip Select 5 Addition Control Register EIM Configuration Register M3IF control register M3IF Snooping Configuration Register 0 M3IF Snooping Configuration Register 1 M3IF Snooping Configuration Register 2 M3IF Snooping Status Register 0 M3IF Snooping Status Register 1 M3IF Master Lock WEIM CS0 Register M3IF Master Lock WEIM CS1 Register M3IF Master Lock WEIM CS2 Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-44 Freescale Semiconductor System Memory and Register Map Table 2-8. Register Map (continued) Module Name M3IF M3IF M3IF PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA Address 0xD800_304C 0xD800_3050 0xD800_3054 0xD800_4000 0xD800_4004 0xD800_4008 0xD800_400C 0xD800_4010 0xD800_4014 0xD800_4018 0xD800_401C 0xD800_4020 0xD800_4024 0xD800_4028 0xD800_402C 0xD800_4030 0xD800_4034 0xD800_4038 0xD800_403C 0xD800_4040 0xD800_4044 0xD800_4048 0xD800_404C 0xD800_4050 0xD800_4054 0xD800_4058 0xD800_405C 0xD800_4060 0xD800_4064 Register Name M3IFMLWE3 M3IFMLWE4 M3IFMLWE5 PCMCIA_PIPR PCMCIA_PSCR PCMCIA_PER PCMCIA_PBR0 PCMCIA_PBR1 PCMCIA_PBR2 PCMCIA_PBR3 PCMCIA_PBR4 PCMCIA_PBR5 PCMCIA_PBR6 PCMCIA_POR0 PCMCIA_POR1 PCMCIA_POR2 PCMCIA_POR3 PCMCIA_POR4 PCMCIA_POR5 PCMCIA_POR6 PCMCIA_POFR0 PCMCIA_POFR1 PCMCIA_POFR2 PCMCIA_POFR3 PCMCIA_POFR4 PCMCIA_POFR5 PCMCIA_POFR6 PCMCIA_PGCR PCMCIA_PGSR Description M3IF Master Lock WEIM CS3 Register M3IF Master Lock WEIM CS4 Register M3IF Master Lock WEIM CS5 Register PCMCIA Input Pins Register PCMCIA Status Changed Register PCMCIA Enable Register PCMCIA Base Register 0 PCMCIA Base Register 1 PCMCIA Base Register 2 PCMCIA Base Register 3 PCMCIA Base Register 4 PCMCIA Base Register 5 PCMCIA Base Register 6 PCMCIA Option Register 0 PCMCIA Option Register 1 PCMCIA Option Register 2 PCMCIA Option Register 3 PCMCIA Option Register 4 PCMCIA Option Register 5 PCMCIA Option Register 6 PCMCIA Offset Register 0 PCMCIA Offset Register 1 PCMCIA Offset Register 2 PCMCIA Offset Register 3 PCMCIA Offset Register 4 PCMCIA Offset Register 5 PCMCIA Offset Register 6 PCMCIA General Control Register PCMCIA General Status Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 2-45 System Memory and Register Map MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2-46 Freescale Semiconductor Chapter 3 Clocks, Power Management, and Reset Control 3.1 Introduction There are two clock controller modules in the i.MX27 Multimedia Applications Processor: The ARM9 Platform Clock Controller and the PLL Clock Controller module (CCM), which produces the clock signals used and distributed by the ARM9 Platform Clock Controller. • ARM9 Platform Clock Controller—The primary function of the ARM9 Platform Clock Controller is to take the clock signals from the PLL Clock Controller and distribute them to various peripherals on the ARM9 Platform. The clock control module contains the logic to turn clocks on or off and to determine when the ARM9 Platform’s clock can be turned off. This module also synchronizes the JTAG interface to the CLK domain. • PLL Clock Controller—This module generates clock signals used throughout the i.MX27 chip and external peripherals. The PLL Clock Controller also serves as the interface between the ARM9 Platform and the peripherals on the i.MX27 device. The ARM9 Platform Clock Controller is not a user-programmable or accessible module, whereas the PLL Clock Controller is accessible—therefore, only the PLL Clock Controller is described in this chapter. 3.2 Clock Controller Architecture Block Diagram There are two DPLLs in the PLL Clock Controller—the MCU/System PLL (MPLL) and the Serial Peripheral PLL (SPLL), which uses digital and mixed analog/digital circuits to provide clock frequencies for wireless communication and other applications. The MPLL primarily generates the CLK signal to the ARM9 and HCLK (also called System clock) for the system bus and for most of the on-chip peripherals, including the LCDC pixel clock and the NAND Flash Controller clock. The SPLL produces the primary clock to the clock dividers for USB OTG, SSI1, and SSI2. Both MPLL and SPLL accept either the output of the FPM or the OSC26M as a source from which to generate the required frequencies for the ARM9 Platform and/or peripherals using a fractional frequency multiplication method. Detailed information about the calculation of the DPLL settings is shown in Section 3.2.2, “Output Frequency Calculations.” To produce the wide range of on-chip clock frequencies required by the i.MX27 processor, the core clock generator uses a two-stage phase locked loop. The first stage is a Frequency Pre-Multiplier PLL (FPM), which multiplies the input frequency by a factor of 1024. If the input crystal frequency is 32.768 kHz, the premultiplier multiplies it by a factor of 1024 to 33.554 MHz (32.768 MHz for a 32.0 KHz crystal). The output of the FPM is one of the clock sources for the MPLL and SPLL. Power management in the i.MX27 device is accomplished by controlling the clock output of the MPLL and SPLL units. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-1 Clocks, Power Management, and Reset Control The distribution of clocks in the i.MX27 processor is shown in the general block diagram, Figure 3-1. There are two external clock sources to the PLL Clock Controller, as follows: • 32 kHz external crystal • 26 MHz external source/crystal Settings in the Clock Source Control Register (CSCR) are used to independently configure the external clock sources applied to the MPLL and SPLL. OSC 32K CLK 32K FPM 0 MPLL 1 MPLL CLK FPM EN BYPASS[1] OSC26M DIS BYPASS[0] DIV 1P5 OSC 26M EXT 60M 0 0 1 BYPASS[0] OSC26M DIV1p5 0 1 MPLLCLK SEL BYPASS[1] UPLLCLK SEL BYPASS[1] UPLL SPLL 1 0 1 SPLL CLK UPLL CLK BYPASS[2] Figure 3-1. i.MX27 Clock Distribution Block Diagram (1 of 2) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-2 Freescale Semiconductor Clocks, Power Management, and Reset Control B Y PA S S [2] A RM SRC A R M D IV : 1 D IV 2 2X Clo c k Por t A RM CLK 1 0 E XT 26 6 M 0 A R M D IV M CU DP LL MPLL A HB D IV : D IV 3 0 A H B D IV 1 IP G D IV B Y PA S S [2 ] N F C D IV : A HB CLK IP G C L K E XT 2 6 6 M N F C D IV PER 1 D IV : NFC U A R T/ G P T/ P W M P E R 1 D IV P E R 2 D IV : S DHC/CS P I P E R 2 D IV P E R 3 D IV : LC D C P E R 3 D IV PER 4 D IV : P E R 4 D IV CS I S S I1 D IV : 1 Ref Cloc k S S I1D IV US B DP LL SPLL 0 S S I2 D IV : S S I1 1 S S I2D IV 0 M S HC D IV : S S I2 1 M S H C D IV 0 H2 6 4 D IV : M SHC 1 H 26 4 D IV 0 U S B D IV : H 26 4 U S B D IV US B Figure 3-2. i.MX27 Clock Distribution Block Diagram (2 of 2) Table 3-1. PLL Clock Controller Signal Descriptions Signal Names CLK HCLK Description Fast clock used only by ARM9 Platform for internal operations, such as executing instructions from the cache. Can be gated during Doze and Sleep mode when all the criteria are met to enter a low power. System clock. Appears as the BCLK input to the CPU and the HCLK to the system. This is a continuous clock (when the system is not in Sleep mode). It can be gated during Doze and Sleep mode when all the criteria are met to enter a low power. Used to signify the rising edge of CLK that corresponds to the rising edge of HCLK. It is used by the ARM9 Platform only. 60 MHz clock for the USB OTG module Divided clock output for the SSI1 module Divided clock output for the SSI2 module Divided clock output for the NAND Flash Controller module Divided clock output for the H264 module Divided clock output for the MSHC module HCLKEN CLK60M SSI1CLK SSI2CLK NFCCLK H264CCLK MSHCCLK MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-3 Clocks, Power Management, and Reset Control Table 3-1. PLL Clock Controller Signal Descriptions (continued) Signal Names PERCLK1 PERCLK2 PERCLK3 PERCLK4 CLKO Description Divided clock output for peripheral set 1 (UART, Timer, PWM) Divided clock output for peripheral set 2 (SDHC, CSPI) Divided clock output for the LCDC Divided clock output for the CSI Selected internal clock output to the CLKO pin A9P_CLK_OFF Control signal from the ARM9 Platform Clock Controller 3.2.1 High Frequency Clock Source and Distribution Two DPLLs—MPLL and SPLL—on the i.MX27 device are used to generate two separate clock frequencies from either the Frequency Pre-Multiplier (FPM) or an external high frequency source (CLK26M). The clock source for each DPLL is individually selected using bits in the Clock Source Control Register (CSCR). The MCU/System PLL (MPLL) is configured by the MPCTL registers (MPCTL0, MPCTL1) to produce system clock signals that are divided down to output the FCLK (for example 266 MHz) and the HCLK (for example, 133 MHz) clock signals. MPLL serves as the clock source for the PERCLK4, PERDIV3, PERDIV2, and PERDIV1. FCLK serves as the clock source for the NFCDIV divider. These dividers produce the clock signals for the following: • NAND Flash Controller (NFC) • Peripheral set 1 (PERCLK1): UART, Timer, and PWM • Peripheral set 2 (PERCLK2): SDHC and CSPI • LCDC Pixel Clock (PERCLK3) • CSI (PERCLK4) Serial Peripheral PLL (SPLL) is configured by SPCTL registers (SPCTL0, SPCTL1) and produces input signals for the USBDIV, SSI1DIV, SSI2DIV, H264DIV, and MSHCDIV dividers, which generate clock signals for serial peripherals that require special clock frequencies: • CLK60M—for the USB OTG • SSI1CLK—Clock signal for SSI1 • SSI2CLK—Clock signal for SSI2 • H264CCLK—Clock signal for H264 • MSHCCLK—Clock signal for MSHC The clock source for the SSI1DIV and SSI2DIV dividers can be the MPLL or SPLL. Source selection is controlled by the respective bits in the Clock Source Control register (CSCR). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-4 Freescale Semiconductor Clocks, Power Management, and Reset Control 3.2.2 Output Frequency Calculations Both DPLLs produce a high frequency clock that exhibits a low frequency jitter and a low phase jitter. The DPLL output clock frequency (fdpll) is determined by the Equation 3-1: fdpll = 2fref • MFI + MFN / (MFD+1) PD+1 Eqn. 3-1 where: • fref is the reference frequency (1024 × 32.768 kHz, 1024 × 32.0 kHz, or 26 MHz). • MFI is an integer part of a multiplication factor (MF). • MFN is the numerator and MFD is the denominator of the MF. • PD is the predivider factor. NOTE In bootstrap mode, the PLL registers assume a source clock of 32.768 KHz. If using bootstrap mode, use a 32.768 KHz crystal. 3.3 Power Management The PLL Clock Controller module is designed with clock control at various stages of clock supply to achieve optimum power savings. The operation of the PLL and clock controller at different stages of power management is described in the following sections. 3.3.1 PLL Operation at Power-Up The crystal oscillator begins oscillating within several hundred milliseconds of initial power-up. While system reset remains asserted the PLL begins the lockup sequence and locks 1 ms after the crystal oscillator becomes stable. Both DPLLs are enabled on power-up. The system reset is held asserted by the PLL Clock Controller for 300 ms + 14 cycles of the 32 kHz, as shown in Figure 3-17. 3.3.2 PLL Operation at Wake-Up When the device is awakened from Sleep mode by a wake-up event, the DPLL locks within 350 µs. The crystal oscillator is always on after initial power-up, so crystal startup time is not a factor. The PLL output clock starts operating as soon as it achieves lock. 3.3.3 i.MX27 Processor Low-Power Modes The i.MX27 processor provides two power saving modes—Doze mode and Sleep mode: • In Doze mode, the ARM9 executes a wait for interrupt (WFI) instruction. System clocks are still active. • In Sleep mode, the ARM9 executes a wait for interrupt (WFI) instruction. The output of the MPLL and SPLL are shut down and only the 32 kHz clock is running. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-5 Clocks, Power Management, and Reset Control These modes are controlled by the clock control logic and a sequence of CPU instructions. Most of the peripheral modules can enable or disable the incoming clock signal through clock gating circuitry from the peripheral bus. Each module has a module enable bit which, when disabled, disables the operational clock to the module. The i.MX27 PLL Clock Controller provides the Low-Power mode information to the Watchdog (WDOG) module. 3.3.3.1 Doze Mode Doze mode is defined as when the ARM9 executes a wait for an interrupt instruction, after which the buffered clock supply to the MCU is turned off. The sequence of operation to set the system to Doze mode is as follows: 1. Enable desired interrupts for wake-up from Doze mode. 2. Disable watchdog timer interrupt. 3. Execute wait-for-interrupt instruction. The ARM9 executes a wait for interrupt instruction if all required conditions are met (no irq, fiq, or debug requests pending), the ARM9 Platform generates an A9P_CLK_OFF signal to the PLL Clock Controller module. The CLK signal to the MCU is immediately turned off when the A9P_CLK_OFF signal goes active. CLK_ALWAYS and system bus (HCLK) remain running. HCLK is required by the Cross Bar Switch within the ARM9 Platform for continuous operation of peripheral modules. When an unmasked interrupt event occurs, the CLK signal to the ARM9 is re-enabled. 3.3.3.2 Sleep Mode Sleep mode is defined as when all the DPLLs clock outputs are disabled. A sequence of operations and criteria must be satisfied before the system turns off the MPLL and SPLL. The Sleep mode sequence is initiated when the MPEN bit in the CSCR register is cleared disabling the MPLL. This action also automatically turns off the SPLL. The sequence to put the system into Sleep mode is as follows: 1. Disable AHB peripherals from bus accesses. 2. Enable desired interrupts to be used for system wake-up. 3. Disable watchdog timer interrupt. 4. Set the required value to the SD_CNT (CSCR register) for shutdown countdown. 5. Disable the MPLL by clearing the MPEN bit (CSCR register). 6. Execute wait-for-interrupt instruction. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-6 Freescale Semiconductor Clocks, Power Management, and Reset Control The example of programming setup to enter Sleep mode is as follows: Code Example 3-1. Programming Setup for Entering Sleep Mode MRS AND MSR LDR LDRH ORR STRH LDR LDR ORR STR BIC STR LDR MCR r0, CPSR ; Enable interrupts r1, r0, #(ENABLE_IRQ+ENABLE_FIQ+MODE_BITS) CPSR_c, r1 r3, =WDG_BASEADDR ; Disable WDG Timer r4, [r3, #0x0] r4, r4, #0x00000001 r4, [r3, #0x0] r1, =CRM_BASEADDR ; Set SDCNT to ‘01’ r2, [r1, #0x0] r2, r2, #0x0100_0000 r2, [r1, #0x0] r2, r2, #0x00000001 ; Disable MPEN r2, [r1, #0x0] r1, 0x00000000 p15, 0, r1, c7, c0, 4 ; WFI The MPLL and SPLL are turned off when the countdown value in SD_CNT is satisfied. For the MPLL, there are a number of conditions that must be satisfied before the Clock Controller module turns off the DPLL. The conditions to be satisfied before the PLL Clock Controller actually turns off the MPLL are as follows: 1. Clock Controller module has successfully mastered the system bus. 2. The A9P_CLK_OFF signal from the ARM9 Platform is active. 3. SDRAM controller has successfully placed the external SDRAM into Self-Refresh mode. 4. After the above conditions are satisfied, the countdown based on the value in the SD_CNT field will be initiated. 5. SD_CNT countdown completes. When the conditions listed above are satisfied the MPLL and the SPLL will be turned off. The Frequency Premultiplier (FPM) is also disabled in the Sleep mode. The FPM_EN bit (CSCR register) must not be cleared if the FPM is providing the clock source to the DPLL. When an unmasked interrupt event occurs, the FPM and then the MPLL are re-enabled and the MPLL enable bit (MPEN) automatically restored to its enable setting. The SPLL is restored to its original state based on the setting of the SPEN bit before Sleep mode. If the SPLL was not enabled before entering Sleep mode the SPLL will not be enabled. The total start-up time from Sleep mode is the sum of the FPM lock time and the DPLL lock time. In Sleep mode, the i.MX27 device retains all RAM data and register configuration values. Data to output terminals is also maintained and thus will continue to sink/source static current. NOTE System software must ensure that if there are any clocks being sourced by the i.MX27 processor to external peripherals (for example, SSI MCLK), then the corresponding PLL must not be turned off. In such cases, the i.MX27 processor must remain in Doze mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-7 Clocks, Power Management, and Reset Control 3.3.4 SDRAM Power Modes When the SDRAM controller (SDRAMC) is enabled, the external SDRAM operates in Distributed-Refresh mode or in Self-Refresh mode (as shown in Table 3-2). The SDRAM wake-up latency is approximately 20 system clock cycles (HCLK). The SDRAMC can wake up from Self-Refresh mode when it is in a SDRAM cycle. In Doze and Run mode, the Power Down timers within the SDRAMC can be enabled to cause the SDRAM to enter Power Down mode on detecting no activity. The SDRAMC still controls the refresh and it takes the SDRAM out of the Power Down mode to perform refresh when needed and then put it back into the Power Down mode. In Power Down mode the clock to the SDRAM is gated off and the CKE pin goes low. In addition since the SDRAM will be in self refresh just when the system get into Sleep mode, no bus cycle can access the SDRAM to cause it to exit the Self-Refresh mode. Exit from Self-Refresh mode will happen when the chip will exit the Sleep mode and re-enable the MPEN. Table 3-2. SDRAM Operation During Power Modes SDRAM SDRAM Run Distributed-refresh, Note 1 Doze Distributed-refresh, Note 1 Stop Self-refresh 3.3.5 Power Management in the PLL Clock Controller The i.MX27 device has a very efficient clock control scheme that enables clocking control of the modules and devices at various stages. Power management in the i.MX27 device is achieved by controlling the duty cycles of the clock system efficiently. The clocking control scheme is shown in Table 3-3. Table 3-3. Power Management in the Clock Controller Device/Signal MPLL SPLL FPM CLK32 Shut-Down Conditions When 0 is written to the MPEN bit and the PLL shut-down count times out (for details see the SD_CNT settings in Table 3-6). When 0 is written to the SPEN bit. When 0 is written to the FPMEN bit. Continuously running. Wake-Up Conditions When IRQ or FIQ is asserted When the SPEN bit is set to 1 When the FPMEN bit is set to 1 Continuously running Most modules in the i.MX27 processor have a module enable bit assigned which must be enabled before the module is active. Enabling the module enables the clock source for the module to be provided for its main operations. The clock input to the dividers from the SPLL is also controlled separately in the same manner. 3.3.6 Power Management Using Frequency Control The i.MX27 processor has DPTC, but does not support the DVFS feature. The i.MX27 device provides a way for software to save power under different operating conditions. • Software determines whether to change the operation frequency or not. • Software uses DPTC to determine whether to reduce or increase the power supply. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-8 Freescale Semiconductor Clocks, Power Management, and Reset Control • • After the power supply has been changed, software can update MPLL configuration. It restarts the MPLL and operates with new frequency. 3.4 Memory Map and Register Definition The PLL Clock Controller module includes six user-accessible 32-bit registers. Table 3-4 provides the memory map for the PLL Clock Controller. Table 3-4. PLL Clock Controller Memory Map Address Register General Registers 0x1002_7000 (CSCR) 0x1002_7004 (MPCTL0) 0x1002_7008 (MPCTL1) 0x1002_700C (SPCTL0) 0x1002_7010 (SPCTL1) 0x1002_7014 (OSC26MCTL) 0x1002_7018 (PCDR0) 0x1002_701C (PCDR1) 0x1002_7020 (PCCR0) 0x1002_7024 (PCCR1) 0x1002_7028 (CCSR) 0x1002_7034 (WKGDCTL) Clock Source Control Register MPLL Control Register 0 MPLL Control Register 1 SPLL Control Register 0 SPLL Control Register 1 Oscillator 26M Register Peripheral Clock Divider Register 0 Peripheral Clock Divider Register 1 Peripheral Clock Control Register 0 Peripheral Clock Control Register 1 Clock Control Status Register Wakeup Guard Mode Control Register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x33F0_1307 0x0021_1803 0x0000_8000 0x8403_1C53 0x0000_8000 0x0000_3F00 0x2008_3403 0x1204_1303 0x0401_01C0 0xFF4B_6848 0x0000_0300 0x0000_0000 3.4.2/3-10 3.4.3/3-13 3.4.4/3-14 3.4.6/3-16 3.4.7/3-17 3.4.8/3-18 3.4.9/3-20 3.4.10/3-22 3.4.11/3-23 3.4.12/3-26 3.4.13/3-29 3.4.14/3-31 Access Reset Value Section/Page 3.4.1 Register Summary The conventions in Figure 3-3 and Table 3-5 serve as a key for the register summary and individual register diagrams. Always reads 1 1 Always reads 0 0 Write 1 BIT Self-clear 0 R/W BIT Read- BIT Writebit BIT bit only bit only bit BIT to clear w1c N/A Figure 3-3. Key to Register Fields MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-9 Clocks, Power Management, and Reset Control Table 3-5 provides a key for register figures and tables and the register summary. Table 3-5. Register Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types R W R/W rwm w1c Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr) Reset Values 0 1 — u [signal_name] Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. Reset value is determined by polarity of indicated signal. 3.4.2 Clock Source Control Register (CSCR) The Clock Source Control Register controls the various clock sources to the internal modules of the i.MX27 processor. Figure 3-4 shows the register and Table 3-6 provides the field descriptions. 0x1002_7000 (CSCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 USB_DIV 0 0 1 1 0 0 SD_CNT SPLL MPLL SSi2_ SSI1_ H264 MSHC SP_S MCU _RES _RES SEL SEL _SEL _SEL EL _SEL TART TART 1 1 1 1 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARM W SRC Reset 0 R 0 ARMDIV 0 0 1 0 0 AHBDIV 0 0 0 OSC2 OSC2 FPM_ SPE MPE 6M_DI 6M_D EN N N V1P5 IS 0 0 1 1 1 0 0 1 1 0 0 0 Figure 3-4. Clock Source Control Register (CSCR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-10 Freescale Semiconductor Clocks, Power Management, and Reset Control Table 3-6. Clock Source Control Register Field Descriptions Field 31 UPDATE_DIS 30–28 USB_DIV Description Disable source selection and divider update until next MPLL lock. This bit is cleared automatically. When reprogramming the PLL and corresponding CSCR settings, this bit must first be set before the CSCR is updated and DPLL is reprogrammed to ensure that erratic clock behavior does not occur. USB Clock Divider. Contains the 3-bit integer divider value for generation of CLK60M. 000 SPLL_CLK divided by 1 001 SPLL_CLK divided by 2 ... 111 SPLL_CLK divided by 8 Reserved. These bits are reserved and should read 0. Shut-Down Control. Contains the value that determines duration of DPLL clock output before it goes off after a 0 is written to the MPEN or SPEN bit. Note: Power controller requests the bus before SPLL shutdown. Any unmasked interrupt event will enable MPLL. 00 DPLL shuts down after the next rising edge of CLK32 is detected and the current bus cycle is completed. A minimum of 16 HCLK cycles is occurs after writing 0 to MPEN bit. 01 DPLL shuts down after second rising edge of CLK32 is detected and the current bus cycle is completed. 10 DPLL shuts down after third rising edge of CLK32 is detected and the current bus cycle is completed. 11 DPLL shuts down after forth rising edge of CLK32 is detected and the current bus cycle is completed. 23 SSI2_SEL 22 SSI1_SEL 21 H264_SEL 20 MSHC_SEL 19 SPLL_RESTART SSI2 Baud Source Select. Selects the clock source to SSI2 fractional divider (SSI2_DIV). 0 Source clock to SSI2 fractional divider from SPLL 1 Source clock to SSI2 fractional divider from MPLL SSI1 Baud Source Select. Selects the clock source to SSI1 fractional divider (SSI1_DIV). 0 Source clock to SSI1 fractional divider from SPLL 1 Source clock to SSI1 fractional divider from MPLL H264 CCLK Source Select. Selects the clock source to H264 divider (H264_DIV). 0 Source clock to H264 divider is from SPLL 1 Source clock to H264 divider is from MPLL MSHC CCLK Source Select. Selects the clock source to MSHC divider (MSHC_DIV). 0 Source clock to MSHC divider is from SPLL 1 Source clock to MSHC divider is from MPLL SPLL Restart. Restarts SPLL at the new assigned frequency. SPLL_RESTART self-clears after 1 (min) or 2 (max) cycles of CLK32. 0 No Effect 1 Restarts SPLL at new frequency 27–26 25–24 SD_CNT 18 MPLL Restart. Restarts MPLL at the new assigned frequency. MPLL_RESTART self-clears after 1 (min) MPLL_RESTART or 2 (max) cycles of CLK32. 0 No Effect 1 Restarts MPLL at new frequency 17 SP_SEL SPLL Select. Selects clock source of SPLL input. When set, the external high frequency clock input is selected. 0 Clock source is the internal premultiplier. Register map shows this bit as reserved also conflicts with 1 Clock source is the external high frequency clock MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-11 Clocks, Power Management, and Reset Control Table 3-6. Clock Source Control Register Field Descriptions (continued) Field 16 MCU_SEL Description MPLL Select. Selects clock source of MPLL input. When set, the external high frequency clock input is selected. 0 Clock source is the internal premultiplier. 1 Clock source is the external high frequency clock. ARMSRC. It selects the ARM clock source. 0 MPLL CLK * 2 / 3 1 MPLL CLK ARM_DIV. Divider value for arm clk. 00 divide by 1 01 divide by 2 10 divide by 3 11 divide by 4 Reserved AHB_DIV. Divider value for AHB clk. 00 divide by 1 01 divide by 2 10 divide by 3 11 divide by 4 Reserved 15 ARM SRC 13–12 ARM_DIV 11–10 9-8 AHB_DIV 7–5 4 Oscillator 26M Divide Enable. Divides osc26m output by 1 or 1.5. OSC26M_DIV1P5 0 osc26m output divide by 1 (default) 1 osc26m output divide by 1.5 3 OSC26M_DIS 2 FPM_EN Oscillator Disable. Disables the internal (on-chip) 26 MHz oscillator circuit when this bit is set to 1. 0 Enable the internal 26 MHz oscillator circuit 1 Disable the internal 26 MHz oscillator circuit Frequency Premultiplier Enable. Enables/disables FPM when set/cleared. This bit is set automatically on system reset. When the software writes a 0 to this bit, FPM is shut down immediately. This bit must remain at 1 prior and during Sleep mode if FPM is providing the source to the DPLL. 0 Disable the frequency premultiplier circuit 1 Enable the frequency premultiplier circuit Serial Peripheral PLL Enable. Enables/disables the SPLL. When software writes 0 to SPEN, SPLL shuts down after timeout determined by SD_CNT. SPEN sets automatically when SPLLEN asserts, and on system reset. 0 Serial Peripheral PLL disabled 1 Serial Peripheral PLL enabled MPLL Enable. Enables/disables the MPLL. When software writes 0 to MPEN, MPLL shuts down after SDCNT timeout. MPEN sets automatically when MPLLEN asserts, and on system reset. 0 MCU and Serial PLL disabled 1 MCU and Serial PLL enabled 1 SPEN 0 MPEN NOTE When PRESC and BCLKDIV are modified at the same time, it must be performed in two programming steps: The first step is to change BCLKDIV, and then to change PRESC. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-12 Freescale Semiconductor Clocks, Power Management, and Reset Control 3.4.3 MPLL Control Register 0 (MPCTL0) The MCU and System PLL Control Register 0 (MPCTL0) is a 32-bit register that controls the operation of the MPLL. The MPCTL0 control bits are described in the following sections. Figure 3-5 shows the register and Table 3-7 provides the field descriptions. The following is the recommended procedure for changing the MPLL settings: 1. Program the desired values of PD, MFD, MFI, and MFN into the MPCTL0. 2. Set the MPLL_RESTART bit in the CSCR (it will self-clear). 3. New MPLL settings will take effect. 4. The new PLL clock output is valid upon the assertion of the DPLL lock flag. 0x1002_7004 (MPCTL0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R CPLM W Reset 0 0 PD 0 0 0 0 0 0 0 0 0 MFD 1 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 MFI MFN 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 Figure 3-5. MPLL Control Register 0 (MPCTL0) Table 3-7. MPLL Register 0 Field Descriptions Field 31 CPLM Description Phase Lock Mode. DPLL operates in the Frequency Only Lock mode (FOL) when CPLM bit is cleared, and in Frequency and Phase Lock mode (FPL) when the bit is set. FPL mode can be used for both integer and fractional multiplication factor, but phase skew elimination is accomplished only for integer MF. 0 FOL 1 FPL Reserved. This bit is reserved and should read 0. Predivider Factor. Defines the predivider factor (PD) applied to MPLL input frequency. PD is an integer between 0 and 15 (inclusive). PD is chosen to ensure that the resulting output frequency remains within the specified range. When a new value is written into PD, MPLL loses its lock; and after a time delay, MPLL re-locks. MPLL output is determined by Equation 3-1. 0000 0 0001 1 … 1111 15 30 29–26 PD MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-13 Clocks, Power Management, and Reset Control Table 3-7. MPLL Register 0 Field Descriptions (continued) Field 25–16 MFD Description Multiplication Factor (Denominator Part). Defines the denominator part of BRM value for MF. When a new value is written into the MFD bits, MPLL loses its lock; and after a time delay, MPLL re-locks. 000 Reserved 001 1 … 3FF 1023 Reserved. These bits are reserved and should read 0. Multiplication Factor (Integer). Defines the integer part of BRM value for MF. MFI is encoded so that MFI < 5 results in MFI = 5. When a new value is written into the MFI bits, PLL loses its lock: and after a time delay, PLL re-locks. VCO oscillates at a frequency determined by Equation 3-1. Where PD is the division factor of the predivider, MFI is the integer part of total MF, MFN is the numerator of the fractional part of MF, and MFD is its denominator part. MF is chosen to ensure that the resulting VCO output frequency remains within the specified range. 0000–01015 0110 6 ... 1111 15 Multiplication Factor (Numerator). Defines the numerator of BRM value for MF. The MFN is the only part in the DPLL Configuration that can be changed after the DPLL was locked without resetting the DPLL (on the fly).The bit 9 is the sign bit. When MFN is zero, the circuitry for fractional division is disabled to save power. 000 0 001 1 ... 1FE 510 1FF reserved ... 3FE –510 3FF Reservoir 15–14 13–10 MFI 9–0 MFN The recommended settings for MPLL and SPLL that produce the least amount of signal jitter are shown in Table 3-8. Table 3-8. Recommend Settings for Frequency Stability Ref Frequency 32.768 kHz 32.000 kHz 26 MHz Target Frequency 399 MHz 399 MHz 399 MHz MFI 5 6 7 MFN 469 3 35 MFD 495 21 51 PD 0 0 0 MPCTL0 Setting 0x01EF15D5 0x00211803 0x00331C23 Actual Calculated Frequency 399.000 398.998 399 3.4.4 MCU and System PLL Control Register 1 (MPCTL1) The MCU and System PLL Control Register 1 (MPCTL1) is a 32-bit register that directs the operation of the on-chip MCU PLL. Figure 3-6 shows the register and Table 3-9 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-14 Freescale Semiconductor Clocks, Power Management, and Reset Control 0x1002_7008 (MPCTL1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LF W Reset 1 0 0 0 0 0 0 0 0 BRMO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3-6. MCU and System PLL Control Register 1 (MPCTL1) Table 3-9. MCU and System PLL Control Register 1 Field Descriptions Field 31–16 15 LF Description Reserved. These bits are reserved and should read 0. Lock Flag. Indicates whether MPLL is locked or not. When set, MPLL clock output is valid. When cleared, MPLL clock output remains at logic high. 0 MPLL is not locked. 1 MPLL is locked. Reserved. These bits are reserved and should read 0. BRM Order. Controls the BRM order which affects jitter performance of MPLL. The first order BRM is used if a MF fractional part is more than 1/10 and less than 9/10. In other cases, second order BRM is used. BRMO bit is cleared by a hardware reset. A delay of reference cycles is required between two write accesses to BRMO. 0 BRM contains first order. 1 BRM contains second order. Reserved. These bits are reserved and should read 0. 14–7 6 BRMO 5–0 3.4.5 Programming the Serial Peripheral PLL (SPLL) One of the clock frequencies that the SPLL generates is for the USB OTG module (CLK60M). Its frequency is set to 60 MHz using the SPLL control registers assuming a default input clock frequency 32.768 MHz. This input clock frequency assumes a 32 kHz crystal input. The predivider/multiplier output depends on the input clock frequency. Recommended settings are provided for the Serial Peripheral PLL as shown in Table 3-10. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-15 Clocks, Power Management, and Reset Control Table 3-10. Serial PLL Multiplier Factor Ref Frequency 32.768 kHz 32.768 kHz 32 kHz 32 kHz 26 MHz 26 MHz Target Frequency 300 MHz 240 MHz 300 MHz 240 MHz 300 MHz 240 MHz MFI 8 7 9 7 11 9 MFN 111 9 25 83 7 3 MFD 117 58 160 255 12 12 PD 1 1 1 1 1 1 SPCTL0 Setting 0x0475206F 0x043A1C09 0x04A02419 0x04FF1C53 0x040C2C07 0x040C2403 Actual Calculated Frequency 299.99937 MHz 239.99950 MHz 300.00020 MHz 240 MHz 300 MHz 240 MHz 3.4.6 SPLL Control Register 0 (SPCTL0) The Serial Peripheral PLL Control Register 0 (SPCTL0) is a 32-bit register that controls the operation of the SPLL. The SPCTL0 control bits are described in the following sections. Figure 3-7 shows the register and Table 3-11 provides the field descriptions. The following is a procedure for changing the Serial Peripheral PLL settings: 1. Program the desired values of PD, MFD, MFI, and MFN into the SPCTL0. 2. Set the SPLL_RESTART bit in the CSCR (it will self-clear). 3. New PLL settings will take effect. 4. The new PLL clock output is valid upon the assertion of the DPLL lock flag. 0x1002_700C (SPCTL0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R CPLM W Reset 1 0 PD 0 0 0 0 1 0 0 1 1 MFD 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 MFI MFN 1 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 Figure 3-7. SPLL Control Register 0 (SPCTL0) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-16 Freescale Semiconductor Clocks, Power Management, and Reset Control Table 3-11. SPLL Control Register 0 Field Descriptions Field 31 CPLM Description Phase Lock Mode. DPLL operates in the Frequency Only Lock mode (FOL) when CPLM bit is cleared, and in Frequency and Phase Lock mode (FPL) when the bit is set. FPL mode can be used for both integer and fractional multiplication factor, but phase skew elimination is accomplished only for integer MF. 0 FOL 1 FPL Reserved. These bit is reserved and should read 0. Predivider Factor. Defines the predivider factor (PD) that is applied to the PLL input frequency. PD is an integer between 0 and 15 (inclusive). SPLL oscillates at a frequency determined by Equation 3-1. PD is chosen to ensure that the resulting VCO output frequency remains within the specified range. When a new value is written into the PD bits, SPLL loses its lock: and after a time delay, SPLL re-locks. 0000 0 0001 1 … 111115 Multiplication Factor (Denominator Part). Defines the denominator part of BRM value for the MF. When a new value is written into the MFD9 to MFD0 bits, PLL loses its lock: and after a time delay, PLL re-locks. 000 Reserved 001 1 … 3FF 1023 Reserved. These bits are reserved and should read 0. Multiplication Factor (Integer Part). Defines the integer part of BRM value for MF. MFI is decoded so that MFI < 5 results in MFI = 5. SPLL oscillates at a frequency determined by Equation 3-1. Where PD is the division factor of the predivider, MFI is the integer part of total MF, MFN is the numerator of fractional part of MF, and MFD is the denominator part of MF. MF is chosen to ensure that the resulting VCO output frequency remains within the specified range. When a new value is written into the MFI bits, SPLL loses its lock; and after a time delay, SPLL re-locks. 0000–01015 0110 6 ... 1111 15 Multiplication Factor (Numerator). Defines the numerator of BRM value for MF. The MFN is the only part in the DPLL Configuration that can be changed after the DPLL was locked without resetting the DPLL (on the fly).The bit 9 is the sign bit. When MFN is zero, the circuitry for fractional division is disabled to save power. 0x0000 0x0011 ... 0x1FE 510 0x1FF Reserved ... 0x3FE-510 0x3FF Reserved 30 29–26 PD 25–16 MFD 15–14 13–10 MFI 9–0 MFN 3.4.7 SPLL Control Register 1 (SPCTL1) The Serial PLL Control Register 1 (SPCTL1) is a 32-bit read/write register that directs the operation of the SPLL. The SPCTL1 control bits are described in this section. Figure 3-8 shows the register and Table 3-12 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-17 Clocks, Power Management, and Reset Control 0x1002_7010 (SPCTL1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LF W Reset 1 0 0 0 0 0 0 0 0 BRMO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3-8. SPLL Control Register 1 (SPCTL1) Table 3-12. Serial Peripheral PLL Control Register 1 Field Descriptions Field 31–16 15 LF Description Reserved. These bits are reserved and should read 0. Lock Flag. Indicates whether SPLL is locked or not. When set, SPLL clock output is valid. When cleared, SPLL clock output remains at logic high. 0 SPLL is not locked. 1 SPLL is locked. Reserved. These bits are reserved and should read 0. BRM Order. Controls the BRM order which affect SPLL jitter performance. The first order BRM is used if a MF fractional part is more than 1/10 and less than 9/10. In other cases, second order BRM is used. BRMO bit is cleared by a hardware reset. A delay of reference cycles is required between two write accesses to BRMO. 0 BRM contains first order. 1 BRM contains second order. Reserved. These bits are reserved and should read 0. 14–7 6 BRMO 5–0 3.4.8 Oscillator 26M Register This register is use to program the 26 MHz oscillator test modes as well as the gain control. Trimming of the oscillator is necessary only on initial power up; the trim may be stored in Flash for future reference. Figure 3-9 shows the register and Table 3-13 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-18 Freescale Semiconductor Clocks, Power Management, and Reset Control 0x1002_7014 (OSC26MCTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC26M_ PEAK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 AGC 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Figure 3-9. Oscillator 26M Control Register (OSC26MCTL) Table 3-13. Oscillator 26M Control Register Field Descriptions Field 31–18 Description Reserved. These bits are reserved and should read 0. 17–16 OSC26M_PEAK. These bits indicates the current amplitude status from the oscillator. OSC26M_PEAK 00 Amplitude in desired operating range 01 Amplitude too low; trim higher 10 Amplitude too high; trim lower 11 Invalid state 13–8 AGC 7–0 Reserved Bits 7–0 Automatic Gain Control. These bits sets the magnitude of crystal oscillations based on OSC26M_PEAK status. Optimum settings for these bits is determined using the algorithm in Section 3.4.8.1, “Adjusting the 26 MHz Oscillator Trim.” Reserved. These bits are reserved and should read 0. Reserved—These bits are reserved and should read 0. 3.4.8.1 Adjusting the 26 MHz Oscillator Trim To ensure a proper startup of the 26 MHz oscillator on power-up or system reset use the following steps to determine the optimum trim of the oscillator AGC. To ensure proper startup of 26 MHz oscillator on power-up or system reset, use Example 3-2 to determine optimum trim. This algorithm must be run to determine optimum AGC setting. Once done, software must read the trim value from external memory and write it to OSC26M_AGC[5:0]. Example 3-2. 26 MHz Oscillator Trim Programming Algorithm 1. At power up or system reset, OSC26M_AGC[5:0] bits in the OSC26MCTL register are reset to logic 1 (done in hardware, no software interaction required). 2. Read the peak amplitude value in bits OSC26M_PEAK[1:0] in the OSC26MCTL register. 3. If the amplitude is not in the desired range, adjust by decrementing the OSC26M_AGC[5:0] by 1 count. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-19 Clocks, Power Management, and Reset Control 4. 5. 6. 7. Wait at least 30.5 us (1 cycle of 32 kHz clock) for system to update OSC26M_PEAK bits. Repeat steps 2 to 4 until trimmed in desired range. Decrement 4 additional counts to provide a margin of error for temperature drift. Store trim value in an external memory—that is, Flash, for future use. It is suggested that the proceeding algorithm be run to determine the optimum AGC setting. Once this is done on power-up or system reset the software must read the trim value from the external memory and write it to the OSC26M_AGC[5:0]. 3.4.9 Peripheral Clock Divider Register 0 (PCDR0) The Peripheral Clock Divider Register 0 (PCDR0) contains the divider values for the peripheral clock dividers in the PLL Clock Controller. Peripherals in the i.MX27 device require special clock frequency which is divided down from the MPLL and the SPLL clock output. Each of these peripheral modules receive their clock input from the respective clock divider. These modules will still have the clock gating scheme as with other modules for power saving advantages. Figure 3-10 shows the register and Table 3-14 provides the field descriptions. Table 3-16 lists the clock sources associated with the i.MX27 peripherals given in the PCDR0. 0x1002_7018 (PCDR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R SSI2DIV W Reset 0 0 0 1 0 0 CLKO _EN 1 0 CLKO_DIV 0 0 0 0 SSI1DIV 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R H264DIV W Reset 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 NFCDIV MSHCDIV Figure 3-10. Peripheral Clock Divider Register 0 (PCDR0) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-20 Freescale Semiconductor Clocks, Power Management, and Reset Control Table 3-14. Peripheral Clock Divider Register 0 Field Descriptions Field 31–26 SSI2DIV Description SSI2 Baud Clock Divider. Contains 6-bit fractional divider that produces the clock for SSI2CLK clock signal for the peripherals. The value of the divider starts from 0. 02 1 2.5 23 .... 63 33.5 Note: Formula for all others: clkin / (2 + 0.5 * SSI2DIV) 25 Clock Out Enable. Enable bit for CLKO pin. CLKO_EN 0 disable CLKO output 1 enable CLKO output 24–22 Clock Out Divider. Contains the 3-bit divider that divides output clocks to CLKO pin. CLKO_DIV 000 Divide by 1 001 Divide by 2 … 111 Divide by 8 21–16 SSI1DIV SSI1 Baud Clock Divider. Contains 6-bit fractional divider that produces the clock for SSI1CLK clock signal for the peripherals. The value of the divider starts from 0. 02 1 2.5 23 .... 63 33.5 Note: Formula for all others: clkin / (2 + 0.5 * SSI1DIV) H264 Baud Clock Divider. Contains 6-bit fractional divider that produces the clock for H264CLK clock signal for the peripherals. The value of the divider starts from 0. 02 1 2.5 23 .... 63 33.5 Note: Formula for all others: clkin / (2 + 0.5 * H264DIV) NAND Flash Controller Clock Divider. Contains 4-bit divider that produces the clock for NFCCLK clock signal of the NAND Flash Controller. 0000 Divide by 1 0001 Divide by 2 … 1111 Divide by 16 15–10 H264DIV 9–6 NFCDIV 5–0 MSHC Clock Divider. Contains 6-bit divider that produces the clock for MSHCCLK clock signal of MSHC. MSHCDIV 000000 Divide by 1 000001 Divide by 2 … 111111 Divide by 64 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-21 Clocks, Power Management, and Reset Control 3.4.10 Peripheral Clock Divider Register 1 (PCDR1) The Peripheral Clock Divider Register 1 (PCDR1) contains the divider values for the peripheral clock dividers in the PLL Clock Controller. Peripherals in i.MX27 requires special clock frequency which is divided down from the MPLL and the SPLL clock output. Each of these peripheral modules receive their clock input from the respective clock divider. These modules will still have the clock gating scheme as with other modules for power saving advantages. Figure 3-11 shows the register and Table 3-15 provides the field descriptions. Table 3-16 lists the clock sources associated with the i.MX27 peripherals given in the PCDR1. 0x1002_701C (PCDR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 PERDIV4 0 0 PERDIV3 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 PERDIV2 0 0 PERDIV1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 Figure 3-11. Peripheral Clock Divider Register 1(PCDR1) Table 3-15. Peripheral Clock Divider Register 1 Field Descriptions Field 31–30 29–24 PERDIV4 These are reserved bits and should read 0. Peripheral Clock Divider 4. Contains 6-bit integer divider that produces PERCLK4 clock signal for CSI MCLK Clock. 000000 Divide by 1 000001 Divide by 2 … 111111 Divide by 64 These are reserved bits and should read 0. Peripheral Clock Divider 3. Contains 6-bit integer divider that produces PERCLK3 clock signal for LCDC Pixel Clock. 000000 Divide by 1 000001 Divide by 2 … 111111 Divide by 64 These are reserved bits and should read 0. Description 23–22 21–16 PERDIV3 15–14 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-22 Freescale Semiconductor Clocks, Power Management, and Reset Control Table 3-15. Peripheral Clock Divider Register 1 Field Descriptions (continued) Field 13–8 PERDIV2 Description Peripheral Clock Divider 2. Contains 6-bit integer divider that produces PERCLK2 clock signal for the peripheral 2set (CSPI and SDHC). 000000 Divide by 1 000001 Divide by 2 … 111111 Divide by 64 These are reserved bits and should read 0. Peripheral Clock Divider 1. Contains 6-bit integer divider that produces PERCLK1 clock signal for the peripheral 1 set (UART, GPT, PWM). 000000 Divide by 1 000001 Divide by 2 … 111111 Divide by 64 7–6 5–0 PERDIV1 Table 3-16. Clock Sources for i.MX27 Peripherals Clock Source SSI1CLK SSI2CLK H264CCLC Peripherals SSI1 SSI2 H264 Clock Source NFCCLK MSHCCLK Peripherals NFC MSHC 3.4.11 Peripheral Clock Control Register 0 (PCCR0) The Peripheral Clock Control Register 0 (PCCR0) provides additional power saving capabilities by controlling the clocks in the i.MX27 modules. It also controls the clock source for Bootstrap mode. The PCCR0 allows for gating of HCLK to modules or peripherals that access the AHB bus and perform AHB bus transfers and also allows for gating of the ipg clk (PERCLK) to specific peripherals. Figure 3-12 shows the register and Table 3-17 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-23 Clocks, Power Management, and Reset Control 0x1002_7020 (PCCR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 EMMA_EN CSPI1_EN CSPI2_EN CSPI3_EN GPT1_EN GPT2_EN GPT3_EN GPT4_EN GPT5_EN DMA_EN I2C1_EN I2C2_EN 0 1 FEC_EN W Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SAHARA_EN SDHC1_EN SDHC2_EN SDHC3_EN OWIRE_EN MSHC_EN LCDC_EN PWM_EN RTIC_EN SSI1_EN 0 W Reset 0 0 0 0 0 0 0 1 1 1 0 0 0 0 Figure 3-12. Peripheral Clock Control Register 0 (PCCR0) Table 3-17. Peripheral Clock Control Register 0 Field Descriptions Field 31 CSPI1_EN 30 CSPI2_EN 29 CSPI3_EN 28 DMA_EN 27 EMMA_EN 26 FEC_EN 25 GPIO_EN 24 GPT1_EN Description CSPI1 IPG Clock Enable. Enables/Disables IPG clock input to CSPI1 module. 0 CSPI1 IPG clock input is disabled. 1 CSPI1 IPG clock input is enabled. CSPI2 IPG Clock Enable. Enables/Disables IPG clock input to CSPI2 module. 0 CSPI2 IPG clock input is disabled. 1 CSPI2 IPG clock input is enabled. CSPI3 IPG Clock Enable. Enables/Disables IPG clock input to CSPI3 module. 0 CSPI3 IPG clock input is disabled. 1 CSPI3 IPG clock input is enabled. DMA IPG Clock Enable. Enables/Disables IPG clock input to DMA module. 0 DMA IPG clock input is disabled. 1 DMA IPG clock input is enabled. EMMA IPG Clock Enable. Enables/Disables IPG clock input to EMMA module. 0 EMMA IPG clock input is disabled. 1 EMMA IPG clock input is enabled. FEC IPG Clock Enable. Enables/Disables IPG clock input to FEC module. 0 FEC IPG clock input is disabled. 1 FEC IPG clock input is enabled. GPIO IPG Clock Enable. Enables/Disables IPG clock input to GPIO module. 0 GPIO IPG clock input is disabled. 1 GPIO IPG clock input is enabled. GPT1 IPG Clock Enable. Enables/Disables IPG clock input to GPT1 module. 0 GPT1 IPG clock input is disabled. 1 GPT1 IPG clock input is enabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-24 Freescale Semiconductor SSI2_EN 0 SCC_EN RTC_EN KPP_EN R 0 SLCDC_EN IIM_EN 1 0 R GPT6_EN GPIO_EN Clocks, Power Management, and Reset Control Table 3-17. Peripheral Clock Control Register 0 Field Descriptions (continued) Field 23 GPT2_EN 22 GPT3_EN 21 GPT4_EN 20 GPT5_EN 19 GPT6_EN 18 I2C1_EN 17 I2C2_EN 16 IIM_EN 15 KPP_EN 14 LCDC_EN 13 MSHC_EN 12 OWIRE_EN 11 PWM_EN 10 9 RTC_EN Description GPT2 IPG Clock Enable. Enables/Disables IPG clock input to GPT2 module. 0 GPT2 IPG clock input is disabled. 1 GPT2 IPG clock input is enabled. GPT3 IPG Clock Enable. Enables/Disables IPG clock input to GPT3 module. 0 GPT3 IPG clock input is disabled. 1 GPT3 IPG clock input is enabled. GPT4 IPG Clock Enable. Enables/Disables IPG clock input to GPT4 module. 0 GPT4 IPG clock input is disabled. 1 GPT4 IPG clock input is enabled. GPT5 IPG Clock Enable. Enables/Disables IPG clock input to GPT5 module. 0 GPT5 IPG clock input is disabled. 1 GPT5 IPG clock input is enabled. GPT6 IPG Clock Enable. Enables/Disables IPG clock input to GPT6 module. 0 GPT6 IPG clock input is disabled. 1 GPT6 IPG clock input is enabled. I2C1 IPG Clock Enable. Enables/Disables IPG clock input to I2C1 module. 0 I2C1 IPG clock input is disabled. 1 I2C1 IPG clock input is enabled. I2C2 IPG Clock Enable. Enables/Disables IPG clock input to I2C2 module. 0 I2C2 IPG clock input is disabled. 1 I2C2 IPG clock input is enabled. IIM IPG Clock Enable. Enables/Disables IPG clock input to IIM module. 0 IIM IPG clock input is disabled. 1 IIM IPG clock input is enabled. KPP IPG Clock Enable. Enables/Disables IPG clock input to KPP module. 0 KPP IPG clock input is disabled. 1 KPP IPG clock input is enabled. LCDC IPG Clock Enable. Enables/Disables IPG clock input to LCDC module. 0 LCDC IPG clock input is disabled. 1 LCDC IPG clock input is enabled. MSHC IPG Clock Enable. Enables/Disables IPG clock input to MSHC module. 0 MSHC IPG clock input is disabled. 1 MSHC IPG clock input is enabled. OWIRE IPG Clock Enable. Enables/Disables IPG clock input to OWIRE module. 0 OWIRE IPG clock input is disabled. 1 OWIRE IPG clock input is enabled. PWM IPG Clock Enable. Enables/Disables IPG clock input to PWM module. 0 PWM IPG clock input is disabled. 1 PWM IPG clock input is enabled. Reserved. This bit is reserved. RTC IPG Clock Enable. Enables/Disables IPG clock input to RTC module. 0 RTC IPG clock input is disabled. 1 RTC IPG clock input is enabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-25 Clocks, Power Management, and Reset Control Table 3-17. Peripheral Clock Control Register 0 Field Descriptions (continued) Field 8 RTIC_EN 7 SAHARA_EN 6 SCC_EN 5 SDHC1_EN 4 SDHC2_EN 3 SDHC3_EN 2 SLCDC_EN 1 SSI1_EN 0 SSI2_EN Description RTIC IPG Clock Enable. Enables/Disables IPG clock input to RTIC module. 0 RTIC IPG clock input is disabled. 1 RTIC IPG clock input is enabled. SAHARA IPG Clock Enable. Enables/Disables IPG clock input to SAHARA module. 0 SAHARA IPG clock input is disabled. 1 SAHARA IPG clock input is enabled. SCC IPG Clock Enable. Enables/Disables IPG clock input to SCC_EN module. 0 SCC_EN IPG clock input is disabled. 1 SCC_EN IPG clock input is enabled. SDHC1 IPG Clock Enable. Enables/Disables IPG clock input to SDHC1 module. 0 SDHC1 IPG clock input is disabled. 1 SDHC1 IPG clock input is enabled. SDHC2 IPG Clock Enable. Enables/Disables IPG clock input to SDHC2 module. 0 SDHC2 IPG clock input is disabled. 1 SDHC2 IPG clock input is enabled. SDHC3 IPG Clock Enable. Enables/Disables IPG clock input to SDHC3 module. 0 SDHC3 IPG clock input is disabled. 1 SDHC3 IPG clock input is enabled. SLCDC IPG Clock Enable. Enables/Disables IPG clock input to SLCDC module. 0 SLCDC IPG clock input is disabled. 1 SLCDC IPG clock input is enabled. SSI1 IPG Clock Enable. Enables/Disables IPG clock input to SSI1 module. 0 SSI1 IPG clock input is disabled. 1 SSI1 IPG clock input is enabled. SSI2 IPG Clock Enable. Enables/Disables IPG clock input to SSI2 module. 0 SSI2 IPG clock input is disabled. 1 SSI2 IPG clock input is enabled. 3.4.12 Peripheral Clock Control Register 1 (PCCR1) The Peripheral Clock Control Register 1 (PCCR1) provides additional power saving capabilities by controlling the clocks in the i.MX27 modules. It also controls the clock source for Bootstrap mode. The PCCR1 allows for gating of the ipg clk (PERCLK) to specific peripherals. Figure 3-13 shows the register and Table 3-18 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-26 Freescale Semiconductor Clocks, Power Management, and Reset Control 0x1002_7024 (PCCR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 HCLK_EMMA HCLK_BROM W Reset 1 1 1 1 1 1 1 1 0 1 0 0 1 0 HCLK_FEC 1 1 UART1_EN UART2_EN UART3_EN UART4_EN UART5_EN UART6_EN HCLK_EMI HCLK_ATA HCLK_CSI WDT_EN USB_EN R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SSI2+BAUDEN SSI1_BAUDEN W Reset 0 1 1 0 1 0 0 0 0 1 0 0 NFC_BAUDEN HCLK_SLCDC PERCLK1_EN PERCLK2_EN PERCLK3_EN PERCLK4_EN HCLK_LCDC HCLK_RTIC HCLK_USB R MSHC_BAUDEN HCLK_SAHARA H264_BAUDEN 0 1 0 0 Figure 3-13. Peripheral Clock Control Register 1(PCCR1) Table 3-18. Peripheral Clock Control Register 1 Field Descriptions Field 31 UART1_EN 30 UART2_EN 29 UART3_EN 28 UART4_EN 27 UART5_EN 26 UART6_EN 25 USB_EN 24 WDT_EN Description UART1 IPG Clock Enable. Enables/Disables IPG clock input to UART1 module. 0 UART1 IPG clock input is disabled. 1 UART1 IPG clock input is enabled. UART2 IPG Clock Enable. Enables/Disables IPG clock input to UART2 module. 0 UART2 IPG clock input is disabled. 1 UART2 IPG clock input is enabled. UART3 IPG Clock Enable. Enables/Disables IPG clock input to UART3 module. 0 UART3 IPG clock input is disabled. 1 UART3 IPG clock input is enabled. UART4 IPG Clock Enable. Enables/Disables IPG clock input to UART4 module. 0 UART4 IPG clock input is disabled. 1 UART4 IPG clock input is enabled. UART5 IPG Clock Enable. Enables/Disables IPG clock input to UART5 module. 0 UART5 IPG clock input is disabled. 1 UART5 IPG clock input is enabled. UART6 IPG Clock Enable. Enables/Disables IPG clock input to UART6 module. 0 UART6 IPG clock input is disabled. 1 UART6 IPG clock input is enabled. USB IPG Clock Enable. Enables/Disables IPG clock input to USB module. 0 USB IPG clock input is disabled. 1 USB IPG clock input is enabled. WDT IPG Clock Enable. Enables/Disables IPG clock input to WDT module. 0 WDT IPG clock input is disabled. 1 WDT IPG clock input is enabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-27 HCLK_H264 1 0 HCLK_DMA 0 0 Clocks, Power Management, and Reset Control Table 3-18. Peripheral Clock Control Register 1 Field Descriptions (continued) Field 23 HCLK_ATA 22 HCLK_BROM 21 HCLK_CSI 20 HCLK_DMA 19 HCLK_EMI 18 HCLK_EMMA 17 HCLK_FEC 16 HCLK_H264 15 HCLK_LCDC 14 HCLK_RTIC 13 HCLK_SAHARA 12 HCLK_SLCDC 11 HCLK_USB 10 PERCLK1_EN Description ATA AHB Clock Enable. Enables/Disables AHB clock input to ATA module. 0 ATA AHB clock input is disabled. 1 ATA AHB clock input is enabled. BROM AHB Clock Enable. Enables/Disables AHB clock input to BROM module. 0 BROM AHB clock input is disabled. 1 BROM AHB clock input is enabled. CSI AHB Clock Enable. Enables/Disables AHB clock input to CSI module. 0 CSI AHB clock input is disabled. 1 CSI AHB clock input is enabled. DMA AHB Clock Enable. Enables/Disables AHB clock input to DMA module. 0 DMA AHB clock input is disabled. 1 DMA AHB clock input is enabled. EMI AHB Clock Enable. Enables/Disables AHB clock input to EMI module. 0 EMI AHB clock input is disabled. 1 EMI AHB clock input is enabled. EMMA AHB Clock Enable. Enables/Disables AHB clock input to EMMA module. 0 EMMA AHB clock input is disabled. 1 EMMA AHB clock input is enabled. FEC AHB Clock Enable. Enables/Disables AHB clock input to FEC module. 0 FEC AHB clock input is disabled. 1 FEC AHB clock input is enabled. H264 AHB Clock Enable. Enables/Disables AHB clock input to H264 module. 0 H264 AHB clock input is disabled. 1 H264 AHB clock input is enabled. LCDC AHB Clock Enable. Enables/Disables AHB clock input to LCDC module. 0 LCDC AHB clock input is disabled. 1 LCDC AHB clock input is enabled. RTIC AHB Clock Enable. Enables/Disables AHB clock input to RTIC module. 0 RTIC AHB clock input is disabled. 1 RTIC AHB clock input is enabled. SAHARA AHB Clock Enable. Enables/Disables AHB clock input to SAHARA module. 0 SAHARA AHB clock input is disabled. 1 SAHARA AHB clock input is enabled. SLCDC AHB Clock Enable. Enables/Disables AHB clock input to SLCDC module. 0 SLCDC AHB clock input is disabled. 1 SLCDC AHB clock input is enabled. USB AHB Clock Enable. Enables/Disables AHB clock input to USB module. 0 USB AHB clock input is disabled. 1 USB AHB clock input is enabled. PERCLK1 Clock Enable. Enables/Disables Peripheral clock1. 0 Peripheral clock1 is disabled. 1 Peripheral clock1 is enabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-28 Freescale Semiconductor Clocks, Power Management, and Reset Control Table 3-18. Peripheral Clock Control Register 1 Field Descriptions (continued) Field 9 PERCLK2_EN 8 PERCLK3_EN 7 PERCLK4_EN 6 H264_BAUDEN 5 SSI1_BAUDEN 4 SSI2_BAUDEN 3 NFC_BAUDEN 2 MSHC_BAUDEN 1–0 Description PERCLK2 Clock Enable. Enables/Disables Peripheral clock2. 0 Peripheral clock2 is disabled. 1 Peripheral clock2 is enabled. PERCLK3 Clock Enable. Enables/Disables Peripheral clock3. 0 Peripheral clock3 is disabled. 1 Peripheral clock3 is enabled. PERCLK4 Clock Enable. Enables/Disables Peripheral clock4. 0 Peripheral clock4 is disabled. 1 Peripheral clock4 is enabled. H264 BAUD Clock Enable. Enables/Disables BAUD clock input to H264 module. 0 H264 BAUD clock input is disabled. 1 H264 BAUD clock input is enabled. SSI1 BAUD Clock Enable. Enables/Disables BAUD clock input to SSI1 module. 0 SSI1 BAUD clock input is disabled. 1 SSI1 BAUD clock input is enabled. SSI2 BAUD Clock Enable. Enables/Disables BAUD clock input to SSI2 module. 0 SSI2 BAUD clock input is disabled. 1 SSI2 BAUD clock input is enabled. NFC BAUD Clock Enable. Enables/Disables BAUD clock input to NFC module. 0 NFC BAUD clock input is disabled. 1 NFC BAUD clock input is enabled. MSHC BAUD Clock Enable. Enables/Disables BAUD clock input to MSHC module. 0 MSHC BAUD clock input is disabled. 1 MSHC BAUD clock input is enabled. Reserved. These bits are reserved and should read 0. 3.4.13 Clock Control Status Register (CCSR) The Clock Control Status Register (CCSR) provides information on the configuration of the Analog and Digital block. The clocks within the chip can also be monitored by the CLKO_SEL programming. Figure 3-14 shows the register and Table 3-19 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-29 Clocks, Power Management, and Reset Control 0x1002_7028 (CCSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 32K W _SR Reset 0 0 0 0 0 0 CLKMODE 0 0 0 CLKO_SEL 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Figure 3-14. Clock Control Status Register (CCSR) Table 3-19. Clock Control Status Register Field Descriptions Field 31–16 15 32K_SR Description Reserved. These bit are reserved and should read 0. 32K Status Register. It contains status information of 32 KHz clock. It is cleared to zero during the assertion of HARD_ASYNC_RESET signal. The sampled 32KHz clock phase is continuously registered into the bit upon the de-assertion of HARD_ASYNC_RESET signal. 0 CLK32 in low phase 1 CLK32 in high phase Reserved. These bits are reserved and should read 0. CLKMODE. Determines the configuration of FPM, OSC26M and DPLL on the chip. Its reset value depends on CLKMODE input signals. 00 DPLL, FPM, OSC26M bypassed 01 FPM bypassed. 10 FPM and OSC26M bypassed 11 FPM and DPLL in use (Default) 14–12 9–8 CLKMODE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-30 Freescale Semiconductor Clocks, Power Management, and Reset Control Table 3-19. Clock Control Status Register Field Descriptions (continued) Field 7–5 4–0 CLKO_SEL Description Reserved. These bits are reserved and should read 0. CLKO Select. Selects which clock signal source is the output of CLKO pin. 00000 CLK32 00001 PREMCLK 00010 CLK26M 00011 MPLL Reference CLK 00100 SPLL Reference CLK 00101 HCLK Source (MPLL 2x clock output / 3) 00110 SPLL CLK 00111 FCLK 01000 HCLK 01001 IPG_CLK 01010 PERCLK1 01011 PERCLK2 01100 PERCLK3 01101 PERCLK4 01110 SSI 1 Baud 01111 SSI 2 Baud 10000 NFC Baud 10001 MSHC_Baud 10010 H264 Baud 10011 CLK60M Always 10100 CLK32K Always 10101 CLK60M 10110 DPTC Reference Clock 3.4.14 Wakeup Guard Mode Control Register (WKGDCTL) The Wakeup Guard mode Control Register (WKGDCTL) provides the configuration of the Wakeup Guard mode. This is a write once only bit in order to be compatible with the watchdog behavior. After enable/disable, it will not be modifiable. When enabled, the battery detector external to the chip provides a glitch free signal through the TIN pin. Battery must be intact for the chip to wakeup from sleep. Figure 3-15 shows the register and Table 3-20 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-31 Clocks, Power Management, and Reset Control 0x1002_7034 (WKGDCTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User write-once 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKGD_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3-15. Wakeup Guard Mode Control Register (WKGDCTL) Table 3-20. Wakeup Guard Mode Control Register Field Descriptions Field 31–1 Description Reserved. These bits are reserved and should read 0. 0 Wakeup Guard Mode Enable. Enables /disables the wakeup guard logic. Write- once-only bit and can only be WKDG_EN cleared through system reset. Once enabled, battery indicator through TIN will be used to qualify the wakeup process. When battery is intact, that is, TIN=1, wakeup from sleep proceed as per normal. When WKGD_EN=1 and battery is removed, 32 kHz clock to watchdog module is gated off. Clock resumes when battery is back in place. 0 Wakeup Guard mode is disabled. 1 Wakeup Guard mode is enabled. 3.5 Functional Description of the Reset Module The reset module controls or distributes all of the system reset signals used by the i.MX27 processor. A simplified block diagram of the reset module is shown in Figure 3-16. The reset module generates two distinct events—a global reset and an ARM9 Platform reset. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-32 Freescale Semiconductor Clocks, Power Management, and Reset Control RESET_POR POR 300 ms Counter RESET_POR 7-cycle stretcher RESET_DRAM CLK32 POR_TIMEOUT (programmed values) CLK32 14-cycle stretcher CLK32 3-cycle hclk fuse_latch HRESET syn logic HARD_ASYNC_RESET syn logic GLOBAL_RESET CLK32 RESET WDOG_RESET stretcher Rising edge detector 4-cycle qualifier RSR IP bus EXT_RESET Figure 3-16. Reset Module Clock Diagram 3.5.1 Global Reset A global reset is produced by the simultaneous assertion of the following resets: • RESET_DRAM • HRESET • HARD_ASYNC_RESET • RESET_POR There is one source capable of generating a global reset: A low condition on the POR pin when the 32 kHz crystal oscillator is running. The HRESET and HARD_ASYNC_RESET are armed simultaneously; they remain in that state for 14 CLK32 cycles. RESET_DRAM is deasserted seven CLK32 cycles before HRESET and HARD_ASYNC_RESET are deasserted. The SDRAM executes the necessary self refresh operations during this time. The timing diagram in Figure 3-16 shows the relationship of the reset signal timings. See Table 3-21 for reset module signal and pin definitions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-33 Clocks, Power Management, and Reset Control The following signal conditions are not capable of generating a global reset, however their assertion will reset the ARM9 Platform: • An external qualified low condition on the RESET_IN pin • A low condition on WDOG_RESET Furthermore, these reset conditions will not reset the SDRAMC, Real Time Clock, WatchDog module, or allow a change in Boot mode—that is, changes made to BOOT[3:0] during these resets conditions will not take effect. Only the global reset is capable of this. The source of the last hardware reset can be determined in the watchdog status register. NOTE Due to the asynchronous nature of the RESET_IN signal, the time period required to qualify the signal may vary, and the HRESET timing relative to the rising edge of the RESET_IN is also affected. A RESET_IN signal shorter than three CLK32 cycles will not be qualified, a RESET_IN signal equal to or longer than four CLK32 cycles will always be qualified, and any period length that is more than three and less than four CLK32 cycles is undefined. POR is the reset signal for all the reset module flip-flops. For this reason, an external reset signal is qualified if it lasts more than four CLK32 cycles when POR is deasserted. During power on the user must ensure that POR stay asserted (low) long enough for the 32kHz crystal to stabilize. The time it takes for the crystal to stabilize depends upon on the crystal used. Consult the crystal’s specification for details about its stabilization timing. NOTE Refer to the i.MX27 Multimedia Applications Processor Data Sheet for power-up and power-down sequence requirements. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-34 Freescale Semiconductor Clocks, Power Management, and Reset Control POR RESET_POR 300 ms 7 cycles @ clk32 RESET_DRAM u 14 cycles @ clk32 n d e f i n e RESET_CPU RESET_SYS CLK32 HCLK d Figure 3-17. DRAM and Internal Reset Timing Diagram 3.5.2 ARM9 Platform Reset Any qualified global reset signal resets the ARM9 Platform and all related peripherals to their default state. After the internal reset is deasserted, the ARM9 processor begins fetching code from the internal bootstrap ROM or CS0 space. The memory location of the fetch depends on the configuration of the BOOT pins and the value of the TEST pin on the rising edge of the HRESET. Table 3-21. Reset Module Pin and Signal Descriptions Signal Name CLK32 POR Direction IN IN Signal Description 32 kHz Clock—A 32 kHz clock signal derived from the 32.768 KHz or 32.0 KHz crystal oscillator circuit in the PLL Clock Controller. Power-On Reset—An internal active Schmitt trigger signal from the POR pin. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. Reset—An external active low Schmitt trigger signal from the RESET_IN pin. When this signal goes active, all modules (except the SDRAMC, Real Time Clock, WatchDog, and the BOOT[3:0] signals) are reset. Watchdog Timer Reset—An active low signal generated by the watchdog timer when a time-out period has expired. Resets the same modules as RESET_IN. Hard Asynchronous Reset—An active low signal that resets all peripheral modules except the watchdog module’s status register. The rising edge of this signal is synchronous with IPG_CLK. RESET_IN IN WDOG_RESET HARD_ASYN_RESET IN OUT MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3-35 Clocks, Power Management, and Reset Control Table 3-21. Reset Module Pin and Signal Descriptions (continued) Signal Name HRESET Direction OUT Signal Description Hard Reset—An active low signal that resets the ARM9 Platform. This signal is deasserted during the low phase of HCLK. This signal also appears on the RESET_OUT pin of the i.MX27. DRAM Reset—An active low signal that resets the SDRAM controller. RESET_DRAM OUT MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 3-36 Freescale Semiconductor Chapter 4 System Control 4.1 Introduction This chapter describes the system control module of the i.MX27 microprocessor. The system control module enables system software to control, customize, or read the status of the following functions: • Chip ID • Multiplexing of I/O signals • I/O Drive Strength • I/O Pull Enable Control • Well Bias Control • System boot mode selection • DPTC Control 4.2 Memory Map and Register Definition The system control module includes one 32-bit Silicon ID and twenty-four user-accessible 32-bit registers. Table 4-1 summarizes these registers and their addresses. Table 4-1. Block Memory Map Address Register General Registers 0x1002_7800 (CID) 0x1002_7814 (FMCR) 0x1002_7818 (GPCR) 0x1002_781C (WBCR) 0x1002_7820 (DSCR1) 0x1002_7824 (DSCR2) 0x1002_7828 (DSCR3) 0x1002_782C (DSCR4) Chip ID Register Function Multiplexing Control Register Global Peripheral Control Register Well Bias Control Register Drive Strength Control Register 1 Drive Strength Control Register 2 Drive Strength Control Register 3 Drive Strength Control Register 4 R/W R/W R/W R/W R/W R/W R/W R/W 0x1882_181D 0xFFFF_FFCB 0x0000_0808 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 4.2.1/4-3 4.2.2/4-4 4.2.3/4-6 4.2.5/4-8 4.2.6/4-10 4.2.7/4-12 4.2.8/4-14 4.2.9/4-17 Access Reset Value Section/Page MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-1 System Control Table 4-1. Block Memory Map (continued) Address 0x1002_7830 (DSCR5) 0x1002_7834 (DSCR6) 0x1002_7838 (DSCR7) 0x1002_783C (DSCR8) 0x1002_7840 (DSCR9) 0x1002_7844 (DSCR10) 0x1002_7848 (DSCR11) 0x1002_784C (DSCR12) 0x1002_7850 (DSCR13) 0x1002_7854 (PSCR) 0x1002_7858 (PCSR) 0x1002_7860 (PMCR) 0x1002_7864 (DCVR0) 0x1002_7868 (DCVR1) 0x1002_786C (DCVR2) 0x1002_7870 (DCVR3) Register Drive Strength Control Register 5 Drive Strength Control Register 6 Drive Strength Control Register 7 Drive Strength Control Register 8 Drive Strength Control Register 9 Drive Strength Control Register 10 Drive Strength Control Register 11 Drive Strength Control Register 12 Drive Strength Control Register 13 Pull Strength Control Register Priority Control and Select Register Power Management Control Register DPTC Comparator Value Register 0 DPTC Comparator Value Register 1 DPTC Comparator Value Register 2 DPTC Comparator Value Register 3 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0003 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 4.2.10/4-18 4.2.11/4-21 4.2.12/4-23 4.2.13/4-25 4.2.14/4-28 4.2.15/4-30 4.2.16/4-32 4.2.17/4-34 4.2.18/4-36 4.2.19/4-38 4.2.20/4-40 4.2.21/4-41 4.2.22/4-43 4.2.23/4-43 4.2.24/4-44 4.2.25/4-45 The conventions in Figure 4-1 and Table 4-2 serve as a key for the register summary and individual register diagrams. Always reads 1 1 Always reads 0 0 Write 1 BIT Self-clear 0 R/W BIT Read- BIT Writebit BIT bit only bit only bit BIT to clear w1c N/A Figure 4-1. Key to Register Fields Table 4-2 provides a key for register figures and tables and the register summary. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-2 Freescale Semiconductor System Control Table 4-2. Register Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types R W R/W rwm w1c Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr) Reset Values 0 1 — u [signal_name] Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. Reset value is determined by polarity of indicated signal. 4.2.1 Chip ID Register (CID) The Chip ID register contains the chip identification number. Figure 4-2 shows the register and Table 4-3 provides its field descriptions. 0x1002_7800 (CID) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 15 VERSION ID 0 14 PART NUMBER 1 12 0 13 1 11 0 10 0 9 0 8 1 7 0 6 0 5 0 4 0 3 0 2 1 1 0 0 R W Reset 0 PART NUMBER 0 0 1 0 0 0 0 MANUFACTURER ID 0 0 0 1 1 1 0 1 Figure 4-2. Chip ID Register (CID) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-3 System Control Table 4-3. Chip ID Register Field Descriptions Field 31–28 VERSION ID 27–12 PART NUMBER Description VERSION ID. This field contains the 4-bit version ID number. PART NUMBER. This field contains the 16-bit part number of the chip. 11–0 MANUFACTURER ID. This field contains the 12-bit manufacturer ID MANUFACTURER ID number of the chip. 4.2.2 Function Multiplexing Control Register (FMCR) The FMCR controls the multiplexing of the signal lines shared by the SLCDC module, UART module, and Keypad module as well as the SDRAM chip select lines. The FMCR also allows control or indicates the boot status of the NAND Flash page size and data port size. Figure 4-3 shows the register and Table 4-4 provides its field descriptions. 0x1002_7814 (FMCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 UART4_RXD_CTL KP_ROW7_CTL 1 1 W Reset 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 PC_READY_CTL PC_BVD1_CTL PC_BVD2_CTL NF_16BIT_SEL PC_VS1_CTL PC_VS2_CTL R W 1 PC_WAIT_B_CTL 1 IOIS16_CTL 1 NF_FMS 1 SLCDC_SEL SDCS1_SEL SDCS0_SEL 1 Reset 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 Figure 4-3. Function Multiplexing Control Register (FMCR) Table 4-4. Function Multiplexing Control Register Description Field 31–26 25 UART4_RXD_CTL Description Reserved. These bits are reserved and should read 1. UART4 RXD Control. When set, the alternate signal of USBH1_RXDP (PB31) is input to RXD of UART4. When 0, the USBH1_TXDP (PB29) GPIO’s AOUT is input to RXD of UART4. With either setting, the user must also ensure that the proper GPIO registers have been programmed to select the desired multiplexing. 0 The USBH1_TXDP (PB29) GPIO’s AOUT is input to RXD of UART4. 1 The alternate signal of USBH1_RXDP (PB31) is input to RXD of UART4. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-4 Freescale Semiconductor KP_ROW6_CTL 1 0 KP_COL6_CTL R 1 1 1 1 1 1 UART4_RTS_CTL 1 1 1 1 1 System Control Table 4-4. Function Multiplexing Control Register Description (continued) Field 24 UART4_RTS_CTL Description UART4 RTS Control. When set, the alternate signal of USBH1_FS (PB26) is input to RTS of UART4. When 0, the USBH1_RXDP (PB31) GPIO’s AOUT is input to RTS of UART4. With either setting, the user must also ensure that the proper GPIO registers have been programmed to select the desired multiplexing. 0 The USBH1_RXDP (PB31) GPIO’s AOUT is input to RTS of UART4. 1 The alternate signal of USBH1_FS (PB26) is input to RTS of UART4. Reserved. These bits are reserved and should read 1. Keypad Column 6 Control. When set, the alternate signal of UART2_TXD (PE6) is input to column 6 of keypad. When 0, the alternate signal of TEST_WB2 (PE0) is input to column 6 of keypad. With either setting, the user must also ensure that the proper GPIO registers have been programmed to select the desired multiplexing. 0 The alternate signal of TEST_WB2 (PE0) is input to column 6 of keypad. 1 The alternate signal of UART2_TXD (PE6) is input to column 6 of keypad. Keypad Row 7 Control. When set, the alternate signal of UART2_RTS (PE4) is input to row 7of keypad. When 0, the alternate signal of TEST_WB0 (PE2) is input to row 7 of keypad. With either setting, the user must also ensure that the proper GPIO registers have been programmed to select the desired multiplexing. 0 The alternate signal of TEST_WB0 (PE2) is input to row 7 of keypad. 1 The alternate signal of UART2_RTS (PE4) is input to row 7of keypad. Keypad Row 6 Control. When set, the alternate signal of UART2_RXD (PE7) is input to row 6 of keypad. When 0, the alternate signal of TEST_WB1 (PE1) is input to row 6 of keypad. With either setting, the user must also ensure that the proper GPIO registers have been programmed to select the desired multiplexing. 0 The alternate signal of TEST_WB1 (PE1) is input to row 6 of keypad. 1 The alternate signal of UART2_RXD (PE7) is input to row 6 of keypad. Reserved. These bits are reserved and should read 1. PC_WAIT_B Control. When set, signal pc_wait_b of PCMCIA is input from PC_WAIT_B. When 0, it is input from BOUT of GPIO PORT C[31]. 0 The signal pc_wait_b of PCMCIA is input from BOUT of GPIO PORT C[31]. 1 The signal pc_wait_b of PCMCIA is input from PC_WAIT_B. PC_READY Control. When set, signal pc_ready of PCMCIA is input from PC_READY. When 0, it is input from BOUT of GPIO PORT C[30]. 0 The signal pc_ready of PCMCIA is input from BOUT of GPIO PORT C[30]. 1 The signal pc_ready of PCMCIA is input from PC_READY. PC_VS1 Control. When set, signal pc_vs1 of PCMCIA is input from PC_VS1. When 0, it is input from BOUT of GPIO PORT C[29]. 0 The signal pc_vs1 of PCMCIA is input from BOUT of GPIO PORT C[29]. 1 The signal pc_vs1 of PCMCIA is input from PC_VS1. PC_VS2 Control. When set, signal pc_vs2 of PCMCIA is input from PC_VS2. When 0, it is input from BOUT of GPIO PORT C[28]. 0 The signal pc_vs2 of PCMCIA is input from BOUT of GPIO PORT C[28]. 1 The signal pc_vs2 of PCMCIA is input from PC_VS2. PC_BVD1 Control. When set, signal pc_bvd1 of PCMCIA is input from PC_BVD1. When 0, it is input from BOUT of GPIO PORT C[19]. 0 The signal pc_bvd1 of PCMCIA is input from BOUT of GPIO PORT C[19]. 1 The signal pc_bvd1 of PCMCIA is input from PC_BVD1. 23–19 18 KP_COL6_CTL 17 KP_ROW7_CTL 16 KP_ROW6_CTL 15 14 PC_WAIT_B_CTL 13 PC_READY_CTL 12 PC_VS1_CTL 11 PC_VS2_CTL 10 PC_BVD1_CTL MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-5 System Control Table 4-4. Function Multiplexing Control Register Description (continued) Field 9 PC_BVD2_CTL Description PC_BVD2 Control. When set, signal PC_BVD2 of PCMCIA is input from PC_BVD2. When 0, it is input from BOUT of GPIO PORT C[18]. 0 The signal pc_bvd2 of PCMCIA is input from BOUT of GPIO PORT C[18]. 1 The signal pc_bvd2 of PCMCIA is input from PC_BVD2. IOIS16 Control. When set, signal iois16 of PCMCIA is input from IOIS16. When 0, it is input from BOUT of GPIO PORT C[17]. 0 The signal iois16 of PCMCIA is input from BOUT of GPIO PORT C[17]. 1 The signal iois16 of PCMCIA is input from IOIS16. Reserved. These bits are reserved and should read 1. Flash Memory Select. When Boot[3:0] = 0010 or 0011, the NF_FMS will be set, otherwise it will be 0. After boot up, this bit is user programmable. 0 NAND Flash with 512B page size (64Mb/128Mb/256Mb/512Mbyte/ 1Gbyte DDP) 1 NAND Flash with 2 Kbyte page size (1Gbyte/2Gbyte DDP/2Gbyte) Note: DDP means Double Density Package. NAND Flash 16-bit Select. Selects 16-bit NF operation. Setting this bit forces the NAND Flash into 16-bit operation and the NAND Flash upper data is available to the pins. Clearing this bit forces the NF to 8-bit operation and the A[25:21]signals become the function pins. The muxing is done in the EMI module, not I/O MUX module. During system boot up, if the BOOT[3:0] input pins are configured to select 16-bit mode, this NF_16BIT_SEL bit is set. 0 NAND Flash 8-bit operation 1 NAND Flash 16-bit operation Reserved. This bit is reserved and should read 0. SLCDC Select. Selects whether a BaseBand chip (BB) or the i.MX27 processor drives the SLCDC display port in serial mode. 0 On Chip SLCDC drives the SLCDC port. 1 BB can write directly to the SLCDC port. SDRAM Chip Select. Selects the function of the CS3/CSD1 pin. 0 CS3 is selected. 1 CSD1 is selected. SDRAM Chip Select. Selects the function of the CS2/CSD0 pin. 0 CS2 is selected. 1 CSD0 is selected. 8 IOIS16_CTL 7–6 5 NF_FMS 4 NF_16BIT_SEL 3 2 SLCDC_SEL 1 SDCS1_SEL 0 SDCS0_SEL 4.2.3 Global Peripheral Control Register (GPCR) The Global Peripheral Control Register (GPCR) displays the current boot mode of the i.MX27 device. The clock gating to the processor’s modules is also controlled by this register. Figure 4-4 shows the register and Table 4-5 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-6 Freescale Semiconductor System Control 0x1002_7818 (GPCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 BOOT 0 3 0 2 0 1 0 0 R W 0 0 0 0 USB_ PP_ DMA_ ETM9 Burst Burst Burst _PAD _Over _Over _Over _EN ride ride ride 1 0 0 0 0 0 0 0 CLOC CLK_ K_GA DDR_ DDR_ DDR_ TING_ MODE INPUT MODE EN 1 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 4-4. Global Peripheral Control Register (GPCR) Table 4-5. Global Peripheral Control Register Descriptions Field 31–20 19–16 BOOT Description Reserved. These bits are reserved and should read 0. Boot Mode. These are 4-bit system boot mode for the i.MX27 device. 0000 Bootstrap from UART/USB 0001 Reserved 0010 8-bit NAND Flash (2 Kbyte per page) 0011 16-bit Nand Flash (2 Kbyte per page) 0100 16-bit Nand Flash (512 bytes per page) 0101 16-bit CS0 0110 32-bit CS0 0111 8 bit Nand Flash (512 bytes per page) 1xxx Reserved Reserved. These bits are reserved and should read 0. ETM9 Pad Enable. When this bit is set, pads for ETM9 are enabled. 0 Disable ETM9 pads 1 Enable ETM9 pads 15–12 11 ETM9_PAD_EN 10 USB Burst Override Control. When this bit is set, the burst type of USB will be forced to INCR8. USB_Burst_Override 0 Bypass. The burst type will not be forced. 1 Burst type of USB is INCR8 9 PP_Burst_Override EMMA PP Burst Override Control. When this bit is set, the burst type of EMMA PP will be forced to INCR4 or INCR8. 0 Bypass. The burst type will not be forced. 1 Burst type of EMMA PP is INCR4 or INCR8. 8 DMA Burst Override Control. When this bit is set, the burst type of DMA will be forced to INCR4 DMA_Burst_Override or INCR8. 0 Bypass. The burst type will not be forced. 1 Burst type of DMA is INCR4 or INCR8. 7–4 Reserved. These bits are reserved and should read 0. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-7 System Control Table 4-5. Global Peripheral Control Register Descriptions (continued) Field Description 3 Clock Gating Enable. When set to 1, the peripheral register access clocks are gated by the AIPI CLOCK_GATING_EN modules. For example, when there is a register read or write access to the peripherals of AIPI1, the ipg_clk_s1 clock will be running, otherwise if no access is taking place the clock will shut off and when there is a register read or write access to the peripherals of AIPI2. The clock is running, otherwise if no access is taking place the clock shuts off. When this bit is cleared to 0 then the AIPI clocks become a continuous clock, regardless of peripheral accesses. It is recommended for maximum power savings to ensure this bit is set to 1. 2 DDR_MODE DDR Drive Strength Control. used to select DDR drive strength of all DDR pads except the SDCLK pad. 0 Drive strength is selected by associated fields in the DSCRx registers. 1 Drive strength of about 20 mA, as defined in SSTL_18 CLK DDR MODE. used to select DDR drive strength of SDCLK pad. 0 Drive strength is selected by associated fields in the DSCR8 registers. 1 Drive strength of about 20 mA, as defined in SSTL_18 DDR_INPUT. Used to force input mode of DDR pads to CMOS input mode. 0 No force on input mode of DDR pads 1 DDR pads will be forced to CMOS input mode. 1 CLK_DDR_MODE 0 DDR_INPUT 4.2.4 Well Bias System The i.MX27 processor employs an innovative system feature to help reduce leakage current called Well Biasing. The Well Bias System reduces the leakage current of the QVDDx sub-system during low-power mode by increasing the threshold voltage of the QVDDx sub-system transistors. The i.MX27 contains two Well Biasing System, one for ARM core logic and one for EMI module. The following section describes how to enable and take advantage of this power saving feature. 4.2.5 Well Bias Control Register (WBCR) The Well Bias Control Register (WBCR) allows the user to enable the A926P Well Biasing System and EMI Well Biasing System. The default setting is both Well Biasing Systems are disabled. A926P Well Biasing System can operate under both Doze mode and Sleep mode, while EMI Well Biasing System can operate under Sleep mode only. To enable Well Biasing Systems and take advantage of this power saving feature, CRM_WBFA or CRM_WBFA_EMI bit must be set to 1. Figure 4-5 shows the register and Table 4-6 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-8 Freescale Semiconductor System Control 0x1002_781C (WBCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 CRM_SPA_EMI 0 11 0 0 8 0 0 6 0 0 5 0 0 4 CRM_WBFA CRM_WBM_ _EMI EMI 0 3 0 10 0 9 0 7 0 2 0 1 0 0 R W Reset 0 0 0 0 0 0 0 0 0 CRM_SPA 0 0 0 0 0 0 0 0 0 0 0 CRM_WBFA 0 0 CRM_WBM 0 0 Figure 4-5. Well Bias Control Register (WBCR) Table 4-6. Well Bias Control Register Field Descriptions Field 31–28 27–26 CRM_SPA_EMI Description Reserved. These bits are reserved and should read 0. EMI PWELL Set Point Adjust. Describe the configuration of the EMI PWELL bias circuit’s set point or regulation level. 00 Minimum Back Bias applied to the Pwells. 01 Decreased Back Bias applied to the Pwells. 10 Moderate Back Bias applied to the Pwells. 11 Increased Back Bias applied to the Pwells. EMI NWELL Set Point Adjust. Describe the configuration of the EMI NWELL bias circuit’s set point or regulation level. 00 Minimum Back Bias applied to the Nwells. 01 Decreased Back Bias applied to the Nwells. 10 Moderate Back Bias applied to the Nwells. 11 Increased Back Bias applied to the Nwells. Reserved. These bits are reserved and should read 0. Well Bias Frequency Adjust. For optimal power savings, the user should set this bit to 1 when EMI Well Bias is enabled. 0 Standard 1 Adjusted Suggested setting for optimal power savings when Well Bias is enabled. Note: This bit has no effect when Well Bias is disabled. CRM_WBM. Enables or disables EMI Well Bias System during Sleep mode. To enable Well Bias during Sleep mode, these bits must be set to 001. To disable Well Bias, these bits must be set to 000. All other bit settings are reserved. 000 Well Bias not applied 001 Well Bias @ Sleep 010–111Well Bias not applied Reserved. These bits are reserved and should read 0. A926P PWELL Set Point Adjust. Describes the configuration of the A926P PWELL bias circuit’s set point or regulation level. 00 Minimum Back Bias applied to the Pwells. 01 Decreased Back Bias applied to the Pwells. 10 Moderate Back Bias applied to the Pwells. 11 Increased Back Bias applied to the Pwells. 25–24 CRM_SPA_EMI 23–20 19 CRM_WBFA_EMI 18–16 CRM_WBM_EMI 15–12 11–10 CRM_SPA MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-9 System Control Table 4-6. Well Bias Control Register Field Descriptions (continued) Field 9–8 CRM_SPA Description A926P NWELL Set Point Adjust. Describe the configuration of the A926P Nwell bias circuit’s set point or regulation level. 00 Minimum Back Bias applied to the Nwells. 01 Decreased Back Bias applied to the Nwells. 10 Moderate Back Bias applied to the Nwells. 11 Increased Back Bias applied to the Nwells. Reserved. These bits are reserved and should read 0. Well Bias Frequency Adjust. For optimal power savings, the user should set this bit to 1 when A926P Well Bias is enabled. 0 Standard. 1 Adjusted Suggested setting for optimal power savings when Well Bias is enabled This bit has no effect when Well Bias is disabled. CRM_WBM. Controls when the A926P well bias will be applied.Enables or disables Well Bias System during Sleep mode. To enable Well Bias during Sleep mode, these bits must be set to 001. To disable Well Bias, these bits must be set to 000. All other bit settings are reserved. 000 Well Bias not applied 001 Well Bias @ Sleep 010 Well Bias @ Sleep and DOZE 100–111Well Bias not applied 7–4 3 CRM_WBFA 2–0 CRM_WBM 4.2.6 Drive Strength Control Register 1 (DSCR1) The Drive Strength Control Register 1 (DSCR1) controls the driving force parameters of all slow I/O signals in the i.MX27 device. Figure 4-6 shows the register and Table 4-7 provides its field descriptions. 0x1002_7820 (DSCR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 DS_SLOW11 DS_SLOW10 DS_SLOW9 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_SLOW8 DS_SLOW7 DS_SLOW6 DS_SLOW5 DS_SLOW4 DS_SLOW3 DS_SLOW2 DS_SLOW1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-6. Drive Strength Control Register (DSCR1) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-10 Freescale Semiconductor System Control Table 4-7. Drive Strength Control Register 1 Field Description Field 31–22 21–20 DS_SLOW11 Description Reserved. These bits are reserved and should read 0. Drive Strength Slow I/O. Controls the driving strength of slow I/O group 11. (DVS_PMIC) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 10. (SDHC1 and CSPI3) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 9. (JTAG) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 8. (PWM, KPP, UART1, UART2, UART3, and RESET_OUT_B) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 7. (CSPI1 and CSPI2) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 6. (SSI1, SSI2, SAP, SSI3, GPT4, and GPT5) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 5. (GPT1, I2C1, and I2C2) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 4. (USBH1, UART4, and USBG) 00 Normal 01 High 10 Max high 11 Max high 19–18 DS_SLOW10 17–16 DS_SLOW9 15–14 DS_SLOW8 13–12 DS_SLOW7 11–10 DS_SLOW6 9–8 DS_SLOW5 7–6 DS_SLOW4 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-11 System Control Table 4-7. Drive Strength Control Register 1 Field Description (continued) Field 5–4 DS_SLOW3 Description Drive Strength Slow I/O. Controls the driving strength of slow I/O group 3. (CSI, UART5, and UART6) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 2.(SDHC2 and MSHC) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Slow I/O. Controls the driving strength of slow I/O group 1. (LCDC) 00 Normal 01 High 10 Max high 11 Max high 3–2 DS_SLOW2 1–0 DS_SLOW1 4.2.7 Drive Strength Control Register 2 (DSCR2) The Drive Strength Control Register 2 (DSCR2) controls the driving force parameters of the fast I/O signals in the i.MX27 processor. Figure 4-7 shows the register and Table 4-8 provides its field descriptions. 0x1002_7824 (DSCR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset DS_FAST16 DS_FAST15 DS_FAST14 DS_FAST13 DS_FAST12 DS_FAST11 DS_FAST10 0 15 DS_FAST9 0 1 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 0 R W Reset DS_FAST8 0 0 DS_FAST7 0 0 DS_FAST6 0 0 DS_FAST5 0 0 DS_FAST4 0 0 DS_FAST3 0 0 DS_FAST2 0 0 DS_FAST1 0 0 Figure 4-7. Drive Strength Control Register 2 (DSCR2) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-12 Freescale Semiconductor System Control Table 4-8. Drive Strength Control Register 2 Field Descriptions Field 31–30 DS_FAST16 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 16 (D15). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 15 (D14). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 14 (D13). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 13 (D12). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 12 (D11). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 11(D10). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 10 (D9). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 9 (D8). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 8 (D7). 00 Normal 01 High 10 Max high 11 Max high 29–28 DS_FAST15 27–26 DS_FAST14 25–24 DS_FAST13 23–22 DS_FAST12 21–20 DS_FAST11 19–18 DS_FAST10 17–16 DS_FAST9 15–14 DS_FAST8 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-13 System Control Table 4-8. Drive Strength Control Register 2 Field Descriptions (continued) Field 13–12 DS_FAST7 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 7 (D6). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 6 (D5). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 5 (D4). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 4 (D3). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 3 (D2). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 2 (D1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 1 (D0). 00 Normal 01 High 10 Max high 11 Max high 11–10 DS_FAST6 9–8 DS_FAST5 7–6 DS_FAST4 5–4 DS_FAST3 3–2 DS_FAST2 1–0 DS_FAST1 4.2.8 Drive Strength Control Register 3 The Drive Strength Control Register 3 (DSCR3) controls the driving force parameters of the fast I/O signals in the i.MX27. Figure 4-8 shows the register and Table 4-9 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-14 Freescale Semiconductor System Control 0x1002_7828 (DSCR3) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset DS_FAST32 DS_FAST31 DS_FAST30 DS_FAST29 DS_FAST28 DS_FAST27 DS_FAST26 DS_FAST25 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST24 DS_FAST23 DS_FAST22 DS_FAST21 DS_FAST20 DS_FAST19 DS_FAST18 DS_FAST17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-8. Drive Strength Control Register 3 (DSCR3) Table 4-9. Drive Strength Control Register 3 Field Descriptions Field 31–30 DS_FAST32 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 32 (A15). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 31 (A14). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 30 (A13). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 29 (A12). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 28 (A11). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 27 (A10). 00 Normal 01 High 10 Max high 11 Max high 29–28 DS_FAST31 27–26 DS_FAST30 25–24 DS_FAST29 23–22 DS_FAST28 21–20 DS_FAST27 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-15 System Control Table 4-9. Drive Strength Control Register 3 Field Descriptions (continued) Field 19–18 DS_FAST26 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 26 (A9). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 25 (A8). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 24 (A7). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 23 (A6). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 22 (A5). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 21 (A4). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 20 (A3). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 19 (A2). 00 Normal 01 High 10 Max high 11 Max high 17–16 DS_FAST25 15–14 DS_FAST24 13–12 DS_FAST23 11–10 DS_FAST22 9–8 DS_FAST21 7–6 DS_FAST20 5–4 DS_FAST19 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-16 Freescale Semiconductor System Control Table 4-9. Drive Strength Control Register 3 Field Descriptions (continued) Field 3–2 DS_FAST18 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 18 (A1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 17 (A0). 00 Normal 01 High 10 Max high 11 Max high 1–0 DS_FAST17 4.2.9 Drive Strength Control Register 4 The Drive Strength Control Register 4 (DSCR4) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-9 shows the register and Table 4-10 provides its field descriptions. 0x1002_782C (DSCR4) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 DS_FAST42 DS_FAST41 0 3 0 2 0 1 0 0 R W Reset DS_FAST40 DS_FAST39 DS_FAST38 DS_FAST37 DS_FAST36 DS_FAST35 DS_FAST34 DS_FAST33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-9. Drive Strength Control Register 4 (DSCR4) Table 4-10. Drive Strength Control Register 4 Field Descriptions Field 31–20 19–18 DS_FAST42 Description Reserved. These bits are reserved and should read 0. Drive Strength Fast I/O. Controls the driving strength of fast I/O group 42 (A25). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 41 (A24). 00 Normal 01 High 10 Max high 11 Max high 17–16 DS_FAST41 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-17 System Control Table 4-10. Drive Strength Control Register 4 Field Descriptions (continued) Field 15–14 DS_FAST40 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 40 (A23). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 39 (A22). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 38 (A21). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 37 (A20). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 36 (A19). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 35 (A18). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 34 (A17). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 33 (A16). 00 Normal 01 High 10 Max high 11 Max high 13–12 DS_FAST39 11–10 DS_FAST38 9–8 DS_FAST37 7–6 DS_FAST36 5–4 DS_FAST35 3–2 DS_FAST34 1–0 DS_FAST33 4.2.10 Drive Strength Control Register 5 The Drive Strength Control Register 5 (DSCR5) controls the driving force parameters of the fast I/O signals in the i.MX27 processor. Figure 4-10 shows the register and Table 4-11 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-18 Freescale Semiconductor System Control 0x1002_7830 (DSCR5) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset DS_FAST64 DS_FAST63 DS_FAST62 DS_FAST61 DS_FAST60 DS_FAST59 DS_FAST58 DS_FAST57 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST56 DS_FAST55 DS_FAST54 DS_FAST53 DS_FAST52 DS_FAST51 DS_FAST50 DS_FAST49 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-10. Drive Strength Control Register 5 (DSCR5) Table 4-11. Drive Strength Control Register 5 Field Descriptions Field 31–30 DS_FAST64 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 64 (SD15). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 63 (SD14). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 62 (SD13). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 61 (SD12). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 60 (SD11). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 59 (SD10). 00 Normal 01 High 10 Max high 11 Max high 29–28 DS_FAST63 27–26 DS_FAST62 25–24 DS_FAST61 23–22 DS_FAST60 21–20 DS_FAST59 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-19 System Control Table 4-11. Drive Strength Control Register 5 Field Descriptions (continued) Field 19–18 DS_FAST58 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 58 (SD9). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 57 (SD8). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 56 (SD7). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 55 (SD6). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 54 (SD5). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 53 (SD4). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 52 (SD3). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 51 (SD2). 00 Normal 01 High 10 Max high 11 Max high 17–16 DS_FAST57 15–14 DS_FAST56 13–12 DS_FAST55 11–10 DS_FAST54 9–8 DS_FAST53 7–6 DS_FAST52 5–4 DS_FAST51 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-20 Freescale Semiconductor System Control Table 4-11. Drive Strength Control Register 5 Field Descriptions (continued) Field 3–2 DS_FAST50 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 50 (SD1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 49 (SD0). 00 Normal 01 High 10 Max high 11 Max high 1–0 DS_FAST49 4.2.11 Drive Strength Control Register 6 The Drive Strength Control Register 6 (DSCR6) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-11 shows the register and Table 4-12 provides its field descriptions. 0x1002_7834 (DSCR6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset DS_FAST80 DS_FAST79 DS_FAST78 DS_FAST77 DS_FAST76 DS_FAST75 DS_FAST74 DS_FAST73 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST72 DS_FAST71 DS_FAST70 DS_FAST69 DS_FAST68 DS_FAST67 DS_FAST66 DS_FAST65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-11. Drive Strength Control Register 6 (DSCR6) Table 4-12. Drive Strength Control Register 6 Field Descriptions Field 31–30 DS_FAST80 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 80 (SD31). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 79 (SD30). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 78 (SD29). 00 Normal 01 High 10 Max high 11 Max high 29–28 DS_FAST79 27–26 DS_FAST78 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-21 System Control Table 4-12. Drive Strength Control Register 6 Field Descriptions (continued) Field 25–24 DS_FAST77 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 77 (SD28). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 76 (SD27). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 75 (SD26). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 74 (SD25). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 73 (SD24). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 72 (SD23). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 71 (SD22). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 70 (SD21). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 69 (SD20). 00 Normal 01 High 10 Max high 11 Max high 23–22 DS_FAST7 21–20 DS_FAST75 19–18 DS_FAST74 17–16 DS_FAST73 15–14 DS_FAST72 13–12 DS_FAST71 11–10 DS_FAST70 9–8 DS_FAST69 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-22 Freescale Semiconductor System Control Table 4-12. Drive Strength Control Register 6 Field Descriptions (continued) Field 7–6 DS_FAST68 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 68 (SD19). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 67 (SD18). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 66 (SD17). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 65 (SD16). 00 Normal 01 High 10 Max high 11 Max high 5–4 DS_FAST67 3–2 DS_FAST66 1–0 DS_FAST65 4.2.12 Drive Strength Control Register 7 The Drive Strength Control Register 7 (DSCR7) controls the driving force parameters of the fast I/O signals in the i.MX27 processor. Figure 4-12 shows the register and Table 4-13 provides its field descriptions. 0x1002_7838 (DSCR7) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 DS_FAST95 DS_FAST94 DS_FAST93 DS_FAST92 DS_FAST91 DS_FAST90 DS_FAST89 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST88 DS_FAST87 DS_FAST86 DS_FAST85 DS_FAST84 DS_FAST83 DS_FAST82 DS_FAST81 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-12. Drive Strength Control Register 7 (DSCR7) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-23 System Control Table 4-13. Drive Strength Control Register 7 Field Descriptions Field 31–30 29–28 DS_FAST95 Description Reserved. These bits are reserved and should read 0. Drive Strength Fast I/O. Controls the driving strength of fast I/O group 95 (RW_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 94 (BCLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 93 (LBA_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 92 (OE_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 91 (ECB_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 90 (CS5_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 89 (CS4_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 88 (CS3_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 87 (CS2_B). 00 Normal 01 High 10 Max high 11 Max high 27–26 DS_FAST94 25–24 DS_FAST93 23–22 DS_FAST92 21–20 DS_FAST91 19–18 DS_FAST90 17–16 DS_FAST89 15–14 DS_FAST88 13–12 DS_FAST87 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-24 Freescale Semiconductor System Control Table 4-13. Drive Strength Control Register 7 Field Descriptions (continued) Field 11–10 DS_FAST86 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 86 (CS1_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 85 (CS0_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 84 (EB1_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 83 (EB0_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 82 (SDBA1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 81 (SDBA0). 00 Normal 01 High 10 Max high 11 Max high 9–8 DS_FAST85 7–6 DS_FAST84 5–4 DS_FAST83 3–2 DS_FAST82 1–0 DS_FAST81 4.2.13 Drive Strength Control Register 8 The Drive Strength Control Register 8 (DSCR8) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-13 shows the register and Table 4-14 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-25 System Control 0x1002_783C (DSCR8) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 DS_FAST111 DS_FAST110 DS_FAST109 DS_FAST108 DS_FAST107 DS_FAST106 DS_FAST105 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R DS_FAST10 DS_FAST103 DS_FAST102 DS_FAST101 DS_FAST100 DS_FAST99 4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 DS_FAST98 0 0 DS_FAST97 0 0 Figure 4-13. Drive Strength Control Register 8 (DSCR8) Table 4-14. Drive Strength Control Register 8 Field Descriptions Field 31–30 29–28 DS_FAST111 Description Reserved. These bits are reserved and should read 0. Drive Strength Fast I/O. Controls the driving strength of fast I/O group 111 (SDQS3). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 110 (SDQS2). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 109 (SDQS1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 108 (SDQS0). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 107 (SDCLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 106 (SDCKE1). 00 Normal 01 High 10 Max high 11 Max high 27–26 DS_FAST110 25–24 DS_FAST109 23–22 DS_FAST108 21–20 DS_FAST107 19–18 DS_FAST106 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-26 Freescale Semiconductor System Control Table 4-14. Drive Strength Control Register 8 Field Descriptions (continued) Field 17–16 DS_FAST105 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 105 (SDCKE0). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 104 (SDWE_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 103 (CAS_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 102 (RAS_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 101 (MA10). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 100 (DQM3). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 99 (DQM2). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 98 (DQM1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 97 (DQM0). 00 Normal 01 High 10 Max high 11 Max high 15–14 DS_FAST104 13–12 DS_FAST103 11–10 DS_FAST102 9–8 DS_FAST101 7–6 DS_FAST100 5–4 DS_FAST99 3–2 DS_FAST98 1–0 DS_FAST97 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-27 System Control 4.2.14 Drive Strength Control Register 9 The Drive Strength Control Register 9 (DSCR9) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-14 shows the register and Table 4-15 provides its field descriptions. 0x1002_7840 (DSCR9) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 DS_FAST127 DS_FAST126 DS_FAST125 DS_FAST124 DS_FAST123 DS_FAST122 DS_FAST121 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST120 DS_FAST119 DS_FAST118 DS_FAST117 DS_FAST116 DS_FAST115 DS_FAST114 DS_FAST113 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-14. Drive Strength Control Register 9 (DSCR9) Table 4-15. Drive Strength Control Register 9 Field Descriptions Field 31–30 29–28 DS_FAST127 Description Reserved. These bits are reserved and should read 0. Drive Strength Fast I/O. Controls the driving strength of fast I/O group 127 (M_REQUEST). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 126 (M_GRANT). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 125 (IOIS16). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 124 (PC_POE). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 123 (PC_RW_B). 00 Normal 01 High 10 Max high 11 Max high 27–26 DS_FAST126 25–24 DS_FAST125 23–22 DS_FAST124 21–20 DS_FAST123 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-28 Freescale Semiconductor System Control Table 4-15. Drive Strength Control Register 9 Field Descriptions (continued) Field 19–18 DS_FAST122 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 122 (PC_RST). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 121 (PC_BVD2). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 120 (PC_BVD1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 119 (PC_VS2). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 118 (PC_VS1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 117 (PC_PWRON). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 116 (PC_READY). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 115 (PC_WAIT_B). 00 Normal 01 High 10 Max high 11 Max high 17–16 DS_FAST121 15–14 DS_FAST120 13–12 DS_FAST119 11–10 DS_FAST118 9–8 DS_FAST117 7–6 DS_FAST116 5–4 DS_FAST115 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-29 System Control Table 4-15. Drive Strength Control Register 9 Field Descriptions (continued) Field 3–2 DS_FAST114 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 114 (PC_CD2_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 113 (PC_CD1_B). 00 Normal 01 High 10 Max high 11 Max high 1–0 DS_FAST113 4.2.15 Drive Strength Control Register 10 The Drive Strength Control Register 10 (DSCR10) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-15 shows the register and Table 4-16 provides its field descriptions. 0x1002_7844 (DSCR10) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 DS_FAST143 DS_FAST142 DS_FAST141 DS_FAST140 DS_FAST139 DS_FAST138 DS_FAST137 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST136 DS_FAST135 DS_FAST134 DS_FAST133 DS_FAST132 DS_FAST131 DS_FAST130 DS_FAST129 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-15. Drive Strength Control Register 10 (DSCR10) Table 4-16. Drive Strength Control Register 10 Field Descriptions Field 31–30 29–28 DS_FAST143 Description Reserved. These bits are reserved and should read 0. Drive Strength Fast I/O. Controls the driving strength of fast I/O group 143 (SD3_CMD). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 142 (SD3_CLK). 00 Normal 01 High 10 Max high 11 Max high 27–26 DS_FAST142 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-30 Freescale Semiconductor System Control Table 4-16. Drive Strength Control Register 10 Field Descriptions (continued) Field 25–24 DS_FAST141 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 141 (SD2_CLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 140 (LSCLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 139 (CSI_MCLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 138 (CSI_PIXCLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 137 (CLKO). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 136. 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 135 (NFWE_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 134 (NFRE_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 133 (NFALE). 00 Normal 01 High 10 Max high 11 Max high 23–22 DS_FAST140 21–20 DS_FAST139 19–18 DS_FAST138 17–16 DS_FAST137 15–14 DS_FAST136 13–12 DS_FAST135 11–10 DS_FAST134 9–8 DS_FAST133 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-31 System Control Table 4-16. Drive Strength Control Register 10 Field Descriptions (continued) Field 7–6 DS_FAST132 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 132 (NFCLE). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 131 (NFWP_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 130 (NFCE_B). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 129 (NFRB). 00 Normal 01 High 10 Max high 11 Max high 5–4 DS_FAST131 3–2 DS_FAST130 1–0 DS_FAST129 4.2.16 Drive Strength Control Register 11 The Drive Strength Control Register 11 (DSCR11) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-16 shows the register and Table 4-17 provides its field descriptions. 0x1002_7848 (DSCR11) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset DS_FAST160 DS_FAST159 DS_FAST158 DS_FAST157 DS_FAST156 DS_FAST155 DS_FAST154 DS_FAST153 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST152 DS_FAST151 DS_FAST150 DS_FAST149 DS_FAST148 DS_FAST147 DS_FAST146 DS_FAST145 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-16. Drive Strength Control Register 11 (DSCR11) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-32 Freescale Semiconductor System Control Table 4-17. Drive Strength Control Register 11 Field Descriptions Field 31–30 DS_FAST160 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 160 (ATA_DATA15). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 159 (ATA_DATA14). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 158 (ATA_DATA13). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 157 (ATA_DATA12). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 156 (ATA_DATA11). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 155 (ATA_DATA10). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 154 (ATA_DATA9). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 153 (ATA_DATA8). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 152 (ATA_DATA7). 00 Normal 01 High 10 Max high 11 Max high 29–28 DS_FAST159 27–26 DS_FAST158 25–24 DS_FAST157 23–22 DS_FAST156 21–20 DS_FAST155 19–18 DS_FAST154 17–16 DS_FAST153 15–14 DS_FAST152 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-33 System Control Table 4-17. Drive Strength Control Register 11 Field Descriptions (continued) Field 13–12 DS_FAST151 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 151 (ATA_DATA6). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 150 (ATA_DATA5). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 149 (ATA_DATA4). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 148 (ATA_DATA3). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 147 (ATA_DATA2). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 146 (ATA_DATA1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 145 (ATA_DATA0). 00 Normal 01 High 10 Max high 11 Max high 11–10 DS_FAST150 9–8 DS_FAST149 7–6 DS_FAST148 5–4 DS_FAST147 3–2 DS_FAST146 1–0 DS_FAST145 4.2.17 Drive Strength Control Register 12 The Drive Strength Control Register 12 (DSCR12) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-17 shows the register and Table 4-18 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-34 Freescale Semiconductor System Control 0x1002_784C (DSCR12) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 DS_FAST172 DS_FAST171 DS_FAST170 DS_FAST169 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R DS_FAST DS_FAST DS_FAST DS_FAST DS_FAST164 DS_FAST163 DS_FAST162 DS_FAST161 168 167 166 165 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-17. Drive Strength Control Register 12 (DSCR12) Table 4-18. Drive Strength Control Register 12 Field Descriptions Field 31–24 23–22 DS_FAST172 Description Reserved. These bits are reserved and should read 0. Drive Strength Fast I/O. Controls the driving strength of fast I/O group 172 (USBOTG_CLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 171 (USBOTG_NXT). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 170 (USBOTG_STP). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 169 (USBOTG_DIR). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 168 (USBOTG_DATA7). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 167 (USBOTG_DATA6). 00 Normal 01 High 10 Max high 11 Max high 21–20 DS_FAST171 19–18 DS_FAST170 17–16 DS_FAST169 15–14 DS_FAST168 13–12 DS_FAST167 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-35 System Control Table 4-18. Drive Strength Control Register 12 Field Descriptions (continued) Field 11–10 DS_FAST166 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 166 (USBOTG_DATA5). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 165 (USBOTG_DATA4). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 164 (USBOTG_DATA3). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 163 (USBOTG_DATA2). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 162 (USBOTG_DATA1). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 161 (USBOTG_DATA0). 00 Normal 01 High 10 Max high 11 Max high 9–8 DS_FAST165 7–6 DS_FAST164 5–4 DS_FAST163 3–2 DS_FAST162 1–0 DS_FAST161 4.2.18 Drive Strength Control Register 13 The Drive Strength Control Register 13 (DSCR13) controls the driving force parameters of the fast I/O signals in the i.MX27 device. Figure 4-18 shows the register and Table 4-19 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-36 Freescale Semiconductor System Control 0x1002_7850 (DSCR13) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 DS_FAST188 DS_FAST187 DS_FAST186 DS_FAST185 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset DS_FAST184 DS_FAST183 DS_FAST182 DS_FAST181 DS_FAST180 DS_FAST179 DS_FAST178 DS_FAST177 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4-18. Drive Strength Control Register 13 (DSCR13) Table 4-19. Drive Strength Control Register 13 Field Descriptions Field 31–24 23–22 DS_FAST188 Description Reserved. These bits are reserved and should read 0. Drive Strength Fast I/O. Controls the driving strength of fast I/O group 188 (USBH2_CLK). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 187 (USBH2_DIR). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 186 (USBH2_NXT). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 185 (USBH2_STP). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 184 (USBH2_DATA7). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 183 (USBH2_DATA6). 00 Normal 01 High 10 Max high 11 Max high 21–20 DS_FAST187 19–18 DS_FAST186 17–16 DS_FAST185 15–14 DS_FAST184 13–12 DS_FAST183 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-37 System Control Table 4-19. Drive Strength Control Register 13 Field Descriptions (continued) Field 11–10 DS_FAST182 Description Drive Strength Fast I/O. Controls the driving strength of fast I/O group 182 (USBH2_DATA5). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 181 (USBH2_DATA4). 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 180.(USBH2_DATA3) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 179 (USBH2_DATA2) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 178 (USBH2_DATA1) 00 Normal 01 High 10 Max high 11 Max high Drive Strength Fast I/O. Controls the driving strength of fast I/O group 177 (USBH2_DATA0) 00 Normal 01 High 10 Max high 11 Max high 9–8 DS_FAST181 7–6 DS_FAST180 5–4 DS_FAST179 3–2 DS_FAST178 1–0 DS_FAST177 4.2.19 Pull Strength Control Register (PSCR) The Pull Strength Control Register (PSCR) controls the pull strength value and direction for the chip. Figure 4-19 shows the register and Table 4-20 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-38 Freescale Semiconductor System Control 0x1002_7854 (PSCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 R W Reset PUENCR7 0 0 PUENCR6 0 0 PUENCR5 0 0 PUENCR4 0 0 PUENCR3 0 0 PUENCR2 0 0 PUENCR1 0 0 PUENCR0 0 0 Figure 4-19. Pull Strength Control Register (PSCR) Table 4-20. Pull Strength Control Register Field Descriptions Field 31–16 15–14 PUENCR Description Reserved. These bits are reserved and should read 0. PUEN Strength Control 7. Bit selects direction (up or down) and strength. (SD2_D0_MSHC_DATA0) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up PUEN Strength Control 6. Bit selects direction (up or down) and strength. (SD2_D1_MSHC_DATA1) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up PUEN Strength Control 5. Bit selects direction (up or down) and strength. (SD2_D2_MSHC_DATA2) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up PUEN Strength Control 4. Bit selects direction (up or down) and strength. (SD2_D3_MSHC_DATA3) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up PUEN Strength Control 3. Bit selects direction (up or down) and strength. (SD2_CMD_MSHC_BS) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 13–12 PUENCR6 11–10 PUENCR5 9–8 PUENCR4 7–6 PUENCR3 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-39 System Control Table 4-20. Pull Strength Control Register Field Descriptions (continued) Field 5–4 PUENCR2 Description PUEN Strength Control 2. Bit selects direction (up or down) and strength. (SD2_CLK_MSHC_SCLK) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up PUEN Strength Control 1. Bit selects direction (up or down) and strength. (SD1_D3_CSPI3_SS) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up PUEN Strength Control 0. Bit selects direction (up or down) and strength. (ATA_DATA3_SD3_D3S) 00 100k pull-down 01 100k pull-up 10 47k pull-up 11 22k pull-up 3–2 PUENCR1 1–0 PUENCR0 4.2.20 Priority Control and Select Register (PCSR) The Priority Control and Select Register (PCSR) consist of the master high priority and slave alternate context priority select to the ARM9 Platform. Figure 4-20 shows the register and Table 4-21 provides its field descriptions. Address 0x1002_7858 (PCSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 S3_AMPR_SEL S2_AMPR_SEL S1_AMPR_SEL 0 1 R W 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 M5_HIGH_PRIORITY M4_HIGH_PRIORITY M3_HIGH_PRIORITY M2_HIGH_PRIORITY M1_HIGH_PRIORITY R W 0 0 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 4-20. Priority Control and Select Register (PCSR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-40 Freescale Semiconductor M0_HIGH_PRIORITY 1 S0_AMPR_SEL 0 0 System Control Table 4-21. Priority Control and Select Register Field Descriptions Field 31–20 19–16 S3_AMPR_SEL S2_AMPR_SEL S1_AMPR_SEL S0_AMPR_SEL 15–6 5–0 M5_HIGH_PRIORITY M4_HIGH_PRIORITY M3_HIGH_PRIORITY M2_HIGH_PRIORITY M1_HIGH_PRIORITY M0_HIGH_PRIORITY Description Reserved. These bits are reserved and should read 0. Slave Alternate Context Priority Select. Inputs to the ARM9 Platform to select the priority determination and control source for the appropriate slave port. (Note s0 is the primary AHB and does not come out of the ARM9 Platform. 0 Priority determination and control is made by regular registers. 1 Priority determination and control is made by alternate registers set in the Crossbar switch. Reserved. These bits are reserved and should read 0. Master High Priority. Inputs to the ARM9 Platform to elevate to highest appropriate master ports priority level to each slave above all other master ports priority levels which do not have this input asserted. If more than one master has its high priority input asserted, priority level is determined by the software programmed priority assignments inside the Crossbar switch. 0 Master port low priority 1 Master port high priority 4.2.21 Power Management Control Register (PMCR) The Power Management Control Register (PMCR) controls the DPTC function of the chip. Figure 4-21 shows the register and Table 4-22 provides its field descriptions. 0x1002_7860 (PMCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset MC 0 15 EM 0 14 UP 0 13 LO 0 12 0 0 11 REFCOUNTER 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset RVEN 0 0 0 VSTBY 0 0 0 0 DCR 0 RCLK DRCE DRCE DRCE DRCE 3 1 2 0 ON 0 0 0 0 0 0 DIM 0 DIE 0 DPTE N 0 0 0 Figure 4-21. Power Management Control Register (PMCR) Table 4-22. Power Management Control Register Field Descriptions Field 31 MC 30 EM 29 UP MC. Measure complete status bit 0 On progress or idle 1 Measure completed EM. Emergency interrupt state bit 0 No Emergency interrupt 1 Emergency interrupt is detected. UP. Upper_limit interrupt state bit 0 No Upper_limit interrupt is detected. 1 Upper_limit interrupt is detected. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-41 System Control Table 4-22. Power Management Control Register Field Descriptions (continued) Field 28 LO 27 26–16 REFCOUNTER 15 RVEN LO. Lower_limit interrupt state bit. 0 No lower_limit interrupt. 1 Lower_limit interrupt is detected. Reserved. These bits are reserved and should read 0. Reference Counter Value. These bits contains the value of reference counter in comparison stage. Reduced Voltage Mode Enable. This bit controls whether enable RV mode when chip is in sleep mode. 0 Disable RV mode is in sleep mode. 1 Enable RV mode is in sleep mode. Reserved. These bits are reserved and should read 0. Voltage Standby Control. These two bits will be put on Boot1 and Boot0 when chip is in sleep mode. And used to inform PMIC to change the voltage to the chip. Reserved. These bits are reserved and should read 0. DPTC counting range. This bit sets how many times the system clock may increment and the reference circuits remain active (and their output signals will be counted). Value of ‘1’ causes a 256 system clock count. Value of ‘0’ causes a 128 system clock count. 0 128 system clock count 1 256 system clock count DPTC Reference Clock Monitor On. Enable Reference clock for debug. 0 Normal operation 1 Reference clock always on DPTC reference circuit3 enable. This bit defines if reference circuit3 is enabled during DPTC operation. 0 DPTC reference circuit3 is disabled. 1 DPTC reference circuit3 is enabled. DPTC reference circuit2 enable. This bit defines if reference circuit2 is enabled during DPTC operation. 0 DPTC reference circuit2 is disabled. 1 DPTC reference circuit2 is enabled. DPTC reference circuit1 enable. This bit defines if reference circuit1 is enabled during DPTC operation. 0 DPTC reference circuit1 is disabled. 1 DPTC reference circuit1 is enabled. DPTC reference circuit0 enable. This bit defines if reference circuit0 is enabled during DPTC operation. 0 DPTC reference circuit0 is disabled. 1 DPTC reference circuit0 is enabled. DPTC interrupt mask. these bits control how DPTC generate its interrupt. 00 DPTC will generate an interrupt in all cases. 01 DPTC will generate an interrupt only in lower_limit case. 10 DPTC will generate an interrupt only in upper_limit case. 11 DPTC will generate an interrupt only in emergency case. Description 14 13–12 VSTBY 11–10 9 DCR 8 RCLKON 7 DRCE3 6 DRCE2 5 DRCE1 4 DRCE0 3–2 DIM MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-42 Freescale Semiconductor System Control Table 4-22. Power Management Control Register Field Descriptions (continued) Field 1 DIE 0 DPTEN Description DPTC Interrupt enable. This bit enables DPTC interrupt generation. 0 No interrupt will be generated. 1 Enable interrupt generation DPTC enable. This bit enables the DPTC block and starts the reference circuit clock counting and compares this to look-up table values. 0 DPTC is disabled. 1 DPTC is enabled. 4.2.22 DPTC Comparator Value Register 0 (DCVR0) The DPTC Comparator Value Register 0 (DCVR0) contains the DPTC comparator value for the DPTC in the i.MX27 processor. Figure 4-22 shows the register and Table 4-23 provides its field descriptions. 0x1002_7864 (DCVR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 15 ULV 0 14 LLV 0 9 0 13 0 12 0 11 0 10 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset 0 0 0 LLV 0 0 0 0 0 0 0 0 ELV 0 0 0 0 0 Figure 4-22. DPTC Comparator Value Register 0 (DCVR0) Table 4-23. DPTC Comparator Value Register 0 Field Description Field 31–21 ULV 20–10 LLV 9–0 ELV Description Upper Limit. Value for the upper performance limit of the reference circuit 0 clock counter. Lower Limit. Value for the lower performance limit of the reference circuit 0 clock counter. Emergency Limit. Value for the lower performance limit of the reference circuit 0 clock counter. This serves as an “emergency” lower limit, which indicates a critical value. 4.2.23 DPTC Comparator Value Register 1 (DCVR1) The DPTC Comparator Value Register 1 (DCVR1) contains the DPTC comparator value for the DPTC in the i.MX27 processor. Figure 4-23 shows the register and Table 4-24 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-43 System Control 0x1002_7868 (DCVR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 15 ULV 0 14 LLV 0 9 0 13 0 12 0 11 0 10 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset 0 0 0 LLV 0 0 0 0 0 0 0 0 ELV 0 0 0 0 0 Figure 4-23. DPTC Comparator Value Register 1 (DCVR1) Table 4-24. DPTC Comparator Value Register 1 Field Descriptions Field 31–21 ULV 20–10 LLV 9–0 ELV Description Upper Limit. Value for the upper performance limit of the reference circuit 1 clock counter. Lower Limit. Value for the lower performance limit of the reference circuit 1 clock counter. Emergency Limit. Value for the lower performance limit of the reference circuit 1 clock counter. This serves as an “emergency” lower limit, which indicates a critical value 4.2.24 DPTC Comparator Value Register 2 The DPTC Comparator Value Register 2 (DCVR2) contains the DPTC comparator value for the DPTC in the i.MX27 processor. Figure 4-24 shows the register and Table 4-25 provides its field descriptions. 0x1002_786C (DCVR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 15 ULV 0 14 LLV 0 9 0 13 0 12 0 11 0 10 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset 0 0 0 LLV 0 0 0 0 0 0 0 0 ELV 0 0 0 0 0 Figure 4-24. DPTC Comparator Value Register 2 (DCVR2) Table 4-25. DPTC Comparator Value Register 2 Field Descriptions Field 31–21 ULV Description Upper Limit. Value for the upper performance limit of the reference circuit 2 clock counter. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-44 Freescale Semiconductor System Control Table 4-25. DPTC Comparator Value Register 2 Field Descriptions (continued) Field 20–10 LLV 9–0 ELV Description Lower Limit. Value for the lower performance limit of the reference circuit 2 clock counter. Emergency Limit. Value for the lower performance limit of the reference circuit 2 clock counter. This serves as an “emergency” lower limit, which indicates a critical value. 4.2.25 DPTC Comparator Value Register 3 The DPTC Comparator Value Register 3 (DCVR3) contains the DPTC comparator value for the DPTC in the i.MX27 processor. Figure 4-25 shows the register and Table 4-26 provides its field descriptions. 0x1002_7870 (DCVR3) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 15 ULV 0 14 LLV 0 9 0 13 0 12 0 11 0 10 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset 0 0 0 LLV 0 0 0 0 0 0 0 0 ELV 0 0 0 0 0 Figure 4-25. DPTC Comparator Value Register 3 (DCVR3) Table 4-26. DPTC Comparator Value Register 3 Description Field 31–21 ULV 20–10 LLV 9–0 ELV Description Upper Limit. Value for the upper performance limit of the reference circuit 3 clock counter. Lower Limit. Value for the lower performance limit of the reference circuit 3 clock counter. Emergency Limit. Value for the lower performance limit of the reference circuit 3 clock counter. This serves as an “emergency” lower limit, which indicates a critical value. 4.2.26 PMIC Pad Control Register (PPCR) The PMIC Pad Control Register (PPCR) contains control bits of Boot0 and Boot1 pads which used for RV function in low power mode. Figure 4-26 shows the register and Table 4-27 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-45 System Control 0x1002_7874 (PPCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 R W Reset 0 0 0 0 0 PUS1 1 PUE1 0 0 DSE1 0 OE1 0 0 0 0 0 0 PUS0 1 PUE0 0 0 DSE0 1 OE0 1 Figure 4-26. PMIC Pad Control Register (PPCR) Table 4-27. PMIC Pad Control Register Field Description Field 31–14 13–12 PUS1 11 PUE1 10–9 DSE1 8 OE1 7–16 5–4 PUS0 3 PUE0 2–1 DSE0 0 OE0 Description Reserved. These bits are reserved and should read 0. PUS1. PUS control of BOOT1 pad. Only used when RVEN bit is set. PUE1. PUE control of BOOT1 pad. Only used when RVEN bit is set. DSE1. DSE control of BOOT1 pad. Only used when RVEN bit is set. OE1. OE control of BOOT1 pad. Only used when RVEN bit is set. Reserved. These bits are reserved and should read 0. PUS0. PUS control of BOOT0 pad. Only used when RVEN bit is set. PUE0. PUE control of BOOT0 pad. Only used when RVEN bit is set. DSE0. DSE control of BOOT0 pad. Only used when RVEN bit is set. OE0. OE control of BOOT0 pad. Only used when RVEN bit is set. 4.3 System Boot Mode Selection The operational system boot mode of the i.MX27 processor upon system reset is determined by the configuration of the four external input pins, BOOT[3:0]. The settings of these pins control where the system is boot from and the memory port size. The i.MX27 processor always begins fetching instruction from the address 0x00000000 after reset. The BOOT[3:0] pins control the memory region that is mapped to the address 0x0. Upon power up, if the BOOT_INT is 1, the Boot Address will always be 0x00000000. If the fuse of the BOOT_INT is blown, the BOOT Address will be generated based on the BOOT[3:0] information. The boot modes are defined in Table 4-28. These boot modes information are registered during the system reset. When an external chip MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-46 Freescale Semiconductor System Control select is enabled by the BOOT[3:0] pins, the reset vector 0x0 will jump to the corresponding boot address space. NOTE The BOOT pins must not change once the i.MX27 device is out of reset. For proper operation, BOOT[3] must always be tied to VSS. Table 4-28. System Boot Mode Selection Inputs BOOT[3:0] 0000 0010 0011 0100 0101 0110 0111 Output Signals Active Device (Boot Internal) iROM (Bootstrap USB/UART) iROM (8-bit 2 Kbyte NAND Flash) iROM (16-bit 2 Kbyte NAND Flash) iROM (16-bit 512 byte NAND Flash) iROM (16-bit CS0 at D[15:0] (NOR Flash)) Reserved iROM (8-bit 512 byte NAND Flash) Output Signals Active Device (Boot External) iROM Bootstrap USB/UART 8-bit 2 Kbyte NAND Flash 16-bit 2 Kbyte NAND Flash 16-bit 512 Kbyte NAND Flash 16-bit CS0 at D[15:0] (NOR Flash) Reserved 8-bit 512B NAND Flash Boot Address 0x00000030 0xD8000000 0xD8000000 0xD8000000 0xC0000000 0xC0000000 0xD8000000 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 4-47 System Control MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4-48 Freescale Semiconductor Chapter 5 Signal Descriptions and Pin Assignments 5.1 Introduction This chapter identifies and describes the i.MX27 signals and their pin assignments. 5.2 Signal Descriptions The i.MX27 signals are described in Table 5-1. Most of the signals shown in Table 5-1 are multiplexed with other signals. For simplicity, only the primary signal names are shown. See Table 5-2 for complete information on the signal multiplexing schemes of these signals. Table 5-1. i.MX27 Signal Descriptions Pad Name Function/Notes External Bus/Chip Select (EMI) A [13:0] MA10 A [25:14] SDBA[1:0] SD[31:0] SDQS[3:0] DQM0–DQM3 EB0 EB1 OE CS [5:0] Address bus signals, shared with SDRAM/MDDR, WEIM and PCMCIA, A[10] for SDRAM/MDDR is not the address but the pre-charge bank select signal. Address bus signals for SDRAM/MDDR Address bus signals, shared with WEIM and PCMCIA SDRAM/MDDR bank address signals Data bus signals for SDRAM, MDDR MDDR data sample strobe signals SDRAM data mask strobe signals Active low external enable byte signal that controls D [15:8], shared with PCMCIA PC_REG. Active low external enable byte signal that controls D [7:0], shared with PCMCIA PC_IORD. Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR. Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is selected. DTACK is multiplexed with CS4. CS[5:4] are multiplexed with ETMTRACECLK and ETMTRACESYNC; PF22, 21. Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by flash device causing external burst device to latch the starting burst address. ECB LBA MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-1 Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name BCLK RW RAS CAS SDWE SDCKE0 SDCKE1 SDCLK SDCLK_B NFWE_B NFRE_B NFALE NFCLE NFWP_B NFCE_B NFRB D[15:0] PC_CD1_B PC_CD2_B PC_WAIT_B PC_READY PC_PWRON PC_VS1 PC_VS2 PC_BVD1 PC_BVD2 PC_RST IOIS16 PC_RW_B PC_POE Function/Notes Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also shared with the PCMCIA PC_WE. SDRAM/MDDR Row Address Select signal SDRAM/MDDR Column Address Select signal SDRAM Write Enable signal SDRAM Clock Enable 0 SDRAM Clock Enable 1 SDRAM Clock SDRAM Clock_B NFC Write enable signal, multiplexed with ETMPIPESTAT2; PF6 NFC Read enable signal, multiplexed with ETMPIPESTAT1; PF5 NFC Address latch signal, multiplexed with ETMPIPESTAT0; PF4 NFC Command latch signal, multiplexed with ETMTRACEPKT0; PF1 NFC Write Permit signal, multiplexed with ETMTRACEPKT1; PF2 NFC Chip enable signal, multiplexed with ETMTRACEPKT2; PF3 NFC read Busy signal, multiplexed with ETMTRACEPKT3; PF0 Data Bus signal, shared with EMI, PCMCIA, and NFC PCMCIA card detect signal, multiplexed with ATA ATA_DIOR signal; PF20 PCMCIA card detect signal, multiplexed with ATA ATA_DIOW signal; PF19 PCMCIA WAIT signal, multiplexed with ATA ATA_CS1 signal; PF18 PCMCIA READY/IRQ signal, multiplexed with ATA ATA_CS0 signal; PF17 PCMCIA signal, multiplexed with ATA ATA_DA2 signal; PF16 PCMCIA voltage sense signal, multiplexed with ATA ATA_DA1 signal; PF14 PCMCIA voltage sense signal, multiplexed with ATA ATA_DA0 signal; PF13 PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMARQ signal; PF12 PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMACK signalPF11 PCMCIA card reset signal, multiplexed with ATA ATA_RESET_B signal; PF10 PCMCIA mode signal, multiplexed with ATA ATA_INTRQ signal; PF9 PCMCIA read write signal, multiplexed with ATA ATA_IORDY signal; PF8 PCMCIA output enable signal, multiplexed with ATA ATA_BUFFER_EN signal; PF7 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name Function/Notes Clocks and Resets CLKO EXT_60M EXT_266M OSC26M_TEST RESET_IN Clock Out signal selected from internal clock signals. Refer to the clock controller for internal clock selection; PF15. This is a special factory test signal. To ensure proper operation, connect this signal to ground. This is a special factory test signal. To ensure proper operation, connect this signal to ground. This is a special factory test signal. To ensure proper operation, leave this signal as a no connect. Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module, SDRAMC module, and the clock control module) are reset. Reset_Out—Output from the internal Hreset_b; and the Hreset can be caused by all reset source: power on reset, system reset (RESET_IN), and watchdog reset. Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. Oscillator output to external crystal Crystal input (26 MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal oscillator circuit is shut down. These are special factory test signals. To ensure proper operation, do not connect to these signals. 32 kHz crystal input (Note: in the RTC power domain) Oscillator output to 32 kHz crystal (Note: in the RTC power domain) (Note: in the RTC power domain) (Note: in the RTC power domain) The signal for osc32k input bypass (Note: in the RTC power domain) Bootstrap BOOT [3:0] System Boot Mode Select—The operational system boot mode of the i.MX27 processor upon system reset is determined by the settings of these pins. BOOT[1:0] are also used as handshake signals to PMIC(VSTBY). JTAG JTAG_CTRL JTAG Controller select signal—JTAG_CTRL is sampled during rising edge of TRST. Must be pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes only. Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. RESET_OUT POR XTAL26M EXTAL26M CLKMODE[1:0] EXTAL32K XTAL32K Power_cut Power_on_reset osc32K_bypass TRST TDO TDI TCK MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-3 Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name TMS RTCK Function/Notes Test Mode Select to sequence JTAG test controller’s state machine. Sampled on rising edge of TCK. JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed with 1-Wire; thus, utilizing 1-Wire will render RTCK unusable and vice versa; PE16. Secure Digital Interface (X2) SD1_CMD SD Command bidirectional signal—If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 4. 7K–69 K external pull up resistor must be added. This signal is multiplexed with CSPI3_MOSI; PE22. SD Output Clock. This signal is multiplexed with CSPI3_SCLK; PE23. SD Data bidirectional signals—If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 50 K–69 K external pull up resistor must be added. SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO PE21–18. SD Command bidirectional signal. This signal is multiplexed with MSHC_BS; through GPIO multiplexed with SLCDC1_CS; PB8. SD Output Clock signal. This signal is multiplexed with MSHC_SCLK, through GPIO multiplexed with SLCDC1_CLK; PB9. SD Data bidirectional signals. SD2_D[3:0] multiplexed with MSHC_DATA[0:3], also through GPIO SD2_1:0] multiplexed with SLCDC1_RS and SLDCD1_D0; PB7–PB4. SD Command bidirectional signal. This signal is multiplexed with ETMTRACEPKT15 and also through GPIO PD1 multiplexed with FEC_TXD1. SD Output Clock signal. This signal is through GPIO PD0 multiplexed with FEC_TXD0. SD1_CLK SD1_D[3:0] SD2_CMD SD2_CLK SD2_D[3:0] SD3_CMD SD3_CLK Note: SD3_DATA is multiplexed with ATA_DATA3–0. UARTs (X6) UART1_RTS UART1_CTS UART1_RXD UART1_TXD UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART3_RTS UART3_CTS UART3_RXD UART3_TXD Request to Send input signal; PE15 Clear to Send output signal; PE14 Receive Data input signal; PE13 Transmit Data output signal, PE12 Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP; PE7. Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP; PE6. Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP; PE4. Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP; PE3. Request to Send input signal, PE11 Clear to Send output signal; PE10 Receive Data input signal; PE9 Transmit Data output signal; PE8 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-4 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name Function/Notes Note: UART 4, 5, and 6 are multiplexed with COMS Sensor Interface signals. Keypad KP_COL[5:0] Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and UART2_TXD respectively. Alternatively, KP_COL6 is also available on the internal factory test signal TEST_WB2. The Function Multiplexing Control Register in the System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signal KP_COL6 is available. Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and UART2_RXD signals respectively. The Function Multiplexing Control Register in the System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available. KP_ROW[5:0] Note: KP_COL[7:6] and KP_ROW[7:6] are multiplexed with UART2 signals as show above, also see UARTs table. PWM PWMO PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and TOUT3 of the General Purpose Timer module; PE5. CSPI (X3) CSPI1_MOSI CSPI1_MISO CSPI1_SS[2:0] CSPI1_SCLK CSPI1_RDY CSPI2_MOSI CSPI2_MISO CSPI2_SS[2:0] CSPI2_SCLK Master Out/Slave In signal, PD31 Master In/Slave Out signal, PD30 Slave Select (Selectable polarity) signal, the CSPI1_SS2 is multiplexed with USBH2_DATA5/RCV; and CSPI1_SS1 is multiplexed with EXT_DMAGRANT; PD26–28. Serial Clock signal, PD29 Serial Data Ready signal, shared with Ext_DMAReq_B signal; PD25 Master Out/Slave In signal, multiplexed with USBH2_DATA1/TXDP; PD24 Master In/Slave Out signal, multiplexed with USBH2_DATA2/TXDm; PD23 Slave Select (Selectable polarity) signals, multiplexed with USBH2_DATA4/RXDM, USBH2_DATA3/RXDP, USBH2_DATA6/SPEED; PD19–PD21 Serial Clock signal, multiplexed with USBH2_DATA0/OEn; PD22 Note: CSPI3 CSPI3_MOSI, CSPI3_MISO, CSPI3_SS, andCSPI3_SCLK are multiplexed with SD1 signals. I2C I2C2_SCL I2C2_SDA I2C_CLK I2C_DATA I2C2 Clock, through GPIO, multiplexed with SLCDC_data8; PC6 I2C2 Data, through GPIO, multiplexed with SLCDC_data7; PC5 I2C1 Clock; PD18 I2C1 Data; PD17 CMOS Sensor Interface CSI_HSYNC Sensor port horizontal sync, multiplexed with UART5_RTSP; PB21 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-5 Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name CSI_VSYNC CSI_D7 CSI_D6 CSI_D5 CSI_PIXCLK CSI_MCLK CSI_D4 CSI_D3 CSI_D2 CSI_D1 CSI_D0 Function/Notes Sensor port vertical sync, multiplexed with UART5_CTS; PB20 Sensor port data, multiplexed with UART5_RXD; PB19 Sensor port data, multiplexed with UART5_TXD; PB18 Sensor port data; PB17 Sensor port data latch clock; PB16 Sensor port master clock, PB15 Sensor port data, PD14 Sensor port data, multiplexed with UART6_RTS; PB13 Sensor port data, multiplexed with UART6_CTS; PB12 Sensor port data, multiplexed with UART6_RXD; PB11 Sensor port data, multiplexed with UART6_TXD; PB10 Serial Audio Port—SSI (Configurable to I2S Protocol and AC97) (2 to 4) SSI1_CLK SSI1_TXD SSI1_RXD SSI1_FS SSI2_CLK SSI2_TXD SSI2_RXD SSI2_FS SSI3_CLK SSI3_TXD SSI3_RXD SSI3_FS SSI4_CLK SSI4_TXD SSI4_RXD SSI4_FS Serial clock signal that is output in master or input in slave; PC23 Transmit serial data; PC22 Receive serial data; PC21 Frame Sync signal that is output in master and input in slave; PC20 Serial clock signal that is output in master or input in slave, multiplexed with GPT4_TIN. PC27 Transmit serial data signal, multiplexed with GPT4_TOUT; PC26 Receive serial data, multiplexed with GPT5_TIN; PC25 Frame Sync signal which is output in master and input in slave, multiplexed with GPT5_TOUT: PC24 Serial clock signal which is output in master or input in slave. This signal is multiplexed with SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31. Transmit serial data signal which is multiplexed with SLCDC2_CS, through GPIO multiplexed with PC_READY; PC30 Receive serial data which is multiplexed with SLCDC2_RS; through GPIO multiplexed with PC_VS1; PC29 Frame Sync signal which is output in master and input in slave. This signal is multiplexed with SLCDC2_D0; through GPIO multiplexed with PC_VS1; PC28. Serial clock signal which is output in master or input in slave; through GPIO multiplexed with PC_BVD1; PC19 Transmit serial data; through GPIO multiplexed with PC_BVD2; PC18 Receive serial data; through GPIO multiplexed with IOIS16; PC17 Frame Sync signal which is output in master and input in slave; PC16 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-6 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name Function/Notes General Purpose Timers (X6) TIN Timer Input Capture or Timer Input Clock—The signal on this input is applied to GPT 1–3 simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15. Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply TOUT, and is also multiplexed with GPT6_TIN; PC14. TOUT1 Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads. USB2.0 USBOTG_DIR/TXDM USBOTG_STP/TXDM USBOTG_NXT/TXDM USBOTG_CLK/TXDM USBOTG_DATA7/SUSPEND USBH2_STP/TXDM USBH2_NXT/TXDM USBH2_DATA7/SUSPEND USBH2_DIR/TXDM USBH2_CLK/TXDM USBOTG_DATA3/RXDP USBOTG_DATA4/RXDM USBOTG_DATA1/TXDP USBOTG_DATA2/TXDm USBOTG_DATA0/Oen USBOTG_DATA6/SPEED USBOTG_DATA5/RCV USBH1_RXDP USBH1_RXDM USBH1_TXDP USBH1_TXDM USBH1_OE_B USB OTG direction/Transmit Data Minus signal, multiplexed with KP_ROW7A; PE2 USB OTG Stop signal/Transmit Data Minus signal, multiplexed with KP_ROW6A; PE1 USB OTG NEXT/Transmit Data Minus signal, multiplexed with KP_COL6A; PE0 USB OTG Clock/Transmit Data Minus signal, PE24 USB OTG Data7/Suspend signal, PE25 USB Host2 Stop signal/Transmit Data Minus signal, PA4 USB Host2 NEXT/Transmit Data Minus signal, PA3 USB Host2 Data7/Suspend signal, PA2 USB Host2 Direction/Transmit Data Minus signal, PA1 USB Host2 Clock/Transmit Data Minus signal; PA0 USB OTG data4/Receive Data Plus signal; multiplexed with SLCDC1_DAT15 through PC13 USB OTG data4/Receive Data Minus signal; multiplexed with SLCDC1_DAT14 through PC12 USB OTG data1/Transmit Data Plus signal; multiplexed with SLCDC1_DAT13 through PC11 USB OTG data2/Transmit Data Minus signal; multiplexed with SLCDC1_DAT12 through PC10 USB OTG data0/Output Enable signal; multiplexed with SLCDC1_DAT11 through PC9 USB OTG data6/Suspend signal; multiplexed with SLCDC1_DAT10 and USBG_TXR_INT_B through PC8 USB OTG data5/RCV signal; multiplexed with SLCDC1_DAT9 through PC7 USB Host1 Receive Data Plus signal, multiplexed with UART4_RXD; multiplexed with SLCDC1_DAT6 and UART4_RTS_ALT through PB31 USB Host1 Receive Data Minus signal; multiplexed with SLCDC1_DAT5 and UART4_CTS through PB30 USB Host1 Transmit Data Plus signal; multiplexed with UART4_CTS, multiplexed with SLCDC1_DAT4 and UART4_RXD_ALT through PB29 USB Host1 Transmit Data Minus signal; multiplexed with UART4_TXD, multiplexed with SLCDC1_DAT3 through PB28 USB Host1 Output Enable signal; multiplexed with SLCDC1_DAT2 through PB27 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-7 Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name USBH1_FS USBH1_RCV USB_OC_B USB_PWR USBH1_SUSP Function/Notes USB Host1 Full Speed output signal, multiplexed with UART4_RTS, multiplexed with SLCDC1_DAT1 through PB26 USB Host1 RCV signal; multiplexed with SLCDC1_DAT0 through PB25 USB OC signal. PB24 USB Power signal; PB23 USB Host1 Suspend signal; PB22 LCD Controller and Smart LCD Controller OE_ACD CONTRAST VSYNC HSYNC SPL_SPR PS CLS REV LD [17:0] LSCLK Alternate Crystal Direction/Output Enable; PA31 This signal is used to control the LCD bias voltage as contrast control; PA30 Frame Sync or Vsync—This signal also serves as the clock signal output for gate; driver (dedicated signal SPS for Sharp panel HR-TFT); PA29. Line Pulse or HSync; PA28 Sampling start signal for left and right scanning. Through GPIO, this signal is multiplexed with the SLCDC1_CLK; PA27. Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the SLCDC1_CS; PA26. Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This signal is multiplexed with the SLCDC1_RS; PA25. Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is multiplexed with SLCDC1_D0; PA24. LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. Through GPIO, LD[15:0] signals are multiplexed with SLCDC1_DAT[15:0], SLCDC. PA23–PA6. Shift Clock; PA5 Note: SLCDC signals are multiplexed with LCDC signals. ATA ATA_DATA15–0 ATA Data Bus, [15:0] are multiplexed with ETMTRACEPKT4–12, FEC_MDIO, ETMTRACEPKT13–14 SD3_D3–0; Through GPIO also are multiplexed with SLCDC 15–0, and FEC signals; PF23, PD16–PD2. Noisy I/O Supply Pins NVDD1–15, AVDD Noisy Supply for the I/O pins. There are 16 I/O voltage pads, NVDD1 through NVDD15 + AVDD. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-8 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-1. i.MX27 Signal Descriptions (continued) Pad Name Function/Notes Analog Supply Pins FPMVDD MPLLVDD OSC26VDD UPLLVDD OSC32VDD FPMVSS MPLLVSS OSC26VSS OSC32VSS UPLLVSS Supply for analog blocks Quiet GND for analog blocks QVDD Internal Power Supply QVDD QVSS FUSEVDD RTCVDD RTCVSS Power supply pins for silicon internal circuitry GND pins for silicon internal circuitry For FuseVDD For RTC, SCC power supply For RTC, SCC GND Note: Note: Both 1-Wire and Fast Ethernet Controller signals are multiplexed with other signals. As a result these signal names do not appear in this list. The signals are listed below with the named signal that they are multiplexed. 1-Wire Signals: The 1-Wire input and output signal is multiplexed with JTAG RTCK pad, PE16. Fast Ethernet Controller (FEC) Signals: FEC_TX_EN: Transmit enable signal, through GPIO multiplexed with ATA_DATA15 pad; PF23 FEC_TX_ER: Transmit Data Error; through GPIO multiplexed with ATA_DATA14 pad; PD16 FEC_COL: Collision signal; through GPIO multiplexed with ATA_DATA13 pad; PD15 FEC_RX_CLK: Receive Clock signal; through GPIO multiplexed with ATA_DATA12 pad; PD14 FEC_RX_DV: Receive data Valid signal; through GPIO multiplexed with ATA_DATA11 pad; PD13 FEC_RXD0: Receive Data0; through GPIO multiplexed with ATA_DATA10 pad; PD12 FEC_TX_CLK: Transmit Clock signal; through GPIO multiplexed with ATA_DATA9 pad; PD11 FEC_CRS: Carrier Sense enable; through GPIO multiplexed with ATA_DATA8 pad; PD10 FEC_MDC: Management Data Clock; through GPIO multiplexed with ATA_DATA7 pad; PD9 FEC_MDIO: Management Data Input/Output, multiplexed with ATA_DATA6 pad; PD8 FEC_RXD3–1: Receive Data; through GPIO multiplexed with ATA_DATA5–3 pad; PD7–5 FEC_RX_ER: Receive Data Error; through GPIO multiplexed with ATA_DATA2 pad; PD4 FEC_TXD3–2: Transmit Data; through GPIO multiplexed with ATA_DATA1–0; pad; PD3–2 FEC_TXD1: Transmit Data; through GPIO multiplexed with SD3_CLK pad; PD1 FEC_TXD0: Transmit Data; through GPIO multiplexed with SD3_CMD pad; PD0 Note: The Rest ATA signals are multiplexed with PCMCIA Pads. 5.3 I/O Power Supply and Signal Multiplexing Scheme This section describes information about both the power supply for each I/O pin and its functional multiplexing scheme. Section 5.3.3, “I/O Mode and Supply Level” provides information on how to configure the power supply scheme for each device in the system (memory and external peripherals). The MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-9 Signal Descriptions and Pin Assignments functional multiplexing information shown in Table 5-2 enables the user to select the function of each pin by configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions. In some cases, the use of the Function Multiplexing Control Register (FMCR) in Chapter 4, “System Control” may be required to select multiplex functionality. 5.3.1 Pull/Pull Strength/Open Drain Descriptions For Table 5-2, the following notes describe the abbreviations used in the Pull/Pull Strength/Open Drain section. • KP—Keeper Circuit permanently On when in Primary/Alternate Mode • PU—Pull Up permanently On when in Primary/Alternate Mode • PD—Pull Down permanently On when in Primary/Alternate Mode • PUEN—Pull Up controllable from Module when in Primary/Alternate Mode • PDEN—Pull Down controllable from Module when in Primary/Alternate Mode • OD—Open Drain permanently On when in Primary/Alternate Mode • ODEN—Open Drain Enable controllable from Module when in Primary/Alternate Mode 5.3.2 • • • GPIO Default and Pull-Up Configuration The term Primary name is the package contact name. The Default column contains the GPIO default configuration as it appears after chip reset. Pull-up configuration and pull strength—Pin mux with GPIO means that Pull Up is controlled by the GPIO PUEN register (in Primary, Alternate or GPIO Mode), and the default pull strength is 100 K for all GPIO use. 5.3.3 I/O Mode and Supply Level The supply level shown in Table 5-2 relates to the power bank segment. The same bank pad can be supplied same voltage. The voltage limitation relates to the I/O mode selected. — I/O type of DDR mode—Voltage rating 1.65–1.95 V. Supply level 1.8 V is recommended for 100% duty cycle. — I/O type of slow mode—Voltage rating 1.65–3.3 V. Supply level 3.05 V is recommended for 100% duty cycle; — I/O type of fast mode—Voltage rating 1.65–3 V. Supply level 2.8 V is recommended for 100% duty cycle; — For every analog pad a recommended supply voltage is shown. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-10 Freescale Semiconductor Pull-up/Pull Strength/Open Drain2 Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 T19 U18 U19 V23 Y22 Y23 M18 P15 R18 R19 R15 T18 GND H1 J1 AVDD AVDD AVDD AVDD AVDD AVDD FPMVDD FPMVDD FUSEVDD FUSEVDD MPLLVDD MPLLVDD NVDD1 NVDD1 NVDD1 Supply Supply Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Supply Supply Supply Supply Supply Supply Supply Fast Fast AVSS AVDD BOOT2 BOOT0 BOOT3 BOOT1 FPMVDD FPMVSS FUSEVDD FUSEVSS MPLLVSS MPLLVDD NVSS1 NFRB NFWP_B static static I I I I static static static static static static static I O ETMTRACE PKT3 ETMTRACE PKT1 O O PF0 PF2 PUEN PUEN AVSS AVDD BOOT2 BOOT0 BOOT3 BOOT1 FPMVDD FPMVSS FUSEVD D FUSEVS S MPLLVSS MPLLVD D NVSS1 NFRB NFWP_B Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-11 Table 5-2. i.MX27 Pin MUX Table Primary Alternate GPIO MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 K1 L1 L2 L5 L6 M1 M2 M3 M5 M6 N1 N2 N3 N5 N6 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 Fast Fast Fast Fast Fast DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR NFALE NFWE_B NFCE_B NFRE_B NFCLE D14 D15 D11 D13 D9 D12 D7 D5 D3 D1 O O O O O B B B B B B B B B B KP KP KP KP KP KP KP KP KP KP ETMPIPES TAT0 ETMPIPES TAT2 ETMTRACE PKT2 ETMPIPES TAT1 ETMTRACE PKT0 O O O O O PF4 PF6 PF3 PF5 PF1 PUEN PDEN PUEN PUEN PUEN NFALE NFWE_B NFCLE NFRE_B NFCE_B D14 D15 D11 D13 D9 D12 D7 D5 D3 D1 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-12 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 NVDD 1 P1 P2 R1 R2 T1 T2 A10 A11 A12 A13 A8 A9 B10 NVDD1 Supply NVDD1 static NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD1 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 DDR DDR DDR DDR DDR DDR Slow/Hyst Slow/Hyst D10 D8 D6 D4 D2 D0 SSI2_RXD AT SSI3_RXD AT B B B B B B B B B B B B B KP KP KP KP KP KP GPT5_TIN SLCDC2_R S PU/100k PU/100k PC17 PC21 GPT4_TIN I PC27 PUEN PUEN PUEN IOIS16 I I PC25 PC29 PUEN PUEN PC_V S1 D10 D8 D6 D4 D2 D0 PC25 PC29 KP_ROW 1 KP_ROW 5 PC17 PC21 PC27 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-13 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Signal Descriptions and Pin Assignments Slow_/Hyst KP_ROW1 Slow1/Hyst KP_ROW5 Slow/Hyst Slow/Hyst Slow/Hyst SSI4_RXD AT SSI1_RXD AT SSI2_CLK Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 B11 B12 NVDD10 NVDD10 Slow/Hyst Slow/Hyst SSI3_CLK KP_ROW3 B B PU/100k SLCDC2_C LK I PC31 PUEN PC_W AIT_B PC31 KP_ROW 3 B7 B8 B9 C12 C9 E10 E11 E8 E9 F10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst TIN SSI4_CLK SSI1_CLK KP_ROW2 SSI3_TXD AT SSI3_FS KP_ROW4 TOUT SSI1_TXD AT SSI2_TXD AT I B B B B B B O B B GPT4_TOU T O PU/100k PU/100k SLCDC2_C S SLCDC2_D 0 I I PC15 PC19 PC23 PUEN PUEN PUEN GPT6_ TOUT WKGD _B PC_B VD1 PC15 PC19 PC23 KP_ROW 2 PC30 PC28 PUEN PUEN PC_R EADY PC_V S2 PC30 PC28 KP_ROW 4 PC14 PC22 PC26 PUEN PUEN PUEN SSI_M SSI_M CLK1 CLK2 GPT6_ TIN PC14 PC22 PC26 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-14 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 F11 NVDD10 Slow/Hyst KP_ROW0 B PU/100k KP_ROW 0 PC16 PC20 PUEN PUEN PC16 PC20 NVDD10 PC18 GPT5_TOU T O PC24 PUEN PUEN PC_B VD2 PC18 PC24 NVSS10 UART6_RT S I PB13 PUEN LCDC _TEST 9 LCDC _TEST 11 LCDC _TEST 15 LCDC _TEST 7 PB13 Signal Descriptions and Pin Assignments F8 F9 G11 G8 G9 GND A5 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD10 NVDD11 Slow/Hyst Slow/Hyst Supply Slow/Hyst Slow/Hyst Supply Slow/Hyst SSI4_FS SSI1_FS NVDD10 SSI4_TXD AT SSI2_FS NVSS10 CSI_D3 B B static B B static I A6 NVDD11 Slow/Hyst CSI_D5 I PB17 PUEN PB17 A7 NVDD11 Slow/Hyst CSI_HSYN C CSI_D1 I UART5_RT S UART6_RX D I PB21 PUEN PB21 B4 NVDD11 Slow/Hyst I I PB11 PUEN PB11 B5 NVDD11 Fast/Hyst CSI_MCLK O PB15 PUEN PB15 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-15 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 B6 NVDD11 Slow/Hyst CSI_D7 I UART5_RX D UART6_TX D UART6_CT S I PB19 PUEN LCDC _TEST 13 LCDC _TEST 6 LCDC _TEST 8 PB19 C4 NVDD11 Slow/Hyst CSI_D0 I O PB10 PUEN PB10 E6 NVDD11 Slow/Hyst CSI_D2 I O PB12 PUEN PB12 E7 F6 NVDD11 NVDD11 Fast/Hyst Slow/Hyst CSI_PIXCL K CSI_D4 I I PB16 PB14 PUEN PUEN LCDC _TEST 10 LCDC _TEST 12 PB16 PB14 F7 NVDD11 Slow/Hyst CSI_D6 I UART5_TX D O PB18 PUEN PB18 G10 G7 NVDD11 NVDD11 Supply Slow/Hyst NVDD11 CSI_VSYN C NVSS11 SPL_SPR static I UART5_CT S O PB20 PUEN LCDC _TEST 14 NVDD11 PB20 GND B3 NVDD11 NVDD12 Supply Slow/Hyst static O PA27 PDEN SLCD C1_CL K NVSS11 PA27 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-16 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 C2 D1 D2 D3 E1 E2 NVDD12 NVDD12 NVDD12 NVDD12 NVDD12 NVDD12 Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst CONTRAS T HSYNC PS OE_ACD REV LD16 O O O O O O PA30 PA28 PA26 PA31 PA24 PA22 PUEN PUEN PDEN PUEN PDEN PUEN SLDC D1_D0 Ext_D MAGra nt_B SLCD C1_DA T14 SLCD C1_DA T10 SLCD C1_DA T6 SLCD C1_DA T2 SLCD C1_CS PA30 PA28 PA26 PA31 PA24 PA22 F1 NVDD12 Slow/Hyst LD14 O PA20 PUEN PA20 Signal Descriptions and Pin Assignments F2 NVDD12 Slow/Hyst LD10 O PA16 PUEN PA16 F5 G1 NVDD12 NVDD12 Slow/Hyst Slow/Hyst VSYNC LD8 O O PA29 PA14 PUEN PUEN SLCD C1_DA T8 SLCD C1_DA T6 SLCD C1_DA T0 PA29 PA14 G2 5-17 NVDD12 Slow/Hyst LD6 O PA12 PUEN PA12 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 G5 G6 GND H2 NVDD12 NVDD12 NVDD12 NVDD12 Slow/Hyst Slow/Hyst Supply Slow/Hyst LD17 CLS NVSS12 LD4 O O static O PA23 PA25 PUEN PDEN SLCD C1_RS PA23 PA25 NVSS12 PA10 PUEN SLCD C1_DA T4 SLCD C1_DA T12 SLCD C1_DA T13 SLCD C1_DA T15 SLCD C1_DA T0 SLCD C1_DA T2 SLCD C1_DA T7 SLCD C1_DA T4 SLCD C1_DA T5 SLCD C1_DA T7 PA10 H3 NVDD12 Slow/Hyst LD12 O PA18 PUEN PA18 H5 NVDD12 Slow/Hyst LD13 O PA19 PUEN PA19 H6 NVDD12 Slow/Hyst LD15 O PA21 PUEN PA21 J2 NVDD12 Slow/Hyst LD0 O PA6 PUEN PA6 J3 NVDD12 Slow/Hyst LD2 O PA8 PUEN PA8 J5 NVDD12 Slow/Hyst LD7 O PA13 PUEN PA13 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-18 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 J6 NVDD12 Slow/Hyst LD5 O PA11 PUEN SLCD C1_DA T5 SLCD C1_DA T11 SLCD C1_DA T3 PA11 J7 NVDD12 Slow/Hyst LD11 O PA17 PUEN PA17 K2 K5 NVDD12 NVDD12 Fast/Hyst Slow/Hyst LSCLK LD3 O O PA5 PA9 PUEN PUEN SLCD C1_DA T3 SLCD C1_DA T1 SLCD C1_DA T9 SLCD C1_DA T1 PA5 PA9 K6 NVDD12 Slow/Hyst LD1 O PA7 PUEN PA7 K7 NVDD12 Slow/Hyst LD9 O PA15 PUEN PA15 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-19 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Signal Descriptions and Pin Assignments L7 GND L24 M19 N19 NVDD12 NVDD13 NVDD13 NVDD13 NVDD13 Supply Supply Slow/Hyst Supply Slow/Hyst NVDD12 NVSS13 osc32k_by pass NVDD13 Power_on_ reset static static I static I PU/100k NVDD12 NVSS13 osc32k_b ypass NVDD13 Power_on _reset Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 N22 C23 C24 NVDD13 NVDD14 NVDD14 Slow/Hyst Fast/Hyst Slow/Hyst Power_cut CSPI2_SS 1 USBH1_O E_B CSPI2_SS 2 CSPI2_SC LK USBH1_TX DP USBH1_FS I B B PD/100k USBH2_DA TA3/RXDP B PD20 PB27 PUEN PUEN SLCD C1_DA T2 Power_cu t PD20 PB27 D22 D23 D24 NVDD14 NVDD14 NVDD14 Fast/Hyst Fast/Hyst Slow/Hyst B B O USBH2_DA TA4/RXDM USBH2_DA TA0/OEn UART4_CT S UART4_RT S USBH2_DA TA5/RCV USBH2_DA TA1/TXDP B B O PD19 PD22 PB29 PUEN PUEN PDEN SLCD C1_DA T4 SLCD C1_DA T1 UART4 _RXD_ ALT PD19 PD22 PB29 E19 NVDD14 Slow/Hyst B I PB26 PDEN PB26 E22 E23 NVDD14 NVDD14 Fast/Hyst Fast/Hyst CSPI1_SS 2 CSPI2_MO SI USBH1_R XDP B B B B PD26 PD24 PUEN PUEN PD26 PD24 E24 NVDD14 Slow/Hyst B UART4_RX D I PB31 PDEN SLCD C1_DA T6 UART4 _RTS_ ALT PB31 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-20 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 F19 NVDD14 Slow/Hyst USBH1_TX DM CSPI2_SS 0 USB_PWR I2C2_SCL O UART4_TX D USBH2_DA TA6/SPEED O PB28 PDEN SLCD C1_DA T3 PB28 F20 F23 F24 NVDD14 NVDD14 NVDD14 Fast/Hyst Slow/Hyst Slow/Hyst B O B OD B PD21 PB23 PC6 PUEN PUEN PUEN SLCD C1_DA T8 PD21 PB23 PC6 G19 G20 NVDD14 NVDD14 Slow/Hyst Fast/Hyst USBH1_S USP CSPI2_MIS O NVSS14 NVDD14 USB_OC_ B USBH1_R CV USBH1_R XDM B B USBH2_DA TA2/TXDm static static I B B PB22 PD23 PUEN PUEN USB_BY P_B PD23 Signal Descriptions and Pin Assignments GND H18 H20 H22 NVDD14 NVDD14 NVDD14 NVDD14 Supply Supply Slow/Hyst Slow/Hyst NVSS14 NVDD14 PB24 PB25 PUEN PUEN SLCD C1_DA T0 SLCD C1_DA T5 UART4 _CTS PB24 PB25 J20 5-21 NVDD14 Slow/Hyst B PB30 PDEN PB30 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 J22 NVDD14 Slow/Hyst I2C2_SDA B OD PC5 PUEN SLCD C1_DA T7 SLCD C1_RS LCDC _TEST 3 LCDC _TEST 5 LCDC _TEST 0 SLCD C1_CS SLDC D1_D0 SLCD C1_CL K LCDC _TEST 4 LCDC _TEST 2 LCDC _TEST 1 PC5 A3 NVDD15 Slow/Hyst SD2_D3 B PU/PD/1 MSHC_DAT 00k A3 MSHC_SCL K PU/100k MSHC_DAT A0 PU/100k MSHC_BS B PU/PD/1 00k PB7 PDEN PB7 A4 NVDD15 Fast/Hyst SD2_CLK O O PB9 PDEN PB9 C1 NVDD15 Slow/Hyst SD2_D0 B B PD/100k PB4 PDEN PB4 C5 NVDD15 Slow/Hyst SD2_CMD B O PD/100k PB8 PDEN PB8 C8 NVDD15 Slow/Hyst SD2_D2 B PU/100k MSHC_DAT A2 PU/100k MSHC_DAT A1 B PD/100k PB6 PDEN PB6 E3 NVDD15 Slow/Hyst SD2_D1 B B PD/100k PB5 PDEN PB5 GND H7 AA1 AA2 NVDD15 NVDD15 NVDD2 NVDD2 Supply Supply DDR DDR NVSS15 NVDD15 SD30 A24 static static B O KP KP NVSS15 NVDD15 SD30 A24 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-22 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 AA3 AB1 AB2 AB4 AB5 AB8 AC3 AC4 AC5 AC6 AC7 AD3 AD4 AD5 AD6 AD7 GND NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR Supply SD27 A23 SD24 A21 SD21 SD10 A22 SD20 SD17 A18 A17 SD22 SD19 SD16 SD14 SD11 NVSS2 B O B O B B O B B O O B B B B B static KP KP KP KP KP KP KP KP KP KP KP KP KP KP KP KP SD27 A23 SD24 A21 SD21 SD10 A22 SD20 SD17 A18 Signal Descriptions and Pin Assignments A17 SD22 SD19 SD16 SD14 SD11 NVSS2 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-23 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 NVDD 2 P5 P6 R5 R6 T3 T5 T6 U1 U2 U3 U5 U6 V1 V2 V5 V6 NVDD2 Supply NVDD2 static NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR A9 A12 A5 A7 MA10 SDBA1 A1 A13 A11 A3 SD31 A25 A8 A6 SD26 SD28 B B B B O O B B B B B O B B B B KP KP KP KP A9 A12 A5 A7 MA10 KP KP KP KP KP KP KP KP KP KP KP SDBA1 A1 A13 A11 A3 SD31 A25 A8 A6 SD26 SD28 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-24 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 V7 V8 W1 W2 W5 W6 W7 W8 W9 Y1 Y2 Y3 Y6 Y7 Y8 Y9 AB12 AB9 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD2 NVDD3 NVDD3 DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR SD29 A19 A4 A2 SD23 SDQS2 SD25 SDQS1 SD13 A0 SDBA0 SDQS3 A20 SD18 SD15 SD12 SD0 A14 B O B B B B B B B B O B O B B B B B KP KP KP KP KP KP KP KP KP KP KP KP KP KP KP KP KP KP SD29 A19 A4 A2 SD23 SDQS2 SD25 SDQS1 SD13 A0 Signal Descriptions and Pin Assignments SDBA0 SDQS3 A20 SD18 SD15 SD12 SD0 A14 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-25 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 AC10 AC11 AC8 AC9 AD10 AD11 AD8 AD9 GND NVDD 3 W10 W11 Y10 Y11 Y12 AB13 AB16 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 DDR DDR DDR DDR DDR DDR DDR DDR Supply Supply SD4 SD1 SD9 SD5 SD3 DQM3 SD7 SDQS0 NVSS3 NVDD3 B B B B B O B B static static KP KP KP KP KP KP KP KP SD4 SD1 SD9 SD5 SD3 DQM3 SD7 SDQS0 NVSS3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD3 NVDD4 NVDD4 DDR DDR DDR DDR DDR DDR DDR SD6 A16 SD8 A15 SD2 RAS_B CS1_B B O B B B O O KP KP KP KP KP KP SD6 A16 SD8 A15 SD2 RAS_B CS1_B Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-26 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 AB17 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AD12 AD13 AD14 AD15 AD16 AD17 AD18 GND NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 DDR DDR DDR DDR DDR Fast DDR Fast DDR DDR_CLK DDR_CLK Fast DDR Fast Fast Supply BCLK A10 CAS_B SDCKE0 RW_B ECB_B EB1_B JTAG_CTR L DQM0 SDCLK SDCLK_B CS4_B CS0_B CLKO EXT_266M NVSS4 O B O O O I O I O B B O O O I static PF15 PUEN ETMTRACE SYNC O PF21 PUEN CS5_D TACK PU/100k KP PU/100k KP KP KP BCLK A10 CAS_B SDCKE0 RW_B ECB_B EB1_B JTAG_CT RL DQM0 Signal Descriptions and Pin Assignments SDCLK SDCLK_ B CS4_B CS0_B CLKO EXT_266 M NVSS4 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-27 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 V13 W12 W13 W14 W15 W16 W17 Y13 Y14 Y15 Y16 Y17 AA22 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD4 NVDD5 Supply DDR DDR DDR Fast DDR Fast DDR DDR DDR DDR DDR Slow/Hyst NVDD4 DQM1 SDWE_B CS3_B CS5_B EB0_B EXT_60M DQM2 SDCKE1 CS2_B LBA_B OE_B RESET_O UT_B CLKMODE 0 CLKMODE 1 static O O O O O I O O O O O O PE17 PUEN PC_TE ST_AH BST0 KP KP KP KP KP KP ETMTRACE CLK O PF22 PUEN NVDD4 DQM1 SDWE_B CS3_B CS5_B EB0_B EXT_60M DQM2 SDCKE1 CS2_B LBA_B OE_B RESET_ OUT_B CLKMOD E0 CLKMOD E1 AB20 AB21 NVDD5 NVDD5 Slow/Hyst Slow/Hyst I I PU/100k PU/100k Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-28 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 AC19 AC20 AC21 AC22 AD19 AD20 AD21 AD22 GND NVDD 5 U20 V20 W18 NVDD5 NVDD5 NVDD5 NVDD5 NVDD5 NVDD5 NVDD5 NVDD5 NVDD5 NVDD5 Slow Slow Slow Slow/Hyst Slow Slow Slow Slow/Hyst Supply Supply PC_CD2_B PC_VS1 PC_RST RESET_IN _B PC_READ Y PC_BVD1 PC_RW_B POR_B NVSS5 NVDD5 I I O I I I O I static static PU/100k ATA_DIOW ATA_DA1 ATA_RESE T_B O O O PF19 PF14 PF10 PUEN PUEN PUEN PC_CD2_ B PC_VS1 PC_RST RESET_I N_B ATA_CS0 ATA_DMAR Q ATA_IORDY O I I PF17 PF12 PF8 PUEN PUEN PUEN PC_REA DY PC_BVD 1 PC_RW_ B POR_B NVSS5 NVDD5 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-29 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Signal Descriptions and Pin Assignments NVDD5 NVDD5 NVDD5 Slow Slow Slow IOIS16 PC_POE PC_CD1_B I O I ATA_INTRQ ATA_BUFF ER_EN ATA_DIOR I O O PF9 PF7 PF20 PUEN PUEN PUEN IOIS16 PC_POE PC_CD1_ B Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 W19 W20 Y18 Y19 GND NVDD 6 P19 NVDD5 NVDD5 NVDD5 NVDD5 NVDD6 NVDD6 Slow Slow Slow Slow Supply Supply PC_VS2 PC_BVD2 PC_WAIT_ B PC_PWRO N NVSS6 NVDD6 I I I I static static ATA_DA0 ATA_DMAC K ATA_CS1 ATA_DA2 O O O O PF13 PF11 PF18 PF16 PUEN PUEN PUEN PDEN PC_VS2 PC_BVD 2 PC_WAIT _B PC_PWR ON NVSS6 NVDD6 NVDD6 Slow/Hyst ATA_DATA6 B FEC_MDIO B PD8 PUEN SLCD C1_DA T6 SLCD C1_DA T2 FEC_T XD0 FEC_T XD1 SLCD C1_DA T10 FEC_ RXD0 FEC_ RX_E R ATA_DAT A6 ATA_DAT A2 SD3_CM D SD3_CLK ATA_DAT A10 P20 NVDD6 Slow/Hyst ATA_DATA2 B SD3_D2 B PD4 PUEN P23 P24 R20 NVDD6 NVDD6 NVDD6 Slow/Hyst Slow/Hyst Slow/Hyst SD3_CMD SD3_CLK ATA_DATA1 0 B O B ETMTRACE PKT15 ETMTRACE PKT9 O O PD0 PD1 PD12 PUEN PUEN PUEN Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-30 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 R23 NVDD6 Slow/Hyst ATA_DATA0 B SD3_D0 B PD2 PUEN FEC_T XD2 FEC_T XD3 FEC_T X_ER SLCD C1_DA T0 SLCD C1_DA T1 SLCD C1_DA T14 SLCD C1_DA T4 SLCD C1_DA T5 SLCD C1_DA T3 SLCD C1_DA T8 FEC_ RXD2 FEC_ RXD3 FEC_ RXD1 FEC_ CRS ATA_DAT A0 ATA_DAT A1 ATA_DAT A14 ATA_DAT A4 ATA_DAT A5 Signal Descriptions and Pin Assignments ATA_DAT A3 ATA_DAT A8 ATA_DAT A12 ATA_DAT A7 R24 NVDD6 Slow/Hyst ATA_DATA1 B SD3_D1 B PD3 PUEN T20 NVDD6 Slow/Hyst ATA_DATA1 4 ATA_DATA4 B ETMTRACE PKT5 ETMTRACE PKT14 ETMTRACE PKT13 SD3_D3 O PD16 PDEN T22 NVDD6 Slow/Hyst B O PD6 PUEN T23 NVDD6 Slow/Hyst ATA_DATA5 B O PD7 PUEN T24 NVDD6 Slow/Hyst ATA_DATA3 B B PU/PD/1 00k PD5 PDEN U22 NVDD6 Slow/Hyst ATA_DATA8 B ETMTRACE PKT11 ETMTRACE PKT7 ETMTRACE PKT12 O PD10 PUEN U23 NVDD6 Slow/Hyst ATA_DATA1 2 ATA_DATA7 B O PD14 PUEN SLCD FEC_ C1_DA RX_CL T12 K FEC_ MDC SLCD C1_DA T7 U24 5-31 NVDD6 Slow/Hyst B O PD9 PUEN Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 V24 NVDD6 Slow/Hyst ATA_DATA9 B ETMTRACE PKT10 ETMTRACE PKT8 ETMTRACE PKT6 ETMTRACE PKT4 O PD11 PUEN SLCD FEC_T C1_DA X_CLK T9 SLCD C1_DA T11 SLCD C1_DA T13 FEC_T X_EN SLCD C1_DA T13 SLCD C1_DA T12 SLCD C1_DA T10 USBG _TXR_ INT_B SLCD C1_DA T15 FEC_ RX_D V FEC_ COL ATA_DAT A9 ATA_DAT A11 ATA_DAT A13 ATA_DAT A15 PC11 W23 NVDD6 Slow/Hyst ATA_DATA1 1 ATA_DATA1 3 ATA_DATA1 5 B O PD13 PUEN W24 NVDD6 Slow/Hyst B O PD15 PUEN Y24 NVDD6 Slow/Hyst B O PF23 PDEN G18 NVDD7 Fast/Hyst USBOTG_ DATA1/TXD P B PC11 PUEN G23 NVDD7 Fast/Hyst USBOTG_ DATA2/TXD m B PC10 PUEN PC10 G24 NVDD7 Fast/Hyst USBOTG_ DATA6/SPE ED B PC8 PUEN PC8 GND NVDD7 Supply NVSS7 static NVSS7 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-32 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 H19 NVDD7 Fast/Hyst USBOTG_ DATA5/RC V B PC7 PUEN SLCD C1_DA T9 PC7 H23 H24 NVDD7 NVDD7 Fast/Hyst Fast/Hyst USBH2_CL K/TXDM USBOTG_ DATA4/RX DM I B PA0 PC12 PUEN PUEN SLCD C1_DA T14 SLCD C1_DA T11 PA0 PC12 J19 NVDD7 Fast/Hyst USBOTG_ DATA0/Oen B PC9 PUEN PC9 J23 J24 NVDD7 NVDD7 Fast/Hyst Fast/Hyst USBH2_ST P/TXDM USBH2_DA TA7/SUSP END USBOTG_ DATA3/RX DP O B PA4 PA2 PUEN PUEN PA4 Signal Descriptions and Pin Assignments PA2 K20 NVDD7 Fast/Hyst B PC13 PUEN SLCD C1_DA T15 PC13 K23 K24 5-33 NVDD7 NVDD7 Fast/Hyst Fast/Hyst USBH2_DI R/TXDM USBOTG_ CLK/TXDM I I PA1 PE24 PUEN PUEN PA1 PE24 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 L20 L23 NVDD7 NVDD7 Fast/Hyst Fast/Hyst USBH2_N XT/TXDM USBOTG_ STP/TXDM I O KP_ROW6A B PA3 PE1 PUEN PUEN PA3 PE1 M20 NVDD7 Fast/Hyst USBOTG_ NXT/TXDM I KP_COL6A B ODEN PE0 PUEN PE0 M22 NVDD7 Fast/Hyst USBOTG_ DATA7/SU SPEND B PE25 PUEN PE25 N20 NVDD 7 A19 A20 NVDD7 NVDD7 Fast/Hyst Supply USBOTG_ DIR/TXDM NVDD7 I static KP_ROW7A B PE2 PUEN PE2 NVDD7 NVDD8 NVDD8 Slow/Hyst Slow/Hyst RTCK SD1_D0 O B OWIRE CSPI3_MIS O CSPI3_MO SI B I OD PE16 PE18 PUEN PUEN PC_TE ST_AH BST1 PC_TE ST_IN T_ER R RTCK PE18 A21 NVDD8 Slow/Hyst SD1_CMD B O PE22 PUEN PE22 A22 NVDD8 Slow/Hyst CSPI1_MIS O B PD30 PUEN PD30 Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-34 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 B18 B19 B20 NVDD8 NVDD8 NVDD8 Slow/Hyst Slow/Hyst Slow/Hyst TDI TMS SD1_D2 I I B PU/100k PU/100k PE20 PUEN PC_TE ST_CA RDST 1 TDI TMS PE20 B21 NVDD8 Slow/Hyst CSPI1_RD Y/Ext_DMA REQ_B CSPI1_SS 0 TRST_B CSPI1_SS 1 CSPI1_MO SI TDO SD1_D1 I PD25 PUEN PD25 B22 C17 C20 NVDD8 NVDD8 NVDD8 Slow/Hyst Slow/Hyst Slow/Hyst B I B PU/100k PD28 PUEN PD28 TRST_B PD27 PUEN Ext_D MAGra nt_B Ext_D MAGra nt_B PD27 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-35 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Signal Descriptions and Pin Assignments C21 E16 E17 NVDD8 NVDD8 NVDD8 Slow/Hyst Slow/Hyst Slow/Hyst B O B PD31 PUEN PD31 TDO PE19 PUEN PC_TE ST_CA RDST 0 PE19 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 E18 NVDD8 Slow/Hyst SD1_D3 B PU/PD/1 00k CSPI3_SS O PU/PD PE21 PDEN PC_TE ST_CA RDST 2 PE21 F17 F18 G15 G17 NVDD8 NVDD8 NVDD8 NVDD8 Slow/Hyst Slow/Hyst Supply Slow/Hyst TCK CSPI1_SC LK NVDD8 SD1_CLK I B static O PU/100k PD29 PUEN TCK PD29 NVDD8 CSPI3_SCL K O PE23 PUEN PC_TE ST_IN T_ALL PE23 GND A14 A15 A16 A17 A18 B13 NVDD8 NVDD9 NVDD9 NVDD9 NVDD9 NVDD9 NVDD9 Supply NVSS8 static I B O O O B OD PU/100k/ ODEN KP_COL6 B ODEN PE6 PE10 PE14 PD18 PUEN PUEN PUEN PUEN KP_ROW7 B PE4 PUEN NVSS8 UART2_R TS KP_COL2 UART2_T XD PE10 UART1_C TS PD18 Slow2/Hyst UART2_RT S Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst KP_COL2 UART2_TX D UART3_CT S UART1_CT S I2C_CLK Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-36 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 B14 B15 B16 B17 C13 NVDD9 NVDD9 NVDD9 NVDD9 NVDD9 Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst KP_COL0 KP_COL4 UART3_TX D UART1_TX D PWMO B B O O O PU/100k/ ODEN PU/100k/ ODEN PE8 PE12 PE5 PUEN PUEN PUEN PC_S PKOU T TOUT 2 TOUT 3 KP_COL0 KP_COL4 PE8 UART1_T XD PE5 C16 E12 E13 E14 E15 F12 F13 NVDD9 NVDD9 NVDD9 NVDD9 NVDD9 NVDD9 NVDD9 Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst Slow/Hyst UART1_RT S UART2_CT S KP_COL3 UART2_RX D UART3_RT S I2C_DATA KP_COL1 I O B I I B B OD PU/100k/ ODEN PU/100k/ ODEN KP_ROW6 B KP_COL7 B ODEN PE15 PE3 PUEN PUEN UART1_R TS Signal Descriptions and Pin Assignments UART2_C TS KP_COL3 PE7 PE11 PD17 PUEN PUEN PUEN UART2_R XD PE11 PD17 KP_COL1 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconductor 5-37 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 F14 F15 F16 G14 GND AA23 AA24 AB23 AB24 V19 M23 M24 N23 NVDD9 NVDD9 NVDD9 NVDD9 NVDD9 OSC26VDD OSC26VDD OSC26VDD OSC26VDD OSC26VDD OSC32VDD OSC32VDD OSC32VDD Slow/Hyst Slow/Hyst Slow/Hyst Supply Supply Supply Analog_By p Supply KP_COL5 UART3_RX D UART1_RX D NVDD9 NVSS9 OSC26VD D XTAL26M OSC26VS S B I I static static static static static static I static I static PU/100k/ ODEN PE9 PE13 PUEN PUEN KP_COL5 PE9 UART1_R XD NVDD9 NVSS9 OSC26V DD XTAL26M OSC26V SS EXTAL26 M OSC26M _TEST OSC32V DD EXTAL32 K OSC32V SS Analog_By EXTAL26M p Analog Supply Analog Supply OSC26M_ TEST OSC32VD D EXTAL32K OSC32VS S Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-38 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Direction1 Direction2 N24 GND QVDD GND QVDD GND QVDD GND QVDD GND QVDD GND QVDD GND QVDD GND OSC32VDD QVDD10 QVDD10 QVDD12 QVDD12 QVDD2 QVDD2 QVDD3 QVDD3 QVDD5 QVDD5 QVDD6 QVDD6 QVDD7 QVDD7 QVDD8 Analog Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply XTAL32K QVSS10 QVDD10 QVSS12 QVDD12 QVSS2 QVDD2 QVSS3 QVDD3 QVSS5 QVDD5 QVSS6 QVDD6 QVSS7 QVDD7 QVSS8 I static static static static static static static static static static static static static static static XTAL32K QVSS10 QVDD10 QVSS12 QVDD12 QVSS2 QVDD2 QVSS3 QVDD3 QVSS5 QVDD5 QVSS6 QVDD6 QVSS7 QVDD7 QVSS8 Default Signal BOUT AOUT Mux3 AIN BIN CIN Freescale Semiconduter Signal Descriptions and Pin Assignments 5-39 Power Bank I/O Power Supply and Signal Multiplexing Scheme Table 5-2. i.MX27 Pin MUX Table (continued) Primary Pull-up/Pull Strength/Open Drain2 Alternate GPIO Ball map Location Pull-up /Pull Strength /Open Drain Signal/Pad Name I/O Type PUEN/PDEN Power Bank Direction1 Direction2 QVDD K18 K19 J18 QVDD8 RTCVDD RTCVDD UPLLVDD Supply Supply Supply Supply QVDD8 RTCVSS RTCVDD UPLLVDD static static static static QVDD8 RTCVSS RTCVDD UPLLVDD M15 1 2 UPLLVDD Supply UPLLVSS static UPLLVSS Indicates direction of primary signal. It may not indicate the direction of the pin as it may be dependent on other functions. KP = Keeper Circuit permanently On when in Primary/Alternate Mode; PU = Pull Up permanently On when in Primary/Alternate Mode; PUEN = Pull Up controllable from Module when in Primary/Alternate Mode; OD = Open Drain permanently On when in Primary/Alternate Mode; ODEN = Open Drain controllable from Module when in Primary/Alternate Mode. 3 Pin mux with GPIO has its Pull Up controlled by the GPIO PUEN register (in Primary, Alternate, or GPIO Mode) Default Signal BOUT AOUT Mux3 AIN BIN CIN 5-40 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor Signal Descriptions and Pin Assignments Signal Descriptions and Pin Assignments 5.4 Package Pin Assignments Table 5-3 through Table 5-6 identifies the i.MX27 full package MAPBGA pin assignments. The connection of these pins depends solely upon the user application, however there are a few factory test signals that are not used in normal applications. Following is a list of these signals and how they are to be terminated for proper operation of the i.MX27 processor: • CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects. • OSC26M_TEST: To ensure proper operation, leave this signal as no connect. • EXT_48M: To ensure proper operation, connect this signal to ground. • EXT_266M: To ensure proper operation, connect this signal to ground. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-41 Signal Descriptions and Pin Assignments Table 5-3. i.MX27 Full Package MAPBGA Pin Assignment (1 of 4) 1 2 3 4 5 6 7 8 A GN D GN D SD 2_D 3_M SH C SD 2_C LK_M SH C SI_D 3_UA R T 6 _D A T A 3_P B 7_ C _SC LK_P B 9_ _R T S_P B 13_P A PAD PAD D C SI_D 5_P B 17_ PAD C SI_H SYN C _U SSI4_R XD A T _P A R T5_R T S_P B C 17_P A D 21_P A D B GN D GN D C SI_D 1_UA R T 6 C SI_D 7_UA R T 5 SP L_SP R _P A 2 C SI_M C LK_P B 1 SSI4_C LK_P C 19 _R XD _P B 11_P A _R XD _P B 19_P T IN _P C 15_P A D 7_P A D 5_P A D _P A D D AD C SD 2_D 0_M SH C _D A T A 0_P B 4_ PAD C ON TR A ST _P A 30_P A D C SI_D 0_UA R T 6 SD 2_C M D _M S _T XD _P B 10_P A H C _B S_P B 8_P D AD SD 2_D 2_M SH C _D A T A 2_P B 6_ PAD D H SYN C _P A 28_ PAD P S_P A 26_P A D OE_A C D _P A 31 _P A D E R EV_P A 24_P A D LD 16_P A 22_P A D SD 2_D 1_M SH C _D A T A 1_P B 5_ PAD C SI_D 2_UA R T 6 _C T S_P B 12_P A D C SI_P IXC LK_P B 16_P A D T OUT _P C 14_P AD F LD 14_P A 20_P A D LD 10_P A 16_P A D VSYN C _P A 29_ PAD C SI_D 4_P B 14_ PAD C SI_D 6_UA R T 5 SSI4_F S_P C 16_ _T XD _P B 18_P A PAD D G LD 8_P A 14_P A D LD 6_P A 12_P A D LD 17_P A 23_P A D C LS_P A 25_P A D C SI_VSYN C _UA SSI4_T XD A T _P R T 5_C TS_P B 2 C 18_P A D 0_P A D H N F R B _ET M T R LD 12_P A 18_P A LD 4_P A 10_P A D A C EP KT 3_P F 0 D LD 13_P A 19_P A D LD 15_P A 21_P A D N VD D 15 J N F WP _B _ETM T R A C EP KT 1 _P F2 LD 0_P A 6_P A D LD 2_P A 8_P A D LD 7_P A 13_P A D LD 5_P A 11_P A D LD 1 1_P A 17_P A D K N F A LE_ET M P I P EST A T 0_P F 4 LSC LK_P A 5_P AD LD 3_P A 9_P A D LD 1_P A 7_P A D LD 9_P A 15_P A D L N F WE_B _ETM N F C E_B _ET M T P IP EST A T 2_P F R A C EP KT 2_P F 6 3 N F R E_B _ETM N F C LE_ETM T R P IP EST A T 1_P F A C EP KT 0_P F 1 5 N VD D 12 M D 14_P A D D 15_P A D D 11_P A D D1 3_P A D D 9_P A D N VD D 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-42 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-4. i.MX27 Full Package MAPBGA Pin Assignment (2 of 4) 13 14 15 16 17 18 19 20 21 22 23 24 S 1_C D S I3 D M _C P UR A T2_TX _K DP U R TS P A T2_R _K U R TS E U R TS E R K W E P S 1_D S I3_ A T3_C _P A T1_C _P TC _O IR _ D 0_C P C P IS _P S I1_M O D _M S E A O I_P 22_P O EA K _R W A _R W E A K _C L2_P D _C L6_P 6_P P O 5_P D O 7_P 4_P P O A 10_P D A 14_P D A EA 16_P D M O E A IS _P 18_P D 30_P D A D D D GD N GD N A UR A T3_TX _P U R D E A T1_TX _P DE I2C LK D _C _P 18_ K _C L0_P D K _C L4_P D PO A PO A 8_P D A 12_P D A PD A TD I_PAD TM _P D SA S 1_D E P C P D _P 2 C P S D D 2_P 20_ S I1_R Y D S I1_S 0_P 2 A D 5_P D A 8_P D A GD N GD N B P M _P 5_P WO E A D U R TS E A T1_R _P TR T_B A S _P D 15_P D A C P S D C P O I_P S I1_S 1_P 2 S I1_M S D 7_P D A 31_P D A C P S S U B 1_O _B P S I2_S 1_U B S H E _ C H A 3_P 20 B A 2_D TA D 27_P D C P C _U S I2_S LK S CP S S S I2_S 2_U B U B 1_TX P U SH D_ B 2_D TA D H A 0_P D H A 4_P 19 2_D TA D A T4_C _P 29 R TS B 22 U R X _K A T2_R D P U R TS E A T3_R _P K _C L3_P D _R W E A PO A O 6_P 7_P 11_P D A D TD _P D OA U B 1_FS A S H _U R S 1_D E P S 1_D S I3_ D 1_P 19_ D 3_C P T4_R _P 26_P TS B A D S _P 21_P D SE A A D C P O I_U S I2_M S S U B 1_R D _U SH XP CP S S S I1_S 2_U B E B 2_D TA D H A 1_P H A 5_P 26 2_D TA D A T4_R D B R X _P 31 24 K _C L1_P D K _C L5_P D PO A PO A U R X _P U R X _P A T3_R D E A T1_R D E 9_P D A 13_P D A TC _P D KA C P C _P U B 1_TX M U C P S S S I1_S LK D S H D _ S I2_S 0_U B 29_P D A A T4_TX _P 28 H A 6_P 21 R D B 2_D TA D U B W _P 23 I2C C C S _P R B 2_S L_P 6_ _P D A PD A F QD VD ND9 VD ND8 VD QD VD S 1_C _C P3 D LK S I C P IS _U S I2_M O S U B TG A A U B 1_S S _P S O _D T 1 S H U P _S LK E A C _P 23_P B 2_D TA D H A 2_P _P 11_P D CA BA 22_P D 23 D U B T _D TA U B TG A 6 S O G A 2 S O _D TA G _P 10_P D CA _P 8_P D CA N D 14 VD U B TG A 5 U B C _P 2 S O _D TA S _O _B B _P 7_P D CA 4_P D A U B 1_R V B U B 2_C _P U B TG A 4 S H C _P S H LK A S O _D TA H 25_P D A 0_P D A _P 12_P D CA U LLV D A P D _P D U B TG A 0 U B 1_R D _P S O _D TA S H X M _P 9_P D CA BA 30_P D I2C D _P 5_ U B 2_S _P U B 2_D TA 2_S A C S H TP A S H A 7_ PD A 4_P D A P 2_P D AA J GD N GD N GD N R V S A R C D _P D TC S _P D T V D A U B TG A 3 S O _D TA _P 13_P D CA U B 2_D _P 1 U B TG LK P S H IR A S O _C _ K _P D A EA 24_P D GD N GD N GD N ND7 VD ND7 VD U B 2_N T_P SH X A 3_P D A U B TG TP K S O _S _ O C _B P S S 32K Y A P O 6A E _ _R W _P 1 SA _P D PD A L GD N GD N U LLV S A P S _P D FP V D A M D _P D N D 13 VD U TG X K SBO _N T_ P O _P 0_P _C L6A E A D U B T _D TA S OG A 7 O C D _P D E TA _P D M S 32V D A X L32K A _P 25_P D EA MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-43 Signal Descriptions and Pin Assignments Table 5-5. i.MX27 Full Package MAPBGA Pin Assignment (3 of 4) N DA 12_P D DA 7_P D DA 5_P D DA 3_P D DA 1_P D ND1 VD GD N GD N GD N P DA 10_P D DA 8_P D AA 9_P D AA 12_P D QD VD GD N GD N GD N R DA 6_P D DA 4_P D AA 5_P D AA 7_P D ND2 VD GD N GD N GD N T DA 2_P D DA 0_P D M 10_P D AA S B 1_P D DA A AA 1_P D ND2 VD U AA 13_P D AA 11_P D AA 3_P D S 31_P D DA AA 25_P D ND2 VD V AA 8_P D AA 6_P D S 26_P D DA S 28_P D DA S 29_P D DA AA 19_P D ND2 VD ND2 VD ND3 VD ND3 VD W AA 4_P D AA 2_P D S 23_P D DA S Q 2_P D DS A S 25_P D DA S Q 1_P D DS A S 13_P D DA S 6_P D DA AA 16_P D DM A Q 1_P D Y AA 0_P D S B 0_P D DA A S Q 3_P D DS A AA 20_P D S 18_P D DA S 15_P D DA S 12_P D DA S 8_P D DA AA 15_P D S 2_P D DA A A S 30_P D DA AA 24_P D S 27_P D DA A B AA 23_P D S 24_P D DA AA 21_P D S 21_P D DA S 10_P D DA AA 14_P D S 0_P D DA A C GD N GD N AA 22_P D S 20_P D DA S 17_P D DA AA 18_P D AA 17_P D S 9_P D DA S 5_P D DA S 4_P D DA S 1_P D DA AA 10_P D A D GD N GD N S 22_P D DA S 19_P D DA S 16_P D DA S 14_P D DA S 11_P D DA S 7_P D DA S Q 0_P D DS A S 3_P D DA DM A Q 3_P D DM A Q 0_P D 1 2 3 4 5 6 7 8 9 10 11 12 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-44 Freescale Semiconductor Signal Descriptions and Pin Assignments Table 5-6. i.MX27 Full Package MAPBGA Pin Assignment (4 of 4) GD N GD N GD N ND6 VD U B TG IR K S O _D _ P WR N E O E _O _R P O 7A E _ _R W _P 2 S T_P D EA PD A P WR U O E _C T_P O C S _P D X L32K A S 32V S A TA _P D A D N GD N GD N FP V S A M S _P D ND6 VD A _D TA TA A 6_FE ATA_D TA2_S A D C D _P 8_P _M IO D 3_D D A 2_P 4_P D A D S 3_C _E T D LK TM S 3_C D D _ D M _P 0 R C P T15_P P AEK D PD A 1 GD N GD N M LLV S A P S _P D A _D TA T TA A 10_E FU E D _P D F S V S A M A E K P S V D A U E S _P D TR C P T9_ D 12 A _D TA D A _D TA D TA A 0_S TA A 1_S R 3_D D A 3_D D A 0_P 2_P D 1_P 3_P D M LLV D A P D _P D A S _P D VS A A _D TA T TA A 14_E M AEK P TR C P T5_ D 16 A _D TA T A _D TA T TA A 4_E TA A 5_E A _D TA D TA A 3_S M A E K 14_ M A E K 13_ TR C P T TR C P T 3_D D A 3_P 5_P D P6 D P7 D T A D _P D VD A BO A O T2_P D IO 16_A _IN IS TA T R _P A Q F9_P D A _D TA T A _D TA T A _D TA T TA A 8_E TA A 12_E TA A 7_E M A E K 11_ M A E K 7_P M A E K _ U TR C P T TR C P T12 TR C P T P 10 D D 14 P9 D ND4 VD QD VD QD VD QD VD ND5 VD ND5 VD P _P E TA B C O _A _ O C _TEST_ S 26M U R N F7_ FFE _E _P PD A PD A A _D TA T TA A 9_E BO A M AEK _ V O T0_P D TR C P T10 P 11 D S W _B A D E _P D C 5_B TM A S _E TR A B _P D C 3_B A C C _P S _P D E LK F22_P E 0_B A D P _B D T _ C V 2_A A P _C 1_B TA C D _A P _V 2_A _D C S TA D A K F11_P M C _P A E T_60M A _D R F20_P X _P D IO _P A F13_P D 0_P A A D D A _D TA T A _D TA T TA A 11_E TA A 13_E M A E K 8_P M R C P T6_P W TR C P T TAEK D 13 D 15 DM A Q 2_P D S CE A D K 1_P D C 2_B A S _P D LB _B A A _P D O _B A E _P D P _W IT_B T P _P R N T C A _A C W O _A A _D 2_P A A S F18_P A A F16_P _C 1_P D D BO A O T3_P D A _D TA T TA A 15_E B O A M R C P T4_P Y O T1_P D T A E K F23 RST U _ E E _O T_B O C D _P D X L26M A S 26V D A TA _P D A A P 17_P D EA R S _P D A _B A C 1_B A S _P D B LK A C _P D C M D 0_P DC M D 1_P D LK O E A LK O E A O C S _P D E TA _P D A S 26V S A X L26M A B C S _P D A _B A S CE A D K 0_P D R _B A W _P D E B _P D C _B A E 1_B A B _P D P _C 2_B TA C D _A P _R T_A _R C S TA JTA _C L_P G TR A P _V 1_A _D C S TA R S T _B A E E _IN _P _D W F19_P IO _P A E E _P 10_P S T_B F D A F14_P D 1_P A D D A D GD N GD N A C S C _P D D LK A C 4_B TM A S _E TR S C _P D C S N _P D LK A _B E Y C F21_ C 0_B A S _P D PD A P _B D T _ C V 1_A A P _R A Y TA C E D _A C O F15_P LK _P A P _R _B TA C W _A _ E T_266M A X _P D DAQ F P M R _P 12_ P R _P D O _B A D _C 0_P S F17_P D A IO D _P A R Y F8_P D A D GD N GD N A D 13 14 15 16 17 18 19 20 21 22 23 24 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 5-45 Signal Descriptions and Pin Assignments MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 5-46 Freescale Semiconductor Chapter 6 General-Purpose I/O (GPIO) 6.1 Introduction The GPIO module in i.MX27 processor provides six general purpose I/O (GPIO) ports (PA, PB, PC, PD, PE, and PF). Each GPIO port is a 32-bit port that may be multiplexed with one or more dedicated functions. This chapter contains the description of the top level i.MX27 I/O multiplexing strategy that consists of two parts: • Software controllable multiplexing done in the GPIO module • Hardware multiplexing done by the IOMUX module The I/O multiplexing strategy is designed to configure the inputs and outputs of the BONO Device chip in different modes. It allows a user to use the same I/O pad for alternative purposes of the chip. The design of I/O multiplexer is targeted to be as flexible as possible. Refer to Chapter 5, “Signal Descriptions and Pin Assignments” for detailed I/O multiplexing information. Figure 6-1 shows the block diagram of the GPIO and IOMUX modules’ partition at the top level of the BONO processor. Figure 6-2 shows a block diagram of an individual port of the GPIO module. NOTE A_IN, B_IN, C_IN, A_OUT, and B_OUT are internal signals and do not represent individual port signals. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-1 General-Purpose I/O (GPIO) IOMUX (Part of GPIO) Primary Function 0 Alternate Function 1 GP GOUT A_IN B_IN C_IN GDIR A_OUT B_OUT PUEN MUX 1 GPIO INUSE Pin MUX 0 I/O 1 MUX 0 GIN Figure 6-1. Functional Block Diagram of GPIO MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-2 Freescale Semiconductor General-Purpose I/O (GPIO) OCR1 OCR2 A_IN[i] MUX B_IN[i] C_IN[i] DDIR[i] G_DIR[31:0] G_DIR[i] G_OUT [i] PAD G_IN[i] i DR ICONFA1 ICONFA2 SSR A_OUT[i] ISR[i] 1’b0 1’b1 MUX Interrupt Module ISR ICONFB1 ICONFB2 B_OUT[i] ISR[i] 1’b0 1’b1 MUX ICR1 ICR2 IMR GP IN_USE_RESET_SEL [31:0] GIUS GPR[31:0] IN_USE[31:0] PUEN PUEN[31:0] Figure 6-2. GPIO Block Diagram for an Individual Port 6.2 Overview The GPIO module provides General Purpose I/O capability to the device. Each I/O port can be programmed as either a general purpose input or general purpose output. In addition to GPIO functionality, pins can be changed from their default dedicated functions to alternate functions. Input and output signals of peripherals are connected to the IOMUX module at the dedicated (primary) or alternate inputs. In the output direction, one out of three alternate sources (originating from peripherals) can be selected. From the input direction, one out of two alternate destinations (input to a peripheral) can be selected. 6.3 GPIO Features The following list contains the GPIO features: • Six 32-bit ports, each with direction-configurable pins MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-3 General-Purpose I/O (GPIO) • • • • • • • • • • Software control for input/output pin configuration through 32-bit direction register Software control for multiplexing one out of four different sources for every output. Three of them are functional pins from internal modules while the fourth is from the data register of the module. Software control for routing of every input to two different destinations Input data can be sampled to the data register. Inputs can be internally tied to a logic 1 or 0 to ensure any transitions attempted to be processed are ignored. One 32-bit general purpose register is dedicated to each GPIO port. These registers may be used for software control of IOMUX block of the GPIO. Every input is configurable as an interrupt and each interrupt can be defined as either: — Rising-edge triggered — Falling-edge triggered — Level sensitive The interrupts can be masked using a 32-bit mask register. Two levels of interrupt masking are provided. Interrupts can be individually masked at the bit level or at the port level. Software reset function: when the SWR bit (SWR register, 0 bit) is written as a 1, the entire GPIO module is reset immediately, and this reset signal is asserted for three system cycles. After this, the reset signal will be released automatically. 6.4 External Signals Description Refer to Chapter 5, “Signal Descriptions and Pin Assignments” for details on the I/O multiplexing scheme and external connection to the GPIO module. 6.5 Interrupts Every external input passes through the interrupt module in the GPIO module. Inside this module, the interrupts may be defined as rising-edge triggered, or falling-edge triggered. Each interrupt can be masked and also be designated as a high-level interrupt, or a low-level sensitive interrupt. The interrupt status register bits corresponding to the interrupts waiting for service are stored as a value of 1. The interrupt status register is Write 1 to Clear (w1c). The user is responsible for clearing the interrupt status register bit after it has been serviced. 6.6 Memory Map and Register Definitions The GPIO module has six ports and each port has 17 registers. In total, the GPIO has 102 registers. The registers, other than the Sample Status Register (SSR) and the Interrupt Status Register (ISR), have both read and write capability. The Sample Status Register is a read only register, while the Interrupt Status Register is a w1c register; the register can be read, but writing a 1 to any register bit clears the bit. Writing a value of 0 to the bit has no effect. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-4 Freescale Semiconductor General-Purpose I/O (GPIO) While there are six GPIO ports, each capable of representing 32 GPIO configurable pins as inputs or outputs, not all bits are mapped to a pin and hence these bits do not have any effect and are marked as reserved. These reserved bits are indicated in Section 6.6.10, “GPIO IN USE Registers (GIUS).” Table 6-1 shows the GPIO memory map. Table 6-1. GPIO Memory Map Address Register General Registers 0x1001_5000 (PTA_DDIR) 0x1001_5100 (PTB_DDIR) 0x1001_5200 (PTC_DDIR) 0x1001_5300 (PTD_DDIR) 0x1001_5400 (PTE_DDIR) 0x1001_5500 (PTF_DDIR) 0x1001_5004 (PTA_OCR1) 0x1001_5104 (PTB_OCR1) 0x1001_5204 (PTC_OCR1) 0x1001_5304 (PTD_OCR1) 0x1001_5404 (PTE_OCR1) 0x1001_5504 (PTF_OCR1) 0x1001_5008 (PTA_OCR2) 0x1001_5108 (PTB_OCR2) 0x1001_5208 (PTC_OCR2) 0x1001_5308 (PTD_OCR2) 0x1001_5408 (PTE_OCR2) Data Direction Register Data Direction Register Data Direction Register Data Direction Register Data Direction Register Data Direction Register Output Configuration Register 1) Output Configuration Register 1 Output Configuration Register 1) Output Configuration Register 1 Output Configuration Register 1 Output Configuration Register 1 Output Configuration Register 2 Output Configuration Register 2 Output Configuration Register 2 Output Configuration Register 2 Output Configuration Register 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 6.6.2/6-11 6.6.2/6-11 6.6.2/6-11 6.6.2/6-11 6.6.2/6-11 6.6.2/6-11 6.6.3/6-11 6.6.3/6-11 6.6.3/6-11 6.6.3/6-11 6.6.3/6-11 6.6.3/6-11 6.6.4/6-12 6.6.4/6-12 6.6.4/6-12 6.6.4/6-12 6.6.4/6-12 Access Reset Value Section/Page MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-5 General-Purpose I/O (GPIO) Table 6-1. GPIO Memory Map (continued) Address 0x1001_5508 (PTF_OCR2) 0x1001_500C (PTA_ICONFA1) 0x1001_510C (PTB_ICONFA1) 0x1001_520C (PTC_ICONFA1) 0x1001_530C (PTD_ICONFA1) 0x1001_540C (PTE_ICONFA1) 0x1001_550C (PTF_ICONFA1) 0x1001_5010 (PTA_ICONFA2) 0x1001_5110 (PTB_ICONFA2) 0x1001_5210 (PTC_ICONFA2) 0x1001_5310 (PTD_ICONFA2) 0x1001_5410 (PTE_ICONFA2) 0x1001_5510 (PTF_ICONFA2) 0x1001_5014 (PTA_ICONFB1) 0x1001_5114 (PTB_ICONFB1) 0x1001_5214 (PTC_ICONFB1) 0x1001_5314 (PTD_ICONFB1) 0x1001_5414 (PTE_ICONFB1) 0x1001_5514 (PTF_ICONFB1) 0x1001_5018 (PTA_ICONFB2) Register Output Configuration Register 2 Input Configuration Register A1 Input Configuration Register A1 Input Configuration Register A1 Input Configuration Register A1 Input Configuration Register A1 Input Configuration Register A1 Input Configuration Register A2 Input Configuration Register A2 Input Configuration Register A2 Input Configuration Register A2 Input Configuration Register A2 Input Configuration Register A2 Input Configuration Register B1 Input Configuration Register B1 Input Configuration Register B1 Input Configuration Register B1 Input Configuration Register B1 Input Configuration Register B1 Input Configuration Register B2 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0000 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF Section/Page 6.6.4/6-12 6.6.5/6-13 6.6.5/6-13 6.6.5/6-13 6.6.5/6-13 6.6.5/6-13 6.6.5/6-13 6.6.6/6-14 6.6.6/6-14 6.6.6/6-14 6.6.6/6-14 6.6.6/6-14 6.6.6/6-14 6.6.7/6-15 6.6.7/6-15 6.6.7/6-15 6.6.7/6-15 6.6.7/6-15 6.6.7/6-15 6.6.8/6-16 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-6 Freescale Semiconductor General-Purpose I/O (GPIO) Table 6-1. GPIO Memory Map (continued) Address 0x1001_5118 (PTB_ICONFB2) 0x1001_5218 (PTC_ICONFB2) 0x1001_5318 (PTD_ICONFB2) 0x1001_5418 (PTE_ICONFB2) 0x1001_5518 (PTF_ICONFB2) 0x1001_501C (PTA_DR) 0x1001_511C (PTB_DR) 0x1001_521C (PTC_DR) 0x1001_531C (PTD_DR) 0x1001_541C (PTE_DR) 0x1001_551C (PTF_DR) 0x1001_5020 (PTA_GIUS) 0x1001_5120 (PTB_GIUS) 0x1001_5220 (PTC_GIUS) 0x1001_5320 (PTD_GIUS) 0x1001_5420 (PTE_GIUS) 0x1001_5520 (PTF_GIUS) 0x1001_5024 (PTA_SSR) 0x1001_5124 (PTB_SSR) 0x1001_5224 (PTC_SSR) Register Input Configuration Register B2 Input Configuration Register B2 Input Configuration Register B2 Input Configuration Register B2 Input Configuration Register B2 Data Register Data Register Data Register Data Register Data Register Data Register GPIO In Use Register A GPIO In Use Register B GPIO In Use Register C GPIO In Use Register D GPIO In Use Register E GPIO In Use Register F Sample Status Register Sample Status Register Sample Status Register Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R Reset Value 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFFF_FFFF 0xFF3F_FFF3 0xFFFF_FFFF 0xFFFE_0000 0xFFFC_0F27 0xFF00_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 6.6.8/6-16 6.6.8/6-16 6.6.8/6-16 6.6.8/6-16 6.6.8/6-16 6.6.9/6-17 6.6.9/6-17 6.6.9/6-17 6.6.9/6-17 6.6.9/6-17 6.6.9/6-17 6.6.11/6-19 6.6.11/6-19 6.6.11/6-19 6.6.11/6-19 6.6.11/6-19 6.6.11/6-19 6.6.12/6-22 6.6.12/6-22 6.6.12/6-22 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-7 General-Purpose I/O (GPIO) Table 6-1. GPIO Memory Map (continued) Address 0x1001_5324 (PTD_SSR) 0x1001_5424 (PTE_SSR) 0x1001_5524 (PTF_SSR) 0x1001_5028 (PTA_ICR1) 0x1001_5128 (PTB_ICR1) 0x1001_5228 (PTC_ICR1) 0x1001_5328 (PTD_ICR1) 0x1001_5428 (PTE_ICR1) 0x1001_5528 (PTF_ICR1) 0x1001_502C (PTA_ICR2) 0x1001_512C (PTB_ICR2) 0x1001_522C (PTC_ICR2) 0x1001_532C (PTD_ICR2) 0x1001_542C (PTE_ICR2) 0x1001_552C (PTF_ICR2) 0x1001_5030 (PTA_IMR) 0x1001_5130 (PTB_IMR) 0x1001_5230 (PTC_IMR) 0x1001_5330 (PTD_IMR) 0x1001_5430 (PTE_IMR) Register Sample Status Register Sample Status Register Sample Status Register Interrupt Configuration Register 1 Interrupt Configuration Register 1 Interrupt Configuration Register 1 Interrupt Configuration Register 1 Interrupt Configuration Register 1 Interrupt Configuration Register 1 Interrupt Configuration Register 2 Interrupt Configuration Register 2 Interrupt Configuration Register 2 Interrupt Configuration Register 2 Interrupt Configuration Register 2 Interrupt Configuration Register 2 Interrupt Mask Register Interrupt Mask Register Interrupt Mask Register Interrupt Mask Register Interrupt Mask Register Access R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 6.6.12/6-22 6.6.12/6-22 6.6.12/6-22 6.6.13/6-23 6.6.13/6-23 6.6.13/6-23 6.6.13/6-23 6.6.13/6-23 6.6.13/6-23 6.6.14/6-24 6.6.14/6-24 6.6.14/6-24 6.6.14/6-24 6.6.14/6-24 6.6.14/6-24 6.6.15/6-25 6.6.15/6-25 6.6.15/6-25 6.6.15/6-25 6.6.15/6-25 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-8 Freescale Semiconductor General-Purpose I/O (GPIO) Table 6-1. GPIO Memory Map (continued) Address 0x1001_5530 (PTF_IMR) 0x1001_5034 (PTA_ISR) 0x1001_5134 (PTB_ISR) 0x1001_5234 (PTC_ISR) 0x1001_5334 (PTD_ISR) 0x1001_5434 (PTE_ISR) 0x1001_5534 (PTF_ISR) 0x1001_5038 (PTA_GPR) 0x1001_5138 (PTB_GPR) 0x1001_5238 (PTC_GPR) 0x1001_5338 (PTD_GPR) 0x1001_5438 (PTE_GPR) 0x1001_5538 (PTF_GPR) 0x1001_503C (PTA_SWR) 0x1001_513C (PTB_SWR) 0x1001_513C (PTB_SWR) 0x1001_533C (PTD_SWR) 0x1001_543C (PTE_SWR) 0x1001_553C (PTF_SWR) 0x1001_5040 (PTA_PUEN) Register Interrupt Mask Register Interrupt Status Register Interrupt Status Register Interrupt Status Register Interrupt Status Register Interrupt Status Register Interrupt Status Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register Software Reset Register Software Reset Register Software Reset Register Software Reset Register Software Reset Register Software Reset Register Pull-Up Enable Register Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R/W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFFF_FFFF Section/Page 6.6.15/6-25 6.6.16/6-26 6.6.16/6-26 6.6.16/6-26 6.6.16/6-26 6.6.16/6-26 6.6.16/6-26 6.6.17/6-27 6.6.17/6-27 6.6.17/6-27 6.6.17/6-27 6.6.17/6-27 6.6.17/6-27 6.6.18/6-28 6.6.18/6-28 6.6.18/6-28 6.6.18/6-28 6.6.18/6-28 6.6.18/6-28 6.6.19/6-29 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-9 General-Purpose I/O (GPIO) Table 6-1. GPIO Memory Map (continued) Address 0x1001_5140 (PTB_PUEN) 0x1001_5240 (PTC_PUEN) 0x1001_5340 (PTD_PUEN) 0x1001_5440 (PTE_PUEN) 0x1001_5540 (PTF_PUEN) 0x1001_5600 (PMASK) Register Pull-Up Enable Register Pull-Up Enable Register Pull-Up Enable Register Pull-Up Enable Register Pull-Up Enable Register Port Interrupt Mask Register Access R/W R/W R/W R/W R/W R/W Reset Value 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0x0000_003F Section/Page 6.6.19/6-29 6.6.19/6-29 6.6.19/6-29 6.6.19/6-29 6.6.19/6-29 6.6.20/6-30 6.6.1 Register Summary The conventions in Figure 6-3 and Table 6-2 serve as a key for the register summary and individual register diagrams. Always reads 1 1 Always reads 0 0 Write 1 BIT Self-clear 0 R/W BIT Read- BIT Writebit BIT bit only bit only bit BIT to clear w1c N/A Figure 6-3. Key to Register Fields Table 6-2 provides a key for register figures and tables and the register summary. Table 6-2. Register Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types R W R/W rwm w1c Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr) Reset Values 0 1 Resets to zero. Resets to one. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-10 Freescale Semiconductor General-Purpose I/O (GPIO) Table 6-2. Register Conventions (continued) Convention — u [signal_name] Undefined at reset. Unaffected by reset. Reset value is determined by polarity of indicated signal. Description 6.6.2 Data Direction Register (PTn_DDIR) The Data Direction registers determine whether each port pin operates as an input or an output pin. Figure 6-4 shows the register and Table 6-3 provides its field descriptions. 0x1001_5000 (PTA_DDIR) 0x1001_5100 (PTB_DDIR) 0x1001_5200 (PTC_DDIR) 0x1001_5300 (PTD_DDIR) 0x1001_5400 (PTE_DDIR) 0x1001_5500 (PTF_DDIR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R DDIR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DDIR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-4. Data Direction Register (PTn_DDIR) Table 6-3. Data Direction Register Field Descriptions Field 31–0 DDIR Description Data Direction. This is a read/write register that defines the current direction of the 32 pins of a port in the GPIO module. 0 Pin operates as an input. 1 Pin operates as an output. 6.6.3 Output Configuration Register 1 (OCR1) Each port consists of 32-pins. Because the output configuration for each pin is described using a two-bit combination the output configuration of the pins is controlled by two identical 32-bit registers (OCR1 and OCR2). The Output Configuration register 1 (OCR1) configures the output signal for lower 16 pins (0–15) of the associated port. Figure 6-5 shows the register and Table 6-4 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-11 General-Purpose I/O (GPIO) 0x1001_5004 (PTA_OCR1) 0x1001_5104 (PTB_OCR1) 0x1001_5204 (PTC_OCR1) 0x1001_5304 (PTD_OCR1) 0x1001_5404 (PTE_OCR1) 0x1001_5504 (PTF_OCR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 15 0 0 PIN 14 0 0 PIN 13 0 0 PIN 12 0 0 OCR1 PIN 11 0 0 0 PIN 10 0 0 PIN 9 0 PIN 8 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 PIN 7 0 0 PIN 6 0 PIN 5 0 0 0 PIN 4 0 OCR1 PIN 3 0 0 0 PIN 2 0 0 PIN 1 0 PIN 0 0 0 Figure 6-5. Output Configuration Register 1 (OCR1) Table 6-4. Output Configuration Register 1 Field Descriptions Field 31–0 OCR1 Description Output Configuration Register 1. Each field selects how each pin (0–15) is used as an output by the GPIO. 00 Input A_IN output selected. 01 Input B_IN output selected. 10 Input C_IN output selected. 11 Data Register output selected. 6.6.4 Output Configuration Register 2 (OCR2) The Output Configuration register 2 (OCR2) specifies the output signal for upper 16 pins (16–31) of the associated port. The output configuration for each pin is described with a two-bit combination. Figure 6-6 shows the register and Table 6-5 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-12 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5008 (PTA_OCR2) 0x1001_5108 (PTB_OCR2) 0x1001_5208 (PTC_OCR2) 0x1001_5308 (PTD_OCR2) 0x1001_5408 (PTE_OCR2) 0x1001_5508 (PTF_OCR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 31 0 0 PIN 30 0 0 PIN 29 0 0 PIN 28 0 0 OCR2 PIN 27 0 0 0 PIN 26 0 PIN 25 0 0 PIN 24 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset PIN 23 0 0 PIN 22 0 0 PIN 21 0 0 PIN 20 0 0 OCR2 PIN 19 0 0 0 PIN 18 0 PIN 17 0 0 PIN 16 0 0 Figure 6-6. Output Configuration Register 2 (OCR2) Table 6-5. Output Configuration Register 2 Field Descriptions Field 31–0 OCR2 Description Output Configuration Register 2. Each field selects how each pin (16–31) is used as an output by the GPIO. 00 Input A_IN output selected. 01 Input B_IN output selected. 10 Input C_IN output selected. 11 Data Register output selected. 6.6.5 Input Configuration Register A1 (ICONFA1) The input configuration registers (ICONFA1) specify the signal or value driven to the A_OUT signals that is connected to internal modules of the BONO Device processor. Each port pin is defined by two bits in the input configuration registers. Figure 6-7 shows the register and Table 6-6 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-13 General-Purpose I/O (GPIO) 0x1001_500C (PTA_ICONFA1) 0x1001_510C (PTB_ICONFA1) 0x1001_520C (PTC_ICONFA1) 0x1001_530C (PTD_ICONFA1) 0x1001_540C (PTE_ICONFA1) 0x1001_550C (PTF_ICONFA1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 15 1 1 PIN 14 1 1 PIN 13 1 1 PIN 12 1 ICONFA1 PIN 11 1 1 1 PIN 10 1 1 PIN 9 1 PIN 8 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 1 PIN 7 1 1 PIN 6 1 PIN 5 1 1 1 PIN 4 ICONFA1 PIN 3 1 1 1 1 PIN 2 1 1 PIN 1 1 PIN 0 1 1 Figure 6-7. Input Configuration Register A1 (ICONFA1) Table 6-6. Input Configuration Register A1 Field Descriptions Field 31–0 ICONFA1 Description Input Configuration. Corresponds to port pins 0–15 and defines which one of the four options is driven to A_OUT. Each port pin requires two ICONFA1 bits to determine the input value. 00 GPIO_In 01 Interrupt Status Register 10 0 11 1 6.6.6 Input Configuration Register A2 (ICONFA2) The input configuration registers (ICONFA2) specify the signal or value driven to the A_OUT signals connected to internal modules. There are two bits in the input configuration registers for each port pin. Figure 6-8 shows the register and Table 6-7 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-14 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5010 (PTA_ICONFA2) 0x1001_5110 (PTB_ICONFA2) 0x1001_5210 (PTC_ICONFA2) 0x1001_5310 (PTD_ICONFA2) 0x1001_5410 (PTE_ICONFA2) 0x1001_5510 (PTF_ICONFA2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 31 1 1 PIN 30 1 1 PIN 29 1 1 PIN 28 1 ICONFA2 PIN 27 1 1 1 PIN 26 1 PIN 25 1 1 PIN 24 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset PIN 23 1 1 PIN 22 1 1 PIN 21 1 1 PIN 20 1 ICONFA2 PIN 19 1 1 1 PIN 18 1 PIN 17 1 1 PIN 16 1 1 1 Figure 6-8. Input Configuration Register A2 (ICONFA2) Table 6-7. Input Configuration Register A2 Field Descriptions Field 31–0 ICONFA2 Description Input Configuration. Corresponds to port pins 16–31 and defines which one of the four options is driven to A_OUT. Each port pin requires two ICONFA2 bits to determine the input value. 00 GPIO_In 01 Interrupt Status Register 10 0 11 1 6.6.7 Input Configuration Register B1 (ICONFB1) The input configuration registers ICONFB1 specify the signal or value driven to the B_OUT signals connected to internal modules. There are two bits in the input configuration registers for each port pin. Figure 6-9 shows the register and Table 6-8 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-15 General-Purpose I/O (GPIO) 0x1001_5014 (PTA_ICONFB1) 0x1001_5114 (PTB_ICONFB1) 0x1001_5214 (PTC_ICONFB1) 0x1001_5314 (PTD_ICONFB1) 0x1001_5414 (PTE_ICONFB1) 0x1001_5514 (PTF_ICONFB1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 15 1 1 PIN 14 1 1 PIN 13 1 1 PIN 12 1 ICONFB1 PIN 11 1 1 1 PIN 10 1 1 PIN 9 1 PIN 8 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 1 PIN 7 1 1 PIN 6 1 PIN 5 1 1 1 PIN 4 ICONFB1 PIN 3 1 1 1 1 PIN 2 1 1 PIN 1 1 PIN 0 1 1 Figure 6-9. Input Configuration Register B1 (ICONFB1) Table 6-8. Input Configuration Register B1 Field Descriptions Name 31–0 ICONFB1 Description Input Configuration. Corresponds to pins 0–15 of the port and defines which one of the four options is driven to b_OUT. Each port pin requires two ICONFB1 bits to determine the input value. 00 GPIO_IN 01 Interrupt Status register 10 0 11 1 6.6.8 Input Configuration Register B2 (ICONFB2) The input configuration registers ICONFB2 specify the signal or value driven to the B_OUT signals connected to internal modules. There are two bits in the input configuration registers for each port pin. Figure 6-10 shows the register and Table 6-9 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-16 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5018 (PTA_ICONFB2) 0x1001_5118 (PTB_ICONFB2) 0x1001_5218 (PTC_ICONFB2) 0x1001_5318 (PTD_ICONFB2) 0x1001_5418 (PTE_ICONFB2) 0x1001_5518 (PTF_ICONFB2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 31 1 1 PIN 30 1 1 PIN 29 1 1 PIN 28 1 ICONFB2 PIN 27 1 1 1 PIN 26 1 PIN 25 1 1 PIN 24 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset PIN 23 1 1 PIN 22 1 1 PIN 21 1 1 PIN 20 1 ICONFB2 PIN 19 1 1 1 PIN 18 1 PIN 17 1 1 PIN 16 1 1 1 Figure 6-10. Input Configuration Register B1 (ICONFB2) Table 6-9. Input Configuration Register B2 Description Name 31–0 ICONFB2 Description Input Configuration. Corresponds to pins 16–31 of the port and defines which one of the four options is driven to b_OUT. Each port pin requires two ICONFB2 bits to determine the input value. 00 GPIO_IN 01 Interrupt Status register 10 0 11 1 6.6.9 Data Register (DR) The Data Register holds data for output from an associated port when a pin is configured as an output and the Data Register is chosen using Output Configuration Register 1 and Output Configuration Register 2. Figure 6-11 shows the register and Table 6-10 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-17 General-Purpose I/O (GPIO) 0x1001_501C (PTA_DR) 0x1001_511C (PTB_DR) 0x1001_521C (PTC_DR) 0x1001_531C (PTD_DR) 0x1001_541C (PTE_DR) 0x1001_551C (PTF_DR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R DR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-11. Data Register (DR) Table 6-10. Data Register Field Descriptions Field 31–0 DR Description Data Register. Contains the GPIO output values when the Output Configuration Registers select the Data Register as the output for the pin (selection 11). 0 Drives the output signal is low. 1 Drives the output signal is high. 6.6.10 GPIO IN USE Registers (GIUS) The GPIO In Use Registers control a multiplexer in the IOMUX module. The settings in these registers choose whether a pin is utilized for a peripheral function or for its GPIO function. If the register is set to a zero for a corresponding pin, then this register is used in conjunction with the GPR register to control the peripheral functionality. Figure 6-12 shows a GIUS overview register and Table 6-11 provides field descriptions of the GIUS registers. Reset values for individual registers are shown in the following sections. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-18 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5020 (PTA_GIUS) 0x1001_5120 (PTB_GIUS) 0x1001_5220 (PTC_GIUS) 0x1001_5320 (PTD_GIUS) 0x1001_5420 (PTE_GIUS) 0x1001_5520 (PTF_GIUS) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R GIUS W Reset1 — — — — — — — — — — — — — — — — 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GIUS W Reset1 — — — — — — — — — — — — — — — — 1 The reset value of this register is determined by the input value of the signal INUSE_RESET_SEL [31:0]. Figure 6-12. GPIO IN USE Register (GIUS) Table 6-11. GPIO In Use Register Field Descriptions Field 31–0 GIUS Description GPIO In Use. Informs the IOMUX module whether the port pin is utilized for its GPIO function. When the pin is utilized for its GPIO function, the multiplexed functions are not available. The reset value of this register is determined by the input value of the signal INUSE_RESET_SEL [31:0]. 0 Pin utilized for multiplexed function 1 Pin utilized for GPIO function 6.6.11 GPIO IN USE Register Reset Values The following sections describe the GPIO In Use (GIUS) reset values for the various ports. Additionally, the registers also indicate the reserved bits (unimplemented GPIO bits) of the GPIO ports. 6.6.11.1 GPIO IN USE Register A (PTA_GIUS) The reset value of the PTA_GIUS register is (0xFFFF_FFFF). Figure 6-13 shows the register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-19 General-Purpose I/O (GPIO) 0x1001_5020 (PTA_GIUS) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R GIUS W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GIUS W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-13. GPIO IN USE Register A Reset Values (PTA_GIUS) 6.6.11.2 GPIO IN USE Register B (PTB_GIUS) The reset value of the PTB_GIUS register is (0xFF3F_FFF3). Figure 6-14 shows the register. 0x1001_5120 (PTB_GIUS) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R GIUS W Reset 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GIUS W Reset 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 Figure 6-14. GPIO IN USE Register B Reset Values (PTB_GIUS) 6.6.11.3 GPIO IN USE Register C (PTC_GIUS) The reset value of the PTC_GIUS register is (0xFFFF_FFFF). Figure 6-15 shows the register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-20 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5220 (PTC_GIUS) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R GIUS W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GIUS W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-15. GPIO IN USE Register C Reset Values (PTC_GIUS) 6.6.11.4 GPIO IN USE Register D (PTD_GIUS) The reset value of the PTD_GIUS register is (0xFFFE_0000). Figure 6-16 shows the register. 0x1001_5320 (PTD_GIUS) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R GIUS W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GIUS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-16. GPIO IN USE Register D Reset Values (PTD_GIUS) 6.6.11.5 GPIO IN USE Register E (PTE_GIUS) The reset value of the PTE_GIUS register is (0xFFFC_0F27). Figure 6-17 shows the register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-21 General-Purpose I/O (GPIO) 0x1001_5420 (PTE_GIUS) 31 30 29 28 27 26 25 24 1 Access: User R/W 23 22 21 20 19 18 17 16 R GIUS W Reset 1 1 1 1 1 1 1 GIUS 1 1 1 1 1 1 1 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GIUS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-17. GPIO IN USE Register E Reset Values (PTE_GIUS) 6.6.11.6 GPIO IN USE Register F (PTF_GIUS) The reset value of the PTF_GIUS register is (0xFF00_0000). Figure 6-17 shows the register. 0x1001_5520 (PTF_GIUS) 31 30 1 Access: User R/W 27 26 1 29 28 1 25 24 1 23 22 21 20 19 18 17 16 R W Reset 1 1 1 1 0 GIUS 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GIUS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-18. GPIO IN USE Register F Reset Values (PTF_GIUS) 6.6.12 Sample Status Register (SSR) The read-only Sample Status Registers contain the value of the GPIO pins for each associated port. The register is updated on every clock tick. The contents are used as a status indicator when the pins are configured as inputs. Figure 6-19 shows the register and Table 6-12 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-22 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5024 (PTA_SSR) 0x1001_5124 (PTB_SSR) 0x1001_5224 (PTC_SSR) 0x1001_5324 (PTD_SSR) 0x1001_5424 (PTE_SSR) 0x1001_5524 (PTF_SSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-only 18 17 16 R W Reset 0 0 0 0 0 0 0 0 SSR 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 SSR 0 0 0 0 0 0 0 0 Figure 6-19. Sample Status Register (SSR) Table 6-12. Sample Status Register Field Descriptions Field 31–0 SSR Description Sample Status. Contains the value of the GPIO pin [i]. It is sampled on every clock. 0 Pin value is low. 1 Pin value is high. 6.6.13 Interrupt Configuration Register 1 (ICR1) This register specifies the external interrupt configuration for each of the lower 16 interrupts of a port. There are two bits in the register for each port pin. Figure 6-20 shows the register and Table 6-13 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-23 General-Purpose I/O (GPIO) 0x1001_5028 (PTA_ICR1) 0x1001_5128 (PTB_ICR1) 0x1001_5228 (PTC_ICR1) 0x1001_5328 (PTD_ICR1) 0x1001_5428 (PTE_ICR1) 0x1001_5528 (PTF_ICR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 15 0 0 PIN 14 0 0 PIN 13 0 0 PIN 12 0 0 ICR1 PIN 11 0 0 0 PIN 10 0 0 PIN 9 0 PIN 8 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 PIN 7 0 0 PIN 6 0 PIN 5 0 0 0 PIN 4 0 ICR1 PIN 3 0 0 0 PIN 2 0 0 PIN 1 0 PIN 0 0 0 Figure 6-20. Interrupt Configuration Register 1 (ICR1) Table 6-13. Interrupt Configuration Register 1 Field Descriptions Field 31–0 ICR1 Description Interrupt Configuration. Corresponds to interrupts 0–15 of the port and defines which one of the four options is the sensitivity of the interrupt. Each interrupt [i] (i= 0 through 15) requires two ICR1 bits to determine the sensitivity. 00 Rising edge sensitive 01 Falling edge sensitive 10 High level sensitive 11 Low level sensitive 6.6.14 Interrupt Configuration Register 2 (ICR2) This register specify the external interrupt configuration for each of the upper 16 interrupts of the port. There are two bits in the register for each port pin. Figure 6-21 shows the register and Table 6-14 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-24 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_502C (PTA_ICR2) 0x1001_512C (PTB_ICR2) 0x1001_522C (PTC_ICR2) 0x1001_532C (PTD_ICR2) 0x1001_542C (PTE_ICR2) 0x1001_552C (PTF_ICR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset PIN 31 0 0 PIN 30 0 0 PIN 29 0 0 PIN 28 0 0 ICR2 PIN 27 0 0 0 PIN 26 0 PIN 25 0 0 PIN 24 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset PIN 23 0 0 PIN 22 0 0 PIN 21 0 0 PIN 20 0 0 ICR2 PIN 19 0 0 0 PIN 18 0 PIN 17 0 0 PIN 16 0 0 Figure 6-21. Interrupt Configuration Register 2 (ICR2) Table 6-14. Interrupt Configuration Register 2 Field Descriptions Field 31–0 ICR2 Description Interrupt Configuration. Corresponds to interrupts 16–31 of the port and defines which one of the four options is the sensitivity of the interrupt. Each interrupt requires two ICR2 bits to determine the sensitivity. 00 Rising edge sensitive 01 Falling edge sensitive 10 High level sensitive 11 Low level sensitive 6.6.15 Interrupt Mask Register (IMR) The Interrupt Mask Registers (IMR) determine if an interrupt will be asserted when an interrupt event occurs and when the pin and corresponding bit is configured in an interrupt mode. An interrupt is asserted when corresponding bits in the IMR and ISR are set. Figure 6-22 shows the register and Table 6-15 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-25 General-Purpose I/O (GPIO) 0x1001_5030 (PTA_IMR) 0x1001_5130 (PTB_IMR) 0x1001_5230 (PTC_IMR) 0x1001_5330 (PTD_IMR) 0x1001_5430 (PTE_IMR) 0x1001_5530 (PTF_IMR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R IMR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IMR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-22. Interrupt Mask Register (IMR) Table 6-15. Interrupt Mask Register Description Name 31–0 IMR Description Interrupt Mask. Masks the interrupts for this module. 0 Interrupt is masked. 1 Interrupt is not masked. 6.6.16 Interrupt Status Register (ISR) The Interrupt Status Registers (ISR) indicate if an interrupt has occurred. When an interrupt event occurs, the bit in this register is set. The condition necessary to set the bit is determined by the Interrupt Configuration Registers (ICR) and the inputs satisfying the interrupt condition. Figure 6-23 shows the register and Table 6-16 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-26 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5034 (PTA_ISR) 0x1001_5134 (PTB_ISR) 0x1001_5234 (PTC_ISR) 0x1001_5334 (PTD_ISR) 0x1001_5434 (PTE_ISR) 0x1001_5534 (PTF_ISR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W w1c Reset 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 ISR w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W w1c Reset 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 ISR w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 Figure 6-23. Interrupt Status Register (ISR) Table 6-16. Interrupt Status Register Field Descriptions Field 31–0 ISR Description Interrupt Status. Indicates whether the interrupt [i] has occurred for in the GPIO module. The bits of this register are write 1 to clear. The w1c bit is cleared when a value of 1 is written to the associated bit. 0 Interrupt has not occurred. 1 Interrupt has occurred. 6.6.17 General Purpose Register (GPR) The General Purpose Registers (GPR) control a multiplexer in the IOMUX module. When the corresponding bit in the associated GIUS register is set to zero, the settings in these registers determine whether a pin is utilized for its primary peripheral function or for its alternate peripheral function. When the corresponding bit in the GIUS is set, the settings of this register have no effect. Figure 6-24 shows the register and Table 6-17 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-27 General-Purpose I/O (GPIO) 0x1001_5038 (PTA_GPR) 0x1001_5138 (PTB_GPR) 0x1001_5238 (PTC_GPR) 0x1001_5338 (PTD_GPR) 0x1001_5438 (PTE_GPR) 0x1001_5538 (PTF_GPR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R GPR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GPR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-24. General Purpose Register Table 6-17. General Purpose Register Field Descriptions Field 31–0 GPR Description General Purpose Register. Selects between the primary and alternate functions of the pin. When the associated bit in the GIUS register is set, this bit has no meaning. Note: Ensure that this bit is cleared when there is not an alternate function for the associated pin. 0 Select primary pin function 1 Select alternate pin function 6.6.18 Software Reset Register (SWR) The Software Reset Register (SWR) controls the reset of the individual ports in the GPIO module. When the SWR bit of the Software Reset Register is set, the GPIO circuitry for the individual port resets immediately. The total time of the software reset sequence will take six clock cycles. The reset will be asserted from the third cycle and remains asserted for three clocks. Figure 6-25 shows the register and Table 6-18 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-28 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_503C (PTA_SWR) 0x1001_513C (PTB_SWR) 0x1001_523C (PTC_SWR) 0x1001_533C (PTD_SWR) 0x1001_543C (PTE_SWR) 0x1001_553C (PTF_SWR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-25. Software Reset Register (SWR) Table 6-18. Software Reset Register Field Descriptions Field 31–1 0 SWR Description Reserved. These bits are reserved and should read 0 Software Reset. Controls software reset of the port. The reset signal is active for 3 system clock cycles and then it is released automatically. It is a self-clearing bit. 0 No effect 1 GPIO circuitry for Port X reset 6.6.19 Pull-Up Enable Register (PUEN) The Pull-Up Enable (PUEN) Registers enable or disable a 69 kΩ pull-up resistor on the associated pin. The pull-up can be applied to any GPIO pin regardless of whether it is configured as primary, alternate or GPIO function. The pin is tri-stated when the pull-up is disabled and the pin is not driven. Figure 6-26 shows the register and Table 6-19 provides its field descriptions. NOTE Bits 27–24 on Port A (PTA_PUEN) enables or disables a 69 kΩ pull-down resistor on the associated pin. Bits 31–28, 26, and 9 on Port B (PTB_PUEN) enables or disables a 69 kΩ pull-down resistor on the associated pin. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-29 General-Purpose I/O (GPIO) 0x1001_5040 (PTA_PUEN) 0x1001_5140 (PTB_PUEN) 0x1001_5240 (PTC_PUEN) 0x1001_5340 (PTD_PUEN) 0x1001_5440 (PTE_PUEN) 0x1001_5540 (PTF_PUEN) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R PUEN W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PUEN W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6-26. Pull-Up Enable Register (PUEN) Table 6-19. Pull-Up Enable Register Field Descriptions Field 31–0 PUEN Description Pull-Up Enable. Determines whether the corresponding pad is pulled up to a logic-high or tri-stated. When the pin is configured as an input, clearing this bit causes the signal to be tri-stated when not driven by an external source. When the pin is configured as an output, clearing this bit causes the signal to be tri-stated when it is not enabled. 0 Pin [i] is tri-stated when not driven internally or externally. 1 Pin [i] is pulled high1 when not driven internally or externally. 6.6.20 Port Interrupt Mask Register (PMASK) The GPIO has six ports, each with interrupt generation capability. The PMASK register provides interrupt masking capability at the port level while the Interrupt Mask Register provides control over individual interrupts. If a bit is zero, then all interrupts for that port are masked. A software reset on a port (SWR is set) will clear the corresponding mask bit of the port in this register. Figure 6-27 shows the register and Table 6-20 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-30 Freescale Semiconductor General-Purpose I/O (GPIO) 0x1001_5600 (PMASK) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 PTF PTE 1 PTD 1 PTC 1 PTB 1 PTA 1 0 0 0 0 0 0 0 0 0 0 1 Figure 6-27. Port Interrupt Mask Register (PMASK) Table 6-20. Port Interrupt Mask Register Field Descriptions Field 31–6 5 PTF 4 PTE 3 PTD 2 PTC 1 PTB 0 PTA Description Reserved. These bits are reserved and should read 0. Port F. The bit helps in masking the Port F interrupt. The bit clears during software reset of Port F. 0 Interrupt is masked. 1 Interrupt is not masked. Port E. The bit helps in masking the Port E interrupt. The bit clears during software reset of Port E. 0 Interrupt is masked. 1 Interrupt is not masked. Port D. The bit helps in masking the Port D interrupt. The bit clears during software reset of Port D. 0 Interrupt is masked. 1 Interrupt is not masked. Port C. The bit helps in masking the Port C interrupt. The bit clears during software reset of Port C. 0 Interrupt is masked. 1 Interrupt is not masked. Port B. The bit helps in masking the Port B interrupt. The bit clears during software reset of Port B. 0 Interrupt is masked. 1 Interrupt is not masked. Port A. The bit helps in masking the Port A interrupt. The bit clears during software reset of Port A. 0 Interrupt is masked. 1 Interrupt is not masked. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 6-31 General-Purpose I/O (GPIO) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 6-32 Freescale Semiconductor Chapter 7 JTAG Controller (JTAGC) 7.1 Introduction The JTAG Controller (JTAGC) module supports Debug access to ARM926 core and tri-state enabling of the I/O pads. The JTAGC is compatible with 1EEE1149.1 Standard Test Access Port and Boundary Scan Architecture. 7.2 Features The Test and debug features of JTAG provide the following capabilities: • Provide debug access to ARM926 core and execute its specific JTAG instructions independently • Controls tri-state enable of I/O pads 7.3 Implementation The JTAG Controller consists of the JTAG Controller state machine, Instruction Register (IR), Bypass Register, Boundary Scan Register, Instruction decode, and various user specific data registers collectively reside inside the ExtraDebug register. The TDO output from the JTAG Controller is the muxed output based on whether i.MX27 JTAG Controller or ARM926 Platform JTAG mode is active. It changes on falling edge of TCK. The TDO output enable is selected based on whether i.MX27 JTAG Controller or ARM926 Platform JTAG mode is active. TCK TRST_N TMS TAP_STATE TDI TDO TDO_EN Reset RTI DR IR Capture Shift IR EIR Update RTI Figure 7-1. JTAG Signals Timing Diagram The Test Mode Select (TMS) input from external pin by default connects to the ARM926 Platform after gating with the laser fuse output. At the rising edge of TRST_B, the JTAG_control input controls whether the TMS pin should be connected to ARM926 Platform or to i.MX27 JTAG Controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 7-1 JTAG Controller (JTAGC) When JTAG_control input is HIGH (by default), the TMS pin will be connected to ARM926 Platform after gating with the laser fuse output. The TMS input of i.MX27 JTAG Controller will be held HIGH in this case. When JTAG_control input is LOW, the TMS pin will be connected to i.MX27 JTAG Controller. The TMS input of ARM926 Platform will be held HIGH. • The Test Reset (TRST_B) input from external pin will be connected to both ARM926 Platform and i.MX27 JTAG Controller. • The Test Data Input (TDI) input from external pin will be connected to both ARM926 Platform and i.MX27 JTAG Controller. • The Test Clock (TCK) input from external pin will be connected to both ARM926 Platform and i.MX27 JTAG Controller. 7.4 JTAG Controller Pin List Table 7-1. JTAGC Pin List Pin Name tdo tck Direction Output Input Description Test Data Output TDO is asserted during rising edge of TCK Test Clock Test Clock input is used to synchronize the Test Logic. This includes an internal pull-up resistor. Test Data Input TDI is captured during rising edge of TCK. TDI includes an internal pull-up resistor. Test Mode Select TMS is captured during rising edge of TCK. TMS includes an internal pull-up resistor. TMS input for the ARM926 Platform and JTAG Controller is gated by the system logic. Test Reset TRST_B includes an internal pull-up resistor Table 7-1 provides a list of the JTAGC pins. tdi Input tms Input trst_b Input 7.5 JTAG Overview Figure 7-2 shows the i.MX27 JTAG block diagram. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 7-2 Freescale Semiconductor JTAG Controller (JTAGC) ARM926EJS + ICE ARM JTAG CNTLR TCK TRST_B TDI JTAG_tms JTAG_tdo i.MX27 JTAG Controller TMS TDO Figure 7-2. i.MX27 JTAG Block Diagram 7.6 JTAG Modes Two JTAG modes are created based on the I/O pin JTAG_control. These modes are used to maintain compatibility to ARM MCU Multi-ICETM products as well as maintain IEEE JTAG standards. 7.6.1 ARM926 Platform mode This mode connects the processed TMS input to the ARM926 Platform. TRST_B must be asserted to exit this mode. 7.6.2 i.MX27 JTAG Controller mode This mode will connect the processed TMS input to the i.MX27 JTAG Controller. This will provide a dedicated user-accessible test access port that uses the same communication style as the IEEE1149.1 Standard. TRST_B or POR_B must be asserted to leave this mode. In this mode, i.MX27 JTAG Controller supports the following capabilities: • Query identification information (manufacturer, part number and version) of i.MX27 (IDCODE) • Tri-state I/O pads for iddq test (HIGHZ) • BYPASS instruction 7.7 Boundary Scan Register The boundary scan register (BSR) in the i.MX27 JTAG implementation contains bits for all device signals and clock pins and associated control signals. All i.MX27 bidirectional pins have a single register bit in the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 7-3 JTAG Controller (JTAGC) 7.8 Instruction Register Table 7-2. JTAG Instruction Register Bit2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Bit1 0 1 0 1 0 1 0 1 Bit0 IDCODE SAMPLE/PRELOAD EXTEST ENABLE_ExtraDebug HIGHZ ACCESS_GENERIC_MBIST CLAMP BYPASS Instruction The JTAG Instruction register is 3 bits wide. The settings of the IR is shown in Table 7-2. The instruction register is reset to 3’b000 which is equivalent to the IDCODE instruction. During the capture-IR state, the parallel inputs to the instruction register are loaded with the code 01 in the least significant bits as required by the IEEE standard, the most significant bits are loaded with the values 0, leading to a capture value of 3’b001. 7.8.1 EXTEST Instruction The EXTEST instruction selects the boundary scan register, and the 1149.1 test logic has control of the I/O pins. EXTEST also asserts internal reset for the Core to force a predictable internal state while performing external boundary scan operations. By using the TAP Controller, the register is capable of: • Scanning user-defined values into the output buffers • Capturing values presented to input pins controlling the direction of bidirectional pins • Controlling the output drive of tri-statable output pins For more details on the function and use of EXTEST, refer to the IEEE 1149.1 document. 7.8.2 SAMPLE/PRELOAD Instruction This selects the boundary scan register and the system logic controls the I/O pins. The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the capture-DR Controller state. The data can be observed by shifting it transparently through the boundary scan register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 7-4 Freescale Semiconductor JTAG Controller (JTAGC) NOTE Since there is no internal synchronization between the JTAG clock (TCK) and the system clock (CLK), the user must provide some form of external synchronization to achieve meaningful results. The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output cells prior to selection of EXTEST. This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction. 7.8.3 IDCODE Instruction This selects the ID register and the system logic controls the I/O pins. This instruction is a public instruction to allow the manufacturer, part number and the version of the IC to be available through TAP. Figure 7-3 shows the ID register configuration. 0x0000_7000 (IDCODE) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User R/W 18 17 16 R W Reset 0 Version Information Design Center Part Number Device Number [21:12] 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset Device Number [21:12] MFG 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 0 1 Figure 7-3. ID Register Configuration 7.8.4 ENABLE_ExtraDebug Instruction The ExtraDebug register consists of 44 bits comprising a 40-bits register (maximum), a 3-bit address field and one read/write bit. The register data field does not need to be filled in during register read. The particular ExtraDebug register connected between TDI and TDO is selected by the ExtraDebug Controller based on the currently decoded address during Update_DR state. All communication with the ExtraDebug Controller is done through the Select-DR-Scan path of the i.MX27 JTAG Controller. 7.8.5 HIGHZ Instruction All output drivers, including the two-state drivers, are turned off (that is, high impedance). The instruction selects the bypass register. The HIGHZ instruction also asserts internal reset for the Core to force a predictable internal state while performing external boundary scan operations. In this mode, all internal pull-up resistors on all the pins (except for the TMS TDI TCK TRST COLD_START MUXCTL pins) will be disabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 7-5 JTAG Controller (JTAGC) 7.8.6 CLAMP Instruction Selects the 1-bit bypass register as the serial path between TDI and TDO while allowing signals driven from the component pins to be determined from the boundary scan register. During testing of ICs on PCB, it may be necessary to place static guarding values on signals that control operation of logic not involved in the test. The EXTEST instruction could be used for this purpose, but since it selects the boundary-scan register the required guarding signals would be loaded as part of the complete serial data stream shifted in, both at the start of the test and each time a new test pattern is entered. Since the CLAMP instruction allows guarding values to be applied using the boundary-scan register of the appropriate ICs while selecting their bypass registers, it allows much faster testing than does the EXTEST instruction. Data in the boundary scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its reset state. The CLAMP instruction also asserts internal reset for the Core to force a predictable internal state while performing external boundary scan operations. 7.8.7 BYPASS Instruction Selects the single bit Bypass register and the system logic controls the I/O pins. This creates a shift register path from TDI to the bypass register and finally to TDO. When the bypass register is selected by the current instruction, the shift-register stage is set to a logic zero on the rising edge of TCK in the capture-DR controller state. The first bit to be shifted out after selecting the bypass register will always be a logic zero. 7.9 7.9.1 TMS Sequences TMS Sequence to Check ID Code The following table shows the TMS sequence to check the ID Code value, starting from any point in the state machine. Table 7-1. TMS Sequence To Check ID Code Step 0 1 2 3 4 5 6 7 8 9 x5 x1 x1 x1 x1 x1 x2 x1 x1 x1 TCK 1 0 1 1 0 0 0 1 1 0 TMS State Test Logic Reset Run-Test/Idle Select DR Select IR Capture IR Shift IR Shift Exit1 Update Run-Test/Idle Select Idcode register Shift ’Idcode’ inst.= 3'b010 thru TDI IR Path : Loading ’Idcode’ instr. Comment SEQUENCE IS : IDCODE READ MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 7-6 Freescale Semiconductor JTAG Controller (JTAGC) Table 7-1. TMS Sequence To Check ID Code Step 10 11 12 13 14 15 16 x1 x1 x1 x31 x1 x1 x1 TCK 1 0 0 0 1 1 0 TMS State Select DR Capture DR Shift DR Shift Exit1 Update Run-Test/Idle DR Path: Comment Reading Idcode reg. Capture Idcode value Shift out Idcode on 32bits 7.9.2 TMS Sequence to Write to ExtraDebug Register Table 7-2 shows the TMS sequence to Write to any of the ExtraDebug registers, starting from any point in the state machine. Table 7-2. TMS Sequence to Write to ExtraDebug Register Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x5 x1 x1 x1 x1 x1 x2 x1 x1 x1 x1 x1 x1 x43 x1 x1 x1 TCK 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 1 0 TMS State Test Logic Reset Run-Test/Idle Select DR Select IR Capture IR Shift IR Shift Exit1 Update Run-Test/Idle Select DR Capture DR Shift DR Shift Exit1 Update Run-Test/Idle Write to the ExtraDebug register Shift In Writ bit(1’b0) + Register Address + Data DR Path: Select Extradebug register to write data Select ExtraDebug register Shift ‘Enable ExtraDebug’ inst.= 3'b011 thru TDI IR Path : Select ExtraDebug register. Comment SEQUENCE IS : WRITE ExtraDebug Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 7-7 JTAG Controller (JTAGC) 7.9.3 TMS Sequence to Read ExtraDebug Register The following table shows the TMS sequence to READ any of the ExtraDebug registers, starting from any any point in the state machine. Table 7-3. TMS Sequence to Read ExtraDebug Register Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 x5 x1 x1 x1 x1 x1 x2 x1 x1 x1 x1 x1 x1 x3 x1 x1 x1 x1 x1 x1 x39 x1 x1 x1 TCK 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 1 0 TMS State Test Logic Reset Run-Test/Idle Select DR Select IR Capture IR Shift IR Shift Exit1 Update Run-Test/Idle Select DR Capture DR Shift DR Shift Exit1 Update Run-Test/Idle Select DR Capture DR Shift DR Shift Exit1 Update Run-Test/Idle 2nd DR Path: ExtraDebug Read access Read the ExtraDebug register Shift out the captured value Decode the 4 bits shifted in Shift In Read bit(1’b1) + Register Address DR Path: Select Extradebug register to Read Select ExtraDebug register Shift ’Enable ExtraDebug’ inst.= 3'b011 thru TDI IR Path : Select ExtraDebug register. Comment SEQUENCE IS : READ ExtraDebug Register 7.10 i.MX27 JTAG Restrictions TRST_b must be externally asserted to force the selection of ARM926 Platform TAP or i.MX27 JTAG Controller. During POR_B assertion, ARM926 Platform TAP is selected. If TMS either remains unconnected or connected to VDD, then the TAP controller cannot leave the Test-Logic-Reset state regardless of TCK. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 7-8 Freescale Semiconductor Chapter 8 Bootstrap Mode Operation 8.1 Introduction The bootstrap program is a small program that resides in the internal ROM of the i.MX27 processor. It is activated when the BOOT[3:0] selection pins are set to 4’b0000 or if there is any exception during the HAB checking during boot-up. The bootstrap operation handles the commands from either USB or UART1 to establish a channel to interface the i.MX27 processor’s hardware and the external machine such as PC. It provides the following functions. 1. For HAB Enable-type silicon, it downloads authenticated binary image code to memory so as to execute in run time or perform Flash update. 2. For HAB Disable-type silicon, it downloads binary image code to memory as to execute in run time or perform Flash update. For HAB Enable-type silicon, a shell provides essential information such as the signatures, optimized commands, and the authenticated binary image to the iROM to validate before the core to execute. 8.2 UART/USB Configuration The configuration for RS 232 is using baud rate 115200, 8 Data bits, No Parity, 1 Stop bits, and No Flow Control. The Configuration for USB is for Control Endpoint 0 with Max Packet Size equal 8 byte. Bulk IN at Endpoint 2 with Max Packet Size equal 64 bytes, Bulk OUT at Endpoint 1 with Max Packet Size equal 64 bytes. NOTE Current ROM code only supports Full Speed transmission over Full Speed transceiver(ISP1301 and Atlas) and High Speed USB transceiver (ISP 1504 or the like). The ROM code does not support high-speed transmission over high-speed USB transceiver (ISP 1504 or the like). 8.3 Enter Bootstrap Mode Configuration The i.MX27 processor enters bootstrap mode under the following conditions: 1. BOOT[3:0] is selected bootstrap mode or 2. For HAB Enabled type of silicon: HAB authentication fails when booting from Flash (for example NAND Flash, NOR Flash) Refer to Chapter 4, “System Control” for the details of bootstrap mode configuration and operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 8-1 Bootstrap Mode Operation 8.4 Bootstrap Flow The overall flow of the bootstrap program is shown in Figure 8-1. Call USB/UART bootloader to download RAM Application. CSF Address Execute Address Hardware Hardware Configuration Address Valid Execute Address? YES YE HAB Enabled? NO YES YE Hardware Configuration Vector Hardware Configuration CSF Data for downloaded code HAB Process CSF Return Status Execute Address HAB Assert Verification NO Return status = HAB PASSED? HAB SU Type = Engg? NO YES YE Jump to Application code YES YE Figure 8-1. Flow Diagram for Bootstrap Mode MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 8-2 Freescale Semiconductor Bootstrap Mode Operation 8.4.1 Bootstrap Protocol and Definition In this section, bootstrap protocol and the command, response definition is defined. For the i.MX27 processor’s boot-up sequence, refer to System Boot. For the CSF, HW Configuration, Image definition, refer to the High Assurance Boot (HAB). 8.4.1.1 Synchronization Operation When bootstrap is firstly entered, the status of the iROM can be obtained by issuing the command shown in Figure 8-2. PC to i.MX27: i.MX27 to PC: SYNCH COMMAND RESPONSE A Figure 8-2. iROM Status Command The SYNC COMMAND consists of 16 bytes using the format shown in Table 8-1. : Table 8-1. Synch Command Response Definition Header (2 bytes) 0505 Address (4 bytes) 00000000 Format (1 byte) 00 Bytecount (4 bytes) 00000000 Data (4 bytes) 00000000 End (1 byte) 00 RESPONSE A is 4 bytes long using the format shown in Table 8-2. Table 8-2. Response A Definition Byte 0 STATUS CODE Byte 1 STATUS CODE Byte 2 STATUS CODE Byte 3 STATUS CODe 8.4.1.2 Write Register Operation To write to a register through bootstrap, requires a specific protocol. After the command is sent from PC to MX27 processor, two responses are returned from MX27. One is used to indicate the type of silicon (either HAB enable or disable), the other is used to indicate whether the write operation is successful. PC to i.MX27: i.MX27 to PC: WRITE COMMAND RESPONSE B RESPONSE C Figure 8-3. Write Register Command WRITE COMMAND is 16 bytes long using the format shown in Table 8-3. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 8-3 Bootstrap Mode Operation Table 8-3. Write Register Command Definition Header (2 bytes) 0202 Address (4 bytes) Address to be written Format (1 byte) Format to be written (08: byte access 10: halfword access 20: word access) Bytecount (4 bytes) 00 Data (4 bytes) Data to be written to the register End (1 byte) 00 RESPONSE B indicates type of silicon. It is composed of 8 bytes using the format shown in Table 8-4. Table 8-4. Response B Definition Byte 0 HAB Disable/ Development HAB Enable 56 12 Byte 1 78 34 Byte 2 78 34 Byte 3 56 12 RESPONSE C indicates the success of a write operation as shown in Table 8-5. Table 8-5. Response C Definition Byte 0 12 Byte 1 8A Byte 2 8A Byte 3 12 Remarks: For HAB enabled silicon, users can only write the following range of registers: 1. System Control registers (address: 0x10027800-0x10027870) 2. Phase-Locked Loop, Clock and Reset Controller registers (address: 0x10027000–0x10027034) 3. NFC registers (address: 0xD8000000–0xD8000FFF) 4. SDRAMC registers (address: 0xD8001000–0xD8001FFF) 5. WEIM registers (address: 0xD8002000–0xD8002FFF) 6. Memory area of CS0, CS1, CS2, CS3, CS4, CS5, CSD0, and CSD1 (address: 0xA0000000–0xD7FFFFFF) 8.4.1.3 Download Operation Memory is initialized before downloading a binary file to it. The following command can be used: PC to i.MX27: i.MX27 to PC: DOWNLOAD COMMAND RESPONSE B BINARY DATA Figure 8-4. Download Command The DOWNLOAD COMMAND is 16 bytes long using the formats shown in Table 8-6. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 8-4 Freescale Semiconductor Bootstrap Mode Operation Table 8-6. Download Command Definition Header (2 bytes) CSF 0404 Address (4 Bytes) Start address where the binary data is to be downloaded Start address where the binary data is to be downloaded Start address where the binary data is to be downloaded Start address where the binary data is to be downloaded Format (1 byte) 00 Bytecount (4 bytes) Number of byte to be written in Hex Number of byte to be written in Hex Number of byte to be written in Hex (max 0x1F0000) Number of byte to be written in Hex Data (4 bytes) Start address in memory where data is to be written Start address in memory where data is to be written Start address in memory where data is to be written Start address in memory where data is to be written End (1 byte) CC HWC 0404 00 EE Image file 0404 00 00 Image file 0404 00 AA RESPONSE B indicates the type of silicon. It is 8 bytes long using the format shown in Table 8-7. Table 8-7. Response B Silicon Type Definition BYTE 0 HAB Disable/ Development HAB Enable 56 12 BYTE 1 78 34 BYTE 2 78 34 BYTE 3 56 12 After the RESPONSE B is received by the MX27 processor, the attached PC can start to download the binary data to MX27 until all the BYTECOUNT is downloaded. Each time the Image File is downloaded through HEADER (0404), the maximum data to be download is 0x1F0000. Thus, if the Image File size is greater then 0x1F0000, it will send the command repeatedly with END (0x00). After all the data is downloaded, PC must send a DOWNLOAD command with END (AA) to the target execution address. 8.4.1.4 Bootstrap End Indication Operation After all the bootstrap operations are completed, the i.MX27 processor will send RESPONSE D to PC after the Application Pointer was sent to indicate bootstrap was completed. After RESPONSE D, it will enter iROM to perform the authentication check for HAB enable silicon or to execute the image for HAB disable/development silicon. i.MX27 to PC: RESPONSE D Figure 8-5. Bootstrap End Indication Operation Diagram RESPONSE D is indicates the success of the write operation as shown in Table 8-8. Table 8-8. Bootstrap End Indication Operation Diagram BYTE 0 88 BYTE 1 88 BYTE 2 88 BYTE 3 88 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 8-5 Bootstrap Mode Operation MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 8-6 Freescale Semiconductor Book II: Applications Processors’ Core and Peripherals Introduction Book II comprises detailed information on the applications processors’ core and peripherals. Book II includes the following chapters. Book II, Part 1: ARM9 Core and Interrupts Chapter 9, “ARM9 Platform,” on page 9-3 Chapter 10, “ARM926EJ-S Interrupt Controller (AITC),” on page 10-1 Book II, Part 2: Security Chapter 11, “Security Controller (SCC),” on page 11-1 Chapter 12, “Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2),” on page 12-1 Chapter 13, “Run-Time Integrity Checker (RTIC),” on page 13-1 Chapter 14, “IC Identification (IIM),” on page 14-1 Book II, Part 3: External Interfaces Chapter 15, “External Memory Interface (EMI),” on page 15-1 Chapter 16, “Multi-Master Memory Interface (M3IF),on page 16-1 Chapter 17, “Wireless External Interface Module (WEIM),” on page 17-1 Chapter 18, “Enhanced SDRAM Controller (ESDRAMC),” on page 18-1 Chapter 19, “NAND Flash Controller (NFC),” on page 19-1 Chapter 20, “Personal Computer Memory Card International Association (PCMCIA) Controller,” on page 20-1 Book II, Part 4: Connectivity Peripherals Chapter 21, “1-Wire Interface (1-Wire),” on page 21-1 Chapter 22, “Advanced Technology Attachment (ATA)”, on page 22-1 Chapter 23, “Configurable Serial Peripheral Interface (CSPI),” on page 23-1 Chapter 24, “Inter-Integrated Circuit (I2C),” on page 24-1 Chapter 25, “Keypad Port (KPP),” on page 25-1 Chapter 26, “Memory Stick Host Controller (MSHC),” on page 26-1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 Chapter 27, “Secured Digital Host Controller (SDHC),” on page 27-1 Chapter 28, “Universal Asynchronous Receiver/Transmitters (UART),” on page 28-1 Chapter 29, “Fast Ethernet Controller (FEC),” on page 29-1 Chapter 30, “High-Speed USB On-The-Go (HS USB-OTG),” on page 30-1 Book II, Part 5: Timer Peripherals Chapter 31, “General Purpose Timer (GPT),” on page 31-1 Chapter 32, “Pulse-Width Modulator (PWM),” on page 32-1 Chapter 33, “Real Time Clock (RTC),” on page 33-1 Chapter 34, “Watchdog Timer (WDOG),” on page 34-1 Book II, Part 6: System Control Peripherals Chapter 35, “AHB-Lite IP Interface (AIPI) Module,” on page 35-1 Chapter 36, “Multi-Layer AHB Crossbar Switch (MAX),” on page 36-1 Chapter 37, “Direct Memory Access Controller (DMAC),” on page 37-1 Book II, Part 7: Multimedia Peripherals Chapter 38, “Digital Audio MUX (AUDMUX),” on page 38-1 Chapter 39, “CMOS Sensor Interface (CSI),” on page 39-1 Chapter 40, “Video Codec (Video_Codec),” on page 40-1 Chapter 41, “enhanced Multimedia Accelerator Light (eMMA_lt),” on page 41-1 Chapter 42, “Synchronous Serial Interface (SSI),” on page 42-1 Chapter 43, “Liquid Crystal Display Controller (LCDC),” on page 43-1 Chapter 44, “Smart Liquid Crystal Display Controller (SLCDC),” on page 44-1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Book II, Part 1: ARM9 Core and Interrupts Introduction This part provides an overview of the modules that make up the ARM9 core and interrupts. Chapter 9, “ARM9 Platform,” on page 9-3 Chapter 10, “ARM926EJ-S Interrupt Controller (AITC),” on page 10-1 ARM9 Platform The ARM9 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6 x 3 Multi-Layer AHB crossbar switch (MAX), and a “primary AHB” complex. The instruction bus of the ARM926EJ-S processor (I-AHB) is connected directly to MAX Master Port 0. The data bus of the ARM926EJ-S processor (D-AHB) is connected directly to MAX Master Port 1. All four alternate bus master interfaces are connected to MAX Master Ports 2-5. The three slave ports of the MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB is internal to the platform and has six slaves connected to it: the AITC interrupt module, the MCTL memory controller, two AIPI peripheral interface gaskets, and a ROMPATCH module. Slave ports 1 and 2 of the MAX are referred to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform. ARM936EJ-S Interrupt Controller (AITC) The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral which collects interrupt requests from up to 64 sources and provides an interface to the ARM926EJ-S core. The AITC includes software controlled priority levels for normal interrupts. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Chapter 9 ARM9 Platform 9.1 Introduction The ARM9 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6 x 3 Multi-Layer AHB crossbar switch (MAX), and a “primary AHB” complex. The instruction bus of the ARM926EJ-S processor (I-AHB) is connected directly to MAX Master Port 0. The data bus of the ARM926EJ-S processor (D-AHB) is connected directly to MAX Master Port 1. All four alternate bus master interfaces are connected to MAX Master Ports 2–5. The three slave ports of the MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB is internal to the platform and has six slaves connected to it: the AITC interrupt module, the MCTL memory controller, two AIPI peripheral interface gaskets, and a ROMPATCH module. Slave ports 1 and 2 of the MAX are referred to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform. The four alternate bus master ports on the ARM9 Platform, which are connected directly to master ports of the Multi-Layer Crossbar Switch (MAX), are designed to support connections to multiple AHB masters external to the platform. An external arbitration and AHB control module is needed if multiple external masters are desired to share an ARM9 Platform alternate bus master port. However, the alternate bus master ports on the platform support seamless connection to a single master with no external interface logic required. A PAHBMUX module (primary AHBMUX) performs address decoding, read data muxing, bus watchdog, and other miscellaneous functions for the primary AHB within the platform. A clock control module (CLKCTL) is provided to support a power conscious design methodology as well as implementation of several clock synchronization circuits. The JAM (Just Another Module) implements the platform’s general purpose registers and also contains miscellaneous platform logic. A block diagram of the ARM9 Platform can be seen in Figure 9-1. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-3 ARM9 Platform RT Debug JTAG ARM926 PLATFORM CLKCTL JTAG SYNC Interrupts External RAM/ROM Two IP-bus Peripheral Ports AITC MCTL AIPI1 AIPI2 Primary AHB ETM9 ETB IP Bus ETM ARM926EJ-S IP Bus JAM PAHBMUX IP Bus D-AHB I-AHB ROMPATCH 6x3 MAX I-AHB Patch D-AHB Patch M0 M1 M2 M3 M4 M5 CCM S0 S1 S2 Four AHB-Lite Alternate Bus Master Ports (ABM) Clock Control “Bus Request” Two AHB-Lite “Secondary” Slave Ports Figure 9-1. ARM9 Platform Block Diagram 9.1.1 Design Methodology Summary Other than the CPU and ETB memories, this platform is a fully synthesizable, mux-D, rising edge clock based design. DFT goals are for 95% fault coverage and the design includes BIST engines for all memories implemented on the ARM926EJ-S, the ETB module and RAM or ROM controlled by the MCTL module. The platform will be designed with a DFT friendly scan wrapper to allow for deeply embedded integrations. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-4 Freescale Semiconductor ARM9 Platform 9.1.2 Performance Characteristics The ARM9 Platform will support two main clocks—clk and hclk. clk will be connected to the ARM926EJ-S processor, ETM9, ETB and the Clock Control Module only. The remainder of the platform will be connected to hclk. The I-AHB and D-AHB from the ARM926EJ-S BIU module will run at the hclk frequency and will be controlled by a single hclken input—that is, the two buses cannot be decoupled. Refer to Section 9.6, “Platform Clocking” for more information on ARM926EJ-S clock control. 9.1.2.1 Performance Target The ARM9 Platform team has committed to making an operating frequency of 266MHz characterized at the 1.1V, 105C WCS 3 sigma cmos90lp standard Vt library and 400MHz characterized at the 1.45V, 105C WCS 3 sigma cmos90lp standard Vt library. This is the level of performance required to meet functional requirements. Due to the increased leakage of the cmos90lp library, well back-biasing will be employed along with other standard low power clocking methodologies. 9.2 ARM9 Platform Sub-Modules The sub-modules of the platform are listed below along with short functional descriptions. 9.2.1 ARM926EJ-S Processor The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors targeted at multi-tasking applications. The ARM926 supports the 32-bit ARM and 16-bit THUMB instructions sets. The ARM926 includes features for efficient execution of Java byte codes. A JTAG port is provided to support the ARM Debug Architecture, along with associated signals to support the ETM9 real-time trace module. The ARM926EJ-S is a Harvard cached architecture including an ARM9EJ-S integer core, a Memory Management Unit (MMU), separate instruction and data AMBA AHB interfaces, separate instruction and data caches, and separate instruction and data tightly coupled memory (TCM) interfaces. The ARM926 co-processor, instruction TCM, and data TCM interfaces will be tied off within the ARM9 Platform and will not be available for external connection. The ARM926EJ-S processor is a fully synthesizable macrocell with a configurable memory system. Both instruction and data caches will be 16 Kbytes on the platform. The cache is virtually accessed and virtually tagged. The data cached has physical tags as well. The MMU provides virtual memory facilities which are required to support various platform operating systems such as Symbian OS, Windows CE, and Linux. The MMU contains eight fully associative TLB entries for lockdown and 64 set associative entries. Refer to the ARM926EJ-S Technical Reference Manual for more information. 9.2.1.1 ARM926EJ-S Co-Processor Interface The co-processor interface will not exit the ARM9 platform and will be tied off internally and synthesized away to improve routing congestion and timing. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-5 ARM9 Platform 9.2.1.2 TCM Interfaces Both instruction and data tightly-coupled memory (TCM) interfaces will not exit the ARM9 platform and will be tied off internally and synthesized away to improve routing congestion and timing. 9.2.2 ARM9 Embedded Trace Macrocell and Embedded Trace Buffer The ARM9 platform will include an ARM9 Embedded Trace Macrocell (ETM9) and Embedded Trace Buffer (ETB) supporting real-time instruction and data tracing. The ETM9/ETB external interface may run at the ARM926EJ-S clock frequency or at half the ARM926EJ-S clock frequency. The Embedded Trace Buffer is sized at 2048x 32 and can be used as general scratch pad memory when not being used for real-time tracing. This scratch pad memory is accessible via AIPI2 slots 27 and 28. The ETB registers can be accessed via AIPI2 slot 29. Refer to the ETM9 and ETB technical reference manuals for more information. 9.2.3 The 6 x 3 Multi-Layer AHB Crossbar Switch (MAX) The ARM926EJ-S processor’s instruction and data buses and all alternate bus master interfaces arbitrate for resources via a 6 X 3 Multi-Layer AHB Crossbar Switch (MAX). There are six (M0–M5) fully functional master ports and three (S0–S2) fully functional slave ports. The MAX is uni-directional. All master and slave ports are AHB-Lite compliant. See Section 9.9.1, “Definition of AHB-Lite” for an explanation of AHB-Lite. The design of the crossbar switch allows for concurrent transactions to proceed from any master port to any slave port. That is, it is possible for all three slave ports to be active at the same time as a result of three independent master requests. If a particular slave port is simultaneously requested by more than one master port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration schemes supported are fixed, programmable fixed, programmable default input port parking, and a round robin arbitration scheme. The Crossbar Switch also monitors the ccm_br input (clock control module bus request) which request a bus grant from all four slave ports. The priority of ccm_br is programmable and defaults to the highest. Upon receiving bus grants for all four output ports, the ccm_bg output will assert. At this point, the clock control module can turn off hclk and be assured there are no outstanding AHB transactions in progress. Once the CCM is granted a port, no other master will receive a grant on that port until the CCM bus request (ccm_br) negates. Brief descriptions below provide more detail on the MAX. For complete functionality, refer to the ARM9 Platform “Multi-Layer AHB Crossbar Switch” Module (MAX) specification. 9.2.3.1 MAX Configuration Registers The Crossbar Switch has configuration and control registers accessible via the IP Bus (slot 31 of AIPI2). Programmable registers exist to control arbitration schemes, bus parking, as well as other crossbar bus switch functionality. Alternate master priority registers exists within the MAX module for each slave MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-6 Freescale Semiconductor ARM9 Platform output port. The alternate priority register can be selected for use by the internal arbitration logic by driving the sx_ampr_sel (x=0-2) input high. A write-block sticky bit is implemented for those applications where it is desirable to prevent changes to the MAX registers after boot. Refer to the MAX module design specification for more details. 9.2.3.2 Master Ports Master Port 0 of the MAX is connected directly to the ARM926EJ-S I-AHB. Master Port 1 of the MAX is connected directly to the ARM926EJ-S D-AHB. The other four master ports exit the platform and will be connected to external alternate bus masters. Multiple external masters may be attached to a single alternate bus master port via use of an external arbiter. See Section 9.9.3, “Single Master Seamless Connection to ABM Port” and Section 9.9.4, “Multiple External Masters Connection to ABM Port” for more information on how to connect either a single master or multiple masters to a single alternate master port. Master Port priorities are determined by the MAX priority register bit settings. Refer to the MAX module design specification for more details. 9.2.3.3 Slave Ports Slave port 0 through 2 are identical AHB-Lite buses. Slave Port 0 is designated as the “Primary AHB” bus, and is internal to the platform. Slave port 1 and 2 are identical “Secondary AHB” buses and are available external to the platform. See Section 9.9.6, “MAX AHB Slave Ports” for more details. 9.2.3.4 Debug Support In addition to the JTAG, ETM9 and ETB9 interfaces, several internal ARM926EJ-S signals, several internal primary AHB signals as well as some internal signals from Master Ports 0 and 1, have been brought out of the platform. These signals, along with alternate bus master and secondary AHB signals already available on the top-level of the platform, enable the user to gain insight into the operation of the processor and the MAX. Specifically, it is possible to monitor these signals and determine which master currently owns each slave port. In addition, it is possible to determine which slave each master is targeting for its next request. 9.2.4 ARM Interrupt Controller (AITC) The ARM9 platform’s interrupt controller is called the AITC and is connected to the primary AHB as a slave device. It will generate the normal and fast interrupts to the ARM926EJ-S processor. The AITC also supports hardware assisted vectoring. NOTE If hardware assisted vectoring is used, the vector space must be marked non-cacheable. Since the vector is dynamically “jammed” in by the AITC during a vector fetch, there would be no way to do this if cached. Refer to the AITC specification for more details. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-7 ARM9 Platform 9.2.5 Memory Controller and BIST Engine (MCTL) The MCTL module interfaces the primary AHB to RAM and ROM. BIST engines are provided for both RAM and ROM. 9.2.5.1 RAM The ram_connect input on the ARM9 Platform must be tied high if RAM exists on the MCTL RAM interface. The MCTL module supports a minimum of 1 Kbyte of RAM and a maximum of 1 Mbyte. Non power-of-two sizes between 1 Kbyte and 1 Mbyte are supported by strapping the ram_max_addr[9:0] inputs, which correspond to the primary AHB’s haddr[19:10]. The ram_wait input should be tied high at integration time if a wait state is required to make read data timing on RAM accesses (writes will still be zero wait state). The RAM interface will support single clock edge non late-write style compiled memories, and will implement an internal write buffer to mimic the late-write capability for improved performance. A configurable BIST engine is provided. Refer to the ARM9 Platform MCU Memory Controller specification for more detail on the RAM controller design. Refer to Table 9-4 for the RAM’s location within the platform’s memory map. 9.2.5.2 ROM The rom_connect input on the ARM9 Platform must be tied high if ROM exists on the MCTL ROM interface. The MCTL module supports a minimum of 1 Kbyte of ROM and a maximum of 4 Mbyte. Non power-of-two sizes between 1 Kbyte and 4 Mbyte are supported by strapping the rom_max_addr[11:0] inputs, which correspond to the primary AHB’s haddr[21:10]. The rom_wait input should be tied high at integration time if a wait state is required to make read data timing on ROM accesses. A configurable BIST engine is provided. 9.2.5.2.1 ROM Addressing The first 16 Kbytes of ROM will always be mapped starting at haddr[31:0]=32’h0000_0000. Any ROM larger than 16Kbyte will have the remainder of its space mapped starting at haddr[31:0]=32’h0040_4000. Any ROM size smaller than 16 Kbyte, will be aliased throughout the 16 Kbyte region. Accesses to the “hole” between these two regions will be terminated with an ERROR response by the MCTL. Refer to the ARM9 Platform MCU Memory Controller specification for more detail on the ROM controller design. 9.2.6 AHB IP Bus Interface (AIPI) There are two AHB IP Bus Interface (AIPI) modules that interface the primary AHB to two external IP Bus interfaces. The IP Bus interfaces and their peripherals will conform to the IP Bus Rev 2.0/3.0 specification. Each AIPI module supports up to 31 peripherals (the AIPI configuration registers consume the slot 0), however the ARM9 Platform will only support 48 external peripherals as shown in Table 9-1. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-8 Freescale Semiconductor ARM9 Platform Table 9-1. AIPI ARM9 Platform IP Bus Support AIPI # 1 1 2 2 2 2 2 2 2 2 Module Slot(s) 0 1–31 0 1–17 18–26 27 28 29 30 31 Use AIPI1 Configuration Registers Off platform IP Bus module support AIPI2 Configuration Registers Off platform IP Bus module support Reserved On platform ETB Register Interface On platform ETB RAM Interface On platform ETB RAM Interface On platform JAM Interface On platform MAX Interface Refer to the ARM9 Platform AIPI specification for more details on the operation of the AIPI. 9.2.7 PAHBMUX–Primary AHB Mux The PAHBMUX module is responsible for address decoding for the primary AHB module selects. In addition, the PAHBMUX module will perform the primary AHB read data muxing, the primary AHB watchdog, and other miscellaneous functions. Refer to the ARM9 Platform AHBMUX design specification for more detail. 9.2.8 ROMPATCH The ROMPATCH will sit on the ARM926EJ-S I-AHB and D-AHB interfaces which are connected to MAX Master Ports 0 and 1. This location will allow for patching of both internal and external memory addresses on both ARM926EJ-S processor buses. The registers of the ROMPATCH will be programmed via the Primary AHB. The ROMPATCH can be used to patch source code or data tables. The ROMPATCH supports 32 patches. 9.2.8.1 External Boot An external boot feature exists in the ROMPATCH module which allows patching of the reset vector fetch (address = 32’h0000_0000) if the boot_int signal is negated. This mechanism will cause the ARM926EJ-S to, in effect, fetch the reset vector from the address indicated by the ext_boot_addr[31:2] inputs. Refer to the ARM9 Platform ROMPATCH design specification for more details. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-9 ARM9 Platform 9.2.9 Clock Control Module (CLKCTL) The CLKCTL module performs block level clock gating, ARM926EJ-S JTAG synchronization requirements, as well as other miscellaneous clock control for the platform. Refer to the ARM9 Platform CLKCTL design specification for more detail on design implementation. 9.2.10 JAM The JAM (“Just Another Module”) implements miscellaneous logic with the platform. Functionality within the JAM includes IP Bus #2 read data muxing, gating of the AHB debug signals in order to save power, and an IP Bus interface for accessing ARM9 Platform general purpose registers. The IP Bus interface on the JAM populates AIPI2, slot 30. The IP bus registers implemented in the JAM are shown in Table 9-2. Table 9-2. JAM IP Bus General Purpose Registers Primary haddr 32’h1003_E000 32’h1003_E010 Register Name ARM9P_GPR0 ARM9P_GPR4 Type Write/Read Read Only Implementation {30’h0, etb_reg_clken, ahb_dbg_en} tapid[31:0] The registers may be aliased throughout the AIPI2 slot 30 location; however, the registers should only be accessed at the above listed addresses. Attempts to access the registers at aliased locations may result in an error response. Additionally, attempts to access the registers in user mode or in non-word sizes will result in an error response. Writes to the read only ARM9P_GPR4 register are ignored and will not cause an AHB transfer error. ARM9P_GPR0 bit [1], etb_reg_clken, is reset to zero on power-up and disables the clocks to the ETB for non debug purposes. When set to one, etb_reg_clken will enable clocks to the ETB such that the memory in the ETB can be used as general scratch-pad memory. ARM9P_GPR0 bit [0], ahb_dbg_en, is reset to zero on power-up and disables the AHB debug related signals from toggling in order to save power. When set to a one, ahb_dbg_en enables the following top-level platform AHB related signals to toggle for platform debug: • I-AHB: dbg_iahb_hready, dbg_iahb_htrans1, dbg_iahb_haddr[31:29] • D-AHB: dbg_dahb_hready, dbg_dahb_htrans1, dbg_dahb_haddr[31:29] • P-AHB: dbg_dahb_hready, dbg_dahb_htrans1, dbg_dahb_hmaster These signals, along with signals available on the alternate bus master and secondary AHB ports, can be used to gain insight into the functionality of the MAX. ARM9P_GPR4 is provided for software to determine the version of the platform. These bits correspond to the static state of the tapid[31:0] signals which include the tapid_ver[3:0] platform inputs. See Section 9.4, “JTAG ID Register” for more details. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-10 Freescale Semiconductor ARM9 Platform 9.2.11 Test Wrapper The ARM9 Platform’s test architecture is composed primarily of two functions: scan and BIST. The test module (ARM926P_TEST) includes a test control unit which decodes primary test mode input signals and places the platform into various test modes including scan, ac path testing, BIST, and safe state. These test modes support the ability to test a deeply embedded platform. Refer to the ARM9 Platform DFT specification for more information. 9.3 ARM9 Platform Hierarchy The first two levels of the ARM9 Platform design hierarchy are shown in Figure 9-2. ARM9P PLATFORM ARM926P_CORE ARM926P_DEBUG ETM9 ARM926EJ-S ETB9 ARM926P_TEST ARM926P_WRAPPER ARM926P_TCU ARM926P_ROUTER CLKCTL ARM926P_TSECURE MAX (CROSSBAR SWITCH) ARM926P_TCLOCKS JAM PAHBMUX MCTL ROMPATCH AIPI1 JAM AIPI2 AITC Figure 9-2. ARM9 Platform Hierarchy MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-11 ARM9 Platform 9.4 JTAG ID Register The ARM926EJ-S processor has a 32-bit input bus which corresponds to the JTAG ID register. This 32-bit register is defined fields as shown in Table 9-3. ARM requires bits [31:12] be set in accordance with their general rules such that Multi-ICE can auto-detect the device type. Table 9-3. ARM926EJ-S JTAG ID Register Definition tapid[31:28] Version 4’b0 tapid[27:12] Part Number 16’h7926 tapid[11:8] tapid[7:1] tapid[0] 1’b1 1’b1 Manufacturing ID tapid_ver[3:0] 7’b001_0000 9.5 System Memory Map haddr[31:29] on the MAX master ports are decoded determine which slave port has been selected. Only three bits are used in order to keep output port decode time to a minimum. Table 9-4 shows a simplified breakdown of the eight 512 Mbyte regions decoded within the 4 Gbyte address space. Table 9-4. Upper Address Bit Decode haddr[31:29] 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111 512 Mbyte Primary AHB–MCTL (RAM) Size 512 Mbyte 512 Mbyte 512 Mbyte 512 Mbyte 512 Mbyte 1 Gbyte Use Primary AHB—AIPI1, AIPI2, AITC, MCTL (ROM), ROMPATCH Reserved Reserved Reserved Secondary AHB Slave Port 1 Secondary AHB Slave Port 2 9.5.1 ARM9 Platform Memory Map Table 9-5. ARM9 Platform Memory Map Address Range 0000_0000–0000_3FFF 0000_4000–0040_3FFF 0040_4000–007F_FFFF 0080_0000–0FFF_FFFF 1000_0000–1000_0FFF 1000_1000–1001_FFFF Size 16 Kbyte 4 Mbyte 4 Mbyte–16 Kbyte 256 Mbyte–8 Mbyte 4 Kbyte 124 Kbyte Use ROM: First 16Kb (Primary AHB) Reserved ROM: Exceeding 16Kbyte (Primary AHB) Reserved AIPI1 Control Registers (Primary AHB) AIPI1 Peripheral Space (Primary AHB) Table 9-5 shows the complete ARM9 Platform memory map. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-12 Freescale Semiconductor ARM9 Platform Table 9-5. ARM9 Platform Memory Map (continued) Address Range 1002_0000–1002_0FFF 1002_1000–1003_1FFF 1003_2000–1003_AFFF 1003_B000–1003_BFFF 1003_C000–1003_CFFF 1003_D000–1003_DFFF 1003_E000–1003_EFFF 1003_F000–1003_FFFF 1004_000–1004_0FFF 1004_1000–1004_1FFF 1004_2000–1FFF_FFFF 2000_0000–7FFF_FFFF 8000_0000–9FFF_FFFF A000_0000–DFFF_FFFF E000_0000–FFEF_FFFF FFF0_0000–FFFF_FFFF Size 4 Kbyte 68 Kbyte 36 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 256 Mbyte–280 Kbyte 1.5Gbyte 512 Mbyte 1 Gbyte 511 Mbyte 1 Mbyte Use AIPI2 Control Registers (Primary AHB) AIPI2 Peripheral Space (Primary AHB) Reserved AIPI2—ETB Registers (Primary AHB) AIPI2—ETB RAM (Primary AHB) AIPI2—ETB RAM (Primary AHB) AIPI2—JAM (Primary AHB) AIPI2—MAX (Primary AHB) AITC (Primary AHB) ROMPATCH (Primary AHB) Reserved Reserved Secondary AHB Slave Port 1 Secondary AHB Slave Port 2 Reserved (Aliased RAM Space) RAM (Primary AHB) 9.5.2 External Peripheral Space AIPI1 supports 31 external peripherals starting at 32’h1000_1000. AIPI2 has three slots used internal to the ARM9 Platform and supports 17 external peripherals from 1002_1000–1003_EFFF. NOTE Care should be taken when programming the PSR of AIPI2 since slot 31 (MAX), slot 30 (JAM), slot 29 (ETB Registers), slot 28 (ETB RAM) and slot 27 (ETB RAM) will always be occupied and slots 26:18 will always be unoccupied. 9.5.3 External Boot When the boot_int input signal is asserted, the ARM926EJ-S will boot internal from ROM on the Primary AHB. When boot_int is negated, the ARM926EJ-S reset vector fetch will essentially be routed to an address indicated by the ext_boot_addr[31:2] input pins. This vectoring is done by the ROMPATCH module, which monitors the I-AHB of the ARM926EJ-S and over-rides the reset vector fetch. Refer to the ROMPATCH design specification for more detail on the external boot mechanism. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-13 ARM9 Platform NOTE When boot_int is negated and the ARM926EJ-S boots externally the ARM9 Platform is placed in an insecure state. 9.5.4 • • • • Memory Map Considerations Accesses to “Reserved” locations in Table 9-5 other than aliased RAM space will result in an AHB error response. Accesses to unsupported address locations through the MAX will result in an AHB error response and the access will not pass through the MAX. Accesses to address locations on the Primary AHB bus which do not map to a specific module will time-out in accordance with the bmon_timeout[2:0] inputs. Accesses to unimplemented locations within the AITC and ROMPATCH register space will be terminated without a bus-error. Writes will have no effect and reads will return all zeros. 9.6 Platform Clocking This section will describe some of the clocking considerations within the ARM9 Platform. The circuits contained in the ARM9 Platform to address most of these issues will be implemented within the Clock Control Module (CLKCTL). However, there are some external clock control issues that will be discussed. Refer to the ARM9 Platform CLKCTL Module design specification for more detail. 9.6.1 ARM926EJ-S Clock Considerations The ARM926EJ-S processor design uses a single clock, clk. In many systems, it will be desirable for the ARM926EJ-S processor to run at a higher frequency than the AHB system bus (which runs on hclk). To support this, ARM926EJ-S requires a separate AHB clock enable for each of the two bus masters. dhclken is used to signify the rising edge of hclk for the system in which the data BIU is the bus master. ihclken is used to signify the rising edge of hclk for the system in which the instruction BIU is the bus master. Figure 9-3 shows the relationship between clk, hclk and dhclken/ihclken. The ARM9 Platform will provide a single hclken input pin that will be fed to both the dhclken and ihclken inputs on the ARM926EJ-S. If hclk and clk are the same frequency, the hclken input to the platform must be tied HIGH. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-14 Freescale Semiconductor ARM9 Platform (hclken) Figure 9-3. AHB Clock Relationship clk and hclk must be synchronous and the skew between clk and hclk to the ARM9 Platform should be minimized. This will require some synchronization inside the chip clock control module. An example of this is provided in Figure 9-4. In the example, clk and hclk are completely asynchronous and clk must be much faster to sample the slower clock, otherwise a different scheme will be needed. Also, if clk and hclk are synchronous to each other by design, then a synchronizer may not be needed, but care must still be taken in aligning the rising edges of both clocks to the ARM9 Platform. hclken BUS CLOCK (Slow Clock) D Q D Q D Q Insertion Delay HCLK CLK CLK CPU CLOCK (Fast Clock) GATE_HCLK CLK CLK Insertion Delay + F/F Clk->Q >Q CLK_ALWAYS GATE_CLK Insertion Delay + F/F Clk->Q CLK ARM9 Platform CCM Boundary Boundary Figure 9-4. Example hclk to clk Synchronization When clk Is Faster MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-15 ARM9 Platform 9.6.2 ARM926EJ-S JTAG Port Clocking Considerations The ARM926EJ-S does not support direct connection to the JTAG interface. The JTAG interface must be synchronized to the clk domain. This synchronization will take place within the platform’s CLKCTL module. Refer to the ARM9 Platform CLKCTL design specification for more detail. 9.6.2.1 JTAG_TCK The jtag_tck clock must be less than 1/8 the frequency of the clk input in order for the JTAG port and synchronizer to function properly. Note that the frequency of clk can vary when executing low-power code. Therefore, care must be taken such that jtag_tck is less than 1/8 the lowest possible frequency of clk. 9.6.3 External Alternate Bus Master Interfaces All four alternate bus master ports on the ARM9 Platform MUST have the AHB synchronized to hclk external to the platform. All alternate bus master AHB inputs and outputs to/from the ARM9 Platform will be synchronous to hclk. 9.6.4 External Secondary AHB Ports Both secondary AHB ports inputs and outputs to and from the ARM9 Platform must be synchronous to the hclk and will run at the hclk frequency. 9.7 Platform Resets This section will describe the various ARM9 Platform reset inputs. Figure 9-5 shows the reset paths within the ARM9 Platform. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-16 Freescale Semiconductor ARM9 Platform ARM9 Platform ARM926P_TEST hreset_b ctbuf DBGnTRST ETM9 nRESET CLKCTL nTRST por jtag_trst_b OR and sync dbg_clear_b ctbuf ETB9 HRESETn nTRST nRESET tcu_hreset_b hreset_b ARM926P_CORE ARM926EJ-S HRESETn clk_always hreset_b (to all other platform modules) Figure 9-5. ARM9 Platform Resets 9.7.1 HRESET The hreset_b input is the asynchronous system reset for both the clk and hclk domains. It is gated with a test mode signal in the scan wrapper, and is then buffered for distribution throughout the platform. The hreset_b signal must satisfy the setup and hold time requirements relative to both clk and hclk rising edges. 9.7.2 POR and JTAG_TRST The power-on-reset (POR) and the JTAG reset (jtag_trst_b) will be combined in the CLKCTL module to drive the dbg_clear_b signal to the ARM926EJ-S and ETM9 modules. The dbg_clear_b output of the CLKCTL module can be considered as the JTAG or debug reset of the platform. The dbg_clear_b signal will assert asynchronously when either POR or jtag_trst_b asserts, and will negate synchronously to clk (through a synchronizer). Refer to the CLKCTL module design specification for more detailed information. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-17 ARM9 Platform 9.8 9.8.1 Power Management Register Level Clock Gating A Synopsys power compiler will be used to implement clock-gating on all components of the ARM9 Platform. That is, under normal operating conditions, clocks internal to the platform will only be issued to registers or banks of flops that need a rising edge for proper functionality. Otherwise, the clocks will be held low. 9.8.2 Block Level Clock Gating Clocks to individual modules within the platform will be enabled only when necessary. On the Primary AHB for example, the CLKCTL module will only enable hclk to a slave module when the current AHB access is addressed to that module. Slaves can also drive a signal to the CLKCTL if it requires its hclk to run for any other reason. See the CLKCTL module design specification for more detail. 9.8.3 External Clock Gating The ARM926EJ-S processor may be put into a low-power state by the wait-for-interrupt instruction. This instruction switches the ARM926EJ-S into a low-power state until either an interrupt (nIRQ/nFIQ) or a debug request occurs. The switch into the low-power state is indicated by the assertion of the arm_standbywfi output signal. If arm_standbywfi is asserted then it is guaranteed that all ARM926EJ-S external interfaces will be in an IDLE state. The arm_standbywfi signal is intended to be used to shut down clocks to the other parts of the system, such as external coprocessors, which do not need to be clocked if the ARM926EJ-S is idle. NOTE: The ARM926EJ-S clk must NOT be stopped during wait-for-interrupt mode if an external debugger is connected to the JTAG port. An active clk is required to be able to write values into the ARM9EJ-S debug control register, which is required for a debugger to be able to force wait-for-interrupt mode to be exited. It should also be noted that the ARM926EJ-S needs clk to run in order for an interrupt to cause the negation of arm_standbywfi. The JTAG synchronizer in the CLKCTL module needs to have an “always” clock running to it in order to, at any time, detect JTAG activity and thereby determine that a debugger is connected to the JTAG port. The presence of an active JTAG debugger will be detected by monitoring the JTAG TMS signal. After POR (or trst_b) assertion, a low state on TMS coincident with a rising-edge on TCK will transition the JTAG tap-controller from the test-logic-reset state to the run-test-idle state. The dbgen signal will be asserted, and held asserted, whenever the tap-controller is not in the test-logic-reset state. Once dbgen asserts, an active trst_b or POR is required to clear it (that is, once a debugger is detected to be connected, it is assumed to stay connected). When asserted, the a9p_clk_off output of the platform will indicate to an external clock control module that clk and hclken should be turned off at the earliest opportunity. However, in order to assure that no alternate bus masters are in the middle of a transaction, the external clock control module must assert the ccm_br input (bus request) of the crossbar switch. This will request ownership of all AHB Output Ports. Once the bus grant is asserted (ccm_bg), the external clock control module is then free to gate off hclk as all transactions on both the primary and secondary AHBs will have completed. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-18 Freescale Semiconductor ARM9 Platform Figure 9-6 shows a block diagram of how the clocks to the platform might be handled in a typical implementation. ARM9 PLATFORM CLK CLK ARM926EJ-S CLK IHCLKEN HCLKEN HCLKEN DHCLKEN STANDBYWFI RESET FLOP HCLK HCLK Module Clk Gating Individual Module Enables ETB9 ETM9 CLK_ALWAYS ETM CG DBGTCKEN CLK “ARM” JTAG JTAG CCM_BR CCM_BG JTAG SYNC CLKCTL AITC DBGEN IRQ_B FIRQ_B irq[63:0] A9P_CLK_OFF EXTERNAL CLOCK CONTROL MODULE IP Bus Figure 9-6. ARM9 Platform Clocking Strategy 9.8.4 Well Biasing A well bias clamp enable input, wt_en, will be driven by an external clock control module to the ARM9 Platform. When asserted, VBB+ will be shorted to VDD and VBB- will be shorted to GND. 9.9 Platform AHB Interfaces This section will describe the major bus interfaces of the ARM9 Platform and the crossbar switch. A simple block diagram of the bus connections to the platform is shown in Table 9-1. A definition of MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-19 ARM9 Platform AHB-Lite, a functional description of the alternate bus master ports, and finally a description of the multi-layer crossbar switch slave ports follows. 9.9.1 Definition of AHB-Lite All master and slave ports of the Multi-Layer AHB Crossbar switch are AHB-Lite compliant. Therefore, all AHBs connected externally to the ARM9 Platform must be AHB-Lite compliant. The definition of “AHB-Lite” for the ARM9 Platform is as follows: • AHB split and retry protocols are not supported within the ARM9 Platform. This means that all slaves connected to AHB-Lite ports (input or output) are prohibited from requesting a split or a retry. This also means there is only one response signal, hresp0. • AMBA bus request and bus grant are not supported on the AHB-Lite interfaces. • Bursts are supported. The default configuration of the Crossbar Switch (MAX) insures no early fixed length burst terminations due to the switch arbiter. 9.9.2 Alternate Bus Master Ports There are four alternate bus master ports (ABM) on the ARM9 Platform which are connected directly to the Multi-Layer AHB Crossbar Switch. These four ABM interfaces are AHB-Lite compliant. Table 9-6 lists the ABM interface signals (“x” is equal to 2 through 5). All signals function as documented in the AMBA Specification, Rev 2.0, AMBA AHB chapter. It is assumed that the alternate bus masters are using the same hclk and hreset_b as the ARM9 Platform. Table 9-6. Alternate Bus Master Interface Signal List Pin List mx_haddr[31:0] mx_hmaster[3:0] mx_htrans[1:0] mx_hprot[3:0] mx_hlock mx_hmastlock mx_hwrite mx_hsize[1:0] mx_hburst[2:0] mx_hwdata[31:0] mx_hready_out mx_hrdata[31:0] mx_hresp0 1 Direction1 Input Input Input Input Input Input Input Input Input Input Output Output Output Description AHB Address Bus AHB Master ID AHB Transfer Type AHB Access Protection Indicator AHB Master Lock Indicator AHB-Lite Master Lock Indicator AHB Access Write Indicator AHB Transfer Size AHB Access Burst Type AHB Write Data AHB Termination/Take Indicator AHB Read Data AHB Error Indicator Direction is relative to the ARM9 Platform. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-20 Freescale Semiconductor ARM9 Platform 9.9.3 Single Master Seamless Connection to ABM Port A single external master can connect seamlessly (no logic) to any of the four alternate bus master interfaces (all four ABM interfaces are identical). In this configuration, Table 9-7 lists the AHB signals which deserve special consideration. Table 9-7. Single External Master Connections to an Alternate Bus Master Interface AHB Signal Master’s hbusreq Output Master’s hgrant Input Master’s hready Input Master’s hlock Output Master’s hmastlock Output 1 2 Connection If present leave unconnected If present tie asserted (high) Connect to ABM hready_out Output If present connect to ABM hlock Input1 If present connect to ABM hmastlock Input2 If the Master does not have an hlock output, tie the ABM hlock input negated (low). If the Master does not have an hmastlock output, tie the ABM hmastlock input negated (low). NOTE The alternate bus master must drive htrans = IDLE when not requesting the bus as the arbiter may be parked on that input port. 9.9.4 Multiple External Masters Connection to ABM Port The four alternate bus master interfaces of the ARM9 Platform have been designed to support connection of multiple external AHB-Lite masters and slaves directly to the interface. Figure 9-7 shows the connection of two external masters to a ARM9 Platform alternate bus master interface. Note the location of the ARM9 Platform in the figure below and that only one of four ABM ports is shown. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-21 ARM9 Platform EXTERNAL ARBITER DATA_SELECT ADR_SELECT (Only one of four alternate Bus Master Interfaces Shown) M1_HBUSREQ M1_HBGRANT HREADY M1_HADDR/CTRL ARM9 PLATFORM HADDR/CTRL M2_HADDR/CTRL BUS MASTER #1 HWDATA HRDATA HWDATA A9P_HRDATA M2_HBUSREQ M2_HGRANT HREADY BUS MASTER #2 M2_HADDR/CTRL A9P_HREADY M2_HREADY_OUT M2_HWDATA M2_HRDATA HWDATA HRDATA Figure 9-7. Example of Two External Masters Connected to an ABM Port In the figure, two external masters, #1 and #2, arbitrate for control of the ABM interface on the ARM9 Platform. An external arbiter is required. The arbiter accepts the bus master’s hbusreq signals, and responds to the masters with hgrants. The arbiter also controls the address/control and data muxing in the external AHBMUX module. 9.9.5 Alternate Bus Master Design Considerations This section will discuss various issues which should be taken into account by engineers designing AHB masters to connect to the ARM9 Platform’s alternate bus master interfaces. 9.9.5.1 Edge-Based Design All alternate bus masters should be edge-based designs in order to meet the stringent timing imposed. Specifically, an AHB master’s address and control information should be driven directly from the output of a flip-flop. Similarly, an AHB master’s read data should go directly to a D-input of a flip-flop. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-22 Freescale Semiconductor ARM9 Platform 9.9.5.2 htrans [1:0] Some important issues to remember about the AHB htrans signals: • It is important that alternate bus masters drive htrans = IDLE when not requesting the bus. This is critical because the arbiter can grant the bus to a master even when the master is not requesting it (for example, a “parked” condition). • Although the AMBA AHB specification does not require it, it is suggested that alternate bus masters assert htrans = NSEQ with the initial assertion of hbusreq. In those systems where only a single master is connected to an input port, the hgrant signal will tied high, and improved performance may result. • It is highly recommended that alternate bus masters insert an IDLE cycle after any locked sequence to provide an opportunity for the arbitration to change before commencing further transfers. 9.9.5.3 hlock/hmastlock The mx_hlock and mx_hmastlock ABM interface signal connections are dependent on whether there is a single external master or connection to an external arbiter. The following notes specify the connections: • For single masters only, the mx_hlock input should be connected directly to the master’s hlock output. In this case, the mx_hmastlock input should be tied LOW. If the single master produces an hmastlock instead the mx_hmastlock input should be connected directly to the master’s hmastlock output. In this case, the mx_hlock input should be tied LOW. • For multiple master connections on an ABM port, the mx_hmastlock input signal should be connected to the external arbiter’s hmastlock output. In this case, mx_hlock should be tied LOW. In either case above, logic within the crossbar switch will insure the locked cycles’ functionality. 9.9.5.4 hmaster Alternate bus masters external to the ARM9 Platform should be aware that four values of the hmaster field are used by bus masters internal to the platform. The reserved and available hmaster encodings are shown in Table 9-8. Table 9-8. hmaster Encodings hmaster 4’h0 4’h1 4’h2 4’h3 4’h4–4’hF Use Reserved: MAX default Reserved Reserved: ARM926EJ-S I-AHB Reserved: ARM926EJ-S D-AHB Available to External Bus Masters MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-23 ARM9 Platform 9.9.5.5 hresp0—Bus Error A slave two cycle ERROR response (hresp0 = HIGH) allows for a bus master to cancel the remaining transfers in a burst. However, this is not an AHB requirement, and it is acceptable for the master to continue the remaining transfers of the burst. AHB error responses generated on accesses to cacheable or bufferable memory address on the I-AHB and D-AHB interfaces of the ARM926EJ-S are normally ignored by the processor. In the ROMPATCH module, a feature can be enabled which will, on the above described accesses, gate 0’s onto hrdata[31:0] on data reads, and SWI opcodes onto hrdata[31:0] for instruction prefetches. At the same time, the ROMPATCH module will generate an abort which will guarantee entry into the ARM926EJ-S platform’s abort exception handler. See the ARM9 Platform ROMPATCH design specification for more detail. 9.9.5.6 Unaligned Transfers Alternate bus masters should not request unaligned transfers. That is, a word access to a non-word aligned address; and, a halfword access to a non-halfword aligned address should not be requested as neither transactions are supported by this platform. The transfers will complete as normal, however the lower order address bits will be ignored according to Figure 9-4 and Figure 9-5. 9.9.5.7 Alternate Bus Master Throttle Control Alternate bus masters should be designed with programmable maximum burst lengths as well as programmable bus request interval timers. This will allow software to effectively “tune” the overall system for maximum throughput and efficiency. 9.9.5.8 Halt Request (ccm_br) Care must be taken to ensure that the Halt Low Priority bit is not changing as the Clock Control Module’s Halt request is asserted. This will result in unpredictable behavior. This can be avoided by not modifying this bit in the Slave General Purpose Control Register or in the Alternate Slave General Purpose Control register in software where Halt could be requested. Also, the Halt Low Priority bit should be programmed the same in both the Slave General Purpose Control Register and the Alternate Slave General Purpose Control Register, if it is likely the MAX can change between the General Purpose and Alternate registers during the time Halt could be requested. Care should also be taken to ensure that the Clock Control Module’s Halt request is not asserted until at least two clock cycles after the last locked access performed by any master connected to the MAX. 9.9.6 MAX AHB Slave Ports Each slave port of the Multi-Layer Crossbar Switch is an AHB-Lite compliant bus. Brief functional descriptions and attributes of each output port are provided. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-24 Freescale Semiconductor ARM9 Platform 9.9.6.1 Slave Port 0—Primary AHB (Internal) Slave Port 0 of the MAX is connected to the “Primary” AHB of the ARM9 Platform. The primary AHB is completely contained within the ARM9 Platform. A simplified block diagram of the Primary AHB components is shown in Figure 9-8. MCTL AIPI1 AIPI2 ROM PATCH REGS AITC hsel_x haddr hcontrol hwdata aipi2_rdata AHB MULTI-LAYER CROSSBAR SWITCH (MAX) hrdata hready hresp0 aitc_rdata haddr mctl_rdata aipi1_rdata addr decode select hrdata[31:0] hready hresp0 gnd combine bus monitor PAHBMUX aitc_rdata_ovr hready_out, hresp0 from slaves rompatch_rdata (ONLY PRIMARY AHB SLAVE PORT 0 SIGNALS ARE SHOWN) Figure 9-8. The Primary AHB The primary AHB will have the AITC, AIPI (2), MCTL and ROMPATCH modules connected as slave devices. The PAHBMUX (Primary AHB mux) module is the glue that pulls the primary AHB and its components together. It will decode the primary AHB haddr lines and issue module selects to the slaves, combine the slave hready and hresp0 signals from the slaves into the single bus hready and hresp0, and mux the read data from the currently selected slave onto the bus hrdata lines. A bus monitor module inside of PAHBMUX will terminate timed-out bus transactions. In addition, the PAHBMUX will contain logic to terminate any IDLE cycles and issue the required assertion of hready following negation of the hreset_b. 9.9.6.1.1 Primary AHB Device Latencies The latency of each slave device on the primary AHB can be found in Table 9-1. The clock latency number does not take into account the possible one clock arbitration delay of the MAX. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-25 ARM9 Platform Table 9-1. Primary AHB Slave Device Latencies Slave Device AITC AIPI1 MCTL ROMPATCH 1 Transaction Type Register Access Writes Reads Memory Access Register Access Latency 1 clock 3 clocks 2 clocks 1 clock2 1 clock The latency listed for the AIPIs are best case and based on a zero wait state response from the IP bus target device. Each wait state the IP Bus target device adds will add one extra clock to the listed latency value. 2 Assumes ram_wait and rom_wait are negated. 9.9.6.2 Secondary AHB Slave Ports 1 and 2 Each of the secondary AHB slave ports are identical AHB-Lite compliant buses. It is envisioned that these ports will interface predominately to internal and external memory. However, it is possible to connect an external AIPI interface along with associated peripherals to these ports. The secondary port slave signals are list in Table 9-2 where “x” is equal to 1 or 2. Table 9-2. Secondary AHB Interface Signal List Pin List sx_haddr[31:0] sx_hmaster[3:0] sx_htrans[1:0] sx_hprot[3:0] sx_hmastlock sx_hwrite sx_hsize[1:0] sx_hburst[2:0] sx_hwdata[31:0] sx_hready sx_hrdata[31:0] sx_hresp0 1 Direction1 Output Output Output Output Output Output Output Output Output Input Input Input Description AHB Address Bus AHB Master ID AHB Transfer Type AHB Access Protection Indicator AHB-Lite Master Lock Indicator AHB Access Write Indicator AHB Transfer Size AHB Access Burst Type AHB Write Data AHB Termination/Take Indicator AHB Read Data AHB Error Indicator Direction is relative to the ARM9 Platform. 9.9.7 Endian Modes The ARM9 Platform will support both Big and Little Endian modes. The relevant signals to/from the ARM926EJ-S processor are shown in Table 9-3 below along with brief descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-26 Freescale Semiconductor ARM9 Platform Table 9-3. ARM926EJ-S Endian Related Signals Signal BIGENDINIT Direction Input Description Determines the setting of the BIGEND bit held in the CP15 control register after system reset. When HIGH, the reset state of the BIGEND bit will be 1 (Big Endian). When LOW, the reset state of the BIGEND bit will be 0 (Little Endian). ARM926EJ-S BIGEND configuration indicator. This signal reflects the value of the BIGEND bit held in the CP15 control register, which is used to determine the behavior of the ARM926EJ-S WRT endianness. When HIGH, the ARM926EJ-S treats bytes in memory as being in Big Endian format. When LOW, memory is treated as Little Endian. CFGBIGEND Output The bigendinit platform input is connected directly to the BIGENDINIT input of the ARM926EJ-S and determines the processor and platform Endian mode of operation upon exiting system reset. However, the endian mode of operation of the processor (and therefore the platform and associated memory systems) may be changed according to the BIGEND bit in the CP15 control register. This output, cfg_bigend, reflects the BIGEND bit and is used to indicate the current Endian mode of operation for the platform as well as all external bus masters and slaves. The relevant Endian signals are shown in Figure 9-9. ARM9 PLATFORM ETM/ETB etm_bigend ARM926EJ-S bigendinit BIGENDINIT CFGBIGEND (to external AHB masters and slaves) MCTL cfg_bigend ROMPATCH AIPI(2) Figure 9-9. Endian Configuration Routing The DHBL signals of the ARM926EJ-S will not be used within the platform. Instead, all modules affected by the Endian mode will use the cfg_bigend signal in conjunction with hsize and haddr[1:0] in order to handle non-word transfers correctly. It is not envisioned that applications will need to dynamically change Endianness. However, this is still under investigation, and should be possible since the platform will support both Endian modes in hardware. It then becomes a software issue to insure a graceful mode change. For example, the write buffers should be drained prior to changing Endian modes. 9.9.7.1 Affected Modules Only the AIPI (2), MCTL (RAM and ROM) and ROMPATCH modules are affected by the cfg_bigend signal within the platform. ETM9/ETB is affected by the Endian mode, and instead is connected to the etm_bigend signal internally. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-27 ARM9 Platform 9.9.7.2 Unaffected Modules The AITC module is 32-bit write only. The registers within the MAX are also 32-bit access only, and the Endian mode is transparent from the AHB switch perspective. The PAHBMUX module has no registers associated with it and the Endian mode is transparent to its data muxing. 9.9.7.3 Un-Aligned Transfers Unaligned transfers are not supported by the ARM9 Platform and therefore should not be attempted by alternate bus masters connected to it. That is, alternate bus masters should not attempt a 32-bit access to a non-word aligned address, nor a 16-bit access to a non half-word aligned address. The transfers will complete as normal, however the lower order address bits will be ignored according to Figure 9-4 and Figure 9-5. 9.9.7.4 Endian Mode and Alternate Bus Masters Alternate bus masters must be cognizant of the Endian mode if they are capable of performing non-word accesses. Non-word register and memory transactions will be performed according to the state of the cfg_bigend output signal. The manner in which memory is accessed in the two Endian modes is described in the following two sections. 9.9.7.5 Little Endian Operation A Little Endian configured ARM9 Platform (cfg_bigend = 0) should have memory connected to its secondary AHB ports as follows: • Byte 0 of the memory connected to D[7:0] • Byte 1 of the memory connected to D[15:8] • Byte 2 of the memory connected to D[23:16] • Byte 3 of the memory connected to D[31:24] The byte write enables should be decoded by the AHB slaves as in Table 9-4. Table 9-4. Little Endian Byte Write Enable Decoding hwrite 0 1 1 1 1 1 1 1 1 hsize[1:0] x 00 00 00 00 01 01 10 11 haddr[1:0] x 00 01 10 11 0x 1x xx we[31:24] 0 0 0 0 1 0 1 1 we[23:16] 0 0 0 1 0 0 1 1 Reserved we[15:8] 0 0 1 0 0 1 0 1 we[7:0] 0 1 0 0 0 1 0 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-28 Freescale Semiconductor ARM9 Platform 9.9.7.6 Big Endian Operation A Big Endian configured ARM9 Platform (cfg_bigend=1) should have memory connected to its secondary AHB ports as follows: • Byte 0 of the memory connected to D[31:24] • Byte 0 of the memory connected to D[23:16] • Byte 0 of the memory connected to D[15:8] • Byte 0 of the memory connected to D[7:0] The byte write enables should be decoded by the slaves as in Table 9-5. Table 9-5. Big Endian Byte Write Enable Decoding hwrite 0 1 1 1 1 1 1 1 1 hsize[1:0] x 00 00 00 00 01 01 10 11 haddr[1:0] x 00 01 10 11 0x 1x xx we[31:24] 0 1 0 0 0 1 0 1 we[23:16] 0 0 1 0 0 1 0 1 Reserved we[15:8] 0 0 0 1 0 0 1 1 we[7:0] 0 0 0 0 1 0 1 1 9.10 Preliminary Size Estimate Table 9-6 show preliminary size estimates for the ARM9 Platform. Note that the area estimates correspond to C90LP, WCS, 1.1 V, 105C. clk = 266 MHz, hclk = 133 MHz. Gate equivalents are scaled to the area of the C90LP NAND2_2 cell. Table 9-6. ARM9 Platform Size Estimates Block I-Cache Data Memory (1024x32) I-Cache Tag Memory (128x22) I-Cache Valid Memory (32x24) D-Cache Data Memory (1024x32) D-Cache Tag Memory (256x22) D-Cache Valid Memory (32x24) D-Cache Dirty Memory (128x8) MMU RAM (32x64) Number Included in Platform 4 4 1 4 4 1 1 2 Area in µm2 259,512 74,990 16,122* 259,512 149,980* 16,122* 8,242 73,286 Gate Count Total (NAND2_2) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-29 ARM9 Platform Table 9-6. ARM9 Platform Size Estimates (continued) Block ETB RAM (1024x32) Memories Total ARM926 Core ETM9 (Medium +) ETB11 AITC MCTL + ROM BIST AIPI AHBMUX MAX Scan Wrapper ROMPATCH BIST for Memories IP to AHB (for ETB11) Clock and Sync Control JAM Secure ROM monitor Clock Tree Logic Total 55% routing efficiency (logic only) Platform Total Number Included in Platform 2 23 1 1 1 1 1 2 1 1 1 1 4 1 1 1 1 2 TBD TBD TBD Area in µm2 129,756 987,522 350K TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Gate Count Total (NAND2_2) 9.11 Power Consumption Table 9-7 summarizes preliminary power estimates for the various ARM9 Platform operating modes. Power numbers will be measured off of the final freeze post-route netlist. There is no padding or margin included in these numbers. Table 9-7. ARM9 Platform Power Estimates Mode of Operation Run Mode Doze Mode BCS Corner (1.3 V –20C) TBD TBD TYP Corner (1.2 V 25C) TBD TBD WCS Corner (1.1 V, 105C) TBD TBD MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-30 Freescale Semiconductor ARM9 Platform Table 9-7. ARM9 Platform Power Estimates (continued) Mode of Operation Sleep Mode without Well Bias Active Sleep Mode with Well Bias Active BCS Corner (1.3 V –20C) TBD TBD TYP Corner (1.2 V 25C) TBD TBD WCS Corner (1.1 V, 105C) TBD TBD The operating modes are described below: • Run Mode clk, clk_always = 266MHz, hclk = 133MHz. Code running out of cache, once instructions loaded into cache. Exercising cache/MMU memories. Core busy with arithmetic operations. Activity on all alternate master ports and all slave ports concurrently. Compiled memory models pessimistic when memories not being accessed. Estimated loads on all platform outputs ranging from 0.5pf to 1.5pf. • Doze Mode clk, clk_always, and hclken stopped. hclk = 117MHz. No alternate bus master activity. Estimated loads on all platform outputs ranging from 0.5pf to 1.5pf. • Sleep Mode All clocks stopped. Includes: clk, clk_always, hclken, and hclk. Basically represents platform leakage current. No Dynamic or Static power in Sleep Mode. Well bias active power TYP very crude estimate of 10x reduction + compiled memories. Power due to charge pump not included since charge pump is external to the platform. WCS measured with well bias standard cell library. 9.12 ARM9 Platform I/O Signal List Table 9-8. ARM9 Platform Signal List Signal Type Clocks and Resets clk clk_always hclk hclken a9p_clk_off por hreset_b Input Input Input Input Output Input Input Processor and Nexus reference clock CLK that always runs AHB domain reference clock Controls ARM926EJ-S sampling of HCLK domain To External Clock Control Module: The ARM9 Platform CLK may be turned off Power-On Reset System reset (ARM926EJ-S and AHB reset) Description The complete list of inputs and outputs for the ARM9 Platform are listed in Table 9-8. Platform Configuration MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-31 ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal bigendinit cfg_bigend Type Input Output Description 1 = Big Endian, 0 = Little Endian Determines initial Endian mode out of reset 1 = Big Endian, 0 = Little Endian Reflects the value of BIGEND bit in ARM926EJ-S CP15 register. Determines endianness of platform slaves and external AHBs. Internal Boot Indicator External Boot Address Bus monitor timeout boot_int ext_boot_adr[31:2] bmon_timeout[2:0] Input Input Input JTAG Interface and Related I/O jtag_tck jtag_trst_b jtag_tms jtag_tdi jtag_tdo jtag_tdoen_b tapid_ver[3:0] dbgrtck Input Input Input Input Output Output Input Output JTAG Test Clock JTAG Test Reset JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output JTAG Test Data Output Tri-state Control Platform Version Number (JTAG ID register bits [11:8]) TCK “return clock” from JTAG synchronization ARM926 Debug Related Signals dbgrq dbgack dbgext[1:0] dbgiebkpt dbgdewpt arm_dbgrng[1:0] arm_standbywfi arm_java_mode arm_thumb_mode arm_fiq_b arm_irq_b arm_fiq_disable arm_irq_disable arm_cpsr_mode[4:0] Input Output Input Input Input Output Output Output Output Output Output Output Output Output To ARM926: Debug request (connected to EDBGRQ) From ARM926: Debug Acknowledge To ICE: External breakpoints/watchpoints To ARM926: Instruction breakpoint To ARM926: Data watchpoint From ARM926: Embedded ICE-RT range out From ARM926: Processor is in wait for interrupt mode From ARM926: Processor is in JAVA mode From ARM926: Processor is in THUMB mode From AITC: Fast interrupt request to processor From AITC: Interrupt request to processor From ARM926: Processor has disabled FIQ interrupts From ARM926: Processor has disabled IRQ interrupts From ARM926: Processor CPSR mode bits Platform Debug Related Signals MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-32 Freescale Semiconductor ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal dbg_iahb_hready dbg_iahb_htrans1 dbg_iahb_haddr[31:29] dbg_dahb_hready dbg_dahb_htrans1 dbg_dahb_haddr[31:29] dbg_pahb_hready dbg_pahb_htrans1 dbg_pahb_hmaster[3:0] dbg_a9p_ahb_en Type Output Output Output Output Output Output Output Output Output Output Description ARM926EJ-S I-AHB hready ARM926EJ-S I-AHB htrans[1] ARM926EJ-S I-AHB requested address (top 3 bits) ARM926EJ-S D-AHB hready ARM926EJ-S D-AHB htrans[1] ARM926EJ-S D-AHB requested address (top 3 bits) Primary AHB hready Primary AHB htrans[1] Primary AHB hmaster ownership Enable output used for GPIO muxing of these debug signals MCTL ROM Memory Interface rom_connect rom_max_addr[11:0] rom_wait Input Input Input Indicates ROM exists on the MCTL interface. Indicates ROM size. Corresponds to HADDR[21:10]. Smallest size supported is 1Kbyte, largest 4 Mbyte. ROM wait-state indicator 0 = No wait-state required 1 = One wait-state required MCU ROM chip enable MCU ROM address. ROM read data mctl_ce_rom_b mctl_addr_rom[19:0] mem_q_rom[31:0] Output Output Input MCTL RAM Memory Interface ram_connect ram_max_addr[9:0] ram_wait Input Input Input Indicates RAM exists on the MCTL interface. Indicates RAM size. Corresponds to HADDR[19:10]. Smallest size supported is 1Kbyte, largest 1 Mbyte. RAM read cycle wait-state indicator 0 = No wait-state required 1 = One wait-state required MCU RAM mbist SDD test mode output Testmode control of external memories’ output enable. This output should be connected to the OEN ports of all memories external to the ARM9 Platform (SRAM and TCM). MCU RAM chip enable MCU RAM access type: read=0, write=1 MCU RAM address MCU RAM byte enables mctl_mbist_sddtm extram_oe Output Output mctl_ce_ram_b mctl_wr_ram_b mctl_addr_ram[17:0] mctl_ben_ram_7_0 Output Output Output Output MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-33 ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal mctl_ben_ram_15_8 mctl_ben_ram_23_16 mctl_ben_ram_31_24 mctl_d_ram[31:0] mem_q_ram[31:0] Type Output Output Output Output Input MCU RAM byte enables MCU RAM byte enables MCU RAM byte enables RAM write data RAM read data Description Multi-Layer AHB Master Port 2 m2_hlock m2_hmastlock m2_hmaster[3:0] m2_htrans[1:0] m2_hprot[3:0] m2_hwrite m2_hsize[1:0] m2_hburst[2:0] m2_haddr[31:0] m2_hwdata[31:0] m2_hready_out m2_hrdata[31:0] m2_hresp0 Input Input Input Input Input Input Input Input Input Input Output Output Output AHB Locked Cycle Indicator (bus request timing) AHB Locked Cycle Indicator (address timing) AHB Master AHB Transfer Type AHB Protection Control AHB Write/Read Indicator AHB Transfer Size AHB Burst Length AHB Address AHB Write Data AHB Transfer Done Out AHB Read Data AHB Transfer Response Multi-Layer AHB—Master Port 3 m3_hlock m3_hmastlock m3_hmaster[3:0] m3_htrans[1:0] m3_hprot[3:0] m3_hwrite m3_hsize[1:0] m3_hburst[2:0] m3_haddr[31:0] m3_hwdata[31:0] m3_hready_out m3_hrdata[31:0] Input Input Input Input Input Input Input Input Input Input Output Output AHB Locked Cycle Indicator (bus request timing) AHB Locked Cycle Indicator (address timing) AHB Master AHB Transfer Type AHB Protection Control AHB Write/Read Indicator AHB Transfer Size AHB Burst Length AHB Address AHB Write Data AHB Transfer Done Out AHB Read Data MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-34 Freescale Semiconductor ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal m3_hresp0 Type Output AHB Transfer Response Description Multi-Layer AHB Master Port 4 m4_hlock m4_hmastlock m4_hmaster[3:0] m4_htrans[1:0] m4_hprot[3:0] m4_hwrite m4_hsize[1:0] m4_hburst[2:0] m4_haddr[31:0] m4_hwdata[31:0] m4_hready_out m4_hrdata[31:0] m4_hresp0 Input Input Input Input Input Input Input Input Input Input Output Output Output AHB Locked Cycle Indicator (bus request timing) AHB Locked Cycle Indicator (address timing) AHB Master AHB Transfer Type AHB Protection Control AHB Write/Read Indicator AHB Transfer Size AHB Burst Length AHB Address AHB Write Data AHB Transfer Done Out AHB Read Data AHB Transfer Response Multi-Layer AHB Master Port 5 m5_hlock m5_hmastlock m5_hmaster[3:0] m5_htrans[1:0] m5_hprot[3:0] m5_hwrite m5_hsize[1:0] m5_hburst[2:0] m5_haddr[31:0] m5_hwdata[31:0] m5_hready_out m5_hrdata[31:0] m5_hresp0 Input Input Input Input Input Input Input Input Input Input Output Output Output AHB Locked Cycle Indicator (bus request timing) AHB Locked Cycle Indicator (address timing) AHB Master AHB Transfer Type AHB Protection Control AHB Write/Read Indicator AHB Transfer Size AHB Burst Length AHB Address AHB Write Data AHB Transfer Done Out AHB Read Data AHB Transfer Response Multi-Layer AHB Slave Port 1 s1_hmastlock s1_hmaster[3:0] Output Output AHB Locked Transfer AHB Master MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-35 ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal s1_htrans[1:0] s1_hprot[3:0] s1_hwrite s1_hsize[1:0] s1_hburst[2:0] s1_haddr[31:0] s1_hwdata[31:0] s1_hrdata[31:0] s1_hready s1_hresp0 Type Output Output Output Output Output Output Output Input Input Input AHB Transfer Type AHB Protection Control AHB Write/Read Indicator AHB Transfer Size AHB Burst Length AHB Address AHB Write Data AHB Read Data Transfer Done Transfer Response Description Multi-Layer AHB Slave Port 2 s2_hmastlock s2_hmaster[3:0] s2_htrans[1:0] s2_hprot[3:0] s2_hwrite s2_hsize[1:0] s2_hburst[2:0] s2_haddr[31:0] s2_hwdata[31:0] s2_hrdata[31:0] s2_hready s2_hresp0 Output Output Output Output Output Output Output Output Output Input Input Input AHB Locked Transfer AHB Master AHB Transfer Type AHB Protection Control AHB Write/Read Indicator AHB Transfer Size AHB Burst Length AHB Address AHB Write Data AHB Read Data Transfer Done Transfer Response MAX Specific (Crossbar Switch) ccm_hbusreq ccm_hgrant s0_ampr_sel s1_ampr_sel s2_ampr_sel Input Output Input Input Input External Clock Control Module Low-power Bus Request Low-power Mode Bus Grant Slave port 0 alternate master priority register select. Slave port 1 alternate master priority register select. Slave port 2 alternate master priority register select. IP Bus #1 (A) ipsa_module_en[31:1] ipsa_addr[11:0] Output Output IP Bus “A” Module Select IP Bus “A” Address MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-36 Freescale Semiconductor ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal ipsa_wdata[31:0] ipsa_byte_31_24 ipsa_byte_23_16 ipsa_byte_15:8 ipsa_byte_7_0 ipsa_rwb ipsa_supervisor_access ipsa_rdata[31:0] ipsa_xfr_wait ipsa_xfr_err Type Output Output Output Output Output Output Output Input Input Input IP Bus “A” Write Data IP Bus “A” Byte Select IP Bus “A” Byte Select IP Bus “A” Byte Select IP Bus “A” Byte Select IP Bus “A” Read/Write Indicator IP Bus “A” Supervisor Mode Access Control IP Bus “A” Read Data IP Bus “A” Transfer Wait State Indicator IP Bus “A” Transfer Error Indicator IP Bus #2 (B) ipsb_module_en[17:1] ipsb_addr[11:0] ipsb_wdata[31:0] ipsb_byte_31_24 ipsb_byte_23_16 ipsb_byte_15:8 ipsb_byte_7_0 ipsb_rwb ipsb_supervisor_access ipsb_rdata[31:0] ipsb_xfr_wait ipsb_xfr_err Output Output Output Output Output Output Output Output Output Input Input Input IP Bus “B” Module Select IP Bus “B” Address IP Bus “B” Write Data IP Bus “B” Byte Select IP Bus “B” Byte Select IP Bus “B” Byte Select IP Bus “B” Byte Select IP Bus “B” Read/Write Indicator IP Bus “B” Supervisor Mode Access Control IP Bus “B” Read Data IP Bus “B” Transfer Wait State Indicator IP Bus “B” Transfer Error Indicator ETM/ETB etm_traceclk etm_clkdivtwoen etm_dbgrq etm_etmen etm_pipestat[2:0] etm_tracepkt[15:0] etm_tracesync etm_portsize[2:0] Output Output Output Output Output Output Output Output ETM Trace Clock ETM half rate clocking mode Debug Request. ETM Enabled Pipeline Status ETM Trace Packet Trace synchronization. ETM Port Size. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-37 ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal etm_portmode[1:0] etb_full etb_acqcomp etm_extout ect_dbgrq etm_extin[3:0] Type Output Output Output Output Input Input Description Normal, Multiplexed, or Demultiplexed mode of operation ETB Overflow Indicator ETB Trace Acquisition Complete External ETM Outputs Debug Request. External ETM Inputs. Miscellaneous aitc_rise_arb a9p_mem_on a9p_mem_pwr_dn a9p_int_b[63:0] a9p_dsm_int_holdoff wt_en wt_en_dnw Output Input Input Input Input Input Input Interrupt pending, raise arbitration priority if desired Used with a9p_mem_pwr_dn to power off ARM926 ICACHE, DCACHE, and MMU memories Used with a9p_mem_on to power off ARM926 ICACHE, DCACHE, and MMU memories External Interrupts Deep Sleep Module Interrupt Disable Well Tie Input (Physical connection only) Well Tie Input for deep n-wells (Physical connection only) Platform Scan Test Interface ipt_mode[3:0] ipt_clk_se ipt_memory_read_inhibit_int Input Input Input Test Mode Control Clock Gating Cell Scan Enable Disables memory read operations from internal memories (caches, ETB) during scan testing. Read data is forced to zeros when asserted. When negated, memories function normally. Scan Chain Length Control Scan Shift Enable Platform Test Serial In Platform Test Serial Out ipt_scan_size[1:0] ipt_scan_enable ipt_scan_in[66:0] ipt_scan_out[66:0] Input Input Input Output Scan Wrapper Test Interface ipt_wrapper_clk_in[1:0] Input Platform Wrapper Clocks [0] = CLK Domain [1] = HCLK Domain Scan Shift Enable Scan Wrapper Chain Length Scan Wrapper Test Serial In [2:0] = CLK [11:3] = HCLK ipt_wrapper_se ipt_wrapper_scan_size[1:0] ipt_wrapper_scan_in[23:0] Input Input Input MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-38 Freescale Semiconductor ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal ipt_wrapper_scan_out[23:0] Type Output Description Scan Wrapper Test Serial Out [2:0] = CLK [11:3] = HCLK Memory BIST Interface ipt_bist_fail ipt_bist_done ipt_bist_bitmap[15:0] ipt_bist_sdo ipt_bist_addr_out[17:0] ipt_bist_bmdata_avail ipt_bist_done_dcache ipt_bist_done_etb ipt_bist_done_icache ipt_bist_done_mmu ipt_bist_done_mram ipt_bist_done_mrom ipt_bist_fail_dcache ipt_bist_fail_etb ipt_bist_fail_icache ipt_bist_fail_mmu ipt_bist_fail_mram ipt_bist_config_addr_mode[2:0] ipt_bist_config_alt_al_en ipt_bist_config_aftest_en ipt_bist_config_dpat_en[7:0] ipt_bist_config_dret_en ipt_bist_config_dsof ipt_bist_config_marchc_en ipt_bist_config_sdd_en ipt_bist_config_sel_dcache ipt_bist_config_sel_etb ipt_bist_config_sel_icache ipt_bist_config_sel_mmu Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Aggregate Memory BIST Fail Status Aggregate Memory BIST Execution Status Memory BIST Bitmap Data Out Memory BIST Bitmap Serial Data Out Memory BIST Address Out Memory BIST Bitmap Data Strobe Data Cache Memory BIST Done ETB Memory BIST Done Instruction Cache Memory BIST Done MMU Memory BIST Done MCTL RAM Memory BIST Done MCTL ROM Memory BIST Done Data Cache Memory BIST Fail ETB Memory BIST Fail Instruction Cache Memory BIST Fail MMU Memory BIST Fail MCTL RAM Memory BIST Fail Memory BIST Address Mode Selection Memory BIST Alternate Algorithm Enable Memory BIST Address Fault Test Enable Memory BIST Data Pattern Enable Memory BIST Data Retention Test Enable Memory BIST Disable “Stop on Fail” Memory BIST Marching Pattern Test Enable Memory BIST SDD Test Enable Memory BIST Data Cache Engine Select Memory BIST ETB Engine Select Memory BIST Instruction Cache Engine Select Memory BIST MMU Engine Select MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-39 ARM9 Platform Table 9-8. ARM9 Platform Signal List (continued) Signal ipt_bist_config_sel_mram ipt_bist_config_sel_mrom ipt_bist_config_usrctrl_bm ipt_bist_invoke ipt_bist_mode[2:0] ipt_bist_release ipt_bist_repdata_out_en ipt_bist_reset ipt_bist_retention_en ipt_bist_sdi ipt_bist_serial_data_en ipt_bist_shift_clk Type Input Input Input Input Input Input Input Input Input Input Input Input Description Memory BIST MCTL RAM Engine Select Memory BIST MCTL ROM Engine Select Memory BIST User Controlled Parallel Bitmap Output Rate Memory BIST Invoke Memory BIST Mode Select Memory BIST Pause State Release Memory BIST Repair Data Output Enable Memory BIST Reset Memory BIST Retention Enable Memory BIST Serial Data In Memory BIST Serial Data Enable Memory BIST Shift Clock 9.13 Electrical Specifications This section will present timing information for all major AHBs (both internal and external) to the platform. Timing information on all other signals on the platform periphery will be grouped by functionality and presented after the AHB timings. 9.13.1 Conditions The timing presented in this section were derived from an ARM926EJ-S synthesis run using the C90LP library, worst case process, 105oC, 1.10 V with clk running at 266 MHz. In this case, the hclk domain (all AHBs) will run at half the clk speed or 133 MHz. 9.13.2 Well Bias Mode The timing specifications in this section do not cover the well bias mode of operation. At the present time, well bias mode is planned to be used in Sleep Mode only. That is, clk and hclk will be stopped and the platform buses will be inactive. However, the negation of the a9p_clock_off output when an interrupt is asserted is still required in order for the external clock control module to exit Sleep Mode and turn on the clocks. The delay for the a9p_int_b[61:0] to a9p_clock_off path will be affected by well bias mode, but not significantly so. 9.13.2.1 Functional Operation in Well Bias Mode Programmable options should be used to support laboratory testing of the platform in well bias mode. The platform’s AC performance will be impacted (slower) when well biasing is enabled and is TBD. Care MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-40 Freescale Semiconductor ARM9 Platform should be taken to identify external interfaces which may not be running in well bias mode as clock insertion and clock skew differences may prevent proper operation. 9.13.3 clk and jtag_tck Relationship The jtag_tck clock input must always be less than 1/8 the frequency of the clk clock input. This constraint is due to the JTAG synchronization logic in the CLKCTL module. During the execution of low-power code, the frequency of clk is dynamic, and therefore care should be taken that jtag_tck is always less than 1/8 the frequency of clk at any given instant. To maximize throughput via the JTAG port when uploading/downloading code or memory images, it is suggested the debugger enter debug mode directly out of reset with clk and jtag_tck running as fast as possible. However, once normal mode low-power code execution begins, the jtag_tck frequency should be set to be 1/8 the frequency of the lowest possible clk frequency. 9.13.4 Clocks and Reset Timing Table 9-9 and Figure 9-10 are valid for all AHB interfaces on the ARM9 Platform. The same clock insertion delay and hreset_b negation timing will be used for all modules on the ARM9 Platform. Table 9-9. ARM9 Platform AHB Clock and Reset Timing Constraints Description CLK_ROOT Period CLK_ROOT jitter (3% rounded up) HCLK_ROOT Period HCLK_ROOT jitter (3% rounded up) CLK_ROOT to CLK and HCLK_ROOT to HCLK Insertion Delay (Tinsert) CLK and HCLK Uncertainty HRESET_B hold time to HCLK_LEAF (Tihrst) HRESET_B setup time to HCLK_LEAF (Tisrst) HCLKEN setup time to CLK_LEAF (Tisclken) HCLKEN hold time to CLK_LEAF (Tihclken) Delay 3.75 ns (266 MHz) 115.0 ps 7.5 ns (133 MHz) 230.0 ps 1.60 +/- 0.100 ns 200 ps 1.80 ns 1.60 ns 2.00 ns 0.00 ns MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-41 ARM9 Platform CLK_ROOT CLK_LEAF HCLK_ROOT HCLK_LEAF HRESET_B Tihrst Tinsert HCLKEN Tisclken Tisrst Figure 9-10. ARM9 Platform AHB Clock and Reset Timing Relationship 9.13.5 Alternate Bus Master (ABM) Interface Timing Table 9-10 shows the loading constraints used on all ARM9 Platform Alternate Bus Master bus interfaces. The timing parameters in Figure 9-11 reflect these constraints. The Alternate Bus Master signals are designated by the “MX_” prefix attached to the normal AHB naming convention. Table 9-10. Alternate Bus Master Constraints Description All Output Loading Input Transition Time (platform boundary) Value 0.50 pf 0.750 ns (20/80) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-42 Freescale Semiconductor ARM9 Platform HCLK_ROOT Tinsert HCLK_LEAF MX_HTRANS[1:0] MX_HPROT[3:0] MX_HLOCK MX_HMASTLOCK MX_HMASTER Transfer Type Tistr Address Tihtr MX_HADDR[31:0] Tisa MX_HBURST[3:0] MX_HWRITE Transfer Control Tiha Tisctl MX_HWDATA[31:0] MX_HSIZE[2:0] Tihctl Write Data (A) Tihwd Tiswd MX_HREADY_OUT Tovrdyo MX_HRDATA[31:0] Read Data (A) Tohrdyo Tovrd Tohrd MX_HRESP[1:0] OK Tovrsp Tohrsp Figure 9-11. Alternate Bus Master Timing Parameters MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-43 ARM9 Platform Table 9-11. Alternate Bus Master Interface AC Timing Parameters Description HCLK_LEAF minimum clock period including jitter MX_HMASTER/MX_HTRANS/MX_HPROT/MX_HLOCK/MX_HMASTLOCK/M X_HMASTER Transfer Type setup time before HCLK_LEAF MX_HMASTER/MX_HTRANS/MX_HPROT/MX_HLOCK/MX_HMASTLOCK/ MX_HMASTER Transfer Type hold time after HCLK_LEAF MX_HADDR[31:0] Address setup time before HCLK_LEAF MX_HADDR[31:0] Address hold time after HCLK_LEAF MX_HWRITE/MX_HSIZE/MX_HBURST control signal setup time before HCLK_LEAF MX_HWRITE/MX_HSIZE/MX_HBURST control signal hold time after HCLK_LEAF MX_HWDATA Write Data setup time before HCLK_LEAF MX_HWDATA Write Data hold time after HCLK_LEAF MX_HREADY_OUT Ready Out valid time after HCLK_LEAF MX_HREADY_OUT Ready Out hold time after HCLK_LEAF MX_HRDATA Read Data valid time after HCLK_LEAF MX_HRDATA Read Data hold time after HCLK_LEAF MX_HRESP0 valid time after HCLK_LEAF MX_HRESP0 hold time after HCLK_LEAF Parameter Tclk Tistr Tihtr Tisa Tiha Tisctl Tihctl Tiswd Tihwd Tovrdyo Tohrdyo Tovrd Tohrd Tovrsp Tohrsp Timing (ns) 7.27 6.23 >0 6.23 >0 6.23 >0 6.00 >0 4.80 >0 6.00 >0 6.00 >0 9.13.6 Secondary AHB Timing Table 9-12 shows the loading constraints used on all ARM9 Platform Secondary AHB interfaces. The timing parameters in Figure 9-13 reflect these constraints. The constraints and AC parameters are valid for all 3 of the platform’s secondary AHBs. The Secondary AHB signals are designated by the “SX_” prefix attached to the normal AHB naming convention. Table 9-12. Secondary AHB Constraints Description SX_HADDR, SX_HWDATA Loading All Other Output Loading Input Transition Time (at platform boundary) Value 0.50 pf 0.50 pf 0.75 ns (20/80) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-44 Freescale Semiconductor ARM9 Platform HCLK_ROOT Tinsert HCLK_LEAF SX_HTRANS[1:0] SX_HPROT[3:0] SX_HMASTLOCK SX_HMASTER[3:0] Transfer Type Tohtr Tovtr Address SX_HADDR[31:0] Tova SX_HWRITE SX_HSIZE[1:0] SX_HBURST[3:0] Transfer Control Toha Tovctl SX_HWDATA[31:0] Tohctl Write Data (A) Tovwd SX_HREADY Tohwd Tisrdy Tihrdy SX_HRDATA[31:0] Read Data (A) Tisrd SX_HRESP0 OK Tihrd Tisrsp Figure 9-12. Secondary AHB AC Timing Parameters Table 9-13. Secondary AHB AC Timing Parameters Description HCLK_LEAF minimum clock period including jitter SX_HTRANS/SX_HPROT/SX_HMASTLOCK/SX_HMASTER Transfer Type valid time after HCLK_LEAF Parameter Tclk Tovtr Tihrsp Timing (ns) 7.27 5.00 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-45 ARM9 Platform Table 9-13. Secondary AHB AC Timing Parameters (continued) Description SX_HTRANS/SX_HPROT/SX_HMASTLOCK/SX_HMASTER Transfer Type hold time after HCLK_LEAF SX_HADDR[31:0] Address valid time after HCLK_LEAF SX_HADDR[31:0] Address hold time after HCLK_LEAF SX_HWRITE/SX_HSIZE/SX_HBURST control signal valid time after HCLK_LEAF SX_HWRITE/SX_HSIZE/SX_HBURST control signal hold time after HCLK_LEAF SX_HWDATA Write Data valid time after HCLK_LEAF SX_HWDATA Write Data hold time after HCLK_LEAF SX_HREADY setup time before HCLK_LEAF (input to slaves) SX_HREADY hold time after HCLK_LEAF SX_HRDATA setup time before HCLK_LEAF SX_HRDATA hold time after HCLK_LEAF SX_HRESP0 setup time before HCLK_LEAF SX_HRESP0 hold time after HCLK_LEAF Parameter Tohtr Tova Toha Tovctl Tohctl Tovwd Tohwd Tisrdy Tihrdy Tisrd Tihrd Tisrsp Tihrsp Timing (ns) >0 4.30 >0 5.70 >0 5.70 >0 5.60 >0 4.10 >0 4.10 >0 9.13.7 RAM and ROM Interface Timing Table 9-14 shows the loading constraints used when generating timing parameters on the ARM9 Platform’s RAM and ROM interfaces. External RAM and ROM interface signals not shown in the table below are either static or test related. Table 9-14. RAM and ROM Interface Loading Constraints Signal RAM MCTL_OEN_RAM MCTL_CE_RAM_B MCTL_WR_RAM_B MCTL_ADDR_RAM[17:0] MCTL_BEN_RAM_*_* MCTL_D_RAM[31:0] MEM_Q_RAM[31:0] Output Output Output Output Output Output Input 0.50 pf 0.25 pf 0.50 pf 0.50 pf 0.50 pf 0.50 pf 0.75 ns (Input Transition Time) Type Constraint ROM MCTL_CE_ROM_B Output 0.25 pf MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-46 Freescale Semiconductor ARM9 Platform Table 9-14. RAM and ROM Interface Loading Constraints (continued) Signal MCTL_ADDR_ROM[19:0] MEM_Q_ROM[31:0] Type Output Input Constraint 0.50 pf 0.75 ns (Input Transition Time) hclk hclk_leaf Tovaram mctl_addr_ram[17:0] Tovdram mctl_d_ram[31:0] Tovcram mctl_ce_ram_b Tovwram mctl_wr_ram_b Tovbram mctl_ben_ram Tisqram mem_q_ram[31:0] Tovarom mctl_addr_rom[19:0] Tovcrom mctl_ce_rom_b Tisqrom mem_q_rom[31:0] Figure 9-13. RAM and ROM Interface AC Timing Parameters Table 9-15. RAM and ROM Interface AC Timing Parameters Description HCLK_LEAF minimum clock period RAM MCTL_ADDR_RAM valid time after HCLK_LEAF Tovaram 6.65 Parameter Tclk Timing (ns) 8.40 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 9-47 ARM9 Platform Table 9-15. RAM and ROM Interface AC Timing Parameters (continued) Description MCTL_D_RAM valid time after HCLK_LEAF MCTL_CE_RAM_B valid time after HCLK_LEAF MCTL_WR_RAM_B valid time after HCLK_LEAF MCTL_BEN_RAM_*_* valid time after HCLK_LEAF MEM_Q_RAM setup time before HCLK_LEAF MEM_Q_RAM hold time after HCLK_LEAF ROM MCTL_ADDR_ROM valid time after HCLK_LEAF MCTL_CE_ROM_B valid time after HCLK_LEAF MEM_Q_ROM setup time before HCLK_LEAF MEM_Q_ROM hold time after HCLK_LEAF Tovarom Tovcrom Tisqrom Tihqrom 6.55 6.80 3.85 >0 Parameter Tovdram Tovcram Tovwram Tovbram Tisqram Tihqram Timing (ns) 6.60 6.70 6.55 6.6 4.65 >0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 9-48 Freescale Semiconductor Chapter 10 ARM926EJ-S Interrupt Controller (AITC) The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral that collects interrupt requests from up to 64 sources, and provides an interface to the ARM926EJ-S core. The AITC includes software-controlled priority levels for normal interrupts. Figure 10-1 shows the simplified block diagram of the AITC. 64 INTENABLE 64 intin FORCE 64 INTTYPE 64 64 64 fipend aitc_fiq 6 Priority Encoder fivector 64 nipend Software Priority Encoder nivector 6 aitc_irq aitc_rdata_ovr NM 32 haddr Equals to 0x0000_0018? Equals to 0x0000_001C? FM hready 32 aitc_rdata Opcode Generator Figure 10-1. AITC Block Diagram 10.1 Overview The AITC consists of a set of control registers and associated logic to perform interrupt masking, and priority support of normal interrupts. Interrupt source registers (INTSRCH/INTSRCL) are a pair of 32-bit status registers with a single interrupt source associated with each of the 64 bits. An interrupt line or set of interrupt lines are routed from each interrupt source to the INTSRCH or INTSRCL register. This allows up to 64 distinct interrupt sources in an implementation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-1 ARM926EJ-S Interrupt Controller (AITC) 10.1.1 10.1.2 Features Modes of Operation Interrupt requests may be forced to be asserted by way of the interrupt force registers (INTFRCH/INTFRCL). Each bit in this register is logically “OR-ed” with the corresponding hardware request line prior to feeding the INTSRCH or INTSRCL register inputs. There is a corresponding set of interrupt enable registers (INTENABLEH/INTENABLEL), also 32-bits wide which allow individual bit masking of the INTSRCH/INTSRCL registers. There is also a corresponding set of interrupt type register (INTTYPEH/INTTYPEL), which selects whether an interrupt source will generate a normal or fast interrupt to the ARM926EJ-S core. There is a corresponding set of normal interrupt pending registers (NIPNDH/NIPNDL) which indicate pending normal interrupt requests. These registers are equivalent to the logical AND of the interrupt source registers (INTSRCH/INTSRCL), the interrupt enable registers (INTENABLEH/INTENABLEL), and the NOT of the interrupt type registers (INTTYPEH/INTTYPEL). (Refer to Figure 10-1) The NIPNDH/NIPNDL register bits are bit-wise “NOR-ed” together to form the nIRQ signal routed to the ARM926EJ-S core. This core input signal is maskable by the normal interrupt disable bit (I bit) in the processor status register (CPSR). The normal interrupt vector register (NIVECSR) indicates the vector index of highest priority pending normal interrupt. There is a corresponding set of fast interrupt pending registers (FIPNDH/FIPNDL) which indicate pending fast interrupt requests. These registers are equivalent to logical AND of interrupt source registers (INTSRCH/INTSRCL), interrupt enable registers (INTENABLEH/INTENABLEL), and interrupt type registers (INTTYPEH/INTTYPEL). (Refer to Figure 10-1) FIPNDH/FIPNDL register bits are bit-wise “NOR-ed” together to form the nFIQ signal routed to the ARM926EJ-S core. This core input signal is maskable by the fast interrupt disable bit (F bit) in the CPSR. The fast interrupt vector register (FIVECSR) indicates the vector index of highest priority pending fast interrupt. AITC supports two vector table modes: high memory and low memory. If AITC is in high memory vector table mode, opcode is “LDR PC, [PC,#-(288-4*(vector index)]”. This causes ARM926-ES core to load the Program Counter (PC) with a vector from a table of 64 vectors located at 0xFFFF_FF00 to 0xFFFF_FFFF; more specifically the PC is loaded with the vector located at 0xFFFF_FF00 + 4*(vector index). If AITC is in low memory vector table mode, this opcode is “LDR PC, [PC, #((table pointer)+4*(vector index) –32]”. This causes the ARM926-EJS core to load the PC with a vector from a table of 64 vectors beginning at (table pointer) and ending at (table pointer)+0xFF; more specifically the PC is loaded with the vector located at (table pointer) + 4*(vector index). This hardware mechanism alleviates the need for software to determine which interrupt source caused the interrupt to be asserted. All interrupt controller registers can be read and written during privileged mode only. Writes attempted to read-only registers will be ignored. These registers can be only modified using 32-bit writes. INTFRCH/INTFRCL registers are provided for software generation of interrupts. By enabling interrupts for these bit positions, software can force an interrupt request. This register can also be used to debug hardware interrupt service routines by providing an alternate method of interrupt assertion. The interrupt requests are prioritized in the following sequence: 1. Fast interrupt requests, in order of highest number 2. Normal interrupt requests, in order of highest priority level, then highest source number with the same priority MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-2 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) AITC provides 16 software controlled priority levels for normal interrupts. Every interrupt can be placed in any priority level. The AITC also provides a normal interrupt priority level mask (NIMASK) which disables any interrupt with a priority level lower than or equal to the mask. If a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt will be selected assuming that NIMASK has not disabled level 1 normal interrupts. If two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number will be selected, also assuming that NIMASK has not disabled level 1 normal interrupts. 10.2 Memory Map and Register Definition AITC module has 26 registers. All of these registers are single cycle access as the AITC sits on the native bus of the ARM926EJ-S core. This section provides the detailed descriptions for all of the AITC registers. 10.2.1 Memory Map Table 10-1. AITC Memory Map Table 10-1 shows the AITC memory map. Address Register General Registers Access Reset Value Section/Page 0x1004_0000 (INTCNTL) 0x1004_0004 (NIMASK) 0x1004_0008 (INTENNUM) 0x1004_000C (INTDISNUM) 0x1004_0010 (INTENABLEH) 0x1004_0014 (INTENABLEL) 0x1004_0018 (INTTYPEH) 0x1004_001C (INTTYPEL) 0x1004_0020 (NIPRIORITY7) 0x1004_0024 (NIPRIORITY6) 0x1004_0028 (NIPRIORITY5) 0x1004_002C (NIPRIORITY4) Interrupt Control Register Normal Interrupt Mask Register Interrupt Enable Number Register Interrupt Disable Number Register Interrupt Enable Register High Interrupt Enable Register Low Interrupt Type Register High Interrupt Type Register Low Normal Interrupt Priority Level Register 7 Normal Interrupt Priority Level Register 6 Normal Interrupt Priority Level Register 5 Normal Interrupt Priority Level Register 4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x0000_0000 0x0000_001F 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 10.2.3/10-8 10.2.4/10-10 10.2.5/10-11 10.2.6/10-11 10.2.7/10-12 10.2.7/10-12 10.2.8/10-13 10.2.8/10-13 10.2.9/10-14 10.2.9/10-14 10.2.9/10-14 10.2.9/10-14 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-3 ARM926EJ-S Interrupt Controller (AITC) Table 10-1. AITC Memory Map (continued) Address 0x1004_0030 (NIPRIORITY3) 0x1004_0034 (NIPRIORITY2) 0x1004_0038 (NIPRIORITY1) 0x1004_003C (NIPRIORITY0) 0x1004_0040 (NIVECSR) 0x1004_0044 (FIVECSR) 0x1004_0048 (INTSRCH) 0x1004_004C (INTSRCL) 0x1004_0050 (INTFRCH) 0x1004_0054 (INTFRCL) 0x1004_0058 (NIPNDH) 0x1004_005C (NIPNDL) 0x1004_0060 (FIPNDH) 0x1004_0064 (FIPNDL) Register Normal Interrupt Priority Level Register 3 Normal Interrupt Priority Level Register 2 Normal Interrupt Priority Level Register 1 Normal Interrupt Priority Level Register 0 Normal Interrupt Vector and Status Register Fast Interrupt Vector and Status Register Interrupt Source Register High Interrupt Source Register Low Interrupt Force Register High Interrupt Force Register Low Normal Interrupt Pending Register High Normal Interrupt Pending Register High Fast Interrupt Pending Register High Fast Interrupt Pending Register Low Access R/W R/W R/W R/W R R R R R/W R/W R R R R Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xFFFF_FFFF 0xFFFF_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 10.2.9/10-14 10.2.9/10-14 10.2.9/10-14 10.2.9/10-14 10.2.10/10-22 10.2.11/10-23 10.2.12/10-24 10.2.12/10-24 10.2.13/10-27 10.2.13/10-27 10.2.14/10-28 10.2.14/10-28 10.2.15/10-29 10.2.15/10-29 10.2.2 Register Summary Figure 10-2 shows the key to the register fields and Table 10-2 shows the register figure conventions. Always reads 1 1 Always 0 reads 0 R/W BIT Read- BIT Write-only bit only bit bit Write 1 BIT Self-clear 0 to clear bit w1c BIT N/A BIT Figure 10-2. Key to Register Fields MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-4 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Table 10-2. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 10-3 shows the AITC register summary. Table 10-3. AITC Register Summary Name R 0x1004_0000 (INTCNTL) W R W R 0x1004_0004 (NIMASK) W R W R 0x1004_0008 (INTENNUM) W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 NIDI FIDI S S NIA D FIA D 0 0 MD 0 0 0 0 0 0 POINTER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NIMASK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENNUM MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-5 ARM926EJ-S Interrupt Controller (AITC) Table 10-3. AITC Register Summary (continued) Name R 0x1004_000C (INTDISNUM) W R W R INTENABLE[63:48] 0x1004_0010 W (INTENABLEH) R INTENABLE[47:32] W R INTENABLE[31:16] 0x1004_0014 (INTENABLEL) W R INTENABLE[15:0]] W R INTTYPE[63:48] 0x1004_0018 (INTTYPEH) W R INTTYPE[47:32] W R INTTYPE[31:16] 0x1004_001C (INTTYPEL) W R INTTYPE[16:0] W R NIPR63 0x1004_0020 W (NIPRIORITY7) R NIPR59 W R NIPR55 0x1004_0024 W (NIPRIORITY6) R NIPR51 W R NIPR47 0x1004_0028 W (NIPRIORITY5) R NIPR43 W NIPR42 NIPR41 NIPR40 NIPR46 NIPR45 NIPR44 NIPR50 NIPR49 NIPR48 NIPR54 NIPR53 NIPR52 NIPR58 NIPR57 NIPR56 NIPR62 NIPR61 NIPR60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DISNUM MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-6 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Table 10-3. AITC Register Summary (continued) Name R NIPR39 0x1004_002C W (NIPRIORITY4) R NIPR35 W R NIPR31 0x1004_0030 W (NIPRIORITY3) R NIPR27 W R NIPR23 0x1004_0034 W (NIPRIORITY2) R NIPR19 W R NIPR15 0x1004_0038 W (NIPRIORITY1) R NIPR11 W R NIPR7 0x1004_003C W (NIPRIORITY0) R NIPR3 W R 0x1004_0040 (NIVECSR) W R W R 0x1004_0044 (FIVECSR) W R W R 0x1004_0048 (INTSRCH) W R W INTIN[48:32] INTIN[63:48] FIVECTOR FIVECTOR NIPRILVL NIVECTOR NIPR2 NIPR1 NIPR0 NIPR6 NIPR5 NIPR4 NIPR10 NIPR9 NIPR8 NIPR14 NIPR13 NIPR12 NIPR18 NIPR17 NIPR16 NIPR22 NIPR21 NIPR20 NIPR26 NIPR25 NIPR24 NIPR30 NIPR29 NIPR28 NIPR34 NIPR33 NIPR32 NIPR38 NIPR37 NIPR36 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-7 ARM926EJ-S Interrupt Controller (AITC) Table 10-3. AITC Register Summary (continued) Name R 0x1004_004C (INTSRCL) W R W R 0x1004_0050 (INTFRCH) W R W R 0x1004_0054 (INTFRCL) W R W R 0x1004_0058 (NIPNDH) W R W R 0x1004_005C (NIPNDL) W R W R 0x1004_0060 (FIPNDH) W R W R 0x1004_0064 (FIPNDL) W R W FIPEND[15:0] FIPEND[31:16] FIPEND[47:32] FIPEND[63:48] NIPEND[15:0] NIPEND[31:16] NIPEND[47:32] NIPEND[63:48] FORCE[15:0] FORCE[31:16] FORCE[47:32] FORCE[63:48] INTIN[15:0] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 INTIN[31:16] 10.2.3 Interrupt Control Register (INTCNTL) INTCNTL controls the interrupts in AITC. Both normal and fast interrupts can be enabled to jump directly to the interrupt service routine. For fast interrupts, it may be faster to begin to fast interrupt routine at MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-8 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) 0x0000_001C instead of jumping to a service routine. The vector table can be sourced in high memory, 0xFFFF_FF00 to 0xFFFF_FFFF, or in low memory. If the vector table is located in low memory (MD=1), a register has been provided to control where the vector table is located. This register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. This register can be only modified using 32-bit writes. 0x1004_0000 (INTCNTL) 31 30 29 28 27 26 25 24 23 22 21 20 Access: Supervisor read/write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NIDIS FIDIS NIAD FIAD 0 0 0 0 0 0 0 0 MD 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 POINTER 0 0 0 0 0 0 0 0 0 0 Figure 10-3. Interrupt Control Register Format Table 10-4. Interrupt Control Register Field Description Field 31–23 22 NIDIS Description Reserved. These bits are reserved and should read 0. Normal Interrupt Disable. This bit, when set, disables the generation of the normal interrupt signal. This bit is similar to the I bit of the ARM926EJ-S core. This bit along with the FIDIS bit is used to enable secure operations. 0 Does not affect the normal interrupt generation 1 Disable all normal interrupts Fast Interrupt Disable. This bit, when set, disables the generation of the fast interrupt signal. This bit is similar to the F bit of the ARM926EJ-S core. This bit along with the NIDIS bit is used to enable secure operations. 0 Does not affect the fast interrupt generation 1 Disable all fast interrupts Normal Interrupt Arbiter Rise ARM Level. This bit, when asserted, increases bus arbitration priority of ARM core when normal interrupt signal (nIRQ) is asserted. If an alternate master has ownership of the bus when a normal interrupt occurs, bus will be given back to the processor core after the DMA device has completed its accesses. NIAD bit does not affect alternate master accesses that are in progress. To prevent an alternate master from accessing the bus during an interrupt service routine, the interrupt flag must not be cleared until the end of the service routine. Another option is to use the ABFEN and ABFLAG bits. 0 Disregard the normal interrupt flag when evaluating bus requests 1 Normal interrupt flag increases bus arbitration priority of the ARM core to decrease the latency of Interrupt service routine Fast Interrupt Arbiter Rise ARM Level. This bit functions same as NIAD bit except for the fast interrupts (nFIQ). 0 Disregard the fast interrupt flag when evaluating bus requests 1 Fast interrupt flag increases bus arbitration priority of the ARM core to decrease the latency of interrupt service routine. Reserved. These bits are reserved and should read 0. Interrupt Vector Table Mode. Indicates whether the interrupt vector is located in high memory or low memory. 0 Interrupt vector table located in high memory from 0xFFFF_FF00 to 0xFFFF_FFFF 1 Interrupt vector table located in low memory from POINTER to POINTER+0xFF 21 FIDIS 20 NIAD 19 FIAD 18–17 16 MD MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-9 ARM926EJ-S Interrupt Controller (AITC) Table 10-4. Interrupt Control Register Field Description (continued) Field 15–12 Description Reserved. These bits are reserved and should read 0. 11–2 Interrupt Vector Table Pointer. Indicates start of vector table when in low memory (MD=1). Only word-aligned tables POINTER are allowed, and 2 zeros are added in the LSBs when this value is used by AITC. The value stored here is left shifted by 2 bits, so the actual table vector can be directly written into the appropriate bits. The value stored in 10 bits, times 4, must be set greater than or equal to 0x0000_0024 and less than or equal to 0x0000_0F00. 1–0 Reserved. These bits are reserved and should read 0. 10.2.4 Normal Interrupt Mask Register (NIMASK) NIMASK controls the normal interrupt mask level. All normal interrupts with a priority level lower than or equal to NIMASK are disabled. The priority level of normal interrupts are determined by the normal interrupt priority level registers (NIPRIORITY7–0). Reset state of this register does not disable any normal interrupts. Writing all 1’s, or –1, to NIMASK sets normal interrupt mask to –1 which does not disable any normal interrupt priority levels. This hardware mechanism can be used to create reentrant normal interrupt routines by disabling lower priority normal interrupts. Refer Section 10.3.6 for more details on use of NIMASK register. This register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. This register can be only modified using 32-bit writes. Address 0x1004_0004 (NIMASK) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 NIMASK 1 1 1 Figure 10-4. Normal Interrupt Mask Register Format Table 10-5. Normal Interrupt Mask Register Field Description Field 31–5 4–0 NIMASK Description Reserved. These bits are reserved and should read 0. Normal Interrupt Mask. Controls normal interrupt mask level. All normal interrupts of priority level lower than or equal to the NIMASK will be disabled. 0 Disable priority level 0 normal interrupts 1 Disable priority level 1 and lower normal interrupts ... 0xE (14)Disable priority level 14 and lower normal interrupts 0xF (15)Disable all normal interrupts 0x10–0x1FDo not disable any normal interrupts MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-10 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) 10.2.5 Interrupt Enable Number Register (INTENNUM) The Interrupt Enable Number Register provides hardware accelerated enabling of interrupts. Any write to this register enables an interrupt source. If 6 LSBs are 000000, then interrupt source 0 is enabled. If 6 LSBs are 000001, then interrupt source 1 is enabled. And so forth. This register is decoded into a one hot mask that is logically OR-ed with INTENABLEH/INTENABLEL register. This hardware mechanism alleviates the need for an atomic read/modify/write sequence to enable an interrupt source. To enable interrupts 10 and 20, software only preforms two writes to AITC: first write 10 to INTENNUM register, then write 20 to INTENNUM register (order of writes is irrelevant). This register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. This register can be only modified using 32-bit writes. This register always reads back all 0s. Address 0x1004_0008 (INTENNUM) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENNUM Figure 10-5. Interrupt Enable Number Register Format Table 10-6. Interrupt Enable Number Register Description Field 31–6 5–0 ENNUM Description Reserved. These bits are reserved and should read 0. Interrupt Enable Number. Writing to this register will enable the interrupt source associated with this value. 0 Enable interrupt source 0 1 Enable interrupt source 1 ... 63 Enable interrupt source 63 10.2.6 Interrupt Disable Number Register (INTDISNUM) The Interrupt Disable Number Register provides hardware accelerated disabling of interrupts. Any write to this register disables one interrupt source. If the 6 LSBs are equal 000000, then interrupt source 0 is disabled. If the 6 LSBs equal 000001, then interrupt source 1 is disabled, and so on. This register is decoded into a one hot mask which is inverted and logically AND-ed with the INTENABLEH/INTENABLEL register. The hardware mechanism alleviates the need for an atomic read/modify/write sequence to disable an interrupt source. To disable interrupts 10 and 20, the software need only preform two writes to the AITC: first write 10 to INTDISNUM register, then write 20 to INTDISNUM register (the order of the writes is irrelevant). This register is located on the ARM926EJ-S MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-11 ARM926EJ-S Interrupt Controller (AITC) native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. This register can be only modified using 32-bit writes. This register always reads back all 0s. Address 0x1004_000C (INTDISNUM) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DISNUM Figure 10-6. Interrupt Enable Number Register Format Table 10-7. Interrupt Disable Number Register Field Description Field 31–6 5–0 DISNUM Description Reserved. These bits are reserved and should read 0. Interrupt Disable Number. Writing to this register will disable the interrupt source associated with this value. 0 Disable interrupt source 0 1 Disable interrupt source 1 ... 63 Disable interrupt source 63 10.2.7 Interrupt Enable Register High (INTENABLEH) and Low (INTENABLEL) The INTENABLEH and INTENABLEL registers are used to enable pending interrupt requests to the ARM9 core. Each bit in these registers corresponds to an interrupt source available in the system. The reset state of these registers are to have all interrupts masked. These registers can be updated by various methods: writing directly to INTENABLEH/INTENABLEL registers, setting bits in the INTENNUM register, or clearing bits in the INTDISNUM register. These registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. These registers can be only modified using 32-bit writes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-12 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_0010 (INTENABLEH) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W rwm Reset 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 0 INTENABLE[63:48] rwm rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W rwm Reset 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 0 INTENABLE[47:32] rwm rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 Figure 10-7. Interrupt Enable Register High Format Address 0x1004_0014 (INTENABLEL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W rwm Reset 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 0 INTENABLE[31:16] rwm rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W rwm Reset 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 0 INTENABLE[15:0] rwm rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 rwm 0 Figure 10-8. Interrupt Enable Register Low Format Table 10-8. Interrupt Enable Register Low and High Field Descriptions Field Description 31–0 Interrupt Enable. This bit enables the corresponding interrupt source to request a normal interrupt or a fast INTENABLE interrupt. A reset operation clears this bit. If an enable bit is set and the corresponding interrupt source is asserted, the interrupt controller will assert a normal or a fast interrupt request depending on associated INTTYPEH/INTTYPEL setting. 0 Interrupt disabled 1 Interrupt enabled and will generate a normal or fast interrupt upon assertion 10.2.8 Interrupt Type Register High (INTTYPEH) and Low (INTTYPEL) The INTTYPEH and INTTYPEL registers are used to select whether a pending interrupt source, when enabled with the INTENABLEH/INTENABLEL, will create a normal interrupt or a fast interrupt to the ARM9 core. Each bit in these registers corresponds to an interrupt source available in the system. The reset state of these registers will cause all enabled interrupt sources to generate a normal interrupt. These registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. These registers can be only modified using 32-bit writes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-13 ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_0018 (INTTYPEH) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 INTTYPE[63:48] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 INTTYPE[47:32] 0 0 0 0 0 0 0 0 0 Figure 10-9. Interrupt Type Register High Format Address 0x1004_001C (INTTYPEL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 INTTYPE[31:16] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 INTTYPE[15:0] 0 0 0 0 0 0 0 0 0 Figure 10-10. Interrupt Type Register Low Format Table 10-9. Interrupt Type Register High and Low Register Description Field 31–0 INTTYPE Description Interrupt Type. This bit indicates whether the corresponding interrupt source will request a normal interrupt or a fast interrupt. If INTTYPE bit is set and the corresponding interrupt source is asserted, the interrupt controller will assert a fast interrupt request. 0 Interrupt source will generate a normal interrupt (nIRQ). 1 Interrupt source will generate a fast interrupt (nFIQ). 10.2.9 Normal Interrupt Priority Level Registers (NIPRIORITYn) The Normal Interrupt Priority Level Registers (NIPRIORITY7–0) provide a software controllable prioritization of normal interrupts. Normal interrupts with a higher priority level will preempt normal interrupts with a lower priority. The reset state of these registers forces all normal interrupts to the lowest priority level. If a level 0 normal interrupt and a level 1 normal interrupt are asserted at the same time, the level 1 normal interrupt will be selected assuming that NIMASK has not disabled level 1 normal interrupts. If two level 1 normal interrupts are asserted at the same time, the level 1 normal interrupt with the highest source number will be selected, also assuming that NIMASK has not disabled level 1 normal interrupts. These registers can only be accessed to in privileged mode using 32-bit writes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-14 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_0020 (NIPRIORITY7) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 NIPR63 0 0 0 0 NIPR62 0 0 0 0 NIPR61 0 0 0 0 NIPR60 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR59 0 0 0 0 NIPR58 0 0 0 0 NIPR57 0 0 0 0 NIPR56 0 0 0 Figure 10-11. Normal Interrupt Priority Level 7 Register Format Table 10-10. Normal Interrupt Priority Level Register 7 Field Description Bits Field 31–28 NIPR63 27–24 NIPR62 23–20 NIPR61 19–16 NIPR60 15–12 NIPR59 11–8 NIPR58 7–4 NIPR57 3–0 NIPR56 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-15 ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_0024 (NIPRIORITY6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 NIPR55 0 0 0 0 NIPR54 0 0 0 0 NIPR53 0 0 0 0 NIPR52 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR51 0 0 0 0 NIPR50 0 0 0 0 NIPR49 0 0 0 0 NIPR48 0 0 0 Figure 10-12. Normal Interrupt Priority Level 6 Register Format Table 10-11. Normal Interrupt Priority Level Register 6 Field Description Field 31–28 NIPR55 27–24 NIPR54 23–20 NIPR53 19–16 NIPR52 15–12 NIPR51 11–8 NIPR50 7–4 NIPR49 3–0 NIPR48 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-16 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_0028 (NIPRIORITY5) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 NIPR47 0 0 0 0 NIPR46 0 0 0 0 NIPR45 0 0 0 0 NIPR44 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR43 0 0 0 0 NIPR42 0 0 0 0 NIPR41 0 0 0 0 NIPR40 0 0 0 Figure 10-13. Normal Interrupt Priority Level 5 Register Format Table 10-12. Normal Interrupt Priority Level Register 5 Field Description Field 31–28 27–24 23–20 19–16 15–12 11–8 7–4 3–0 NIPR47 NIPR46 NIPR45 NIPR44 NIPR43 NIPR42 NIPR41 NIPR40 Access: Supervisor read/write 27 26 25 24 23 22 21 20 19 18 17 16 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt Address 0x1004_002C (NIPRIORITY4) 31 30 29 28 R W Reset 0 NIPR39 0 0 0 0 NIPR38 0 0 0 0 NIPR37 0 0 0 0 NIPR36 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR35 0 0 0 0 NIPR34 0 0 0 0 NIPR33 0 0 0 0 NIPR32 0 0 0 Figure 10-14. Normal Interrupt Priority Level 4 Register Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-17 ARM926EJ-S Interrupt Controller (AITC) Table 10-13. Normal Interrupt Priority Level Register 4 Field Description Field 31–28 NIPR39 27–24 NIPR38 23–20 NIPR37 19–16 NIPR36 15–12 NIPR35 11–8 NIPR34 7–4 NIPR33 3–0 NIPR32 Address 0x1004_0030 (NIPRIORITY3) 31 30 29 28 27 26 25 24 23 22 21 20 19 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt Access: Supervisor read/write 18 17 16 R W Reset 0 NIPR31 0 0 0 0 NIPR30 0 0 0 0 NIPR29 0 0 0 0 NIPR28 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR27 0 0 0 0 NIPR26 0 0 0 0 NIPR25 0 0 0 0 NIPR24 0 0 0 Figure 10-15. Normal Interrupt Priority Level 3 Register Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-18 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Table 10-14. Normal Interrupt Priority Level Register 3 Field Description Field 31–28 NIPR31 27–24 NIPR30 23–20 NIPR29 19–16 NIPR28 15–12 NIPR27 11–8 NIPR26 7–4 NIPR25 3–0 NIPR24 Address 0x1004_0034 (NIPRIORITY2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt Access: Supervisor read/write 18 17 16 R W Reset 0 NIPR23 0 0 0 0 NIPR22 0 0 0 0 NIPR21 0 0 0 0 NIPR20 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR19 0 0 0 0 NIPR18 0 0 0 0 NIPR17 0 0 0 0 NIPR16 0 0 0 Figure 10-16. Normal Interrupt Priority Level 2 Register Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-19 ARM926EJ-S Interrupt Controller (AITC) Table 10-15. Normal Interrupt Priority Level Register 2 Field Description Bits 31–28 27–24 23–20 19–16 15–12 11–8 7–4 3–0 Field NIPR23 NIPR22 NIPR21 NIPR20 NIPR19 NIPR18 NIPR17 NIPR16 Access: Supervisor read/write 27 26 25 24 23 22 21 20 19 18 17 16 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt Address 0x1004_0038 (NIPRIORITY1) 31 30 29 28 R W Reset 0 NIPR15 0 0 0 0 NIPR14 0 0 0 0 NIPR13 0 0 0 0 NIPR12 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR11 0 0 0 0 NIPR10 0 0 0 0 NIPR9 0 0 0 0 NIPR8 0 0 0 Figure 10-17. Normal Interrupt Priority Level 1 Register Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-20 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Table 10-16. Normal Interrupt Priority Level Register 1 Field Description Field 31–28 NIPR15 27–24 NIPR14 23–20 NIPR13 19–16 NIPR12 15–12 NIPR11 11–8 NIPR10 7–4 NIPR9 3–0 NIPR8 Address 0x1004_003C (NIPRIORITY0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt Access: Supervisor read/write 18 17 16 R W Reset 0 NIPR7 0 0 0 0 NIPR6 0 0 0 0 NIPR5 0 0 0 0 NIPR4 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 NIPR3 0 0 0 0 NIPR2 0 0 0 0 NIPR1 0 0 0 0 NIPR0 0 0 0 Figure 10-18. Normal Interrupt Priority Level 1 Register Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-21 ARM926EJ-S Interrupt Controller (AITC) Table 10-17. Normal Interrupt Priority Level Register 0 Field Description Bits 31–28 27–24 23–20 19–16 15–12 11–8 7–4 3–0 Field NIPR7 NIPR6 NIPR5 NIPR4 NIPR3 NIPR2 NIPR1 NIPR0 Description Normal Interrupt Priority Level. Selects the software controlled priority level for the associated normal interrupt source. These registers do not affect the prioritization of fast interrupt priorities. 0 Lowest priority normal interrupt ... 15 Highest priority normal interrupt 10.2.10 Normal Interrupt Vector and Status Register (NIVECSR) The NIVECSR register displays the priority of the highest pending normal interrupt and also provides vector index of the interrupt’s service routine. This number can be used directly as an index into a vector table to select the highest pending normal interrupt source. This read-only register can only be accessed to in privileged mode. Address 0x1004_0040 (NIVECSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset 0 0 0 0 0 0 0 NIVECTOR 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 NIPRILVL 0 0 0 0 0 0 0 0 0 Figure 10-19. Normal Interrupt Vector and Status Register Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-22 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Table 10-18. Normal Interrupt Vector and Status Register Field Description Field Description 31–16 Normal Interrupt Vector. Indicates vector index for the highest pending normal interrupt. NIVECTOR –1 No normal interrupt request pending 0 Interrupt 0 highest priority pending normal interrupt 1 Interrupt 1 highest priority pending normal interrupt ... 63 Interrupt 63 highest priority pending normal interrupt 64+ (not –1)unused, will not occur 15–0 NIPRILVL Normal Interrupt Priority Level. Indicates priority level of highest priority normal interrupt. This number can be written to NIMASK to disable current priority normal interrupts to build a reentrant normal interrupt system. –1 No normal interrupt request pending 0 Highest priority normal interrupt is level 0 1 Highest priority normal interrupt is level 1 ... 15 Highest priority normal interrupt is level 15 16+ (not –1)unused, will not occur 10.2.11 Fast Interrupt Vector and Status Register (FIVECSR) FIVECSR provides the vector index for highest priority active fast interrupt’s service routine (higher the source number of fast interrupt, higher will be the priority level). This hardware mechanism replaces the previous necessity for core support of the FF1 command. This number can be directly used as an index into a vector table to select the highest pending fast interrupt source. This read-only register is located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. Address 0x1004_0044 (FIVECSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset 1 1 1 1 1 1 1 FIVECTOR[31:16] 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 1 1 1 1 1 1 1 FIVECTOR[15:0] 1 1 1 1 1 1 1 1 1 Figure 10-20. Fast Interrupt Vector and Status Register Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-23 ARM926EJ-S Interrupt Controller (AITC) Table 10-19. Fast Interrupt Vector and Status Register Description Field 31–0 FIVECTOR Description Fast Interrupt Vector. Indicates vector index for the highest pending fast interrupt. –1 No fast interrupt request pending (–1 is defined as all bits in the field are set to 1.) 0 Interrupt 0 highest pending fast interrupt 1 Interrupt 1 highest pending fast interrupt ... 63 Interrupt 63 highest pending fast interrupt 64+ (not –1)unused, will not occur 10.2.12 Interrupt Source Register High (INTSRCH) and Low (INTSRCL) INTSRCH and INTSRCL are both 32-bits wide. INTSRCH and INTSRCL reflect the status of all interrupt request inputs into the interrupt controller. Unused bit positions always read zero (no request pending). The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests would be inactive. These read-only registers can only be accessed in privileged mode and can only accessed with 32-bit reads. Address 0x1004_0048 (INTSRCH) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset1 0 0 0 0 0 0 0 INTIN[63:48] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset1 1 INTIN[47:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-21. Interrupt Source Register High Format The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests would be inactive. Address 0x1004_004C (INTSRCL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset1 0 0 0 0 0 0 0 INTIN[31:16] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset1 0 0 0 0 0 0 0 INTIN[15:0] 0 0 0 0 0 0 0 0 0 Figure 10-22. Interrupt Source Register High Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-24 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) 1 The state of this register out of reset is determined by the peripheral circuits generating the requests; normally, the requests would be inactive. Table 10-20. Interrupt Source Register High and Low Description Field 31–0 INTIN Description Interrupt Source. Indicates the state of the corresponding hardware interrupt source. 0 Interrupt source negated 1 Interrupt source asserted 10.2.12.1 Interrupt Assignments High Table 10-21. Interrupt Source High (INTSRCH) Assignment Name INT_DPTC INT_IIM INT_LCDC INT_SLCDC INT_SAHARA INT_SCM INT_SMN INT_USBOTG INT_USBHS2 INT_USBHS1 INT_H264 INT_EMMAPP INT_EMMAPRP INT_FEC INT_UART5 INT_UART6 INT_DMACH15 INT_DMACH14 INT_DMACH13 INT_DMACH12 INT_DMACH11 INT_DMACH10 INT_DMACH9 INT_DMACH8 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit Interrupt Source Module Dynamic Process Temperature Compensate (DPTC) IC Identify Module (IIM) LCD Controller (LCDC) Smart LCD Controller (SLCDC) Symmetric/Asymmetric Hashing and Random Accelerator SCC SCM SCC SMN USB OTG USB HOST2 USB HOST1 H264 eMMA Post Processor eMMA Pre Processor Fast Ethernet Controller UART5 UART6 DMA Channel 15 DMA Channel 14 DMA Channel 13 DMA Channel 12 DMA Channel 11 DMA Channel 10 DMA Channel 9 DMA Channel 8 Notes MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-25 ARM926EJ-S Interrupt Controller (AITC) Table 10-21. Interrupt Source High (INTSRCH) Assignment (continued) Name INT_DMACH7 INT_DMACH6 INT_DMACH5 INT_DMACH4 INT_DMACH3 INT_DMACH2 INT_DMACH1 INT_DMACH0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Interrupt Source Module DMA Channel 7 DMA Channel 6 DMA Channel 5 DMA Channel 4 DMA Channel 3 DMA Channel 2 DMA Channel 1 DMA Channel 0 Notes 10.2.12.2 Interrupt Assignments Low Table 10-22. Interrupt Source Low (INTSRCL) Assignment Name INT_CSI INT_ATA INT_NFC INT_PCMCIA INT_WDOG INT_GPT1 INT_GPT2 INT_GPT3 INT_PWM INT_RTC INT_KPP INT_UART1 INT_UART2 INT_UART3 INT_UART4 INT_CSPI1 INT_CSPI2 INT_SSI1 INT_SSI2 INT_I2C1 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit Interrupt Source Module CMOS Sensor Interface (CSI) Advanced Technology Attachment (ATA) NAND Flash Controller (NFC) PCMCIA/CF Host Controller (PCMCIA) Watchdog (WDOG) General Purpose Timer (GPT1) General Purpose Timer (GPT2) General Purpose Timer (GPT3) Pulse Width Modulator (PWM) Real-Time Clock (RTC) Key Pad Port (KPP) UART1 UART2 UART3 UART4 Configurable SPI (CSPI1) Configurable SPI (CSPI2) Synchronous Serial Interface (SSI1) Synchronous Serial Interface (SSI2) I2C Bus Controller (I2C1) Hard Disk Notes MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-26 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Table 10-22. Interrupt Source Low (INTSRCL) Assignment (continued) Name INT_SDHC1 INT_SDHC2 INT_SDHC3 INT_GPIO INT_MSHC INT_CSPI3 INT_RTIC INT_GPT4 INT_GPT5 INT_GPT6 INT_I2C2 Reserved Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Interrupt Source Module Secure Digital Host Controller (SDHC1) Secure Digital Host Controller (SDHC2) Secure Digital Host Controller (SDHC3) General Purpose Input/Output (GPIO) Memory Stick Host Controller (MSHC) Configurable SPI (CSPI3) Real Time Integrity Checker (RTIC) General Purpose Timer (GPT4) General Purpose Timer (GPT5) General Purpose Timer (GPT6) I2C Bus Controller (I2C2) Reserved Notes 10.2.13 Interrupt Force Register High (INTFRCH) and Low (INTFRCL) INTFRCH and INTFRCL are both 32-bits wide. They allow software generation of interrupts for each of the possible interrupt sources for functional or debug purposes. System level design may reserve one or more sources for software purposes to allow software to self-schedule interrupts by forcing one or more of these “sources” in appropriate interrupt force register(s). These registers can only be accessed to in privileged mode. These registers can be only modified using 32-bit writes. Address 0x1004_0050 (INTFRCH) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 FORCE[63:48] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 FORCE[47:32] 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-27 ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_0054 (INTFRCL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 FORCE[31:16] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 FORCE[15:0] 0 0 0 0 0 0 0 0 0 Figure 10-23. Interrupt Force Register Format Table 10-23. Interrupt Force Register High and Low Field Description Field 31–0 FORCE Description Interrupt Source Force Request. Used to force a request for the corresponding interrupt source. 0 Standard interrupt operation 1 Interrupt forced asserted 10.2.14 Normal Interrupt Pending Register High (NIPNDH) and Low (NIPNDL) NIPNDH and NIPNDL are both 32-bits wide registers used to monitor the outputs of the enable and masking operations. These registers are actually a set of buffers; therefore, reset state of these registers are determined by normal interrupt enable registers, interrupt mask register and interrupt source registers. The value reflected in these registers is unaffected by the value of NIMASK register. These read-only registers are located on ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed in privileged mode Address 0x1004_0058 (NIPNDH) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset 0 0 0 0 0 0 0 NIPEND[63:48] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 NIPEND[47:32] 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-28 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_005C (NIPNDL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset 0 0 0 0 0 0 0 NIPEND[31:16] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 NIPEND[15:0] 0 0 0 0 0 0 0 0 0 Table 10-24. Normal Interrupt Pending Register High and Low Description Field 31–0 NIPEND Description Normal Interrupt Pending Bit. If a normal interrupt enable bit is set and the corresponding interrupt source is asserted, the interrupt controller will assert a normal interrupt request. The normal interrupt pending bits reflect the interrupt input lines which are asserted and are currently enabled to generate a normal interrupt. 0 No normal interrupt request 1 Normal interrupt request pending 10.2.15 Fast Interrupt Pending Register High (FIPNDH) and Low (FIPNDL) FIPNDH and FIPNDL are both 32-bits wide registers used to monitor the outputs of enable and masking operations. These registers are actually a set of buffers; therefore, reset state of these registers are determined by fast interrupt enable registers, interrupt mask register and interrupt source registers. These read-only registers are located on the ARM926EJ-S native bus, accessible in 1 cycle, and can only be accessed to in privileged mode. Address 0x1004_0060 (FIPNDH) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset 0 0 0 0 0 0 0 FIPEND[63:48] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 FIPEND[47:32] 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-29 ARM926EJ-S Interrupt Controller (AITC) Address 0x1004_0064 (FIPNDL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: Supervisor read 18 17 16 R W Reset 0 0 0 0 0 0 0 FIPEND[31:16] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 FIPEND[15:0] 0 0 0 0 0 0 0 0 0 Figure 10-24. Fast Interrupt Pending Register High and Low Format Table 10-25. Fast Interrupt Pending Register High and Low Field Description Field 31–0 FIPEND Description Fast Interrupt Pending Bit. If fast interrupt enable bit is set and the corresponding interrupt source is asserted, interrupt controller will assert fast interrupt request. Fast interrupt pending bits reflect interrupt input lines which are asserted and are currently enabled to generate a fast interrupt. 0 No fast interrupt request 1 Fast interrupt request pending 10.3 10.3.1 ARM926EJ-S Interrupt Controller Operation ARM926EJ-S Prioritization of Exception Sources The ARM926EJ-S core imposes the following priority among the various exceptions: • Reset (highest priority) • Data Abort • Fast Interrupt • Normal Interrupt • Prefetch Abort • Undefined Instruction and SWI (lowest priority) 10.3.2 AITC Prioritization of Interrupt Sources AITC module prioritizes various interrupt sources by source number where higher source numbers have higher priority. Fast interrupt always have higher priority over normal interrupts. Interrupt requests are prioritized in the following sequence: 1. Fast interrupt requests, in order of highest source number 2. Normal interrupt requests, in order of highest priority level, then in order of highest source number with the same priority level MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-30 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) 10.3.3 Assigning and Enabling Interrupt Sources Interrupt controller provides for flexible assignment of any interrupt source to one of the two core interrupt request inputs. This is done by setting the appropriate bits in INTENABLEH/INTENABLEL registers and INTTYPEH/INTTYPEL registers. Usually, interrupt assignment is done once during system initialization and does not affect interrupt latency. Interrupt assignment is the first of three steps required to enable an interrupt source, and this is done at chip integration. The second step is to program the source to generate interrupt requests. The final step is to enable the interrupt inputs in the core by clearing the normal interrupt disable (I) and/or the fast interrupt disable (F) bits in the program status register (CPSR). 10.3.4 Enabling Interrupt Sources There are two methods of enabling or disabling interrupts in the AITC. The first method is directly reading INTENABLEH/INTENABLEL registers, logically OR or BIT CLEAR these registers with a generated masks, then writing back to INTENABLEH/INTENABLEL registers. The second method is performing an atomic write to source number in INTENNUM register. AITC will decode this 6-bit register and enable one of the 64 interrupt sources. AITC will automatically generate a “one hot” enable mask and logically OR this mask to the correct INTENABLEH or INTENABLEL register. To disable interrupts is the same except the source number is written to the INTDISNUM register. 10.3.5 Typical Interrupt Entry Sequences Table 10-26 shows a typical pipeline sequence for ARM926EJ-S core when a normal interrupt occurs, assuming single cycle memories, it approximately takes 6 clocks from normal interrupt acknowledgment within ARM926EJ-S to fetch first opcode of interrupt routine. Table 10-27 shows a typical pipeline sequence for ARM926EJ-S core when a fast interrupt occurs, assuming that FIQ service routine begins at 0x0000_001C and single cycle memories. Table 10-26. Typical Hardware Accelerated Normal Interrupt Entry Sequence TIME ADDR –2 nIRQ assert Last ADDR before nIRQ +4 / +2 +8 / +4 0x0000_0018 +4 +8 Vector Table n/a nIRQ Routine Fetch Dec Exec Fetch Dec Fetch –1 0 nIRQ ack. Exec Dec Fetch Fetch Dec Fetch Exec Dec Fetch Vector Data Wrbk Link Adjust 1 2 3 4 5 6 7 8 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-31 ARM926EJ-S Interrupt Controller (AITC) Table 10-26. Typical Hardware Accelerated Normal Interrupt Entry Sequence (continued) TIME ADDR –2 +4 +8 –1 0 1 2 3 4 5 6 7 Fetch 8 Dec Fetch Table 10-27. Typical Fast Interrupt Entry Sequence TIME ADDR –2 nFIQ assert Last ADDR before nFIQ +4 / +2 +8 / +4 0x0000_001c +4 +8 Fetch Dec Fetch –1 0 nFIQ ack. Exec Dec Fetch Fetch Dec Fetch Exec Dec Fetch Link Adjust 1 2 3 10.3.6 Writing Reentrant Normal Interrupt Routines AITC can be used to create a reentrant normal interrupt system. This enables preempting of lower priority level interrupts by higher priority level interrupts. This requires a small amount of software support and overhead. 1. Push the link register (LR_irq) on to the stack (SP_irq) 2. Push the saved status register (SPSR_irq) on to the stack 3. Read the current value of NIMASK and push this value on to the stack 4. Read current priority level via NIVECSR 5. Interrupts of the equal or lesser priority than the current priority level must be masked via the NIMASK register by writing value from NIVECSR 6. Clear I bit in ARM926EJ-S core by a MSR or MRS command sequence (now a higher priority normal interrupt can preempt a lower priority one). Also change operating mode of the core to System Mode from IRQ mode 7. Push System Mode link register (LR) on to the stack (SP_user) 8. The traditional interrupt service routine is now included 9. Pop System Mode link register (LR) from the stack (SP_user) 10. Set I bit in ARM926EJ-S core by MSR or MRS command sequence (disables all normal interrupts) 11. Also change the operating mode of the core to IRQ Mode from System mode 12. Pop the original value of normal interrupt mask and write to the NIMASK register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-32 Freescale Semiconductor ARM926EJ-S Interrupt Controller (AITC) 13. The saved status register must be popped from the stack (SP_irq) 14. The link register must be popped from the stack into the PC 15. Return from nIRQ NOTE Steps 1, 2, 13, and 14 are automatically done by most C compilers and are included for completeness. 10.3.7 AHB Interface of AITC AITC is AHB compliant. This means, IDLE or BUSY cycles which are presented to AITC will receive an aitc_hready (as required by specification). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 10-33 ARM926EJ-S Interrupt Controller (AITC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 10-34 Freescale Semiconductor Book II, Part 2: Security Introduction This part provides an overview of the modules that make up the i.MX27 security systems. Chapter 11, “Security Controller (SCC),” on page 11-1 Chapter 12, “Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2),” on page 12-1 Chapter 13, “Run-Time Integrity Checker (RTIC),” on page 13-1 Chapter 14, “IC Identification (IIM),” on page 14-1 Security Controller (SCC) The Security Controller (SCC) is a hardware component composed of two sub-blocks, the Secure RAM and the Security Monitor. The primary functionality of the SCC is associated with establishing the following: • A centralized security state controller and hardware security state with a hardware configured, unalterable security policy • An uninterruptable hardware mechanism to detect and respond to threat detection signals (specifically platform test access signals) • A device-unique data protection/encryption resource to enable off chip storage of security sensitive data • An internal storage resource that automatically and irrevocably destroys plain text security sensitive data upon threat detection Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) is a security co-processor that can be used on cell phone baseband processors or wireless PDAs. It implements block encryption algorithms, (AES, DES, and 3DES), hashing algorithms (MD5, SHA-1, SHA-224, and SHA-256), stream cipher algorithm (ARC4), and a hardware random number generator. It has a slave IP bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an AHB bus interface, to reduce the burden on the host to move the required data to and from memory. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 Run Time Integrity Checker (RTIC) The Run Time Integrity Checker (RTIC) ensures the integrity of the peripheral memory contents and assist with boot authentication. The RTIC has the ability to verify the memory contents during system boot and during run time execution. If the memory contents at runtime fail to match the hash signature, an error in the security monitor is triggered. IC Identification (IIM) The IC Identification Module (IIM) provides an interface for reading and in some cases programming and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals which can be used for software control of hardware elements, not requiring non-volatility. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Chapter 11 Security Controller (SCC) The Security Controller (SCC) is composed of two sub-blocks, the Secure RAM and the Security Monitor (see Figure 11-1). The primary functionality of the SCC is associated with establishing the following: • A centralized security state controller and a hardware security state with a hardware configured, unalterable security policy • An uninterruptible hardware mechanism that detects and responds to threat detection signals (specifically, platform test access signals) • A device-unique data protection/encryption resource that enables off-chip storage of security-sensitive data An internal storage resource that automatically and irrevocably destroys plain text security-sensitive data upon threat detection. Debug Ports (indicating JTAG or Test modes) Security Key (SLID) Debug Detector Secure State Controller Timer Algorithm Sequence Checker Security Monitor Key Encryption Module Status Security Policy State Memory Controller Black Memory Red Memory Secure RAM Bus Interface Security Controller (SCC) IP Bus Figure 11-1. Security Controller Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 11-1 Security Controller (SCC) 11.1 Overview Security and security services, in an embedded or data processing platform, refer to the platform’s ability to provide mandatory and optional information protection services. Information in this context refers to all embedded data, both to program store and data load. Therefore, a secure platform is intended to protect information and data from unauthorized access in the form of inspection (read), modification (write), or execution (use). 11.2 External Signal Description NOTE Contact your Freescale Semiconductor sales office or distributor for additional information on SCC. The SCC has no external signals. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 11-2 Freescale Semiconductor Chapter 12 Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) The Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) is a security co-processor that can be used on cell phone baseband processors or wireless PDAs. It implements block encryption algorithms, (AES, DES, and 3DES), hashing algorithms (MD5, SHA-1, SHA-224, and SHA-256), stream cipher algorithm (ARC4), and a hardware random number generator. It has a slave IP bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an AHB bus interface, to reduce the burden on the host to move the required data to and from memory. 12.1 Features SAHARA2 accelerates the following security functions: • AES encryption/decryption — ECB, CBC, CTR, and CCM modes — 128 bit key • DES/3DES — EBC, CBC and CTR modes — 56-bit key with parity (DES) — 112-bit or 168-bit key with parity (3DES) • ARC4 (RC4-compatible cipher) — 5-16 byte key — Host accessible S-box • MD5, SHA-1, SHA-224 and SHA-256 hashing algorithms. — Messages lengths which are multiples of bytes. — Autopadding supported. — HMAC (support for IPAD and OPAD via descriptors). — Up to 232 byte message length. • Random number generator (based NIST Approved PRNG - FIPS 186-2). — Entropy is generated via an independent free running ring oscillators SAHARA2 also provides the following enhanced features: • Descriptor based processing to reduce communication between host processor and SAHARA2 • Low power design MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 12-1 Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) • • — Automatic power down of individual blocks when not in use — Clock gating on registers — RNG sleep mode Restricted access to potentially sensitive information — Internal registers are cleared after descriptor chain has completed processing in BATCH mode — Security Monitor can cause data to be cleared. — Scan reset and scan exit signals prevent data being scanned out. Mixed Endianness support. NOTE Contact your Freescale Semiconductor sales office or distributor for additional information on SAHARA2. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 12-2 Freescale Semiconductor Chapter 13 Run-Time Integrity Checker (RTIC) The Run-Time Integrity Checker (RTIC) function is to ensure the integrity of the peripheral memory contents, and assist with boot authentication. The RTIC has the ability to verify the memory contents during system boot and during run-time execution. If the memory contents at run-time fail to match the hash signature, an error in the security monitor is triggered. Figure 13-1 is a block diagram of the RTIC. AHB DMAC SAM hclk_gated en Clock Controller Controller hclk_gated IP-Bus IP-Bus scc_rtic_err hclk Run-time IP-Bus T-Secure ckil (32 kHz) Timer Hash Once Timer Module Hash Register File Figure 13-1. RTIC Block Diagram 13.1 Features The RTIC offers the following features: • SHA-1 message authentication • Input DMA interface • Segmented data gathering to support non-contiguous data blocks in memory (up to two segments per block) • Works with high assurance boot process • Support for up to four independent memory blocks • Programmable DMA bus duty cycle timer and watchdog timer • Power-saving clock gating logic MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 13-1 Run-Time Integrity Checker (RTIC) • • Hardware configurable Big/Little-Endian data format Full word memory reads (word-aligned addresses, multiple of 32-bit lengths) 13.1.1 Modes of Operation The RTIC operates in two primary modes: • One-time hash mode — Is used during high assurance boot for code authentication or one time integrity checking — Stores hash result internally and signals interrupt to host • Continuous hash mode — Is used at run-time to continuously to verify integrity of memory contents — Checks re-generated hash against internally stored values and interrupts host only if error occurs 13.2 13.2.1 Initialization/Application Information System Application The RTIC is intended to serve as a single-use hash accelerator to assist with code authentication and other services at boot time, and as an autonomous/passive memory integrity checker during run-time. It is programmed through the IP-slave interface, and scans the peripheral memory contents over the AHB interface using direct memory access. A typical system configuration using the RTIC is shown in Figure 13-2. Memory A Memory B Memory C Memory D AHB ARM Host Processor ipi_err_int Run-Time Integrity Checker SCC IP Interface Figure 13-2. System Diagram In this example, there are four independent memory blocks that can be checked by the RTIC. Memories A,B, and C have their contents partitioned over non-contiguous spaces. Memory D does not contain any MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 13-2 Freescale Semiconductor Run-Time Integrity Checker (RTIC) physical partitioning. The host would program the RTIC with the starting address and length of each partition inside memory A, B, and C. For memory D, only one starting address and length would be specified, with the second start address/length fields for memory D being set to 0. After setting the A/B/C/D hash once memory enable bits in the RTIC control register and hash once bit in the RTIC command register, the RTIC hashes each memory and stores the result in its hash register file to be read by the host. If the RTIC is used to verify that the memories are not corrupted during run-time, the A/B/C/D run-time memory enable bits in the control register must be set, followed by the tun time check bit in the RTIC command register. The RTIC re-hashes each enabled memory in a continuous loop until either an error occurs or the RTIC is reset. NOTE Contact your Freescale Semiconductor sales office or distributor for additional information on RTIC. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 13-3 Run-Time Integrity Checker (RTIC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 13-4 Freescale Semiconductor Chapter 14 IC Identification (IIM) The IC Identification Module (IIM) provides an interface for reading and, in some cases, programming and/or overriding identification and control information stored in on-chip fuse elements. The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. 14.1 Overview The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller and a set of registers to hold the values of signals visible outside the module. Up to eight arrays of fuses (e-Fuses) are associated with the IIM. The IIM is accessible using an 8-bit IP bus interface. An 8-bit interface is used because it matches the natural width of the fuse arrays. 14.1.1 • • • • • • • • • • • Features Up to eight independent fuse banks (number of fuse banks and size of the bank are parameterized) Maximum usable fuse bank size is 2048 bits Laser- and e-Fuse banks may be intermixed on a per bank basis Support for driving secure JTAG challenge and response values to the SJC (size of each field configurable using RTL parameter; challenge default size is 64 bits, response default size is 56 bits) Up to 28 externally visible software-controlled volatile signals (driving SoC-level nets for feature enabling) lockable in groups of 7 Ability to provide up to two distinct 168-bit 3DES keys from a single set of fuses Ability to override fuse values in software (does not affect the fuse element); override capability can be permanently disabled on a per-bank basis Ability to write-protect e-Fuses on a per-bank basis Ability to scan-protect (read and program) on a per-bank basis Fuses may be programmed by software, directly by JTAG, or indirectly by JTAG using a processor Recommended signal assignments to maximize software re-use MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 14-1 IC Identification (IIM) NOTE Contact your Freescale Semiconductor sales office or distributor for additional information on IIM. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 14-2 Freescale Semiconductor Book II, Part 3: External Interfaces Introduction The i.MX27 processor contains the following external interfaces: Chapter 15, “External Memory Interface (EMI),” on page 15-1 Chapter 16, “Multi-Master Memory Interface (M3IF),” on page 16-1 Chapter 17, “Wireless External Interface Module (WEIM),” on page 17-1 Chapter 18, “Enhanced SDRAM Controller (ESDRAMC),” on page 18-1 Chapter 19, “NAND Flash Controller (NFC),” on page 19-1 Chapter 20, “Personal Computer Memory Card International Association (PCMCIA) Controller,” on page 20-1 External Memory Interface (EMI) The External Memory Interface (M3IF) controls all IC external memory accesses (read/write/erase/program) from all the masters in the system, through two Master Port Gaskets (MPG)—(interface [AHB 32-bit] and MPG64 [AHB 64-bit])—to different external memories. All accesses are arbitrated by the Multi Master Memory Interface (M3IF) module and controlled by the respective memory controller. The EMI contains different external memory controllers to support several memory devices: • M3IF—Multi Master Memory Interface • ESDCTL/MDDRC—Enhanced SDRAM/LPDDR memory controller • PCMCIA—PCMCIA memory controller • NFC—NAND Flash memory controller • WEIM—SRAM/PSRAM/FLASH memory controller Multi-Master Memory Interface (M3IF) The Multi-Master Memory Interface (M3IF) controls memory accesses (read/write/erase/program) from one or more masters through different port interfaces to different external memory controllers ESDCTL/MDDRC, PCMCIA, NANDFLASH, and WEIM. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 Wireless External Interface Module (WEIM) The Wireless External Interface Module (WEIM) provides the capability to the system for accessing external Flash and RAM memories connected to either of its six chip selects. It has the ability to provide a single-cycle burst access for external flashes and support for multiple burst devices when not using its smart burst feature. Other features include Big/Endian mode support, Cellular RAM support, and support for multiplexed address/data bus. Enhanced SDRAM Controller (ESDCTL) The Enhanced Synchronous Dynamic RAM Controller (ESDCTL) provides interface and control for synchronous DRAM memories for the system. SDRAM memories use a synchronous interface with all signals registered on a clock edge. A command protocol is used for initialization, read, write, and refresh operations to the SDRAM and is generated on the signals by the controller when required due to external or internal requests. It has support for both single data rate RAMs and double data rate SDRAMs. It supports 64, 128, 256, and 512-Mbit, 4 bank synchronous DRAM by two independent chip selects and with up to 64 Mbytes addressable memory per chip select. NAND Flash Controller (NFC) The NAND Flash Controller (NFC) device is a type of flash memory that is optimized for data storage applications with its unique cell structure, providing significant cost advantages over conventional NOR flash memory. The NAND Flash Controller integrates the functionality necessary for access to these devices. NAND Flash has a smaller bit cell but has a fast sequential access as compared to a NOR flash which has a large bit cell but a fast random access. This makes NAND Flash perfect as a data memory for storing audio/video files in NAND Flash because typically these files are stored in sequential manner while access to processor code is quite random. Personal Computer Memory Card International Association (PCMCIA) Controller The PCMCIA host adapter module provides the control logic for PCMCIA socket interfaces, and requires some additional external analog power switching logic and buffering. The additional external buffers allow the PCMCIA host adapter module to support one PCMCIA socket. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Chapter 15 External Memory Interface (EMI) The Master Memory Interface (M3IF) is an External Memory Interface that controls all IC external memory accesses (read/write/erase/program) from all the masters in the system, through two port interfaces (MPG (AHB 32 bit) and MPG64 (AHB 64-bit) to different external memories. All accesses are arbitrated by the M3IF module and controlled by the respective memory controller. EMI contains different external memory controllers in order to support several memory devices: • M3IF—Multi Master Memory Interface • ESDRAMC/MDDRC—Enhanced SDRAM/LPDDR memory controller • PCMCIA—PCMCIA memory controller • NFC—NAND Flash memory controller • WEIM—SRAM/PSRAM/Flash memory controller 15.1 Overview The M3IF-ESDCTL/MDDRC interface is optimized and designed to reduce access latency by generating multiple accesses through dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls access to/from the Enhanced SDRAM/MDDR memory controller. For other memory interfaces, M3IF only arbitrates and forwards the masters requests received through the Master Port Gasket (MPG/MPG64) interface (and M3IF arbitration) to the respective memory controller. When a master request a memory access, the access will immediately be taken by the M3IF if no other access is in progress. The M3IF will forward the access to the respective memory controller (slave), and depending on the respective memory controller state a command to the memory will be generated. If the access can’t be started due to a previous active access, the master request pends (“HREADY” held negated) until it will be executed by the memory controller. When the access execution is completed the HREADY will be asserted and a new request can be processed. EMI provides the ability to connect to a wide variety of memory devices. This chapter contains technical information about the operation and configuration of the EMI modules in the chip to allow the designer to quickly integrate external memory devices into new and existing designs. Several of the modules in the EMI portion of the chip share pins with the PCMCIA, EIM, SDRAMC, and NAND controllers. The chip contains interfaces for the following types of memory devices: • PCMCIA • Flash Memory Devices • SDRAM/Low Power DDR (LPDDR) Figure 15-1 shows the M3IF block diagram. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-1 External Memory Interface (EMI) External Module Interface (EMI) Multi Master Memory Interface (M3IF) EMI AHB MUX 64 #0 MPG64 LCDC TMAX EMI I/O MUX SLCDC ESDCTL/MDDRC CONTROLLER FEC 64 eMMA-IT 64 M3IF ARBITRATION (AMB + M3A) PCMCIA CONTROLLER Application (ARM) Platform A/P MAX M2 S2 M3 M4 M5 #4 MPG64 32 #3 MPG #2 MPG64 RTIC/ SAHARA2 DMA NAND FLASH CONTROLLER H264-AHB H264-PO 64 H264-PO 64 32 USBOTG Figure 15-1. M3IF System Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-2 Freescale Semiconductor #7 MPG WEIM CONTROLLER #6 MPG64 SRAM/PSRAM FLASH H264-PO 64 #5 MPG64 NAND FLASH PCMCIA SDRAM/MDDR #1 MPG64 External Memory Interface (EMI) 15.2 Features M3IF includes these distinctive features: • Multi Master Memory Interface (M3IF) — Supports multiple requests from 8 masters through two different input ports interfaces: Master Port Gasket (MPG)—ARM9 AMBA AHB-Lite bus protocol. Master Port Gasket (MPG64)—AMBA AHB access with 64 bits data bus width. — Supports memory “snooping,” which monitors a region (from 2 Kbytes up to 16 Mbytes) in external memory for write accesses. • Enables AHB accesses to four different memory controllers (that share some of their I/O pads, through the EMI AHB MUX and EMI I/O MUX) • Enhanced SDRAM Controller (ESDCTL) or MDDR Controller (MDDRC) — Up to two chip selects (due to PADS sharing all 2 chip selects are supported only in case that WEIM CS2 and CS3 are not is use). — Supports 32 bit SDR SDRAM (up to 2 Gbytes @133 MHz) — Supports 32 bit MDDR SDRAM (up to 2 Gbytes @ 266 MHz) • NAND Flash Controller (NFC) — 8/16 bit NAND Flash (up to 2 Gbyte address space) — 2-Kbyte RAM Internal Buffer • Personal Computer Memory Card International Association Controller (PCMCIA) — Support PCMCIA Rel 2.1 — Compact Flash — PC Card — TrueID Mode • Wireless External Interface Memory Controller (WEIM) — Up to 6 chip selects (due to PADS sharing all 6 chip selects are supported only in case that both ESDCTL/MDDRC chip selects are not is use). — Supports 16-bit SRAM memories — Supports 16-bit PSRAM (up to 133 MHz) memories — Support s16-bit (NOR) Flash memories 15.3 PCMCIA Host Adapter The Personal Computer Memory Card International Association (PCMCIA) interface provides a glueless interface to devices that comply with the PCMCIA association standard PCMCIA 2.1, which defines usage of memory and I/O devices as insertable and exchangeable peripherals for personal computers or PDAs. Examples of these types of devices include Compact Flash and WLAN adapters. Figure 15-2 shows a simplified block diagram of the PCMCIA controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-3 External Memory Interface (EMI) PC Card A[25:0] D[15:0] CARD Interface PCMCIA Controller OE WE IORD IOWR REG WAIT CE1 AHB bus CE2 R/W AHB Interface POE RESET access error RDY/BSY IOIS16/WP BVD1 BVD2 CD1 CD2 VS1 VS2 Vcc/Vpp Card Power Circuit pcmcia_access PWRON endianness INT GEN Static Signals Interface interrupts debug_signals Figure 15-2. PCMCIA Host Adapter Simplified Block Diagram PCMCIA host adapter module provides the all the necessary control logic for a single PCMCIA socket and only requires some additional external analog power switching logic and buffering for PC card operations. PCMCIA host adapter module can support one PCMCIA socket. PCMCIA controller shares its pins with other modules in the EIM area of the chip. The modules that share pins with PCMCIA are EIM, SDRAMC and NAND controllers. 15.3.1 Interrupt Generation There are 14 interrupt sources in PCMCIA controller. In addition, PCMCIA generates a signal which is a locator of all the possible interrupts. It is up to the system’s integrator to decide which signal(s) to connect to the system’s interrupt controller module. PCMCIA Input Pins Register (PIPR) reports any change of inputs from the PCMCIA card to the host (BVD,CD,RDY,VS). PCMCIA Controller Status Changed MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-4 Freescale Semiconductor External Memory Interface (EMI) Register (PSCR) contents are logically ANDed with PCMCIA Controller Enable Register (PER) to generate a PCMCIA controller interrupt. The interrupt level is user programmable and the PCMCIA controller can generate an additional interrupt for RDY/IREQ that can trigger upon a level (low or high) change or edge (fall or rise) of the input signal. 15.3.2 Card Extraction When a PC card is extracted the PCMCIA controller’s registers are not reset. The registers settings remain the same as before the card’s extraction. This allows the host software to quickly activate the card once the CIS indicates that it’s the same card on reinsertion. 15.3.3 TrueIDE Support The ATA standard specifies an AT attachment interface between the host systems and storage devices. PCMCIA controller can be dynamically configured to support a PCMCIA-compatible ATA disk interface (commonly known as IDE) instead of the standard PCMCIA card interface. Using the TrueIDE interface on the PCMCIA controller changes the function of some card socket signals to support the needs of ATA disk interface. 15.4 NAND Flash Controller (NFC) The NFC module interfaces standard NAND Flash devices to the IC and hides the complexities of accessing a NAND Flash memory device. It provides a glueless interface to both 8-bits and 16-bits NAND Flash parts with page sizes of 512 Bytes or 2 Kilobytes and densities up to 2 Gbit. Figure 15-3 shows a simplified block diagram of the NAND Flash controller. BOOTLOADER NAND FLASH CONTROL CLE ALE CE RE READ and WRITE RAM BUFFER ECC CONTROL AHB BUS INTERFACE HOST CONTROL WE AHB BUS WP DATA OUTPUT REGISTER (COMMAND ADDRESS/ STATUS) ADDRESS CONTROL RB DIN DOUT Figure 15-3. NAND Flash Controller Simplified Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-5 External Memory Interface (EMI) 15.4.1 Operation Communicating with a Flash memory device begins by the AHB host initiating a read from the NAND Flash controller (NFC). This is accomplished by configuring the NFC and then waiting for an interrupt from the Flash memory device to be generated. When the NFC receives the interrupt, it inputs a page from the Flash memory device, and upon completion, generates an interrupt to the AHB Host. When AHB host receives the NFC interrupt, it reads the content from the internal RAM buffer of the NFC. To complete the operation the AHB host checks the status of operation by reading the NFC status registers. Data that is exchanged with the Flash memory device is temporarily maintained in a 2 kilobyte RAM buffer. This buffer is used as the boot RAM during a cold reset (if the IC is configured for a boot to be carried out from the NAND Flash device). After the boot load completes, the RAM is available as buffer RAM for normal Flash memory operations. 15.4.1.1 Internal and External Communications To ensure the greatest degree of flexibility, NFC provides an internal X16 bit and X32 bit interface to the AHB bus allowing, 16-bit or 32-bit bus transfers, and a pin selectable X8 or X16 interface to the external NAND Flash memory device. All communications between the NFC and the ARM9 platform is accomplished through the AHB host. Configuration and control of the NFC by the host is done using 14 16-bit registers. NFC generates all the control signals that controls the NAND Flash: CE (Flash Chip Enable), RE (Read Enable for read operations), WE (Flash Write Enable), CLE (Flash Command Latch Enable), ALE (Flash Address Latch Enable). It also monitors the R/nB (Flash Ready/Busy indication) signal to check if the NAND Flash memory device is currently in the middle of an operation. Flash memory data’s integrity is monitored by automatic generation of ECC code of data during NFCs data loading from NAND Flash memory devices. 15.4.1.2 Sharing of I/O Pins The NFC provides necessary logic to share I/O pins with pins of another memory controller. NFC state machine halts when a request to free the pins is asserted. NAND Flash signals when it finishes the existing transfer allowing other memory controller to control them. Since NAND Flash memory accesses are typically long and relatively slow, priority is given to other memory controller sharing the pins. NFC must wait until other memory controller is finished with its operation and the pins are free before it can continue with its accesses. One example for this pin muxing is sharing the 16 I/O pins of the NAND Flash Controller with the Data pins of the Wireless External Interface Module (WEIM) when interfacing to a PSRAM. 15.5 Enhanced SDRAM Controller (ESDRAMC) The ESDRAMC module provides interface, configuration and control for many different types synchronous SDRAM and Low Power Mobile DDR (LPDDR) memories. Figure 18-1 is the Enhanced SDRAM Controller top-level diagram that shows the functional organization of the block. Enhanced SDRAM Controller consists of 9 major blocks, including the SDRAM command state machine controller, bank register (page and bank address comparators), Row/Column Address Multiplexer, configuration registers, refresh request counter, command sequencer, size logic (splitting access), data path (data aligner/multiplexer), LPDDR interface and the Power Down timer. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-6 Freescale Semiconductor External Memory Interface (EMI) 15.6 M3IF AHB MUX The M3IF AHB MUX module controls traffic on the AHB bus (address and controls) between the memory controllers and the IC. M3IF uses several muxes/glue logic to control the traffic on the AHB bus. Only several AHB signals/busses are routed through the EMI AHB MUX toward the memory controllers. Most of the AHB busses (data, address and controls) are directly routed from the M3IF to the memory controllers. 15.6.1 Overview of EMI AHB MUX Operation Figure 15-4 illustrates EMI AHB MUX block diagram. The interface is ARM’s 11 AMBA-AHB-Lite compliant (does not support RETRY and SPLIT transfers). All AHB signals that are not shown in Figure 15-4 are directly routed between the M3IF and the relevant memory controllers. For the entire list of AHB signals refer to Table 15-3 and to the relevant memory controller specification document. EMI AHB MUX generates HSEL signals for all memory controllers except ESDCTL (generated within the M3IF due to latency hiding logic). 15.7 M3IF I/O MUX M3IF I/O MUX controls the traffic (data, address and controls) between the memory controllers and the external devices (via the IC I/O MUX/PADS), and vice versa, for example, from the external devices to the memory controllers. The M3IF uses several muxes/glue logic to control the traffic. Refer Figure 15-4 and Figure 15-5 for a top level diagram of the EMIAHB and the EMI I/O MUX. Only shared IC PADS signals/busses are routed through the EMI I/O MUX toward the external devices. Signals (mainly controls) that have dedicated PADS are directly routed from the memory controllers to the external devices. 15.7.1 Overview of EMI I/O MUX Operation The signals not shown in Figure 15-5 are directly routed between the memory controllers and the respective external device. For entire list of signals, refer Table 15-3 and the relevant memory controller section. The select for muxes is CHOOSEN_SLAVE[1:0] bus driven by M3IF. CHOOSEN_SLAVE encoding is listed in Table 15-1 which summarizes EMI outputs to IC pads (dedicated and shared among all memory controllers). Table 15-1. CHOOSEN_SLAVE Encoding CHOOSEN_SLAVE Value 00 01 10 11 Selected Memory Controller ESDCTL/MDDRC WEIM PCMCIA NFC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-7 External Memory Interface (EMI) PCMCIA_HSEL_CARD PCMCIA_HSEL_REG HREADY M3IF ARBITRATION (AMB + M3A) HRESP_NFC HSEL_NFC HREADY HADDR[31:12] EMI AHB MUX HREADY_EIM HRESP_EIM HREADY HSEL_WEIM_CS0 HSEL_WEIM_CS1 HSEL_WEIM_CS2 HSEL_WEIM_CS3 HSEL_WEIM_CS4 HSEL_WEIM_CS5 HSEL_WEIM_REG HRESP0 Figure 15-4. EMI AHB MUX Interface Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-8 Freescale Semiconductor WEIM CONTROLLER NAND Flash HREADY_NFC CONTROLLER PCMCIA CONTROLLER HREADY_PCMCIA HRESP_PCMCIA External Memory Interface (EMI) ESDCTL/MDDRC CONTROLLER SDCTL_CSD0_SEL_B SDCTL_CSD1_SEL_B M3IF_MA M3IF_CS_B 14 2 M3IF_WR_DATA 32 32 M3IF_RD_DATA IPP_DO_CARD_ADDRESS_O 26 IPP_DO_CARD_WR_DATA_O 16 IPP_DO_E M I_IO_EB_B IPP_DO_E M I_IO_OE_B 2 PCMCIA CONTROLLER IPP_DO_CARD_CE_B IPP_DO_CARD_OE_B IPP_DO_CARD_REG_B_O IPP_DO_CARD_IORD_B IPP_DO_CARD_IOWR_B IPP_DO_CARD_WE_B IPP_DO_CARD_RW_B 2 IPP_OBE_E M I_IO_DATA_DIIR 2 IPP_DO_WEIM_CS_B2_CSD0 IPP_DO_WEIM_CS_B3_CSD1 EMI I/O MUX IPP_DO_E M I_ADDR 26 IPP_DO_WEIM_RW_B NAND Flash CONTROLLER 16 IPP_NFC_READ_DATA_IN 31 IPP_IND_EMI_DATA_IN 16 IPP_IND_NFC_READ_DATA_IN 16 WEIM_ADDR WEIM_DATA_OUT WEIM_EB_B WEIM_ADDR_IN 26 16 2 2 WEIM CONTROLLER IPP_DO_WEIM_CS_B WEIM_RW_B WEIM_WR_OE WEIM_OE_B 4 CHOOSEN_SLAVE(M3IF) 2 Figure 15-5. EMI I/O MUX Interface Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-9 SRAM/PSRAM FLASH NAND Flash DEVICE IPP_NFC_WRITE_DATA_OUT 16 16 IPP_IND_ADDR_IN IC I O M U X - P A D S PCMCIA DEVICE IPP_DO_NFC_WRITE_DATA_O16 SDRAM/MDDR DEVICE External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description MEMORY Controller Outputs EMI Output SDRAMC MDDRC PCMCIA WEIM NFC IC Pin Name WEIM/ESDCTL/PCMCIA Address MUXING/WEIM Muxed Mode Data[15:0] M3IF_MA[0] — M3IF_MA[1] — M3IF_MA[2] — M3IF_MA[3] — M3IF_MA[4] — M3IF_MA[5] — M3IF_MA[6] — M3IF_MA[7] — M3IF_MA[8] — IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[0] UT[0] — WEIM_ADDR_DATA_I N[0] — — IPP_DO_E M I _ADDR [0] IPP_IND_ADDR_IN [0] IPP_DO_E M I _ADDR [1] IPP_IND_ADDR_IN [1] — IPP_DO_E M I _ADDR [2] IPP_IND_ADDR_IN [2] — IPP_DO_E M I _ADDR [3] IPP_IND_ADDR_IN [3] — IPP_DO_E M I _ADDR [4] IPP_IND_ADDR_IN [4] — IPP_DO_E M I _ADDR [5] IPP_IND_ADDR_IN [5] — IPP_DO_E M I _ADDR [6] IPP_IND_ADDR_IN [6] — IPP_DO_E M I _ADDR [7] IPP_IND_ADDR_IN [7] — IPP_DO_E M I _ADDR [8] IPP_IND_ADDR_IN [8] A8 A7 A6 A5 A4 A3 A2 A1 A0 IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[1] UT[1] — WEIM_ADDR_DATA_I N[1] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[2] UT[2] — WEIM_ADDR_DATA_I N[2] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[3] UT[3] — WEIM_ADDR_DATA_I N[3] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[4] UT[4] — WEIM_ADDR_DATA_I N[4] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[5] UT[5] — WEIM_ADDR_DATA_I N[5] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[6] UT[6] — WEIM_ADDR_DATA_I N[6] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[7] UT[7] — WEIM_ADDR_DATA_I N[7] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[8] UT[8] — WEIM_ADDR_DATA_I N[8] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-10 Freescale Semiconductor External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC MDDRC PCMCIA WEIM NFC — IPP_DO_E M I _ADDR [9] IPP_IND_ADDR_IN [9] — IPP_DO_E M I _ADDR [10] IPP_IND_ADDR_IN [10] — IPP_DO_E M I _ADDR [11] IPP_IND_ADDR_IN [11] — IPP_DO_E M I _ADDR [12] IPP_IND_ADDR_IN [12] — IPP_DO_E M I _ADDR [13] IPP_IND_ADDR_IN [13] — IPP_DO_E M I _ADDR [14] IPP_IND_ADDR_IN [14] — IPP_DO_E M I _ADDR [15] IPP_IND_ADDR_IN [15] — — — — — IPP_DO_E M I _ADDR [16] IPP_DO_E M I _ADDR [17] IPP_DO_E M I _ADDR [18] IPP_DO_E M I _ADDR [19] IPP_DO_E M I _ADDR [20] A16 A17 A18 A19 A20 A15 A14 A13 A12 A11 A10 IC Pin Name A9 M3IF_MA[9] — — — M3IF_MA[11] — M3IF_MA[12] — M3IF_MA[13] — — IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[9] UT[9] — WEIM_ADDR_DATA_I N[9] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[10] UT[10] — WEIM_ADDR_DATA_I N[10] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[11] UT[11] — WEIM_ADDR_DATA_I N[11] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[12] UT[12] — WEIM_ADDR_DATA_I N[12] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[13] UT[13] — WEIM_ADDR_DATA_I N[13] IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[14] UT[14] WEIM_ADDR_DATA_I N[14] — IPP_DO_CARD_ADD WEIM_ADDR_DATA_O RESS_O[15] UT[15] WEIM_ADDR_DATA_I N[15] — — — — — IPP_DO_CARD_ADD WEIM_ADDR_OUT[16] RESS_O[16] IPP_DO_CARD_ADD WEIM_ADDR_OUT[17] RESS_O[17] IPP_DO_CARD_ADD WEIM_ADDR_OUT[18] RESS_O[18] IPP_DO_CARD_ADD WEIM_ADDR_OUT[19] RESS_O[19] IPP_DO_CARD_ADD WEIM_ADDR_OUT[20] RESS_O[20] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-11 External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC — — — — — MDDRC PCMCIA WEIM NFC — — — — — IPP_DO_E M I _ADDR [21] IPP_DO_E M I _ADDR [22] IPP_DO_E M I _ADDR [23] IPP_DO_E M I _ADDR [24] IPP_DO_E M I _ADDR [25] IC Pin Name A21 A22 A23 A24 A25 IPP_DO_CARD_ADD WEIM_ADDR_OUT[21] RESS_O[21] IPP_DO_CARD_ADD WEIM_ADDR_OUT[22] RESS_O[22] IPP_DO_CARD_ADD WEIM_ADDR_OUT[23] RESS_O[23] IPP_DO_CARD_ADD WEIM_ADDR_OUT[24] RESS_O[24] IPP_DO_CARD_ADD WEIM_ADDR_OUT[25] RESS_O[25] ESDCTL address bit M3IF_MA[10] has a dedicated pad MA10 (required due to PRECHARGE ALL during AUTO REFRESH commands). ESDCTL BANK address bits have dedicated PADS due to PRECHARGE BANK during PRECHARGE TIMER time-out WEIM CRE signal is driven on A23 in MUXED MODE OPERATION. M3IF_MA[10] M3IF_BA[0] M3IF_BA[1] — IPP_DO_CARD_CE_ B[2] IPP_DO_CARD_CE_ B[1] — — — — — — IPP_DO_E M I _MA10 IPP_DO_SDBA[1:0] MA10 SDBA0 SDBA1 Since SDBA PADS are shared between SDR/DDR SDRAM BANK ADDRESS and PCMCIA CE‘, ESDCTL PRECHARGE TIMER cannot be used. During precharge timer, after selected inactivity period of time expires, ESDCTL issue a PRECHARGE command to a specific bank during OFF LINE period. It means that PRECHARGE command can be issued during the time when EMI BUS is not possessed by ESDCTL. SDRAM/MDDR Dedicated Data Pads M3IF_WR_DATA[0] M3IF_RD_DATA[0] M3IF_WR_DATA[1] M3IF_RD_DATA[1] M3IF_WR_DATA[2] M3IF_RD_DATA[2] — — — — — — — — — IPP_DO_EMII_DATA [0] IPP_IND_EMII_DATA _IN [0] IPP_DO_EMII_DATA [1] IPP_IND_EMII_DATA _IN [1] IPP_DO_EMII_DATA [2] IPP_IND_EMII_DATA _IN [2] SD2 SD1 SD0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-12 Freescale Semiconductor External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC MDDRC PCMCIA — WEIM — NFC — IPP_DO_EMII_DATA [3] IPP_IND_EMII_DATA _IN [3] — — — IPP_DO_EMII_DATA [4] IPP_IND_EMII_DATA _IN [4] — — — IPP_DO_EMII_DATA [5] IPP_IND_EMII_DATA _IN [5] — — — IPP_DO_EMII_DATA [6] IPP_IND_EMII_DATA _IN [6] — — — IPP_DO_EMII_DATA [7] IPP_IND_EMII_DATA _IN [7] — — — IPP_DO_EMII_DATA [8] IPP_IND_EMII_DATA _IN [8] — — — IPP_DO_EMII_DATA [9] IPP_IND_EMII_DATA _IN [9] — — — IPP_DO_EMII_DATA [10] IPP_IND_EMII_DATA _IN [10] — — — IPP_DO_EMII_DATA [11] IPP_IND_EMII_DATA _IN [11] SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 IC Pin Name SD3 M3IF_WR_DATA[3] M3IF_RD_DATA[3] M3IF_WR_DATA[4] M3IF_RD_DATA[4] M3IF_WR_DATA[5] M3IF_RD_DATA[5] M3IF_WR_DATA[6] M3IF_RD_DATA[6] M3IF_WR_DATA[7] M3IF_RD_DATA[7] M3IF_WR_DATA[8] M3IF_RD_DATA[8] M3IF_WR_DATA[9] M3IF_RD_DATA[9] M3IF_WR_DATA[10] M3IF_RD_DATA[10] M3IF_WR_DATA[11] M3IF_RD_DATA[11] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-13 External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC MDDRC PCMCIA — WEIM — NFC — IPP_DO_EMII_DATA [12] IPP_IND_EMII_DATA _IN [12] — — — IPP_DO_EMII_DATA [13] IPP_IND_EMII_DATA _IN [13] — — — IPP_DO_EMII_DATA [14] IPP_IND_EMII_DATA _IN [14] — — — IPP_DO_EMII_DATA [15] IPP_IND_EMII_DATA _IN [15] — — — IPP_DO_EMII_DATA [16] IPP_IND_EMII_DATA _IN [16] — — — IPP_DO_EMII_DATA [17] IPP_IND_EMII_DATA _IN [17] — — — IPP_DO_EMII_DATA [18] IPP_IND_EMII_DATA _IN [18] — — — IPP_DO_EMII_DATA [19] IPP_IND_EMII_DATA _IN [19] — — — IPP_DO_EMII_DATA [20] IPP_IND_EMII_DATA _IN [20] SD20 SD19 SD18 SD17 SD16 SD15 SD14 SD13 IC Pin Name SD12 M3IF_WR_DATA[12] M3IF_RD_DATA[12] M3IF_WR_DATA[13] M3IF_RD_DATA[13] M3IF_WR_DATA[14] M3IF_RD_DATA[14] M3IF_WR_DATA[15] M3IF_RD_DATA[15] M3IF_WR_DATA[16] M3IF_RD_DATA[16] M3IF_WR_DATA[17] M3IF_RD_DATA[17] M3IF_WR_DATA[18] M3IF_RD_DATA[18] M3IF_WR_DATA[19] M3IF_RD_DATA[19] M3IF_WR_DATA[20] M3IF_RD_DATA[20] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-14 Freescale Semiconductor External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC MDDRC PCMCIA — WEIM — NFC — IPP_DO_EMII_DATA [21] IPP_IND_EMII_DATA _IN [21] — — — IPP_DO_EMII_DATA [22] IPP_IND_EMII_DATA _IN [22] — — — IPP_DO_EMII_DATA [23] IPP_IND_EMII_DATA _IN [23] — — — IPP_DO_EMII_DATA [24] IPP_IND_EMII_DATA _IN [24] — — — IPP_DO_EMII_DATA [25] IPP_IND_EMII_DATA _IN [25] — — — IPP_DO_EMII_DATA [26] IPP_IND_EMII_DATA _IN [26] — — — IPP_DO_EMII_DATA [27] IPP_IND_EMII_DATA _IN [27] — — — IPP_DO_EMII_DATA [28] IPP_IND_EMII_DATA _IN [28] — — — IPP_DO_EMII_DATA [29] IPP_IND_EMII_DATA _IN [29] SD29 SD28 SD27 SD26 SD25 SD24 SD23 SD22 IC Pin Name SD21 M3IF_WR_DATA[21] M3IF_RD_DATA[21] M3IF_WR_DATA[22] M3IF_RD_DATA[22] M3IF_WR_DATA[23] M3IF_RD_DATA[23] M3IF_WR_DATA[24] M3IF_RD_DATA[24] M3IF_WR_DATA[25] M3IF_RD_DATA[25] M3IF_WR_DATA[26] M3IF_RD_DATA[26] M3IF_WR_DATA[27] M3IF_RD_DATA[27] M3IF_WR_DATA[28] M3IF_RD_DATA[28] M3IF_WR_DATA[29] M3IF_RD_DATA[29] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-15 External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC MDDRC PCMCIA — WEIM — NFC — IPP_DO_EMII_DATA [30] IPP_IND_EMII_DATA _IN [30] — — — IPP_DO_EMII_DATA [31] IPP_IND_EMII_DATA _IN [31] WEIM/NFC/PCMCIA Data Muxing — IPP_DO_CARD_WR _DATA_O[0] IPP_IND_CARD_RD _DATA_I[0] — IPP_DO_CARD_WR _DATA_O[1] IPP_IND_CARD_RD _DATA_I[1] — IPP_DO_CARD_WR _DATA_O[2] IPP_IND_CARD_RD _DATA_I[2] — IPP_DO_CARD_WR _DATA_O[3] IPP_IND_CARD_RD _DATA_I[3] — IPP_DO_CARD_WR _DATA_O[4] IPP_IND_CARD_RD _DATA_I[4] — IPP_DO_CARD_WR _DATA_O[5] IPP_IND_CARD_RD _DATA_I[5] — IPP_DO_CARD_WR _DATA_O[6] IPP_IND_CARD_RD _DATA_I[6] WEIM_DATA_OUT[0] WEIM_DATA_IN[0] WEIM_DATA_OUT[1] WEIM_DATA_IN[1] WEIM_DATA_OUT[2] WEIM_DATA_IN[2] WEIM_DATA_OUT[3] WEIM_DATA_IN[3] WEIM_DATA_OUT[4] WEIM_DATA_IN[4] WEIM_DATA_OUT[5] WEIM_DATA_IN[5] WEIM_DATA_OUT[6] WEIM_DATA_IN[6] IPP_NFC_WRITE_D ATA_OUT[0] IPP_NFC_READ_DA TA_IN[0] IPP_NFC_WRITE_D ATA_OUT[1] IPP_NFC_READ_DA TA_IN[1] IPP_NFC_WRITE_D ATA_OUT[2] IPP_NFC_READ_DA TA_IN[2] IPP_NFC_WRITE_D ATA_OUT[3] IPP_NFC_READ_DA TA_IN[3] IPP_NFC_WRITE_D ATA_OUT[4] IPP_NFC_READ_DA TA_IN[4] IPP_NFC_WRITE_D ATA_OUT[5] IPP_NFC_READ_DA TA_IN[5] IPP_NFC_WRITE_D ATA_OUT[6] IPP_NFC_READ_DA TA_IN[6] IPP_DO_NFC_WRIT E_ DATA_OUT [0] IPP_IND_NFC_REA D_ DATA_IN [0] IPP_DO_NFC_WRIT E_ DATA_OUT [1] IPP_IND_NFC_REA D_ DATA_IN [1] IPP_DO_NFC_WRIT E_ DATA_OUT [2] IPP_IND_NFC_REA D_ DATA_IN [2] IPP_DO_NFC_WRIT E_ DATA_OUT [3] IPP_IND_NFC_REA D_ DATA_IN [3] IPP_DO_NFC_WRIT E_ DATA_OUT [4] IPP_IND_NFC_REA D_ DATA_IN [4] IPP_DO_NFC_WRIT E_ DATA_OUT [5] IPP_IND_NFC_REA D_ DATA_IN [5] IPP_DO_NFC_WRIT E_ DATA_OUT [6] IPP_IND_NFC_REA D_ DATA_IN [6] D6 D5 D4 D3 D2 D1 D0 SD31 IC Pin Name SD30 M3IF_WR_DATA[30] M3IF_RD_DATA[30] M3IF_WR_DATA[31] M3IF_RD_DATA[31] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-16 Freescale Semiconductor External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC — MDDRC PCMCIA IPP_DO_CARD_WR _DATA_O[7] IPP_IND_CARD_RD _DATA_I[7] — IPP_DO_CARD_WR _DATA_O[8] IPP_IND_CARD_RD _DATA_I[8] — IPP_DO_CARD_WR _DATA_O[9] IPP_IND_CARD_RD _DATA_I[9] — IPP_DO_CARD_WR _DATA_O[10] IPP_IND_CARD_RD _DATA_I[10] — IPP_DO_CARD_WR _DATA_O[11] IPP_IND_CARD_RD _DATA_I[11] — IPP_DO_CARD_WR _DATA_O[12] IPP_IND_CARD_RD _DATA_I[12] — IPP_DO_CARD_WR _DATA_O[13] IPP_IND_CARD_RD _DATA_I[13] — IPP_DO_CARD_WR _DATA_O[14] IPP_IND_CARD_RD _DATA_I[14] — IPP_DO_CARD_WR _DATA_O[15] IPP_IND_CARD_RD _DATA_I[15] WEIM WEIM_DATA_OUT[7] WEIM_DATA_IN[7] WEIM_DATA_OUT[8] WEIM_DATA_IN[8] WEIM_DATA_OUT[9] WEIM_DATA_IN[9] WEIM_DATA_OUT[10] WEIM_DATA_IN[10] WEIM_DATA_OUT[11] WEIM_DATA_IN[11] WEIM_DATA_OUT[12] WEIM_DATA_IN[12] WEIM_DATA_OUT[13] WEIM_DATA_IN[13] WEIM_DATA_OUT[14] WEIM_DATA_IN[14] WEIM_DATA_OUT[15] WEIM_DATA_IN[15] NFC IPP_NFC_WRITE_D ATA_OUT[7] IPP_NFC_READ_DA TA_IN[7] IPP_NFC_WRITE_D ATA_OUT[8] IPP_NFC_READ_DA TA_IN[8] IPP_NFC_WRITE_D ATA_OUT[9] IPP_NFC_READ_DA TA_IN[9] IPP_NFC_WRITE_D ATA_OUT[10] IPP_NFC_READ_DA TA_IN[10] IPP_NFC_WRITE_D ATA_OUT[11] IPP_NFC_READ_DA TA_IN[11] IPP_NFC_WRITE_D ATA_OUT[12] IPP_NFC_READ_DA TA_IN[12] IPP_NFC_WRITE_D ATA_OUT[13] IPP_NFC_READ_DA TA_IN[13] IPP_NFC_WRITE_D ATA_OUT[14] IPP_NFC_READ_DA TA_IN[14] IPP_NFC_WRITE_D ATA_OUT[15] IPP_NFC_READ_DA TA_IN[15] IPP_DO_NFC_WRIT E_ DATA_OUT [7] IPP_IND_NFC_REA D_ DATA_IN [7] IPP_DO_NFC_WRIT E_ DATA_OUT [8] IPP_IND_NFC_REA D_ DATA_IN [8] IPP_DO_NFC_WRIT E_ DATA_OUT [9] IPP_IND_NFC_REA D_ DATA_IN [9] IPP_DO_NFC_WRIT E_ DATA_OUT [10] IPP_IND_NFC_REA D_ DATA_IN [10] IPP_DO_NFC_WRIT E_ DATA_OUT [11] IPP_IND_NFC_REA D_ DATA_IN [11] IPP_DO_NFC_WRIT E_ DATA_OUT [12] IPP_IND_NFC_REA D_ DATA_IN [12] IPP_DO_NFC_WRIT E_ DATA_OUT [13] IPP_IND_NFC_REA D_ DATA_IN [13] IPP_DO_NFC_WRIT E_ DATA_OUT [14] IPP_IND_NFC_REA D_ DATA_IN [14] IPP_DO_NFC_WRIT E_ DATA_OUT [15] IPP_IND_NFC_REA D_ DATA_IN [15] D15 D14 D13 D12 D11 D10 D9 D8 IC Pin Name D7 MASK (Byte Enable) Muxing MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-17 External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC — — MDDRC — — PCMCIA IPP_DO_CARD_RE G_B_O IPP_DO_CARD_IOR D_B WEIM WEIM_EB_B[0] WEIM_EB_B[1] NFC — — IPP_DO_E M I _IO_EB_B[1:0] IC Pin Name EB0 EB1 EB_B[2] and EB_B[3] WILL BE DRIVEN ON A24 and A25 RESPECTIVELLY DURING MUXED MODE (IN ORDER TO USE 32 BIT MEMORY DEVICE. SDRAM/MDDR Mask (Byte Enable) M3IF_DQM[0] M3IF_DQM[1] M3IF_DQM[2] M3IF_DQM[3] — — — — — — — — Output Enable Muxing — IPP_DO_CARD_IOW R_B WEIM_WR_OE — IPP_DO_EMI _OE_B OE — — — — IPP_DO_DQM [3:0] DQM0 DQM1 DQM2 DQM3 Chip Select Muxing — — — — — — — — — — IPP_DO_WEIM_CS_B[ 0] IPP_DO_WEIM_CS_B[ 1] IPP_DO_WEIM_CS_B[ 2] IPP_DO_WEIM_CS_B[ 3] IPP_DO_WEIM_CS_B[ 4] IPP_DO_WEIM_CS_B[ 5] — — — — — — IPP_DO_WEIM_ CS_B0 IPP_DO_WEIM_ CS_B1 IPP_DO_WEIM_ CS_B2_CSD0 IPP_DO_WEIM_ CS_B3_CSD1 IPP_DO_WEIM_ CS_B4 IPP_DO_WEIM_ CS_B5 CS0 CS1 CS2 CS3 CS4 CS5 M3IF_CS_B[0] M3IF_CS_B[1] — — — — CHIP SELECT are SYSTEM CONTROL REGISTER bits SDCTL_CSD0_SEL and SDCTL_CSD1_SEL respectively. Default select for both CHIP SELECTS are for the ESDCTL/MDDRC. WRITE Enable Muxing — — IPP_DO_CARD_WE _B WEIM_RW_B — IPP_DO_WEIM_ RW_B RW SDRAM/MDDR Command Dedicated Pads RAS_B — — — IPP_DO_M3IF_RAS_ B RAS MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-18 Freescale Semiconductor External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC MDDRC PCMCIA — — — — — — WEIM — — — — — — NFC — — — — — — IPP_DO_M3IF_CAS_ B IPP_DO_SDRC_SD WE IC Pin Name CAS SDWE CAS_B WE_B CKE[1] CKE[0] SDCLK_OUT — MDDR_ SDCLK_ B DQS_O UT [3] DQS_IN [3] — — — — — — — DQS_O UT [2] DQS_IN [2] DQS_O UT [1] DQS_IN [1] DQS_O UT [0] DQS_IN [0] — IPP_DO_SDRC_SDC SDCK KE[1] E [1] IPP_DO_SDRC_SDC SDCK KE[0] E [0] IPP_DO_SDRC_SDC SDCLK LK IPP_DO_MDDR_SD SDCLK CLK_B _B IPP_DO_DQS[3] IPP_DIN_DQS[3] DQS[3] — — — — — — — — — — — — — — — — — — — — — — — — — IPP_DO_DQS[2] IPP_DIN_DQS[2] IPP_DO_DQS[1] IPP_DIN_DQS[1] IPP_DO_DQS[0] IPP_DIN_DQS[0] M_REQUEST DQS[2] DQS[1] DQS[0] M_RE QUES T M_GR ANT — — — — — M_GRANT NFC Command Dedicated Pads — — — — — — — — IPP_NFC_WE_OUT IPP_NFC_WP_OUT IPP_NFC_WE_OUT IPP_NFC_WP_OUT NFWE _B NFWP _B MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-19 External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC — — — — — MDDRC — — — — — PCMCIA — — — — — WEIM — — — — — NFC IPP_NFC_RE_OUT IPP_NFC_ALE_OUT IPP_NFC_CLE_OUT IPP_NFC_CE_OUT IPP_NFC_RB_IN IPP_NFC_RE_OUT IC Pin Name NFRE_ B IPP_NFC_ALE_OUT NFALE IPP_NFC_CLE_OUT NFCLE IPP_NFC_CE_OUT IPP_NFC_RB_IN NFCE_ B NFRB WEIM Command Dedicated Pads — — — — — — IPP_DO_CARD_OE_ B — — IPP_DO_WEIM_LBA_ B IPP_DO_WEIM_BCLK IPP_IND_WEIM_ECB_ B — — — IPP_DO_WEIM_LBA LBA_B _B IPP_DO_WEIM_BCL K IPP_IND_WEIM_EC B_B BCLK ECB PCMCIA Command Dedicated Pads — — — — — — — — — — — — — — — — — — — — — — IPP_INT_CD1_B IPP_INT_CD2_B IPP_IND_WAIT_B_I IPP_IND_PWR_ON_I IPP_IND_RDY_IRQ_ B_I IPP_IND_VS1_B IPP_IND_VS2_B IPP_IND_BVD1_STS CH_B_I IPP_IND_BVD2_SPK R_I IPP_DO_CARD_RES ET IPP_DO_CARD_POE _O_B — — — — — — — — — — — — — — — — — — — — — — IPP_INT_CD1_B IPP_INT_CD2_B IPP_IND_WAIT_B_I IPP_IND_PWR_ON_I PC_C D1_B PC_C D2_B PC_W AIT_B PC_P WRON IPP_IND_RDY_IRQ_ PC_RE B_I ADY IPP_IND_VS1_B IPP_IND_VS2_B PC_VS 1 PC_VS 2 IPP_IND_BVD1_STS PC_BV CH_B_I D1 IPP_IND_BVD2_SPK PC_BV R_I D2 IPP_DO_CARD_RES PC_RS ET T IPP_DO_CARD_POE _O_B PC_P OE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-20 Freescale Semiconductor External Memory Interface (EMI) Table 15-2. External Memory Interface I/O MUX Description (continued) MEMORY Controller Outputs EMI Output SDRAMC — — MDDRC — — PCMCIA IPP_DO_CARD_RW _B IPP_IND_WP_I WEIM — — NFC — — IPP_DO_CARD_RW _B IPP_IND_WP_I IC Pin Name PC_R W_B IOIS16 15.7.2 EMI Input/Output Signals This section lists all input and output signals for the entire EMI module. Table 15-3 summarizes interface signals. For detailed descriptions of each signal function, refer to the relevant module chapters in this manual. Table 15-3. EMI Signal Properties Name Port Function AHB Interface Outputs M3IF_HREADY_M0 M3IF_HREADY_M1 M3IF_HREADY_M2 M3IF_HREADY_M3 M3IF_HREADY_M4 M3IF_HREADY_M5 M3IF_HREADY_M6 M3IF_HREADY_M7 M3IF_HRESP_M0 M3IF_HRESP_M1 M3IF_HRESP_M2 M3IF_HRESP_M3 M3IF_HRESP_M4 M3IF_HRESP_M5 M3IF_HRESP_M6 M3IF_HRESP_M7 M3IF_HRDATA_M0[63:0] M3IF_HRDATA_M1[63:0] M3IF_HRDATA_M2[63:0] M3IF_HRDATA_M3[31:0] M3IF_HRDATA_M4[63:0] O O O O O O O O O O O O O O O O O O O O O AHB access completion strobe to master #0 — LCDC AHB access completion strobe to master #1 — FEC AHB access completion strobe to master #2 eMMA AHB access completion strobe to master #3 MAX AHB access completion strobe to master #4 — H264 AHB access completion strobe to master #5 — H264 AHB access completion strobe to master #6 — H264 AHB access completion strobe to master #7 — USBOTG AHB error response to master #0 — LCDC AHB error response to master #1 — FEC AHB error response to master #2 eMMA AHB error response to master #3 MAX AHB error response to master #4 — H264 AHB error response to master #5 — H264 AHB error response to master #6 — H264 AHB error response to master #7 — USBOTG AHB read data bus to master #0 — LCDC AHB read data bus to master #1 — FEC AHB read data bus to master #2 eMMA AHB read data bus to master #3 MAX AHB read data bus to master #4 — H264 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset State MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-21 External Memory Interface (EMI) Table 15-3. EMI Signal Properties (continued) Name M3IF_HRDATA_M5[63:0] M3IF_HRDATA_M6[63:0] M3IF_HRDATA_M7[31:0] Port O O O Function AHB read data bus to master #5 — H264 AHB read data bus to master #6 — H264 AHB read data bus to master #7 — USBOTG M3IF and ESDCTL/MDDRC Outputs IPP_DO_SDRC_SDCKE[1:0] M3IF_DQM[3:0] O O SDRAM/MDDR clock enable SDRAM data mask strobes. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. MDDR data sample strobes for write accesses. DQS0 corresponds to DQ0–DQ7, DQS1 corresponds to DQ8–DQ15, DQS2 corresponds to DQ16–DQ23 and DQS3 corresponds to DQ24–DQ31. DQS output enable strobe SDRAM/MDDR address bits SDRAM/MDDR bank address bits SDRAM/MDDR address bit A10 SDRAM/MDDR chip select strobe SDRAM/MDDR CAS strobe SDRAM/MDDR RAS strobe SDRAM/MDDR WE strobe M3IF arbitration chosen master (for debug) SDRAM/MDDR clock (up to 133MHz) MDDR clock (up to 133MHz) Low power mode acknowledge — toward CCM Memory wakeup acknowledge indication to WDOG NFC Outputs IPP_DO_NFC_WRITE_DATA_O UT[15:0] IPI_INT_NFC_B IPP_NFC_ALE_OUT IPP_NFC_CE_OUT IPP_NFC_CLE_OUT IPP_NFC_RE_OUT IPP_NFC_WE_OUT IPP_NFC_WP_OUT O 0 O O O O O O NFC write data out toward I/O MUX/PADS. NFC interrupt (indicating an access completion) NFC out NF_ALE NFC out NF_CE NFC out NF_CLE NFC out NF_RE NFC out NF_WE NFC out NF_WP 0 1 0 0 0 0 0 0 0 0 Reset State 0 0 0 DQS_OUT[3:0] O 0 DQS_OUT_EN_X M3IF_MA[13:0] M3IF_BA[1:0] IPP_DO_M3IF_MA10 M3IF_CS_B[1:0] CAS_B RAS_B WE_B M3IF_CHOOSEN_MASTER[2:0] IPP_DO_SDRC_SDCLK IPP_DO_MDDR_SD_CLK_B LPACK SDRC_SF_WACK O O O O O O O O O O O O O 0 0 0 0 3 1 1 1 3 0 0 1 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-22 Freescale Semiconductor External Memory Interface (EMI) Table 15-3. EMI Signal Properties (continued) Name Port WEIM Outputs IPP_DO_WEIM_CS_B0 IPP_DO_WEIM_CS_B1 IPP_DO_WEIM_CS_B2_CSD0 IPP_DO_WEIM_CS_B3_CSD1 IPP_DO_WEIM_CS_B4 IPP_DO_WEIM_CS_B5 IPP_DO_WEIM_BCLK IPP_DO_LBA_B IPP_DO_WEIM_RW_B O O O O O O O O O WEIM CS0 chip select toward I/O MUX/PADS WEIM CS1 chip select toward I/O MUX/PADS WEIM CS2 or ESDCTL/MDDRC CSD0 chip select toward I/O MUX/PADS WEIM CS2 or ESDCTL/MDDRC CSD1 chip select toward I/O MUX/PADS WEIM CS4 chip select toward I/O MUX/PADS WEIM CS5 chip select toward I/O MUX/PADS WEIM Burst Clock WEIM Load Burst Address (LBA) WEIM read/write strobe PCMCIA Outputs IPI_INT_BVD1_B IPI_INT_BVD2_B IPI_INT_CD1_B IPI_INT_CD2_B IPI_INT_ERR_B IPI_INT_IRQ_B IPI_INT_NFC_B IPI_INT_PCMCIA_B IPI_INT_POWERON_B IPI_INT_RDY_F_B IPI_INT_RDY_H_B IPI_INT_RDY_L_B IPI_INT_RDY_R_B IPI_INT_STS_B IPI_INT_VS1_B IPI_INT_VS2_B IPI_INT_WP_B IPP_DO_CARD_POE_O IPP_DO_CARD_RESET_O IPP_DO_CARD_RW_B O O O O O O O O O O O O O O O O O O O O BVD1 changed interrupt BVD2 changed interrupt CD1 changed interrupt CD2 changed interrupt Access error interrupt or of all the ready interrupts NFC interrupt (indicating an action completed) or of all the interrupts (status+access+ready) POWER_ON changed interrupt RDY negedge interrupt RDY is high interrupt RDY is low level sensitive interrupt RDY posedge sensitive interrupt or of all the status interrupts VS1 changed interrupt VS2 changed interrupt WP changed interrupt POE signal to transceivers RESET signal to card RW_B Signal to data transceiver 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 Function Reset State MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-23 External Memory Interface (EMI) Table 15-3. EMI Signal Properties (continued) Name IPP_DO_SPKR_OUT_O Port O Function speaker out Global Outputs M3IF_DMA_ACCESS IPP_OBE_DDR_EN IPP_DO_EMI_ADDR[25:0] IPP_DO_NFC_WRITE_DATA_O UT[15:0] IPP_DO_EMI_DATA[31:0] IPP_OBE_EMI_DATA_DIR IPP_OBE_NFC_DIR_HIGH IPP_OBE_NFC_DIR_LOW IPP_DO_SDBA[1:0] IPP_DO_M3IF_MA10 IPP_DO_EMI_IO_DQM[3:0] IPP_DO_EMI_OE_B IPP_OBE_IO_ADDR_DIR[1:0] O O O O O O O O O O O O O Snooping detection indication toward IPU module MDDR active indication to ESDCTL/MDDRC DATA PADS EMI address out toward I/O MUX/PADS EMI data (NFC, WEIM) out toward I/O MUX/PADS EMI SDRAM/DDR data out toward I/O MUX/PADS EMI SDRAM/DDR data direction toward I/O MUX/PADS EMI (NFC, WEIM, PCMCIA) data direction toward I/O MUX/PADS EMI (NFC, WEIM, PCMCIA) data direction toward I/O MUX/PADS SDRAM/MDDR bank address toward I/O MUX/PADS SDRAM/MDDR address bit MA10 toward I/O MUX/PADS SDRAM/MDDR enable bytes toward I/O MUX/PADS EMI output enable toward I/O MUX/PADS EMI output enable (dir) toward I/O ADDR/WEIM MUXED DATA MUX/PADS AHB Interface Inputs M3IF_HADDR_M0[31:0] M3IF_HADDR_M1[31:0] M3IF_HADDR_M2[31:0] M3IF_HADDR_M3[31:0] M3IF_HADDR_M4[31:0] M3IF_HADDR_M5[31:0] M3IF_HADDR_M6[31:0] M3IF_HADDR_M7[31:0] M3IF_HWDATA_M0[63:0] M3IF_HWDATA_M1[63:0] M3IF_HWDATA_M2[63:0] M3IF_HWDATA_M3[31:0] M3IF_HWDATA_M4[63:0] M3IF_HWDATA_M5[63:0] M3IF_HWDATA_M6[63:0] I I I I I I I I I I I I I I I AHB address bus from master #0 — LCDC AHB address bus from master #1 — FEC AHB address bus from master #2 eMMA AHB address bus from master #3 MAX AHB address bus from master #4 — H264 AHB address bus from master #5 — H264 AHB address bus from master #6 — H264 AHB address bus from master #7 — USBOTG AHB write data bus (bit) from master #0 — LCDC AHB write data bus (bit) from master #1 — FEC AHB write data bus (32 bit) from master #2 eMMA AHB write data bus (32 bit) from master #3 MAX AHB write data bus (32 bit) from master #4 — H264 AHB write data bus (32 bit) from master #5 — H264 AHB write data bus (32 bit) from master #6 — H264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset State 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-24 Freescale Semiconductor External Memory Interface (EMI) Table 15-3. EMI Signal Properties (continued) Name M3IF_HWDATA_M7[31:0] M3IF_HBURST_M0[2:0] M3IF_HBURST_M1[2:0] M3IF_HBURST_M2[2:0] M3IF_HBURST_M3[2:0] M3IF_HBURST_M4[2:0] M3IF_HBURST_M5[2:0] M3IF_HBURST_M6[2:0] M3IF_HBURST_M7[2:0] M3IF_HSIZE_M0[1:0] M3IF_HSIZE_M1[1:0] M3IF_HSIZE_M2[1:0] M3IF_HSIZE_M3[1:0] M3IF_HSIZE_M4[1:0] M3IF_HSIZE_M5[1:0] M3IF_HSIZE_M6[1:0] M3IF_HSIZE_M7[1:0] M3IF_HBSTRB_M0[7:0] M3IF_HBSTRB_M1[7:0] M3IF_HBSTRB_M2[7:0] M3IF_HBSTRB_M3[3:0] M3IF_HBSTRB_M4[7:0] M3IF_HBSTRB_M5[7:0] M3IF_HBSTRB_M6[7:0] M3IF_HBSTRB_M7[3:0] M3IF_HTRANS_M0[1:0] M3IF_HTRANS_M1[1:0] M3IF_HTRANS_M2[1:0] M3IF_HTRANS_M3[1:0] M3IF_HTRANS_M4[1:0] M3IF_HTRANS_M5[1:0] M3IF_HTRANS_M6[1:0] M3IF_HTRANS_M7[1:0] Port I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Function AHB write data bus (32 bit) from master #7 — USBOTG AHB burst size bus from master #0 — LCDC AHB burst size bus from master #1 — FEC AHB burst size bus from master #2 eMMA AHB burst size bus from master #3 MAX AHB burst size bus from master #4 —H264 AHB burst size bus from master #5 — H264 AHB burst size bus from master #6 — H264 AHB burst size bus from master #7 — USBOTG AHB data transfer width bus from master #0 — LCDC AHB data transfer width bus from master #1 — FEC AHB data transfer width bus from master #2 eMMA AHB data transfer width bus from master #3 MAX AHB data transfer width bus from master #4 — H264 AHB data transfer width bus from master #5 — H264 AHB data transfer width bus from master #6 —H264 AHB data transfer width bus from master #7 —USBOTG byte lane (8) bus from master #0 — LCDC byte lane (8) bus from master #1 — FEC byte lane (4) bus from master #2 eMMA byte lane (4) bus from master #3 MAX byte lane (4) bus from master #4 — H264 byte lane (4) bus from master #5 — H264 byte lane (4) bus from master #6 — H264 byte lane (4) bus from master #7 — USBOTG AHB transfer state bus from master #0 — LCDC AHB transfer state bus from master #1 — FEC AHB transfer state bus from master #2 eMMA AHB transfer state bus from master #3 MAX AHB transfer state bus from master #4 — H264 AHB transfer state bus from master #5 — H264 AHB transfer state bus from master #6 — H264 AHB transfer state bus from master #7 — USBOTG Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-25 External Memory Interface (EMI) Table 15-3. EMI Signal Properties (continued) Name M3IF_HWRITE_M0 M3IF_HWRITE_M1 M3IF_HWRITE_M2 M3IF_HWRITE_M3 M3IF_HWRITE_M4 M3IF_HWRITE_M5 M3IF_HWRITE_M6 M3IF_HWRITE_M7 M3IF_HPROT_M0 M3IF_HPROT_M1 M3IF_HPROT_M2 M3IF_HPROT_M3 M3IF_HPROT_M4 M3IF_HPROT_M5 M3IF_HPROT_M6 M3IF_HPROT_M7 M3IF_HUNALIGN_M0 M3IF_HUNALIGN_M1 M3IF_HUNALIGN_M2 M3IF_HUNALIGN_M3 M3IF_HUNALIGN_M4 M3IF_HUNALIGN_M5 M3IF_HUNALIGN_M6 M3IF_HUNALIGN_M7 Port I I I I I I I I I I I I I I I I I I I I I I I I Function AHB read/write signal from master #0 — LCDC AHB read/write signal from master #1 — FEC AHB read/write signal from master #2 eMMA AHB read/write signal from master #3 MAX AHB read/write signal from master #4 — H264 AHB read/write signal from master #5 — H264 AHB read/write signal from master #6 — H264 AHB read/write signal from master #7 — USBOTG AHB protection mode signal from master #0 — LCDC AHB protection mode signal from master #1 — FEC AHB protection mode signal from master #2 eMMA AHB protection mode signal from master #3 MAX AHB protection mode signal from master #4 — H264 AHB protection mode signal from master #5 — H264 AHB protection mode signal from master #6 —H264 AHB protection mode signal from master #7 —USBOTG Unalign access signal from master #0 — LCDC Unalign access signal from master #1 — FEC Unalign access signal from master #2 eMMA Unalign access signal from master #3 MAX Unalign access signal from master #4 — H264 Unalign access signal from master #5 — H264 Unalign access signal from master #6 — H264 Unalign access signal from master #7 — USBOTG M3IF and ESDCTL/MDDRC Inputs M3IF_HCLK HCLK32 IPP_IND_SDRC_SDCLK_FB LPMD DQS_IN[3:0] I I I I I M3IF AHB system clock—up to 133 MHz 32 KHz clock for ESDCTL refresh counter SDRAM/MDDR feedback clock (up to 133MHz) Low power mode indication signal, “0”=STOP, “1”=RUN. MDDR data sample strobes for read accesses. DQS0 corresponds to DQ0–DQ7, DQS1 corresponds to DQ8–DQ15, DQS2 corresponds to DQ16–DQ23 and DQS3 corresponds to DQ24–DQ31. 0 0 0 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-26 Freescale Semiconductor External Memory Interface (EMI) Table 15-3. EMI Signal Properties (continued) Name SDCTL_CSD0_SEL_B SDCTL_CSD1_SEL_B Port I I Function SDRAM/MDDR CSD0 select multiplexed with CS2 (configurable via the system control register, FMCR) SDRAM/MDDR CSD1 select multiplexed with CS3 (configurable via the system control register, FMCR) NFC Inputs NF16_BOOT_B NF8_BOOT_B NF_16BIT_SEL NFC_HCLK NFC_RD_OE NFC_WR_OE IPP_IND_FLASH_CLK IPP_IND_NFC_RB_IN I I I I I I I I Boot mode source is 16 bit NAND Flash memory. Boot mode source is 8 bit NAND Flash memory. 16 bit NAND Flash memory is use indication. NFC AHB input clock NFC read output enable — controls the direction of data bus NFC write output enable — controls the direction of data bus NAND Flash side clock with period of 40nS NFC in NF_RB WEIM Inputs WEIM_BOOT_CFG[3:0] IPP_IND_WEIM_ECB_B WEIM_HCLK IPP_IND_WEIM_DTACK_B I I I I WEIM BootMode select (from CCM) “101” - 16 bit CS0 at D[15:0] WEIM End Current Burst WEIM AHB input clock External DTACK acknowledge PCMCIA Inputs IPP_IND_CD_B_I[1:0] IPP_IND_VS_I[1:0] IPP_IND_BVD1_STSCH_B_I IPP_IND_BVD2_SPKR_I IPP_IND_PWR_ON_I IPP_IND_RDY_IRQ_B_I IPP_IND_WP_I I I I I I I I CD[1:0] signals from card VS[1:0] signals from card BVD1/STSCHG signals from card BVD2/SPKR signals from card POWER_ON signals from card/board READY/IRQ_B signals from card WP signals from card Global Inputs IPP_IND_RESETB HRESET_HCLK_B IPP_IND_NFC_READ_DATA_IN[ 15:0] IPP_IND_EMI_DATA_IN[31:0] I I I I Reset signal Reset signal External memories (non SDRAM) read data in from I/O MUX/PADS EMI SDRAM/DDR data in from I/O MUX/PADS 1 1 0 0 3 0 0 0 0 1 1 application dependent 1 0 1 application dependent application dependent 0 0 0 0 0 0 Reset State 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-27 External Memory Interface (EMI) Table 15-3. EMI Signal Properties (continued) Name IPP_IND_ADDR_IN[15:0] IPP_IND_EMI_DATA_IN[31:0] M3IF_BIGEND_M0 M3IF_BIGEND_M1 M3IF_BIGEND_M2 M3IF_BIGEND_M3 M3IF_BIGEND_M4 M3IF_BIGEND_M5 M3IF_BIGEND_M6 M3IF_BIGEND_M7 Port I I I I I I I I I I Function EMI WEIM muxed data in from I/O MUX/PADS. WEIM/NFC/PCMCIA address out to I/O MUX/PADS. SDRAM/MDDR read data in from I/O MUX/PADS Endian mode signal from master #0 — LCDC Endian mode signal from master #1 — FEC Endian mode signal from master #2 eMMA Endian mode signal from master #3 MAX Endian mode signal from master #4 — H264 Endian mode signal from master #5 — H264 Endian mode signal from master #6 — H264 Endian mode signal from master #7 — USBOTG Reset State 0 0 master dependent master dependent master dependent master dependent master dependent master dependent master dependent master dependent 15.8 Memory Map and Register Definitions The EMI supports four memory controllers. Table 15-4 and Table 15-5 illustrates the EMI registers and memory map (mapped by all memory controllers). For detailed descriptions regarding registers definitions and memory map, refer to the relevant module chapters in this manual. Table 15-4. EMI Registers Definition Address Use M3IF Registers Space 0xD800_3000–0xD800_3FFF M3IF registers space (4K) ESDCTL/MDDRC Registers Space 0xD800_1000–0xD800_1FFF ESDCTL/MDDRC registers space (4K) PCMCIA Registers Space 0xD800_4000–0xD800_4FFF PCMCIA registers space (4K) WEIM Registers Space 0xD800_2000–0xD800_2FFF WEIM registers space (4K) NFC Memory Space 0xD800_0E00–0xD800_0FFF NFC registers space Read/Write Read/Write Read/Write Read/Write Read/Write Access MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-28 Freescale Semiconductor External Memory Interface (EMI) Table 15-5. EMI Memory Map Address Use ESDCTL/MDDRC Memory Space 0xA000_0000–0xAFFF_FFFF 0xB000_0000–0xBFFF_FFFF CSD0 SDRAM/MDDR memory region (256 Mbytes) CSD1 SDRAM/MDDR memory region (256 Mbytes) PCMCIA Memory Space 0xDC00_0000–0xDCFF_FFFF PCMCIA/CF memory region (64 Mbytes) WEIM Memory Space 0xC000_0000–0xC7FF_FFFF 0xC800_0000–0xCFFF_FFFF 0xD000_0000–0xD1FF_FFFF 0xD200_0000–0xD3FF_FFFF 0xD400_0000–0xD5FF_FFFF 0xD600_0000–0xD7FF_FFFF WEIM CS0 memory region1 (128 Mbytes) WEIM CS1 memory region (128 Mbytes) WEIM CS2 memory region (32 Mbytes) WEIM CS3 memory region (32 Mbytes) WEIM CS4 memory region (32 Mbytes) WEIM CS5 memory region (32 Mbytes) NFC Memory Space 0xD800_0000–0xD800_0FFF 1. Can be used as a boot memory region. NFC memory region1 (4K, NAND Flash) Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Access MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 15-29 External Memory Interface (EMI) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 15-30 Freescale Semiconductor Chapter 16 Multi-Master Memory Interface (M3IF) The M3IF controls memory accesses (read/write/erase/program) from one or more masters through different port interfaces to different external memory controllers ESDCTL/MDDRC, PCMCIA, NAND Flash, and WEIM. Figure 16-1 provides top-level diagram that shows the functional organization of the block. 16.1 Overview The M3IF-ESDCTL/MDDRC interface is optimized and designed to reduce access latency by generating multiple accesses through the dedicated ESDCTL/MDDRC arbitration (MAB) module, which controls the access to/from the Enhanced SDRAM/MDDR memory controller. For the other port interfaces, the M3IF only arbitrates and forwards the master requests received through the Master Port Gasket (MPG) interface and M3IF Arbitration (M3A) module toward the respective memory controller. The masters that interface with the M3IF include the ARM Platform, SDMA, MPEG-4 encoder, and the IPU. The controllers are the ESDCTL/MDDRC, PCMCIA, NAND Flash, and WEIM. When a master requests a memory access, the access is immediately taken by the M3IF if no other access is in progress. The M3IF forwards the access to the respective memory controller (slave), and depending on the state of the respective memory controller, a command to the memory is generated. If the access cannot be started due to a previous active access, the master request remains pending (HREADY held negated) until it is executed by the memory controller. When the access execution is complete, the HREADY is asserted and a new request can be processed. Accesses to SDRAM or MDDR external devices are optimized through command anticipation (MIF2 strategy). For example, the next access control phase (memory address and command) is driven during the previous access data phase (data flow to/from the memory), thus an overlap between accesses is created and latency is partially or fully hidden. 16.1.1 M3IF Interfaces The interface between M3IF and the controllers can be divided into two different types: M3IF-ESDCTL, and M3IF-all others. The M3IF-ESDCTL/MDDRC interface reduces access latency by generating multiple accesses using the dedicated ESDCTL/MDDRC arbitration (MAB) module. For other port interfaces, M3IF arbitrates and forwards the masters’ requests received through the Master Port Gasket (MPG) interfaces and the M3IF arbitration (M3A) module toward the respective memory controller. To support multiple accesses to the ESDCTL/MDDRC, the MAB includes a FIFO which controls the access traffic from/to the ESDCTL/MDDRC. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-1 Multi-Master Memory Interface (M3IF) Multi Master Memory Interface (M3IF) Module M3IF REGISTERS 64 #0 MPG64 LCDC TMAX SLCDC FEC 64 (SDCTL) MASTER ARBITRATION and BUFFERING (MAB) eMMA-IT 64 Application (ARM) Platform A/P MAX M2 32 #3 MPG S2 M3 M4 M5 PCMCIA CTRL PCMCIA SRAM FLASH NAND Flash RTIC/ SAHARA2 DMA #2 MPG64 #1 MPG64 ESDCTL MDDRC H264-AHB M3IF ARBITRATION (M3A) NFC CTRL H264-PO 64 H264-PO 64 #5 MPG64 #4 MPG64 H264-PO 64 USBOTG #7 MPG 32 #6 MPG64 WEIM CTRL VIA EMI AND IO MUXES Figure 16-1. M3IF Block Diagram—System Overview MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-2 Freescale Semiconductor SDRAM/LP DDR Multi-Master Memory Interface (M3IF) M3IF can be viewed as a device that has multiple SDRAM/MDDR controllers and one controller per other memory type, therefore, the M3A arbitrates the requests as follows: • A round robin chooses the next master that is going to grant the bus: — If this master is requesting access to non-SDRAM/MDDR memory controller, M3A waits until the previous access finishes and only then passes the request. — If the master is requesting access to ESDCTL/MDDRC, M3IF arbitration passes the access to MAB in two cases: – After previous non-ESDCTL access is accomplished. – If previous access was to ESDCTL, M3IF arbitration will pass the request immediately without waiting for the previous access to accomplished. M3IF Arbitration (M3A) and the ESDCTL/MDDRC Master Arbitration and Buffering (MAB) supports a round-robin arbitration scheme (which can be programed to non-equal probability). If two masters request access to the memory port on the same cycle the master with the token (see Section 16.4.3.2, “M3A–Find First 1 (FF1) Algorithm” for more details) gains control on the bus to the slave. To support multiple accesses to the ESDCTL/MDDRC, the MAB includes a FIFO which controls the access traffic from/to the ESDCTL/MDDRC. Once a master grants the bus, the Memory Controller gaining the access converts the access to a command to the specified memory. 16.1.2 Features M3IF Master Port Gasket (MPG) converts the master request (data write, data read, address, and controls) to a set of bus/signals that the M3IF arbitration, the SDCTL/MDDRC arbitration, and other memory controllers need. The MPG is also responsible to give the right response to the master after getting the response from the relevant memory controller. M3IF support 2 port interfaces (the number and types of gasket ports used depends on the system requirements): MPG—Master Port Gasket for ARM9 AMBA-AHB lite with 32 bit data bus.MPG64—Master Port Gasket for AMBA-AHB lite with 64 bit data bus.The M3IF includes these distinctive features: • Supports multiple requests from masters through 2 different input port interfaces: — Master Port Gasket (MPG)—ARM9 AMBA AHB lite bus protocol. • Master Port Gasket (MPG64)—AMBA AHB access with 64 bits data bus width.Arbitrates requests to four different memory controllers (that share some of their I/O pads) — Enhanced SDRAM Controller (ESDCTL) or MDDR Controller (MDDRC) — NAND Flash Controller—(NFC) — PCMCIA Controller—Wireless External Interface Memory (WEIM) Controller • Multiple requests capabilities to ESDCTL through a dedicated arbitration mechanism. • Flexible round robin access arbitration, with equal priority or 50% priority to selective masters. • Programmable master that controls (lock) accesses to SDRAM/DDR and programmable master that controls (lock) accesses to other memories (= general: NFC, WEIM, PCMCIA). • Multi-endianness support to all memory controllers. • Supports memory snooping, an example of which would be monitoring a region in external memory for write accesses: MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-3 Multi-Master Memory Interface (M3IF) — The region’s location is specified by a base address (from 2 KB up to 16 MB), which is divided into 64 equal segments. — Each segment has an access status and enable bit in the M3IF register definition. — M3IF generates a one cycle DMA_ACCESS for each snooping detection. 16.2 16.2.1 External Signal Description Overview This section discusses input and output signals between the M3IF, masters, and the memory controllers. Table 16-1 summarizes the interface signals, and is followed by a detailed description of signal functions. Interconnect and timing diagrams are included as part of the detailed discussion on controller operation in Section 16.4, “Functional Description.” Detailed M3IF sub-block diagrams are shown in Figure 16-11 and Figure 16-19. Table 16-1. M3IF Signal Properties Name M3IF_HRDATA_M#[63:0] M3IF_HREADY_M# M3IF_HRESP_M# HTRANS[1:0] HPROT HWDATA[31:0] HADDR[31:0] HBURST[2:0] HSIZE[1:0] HWRITE HBSTRB[3:0] HUNALIGN BIGENDIAN DVFS_GRANT MA10_SHARE M3IF_GUARD_2_PCMCIA M3IF_GUARD_2_EIM EIM_PCMCIA_ACTIVE Port O O O O O O O O O O O O O O O O O O Function read data to master access completion strobe to master error response to master transfer state bus to memory controllers protection mode signal to memory controllers write data bus to memory controllers address bus to memory controllers burst size bus to memory controllers data transfer width bus to memory controllers read/write signal to memory controllers byte lane bus to memory controllers unalign signal to memory controllers big/little endian signal (internal) to memory controllers M3IF acknowledge to CCM, indicating that M3IF is ready for frequency changes (DVFS activation) MA10 share indication toward EMI assert high during active ESDCTL/MDDRC/NFC/WEIM request execution assert high during active ESDCTL/MDDRC/NFC/PCMCIA request execution assert high during request/active WEIM/PCMCIA access execution Reset State 0 1 0 0 0 0 0 0 0 0 0 0 system dependent 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-4 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Table 16-1. M3IF Signal Properties (continued) Name CHOSEN_SLAVE[1:0] DMA_ACCESS M3IF_CHOSEN_MASTER[2:0] HCLK HCLK32 M3IF_HADDR_M#1[31:0] M3IF_HWDATA_M#[63:0] M3IF_HBURST_M#[2:0] M3IF_HSIZE_M#[1:0] M3IF_HBSTRB_M#[7:0] M3IF_HTRANS_M#[1:0] M3IF_HWRITE_M# M3IF_HPROT_M# M3IF_HUNALIGN_M# M3IF_HMASTLOCK_M# M3IF_BIGEND_M# HREADY_EIM HREADY_PCMCIA HREADY_NF HRESP_EIM HRESP_PCMCIA HRESP_NF HRDATA_EIM HRDATA_PCMCIA HRDATA_NF RESET EIM_GUARD NF_ACTIVE DVFS_REQ 1Signals Port O O O I I I I I I I I I I I I I I I I I I I I I I I I I I Function num of slave to be activated snooping detected strobe Reflects the current master number that has ownership on the external DATA bus (to/from memories). AHB system clock (up to 133 MHz) 32 KHz clock (use for SDRAM/MDDR refresh) address bus from master write data bus from master burst size bus from master data transfer width bus from master byte lane bus from master transfer state bus from master read/write signal from master protection mode signal from master unalign access signal from master hmasterlock access indication from master big/little endian signal specific/dedicated from each master connected to M3IF MPG EIM controller ready signal PCMCIA controller ready signal NF controller ready signal EIM controller error response signal PCMCIA controller error response signal NF controller error response signal read data bus from EIM controller read data bus from PCMCIA controller read data bus from NF controller reset signal assert high during WEIM write burst access to PSRAM external memory assert high during NFC page fetch CCM request signal to M3IF, indicating CCM frequency change is pending for acknowledge (DVFS algorithm) Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 system dependent 1 1 1 0 0 0 0 0 0 1 0 0 0 names with suffix “_M#”, states for master number. The number of masters in use is system architecture dependent. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-5 Multi-Master Memory Interface (M3IF) 16.3 Memory Map and Register Definition M3IF programming model consists of two classes of registers, M3IF control and lock registers and snooping configuration and status registers as shown in Table 16-2. The control and master lock general register defines the M3IF configurable logic functionality. The configuration and status registers set and monitor snooping activity. All M3IF registers are 32-bits in length with bit fields defined in Figure 16-3 to Figure 16-10. All implemented bits are fully readable and writable in supervisor mode only (an error response will be generated in case of user mode access to M3IF registers). All M3IF (and ESDCTL) registers can be accessed only by a SINGLE word (32-bit) access, through the AHB bus protocol. Accesses of any other size or type will cause an undetermined behavior. All registers can be accessed by only one master at a time. Multi access to M3IF register causes undetermined behavior. The only exception is M3IF Master Lock General register can be accessed by more than one master at a time. The reset state of each bit is shown underneath the bit field name. An asterisk indicates that the value is dependent on the operating mode selected during reset. Details are provided in the following bit field descriptions. 16.3.1 Memory Map M3IF supports four different memory controllers. Each memory controller defines a specific memory address mapped as shown in Table 16-2. Table 16-3 shows the M3IF Memory Space Summary. Table 16-2. M3IF Memory Map Address 0xD800_3000 (M3IFCTL) 0xD800_3028 (M3IFSCFG0) 0xD800_302C (M3IFSCFG1) 0xD800_3030 (M3IFSCFG2) 0xD800_3034 (M3IFSSR0) 0xD800_3038 (M3IFSSR1) 0xD800_3040 (M3IFMLWE0) 0xD800_3044 (M3IFMLWE1) 0xD800_3048 (M3IFMLWE2) 0xD800_304C (M3IFMLWE3) 0xD800_3050 (M3IFMLWE4) 0xD800_3054 (M3IFMLWE5) Register M3IF Control Register M3IF Snooping Configuration Register 0 M3IF Snooping Configuration Register 1 M3IF Snooping Configuration Register 2 M3IF Snooping Status Register 0 M3IF Snooping Status Register 1 M3IF Master Lock WEIM CS0 Register M3IF Master Lock WEIM CS1 Register M3IF Master Lock WEIM CS2 Register M3IF Master Lock WEIM CS3 Register M3IF Master Lock WEIM CS4 Register M3IF Master Lock WEIM CS5 Register Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 16.3.3.1/16-10 16.3.3.2/16-12 16.3.3.3/16-13 16.3.3.3/16-13 16.3.3.4/16-14 16.3.3.4/16-14 16.3.3.5/16-16 16.3.3.5/16-16 16.3.3.5/16-16 16.3.3.5/16-16 16.3.3.5/16-16 16.3.3.5/16-16 Table 16-3. M3IF Memory Space Summary Address Use ESDCTL/MDDRC Memory Space 0xA000_0000–0xAFFF_FFFF CSD0 SDRAM or MDDR memory region (256 Mbyte) READ/WRITE Access MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-6 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Table 16-3. M3IF Memory Space Summary (continued) Address 0xB000_0000–0xBFFF_FFFF Use CSD1 SDRAM or MDDR memory region (256 Mbyte) WEIM Memory Space 0xC000_0000–0xC7FF_FFFF 0xC800_0000–0xCFFF_FFFF 0xD000_0000–0xD1FF_FFFF 0xD200_0000–0xD3FF_FFFF 0xD400_0000–0xD5FF_FFFF 0xD600_0000–0xD7FF_FFFF WEIM CS0 memory region (128 Mbyte) WEIM CS1 memory region (128 Mbyte) WEIM CS2 memory region (32 Mbyte) WEIM CS3 memory region (32 Mbyte) WEIM CS4 memory region (32 Mbyte) WEIM CS5 memory region (32 Mbyte) NFC Memory Space 0xD800_0000–0xD800_0FFF NAND Flash memory region1 (4 Kbyte) PCMCIA Memory Space 0xDC00_0000–0xDFFF_FFFF 1 Can be used as a boot memory region. PCMCIA memory region (64 Mbyte) READ/WRITE READ/WRITE READ/WRITE READ/WRITE READ/WRITE READ/WRITE READ/WRITE READ/WRITE Access READ/WRITE 16.3.2 Register Summary Figure 16-2 shows the key to the register fields and Table 16-4 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0 bit only bit only bit BIT to clear w1c bit BIT N/A Figure 16-2. Key to Register Fields Table 16-4. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-7 Multi-Master Memory Interface (M3IF) Table 16-4. Register Figure Conventions (continued) Convention Description Reset Values 0 1 — u [signal_name] Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. Reset value is determined by polarity of indicated signal. Table 16-5 shows the M3IF register summary. Table 16-5. M3IF Register Summary Name 0xD800_3000 (M3IFCTL) R W R W 0xD800_3028 (M3IFSCFG0) R SWBA W R SWBA W 0xD800_302C (M3IFSCFG1) R SSE0 W R SSE0 W 0xD800_3030 (M3IFSCFG2) R SSE1 W R SSE1 W 0xD800_3034 (M3IFSSR0) R SSS0 W R SSS0 W 0 0 0 0 0 0 SWSZ SE 0 0 0 0 MLSD _EN MLSD MRRP 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-8 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Table 16-5. M3IF Register Summary (continued) Name 0xD800_3038 (M3IFSSR1) R SSS1 W R SSS1 W 0xD800_3040 (M3IFMLWE0) R W R W 0xD800_3048 (M3IFMLWE2) R W R W 0xD800_3048 (M3IFMLWE2) R W R W 0xD800_304C (M3IFMLWE3) R W R W 0xD800_3050 (M3IFMLWE4) R W R W 0 0 0 0 0 0 0 0 0 0 0 0 MLW E4_E N MLWE4 WEM A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MLW E3_E N 0 0 MLWE3 WEM A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MLW E2_E N 0 0 MLWE2 WEM A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MLW E2_E N 0 0 MLWE2 WEM A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MLW E0_E N 0 0 MLWE0 WEM A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-9 Multi-Master Memory Interface (M3IF) Table 16-5. M3IF Register Summary (continued) Name 0xD800_3054 (M3IFMLWE5) R W R W 0 0 0 0 0 0 0 0 0 0 0 0 MLW E5_E N MLWE5 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 WEM A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16.3.3 Register Descriptions This section contains detailed register descriptions for M3IF registers. 16.3.3.1 M3IF Control Register (M3IFCTL) M3IFCTL contains access status, provides access control to SDRAM/MDDR memory devices and arbitration priority for M3IF port masters. The field assignments for this register are shown in Figure 16-3 and the field descriptions are listed in Table 16-6. 0xD800_3000 (M3IFCTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R SDA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 MLSD _EN 0 0 MLSD 0 0 0 0 0 MRRP 0 0 0 0 0 0 0 0 0 Figure 16-3. M3IF Control Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-10 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Table 16-6. M3IF Control Register Field Descriptions Field 31 SDA Description SDRAM/MDDR Memory Active. This is a read-only status bit, that if set, indicates that an active/pending access to SDRAM/MDDR memory exists. The SDA bit will be set on one of the following conditions: • MLSD_EN cleared—Any active/pending access to SDRAM/MDDR memory space will set the bit (until the access is completed). • MLSD_EN is set—Any accesses to SDRAM/MDDR memory space initiated previously to MLSD_EN assertion, will keep the SDA status bit set. The bit will clear after all pending/active accesses execution is completed. Access from master number equal to MLSD field will not assert the status bit. Note: When MLSD_EN is set, any new accesses (initiated after MLSD_EN assertion) to SDRAM/MDDR not from MLSD master will be pending without setting SDA to 1. Only the SDRAM/MDDR memory space region will be lock to the MLSD port. Accesses to M3IF/ESDCTL registers are available to all masters in the system and its system/software responsibility not to access those registers during lock period. 0 No active/pending access to SDRAM/MDDR memory exists. 1 Indicates an active/pending access to SDRAM/MDDR memory exists. Reserved 30–12 11 Master Lock SDRAM/MDDR Access. This bit enables the Master Control SDRAM/MDDR access (MLSD). MLSD_EN The reset value of this bit is “0”. 0 Master Control SDRAM/MDDR access (MLSD) disabled. 1 Master Control SDRAM/MDDR access (MLSD) enabled. 10–8 MLSD Master Lock SDRAM/MDDR Access. This 3-bit field defines the master port number (MPG) that will be the only master in the system that will be served by the SDRAM/MDDR controller. All accesses toward the SDRAM/MDDR from the other masters will be postponed, until the MLSD master will clear MLSD_EN bit. The reset value of the MLSD is “0”. Note: Accesses to ESDCTL registers are not effected by the MLSD field. For example, they can be accessed by any master even if MLSD_EN is set. Prior to lock accesses, the MLSD master should perform the following steps: 1. Set MLSD_EN bit and MLSD field (with the desired value) in the M3IFCTL register. 2. Read M3IFCTL register and check: 3. SDA status bit is cleared (no pending/active access to SDRAM/MDDR memory space exists). 4. MLSD_EN bit is set. 5. MLSD (value) points to the required port number (master port number that requires lock access). 000 Master Port Gasket 0 001 Master Port Gasket 1 010 Master Port Gasket 2 011 Master Port Gasket 3 100 Master Port Gasket 4 101 Master Port Gasket 5 110 Master Port Gasket 6 111 Master Port Gasket 7 7–0 MRRP Master Round Robin Priority. MRRP field is an 8-bit field with one bit per master (bit #i to master #i). Masters with their MRRP bit set are added to a priority arbitration “list” so that together they will have 50% probability to gain access through both M3A and MAB arbitration processes (50% probability for each one of the arbitration separately). Assertion of MRRP bit for an unused master is forbidden. If all MRRP bits are cleared the masters will have equal probability to pass the arbitration processes. For more details about the M3IF arbitration see Section 16.4.3.2, “M3A–Find First 1 (FF1) Algorithm.” 0 The respective master is not on the priority arbitration “list”. 1 Add respective master to priority arbitration “list” with a 50% probability to pass the arbitration processes. 10–8 MLSD MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-11 Multi-Master Memory Interface (M3IF) 16.3.3.2 M3IF Snooping Configuration Register 0 (M3IFSCFG0) M3IFSCFG0 register contains the Snooping window base address, the size of snooping window and the snooping control bit fields which are used by the M3IF to monitor the write access. The Snooping feature is described in detail in Section 16.4.5, “Snooping Logic.” The field assignments for this register are shown in Figure 16-5 and the field descriptions are listed in Table 16-7. 0xD800_3028 (M3IFSCFG0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R SWBA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SWBA W Reset 0 0 0 0 0 0 0 0 0 0 0 SWSZ SE 0 0 0 0 0 0 0 0 0 0 0 Figure 16-5. M3IF Snooping Configuration Register 0 (M3IFSCFG0) Table 16-7. M3IF Snooping Configuration Register 0 Field Descriptions Field 31–11 SWBA 10–5 4–1 SWSZ 0 SE Description Snooping Window Base Address. This field defines the snooping window base address to be monitored by the M3IF. M3IF monitors write accesses to the memory region above the base address window. Reserved Snooping Window Size. This field define the snooping window size as described in Table 16-8. Snooping Enable. This bit enables snooping detection. The M3IF monitors and detects write accesses to the snooping window. 0 Snooping feature is disabled. 1 Snooping feature is enabled. Table 16-8. SWSZ Field Descriptions SWSZ Snooping Window Size Window Base Address Bits [31:11] [31:12] [31:13] [31:14] [31:15] Window Address Bits in Use [10:0] [11:0] [12:0] [13:0] [14:0] 0000 0001 0010 0011 0100 2 KByte 4 KByte 8 KByte 16 KByte 32 KByte MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-12 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Table 16-8. SWSZ Field Descriptions (continued) SWSZ Snooping Window Size Window Base Address Bits [31:16] [31:17] [31:18] [31:19] [31:20] [31:21] [31:22] [31:23] [31:24] — — Window Address Bits in Use [15:0] [16:0] [17:0] [18:0] [19:0] [20:0] [21:0] [22:0] [23:0] — — 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 64 KByte 128 KByte 256 KByte 512 KByte 1 MByte 2 MByte 4 MByte 8 MByte 16 MByte Reserved Reserved 16.3.3.3 M3IF Snooping Configuration Register 1–2 (M3IFSCFG1–2) M3IFSCFG1 register contains enable bits for lower 32 segments [31:0] in M3IFSCFG0 register. M3IFSCFG2 register contains enable bits for upper 32 segments [63:32] in M3IFSCFG0 register. Snooping feature is described in detail in Section 16.4.5, “Snooping Logic.” The field assignments for these register are shown in Figure 16-6 and Figure 16-7 and the field descriptions are listed in Table 16-9. 0xD800_302C (M3IFSCFG1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R SSE0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SSE0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-6. M3IF Snooping Configuration Register 1 (M3IFSCFG1) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-13 Multi-Master Memory Interface (M3IF) 0xD800_3030 (M3IFSCFG2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R SSE1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SSE1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-7. M3IF Snooping Configuration Register 2 (M3IFSCFG2) Table 16-9. M3IF Snooping Configuration Register 1–2 Field Descriptions Field 31–0 SSE0 Description Snooping Segment Enable 0. This register contains the enable bits for the lower 32 segments [31:0] in the snooping window (defined by the M3IFSCFG0 register). If snooping is enabled for segment #x (respective SSE0 bit is high), than any write access detected to that segment will set the DMA_ACCESS for one cycle and the respective snooping status bit will be set. If the SSE0 bit is low, and a write access to the respective segment is detected by the M3IF, only the relevant status bit in the snooping status register will be set but the DMA_ACCESS will not be generated. 0 Snooping segment #x is disabled. 1 Snooping segment #x is enabled. Snooping Segment Enable 1. This register contains the enable bits for the higher 32 segments [63:32] in the snooping window (defined by the M3IFSCFG1 register). If snooping is enabled for segment #x (respective SSE1 bit is high), than any write access detected to that segment will set the DMA_ACCESS for one cycle and the respective snooping status bit will be set. If the SSE1 bit is low, and a write access to the respective segment is detected by the M3IF, only the relevant status bit in the snooping status register will be set but the DMA_ACCESS will not be generated. 0 Snooping segment #x is disabled. 1 Snooping segment #x is enabled. 31–0 SSE1 16.3.3.4 M3IF Snooping Status Register 0–1 (M3IFSSR0–1) M3IFSSR0 register contains the snooping status bits for the lower 32 segments. M3IFSSR1 register contains the snooping status bits for the higher 32 segments.The Snooping feature is described in detail in Section 16.4.5, “Snooping Logic.” The field assignments for these registers are shown in Figure 16-8 and Figure 16-9 and the field descriptions are listed in Table 16-10 and Table 16-11. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-14 Freescale Semiconductor Multi-Master Memory Interface (M3IF) 0xD800_3034 (M3IFSSR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R SSS0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SSS0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-8. M3IF Snooping Status Register 0 (M3IFSSR0) Table 16-10. M3IF Snooping Status Register 0 Field Descriptions Field 31–0 SSS0 Description Snooping Segment Status 0. This register contains the snooping status bits for the lower 32 segments [31:0] in the snooping window (defined by the M3IFSCFG0 register). A bit in the SSS0 register is asserted if snooping to the respective segment occurred. Note: If snooping occurred the status bit will be updated regardless of the respective snooping segment enable bit SSE0[x]. The DMA_ACCESS will be asserted only if the respective snooping segment enable bit SSE0[x] is enabled. 0 Snooping for segment #x did not occur. 1 Snooping for segment #x occurred. 0xD800_3038 (M3IFSSR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R SSS1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SSS1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-9. M3IF Snooping Status Register 1 (M3IFSSR1) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-15 Multi-Master Memory Interface (M3IF) Table 16-11. M3IF Snooping Status Register 1 Field Descriptions Field 31–0 SSS1 Description Snooping Segment Status 1. This register contains the snooping status bits for the higher 32 segments [63:32] in the snooping window (defined by the M3IFSCFG1 register). A bit in the SSS1 register is asserted if snooping to the respective segment occurred. Note: If snooping occurred the status bit will be updated regardless of the respective snooping segment enable bit SSE0[x]. The DMA_ACCESS will be asserted only if the respective snooping segment enable bit SSE1[x] is enabled. 0 Snooping for segment #x did not occur. 1 Snooping for segment #x has occurred. 16.3.3.5 M3IF Master Lock WEIM CSx Register (M3IFMLWEx) The field assignments for this register are shown in Figure 16-10 and the field descriptions are listed in Table 16-12. 0xD800_3040 (M3IFMLWE0) 0xD800_3044 (M3IFMLWE1) 0xD800_3048 (M3IFMLWE2) 0xD800_304C (M3IFMLWE3) 0xD800_3050 (M3IFMLWE4) 0xD800_3054 (M3IFMLWE5) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R WEM Ax W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 MLG E_EN 0 0 MLGE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16-10. M3IF Lock General Register (M3IFMLGE) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-16 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Table 16-12. M3IF Lock General Register Field Descriptions Field 31 WEMAx Description WEIM CSx (0-) Memory Active. This is a read-only status bit, that if set indicates that an active/pending access to a WEIM CSx memory exists. The WEIMx bit is set on one of the following conditions: • MLWEx_EN cleared—Any active/pending access to WEIM CSx memory space will set the bit (until the access is completed). • MLWEx_EN is set—Any accesses to WEIM CSx memory space initiated previously to MLWEx_EN assertion, will keep the WEMAx status bit set. The bit clears after all pending/active accesses execution is completed. Access from master number equal to MLWEx field does not assert the status bit. Note: When MLWEx_EN is set, any new accesses (initiated after MLWEx_EN assertion) to WEIM CSx memories (or to M3IFMLWEx register) not from MLWEx master will be pending without setting WEMAx to 1. Both the M3IFMLWEx register and the WEIM CSx space region will be lock to the MLWEx port. 0 No active/pending access to WEIM CSx memory exists. 1 Indicates an active/pending access to WEIM CSx memory exists. Reserved 30–4 3 Master Lock WEIM CSx Access Enable. This bit enables the Master Lock WEIM CSx access (MLWEx). The MLWEx_EN reset value of this bit is 0. Note: After MLWEx master does not need the lock any more, the master should clear MLWEx_EN bit, so WEIM CSx memory region is open to all masters. 0 Master Lock WEIM CSx access (MLWEx) is disabled. 1 Master Lock WEIM CSx access (MLWEx) is enabled. 2–0 MLWEx Master Lock WEIM CSxl Access. This 3 bits field defines the master port number (MPG) that will be the only one in the system served by the WEIM controller. All accesses to the WEIM CSx memory space from the other masters will be postponed. The reset value of the MLWEx is 0. 1. Prior to lock accesses, the MLGE master should perform the following steps: 2. Set the MLWEx_EN bit and the MLWEx field (with the desired value) in the M3IFMLWEx register. 3. Read M3IFMLWEx register and check: WEMAx status bit is cleared (no pending/active accesses to WEIM CSx memory space exists). MLWEx_EN bit is set. MLWEx (value) points to the required port number (master port number that requires lock accesses). 000 Master Port Gasket 0 001 Master Port Gasket 1 010 Master Port Gasket 2 011 Master Port Gasket 3 100 Master Port Gasket 4 101 Master Port Gasket 5 110 Master Port Gasket 6 111 Master Port Gasket 7 16.4 Functional Description This section provides the functional description for the M3IF module. 16.4.1 Master Port Gasket (MPG) MPG is a flexible port gasket. Up to 8 masters can be connected to the M3IF with any combination of MPG type, which support the following different port types: • MPG—Master port gasket for ARM9 AMBA-AHB lite 32 bits data bus. • MPG64—Master port gasket AMBA-AHB lite 64 bits data bus MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-17 Multi-Master Memory Interface (M3IF) The number and type of ports in use is system dependent, and the unused ports will be unconnected at the system level. Each one of the MPG gaskets communicates with a single master, through one of the (two) defined port interfaces/protocols. 16.4.1.1 Overview of MPG Operation MPG port gasket is used for those system masters that are 32-bit ARM9 AHB lite bus compliant. MPG port gasket appears as another slave to any master it connects to. Table 16-13 lists the access types supported by the MPG. Table 16-13. MPG Supported Burst Accesses M3IF SLAVES HBURST TYPE ESDCTL 32-bit YES YES YES YES YES YES NO NO EIM 32-bit YES YES YES YES YES YES YES YES NFC 16/32-bit YES YES NO YES NO YES NO YES PCMCIA 8/16-bit YES YES YES YES YES YES YES YES 000 001 010 011 100 101 110 111 SINGLE INCR WRAP 4 INCR 4 WRAP 8 INCR 8 WRAP 16 INCR 16 NOTE Unsupported access types will produce undefined behavior but an error response will not be generated. Figure 16-11 shows MPG port interface diagram. The interface is ARM 11 AMBA-AHB lite compliant (does not support RETRY and SPLIT transfers). MPG works with both M3A and MAB, and output AHB_BUS and CONTROL signals to/from M3A (including request to ESDCTL/MDDRC signal and request to non-ESDCTL/MDDRC = general signal). MPG decodes AHB bus inputs and convert them to MAB_CONTROL bus, which includes ADDR, DATA and CONTROL signals (like suspend and abort commands). Once an accesses is initiated by one of the M3IF masters, the access reaches the respective MPG. The MPG asserts the request signal toward the M3A which starts the arbitration process. Once the arbitration is completed and the request can gain access to the bus, the request is accepted by the MPG and the handshake between the MPG and the M3A is completed for that access. If the access was not targeted toward the ESDCTL, the master can start the access (by passing the master AHB bus) toward the respective slave (NFC, EIM). If initiated access is targeted to the ESDCTL after M3A arbitration process is completed, the request is transferred toward the MAB, which arbitrates and schedules the access toward the ESDCTL as a function of ESDCTL state. An internal handshake between the MAB and ESDCTL is used to schedule the new MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-18 Freescale Semiconductor Multi-Master Memory Interface (M3IF) access, and once the handshake is completed, the MAB asserts the request accept signal toward the MPG. All ESDCTL related AHB signals are transferred from the master to the MPG which convert them to an internal protocol between the MPG and the MAB. S#_HWRITE S#_HPROT S#_HSIZE S#_HBURST S#_HADDR S#_HWDATA S#_HMASTER S#_HTRANS S#_HUNALIGN S#_HBSTRB 4 4 2 3 32 32 4 2 MASTER PORT GASKET AHB_BUS(M3A) M3A_CONTROL(M3A) MAB_CONTROL(MAB) M3IF_HREADY_M# M3IF_HRESP0_M# 32 M3IF_HRDATA M#—M3IF Master port number (from 0 to 8) S#—Slave port number MAB—Master Arbitrator and Buffering Figure 16-11. Master Port Gasket (MPG) Interface Diagram MPG also converts MAB or M3A outputs to the AHB standard interface. Table 16-14 presents the signals name in both modules. Table 16-14. MPG MAX Signals AHB Master—Signal Name S#_HWRITE (o) S#_HPROT[3:0] (O) MPG—Signal Name M3IF_HWRITE_M# (I) M3IF_HPROT_M#[3:0] (I) Description HWRITE is HIGH—Indicates a write transfer. HWRITE is LOW—Indicates a read transfer. The protection control signals provide additional information about a bus access. For more information on this signal see Protection discussion in the AHB document. M3IF is using only HPROT[1] signal—user/supervisor access. This signal is used to protect both registers and restricted memory regions. An error response will be generated in case of protection violation, for example, access supervisor registers/memory regions in user mode. Indicates the size of the transfer. 00 8-bits (Byte) 01 16-bits (Half-word) 10 32-bits (Word) 11 Not define for MPG Not used by M3IF. S#_HSIZE[1:0] (O) M3IF_HSIZE_M#[1:0] (I) S#_HMASTER[3:0] (O) not defined MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-19 Multi-Master Memory Interface (M3IF) Table 16-14. MPG MAX Signals (continued) AHB Master—Signal Name S#_HBURST[2:0] (O) MPG—Signal Name M3IF_HBURST_M#[2:0] (I) Description Burst information is provided using HBURST signal, and the 8 possible types are: 000 SINGLE (Single transfer) 001 INCR (Incrementing burst of unspecified length) 010 WRAP4 (4-beat wrapping burst) 011 INCR4 (4-beat incrementing burst) 100 WRAP8 (8-beat wrapping burst) 101 INCR8 (8-beat incrementing burst) 110 WRAP16 (16-beat wrapping burst)1 111 INCR16 (16-beat incrementing burst)1 Indicates the 32 bits memory ADDRESS bus. The write data bus is driven by the master during write transfers (on data phase). If the transfer is extended then the bus master hold the data valid until the transfer completes, as indicated by HREADY HIGH. Each transfer can be classified into one of four different types, as indicated by the HTRANS[1:0] signals: 00 IDLE. Indicates that no data transfer is required. The IDLE transfer type is used when a bus master is granted the bus, but does not wish to perform a data transfer. M3IF will provide a zero wait state OKAY response to IDLE transfers. 01 BUSY. BUSY transfer type allows bus masters to insert IDLE cycles in the middle of bursts of transfers. This transfer type indicates that the bus master is continuing with a burst of transfers, but the next transfer cannot take place immediately. M3IF will provide a zero wait state OKAY response to IDLE transfers. When a master uses the BUSY transfer type the address and control signals reflects the next transfer in the burst. 10 NONSEQ. Indicates the first transfer of a burst or a single transfer. Single transfers on the bus are treated as bursts of one and therefore transfer type is NONSEQUENTIAL. 11 SEQ. The remaining transfers in a burst are SEQUENTIAL and the address and control are related to the previous transfer. In the case of a wrapping burst the address of the transfer wraps at the boundary equal to the size (in bytes) multiplied by the number of beats in the transfer (4,8 or 16). Indicates which byte lanes are valid for each word transfer.2 Signal to indicate an unalign access requiring HBSTRB information.2 Indicates that the current master is performing a locked sequence of transfers. M3IF uses HREADY signal to insert the appropriate number of wait states in to the transfer (the M3IF adds wait states as long as the HREADY in signal is deasserted). The transfer completes with HREADY HIGH (and an OKAY response, which indicates the successful completion of the transfer). One wait state will be added for every cycle that has HREADY diasserted. S#_HADDR[31:0] (O) S#_HWDATA[31:0] (O) M3IF_HADDR_M#[31:0] (I) M3IF_HWDATA_M#[31:0] (I) S#_HTRANS[1:0] (O) M3IF_HTRANS_M#[1:0] (I) S#_HBSTRB[3:0] (O) S#_HUNALIGN (O) S#_HMASTLOCK (O) S#_HREADY (I) M3IF_HBSTRB_M#[3:0] (I) M3IF_HUNALIGN (I) M3IF_HMASTLOCK (I) M3IF_HREADY_M# (O) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-20 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Table 16-14. MPG MAX Signals (continued) AHB Master—Signal Name S#_HRESP0 (I) MPG—Signal Name M3IF_HRESP0_M# (O) Description HRESP0 response is used by M3IF to indicate some form of error condition with the associated transfer. Since M3IF is AHB Lite compliant (AHB SPLIT and RETRY protocols are not supported) means that only one response signal is needed. HREPS0 encoding is: 0 OKAY. When HREADY is HIGH this shows the transfer has completed successfully. OKAY response is also used for any additional cycles that are inserted, with HREADY LOW. 1 ERROR. This (two cycle) response shows an error has occurred. The error condition is signalled to the bus master so it is aware the transfer has been unsuccessful. M3IF response with Error on cases as specified in Section 16.4.1.4, “MPG Transfer Response.” The read data bus is driven by the M3IF during read transfers. If M3IF extends the read transfer by holding HREADY LOW then M3IF will provide valid data at the end of the final cycle of the transfer, as indicated by HREADY HIGH. or PCMCIA. S#_HRDATA[31:0] (I) M3IF_HRDATA[31:0] (O) 1INCR16/WRAP16 are supported only for accesses addressed to the EIM 2HUANLIGN and HBSTRB are supported only by ESDCTL and WEIM. A granted bus master starts an AMBA AHB transfer by driving the address and control signals. These signals provides information on the address, direction and width of the transfer, as well as indication if the transfer forms parts of a burst. Two different forms of burst transfers are allowed: • Incrementing bursts, which do not wrap at address boundaries. • Wrapping bursts, which wrap at particular address boundaries. A write data bus is used to move data from the master to M3IF, while read data bus is used to move data from M3IF to the master. Every transfer consists of: • An address and control cycle (address phase) • One or more cycles for the data (data phase) Since the first address phase cannot be extended (since it will always get HREADY asserted high) M3IF samples all control bus during first address phase, so if the master does not gain access immediately, the address phase information will be saved. The data, however, can be extended by using M3IF_HREADY_MX signal. When LOW this signal causes wait states to be inserted into the transfer and allows extra time for M3IF (ESDCTL/MDDRC or memories) to provide or sample data. In this way, back to back access between different/same slave can be performed and MPG will store all needed bus/signals so that when the master gains access, all the needed bus/signals will be available. During a transfer, M3IF shows the status using only one response signal HRESP0 (since M3IF is only AHB Lite compliant). • 0-OKAY—The OKAY response is used to indicate that the transfer is progressing normally and when M3IF_HREADY_MX goes high this shows the transfer has completed successfully. • 1-ERROR—The ERROR response indicates that a transfer error has occurred and the transfer has been unsuccessful. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-21 Multi-Master Memory Interface (M3IF) 16.4.1.2 MPG Basic Transfer An AMBA AHB transfer consists of two distinct sections: • Address phase. • Data phase that may require several cycles. This is achieved using M3IF_HREADY_MX signal. Figure 16-12 shows the simplest transfer, one data with no wait states. • The AHB lite bus compliant master drives the address and control signals onto the bus after the rising edge of the clock. • M3IF then samples the address and control information in the next rising edge of the clock and access starts (memory is not busy). • After M3IF has sampled the address and control (and derived the appropriate command to the memory) it can start to drive the appropriate response and this is sampled by the bus master on the third rising edge of the clock. Address phase Data phase CLOCK SX_HADDR[31:0] Addr A CONTROL BUS Control A SX_HWDATA[31:0] Data A M3IF_HREADY_MX M3IF_HRDATA[31:0] Data A Figure 16-12. MPG Simple Transfer The address phase of any transfer occurs during the data phase of the previous transfer. This overlapping of address and data is at the pipelined nature of the AHB bus and allows for high performance operation. M3IF may insert wait states into any transfer, as shown in Figure 16-13, which extends the transfer allowing additional time for completion. • For write operations the bus master will hold the data stable throughout the extended cycles. • For read transfer, M3IF does not have to provide valid data until the transfer is about to complete. When a transfer is extended in this way, it will have side effect to extend address phase for the next transfer. This is shown in Figure 16-14, which shows three transfers to unrelated addresses, A, B, and C. • The transfers to addresses A and C are both zero state. • The transfer to address B is one wait state. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-22 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Extending the data phase of the transfer to address B has the effect of extending the address phase of the transfer to address C. Addr phase Data phase CLOCK Addr A SX_HADDR[31:0] CONTROL BUS Control A SX_HWDATA[31:0] Data A M3IF_HREADY_MX Data A M3IF_HRDATA[31:0] Figure 16-13. MPG with Wait States CLOCK SX_HADDR[31:0] Addr A Addr B Addr C CONTROL BUS Control A Control B Control C SX_HWDATA[31:0] Data A Data B Data C M3IF_HREADY_MX M3IF_HRDATA[31:0] Data A Data B Data C Figure 16-14. MPG Multiple Transfers 16.4.1.3 MPG Transfer Type Every transfer can be classified into one of four different types, as indicated by SX_HTRANS[1:0] signals as described in Table 16-14. Figure 16-15 shows a number of different transfer types being used. • The first transfer is the start of a burst and therefore is NON-SEQUENTIAL. • The master is unable to perform the second transfer of the burst immediately and therefore the master uses BUSY transfer to delay the start of the next transfer (after M3IF sees BUSY with HREADY high it continues to give HREADY high until HTRANS bus changes from BUSY and MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-23 Multi-Master Memory Interface (M3IF) • • then HREADY will act as usual). In this example the master requires only one cycle before it is ready to start the next transfer in the burst, which completes with no wait states. The master performs the third transfer of the burst immediately, but this time the M3IF is unable to complete and uses M3IF_HREADY_MX to insert a single wait state. The final transfer of the burst completes with zero wait states. CLOCK SX_HTRANS[1:0] NONSEQ BUSY SEQ SEQ SEQ SX_HADDR[31:0] 0x20 0x24 0x24 0x28 0x2C SX_HBURST[2:0] INC SX_HWDATA[31:0] D 20 D 24 D 28 D 2C M3IF_HREADY_MX M3IF_HRDATA[31:0] D 20 D 24 D 28 D 2C Figure 16-15. MPG—Transfer Type Examples 16.4.1.4 MPG Transfer Response Whenever M3IF is accessed it provides a response which indicates the status of the transfer. The M3IF_HREADY_MX signal is used to extend the transfer and this works in combination with the response signals, M3IF_HRESP_MX, which provide the status of the transfer. M3IF can complete the transfer in a number of ways: • Complete the transfer immediately. • Insert one or more wait states to allow time to complete the transfer. • Signal error to indicate that the transfer has failed. The M3IF_HREADY_MX signal is used to extend the data portion/phase of a transfer. When LOW the M3IF_HREADY_MX indicates the transfer is to be extended and when HIGH indicates that data transfer had completed. Both M3IF_HREADY_MX and M3IF_HRESP0 encoding is described in Figure 16-12. It should be noted that M3IF does not support AMBA AHB, SPLIT and RETRY transfer response. A transfer will complete successfully (as defined by the AHB bus protocol) with M3IF_HREADY_MX HIGH and an OKAY response (M3IF_HRESP[1] LOW). A transfer will complete unsuccessfully (ERROR response) with two consecutive cycles of M3IF_HRESP[1] HIGH, while during the first cycle M3IF_HREADY_MX is LOW and during the second cycle M3IF_HREADY_MX is HIGH (as defined by the AHB bus protocol). The ERROR response is used by the M3IF to indicate one of the following error types (which can be associated with the transfer): MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-24 Freescale Semiconductor Multi-Master Memory Interface (M3IF) • • • • • Master is trying to access a disabled CSD in the ESDCTL/MDDRC system register. Master in user mode is trying to access a CSD that is configured to SUPERVISOR access only. System gave software reset command to ESDCTL/MDDRC while access to ESDCTL/MDDRC is in progress. Error response coming from all other memory controllers (except ESDCTL/MDDRC). Access to ESDCTL registers during an active access to SDRAM memory. NOTE M3IF controls/handles ESDCTL error response logic, and only transfer the error response signal from all other memory controllers (PCMCIA, NFC, and WEIM). For more details regarding the error response generation from other memory controllers, consult the respective memory controller chapter available in the respective system architecture. If an error response is generated by the MPG on the beginning of an access, the access will not be executed and none of the data that is supposed to be read/write will get transferred; however, if the error response has been given after few data transfers (in a burst access), the status of the first data transfer before the error response, for write access, is unknown (data maybe written or not) and the master should treat the data of the whole access as unknown data. In the case that this access was a read access the data that has been transferred until the error response is valid data and master can use it. If an error occurs during a burst access, the M3IF will generate an (AHB) error response for all remaining beats from the burst. 16.4.1.5 MPG Burst Operation Four, eight and sixteen-beat bursts are defined in the AMBA AHB protocol, as well as incremental undefined length bursts and single transfers. Both incrementing and wrapping bursts are supported in the protocol. A detailed description of the supported access type by the MPG is shown at Table 16-13. Burst information is provided using SX_HBURST[2:0] signal and the eight possible types are defined in Figure 16-12. It is acceptable to perform single transfers using an unspecified length incrementing burst which only has a burst length of one. The burst size indicates the number of beats in the burst, not the number of bytes transferred. The total amount of data transferred in a burst is calculated by multiplying the number of beats by the amount of data in each beat, as indicated by SX_HSIZE[1:0]. SX_HSIZE[1:0] encoding is shown in Figure 16-12. The size is used in conjunction with the SX_HBURST[2:0] signals to determine the address boundary for wrapping bursts. All transfers within a burst must be aligned to the address boundary equal to the size of the transfer (that must be a word as mentioned). For example, word transfers must be aligned to word address boundaries (that is A[1:0]=00). If an unalign access is being perform HUNALIGN signal must be asserted high and the respective HBSTRB bus must be given by the master. NOTE Unaligned burst crossing bus width boundary is supported only if eventual number of transfers on the bus is not higher than the value implied by HBURST. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-25 Multi-Master Memory Interface (M3IF) Four beat wrapping and incrementing burst are shown in Figure 16-16 and Figure 16-17, respectively. CLOCK SX_HTRANS[1:0] SX_HADDR[31:0] SX_HBURST[2:0] CONTROL SX_HWDATA[31:0] M3IF_HREADY_MX M3IF_HRDATA[31:0] D 38 D 3C D 30 D 34 NONSEQ 0x38 SEQ 0x3C WRAP 4 Control for burst, SIZE = Word D 38 D 3C D 30 D 34 SEQ 0x30 SEQ 0x34 Figure 16-16. MPG Four Beat Wrapping Burst CLOCK SX_HTRANS[1:0] SX_HADDR[31:0] SX_HBURST[2:0] CONTROL SX_HWDATA[31:0] M3IF_HREADY_MX M3IF_HRDATA[31:0] D 38 D 3C D 40 D 44 NONSEQ 0x38 SEQ 0x3C INCR 4 Control for burst, SIZE = Word D 38 D 3C D 40 D 44 SEQ 0x40 SEQ 0x44 Figure 16-17. MPG Four Beat Incrementing Burst 16.4.1.6 MPG Early Burst Termination M3IF can determine when a burst has terminated early by monitoring the SX_HTRANS[1:0] signals and ensuring that after the start of the burst every transfer is labelled as SEQUENTIAL or BUSY. If a NON-SEQUENTIAL transfer occurs in middle of a burst it indicates that a new burst has started and therefore the previous one must be terminated immediately. If an IDLE transfer occurs in middle of a burst, it indicates the burst should be terminated immediately. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-26 Freescale Semiconductor Multi-Master Memory Interface (M3IF) If a master cannot complete a burst because it loses ownership of the bus (for example, MAX slave port SX_HTRANS[1:0] is IDLE during a burst access due to MAX internal arbitration logic, means that the served MAX master port loses ownership of the bus) then it must rebuild the burst appropriately when it re-gains access to the bus. For example, if a master has only completed one beat of a four-beat burst then it must use an undefined-length burst to perform the remaining three transfers. Figure 16-18 shows incrementing bursts of undefined length that starts after aborting previous INCR 4 burst access. CLOCK SX_HTRANS[1:0] NONSEQ SEQ NONSEQ SEQ SEQ SX_HADDR[31:0] 0x20 0x22 0x5C 0x60 0x64 SX_HBURST[2:0] INCR 4 INCR CONTROL SIZE = Word SIZE = Word SX_HWDATA[31:0] D 20 D 22 D 5C D 60 D 64 M3IF_HREADY_MX M3IF_HRDATA[31:0] D 20 D 22 D 5C D 60 D 64 Figure 16-18. MPG Undefined Length Bursts NOTE To perform burst access length not equal to 4 or 8 words, it is possible to start INCR access of undefined length and to abort it after the desired words, or to start 4/8 burst length access and to abort it after the desired word., Both ways are supported by the M3IF and it is the master’s decision which way to choose. 16.4.1.7 Multi-Endianness M3IF supports multi-endianness, an example of this is there is an endian signal input to each one of the MPGs. The endianness signal from each master should be static after reset, means that all accesses from each master will have the same endianness type. If in a given system, there are masters connected to the M3IF that does not drive endian signal (means they support only one endian type, big or little) the respective MPGs big end signal should be static, meaning connected to 0 or 1 (depends on the endianness supported by the master connected to it). M3IF does NOT support shared external memory area for masters with different endianness mode. This feature should be handled by software or other additional hardware in the system. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-27 Multi-Master Memory Interface (M3IF) 16.4.2 16.4.2.1 Master Port Gasket 64 (MPG64) Overview MPG64 port gasket is used for those system masters that have 64 bits data bus.Table 16-15 presents the access types supported by the MPG. Figure 16-19 shows the MPG64 port interface diagram. MPG64 does not support RETRY and SPLIT transfers. Table 16-15. MPG64 Supported Burst Accesses M3IF slaves HBURST TYPE ESDCTL 32 Bit 000 001 010 011 100 101 110 111 SINGLE INCR WRAP 4 INCR 4 WRAP 8 INCR 8 WRAP 16 INCR 16 YES YES YES YES YES YES NO NO 64 Bit YES YES YES YES NO YES NO NO 32 Bit YES3 YES YES YES YES YES YES YES EIM 64 Bit YES YES YES YES NO YES NO NO NFC 16/32 Bit YES YES NO YES NO YES NO YES 64 Bit YES YES NO YES NO YES NO NO PCMCIA 8/16 Bit YES YES YES YES YES YES YES YES 64 Bit NO NO NO NO NO NO NO NO 1. NFC does not support accesses of 8 bit data width. 2. PCMCIA does not support accesses of 32 or 64 bit data width. 3. M3IF MPG64 supports only double word (64 bits) or word (32 bits) size bursts. Since SINGLE access is not a burst type access, byte (8 bits) or half word (16 bits) is supported as well. For MPG64 brief overview description, see Section 16.4.1.1, “Overview of MPG Operation.” Table 16-17 only shows the buses that have different widths, all other signals are the same as described in Table 16-15. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-28 Freescale Semiconductor Multi-Master Memory Interface (M3IF) S#_HWRITE(L2C) S#_HPROT(L2C) S#_HSIZE(L2C) S#_HBURST(L2C) S#_HADDR(L2C) S#_HWDATA(L2C) S#_HMASTER(L2C) S#_HTRANS(L2C) S#_HUNALIGN(L2C) S#_HBSTRB(L2C) MAB_CONTROL(MAB) 8 4 2 3 32 64 4 2 MASTER PORT GASKET 64 M3A_CONTROL(M3A) AHB_BUS(M3A) M3IF_HREADY_M#(MAX) M3IF_HRESP0_M#(MAX) 64 M3IF_HRDATA(MAX) L2C—Layer 2 Cache MAB—Master Arbitrator and Buffering S#—L2C port number M#—M3IF Master port number (from 0 to 8) Figure 16-19. MPG64 Port Interface Diagram Table 16-17. MPG64 Additional Signals 64-Bit Master—Signal Name S#_HBSTRB[7:0] (O) S#_HWDATA[63:0] (o) S#_HSIZE[1:0] (O) MPG64—Signal Name M3IF_HBSTRB_M#[7:0] (I) M3IF_HWDATA_M#[63:0] (I) M3IF_HSIZE_M#[1:0] (I) Description Indicates which byte lanes are valid (each bit for each byte)—extended to 8 bits. The write data bus extended to 64 bit width Indicates the size of the transfer 00 8 bits (Byte) 01 16 bits (Halfword) 10 32 bits (Word) 11 64 bits (Double-Word) (defined only for MPG64) Burst information is provided using HBURST signal, and the 8 possible types are; 000 SINGLE (Single transfer) 001 INCR (Incrementing burst of unspecified length) 010 WRAP4 (4-beat wrapping burst) 011 INCR4 (4-beat incrementing burst) 100 WRAP8 (8-beat wrapping burst) 101 INCR8 (8-beat incrementing burst) 110 WRAP16 (16-beat wrapping burst) 111 INCR16 (16-beat incrementing burst) The read data bus extended to 64 bit width S#_HBURST[2:0] (O) M3IF_HBURST_M#[2:0] (I) S#_HRDATA[63:0] (I) M3IF_HRDATA_M#[63:0] (O) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-29 Multi-Master Memory Interface (M3IF) 16.4.2.2 MPG64 Basic Transfer All Basic transfer for 32 bits access are perform as AMBA-AHB usual access as described in 16.4.1.2, “MPG Basic Transfer.” All 64 bits access are performed differently. Since the output data port is 32 bits wide, each 64 bit (double word) access is translated into 2 separated access, so a single read/write access of 64 bits is translated by the MPG64 into two single read/write 32 bits access. Burst length of 4 double words is being translated into 8 words (32 bits) burst length and 8 double words burst length is translated into 2 bursts of 8 words (32 bits) length. For 32 bit MDDR there is no need for the MPG64 gasket to translate the access since 64 bits can be transferred by the MDDR each cycle. Figure 16-20 shows the simplest transfer of a single double word, one data with two wait states (one cycle translation and one cycle per two single access of 32 bits access should be perform). • The master drives the address and control signals onto the bus after the rising edge of the clock. • M3IF then samples the address and control information and translate it to 2 separated single access of 32 bits. • First and then second access is performed on the SDRAM. • Each single access is treated as described in Section 16.4.1.2, “MPG Basic Transfer.” • The response that the 64 bit master sees is similar to AMBA-AHB response. Figure 16-20. MPG64 Simple Double Word Transfer CLOCK SX_HADDRS[31:0] INTERNAL_HADDRS CONTROL BUS INTERNAL CONTROL SX_HWDATA[63:0] INTERNAL_HWDATA[31:0] M3IF_HREADY_MX INTERNAL_HREADY M3IF_HRDATA[63:0] INTERNAL_HRDATA[31:0] D A[31:0] Data A D A[63:32] Control A Control A1 Data A D A[31:0] D A[63:32] Control A2 Addr A Addr A Addr A+4 16.4.2.3 MPG64 Transfer Type See Section 16.4.1.3, “MPG Transfer Type.” MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-30 Freescale Semiconductor Multi-Master Memory Interface (M3IF) 16.4.2.4 Mpg64 Transfer Response See Section 16.4.1.4, “MPG Transfer Response.” 16.4.2.5 MPG64 Burst Operation There are few things different than what is described in Section 16.4.1.5, “MPG Burst Operation.” The size of each beat can be either 8, 16, 32 or 64-bits (byte/half word/word/double word), as shown in Table 16-15. If a burst access of double word is issued, WRAP8, INCR16 and WRAP16 are not supported by the M3IF. Eight beat incremental burst of double word beat size is translated into 2 burst of 8 words length each, as shown in Figure 16-21 (for 32 bit MDDR there is no need for the MPG64 gasket to translate the access). CLOCK SX_HTRANS[1:0] INTERNAL HTRANS[1:0] SX_HADDR[31:0] INTERNAL_HADDR[31:0] SX_HBURST[2:0] CONTROL SX_HWDATA[63:0] M3IF_HREADY_MX INTERNAL HREADY M3IF_HRDATA[63:0] D 38 D 40 D 48 D 50 D 58 NONSEQ IDLE 0x38 0x38 NON SEQ SEQ 0x40 0x3C 0x40 SEQ SEQ SEQ SEQ SEQ SEQ SEQ SEQ SEQ NON SEQ SEQ SEQ 0x48 0x44 0x48 0x50 0x4C 0x50 0x58 0x58 0x60 0x60 0x54 0x5C INCR 8 Control for burst, SIZE = double Word D 38 D 40 D 48 D 50 D 58 Figure 16-21. MPG64—8 Beat Incremental Burst of Double Words to 32-bit SDRAM 16.4.2.6 MPG64 Early Burst Termination See Section 16.4.1.6, “MPG Early Burst Termination.” 16.4.2.7 Multi Endianness See Section 16.4.1.7, “Multi-Endianness.” MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-31 Multi-Master Memory Interface (M3IF) 16.4.3 16.4.3.1 M3IF Arbitration (M3A) Overview M3A is a programmable arbiter. All incoming requests from the different masters are on hold until access is granted by the arbiter. The arbitration is performed by a round robin algorithm which grants the access to the master that holds the token. In the case that a master holds the token but does not request access (to one of the M3IF slaves), the bus is granted to the nearest requesting master with a higher round robin number. The internal signal bus free indicates the FF1 algorithm to choose a new master. The bus_free signal is asserted high by the M3A by monitoring HTRANS bus of the active master (the master that grants access). As soon as the M3A notices that the access has been accomplished (HTRANS equal to NONSEQ or IDLE with HREADY asserted high) it allows to a new master to gain access according to the round robin value. When a new master gain an access the M3A will transfer the AHB bus coming from this master to all memory controllers with an hsel signal to the specific memory controller, (all other will get low hsel). Because MAB can get multiple access to the ESDCTL and pass accesses to the ESDCTL according to internal handshake between the ESDCTL and the MAB, the M3A will allow multiple access to pass to the MAB without waiting for previous accesses to be completed. The M3A will pass the request to the MAB if the access is to the ESDCTL, and will pass a new access to the MAB (before the previous/active master access is completed) if the master with the token is accessing the ESDCTL If the request is for a different memory controller the M3A will hold the access until all pending transfers in the MAB (ESDCTL accesses) are finished. In this case (multiple access to MAB are in progress) the bus_free signal will assert high when the MAB completes all incoming requests. There two different access paths: 1. Access request to SDRAM/MDDR—involves ESDCTL/MDDRC memory controller. The access path is as follows: a) Master #x initiates access to SDRAM/MDDR memory —> M#_ESDCTL_REQ signal is high. b) M3A arbitrates master request. c) After successful arbitration M3A passes the request to MAB (by MASTER_REQ_EN signal set to 1). d) MAB and the respective MPG (the one that initiated the access) are handling the access directly from/to the ESDCTL/MDDRC (M3A is not involved). e) All data transfer is accomplished by the ESDCTL/MDDRC and the SDRAM/MDDR external memory. 2. Access request not to SDRAM/MDDR memory—involves the respective memory controller. The access path is as follows: a) Master #x initiates access not to SDRAM/MDDR memory —> M#_GENERAL_REQ signal is high. b) M3A arbitrates master request. c) After successful arbitration M3A passes the AHB bus (address, data, control signals) of the respective master to the relevant memory controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-32 Freescale Semiconductor Multi-Master Memory Interface (M3IF) d) M3A and the respective MPG (the one that initiated the access) are handling the access from/to the relevant memory controller (MAB is not involved). e) All data transfer is accomplished by the relevant memory controller and the external memory. M1_AHB_BUS MASTER M1_GENERAL_REQ PORT GASKET M1_ESDCTL_REQ #1 1 0 AHB MUX AHB_BUS(SLAVES) MASTER_REQ_EN(MAB) n REQUEST LOGIC ... BUS FREE LOGIC ROUND ROBIN SCHEME (FF1) CHOOSEN_SLAVE M#_ESDCTL_REQ MASTER M#_GENERAL_REQ PORT GASKET M#_AHB_BUS #n Figure 16-22. M3A Block Diagram NOTE Although AHB bus indicates only one direction, the round robin scheme DEMUX the AHB response signals (hready, hresp, and hrdata) from all slaves (except from ESDCTL that goes directly to the MPG). Figure 16-23 illustrates a simple transfer (all previous accesses are completed, and there are no other pending requests) between one of the M3IF masters and the EIM module. There is one cycle penalty at the beginning of the access. The MPG samples the access relevant signals and de-asserts HREADY signal toward the master, until the target slave confirms the access (EIM_HREADY high with EIM_NONSEQ cycle). After the target slave (EIM in this example) confirms the request (HREADY high with EIM_NONSEQ cycle) the access traffic (control and data) is direct between the master and the target slave (EIM). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-33 M3IF REGISTERS Multi-Master Memory Interface (M3IF) CLOCK SX_HTRANS[1:0] SX_HADDR[31:0] SX_CONTROL SX_HWDATA[31:0] M3IF_HREADY_MX M3IF_HRDATA[31:0] D 38 D 3C D 30 D 34 NONSEQ 0x38 SEQ 0x3C Control for burst, SIZE = Word D 38 D 3C D 40 D 44 SEQ 0x30 SEQ 0x34 EIM_HTRANS[1:0] EIM_HADDR[31:0] EIM_CONTROL EIM_HWDATA[31:0] EIM_HREADY EIM_HRDATA[31:0] IDLE NONSEQ 0x38 SEQ 0x3C SEQ 0x30 SEQ 0x34 Control for burst, SIZE = Word D 38 D 3C D 40 D 44 D 38 D 3C D 40 D 44 Figure 16-23. M3A Simple Transfer Timing Diagram 16.4.3.2 M3A–Find First 1 (FF1) Algorithm Arbitration between the various requests is done by Find First 1 algorithm based on round robin algorithm (see Figure 16-24). If two or more masters request access to the M3IF the master with the token, or the master that will be the first to receive the token (in case the master with the token does not request access) will gain control over the AHB bus or will enable his request signal to the MAB. For example, if masters 0, 1, and 6 requesting access at the same time and the token is at master 2, then master 6 will gain control over the AHB bus or his request signal to the MAB will be enabled, since it will be the first to receive the token (this is done to reduce arbitration time, in this example 4 clock cycles are saved). The Round Robin pointer increase its value in two cases, if the master with the token does not request access or if the master with the token requests access and gains the AHB bus/enable request—on the cycle that the master gains the AHB bus/enable request the Round Robin pointer will increase its value. If a master requests an access and has the token but does not gain access because no new access can pass on, the Round Robin will not increase until the master gains the AHB bus/enable request. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-34 Freescale Semiconductor Multi-Master Memory Interface (M3IF) With each clock cycle the “token” can shift between the masters if one of the conditions come true. Master 0 Master 0 Master 1 Master 2 Master n-1 Master n Since bus_free signal is low no new master can gain access. and Round Robin does not change its value since Master #0 is requesting access. Round Robin parks on master #0 until he gains access to the bus. After previous access execution completes, bus_free signal is high, so Master #0 will gain access to the bus and the round robin will change its value. bus_free is low, means an access is in progress. Figure 16-24. M3A—Round Robin Token Chain—Equal Priority There is an option to program the Round Robin to work with different priority using MRRP field of the M3IF control register. When the MRRP equal to 0 no priority is given to any master so the probability to gain access is equal for each one of the masters. If one or more bits of the MRRP are set to 1, the priority changes, and all master with their bit set to 1, will get together 50% priority of gaining access. For example, if both master 1 and master 4 bits set to 1 in the MRRP field, the priority to gain access of master 1 and 4 together will be 50%. If only one bit is set the respective master (that his bit is set) will alone have 50% priority to gain access. NOTE By default (after reset) all MRRP bits are cleared, means that all M3IF masters have the same priority. The 50% priority refers only to Round Robin mechanism. If a non priority master (MRRP respective bit is not set) with the token is already waiting to gain the bus the new coming request from the priority master (MRRP respective bit is set) will not gain access before the previous master request is completed. Additionally, priority master cannot and will not terminate an on going access of any other masters. Figure 16-25 shows Round Robin chain in case that MRRP configured to 8’b00010010–master 1 and 4 set to 1. Master 0 Master 1 Master 2 Master 4 Master 3 Master 1 Master 5 Master 4 Master n Master 1/4 Master 1 and 4 together has the probability of 50% to gain access. Figure 16-25. M3A—Round Robin Token Chain—Masters 1 and 4 has 50% Priority MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-35 Multi-Master Memory Interface (M3IF) 16.4.3.3 Bus_free Signal Algorithm When the bus_free signal asserts high, it indicates the new master can gain access. The bus_free asserts high in the following cases: • When the previous access was a NON ESDCTL access and the HTRANS bus of the previous master that gained the access was equal to NON SEQUENTIAL or IDLE and HREADY asserted high. • When the previous access was an ESDCTL access and the new master that gained access was also an ESDCTL access. • When the previous access or accesses were ESDCTL accesses and all previous accesses finished. NOTE To avoid contention between the memory controllers/memories, there is a special signal coming from the MPG and from the MAB to the M3A and going to the bus_free algorithm indicating which kind of slave is still using shared I/O pins so no new access to a different memory begins. 16.4.4 16.4.4.1 Master Arbitration and Buffering (MAB) Overview of MAB Operation MAB arbiter uses the same programmable arbiter as the M3A (Section 16.4.3.2, “M3A–Find First 1 (FF1) Algorithm”). All incoming requests from the different masters are put on hold until access is granted by the arbiter. The MAB communicates with the ESDCTL and grants access at the earliest possible time, for example when the ESDCTL is ready to handle a new memory request. Each time ESDCTL can get a new access, the new access is sampled into the CONTROL and DATA buffers so ESDCTL receives stable inputs during the time the access is in progress. The DATA buffer is sampled according to ESDCTL write acknowledge response. Figure 16-26 shows MAB operation block diagram. 16.4.4.2 M3B–Find First 1 (FF1) Algorithm This operation of the arbiter algorithm is identical to the M3A arbiter algorithm described in Section 16.4.3.2, “M3A–Find First 1 (FF1) Algorithm.” Each time NEW_ACCESS goes HIGH it indicates that the ESDCTL is ready to handle a new memory request, meaning that the previous request is either completed or controlled by the SDRAM memory. During the same cycle the memory port is granted to the master with the token. Figure 16-27 shows the arbitration process for 4 master requests. At the first clock cycle masters M0, M1, and M2 simultaneously request the memory port. At the rising edge of the clock (while NEW_ACCESS is HIGH) master M0 has the token, so the memory port is controlled by M0 (see MASTER_CONTROL signals). During that time all M3IF_HREADY_M# signals are low, besides M3IF_HREADY_M3 which was the previous served master. The same arbitration process occurs for the following requests. Master M1 has the token and grant access to the ESDCTL (see MASTER_CONTROL). HREADY of master M0 asserted high and accomplished the previous access. After several cycles M0 assert the REQUEST signal again due to a new access. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-36 Freescale Semiconductor Multi-Master Memory Interface (M3IF) M3IF REGISTERS M1_ADDR and CONTROL M1_WDATA M1_RESPONSE(MPG) MASTER ARBITRATION and BUFFERING Round Robin Scheme (FF1) MASTER PORT GASKET #1 ADDR/CTRL MUX 0 FIFO BUFFER M2_ADDR and CONTROL MASTER PORT GASKET #2 M2_WDATA M2_RESPONSE(MPG) SELECT 1 n M1_REQUEST ... M2_REQUEST M#_REQUEST 0 1 DECODE CONTROL RESP ESDCTL M3A N WDATA MUX WDATA 0 1 N RBUFFER RDATA 16-37 M#_ADDR and CONTROL MASTER PORT GASKET #N M#_WDATA M#_RESPONSE(MPG) RDATA (shared bus to all MPGs) Figure 16-26. MAB Overview Block Diagram Once a master has control over the port, the other requests remain on hold, meaning that their M3IF_HREADY_M# is LOW. The current master has control over the memory port until it completes the requested transfer. The new master gaining access to the memory port is the master with the new token. The MAB ADDR/CTRL MUX and WDATA MUX connect (using the round robin algorithm) the selected master and when NEW_ACCESS arrives the MUX output is sampled by the MAB so that a stable bus is provided to ESDCTL. After a new access is detected by the ESDCTL, data transfer between the memory and the masters can start. In order for the MAB to serve more than one master at a time, a cyclic 4 entry FIFO with two pointers (read/write) is used. The FIFO read pointer is used (by the Decode block) as the selector for the memory RESPONSE signals and for the WDATA MUX, while the FIFO write pointer is used to add a new master to the FIFO entries. (since ESDCTL hides latency a new access can start before previous access ended. This why this MUX control should work separately for information to the ESDCTL and ESDCTL response. Figure 16-27 shows the MAB arbitration process timing diagram. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor WBUFFER SDRAM BUS Multi-Master Memory Interface (M3IF) CLOCK ROUND_ROBIN REQUEST_M0 REQUEST_M1 REQUEST_M2 REQUEST_M3 NEW_ACCESS MASTER_CONTROL M3IF_HREADY_M0 M3IF_HREADY_M1 M3IF_HREADY_M2 M3IF_HREADY_M3 M3 M0 M1 M2 0 0 1 1 1 2 2 3 3 3 Figure 16-27. MAB Arbitration Process Timing Diagram Figure 16-28 shows a detailed multi master memory request time diagram. The diagram shows two masters presenting memory request (AMBA AHB) signals and their conversion by the MPG and MAB to the ESDCTL. The HRDATA timing is also shown with the respective M3IF_HREADY_M# signal. The HRDATA bus from the memory (during READ transfers) is shared with all present masters (except 64-bit masters that become a 64-bit bus after decoding by MPG64) while the arbitration is completed by the use of the M3IF_HREADY_M# signals at the master level. 16.4.4.3 M3IF Operation During HMASTLOCK Accesses If a HMASTLOCK access to any memory controller (memory space) is initiated by one of the M3IF masters, the request need to pass the arbitration like a regular access. After the access passes the arbitration it “locks” the arbitration and all other accesses (regardless to memory space destination) will remain pending until the HAMSTLOCK signal (from the master that initiated the HMASTLOCK access) de-asserts. While the HMASTLOCK is high all accesses initiated by the locking master will be executed without arbitration, while all other masters accesses will remain pending. NOTE During HMASTLOCK high, the locking master is NOT ALLOWED to change the memory space destination, from SDR/DDR SDRAM space to non SDR/DDR SDRAM, or vice versa. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-38 Freescale Semiconductor Multi-Master Memory Interface (M3IF) CLOCK ROUND_ROBIN 1 2 3 0 1 1 1 2 3 0 0 REQUEST_M0 REQUEST_M1 NEW_ACCESS S0_HADDR[31:0] A20 A24 A28 A2C A40 S0_HBURST Burst size = 4 Burst size = 8 S0_HWRITE S1_HADDR[31:0] A10 S1_HBURST Burst size = 0, Single Access S1_HWRITE MASTER_CONTROL M0 M1 MAB_ADDR[31:0] A20 A10 MAB_BURST Burst size = 4 Burst size = 0 MAB_RW M3IF_HREADY_M0 M3IF_HREADY_M1 M3IF_HRDATA[31:0] D20 D24 D28 D2C D10 Figure 16-28. MAB Multi-Master Request Time Diagram 16.4.5 Snooping Logic M3IF snooping feature (used by the Image Processor Unit, IPU), monitors and detects write accesses to a configurable window (snooping window) in one of the memory regions mapped by the M3IF. The snooping window base address, memory region, and window size are configurable parameters through the M3IFSCFG0 register (register details at Section 16.3.3.2, “M3IF Snooping Configuration Register 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-39 Multi-Master Memory Interface (M3IF) (M3IFSCFG0)”). Snooping window is further divided into 64 equally sized segments. A detected write access to the snooping window results in: • The respective segment status bit in M3IFSSR0 and/or M3IFSSR1 registers is set. • DMA_ACCESS strobe is asserted for 1 clock cycle if the snooping segment enable bit is set for the snooped segment. The snooping segment enable bit is configured via 2 snooping configuration registers, M3IFSCFG1 and M3IFSCFG2. It is the software’s responsibility to clear the snooped segment status bits, but the snooped segment status bit will be set for each snooping detection regardless of its value. 16.5 16.5.1 Initialization/Application Information M3IF in a System This section provides an example of M3IF initialization, integration and configuration in a given system. The system requirements are listed below: • Several masters with external memories access capabilities. — Several masters access the M3IF via AP MAX crossbar switch. — ARM I-Cache—32-bit data bus — ARM D-Cache—32-bit data bus • The system uses 2 SDRAM memory devices (32 bits), a 32-bit Flash (via WEIM CS0) and one SRAM (via WEIM CS1). Figure 16-29 presents M3IF integration in the system. All the above masters are connected to the M3IF through ports. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-40 Freescale Semiconductor Multi-Master Memory Interface (M3IF) Multi Master Memory Interface (M3IF) M3IF REGISTERS CSD0 SDRAM LCDC MPG64 ESDCTL SNOOPING LOGIC SDRAM CSD1 FCE #0 MPG64 ARM Platform FLASH DMA A/P MAX RTIC #3 MPG WEIM CONTROLLER CS0 SRAM CS1 H264 #4 MPG64 VIA EMI AND IO MUXES Figure 16-29. M3IF System Example MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 16-41 Multi-Master Memory Interface (M3IF) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 16-42 Freescale Semiconductor Chapter 17 Wireless External Interface Module (WEIM) The Wireless External Interface Module (WEIM) handles interface to devices external to the chip, including generation of chip selects, clock and control for external peripherals and memory. It provides asynchronous and synchronous access to devices with SRAM-like interface. Figure 17-1 shows a top-level WEIM block diagram. All block signals are shown in Table 17-1 and described in Table 17-2. 17.1 • • • • • • • • • • • • Features Six Chip Selects for external devices, with CS0 and CS1 each covering a range of 128 Mbytes, and CS2–CS5, each covering a range of 32 Mbytes CS0 range can be increased to 256 Mbytes when collapsed with CS1 Selectable Protection for each Chip Select Programmable Data Port Size for each Chip Select Asynchronous accesses with programmable setup and hold times for control signals Synchronous Memory Burst Read Mode support for AMD, Intel, and Micron burst flash memory Synchronous Memory Burst Write Mode support for PSRAM (CellularRAMTM from Micron, Infineon, and Cypress) Support for multiplexed address/data bus operation External cycle termination/postpone with DTACK signal Programmable Wait-State generator for each Chip Select Support for Big Endian and Little Endian modes of operation per access ARM AHB slave interface 17.2 Overview WEIM has six modes of operation. WEIM does not require a dedicated low-power mode because most of clocks are gated anytime when there are no accesses to WEIM providing maximum energy conservation. • Asynchronous mode. This is a non-burst mode is used for SRAM access. In this mode a single data is read/written with each access (asserted address). All controls timings are controlled by preset values in Chip Select control registers. • Synchronous read mode. This is a burst mode is used for reading Flash memory devices. In this mode after address assertion, a burst of sequential data can be read. Data exchange is carried out according to BCLK clock that is generated by WEIM. An access may be delayed by external ECB signal assertion after first word of data. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-1 Wireless External Interface Module (WEIM) • Page mode. This mode is used for memory burst read, but address is asserted for each data in the burst as LBA and BCLK operate asynchronously. In this mode, setup time is greater for first data burst than for the remaining data burst (in the same page). STROBE GUARD AHB controls AHB Capture Bus Controller STATE WR_GUARD IO_DIR [3:0] CS[5:0] RW OE ENABLES Output Control EB[3:0] LBA BCLK EIM Clock AHB clock (HCLK 133 MHz) BOOT_CFG BIGEND [5:0] EIM Config GATED CLOCKS CONFIGURATION Input Capture ECB DTACK AHB HWDATA[31:0] ADDR[25:16] ADDR[15:0]/ M_DATA_OUT[15:0] DATA_OUT[15:0]/ M_DATA_OUT[31:16] Addr Write Data Path Data MUX Addr Path AHB HADDR[31:0] M_DATA_IN[15:0] DATA_IN[15:0]/ M_DATA_IN[31:16] AHB HRDATA[31:0] Read Data Path BCLK_FB Figure 17-1. WEIM Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-2 Freescale Semiconductor Wireless External Interface Module (WEIM) • • • Synchronous read/write mode (PSRAM synchronous mode). In this mode, read and write are synchronous. Access may be additionally delayed according to ECB state before first piece of data arrives (refresh wait enable). DTACK mode. This is a non-burst mode used for PCMCIA access. In this mode, WEIM waits for DTACK acknowledge until 1024 counts of AHB clock have passed. In this mode, DTACK can be used as posedge or level sensitive according to WSC field and EW bit settings. Multiplexed Address/Data mode. In this mode, multiplexing addresses and data bits on same pins is supported for synchronous/asynchronous accesses to the 32-bit data width memory devices. 17.3 External Signal Description Table 17-1. Signal Properties Name ADDR[25:16] Port — — — — — — — — — — — — — — — — — — — Function Address Bus MSB/EB[3:2], CRE Address Bus LSB/Output Data Multiplexed Bus LSB Burst Clock Feedback Burst Clock Data Endian Boot Configuration Chip Selects Input Data Bus LSB/Input Data Multiplexed Bus MSB Output Data Bus LSB/Output Data Multiplexed Bus MSB Data Transfer Acknowledge/Wait Enable Byte End Current Burst/Wait Input Guard IO Direction Load Burst Address Input Data Multiplexed Bus LSB Output Enable Read/Write Write Guard Direction Out Out Out In In In Out In Out In Out In In Out Out In Out Out Out Reset State Low Low Low — — — High — Low — High — — Low High — High High High This section discusses input and output signals (see Table 17-1) between WEIM and external devices. ADDR[15:0]/ M_DATA_OUT[15:0] BCLK BCLK_FB BIGEND BOOT_CFG[5:0] CS[5:0] DATA_IN[15:0]/ M_DATA_IN[31:16] DATA_OUT[15:0]/ M_DATA_OUT[31:16] DTACK EB[3:0] ECB GUARD IO_DIR[3:0] LBA M_DATA_IN[15:0] OE RW WR_GUARD MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-3 Wireless External Interface Module (WEIM) 17.4 Detailed Signal Descriptions Table 17-2. WEIM Detailed Signal Descriptions Signal I/O Description ADDR[25:16] IO Address Bus MSB. These pins are used as address bits [25:16]. In the multiplexed mode these pins do not change their state. If corresponding AUSx bit is set, those pins reflect [25:16] AHB address bits. If AUSx bit is not set, these pins represent [27:18] AHB address bits for word-width memory, [26:17] bits for halfword width memory and [25:16] bits for byte-width memory. ADDR[25:24] also are used as EB[3:2] in the multiplexed mode (MUM=1). ADDR[23] also is used as CRE in PSRAM mode (PSR=1). IO Multiplexed Address Bus LSB/Output Data Bus LSB. In non-multiplexed mode those pins are used as address bits [15:0]. If corresponding AUSx bit is set those pins reflect [15:0] AHB address bits. If AUSx bit is not set, those pins reflect [17:2] AHB address bits for word width memory, [16:1] bits for halfword width memory and [15:0] bits for byte width memory. In multiplexed Address/Data mode those bits are multiplexed between address and output data [15:0] bits. In the multiplexed Address/Data mode its behavior is affected by the LBA, LBN and LAH fields in the Chip Select control registers. In synchronous multiplexed mode its behavior is affected by the BCS, BCD and LAH fields. Bidirectional LSB address/data bus are made in IO PAD from M_DATA_IN[15:0] and ADDR[15:0]/M_DATA_OUT[15:0]. O Burst Clock. This active-high output signal BCLK is used to clock external, burst-capable devices to synchronize the loading and incrementing of addresses and delivery of burst read and write data to/from the WEIM. Its behavior is affected by the BCM bit in the WEIM configuration register and the SYNC bit and BCD and BCS fields in the Chip Select control registers. BCLK can start on both rising and falling edge of HCLK. Burst Clock Feedback. This input is used to provide input data sampling clock in high data speed. It is a feedback from the IO PAD of the BCLK output pin that intend to align the clock used by the memory, and the one that is used to sample the read data. Big/Little Endian. This input is used to provide big/little endian support in the WEIM. WEIM supports big and little endian accesses according Table 17-4. WEIM supports mixing big and little endian accesses. Boot Configuration. These input pins determine the state of some WEIM configuration bits after hardware reset. See Table 17-3 for settings. Chip Selects. The CS[5:0] signals are chip selects active-low output pins. Its behavior is affected by the CSA and CSN fields in the Chip Select control registers. CS[0] address space range can be increased to 256 Mbytes by merging the CS[0] and CS[1] ranges. In this case the Merged Address Space (MAS) bit is set in the WEIM Configuration register, and the CS[1] pin is used as address line A26. As shown in Table 17-6, the chip select signals are asserted based on a decode of address lines [31:24] (when enabled). ADDR[15:0]/ M_DATA_OUT[15:0] BCLK BCLK_FB I BIGEND I BOOT_CFG[5:0] CS[5:0] O O DATA_IN[15:0]/M_DAT A_IN[31:16] IO Input Data Bus LSB/Input Data Multiplexed Bus MSB. These signals are the input data bus used to transfer data from external devices. In a non multiplexed mode it is LSB, in a multiplexed mode it is MSB. Bidirectional LSB data bus are made in IO PAD from DATA_IN[15:0]/M_DATA_IN[31:16] and DATA_OUT[15:0]/M_DATA_OUT[31:16]. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-4 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-2. WEIM Detailed Signal Descriptions (continued) Signal DATA_OUT[15:0]/ M_DATA_OUT[31:16] I/O 0 Description Output Data Bus LSB/Output Data Multiplexed Bus MSB. These signals are the output data bus used to transfer data to an external devices. In a non-multiplexed mode, it is LSB and in a multiplexed mode, it is MSB. Bidirectional LSB data bus are made in IO PAD from DATA_IN[15:0]/M_DATA_IN[31:16] and DATA_OUT[15:0]/M_DATA_OUT[31:16]. Data Transfer Acknowledge. This input signal is used to externally terminate a data transfer when enabled. For DTACK enabled cycles, the bus time-out monitor generates a bus error if DTACK after has been asserted is not deasserted before 1024 clocks have elapsed. This signal is used in two modes: with rising edge detection or with level detection with an insensitiveness time. Edge detection mode is used for devices like PCMCI card. Level detection mode is used for asynchronous devices like ATI graphic controller. DTACK control keeps backward compatibility with previous architectures that used it in the Application processors. Enable Byte. Those active-low output pins indicate active data bytes for the current access. They may be configured to assert for read and write cycles or for write cycles only as programmed in the Chip Select control registers. EB[0] corresponds to DATA_OUT[7:0] and M_DATA_OUT[7:0]. EB[1] corresponds to DATA_OUT[15:8] and M_DATA_OUT[15:8]. EB[2] corresponds to M_DATA_OUT[23:16]. EB[3] corresponds to M_DATA_OUT[31:24]. EB[3:2] also are multiplexed to the ADDR[25:24] bits in the multiplexed mode (MUM = 1). In the write accesses its behavior is affected by the EBWA and EBWN fields and EBC bit in the Chip Select control registers. In the read accesses its behavior is affected by the EBRA and EBRN fields in the Chip Select control registers. End Current Burst (WAIT). This active-low input signal ECB is asserted by external burst capable devices. It is serviced in synchronous mode only (SYNC=1). This signal can be used in two different modes depending on the EW bit in the Chip Select Control Register. In the ECB mode (EW=0) ECB indicates the end of the current (continuous) burst sequence. Following assertion, the WEIM terminates the current burst sequence and initiate a new one. In the WAIT mode (EW=1) the memory device asserts this signal to insert wait states during refresh collisions or during a row boundary crossing. Following assertion, the WEIM does not terminate the current burst sequence and continues it once WAIT is negated. ECB will have a pull up resistor in IO. For burst devices ECB/WAIT output should be configured to change one cycle before data is ready (before delay). Guard. This active-high input signal indicates that IO is locked by another module and current access should be postponed till IO unlocked. GUARD and WR_GUARD together are used in back to back accesses between memory controllers to avoid contention on the shared pins. IO Direction. These active-high output signal indicates IO direction (0 for input and “1” for output). Bidirectional buses are made in IO module from ADDR[15:0]/M_DATA_OUT[15:0] and M_DATA_IN[15:0] from DATA_OUT[15:0]/M_DATA_OUT[31:16] and DATA_IN[15:0]/M_DATA_IN[31:16]. Bit IO_DIR[0] corresponds to ADDR[7:0]/M_DATA_OUT[7:0]/M_DATA_IN[7:0], Bit IO_DIR[1] corresponds to ADDR[15:8]/M_DATA_OUT[15:8]/M_DATA_IN[15:8], Bit IO_DIR[2] corresponds to DATA_OUT[7:0]/M_DATA_OUT[23:16]/DATA_IN[7:0]/M_DATA_IN[23:16], and Bit IO_DIR[3] corresponds to DATA_OUT[15:8]/M_DATA_OUT[31:24]/DATA_IN[15:8]/M_DATA_IN[31:24] Load Burst Address. This active-low output signal is asserted during burst mode accesses to cause the external burst capable device to load a new starting burst address. Assertion of LBA indicates that a valid address is present on the address bus. Its behavior is affected by the SYNC bit, BCD, BCS, LBA and LBN fields in the Chip Select control registers. In asynchronous mode (SYNC=0) LBA length decreased by LBA and LBN fields. In the synchronous mode (SYNC=1) LBA length is equal BCD + BCS + LBN + 1 half AHB clock cycles. DTACK I EB[3:0] O ECB I GUARD I IO_DIR[3:0] O LBA O MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-5 Wireless External Interface Module (WEIM) Table 17-2. WEIM Detailed Signal Descriptions (continued) Signal M_DATA_IN[15:0] I/O I Description MUX Data Input Bus. These signals are LSB input data bus used to transfer data from an external devices in multiplexed mode. Bidirectional LSB address/data bus are made in IO PAD from M_DATA_IN[15:0] and ADDR[15:0]/M_DATA_OUT[15:0]. Output Enable. This active-low output signal OE indicates the bus access is a read and enables slave devices to drive the data bus with read data. Its behavior is affected by the OEA and OEN fields in the Chip Select control registers. Read/Write. RW output signal indicates if the current bus access is a read or write cycle. A high (logic one) level indicates a read cycle and a low (logic zero) level indicates a write cycle. Its behavior is affected by the RWA and RWN fields in the Chip Select control registers. Strobe. This signal allows capture current access controls, address and data on logic analyzer. sync. and async. accesses are supported. WR_GUARD. This active-high output signal indicates that IO is locked by WEIM. (It is asserted also in Extra Dead Cycles time). WR_GUARD and GUARD together are used in back to back accesses between memory controllers to avoid contention on the shared pins. OE O RW O STROBE WR_GUARD O O Table 17-3. Boot Configuration Settings BOOT_CFG Bits 5 4 3 2:0 Configured Bits AUS0 MUM MAS DSZ[2:0] Place WCR CSCR0A WCR CSCR0U MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-6 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-4. WEIM Out/in Data in Case AHB Out/in Data is 0xB3B2B1B0 Port Size and Used Bits AHB Address [1:0] [31:24] Word Port Halfword Port External address [0] 0 Byte Port External address [1:0] 0 1 1 0xB1 0xB0 2 3 Half Word 0 0xB3 0xB2 0 0xB3 0xB2 0 1 2 0xB1 0xB0 1 0xB1 0xB0 2 3 Byte 0 1 2 3 Little Word 0 0xB3 0xB2 0xB1 0xB3 0xB2 0xB1 0xB0 0xB0 0 0xB1 1 0xB1 0xB0 0xB0 0 0xB3 0xB2 0 1 2 3 0 1 1 0xB3 0xB2 2 3 Half Word 0 0xB1 0xB0 0 0xB1 0xB0 0 1 2 0xB3 0xB2 1 0xB3 0xB2 2 3 Byte 0 1 2 3 0xB3 0xB2 0xB1 1 0xB3 0xB0 0 0xB1 0xB2 0xB0 0 1 2 3 [31:24] ([15:8], [23:16], [7:0]) 0xB3 0xB2 0xB1 0xB0 0xB3 0xB2 0xB1 0xB0 0xB3 0xB2 0xB1 0xB0 0xB0 0xB1 0xB2 0xB3 0xB0 0xB1 0xB2 0xB3 0xB0 0xB1 0xB2 0xB3 Endian Mode AHB Access [23:16] [15:8] [7:0] [31:24] ([15:8]) [23:16] ([7:0]) Big Word 0 0xB3 0xB2 0xB1 0xB0 0xB3 0xB2 17.5 Memory Map and Register Definition The WEIM module includes 19 user-accessible 32-bit registers. There is a common register called WEIM Configuration Register (WCR) that contains control bits to configure WEIM for certain operation modes. The other 18 registers: Chip Select Control Register 0–5 Upper, Lower, and Additional (CSCR0U, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-7 Wireless External Interface Module (WEIM) CRCR0L, CRCR0A,..., CSCR5U, CSCR5L, CSCR5A) and six Chip Select Control Registers 0–5 (CSCR0–CSCR5) for each chip select. The layout of control register is slightly different for the CSCR0 register because the CSCR0 reset state depends on BOOT_CFG input. These registers are accessible only in supervisor mode with word (32-bit) reads and writes. Complete decoding is not performed, so shadowing can occur with these registers. The user should not attempt to address these registers at any other address location other than those listed in Table 17-5 and Table 17-6. 17.5.1 Memory Map Table 17-5. WEIM Memory Map Address Definition Chip Select 0 Upper Control Register Chip Select 0 Lower Control Register Chip Select 0 Addition Control Register Chip Select 1 Upper Control Register Chip Select 1 Lower Control Register Chip Select 1 Addition Control Register Chip Select 2 Upper Control Register Chip Select 2 Lower Control Register Chip Select 2 Addition Control Register Chip Select 3 Upper Control Register Chip Select 3 Lower Control Register Chip Select 3 Addition Control Register Chip Select 4 Upper Control Register Chip Select 4 Lower Control Register Chip Select 4 Addition Control Register Chip Select 5 Upper Control Register Chip Select 5 Lower Control Register Chip Select 5 Addition Control Register WEIM Configuration Register (WCR) Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x0000_1E00 0x000_081 1 Memory map for WEIM is shown in Table 17-5 and memory map for Chip Select is shown in Table 17-6. Section/Page 17.5.3.1/17-12 17.5.3.2/17-16 17.5.3.3/17-20 17.5.3.1/17-12 17.5.3.2/17-16 17.5.3.3/17-20 17.5.3.1/17-12 17.5.3.2/17-16 17.5.3.3/17-20 17.5.3.1/17-12 17.5.3.2/17-16 17.5.3.3/17-20 17.5.3.1/17-12 17.5.3.2/17-16 17.5.3.3/17-20 17.5.3.1/17-12 17.5.3.2/17-16 17.5.3.3/17-20 17.5.3.4/17-23 0xD800_2000 (CSCR0U) 0xD800_2004 (CSCR0L) 0xD800_2008 (CSCR0A) 0xD800_2010 (CSCR1U) 0xD800_2014 (CSCR1L) 0xD800_2018 (CSCR1A) 0xD800_2020 (CSCR2U) 0xD800_2024 (CSCR2L) 0xD800_2028 (CSCR2A) 0xD800_2030 (CSCR3U) 0xD800_2034 (CSCR3L) 0xD800_2038 (CSCR3A) 0xD800_2040 (CSCR4U) 0xD800_2044 (CSCR4L) 0xD800_2048 (CSCR4A) 0xD800_2050 (CSCR5U) 0xD800_2054 (CSCR5L) 0xD800_2058 (CSCR5A) 0xD800_2060 (WCR) 1 0x0000_000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0100 Some bits are set according BOOT_CFG input. Table 17-6. WEIM Chip Selection Memory Map Address 0xC000_0000 … 0xC7FF_FFFF 0xC800_0000 … 0xCFFF_FFFF Use CS0 memory region CS1 memory region Access R/W R/W MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-8 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-6. WEIM Chip Selection Memory Map (continued) Address 0xD000_0000 … 0xD1FF_FFFF 0xD200_0000 … 0xD3FF_FFFF 0xD400_0000 … 0xD5FF_FFFF 0xD600_0000 … 0xD7FF_FFFF Use CS2 memory region CS3 memory region CS4 memory region CS5 memory region Access R/W R/W R/W R/W 17.5.2 Register Summary Figure 17-2 shows the key to the register fields and Table 17-7 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0 bit only bit only bit BIT to clear w1c bit BIT N/A Figure 17-2. Key to Register Fields Table 17-7. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types R W rw rwm w1c slfclr Read-only. Writing this bit has no effect. Write-only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. 17.5.3 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bits and field function follow the register diagrams, in bit order. Table 17-8 provides a summary of the registers in the WEIM module. The 96 bits MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-9 Wireless External Interface Module (WEIM) used to control Chip Select are divided into three registers: Chip Select x Upper Control Register (CSCRxU), Chip Select x Lower Control Register (CSCRxL) and Chip Select x Additional Control Register (CSCRxA). • Bits [95:64] are located in Chip Select x Upper Control Register (see Figure 17-3). • Bits [63:32] are located in Chip Select x Lower Control Register (see Figure 17-4). • Bits [31:0] are located in Chip Select x Additional Control Register (see Figure 17-5). Table 17-8. WEIM Register Summary Name 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0xD800_2000 R SP (CSCR0U) W R WP BCD BCS PSZ PME SYN C DOL CNC W 0xD800_2004 R (CSCR0L) W R CSA W 0xD800_2008 R (CSCR0A) W R MU WM 0xD800_2010 R SP (CSCR1U) W R CNC W 0xD800_2014 R (CSCR1L) W R CSA W 0xD800_2018 R (CSCR1A) W R MU WM EBRA OEA EBRA OEA WSC EW WWS EDC OEN EBWA EBWN WRA CSE P N EBC DSZ CSN PSR CRE EBRN RWA RWN WW CNC AGE U 2 DOL LAH LBN LBA DWW DCT SYN C FCE WP BCD BCS PSZ PME WSC EW WWS EDC OEN EBWA EBWN WRA CSE P N EBC DSZ CSN PSR CRE EBRN RWA RWN WW CNC AGE U 2 LAH LBN LBA DWW DCT FCE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-10 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-8. WEIM Register Summary (continued) Name 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0xD800_2020 R SP (CSCR2U) W R WP BCD BCS PSZ PME SYN C DOL CNC W 0xD800_2024 R (CSCR2L) W R CSA W 0xD800_2028 R (CSCR2A) W R MU WM 0xD800_2030 R SP (CSCR3U) W R CNC W 0xD800_2034 R (CSCR3L) W R CSA W 0xD800_2038 R (CSCR3A) W R MU WM 0xD800_2040 R SP (CSCR4U) W R CNC W 0xD800_2044 R (CSCR4L) W R CSA W OEA EBRA OEA EBRA OEA WSC EW WWS EDC OEN EBWA EBWN WRA CSE P N EBC DSZ CSN PSR CRE EBRN RWA RWN WW CNC AGE U 2 DOL LAH LBN LBA DWW DCT SYN C FCE WP BCD BCS PSZ PME WSC EW WWS EDC OEN EBWA EBWN WRA CSE P N EBC DSZ CSN PSR CRE EBRN RWA RWN WW CNC AGE U 2 DOL LAH LBN LBA DWW DCT SYN C FCE WP BCD BCS PSZ PME WSC EW WWS EDC OEN EBWA EBWN WRA CSE P N EBC DSZ CSN PSR CRE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-11 Wireless External Interface Module (WEIM) Table 17-8. WEIM Register Summary (continued) Name 0xD800_2048 R (CSCR4A) W R MU WM 0xD800_2050 R SP (CSCR5U) W R CNC W 0xD800_2054 R (CSCR5L) W R CSA W 0xD800_2058 R (CSCR5A) W R MU WM 0xD800_2060 R (WCR) W R ECP EC P0 W1 AUS AUS AUS AUS AUS AUS 5 4 3 2 1 0 EBRA EBRN RWA EBC DSZ CSN PSR CRE OEA OEN EBWA EBWN WRA CSE P N WSC EW WWS EDC 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 EBRA EBRN RWA RWN WW CNC AGE U 2 DOL LAH LBN LBA DWW DCT SYN C FCE WP BCD BCS PSZ PME RWN WW CNC AGE U 2 ECP ECP ECP 5 4 3 BC M LAH LBN LBA DWW DCT FCE ECP 2 MAS 17.5.3.1 Chip Select x Upper Control Register (CSCRxU) Figure 17-3 shows the register and Table 17-9 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-12 Freescale Semiconductor Wireless External Interface Module (WEIM) 0xD800_2000 (CSCR0U) 0xD800_2010 (CSCR1U) 0xD800_2020 (CSCR2U) 0xD800_2030 (CSCR3U) 0xD800_2040 (CSCR4U) 0xD800_2050 (CSCR5U) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R SP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WP BCD BCS PSZ PME SYNC DOL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CNC W Reset 0 0 0 0 WSC1 0 0 0 0 EW 0 0 WWS 0 0 0 0 EDC 0 0 Figure 17-3. Chip Select x Upper Control Register 1 WSC field (bits 8–13) reset value is 011110 for CS0U register and is 0 for all others. Table 17-9. Chip Select x Upper Control Register Field Descriptions Field 31 SP Description Supervisor Protect. This bit prevents accesses to the address range defined by the corresponding chip select when the access is attempted in the User mode. SP is cleared by a hardware reset. 0 User mode accesses are allowed in the memory range defined by chip select. 1 User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in a error response on the AHB and no assertion of the chip select output. Write Protect. This bit prevents writes to the address range defined by the corresponding chip select. WP is cleared by a hardware reset. 0 Writes are allowed in the memory range defined by chip. 1 Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response on the AHB and no assertion of the chip select output. Burst Clock Divisor. This bit field contains the value used to program the burst clock divisor for BCLK generation. It is used to divide the internal AHB bus frequency (HCLK 133 MHz). See 17.6.4/17-26 for more information on the burst clock divisors. An example is shown in Figure 17-41. When the BCM bit is set in the WEIM configuration register, BCD is ignored. BCD is cleared by a hardware reset. 00 Divide AHB clock by 1 01 Divide AHB clock by 2 10 Divide AHB clock by 3 11 Divide AHB clock by 4 Burst Clock Start. If SYNC 1 this bit field determines the number of half cycles after address assertion before the first rising edge of BCLK is seen. See example on the Figure 17-41. A value of 0 results in a half clock delay, not an immediate assertion. When the BCM bit is set in the WEIM configuration register, this overrides the BCS bits. BCS is cleared by a hardware reset. 0000 1 half AHB clock cycle. 0001 2 half AHB clock cycles. 1111 16 half AHB clock cycles. 30 WP 29–28 BCD 27–24 BCS MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-13 Wireless External Interface Module (WEIM) Table 17-9. Chip Select x Upper Control Register Field Descriptions (continued) Field 23–22 PSZ Description Page Size. If PME is clear the PSZ bit field indicates memory burst length in words (where word is defined by the DSZ field) and should be properly initialized for mixed wrap/increment AHB accesses support. Continuous PSZ value corresponds to continuous burst length setting of the external memory device. If PME is set (set to 1) the PSZ bit field indicates number of words (where “word” is defined by the port size in DSZ field) in a page in memory. This ensures that the WEIM does not burst past a page boundary at increment access when the PME bit is set. PSZ is cleared by a hardware reset. See Table 17-10 for PSZ Bit Field Combinations. Page Mode Emulation. This bit enables page mode emulation in burst mode. When PME is set (and SYNC equals 1), the external address is asserted for each piece of data requested. Additionally, the LBA and BCLK signals behave in the same way when an asynchronous access is performed (see Figure 17-25). PME is cleared by a hardware reset. 0 Disables page mode emulation 1 Enables page mode emulation Synchronous Burst Mode Enable. This bit enables synchronous burst mode if PME is clear (see also PME and PSR description). When enabled, the WEIM is capable of interfacing to burst flash devices through additional burst control signals: BCLK, LBA, and ECB (see example on the Figure 17-29). The sequencing of these additional I/Os is controlled by other WEIM configuration register bit settings as described in Section 17.6.3, “Burst Mode Memory Operation.” SYNC is cleared by a hardware reset. 0 Disables synchronous burst mode 1 Enables synchronous burst mode Data Output Length. If SYNC is set (equals 1) the DOL bit field specifies number of wait states during the burst access after the delay of the first data according to the settings shown below (see examples on the Figure 17-25 and Figure 17-40). The reset value 0 specifies that burst data is held for a single AHB clock period. As AHB clock frequencies increase, it may become necessary to delay sampling the data for multiple AHB clock periods in order to meet burst memory setup and/or frequency specifications and/or WEIM data setup time requirements. DOL has no effect on burst data length when SYNC = 0. DOL is cleared by a hardware reset. 0000 1 AHB clock cycle data length. 0001 2 AHB clock cycles data length. — 1111 16 AHB clock cycles data length. Chip Select Negation Clock Cycles. This bit field specifies the minimum number of clock cycles a chip select must remain negated after it is negated (but doesn’t guarantee negation for back-to-back accesses, it requires EDC using) according to the settings shown below. See examples on the Figure 17-12, and Figure 17-13. CNC has no effect on write accesses when any CSA bit is set. CNC is cleared by a hardware reset. The number of clock cycles of this field can be increased using the CNC2 bit in the appropriate Chip Select Addition Control Register. 00 0 Minimum number of AHB clock cycles CS must remain negated. 01 1 Minimum number of AHB clock cycles CS must remain negated. 10 2 Minimum number of AHB clock cycles CS must remain negated. 11 3 Minimum number of AHB clock cycles CS must remain negated. 21 PME 20 SYNC 19–16 DOL 15–14 CNC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-14 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-9. Chip Select x Upper Control Register Field Descriptions (continued) Field 13–8 WSC Description Wait State Control. This bit field programs the number of wait-states for an access to the external device connected to the chip select (see Figure 17-7). For SYNC = 1 WSC programs the number of AHB clock cycles required for the initial access (see Figure 17-25, and Figure 17-32) of a memory burst sequence initiated by the WEIM to an external burst device. For EW = 1 after the wait cycle count expires ECB is sampled and the cycle terminates when the ECB is negated. On other case WEIM special watch dog counter check that ECB will not be asserted for more than 1024 AHB clocks. Additionally in this case WEIM suppresses LBA generation after next ECB assertion (during increment burst at page boundary crossing). For write accesses the number of wait-states is increased according WWS value or decreased by DWW (see Table 17-11). WSC = 11_1111 indicates operation in a positive edge-sensitive DTACK mode. It selects DTACK input as access length control sign (instead of default WSC counter). It means that access length is determined by DTACK length. WSC is set to 01_1110 by a hardware reset for CSCR0. WSC is cleared by a hardware reset for CSCR1 – CSCR5. Note: For SYNC=1 and DOL=0, WSC value should be at least 4. For SYNC=1, MUM =0, WSC≥ 2(BCD + 1) + (BCS + LBN + 2)/2. For SYNC=1, MUM =1, WSCŠ 2(BCD + 1) + (BCS + LBN + 2 + LBH) + 2/2. For PSR=1, the number of wait-states is increased by one for read access. ECB/WAIT. This bit determines how WEIM supports the ECB input in the synchronous mode. In asynchronous mode this bit determines the operation of level-sensitive DTACK mode. (see Table 17-18 for EW effect on WEIM operation modes) 0 For SYNC = 1, if ECB goes to low state in the middle of memory burst access then the WEIM starts a new access by asserting the current AHB address to the ADDR pins and LBA assertion (ECB mode). If SYNC = 0 and WSC=111111, the WEIM waits for DTACK posedge for access termination. 1 If ECB goes to low state in the middle of a memory burst access then the WEIM waits until ECB goes high (WAIT mode) to continue current access; at the end of first access in burst it allows to wait ECB negation till 1024 clock. For SYNC = 0 WEIM begins access and after (2+DCT) clocks tests DTACK input. If DTACK is low WEIM waits DTACK high state then loads WSC value (see Figure 17-27 and Figure 17-28). Write Wait State. This bit field determines whether additional wait-states are required for write cycles (see Table 17-11). This is useful for writing to memories that require additional data setup time (see example on Figure 17-9). The DWW field should be zero when this field is in use. WWS is cleared by a hardware reset. Note: To decrease write wait states use the DWW bit field. Extra Dead Cycles. This bit field determines whether idle cycles are inserted before a new access (see example in Figure 17-10). If the currently accessed CS EDC field is not empty then idle cycles are inserted before next access except for two conditions: current access is an asynchronous write (its SYNC = 0) or the next access is an asynchronous read from the same chip select. This field is used in two cases: • Slow memory or peripherals that use long CS or OE to output data hold times to prevent data bus contention on back-to-back external transfers. • Synchronous accesses (SYNC = 1) to provide CS high minimum pulse width (even for back-to-back accesses). The EDC field is cleared by a hardware reset. Note: On some occasions, setting EDC field to 0000 may result in memory read/write mistakes. Therefore, the recommended configuration for EDC field is 2 or higher. 0000 No idle AHB clock cycles inserted. 0001 1 Idle AHB clock cycle inserted. — 1111 15 AHB clock cycles inserted. 7 EW 6–4 WWS 3–0 EDC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-15 Wireless External Interface Module (WEIM) Table 17-10. PSZ Bit Field Values PSZ 00 01 10 11 PME=0 Memory Burst Length 4 8 16 continuous PME=1 Number of Words in Page 4 8 16 32 Table 17-11. WSC Bit Field Values Number of Wait-States WSC Write Access Read Access WWS = 0, DWW = 0 1 1 2 3 4 — 119 120 121 122 123 124 125 126 WWS = 1, DWW = 0 1 2 3 4 5 — 120 121 122 123 124 125 126 127 WWS = 7, DWW = 0 7 8 9 10 11 — 126 127 127 127 127 127 127 127 WWS = 0, DWW = 1 1 1 1 2 3 — 118 119 120 121 122 123 124 125 WWS = 0, DWW = 2 1 1 1 1 2 — 117 118 119 120 121 122 123 124 000000 000001 000010 000011 000100 1 1 2 3 4 — 119 120 121 122 123 124 125 126 … 110111 111000 111001 111010 111011 111100 111101 111110 111111 Posedge sensitive DTACK mode 17.5.3.2 Chip Select x Lower Control Register (CSCRxL) Figure 17-4 shows the register and Table 17-12 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-16 Freescale Semiconductor Wireless External Interface Module (WEIM) 0xD800_2004 (CSCR0L) 0xD800_2014 (CSCR1L) 0xD800_2024 (CSCR2L) 0xD800_2034 (CSCR3L) 0xD800_2044 (CSCR4L) 0xD800_2054 (CSCR5L) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R W Reset 0 0 OEA1 0 0 0 0 OEN 0 0 0 EBWA 0 0 0 0 EBWN 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CSA W Reset 0 0 0 0 EBC2 0 0 DSZ3 0 0 0 0 CSN4 0 0 PSR 0 CRE 0 WRA CSEN P 0 05 Figure 17-4. Chip Select x Lower Control Register 1 2 3 4 5 OEA (bits 28–31) reset value is 1010 for CSCR0L register and 0 for other registers EBC (bit 11) reset value is 1 for CSCR0L register and 0 for other registers DSZ (bits 8–10) reset value is configurable for the CSCR0L register and 0 for other registers CSN (bits 4–7) reset value is 0100 for CSCR0L register and 0 for other registers Bit 0 reset value is 1 for CSCR0L register and 0 for other registers MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-17 Wireless External Interface Module (WEIM) Table 17-12. Chip Select x Lower Control Register Field Descriptions Field 31–28 OEA Description OE Assert. This bit field determines when OE is asserted during a read cycle. For SYNC = 0, OEA determines number of half clocks before OE asserts during a read cycle. For SYNC = 1, after initial memory burst access, OE is asserted continuously for subsequent memory burst accesses, and is not affected by OEA (see memory burst read timing diagram for more detail); the behavior of OE on initial memory burst access is same as when SYNC = 0 (see example on Figure 17-25). OEA field do not affect the cycle length. OEA is set to 1010 by a hardware reset for CSCR0L register and is cleared for other registers. Note: Minimum time OE is asserted is one clock cycle. 0000 0 Half AHB clock cycles between OE assertion and end of access 0001 1 Half AHB clock cycle between OE assertion and end of access — 1111 15 Half AHB clock cycles between OE assertion and end of access OE Negate. This bit field determines when OE is negated during a read cycle (see example on Figure 17-20). Setting the SYNC bit (SYNC = 1) overrides OEN and OE negates at the end of a read access and no sooner. OEN does not affect the cycle length, except in posedge sensitive DTACK mode. OEN is cleared by a hardware reset. Note: The term “end of a read access” is the nearest possible address, data or control signal change by another access (an own next access or an access from others pin shared controller). Minimum time OE is asserted is one clock cycle. 0000 0 Half AHB clock cycles between OE negation and end of access 0001 1 Half AHB clock cycle between OE negation and end of access — 1111 15 Half AHB clock cycles between OE negation and end of access EB Write Assert. This bit field determines when EB [3:0] is asserted during write cycles (see example on Figure 17-8). This is useful to meet data setup time requirements for slow memories. EBWA does not affect the cycle length. EBWA is cleared by a hardware reset. 0000 0 Half AHB clock cycles before EB is asserted. 0001 1 Half AHB clock cycle before EB is asserted. — 1111 15 Half AHB clock cycles before EB is asserted. EB Write Negate. This bit field determines when EB [3:0] outputs are negated during a write cycle (see example on Figure 17-8). This is useful to meet data hold time requirements for slow memories. EBWN does not affect the cycle length, except in posedge sensitive DTACK mode. Setting the SYNC bit (SYNC = 1) overrides EBWN and EB negates at the end of a write access and according AHB hbstrb[3:0]. EBWN is cleared by a hardware reset. 0000 0 Half AHB clock cycles between EB negation and end of access. 0001 1 Half AHB clock cycle between EB negation and end of access. — 1111 15 Half AHB clock cycles between EB negation and end of access. CS Assert. This bit field determines when chip select is asserted for devices that require additional address setup time (see example on Figure 17-11). It does not affect the cycle length. CSA is cleared by a hardware reset. Note: CSA bit setting affects both reads and writes for all WEIM modes. 0000 0 Half AHB clock cycles before CS is asserted. 0001 1 Half AHB clock cycle before CS is asserted. — 1111 15 Half AHB clock cycles before CS is asserted. Enable Byte Control. This bit indicates the types of access that assert Enable Byte outputs EB[3:0] (see example on Figure 17-7). The EB[3:0] outputs can be configured as byte write enables. EBC is set by a hardware reset for CSCR0L register and is cleared for other registers. 0 Both read and write accesses assert the EB[3:0]. 1 Only write accesses assert the EB[3:0], thus configuring as byte write enables. 27–24 OEN 23–20 EBWA 19–16 EBWN 15–12 CSA 11 EBC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-18 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-12. Chip Select x Lower Control Register Field Descriptions (continued) Field 10–8 DSZ Description Data Port Size. This bit field defines the width of an external device’s data port as shown in the Table 17-13. DSZ is mapped by a hardware reset for CSCR0L by the value of the BOOT_CFG [2:0] bits. BOOT_CFG [2] maps to DSZ [2], BOOT_CFG [1] maps to DSZ [1] and BOOT_CFG [0] maps to DSZ [0]. DSZ and MUM (multiplexed mode) affected on data port location as shown in Table 17-13. DSZ is cleared by a hardware reset of CSCR1L–CSCR5L. CS Negate. This bit field determines when chip select is negated for devices that require additional address/data hold times (see example on Figure 17-11). CSN affects only asynchronous (read and write) access (SYNC=0), and is ignored on synchronous (SYNC=1). CSN does not affect cycle length, except in positive edge sensitive DTACK mode. CSN is set to 0100 by a hardware reset for CSCR0L register and is cleared by a hardware reset for other registers. 0000 0 Half AHB clock cycles between CS negation and end of access. 0001 1 Half AHB clock cycle between CS negation and end of access. — 1111 15 Half AHB clock cycles between CS negation and end of access. Pseudo SRAM Enable (Burst Write Enable). This bit enables four function for Pseudo SRAM (for example,. CellularRAMTM) or any other device that support these modes: burst write, write wrap disable, read wait state increase and memory control register accessibility. If PSR=1, then memory burst write is enable (with SYNC = 1). In this mode, WRAP bit is masked on write time, unless WWU bit is set in CSCRxA register, and wait state on read is automatically increased to WSC +1 (see Figure 17-40 and Figure 17-41). An asynchronous access (SYNC=0) should be used with PSR=1 and CRE=1 to write to the memory control register. PSR is cleared by a hardware reset. 0 PSRAM mode is disabled. 1 PSRAM mode is enabled. Control Register Enable. This bit indicates CRE memory pin state while writing to CS address space, for PSRAM control register write. For PSR=1 the CRE bit will be driven on pin ADDR[23] in a write access time. CRE is cleared by a hardware reset. Note: SYNC = 0 should be used to access to PSRAM control register. 0 CRE pin 0 1 CRE pin 1 Wrap Memory Mode. This bit indicates that memory is in wrap mode. Wrap size is set using the PSZ field. In case not matching wrap boundaries in both memory (PSZ field) and AHB access on current address, WEIM puts address on address bus and generates LBA signal (see example on Figure 17-37). WRAP is cleared by a hardware reset. 0 Memory is in not in wrap mode. 1 Memory is in wrap mode. CS Enable. This bit controls the operation of the chip select pin. CSEN is set by a hardware reset for CSCR0L to allow CSCR0L to select from an external boot ROM. CSEN is cleared by a hardware reset to CSCR1L–CSCR5L. 0 Chip select function is disabled; attempts to access an address mapped by this chip select results in a error respond on the AHB and no assertion of the chip select output. 1 Chip select is enabled, and is asserted when presented with a valid AHB access. 7–4 CSN 3 PSR 2 CRE 1 WRAP 0 CSEN Table 17-13. DSZ Bit Field Values Data Port Size DSZ MUM=0 000 001 010 011 Reserved Reserved 8-bit port, resides on DATA_IN/OUT [15:8] pins 8-bit port, resides on DATA_IN/OUT [7:0] pins MUM=1 Reserved Reserved Reserved Reserved MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-19 Wireless External Interface Module (WEIM) Table 17-13. DSZ Bit Field Values (continued) Data Port Size DSZ MUM=0 100 101 110 111 Reserved Reserved Reserved Reserved MUM=1 16-bit port, resides on ADDR/M_DATA_IN/OUT [15:0] pins Reserved 32-bit port, resides on ADDR/M_DATA_IN/OUT [15:0] and M_DATA_IN/OUT [31:16] pins The same 17.5.3.3 Chip Select x Additional Control Register (CSCRxA) Figure 17-5 shows the register and Table 17-14 provides its field descriptions. 0xD800_2008 (CSCR0A) 0xD800_2018 (CSCR1A) 0xD800_2028 (CSCR2A) 0xD800_2038 (CSCR3A) 0xD800_2048 (CSCR4A) 0xD800_2058 (CSCR5A) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R EBRA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBRN RWA RWN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MUM W Reset 13 0 LAH1 0 0 0 LBN2 0 0 0 LBA 0 0 DWW 0 0 DCT 0 WWU AGE CNC2 FCE 0 0 0 0 Figure 17-5. Chip Select x Addition Control Register LAH (bits 13, 14) reset value is 10 for CSCR0A and 0 for other registers LBN (bits 10 -12) reset value is 100 for CSCR0A and 0 for other registers 3 MUM (bit 15) reset value is determined by settings of BOOT_CFG inputs (see Table 17-3) for CSCR0A and 0 for other registers 2 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-20 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-14. Chip Select x Addition Control Register Field Descriptions Field 31–28 EBRA Description EB Read Assert. This bit field determines when EB [3:0] is asserted during read cycles (see example on Figure 17-25). EBRA does not affect the cycle length. EBRA is cleared by a hardware reset. Note: Minimum time EB is asserted is one clock cycle. 0000 0 Half AHB clock cycles before EB asserted. 0001 1 Half AHB clock cycle before EB asserted. — 1111 15 Half AHB clock cycles before EB asserted. EB Read Negate. This bit field determines when EB [3:0] outputs are negated during a read cycle (see example on Figure 17-20). EBRN does not affect the cycle length, except when in positive edge sensitive DTACK mode. Setting the SYNC bit (SYNC = 1) overrides EBRN and EB negates at the end of a read access but not sooner. EBRN is cleared by a hardware reset. Note: Minimum time EB is asserted is one clock cycle. 0000 0 Half AHB clock cycles between EB negation and end of access. 0001 1 Half AHB clock cycle between EB negation and end of access. — 1111 15 Half AHB clock cycles between EB negation and end of access. RW Assertion. This bit field determines when RW is asserted during write cycles. (see example on Figure 17-28). RWA is cleared by a hardware reset. Note: Minimum time RW is asserted is one clock cycle. 0000 0 Half AHB clock cycles RW delay 0001 1 Half AHB clock cycle RW delay. — 1111 15 Half AHB clock cycles RW delay. RW Negation. This bit field determines when RW is negated during a write cycle (see example on Figure 17-28). RWN does not affect the cycle length, except in posedge sensitive DTACK mode. Setting the SYNC bit (SYNC = 1) overrides RWN and RW negates at the end of a write access and no sooner. RWN is cleared by a hardware reset. Note: Minimum time RW is asserted is one clock cycle. 0000 0 Half AHB clock cycles between RW negation and end of access. 0001 1 Half AHB clock cycle between RW negation and end of access. — 1111 15 Half AHB clock cycles between RW negation and end of access. Multiplexed Mode. This bit determines the address/data multiplexed mode for asynchronous and synchronous accesses (see examples in Figure 17-43–Figure 17-46). Port mapping is defined in the Table 17-13. MUM is cleared by a hardware reset for CSCR1A–CSCR5A. For CSCR0A MUM is configured at reset time with the BOOT_CFG[4] (see Table 17-3). 0 Non-multiplexed mode 1 Multiplexed mode LBA to Address Hold. This bit field determines address hold time after LBA de-assertion for MUM = 1 only. See example on the Figure 17-43 and Figure 17-44. LAH is cleared by a hardware reset for CSCR1A–CSCR5A. For CSCR0A LAH is set to 10 by hardware reset. 00 0 AHB half clock cycles between LBA negation and address invalid. 01 1 AHB half clock cycle between LBA negation and address invalid. 10 2 AHB half clock cycles between LBA negation and address invalid. 11 3 AHB half clock cycles between LBA negation and address invalid. 27–24 EBRN 23–20 RWA 19–16 RWN 15 MUM 14–13 LAH MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-21 Wireless External Interface Module (WEIM) Table 17-14. Chip Select x Addition Control Register Field Descriptions (continued) Field 12–10 LBN Description LBA Negation. This bit field determines when LBA is negated. For SYNC=0 and MUM =0 LBN determines how many half AHB clock cycle will be between LBA negation and end of access (see example on the Figure 17-8). For SYNC=0 and MUM =1 this field determines LBA length (see example on the Figure 17-44). Negation time and LBA lengths are listed in Table 17-15. For SYNC=1 (MUM=0 and MUM=1) LBA negation occurs (LBN+BCD+1) half AHB clock cycles after first BCLK posedge detection. LBN does not affect the cycle length, except in positive edge sensitive DTACK mode. LBN is cleared by a hardware reset for CSCR1A–CSCR5A. For CSCR0A LBN is set to 100 by hardware reset. Note: Minimum of time LBA to be asserted is a one clock for MUM = 0 and two clocks for MUM = 1. LBA Assertion. This bit field determines when LBA is asserted according the settings shown below (see example on the Figure 17-11). LBA is cleared by a hardware reset. Note: LBA field affects all modes. Minimum of time LBA to be asserted is a one clock for MUM = 0 and two clocks for MUM = 1. 00 0 AHB half clock cycles between beginning of access and LBA assertion. 01 1 AHB half clock cycle between beginning of access and LBA assertion. 10 2 AHB half clock cycles between beginning of access and LBA assertion. 11 3 AHB half clock cycles between beginning of access and LBA assertion. Decrease Write Wait State. This bit field in combination with WWS determines whether write cycles are shorter than the read cycles (see Table 17-11). WWS field should be zero when this field is in use. DWW is cleared by a hardware reset. DTACK Check Time. This bit field determines time of insensitivity at the beginning of access for SYNC=0 and EW=1 according to the settings shown below (see example on the Figure 17-27). DCT is a number of clock cycles between CS assertion and first DTACK check. DCT is cleared by a hardware reset. 00 2 AHB clock cycles between CS assertion and first DTACK check. 01 6 AHB clock cycles between CS assertion and first DTACK check. 10 8 AHB clock cycles between CS assertion and first DTACK check 11 12 AHB clock cycles between CS assertion and first DTACK check. Write Wrap Unmask. This bit allow unmask WRAP bit in case PSR = 1 and write access. WWU is cleared by a hardware reset. 0 Prevents Wrap during write access 1 Allow wrap on write Acknowledge Glue Enable. This bit is used to enable/disable glue logic between external DTACK and internal control logic. The glue logic is a flip-flop that is reset by CS assertion, it’s data input is a constant 1 and DTACK goes to it’s clock input. This glue logic is used to synchronize the posedge of the external DTACK in a worst noise or a slowly edge grown conditions. AGE is cleared by a hardware reset. 0 Disable glue logic 1 Enable glue logic Chip Select Negation Clock Cycles, Bit [2]. This bit is used to increase the CNC field to a 3-bit field. See CNC field description in the Chip Select x Upper Control Register. CNC2 is cleared by a hardware reset. The number of AHB clock cycles produced by both bit fields is shown in Table 17-16. Feedback Clock Enable. This bit is used to enable/disable data capture by BCLK_FB. If FCE=1, WEIM used addition one clock to synchronize feedback clock captured data to AHB clock, so read access is slow then FCE=0. FCE is cleared by a hardware reset. 0 Data captured using AHB clock 1 Data captured using BCLK_FB 9–8 LBA 7–6 DWW 5–4 DCT 3 WWU 2 AGE 1 CNC2 0 FCE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-22 Freescale Semiconductor Wireless External Interface Module (WEIM) Table 17-15. LBN Bit Field Values Half AHB clock cycle between LBA negation and end of access MUM = 0 000 001 0 1 LBA length, half AHB clock cycle MUM = 1 2 3 LBN … 111 − 7 − 9 Table 17-16. CNC/CNC2 Bit Values CNC2 0 0 0 0 1 1 1 1 CNC 00 01 10 11 00 01 10 11 Minimum CS Negation, in AHB clock cycle 0 2 3 4 5 6 7 8 17.5.3.4 WEIM Configuration Register (WCR) WCR contains control bits for the configuration and operation of WEIM. Figure 17-6 shows the register and Table 17-17 provides its field descriptions. 0xD800_2060 (WCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 ECP5 ECP4 ECP3 ECP2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ECP1 ECP0 AUS5 AUS4 AUS3 AUS2 AUS1 AUS0 W Reset 0 0 0 0 0 0 BCM MAS 0 1/01 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-6. WCR Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-23 Wireless External Interface Module (WEIM) Table 17-17. WEIM Control Register Field Descriptions Field 31–20 19-14 ECP5 ECP4 ECP3 ECP2 ECP1 ECP0 13 AUS5 AUS4 AUS3 AUS2 AUS1 AUS0 7–3 2 BCM Reserved ECB Capture Phase. This bit indicates in which phase of HCLK, BCLK is generated to the memory for synchronous (CS5, CS4, CS3, CS2, CS1 or CS0) write accesses. This bit is XORed with BCS[0] bit in write accesses to determine the BCLK starting phase to memory and it also influence on capturing of ECB in WEIM design. 0 BCLK starting phase is as BCS[0] bit indicates. 1 BCLK starting phase is the opposite of BCS[0] bit indicates for write accesses only. Description Address Unshifted for (CS5, CS4, CS3, CS2, CS1 or CS0). This bit indicates an unshifted mode for address assertion for (CS5, CS4, CS3, CS2, CS1 or CS0) accesses. This bit is cleared by a hardware reset. 0 Address shifted according (CS5, CS4, CS3, CS2, CS1 or CS0) port size. 1 Address unshifted Reserved Burst Clock Mode. This bit selects the burst clock mode of operation. It is mainly used for system debug mode. BCM is cleared by a hardware reset. 0 Burst clock runs only when accessing a chip select range with SYNC bit set; when burst clock is not running, it remains in a logic 0 state; when burst clock is running, it is configured by BCD and BCS fields in chip select control register. 1 Burst clock runs on every memory access (independent of chip select configuration) Reserved Merged Address Space. This bit indicates merged address space mode. If MAS is set the CS1 address space is merged with CS0 for a total of 256 (for halfword width port and 512 for word width port) Mbytes. CS1 output is used as A26. This bit is configured at reset time with the BOOT_CFG[] pin. 0 Standard address space 1 Merged address space 1 0 MAS 17.6 17.6.1 Functional Description Configurable Bus Sizing WEIM supports byte, halfword, and word operands allowing access to 8-bit, 16-bit, and multiplexed 32-bit ports. Port size is programmable via the DSZ field in the corresponding Chip Select control register. In addition, portion of the data bus used for transfer to or from an 8-bit ports is programmable via the same DSZ field. An 8-bit port can reside on DATA_IN/OUT bus bits [15:8] or [7:0]. A 16-bit port reside on DATA_IN/OUT bus bits [15:0]. A 32-bit multiplexed port resides on M_DATA_IN/OUT bus bits [31:0]. NOTE Misaligned transfers are not supported. A word access to or from an 8-bit port requires four external bus cycles to complete the transfer. A word access to or from a 16-bit port requires two external bus cycles to complete the transfer. A halfword access to or from an 8-bit port requires two external bus cycles to complete the transfer. In case of a multi-cycle MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-24 Freescale Semiconductor Wireless External Interface Module (WEIM) transfer, the lower two address bits (ADDR[1:0]) are incremented appropriately. WEIM address bus is configured according to DSZ field and AUSx bits, too. There is either one or two bits right shift of AHB address bits for halfword or word width port accordingly. WEIM has a data multiplexer which takes the four bytes of the AHB interface data bus and routes them to their required positions to properly interface to memory and peripherals. 17.6.2 WEIM Operational Modes WEIM has 9 main operational modes selected by control fields settings as described in the Table 17-18. For details see corresponding bit fields descriptions. Table 17-18. WEIM Operation Modes Field Settings Control Fields Brief Mode Description SYNC 0 PME 0 MUM 0 1 0 0 1 1 0 0 0 1 0 1 EW 0 0 1 0 0 0 0 1 1 11_1111 WSC < 11_1111 Asynchronous Asynchronous multiplexed Asynchronous level sensitive DTACK mode Asynchronous posedge sensitive DTACK mode < 11_1111 Page mode emulation Synchronous burst with restart on ECB negation Synchronous multiplexed burst with restart on ECB negation Synchronous burst with wait on ECB negation Synchronous multiplexed burst with wait on ECB negation 17.6.3 Burst Mode Memory Operation With memory burst mode enabled (SYNC = 1), WEIM attempts to translate AHB burst accesses to memory burst accesses, being limited by the memory burst length, predefined PSZ value, or memory and AHB WRAP/INCR boundary crossing non-matching. WEIM only displays the first address accessed in a memory burst sequence unless the page mode emulation (PME) bit is set. WEIM may translate from some AHB sequential accesses to one or few memory bursts, but not from two AHB nonsequential accesses to one memory burst. For the first access in a memory burst sequence, WEIM asserts LBA—causing the external burst device to latch the starting burst address—and then toggle the burst clock (BCLK) a predefined number of cycles in order to latch the first unit of data. Subsequent accessed data units can then be burst in fewer clock cycles, realizing an overall increase in bus bandwidth. Memory burst accesses are terminated by WEIM whenever it detects that: • The next AHB access is not sequential, • The next sequential access crosses boundary with unequal condition (wrap/increment, burst length) on the AHB and memory, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-25 Wireless External Interface Module (WEIM) • • Current memory burst length reached, By external burst device request it needs additional cycles to retrieve the next requested memory location. In last case, burst memory device provides an ECB (or WAIT) feedback signal to WEIM whenever it is necessary to terminate/postponed the on-going burst sequence. If EW = 0, WEIM initiate a new (with long first access) memory burst sequence, if EW = 1, WEIM only waits for ECB negation to continue current memory burst sequence. Additionally EW = 1 allows wait states insertion after wait state counter expires, but ECB still asserted. Over this a new memory burst sequence should be generated. Synchronous mode is also used for burst Cellular RAM, which supports memory burst writes, which is enabled by PSR = 1. 17.6.4 Burst Clock Divisor In some cases it may be necessary to slow the external bus in relation to the internal bus to allow accesses to burst devices that have a maximum operating frequency which is less than the operating frequency of internal bus. Internal AHB bus frequency (HCLK 133 MHz) can be divided by two, three, or four for presentation on the external bus in burst mode operation. By programming the BCD field to various values, two signals on the external bus are affected; LBA and BCLK. LBA signal is asserted according to LBA field programming and remain asserted until the first falling edge of BCLK signal. BCLK signal runs with 50% duty cycle until a non-sequential internal request is received or an external ECB signal is recognized. Caution should be exercised when programming these fields to ensure WSC and DOL fields are coordinated to provide the desired external bus waveforms. BCD and DOL fields should always get the same value when configured. For example, if BCD field is programmed to 01, DOL field should be programmed to 0001 and if BCD field is programmed to 10, DOL field should be programmed to 0010. BCM bit in WEIM configuration register has priority over the BCD field. If BCM = 1, BCLK runs at full frequency on every memory access (both with SYNC=1 and with SYNC=0). BCM bit is used mainly for system debug mode. It has no functional use of WEIM. 17.6.5 Burst Clock Start In an effort to allow greater flexibility in achieving minimum number of wait states on bursted accesses, user can determine when they want the BCLK to start toggling. This allows BCLK to be skewed from point of data capture on the AHB clock by any number of AHB clock phases. Care must be exercised when setting BCS field in conjunction with the BCD, WSC, and DOL fields. See external timing diagrams from Section 17.8.4, “Burst Memory Accesses Timing Diagrams” for some examples of how to use the BCS, BCD, WSC, and DOL fields together. 17.6.6 Page Mode Emulation Setting PME and SYNC bits causes WEIM to perform memory bursted accesses by emulating page mode operation. LBA signal remains asserted for entire access, burst clock does not send a signal, and the external address asserts when each access are made. The initial access timing is dictated by the WSC field, and the page mode access timing is dictated by the DOL field. See external timing diagrams from the Section 17.8.2, “Page Mode Timing Diagrams” for some examples. WEIM can take advantage of improved page timing for sequential accesses only. Accesses that are on the page but are not sequential in MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-26 Freescale Semiconductor Wireless External Interface Module (WEIM) nature have their timing dictated by the WSC field. The page size can be set via the PSZ field to 4, 8, 16, or 32 words (word size is determined by data width of the external memory, such as the DSZ field). 17.6.7 PSRAM Mode Operation A control bit PSR is provided to enable PSRAM operation. For SYNC = 1, this bit enables a memory burst write. In this mode, WRAP bit on write time is automatically masked (CellularRAMTM SPEC wrap supports only for read accesses) unless WWU bit is set. Initial wait state value is automatically incremented on read access (see Figure 17-40 and Figure 17-41). Bit EW determines how WEIM supports ECB input. For SYNC = 1, if ECB goes to low state in middle of memory burst access then WEIM only waits; it’ll go high (WAIT mode) to continue current access; at the end of first access in memory burst it allows to wait ECB negation during PSRAM refresh insertion. Bit CRE and an unused address line can be used to drive the control register enable (CRE) memory input to load the PSRAM configuration registers. For PSR = 1, CRE bit will be driven on pin ADDR[23] in a write access time. NOTE SYNC = 0 should be used to access the PSRAM control register. 17.6.8 Multiplexed Address/Data mode A control bit MUM allows memory support with multiplexed address/data bus both in asynchronous and synchronous modes. LBN and LBH bit fields should be used for proper bus timing setup (see Figure 17-43–Figure 17-46). 17.6.9 Mixed AHB/Memory Burst Modes Support To provide mixed sequential/wrap accesses with different length, WEIM interprets burst signal and generate additional LBA signals whenever unequal address or burst boundary crossing condition appears (see section 17.6.3/17-25). PSZ field and WRAP bit should be used to notify WEIM about the current memory burst and wrap condition for proper external address generation. In case of non matching boundaries in both the memory and AHB access, WEIM starts a new memory burst access by putting address from AHB on address bus and generating LBA signal. For example, Table 17-20 shows how WEIM interprets with various types of AHB access in the case when memory is configured as 8 beat burst with wrap. 17.6.10 AHB Bus Cycles Support WEIM uses an ARM AHB slave interface. It has a 32-bit bus and supports four transfer types defined in the AHB specification (IDLE, BUSY, NONSEQ, and SEQ). NOTE Only 32-bit accesses are supported for SEQ mode. It also supports AHB transfers shown in Table 17-19. These AHB cycles will be translated into necessary cycles on the memory side. For optimal operation, ARM cache is configured to 8 beat burst with wrap, a synchronous flash and cellular RAM memory should be configured in 16 word wrap burst mode when MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-27 Wireless External Interface Module (WEIM) using a 16-bit data port, and in 8 word wrap burst mode when using a 32-bit data port. WEIM uses WRAP bit and PSZ field for support different memory configurations. The controller splits the transaction when needed in some cases (see section Section 17.6.3, “Burst Mode Memory Operation” on page 17-25). Table 17-19. AHB Burst Cycles Supported HBURST 000 001 010 011 100 101 110 111 TYPE SINGLE INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 Supported Yes Yes Yes Yes Yes Yes Yes Yes Description Single transfer Incrementing burst 4-beat wrapping burst 4-beat incrementing burst 8-beat wrapping burst 8-beat incrementing burst 16-beat wrapping burst 16-beat incrementing burst For example, Table 17-20 shows AHB bus sequential accesses breaking in to external memory bursts for memory configured to 8 beat burst with wrap and for some different AHB burst types and start addresses. LBA(X) means start memory burst access (LBA generation) from address X (all addresses in hex form). Table 17-20. External Memory Bursts Start Addresses for Some AHB Burst Accesses AHB Burst Type WRAP8 Memory Data Port Width 16-bit AHB Burst Start Address 0 LBA(0) LBA(10) 4 LBA(4) LBA(10) LBA(0) 32-bit INCR8 16-bit LBA(0) LBA(0) LBA(10) LBA(4) LBA(4) LBA(10) LBA(20) 32-bit LBA(0) LBA(4) LBA(20) WRAP4 16-bit 32-bit LBA(0) LBA(0) LBA(4) LBA(4) LBA(0) INCR4 16-bit LBA(0) LBA(4) LBA(10) 32-bit LBA(0) LBA(4) 8 LBA(8) LBA(10) LBA(0) LBA(8) LBA(8) LBA(10) LBA(20) LBA(8) LBA(20) LBA(8) LBA(8) LBA(0) LBA(8) LBA(10) LBA(8) C LBA(C) LBA(10) LBA(0) LBA(C) LBA(C) LBA(10) LBA(20) LBA(C) LBA(20) LBA(C) LBA(C) LBA(0) LBA(C) LBA(10) LBA(C) LBA(10) LBA(10) LBA(10) LBA(20) LBA(10) LBA(10) LBA(10) LBA(10) LBA(20) 10 LBA(10) LBA(0) 14 LBA(14) LBA(0) LBA(10) LBA(14) LBA(14) LBA(20) LBA(30) LBA(14) LBA(20) LBA(14) LBA(14) LBA(10) LBA(14) LBA(20) LBA(14) LBA(20) 18 LBA(18) LBA(0) LBA(10) LBA(18) LBA(18) LBA(20) LBA(30) LBA(18) LBA(20) LBA(18) LBA(18) LBA(10) LBA(18) LBA(20) LBA(18) LBA(20) 1C LBA(1C) LBA(0) LBA(10) LBA(1C) LBA(1C) LBA(20) LBA(30) LBA(1C) LBA(20) LBA(1C) LBA(1C) LBA(10) LBA(1C) LBA(20) LBA(1C) LBA(20) Some examples are shown in Figure 17-32 to Figure 17-39. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 17-28 Freescale Semiconductor Wireless External Interface Module (WEIM) 17.6.11 DTACK Mode It is a mode where WEIM timing depends on DTACK input signal. This signal may be used in two ways: by posedge sensitive or by level sensitive (with an initial insensitiveness time). Posedge sensitive mode is set by WSC=111111 (EW=0) and selects DTACK input as access length control sign (instead of default WSC counter). It means that access length is determined by DTACK length. WEIM begins deasserting control signals after approximately 1.5 clock (synchronization delay) in the sequence according to negation control fields. NOTE It may be required to program CSA and/or CSN fields for a correct word access to 16 or 8-bit port in this mode if corresponding module is CS sensitive. CSN maximum value is 6 for this case. Level sensitive mode is set by EW=1 (WSC < 111111). The access length is controlled by WSC. In this case, WEIM begins access (by CS assertion) and after some clocks (according to DCT field) checks DTACK input. If DTACK is low, WEIM waits for DTACK high state and reload wait state counter (see Figure 17-27 and Figure 17-28). For sequential AHB accesses, where CS doesn’t negates during burst, DTACK is being checked on the first access only. Glue logic Enabled by AGE bit of the CSCRxA register can be used for noisy or slowly rising DTACK. Refer AGE bit description for more details. 17.6.12 Internal Input Data Capture In typical case, input data is not sampled by WEIM but it is sampled by AHB master on the rising edge of HCLK when HREADY is high. WEIM assert HREADY signal to AHB master (according to WSC or DOL count). This allows better performance on the data path. There are 2 cases by which input data gets sampled inside the WEIM. First one is when an access size is larger then a port size. In this case, WEIM samples all Data coming from the memory device except the last one. For example, if there is a word access to the byte wide memory, WEIM captures first three input bytes internally and drive them together with the last byte to AHB master (last byte is not sampled in WEIM). WEIM captures data by rising edge of HCLK when WSC (or DOL if it is a part of burst) time expires and (if it depends) suitable ECB or DTACK input condition. Second case is when a feedback clock is used (FCE=1) for synchronous burst. Data will be sampled on the rising edge of the feedback clock (when WSC or DOL time expires and input condition kept) and then those captured data is again sampled by HCLK before it will be driven to the AHB master. 17.6.13 Error Conditions The following conditions cause an error signal: • Access to a disabled chip select (access to a mapped chip select address space where CSEN bit in the corresponding chip select control register is clear) • Write access to a write-protected chip select address space (WP bit in the corresponding chip select control register is set) • User access to a supervisor-protected chip select address space (the SP bit in the corresponding chip select control register is set) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 17-29 Wireless External Interface Module (WEIM) • • • • User read or write access to a chip select control register or the WEIM configuration register Byte or halfword access to a chip select control register or the WEIM configuration register DTACK acknowledge is absent more then 1024 clock WAIT deassertion more then 1024 clock. 17.7 Initialization/Application Information WEIM is ready to work with CS0 after hardware reset, but it has been configured for very slowly access (for boot purpose) without additional setup and hold time. Other CS are disabled by hardware reset. So any CS has to be properly initialized before using it by writing values to high and low configuration register. Example 17-1 shows how to prepare WEIM and 16-bit flash memory to work in the synchronous mode. Example 17-1. WEIM and Flash Memory Initialization for Work in Synchronous Mode @; config WEIM to Async access with EDC, OEA, RWA, RWN, EBC, 16 bit port and PSR WRITE WEIM_CSCR2U, 0x12020802 WRITE WEIM_CSCR2L, 0x80330d03 @ ; config flash to WRAP 8 mode (by half word accesses) WRITE_H (CS2_BASE_ADDR+0x2384), 0x60 @ ; offset = 0x11c2 = tRP >= tRC DATAA PRE-ALL REFA REFA DQ[31:0] DATAA Figure 18-35. Hardware Refresh Timing Diagram CLK32 HCLK HADDR HWRITE HRDATA HREADY SDCLK MA[1x:0] tRP (Minimum) tRC (Minimum) SDRAMx ROWx COMMAND CSDx DQ[31:0] PRE-ALL REFA ACT Figure 18-36. Hardware Refresh with Pending Bus Cycle Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-48 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) Figure 18-35 illustrates 2 refresh sequence. Burst transfers in progress when the refresh request arrives are allowed to complete prior to the refresh operation. SDRAM bus accesses queued after the refresh request are held off until refresh completes. In Figure 18-36, an access is queued just as the refresh begins. This cycle is delayed until the precharge and single refresh (REFR=01) cycles are run. Bus cycles targeted to other memory or peripheral devices are allowed to progress normally while the refresh is in progress. None of the pins shared between the SDRAM and other devices are required for the refresh operation. NOTE Since REFRESH commands (requires all banks to be in IDLE state, achieved by PRECHARGE ALL) are issued automatically by Enhanced SDRAM Controller at each 32 kHz clock, address bits A10 (for both 16 and 32-bit devices) cannot be shared with other peripherals address bus in the system. 18.4.5 Low Power Operating Modes This section describes low power operating modes of Enhanced SDRAM Controller as a function of various memory devices. Table 18-26 lists and summarizes low power modes supported by Enhanced SDRAM Controller. Table 18-26. ESDRAMC Low Power Operating Modes Memory Device System Operating Mode Memory Device Low Power Operating Mode SDRAM RUN RUN RUN STOP LPDDR RUN RUN RUN STOP 1 WakeUp Penalty 1 clock cycle 1 clock cycle 2 Refresh Period 2 Refresh Period tXP 1 clock cycle tXS + 2 Refresh Period tXS + 2 Refresh Period POWER DOWN MODE PRECHARGE BANK(s) MANUAL SELF REFRESH (SMODEx=100) MODE1 SELF REFRESH MODE POWER DOWN MODE PRECHARGE BANK(s) MANUAL SELF REFRESH MODE (SMODEx=100) SELF REFRESH MODE SDCLK stops, only if both chip selects are in manual self refresh mode. 18.4.5.1 Self Refresh Mode for SDRAM/LPDDR Devices This operating mode (see Figure 18-37 and Figure 18-38) allows the software/user to control a Self refresh mode entry of the external SDRAM/LPDDR device if refresh has been enabled, during system RUN mode. When this mode is selected (SMODE=100 in the respective CSD control register) and refresh is enabled the Enhanced SDRAM Controller will complete any active access and a self refresh command to the external device will be issued. No access is allowed to the respective CSD during manual self refresh mode. If refresh has not been enabled, the Enhanced SDRAM Controller places the memory in a low MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-49 Enhanced SDRAM Controller (ESDRAMC) power consumption mode known as power down. The LPACK signal (low power mode acknowledge) will not be asserted if only one CSD enters manual self refresh mode. P_LPMD SYSTEM IN Sleep Mode LPACK HCLK HADDR HWRITE HWDATA HREADY SDCLK CKEx ADDR RAS, CAS, SDWE CSDx MA10=1 tRP (Minimum) PRE-ALL ROWx ROWx REF A WACK SDRAM Self Refresh Mode Entry Figure 18-37. SDRAM/LPDDR Enter Self Refresh Mode During System Sleep Mode MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-50 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) P_LPMD SYSTEM IN RUN MODE LPACK HCLK HADDR HWRITE HWDATA HREADY SDCLK CKEx tXS (Minimum) ADDR RAS, CAS, SDWE CSDx tRP (Minimum) REF A ROWx REF A WACK SDRAM Self Refresh Mode Exit Figure 18-38. SDRAM/LPDDR Exit Self Refresh Mode During System Sleep Mode 18.4.5.2 Manual Self Refresh Mode for SDRAM/LPDDR Devices This operating mode allows the software/user to control a Self refresh mode entry of the external SDRAM/LPDDR device if refresh has been enabled, during the system RUN mode. When this mode is selected (SMODE=100 in the respective CSD control register) and refresh is enabled the Enhanced SDRAM Controller will complete any active access and a self refresh command to the external device will be issued. No access is allowed to the respective CSD during manual self refresh mode. If refresh has not been enabled, the Enhanced SDRAM Controller places the memory in a low power consumption mode known as power down. The LPACK signal (low power mode acknowledge) will not be asserted if only one CSD enters manual self refresh mode. NOTE Manual precharge all should be initiated by user before manual self refresh. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-51 Enhanced SDRAM Controller (ESDRAMC) To exit manual self refresh mode, a different operating mode need to be selected by changing SMODE bits in the respective chip select control register. When a different mode is selected, the controller will take the SDRAM device out of self refresh mode and will begin issuing auto refresh cycles (if the refresh has been enabled). illustrates the entry and exit from manual self refresh mode. See Figure 18-39 and Figure 18-40 for timing information. LPACK HCLK HADDR ESDCTL0 HWRITE HWDATA SMOD=SREF HREADY SDCLK CKEx MA[1x:0] RAS, CAS, SDWE CSDx REFRESH SDCLK stops only if both CS enter Manual Self Refresh Mode SDRAM Self Refresh Mode Entry due to manual self refresh Figure 18-39. Manual Self Refresh Entry Timing Diagram NOTE SDCLK stops, only if both chip selects are in manual self refresh. This is in order to allow the usage of one chip select, while the other is in manual self refresh (in case that both chip selects are in use). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-52 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK LPACK HADDR ESDCTL0 HWRITE HWDATA SMOD!=SREF HREADY SDCLK CKEx MA[1x:0] RAS, CAS, SDWE CSDx >= tRC + 1 Clock NOP NOP NOP REF A SDRAM Self Refresh Mode Exit due to manual self refresh Figure 18-40. Manual Self Refresh Exit Timing Diagram 18.4.5.3 18.4.5.3.1 Precharge Power Down Mode SDRAM Precharge Power Down Mode All low power operating mode described in the above paragraphs will be activated only if the system enters low power operating mode, for example, Sleep Mode. Enhanced SDRAM Controller has the capability to reduce power consumption if SDRAM/LPDDR memory utilization is low, by setting SDRAM device in Power Down Mode. This mode is activated through the PWDT bits in ESDCTL0 and/or ESDCTL1 registers. During this operating mode, ESDRAMC automatically issues the REFRESH commands toward the SDRAM/LPDDR memories at the rate defined by SREFR bits in ESDCTL0 and/or ESDCTL1 registers. Programming PWDT[1:0] = 01 causes Enhanced SDRAM Controller to place the memories in power down mode at anytime the controller detects that no banks are active. This mode is useful in MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-53 Enhanced SDRAM Controller (ESDRAMC) applications where a memory array is accessed infrequently and chances of another access to same page are minimal. Reading or writing to memory activates a page within the addressed bank. Reset, software generated precharge, and hardware initiated refresh are three ways to close an active bank. The periodically occurring refresh will be the normal means that invokes the power down mode. At each refresh interval, all banks will be closed by a precharge-all command, followed by the refresh operation. The controller will then issue the power down command to the memories. A few cycle delay is incurred with the first read or write cycle in order to restart the clocks, but only on the first cycle. After that, the clocks will continue to run until the next refresh operation or until any active banks are manually precharged. Page misses on read and write cycles cause the addressed bank to be closed (precharged) and a new page opened within the bank. This operation does not cause the clocks to stop, nor does manually precharging only a single bank within the memory. All banks within the memory must be inactive before the power down mode is invoked. Power Down Mode occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT, when no accesses are in progress. Entering power down will deactivate the input and output buffers (excluding CKE) of the device. The Power Down Mode state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge. For SDR SDRAM, Figure 18-41 and Figure 18-42 illustrates the power down mode entry and exit respectively. For LPDDR SDRAM, Figure 18-43 and Figure 18-44 illustrates the power down mode entry and exit respectively. PWDT PWDT=00 PWDT=01 HCLK HADDR HWRITE HWDATA HREADY SDCLK CKEx MA[1x:0] RAS, CAS, SDWE CSDx Power Down Mode Entry tRP (Minimum) PRE-ALL REF A NOP ROWx Figure 18-41. SDR SDRAM Precharge Power Down Mode Entry Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-54 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) NOTE Since ESDRAMC doesn’t issue AUTO PRECHARGE commands toward the SDRAM, software will have to issue a PRECHARGE ALL command in order to enter Precharge Low Power Down Mode, to wait for PRECHARGE timer (PRCT) to close/precharge all active banks, or to wait for the next REFRESH cycle in order to enter this low power mode. (During the REFRESH cycle, the ESDRAMC automatically issue the PRECHARGE ALL command). HCLK HADDR ADDRA ADDRB HWRITE HRDATA DATAA HREADY SDCLK CKEx MA[1x:0] RAS, CAS, SDWE CSDx ROWA tRCD Minimum NOP ACT COLUMNA COLUMNA tCAS=2 COLUMNB SDRAMx READ TBST NOP NOP READ DQ DATAA Power Down Mode Exit Figure 18-42. SDR SDRAM Precharge Power Down Mode Exit Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-55 Enhanced SDRAM Controller (ESDRAMC) PWDT PWDT=00 PWDT=01 HCLK HADDR HWRITE HWDATA HREADY SDCLK SDCLK CKEx MA[1x:0] RAS, CAS, SDWE CSDx Power Down Mode Entry tRP (Minimum) PRE-ALL REF A NOP ROWx Figure 18-43. Mobile DDR SDRAM Precharge Power Down Mode Entry Timing Diagram Power Down Mode for several Mobile/Low Power DDRs require the clock CK (and CK) to continue running. (The PWR CK EN (Power Down Clock Enable for Mobile/Low Power DDR SDRAM) should be set to “1” in order to enable this option) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-56 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR ADDRA ADDRB HWRITE HRDATA 2 x DATAA HREADY SDCLK SDCLK CKEx MA[1x:0] tXP RAS, CAS, SDWE CSDx NOP ROWA tRCD Minimum ACT COLUMNA COLUMNA tCAS=2 COLUMNB SDRAMx READ TBST NOP NOP READ DQ Power Down Mode Exit DQS DA DA DB Figure 18-44. Mobile DDR SDRAM Precharge Power Down Mode Exit Timing Diagram 18.4.5.4 18.4.5.4.1 Active Power Down Mode SDRAM/LPDDR Active Power Down Mode The second clock suspend mode is selected whenever PWDT[1:0] = 1x. In this mode the SDCLK is stopped after a selectable delay from the last access to the array. Active banks are not closed prior to disabling the SDRAM/LPDDR clock. Either 64 (PWDT[1:0] = 10) or 128 (PWDT[1:0] = 11) cycle delays are possible. SDRAM/LPDDR clocks are counted from the end of the last read or write access. Subsequent read or write accesses, and self-refresh modes reset the counter. Auto-refresh cycles do not affect the counter; however, if the counter expires during a refresh operation the clock will be disabled immediately following the refresh. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-57 Enhanced SDRAM Controller (ESDRAMC) The distinguishing factor between Precharge Power Down Mode and Active Power Down Mode is whether banks remain active while the clock is stopped. Active Power Down allows banks to remain activated, while Precharge Power down does not. Figure 18-45 and Figure 18-46 illustrates SDR and LPDDR SDRAM Active Power Down Mode entry and exit timing diagram. HCLK HADDR ADDRB HWRITE HRDATA DATAA HREADY SDCLK CKEx 64 Clocks MA[1x:0] C0LUMNA RAS, CAS, SDWE CSDx C0LUMNA tCAS = 2 READ TBST NOP READ C0LUMNB SDRAMx DQ DATAA SDRAM Active Power Down Mode Entry SDRAM Active Power Down Mode Exit Figure 18-45. SDR SDRAM Active Power Down Mode Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-58 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR ADDRB HWRITE HRDATA 2 x DATAA HREADY Clocks will continue running for PWR_CLK_EN=”1” SDCLK SDCLK Clocks will stop running for PWR_CLK_EN=”0” SDCLK SDCLK CKEx 64 Clocks MA[1x:0] C0LUMNA RAS, CAS, SDWE CSDx C0LUMNA tCAS = 2 READ TBST NOP tXP C0LUMNB SDRAMx READ DQ DA DA DQS LPDDR SDRAM Active Power Down Mode Entry LPDDR SDRAM Active Power Down Mode Exit Figure 18-46. Mobile DDR SDRAM Active Power Down Mode Timing Diagram Power Down Mode for several Mobile DDRs require the clock CK (and CK) to continue running. (The PWR CK EN (Power Down Clock Enable for Mobile DDR SDRAM) should be set to “1” in order to enable this option) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-59 Enhanced SDRAM Controller (ESDRAMC) 18.4.5.5 Precharge Bank(s)—Low Power Mode “Closing” (due to precharge command) the last used/open row in any non active bank within a chip select reduces the power consumption of the external memory device. The power saving is device dependent, and one should consult/examine the external memory device specification for more details on power consumption reduction. The precharge bank is activated if PRCT is enabled. A PRECHARGE command is issued after 2xPRCT clocks (HCLK, up to 133 MHz) of no activity (as shown in Table 18-12) to one of the SDRAM/LPDDR banks. The number of cycles before the PRECHARGE command is issued depends on command bus (WE, RAS, CAS and CSD) availability (means there is no active access to other bank) and the memory timing parameters. 18.4.5.6 LPDDR Frequency Change The following steps need to be performed prior to a frequency change in a LPDDR based system, in order for the DDRC delay line re-calibration.locking. 1. Issue PRECHARGE_ALL command. 2. Enter the external memories in SELF_REFRESH operating mode. 3. Change system frequency. 4. Reset the delay line, by setting the MDDR_DL_RST bit in the ESDRAMC MISC register. 5. Wait ~4500 HCLK cycles in order for the delay line to lock on the new frequency. 6. Exit SELF_REFRESH mode. After the above 6 steps are performed the LPDDR is ready for normal operation at the new frequency. 18.4.6 SDRAM (SDR and LPDDR) Command Encoding Table 18-27 summarizes the command encoding utilized by this controller. These commands represent a subset of the commands defined by the JEDEC standard. Table 18-27. SDRAM (SDR and LPDDR) Command Encoding Function Deselect No Operation Read Write Bank Activate Burst Terminate1 Precharge Select Bank Precharge All Banks Auto-Refresh Self Refresh Entry Symbol DSEL NOP READ WRIT ACT TBST PRE PALL CBR SLFRSH CKE n-1 H H H H H H H H H H CKE n X X X X X X X X X L CS H L L L L L L L L L RAS X H H H L H L L L L CAS X H L L H H H H L L WE X H H L H L L L H H A11 X X V V V X V X X X A10 X X L L V X L H X X BA[1:0] X X V V V V V X X X A[13:0] X X V V V X X X X X MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-60 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) Table 18-27. SDRAM (SDR and LPDDR) Command Encoding (continued) Function Self Refresh Exit Power-Down Entry Power-Down Exit Mode Register Set2 1 2 Symbol SLFRSHX PWRDN PWRDNX MRS CKE n-1 L H L H CKE n H L H X CS H X H L RAS X X X L CAS X X X L WE X X X L A11 X X X L A10 X X X L BA[1:0] X X X V A[13:0] X X X V For Mobile DDR, applies only to read bursts (with auto precharge disabled). BA0–BA1 select either the mode register, the extended mode register or the LOW POWER extended mode register. 18.4.6.1 Reset Assertion of the RST signal initializes the controller into the idle state, and disables the module. While disabled, the controller remains in the idle state with the internal clocks stopped. The reset state of the control register allows for basic read/write operations sufficient to fetch the reset vector and execute the initialization code. A complete initialization of the controller should be performed as part of the start-up code sequence. Read/write cycles, refresh and low-power mode requests, and Power Down time-outs will all trigger transitions out of the idle state. As shown in the simplified Enhanced SDRAM Controller state diagram pictured in Figure 18-47, state transitions due to a read or write request depend on the operating mode. Other transitions require the corresponding function to be enabled in the ESDCTL registers. Some state transitions have been removed from the figure to minimize complexity and allow an easier understanding of the basic controller operation. The following subsections document the operation of each of the operating modes. 18.4.7 Normal READ/WRITE Mode The Normal Read/Write mode (SMODE = 000) is used for general read and write accesses (AHB light compliant) to the SDRAM/LPDDR. Single and read burst accesses are supported for both SDRAM/LPDDR memories (although bursts requests are limited as shown in Table 18-28). For SDRAM/LPDDR memories single and burst write accesses are supported as well. Read or write requests to Enhanced SDRAM Controller initiate a check to see whether the page is already open. This check consists of comparing request address against last row accessed within the corresponding bank. If the rows are different, a precharge has occurred since the last access, or there has never been an access to the bank, then the access must follow the “off-page” sequence. If the requested and last row match, the shorter “on-page” access is used. An off-page sequence must first activate the requested row, an operation which is analogous to a conventional DRAM RAS cycle. An activate cycle is the first operation depicted in Figure 18-48. During the activate cycle, the appropriate chip select is driven low, the row addresses are placed on the multiplexed address pins, the non-multiplexed addresses are driven to their respective values, write enable is driven high, CAS is driven high, and RAS is driven low. These latter three pins form the SDRAM command word. The data bus is unused during the activate command. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-61 Enhanced SDRAM Controller (ESDRAMC) Power On AutoRefresh reset Refresh Request Power Down Read or Write Idle Power Down or (Stop and REFR=0) Stop and REFR!= 0 Self Refresh Mode Reg Set NOP Mode Register Set Pre_Cmd and A10=0 Pre_Cmd and A10=1 Precharge All Precharge Bank Read or Write (Normal) Refresh Request or Stop Page Miss Power down Row Active Read or Write Read Burst Active Power Down Write NOP Write Burst Burst Read Figure 18-47. Simplified Enhanced SDRAM Controller State Diagram Once the selected row has been activated, the read operation begins after the row to column delay (tRCD) has been met. This delay is either 2 or 3 clocks, as determined by the tRCD control field. During the read cycle, the chip select is once again asserted, the column addresses are driven onto the multiplexed address bus, the non-multiplexed addresses remain driven to the value presented during the activate cycle, the write enable is driven high (read), RAS is driven high, and CAS is driven low. After the CAS latency has expired, data is transferred across the data bus. CAS latency is programmable via the tCAS control field. As data is being returned across the AHB, transfer acknowledge is asserted back to the CPU indicating that the CPU should latch data. While data is still on the bus, the Enhanced SDRAM Controller must begin monitoring transfer request since the CPU is free to issue the next bus request on the same edge that data is being latched. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-62 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) Table 18-28. SDRAM/LPDDR Burst Access Support Internal AHB WORD Access (32bit) HBURST 000 001 010 011 100 101 110 111 1 External Memory Device3 16-Bit BL=4 No No No No No No No No BL=8 Yes Yes Yes Yes Yes Yes No No BL=FP Yes Yes Yes Yes Yes Yes No No BL=4 Yes Yes Yes Yes Yes Yes No No 32-Bit BL=8 Yes Yes Yes Yes Yes Yes No No BL=FP2 Yes Yes Yes Yes Yes Yes No No Single transfer Incrementing burst 4-beat wrapping burst 4-beat incrementing burst 8-beat wrapping burst 8-beat incrementing burst 16-beat wrapping burst 16-beat incrementing burst Description TYPE SINGLE1,2 INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 ESDCTL supports only burst of 32-bit (word size). Byte (8 bits) or half words (16 bits) accesses are supported only in case of single transfer (SINGLE). The ESDCTL automatically splits (see example in Table 18-29) the AHB bursts as a function of the external memory device, configured via the ESDCTL configuration registers (size and burst length), in such a way that a continuous flow of data is obtained (for both READ or WRITE bursts). 2 BL = Burst Length field in device mode register; FP = Full Page (wrap at external memory device ROW boundary). For both LPDDR 16 and 32-bit devices only BL=8 is supported. Data transfers can be either single operand or a burst (WRAP or INCR) of up to a full page. Burst requests are designated as such by the HBURST bus indicating the length of the access, When HBURST equal to 0 a single access is required, otherwise the access is a burst of HBURST words. SDRAM memories assume that all transfers are burst transfers unless terminated early. Burst transfers can be terminated by a variety of mechanisms: another read or write cycle, a precharge operation, or through a burst terminate command. Burst terminate commands are the general mechanism used by the ESDCTL for early burst termination, The burst terminate command is subject to the CAS latency and must be pipeline similar to the Read command, as shown in Figure 18-48 to Figure 18-68. NOTE The signals displayed in are internal signals, that is, interface signals between the M3IF and the ESDRAMC. All those figures are not cycle accurate and meant to show mainly the external pins activity. For cycle accurate diagrams, refer to Figure 18-70 to Figure 18-72. SDRAM write cycles are different than read cycles in one important aspect. Whereas read data was delayed by the CAS latency, write data has no delay and is supplied at the same time as the Write command. Figure 18-56 illustrates an off-page write cycle followed by one that hits on-page. Note that the write data is driven during the same clock that the Write command is issued. A Burst Terminate command cancels the burst operation, but again without the CAS latency. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-63 Enhanced SDRAM Controller (ESDRAMC) NOTE ESDRAMC handles the HUNALIGN accesses in the following way. The M3IF module converts the original access address to a word align address toward the ESDRAMC. The HBSTRB are used by the ESDRAMC to drive the correct value on the DQM signals toward the external memory. HCLK HADDR HWRITE HRDATA HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx DQ[31:0] Signals for LPDDR DQ[15:0] DQS DATAA DATAA DATAA ROWA tRCD Minimum ADDRA ADDRB DATAA COLUMNA COLUMNA tCAS SDRAMx COLUMNB ACT READ TBST NOP NOP NOP READ SDCLK Figure 18-48. SDR and LPDDR Off-Page Single Read Timing Diagram (32-Bit Memory for SDR and 16-Bit for LPDDR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-64 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HRDATA HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx DQ[31:0] Signals for LPDDR COLUMNA COLUMNA tCAS SDRAMx ADDRA ADDRB DATAA COLUMNB READ TBST NOP NOP NOP READ DATAA DQ[15:0] DQS SDCLK DATAA DATAA Figure 18-49. SDR and LPDDR On-Page Single Read Timing Diagram (32-Bit Memory for SDR, 16-Bit for LPDDR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-65 Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HRDATA HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx DQ[31:0] DATAA1 DATAA2 DATAA3 DATAA4 ROWA tRCD Minimum ADDRA ADDRB DATAA1 DATAA2 DATAA3 DATAA4 COLUMNA tCAS=2 COLUMNB ACT READ NOP NOP NOP NOP READ Signals for LPDDR DQ[15:0] DQS DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 SDCLK Figure 18-50. SDR and LPDDR Off-Page Burst Read Timing Diagram (32-Bit Memory for SDR or 16-Bit for LPDDR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-66 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HRDATA [31:0] HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx ROWA tRCD Minimum ADDRA DATAA1 DATAA2 DATAA3 DATAA4 DATAA5 DAT COLUMNA tCAS=2 ACT READ NOP NOP NOP NOP Signals for MDDR DQ[31:0] DQS SDCLK DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 Figure 18-51. AHB 32-Bit read from a LPDDR: Off-Page Burst Read Timing Diagram (32-Bit) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-67 Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HRDATA [63:0] HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx ROWA tRCD Minimum ADDRA ADDRB DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 COLUMNA tCAS=2 COLUMNB ACT READ NOP NOP NOP NOP READ Signals for LPDDR DQ[31:0] DQS SDCLK DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 Figure 18-52. AHB 64-Bit read from a LPDDR: Off-Page Burst Read Timing Diagram (32-Bit) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-68 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HRDATA HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx DQ[31:0] Signals for LPDDR DATAA1 DATAA2 DATAA3 DATAA4 COLUMNA tCAS=2 READ NOP NOP NOP NOP READ COLUMNB DATAA1 DATAA2 DATAA3 DATAA4 ADDRA ADDRB DQ[15:0] DQS SDCLK DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 Figure 18-53. SDR and LPDDR On-Page Burst Read Timing Diagram (32-Bit Memory for SDR and 16-Bit for LPDDR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-69 Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HREADY SDCLK MA[1x:0] COLn D1n D2n D3n D4n A1n A2n A3n A4n COMMAND DQ[15:0] DQM[1:0] READ NOP SCL NOP NOP NOP NOP NOP NOP NOP NOP D1n D1n+1 D2n D2n+1 D3n D3n+1 D4n D4n+1 Figure 18-54. On-Page Burst Read Timing Diagram (16-Bit Memory for SDR, LPDDR 8-Bit Is Not Supported) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HREADY SDCLK MA[1x:0] BANK, ROW A1n A2n A3n A4n D1n D2n D3n D4n BANK,COLn SRCD COMMAND ACTIVE NOP READ NOP SCL NOP NOP NOP NOP NOP NOP NOP NOP DQ[15:0] DQM[1:0] D1n D1n+1 D2n D2n+1 D3n D3n+1 D4n D4n+1 Figure 18-55. Off-Page Burst Read Timing Diagram (16-Bit Memory, LPDDR 8-Bit Is Not Supported) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-70 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HWDATA HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx DQ[31:0] DATAA DATAB ROWA tRCD ACT WRITE TBST WRITE TBST COLUMNA COLUMNA COLUMNB COLUMNB SDRAMx DATAA DATAB ADDRA ADDRB Figure 18-56. SDR Off-Page Write Followed by On-Page Write Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-71 Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HWDATA [31:0] HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx ROWA tRCD ACT WRITE NOP WRITE NOP COLUMNA COLUMNA COLUMNB COLUMNB SDRAMx DATAA DATAB ADDRA ADDRB Signals for LPDDR DQ[15:0] DQM DA DA DA DA DB DB DB DB DQS SDCLK Figure 18-57. LPDDR Off-Page Write Followed by On-Page Write Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-72 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HWDATA HREADY SDCLK MA[1x:0] BANK,ROWn SRCD BANK,COLn D1n D2n D3n D4n A1n A2n A3n A4n COMMAND DQ[31:0] LPDDR Signals ACTIVE NOP WRITE D1n NOP D2n NOP D3n NOP D4n DQ[15:0] DQS SDCLK D1n D2n D3n D4n D5n D6n D7n Figure 18-58. Off-Page Burst Write Timing Diagram (32-Bit Memory for SDR and 16-Bit for LPDDR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-73 Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HWDATA [63:0] HREADY SDCLK MA[1x:0] BANK,ROWn SRCD BANK,COLn D1n D2n D3n D4n D5n D6n D7n D8n A1n A2n A3n A4n COMMAND ACTIVE NOP WRITE NOP NOP NOP LPDDR Signals DQ[31:0] DQS SDCLK D1n D2n D3n D4n D5n D6n D7n Figure 18-59. AHB 64-Bit Write to LPDDR: Off-Page Burst Write Timing Diagram (32-Bit Memory) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-74 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR A1n A2n A3n A4n A5n A6n A7n A8n HSEL_CSx HWRITE HWDATA [63:0] HREADY SDCLK MA[1x:0] BANK,ROWn SRCD BANK,COLn D1n D2n D3n D4n D5n D6n D7n D8n COMMAND ACTIVE NOP NOP WRITE NOP NOP NOP LPDDR Signals DQ[31:0] DQS SDCLK D1n D2n D3n D4n D5n D6n D7n D8n Figure 18-60. AHB 32-Bit write to LPDDR: Off-Page Burst Write Timing Diagram (32-Bit Memory) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-75 Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HWDATA HREADY SDCLK MA[1x:0] COLn A1n A2n A3n A4n D1n D2n D3n D4n COMMAND DQ[31:0] LPDDR Signals DQ[15:0] DQS[1:0] SDCLK WRITE NOP NOP NOP D1n D2n D3n D4n D1n D2n D3n D4n D5n D6n D7n D8n Figure 18-61. On-Page Burst Write Timing Diagram (32-Bit Memory for SDR and 16-Bit for LPDDR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-76 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSER_CSx HWRITE A1n A2n A3n A4n HWDATA HREADY SDCLK MA[1x:0] D1n D2n D3n D4n ROWn COLn SRCD COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP NOP DQ[15:0] DQM[1:0] D1n D1n+ D2n D2n+ D3n D3n+ D4n D4n+ Figure 18-62. Off-Page Burst Write Timing Diagram (SDR 16-bit Memory, LPDDR 8-Bit is Not Supported) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-77 Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HWDATA HREADY SDCLK MA[1x:0] COLn D1n D2n D3n D4n A1n A2n A3n A4n COMMAND WRITE NOP NOP NOP NOP NOP NOP NOP DQ[15:0] DQM[1:0] D1n D1n+ D2n D2n+ D3n D3n+ D4n D4n+ Figure 18-63. On-Page Burst Write Timing Diagram (SDR 16-Bit Memory, LPDDR 8-Bit Memory is Not Supported) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-78 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HWDATA HREADY SDCLK MA[1x:0] ROW SRCD ACTIVE NOP BANK,COL1 BANK,COL2 D1 D2 A1 A2 COMMAND DQ[31:0] WRITE TBRST READ TBRST SCL D1 D2 Figure 18-64. SDR Single Write followed by On-Page Read Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-79 Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HWDATA HREADY SDCLK MA[1x:0] ROW SRCD ACTIVE NOP BANK,COL1 NOP BANK,COL2 NOP D1 D2 A1 A2 COMMAND WRITE READ TBRST SCL LPDDR Signals DQ[15:0] DQS DQM SDCLK_B D1 D1 D1 D1 D2 D2 Figure 18-65. LPDDR Single Write Followed by On-Page Read Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-80 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HWDATA HREADY SDCLK MA[1x:0] BANK,ROWn SRCD ACTIVE NOP BANK,COLn BANK,COLb D1n D2b A1n A2b COMMAND READ TBRST SCL NOP NOP NOP WRITE TBRST DQ[31:0] DQM[3:0] D1n D2b Figure 18-66. SDR Single Read Followed by On-Page Write Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-81 Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HWDATA HREADY SDCLK MA[1x:0] BANK, ROWn A1n A2b D1n D2b BANK,COLn BANK,COLb COMMAND SRCD ACTIVE NOP READ TBRST SCL NOP NOP NOP WRITE NOP NOP LPDDR Signals DQ[15:0] DQS DQM[3:0] SDCLK_B D1n D1n D2b D2b D2b D Figure 18-67. LPDDR Single Read Followed by On-Page Write Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-82 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HWDATA HREADY SDCLK MA[1x:0] BANK, ROW A1n A2n A3n A4n A1b D1n D2n D3n D4n D1b BANK,COLn BANK,COLb SRCD COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP WRITE TBRST SCL DQ[31:0] DQM[3:0] D1n D2n D3n D4n D1b Figure 18-68. SDR Burst Read Followed by On-Page Write Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-83 Enhanced SDRAM Controller (ESDRAMC) S1 HCLK HADDR HSEL_CSx HWRITE HRDATA HWDATA HREADY SDCLK MA[1x:0] BANK,ROW BANK,COLn A1n A2n A3n A4n A1b D1n D2n D3n D4n D1b BANK,COLb SRCD COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP WRITE NOP SCL LPDDR Signals DQ[31:0] DQM[3:0] DQS SDCLK D1n D2n D3n D4n D5n D6n D7n D8n D1b D1b Figure 18-69. LPDDR Burst Read Followed by On-Page Write Timing Diagram 18.4.7.1 SDR Cycle Accurate Enhanced SDRAM Controller Accesses This section provides cycle accurate timing diagrams for several ESDRAMC (AMBA AHB Lite) supported read and write accesses to both 16 and 32-bit data width SDR memory devices from only one master. This diagrams are provided to emphasis ESDRAMC performance for single master hit (ACTIVE row) requests. The CAS latency for all diagrams is 2 cycles and burst length is set to 4 words for 16-bit memory and 8 words for 32-bit memory. 18.4.7.1.1 Single Read Word Access to 16-Bit Memory The markers in Figure 18-70 marks the request access time, for example, the time period between HREADY goes LOW (the ESDRAMC starts to execute the request) and HREADY goes HIGH (the ESDRAMC request execution is completed). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-84 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HTRANS HADDR HWRITE HBURST HRDATA HREADY SDCLK COMMAND DQ MA COL0 READ NOP BRST D0L D0H NOP SINGLE D0 NSEQ A0 D0L—Data bits [15:0] D0H- Data bits [31:16] Access starts here Access ends here Figure 18-70. Single on Page Read—Word Access to 16-Bit Memory (Cycle Accurate) 18.4.7.1.2 Misaligned INCR4 Burst Read Access to 16-Bit Memory The markers in Figure 18-71 marks the request access time, for example, the time period between HREADY goes LOW (the ESDRAMC starts to execute the request) and HREADY goes HIGH (the ESDRAMC request execution is completed). Two READ commands are issued toward the SDRAM memory, since the misaligned read burst crosses the 16-bit SDRAM (4 words) memory boundary. The read addresses are 0x04, 0x08, 0x0C, and 0x10. Without issuing the second read the last SDRAM data will come from address 0x00. The ESDRAMC issue the second READ command in such a way (at a specific timing) so continuous data flow is obtained. There is no timing difference between an aligned and a misaligned access although the second one requires more commands. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-85 Enhanced SDRAM Controller (ESDRAMC) COMMAND DxL—Data bits [15:0] DxH—Data bits [31:16] MA DQ HREADY HRDATA HBURST HTRANS HWRITE HADDR SDCLK HCLK NSEQ A4 Access starts here READ COLA4 D4L D4H D8L D8H COLA10 DCL DCH D10L D10H A8 INCR4 NOP D4 READ NOP D8 BRST NOP DC AC A10 Access ends here Figure 18-71. Misaligned on Page INCR4 Burst Read Access to 16-Bit Memory MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-86 Freescale Semiconductor D10 Enhanced SDRAM Controller (ESDRAMC) 18.4.7.1.3 Misaligned WRAP8 Burst Read Access to 32-Bit Memory The markers in Figure 18-72 marks the request access time, that is, the time period between HREADY goes LOW (the ESDRAMC starts to execute the request) and HREADY goes HIGH (the ESDRAMC request execution is completed). Only one READ command is issued toward the SDRAM memory, since the misaligned read burst crosses the 32-bit SDRAM memory (8 words) boundary at the memory “natural” boundary. The read addresses are 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C and 0x00. Without issuing the second read the last SDRAM data will come from address 0x00 since this is the “natural” 32-bit memory device boundary as well. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-87 Enhanced SDRAM Controller (ESDRAMC) DxL—Data bits [15:0] DxH—Data bits [31:16] MA DQ COMMAND HREADY HRDATA HBURST HTRANS HWRITE HADDR SDCLK HCLK NSEQ A4 Access starts here READ COLA4 D4 D8 DC D10 D14 D18 D1C D0 A8 WRAP8 SEQ NOP D4 D8 DC D10 D14 D18 AC A10 A14 A18 A1C Access ends here Figure 18-72. Misaligned WRAP8 Burst Read Access to 32-Bit Memory MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-88 Freescale Semiconductor D1C D0 A0 Enhanced SDRAM Controller (ESDRAMC) 18.4.7.2 Single Write Word Access to 32-Bit Memory The markers in Figure 18-73 mark the request access time, for example, the time period between HREADY goes LOW (the ESDRAMC starts to execute the request) and HREADY goes HIGH (the ESDRAMC request execution is completed). HCLK HTRANS HADDR HWRITE HBURST HWDATA HREADY SDCLK COMMAND DQ MA WRITE D0 COL0 BRST NOP SINGLE D0 NSEQ A0 Access starts here Access ends here Figure 18-73. Single on Page Write—Word Access to 32-Bit Memory (Cycle Accurate) 18.4.7.2.1 INCR4 Burst Write Word Access to 32-Bit Memory Two WRITE commands are issued toward the SDRAM memory, since the misaligned write burst crosses the 32-bit SDRAM (8 words) memory boundary. The write addresses are 0x14, 0x18, 0x1C, and 0x20. Without issuing the second write the last SDRAM data will be written to address 0x00. The ESDRAMC issue the second WRITE command in such a way (at a specific timing) so continuous data flow is obtained. There is no timing difference between an aligned and a misaligned access although the second one requires more commands. The markers in Figure 18-74 mark the request access time. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-89 Enhanced SDRAM Controller (ESDRAMC) HCLK HTRANS HADDR HWRITE HBURST HWDATA HREADY SDCLK COMMAND DQ MA WRITE D14 COLA14 D18 D1C WRITE D20 COLA20 BRST NOP D14 INCR4 D18 D1C D20 NSEQ A14 A18 SEQ A1C A20 Access starts here Access ends here Figure 18-74. INCR4 Burst on Page Write—Word Access to 32-Bit Memory (Cycle Accurate) 18.4.7.3 SDRAM Command Sequence for Burst Accesses Table 18-29 show the commands that the ESDRAMC will perform for WRAP and INCR accesses from the AHB. The controller will split the transaction when needed in cases that the access cross WRAP boundaries of the SDRAM. The memory configured to 8 beat burst (BL=8). Unspecified INCR burst accesses will be translated to single accesses to allow the burst to terminate at any length with no additional delays. The number in the brackets represent the address for READ command and the last Burst Address for BTERM command. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-90 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) Table 18-29. SDRAM Command Sequence for Burst Accesses Type Bus 0 16-bit READ(0) READ(10) WRAP8 4 READ(4) READ(10) READ(0) BTERM(0) 32-bit 16-bit READ(0) READ(0) READ(10) READ(4) READ(4) READ(10) READ(20) INCR8 32-bit READ(0) 8 READ(8) READ(10) READ(0) BTERM(4) READ(8) READ(8) READ(10) READ(20) C READ(C) READ(10) READ(0) BTERM(8) READ(C) READ(C) READ(10) READ(20) READ(10) READ(10) READ(20) Address 10 READ(10) READ(0) 14 READ(14) READ(0) READ(10) 18 READ(18) READ(0) READ(10) 1C READ(1C) READ(0) READ(10) BTERM(10) BTERM(14) BTERM(18) READ(14) READ(14) READ(20) READ(30) READ(18) READ(18) READ(20) READ(30) READ(1C) READ(1C) READ(20) READ(30) BTERM(20) BTERM(24) BTERM(28) READ(4) READ(20) READ(8) READ(20) READ(C) READ(20) READ(10) READ(20) BTERM(30) BTERM(34) BTERM(38) READ(14) READ(20) READ(18) READ(20) READ(1C) READ(20) BTERM(20) BTERM(24) BTERM(28) BTERM(2C) BTERM(30) BTERM(34) BTERM(38) 16-bit 32-bit WRAP4 BTERM(C) BTERM(10) READ(0) BTERM(4) 16-bit READ(0) READ(4) READ(10) INCR4 32-bit READ(0) READ(4) READ(8) READ(C) READ(10) READ(14) READ(20) READ(18) READ(20) READ(1C) READ(20) BTERM(C) BTERM(10) BTERM(14) BTERM(18) BTERM(1C) READ(8) READ(10) READ(0) BTERM(8) READ(C) READ(10) READ(0) BTERM(C) READ(10) READ(10) READ(10) READ(10) BTERM(10) BTERM(14) BTERM(18) READ(14) READ(20) READ(18) READ(20) READ(1C) READ(20) READ(0) READ(0) READ(4) READ(4) READ(8) READ(8) READ(C) READ(C) READ(10) READ(10) READ(14) READ(14) READ(18) READ(18) READ(1C) READ(1C) BTERM(10) BTERM(14) BTERM(18) BTERM(20) BTERM(24) BTERM(28) BTERM(20) BTERM(24) BTERM(28) 18.4.8 Precharge Command Mode The Precharge Command Mode (SMODE=001) is used during SDRAM/LPDDR device initialization, and to manually deactivate an active bank(s). While in this mode, an access (either read or write) to the SDRAM/LPDDR address space will generate a precharge command cycle. SDRAM/LPDDR address bit A10 determines whether a single bank, or all banks, are precharged by the command. Accessing an address with the SDRAM/LPDDR address A10 low will precharge only the bank selected by the bank addresses, as illustrated in Figure 18-75. Conversely, accesses with A10 high will precharge all banks regardless of the bank address, as illustrated in Figure 18-76. Note that A10 is the SDRAM pin, not the A10 bit ARM address bus. Translation of the SDRAM A10 to the corresponding ARM address is dependent on the memory configuration. The precharge command access is two clocks in length on the ARM, and one cycle to the SDRAM/LPDDR. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-91 Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR ESDCTL SDRAMx ESDCTL SDRAMx HWRITE HWDATA SMODE=PRE_CMD 0 SMODE=NORMAL HREADY SDCLK BA[1:0] BANK, NUMBER SDRAMx, with A10=0 tRP Min applies only to same bank. PRE NOP NOP NOP SDRAMx Row SDRAMx Row MA[1x:0] RAS, CAS, WE CSDx ACT Figure 18-75. Precharge Specific Bank Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-92 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR ESDCTL SDRAMx ESDCTL SDRAMx HWRITE HWDATA SMODE=PRE_CMD 0 SMODE=NORMAL HREADY SDCLK BA[1:0] SDRAMx Row SDRAMx, with A10=1 tRP Min applies only to same bank. PRE NOP NOP NOP ACT SDRAMx Row MA[1x:0] RAS, CAS, WE CSDx Figure 18-76. Precharge All Banks Timing Diagram 18.4.9 Auto-Refresh Mode The Auto-Refresh Mode (SMODE=010) is used to manually request SDRAM/LPDDR refresh cycles and is normally used only during device initialization, since the ESDRAMC will automatically generate refresh cycles when properly configured. The auto-refresh command (see Figure 18-77) refreshes all banks in the device, therefore the address supplied during the refresh command need only specify the correct SDRAM/LPDDR device. The lower address lines are a don’t care. Either a read or write cycle may be used. If a write is used, the data will be ignored and the external data bus will not be driven. The cycle will be 2 clocks on the ARM and a single clock to the SDRAM/LPDDR device. The ESDRAMC doesn’t guarantees that the SDRAM/LPDDR is in the idle state before the auto-refresh command is given. If one or more rows are active, a precharge-all command should be issued by the software prior to the auto-refresh command. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-93 Enhanced SDRAM Controller (ESDRAMC) HCLK HADDR HWRITE HWDATA HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx DQ SDRAMx SDRAMx tRC Minimum SDCTL SDRAMx SDRAMx SMODE=REF 0 0 SDRAMx REFRESH NOP NOP NOP REFRESH NOP NOP Figure 18-77. Software Initiated Auto-Refresh Timing Diagram 18.4.10 Manual Self Refresh Mode Manual Self Refresh Mode (SMODE=100) is used to enter SDRAM/LPDDR external device in self refresh low power operating mode during RUN system operating mode. For more details, see Section 18.4.5.2, “Manual Self Refresh Mode for SDRAM/LPDDR Devices.” 18.4.11 Set Mode Register Mode Set Mode Register mode (SMODE=011) is used to program SDRAM/LPDDR mode register (see Example 18-1 and Section 18.5.4.2, “SDR SDRAM Load Mode Register”). This mode differs from normal SDRAM write cycles because data to be written is transferred across the address bus. Mode Register Reads are not allowed. After SMODE bits are set to 011, either a read or write cycle may be used to write the external memory device mode register. In both cases (read or write), the ARM data will be ignored and the external data bus will not be driven. The row and bank address signals are used to transfer the data toward the external memory device mode register (see Example 18-1 and Section 18.5.4.2, “SDR SDRAM Load Mode Register”). The cycle will be 2 clocks on the ARM and a single clock to the SDRAM device. Figure 18-78 illustrates the bus sequence for a mode register set operation. Mode register set commands must be issued while the SDRAM/LPDDR is idle. The Enhanced SDRAM Controller does not guarantee that the SDRAMs have been returned to the idle state before issuing the mode register set command. Software must generate a precharge all sequence before issuing the mode register set command if there is MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-94 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) any possibility that one or more banks could be active. Also note, the row cycle time (tRC) must be met before the mode register set command is issued. Section 18.5.4.2, “SDR SDRAM Load Mode Register” provides a detailed example of the mode register data value calculation and mapping to the ARM address. (Read | Write) and SMODE=pre_cmd Precharge All Active Idle (Read | Write) and SMODE = set_mode ILLEGAL SDRAM TRANSITION Set Mode Reg (Read | Write) and SMODE=set_mode Figure 18-78. Set Mode Register State Diagram HCLK HADDR HWRITE HWDATA HREADY SDCLK MA[1x:0] RAS, CAS, WE CSDx SDRAMx tRC Minimum SDRAMx SDCTL SDRAMx 0 SMODE=SET_MODE DON’T CARE MODE REFRESH SET MODE For LPDDR: To program the “Mode Register” BA[1:0] “00” To program the “Extended Mode Register” BA[1:0] “01” To program the “Low Power Extended Mode Register” BA[1:0] “10” Figure 18-79. SDR and LPDDR Set Mode Register Timing Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-95 Enhanced SDRAM Controller (ESDRAMC) 18.5 Initialization/Application Information The following section provides details on selecting compatible SDRAM memories and configuring the controller to work with the memory system. 18.5.1 Memory Device Selection Many SDRAM/LPDDR memory types are supported by the Enhanced SDRAM Controller. Important characteristics to consider when choosing a memory device are: • The page comparators expect 4 bank memories. 2 bank devices are not supported. Their use will result in the memory and controller losing synchronization when crossing page boundaries. • Page (column) addressing must match one of the supported sizes. • Memory density can be larger or smaller than those directly supported, although some memory may be inaccessible or redundantly mapped. Bank addresses are the most significant addresses and connecting a memory smaller than the selected density will result in one or more banks being inaccessible. • Controller is designed for memories meeting PC133 timing specifications up to 133 MHz system operation. Use of non-compliant memories require a thorough analysis of all timing parameters. 18.5.2 Configuring Controller for SDRAM Memory Array Configuration register programming options and controller-memory physical connections provide flexibility to accommodate different memory types and system configurations. Options are broadly grouped into 3 categories: • Physical Characteristics: Row and column address bus widths and data bus width. • Timing Parametric: CAS latency, row precharge, cycle delays, refresh rate, etc. • Functional Features: Clock suspend timer and supervisor/user protection. Table 18-32–Table 18-42 are provided to assist the designer with the selection of the correct physical parameters for a number of preferred memory configurations. Timing parametric are addressed in the following subsections. 18.5.3 CAS Latency CAS latency is determined by the operating frequency and access time of the memories. For a 133 MHz system clock frequency and PC133 compliant memories, the CAS latency will generally be programmed to 3 clocks, although the memory specifications should always be consulted to confirm this value. CAS latency must be programmed in two places: the chip select Control Register and the device Mode Register. See Table 18-17 for a description of the control register encoding, and Section 18.4.11, “Set Mode Register Mode” for the details on programming the SDRAM mode register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-96 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4 SDRAM/LPDDR Initialization Sequence Prior to normal operation (read/write accesses), external memory device must be initialized. The following paragraphs provide detailed information covering device initialization. Register definition, command descriptions and device operation information has been thoroughly described throughout the chapter. 18.5.4.1 SDRAM Initialization SDR and LPDDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified by SDRAM manufacture specification may results in undefined operation. 18.5.4.1.1 SDR SDRAM Initialization Once power is applied to the device and the clock is stable, the SDRAM requires a 200µs delay prior to issuing any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 200µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 200µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command have been applied (the SDRAM_RDY status bit will be asserted), a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. VCC SYSTEM CLOCK DRAM RESET 200 µs Minimum HARD_ASYN_R ESET SDCLK SDRAM COMMAND NOP PRE ALL AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO MODE NORMAL REF REF REF REF REF REF REF REF SET SDRAM Software Initialization Sequence CKE[1:0] SDRAM_RDY Figure 18-80. SDR SDRAM Initialization and Load Mode Register Sequence MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-97 Enhanced SDRAM Controller (ESDRAMC) Once in idle state, several (manufacture dependent) AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command. Figure 18-80 illustrates a SDRAM initialization routine with 8 AUTO REFRESH cycles. Example 18-1 shows an initialization SDRAM example code. It is crucial that the dual parameters (those parameters that are defined both in the SDRAM device register and in ESDRAMC registers, like CAS latency, burst length, etc.) to be identical for proper operation of both SDRAM memory and Enhanced SDRAM Controller. Example 18-1. INIT_SDRAM Example Code (ARM Assembler) init_sdram: ldr ldr str ldr str ldr str ldr ldr ldr subs bne ldr str ldr ldrb ldr str r2, =ESD_ESDCTL0 r3, =PRE_ALL_CMD r3,(r2,#0x0) r4, =SDRAM_CSD0 r1,(r4,#0x0) r3, =AUTO_REF_CMD r3,(r2,#0x0) r4, =SDRAM_CSD0_BASE r6,=0x7 r5,(r4,#0x0) r6,r6,#1 0b r3, =SET_MODE_REG_CMD r3,(r2,#0x0) r3, =MODE_REG_VAL0 r5,(r3,#0x0) r3, =NORMAL_MODE r3,(r2,#0x0) // // // // // // // // // // // // // // // base address of registers SMODE=001 put CSD0 in precharge command mode CSD0 precharge address (A10=1) precharge CSD0 all banks SMODE=010 put array 0 in auto-refresh mode CSD0 base address load loop counter run auto-refresh cycle to array 0 decrease counter value SMODE=011 setup CSD0 for mode register write array 0 mode register value New mode register value on address bus 0: // SMODE=000 // setup CSD0 for normal operation ESD_ESDCTL0 SDRAM_CSD0: SDRAM_CSD0_BASE: PRE_ALL_CMD AUTO_REF_CMD SET_MODE_REG_CMD MODE_REG_VAL0 NORMAL_MODE .long .long .long .long .long .long .long .long 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX // // // // // // // // system/external system/external system/external system/external system/external system/external system/external system/external device device device device device device device device dependent dependent dependent dependent dependent dependent dependent dependent data data data data data data data data (SMODE=001) (SMODE=010) (SMODE=011) (SMODE=000) NOTE To do LOAD MODE REGISTER, address starts from bit 0, so LRDB should be used. 18.5.4.1.2 LPDDR SDRAM Initialization DDR Mobile SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ according to the LPDDR SDRAM manufacture data sheet. Clock enable mast be driven through the SDRAM controller registers to cs0 and/or cs1. After all power supply voltages are stable, and the clock is stable, the DDR Mobile-SDRAM requires a 200µs delay prior to applying a command other than DESELECT or NOP. CKE is driven HIGH by the SDRAM controller on the first edge of the clock. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-98 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) Once the 200us delay has been satisfied, the following command sequence shall be applied using the SDRAM controller registers: 1. A DESELECT or NOP command. 2. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. 3. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied). 4. Two MODE REGISTER SET commands for the Mode Register and Extended Mode Register. Following these cycles, the DDR Mobile-SDRAM is ready for normal operation. NOTE A WRITE access should be performed before the first READ access to the LPDDR (in order to assure that a 0 value will be driven on the DQS pins and held by the keeper of the DDR pads). VCC SYSTEM CLOCK DRAM RESET 200 µs Minimum HARD_ASYN_R ESET SDCLK SDCLK_B SDRAM COMMAND NOP PRE ALL Mode Reg AUTO AUTO REF REF MO SET Extended Mode Reg MOD SET NORMAL LPDDR SDRAM Software Initialization Sequence CKE SDRAM_RDY Figure 18-81. Simplified LPDDR SDRAM Initialization and Load Mode Register Sequence MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-99 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.2 SDR SDRAM Load Mode Register The mode register is used to set the SDRAM operating characteristics including CAS latency, burst length, burst mode, and write data length. The settings depend on system characteristics including the operating frequency, memory device type, burst buffer/cache line length, and bus width. Operating characteristics vary by device type, so the data sheet must be consulted to determine the actual value to be written. In order to demonstrate the procedure, the following system characteristics will be used: • Micron MT48LC4M32B2 128Mb (1M x 32 x 4 banks) SDR SDRAMs • 133 MHz System Clock Frequency • Sequential burst, burst length of 8 • Single word writes (for example, no bursting on writes) Figure 18-82 shows the Mode Register bit assignments for the micron 128 Mb SDRAM and the bit field descriptions are listed in Table 18-30. 128 Mb SDRAM Mode Register A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 TYPE Reserved* WB Op Mode CAS Latency BT Burst Length Figure 18-82. 128 Mbit SDR SDRAM Mode Register Table 18-30. SDRAM Mode Register Description Name A11-A10 A9 Write Burst A8–A7 Op Mode Reserved Write Burst Mode (WB). Selects between burst writes and single location writes. 0 Programmed Burst Length 1 Single Location Access1 Operating Mode. Defines operating modes. 00 Standard operation All other states reserved CAS Latency (CL). Sets latency between column address and data 000 Reserved 001 1 clock1 010 2 clocks 011 3 clocks 1xx Reserved Description A6–A4 CAS Latency MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-100 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) Table 18-30. SDRAM Mode Register Description (continued) Name A3 Burst Type Burst Type (BT). Selects burst type 0 Interleave 1 Sequential Burst Length (BL). A 16-bit wide SDRAM requires a burst length of eight because the four 32-bit line fill cycles will be decomposed into eight 16-bit accesses. 000 11 001 21 010 42 011 8 111 Full Page 10x Reserved 1x0 Reserved Description A2–A0 Burst Length 1 2 Not supported by the ESDCTL. Not supported by the ESDCTL for 16-bit external memory device. For this example: • Sequential burst (BT = 0) • Burst length of 8 (BL = 011) • Programmed burst length (during writes) (WB = 0) • 3 Clock Latency (CAS Latency= 011) Once the mode register value has been determined, it must be converted to an address. The mode register is written via the address bus and the memory data sheet will specify the SDRAM address bits on which to place the data. The Enhanced SDRAM Controller drives the LSB address bits to the pins, so the memory density and bus width don’t need to be taken into account during the conversion. Table 18-31 provides an example conversion using the same system characteristics used in the previous example. Table 18-31. Example Address Calculation for Mode Register Mode Register Program Value 0 0 0 0 WB 0 0 0 0 0 CAS LATENCY 0 1 1 BT 0 0 BL 1 1 SDRAM Pin ARM Address MA11 A11 MA10 A10 MA9 A9 MA8 A8 MA7 A7 MA6 A6 MA5 A5 MA4 A4 MA3 A3 MA2 A2 MA1 A1 MA0 A0 18.5.4.3 SDRAM Memory Configuration Examples 15 different SDRAM (SDR and LPDDR) configurations are demonstrated. These examples are 64 Mb, 128 Mb, and 256 Mb SDRAM memories in single x16, dual x16, and single x32 configurations. All single-configuration 16-bit examples are shown connected to the lower half of the data bus. Alternatively, the memory can be connected to the upper half of the data bus by swapping the data connections to D MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-101 Enhanced SDRAM Controller (ESDRAMC) [31:16] and the data qualifier mask connections to DQM3 and DQM2. In this case, it will be necessary to program the DSIZ field in the Control Register to a value of 0 (configurations shown require a value of 1). 18.5.4.3.1 Single 64Mb (4Mx16) SDRAM Configuration Table 18-32. Single 4Mx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 8 MB 512 12 8 16 (D [15:0]) 2 BA1 BA0 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 BA1 BA0 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQMH DQML DQ[15:0] DQ[15:0] SDCLK CKE0 ESDCTL CONTROLLER CLK CKE 4M x 16 SDRAM Figure 18-83. Single 64 Mb (4M x 16) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-102 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.2 Single 128 Mb (8MBx16) SDRAM Configuration Table 18-33. Single 8MBx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 16 Mb 1024 12 9 16 (D [15:0]) 4 BA1 BA0 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 BA1 BA0 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQMH DQML DQ[15:0] DQ[15:0] SDCLK CKE0 ESDCTL CONTROLLER CLK CKE 8M x 16 SDRAM Figure 18-84. Single 128 Mb (8M x 16) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-103 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.3 Single 256 Mb (16MBx16) SDRAM Configuration Table 18-34. Single 16MBx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 32 Mb 1024 13 9 16 (D [15:0]) 4 BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQMH DQML DQ[15:0] DQ[15:0] SDCLK CKE0 ESDCTL CONTROLLER CLK CKE 16M x 16 SDRAM Figure 18-85. Single 256 Mb (16M x 16) Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-104 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.4 Single 512 Mb (32MBx16) SDRAM Configuration Table 18-35. Single 32MBx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 32 Mb 1024 13 10 16 (D [15:0]) 4 BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 RAS CAS CS WE DQMH DQML DQ[15:0] DQ[15:0] SDCLK CKE0 ESDCTL CONTROLLER CLK CKE 32M x 16 SDRAM Figure 18-86. Single 512 Mb (32M x 16) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-105 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.5 Single 1-Gb (64MBx16) SDRAM Configuration Table 18-36. Single 64MBx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 64 Mb 2048 14 10 16 (D [15:0]) 8 BA1 BA0 BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQMH DQML DQ[15:0] DQ[15:0] SDCLK CKE0 ESDCTL CONTROLLER CLK CKE 64M x 16 SDRAM Figure 18-87. Single 1-Gb (64M x 16) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-106 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.6 Dual 64 Mb (4MBx16) SDRAM Configuration Table 18-37. Dual 4MBx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 16 Mb 1024 12 8 32 (D [31:0]) 4 SDCLK CKE BA1 BA0 MA11 MA[10:0] RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:16] DQ[15:0] ESDCTL CONTROLLER CLK CKE BA1 BA0 MA11 MA[10:0] RAS CAS CS WE DQMH DQML DQ[15:0] 4M x 16 SDRAM CLK CKE BA1 BA0 MA11 MA[10:0] RAS CAS CS WE DQMH DQML DQ[15:0] 4M x 16 SDRAM Figure 18-88. Dual 64 Mb (4M x 16 x 2) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-107 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.7 Dual 128 Mb (8MBx16) SDRAM Configuration Table 18-38. Dual 8MBx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 32 Mb 2048 12 9 32 (D [31:0]) 4 SDCLK CKE BA1 BA0 MA11 MA[10:0] RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:16] DQ[15:0] SDRAM CONTROLLER CLK CKE BA1 BA0 MA11 MA[10:0] RAS CAS CS WE DQMH DQML DQ[15:0] 8M x 16 SDRAM CLK CKE BA1 BA0 A11 A[10:0] RAS CAS CS WE DQMH DQML DQ[15:0] 8M x 16 SDRAM Figure 18-89. Dual 128 Mb (8M x 16 x 2) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-108 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.8 Dual 256 Mb (16MBx16) SDRAM Configuration Table 18-39. Dual 16MBx16 Control Register Value Control Field Page Size ROW COL DSIZ SREFR Value 2048 13 9 32 (D [31:0]) 4 SDCLK CKE BA1 BA0 MA12 MA11 MA[10:0] RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:16] DQ[15:0] SDRAM CONTROLLER CLK CKE BA1 BA0 MA12 MA11 MA[10:0] RAS CAS CS WE DQMH DQML DQ[15:0] 16M x 16 SDRAM CLK CKE BA1 BA0 A12 A11 A[10:0] RAS CAS CS WE DQMH DQML DQ[15:0] 16M x 16 SDRAM Figure 18-90. Dual 256-Mbyte (16M x 16 x 2) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-109 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.9 Single 64-Mbyte (2MBx32) SDRAM Configuration Table 18-40. Single 2MBx32 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 2 Mb 1024 11 8 32 (D [31:0]) 1 BA1 BA0 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:0] SDCLK CKE SDRAM CONTROLLER BA1 BA0 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQ[31:0] CLK CKE 2M x 32 SDRAM Figure 18-91. Single 64-Mbyte (2MBx32) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-110 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.10 Single 128-Mbyte (4MBx32) SDRAM Configuration Table 18-41. Single 4MBx32 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 4 Mb 1024 12 8 32 (D [31:0]) 2 BA1 BA0 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:0] SDCLK CKE SDRAM CONTROLLER BA1 BA0 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQ[31:0] CLK CKE 4M x 32 SDRAM Figure 18-92. Single 128-Mb (4MBx32) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-111 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.11 Single 256-Mb (8MBx32) SDRAM Configuration Table 18-42. Single 8MBx32 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 8 Mb 1024 13 8 32 (D [31:0]) 4 BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:0] SDCLK CKE SDRAM CONTROLLER BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQ[31:0] CLK CKE 8M x 32 SDRAM Figure 18-93. Single 256-MB (8MBx32) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-112 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.12 Single 512-Mb (16MBx32) SDRAM Configuration Table 18-43. Single 16MBx32 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 16 Mb 1024 13 9 32 (D [31:0]) 4 BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:0] SDCLK CKE SDRAM CONTROLLER BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQ[31:0] CLK CKE 16M x 32 SDRAM Figure 18-94. Single 512-Mb (16MBx32) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-113 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.13 Single 1-Gb (32Mx32) SDRAM Configuration Table 18-44. Single 32MBx32 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 32 Mb 1024 14 9 32 (D [31:0]) 8 BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:0] SDCLK CKE SDRAM CONTROLLER BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQ[31:0] CLK CKE 32M x 32 SDRAM Figure 18-95. Single 1-Gb (32MBx32) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-114 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.14 Single 2-Gb (64MBx32) SDRAM Configuration Table 18-45. Single 64MBx32 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 64 Mb 1024 14 10 32 (D [31:0]) 8 BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQ[31:0] SDCLK CKE SDRAM CONTROLLER BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQ[31:0] CLK CKE 64M x 32 SDRAM Figure 18-96. Single 2-Gb (64MBx32) SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-115 Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.15 Single 512-Mb (16MBx32) Mobile DDR SDRAM Configuration Table 18-46. Single 16MBx32 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 16 Mb 1024 13 9 32 (D [31:0]) 4 BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQS3 DQS2 DQS1 DQS0 DQ[31:0] SDCLK SDCLK_B CKE BA1 BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQM3 DQM2 DQM1 DQM0 DQS3 DQS2 DQS1 DQS0 DQ[31:0] CK CK CKE E. SDRAM CONTROLLER 16M x 32 LPDDR SDRAM Figure 18-97. Single 512-Mb (16MBx32) LPDDR SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-116 Freescale Semiconductor Enhanced SDRAM Controller (ESDRAMC) 18.5.4.3.16 Single 512-Mb (32MBx16) Mobile DDR SDRAM Configuration Table 18-47. Single 32MBx16 Control Register Value Control Field Density Page Size ROW COL DSIZ SREFR Value 32 Mb 1024 13 10 16 (D [15:0]) 4 BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CSD[0] SDWE DQM3 DQM2 DQM1 DQM0 DQS3 DQS2 DQS1 DQS0 BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS CAS CS WE DQMH DQML DQS1 DQS0 DQ[15:0] SDCLK SDCLK_B DQ[15:0] CK CK CKE0 ESDCTL CONTROLLER CKE 32M x 16 SDRAM Figure 18-98. Single 512-Mb (32MBx16) LPDDR SDRAM Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 18-117 Enhanced SDRAM Controller (ESDRAMC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 18-118 Freescale Semiconductor Chapter 19 NAND Flash Controller (NFC) Composed of various control logic units and a 2-Kbyte internal RAM buffer, the NAND Flash Controller (NFC) provides an interface to standard NAND Flash memory devices. See Figure 19-1 for the NFC block diagram. NF8BOOT NF16BOOT NF_16BIT_SEL NFC_FMS BOOTLOADER NAND FLASH CONTROL CLE ALE CE RE WE LOGIC AHB BUS INTERFACE AHB BUS HOST CONTROL READ and WRITE CONTROL RAM BUFFER (528x32) ECC CONTROL WP DATA OUTPUT CONTROL nfc_endian REGISTER (COMMAND ADDRESS/ STATUS) ADDRESS CONTROL RB DIN DOUT HRESET Figure 19-1. NAND Flash Controller Block Diagram 19.1 Overview The NFC interfaces standard NAND Flash devices to the IC and hides the complexities of accessing the NAND Flash. It provides a glueless interface to both 8-bit and 16-bit NAND Flash parts with page sizes of 512 bytes or 2 Kbytes, and densities up to 64 Gbits per 2-Kbyte page size NAND Flash, and 8 Gbits per 512 byte page size NAND Flash. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-1 NAND Flash Controller (NFC) 19.2 Operation NFC operation begins by AHB host initiating a read from the NAND Flash device by configuring the controller and then waiting for an interrupt from the NFC. When it receives the interrupt, NFC inputs a page from the NAND Flash device, and upon completion, generates an interrupt to AHB Host. When AHB Host receives this interrupt, it reads the content from NFC’s internal RAM buffer. To complete the operation, AHB Host checks the status of the operation by reading the NFC status registers. The 2 Kbyte RAM buffer is used as boot RAM during a cold reset (if IC is configured for a boot to be carried out from NAND Flash device). After boot procedure completes, RAM is available as buffer RAM. In addition, NAND Flash Controller provides an X16 bit and X32 bit interface to the AHB bus on the chip side, and an X8/X16 interface to the NAND Flash device on the external side. 19.3 • • Features 8-bits/16-bits (Pin Option) NAND Flash Interface Internal RAM buffer (2 Kbytes + 64 bytes) — Can be configured as Boot RAM and operates as a buffer during normal operation — Memory mapped (to the same AHB region) registers and internal RAM buffer Manual interface with NAND Flash devices — Supports all NAND Flash products regardless of density/organization (with pages of 512 bytes/2 Kbytes) AHB Host Interface type — Read/Write Burst — 16-bits/32-bits bus transfers Programmable read latency for internal bus (directly affects AHB bus) ECC mode/Bypass ECC Multiple Reset — Cold Reset/ Warm Reset/Hot Reset (Reset of NFC and NAND Flash device) Internal Bootcode loader during power-up (can be enabled/disabled), providing advanced data protection — Data Protection — Write Protection mode for RAM buffer: Write protection of RAM buffer (LSB 1 Kbyte of RAM buffer). For more details see Section 19.7.14, “NAND Flash Write Protection Status (NAND_FLASH_WR_PR_ST).” — Write Protection mode for NAND Flash device: Block based write protection of NAND Flash Automatic Write protection for RAM buffer and NAND Flash during power-up Write Protection: automatic write protection for RAM buffer and NAND Flash during power-up, in addition to run-time write protection modes for both RAM buffer and NAND Flash device. Handshaking Feature: INT pin indicates ready/busy status of NFC IO pins sharing support — Allows sharing of IO pins with other memory controllers through special arbitration logic. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 • • • • • • • • • • 19-2 Freescale Semiconductor NAND Flash Controller (NFC) 19.4 19.4.1 External Signal Description Overview Table 19-1. NFC Signal Properties Name hclk_in hreset ipi_int_nfc ipp_flash_clk ipp_nfc_ale_out ipp_nfc_ce_out ipp_nfc_cle_out ipp_nfc_rb_in ipp_nfc_re_out Port — — — — NFALE NFCE NFCLE NFRB NFRE IO[15:0] NFWE NFWP IO[15:0] — — — — — Function AHB clock of 133 Mhz WARM Reset (active low) NAND Flash Controller interrupt Clock for the flash side Flash Address Latch Enable Flash Chip Enable Flash Command Latch Enable Flash Ready/Busy Flash Read Enable NFC data input from the NAND Flash Flash Write Enable Flash Write Protect NFC data output towards the NAND Flash Power on Reset for booting Use 8 or 16-bits NAND Flash Boot from 8-bit NAND Flash Flash Memory Select (512 byte/2 Kbyte page size) Boot from 16-bit NAND Flash I/O I I O I O O O I O I O O O I I I I I Reset enable 0 1 enable 0 1 0 1 1 xxxx 1 1 0000 1 1 1 0 1 The signals shown in Table 19-1 are used to configure and control the NFC and its attached Flash device. ipp_nfc_read_data_in[15:0] ipp_nfc_we_out ipp_nfc_wp_out ipp_nfc_write_data_out[15:0] ipp_reset nf_16bit_sel nf8boot nfc_fms ng16boot 19.4.2 Detailed Signal Descriptions Table 19-2. NFC Detailed Signal Descriptions Table 19-2 gives a detailed description of the NFC signals. Signal NFCE NFRE I/O O O Description Flash Chip Enable. This signal indicates the NAND Flash selection. When the NAND Flash device is in the Busy state, or when the NAND Flash device is accessed, this signal is low. Flash Read Enable. This output is the NAND Flash device serial data output control. When active, this signal drives the data from the NAND Flash device onto the NAND Flash I/O bus, allowing the NFC to read the data. When reading a burst from the NAND Flash device, this signal increments the NAND Flash internal column address counter by one. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-3 NAND Flash Controller (NFC) Table 19-2. NFC Detailed Signal Descriptions (continued) Signal NFWE NFCLE I/O O O Description Flash Write Enable.This output controls writes to NAND Flash I/O port, thus allowing the NAND Flash device to read data. Commands, address and data are latched on the rising edge of the WE signal. Flash Command Latch Enable. The CLE output controls the activating path for commands sent to the command register of NAND Flash (NAND_Flash_CMD). When active high, commands are latched into the command register of NAND Flash through the I/O ports on the rising edge of the WE signal. Flash Address Latch Enable. The ALE output controls the activating path for addresses sent to the address register of NAND Flash (NAND_Flash_Add). When active high, addresses are latched into the NAND FC address register of NAND Flash through the I/O ports on the rising edge of the WE signal. Flash Write Protect. This signal provides inadvertent program/erase protection during power transition and is automatically controlled by NFC. This pin status is only active (held low) during power-up. Flash Ready/Busy. This signal indicates the status of the NAND Flash operation. When low, it indicates that a program, erase, or random read operation of NAND Flash is in process. Upon completion of the process, this signal returns to high state. Note: This signal is connected to an open drain output, via a 100 KΩ pull-up resister (outside the external NAND Flash memory device). Warm Reset. This signal produces a Warm reset causing NFC and the NAND Flash device to cease current operation, and set all internal registers to their default state. See Figure 19-2 for a timing diagram of warm reset operation. AHB bus interface is connected directly to this signal (hreset) and will cause a reset immediately when this line goes to low state. NFC will not be reset if hreset pulses are shorter than two ipp_flash_clk cycles (50 ns if the clock period is 25 ns), but NFC will be reset if hreset pulse is longer than 20 ipp_flash_clk cycles (500 ns if this clock period is 25 nS). Warm reset has no effect on the contents of main/spare area buffers. The NF8BOOT and NF16BOOT are boot signals that determine when the chip will boot from the NAND Flash device, in addition to indicating boot selection it is also used to controls the bus width of the NAND Flash (8-bit or 16-bit). If one of the boot inputs is asserted (NF8BOOT or NF16BOOT is low) at System Power-On reset (ipp_reset rising), a 2 Kbyte sized boot code is copied from the NAND Flash device to the RAM buffer. If none of the boot signals are asserted, then the input signal NF_16BIT_SEL is read. This is part of the logic of the operating modes of the NFC. For more information on operating modes, see Section 19.8.1, “Modes of Operation.” Note: The boot signals should remain at the same value before and after the boot process. I Flash Memory Select. NFC_FMS signal indicates size of NAND Flash page (512 byte or 2 Kbyte). 0 NAND Flash page size is 512 bytes. 64Mb/128Mb/256Mb/512Mb/1Gb DDP 1 NAND Flash page size is 2 Kbytes. This input is Power On Reset (POR) signal in the NFC. When it is asserted high, a POR takes place. NFC Interrupt. This output is the NFC interrupt, and is asserted when an NFC event takes place. It sets itself to ‘1’ when basic operation and boot loading is done, or when a warm or hot reset is released. In addition, it is asserted when any of the following occur: • NAND Flash command input • NAND Flash address input • NAND Flash data input • NAND Flash data output H Clock Input. This is NFC clock signal, which arrives from the AHB side. Its value can up to 133 MHz. AHB host uses this path to write data to registers or to internal memory. NFALE O NFWP NFRB O I hreset NF8BOOT NF16BOOT NF_16BIT_SEL NFC_FMS ipp_reset ipi_int_nfc I O hclk_in ipp_nfc_write_d ata_out[15:0] I O MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-4 Freescale Semiconductor NAND Flash Controller (NFC) Table 19-2. NFC Detailed Signal Descriptions (continued) Signal ipp_nfc_read_d ata_in[15:0] ipp_flash_clk I/O I Description AHB host uses this path to read data from registers or from internal memory. This clock signal controls NFC’s state machine when interfacing with a NAND Flash device. hreset NFC Operation Idle Warm reset operation Idle ipi_int_nfc Figure 19-2. Warm Reset Operation 19.5 NFC Buffer Memory Space Table 19-3. Data (Buffer) Organization in Memory Address 0xD800_0000– 0xD800_01FE 0xD800_0200–0xD800_03FE 0xD800_0400–0xD800_05FE 0xD800_0600–0xD800_07FE 0xD800_0800–0xD800_080E 0xD800_0810–0xD800_081E 0xD800_0820–0xD800_082E 0xD800_0830–0xD800_083E 0xD800_0840–0xD800_0BFE 0xD800_0E00–0xD800_0E1C Use Main area Buffer 0 Main area Buffer 1 Main area Buffer 2 Main area Buffer 3 Spare area Buffer 0 Spare area Buffer 1 Spare area Buffer 2 Spare area Buffer 3 Reserved Registers Access R/W R/W R/W R/W R/W R/W R/W R/W — R/W Table 19-3 shows the organization of the buffer memory space in the NFC. 19.5.1 Main and Spare Area Buffers Main area buffer is a general data block. Spare area buffer is used for a variety of functions including Error Correction. Memory is organized in a different manner depending on Flash bus width (8-bit or 16-bit). Table 19-4 shows an 8-bit organization, and Table 19-5 shows a 16-bit configuration. Host can use all of the spare area except for BI and ECC code areas. For example, AHB host can write data to a reserved area in spare area buffer upon program operation. NFC automatically generates ECC code for both main and spare data during NFC’s data loading to NAND Flash, and NFC updates ECC code to NAND Flash spare area, but does not update ECC code to spare buffer. When programming/reading spare area, the spare area buffer number (SB0–SB3) must be selected using the RAM buffer address register (NFC_RAM_BUFF). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-5 NAND Flash Controller (NFC) Table 19-4. Spare Area Buffer (with X8 I/O bus) Address 0xD800_0800 (SB0) 0xD800_0802 (SB0) 0xD800_0804 (SB0) 0xD800_0806 (SB0) 0xD800_0808 (SB0) 0xD800_080A (SB0) 0xD800_080C (SB0) 0xD800_080E (SB0) 0xD800_0810– 0xD800_081E (SB1) 0xD800_0820– 0xD800_082E (SB2) 0xD800_0830– 0xD800_083E (SB3) 2 F E D C B 1 A 9 8 7 6 5 4 3 1 2 1 0 LSN(2nd) LSN(1st) WC(1st)2 BI3 ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) Reserved Reserved Reserved LSN(3rd)1 WC(2nd)2 ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved Reserved SB1–SB3 have same assignment like SB0. LSN: Logical Sector Number WC: Wrap Count and other bytes have same wrap count information and are used as error correction for wrap count itself. 3 BI: Bad Block Information 1 Table 19-5. Spare Area Buffer (with X16 I/O bus) Address 0xD800_0800 (SB0) 0xD800_0802 (SB0) 0xD800_0804 (SB0) 0xD800_0806 (SB0) 0xD800_0808 (SB0) 0xD800_080A (SB0) 0xD800_080C (SB0) 0xD800_080E (SB0) 0xD800_0810– 0xD800_081E (SB1) 0xD800_0820– 0xD800_082E (SB2) 0xD800_0830– 0xD800_083E (SB3) 2 F E D C B A 9 8 7 6 5 4 3 2 1 0 LSN(2nd)1 WC(1st)2 Reserved ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) BI3 Reserved Reserved LSN(1st)1 LSN(3rd)1 WC(2nd)2 ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved Reserved SB1–SB3 have same assignment like SB0. LSN: Logical Sector Number WC: Wrap Count and other bytes have same wrap count information and are used as error correction for wrap count itself. 3 BI: Bad Block Information 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-6 Freescale Semiconductor NAND Flash Controller (NFC) 19.6 Memory Map and Register Definition Section 19.7, “Register Descriptions” provides detail descriptions for all the NFC registers. 19.6.1 Memory Map Table 19-6. NFC Module Register Memory Map Address Register NAND Flash Controller Buffer Size Register Reserved RAM Buffer Address Register NAND Flash Address Register NAND Flash Command Register NFC Internal Buffer Lock Control Controller Status and Result of Flash Operation ECC Error Position Main Area Data Error x8 ECC Error Position Main Area Data Error x16 ECC Error Position Spare Area Data Error x8 ECC Error Position Spare Area Data Error x16 NAND Flash Write Protection Address to Unlock in Write Protection Mode—Start Address to Unlock in Write Protection Mode—End NAND Flash Write Protection Status NAND Flash Operation Configuration1 NAND Flash Operation Configuration 2 R/W R — R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0001 — 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0001 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0002 0x0000_0000 0x0000_0000 0x0000_0002 0x0000_0008 0x0000_0000 Section/Page 19.7.1/19-9 — 19.7.2/19-10 19.7.3/19-10 19.7.4/19-11 19.7.5/19-11 19.7.6/19-12 19.7.7/19-12 19.7.8/19-13 19.7.9/19-14 19.7.10/19-14 19.7.11/19-15 19.7.12/19-15 19.7.13/19-16 19.7.14/19-16 19.7.15/19-17 19.7.16/19-18 Table 19-6 provides the NFC memory map. 0xD800_0E00 (NFC_BUFSIZ) 0xD800_0E02 0xD800_0E04 (RAM_BUFFER_ADDRESS) 0xD800_0E06 (NAND_FLASH_ADD) 0xD800_0E08 (NAND_FLASH_CMD) 0xD800_0E0A (NFC_CONFIGURATION) 0xD800_0E0C (ECC_STATUS_RESULT) 0xD800_0E0E (ECC_RSLT_MAIN_AREA) 0xD800_0E10 (ECC_RSLT_SPARE_AREA) 0xD800_0E12 (NF_WR_PROT) 0xD800_0E14 (UNLOCK_START_BLK_ADD) 0xD800_0E16 (UNLOCK_END_BLK_ADD) 0xD800_0E18 (NAND_FLASH_WR_PR_ST) 0xD800_0E1A (NAND_FLASH_CONFIG1) 0xD800_0E1C (NAND_FLASH_CONFIG2) 19.6.2 Register Summary Figure 19-3 shows the key to the register fields and Table 19-7 shows the register figure conventions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-7 NAND Flash Controller (NFC) Always reads 1 1 Always reads 0 0 Write 1 BIT Self-clear 0 R/W BIT Read- BIT Writebit BIT bit only bit only bit BIT to clear w1c N/A Figure 19-3. Key to Register Fields Table 19-7. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 19-8. NFC Register Summary Name 0xD800_0E00 (NFC_BUFSIZ) R W 0xD800_0E02 (Reserved) R W 0xD800_0E04 (RAM_BUFFER_ADDRESS) 0xD800_0E06 (NAND_FLASH_ADD) 0xD800_0E08 (NAND_FLASH_CMD) R W R ADD W R CMD W 0 0 0 0 0 0 0 0 0 0 0 0 RBA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFSIZE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-8 Freescale Semiconductor NAND Flash Controller (NFC) Table 19-8. NFC Register Summary (continued) Name 0xD800_0E0A (NFC_CONFIGURATION) 0xD800_0E0C (ECC_STATUS_RESULT) 0xD800_0E0E (ECC_RSLT_MAIN_AREA) 0xD800_0E10 (ECC_RSLT_SPARE_AREA) R W R W R W R W 0xD800_0E12 (NF_WR_PROT) R W 0xD800_0E14 R (UNLOCK_START_BLK_ADD) W 0xD800_0E16 (UNLOCK_END_BLK_ADD) 0xD800_0E18 (NAND_FLASH_WR_PR_ST) 0xD800_0E1A (NAND_FLASH_CONFIG1) R UEBA W R W R W 0 0 0 0 0 0 0 0 NF NF_ C_ NF_ INT_ ECC SP_ CE RS BIG MSK _EN EN T 0 0 FDO W INT FDI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 US LS LTS USBA 0 0 0 0 0 0 0 0 0 0 0 0 0 WPC 0 0 0 0 0 0 0 0 0 0 0 ECC Result 4 ECC Result 3 0 0 0 0 ECC Result 1 ECC Result2 0 0 0 0 0 0 0 0 0 0 0 0 ERM ERS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLS 0xD800_0E1C (NAND_FLASH_CONFIG2) R INT 0 0 0 0 0 0 0 FAD FC D MD 19.7 19.7.1 Register Descriptions Internal SRAM SIZE (NFC_BUFSIZE) This 16-bit read-only register contains internal SRAM size installed in the IC. Bit assignments for this register is shown in Figure 19-4 and the field descriptions are shown in Table 19-9. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-9 NAND Flash Controller (NFC) 0xD800_0E00 (NFC_BUFSIZ) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read-only 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 BUFSIZE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 19-4. NFC_BUFSIZE Register Table 19-9. NFC_BUFSIZE Register Field Description Name 15–4 3–0 BUFSIZE Reserved Buffer Size. The size of the internal RAM buffer. 0000 1 Kbyte 0001 2 Kbytes (Default) 0010–1111 Reserved Description 19.7.2 Buffer Number for Page Data Transfer (RAM_BUFFER_ADDRESS) RBA specifies which part of the RAM Buffer is transferred to/from flash memory. Bit assignments for this register is shown in Figure 19-5 and the field description is shown in Table 19-10. 0xD800_0E04 (RAM_BUFFER_ADDRESS) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 RBA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-5. RAM Buffer Address Register Table 19-10. RAM Buffer Address Field Descriptions Field 15–4 3–0 RBA Reserved RAM Buffer Address. Specifies the RAM buffer number to use for data transfers to/from the NAND Flash device. 0000 1st internal RAM buffer 0001 2nd internal RAM buffer 0010 3rd internal RAM buffer 0011 4th internal RAM buffer Description 19.7.3 NAND Flash Address (NAND_FLASH_ADD) NAND Flash Address (NAND_FLASH_ADD) register is a read-write register containing the address of NAND Flash device that will be read, programmed or erased. The address in NAND_FLASH_ADD register is written to the Flash device. Bit assignments for this register is shown in Figure 19-6 and the field descriptions are shown in Table 19-11. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-10 Freescale Semiconductor NAND Flash Controller (NFC) 0xD800_0E06 (NAND_FLASH_ADD) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R ADD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-6. NAND Flash Address Register Table 19-11. NAND Flash Address Register Field Description Field 15–0 ADD Description NAND Flash Address. NAND Flash address which will be read, programmed or erased. This address is written to the NAND Flash device. 19.7.4 NAND Flash Command (NAND_FLASH_CMD) Bit assignments for this register is shown in Figure 19-7 and field descriptions are shown in Table 19-12. 0xD800_0E08 (NAND_FLASH_CMD) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R CMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-7. NAND_Flash_CMD Register Table 19-12. NAND_Flash_CMD Register Field Description Field 15–0 CMD Description NAND Flash Command. This field contains the CMD that is written to the NAND Flash device. 19.7.5 NFC Internal Buffer Lock Control (NFC_CONFIGURATION) Bit assignments for this register is shown in Figure 19-8 and field descriptions are shown in Table 19-13. 0xD800_0E0A (NFC_CONFIGURATION) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 19-8. NFC_Configuration Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-11 NAND Flash Controller (NFC) Table 19-13. NFC_Configuration Register Field Descriptions Field 15–2 1–0 BLS Reserved. Buffer Lock Set. This field specifies the buffer lock status of first 2 pages in the internal buffer. The other two pages are always Unlocked. (For more details, see Section 19.9.3, “Write Protection Operation.”) 00 Locked 01 Locked (default) 10 Unlocked 11 Locked Description 19.7.6 Controller Status and Result of Flash Operation (ECC_STATUS_RESULT) This register shows the number of errors in a page for Spare and Main Area as a result of ECC check upon a page read.Bit assignment is shown in Figure 19-9 and the field descriptions are shown in Table 19-14. 0xD800_0E0C (ECC_STATUS_RESULT) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read-only 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 ERM ERS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-9. ECC_Status_Result Table 19-14. ECC_STATUS_RESULT Register Field Description Field 15–4 3–2 ERM 1–0 ERS Reserved ECC Error for Main Area Data (ERM) and Spare Area Data (ERS). These field shows the number of errors in a page as a result of ECC check upon page read. The ECC algorithm of NFC doesn’t correct if there are greater than two fault bits per page. It interprets any ECC error count greater than two as non-correctable. 00 No error 01 1-bit Error (Correctable Error) 10 2-bits Error or more (Non-correctable Error) 11 Reserved Description 19.7.7 ECC Error Position of Main Area Data Error x8 (ECC_RSLT_MAIN_AREA) (NAND Flash X8 data bus case) This register contains ECC error position address which is used to select the bit to repair in Main Area for 8-bit NAND FlashBit assignments for this register is shown in Figure 19-10, and the field descriptions are shown in Table 19-15. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-12 Freescale Semiconductor NAND Flash Controller (NFC) 0xD800_0E0E (ECC_RSLT_MAIN_AREA) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read-only 2 1 0 R W Reset 0 0 0 0 ECC RESULT1 ECC RESULT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-10. ECC_RSLT_MAIN_AREA Register Table 19-15. ECC_RSLT_MAIN_AREA Register Field Descriptions Field 15–12 11–3 ECC RESULT1 2–0 ECC RESULT2 Reserved ECC Result 1: ECC error position address which selects one of Main area data bytes (one of 512 bytes). ECC Result 2: ECC error position address which selects one of the 8 data bits in the byte. Description 19.7.8 ECC Error Position of Main Area Data Error x16 (ECC_RSLT_MAIN_AREA) (NAND Flash X16 data bus case) This register contains ECC error position address which is used to select the bit to repair in Main Area for 16-bit NAND Flash bit assignments for this register is shown in Figure 19-11, and the field descriptions are shown in Table 19-16. 0xD800_0E0E (ECC_RSLT_MAIN_AREA) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read-only 2 1 0 R W Reset 0 0 0 0 ECC RESULT1 ECC RESULT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-11. ECC_RSLT_MAIN_AREA Register Table 19-16. ECC_RSLT_MAIN_AREA Register Field Descriptions Field 15–12 11–4 ECC RESULT1 3–0 ECC RESULT2 Reserved ECC Result 1: ECC error position address which selects one of the 16 data bits in the half word ECC Result 2: ECC error position address which selects one of the 8 data bits in the byte Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-13 NAND Flash Controller (NFC) 19.7.9 ECC Error Position of Spare Area Data Error x8 (ECC_RSLT_SPARE_AREA) (NAND Flash X8 data bus case) This register contains ECC error position address which is used to select the bit to repair in Spare Area for 8-bit NAND Flash bit assignments for this register is shown in Figure 19-12, and the field descriptions are shown in Table 19-17. 0xD800_0E10 (ECC_RSLT_SPARE_AREA) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read-only 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 ECC Result 4 ECC Result 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-12. ECC_Rslt_Spare_Area Register Table 19-17. ECC_Rslt_Spare_Area Descriptions Field 15–5 4–3 ECC RESULT4 2–0 ECC RESULT3 Reserved ECC Result 4: ECC error position address which selects one of Logical Sector Number (3 bytes) ECC Result 3: ECC error position address which selects one of 8 data bits in the byte. Description 19.7.10 ECC Error Position of Spare Area Data Error x16 (ECC_RSLT_SPARE_AREA) (NAND Flash X16 data bus case) This register contains ECC error position address which is used to select the bit to repair in Spare Area for 16-bit NAND Flash. Bit assignments for this register is shown in Figure 19-13 and the field descriptions are shown in Table 19-18. 0xD800_0E10 (ECC_RSLT_SPARE_AREA) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read-only 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 Result4 Result 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-13. ECC_Rslt_Spare_Area Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-14 Freescale Semiconductor NAND Flash Controller (NFC) Table 19-18. ECC_Rslt_Spare_Area Descriptions Field 15–5 4 ECC RESULT4 3–0 ECC RESULT3 Reserved ECC Result 4: ECC error position address which selects one of Logical Sector Number (3 bytes) ECC Result 3: ECC error position address which selects one of the 8 data bits in the byte. Description 19.7.11 NAND Flash Write Protection (NF_WR_PROT) This register specifies the Protection command that the controller will perform: Lock, Unlock, or Lock Tight. Bit assignments for this register is shown in Figure 19-14 and field descriptions are shown in Table 19-19. 0xD800_0E12 (NF_WR_PROT) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 WPC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Figure 19-14. NAND Flash Write Protection Register Table 19-19. NAND Flash Write Protection Register Field Descriptions Field 15–3 2–0 WPC Reserved Write Protection Command: This field specifies the operation which the controller will perform. 100 Unlock NAND Flash block(s) according to given block address range 010 Lock all NAND Flash block(s) 001 Lock-tight locked blocks(s) (See Section 19.9.3, “Write Protection Operation” for more details.) Description 19.7.12 Address to Unlock in Write Protection Mode—Start (UNLOCK_START_BLK_ADD) Starting address of block memory in the NAND Flash that is unlocked in the Write Protection mode. Bit assignments for this register is shown in Figure 19-15 and the field descriptions are shown in Table 19-20. 0xD800_0E14 (UNLOCK_START_BLK_ADD) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R USBA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-15. Unlock_Start_Blk_Add Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-15 NAND Flash Controller (NFC) Table 19-20. Unlock_Start_Blk_Add Register Field Description Field 15–0 USBA Description Unlock Start Block Address. Starting address of block memory in the NAND Flash that is unlocked in Write Protection mode. For more details on this, see Section 19.9.3.4, “Write Protection Status.” 19.7.13 Address to Unlock in Write Protection Mode—End (UNLOCK_END_BLK_ADD) End address of block memory in the NAND Flash that is unlocked in the Write Protection mode. Bit assignments for this register is shown in Figure 19-16 and the field descriptions are shown in Table 19-21. 0xD800_0E16 (UNLOCK_END_BLK_ADD) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R UEBA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-16. UNLOCK_END_BLK_ADD Register Table 19-21. UNLOCK_END_BLK_ADD Register Field Description Field 15–0 UEBA Description Unlock End Block Address. Ending address of block memory in the NAND Flash that is unlocked in Write Protection mode. For more details, see Section 19.9.3.4, “Write Protection Status.” 19.7.14 NAND Flash Write Protection Status (NAND_FLASH_WR_PR_ST) This status register reads the NAND Flash Write Protection Status: Lock, Unlock or Lock Tight status. Bit assignments for this register is shown in Figure 19-17 and the field descriptions are shown in Table 19-22. 0xD800_0E18 (NAND_FLASH_WR_PR_ST) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read-only 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 US LS 1 LTS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-17. NAND_FLASH_WR_PR_ST Register Table 19-22. NAND_FLASH_WR_PR_ST Register Field Descriptions Field 15–3 0 LTS Reserved Lock-tight Status. Indicates if any of the locked block(s) is (are) have a lock-tight status. 0 Locked block(s) is (are) not lock-tight. 1 Locked block(s) is (are) lock-tight. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-16 Freescale Semiconductor NAND Flash Controller (NFC) Table 19-22. NAND_FLASH_WR_PR_ST Register Field Descriptions (continued) Field 1 LS 2 US Description Locked Status. This bit indicate whether all NAND Flash blocks are in locked status or in lock-Unlock status. 0 Not all NAND Flash blocks are in locked status. 1 There are unlocked block(s) in NAND Flash. Unlocked Status. This bit indicates whether there are any unlocked blocks in the NAND Flash. 0 There are no unlocked blocks in NAND Flash. 1 There are unlocked block(s) in NAND Flash. There are four states for write protected: lock, unlock-lock, unlock-lockt, and lockt. Table 19-23. Write Protected States State Lock—All blocks are locked Unlock-lock—There are unlocked blocks Unlock-Lockt—There are unlocked blocks: cant change to other state Lockt—All block are locked: cant change to other state Status Bits—US -LS -LTS 010 110 101 001 19.7.15 NAND Flash Operation Configuration (NAND_FLASH_CONFIG1) This register is a configuration register for NAND Flash device to control the ECC Enable or Disable Mask Interrupt. Bit assignments for this register is shown in Figure 19-18 and the field descriptions are shown in Table 19-24. 0xD800_0E1A (NAND_FLASH_CONFIG1) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 NF_C NFC_ NF_B INT_ ECC_ SP_E E RST IG MSK EN N 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-18. NAND_FLASH_CONFIG1 Register Table 19-24. NAND_FLASH_CONFIG1 Register Field Descriptions Field 15–8 7 NF_CE Reserved NAND Flash Force CE. This bit forces the CE signal to the NAND Flash device to 0 when enabled. This bit allows a greater range of support new NAND Flash devices. 0 CE signal operates normally. 1 CE signal is asserted as long as this bit is set to 1. NFC Reset. This bit resets the NFC state machine. 0 Do not reset the NFC state machine 1 Reset the NFC state machine Description 6 NFC_RST MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-17 NAND Flash Controller (NFC) Table 19-24. NAND_FLASH_CONFIG1 Register Field Descriptions (continued) Field 5 NF_BIG Description NAND Flash Big Endian Mode. This bit enables big Endian mode when writing from internal RAM to the NAND Flash device or reading from NAND Flash device to internal RAM. 0 Little Endian mode 1 Big Endian mode Mask interrupt Bit. This bit enables the interrupt by masking or not masking the interrupt bit. 0 Mask interrupt is disabled (interrupt enabled). 1 Mask interrupt is enabled (interrupt disabled). ECC operation Enable. This bit determines whether ECC operation is executed or bypassed 0 ECC operation is bypassed. 1 ECC operation is executed. NAND Flash Spare Enable. This bit determines whether host reads/writes are to NAND Flash spare data only or NAND Flash main and spare data. 0 NAND Flash main and spare data is enabled. 1 NAND Flash spare only data is enabled. Reserved 4 INT_MSK 3 ECC_EN 2 SP_EN 1–0 19.7.16 NAND Flash Operation Configuration 2 (NAND_FLASH_CONFIG2) This register controls the NAND Flash signals: CLE, ALE, WE, RE, CE. and sets the interrupt after command completion. Bit assignments for this register is shown in Figure 19-19 and the field descriptions are shown in Table 19-25. 0xD800_0E1C (NAND_FLASH_CONFIG2) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R INT W Reset 0 0 0 0 0 0 0 0 0 0 FDO FDI 0 1 FADD FCMD 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-19. NAND_FLASH_CONFIG2 Register Table 19-25. NAND_FLASH_CONFIG2 Register Field Descriptions Field 15 INT Description Interrupt. This field determines the state of the interrupt output of the NAND FLash Controller. It is set by the controller when a basic operation is done. It is set cleared by the Host writing “0” to this field. (Host can also set this bit by writing “1” to this field). 0 Basic operation or boot loading is still running. 1 Basic operation or boot loading is done. Reserved NAND Flash Data Output. This bit enables NAND Flash Data Output 001 One page data out1 010 NAND Flash ID data out 100 NAND Flash Status Register data out 14–6 5–3 FDO MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-18 Freescale Semiconductor NAND Flash Controller (NFC) Table 19-25. NAND_FLASH_CONFIG2 Register Field Descriptions (continued) Field 2 FDI 1 FADD 0 FCMD 1 Description NAND Flash Data Input. This field enables NAND Flash Data Input 0 No NAND Flash data input operation 1 Enable NAND Flash data input operation NAND Flash Address Input. This field enables NAND Flash Address Input 0 No NAND Flash Address input operation 1 Enable NAND Flash Address input operation NAND Flash Command Input. This field enables the NAND Flash Command Input 0 No NAND Flash Command input operation 1 Allow NAND Flash Command input operation Page size is determined by SP_EN register bit (main + spare or spare only). It is 528 bytes (main+spare) or 16 bytes (spare) regardless of the NFC_FMS setting. NOTE INT bit reset value is 0, but soon after power-up it will change to 1. INT will change from 0 to 1, when performing boot from NAND Flash, after boot code transfer is accomplished. For more information, see Section 19.8.1, “Modes of Operation.” When basic operation is completed, FCMD/FADD/FDI/FDO bits change to LOW automatically. Only one of the bit fields (FCMD/FADD/FDI/FDO) can be set at any given time. 19.8 Functional Description This section provides the functional description for the NAND Flash Controller. 19.8.1 Modes of Operation Operating mode is determined by four input lines: NFC_FMS, NF8BOOT, NF16BOOT, NF_16BIT_SEL, as shown in Table 19-26. It is possible to configure the i.MX31 to boot from a NAND Flash device. For this to occur, one of the signals NF8BOOT or NF16BOOT must be low (0). If both of these signals are high, a boot from the NAND Flash device does not occur. If both of these signals are low, the situation is undefined, and should not be used. The value of the NFC_FMS determines the page size of NAND Flash: 512 bytes if NFC_FMS is low (0), and 2 Kbyte if NFC_FMS is high (1). While booting from NAND Flash device, bus width is determined by the bus width used during boot. While not booting from NAND Flash device, bus width is determined by the value of NF_16BIT_SEL signal (0=8-bit bus, 1=16-bit bus). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-19 NAND Flash Controller (NFC) Table 19-26. NAND Flash Controller Operating Modes NFC_FMS 0 0 0 NF8BOOT 1 1 1 NF16BOOT 1 1 0 NF_16BIT_SEL 0 1 X Function Do not Boot from NAND Flash. NAND Flash is configured to 8-bits I/O bus width and page size is 512 bytes. Do not Boot from NAND Flash. NAND Flash is configured to 16-bits I/O bus width and page size is 512 bytes. Boot from 16-bit NAND Flash. NAND Flash is configured to the same value as it booted from (16-bits) and page size is 512 bytes. Boot from 8-bit NAND Flash. NAND Flash is configured to the same value as it booted from (8-bits) and page size is 512 bytes. Do not Boot from NAND Flash. NAND Flash is configured to 8-bits I/O bus width and a page size is 2 Kbyte. Do not Boot from NAND Flash. NAND Flash is configured to 16-bits I/O bus width and a page size is 2 Kbyte. Boot from 16-bit NAND Flash. NAND Flash is configured to the same value as it booted from (16-bits) and page size is 2 Kbyte. Boot from 8-bit NAND Flash. NAND Flash is configured to the same value as it booted from (8-bits) and page size is 2 Kbyte. NOT DEFINED (Do not use this setting.) 0 0 1 X 1 1 1 1 1 1 1 1 0 0 1 X 1 0 1 X X 0 0 X 19.8.2 Booting From a NAND Flash Device Booting from NAND Flash device proceeds as follows1: 1. BOOTLOADER copies 1 page of 2 Kbytes or 4 Pages of 528 bytes (depending on NFC_FMS input value) from the NAND Flash to the NFC internal RAM buffer. The transfer is done in the following order: — For NAND Flash with 528-byte page depth case: 1st page read => 2nd page read => 3rd page read => 4th page read — For NAND Flash with 2 K page depth case: One page read 2. AHB Host then reads (after exiting from reset state) the first code from NFC internal RAM buffer. 1. A Boot from the NAND Flash device will only occur if one of the Boot inputs is asserted (NF8BOOT or NF16BOOT is low) at System Power-On reset (ipp_resetb rising). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-20 Freescale Semiconductor NAND Flash Controller (NFC) NF8BOOT or NF16BOOT ipp_resetb (POR) Bootcode-copy done NFC Operation Sleep BootCode-Copy 1) Idle hreset ipi_int_nfc 2) Figure 19-20. Boot Mode Operation NOTE 2 Kbytes of bootcode copy takes about 160 µs. Host must read bootcode in the RAM buffer (2 Kbytes) after bootcode copy completion. Interrupt pin (ipi_int_nfc) goes from high to low when the bootcode-copy is completed, and upon hreset rising edge. If hreset goes from Low to High before bootcode-copy is done, Interrupt pin (ipi_int_nfc) goes from High to Low as soon as bootcode-copy is completed. The interrupt can be relevant for cases of secured boot (booting from ROM and then enabling the NFC boot). 19.8.3 NAND Flash Control NAND Flash Control generates all control signals that control the NAND Flash: CE (Flash Chip Enable), RE (Read Enable for read operations), WE (Flash Write Enable), CLE (Flash Command Latch Enable), ALE (Flash Address Latch Enable). It monitors R/nB (Flash Ready/Busy indication) signal to check if the NAND Flash is in the middle of operation. BOOTLOADER is part of NAND Flash Control Block. Figure 19-21, Figure 19-22, and Figure 19-23 show NAND Flash read, program, and erase timing diagrams. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-21 NAND Flash Controller (NFC) Figure 19-21. Read Operation Figure 19-22. Program Operation MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-22 Freescale Semiconductor NAND Flash Controller (NFC) Figure 19-23. Erase Operation 19.8.4 Error Code Correction (ECC) Control Error Code Correction (ECC) block is responsible for correcting one bit per read, and for detecting if there is more then one bit with an error. When NFC accesses the NAND Flash device for Program operation, it generates code (24-bits for Main area data and 10-bits for Spare area data). When it accesses the NAND Flash device for a Read operation, it generates ECC code, and indicates how many errors were detected, and their positions in addition to correcting 1 error bit. The ECC code is updated by the NFC automatically. After a Read operation, AHB host can know whether there is an error or not by reading the status register (see ECC_Status_Result register in Section 19.7.6, “Controller Status and Result of Flash Operation (ECC_STATUS_RESULT)”). The indication in the status register is either a) no error, b) 1 bit error (correctable), or c) greater than 2 bit errors (uncorrectable). Since the generated ECC code at read/program operation is not updated to the internal RAM buffer, but is updated to the NAND Flash spare area upon program operation, the AHB host can read generated ECC code only from NAND Flash spare area. 19.8.5 Address Control This module is responsible for address control and generation. It defines the RAM buffer Address Generation (RAM buffer Address for Data In/ Data Out). It generates and takes into account the Lock State Sequence (For more details see Section 19.9.3, “Write Protection Operation”) and therefore contains the Flash Memory Lock Address Comparator, and RAM buffer Lock Address Comparator which are used to determine if this area is protected or not. It also generates the RAM buffer Address for Boot Load and RAM buffer Address for Error Correction. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-23 NAND Flash Controller (NFC) 19.8.6 RAM Buffer (SRAM) The internal RAM Buffer is a 2112 byte single Port RAM buffer which is a synchronous high performance design. This memory has 528 words of 32-bits each, from which 512 words are used for the main buffer and the remaining 16 Words are allotted to a spare area, which is used for ECC (Error Correction). This Memory is used as a BootRAM during boot from NAND Flash device, and as a buffer at normal operation. 19.8.7 Registers (Command, Address, Status, and Others.) This module contains 15 registers of 16-bits each. Using these registers, the AHB host can control the NFC, read status on various operations and perform a direct access of commands, and insert addresses to the NAND Flash device. For more details, refer to Section 19.6.1, “Memory Map.” 19.8.8 Read and Write Control The Read and Write Control Block contains a connection to the Internal bus (which is connected to the Internal RAM buffer and the registers). This Internal bus is responsible for the Internal Synchronous read and Asynchronous write. It supports Burst Read Latency (3, 4, 5, 6, 7 cycle) and Synchronous Read Burst Length (4, 8, 16, 32, continuous word). It is also responsible for RAM buffer Control and Register Control, RAM buffer Lock Control and Address and Data latches. 19.8.9 Data Output Control This module defines Data output of 16-bits to the Internal bus which is driven to the AHB interface. It includes RAM buffer Data output, Register Data output and RAM buffer Synchronization for the read mode pipeline. 19.8.10 Host Control This module defines Host control which is connected to the AHB Interface though the internal bus. It detects Chip Enable and controls the Reset and Output Enable, and generates the SRAM_WE signal. 19.8.11 AHB BUS INTERFACE AHB bus interface is an adapter between ABMA AHB bus and the internal bus. On the AHB bus side, it supports a 16-bit and 32-bit bus width, burst and non burst operations. On the internal bus side, it supports 32-bit bus width with a Synchronous Burst Read and an Asynchronous Random Write. It also supports Programmable Read latency for the internal bus (this also effects the latency on the AHB bus). 19.8.11.1 Big/Little Endian AHB bus interface supports both Big and Little Endian data types. The nfc_endian pin controls the endian mode. Only the AHB side is controlled by nfc_endian pin; NAND Flash device side is always in little endian mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-24 Freescale Semiconductor NAND Flash Controller (NFC) 19.8.11.2 Burst Access Support When a data transaction from the AHB is a burst, it will create a synchronous burst read on the internal bus for read cycles, and several asynchronous random writes for write cycles. Table 19-27 lists the NFC supported access burst types. t Table 19-27. NAND Flash Burst Access Support HBURST 000 001 010 011 100 101 110 111 BURST TYPE SINGLE INCR WRAP4 INCR4 WRAP8 INCR8 WRAP16 INCR16 SUPPORTED Yes Yes No Yes No Yes No Yes Description Single transfer Incrementing burst 4-beat wrapping burst 4-beat incrementing burst 8-beat wrapping burst 8-beat incrementing burst 16-beat wrapping burst 16-beat incrementing burst NOTE NFC supports bursts of 16/32-bit words only. Bursts of byte words (8-bits) is not supported. 19.8.12 I/O Pins Sharing NFC has logic that allows it to share I/O pins with pins of another memory controller. NFC’s state machine halts when a request to free the pins is asserted. The NAND Flash signals when it finishes the existing transfer allowing the other memory controller to be able to control them. Since the NAND Flash accesses are long and relatively slow, the priority is given to the other memory controller and the NAND Flash Controller will have to wait till the pins are free before it can continue with its accesses. One example for this pin muxing is sharing the 16 I/O pins of the NAND Flash Controller with the Data pins of the WEIM when interfacing to the PSRAM. 19.9 Initialization/Application Information This section describes how to operate the NFC using its registers and its interrupts, and is divided into the following subjects: • Normal operation–In order to operate a NAND Flash device using the NFC the user should use the instructions in Section 19.9.1, “Normal Operation.” • ECC operation–ECC operation is used when an error is detected. • Write protection operation (both to the internal memory and the flash device)–Write protection is used when the programmer wishes to protect part of the NAND Flash device memory from being written except in certain cases. There are two levels of protection: software (for frequently-changed memory locations), and hardware (for memory locations whose contents are rarely changed). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-25 NAND Flash Controller (NFC) 19.9.1 Normal Operation “Normal Operations” are composed of fundamental building block operations (in Section 19.9.1.1, “Fundamental Building Block Operations”), in addition to specific operations, as shown in the flowcharts below (in Section 19.9.1.2, “NAND Flash ID Read Operation” to Section 19.9.1.7, “Hot Reset (Controller and NAND Flash Reset)”). 19.9.1.1 19.9.1.1.1 Fundamental Building Block Operations Preset Operation Figure 19-24 provides a flowchart of the NAND Flash preset operation. Start Set NFC Configuration Register (E0Ah) if needed Set NAND Flash Write Protection Command Register (E12h), Unlock Start Block Address Register (E14h), Unlock End Block Address Register (E16h), if needed. Set NAND Flash Configuration1 Register (E1Ah) (Set ECC_EN and SP_E) Pre-Setting is completed Figure 19-24. Flowchart of Preset Operation 19.9.1.1.2 NAND Flash Command Input Operation Figure 19-25 provides a flowchart of the NAND Flash Command Input operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-26 Freescale Semiconductor NAND Flash Controller (NFC) Start Write NAND Flash Command to NAND Flash Command Register (E08h) Set NAND Flash Operation Configuration2 Register(E1Ch) (Set INT to 0 and FCMD to 1 and other bits to 0) Wait No INT = High? Yes NAND Flash Command Input is completed Figure 19-25. Flowchart of NAND Flash Command Input Operation 19.9.1.1.3 NAND Flash Address Input Operation Figure 19-26 provides a flowchart of the NAND Flash Address Input operation. Start Write NAND Flash Address to NAND Flash Address Register (E06h) Set NAND Flash Operation Configuration2 Register (E1Ch) (Set INT to 0 and FADD to 1 and other bits to 0) Wait No INT = High? Yes No Is Address cycle completed? Yes NAND Flash Address Input is completed Figure 19-26. Flowchart of NAND Flash Address Input Operation MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-27 NAND Flash Controller (NFC) 19.9.1.1.4 NAND Flash Data Input Operation Figure 19-27 provides a flowchart of the NAND Flash Data Input operation. Start Set RAM Buffer Address Register (E04h) where data is loaded from host Write the NAND Flash data to RAM Buffer Set NAND Flash Operation Configuration2 Register (E1Ch) (Set INT to 0 and FDI to 1 and other bits to 0) Wait No INT = High? Yes NAND Flash Data Input is completed Figure 19-27. Flowchart of NAND Flash Data Input Operation 19.9.1.1.5 NAND Flash Data Output Operation Figure 19-28 provides a flowchart of the NAND Flash Data Output operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-28 Freescale Semiconductor NAND Flash Controller (NFC) Start Set NAND Flash Operation Configuration1 Register (E1Ah) (Set ECC_EN and SP_EN) Set RAM Buffer Address Register (E04h) where data is loaded from NAND Flash Set NAND Flash Operation Configuration2 Register (E1Ch) (Set INT to 0 and FD0 to 1 and other bits to 0) Wait INT = High? Yes Read the NAND Flash data from RAM Buffer No NAND Flash Data Output is completed Figure 19-28. Flowchart of NAND Flash Data Output Operation 19.9.1.2 NAND Flash ID Read Operation Figure 19-29 provides a flowchart of the NAND Flash ID Read operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-29 NAND Flash Controller (NFC) Start Preset Operation. Set RAM Buffer Address Register (E04h) (Set RBA to load NAND Flash ID) NAND Flash Command Input Operation (Command: 90h) NAND Flash Address Input Operation. NAND Flash Data Output Operation. Read ID data from assigned RAM buffer (refer Section 19.9.1.2.1, “NAND Flash ID Data Formats”) End Figure 19-29. Flowchart of Read NAND Flash ID Operation 19.9.1.2.1 NAND Flash ID Data Formats Format of NAND Flash ID data stored in RAM buffer (for X8 org. NAND Flash) is shown in Figure 19-30. 1st Half-Word 2nd Half-Word 3rd Half-Word RAM Buffer of RBA address 1st byte of ID 2nd byte of ID 3rd byte of ID 4th byte of ID 5th byte of ID 6th byte of ID LSB MSB Figure 19-30. NAND Flash ID Data Format (x8) The format of NAND Flash ID data stored in RAM buffer (for X16 org. NAND Flash) is shown in Figure 19-31. 1st Half-Word RAM Buffer of RBA address 1st byte of ID LSB XXh MSB 2nd Half-Word 2nd byte of ID XXh 3rd Half-Word 3rd byte of ID XXh MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-30 Freescale Semiconductor NAND Flash Controller (NFC) RAM Buffer of RBA address 4th Half-Word 4th byte of ID LSB XXh MSB 5th Half-Word 5th byte of ID XXh 6thHalf-Word 6th byte of ID XXh Figure 19-31. NAND Flash ID Data Format (x16) 19.9.1.3 NAND Flash Status Read Operation Start Preset Operation. Set RAM Buffer Address Register (E04h) (Set RBA to load NAND Flash Status Data) NAND Flash Command Input Operation (Command: 70h) NAND Flash Data Output Operation. Read ID data from assigned RAM buffer (refer to Section 19.9.1.3.1, “NAND Flash Status Data Format”) End Figure 19-32. Flowchart of Read NAND Flash Status Operation 19.9.1.3.1 NAND Flash Status Data Format The assignment of NAND Flash Status data stored in the RAM buffer (for both X8/X16 org. NAND Flash) is shown in Figure 19-33. 1st half-word 1st byte of Status LSB XXh -------MSB RAM Buffer of RBA address Figure 19-33. NAND Flash Status Data Format MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-31 NAND Flash Controller (NFC) 19.9.1.4 Read NAND Flash Data Operation Figure 19-34 shows a flowchart of the read NAND Flash data operation. Start Preset Operation. Set RAM Buffer Address Register (E04h) (Set RBA to load NAND Flash Status Data) NAND Flash Command Input Operation (Command: NAND Flash Read Command) NAND Flash Address Input Operation (Address: NAND Flash address to be Read) NAND Flash Command Input Operation (Command: NAND Flash Read Confirm Command, which is required with NAND Flash devices that are 1 Gbyte or larger) NAND Flash Data Output Operation. Check ECC Status Register (E0Ch) and do next step according to the result End Figure 19-34. Flowchart of Read NAND Flash Data Operation 19.9.1.5 Program NAND Flash Data Operation Figure 19-35 shows a flowchart of the program NAND Flash data operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-32 Freescale Semiconductor NAND Flash Controller (NFC) Start Preset Operation. Set RAM Buffer Address Register (E04h) (Set RBA to load data to be programmed from Host) NAND Flash Command Input Operation (Command: Data Loading Command) NAND Flash Address Input Operation (Address: NAND Flash address to be Programmed) NAND Flash Data Input Operation. NAND Flash Command Input Operation (Command: Confirm Command NAND Flash Status Read Operation. End Figure 19-35. Flowchart of Program NAND Flash Data Operation 19.9.1.6 Erase NAND Flash Data Operation Figure 19-36 shows a flowchart of the erase NAND Flash data operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-33 NAND Flash Controller (NFC) Start Preset Operation. NAND Flash Command Input Operation (Command: Erase Command) NAND Flash Address Input Operation NAND Flash Command Input Operation (Command: Confirm Command NAND Flash Status Read Operation. End Figure 19-36. Flowchart of Erase NAND Flash Operation 19.9.1.7 Hot Reset (Controller and NAND Flash Reset) A warm (or “hot”) reset causes the NFC and the NAND Flash device cease their current operation and causes the internal registers to revert to their default state. Figure 19-37 shows a flowchart of a hot reset operation. Start Preset Operation. NAND Flash Command Input Operation (Command: ffh) End Figure 19-37. Flowchart of Hot Reset Operation 19.9.2 19.9.2.1 ECC Operation ECC Normal Operation When NFC accesses the NAND Flash device for Program operation, it generates ECC code (24 bits for Main area data and 10 bits for spare area data). When NFC accesses the NAND Flash device for a Read MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-34 Freescale Semiconductor NAND Flash Controller (NFC) operation, it generates ECC code, detects the error number and position and corrects a 1-bit error, if applicable. Table 19-28 shows ECC code assignment of NAND Flash spare area. This ECC code is updated by NFC automatically. After Read operation, AHB host can know whether there is error or not by reading the status register (see ECC_Status_Result register in Section 19.7.6, “Controller Status and Result of Flash Operation (ECC_STATUS_RESULT)”). Error type can be: a) no error, b) 1bit error (correctable), or c) 2 or more bit error (uncorrectable). Since generated ECC code at read/program operation is not updated to the internal buffer RAM, but is updated to NAND Flash spare area immediately upon program operation, AHB host can read generated ECC code only from NAND Flash spare area. 19.9.2.2 ECC Bypass Operation In ECC bypass operation, NFC generates an ECC result which indicates error position (refer ECC Result table), but doesn’t correct the error. After a Read operation, host can know whether there is an error or not by reading the status register (refer ECC status register table). Error type is divided into no error, 1bit error (correctable), or 2bits error (uncorrectable). In 1bit error case, the Host can correct the error by itself after reading the ECC Result register (see ECC_Status_Result register in Section 19.7.6, “Controller Status and Result of Flash Operation (ECC_STATUS_RESULT)”). Table 19-28. ECC Code/Result Readability Read Operation Operation ECC Code from Spare Area Buffer Invalid (Pre-written ECC code 1) Invalid (Pre-written ECC code) ECC Result from Register Valid Valid Program Operation ECC Code from Spare Area Buffer Invalid (old data 2) Invalid (old data) ECC Result from Register — — ECC operation ECC bypass 1 2 Pre-written ECC code: ECC code which is previously written to NAND Flash spare area in program operation. Old data: ECC code is not updated to spare buffer, so ECC code placement of spare buffer remains old data. 19.9.2.3 How to Operate ECC In order to generate ECC and carry out correction by NFC, Program and Read with ECC operation. In order to generate ECC by NFC and carry out correction by AHB host, Program with ECC operation and Read without ECC operation NOTE AHB host can read ECC results from ECC_Status_Result register (see Section 19.7.6, “Controller Status and Result of Flash Operation (ECC_STATUS_RESULT)”) after a read operation in both ECC Normal operation and ECC Bypass cases. When NFC reads NAND Flash data, ECC code for read data is not updated into RAM buffer. 19.9.3 Write Protection Operation NFC offers a software write protection feature, and a hardware write protection feature. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-35 NAND Flash Controller (NFC) 19.9.3.1 Write Protection for RAM Buffer (LSB 1 Kbyte) NFC offers a software write protection feature for the first 2 pages (main + spare area data) of RAM buffer, which protects RAM buffer data. This write protection is carried out by setting BLS bit of the NFC_CONFIGURATION register. The default state is locked state, and first 2 pages go to this state after a cold or warm reset. Write protection availability for main/spare memory regions in the RAM buffer are described on Table 19-29. A state diagram of RAM buffer write protection is shown in Figure 19-38. Table 19-29. Write Protection for Main/Spare RAM Buffer Main Area 1st page RAM buffer 2nd page RAM buffer 3rd page RAM buffer 4th page RAM buffer Spare Area Write Protection Available Write Protection Not available NFC_CONFIGURATION register[1:0] = 00/01/11 Unlocked NFC_CONFIGURATION register[1:0] = 10 Device in Cold or Warm Reset Initial state Locked Figure 19-38. State Diagram of RAM Buffer Write Protection 19.9.3.2 Write Protection Modes NFC offers both hardware and software Write Protection options for the NAND Flash device. Software Write Protection feature is used by executing LOCK BLOCK command or LOCK-TIGHT BLOCK command, and Hardware Write Protection feature is used by executing a cold or warm reset. The WP signal is asserted only upon POR. 19.9.3.3 Write Protection Commands There are two write protection states: Locked and Lock-Tight. • Locked state means that memory block in question is write protected (it cannot be written to), but UNLOCK command can “un”-lock it. Useful for frequently changed memory blocks. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-36 Freescale Semiconductor NAND Flash Controller (NFC) • Lock-Tight state is a higher level of protection, and means that memory block in question is write protected, but UNLOCK command cannot unlock it. Useful for memory blocks whose contents are rarely changed. The following summarizes the locking functionality: • All blocks power-up in a locked state. The UNLOCK command can unlock these blocks. • LOCK-TIGHT BLOCK command locks blocks and prevents it (them) from being unlocked. • Lock-Tight state can be reverted to locked state only when Cold/Warm reset is executed. • Writing to unlock start/end address registers (Unlock_Start_Blk_Add and Unlock_End_Blk_Add) while NFC is in Lock-Tight state does not affect the unlock address. 19.9.3.4 Write Protection Status The current Write Protection status of the NFC can be read in NAND Flash Write Protection status register (NAND_Flash_WR_Pr_St). There are three bits: US,LS, and LTS, which are not cleared by hot reset. These Write Protection status bits are updated as soon as the Write Protection command is entered. Figure 19-39 shows a state diagram for the write protection of the NFC. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-37 NAND Flash Controller (NFC) hreset pin: High and Start block address + End block address + Unlock block Command Unlocked hreset pin: High and Lock block Command hreset pin: High and Start block address + End block address + Unlock block Command Initial state Locked Cold or Warm reset hreset pin: High and Lock-tight block Command LockTight hreset pin: High and Lock-tight block Command hreset pin: Rising edge (This occurs at Cold reset or Warm reset) Figure 19-39. State Diagram of NAND Flash Write Protection 19.9.3.4.1 Lock Sequence The following describes the “lock” sequence: 1. Command Sequence: LOCK BLOCK Command (02h) 2. All blocks default to locked after initial Cold reset or Warm reset. 3. Locking some of the blocks is not available; all memory blocks are locked upon reset. 4. Unlocked memory blocks can be locked by using the LOCK BLOCK command. Status of a locked memory block can be changed to Unlocked or Lock-tight using appropriate software commands. 19.9.3.4.2 Unlock Sequence Command(04h) The following describes the “unlock” sequence: 1. Command Sequence: Start block address + End block address + UNLOCK BLOCK MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-38 Freescale Semiconductor NAND Flash Controller (NFC) 2. Unlocked blocks can be programmed or erased. 3. Status of unlocked block can be changed to locked/lock-tight using appropriate software command. 4. Only one sequential area can be released to unlocked state from locked state; Unlocking multi-areas is not available. 19.9.3.4.3 Lock-tight Sequence The following describes the “lock-tight” sequence: 1. Only locked blocks can be “locked-tight” by the LOCK-TIGHT BLOCK command. 2. Command Sequence: LOCK-TIGHT BLOCK Command (01h) 3. Unlocking multi area is not available 4. Lock-tight blocks revert to the locked state at Cold/Warm reset. 19.9.4 Memory Configuration Examples Table 19-30 shows NFC Pin configurations for various NAND Flash devices. Figure 19-40 and Figure 19-41 show memory connection for various 8-bit and 16-bit configuration. Table 19-30. Examples for NFC Pin Configuration for Selected Memory Devices Device SAMSUNG K9F5608 (32M x 8-bit) Page size is 528 bytes. SAMSUNG K9F5616 (16M x 16bit) Page size is 528 bytes. SAMSUNG K9F1G08 (128M x 8-bit) Page size is 2112 bytes. SAMSUNG K9F1G16 (64M x 16bit) Page size is 2112 bytes. BOOT NO YES NO YES NO YES NO YES NFC_FMS 0 0 0 0 1 1 1 1 NF8BOOT 1 0 1 1 1 0 1 1 NF16BOOT 1 1 1 0 1 1 1 0 NF_16BIT_SEL 0 X 1 X 0 X 1 X NOTE The NFC can support High Speed (HS) NAND Flash by supplying higher frequencies (up to 50 MHz) to the Flash Clock input. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-39 NAND Flash Controller (NFC) 8 bits of the ADRESS BUS ipp_nfc_read_data_out[15] ipp_nfc_read_data_out[14] ipp_nfc_read_data_out[13] ipp_nfc_read_data_out[12] ipp_nfc_read_data_out[11] ipp_nfc_read_data_out[10] ipp_nfc_read_data_out[9] ipp_nfc_read_data_out[8] ipp_nfc_read_data_in[15] ipp_nfc_read_data_in[14] ipp_nfc_read_data_in[13] ipp_nfc_read_data_in[12] ipp_nfc_read_data_in[11] ipp_nfc_read_data_in[10] ipp_nfc_read_data_in[9] ipp_nfc_read_data_in[8] A25_NFIO15 A24_NFIO14 A23_NFIO13 A22_NFIO12 A21_NFIO11 A15_NFIO10 A14_NFIO9 A13NFIO8 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 32 M x 8 NAND Flash ipp_nfc_read_data_out[7] ipp_nfc_read_data_out[6] ipp_nfc_read_data_out[5] ipp_nfc_read_data_out[4] ipp_nfc_read_data_out[3] ipp_nfc_read_data_out[2] ipp_nfc_read_data_out[1] ipp_nfc_read_data_out[0] ipp_nfc_read_data_in[7] ipp_nfc_read_data_in[6] ipp_nfc_read_data_in[5] ipp_nfc_read_data_in[4] ipp_nfc_read_data_in[3] ipp_nfc_read_data_in[2] ipp_nfc_read_data_in[1] ipp_nfc_read_data_in[0] NFIO7 NFIO6 NFIO5 NFIO4 NFIO3 NFIO2 NFIO1 NFIO0 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 ipp_nfc_ce_out ipp_nfc_cle_out ipp_nfc_ale_out ipp_nfc_re_out ipp_nfc_we_out ipp_nfc_wp_out ipp_nfc_rb_in NFCE NFCLE NFALE NFRE NFWE NFWP CE CLE ALE RE WE WP NFRB Vcc R/B VccQ Vcc Vss GND GND Figure 19-40. 256-Mbit (32 Mbit x 8 Bit) NAND Flash Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-40 Freescale Semiconductor NAND Flash Controller (NFC) 16M x 16 NAND Flash 8 bits of the ADRESS BUS ipp_nfc_read_data_out[15] ipp_nfc_read_data_out[14] ipp_nfc_read_data_out[13] ipp_nfc_read_data_out[12] ipp_nfc_read_data_out[11] ipp_nfc_read_data_out[10] ipp_nfc_read_data_out[9] ipp_nfc_read_data_out[8] ipp_nfc_read_data_in[15] ipp_nfc_read_data_in[14] ipp_nfc_read_data_in[13] ipp_nfc_read_data_in[12] ipp_nfc_read_data_in[11] ipp_nfc_read_data_in[10] ipp_nfc_read_data_in[9] ipp_nfc_read_data_in[8] NFIO7 NFIO6 NFIO5 NFIO4 NFIO3 NFIO2 NFIO1 NFIO0 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 A25_NFIO15 A24_NFIO14 A23_NFIO13 A22_NFIO12 A21_NFIO11 A15_NFIO10 A14_NFIO9 A13NFIO8 I/O 15 I/O 14 I/O 13 I/O 12 I/O 11 I/O 10 I/O 9 I/O 8 ipp_nfc_read_data_out[7] ipp_nfc_read_data_out[6] ipp_nfc_read_data_out[5] ipp_nfc_read_data_out[4] ipp_nfc_read_data_out[3] ipp_nfc_read_data_out[2] ipp_nfc_read_data_out[1] ipp_nfc_read_data_out[0] ipp_nfc_read_data_in[7] ipp_nfc_read_data_in[6] ipp_nfc_read_data_in[5] ipp_nfc_read_data_in[4] ipp_nfc_read_data_in[3] ipp_nfc_read_data_in[2] ipp_nfc_read_data_in[1] ipp_nfc_read_data_in[0] ipp_nfc_ce_out ipp_nfc_cle_out ipp_nfc_ale_out ipp_nfc_re_out ipp_nfc_we_out ipp_nfc_wp_out ipp_nfc_rb_in NFCE NFCLE NFALE NFRE NFWE NFWP CE CLE ALE RE WE WP NFRB Vcc R/B VccQ Vcc Vss GND GND Figure 19-41. 256 Mbit (16 M x 16 Bit) NAND Flash Connection Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 19-41 NAND Flash Controller (NFC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 19-42 Freescale Semiconductor Chapter 20 Personal Computer Memory Card International Association (PCMCIA) Controller This chapter describes the Personal Computer Memory Card International Association (PCMCIA) controller for the i.MX27 processor. The association standard is PCMCIA 2.1, which defines the use of memory and I/O devices as insertable and exchangeable peripherals for personal computers or PDAs. Examples of these types of devices include compact flash and WLAN adapters. 20.1 Overview The PCMCIA host adapter module provides the control logic for PCMCIA socket interfaces, and requires some additional external analog power switching logic and buffering. The additional external buffers allow the PCMCIA host adapter module to support one PCMCIA socket. Figure 20-1 shows the PCMCIA controller block diagram. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-1 Personal Computer Memory Card International Association (PCMCIA) Controller PC Card A[25:0] D[15:0] CARD interface PCMCIA controller OE WE IORD IOWR REG WAIT CE1 AHB bus CE2 R/W AHB interface POE RESET access error RDY/BSY IOIS16/WP BVD1 BVD2 CD1 CD2 VS1 VS2 Vcc/Vpp Card Power Circuit pcmcia_access PWRON Endianness INT GEN Static Signals Interface interrupts debug_signals Buffer with OE Transparent latch Transceiver Pull Up to chip Vcc Pull Up to card Vcc Figure 20-1. PCMCIA Controller Interface Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-2 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller 20.2 Features The PCMCIA controller includes the following features: • A host adapter interface fully compliant with the PCMCIA standard release 2.1 (PC Card -16). — Supports one PCMCIA socket — Supports hot-insertion — Supports card detection — Provides mappings to common memory space, attribute memory space, and I/O space. Each space is up to 64 Mbyte in size. — Supports 5 memory windows — Generates a single interrupt to the ARM9 core — Provides fully programmable PC card access timing — Handles interrupts from the card • The PCMCIA controller is part of the EMI complex and shares its pins with the EIM, SDRAMC, and NAND flash controller. • Supports ATA disk emulation 20.3 20.3.1 External Signal Description Detailed Signal Descriptions Table 20-2 shows the PCMCIA signal descriptions for the pins that are used to control the PCMCIA interface. Table 20-2. PCMCIA Signal Descriptions Signal In/Out Standard Pins A[25:0] D[15:0] CE1, CE2 OE WE Output I/O Output Output Output Address Bus. These address bus output lines allows direct addressing of up to 64 Mbytes of linear memory on the PCMCIA card. Data Bus. Bidirectional. PCMCIA socket data I/O pins. Card Enable. When a PCMCIA access is performed, CE1 enables even bytes, CE2 enables odd bytes. See also Section 20.5.9, “Data and Control Signals Relations” and Table 20-20. Output Enable. During PCMCIA accesses, OE is used to drive memory read data from a PC card in a PCMCIA socket. Write Enable. Program during PCMCIA access, WE is used to latch memory write data to the PC card in a PCMCIA socket. Can also be used as the programming strobe for PC cards using programmable memory technologies. Register Accesses Attribute Memory Select. When REG is asserted during PCMCIA access, card access is limited to attribute memory when a memory access occurs (WE or OE are asserted) and to I/O ports when I/O access occurs (IORD or IOWR are asserted). if REG is asserted, accesses to common memory are blocked. Description REG Output MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-3 Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-2. PCMCIA Signal Descriptions (continued) Signal IORD In/Out Output Description I/O Read. This output goes active (low) for I/O reads from the socket. This signal is asserted together with REG and it is used to read data from the PC card I/O space. IORD is valid only when REG and either CE1 or CE2 signals are also asserted. I/O Write. This output goes active (low) for I/O write to the socket. Asserted with REG during PCMCIA accesses, used to latch data into the PC cards I/O space. IOWR is valid only when REG and either CE1 and CE2 signals are also asserted. Extend bus cycle. Input. Asserted by the PC card to delay completion of the pending memory or I/O cycle. I/O port is 16-bits. When the card and its socket are programmed for I/O interface operation, this signal is used as IOIS16 and must be asserted by the PC card when the address on the bus corresponds to an address on the PC card and the I/O port being addressed supports 16-bit accesses. If the I/O region in which the address resides is programmed as 8-bit wide IOIS16 is ignored. Write Protect. When the card and socket are programmed for memory interface operation, this signal is used as WP. It reflects the state of the write protect of the PC card. The PC card must assert WP when the card switch is enabled. It must be negated when the switch is disabled. For a PC card that is writable without a switch, WP must be connected to ground.If the PC card is permanently write-protected, WP must be connected to Vcc. Voltage sense. Input. Generated by the card to notify the socket of the card’s CIS VCC requirements. Card Detect. Provide proper detection of card insertion. They must be connected to ground internally on the PC card, thus, these signals are forced low when a card is placed on the socket. These signals must be pulled up to system Vcc to allow card detection to function when the card socket is powered down. These two lines can be used for battery voltage detection or status change/speaker. Battery Voltage Detect. When the card and its socket are programmed for memory interface operation, these signals are generated by the PC card with on board battery to report the battery condition. See Table 20-3 for a description of the logical combinations representing battery condition. Status Change. When the card is in I/O interface operation, BVD1 is used as Status Change and is generated by the I/O PC card. Status Change must be held negated when the “signal on change” bit and the “change” bit in the card status register are either or both zero. STSCHG must be asserted when both bits = 1. Speaker. Input. When the card is in I/O interface operation BVD2 is used as Audio Digital Waveform. A card that does not this capability should drive SPKR high. READY/IREQ Input Ready. When the card and its socket are programmed for memory interface operation, this signal is used as RDY/BSY and must be asserted by a PC card to indicate that a PC card is busy processing a previous write command. When the card and its socket are programmed for I/O interface operation, this signal is used as IREQ and must be asserted by a PC card to indicate that a device on the PC card requires service by host software. Must be held negated when no interrupt is requested. Card Reset. Output. Provided to clear the card’s configuration option register, thus placing the card in its default (memory only interface) state and beginning an additional card initialization. RESET signal has inverted polarity when in TrueIDE mode. See also Section 20.5.10, “True IDE Mode Access.” IOWR Output WAIT IOIS16/WP Input Input VS1, VS2 CD1, CD2 Input Input BVD1/STSCHG, BVD2/SPKR Input RESET Output MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-4 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-2. PCMCIA Signal Descriptions (continued) Signal In/Out Description PCMCIA Controller Module Pins POWERON R/W POE Input Output Output Power is On. The card supply circuitry can use this signal as an interrupt to notify when the card’s power supply reaches the full required voltage. External Transceiver Direction. Negated during read cycles and asserted during write. PCMCIA buffers output enable. An output line reflecting the value of PGCR[POE] bit. Used to three-state control signals and to latch the address. See Figure 20-1 for a simplified block diagram. Speaker Output. Provides a digital audio waveform to be driven to the system’s speaker. This signal is connected directly to the SPKR input. Endianness control. Input. This input pin defines the Endianness mode of the module. ‘1’ is Big Endian. This module should be tied high or low. See Section 20.5.13, “Endianness Support.” This output signal is used to indicate that a valid access to the card is performed. This signal is used by the EMI muxing to select the pcmcia_if port and drive it to the pins. This is the interrupt line from the pcmcia_if module. This signal is a logical OR of all interrupts generated by the pcmcia_if. This interrupt is generated if the voltage sense #1 input signal from the card has changed. This interrupt is generated if the voltage sense #2 input signal from the card has changed. This interrupt is generated if the write protect input signal from the card has changed. This interrupt is generated if the card detect #1 input signal from the card has changed. This interrupt is generated if the card detect #2 input signal from the card has changed. This interrupt is generated if the battery voltage detect #1 input signal from the card has changed. This interrupt is generated if the battery voltage detect #2 input signal from the card has changed. This interrupt is generated if RDY/IREQ pin is low. This interrupt is generated if RDY/IREQ pin is high. This interrupt is generated if a rising edge was detected on the RDY/IREQ pin. This interrupt is generated if a falling edge was detected on the RDY/IREQ pin. This interrupt is generated if the POWERON input signal from the card has changed This status change interrupt is a logic AND of the following: ipi_int_vs1, ipi_int_vs2, ipi_int_wp, ipi_int_cd1, ipi_int_cd2, ipi_int_bvd1, ipi_int_bvd2, ipi_int_poweron. This interrupt line is a logic AND of the following: ipi_int_rdy_l, ipi_int_rdy_h, ipi_int_rdy_r, ipi_int_rdy_f. This interrupt is generated following an error detected by the PCMCIA controller. See Section 20.5.4.1, “Error Interrupt Conditions” for detailed description of error cases. SPKROUT Endianness Output Input pcmcia_access ipi_int_pcmcia ipi_int_vs1 ipi_int_vs2 ipi_int_wp ipi_int_cd1 ipi_int_cd2 ipi_int_bvd1 ipi_int_bvd2 ipi_int_rdy_l ipi_int_rdy_h ipi_int_rdy_r ipi_int_rdy_f ipi_int_poweron ipi_int_sts ipi_int_ireq ipi_int_err Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Table 20-3 provides descriptions for the BVD1 and BVD2 signals. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-5 Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-3. BVD1 and BVD2 Descriptions BVD1 1 1 BVD2 1 0 Description battery is in good condition battery is in warning condition and should be replaced, although data integrity on the card is assured. battery is in no longer serviceable and data is lost. 0 X 20.4 Memory Map and Register Definition Table 20-4. PCMCIA Controller Memory Map Address 0xD800_4000 (PIPR) 0xD800_4004 (PSCR) 0xD800_4008 (PER) 0xD800_400C (PBR0) 0xD800_4010 (PBR1) 0xD800_4014 (PBR2) 0xD800_4018 (PBR3) 0xD800_401C (PBR4) 0xD800_4028 (POR0) 0xD800_402C (POR1) 0xD800_4030 (POR2) 0xD800_4034 (POR3) 0xD800_4038 (POR4) 0xD800_4044 (POFR0) Register PCMCIA input Pins Register PCMCIA Status Changed Register PCMCIA Enable Register PCMCIA Base Register 0 PCMCIA Base Register 1 PCMCIA Base Register 2 PCMCIA Base Register 3 PCMCIA Base Register 4 PCMCIA Option Register 0 PCMCIA Option Register 1 PCMCIA Option Register 2 PCMCIA Option Register 3 PCMCIA Option Register 4 PCMCIA Offset Register 0 Access Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x0000_00—– 0x0000_0000 0x0000_1018 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 20.4.1.1/20-9 20.4.1.2/20-11 20.4.1.3/20-12 20.4.1.4/20-14 20.4.1.4/20-14 20.4.1.4/20-14 20.4.1.4/20-14 20.4.1.4/20-14 20.4.1.5/20-15 20.4.1.5/20-15 20.4.1.5/20-15 20.4.1.5/20-15 20.4.1.5/20-15 20.4.1.6/20-19 Table 20-4 shows the memory map of the PCMCIA controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-6 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-4. PCMCIA Controller Memory Map (continued) Address 0xD800_4048 (POFR1) 0xD800_404C (POFR2) 0xD800_4050 (POFR3) 0xD800_4054 (POFR4) 0xD800_4060 (PGCR) 0xD800_4064 (PGSR) Register PCMCIA Offset Register 1 PCMCIA Offset Register 2 PCMCIA Offset Register 3 PCMCIA Offset Register 4 PCMCIA General Control Register PCMCIA General Status Register Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0008 0x0000_0000 Section/Page 20.4.1.6/20-19 20.4.1.6/20-19 20.4.1.6/20-19 20.4.1.6/20-19 20.4.1.7/20-20 20.4.1.8/20-21 20.4.1 Register Summary Table 20-2 shows the key to the register fields, and Table 20-5 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 20-2. Key to Register Fields Table 20-5. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — Resets to zero. Resets to one. Undefined at reset. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-7 Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-5. Register Figure Conventions (continued) Convention u Unaffected by reset. Description [signal_name] Reset value is determined by polarity of indicated signal. Table 20-6 shows the PCMCIA register summary. Table 20-6. PCMCIA Controller Register Summary Name 0xD800_4000 (PIPR) R W R 0 0 0 0 0 0 0 PO WE BVD BVD RDY RON 2 1 t 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD WP VS W 0xD800_4004 (PSCR) R W R W 0xD800_4008 (PER) R W R W 0 0 0 PO ERRI WE RDY RDY RDY RDY BVD BVD CDE WP VSE VSE CDE2 NTEN RON RE FE HE LE E2 E1 1 E 2 1 EN 0 0 0 PBA[25:16] 0 0 0 0 0 0 0 0 PO WC w1c 0 RDY RDY RDY RDY BVD BVD CDC2 R F H L C2 C1 w1c 0 w1c 0 0 0 w1c w1c 0 0 w1c 0 CD C1 w1c 0 WP VSC VSC C 2 1 w1c 0 w1c 0 w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xD800_400C (PBR0) 0xD800_4010 (PBR1) 0xD800_4014 (PBR2) 0xD800_4018 (PBR3) 0xD800_401C (PBR4) R W 0 0 0 R W PBA[15:0] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-8 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-6. PCMCIA Controller Register Summary (continued) Name 0xD800_4028 (POR0) 0xD800_402C (POR1) 0xD800_4030 (POR2) 0xD800_4034 (POR3) 0xD800_4038 (POR4) 0xD800_4044 (POFR0) 0xD800_4048 (POFR1) 0xD800_404C (POFR2) 0xD800_4050 (POFR3) 0xD800_4054 (POFR4) 0xD800_4060 (PGCR) R 0 W R W PSST[4:0] PSHT[5:0] 0 BSIZE 0 PV WPE N WP PRS PPS PSL[6:0] PSS T[5] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 R W R W 0 0 0 0 0 0 POFA[25:16] POFA[15:0] R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM SPK RES POE EN REN ET 0 0 0 0 0xD800_4064 (PGSR) R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWIN LPE E w1c w1c SE w1c CDE w1c WP E w1c 20.4.1.1 PCMCIA Input Pins Register (PIPR) This register indicates the status of inputs from the PCMCIA card to the host: battery voltage detect, card detect, ready, voltage sense, and write protect status (BVD, CD, RDY, VS, WP). PIPR is a read-only register. The register should be clocked with a gated clock. This clock is active only when trying to access the peripheral. When accessing this register, a 2-wait state is added by the PCMCIA controller. The reset values in Figure 20-3 are the reset values of the PIPR flip-flops. The actual data read reflects the value to the PCMCIA controller. Table 20-7 provides the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-9 Personal Computer Memory Card International Association (PCMCIA) Controller 0xD800_4000 (PIPR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 POW ERO N RDY BVD2 BVD1 CD WP VS 0 — — — — — — — — Figure 20-3. PCMCIA Input Pins Register (PIPR) Table 20-7. PIPR Field Descriptions Field 31–9 Reserved. Description 8 Power is on. This bit indicates the status of the power signal from the card. POWERON 0 Card indicates that it did not reach its power supply requirements. 1 Card indicates Power is on. 7 RDY RDY/BSY/IREQ. When the card and its socket are in memory interface operation, this bit functions as RDY/BSY indicating that the card is busy processing a previous write command. When the card and its socket are in I/O interface operation, this bit functions as IREQ indicating that a device on the PC card requires service by host software. This interrupt could be either level or pulse and can have either high or low polarity. This data can be read in the CIS of the card itself. 0 PC card is busy processing a previous command or performing initialization. 1 PC card is ready to accept a new data-transfer command. Battery Voltage detect 2/SPKR IN. When the card and its socket are in memory interface mode, this bit reflects the BVD2 signal. For details about settings, see Table 20-3. When the card and its socket are in I/O mode, this bit is used as SPKR IN (speaker in) for a Binary Audio signal, an optional signal which is available only when the card and the socket have been configured for the I/O interface. 5 BVD1 Battery Voltage detect 1/STSCHG IN. When the card and its socket are in memory interface mode, this bit reflects the BVD1 signal. For details, see Table 20-3. When the card and its socket are in I/O mode, this bit is used as STSCHG (status change) indicator. 0 Status has not changed. 1 Status has changed. Note: To find out the exact signals that changed value, the Status Change register of the card itself should be read. 6 BVD2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-10 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-7. PIPR Field Descriptions (continued) Field 4–3 CD Description Card Detect 1 and Card Detect 2. Card Detect 1 and Card Detect 2 bits indicate a proper detection of card insertion. When both bits are ‘0’, the card is inserted properly. 00 Card is inserted properly. 01 Card is inserted improperly. 11 Card is inserted improperly. 11 Card is not inserted. These bits are asynchronous. Write Protect. This bit reflects the state of the write protect switch on the PC card. 0 Write Protect Switch is disabled. 1 Write Protect switch is enabled. Voltage Sensor. VS bits notify the host of the card’s Card Information Structure (CIS) Vcc requirements. This data can be used by the host to control external voltage transceiver. For details see the PCMICA PCCARD standard. 2 WP 1–0 VS 20.4.1.2 PCMCIA Status Change Register (PSCR) Each bit in the PSCR register is set any time a change in the signal it monitors occurs. The status is cleared using a “write 1 to clear” operation on the register. The contents of PSCR, shown in Figure 20-4, are logically ANDed with the PER register to generate a PCMCIA interrupt. The register should be clocked with a gated clock. This clock is active only when trying to access the peripheral. When accessing this register, two wait states are added by the PCMCIA. The inputs to the module are sampled twice before being read, to avoid meta-stability. This is done in spite of the fact that interrupts are generated even when the clock is off. The bit assignments for the PSCR register are shown in Figure 20-4. The bit field descriptions are provided in Table 20-8. Each of the bits in Table 20-8 (excluding RDYL and RDYHare) set (=1) when a change occurs in its corresponding parameter. It is zeroed on system reset. RDYL and RDYH are level sensitive and therefore, reflect the value of the RDY pin and have no reset value. 0xD800_4004 (PSCR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 POWC RDYR RDYF RDYH RDYL w1c w1c 0 w1c 0 w1c — w1c — BVDC BVDC CDC2 CDC1 WPC VSC2 VSC1 2 1 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 0 0 0 0 0 Figure 20-4. PCMCIA Status Change Register (PSCR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-11 Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-8. PSCR Field Descriptions Field 31–12 11 POWC 10 RDYR 9 RDYF 8 RDYH 7 RDYL 6 BVDC2 5 BVDC1 4 CDC2 3 CDC1 2 WPC 1 VSC2 0 VSC1 Reserved. POWERON signal changed. 0 No change has occurred in the POWERON signal since system reset. 1 A change has occurred in the POWERON signal since system reset. RDY/IREQ pin rising edge detect. Device and socket positive edge interrupt. 0 No rising edge has occurred in RDY since system reset. 1 A rising edge occurred in RDY since system reset. RDY/IREQ pin falling edge detect. Device and socket negative edge interrupt. 0 No falling edge has occurred in RDY since system reset. 1 A falling edge occurred in RDY since system reset. This bit reflects value of RDY signal. RDY/IREQ pin is high indicating a device and socket high level interrupt. RDY/IREQ pin is low. Device and socket loveless interrupt. This bit is the inverted value of RDY signal Battery Voltage 2/SPKR IN Changed. 0 No change has occurred in Battery Voltage #2 or SPKR since system reset. 1 A change has occurred in Battery Voltage #2 or SPKR since system reset. Battery Voltage 1/STSCHG Changed. 0 No change has occurred in Battery Voltage #1 since system reset. 1 A change has occurred in Battery Voltage #1 since system reset. Card Detect 2 hanged. 0 No change has occurred in card detect #2 since system reset. 1 A change has occurred in card detect #2 since system reset. Card Detect 1 Changed. 0 No change has occurred in card detect #1 since system reset. 1 A change has occurred in card detect #1 since system reset. Write Protect Changed. 0 No change has occurred in the write protect status since system reset. 1 A change has occurred in the write protect status since system reset. Voltage Sense2 Changed. 0 No change has occurred in voltage sensor #2 since system reset. 1 A change has occurred in voltage sensor #2 since system reset. Voltage Sense1 Changed. 0 No change has occurred in voltage sensor #1 since system reset. 1 A change has occurred in voltage sensor #1 since system reset. Description 20.4.1.3 PCMCIA Enable Register (PER) Setting a bit in PER, shown in Figure 20-5, enables the corresponding interrupt. When accessing this register, one wait state will be added by the PCMCIA. Table 20-9 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-12 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller 0xD800_4008 (PER) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 POW ERRI RDYR RDYF RDYH RDYL BVDE BVDE ERO CDE2 CDE1 WPE VSE2 VSE1 NTEN E E E E 2 1 NEN 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Figure 20-5. PCMCIA Enable Register (PER) Table 20-9. PER Field Descriptions Field 31–13 12 ERRINTEN Reserved. Error Interrupt Enable. Setting this bit enables the interrupt as a result of an error signal. 0 Interrupt is disabled. 1 Interrupt is enabled. Note that the default is to enable the interrupt. Power is On Interrupt Enable. Setting this bit enables the interrupt as a result of any Power On signal change. 0 Interrupt is disabled. 1 Interrupt is enabled. RDY/IREQ pin rising edge interrupt enable. 0 Interrupt is disabled. 1 Interrupt is enabled. RDY/IREQ pin falling edge interrupt enable. 0 Interrupt is disabled. 1 Interrupt is enabled. RDY/IREQ pin is high level interrupt enable. 0 Interrupt is disabled. 1 Interrupt is enabled. RDY/IREQ pin is low level interrupt enable. 0 Interrupt is disabled. 1 Interrupt is enabled. Battery Voltage 2/SPKR IN interrupt enable. Setting this bit enables the interrupt as a result of any signal change from battery voltage sensor #2 OR from the SPKR IN signal. 0 Interrupt is disabled. 1 Interrupt is enabled. Battery Voltage 1/STSCHG interrupt enable. Setting this bit enables the interrupt as a result of any signal change from the battery voltage sensor #1. 0 Interrupt is disabled. 1 Interrupt is enabled. Description 11 POWERONEN 10 RDYRE 9 RDYFE 8 RDYHE 7 RDYLE 6 BVDE2 5 BVDE1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-13 Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-9. PER Field Descriptions (continued) Field 4 CDE2 Description Card Detect 2 interrupt enable. Setting this bit enables the interrupt as a result of any signal change from card detect #2. Note: The default setting enables the interrupt. 0 Interrupt is disabled. 1 Interrupt is enabled. Card Detect 1 interrupt enable. Setting this bit enables the interrupt as a result of any signal change from card detect #1 Note: The default setting enables the interrupt. 0 Interrupt is disabled. 1 Interrupt is enabled. Write Protect interrupt enable. Setting this bit enables the interrupt as a result of any signal change in the write protect status. 0 Interrupt is disabled. 1 Interrupt is enabled. Voltage sense2 interrupt enable. Setting this bit enables the interrupt as a result of any signal change from voltage sensor #2. 0 Interrupt is disabled. 1 Interrupt is enabled. Voltage sense1 interrupt enable. Setting this bit enables the interrupt as a result of any signal change from voltage sensor #1. 0 Interrupt is disabled. 1 Interrupt is enabled. 3 CDE1 2 WPE 1 VSE2 0 VSE1 20.4.1.4 PCMCIA Base Registers 0–4 (PBR0–PBR4) This is compared to the address bus to determine if a PCMCIA window is being accessed by an internal bus master. PBA is used in conjunction with POR[BSIZE]. When accessing this register, 1-wait state will be added by the PCMCIA. The field assignments for this register are shown in Figure 20-6. Table 20-10 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-14 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller 0xD800_400C (PBR0) 0xD800_4010 (PBR1) 0xD800_4014 (PBR2) 0xD800_4018 (PBR3) 0xD800_401C (PBR4) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 PBA[25:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PBA[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-6. PCMCIA Base Registers 0–4 (PBR0–PBR4) Table 20-10. PBR0–PBR4 Field Descriptions Field 31–26 25–0 PBA Reserved. PCMCIA Base Address. Description 20.4.1.5 PCMCIA Option Registers 0–4 (POR0–POR4) The POR registers shown in Figure 20-7 handle time manipulation, provide the address mask for the bank size, and define the region, write protection, and validation. When accessing this register 1-wait state will be added by the PCMCIA. Table 20-11 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-15 Personal Computer Memory Card International Association (PCMCIA) Controller 0xD800_4028 (POR0) 0xD800_402C (POR1) 0xD800_4030 (POR2) 0xD800_4034 (POR3) 0xD800_4038 (POR4) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User Read/Write 18 17 16 R W Reset 0 0 PV WPEN 0 WP 0 PRS 0 0 PPS 0 0 0 0 PSL[6:0] 0 0 0 0 PSST[5] 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PSST[4:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSHT[5:0] BSIZE Figure 20-7. PCMCIA Option Registers 0–4 (POR0–POR4) Table 20-11. POR0–POR4 Field Descriptions Field 31–30 29 PV Reserved. PCMCIA Valid. Defines whether the contents of the PBR and POR pair are valid (window enable). See also Table 20-13. 0 This bank is invalid. 1 This bank is valid. PCMCIA Write Protect Input Enable. This bit is the write protect input signal enable bit, controlled by software. When this bit is cleared, the WP input to the PCMCIA module is ignored. To see the relationship between this bit, the WP bit, and the WP signal coming from the card refer to Section 20.5.7, “Write Protect.” 0 Write Protect input (WP) signal is ignored. 1 Write Protect (WP) input signal is enabled. PCMCIA Write Protect Enable This bit is the write protect enable bit controlled by software. To see the relationship between this bit, the WPEN bit, and the WP signal coming from the card refer to Section 20.5.7, “Write Protect.” 0 Not write protected. 1 Write Protected. Attempting to write to this window causes an interrupt. PCMCIA Region Select. 00 Common memory space. 01 TrueIDE mode. 10 Attribute memory space. 11 I/O space. PCMCIA Port Size. Specifies the port size of the PCMCIA window. Refer to Section 20.5.8, “16-Bit/8-Bit Support” for more details. 0 16-bit port size 1 8-bit port size Description 28 WPEN 27 WP 26–25 PRS 24 PPS MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-16 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-11. POR0–POR4 Field Descriptions (continued) Field 23–17 PSL Description PCMCIA Strobe Length. Determines the number of cycles the strobe is asserted during a PCMCIA access for this window and, thus, it is the main parameter for determining cycle length. The cycle may be lengthened by asserting WAIT. Note: To sample the WAIT signal it must be synchronized by two FF. This means that if the system must rely on the WAIT signal, the PSL should be calculated as the maximum valid time on WAIT plus two. For example, suppose we have a 100 MHz clock (one period is therefore 10 ns) and the card specification says that the time from WE/OE low to WAIT valid is 70 ns. The PSL value should be at least: (70 ns/10 ns)+2=9. 0000000 Strobe asserted 128 clocks cycles. 0000001 Strobe asserted 1 clocks cycles. 0000010 Strobe asserted 2 clocks cycles. ... 1111111 Strobe asserted 127 clocks cycles. PCMCIA Strobe Set Up Time (address to strobe assertion). Specifies when IOWR or WE is asserted during a PCMCIA write access or when IORD or OE are asserted during a PCMCIA read access handled by the PCMCIA controller. This helps meet address/setup time requirements for slow memories and peripherals. 000000 Reserved. 000001 Address to strobe assertion 1 clock. 000010 Address to strobe assertion 2 clock. ... 111111 Address to strobe assertion 63 clock. Note: Using PSST=000001 is not allowed when WPEN bit is set since the synchronization of WP signal takes 2 clocks. 10–5 PSHT PCMCIA Strobe Hold Time (strobe negation to address negation).Specifies when IOWR or WE are negated during a PCMCIA write or when IORD or OE are negated during a PCMCIA read. Used to meet address/data hold time requirements for slow memories and peripherals. 000000 Strobe negation to address change 0 clock. 000001 Strobe negation to address change 1 clock. ... 111111 Strobe negation to address change 63 clock. PCMCIA Bank Size. Determines the address mask field of each POR and provides masking for any of the corresponding bits in the associated PBR. The bank size corresponds to values of this bit field as indicated in Table 20-12. BSIZE determines not only the bank size, but also how the address is compared with PBR[PBA]. If BSIZE is a virtual field, the MASK is defined as shown in Table 20-13. Addr, AND MASK PBA, AND MASK for a valid PCMCIA access; otherwise, it is not a valid PCMCIA access. 16–11 PSST 4–0 BSIZE Table 20-12. BSIZE Values Value 00000 00001 00011 00010 00110 00111 Meaning 1 byte 2 byte 4 byte 8 byte 16 byte 32 byte Value 01111 01110 01010 01011 01001 01000 Meaning 1 Kbyte 2 Kbyte 4Kbyte 8 Kbyte 16 Kbyte 32 Kbyte Value 11110 11111 11101 11100 10100 10101 Meaning 1 Mbyte 2 Mbyte 4 Mbyte 8 Mbyte 16 Mbyte 32 Mbyte MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-17 Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-12. BSIZE Values (continued) Value 00101 00100 01100 01101 Meaning 64 byte 128 byte 256 byte 512 byte Value 11000 11001 11011 11010 Meaning 64 Kbyte 128 Kbyte 256 Kbyte 512 Kbyte Value 10111 Meaning 64 Mbyte NOTE BSIZE determines not only the bank size, but also how the address is compared with PBR[PBA]. According to the virtual field, MASK as defined as shown on Table 20-13. Table 20-13. BSIZE Mask BSIZE 00000 00001 00011 00010 00110 00111 00101 00100 01100 01101 01111 01110 01010 01011 01001 01000 11000 11001 11011 11010 11110 11111 MASK 11111111111111111111111111111111 11111111111111111111111111111110 11111111111111111111111111111100 11111111111111111111111111111000 11111111111111111111111111110000 11111111111111111111111111100000 11111111111111111111111111000000 11111111111111111111111110000000 11111111111111111111111100000000 11111111111111111111111000000000 11111111111111111111110000000000 11111111111111111111100000000000 11111111111111111111000000000000 11111111111111111110000000000000 11111111111111111100000000000000 11111111111111111000000000000000 11111111111111110000000000000000 11111111111111100000000000000000 11111111111111000000000000000000 11111111111110000000000000000000 11111111111100000000000000000000 11111111111000000000000000000000 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-18 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-13. BSIZE Mask (continued) BSIZE 11101 11100 10100 10101 10111 MASK 11111111110000000000000000000000 11111111100000000000000000000000 11111111000000000000000000000000 11111110000000000000000000000000 11111100000000000000000000000000 20.4.1.6 PCMCIA Offset Registers 0–4 (POFR0–POFR4) The offset address of the window. PBA is used in conjunction with POR[BSIZE]. The external address is ext_addr= POFA + haddr and MASK. When accessing this register 1-wait state is added by the PCMCIA/CF controller. The field definition of the POFRx registers is shown in Figure 20-8. Table 20-14 shows the field descriptions. 0xD800_4044 (POFR0) 0xD800_4048 (POFR1) 0xD800_404C (POFR2) 0xD800_4050 (POFR3) 0xD800_4054 (POFR4) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 POFA[25:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R POFA[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-8. PCMCIA Offset Registers 0–4 (POFR0–POFR4) Table 20-14. POFR0–POFR4 Field Descriptions Field 31–26 25–0 POFA Reserved. PCMCIA Offset Address. The offset address of the window. POFA is used in conjunction with POR[BSIZE]. The external address is ext_addr= POFA + haddr and MASK. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-19 Personal Computer Memory Card International Association (PCMCIA) Controller Example 20-1. Calculating Offset Address If: haddr[25:0] = 0x0000263, MASK = 0x3FFFFC0 POFA = 0x0000161 then: ext_addr = 0x0000161 + 0x0000263 & (0x3FFFFC0) = 0x0000161 + 0x0000023 = 0x0000184 20.4.1.7 PCMCIA General Control Register (PGCR) This is the general control register for the PCMCIA controller. When accessing this register, 1-wait state is added by the PCMCIA controller. Field definitions of the POFRx registers are shown in Figure 20-9. Table 20-15 shows the field descriptions. 0xD800_4060 (PGCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User Read/Write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 LPMEN SPKR POE RESET EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 20-9. PCMCIA General Control Register (PGCR) Table 20-15. PGCR Field Descriptions Field 31–4 3 LPMEN Reserved. Low Power Mode Enable. This bit puts the module into low power mode. In this case external memory accesses are disabled. The reset value is “1” (Low power mode). 0 Normal power mode. 1 Low power mode. Description 2 SPKROUT Routing Enable. This bit enables the routing of SPKRIN to SPKROUT. SPKREN 0 Routing disabled. 1 Routing enabled. 1 POE Card Output Enable. This bit enables the POE signal, used to three-state the external buffers. The POE signal will toggle as follows: POE (signal) PGCR[POE]&PCMCIA_ACCESS (signal). 0 POE signal is disabled. 1 POE signal is enabled. Card Reset. This bit provides a software reset to the card. This bit is not self clearing, software must modify this bit to take the card out of reset. 0 Card is not in reset. 1 Card is in reset. 0 RESET MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-20 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller 20.4.1.8 PCMCIA General Status Register (PGSR) This is a general status register. If an error interrupt was generated to the host, the host can access this register to find out what caused the error interrupt. All the bits in this register are cleared by writing ‘1’ to the appropriate bit. When accessing this register, 1-wait state is added by the PCMCIA controller. Field definition of the POFRx registers are shown in Figure 20-10. Table 20-16 shows the field descriptions. 0xD800_4064 (PGSR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 NWIN LPE E 0 0 SE 0 CDE 0 WPE 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20-10. PCMCIA General Status Register (PGSR) Table 20-16. PGSR Field Descriptions Field 31–5 4 NWINE Reserved. No Window Error. Attempt to access a card address to an address that is not mapped by any window. 0 No attempt to access a card address to an address that is not mapped by any window since the last system reset was made. 1 An attempt to access a card address to an address that is not mapped by any window since the last system reset was made. Low Power Error. Attempt to access a card when in low power mode. 0 No attempt to access a card when in low power mode was made since the last system reset 1 An attempt to access a card when in low power mode was made since the last system reset Size Error. A 16-bit access to an 8-bit card was made. 0 No 16-bit access to an 8-bit card was made since the last system reset. 1 A 16-bit access to an 8-bit card was made since the last system reset Card Detect Error. Attempt to access a card when the card is not inserted. 0 No attempt to access a card when the card was not inserted has been made since last system reset. 1 An attempt to access a card when the card was not inserted has been made since last system reset. In addition, once set no accesses are enabled until it is cleared (even if a card was inserted). Write Protect Error. Attempt to write to a write protected address. 0 No attempt was made to write to a protected address since the last system reset. 1 An attempt was made to write to a protected address since the last system reset. Description 3 LPE 2 SE 1 CDE 0 WPE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-21 Personal Computer Memory Card International Association (PCMCIA) Controller 20.5 Functional Description This section describes the operation of memory and I/O cards, interrupt detection and handling, power control, and reset. 20.5.1 Modes of Operation The following are the PCMCIA modes of operation: • Memory-only card mode • I/O card mode • TrueIDE mode • Low power mode 20.5.2 Windowing Capabilities The PCMCIA I/F provides five memory windows. The user can define each memory window as a common memory space, I/O space or attribute memory space. This is done by programming the region select bits (PRS) bits in each POR register for each window. Configuring a window is done by programming the window’s base address (PBA bits in the corresponding PBR register), and by programming the bank size (BSIZE bits in the corresponding POR register). 20.5.2.1 Window Overlapping Window overlapping is not allowed. The PCMCIA I/F does not indicate to the CPU about window overlapping, software responsible for this. Having overlapping windows will cause unexpected results. 20.5.3 WAIT Signal The WAIT signal is asserted by the PC card to delay completion of the pending cycle. The access must terminate before the bus time out monitor generates a bus time error. 20.5.4 Interrupts There are 14 interrupt sources in the PCMCIA controller. The PCMCIA controller generates an interrupt signal for each interrupt source. In addition, the PCMCIA generates a signal which is a locator of all the possible interrupts. It is up to the system’s integrator to decide which signal(s) to connect to the system’s interrupt controller module. The PCMCIA’s interrupt sources are described in Table 20-17. Table 20-17. PCMCIA I/F Interrupt Sources Interrupt VS1 VS2 WP Enabled With PER.VSE1 PER.VSE2 PER.WPE See ipi_int_wp on page 20-5. Comments See ipi_int_vs1 on page 20-5. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-22 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-17. PCMCIA I/F Interrupt Sources (continued) Interrupt CD1 CD2 BVD1 BVD2 POWERON STATUS CHANGE RDY_L RDY_H RDY_R RDY_F IREQ ERR PER.ERRINTEN PER.RDYLE PER.RDYHE PER.RDRE PER.RDYFE This interrupt is an “OR” of RDY_L, RDY_H, RDY_R, and RDY_F. Enabled With PER.CDE1 PER.CDE2 PER.BVDE1 PER.BVDE2 PGCR.POWERONEN Comments See ipi_int_cd1 on page 20-5. See ipi_int_cd2 on page 20-5. See ipi_int_bvd1 on page 20-5. See ipi_int_bvd2 on page 20-5. This signal is not part of the PCMCIA standard. See ipi_int_poweron on page 20-5. “OR” of all the above interrupts. See ipi_int_sts on page 20-5. The PCMCIA input pins register (PIPR) reports any change of inputs from the PCMCIA card to the host (BVD,CD,RDY,VS). The content of the PCMCIA controller status changed register (PSCR) are logically ANDed with the PCMCIA controller enable register (PER) to generate a PCMCIA controller interrupt. The interrupt level is user programmable and the PCMCIA controller can generate an additional interrupt for RDY/IREQ that can trigger upon a level (low or high) change or edge (fall or rise) of the input signal. 20.5.4.1 Error Interrupt Conditions Any of the following error conditions can cause an error interrupt: • Attempt to access a card when the card is in low power mode (LPM). • Attempt to write to a write protected area, see Section 20.5.7, “Write Protect.” • Attempt to access a card when the card is not inserted. • Attempt to do a 16-bit access to an 8-bit card violating the PPS settings or 32-bit access. See Section 20.5.8, “16-Bit/8-Bit Support.” • Attempt to access card with an address which does not match any window. An access to the card which yields an error will take 0-3 wait states to complete according to the following conditions: • Card detect error when PGSR[CDE] is cleared and write protect error which results from the WP signal from the card will take 2 wait states. In case these signals (WP CD) change during access, the access will end two cycles after. • Size error, no window error low power mode and write protect error which comes from POR[WP] will take one wait state. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-23 Personal Computer Memory Card International Association (PCMCIA) Controller Due to the synchronization mechanism on CD signals and WP signal, a change in these signals during access less then two cycles before it finishes would not yield an error. That should not be a problem since these signals typically do not change too much. 20.5.5 Power Control When LPMEN is set in the PGCR, the PCMCIA I/F internal clocks should be gated off. The module is in “listening mode.” It waits for an indication that a card has been inserted. All the static signals are synchronous in both cases and status change interrupts are generated as necessary (to wake up the core from stop on card detect, for example). In the first case (LPMEN) read from PIPR and read/write from/to PSCR should take 2 wait states to complete because of the synchronizations of the static signals to the core’s clock. 20.5.6 Reset and Three-Score Control The card can be reset by software. This is done by writing to the RESET bit in the PGCR register. Output of external latches can be disabled by writing to the POE bit in PGCR register. 20.5.7 Write Protect Write protect is handled in two ways: • Card’s write protect—the WP signal comes from the card. • Window’s write protect—the WP bit in the POR register. When the WPEN is cleared and the card is in memory interface mode, the WP signal coming from the card is ignored. This way it is possible to enable write protection on selected memory regions, even if the card’s WP pin is asserted. The settings for the Write Protect bits are shown in Table 20-18. When the card is in IO mode (POR.PRS = 11),WPEN bit is ignored. Table 20-18. Write Protect POR.PRS X0 (memory I/F) POR.WP bit X WP Signal 0 1 0 1 11(I/O mode) 0 1 X X X POR.WPEN 1 1 0 0 X Protect Mode Write enabled Write protected Write enabled Write protected Write enabled Write protected An interrupt is generated by the PCMCIA controller at any attempt to access a write protected area. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-24 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller 20.5.8 16-Bit/8-Bit Support The PCMCIA controller supports 16-bit/8-bit accesses. The access size is defined by the IOIS16 signal and the PPS bit in the corresponding POR register. The settings for the IOIS16 and PPS bits are shown in Table 20-19. Table 20-19. IOIS16 and PPS Bit Relations IOIS16 0 0 PPS 0 1 Access Size 16-bit access to a 16-bit card, the host can generate 8-bit accesses and 16-bit access. 8-bit access although the card is 16-bit. The host should generate 8-bit accesses only. If the host tries to do a 16-bit access, an interrupt is generated 8-bit access although 16-bit access is selected by PPS. If the host attempts to do a 16-bit access, the PCMCIA I/F writes the lower part of the data to the card. 8-bit access to 8-bit card. The host should generate 8-bit accesses only. If the host tries to do a 16-bit access, an interrupt is generated. 1 0 1 1 20.5.9 Data and Control Signals Relations Table 20-20 describes data and control signal relations in different access modes. Data bus (D) is the data bus of the PC-card. Table 20-20. Data and Control Signal Relations Function Mode Standby mode 8-bit read from common memory 16-bit read from common memory 8-bit write to common memory 16-bit write to common memory 8-bit read from attribute memory 16-bit read from attribute memory 8-bit write to attribute memory REG x 1 1 1 1 1 1 1 1 0 0 0 0 0 0 CE2 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 CE1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 A0 x 0 1 x x 0 1 x x 0 1 x x 0 x OE x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 WE x 1 1 1 1 0 0 0 0 1 1 1 1 0 0 IORD x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IOWR x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D[15:8] High-z High-z High-z Odd-Byte1 Odd-Byte xxx xxx Odd-Byte1 Odd-Byte High-z High-z Not-valid Not-valid xxx xxx D[7:0] High-z Even-Byte Odd-Byte High-z1 Even-Byte Even-Byte Odd-Byte xxx1 Even-Byte Even-Byte Not-valid Even-Byte Even-Byte Even-Byte Even-Byte MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-25 Personal Computer Memory Card International Association (PCMCIA) Controller Table 20-20. Data and Control Signal Relations (continued) Function Mode 8-bit read from I/O REG 0 0 0 0 0 0 0 0 1 CE2 1 1 0 0 1 1 0 0 x CE1 0 0 1 0 0 0 1 0 x A0 0 1 x x 0 1 x x x OE 1 1 1 1 1 1 1 1 x WE 1 1 1 1 1 1 1 1 x IORD 0 0 0 0 1 1 1 1 0 IOWR 1 1 1 1 0 0 0 0 1 D[15:8] High-z High-z Odd-Byte1 Odd-Byte xxx xxx Odd-Byte Odd-Byte High-z D[7:0] Even-Byte Odd-Byte High-z1 Even-Byte Even-Byte Odd-Byte xxx Even-Byte High-z 16-bit read from I/O 8-bit write to I/O 16-bit write to I/O I/O inhibit 1 Note these are all the access modes which are supported by the standard. In the PCMCIA controller, the 8-bit access to odd byte is done by CE1 and A0 only, that is, the data will be always driven on D[7:0]. 20.5.10 True IDE Mode Access In True IDE mode windows, the selection of either task file or alt reg is made by haddr[3] Haddr[3] = 0—will yield an access to task file or data register Haddr[3] = 1—will yield a write to control register or read of Alt. status register Table 20-21 shows data, control and address relations in TrueIDE mode. Table 20-21. Data, Control and Address Relations in TrueIDE Mode Function mode Standby mode Task file Write Task file Read Data Register Write Data Register Read Control Register Write Alt Status Read Invalid Mode CE2 1 1 1 1 1 0 0 0 CE1 1 0 0 0 0 1 1 0 A0-3 xx 1-7h 1-7h 0 0 6h 6h x IORD x 1 0 1 0 1 0 x IOWR x 0 1 0 1 0 1 x D[15:8] High-z xxx High-z Odd-Byte Odd-Byte xxx High-z High-z D[7:0] High-z Data In Data Out Even-Byte Even-Byte Data In Data out High-z 20.5.11 Card Extraction When the card is extracted the PCMCIA controller’s registers are not reset. The registers settings remain the same as before the card’s extraction. This allows the host software to quickly activate the card once the CIS indicates that it is the same card. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-26 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller 20.5.12 TrueIDE Support The ATA standard specifies the AT attachment interface between host systems and storage devices. The PCMCIA controller can be dynamically configured to support a PCMCIA-compatible ATA disk interface (commonly known as IDE) instead of the standard PCMCIA card interface. Using the TrueIDE interface on the PCMCIA controller changes the function of some card socket signals to support the needs of the ATA disk interface. The TrueIDE signals assignment on the PCMCIA connector is described in Table 20-22. Table 20-22. PCMCIA Card TrueIDE Signal Names and Assignments PC Card Signal D[15:0] CE1 CE2 OE TrueIDE D[15:0] CS01 CS11 ATASEL 2 Comment Task file register select in TrueIDE mode. Alternate status register select in TrueIDE mode. The CF card samples this bit on power-on sequence. If low, the card will enter TrueIDE mode, else it will enter PC CARD mode. Address These bits should be connected to ‘0’ on TrueIDE A[2:0] A[10:3] WE READY/IREQ WP/IOIS16 CD1 CD2 VS1 VS2 RESET WAIT REG BVD1/STSCHG BVD2/SPKR IORD IOWR 1 A[2:0] not used WE INTRQ IOCS16 CD1 CD2 VS1 VS2 RESET IOCHRDY not used PDIAG DASP IORD IOWR Interrupt request—INTRQ is the ATA notation and is asserted HIGH. This signal is asserted LOW in ATA mode, HIGH in other modes. IO Channel Ready—asserted HIGH—polarity inversion of WAIT. this bit should be connected to ‘1’ on TrueIDE Diagnostics complete signal. Disk Active In TrueIDE mode, #CS0 and #CS1 (task file chip select) behave differently from #CE1 and #CE2 (byte lane chip selects) 2 Dynamic change of ATASEL is not supported since it requires power up of the card. Therefore the ATASEL pin of the card will grounded in the socket. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-27 Personal Computer Memory Card International Association (PCMCIA) Controller 20.5.13 Endianness Support The PCMCIA controller supports Big and Little Endian. The Endianness is defined according to the Endianness input pin to the module. This input should be tied high or low by the chip integrator. Connecting the input to “1” means Big Endian.Connecting the input to “0” means Little Endian. Dynamic Endianness is not supported. 20.6 Timing Diagrams Figure 20-11 and Figure 20-12 show PCMCIA typical accesses. HCLK HADDR CONTROL HWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 R/W REG OKAY ADDR 1 DATA write 1 OKAY OKAY ADDR 1 CONTROL 1 DATA write 1 POE pulse width setup hold Figure 20-11. Write Accesses PSHT=1, PSST =1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-28 Freescale Semiconductor Personal Computer Memory Card International Association (PCMCIA) Controller HCLK HADDR CONTROL RWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG WE/IORD/IOWR CE1/CE2 REG OKAY ADDR 1 OKAY OKAY ADDR 1 CONTROL 1 DATA read 1 R/W POE pulse width setup hold Figure 20-12. Read Cycle PSHT=1, PSST =1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 20-29 Personal Computer Memory Card International Association (PCMCIA) Controller MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 20-30 Freescale Semiconductor Book II, Part 4: Connectivity Peripherals Introduction The i.MX27 processor contains the following modules that provide communication with a variety of different peripheral using several different interfaces: Chapter 21, “1-Wire Interface (1-Wire),” on page 21-1 Chapter 22, “Advanced Technology Attachment (ATA),” on page 22-1 Chapter 23, “Configurable Serial Peripheral Interface (CSPI),” on page 23-1 Chapter 24, “Inter-Integrated Circuit (I2C),” on page 24-1 Chapter 25, “Keypad Port (KPP),” on page 25-1 Chapter 26, “Memory Stick Host Controller (MSHC),” on page 26-1 Chapter 27, “Secured Digital Host Controller (SDHC),” on page 27-1 Chapter 28, “Universal Asynchronous Receiver/Transmitters (UART),” on page 28-1 Chapter 29, “Fast Ethernet Controller (FEC),” on page 29-1 Chapter 30, “High-Speed USB On-The-Go (HS USB-OTG),” on page 30-1 1-Wire Module The 1-Wire module provides bidirectional communication between the ARM9 core and the Add-Only-Memory EPROM (DS2502). The 1-kilobit EPROM is used to hold battery information and communicate with the ARM9 Platform using the IP interface. The ARM9 (through the 1-Wire interface) acts as the bus master and the DS2502 device is the slave. The 1-Wire peripheral does not trigger interrupts; hence, it is necessary for the ARM9 to poll of the 1-Wire to manage the module. The 1-Wire uses an external pin (to connect to the DS2502). Timing requirements are met in hardware with the help of a 1-MHz clock. The clock divider generates a 1-MHz clock that is used as time reference by the state machine. Timing requirements are crucial for proper operation, and the 1-Wire state machine and the internal clock provide the necessary signal. Advanced Technology Attachment (ATA) The Advanced Technology Attachment (ATA) module provides an AT attachment host interface for the i.MX27. Its main use is to provide an interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA device using industry standard ATA signals. The ATA interface is compliant to the ATA-6 standard, and supports following ATA standard protocols: • PIO mode 0, 1, 2, 3, and 4 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 • • • Multiword DMA mode 0, 1, and 2 Ultra DMA modes 0, 1, 2, 3, and 4 with a bus clock of 50 MHz or higher Ultra DMA modes 5 with bus clock of 80 MHz or higher The ATA interface has 2 buses connected to it. The CPU bus provides communication with the ARM9 host processor and the DMA bus provides communication between the ATA module and the host DMA unit. All internal ATA registers are visible from both buses, allowing Smart Direct Memory Access (SDMA) access to program the interface. There are basically 2 protocols that can be active at the same time on the ATA bus. The first and simplest protocol (PIO mode access) can be started at any time by either the ARM9 or the host SDMA to the ATA bus. The PIO mode is a slow protocol, mainly intended to be used to program an ATA disc drive, but also possible to use to transfer data to/from the disc drive. The second protocol is the DMA mode access. DMA mode is started by the ATA interface after receiving a DMA request from the drive, and only if the ATA interface has been programmed to accept the DMA request. In DMA mode, either multiword DMA or ultra DMA protocol is used on the ATA bus. All transfers between FIFO and host IP or DMA IP bus are zero wait states transfer, so high speed transfer between FIFO and DMA/host bus is possible. Configurable Serial Peripheral Interface (CSPI) There are three identical CSPI modules in the i.MX27 IC. Each CSPI is equipped with data FIFOs, and is a master/slave configurable serial peripheral interface module, capable of interfacing to both SPI master and slave devices. The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data communication with fewer software interrupts. The CSPI is used for fast data communication with fewer software interrupts. It includes the following features: • Full-duplex synchronous serial interface • Master/Slave configurable • Four chip selects to support multiple peripherals • Transfer continuation function allows unlimited length data transfers • 32-bit wide by 8-entry FIFO for both transmit and receive data • Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable • DMA support Inter-Integrated Circuit Bus (I2C) The Inter-Integrated Circuit Bus (I2C) module provides a serial interface for controlling the Sensor Interface and other external devices. Data rates of up to 100 kbps are supported. The I2C module provides functionality of a standard I2C slave and master. The I2C module is designed to be compatible with the standard Phillips I2C bus protocol. The I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor between many devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development. Keypad Port (KPP) The Keypad Port (KPP) is designed to interface with keypad matrix with 2-contact or 3-point contact keys. The KPP is designed to simplify the software task of scanning a keypad matrix. With appropriate software support, the KPP is capable of detecting, debouncing, and decoding one or multiple keys pressed simultaneously in the keypad. The KPP supports up to 8 x 8 external key pad matrices. Its port pins can be used as general purpose I/O. Using an open drain design, the KPP includes glitch suppression circuit design, multiple keys, long key, and standby key detection. Secure Digital Host Controller (SDHC) The Security Digital Host Controller (SDHC) integrates both MultiMediaCard (MMC) support along with Secure Digital (SD) memory and I/O functions, including SD memory and I/O combo card. The Multi Media Card (MMC), is a universal low cost data storage and communication media that is designed to cover a wide area of applications as, among others, electronic toys, organizers, PDAs, and smart phones. The Secure Digital Card (SD), is an evolution of MMC technology, with two additional pins in the form factor. It is specifically designed to meet the security, capacity, performance, and environment requirement inherent in newly emerging audio and video consumer electronic devices. Universal Asynchronous Receiver Transmitter (UART) The Universal Asynchronous Receiver Transmitter (UART) provides serial communication capability with external devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception), or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. The i.MX27 contains six UART modules. Each UART module is capable of standard RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART transmits and receives characters containing either 7 or 8 bits (program selectable). To transmit, data is written from the IP data bus (SkyBlue line interface) to a 32-byte transmitter FIFO (TxFIFO). This data is passed to the shift register and shifted serially out on the transmitter pin (TXD). To receive, data is received serially from the receiver pin (RXD) and stored in a 32-halfwords-deep receiver FIFO (RxFIFO). The received data is retrieved from the RxFIFO on the IP data bus. The RxFIFO and TxFIFO generate maskable interrupts as well as DMA Requests when the data level in each of the FIFO reaches a programmed threshold level. Universal Serial Bus, On-The-Go (USBOTG), High-Speed The i.MX27 uses a Universal Serial Bus, On-The-Go (USBOTG) module that provides all of the functionality required to support three independent USB ports, compatible with the USB 2.0 specification. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 3 In addition to the normal USB functionality, the module also provides support for direct connections to on-board USB peripherals and supports multiple interface types for serial transceivers. The USB module provides high performance USB On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement, and the ULPI 1.0 Low Pin Count specification. Fast Ethernet Controller (FEC) The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface, using a subset of the MII pins. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 4 Freescale Semiconductor Chapter 21 1-Wire Interface (1-Wire) The 1-Wire® module is a peripheral device that communicates with the ARM926EJ-S Core via the IP interface and provides a communication line to a 1 Kbit Add-Only Memory (DS2502). The DS2502 is a 1 kbit 1-Wire EPROM. The 1-Wire interface is able to send or receive one bit at a time to the DS2502. The required protocol for accessing the DS2502 is defined by Maxim-Dallas Semiconductor. Figure 21-1 shows the 1-Wire Connection overview. A block-level description of the 1-Wire module is contained in Figure 21-2. ARM926T R-AHB AIPI O-Wire Interface Module DS2502 i.MX27 Figure 21-1. 1-Wire Connection 21.1 Overview This chapter describes the 1-Wire function, timing diagrams, port definitions as well as notes on testing the 1-Wire module. The DS2502 is used to hold battery characteristic information. The clock divider generates a 1 MHz clock used as a time reference by the state machine. Transitions between the states of the state machine as well as actions triggered at precise time deadlines are expressed using this 1-MHz clock. The state machine performs all required actions to dialog with the external device. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 21-1 1-Wire Interface (1-Wire) AIPI peripheral registers From PAD Clock Divider 1 MHz clock State Machine To PAD Figure 21-2. 1-Wire Block-Level Description 21.2 Port Definitions The inputs and outputs for the 1-Wire are listed in Table 21-1. They are organized in such a way to show the major interfaces for the 1-Wire. The DS2502 input and output lines listed in Table 21-1 are the lines that interface with the DS2502. Table 21-1 lists the inputs and outputs relevant for the AIPI bus protocol. In Table 21-1, the clocks are described. In Table 21-1, the test signals are described. Table 21-1. 1-Wire Port Definitions: DS2502 Signal BATTERY_LINE_IN BATTERY_LINE_OUT OUTPUT_ENABLE input output output I/O 1-Wire bus. Connected to GND for open drain Enable for output driver 1-Wire bus. In hdl model, represents DS2502 input Comments Note: The outputs above have been set for a standard I/O pad. The DS2502 specifies an external 5K pull-up should be used. The i.MX27 provides a 69K pull-up resistor on the 1-Wire pin. An external pull-up is not required if the 1-Wire module is connected within few inches to the DS2502. 21.3 Pin Configuration Table 21-2 identifies the pin used for the 1-Wire module. This pin is multiplexed with other functions on the device and must be configured for 1-Wire operation. Table 21-2. 1-Wire Pin Configuration Module GPIO Setting Alternate Function of GPIO Port E [16] Configuration Procedure 1. Clear bit 16 of Port E GPIO In Use Register (GIUS_E) 2. Set bit 16 of Port E General Purpose Register (GPR_E) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 21-2 Freescale Semiconductor 1-Wire Interface (1-Wire) 21.4 Clock Enable and AIPI Configuration Table 21-3. CRM and API Register Descriptions Module Setting CRM_PCCR0 AIPI1_PSR0 and AIPI1_PSR1 Configuration Procedure Set bit [12] to enable the clock to 1-Wire Set AIPI1_PSR0 bit [9] and Clear AIPI1_PSR1 bit [9] to match 1-Wire bus width 16 bits. PLL Clock Controller and Reset Module AIPI 21.5 Functional Description The 1-Wire interfaces with the 1Kbit Add-only Memory (DS2502) through a simple 1 bit bus. The DS2502 1 Kbit Add-only Memory, manufactured by Maxim-Dallas Semiconductor, uses the 1-Wire line to program and read a 1024-bit EPROM. The DS2502 also has a 64-bit lasered ROM and status bytes. The DS2502 requires a special protocol to access the EPROM. The protocol involves first issuing one of four ROM function commands before the EPROM is accessible: read ROM, match ROM, search ROM and skip ROM. Through the 1-Wire bus, the ARM926EJ-S Core interfaces with the DS2502 and allows the required commands to be issued to control the EPROM. The ARM926EJ-S (through the 1-Wire interface) is the bus master and the DS2502 device(s) are the slave(s). The 1-Wire peripheral does not trigger interrupts; hence a polling of the 1-Wire module register is necessary to manage a correct operation of the block. 21.5.1 Low-Power Modes When the 1-Wire module enters a low power mode it gates off its clock when it is not in use—that is, when the RPP, WR0, and WR1 bits in the Control register are all cleared. 21.5.2 Reset Sequence with Reset Pulse Presence Pulse To begin any communications with the DS2502, it is required that an initialization procedure be issued. A reset pulse must be generated and then a presence pulse must be detected. The minimum reset pulse length is 480 us. The bus master (1-Wire) will generate this pulse, then after the DS2502 detects a rising edge on the 1-Wire bus, it will wait 15-60 µs before it will transmit back a presence pulse. The presence pulse will exist for 60–240 µs. The timing diagram for this sequence is shown in Figure 21-3. Reset and Presence Pulses Set RPP 511 us DS2502 waits 15-60us DS2502 Tx “presence pulse” 60-240us AutoClear RPP Control Bit 1-Wire bus 512us 68us 1-Wire simples (set PST) Figure 21-3. 1-Wire Initialization MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 21-3 1-Wire Interface (1-Wire) The reset pulse begins the initialization sequence and it is initiated when the RPP control register bit is set. When the presence pulse is detected, this bit will be cleared. The presence pulse is used by the bus master to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists. The 1-Wire module will sample for the DS2502 presence pulse. The presence pulse is latched in the 1-Wire control register PST. When the PST bit is set to a one, it means that a DS2502 is present; if the bit is set to a zero, then no device was found. 21.5.3 Write 0 The Write 0 function simply writes a zero bit to the DS2502. The sequence takes 117 µs. The 1-Wire bus is held low for 100 µs. Figure 21-4 shows the Write 0 timing. Set WR0 AutoClear WR0 Write “0” Slot 128us 17us 100us 1-Wire Bus Figure 21-4. Write 0 Timing The Write 0 pulse sequence is initiated when the WR0 control bit register is set. When the write is complete, the WR0 register will be auto cleared. 21.5.4 Write 1 and Read Data The Write 1 and Read timing is identical. The time slot is first driven low. According to the DS2502 documentation, the DS2502 has a delay circuit which is used to synchronize the DS2502 with the bus master (1-Wire). This delay circuit is triggered by the falling edge of the data line and is used to decide when the DS2502 will sample the line. In the case of a write 1 or read 1, after a delay, a 1 will be transmitted/received. When a read 0 slot is issued, the delay circuit will hold the data line low to override the 1 generated by the bus master (1-Wire). For the Write 1 or Read, the control register WR1/RD is set and auto-cleared when the sequence has been completed. After a Read, the control register RDST bit is set to the value of the read. Figure 21-5 shows the Write 1 timing. Set WR1/RD Auto Clear WR1/RD Write “1” Slot 117us 5us Figure 21-5. Write 1 Timing MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 21-4 Freescale Semiconductor 1-Wire Interface (1-Wire) Figure 21-6 shows the read timing. Set WR1/RD Read Timing Auto Clear WR1/RD Set WR1/RD Auto Clear WR1/R Read “0” Slot 117µs 60 µ s Read “1” Slot 117 µs 1-Wire Bus 5 µs 13 µs 5 µs 13 µs 1-Wire samples (set RDST) 1-Wire samples (set RDST) Figure 21-6. Read Timing 21.5.5 Program Pulse The Program Pulse sequence is described in the DS2502 documentation as one of the functions of the 1-Wire signaling. The 12-volt programming pulse function is not used in the 1-Wire. 21.6 Memory Map and Register Definition The 1-Wire module includes three user-accessible 16-bit registers. Table 21-6 summarizes these registers and their addresses. Table 21-4. 1-Wire Memory Map Address 0x1000_9000 (CONTROL) 0x1000_9002 (TIME_DIVIDER) 0x1000_9004 (RESET) Register Control register Time divider register Reset register Reset Value 0x0000 0x0000 0x0000 Access R/W R/W R/W Section/Page 21.6.1.1/21-6 21.6.2/21-7 21.6.3/21-9 21.6.1 Register Summary Figure 21-7 shows the key to the register fields, and Table 21-5 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 21-7. Key to Register Fields Table 21-5. Register Figure Conventions Key to Register Fields Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 21-5 1-Wire Interface (1-Wire) Table 21-5. Register Figure Conventions Key to Register Fields (continued) Convention Description Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 21-6 shows the 1-Wire register summary. Table 21-6. 1-Wire Register Summary Name 0x1000_9000 (CONTROL) R W R 0x1000_9002 (TIME_DIVIDER) W 0x1000_9004 (RESET) R W 0 0 0 0 0 0 0 0 DVDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES ET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 RPP PST WR 0 WR 1 RDS T 0 0 0 21.6.1.1 Control Register (CONTROL) The control register updates the status of the reset, presence, write0, write1, and read bits. when read, this register lets the user know whether the device (1-Wire) is connected. Figure 21-8 shows the CONTROL register, and Table 21-7 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 21-6 Freescale Semiconductor 1-Wire Interface (1-Wire) 0x1000_9000 (CONTROL) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 RPP PST WR0 0 0 WR1 0 RDST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-8. Control Register Table 21-7. Control Register Field Descriptions Field 15–8 7 RPP 6 PST 5 WR0 4 WR1 Reserved Reset presence pulse. This bit is self-clearing and is cleared after the presence is determined. 0 Does nothing. Reset pulse is complete. 1 Generates a reset pulse and a sample for DS2502 presence pulse. Presence status. This bit is valid after the RPP bit is self-cleared. 0 Device is not present. 1 Device is present. Write 0. This bit is self-clearing and is cleared when the write of the bit is complete. 0 Do nothing./ Write sequence complete. 1 Write a 0 bit to the interface. Write 1/ Read. This bit is self-clearing and is cleared when the write of the bit is complete. This reads a bit, since the Write 1 and Read timing are identical. The value of the read bit is stored in RDST, and is valid after WR1/RD is self-cleared. 0 Do nothing./Write sequence complete. 1 Write a 1 bit to the interface. Read status. This bit is valid after the WR1/RD bit is self cleared. 0 A 0 was sampled during a read. 1 A 1 was sampled during a read. Reserved Description 3 RDST 2–0 21.6.2 Time Divider Register (TIME_DIVIDER) 1-Wire Time Divider Register clock divider register used to generate the internal time base within the module. Internal time generation is made up by a clock divider. The purpose of this internal time generation is to make a 1 MHz clock from the main clock. Figure 21-9 shows the TIME_DIVIDER register, and Table 21-8 shows the register’s field descriptions. Table 21-9 shows the system timing requirements. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 21-7 1-Wire Interface (1-Wire) 0x1000_9002 (TIME_DIVIDER) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 DVDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-9. Time Divider Register Table 21-8. Time Divider Register Field Descriptions Field 15–8 7–0 DVDR Reserved Pre-divider factor. The 1-Wire also contains a clock divider register used to generate the internal time base within the module. Internal time generation is made up by a clock divider. The purpose of this internal time generation is to make a 1 MHz clock from the main clock. It is the user’s responsibility to program this register so that the binary rate frequency is as close as possible to 1 MHz (1 /(divider+1). If the clock frequency is 30 MHz, then the proper value to write to the divider register is 29. 00 1 (default) 01 2 ----FF 256 Description Note: It is the user’s responsibility to program this register so that the binary rate frequency is as close as possible to 1 MHz (1 MHz = clock / (divider + 1)). If the clock frequency is 30 MHz, then the proper value to write into the divider register is 29. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 21-8 Freescale Semiconductor 1-Wire Interface (1-Wire) NOTE The precision of the generated clock is very important to ensure the proper operation of the 1-Wire module. This module is based on a state machine which undertakes actions at defined times. Table 21-9. System Timing Requirements Times RSTL PST RSTH LOW0 LOWR READ_sample Values (µs) 511 68 512 100 5 13 Minimum (µs) 480 60 480 60 1 — Maximum (µs) — 75 — 120 15 15 Absolute Precision 31 7 32 20 4 2 Relative Precision 0.0645 0.1 0.0645 0.2 0.8 0.15 The most stringent constraint is 0.0645 as a relative time imprecision. The time relative precision is directly derived from the frequency of the derivative clock (f): time relative precision = 1/f –1 = divider/clock (MHz) –1 The Table 21-10 shows the relative time precision for different main clock frequencies. Table 21-10. System Clock Requirements Main Clock Frequency (MHz) Clock divide ratio Generated frequency (MHz) Relative time imprecision 13 13 1 0 16.8 17 0.9882 0.0117 19.44 19 1.023 0.023 This demonstrates that the user must use care when selecting the main clock frequency if using the 1-Wire module. If the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz. NOTE A main clock frequency below 10 MHz could cause stability problems and incorrect operation in the 1-Wire module. 21.6.3 Reset Register The Reset Register is used to reset the 1-Wire module through software. This register is not self-clearing, therefore the programmer must write a 1 to reset the register and then write a 0 to release the reset signal. Figure 21-10 shows the RESET register, and Table 21-11 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 21-9 1-Wire Interface (1-Wire) 0x1000_9004 (RESET) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-10. Reset Register Table 21-11. Reset Register Field Descriptions Field 15–1 0 RST Reserved Software reset. The reset register is used to reset the module using the software. This register is not self-clearing; therefore, the programmer must write a ‘1’ to reset the registers and then write a ‘0’ to release the reset signal. 0 1-Wire is out of reset. 1 1-Wire is in reset. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 21-10 Freescale Semiconductor Chapter 22 Advanced Technology Attachment (ATA) The ATA host controller complies with the ATA/ATAPI-6 specification. Its main use is to interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA device over a number of ATA signals.See Figure 22-1 for the block diagram of the ATA host controller. ATA Protocol Engine PIO Channel ata_reset_b ata_dior ata_diow ata_cs1 ata_cs0 ata_da2 ata_da1 ata_da0 Multiword DMA Channel FIFO 64x16 ata_fifo.v ata_reg.v Timing Parameters Control Register AHB Bus Bus Interface Drive Register Interrupt Interface ata_dmarq ata_dmack ata_intrq ata_iordy ata_data[15:0] ata_buffer_en ata_ahb.v FIFO control Ultra DMA Channel ata_controller.v Host side Device side ata_top.v Figure 22-1. ATA Host Controller Block Diagram. 22.1 Overview The ATA Host Controller consists of a bus interface compliant with AHB bus protocols, a control register for register setting, a 64x16 data FIFO and an ATA protocol engine. The ATA block is an AT attachment host interface. Its main use is to interface with hard disc drives and optical disc drives which compiles with ATA/ATAPI-6 standard. It interfaces with the ATA device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side. In this case, the ata_buffer_en signal should be used to control the direction the buffer is driving to. If ata_buffer_en is high, it drives outward to the device. If ata_buffer_en is low, it drives inward to the host. The ATA Host Controller supports interface protocols as specified in ATA/ATAPI-6 standard: • PIO mode 0, 1, 2, 3, and 4 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-1 Advanced Technology Attachment (ATA) • • • Multiword DMA mode 0, 1, and 2 Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher Ultra DMA mode 5 with bus clock of 80 MHz or higher Before accessing the ATA bus, the host must program the timing parameters to be used on the ATA bus. The timing parameters control the timing on the ATA bus. Most timing parameters are programmable as a number of clock cycles (1 to 255). Some are implied. All of the ATA device internal registers are visible to users, and they are defined as mirror registers in ATA host controller. As specified in ATA/ATAPI-6 standard, all the features/functions are implemented by reading/writing to the device internal registers. After programming the timing parameters, there are two protocols that can be active at the same time on the ATA bus: • First protocol. This protocol is a PIO mode access that can be performed at any time by the host to the ATA bus. During PIO mode access, the incoming AHB bus cycle is translated into an ATA bus cycle by the ATA protocol engine. The AHB bus cycle is stalled until completion of the ATA bus cycle on read, or until putting the write data on the ATA bus on write. The PIO mode is a slow protocol, mainly intended to program the ATA disc drive, but also possible to use to transfer data to/from the disc drive. During PIO mode, the FIFO is not active. • Second protocol. This protocol is the DMA mode access. DMA mode is started by the ATA interface after receiving a DMA request from the drive, and only if the ATA interface has been programmed to accept the DMA request. In DMA mode, either multiword DMA or ultra DMA protocol is used on the ATA bus. Once started, data transfer is organized between the ATA bus and the FIFO. Data transfer will pause to prevent FIFO overflow/FIFO underflow. Data transfer will resume when there is again space in the FIFO, or when the FIFO has been refilled. During DMA transfer, there is no direct data transfer between the ATA bus and the host CPU or host DMA bus. Instead, the transfer takes place between the ATA bus and the FIFO; the FIFO informs the host DMA unit when it needs to be refilled or emptied. In this case, it sends an FIFO ALARM flag to the host DMA. When the host DMA receives the fifo_tx_alarm, it should write some data to the FIFO. (typically 32 bytes). When the host DMA receives the fifo_rcv_alarm, it should read some data from the FIFO (typically 32 bytes). The FIFO filling level at which the alarms are produced, is programmable. For completion, there is a third alarm associated with the host DMA operation fifo_txfer_end_alarm. This alarm signals the end of the transfer, and requests the host DMA to take steps to complete the transfer: transfer the bytes remaining in the FIFO to the host memory, and inform the host CPU the transfer is completed. All transfers between FIFO and host CPU or DMA bus are zero wait states transfer, so high speed transfer between FIFO and host DMA bus is possible. When a PIO access is performed during a running DMA transfer, the DMA transfer will be paused, the PIO access done, and the DMA transfer will resume again. 22.2 Features The ATA host controller includes the following major features: Programmable timing on the ATA bus. Works with wide range of bus clock frequencies. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-2 Freescale Semiconductor Advanced Technology Attachment (ATA) • • • • • Compliant with ATA/ATAPI-6 standard — Supports PIO modes 0, 1, 2, 3, and 4 — Supports multiword DMA modes 0, 1, and 2 — Supports ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of at least 50 MHz — Supports ultra DMA mode 5 with bus clock of at least 80 MHz Can be used with off-chip bus transceiver if pads are not compliant with ATA voltage levels 64-halfword FIFO part of interface FIFO receive alarm, FIFO transmit alarm, and FIFO end of transmission alarm to host DMA unit Zero-wait cycles transfer between host DMA bus and FIFO allows fast FIFO reading/writing 22.3 Operation The interface offers two transfer modes that can be used together. 22.4 PIO Mode An access to the ATA bus in PIO mode occurs whenever a ATA PIO register is read or written by the host CPU or the host (smart) DMA unit. During a PIO transfer the incoming AHB bus cycle is translated into an ATA PIO bus cycle by the ATA protocol engine. No buffering of data occurs, so the host CPU or host DMA cycle is stalled until the ATA bus read data is available on read, or is stalled until the AHB bus data can we put on the ATA bus during write. PIO accesses can be done to the bus at any time, even during a running ATA DMA transfer. In this case, the DMA transfer is paused, the PIO cycle is completed, and the DMA transfer is resumed. 22.4.1 DMA Mode (Multi-Word DMA and Ultra DMA) In DMA mode, data is transferred between the ATA bus and the FIFO. Two different DMA protocols are supported on the ATA bus: ultra DMA mode and multi-word DMA mode. Selection is by using a control register bit. A DMA transfer will be started when DMA mode transfer has been enabled by writing some control bit, and when the drive connected to the ATA bus pulls its DMARQ line high. During an ATA bus DMA transfer, data is transferred between the ATA bus and the FIFO. The transfer will pause to avoid FIFO overflow and FIFO underflow. It is the task of the host CPU or the host smart DMA unit to read data or write data to the FIFO to keep the transfer going. Normal set-up is that the host (smart) DMA unit takes on this task. For this purpose, the fifo_rcv_alarm and fifo_tx_alarm signals are sent to the host DMA unit. fifo_rcv_alarm informs the host DMA unit that there is at least 1 packet of data waiting in the FIFO to be read by the host DMA. Whenever this signal is high, the host DMA should transfer one packet of data from the FIFO to the main memory. Typical packet size is 32 bytes (8 long words), but other packet sizes can be handled too. fifo_tx_alarm informs the host DMA unit that there is space for at least 1 packet to be written by the host DMA. Whenever this signal is high, the host DMA should transfer one packet of data from main memory to the FIFO. Typical packet size is 32 bytes (8 long words), but other packet sizes can be handled too. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-3 Advanced Technology Attachment (ATA) 22.5 External Signal Description See Table 22-1 for the list of signals entering and existing this module to peripherals within the i.MX27 chip. Table 22-1. Signal Properties Name Port Function External Signals ipp_do_ata_reset_b ipp_do_ata_dior ipp_do_ata_diow ipp_do_ata_cs1 ipp_do_ata_cs1 ipp_do_ata_da2 ipp_do_ata_da1 ipp_do_ata_da0 ipp_ind_ata_dmarq ipp_do_ata_dmack ipp_ind_ata_intrq ipp_ind_ata_iordy ipp_do_ata_data[15:0] ipp_ind_ata_data[15:0] ipp_obe_ata_data ipp_do_ata_buffer_en out out out out out out out out in out in in out in out out ATA bus reset signal. Active low. If active, ata device is reset1 ATA bus read strobe ATA bus write strobe ATA bus chip select 1 ATA bus chip select 0 ATA bus address line 2 ATA bus address line 1 ATA bus address line 0 ATA bus DMA request ATA bus DMA acknowledge ATA bus interrupt request ATA bus iordy ATA output data bus ATA input data bus Data transmit tri-state control signal Buffer enable for external bus transceiver2 0 1 1 1 1 0 0 0 — 1 — — Hi-z Hi-z 0 0 — — — — — — — — — — — — — — — — Reset State Type Interface Signals ipbus_int out Active high ATA interrupt DMA Signals ata_tx_fifo_alarm ata_rcv_fifo_alarm ata_txfer_end_alarm 1 2 0 — out out out DMA transmit fifo alarm request DMA receive fifo alarm request DMA transfer end alarm 0 0 0 — — — This signal is a standard ATA bus signal. It conforms with the ATA-6 standard. It is optional to put a 74xxx245 bus transceiver between the host side of the data bus and the device side of the data bus. If the transceiver is used, its enable should be tied low (always enable), and its direction pin should be tied to ata_buffer_en, in such a way that it drives from host to device when ata_buffer_en is high, and drives from device to host when ata_buffer_en is low. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-4 Freescale Semiconductor Advanced Technology Attachment (ATA) 22.5.1 Detailed Signal Descriptions The following subsections describe each external signals separately. For a detailed description of the ATA bus signal, refer to the ATA/ATAPI-6 standard. 22.5.1.1 ipp_do_ata_reset_b (out) This signal is the ATA reset signal. When low, the ATA bus is in reset state. When high, no reset. The ATA bus is in reset whenever the appropriate bit in the control register is cleared. After system reset, the ATA bus is in reset. 22.5.1.2 ipp_do_ata_dior (out) This signal correspond to ATA signal DIOR. During PIO and multiword DMA transfer, function is read strobe. During ultra DMA in burst, function is HDMARDY. During ultra DMA out burst, function is host strobe (HSTROBE). 22.5.1.3 ipp_do_ata_diow (out) This signal corresponds to ATA signal DIOW. During PIO and multiword DMA transfer, function is write strobe. During ultra DMA burst, function is STOP, signalling whenever host wants to terminate running ultra DMA transfer. 22.5.1.4 ipp_do_ata_cs0, ipp_do_ata_cs1, ipp_do_ata_da2, ipp_do_ata_da1, ipp_do_ata_da0 (out) These signals are the address group of the ATA bus. ata_cs0, ata_cs1 are the chip selects; ata_da2, ata_da1 and ata_da0 are the 3 address lines. All these five lines follow the same timing. 22.5.1.5 ipp_ind_ata_dmarq (in) This signal is the ATA bus device DMA request (DMARQ). Its pulled high by the device if it wants to transfer data using multiword DMA or ultra DMA mode. 22.5.1.6 ipp_do_ata_dmack (out) This signal is the ATA bus host DMA acknowledge (DMACK). Its pulled low by the host when it grants the DMA request. 22.5.1.7 ipp_ind_ata_intrq (in) This signal is the ATA bus interrupt request (INTRQ). Its pulled high by the device whenever it wants to interrupt the host CPU. 22.5.1.8 ipp_ind_ata_iordy (in) This signal is the ATA bus IORDY line. It has three functions: MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-5 Advanced Technology Attachment (ATA) • • • IORDY—Active low wait during PIO cycles. DDMARDY—Active low device ready during ultra DMA out transfers. DSTROBE—Device strobe during ultra DMA in transfers. 22.5.1.9 ipp_do_ata_data[15:0] (out) This is the module output data to ata bus. 22.6 Memory Map and Register Definition Section 22.6.3, “Register Descriptions” provides the detailed descriptions for all of the ATA registers. 22.6.1 Memory Map Table 22-2. ATA Memory Map Address Description ATA timing parameter 0 ATA Timing Parameter 1 ATA Timing Parameter 2 ATA Timing Parameter 3 ATA Timing Parameter 4 ATA Timing Parameter 5 32-Bit Wide Data Port to/from FIFO 16-Bit Wide Data Port to/from FIFO FIFO Filling In Half Words ATA Interface Control Register Interrupt Pending Register Interrupt Enable Register Interrupt Clear Register Access R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W W Reset Value 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0101_0101 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0010 0x0000_0000 0x0000_00— — Section/Page 22.6.3.1.1/22-11 22.6.3.1.2/22-11 22.6.3.1.3/22-12 22.6.3.1.4/22-13 22.6.3.1.5/22-14 22.6.3.1.6/22-14 22.6.3.2.1/22-15 22.6.3.2.2/22-16 22.6.3.3/22-17 22.6.3.4/22-17 22.6.3.5/22-19 22.6.3.5/22-19 22.6.3.5/22-19 Table 22-2 shows the ATA memory map. 0x8000_1000 (TIME_CONFIG0) 0x8000_1004 (TIME_CONFIG1) 0x8000_1008 (TIME_CONFIG2) 0x8000_100C (TIME_CONFIG3) 0x8000_1010 (TIME_CONFIG4) 0x8000_1014 (TIME_CONFIG5) 0x8000_1018 (FIFO_DATA_32) 0x8000_101C (FIFO_DATA_16) 0x8000_1020 (FIFO_FILL) 0x8000_1024 (ATA_CONTROL) 0x8000_1028 (INT_PENDING) 0x8000_102C (INT_ENABLE) 0x8000_1030 (INT_CLEAR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-6 Freescale Semiconductor Advanced Technology Attachment (ATA) Table 22-2. ATA Memory Map (continued) Address 0x8000_1034 (FIFO_ALARM) 0x8000_A0 (DDTR) 0x8000_A4 (DFTR) 0x8000_A8 (DSCR) 0x8000_AC (DSNR) 0x8000_B0 (DCLR) 0x8000_B4 (DCHR) 0x8000_B8 (DDHR) 0x8000_BC (DCDR) 0x8000_BC (DCDR) 0x8000_D8 (DCTR) 0x8000_D8 (DCTR) Description FIFO Alarm Threshold Drive Data Register Drive Features Register Drive Sector Count Register Drive Sector Number Register Drive Cylinder Low Register Drive Cylinder High Register Drive Device Head Register Drive Command Register Drive Status Register Drive Alternate Status Register Drive Control Register Access R/W 16-bit RW R/W R/W R/W R/W R/W R/W W R R W Reset Value 0x0000_0001 ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— ———— Section/Page 22.6.3.6/22-21 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.3.7/22-22 22.6.2 Register Summary Figure 22-2 shows the key to the register fields and Table 22-3 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 22-2. Key to Register Fields Table 22-3. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c slfclr Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero. Reset Values MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-7 Advanced Technology Attachment (ATA) Table 22-3. Register Figure Conventions (continued) Convention 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. Description [signal_name] Reset value is determined by polarity of indicated signal. Table 22-4 shows the ATA register summary. Table 22-4. ATA Register Summary Name R 0x8000_1000 (TIME_CONFIG0) W R W R 0x8000_1004 (TIME_CONFIG1) W R W R 0x8000_1008 (TIME_CONFIG2) W R W R 0x8000_100C (TIME_CONFIG3) W R W R 0x8000_1010 (TIME_CONFIG4) W R W R 0x8000_1014 (TIME_CONFIG5) W R W R 0x8000_1018 (FIFO_DATA_32) W R W FIFO_DATA_32 TIME_CVH TIME_DVS TIME_CYC TIME_SS TIME_MLIX TIME_ZAH TIME_DZFS TIME_DVH TIME_ACK TIME_K TIME_RPX TIME_ENV TIME_M TIME_9 TIME_D TIME_JN TIME_AX TIME_2R TIME_4 TIME_PIO_RDX TIME_ON TIME_OFF 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 TIME_2W TIME_1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-8 Freescale Semiconductor Advanced Technology Attachment (ATA) Table 22-4. ATA Register Summary (continued) Name R 0x8000_101C (FIFO_DATA_16) W R W R 0x8000_1020 (FIFO_FILL) W R W R 0x8000_1024 (ATA_CONTROL) W R W R 0x8000_1028 (INT_PENDING) W R W R 0x8000_102C (INT_ENABLE) W R W R 0x8000_1030 (INT_CLEAR) W R W R 0x8000_1034 (FIFO_ALARM) W R W R 0x8000_A0 (DDTR) W R W R 0x8000_A4 (DFTR) W R W R 0x8000_A8 (DSCR) W R W 0 0 0 0 0 0 0 0 DSCR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFTR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDTR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_ALARM[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_U NDERFIFO_O VER- 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_DATA_16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIF O_ 0 0 ATA _R 0 0 FIF O_ 0 FIF 0 FIF O_ 0 0 0 0 0 0 0 0 0 FIFO_FILL[7:0] 0 0 0 0 0 FIF DM DM DM IOR O_ A_P A_U A_W DY_ 0 CO 0 CO NT 0 0 0 ATA 0 ATA _IN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATA FIF 0 0 ATA FIF _IN O_ 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-9 Advanced Technology Attachment (ATA) Table 22-4. ATA Register Summary (continued) Name R 0x8000_AC (DSNR) W R W R 0x8000_B0 (DCLR) W R W R 0x8000_B4 (DCHR) W R W R 0x8000_B8 (DDHR) W R W R 0x8000_BC (DCDR) W R W R 0x8000_D8 (DCTR) W R W 0 0 0 0 0 0 0 0 DCTR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDHR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCHR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCLR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSNR[7:0] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22.6.3 Register Descriptions This section contains the detailed register descriptions for the ATA host controller registers and mapped device registers. All ATA host controller registers except FIFO_DATA_16 are 32-bit size accessible. FIFO_DATA_16 is only support 16-bit size accessible. All ATA device registers except DDTR are 8-bit size accessible. The DDTR is only support 16-bit size accessible. 22.6.3.1 Timing Registers Registers (ata_base +$00) till (ata_base + $17) contain timing parameters. These timing parameters control the timing on the ATA bus. Every timing parameter is 8-bit wide and can assume valid values between 1 and 255. Reset value is always 1. And all timing parameter registers are 32-bit size accessible. All figures in this section show timing registers. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-10 Freescale Semiconductor Advanced Technology Attachment (ATA) 22.6.3.1.1 TIME_CONFIG0 See Figure 22-3 for an illustration of valid bits in the ATA TIME_CONFIG0 Register and Table 22-5 for descriptions of the bit fields. 0x8000_1000 (TIME_CONFIG0) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R TIME_2W W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TIME_ON W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_OFF Figure 22-3. ATA TIME_CONFIG0 Register Table 22-5. ATA TIME_CONFIG0 Register Field Descriptions Field 31–24 TIME_2W 23–16 TIME_1 15–8 TIME_ON 7–0 TIME_OFF Description Pio mode time parameter counter for time of DIOW- pulse width (t2w or t2), these shall be used the max time of 8-bit and 16-bit. Pio mode time parameter counter for time of address valid to DIOR-/DIOW- setup(t1). Time parameter counter for transceiver to turn on. Time parameter counter for transceiver to turn off. 22.6.3.1.2 TIME_CONFIG1 See Figure 22-4 for an illustration of valid bits in the ATA TIME_CONFIG1 Register and Table 22-6 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-11 Advanced Technology Attachment (ATA) 0x8000_1004 (TIME_CONFIG1) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R TIME_4 W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_PIO_RDX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TIME_AX W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_2R Figure 22-4. ATA TIME_CONFIG1 Register Table 22-6. ATA TIME_CONFIG1 Register Field Descriptions Field 31–24 TIME_4 23–16 TIME_PIO_RDX 15–8 TIME_AX 7–0 TIME_2R Description PIO mode time parameter counter for controlling the time of DIOR- data hold (t4). Pio mode time parameter counter for controlling the time of read data valid to IORDY active (tRD). Pio time parameter counter for timing of IORDY setup time (tA). Pio mode time parameter counter for time of DIOR- pulse width (t2r or t2), these shall be used the max time of 8-bit and 16-bit. 22.6.3.1.3 TIME_CONFIG2 See Figure 22-5 for an illustration of valid bits in the ATA TIME_CONFIG2 Register and Table 22-7 for descriptions of the bit fields. 0x8000_1008 (TIME_CONFIG2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R TIME_D W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_JN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TIME_M W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_9 Figure 22-5. ATA TIME_CONFIG2 Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-12 Freescale Semiconductor Advanced Technology Attachment (ATA) Table 22-7. ATA TIME_CONFIG2 Register Field Descriptions Field 31–24 TIME_D 23–16 TIME_JN 15–8 TIME_M 7–0 TIME_9 Description Multiword DMA mode time parameter counter for time of DIOR-/DIOW- asserted pulse width (tD). Multiword DMA mode time parameter counter for time of DIOW- data hold time (tH). Multiword DMA mode time parameter counter for time from CS valid to DIOR-/DIOW- (tM). Pio mode time parameter counter for controlling the DIOR-/DIOW- to address valid hold time. 22.6.3.1.4 TIME_CONFIG3 See Figure 22-6 for an illustration of valid bits in the ATA TIME_CONFIG3 Register and Table 22-8 for descriptions of the bit fields. 0x8000_100C (TIME_CONFIG3) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R TIME_RPX W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_ENV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TIME_ACK W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_K Figure 22-6. ATA TIME_CONFIG3 Register Table 22-8. ATA TIME_CONFIG3 Register Field Descriptions Field 31–24 TIME_RPX 23–16 TIME_ENV 15–8 TIME_ACK 7–0 TIME_K Description Ultra DMA mode time parameter counter for time of tRP. Ultra DMA mode time parameter counter for min. time of tENV. Ultra DMA mode time parameter counter for time of tACK. Multiword DMA mode time parameter counter for time of DIOW- negated pulse width (tKW). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-13 Advanced Technology Attachment (ATA) 22.6.3.1.5 TIME_CONFIG4 See Figure 22-7 for an illustration of valid bits in the ATA TIME_CONFIG4 Register and Table 22-9 for descriptions of the bit fields. 0x8000_1010 (TIME_CONFIG4) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R TIME_DZFS W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_DVH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TIME_MLIX W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_ZAH Figure 22-7. ATA TIME_CONFIG4 Register Table 22-9. ATA TIME_CONFIG4 Register Field Descriptions Field 31–24 TIME_DZFS 23–16 TIME_DVH 15–8 TIME_MLIX 7–0 TIME_ZAH Description Ultra DMA mode time parameter counter for tDZFS. Ultra DMA mode time parameter counter for tDVH. Ultra DMA mode time parameter counter for tMLI. Ultra DMA mode time parameter counter for tZAH. 22.6.3.1.6 TIME_CONFIG5 See Figure 22-8 for an illustration of valid bits in the ATA TIME_CONFIG5 Register and Table 22-10 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-14 Freescale Semiconductor Advanced Technology Attachment (ATA) 0x8000_1014 (TIME_CONFIG5) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R TIME_CYC W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_SS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TIME_CVH W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 TIME_DVS Figure 22-8. ATA TIME_CONFIG5 Register Table 22-10. ATA TIME_CONFIG5 Register Field Descriptions Field 31–24 TIME_CYC 23–16 TIME_SS 15–8 TIME_CVH 7–0 TIME_DVS Description Ultra DMA mode time parameter counter for tCYC. Ultra DMA mode time parameter counter for tSS. Ultra DMA mode time parameter counter for tCVH. Ultra DMA mode time parameter counter for tDVS. 22.6.3.2 FIFO Data Registers The FIFO_DATA register is used to read or write data to the internal FIFO. It can be accessed as a 16-bit register or as a 32-bit register. Any long write to the register will put the four bytes written into the FIFO. Any word write will put the two bytes written into the FIFO. Any long read will read four bytes from the FIFO. Any word read will read two bytes from the FIFO. 22.6.3.2.1 FIFO_DATA_32 Register in 32-bit Mode See Figure 22-9 for an illustration of valid bits in the FIFO_DATA_32 Register in 32-bit mode and Table 22-11 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-15 Advanced Technology Attachment (ATA) 0x8000_1018 (FIFO_DATA_32) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R FIFO_DATA_32[31:16] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FIFO_DATA_32[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-9. ATA FIFO_DATA_32 Register Table 22-11. ATA FIFO_DATA_32 Register Field Descriptions Field 31–0 FIFO_DATA_32 Description Read/Write 32-bit data from/to the FIFO, reads from this register return zero when the FIFO is empty. 22.6.3.2.2 FIFO_DATA_16 Register See Figure 22-10 for an illustration of valid bits in the FIFO_DATA_16 Register in 16-bit mode and Table 22-12 for descriptions of the bit fields. 0x8000_101C (FIFO_DATA_16) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FIFO_DATA_16[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-10. ATA FIFO_DATA_16 Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-16 Freescale Semiconductor Advanced Technology Attachment (ATA) Table 22-12. FIFO_DATA_16 Register Field Descriptions Field 31–16 Reserved. Description 15–0 Read/Write 16-bit data from/to the FIFO, reads from this register return zero when the FIFO is empty. FIFO_DATA_16 22.6.3.3 FIFO_FILL Register See Figure 22-11 for an illustration of valid bits in the FIFO_FILL Register and Table 22-13 for descriptions of the bit fields. 0x8000_1020 (FIFO_FILL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read only 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 FIFO_FILL[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-11. ATA FIFO_FILL Register Table 22-13. FIFO_FILL Register Field Descriptions Field 31–8 7–0 FIFO_FILL Reserved. FIFO_FILL is a read-only register. Any read to it returns the current number of half-words present in the fifo. Description 22.6.3.4 ATA_CONTROL Register See Figure 22-12 for an illustration of valid bits in the ATA_CONTROL Register and Table 22-13 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-17 Advanced Technology Attachment (ATA) 0x8000_1024 (ATA_CONTROL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W 0 0 0 0 0 0 0 0 DMA_ FIFO ATA_ FIFO FIFO DMA_ ULTR IOR DMA_ _RST RST_ _TX_ _RCV PEND A_SE DY_ WRITE _B B EN _EN ING LECT EN ED 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 22-12. ATA_CONTROL Register Table 22-14. ATA Control Register Field Descriptions Field 31–8 7 FIFO_RST_B 6 ATA_RST_B Reserved This field controls if the internal FIFO is in reset or enabled 0 FIFO reset 1 FIFO normal operation This bit controls the level on the ata_reset_b pin, and controls the reset of the internal ata protocol engine. 0 ATA_RST_B = 0, ata drive is reset, and internal protocol engine reset. 1 ATA_RST_B = 1, ata drive is not reset and internal protocol engine normal operation. FIFO transmit enable. This bit controls if the FIFO will make transmit data requests to the DMA. If enabled, the FIFO will request the DMA to refill it whenever FIFO filling drops below the alarm level. 0 FIFO refill by DMA disabled 1 FIFO refill by DMA enabled FIFO receive enable. This bit controls if the FIFO will make receive data requests to the DMA. If enabled, the FIFO will request the DMA to empty it whenever FIFO filling becomes greater or equal to the alarm level. 0 FIFO empty by DMA disabled 1 FIFO empty by DMA enabled DMA pending bit. This bit controls if the ATA interface will respond to a DMA request originating in the drive. If this bit is asserted, the ATA interface will start a multi-word DMA or ultra DMA burst whenever the drive asserts ata_dmarq. 0 ATA interface will not start DMA burst 1 ATA interface will start multi-word DMA or ultra DMA burst whenever drive asserts dmarq This bit indicates if a DMA burst started, the UDMA or MDMA protocol will be used 0 Multiword DMA protocol will be used 1 Ultra DMA protocol will be used Description 5 FIFO_TX_EN 4 FIFO_RCV_EN 3 DMA_PENDING 2 DMA_ULTRA_SELETED MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-18 Freescale Semiconductor Advanced Technology Attachment (ATA) Table 22-14. ATA Control Register Field Descriptions Field 1 DMA_WRITE 0 IORDY_EN Description This bit indicates the data direction on any DMA burst started 0 DMA in burst, ATA interface reads from drive 1 DMA out burst, ATA interface writes to drive This bit indicates if the ata_iordy handshake will be used during PIO mode 0 IORDY will be disregarded 1 IORDY handshake will be used 22.6.3.5 INT_PENDING, INT_ENABLE, INT_CLEAR Registers These 3 registers control interrupts coming from the ATA and going to the CPU and DMA. See Figure 22-13 for an illustration of valid bits in the INT_PENDING Register and Table 22-15 for descriptions of the bit fields. 0x8000_1028 (INT_PENDING) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read only 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 FIFO FIFO ATA_I _UND _OVE NTR ERFL RFLO Q1 OW W CON ATA_I TROL NTR LER_I Q2 DLE 0 0 0 W Reset 0 0 0 0 0 0 0 0 01 0 0 1 0 0 0 0 Figure 22-13. ATA INT_PENDING Register 1 Interrupts ata_intrq1 and ata_intrq2 only reset to 0 if during reset the interrupt input is low. See Figure 22-14 for an illustration of valid bits in the INT_ENABLE Register and Table 22-15 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-19 Advanced Technology Attachment (ATA) 0x8000_102C (INT_ENABLE) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 FIFO FIFO ATA_I _UND _OVE NTR ERFL RFLO Q1 OW W CON ATA_I TROL NTR LER_I Q2 DLE 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-14. ATA INT_ENABLE Register See Figure 22-15 for an illustration of valid bits in the INT_CLEAR Register and Table 22-15 for descriptions of the bit fields. 0x8000_1030 (INT_CLEAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W 0 0 0 0 0 0 0 0 0 FIFO FIFO _UND _OVE ERFL RFLO OW W 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 — — — — — — — Figure 22-15. ATA INT_CLEAR Register Table 22-15. INT_PENDING Register Field Description Field 31–8 7 ATA_INTRQ1 Reserved. ATA interrupt request 1. This bit reflects the value of the ata_intrq interrupt input. It is set in the interrupt pending register when the drive interrupt is pending, cleared otherwise. When the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, fifo_txfer_end_alarm will be asserted, signalling the DMA the end of the transfer. The interrupt clear register has no influence on this bit. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-20 Freescale Semiconductor Advanced Technology Attachment (ATA) Table 22-15. INT_PENDING Register Field Description (continued) Field 6 FIFO_UNDERFLOW Description FIFO underflow. This bit reports FIFO underflow. Sticky bit. It is set in the interrupt pending register when there is a FIFO underflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the CPU. FIFO overflow. This bit reports FIFO overflow. Sticky bit. It is set in the interrupt pending register when there is a FIFO overflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the CPU. Controller Idle. This bit reports controller idle. It is set when the ATA protocol engine is idle, there is no activity on the ATA bus. It is cleared when there is activity on the ATA bus. When the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the CPU. The interrupt clear register has no influence on this bit. ATA interrupt request 2. This bit reflects the value of the ata_intrq interrupt input. It is set in the interrupt pending register when the drive interrupt is pending, cleared otherwise. It has exactly same functioning as ata_intrq1, but this bit affects ipbus_int, while the other affects interrupt to the DMA. When the bit is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be asserted, signalling the CPU the drive is requesting attention. The interrupt clear register has no influence on this bit. Reserved 5 FIFO_OVERFLOW 4 CONTROLLER_IDLE 3 ATA_INTRQ2 2–0 A group of three registers control the interrupt interface from the ATA module and going to the CPU and DMA. There are two interrupts controlled by these registers: • ipbus_int. This interrupt is controlled by bits 3,4, 5 and 6 of the interrupt registers. It will be asserted if one of the 4 bits is set in the INT_PENDING register, while the same bit is set in the INT_ENABLE register. This interrupt goes to the CPU. • fifo_txfer_end_alarm. This interrupt is controlled by bit 7 of the interrupt registers. If ata_intrq1 is set in both the interrupt enable and interrupt pending register, fifo_txfer_end_alarm will be asserted. The goal of this interrupt is to inform the DMA that the running data transfer has ended. This interrupt goes to the smart DMA. These three registers have mostly the same bits. If a bit is set in the interrupt pending register, its interrupt is pending, and will produce an interrupt if the same bit is set in the interrupt enable register. Some bits in the interrupt pending register are sticky bits. Writing a ‘1’ to the corresponding bit in the interrupt clear bit, will reset them. 22.6.3.6 FIFO Alarm Register See Figure 22-16 for an illustration of valid bits in the FIFO_ALARM Register and Table 22-16 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-21 Advanced Technology Attachment (ATA) 0x8000_1034 (FIFO_ALARM) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 FIFO_ALARM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 22-16. ATA FIFO_ALARM Register Table 22-16. ATA FIFO_ALARM Register Field Descriptions Field 31–8 Reserved Description 7–0 This register contains the threshold to generate fifo_rcv_alarm and fifo_tx_alarm to the DMA interface. FIFO_ALARM If (fifo_tx_en == 1 && fifo_fill < fifo_alarm): fifo_tx_alarm is set 1, request is made to DMA to refill fifo. If (fifo_rcv_en == 1 && fifo_fill >= fifo_alarm): fifo_rcv_alarm is set 1, request is made to DMA to empty fifo. 22.6.3.7 Drive Registers Mapped to Host Module Table 22-17. Drive Registers connected to ATA Bus Address Name drive_data drive_features drive_sector_count drive_sector_num drive_cyl_low drive_cyl_high drive_dev_head drive_command drive_status drive_alt_status driver_control Description Drive Data Register Drive Features Register Drive Sector Count Register Drive Sector Number Register Drive Cylinder Low Register Drive Cylinder High Register Drive Device Head Register Drive Command Register When Write Drive Status Register When Read Drive Alternate Status Register When Read Drive Counter Register When Write Access R/W R/W R/W R/W R/W R/W R/W W R R W 0x8000_A0 (DDTR) 0x8000_A4 (DFTR) 0x8000_A8 (DSCR) 0x8000_AC (DSNR) 0x8000_B0 (DCLR) 0x8000_B4 (DCHR) 0x8000_B8 (DDHR) 0x8000_BC (DCDR) 0x8000_BC (DCDR) 0x8000_D8 (DCTR) 0x8000_D8 (DCTR) Device registers are addressable and all registers except DDTR are 8-bit size accessible, The register DDTR is 16-bit size accessible, but all these registers are not present in the ATA interface module. A list is given in Table 22-17. If a read or write access is made to one of these registers, the read or write is MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-22 Freescale Semiconductor Advanced Technology Attachment (ATA) mapped to a PIO read or write cycle on the ATA bus, and the corresponding register in the device attached to the ATA bus is accessed. 22.7 Functional Description To best describe the organization of the ATA Host controller module from a user’s point of view, it is instructive to view the module at a number of different levels of hierarchy. See Figure 22-17 for an illustration of the organization of ATA and connection to a HDD device. Timing Parameters PIO Channel Control Register BUS Bus Interface Interrupt Interface FIFO 64x16 ata_fifo.v ata_reg.v Drive Register Multiword DMA Channel ata_reset_b ata_dior ata_diow ata_cs1 ata_cs0 ata_da2 ata_da1 ata_da0 ata_dmarq ata_dmack ata_intrq ata_iordy Hard Disk Device ata_ahb.v FIFO control ata_data Ultra DMA Channel ata_controller.v buffer ata_buffer_en Figure 22-17. Block Diagram for ATA Module The ATA host controller module is complied with the ATA/ATAPI-6 specification. The module consists of six main parts: • AHB Bus Interface • Register Block • 64x16 FIFO for data buffer • PIO/MDMA/UDMA protocol engine • CRC block • Input signal synchronizer 22.8 Initialization/Application Information The ATA interface provides two ways to communicate with the ATA peripherals connected to the ATA bus • PIO mode read/write operation to the ATA bus. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-23 Advanced Technology Attachment (ATA) • DMA transfers with the ATA bus The operation of the peripheral is described in detail in the following sections. 22.8.1 Resetting ATA Bus The ATA bus reset ata_reset_b is asserted whenever bit 6 ata_rst_b of register ata_control is cleared to 0. At the same time, the ATA protocol engine is reset. When this bit is set to 1, the reset is released. 22.8.2 Access to ATA Bus in PIO Mode Access to the ATA bus in PIO mode is possible after: • ata_rst_b bit in register ata_control is set. • Timing parameters have been programmed. To access the drive in PIO mode, simply read or write to the correct drive register. The bus cycle will be translated to an ATA cycle, and the drive is accessed. When drive registers are accessed while the ATA bus is in reset, the read or write is discarded, not done. 22.8.3 Using DMA Mode to Receive Data from ATA bus Apart from PIO mode, the ATA interface supports also MDMA and UDMA mode to transfer data. DMA mode can be used to receive data from the drive (DMA in transfer). In DMA receive mode, the protocol engine will transfer data from the drive to the FIFO using multiword DMA or ultra DMA protocol. The transfer will pause when one of following occurs: • The FIFO is full. • The drive deasserts its DMA request signal ata_dmarq. • The bit dma_pending in the ata_control register is cleared. When the cause of the transfer pausing is removed, the transfer restarts. The end of the transfer is signalled by the drive to the host by asserting the ata_intrq signal. Alternatively, the host can read the device status register. In this register, the drive will also indicate if the transfer has ended. The transfer of data from the FIFO into the memory is handled by the host system DMA. Whenever the FIFO filling is above the alarm threshold, the DMA should read one packet of data from the FIFO, and store this in main memory. In doing so, the DMA prevents the FIFO from getting full, and keeps the transfer from drive to FIFO running. The steps for setting up a DMA data transfer from device to host are: 1. Make sure the ATA bus is not in reset and all timing registers are programmed. 2. Make sure the FIFO is empty by reading it until empty or by resetting it. 3. Initialize the DMA channel connected to fifo_rcv_alarm. Every time fifo_rcv_alarm is high, the DMA should read long integers from the FIFO, and store them to main memory. (typical packetsize is 8 longs) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-24 Freescale Semiconductor Advanced Technology Attachment (ATA) 4. Write 2 * to fifo_alarm register. In this way, FIFO will request attention to DMA when there is at least one packet ready for transfer. 5. To make the ATA ready for a DMA transfer from device to host, take the following steps: a) Make sure the FIFO is out of reset by setting bit fifo_rst_b to 1 in the ata control register. b) Program fifo_rcv_en=1 in ata_ control register. This enables the FIFO to be emptied by the DMA. c) Program dma_pending =1, dma_write=0, ultra_mode_selected=0/1 in ata_control register. ultra_mode_selected should be 1 if you want to transfer data using UDMA mode, it should be 0 if you want to transfer data using MDMA mode. 6. Now, the host side of the DMA is ready. Send commands to the drive in PIO mode that cause it to request DMA transfer on the ATA bus. The nature of these commands is beyond the scope of this document. You should consult the ATA specification to know how to communicate with the drive. 7. When the drive now requests DMA transfer by pulling ata_dmarq high, the ATA interface will acknowledge with ata_dmack, and the transfer will start. Data is transferred automatically to the FIFO, and from there on to the host memory. 8. During the transfer, the host can monitor for end of transfer by reading some device ATA registers. These reads will cause the running DMA to pause; after the read is completed, the DMA resumes. The host can also wait unit the drive asserts ata_intrq. This also indicates end of transfer. 9. On end of transfer, the host or host DMA should wait until controller_idle is set, and next read the remaining half words from the FIFO, and transfer these to memory. NOTE There may be less than remaining bytes, so transfer will not be automatic by the DMA. 22.8.4 Using DMA Mode to Transmit Data to ATA bus Apart from PIO mode, the ATA interface supports also MDMA and UDMA mode to transfer data. DMA mode can be used to transmit data to the drive (DMA out transfer). In DMA transmit mode, the protocol engine will transfer data from the FIFO to the drive using multi word DMA or ultra DMA protocol. The transfer will pause when one of following occurs: • The FIFO is empty. • The drive deasserts its DMA request signal ata_dmarq. • The bit dma_pending in the ata_control register is cleared. When the cause of the transfer pausing is removed, the transfer restarts. The end of the transfer is signalled by the drive to the host by asserting the ata_intrq signal. Alternatively, the host can read the device status register. In this register, the drive will also indicate if the transfer has ended. The transfer of data from the memory to the FIFO is handled by the host system DMA. Whenever the FIFO filling is below the alarm threshold, the DMA should read one packet of data from the main memory, and store this in the FIFO. In doing so, the DMA prevents the FIFO from getting empty, and keeps the transfer from FIFO to drive running. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 22-25 Advanced Technology Attachment (ATA) The steps for setting up a DMA data transfer from device to host are: 1. Make sure the ATA bus is not in reset and all timing registers are programmed. 2. Make sure the FIFO is empty by reading it until empty, or by resetting it. 3. Initialize the DMA channel connected to fifo_tx_alarm. Every time fifo_tx_alarm is high, the DMA should read long integers from the main memory, and write them to the FIFO. (typical packetsize is 8 longs). Program the DMA such that it will not transfer more than long words in total. 4. Write FIFO_SIZE - 2 * to fifo_alarm register. In this way, FIFO will request attention to DMA when there is room for at least one extra packet. FIFO_SIZE should be given in half words. (typical 64 half words) 5. To make the ATA ready for a DMA transfer from host to device, perform the following steps: a) Make sure the FIFO is out of reset by setting bit fifo_rst_b to 1 in the ata control register. b) Program fifo_tx_en=1 in ata_control register. This enables the FIFO to be filled by DMA. c) Program dma_pending =1, dma_write=1, ultra_mode_selected=0/1 in ata_control register. ultra_mode_selected should be 1 if you want to transfer data using UDMA mode, it should be 0 if you want to transfer data using MDMA mode. 6. Now, the host side of the DMA is ready. Send commands to the drive in PIO mode that cause it to request DMA transfer on the ATA bus. The nature of these commands is beyond the scope of this document. You should consult the ATA specification to know how to communicate with the drive. 7. When the drive now requests DMA transfer by pulling ata_dmarq high, the ATA interface will acknowledge with ata_dmack, and the transfer will start. Data is transferred automatically from the FIFO, and also from host memory to FIFO. 8. During the transfer, the host can monitor for end of transfer by reading some device ATA registers. These reads will cause the running DMA to pause; after the read is completed, the DMA resumes. The host can also wait unit the drive asserts ata_intrq. This also indicates end of transfer. At end of transfer, no extra FIFO manipulations are needed. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 22-26 Freescale Semiconductor Chapter 23 Configurable Serial Peripheral Interface (CSPI) The i.MX27 processor contains three Configurable Serial Peripheral Interface (CSPI) modules that allow rapid data communication with fewer software interrupts than conventional serial communications. Each CSPI is equipped with two data FIFOs and is a master/slave configurable serial peripheral interface module, allowing i.MX27 to interface with both external SPI master and slave devices. This chapter describes how the CSPI module communicates with external devices. Each CSPI has one 8 × 32-bit data-in FIFO and one 8 × 32-bit data-out FIFO. Incorporating the CSPI1_RDY and SS control signals, it enables fast data communication with fewer software interrupts. Figure 23-1 illustrates the configurable serial peripheral interface block diagram. IP BUS INTERFACE CSPI1_RDY CLOCK GENERATOR CONTROL 3 SS SCLK MISO SHIFT REGISTER MOSI Rx FIFO 8 × 32 Tx FIFO 8 × 32 Figure 23-1. Configurable Serial Peripheral Interface Block Diagram 23.1 Features The primary features of the CSPIs include: • Master/Slave configurable for CSPI1 and CSPI2. CSPI3 is only a master. • CSPI1 and CSPI2 have three chip-selects (SS0-SS3) respectively. CSPI3 has one chip select (SS0). • Up to 32-bit programmable data transfer MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-1 Configurable Serial Peripheral Interface (CSPI) • • • • • • 8 × 32-bit FIFO for both Tx and Rx data Transfer continuation function allows unlimited length data transfers Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable DMA support Full-duplex synchronous serial interface Maximum SPI clock frequency up to 22.167 MHz as a master, 16.625 MHz as a slave 23.1.1 External Signals Description The following signals are visible to external SPI devices. They are used to control the serial peripheral interface: • MOSI—Master Out Slave In bidirectional signal, which is TxD output signal from the data shift register in master mode. In Slave mode it is RxD input to the data shift register. • MISO—Master In Slave Out bidirectional signal, which is RxD input signal to the data shift register in master mode. In Slave mode it is TxD output from the data shift register. • SCLK—CSPI Clock bidirectional signal, which is CSPI clock output in master mode. In slave mode it is an input CSPI clock signal. • SS[2:0], Slave Select bidirectional signal, output in master mode, and input in slave mode. • CSPI1_RDY—This input signal is used for hardware control only in master mode. It indicates that external SPI slave is ready to receive data. It will edge or level trigger a CSPI burst if used. This signal is only available for CSPI1: it is not present on CSPI2 and CSPI3. It is ignored in slave mode. This signal is controlled by DRCTL(ControlReg[13:12]) bits. If the hardware control enabled, CSPI will transfer data only when external SPI slave is ready. 23.2 Module Input/Output Signals Table 23-1. Signal Listing Signal IN/OUT BITS Pad Level Signals IPP_DO_MOSI IPP_DO_MISO IPP_CSPI_CLK_OUT IPP_DO_SS0 OUT OUT OUT OUT 1 1 1 1 Tx data when CSPI is in Master mode. Tx data when CSPI is in Slave mode.It is tri-stated if the selected SSn is not asserted. Clock output when CSPI is in Master mode.Max. frequency is IPG_CLK_PERCLK/3. Slave select0 generated by CSPI in Master mode when CS[1:0] bits are set to ‘00’ in the CONTROL Register. Slave select1 generated by CSPI in Master mode when CS[1:0] bits are set to ‘01’ in the CONTROL Register. DESCRIPTION IPP_DO_SS1 OUT 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-2 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) Table 23-1. Signal Listing (continued) Signal IPP_DO_SS2 IN/OUT OUT BITS 1 DESCRIPTION Slave select2 generated by CSPI in Master mode when CS[1:0] bits are set to ‘10’ in the CONTROL Register. Slave select3 generated by CSPI in Master mode when CS[1:0] bits are set to ‘11’ in the CONTROL Register. Output enable for IPP_DO_MOSI, IPP_CSPI_CLK_OUT, IPP_DO_SS0, IPP_DO_SS1 and IPP_DO_SS2,IPP_DO_SS3 when the CSPI is in master mode. Output enable for ipp_do_miso. Rx data when CSPI is in Master mode. Rx data when CSPI is in Slave mode. Clock input when CSPI is in Slave mode. Slave Select0 signal from an external master when CSPI is in Slave mode. Slave Select1 signal from an external master when CSPI is in Slave mode. Slave Select2 signal from an external master when CSPI is in Slave mode. Slave Select3 signal from an external master when CSPI is in Slave mode. This input signal is used only in master mode. It will edge or level trigger a CSPI burst if used. Used to force CSPI Master mode from top level. IPP_DO_SS3 OUT 1 IPP_OBE_MOSI OUT 1 IPP_OBE_MISO IPP_IND_MIS0 IPP_IND_MOSI IPP_CSPI_CLK_IN IPP_IND_SS0 IPP_IND_SS1 IPP_IND_SS2 IPP_IND_SS3 IPP_IND_DATAREADY IPP_IND_FORCE_MASTER OUT IN IN IN IN IN IN IN IN IN 1 1 1 1 1 1 1 1 1 1 IP Bus Interface Signals IPS_BYTE_31_24 IPS_BYTE_23_16 IPS_BYTE_15_8 IPS_BYTE_7_0 IPS_MODULE_EN IPS_ADDR IPS_RWB IPS_WDATA IPS_RDATA IN IN IN IN IN IN IN IN OUT 1 1 1 1 1 11 1 32 32 Module byte access enable. Enables write to bits [31:24] of addressed register. Module byte access enable. Enables write to bits [23:16] of addressed register. Module byte access enable. Enables write to bits [15:8] of addressed register. Module byte access enable. Enables write to bits [7:0] of addressed register. Peripheral module enable Address bus Read access signal. Active low. Write Data bus Read Data bus MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-3 Configurable Serial Peripheral Interface (CSPI) Table 23-1. Signal Listing (continued) Signal IPS_XFR_WAIT IPS_XFR_ERR IN/OUT OUT OUT BITS 1 1 DESCRIPTION Wait signal to ARM Transfer error acknowledge. ips_xfr_err is generated when a write to a read-only register(RXDATA register) is performed. It is not generated when the write-only register (TXDATA register) is read. INTERRUPTS IPI_INT_CSPI OUT 1 CSPI interrupt request line to the core. DMA INTERFACE SIGNALS IPD_REQ_CSPI_TDMA IPD_REQ_CSPI_RDMA OUT OUT 1 1 DMA Tx request DMA Rx request GLOBAL SIGNALS IPG_HARD_NEG_ASYNC_RES ET IPG_HARD_POS_ASYNC_RES ET IPG_CLK_S IPG_CLK IPG_CLK IPG_CLK_EN IPG_CLK_PERCLK IPG_CLK_32K RESP_SEL IN IN IN IN IN IN OUT IN IN 1 1 1 1 1 1 1 1 1 Asynchronous, Active Low Hardware Reset for FFs clocked by inverted clocks. Asynchronous, Active Low Hardware Reset Clock gated by the OR function of all the ips_module_en signals from AIPI. Continuous Clock gated by the ipg_clk_en. Inverted ipg_clk clock. Used to gate off the ipg_clk depending on the module enable bit residing in the CSPI that is, the SPIEN bit. Reference baud rate clock. It must be slower than or equal to IPG_CLK. 32khz Continuous clock used for counting purpose. When this pin is ‘1’, the module will always return an OKAY response (that is, ips_xfr_err is not asserted) when there is an access to any location within the 4kbyte boundary, whereas, if this pin is’0’, the module will return an ERROR response (ips_xfr_err is asserted) when there is an access to an unused location within the 4kbyte boundary. TEST MODE SIGNALS IPT_TEST_MODE IPT_TEST_ASYNC_SE IPT_TEST_CLK_SE IPT_TEST_RESET_B IN IN IN IN 1 1 1 1 This is used to activate all scan testable logic into scan mode and non-scan logic into bypass mode. Used to handle internally generated resets. Used to switch between 32Khz clock and the ipg_clk. Test mode reset. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-4 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) 23.3 Operation When CSPI is configured as master, the SS (output) and CSPI1_RDY (input) signals, are used for data transfer rate control. The sample period control register can be set if a fixed data transfer rate is required. When CSPI is configured as slave, the SS signal becomes an input signal and can optionally be used for data latching and loading to the internal data shift registers, as well as incrementing internal data FIFO pointers. Figure 23-2 shows the generic CSPI timing. (POL=1, PHA=1) SCLK (POL=1, PHA=0) SCLK (POL=0, PHA=1) SCLK (POL=0, PHA=0) MISO MOSI SCLK Bn Bn-1 Bn-2 Bn-3 ... Bn Bn-1 Bn-2 Bn-3 ... ... ... b1 b1 b0 b0 Figure 23-2. Generic CSPI Timing 23.3.1 Phase and Polarity Configurations The serial peripheral interface master uses the SCLK signal to transfer data in and out of the shift register. Data is clocked using any one of four programmable clock phase and polarity combinations. During Phase 0, Polarity 0 and Phase 1, Polarity 1 operations, output data changes on the falling clock edge and input data is shifted in on the rising edge. The most-significant bit is output when the CPU loads the transmit data. During Phase 1, Polarity 0 and Phase 0, Polarity 1 operations, output data changes on the rising edges of the clock and is shifted in on falling edges. The most-significant bit is output on the first rising SCLK edge. Polarity inverts SCLK, but does not change the edge-triggered events that are internal to the serial peripheral interface master. This flexibility allows it to operate with most serial peripheral devices. Figure 23-2 shows the CSPI timing with various POL and PHA configurations. 23.3.2 Master Mode The CSPI master uses the SS signal to enable an external SPI device and uses SCLK to transfer data in and out of the Shift register. The SPI_RDY enables fast data communication with fewer software interrupts. By using PeriodReg, the CSPI can be used for a fixed data transfer rate. When CSPI is in Master mode the SS, SCLK, and MOSI are output signals and the MISO is an input. Figure 23-3 shows a typical SPI transfer. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-5 Configurable Serial Peripheral Interface (CSPI) SS SCLK MOSI MISO Figure 23-3. Typical SPI Transfer (8-Bit) In Figure 23-3, the SS signal enables the selected external SPI device and the SCLK synchronizes data transfer. MOSI and MISO change on rising edge of SCLK and the MISO is latched on the falling edge of the SLCK clock. The data shifted out is 0xD2, and the data shifted in is 0x66. 23.3.2.1 Master Mode with SPI_RDY By default, the CSPI does not use SPI_RDY in master mode. a SPI transfer begins when the following events happen: the CSPI is enabled, TXFIFO has data in it, and ControlReg[XCH] is set. When ControlReg[DRCTL] contains either 01 or 10, the SPI_RDY controls when a SPI burst starts. If ControlReg[DRCTL] is set to 01, the SPI burst can be triggered only if a falling edge of SPI_RDY has been detected. Figure 23-4 shows the relationship between a SPI transfer and the falling edge of SPI_RDY. SS SPI_RDY SCLK MOSI MISO Figure 23-4. Relationship between a SPI transfer and the Falling Edge of SPI_RDY a SPI transfer does not start until the falling edge of SPI_RDY is detected. The next SPI burst starts when the next SPI_RDY falling edge is detected, after the last transfer has finished. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-6 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) If ControlReg[DRCTL] is set to 10, the SPI burst can be triggered only if SPI_RDY is low. Figure 23-5 shows the relationship between a SPI transfer and SPI_RDY. The SPI transfer does not begin until SPI_RDY goes low. The next SPI transfer begins after the previous transfer has finished if SPI_RDY remains low. SS SPI_RDY SCLK MOSI MISO Figure 23-5. Relationship between a SPI Transfer and SPI_RDY 23.3.2.2 Master Mode with Wait States Wait states can be inserted between SPI transfers. This provides a way for the user to slow down the SPI transfer to meet the timing requirements of a slower SPI device. Figure 23-6 shows wait states inserted between SPI bursts. SS wS SCLK MOSI MISO Figure 23-6. SPI Transfers with Wait States In this case, the number of wait states is controlled by PeriodReg [WAIT] and the wait states’ clock source is selected by PeriodReg [CSRC]. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-7 Configurable Serial Peripheral Interface (CSPI) 23.3.2.3 Master Mode with Continuation Many transfers can be continuous without idle time insertion. This provides a way for the user to maximize data rate without any delay. Figure 23-7 shows the detail timing. SS SCLK MOSI MISO Figure 23-7. SPI continuous transfer with BURST=1 To obtain the Continuation function, the ControlReg [BURST] should be set to 1, with ControlReg [SSCTL] and PeriodReg [WAIT] set to 0. 23.3.2.4 Master Mode with SSCTL Control SSCTL controls whether a SS pulse is inserted between two data transfers. When SSCTL is set, a SS pulse will be inserted in multiple transfers. When SSCTL is cleared, SS signal will stay asserted in multiple transfers. Figure 23-8 and Figure 23-9 show the detail timing. SS SCLK MOSI MISO Figure 23-8. SPI Transfer while SSCTL is Clear MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-8 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) SS SCLK MOSI MISO Figure 23-9. SPI Transfers while SSCTL is Set 23.3.2.5 Master Mode with various configurations of WAIT, BURST and SSCTL Table 23-2 shows CSPI behavior in master mode in various configurations of PeriodReg[WAIT], ControlReg [BURST] and ControlReg [SSCTL]. In this table, x means don’t care (0 or 1). Table 23-2. CSPI Behavior In Master Mode In Various Configurations WAIT 0 0 0 Non-zero Non-zero BURST SSCTL 0 1 x x x 0 0 1 0 1 SCLK Pin 7*Tsclk1 idle time inserted between consecutive data transfers No idle time inserted between consecutive data transfers 7*Tsclk idle time inserted between consecutive data transfers SS Pin No pulse No pulse 2*Tsclk width pulse (7*Tsclk + WAIT*Tsclk_32k2) idle time inserted between consecutive data No pulse transfers (7*Tsclk + WAIT*Tsclk_32k) idle time inserted between consecutive data (2*Tsclk + transfers WAIT*Tsclk_32k) width pulse 1 2 Tsclk is CSPI SCLK period Tsclk_32k is either SCLK or 32KHz clock period 23.3.3 Slave Mode When the CSPI module is configured as a slave, the user can configure the CSPI Control register to match the external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data Shift registers, as well as to increment the data FIFO. The SS, SCLK, and MOSI are inputs and MISO is output. Most of their timing diagrams are the same as in Master mode, because the inputs come from a SPI master device. However, it is different when SS is used to increment data FIFO. When the SSCTL is set while CSPI is in Slave mode, the data FIFO will increment at SS rising edge. Figure 23-10 shows a SPI burst in which data FIFO is incremented by SS rising edge. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-9 Configurable Serial Peripheral Interface (CSPI) SS SCLK MOSI MISO Figure 23-10. Increment Data FIFO by SS Rising Edge In this case, the data received is not 0xD2 but 0x69. Only the most significant 7 bits are loaded to RXFIFO. 23.3.4 Interrupt Control Interrupt control is not a specific mode of operation; however, it provides a basic method to utilize the CSPI FIFOs. You can program the CSPI to enable the TXFIFO empty, TXFIFO half, and TXFIFO full interrupt. You can also use the interrupt service routine to fill the TXFIFO with data to be transferred. Furthermore, you can also enable RXFIFO ready, RXFIFO half, and RXFIFO full to retrieve data from RXFIFO by using the interrupt service routine. Three other interrupt sources can be used to control/debug the SPI transfer. The TxFIFO and Tx Shift Register Empty interrupt tells the user that there is not data left in TXFIFO and the data in the Shift register is shifted out. The bit counter overflow interrupt tells the user that the CSPI received more than 32 bits in a SPI burst and the remaining bits will be lost. The RXFIFO overflow interrupt tells the user that the RXFIFO received more than 8 words and will not accept any other word. Figure 23-11 shows a program sequence of SPI bursts using interrupt. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-10 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) . Enable CSPI Enable interrupts Fill TXFIFO using interrupt service routine Enable XCH Wait until all needed data are transferred Retrieve data using interrupt service routine TSHFE interrupt Done Figure 23-11. Program Sequence of SPI Burst Using Interrupt 23.3.5 DMA Control DMA control provides another way to utilize the FIFOs in the CSPI module. Peripherals such as the CSPI which support DMA, use DMA request and acknowledge signals. Larger amounts of data can be transferred using DMA control, thereby reducing interrupts and CPU loading. When the appropriate conditions are matched, the module will send out a DMA request, and the DMA will deal with the following cases: TXFIFO empty, TXFIFO half, RXFIFO half, and RXFIFO full. Figure 23-12 shows a program sequence of SPI bursts using the DMA. Enable CSPI Enable DMA Fill TXFIFO using DMA Enable XCH Wait until all needed data are transferred Retrieve data using DMA TSHFE interrupt Done Figure 23-12. Program Sequence of SPI Burst Using DMA MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-11 Configurable Serial Peripheral Interface (CSPI) 23.4 Initialization/Application Information This section provides initialization and application information for CSPI.Figure 23-13 shows two flow charts for the master and slave mode of operations supported by the CSPI. Configure Control Reg Configure ControlReg Configure INTREG (optional) Fill TXFIFO Configure DMAREG (optional) Waiting RXFIFO Interrupt (Ready, Half Full, Full) Configure PeriodReg (optional) Read Data from RXFIFO Fill TXFIFO Transfer Completed Set XCH bit Polling XCH bit or waiting TSHFE interrupt Read Data from RXFIFO Transfer Completed Master Mode Slave Mode Figure 23-13. Flow Chart of CSPI Operation Example 23-1 shows a normal example code of CSPI operation using ARM instructions. Example 23-1. CSPI Operation using ARM Instructions LDR R0, =CSPI_BASE_ADDRESS LDR R1, =0x00008C1F STR R1, [R0, #0x08] LDR R1, =0x00000021 STR R1, [R0, #0x0C] LDR R1, =0x00005000 ; Enable RXFIFO half and TXFIFO empty ; interrupt (Alternatively with DMA Mode) ; Enable RXFIFO half and TXFIFO empty ; Load CSPI Base Address to R0 ; Master Mode, 32-bit transaction MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-12 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) STR R1, [R0, #0x18] LDR R5, =0x05 LDR R1, =0x11111111 LDR R2, =0x12345678 Loop_00 STR R2, [R0,#0x04] ADD R2, R2, R1 SUB R5, R5, #1 CMP R5, #0x00 BNE Loop_00 ; DMA (Alternatively with interrupt) ; R5 as number of words to be transferred. ; R1 as increment to generate the data. ; R2 load the data to be transferred. ; Store data into TXFIFO. ; Generating next data to be transferred. ; Decrease the R5. ; Check R5 if it is zero. ; Loop until R5 is zero. LDR R1, =0x00008E1F STR R1, [R0, #0x08] Loop_01 LDR R1, [R0, #0x0C] LDR R2, =0x00000008 AND R1, R2, R1 CMP R1, #0x00 BNE PASS_00 B Loop_01 ; set XCH bit to start transaction. ; check TSHFE bit if it is set. ; if TSHFE bit is set then finish. ; if it isn’t set then continue loop LDR R1, [R0, #0x00] ; Read data from RXFIFO. 23.4.1 Software Restrictions The section should include software restrictions that impact the customer. • All reserved bits cannot be written and always read as 0. • Writes to the TXDATA register are ignored when the CSPI module is disabled (SPIEN bit of CSPI ControlReg is cleared). • The SPI Module Enable Control bit must be asserted before writing to other registers or initiating an exchange. 23.5 Memory Map and Register Definition The CSPI includes eight 32-bit registers. Section 23.5.3, “Register Descriptions” provides the detailed descriptions for the CSPI registers. The following sections provide the register summary and the MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-13 Configurable Serial Peripheral Interface (CSPI) programming model for the 3 CSPI modules in the i.MX27. The Register Summary in Table 23-3 lists all registers of the CSPI module by ascending address. The absolute address of each register is given, as is the value of each bit for reads and writes. 23.5.1 Memory Map Table 23-1. CSPI Memory Map Address Register Receive Data Register (RXDATA) Transmit Data Register (TXDATA) Control Register (CONREG) Interrupt Control Register (INTREG) DMA Control Register (DMAREG) Status Register (STATREG) Sample Period Control Register (PERIODREG) Access R W R/W R/W R/W R/W R/W Reset Value Section/Page Table 23-1 shows the CSPI memory map. 0x1000_E0000 (RXDATA) 0x1000_E0004 (TXDATA) 0x1000_E0008 (CONREG) 0x1000_E000C (INTREG) 0x1000_E0010 (DMAREG) 0x1000_E0014 (STATREG) 0x1000_E0018 (PERIODREG) 0x0000_0000 23.5.3.1/23-16 0x0000_0000 23.5.3.2/23-17 0x0000_0000 23.5.3.3/23-18 0x0000_0000 23.5.3.4/23-20 0x0000_0000 23.5.3.5/23-22 0x0000_0003 23.5.3.6/23-23 0x0000_0000 23.5.3.7/23-24 23.5.2 Register Summary 1 Always reads 0 0 Write 1 BIT Self-clear 0 R/W BIT Read- BIT Writebit BIT bit only bit only bit BIT to clear w1c N/A Figure 23-14 shows the key to the register fields, and Table 23-2 shows the register figure conventions. Always reads 1 Figure 23-14. Key to Register Fields Table 23-2. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-14 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) Table 23-2. Register Figure Conventions (continued) Convention Description Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 23-3. CSPI Register Summary Name RxDataReg 0x1000 E000 0x1000 F000 0x1001 7000 R W R W TxDataReg 0x1000 E004 0x1000 F004 0x1001 7004 R W R W ControlReg 0x1000 E008 0x1000 F008 0x1001 7008 R W R W INTREG 0x1000 E00C 0x1000 F00C 0x1001 700C R W RFE RHE RR N N EN W TestReg 0x1000 E010 0x1000 F010 0x1001 7010 R W R W SS_ LBC INIT ASS ERT SSTATUS[3:0] RXCNT[3:0] TXCNT[3:0] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 RxData[31:16] RxData[15:0] Tx Data [31:16] Tx Data [15:0] 0 0 0 0 0 0 0 0 BUR ST SSC TL SDH C_S PIEN SW AP CS[1:0] DataRate[4:2] DataRate[ 1:0] 0 0 DR CTL[1:0] 0 0 MO DE SPIE N XCH SSP OL PHA POL BIT COUNT[4:0] 0 0 0 0 0 0 0 0 0 0 BO EN ROE N R TSH TFE FEE N N 0 0 THE N 0 TEEN 0 BO 0 RO 0 RF 0 RH 0 RR 0 TSHF E 0 TF 0 TH 0 TE 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-15 Configurable Serial Peripheral Interface (CSPI) Table 23-3. CSPI Register Summary (continued) Name PeriodReg 0x1000 E014 0x1000 F014 0x1001 7014 R W R CSR C W R W THD TED W EN EN ResetReg 0x1000 E01C 0x1000 F01C 0x1001 701C R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STA RT 0 0 R RF D EN 0 RHD EN 0 0 0 0 0 TH TE DMA DMA 0 0 RF DM A 0 RH DM A 0 0 0 0 0 0 0 0 0 0 0 0 0 WAIT[14:0] 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREG 0x1000 E018 0x1000 F018 0x1001 7018 0 0 0 0 0 0 0 0 23.5.3 Register Descriptions The following section describes the detailed register descriptions for the CSPI registers. 23.5.3.1 Receive Data Register (RXDATA) The Receive Data register (RXDATA) is a read-only register that forms the top word of the 8 × 32 receive FIFO. This register holds the data received from an external SPI device during a data transaction. Only word-sized read operations are allowed. Figure 23-15 shows the RXDATA register, and Table 23-4 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-16 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) 0x1000_E0000 (RXDATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-only 18 17 16 R W Reset 0 0 0 0 0 0 0 RXDATA[31:16] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 RXDATA[15:0] 0 0 0 0 0 0 0 0 0 Figure 23-15. RXDATA Register Diagram Table 23-4. RXDATA Register Field Descriptions Field 31–0 RXDATA Description Receive Data. This register holds the top word of the receive data FIFO. The FIFO is advanced for each read of this register. The data read is undefined when the Receive Data Ready (RR) bit in the Interrupt Control/Status register is cleared. Zeros are read when CSPI is disabled. 23.5.3.2 Transmit Data Register (TXDATA) The Transmit Data (TXDATA) register is a write-only data register that forms the top word of the 8 × 32 TXFIFO. The TXFIFO can be written to as long as it is not full, even when the XCH bit in CONREG is set. This allows the user write access to the TXFIFO during a SPI data exchange process. Writes to this register are ignored when the CSPI module is disabled (EN bit of CSPI CONREG is cleared). Figure 23-16 shows the CNTRL register, and Table 23-5 shows the register’s field descriptions. 0x1000_E0004 (TXDATA) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User write-only 18 17 16 R W Reset 0 0 0 0 0 0 0 TXDATA[31:16] 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 TXDATA[15:0] 0 0 0 0 0 0 0 0 0 Figure 23-16. TXDATA Register Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-17 Configurable Serial Peripheral Interface (CSPI) Table 23-5. TXDATA Register Field Descriptions Field 31–0 TXDATA Description Transmit Data. This register holds the top word of data loaded into the FIFO. Data written to this register must be a word operation. The number of bits actually transmitted is determined by the BIT_COUNT field of the corresponding SPI Control register. If this field contains more bits than the number specified by BIT_COUNT, the extra bits are ignored. For example, to transfer 10 bits of data, a 32-bit word must be written to this register. Bits 9-0 are shifted out and bits 31-10 are ignored. When the CSPI module is operating in Slave mode, zeros are shifted out when the FIFO is empty. Zeros are read when CSPI is disabled. 23.5.3.3 Control Register (CONREG) The Control Register (CONREG) allows the user to enable the CSPI module, configure its operating modes, specify the divider value, phase, and polarity of the clock, configure the SS and SPI_RDY control signal, and define the transfer length. The reserved bits are always read as 0. Figure 23-17 shows the CNTRL register, and Table 23-6 shows the register’s field descriptions. 0x1000_E0008 (CONREG) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read/write 19 18 17 16 R W Reset 0 0 0 0 0 0 CHIP SELECT 0 0 0 0 DRCTL 0 DATA RATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 BIT COUNT SSPOL SSCTL 0 0 0 0 PHA 0 POL 0 SMC 0 XCH MODE EN 0 0 0 0 0 0 0 0 0 Figure 23-17. CSPI Control Register Table 23-6. CONREG Register Field Descriptions Field 31–26 25–24 CHIP SELECT Reserved, all bits should read zero. CHIP SELECT. Select one of four external SPI Master/Slave Devices. In master mode, these two bits select the external slave devices by asserting the SSn outputs.Only the selected SSn signal will be active while the remaining 3 signals will be negated. Chip Select 00 SS0 will be asserted. 01 SS1 will be asserted. 10 SS2 will be asserted. 11 SS3 will be asserted. Reserved, all bits should read zero. Description 23–22 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-18 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) Table 23-6. CONREG Register Field Descriptions (continued) Field 21–20 DRCTL Description SPI Data Ready Control. This 2-bit field selects the utilization of the SPI_RDY in master mode. CSPI will check this fields before it start a SPI burst. 00 Don’t Care SPI_RDY 01 Burst will be triggered by failing edge of SPI_RDY. 10 Burst will be triggered by low level of SPI_RDY. 11 RSV. Reserved, all bits should read zero. SPI Data Rate Control. This three-bit field selects the baud rate of the SCLK based on a division of the ipg_clk. These bits allow CSPI to synchronize with different external SPI devices. The max frequency is one quarter of ipg_clk. The divide ratio is determined according to the following table using the equation: 2(n+2). SPI Data Rate Control (Master Mode only) 000 Divide by 4. 001 Divide by 8. 010 Divide by 16. 011 Divide by 32. 100 Divide by 64. 101 Divide by 128. 110 Divide by 256. 111 Divide by 512. Reserved, all bits should read zero. This field selects the length of a word to be transferred. A maximum of 32 bits can be transferred in a single SPI transfer. Multiple transfers may be chained together to form unlimited length messages using the SSCTL bit to keep the SS asserted between transfers. In master mode, BITCOUNT controls the number of bits per serial transfer. The transmit FIFO transfers a 32-bit data word to the shift register, however only the n least-significant (n=BIT COUNT + 1) are shifted out. The remaining bits are ignored. In slave mode, provided SSCTL= 0, this field controls the number of bits (BIT COUNT + 1) received in each data word. After BITCOUNT + 1 bits have been shifted into the shift register, the contents are transferred to the receive FIFO regardless of the state of the SS input. When SSCTL bit is 1, data transfer to/from the FIFO are controlled by the SS input and this field is ignored. SPI Data Rate Control (Master Mode only) 00000 Least 1 bit of a word to be transferred. 00001 Least 2 bits of a word to be transferred. ..... 01111 Least 16 bits of a word to be transferred. 10000 Least 17 bits of a word to be transferred. ..... 11110 Least 31 bits of a word to be transferred. 11111 All 32 bits of a word to be transferred. SPI SS Polarity Select. In both Master and Slave mode, this bit selects the polarity of the SS signal. 0 Active low 1 Active high 19 18–16 DATA RATE 15-13 12–8 BIT COUNT 7 SSPOL MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-19 Configurable Serial Peripheral Interface (CSPI) Table 23-6. CONREG Register Field Descriptions (continued) Field 6 SSCTL Description In master mode, this bit selects the output wave form for the SS signal. 0 SS remains asserted between SPI bursts. 1 Negate SS between SPI bursts. In slave mode, this bit controls the timing of data transfer from the shift register to the receive FIFO. 0 RXFIFO advanced by BIT COUNT. 1 RXFIFO advanced by SS edge. (SSPOL = 0: rising edge; SSPOL = 1: falling edge) SPI Clock/Data Phase Control. This bit controls the clock/data phase relationship. 0 Phase 0 operation. 1 Phase 1 operation. SPI Clock Polarity Control. This bit controls the polarity of the SCLK signal. 0 Active high polarity (0 = Idle) 1 Active low polarity (1 = Idle) Start Mode Control. This bit is used in master mode only and it controls how CSPI start a SPI burst. 0 XCH bit controls when a SPI burst can start. Write a 1 to XCH bit will start a SPI burst or multiple bursts. (controlled by SSCTL) 1 Immediately start a SPI burst when data is written in TXFIFO. SPI Exchange Bit. If the SMC bit is cleared, writing a 1 to this bit starts one SPI bursts/multiple SPI bursts according to SSCTL bit. This bit remains set while either the exchange is in progress, or the CSPI is waiting for active input if SPIRDY is enabled through DRCTL. This bit is cleared automatically when all data in the TXFIFO and Shift register have been shifted out. In Slave mode, this bit is ignored. 0 Idle 1 Initiates exchange (write) or busy (read) SPI Function Mode Select. This bit selects the operating mode of the CSPI. 0 Slave Mode 1 Master Mode SPI Module Enable Control. This bit enables the CSPI. This bit must be asserted before writing to other registers or initiating an exchange. Writing zero to this bit disables the module and resets the internal logic with the exception of the CONREG. The module’s internal clocks are gated off whenever the module is disabled. 0 CSPI is disabled. 1 CSPI is enabled. 5 PHA 4 POL 3 SMC 2 XCH 1 MODE 0 EN 23.5.3.4 Interrupt Control Register (INTREG) The 32-bit Interrupt Control Register (INTREG) enables the generation of interrupts to the MCU. The reserved bits cannot be written and always read as 0. If CSPI is disabled, this register reads zero. Figure 23-18 shows the CNTRL register, and Table 23-7 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-20 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) 0x1000_E000C (INTREG) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 TCEN BOEN ROEN RFEN RHEN RREN TFEN THEN TEEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-18. Interrupt Control Register Diagram Table 23-7. INTREG Register Field Descriptions Field 31–9 8 TCEN 7 BOEN Reserved, all bits should read zero. Transfer Completed Interrupt enable. This bit enables the Transfer Completed Interrupt. 0 Disable 1 Enable Bit Counter Overflow Interrupt enable. This bit enables the Bit Counter overflow Interrupt (More than 32 bits are received in a word). 0 Disable 1 Enable RXFIFO Overflow Interrupt enable. The bit enables the RXFIFO Overflow Interrupt. 0 Disable 1 Enable RXFIFO Full Interrupt enable. The bit enables the RXFIFO Full Interrupt. 0 Disable 1 Enable RXFIFO Half Full Interrupt enable. The bit enables the RXFIFO Half Full Interrupt. 0 Disable 1 Enable RXFIFO Ready Interrupt enable. The bit enables the RXFIFO Ready Interrupt. 0 Disable 1 Enable TXFIFO Full Interrupt enable. The bit enables the TXFIFO Full Interrupt. 0 Disable 1 Enable Description 6 ROEN 5 RFEN 4 RHEN 3 RREN 2 TFEN MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-21 Configurable Serial Peripheral Interface (CSPI) Table 23-7. INTREG Register Field Descriptions (continued) Field 1 THEN 0 TEEN Description TXFIFO Half Empty Interrupt enable. The bit enables the TXFIFO Half Empty Interrupt. 0 Disable 1 Enable TXFIFO Empty Interrupt enable. The bit enables the TXFIFO Empty Interrupt. 0 Disable 1 Enable 23.5.3.5 DMA Control Register (DMAREG) The DMA Control Register (DMAREG) provides the user a way to use the CSPI in DMA. Direct Memory Access (DMA) allows transfer of data between device and memory. Peripherals such as the CSPI supporting DMA use DMA request and acknowledge signals. The CSPI sends out DMA requests when the appropriate FIFO conditions are matched. The reserved bits cannot be written to and are always read as 0. If the CSPI is disabled, this register is also read as 0. Figure 23-19 shows the CNTRL register, and Table 23-8 shows the register’s field descriptions. 0x1000_E0010 (DMAREG) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 RF DEN 0 RH DEN 0 0 0 TH DEN 0 TE DEN 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-19. DMA Control Register Diagram Table 23-8. DMAREG Register Field Descriptions Field 31–6 5 RFDEN 4 RHDEN 3–2 Reserved, all bits should read zero. RXFIFO Full DMA Request Enable. This bit enables/disables the RXFIFO Full DMA Request. 0 Disable 1 Enable RXFIFO Half Full DMA Request Enable. This bit enables/disables the RXFIFO Half Full DMA Request. 0 Disable 1 Enable Reserved, should be cleared. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-22 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) Table 23-8. DMAREG Register Field Descriptions (continued) Field 1 THDEN Description TXFIFO Half Empty DMA Request Enable. This bit enables/disables the TXFIFO Half Empty DMA Request. 0 Disable 1 Enable TXFIFO Empty DMA Request Enable. This bit enables/disables the TXFIFO Empty DMA Request. 0 Disable 1 Enable 0 TEDEN 23.5.3.6 Status Register (STATREG) The CSPI Status Register (STATREG) reflects the status of the CSPI module operating condition. The reserved bits cannot be written and always read as 0. If the CSPI is disabled, this register reads 0x0000_0003. Figure 23-20 shows the CNTRL register, and Table 23-9 shows the register’s field descriptions. 0x1000_E0014 (STATREG) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 TC w1c BO w1c 0 RO RF RH RR TF TH TE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Figure 23-20. Status Register Diagram Table 23-9. STATREG Register Field Descriptions Field 31–9 8 TC Reserved, should be cleared. Transfer Completed. When set, this bit indicates that all the data in TXFIFO has been loaded in the Shift register, and the Shift register has shifted out all the bits. Writing 1 to this bit clears it. 0 Busy 1 Transfer Completed Bit Counter Overflow. When set, this bit indicates that Bit Counter is overflows while the Configurable Serial Peripheral Interface is in slave mode (MODE = 0) with SSCTL = 1. Writing 1 to this bit clears it. 0 Bit Counter is not overflowed. 1 Bit Counter is overflowed. Description 7 BO MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-23 Configurable Serial Peripheral Interface (CSPI) Table 23-9. STATREG Register Field Descriptions (continued) Field 6 RO 5 RF 4 RH 3 RR 2 TF 1 TH 0 TE Description RXFIFO Overflow. When set, this bit indicates that RXFIFO has overflowed. 0 RXFIFO is available. 1 RXFIFO has overflowed. RXFIFO Full. This bit is set when the RXFIFO is full (8 words). 0 Not Full 1 Full RXFIFO Half Full. This bit is set if the RXFIFO is half full (≥ 4 words in RXFIFO). 0 Less than 4 words are stored in RXFIFO. 1 Four or more words are available in RXFIFO. RXFIFO Ready. This bit is set any time there is one or more words stored in RXFIFO (≥ 1 words). 0 No valid data in RXFIFO 1 More than 1 word in RXFIFO TXFIFO Full. This bit is set when if the TXFIFO is full (8 words). 0 TXFIFO is not Full. 1 TXFIFO is Full. TXFIFO Half empty. This bit is set if the TXFIFO is more than half empty (≤ 4 words in TXFIFO). 0 TXFIFO holds more than 4 words. 1 TXFIFO holds 4 or fewer words. TXFIFO Empty. This bit is set if the TXFIFO is empty. 0 TXFIFO contains one or more words. 1 TXFIFO is empty. 23.5.3.7 Sample Period Control Register (PERIODREG) The Sample Period Control Register (PERIODREG) provides the user a way to insert delays (wait states) between consecutive SPI transfers. Control bits in this register select the clock source for the sample period counter and the delay count indicating the number of wait states to be inserted between data transfers. Delay counts are only applicable when the CSPI module is operating in master mode. Figure 23-21 shows the CNTRL register, and Table 23-10 shows the register’s field descriptions. 0x1000_E0018 (PERIODREG) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CSRC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE PERIOD Figure 23-21. Sample Period Control Register Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-24 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) Table 23-10. PERIODREG Register Field Descriptions Field 31–16 15 CSRC 14–0 SAMPLE PERIOD Reserved, all bits should read zero. Clock Source Control. This bit selects the clock source for the sample period counter. 0 SPI Clock (SCLK) 1 CKIL (32.768 KHz) Sample Period Control. These bits control the number of wait states to be inserted in data transfers. During the idle clocks, the state of the SS output will operate according to the SSCTL control field in CONREG. 0x0000 0 wait states inserted 0x0001 1 wait state inserted ...... ...... 0x7FFE 32766 wait states inserted 0x7FFF 32767 wait states inserted Description 23.5.3.8 Test Control Register (TESTREG) The Test Control Register (TESTREG) provides the user a mechanism to internally connect the receive and transmit devices of the CSPI module, display the status of the state machine, monitor the contents of the receive and transmit FIFO, and debug the CSPI. Figure 23-22 shows the CNTRL register, and Table 23-11 shows the register’s field descriptions. 0x1000_E01C0 (TESTREG) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SWAP LBC W Reset 0 0 0 0 SMSTATUS RXCNT TXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23-22. Test Control Register Diagram Table 23-11. TESTREG Register Field Descriptions Field 31–16 15 SWAP Reserved, All bits should be read as zero. Data Swap. This bit is used to swap data as it is read from the RXFIFO. When this bit is set, data read from RXFIFO is swapped. RXDATA[31:0] is swapped as follows: {RXDATA[7:0],RXDATA[15:8], RXDATA[23:16],RXDATA[31:24]} 0 Data read from RXFIFO is unchanged. 1 Data read from RXFIFO is swapped. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-25 Configurable Serial Peripheral Interface (CSPI) Table 23-11. TESTREG Register Field Descriptions (continued) Field 14 LBC Description Loopback Control. This bit is used in Master mode only. When this bit is set, the CSPI module connects the transmitter and receiver sections internally, and the data shifted out from the most-significant bit of the Shift register is looped back into the least-significant bit of the Shift register. In this way, a self-test of the complete transmit/receive path can be made. The output pins are not affected, and the input pins are ignored. 0 Not connected. 1 Internally connected. Reserved, all bits should read zero. State Machine Status. These bits indicate status of the state machine for test purpose. RXFIFO Counter. These bits indicate the number of words in RXFIFO. 0000 0 word in RXFIFO 0001 1 word in RXFIFO ...... ...... 0111 7 words in RXFIFO 1000 8 words in RXFIFO TXFIFO Counter. These bits indicate the number of words in TXFIFO. 0000 0 word in TXFIFO 0001 1 word in TXFIFO ...... ...... 0111 7 words in TXFIFO 1000 8 words in TXFIFO 13–12 11–8 SMSTATUS 7–4 RXCNT 3–0 TXCNT 23.6 Timing Diagrams Figure 23-23 and Figure 23-24 depict the master mode and slave mode timing diagrams of the CSPI and Table 23-12 lists the timing parameters. The values shown in timing diagrams were tested using a worst case core voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad voltage of 1.65 V. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-26 Freescale Semiconductor Configurable Serial Peripheral Interface (CSPI) t7 SSn (output) t8 t5 t9 t6 CSPI1_RDY (input) SCLK (output) MOSI t12 MISO t13 t1 t2 t3 t10 t11 t4 t4 Figure 23-23. CSPI Master Mode Timing Diagram t7’ SSn (input) t6’ t1’ SCLK (input) MISO t12 MOSI t13 t2’ t3’ t5’ t10 t11 t4 t4 t14 t14 Figure 23-24. CSPI Slave Mode Timing Diagram Table 23-12. CSPI Interface Timing Parameters ID Num t1 t2 t3 Parameter Description CSPI master SCLK cycle time CSPI master SCLK high time CSPI master SCLK low time Symbol tclko tclkoH tclkoL Minimum 45.12 22.65 22.47 Maximum — — Units ns ns ns MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 23-27 Configurable Serial Peripheral Interface (CSPI) Table 23-12. CSPI Interface Timing Parameters (continued) ID Num t1’ t2’ t3’ t4 t5 t5’ t6 t6’ t7 t7’ t8 t9 t10 Parameter Description CSPI slave SCLK cycle time CSPI slave SCLK high time CSPI slave SCLK low time CSPI SCLK transition time SSn output pulse width SSn input pulse width SSn output asserted to first SCLK edge (SS output setup time) SSn input asserted to first SCLK edge (SS input setup time) CSPI master: Last SCLK edge to SSn deasserted (SS output hold time) CSPI slave: Last SCLK edge to SSn deasserted (SS input hold time) CSPI master: CSPI1_RDY low to SSn asserted (CSPI1_RDY setup time) CSPI master: SSn deasserted to CSPI1_RDY low Output data setup time Symbol tclki tclkiH tclkiL tpr1 tWsso tWssi tSsso tSssi tHsso tHssi tSrdy tHrdy tSdatao Minimum 60.2 30.1 30.1 2.6 2Tsclk2 +T wait 3 Maximum — — — 8.5 — — — — — — 5Tper — — Units ns ns ns ns — — — — — ns — ns — Tper4 3Tsclk Tper 2Tsclk 30 2Tper 0 (tclkoL or tclkoH or tclkiL or tclkiH) Tipg5 tclkoL or tclkoH or tclkiL or tclkiH Tipg + 0.5 0 0 t11 t12 t13 t14 1 2 Output data hold time Input data setup time Input data hold time Pause between data word tHdatao tSdatai tHdatai tpause — — — — — ns ns ns The output SCLK transition time is tested with 25pF drive. Tsclk = CSPI clock period 3T wait = Wait time as per the Sample Period Control Register value. 4T per = CSPI reference baud rate clock period (PERCLK2) 5T ipg = CSPI main clock IPG_CLOCK period MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 23-28 Freescale Semiconductor Chapter 24 Inter-Integrated Circuit (I2C) The Inter-Integrated Circuit (I2C) module provides the functionality of a standard I2C slave and master. The I2C module is designed to be compatible with the standard Philips I2C bus protocol. The i.MX27 device contains two identical I2C modules. Figure 24-1 shows the I2C block diagram. IP Bus IRQ Registers Interface Address Decode Data MUX Address Data I2C Frequency Divider Register (IFDR) I2C Control Register (I2CR) I2C Status Register (I2SR) I2C Data I/O Register (I2DR) I2C Address Register (IADR) Clock Control Start, Stop, and Arbitration Control Input Sync In/Out Data Shift Register Address Compare SCL SDA Signals connected to Pads Figure 24-1. I2C Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-1 Inter-Integrated Circuit (I2C) 24.1 Overview The I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development. Figure 24-2 provides the connection diagram. +Vdd Rp SDA (Serial Data line) Pull-Up resistors Rp SCL (Serial Clock line) ipp_scl_out 1 ipp_sda_out1 ipp_scl_out2 ipp_sda_out2 ipp_scl_in1 ipp_sda_in1 ipp_scl_in2 ipp_sda_in2 Device1 Device2 Figure 24-2. Connection of Devices to I2C Bus The I2C operates up to 400 kbps, but it depends on the pad loading and timing. For pad requirement details, refer to Philips I2C Bus Specification, Version 2.1. The I2C system is a true multiple-master bus including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. 24.1.1 Features The I2C module has the following key features: • Compatibility with I2C bus standard • Multiple-master operation • Software-programmable for one of 64 different serial clock frequencies • Software-selectable acknowledge bit • Interrupt-driven, byte-by-byte data transfer • Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-2 Freescale Semiconductor Inter-Integrated Circuit (I2C) • • • • Start and stop signal generation/detection Repeated START signal generation Acknowledge bit generation/detection Bus-busy detection 24.2 External Signal Description Two pins are required for I2C: • I2C_SCL Bidirectional Clock Pin • I2C_SDA Bidirectional Data Pin For I2C compliance, all devices connected to the SCL and SDA signals must have open-drain or open-collector outputs. The logic AND function is exercised on both lines with external pull-up resistors. The module port signals going to the pad are tabulated in Table 24-2. Table 24-2. Signal Properties Name IPP_SCL_IN IPP_SCL_OUT IPP_SCL_OUT_EN IPP_SDA_IN IPP_SDA_OUT IPP_SDA_OUT_EN Port — — — — — — Function Serial Clock input Serial Clock output Serial Clock output enable Serial Data input Serial Data output Serial Data output enable Reset State 1 1 0 1 1 0 Pull-Up — Active — — Active — 24.2.1 Detailed External Signal Descriptions The following three signals are connected to the bidirectional driver for the SCL I/O Pad (through the IOMUX module): • IPP_SCL_IN—Serial Input Clock • IPP_SCL_OUT—Serial Output Clock • IPP_SCL_OUT_EN—Serial Output Clock Enable The pad needs to have open-drain connectivity. IPP_SCL_IN will be the input signal from the pad. IPP_SCL_OUT will be the output to the pad from the module. IPP_SCL_OUT_EN will act as the output enable. The following three signals are connected to the bidirectional driver for the SDA I/O Pad (through the IOMUX module): • IPP_SDA_IN—Serial Input Data • IPP_SDA_OUT—Serial Output Data • IPP_SDA_OUT _EN—Serial Output Data Enable MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-3 Inter-Integrated Circuit (I2C) The pad should have open-drain connectivity. IPP_SDA_IN will be the input signal from the pad. IPP_SCL_OUT will be the output to the pad from module. IPP_SDA_OUT_EN will act as the output enable. 24.3 Memory Map and Register Definition The I2C module contains five 16-bit registers. Section 24.3.3, “Register Descriptions” provides the detailed descriptions for all of the I2C registers. 24.3.1 I2C Memory Map Table 24-3. I2C Memory Map Table 24-3 shows the I2C memory map. Address 0x1001_2000 (IADR1) 0x1001_D000 (IADR2) 0x1001_2004 (IFDR1) 0x1001_D004 (IFDR2) 0x1001_2008 (I2CR1) 0x1001_D008 (I2CR2) 0x1001_200C (I2SR1) 0x1001_D008 (I2CR2) 0x1001_2010 (I2DR1) 0x1001_D010 (I2DR2) Register I2C Address Register I2C Frequency Divider Register I2C Control Register I2C Status Register I2C Data I/O Register Access R/W R/W R/W R/W R/W Reset Value 0x0000 0x0000 0x0000 0x0081 0x0000 Section/Page 24.3.3.1/24-6 24.3.3.2/24-6 24.3.3.3/24-7 24.3.3.4/24-9 24.3.3.5/24-10 NOTE There are registers at addresses 0x1001_02, 0x1001_06, 0x1001_a, 0x1001_0e, which are reserved for future additions. 24.3.2 Register Summary Figure 24-3 shows the key to the register fields, and Table 24-5 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 24-3. Key to Register Fields Table 24-5. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-4 Freescale Semiconductor Inter-Integrated Circuit (I2C) Table 24-5. Register Figure Conventions (continued) Convention Description Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 24-4 shows the I2C register summary. Table 24-4. I2C Register Summary Name 0x1001_2010 (I2DR1) 0x1001_D010 (I2DR2) 0x1001_2004 (IFDR1) 0x1001_D004 (IFDR2) 0x1001_2008 (I2CR1) 0x1001_D008 (I2CR2) 0x1001_200C (I2SR1) 0x1001_D00C (I2SR2) 0x1001_2010 (I2DR1) 0x1001_D010 (I2DR2) R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ADR 0 R W 0 0 0 0 0 0 0 0 0 0 IC R W 0 0 0 0 0 0 0 0 0 MST TXA IEN IIEN MTX A K RST A ICF IAA S IBB IAL 0 SR W 0 0 R W R W 0 0 0 0 0 0 0 0 IIF RXA K 0 0 0 0 0 0 0 0 DATA MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-5 Inter-Integrated Circuit (I2C) 24.3.3 Register Descriptions This section contains the detailed register descriptions for the I2C registers in address order. 24.3.3.1 I2C Address Register (IADR) Figure 24-6 shows the I2C Address Register; Table 24-5 provides its field descriptions. 0x1001_2000 (IADR1) 0x1001_D000 (IADR2) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 ADR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-6. I2C Address Register The IADR holds the address the I2C responds to when addressed as a slave. NOTE The slave address is not the address sent on the bus during the address transfer. This register is not reset by a software reset. Table 24-5. I2C Address Register Field Descriptions Field 15–8 7–1 ADR 0 Reserved Slave address. Contains the specific slave address to be used by the I2C module. Slave mode is the default I2C mode for an address match on the bus. Reserved Description 24.3.3.2 I2C Frequency Register (IFDR) The IFDR provides a programmable prescaler to configure the clock for bit-rate selection. The register does not get reset by software reset. Figure 24-7 shows the I2C Frequency Register; Table 24-6 provides its field descriptions. 0x1001_2004 (IFDR1) 0x1001_D004 (IFDR2) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 IC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-7. I2C Frequency Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-6 Freescale Semiconductor Inter-Integrated Circuit (I2C) Table 24-6. I2C Frequency Register Field Descriptions Field 15–6 5–0 IC Reserved I2C clock rate. Prescales the clock for bit-rate selection. Due to potentially slow SCL and SDA rise and fall times, bus signals are sampled at the prescaler frequency. The serial bit clock frequency is equal to IPG_CLK_PATREF divided by the divider shown in Table 24-7. Note: The IC can be changed anywhere in a program. I2C protocol supports bit rates up to 400 kbps. The IC bits need to be programmed in accordance with this constraint. Description Table 24-7. IFDR Register Field Values IC 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Divider 30 32 36 42 48 52 60 72 80 88 104 128 144 160 192 240 IC 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Divider 288 320 384 480 576 640 768 960 1152 1280 1536 1920 2304 2560 3072 3840 IC 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F Divider 22 24 26 28 32 36 40 44 48 56 64 72 80 96 112 128 IC 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Divider 160 192 224 256 320 384 448 512 640 768 896 1024 1280 1536 1792 2048 24.3.3.3 I2C Control Register (I2CR) The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern operation as a slave or a master. Figure 24-8 shows the I2C Control Register; Table 24-8 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-7 Inter-Integrated Circuit (I2C) 0x1001_2008 (I2CR1) 0x1001_D008 (I2CR2) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 IEN IIEN MSTA MTX TXAK 0 RSTA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24-8. I2C Control Register Table 24-8. I2C Control Register Field Descriptions Field 15–8 7 IEN Reserved I2C enable. Also controls the software reset of the entire I2C module. Resetting the bit generates an internal reset to the module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next start condition is detected. Master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the current master or the I2C module to lose arbitration. After which, bus operation returns to normal. 0 The module is disabled, but registers can still be accessed. 1 The I2C module is enabled. This bit must be set before any other I2CR bits have any effect. I2C interrupt enable. 0 I2C module interrupts are disabled, but the status flag I2SR[IIF] continues to be set when an interrupt condition occurs. 1 I2C module interrupts are enabled. An I2C interrupt occurs if I2SR[IIF] is also set. Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal. Note: Module clock should be on for writing to the MSTA bit. 0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode. 1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode. Transmit/receive mode select bit. Selects the direction of master and slave transfers. 0 Receive. When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2SR[SRW]). 1 Transmit. In master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. Transmit acknowledge enable. Specifies the value driven onto SDA during acknowledge cycles for both master and slave receivers. Note: Writing TXAK applies only when the I2C bus is a receiver. 0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. 1 No acknowledge signal response is sent (that is, the acknowledge bit = 1). Repeat start. Always reads as 0. Attempting a repeat start without bus mastership causes loss of arbitration. 0 No repeat start 1 Generates a repeated START condition Reserved Description 6 IIEN 5 MSTA 4 MTX 3 TXAK 2 RSATA 1–0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-8 Freescale Semiconductor Inter-Integrated Circuit (I2C) 24.3.3.4 I2C Status Register (I2SR) The I2SR contains bits that indicate transaction direction and status. Figure 24-9 shows the I2C Address Register; and Table 24-9 provides its field descriptions. 0x1001_200C (I2SR1) 0x1001_D00C (I2SR2) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 ICF IAAS IBB IAL 0 SRW IIF RXA K 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 1 Figure 24-9. I C Status Register Table 24-9. I2C Status Register Field Descriptions Field 15–8 7 ICF 6 IAAS Reserved Data transferring bit. While one byte of data is transferred, ICF is cleared. 0 Transfer is in progress. 1 Transfer is complete, and set by the falling edge of the ninth clock of a byte transfer. I2C addressed as a slave bit. The CPU is interrupted if the interrupt enable (I2CR[IIEN]) is set. The CPU must check the slave read/write bit (SRW) and set its TX/RX mode accordingly. Writing to I2CR clears this bit. 0 Not addressed 1 Addressed as a slave. Set when its own address (IADR) matches the calling address. I2C bus busy bit. Indicates the status of the bus. 0 Bus is idle. If a STOP signal is detected, IBB is cleared. 1 Bus is busy. When START is detected, IBB is set. Arbitration lost. Set by hardware in the following circumstances (IAL must be cleared by software by writing a “0” to it): • SDA input sampled low when the master drives high during an address or data-transmit cycle. • SDA input sampled low when the master drives high during the acknowledge bit of a data-receive cycle. For the above two cases, the bit is set at the falling edge of 9th SCL clock during the ACK cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. Note: Software cannot set the bit. 0 No arbitration is lost. 1 Arbitration is lost. Reserved Slave read/write. When the I2C is addressed as a slave, IAAS is set, and the slave read/write bit (SRW) indicates the value of the R/W command bit of the calling address sent from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated, and the I2C module is a slave and has an address match. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave Description 5 IBB 4 IAL 3 2 SRW MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-9 Inter-Integrated Circuit (I2C) Table 24-9. I2C Status Register Field Descriptions (continued) Field 1 IIF Description I2C interrupt. Must be cleared by the software by writing a “0” to it in the interrupt routine. Note: The software cannot set the bit. 0 No I2C interrupt is pending. 1 An interrupt is pending. This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: • One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). • An address is received that matches its own specific address in slave-receive mode. • Arbitration is lost. Received acknowledge. This is the value received of the SDA input for the acknowledge bit during a bus cycle. 0 An “acknowledge” signal was received after the completion of an 8-bit data transmission on the bus. 1 A “No acknowledge” signal was detected at the ninth clock. 0 RXAK 24.3.3.5 I2C Data Register (I2DR) In master-receive mode, reading the data register (I2DR) allows a read to occur and initiates the next byte to be received. In slave mode, the same function is available after it is addressed. Figure 24-10 shows the I2C Data Register; Table 24-10 provides its field descriptions. 0x1001_2010 (I2DR1) 0x1001_D010 (I2DR2) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 Figure 24-10. I C Data Register Table 24-10. I2C Data Register Field Descriptions Field 15–8 7–0 DATA Reserved Data Byte. Holds the last data byte received or the next data byte to be transferred. Software writes the next data byte to be transmitted or reads the data byte received. Description NOTE The core-written value in I2DR cannot be read back by the core: Only data written by the I2C bus side can be read. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-10 Freescale Semiconductor Inter-Integrated Circuit (I2C) 24.4 24.4.1 Functional Description I2C System Configuration Out of a reset, the I2C module defaults to slave receive operations. Thus, when not operating as a master or responding to a slave transmit address, the I2C module will default to the slave receiver state. For exceptions, see Section 24.5.1, “Initialization Sequence.” NOTE The I C module is designed to be compatible with the Philips I2C bus protocol. For information on system configuration, protocol, and restrictions, refer to the I2C Bus Specification, Version 2.1. The I2C module supports Standard and Fast modes only. 2 24.4.2 I2C Protocol The I2C communication protocol consists of six components, as follows: • START • Data Source/Recipient • Data Direction • Slave Acknowledge • Data Acknowledge • STOP See Figure 24-11 for the I2C standard communication protocol, as defined in the following sections. SCL MSB 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 LSB 8 9 SDA A AD7 AD6AD5 AD4 AD3 AD2 AD1R/W Calling Address B R/W ACK Bit C D XXX D7 D6 D5 D4 D3 D2 D1 D0 Data Byte No STOP ACK Signal Bit F START Signal E Figure 24-11. I2C Standard Communication Protocol 24.4.2.1 START Signal When no other device is a bus master (both SCL and SDA lines are at logic high), a device can initiate communication by sending a START signal (see A in Figure 24-11). A START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-11 Inter-Integrated Circuit (I2C) 24.4.2.2 Slave Address Transmission The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave data transfer direction. Each slave must have a unique address. An I2C master must not transmit an address that is the same as its slave address; it cannot be master and slave at the same time. The slave whose address matches that sent by the master pulls SDA low at the ninth clock (D) to return an acknowledge bit. 24.4.2.3 Data Transfer When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master. Data can be changed only while SCL is low and must be held stable while SCL is high, as shown in Figure 24-11. SCL is pulsed once for each data bit, with the mishap being sent first. The receiving device must acknowledge each byte by pulling SDA low at the ninth clock; therefore, a data byte transfer takes nine clock pulses. If it does not acknowledge the master, the slave receiver must leave SDA high. The master can then generate a STOP signal to abort the data transfer or generate a START signal (a repeated start, as shown in Figure 24-12) to start a new calling sequence. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave. The slave releases SDA for the master to generate a STOP or START signal. 24.4.2.4 STOP Signal The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is at logical high (F). NOTE A master can generate a STOP even if the slave has made an acknowledgment; at which point, the slave must release the bus. 24.4.2.5 Repeat Start Instead of signalling a STOP, the master can repeat the START signal, followed by a calling command (see A in Figure 24-12). A repeated START occurs when a START signal is generated without first generating a STOP signal to end the communication. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-12 Freescale Semiconductor Inter-Integrated Circuit (I2C) MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 LSB 8 9 SDA AD7 AD6AD5 AD4 AD3 AD2 AD1R/W Calling Address XX AD7 AD6 AD5 AD4AD3 AD2 AD1R/W New Calling Address Stop START Signal R/W ACK Repeated Bit START Signal A R/W No STOP ACK Signal Bit Figure 24-12. Repeated START 24.4.3 Arbitration Procedure If multiple devices simultaneously request the bus, the bus clock is determined by a synchronization procedure in which the low period equals the longest clock-low period among the devices, and the high period equals the shortest. A data arbitration procedure determines the relative priority of competing devices. A device loses arbitration if it sends logic high while another sends logic low; it immediately switches to slave-receive mode and stops driving SDA. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets the arbitration lost bit in the I2C Status register (I2SR[IAL] to indicate loss of arbitration. 24.4.4 Clock Synchronization Because wire-AND logic is used, a high-to-low transition on SCL affects devices connected to the bus. Devices start counting their low period when the master drives SCL low. When a device clock goes low, it holds SCL low until the clock high state is reached. However, the low-to-high change in this device clock may not change the state of SCL if another device clock is still in its low period. Therefore, the device with the longest low period holds the synchronized clock SCL low. Devices with shorter low periods enter a high wait state during this time (see Figure 24-13). When all devices involved have counted off their low period, the synchronized clock SCL is released and pulled high. There is then no difference between device clocks and the state of SCL, so all of the devices start counting their high periods. The first device to complete its high period pulls SCL low again. Wait SCL1 Start counting high period SCL2 SCL Internal Counter Reset Figure 24-13. Synchronized Clock SCL MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-13 Inter-Integrated Circuit (I2C) 24.4.5 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices can hold SCL low after completing one byte transfer (9 bits). In such a case, the clock mechanism halts the bus clock and forces the master clock into a wait state until the slave releases SCL. 24.4.6 Clock Stretching Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave SCL low period is longer than the master SCL low period, the resulting SCL bus signal low period is stretched. 24.4.7 IP Bus Accesses I2C is a 16-bit IP module. Only halfword accesses should be performed to the module. 24.4.8 Generation of Transfer Error on IP Bus If an address is received on the IP slave bus interface that is not implemented, an access error is generated (IPS_XFR_ERR is asserted). The input pin resp_sel provides the configuration capability to generate this response. The resp_sel pin must be asserted to enable the IPS_XFR_ERR signal. 24.5 24.5.1 Initialization/Application Information Initialization Sequence Before the interface can transfer serial data, registers must be initialized, as follows: 1. Set the data sampling rate (IFDR[IC] to obtain SCL frequency from the system bus clock. See Section 24.3.3.2, “I2C Frequency Register (IFDR).” 2. Update the address in the (IADR) to define its slave address (address can range from 0 to 0x7f). 3. Set the I2C enable bit (I2CR[IEN]) to enable the I2C bus interface system. 4. Modify the bits in the I2CR to select master/slave mode, transmit/receive mode, and interrupt-enable or not. 24.5.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. On a multiple-master bus system, the busy bus (I2SR[IBB]) must be tested to determine whether the serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the slave address) can be sent. The data written to the data register comprises the address of the desired slave and the LSB indicates the transfer direction. The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period, it may be MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-14 Freescale Semiconductor Inter-Integrated Circuit (I2C) necessary to wait until the I2C is busy after writing the calling address to the data register (I2DR) before proceeding to load data into the data register (I2DR). 24.5.3 Post-Transfer Software Response Sending or receiving a byte sets the data transferring bit (I2SR[ICF]), which indicates one byte communication is finished. Upon completion, the interrupt status (I2SR[IIF]) is also set. An external interrupt is generated if the interrupt enable (I2CR[IIEN]) is set. The software must first clear the interrupt status (I2SR[IIF]) in the interrupt routine. (See the flowchart in Figure 24-14.) The data transferring bit (I2SR[ICF]) is cleared either by reading from I2DR in receive mode or by writing to this register in transmit mode. The software can service the I2C I/O in the main program by monitoring the interrupt status (I2SR[IIF]) if the interrupt enable is de-asserted. In this case, the interrupt status should be polled of the data transferring bit (I2SR[ICF]) because the operation is different when arbitration is lost. When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent. If master receive mode is required, then (I2DR[R/W], I2CR[MTX] should be toggled. During slave-mode address cycles (I2SR[IAAS] = 1), the slave read/write bit I2SR[SRW] is read to determine the direction of the next transfer. The transmit/receive bit (I2CR[MTX]) should also be programmed accordingly. For slave-mode data cycles (IAAS = 0), SRW is invalid. MTX should be read to determine the current transfer direction. 24.5.4 Generation of STOP A data transfer ends when the master signals a STOP, which can occur after all data is sent. For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting the transmit acknowledge bit (I2CR[TXAK]) before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated. 24.5.5 Generation of Repeated START After the data transfer, if the master still wants the bus, it can signal another START followed by another slave address without signalling a STOP. 24.5.6 Slave Mode In the slave interrupt service routine (see Figure 24-14), the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS automatically. The only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode releases SCL, allowing the master to send data. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-15 Inter-Integrated Circuit (I2C) In the slave transmitter routine, the receive acknowledge bit (I2SR[RXAK]) must be tested before sending the next byte of data. Setting RXAK means an end-of-data signal from the master receiver, after which the software must switch it from transmitter to receiver mode. Reading the data register (I2DR) then releases SCL so that the master can generate a STOP signal. 24.5.7 Arbitration Lost If several devices try to engage the bus at the same time, one becomes master. Hardware immediately switches devices that lose arbitration to slave receive mode. Data output to SDA stops, but SCL is still generated until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge of the ninth clock of this transfer if the arbitration is lost (I2SR[IAL] = 1), and the slave mode is selected (I2CR[MSTA] = 0). See the flowchart in Figure 24-14. If a device that is not a master tries to transmit or do a START, hardware inhibits the transmission, clears MSTA without signalling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, the slave service routine should first test IAL, and the software should clear it if it is set. For Multi-master mode, when an I2C module is enabled when the bus is busy and asserts START, the IAL bit gets set only for SDA=0, SCL=0/1, SDA=1, and SCL=0, but not for SDA=1 and SCA=1, which is the same as bus idle state. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-16 Freescale Semiconductor Inter-Integrated Circuit (I2C) Clear IIF Y Master Mode? N TX TX/RX ? RX Y Arbitration Lost? N Last Byte Transmitted ? N Y Clear IAL RXAK= 0 ? Y N Last Byte to be Read ? N Y N IAAS=1 ? Y Y IAAS=1 ? N Data Cycle Tx/RX ? TX ACK from Receiver ? N RX Address Cycle (Read) Y Y End of ADDR Cycle (Master RX) ? N Write Next Byte to I2DR Y 2nd Last Byte to be Read? N Generate STOP Signal SRW=1 ? N (WRITE) Y Set TXAK =1 Set TX Mode Write Data to I2DR Tx Next Byte Read Data from I2DR and Store Switch to RX Mode Set RX Mode Switch to RX Mode Dummy Read from I2DR Generate STOP Signal Read Data from I2DR And Store Dummy Read from I2DR Dummy Read from I2DR RTE Figure 24-14. Flowchart of Typical I2C Interrupt Routine MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 24-17 Inter-Integrated Circuit (I2C) NOTE For a repeated start-only, the stop generation stage will not occur in master mode. A loop will repeat itself without stopping for the next start. 24.5.8 Timing Section Figure 24-15 provides an illustration of the timing for the serial data line (SDA) and serial clock line (SCL) devices on the I2C bus. SDA 5 SCL 4 1 3 2 Figure 24-15. Definition of Timing for Devices on I2C Bus Table 24-11 provides a list of bus timing parameters. Table 24-11. I2C Bus Timing Parameters Reference Number 1 2 3 4 5 Parameter Hold time (repeated) START condition Setup time for STOP condition Data hold time HIGH of the SCL Period LOW period of the SCL Clock Maximum (w.r.t ipg_clk_patref) — — (0.27) * Divider — — Minimum (w.r.t ipg_clk_patref) 4 4 — (0.4) * Divider (Master mode) (0.4) * Divider (Master mode) NOTE See Table 24-7 for details for Divider values. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 24-18 Freescale Semiconductor Chapter 25 Keypad Port (KPP) The Keypad Port (KPP) is a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose input/output (I/O). Figure 25-1 shows the KPP block diagram. TO INTERRUPT CONTROLLER KPSR KDDR (5:8) KPCR (5:8) Glitch Suppression Logic DATA DIRECTION (KDDR) AND OPEN DRAIN ENABLE (KPCR) CONTROLS KPDR (5:8) 32 KHz KPCR(7:0) KPDR(7:0) KEYPAD MATRIX UP TO 8x8 ROW ENABLE CONTROLS (KPCR) PAD DRIVERS KDDR(7:0) PULL-UP/DATA DIRECTION CONTROLS (KDDR) Figure 25-1. KPP Peripheral Block Diagram 25.1 Overview The KPP is designed to interface with the keypad matrix with 2-point contact or 3-point contact keys. The KPP is designed to simplify the software task of scanning a keypad matrix. With appropriate software MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-1 Keypad Port (KPP) support, the KPP is capable of detecting, debouncing, and decoding one or multiple keys pressed simultaneously on the keypad. 25.1.1 Features The KPP includes these distinctive features: • Supports up to an 8 x 8 external key pad matrix • Port pins can be used as general purpose I/O • Open drain design • Glitch suppression circuit design • Multiple-key detection • Long key-press detection • Standby key-press detection • Synchronizer chain clear • Supports a 2-point and 3-point contact key matrix 25.1.2 Modes of Operation This module supports the following modes of operation: • Run Mode—This is the normal functional mode in which the KPP can detect any key press event. • Low Power Modes—The keypad can detect any key press even in low power modes (when there is no MCU clock). 25.2 25.2.1 External Signal Description Overview There are 16 pins dedicated to the KPP. Keypads of any configuration up to eight rows and eight columns are supported through the software configuration of the peripheral pins. Any pins not used for the keypad are available as general purpose I/O. The registers are configured such that the pins can be treated as an I/O port up to 16 bits wide. 25.2.1.1 Input Pins Any of the 16 pins associated with the KPP can be configured as inputs by writing a “0” to the appropriate bits in the KDDR. Additionally, the least significant 8 bits (ROW inputs) corresponding to KDDR7:0 have internal pull-ups, which are enabled when the pin is used as an input. 25.2.1.2 Output Pins Any of these 16 KPP pins can be configured as outputs by writing the appropriate bits in the KDDR to a “1”. Additionally, the 8 most significant bits (15–8) can be designated as open drain outputs by writing a MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-2 Freescale Semiconductor Keypad Port (KPP) “1” to the appropriate bits in the KPCR. The lower 8 bits (7–0) are always in “totem pole” style, driven when configured as outputs. See Table 25-1. Table 25-1. Keypad Port Column Modes KDDR (15:8) 0 1 1 KPCR (15:8) x 0 1 Pin Function Input Totem-Pole Output Open-Drain Output NOTE Totem pole capability should be provided for column pins. Totem pole configuration helps for a faster discharge of keypad capacitance when all columns need to be quickly brought to a “1” during the scan routine. With this configuration, a time delay between the scanning of two subsequent columns is reduced. 25.3 Memory Map and Register Definition The KPP module contains four registers. Section 25.3.3, “Register Descriptions” provides detailed descriptions of the KPP registers. 25.3.1 KPP Memory Map Table 25-2. KPP Memory Map Address Use Keypad Control Register Keypad Status Register Keypad Data Direction Register Keypad Data Register Access R/W R/W R/W R/W Reset Value 0x0000 0x0000 0x0000 0x— — — — Section/Page 25.3.3.1/25-5 25.3.3.2/25-5 25.3.3.3/25-7 25.3.3.4/25-8 Table 25-2 shows the KPP memory map. 0x1000_8000 (KPCR) 0x1000_8002 (KPSR) 0x1000_8004 (KDDR) 0x1000_8006 (KPDR) 25.3.2 Register Summary Figure 25-2 shows the key to the register fields, and Table 25-3 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 25-2. Key to Register Fields MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-3 Keypad Port (KPP) Table 25-3. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 25-4 shows the KPP register summary. Table 25-4. KPP Register Summary Name 0x1000_8000 (KPCR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R KCO KCO KCO KCO KCO KCO KCO KCO KRE KRE KRE KRE KRE KRE KRE KRE 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 W7 R 0 0 0 0 0 KPP _EN KRI E KDI E 0 0 0 0 0 0 KPK KPK R D w1c w1c 0x1000_8002 (KPSR) W KRS KDS S C 0x1000_8004 (KDDR) 0x1000_8006 (KPDR) R KCD KCD KCD KCD KCD KCD KCD KCD KRD KRD KRD KRD KRD KRD KRD KRD D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 W D7 R KCD KCD KCD KCD KCD KCD KCD KCD KRD KRD KRD KRD KRD KRD KRD KRD 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 W7 25.3.3 Register Descriptions This section consists of register descriptions. Each register is listed in the order of its address. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-4 Freescale Semiconductor Keypad Port (KPP) 25.3.3.1 Keypad Control Register (KPCR) The Keypad Control Register determines which of the eight possible column strobes are to be open drain when configured as outputs, and which of the eight row sense lines are considered in generating an interrupt to the core. It is up to the programmer to ensure that pins being used for functions other than the keypad are properly disabled. The KPCR register is byte- or halfword–addressable. Figure 25-3 shows the valid bits in the KPCR register, and Table 25-5 provides its field descriptions. 0x1000_8000 (KPCR) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R KCO7 KCO6 KCO5 KCO4 KCO3 KCO2 KCO1 KCO0 KRE7 KRE6 KRE5 KRE4 KRE3 KRE2 KRE1 KRE0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25-3. KPCR Register Table 25-5. Keypad Control Register Field Descriptions Field 15–8 KCO Description Keypad Column Strobe Open-Drain Enable. Setting a column open-drain enable bit (KCO7–KCO0) disables the pull-up driver on that pin. Clearing the bit allows the pin to drive to the high state. This bit has no effect when the pin is configured as an input. 0 Column strobe output is totem pole drive. 1 Column strobe output is open drain. Note: Configuration of external port control logic (for example, GPIO) should be done properly so that the KPP module controls an open-drain enable of the pin. Keypad Row Enable. Setting a row enable control bit in this register enables the corresponding row line to participate in interrupt generation. Likewise, clearing a bit disables that row from being used to generate an interrupt. This register is cleared by a reset, disabling all rows. The row-enable logic is independent of the programmed direction of the pin. Writing a “0” to the data register of the pins configured as outputs will cause a keypad interrupt to be generated if the row enable associated with that bit is set. 0 Row is not included in the keypad key press detect. 1 Row is included in the keypad key press detect. 7–0 KCO 25.3.3.2 Keypad Status Register (KPSR) The Keypad Status Register reflects the state of the key press detect circuit. The KPSR register is byte- or halfword–addressable. Figure 25-4 shows the KPSR register, and Table 25-6 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-5 Keypad Port (KPP) 0x1000_8002 (KPSR) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 0 0 KPP_ KRIE KDIE EN 0 0 0 0 0 0 0 0 0 KPKR KPKD w1c 0 w1c 0 KRSS KDSC 0 0 0 0 0 0 0 0 0 0 0 Figure 25-4. KPSR Register Table 25-6. Keypad Status Register Field Descriptions Field 15–11 10 KPP_EN Reserved Keypad Clock Gating Enable. The signal generated using this bit can be used by the ‘chip clock-control module’ to gate the module’s high frequency clock for register access and synchronization. Output of this bit is not used anywhere inside KPP module. 0 Disable high frequency clock to keypad module 1 Enable high frequency clock to keypad module Keypad Release Interrupt Enable. The software should ensure that the interrupt for a Key Release event is masked until it has entered the key pressed state, and vice versa, unless this activity is desired (as might be the case when a repeated interrupt is to be generated). The synchronizer chains are capable of being initialized to detect repeated key presses or releases. If they are not initialized when the corresponding event flag is cleared, false interrupts may be generated for depress (or release) events shorter than the length of the corresponding chain. 0 No interrupt request is generated when KPKR is set. 1 An interrupt request is generated when KPKR is set. Keypad Key Depress Interrupt Enable. Software should ensure that the interrupt for a Key Release event is masked until it has entered the key pressed state, and vice-versa, unless this activity is desired (as might be the case when a repeated interrupt is to be generated). The synchronizer chains are capable of being initialized to detect repeated key presses or releases. If they are not initialized when the corresponding event flag is cleared, false interrupts may be generated for depress (or release) events shorter than the length of the corresponding chain. 0 No interrupt request is generated when KPKD is set. 1 An interrupt request is generated when KPKD is set. Reserved, should be cleared Key Release Synchronizer Set. Self-clear bit. The Key release synchronizer is set by writing a logic one into this bit. Reads return a value of “0”. 0 No effect 1 Set bits which sets keypad release synchronizer chain Key Depress Synchronizer Clear. Self-clear bit. The Key depress synchronizer is cleared by writing a logic “1” into this bit. Reads return a value of “0”. 0 No effect 1 Set bits that clear the keypad depress synchronizer chain Description 9 KRIE 8 KDIE 7–4 3 KRSS 2 KDSC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-6 Freescale Semiconductor Keypad Port (KPP) Table 25-6. Keypad Status Register Field Descriptions (continued) Field 1 KPKR Description Keypad Key Release. The keypad key release (KPKR) status bit is set when all enabled rows are detected high after synchronization (the KPKR status bit will be set when cleared by a reset). The KPKR bit may be used to generate a maskable key release interrupt. The key release synchronizer may be set high by software after scanning the keypad to ensure a known state. Due to the logic function of the release and depress synchronizer chains, it is possible to see the re-assertion of a status flag (KPKD or KPKR) if it is cleared by software prior to the system exiting the state it represents. 0 No key release is detected. 1 All keys have been released. Reset value of register is “0” as long as reset is asserted. However when reset is de-asserted, the value of the register depends upon the external row pins and can become “1”. Keypad Key Depress. The keypad key depress (KPKD) status bit is set when one or more enabled rows are detected low after synchronization. The KPKD status bit remains set until cleared by the software. The KPKD bit may be used to generate a maskable key depress interrupt. If desired, the software may clear the key press synchronizer chain to allow a repeated interrupt to be generated while a key remains pressed. In this case, a new interrupt will be generated after the synchronizer delay (4 cycles of the 32 KHz clock) elapses if a key remains pressed. This functionality can be used to detect a long key press. This allows detection of additional key presses of the same key or other keys. Due to the logic function of the release and depress synchronizer chains, it is possible to see the re-assertion of a status flag (KPKD or KPKR) if it is cleared by the software prior to the system exiting the state it represents. 0 No key presses have been detected. 1 A key has been depressed. 0 KPKD 25.3.3.3 Keypad Data Direction Register (KDDR) The bits in the KDDR control the direction of the keypad port pins. The upper eight bits in the register affect the pins designated as column strobes, while the lower eight bits affect the row sense pins. Setting any bit in this register configures the corresponding pin as an output. Clearing any bit in this register configures the corresponding port pin as an input. For the Keypad Row DDR, an internal pull-up is enabled if the corresponding bit is clear. This register is cleared by a reset, configuring all pins as inputs. The KDDR register is byte- or halfword–addressable. NOTE When a pin is used as row pin for keypad purposes, all corresponding pull-ups should be enabled at the upper level (for example, IOMUX) when the bit in row DDR is cleared. Figure 25-5 shows the valid bits in the KDDR register, and Table 25-7 provides its field descriptions. 0x1000_8004 (KDDR) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R KCD W D7 Reset 0 KCD D6 0 KCD D5 0 KCD D4 0 KCD D3 0 KCD D2 0 KCD D1 0 KCD D0 0 KRD D7 0 KRD D6 0 KRD D5 0 KRD D4 0 KRD D3 0 KRD D2 0 KRD D1 0 KRD D0 0 Figure 25-5. KDDR Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-7 Keypad Port (KPP) Table 25-7. Keypad Data Direction Register Field Descriptions Field 15–8 KCDD 7–0 KRDD 1 n=7–0 2 Description Keypad Column Data Direction Register. Setting any bit configures the corresponding pin as an output. 0 COLn pin is configured as an input. 1 COLn1 pin is configured as an output. Keypad Row Data Direction. Setting any bit configures the corresponding pin as an output. 0 ROWn pin configured as an input. 1 ROWn2 pin configured as an output. n=7–0 25.3.3.4 Keypad Data Register (KPDR) This 16-bit register is used to access the column and row data. Data written to this register is stored in an internal latch, and for each pin configured as an output, the stored data is driven onto the pin. A read of this register returns the value on the pin for those bits configured as inputs. Otherwise, the value read is the value stored in the register. The KPDR register is byte- or halfword–addressable. This register is not initialized by a reset. Valid data should be written to this register before any bits are configured as outputs. Figure 25-6 shows the KPDR register, and Table 25-8 provides its field descriptions. 0x1000_8006 (KPDR) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R KCD7 KCD6 KCD5 KCD4 KCD3 KCD2 KCD1 KCD0 KRD7 KRD6 KRD5 KRD4 KRD3 KRD2 KRD1 KRD0 W Reset — — — — — — — — — — — — — — — — Figure 25-6. KPDR Register Table 25-8. Keypad Data Register Field Descriptions Field 15–8 KCD Description Keypad Column Data. A read of these bits returns the value on the pin for those bits configured as inputs. Otherwise, the value read is the value stored in the register. 0 Read/Write “0” from/to column ports 1 Read/Write “1” from/to column ports Keypad Row Data. A read of these bits returns the value on the pin for those bits configured as inputs. Otherwise, the value read is the value stored in the register. 0 Read/Write “0” from/to row ports 1 Read/Write “1” from/to row ports 7–0 KRD MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-8 Freescale Semiconductor Keypad Port (KPP) 25.4 Functional Description The Keypad Port (KPP) is designed to simplify the software task of scanning a keypad matrix. With appropriate software support and matrix organization, the KPP is capable of detecting, debouncing, and decoding one or more keys pressed simultaneously on the keypad. Logic in the KPP is capable of detecting a key press even while the processor is in one of the low power standby modes providing that a 32 KHz clock is on. The KPP may generate a CPU interrupt any time a key press or key release is detected. This interrupt is capable of forcing the processor out of a low power mode. 25.4.1 Keypad Matrix Construction The KPP is designed to interface to a keypad matrix, which shorts the intersecting row and column lines together whenever a key is depressed. The interface is not optimized for any other switch configuration. 25.4.2 Keypad Port Configuration The software must initialize the KPP for the size of the keypad matrix. Pins connected to the keypad columns should be configured as open-drain outputs. Pins connected to the keypad rows should be configured as inputs. On-chip, pull-up resistors should be implemented for active keypad rows. In addition to enabled row inputs in the Keypad Control register, corresponding interrupt (depress or/and release) must also be enabled to generate an interrupt. Discrete switches that are not part of the matrix may be connected to any unused row inputs. The second terminal of the discrete switch is connected to ground. The hardware detects closures of these switches without the need for software polling. 25.4.3 Keypad Matrix Scanning Keypad scanning is performed by a software loop that walks a zero across each of the keypad columns, reading the value on the rows at each step. The process is repeated several times in succession, with the results of each pass optionally compared to those from the previous pass. When several (3 or 4) consecutive scans yield the same key closures, a valid key press has been detected. Software then can decode exactly which switch was depressed and pass the value up to the next higher software layer. The basic debouncing period, which must be defined in the software routine, may be controlled with an internal timer. The basic period is the period between the scan of two consecutive columns, so the debouncing time between two consecutive scans of the whole matrix shall be the number of columns multiplied by the basic period. 25.4.4 Keypad Standby There is no need for the CPU to continually scan the keypad. Between key presses, the keypad can be left in a state that requires no software intervention until the next key press is detected. To place the keypad in a standby state, software should write all column outputs low. Row inputs are left enabled. At this point, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-9 Keypad Port (KPP) the CPU can attend to other tasks or revert to a low power standby mode. The KPP will interrupt the CPU if any key is pressed. Upon receiving a keypad interrupt, the CPU should set all the column strobes high, and begin a normal keypad scanning routine to determine which key was pressed. It is important that open-drain drivers be used when scanning to prevent a possible DC path between power and ground through two or more switches. 25.4.5 Glitch Suppression on Keypad Inputs A glitch suppression circuit qualifies the keypad inputs to prevent noise from inadvertently interrupting the CPU. The circuit is a 4-state synchronizer clocked from a 32 KHz clock source. This clock must continue to run in any low power mode where the keypad is a wake-up source, as the CPU interrupt is generated from the synchronized input. An interrupt is not generated until all four synchronizer stages have latched a valid key assertion. This guarantees the filtering out of any noise less than three clock periods (for 32 KHz clock: 93.75 µs) in duration. Noise filtering of the duration between three to four clock periods (for the 32 KHz clock: between 93.75 µs and 125 µs) cannot be guaranteed. The interrupt output is latched in an S-R latch and remains asserted until cleared by the software. The Set input of the latch is rising-edge clocked. See Figure 25-7. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-10 Freescale Semiconductor Keypad Port (KPP) DQ FF S DQ FF S Row Pins DQ FF S KPKR Set KPKR Synchronizer D R Clear KPKR Status Flag KPCR(7:0) KEYPAD MATRIX NAND DQ FF R DQ FF R DQ FF R 32 KHz KPKD Clear KPKD Synchronizer ANDing of pins with ROW-enable bits Clear KPKD Status Flag D R . Column Pins Figure 25-7. Keypad Synchronizer Functional Diagram 25.4.6 Multiple Key Closures Using the key press and Key release interrupts, the software can detect multiple keys or achieve n key rollover. The key scanning routine can be programmed accordingly. Refer to Section 25.5, “Initialization/Application Information” for more information. See Figure 25-5 and Figure 25-9 for illustrations of the interfacing of a 2-contact keypad matrix with the KPP controller. With proper enabling of row lines and the performing scan-routine, multiple key presses can be detected. When keys present on the same row are pressed, corresponding row lines (multiple lines) become low when the column is driven low during a scan-routine. By reading the data-register, pressed keys can be detected. Similarly, when keys present on same row line are pressed, the corresponding row line (only one line) becomes low when logic “0” is driven on the column line during a scan-routine. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-11 Keypad Port (KPP) Output configuration Column lines Multiple key presses Keypad Port Controller Row lines Switch matrix Input configuration with pull-ups Figure 25-8. Multiple Key Presses on Same Column Line (Simplified View) Output configuration Column Lines Keypad Port Controller Multiple key presses Row Lines Switch matrix Input configuration with pull-ups Figure 25-9. Multiple Key Presses on Same Row Line (Simplified View) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-12 Freescale Semiconductor Keypad Port (KPP) NOTE An n key rollover is a technique the system uses to recognize the order in which keys are pressed. 25.4.6.1 Ghost Key Problem and Correction The KPP module detects if one or multiple keys are pressed or released. In the case where a simple keypad matrix with two-contact switches is used, there is a chance of “ghost” key detection when three or more keys are pressed. This is a limitation imposed by such a keypad matrix. As can be seen in Figure 25-10, three keys pressed simultaneously can cause a short between the column currently “scanned” by the software and another column. Depending on the location of the third key pressed, a “ghost” key press may be detected. However, this can be corrected by using a keypad matrix that provides “ghost” key protection. Such a matrix implements a one-way “diode” at all keypad points between rows and columns. This way, the multiple pressing of three keys will not cause a short at a fourth key (see Figure 25-11). Column pulled down Column not pulled down Three real key presses Pulled down row Pulled down row The path of the zero pull down that reaches the wrong row and so generates a ghost key press Ghost key press Figure 25-10. Decoding Wrong Three-Key Presses MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-13 Keypad Port (KPP) Column pulled down Column not pulled down Three real key presses Switches with diode Pulled down row The path of zero pull down gets stopped at this point Pulled down row The path of the zero pull down cannot reach the wrong row Diode prevents ghost key press Figure 25-11. Matrix with “Ghost” Key Protections 25.4.7 3-Point Contact Keys Support The KPP module supports interfacing to a matrix consisting of 3-point contact keys. As shown in Figure 25-12, two points of such a key are connected to keypad lines, while a third point is connected to ground (low logic). The keypad lines should be configured as input and a pull-up should to be present on these lines. When such a key is pressed, corresponding keypad lines go low and an interrupt is generated. There is no need to perform a scanning routine for identification of pressed key as it can be done by reading the keypad data-register. A limitation with such a matrix is that for every key at least one keypad row line should be used. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-14 Freescale Semiconductor Keypad Port (KPP) Input Configuration with Pull-Ups 3-Point Contact Keys Keypad Port Controller Keypad Lines GND Figure 25-12. KPP Interface with 3-Point Contact Key Matrix (Simplified View) 25.5 Initialization/Application Information This section provides initialization and application information. 25.5.1 Typical Keypad Configuration and Scanning Sequence Perform the following steps to configure the keypad: 1. Enable the number of rows in the keypad (KPCR[7:0]). 2. Write 0s to KPDR[15:8]. 3. Configure the keypad columns as open-drain (KPCR[15:8]). 4. Configure columns as output and rows as input (KDDR[15:0]). 5. Clear the KPKD Status Flag and Synchronizer chain. 6. Set the KDIE control bit, and clear the KRIE control bit (avoid false release events). (The system is now in standby mode, and awaiting a key press.) 25.5.2 Key Press Interrupt Scanning Sequence Perform the following steps to perform a keypad scanning routine: 1. Disable both (depress and release) keypad interrupts. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 25-15 Keypad Port (KPP) 2. 3. 4. 5. 6. 7. 8. 9. Write 1s to KPDR[15:8], setting column data to 1s. Configure columns as totem pole outputs (for quick discharging of keypad capacitance). Configure columns as open-drain. Write a single column to 0, and other columns to 1. Sample row inputs and save data. Multiple key presses can be detected on a single column. Repeat Steps 2–6 for remaining columns. Return all columns to 0 in preparation for standby mode. Clear KPKD and KPKR status bit(s) by writing to a “1”; set the KPKR synchronizer chain by writing a “1” to the KRSS register; and clear the KPKD synchronizer chain by writing a “1” to the KDSC register. 10. Re-enable the appropriate keypad interrupt(s) so that the KDIE detects a key hold condition, or the KRIE detects a key-release event. 25.5.3 Additional Comments The order of key press detection can be done in software only. Therefore, the software may need to run the scan routines at very short intervals of time per the application’s demands. For the keys that require a very precise order (such as game keys), individual GPIO pins may be more useful. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 25-16 Freescale Semiconductor Chapter 26 Memory Stick Host Controller (MSHC) The Memory Stick Host Controller (MSHC) consists of two sub modules—the MSHC gasket and the Sony Memory Stick Host Controller (SMSC). The SMSC module, which is the actual memory stick host controller, is compatible with Sony Memory Stick Ver. 1.x and Memory Stick Pro. The gasket connects the AIPI IP bus to the SMSC interface to allow IP transfers. The MSHC is placed between the AIPI and the Sony Memory Stick to support data transfer from the chip to the MS. The MSHC top level block diagram with input and output signals is shown in Figure 26-1. MSHC Clock and Reset MSHC Gasket Sony Memory Stick Host Controller xscko data[3:0] data[3:0] mssdir Mem. Stick IF IP Bus mspdir bs Figure 26-1. Memory Stick Controller Block Diagram 26.1 Overview This chapter describes the MSHC gasket module in detail. All details regarding the SMSC module can be found separately in Memory Stick/Memory Stick Pro Host Controller IP Specification 1.3. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 26-1 Memory Stick Host Controller (MSHC) 26.1.1 Features The MSHC includes the following features: • A gasket between IP bus and SMSC — IP bus interface transfer functionality as slave — Three internal registers (timeout, interrupt status/clear, and interrupt enable register) — Gasket interrupt for transfer errors, or wait timeout — Timeout function for abnormal transfer wait states — Fixed 32-bit data bus — Little endian to IP data bus and big endian to SMSC data bus • SMSC to communicate to the Sony Memory Stick — Four internal registers structured in 64-bit format — FIFO (4 x 64-bit) — Interrupt after Memory Stick communication completes — DMA in dual address mode (Note: SMSC supports single address mode as well) • Test mode and DFT implementation 26.1.2 Modes of Operation The MSHC gasket has a reduced IP interface and supports the IP bus read/write transfers that include a back-to-back read or write. DMA transfers also take place via the IP interface. A transfer can be initiated by the DMA or the host (through AIPI) in response to an MSHC DMA request or interrupt. The SMSC has two DMA address modes, a single address mode and a dual address mode. The MSHC is set to dual address mode for transfers with the DMA. In dual address mode, when the MSHC requests a transfer with the DMA request (XDRQ), the DMA will initiate a transfer to the MSHC. The MSHC still has the external memory ports and the DMA acknowledge input (XDAK) even though the single address mode is not used in some chip. 26.2 26.2.1 External Signal Description Overview Table 26-1. MSHC I/O Signals Name data[3:0] data[3:0] Port Input Output Output Active — — — MSHC data input from MS MSHC data output to MS MSHC external memory output data Function The MSHC signals are listed in Table 26-1. ipp_do_ms_mdo[63:0] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 26-2 Freescale Semiconductor Memory Stick Host Controller (MSHC) Table 26-1. MSHC I/O Signals (continued) Name ipp_do_ms_mdsl ipp_do_ms_mreq ipp_do_ms_mrws mspdir mssdir xscko Port Output Output Output Output Output Output Active High High — — — — Function MSHC external memory data select. If set to one, external memory is selected. MSHC external memory data request MSHC external memory read/write select (write if one) MSHC parallel data direction (write transfer—MSHC to MS—if one, or read transfer if zero) MSHC serial data direction (write transfer—MSHC to MS—if one, or read transfer if zero) MSHC serial clock output 26.2.1.1 Memory Stick Interface The MSHC module supports Memory Stick Pro, which means a data transfer can be done in serial mode or parallel mode. 26.3 Memory Map and Register Definition The MSHC has seven internal registers; four registers in the SMSC and three registers in the gasket. The gasket internal registers do not require any extra addresses as they share the address space for the SMSC internal registers. IP bus accesses are 32-bit, but all SMSC registers (except the data register) use only the upper 16 bits, so the gasket can utilize the lower 8 bits. The MSHC internal registers are mapped to 64-bit structure, so the required address signal is [4:3]. Due to this address sharing scheme, the host must keep the SMSC register values as necessary while updating the gasket internal registers. Table 26-2 shows the memory map for the MSHC module. Table 26-2. MSHC Memory Map Memory Map ‘h00 Data Bit addr[4:3] [63:57] 0 [56:48] [47:40] Gasket timeout register [39:32] [31:24] [23:16] Not used [15:8] [7:0] SMSC command register ‘h08 1 SMSC data register Not used MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 26-3 Memory Stick Host Controller (MSHC) Table 26-2. MSHC Memory Map (continued) Memory Map ‘h10 Data Bit addr[4:3] [63:57] 2 [56:48] [47:40] Gasket interrupt status/ clear register Gasket interrupt enable register [39:32] [31:24] [23:16] Not used [15:8] [7:0] SMSC status register ‘h18 3 SMSC system register Not used 26.3.1 Register Descriptions The MSHC module uses big endian with 64-bit data while the chip system uses the little endian with 32-bit data. Therefore, the data must be assigned as per Table 26-3. Table 26-3. MSHC Data Endianism and Connection to IP Bus Bus MSHC data IP bus data Endian Big Little [63:56] [7:0] [55:48] [15:8] [47:40] [23:16] Connection [39:32] [31:24] [31:24] — [23:16] — [15:8] — [7:0] — 26.3.1.1 SMSC Registers The SMSC command register contains the MS transfer protocol command (TPC) and transfer data size. It must be set by either the host or DMA before starting a transfer. The SMSC data register is used to access the SMSC internal FIFO, which is of size 4 x 64-bit. It takes 8 32-bit transfers to fill or empty the FIFO. The SMSC status register reflects SMSC status, such as FIFO status, ready flag for transfers and CRC error flag. The host needs to read this register in order to start and manage the transfer. This register is only readable through the IP bus. The SMSC system register has a user command for SMSC modes and options that are required for transfer and communication with the MS. This register must be set before starting a transfer and should not be changed during the communication with the MS. More details can be found in Memory Stick/ Memory Stick PRO Host Controller IP Specification, Ver. 1.3. 26.3.1.2 26.3.1.2.1 Gasket Register Gasket Timeout Register This register is readable or writable. The value after synchronous or asynchronous reset is 0. This register gives a mechanism to time-out if long wait states are encountered. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 26-4 Freescale Semiconductor Memory Stick Host Controller (MSHC) Once the FIFO becomes full while the IP bus has more data to be written, the gasket asserts the wait signal until the FIFO space is available. The gasket will also start to decrement an internal counter from the timeout value for wait, TOVW[7:0]. When the counter reaches zero, the ips_xfr_wait signal is deasserted and an interrupt is generated If the wait state is cleared before the timeout counter reaches zero the suspended transfer will be resumed. When the TOVW[7:0] is set to zero the gasket will not produce wait states if the FIFO is full/empty, but will generate an interrupt. If the gasket interrupt enable bits - INTEN_WFUL and INTEN_REMP - are disabled, the timeout counter has no functionality (it is effectively set to infinity). Once the wait state is entered the MSHC will stay in wait until either the AIPI disables the module (using ips_module_en) or the FIFO becomes available for another transfer. Table 26-4. Timeout Register Bit Name Reset value R/W 47 46 45 44 43 42 41 40 TOVW[7:0] 0 R/W 26.3.1.2.2 Gasket Interrupt Status/Clear Register This register is readable or writable, and is reset to 0 by asynchronous or synchronous reset. Bits should be written as 1 to clear an interrupt. The unused bits are read as zero. The SMSC status register, which has the same address as this register, is a read-only register. The interrupt status/clear register reflects the transfer status. It is used for the gasket to decide if it supports a current transfer, and it can also be used for the gasket interrupt generation. The gasket provides four different interrupts, which are all directly related to the IP bus transfer. Once an interrupts occurs the host needs to check this register to determine which interrupt occurred and also to clear the interrupt (by writing 1 to the register bit). Table 26-5. Interrupt Status/Clear Register Bit Name Reset value R/W 47 IDA 0 R/W 46 IXFR 0 R/W 45 — — R/– 44 — — R/– 43 WFUL 0 R/W 42 REMP 0 R/W 41 — — R/40 — — R/- • IDA (Illegal data access) This bit is asserted if a transfer is not 32-bit, that is, if the ips_byte inputs are not all asserted. It is always readable and can be cleared (if the interrupt enable bit INTEN_IDA is enabled) by writing to this register with ips_wdata[23] set to one. Any illegal data access always asserts IDA, but will not generate a gasket interrupt if the interrupt enable bit INTEN_IDA is disabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 26-5 Memory Stick Host Controller (MSHC) • • • IXFR (Illegal transfer) This bit is asserted if a data transfer direction is not consistent with the SMSC FIFO data direction. It is always readable and can be cleared (if the interrupt enable bit INTEN_IXFR is enabled) by writing to this register with ips_wdata[22] set to one. Any illegal data transfer always asserts IXFR, but will not generate a gasket interrupt if the interrupt enable bit INTEN_IXFR is disabled. WFUL (Write to FIFO when full) This bit is asserted if the SMSC FIFO is full and the current write transfer is not finished. It is always readable and can be cleared (if the interrupt enable bit INTEN_WFUL is set) by writing to this register with ips_wdata[19] set to one. The gasket asserts WFUL when a data write transfer is attempted while the FIFO is full. The update time will be different depending on whether INTEN_WFUL is enabled and the value of TOVW[7:0]. If INTEN_WFUL is disabled WFUL will be updated without the timeout delay. The gasket uses this bit to generate a transfer wait state as well as the interrupt. REMP (Read from FIFO when empty) This bit is asserted if the SMSC FIFO is empty and the current read transfer is not finished. It is always readable and can be cleared (if the interrupt enable bit INTEN_REMP is set) by writing to this register with ips_wdata[18] set to one. The gasket asserts REMP when a normal data read transfer is attempted while the FIFO is empty. The version number read after a reset also asserts REMP as the FIFO is empty at this time. The update time will be different depending on whether INTEN_REMP is enabled and the value of TOVW[7:0]. If INTEN_REMP is disabled REMP will be updated without the timeout delay. The gasket uses this bit to generate a transfer wait state as well as the interrupt. Gasket Interrupt Enable Register 26.3.1.2.3 This register is readable or writable, and is reset to 0 by asynchronous or synchronous reset. This register is used to enable the gasket interrupts. The gasket interrupts are disabled by the default. To enable the gasket interrupt the relevant bit should be set to 1. Table 26-6. Interrupt enable register Bit Name Reset value R/W 47 INTEN_ IDA 0 R/W 46 INTEN_ IXFR 0 R/W 45 — — R/– 44 — — R/– 43 INTEN_ WFUL 0 R/W 42 INTEN_ REMP 0 R/W 41 — — R/40 — — R/- • INTEN_IDA Illegal data access interrupt enable bit. If it is one it will enable the gasket interrupt for an illegal data access. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 26-6 Freescale Semiconductor Memory Stick Host Controller (MSHC) • • • INTEN_IXFR Illegal transfer interrupt enable bit. If it is set to one it will enable the gasket interrupt for an illegal data transfer. INTEN_WFUL Interrupt enable bit for a write transfer to fifo with full. If it is set to one it will enable the gasket interrupt and the wait timeout function. INTEN_REMP Interrupt enable bit for a read transfer from fifo with empty. If it is set to one it will enable the gasket interrupt and the wait timeout function. 26.4 26.4.1 Functional Description Sony Memory Stick Controller (SMSC) The details of the SMSC functionality can be found in Memory Stick/ Memory Stick PRO Host Controller IP Specification, Ver. 1.3. 26.4.2 MSHC Gasket This section describes MSHC clocks, MS interface, the gasket state-machine, IP bus error and wait conditions, the gasket interrupt, and IP bus transfer. 26.4.2.1 Resetting and Clocking The MSHC uses one asynchronous reset and one synchronous reset to reset gasket internal registers. The asynchronous reset is the green-line hardware asynchronous reset that is active low while the synchronous reset is a soft reset from the MSHC system register RST bit that is active high. Once the soft reset is asserted the SMSC will automatically clear the RST bit in the system register after initializing all internal registers. During the soft reset period the behavior of any IP Bus transactions is undefined. MSHC has several clocks, as shown in Figure 26-2. The MSHC has three clock inputs ipg_clk_s is directly connected to the gasket, and the others to SMSC through muxing logic. The MSHC also has one clock output that is inverted in the gasket. The muxing logic allows the MSHC to have only two clock domains during test mode. ipg_clk_s in the gasket and HCKI in the SMSC are connected to one test clock, and all other clocks (SCKI, XSCKI, MSCKI, and XMSCKI) are connected to a different test clock. The test clocks are generated inside the CRM. In normal operation, XSCKI is an inverted version of SCKI and MSCKI is an inverted version of XMSCKI. The gasket uses the ipg_clk_s for all logic that is synchronous to the IP interface signals. This clock is only active when the gasket module enable signal is asserted. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 26-7 Memory Stick Host Controller (MSHC) HCKI in the SMSC is the main clock for most of the internal registers and the FIFO. The MS has a slower clock speed and is asynchronous to HCKI, so XSCKO is generated by the SMSC and is output to provide the MS clock. All logic shown in Figure 26-2 is implemented in the gasket. ipg_clk_s ~mshc_fuse_dis clock gating ipg_clk_s cell clock gating cell MSHC Gasket ipg_clk HCKI ipp_di_scki clock gating cell ipt_se_async SCKI XSCKO ipp_do_xscko XSCKI ipp_di_xmscki clock gating cell XMSCKI MSCKI ipt_mode Sony Memory Stick Host Controller Figure 26-2. MSHC Clock Structure 26.4.2.2 Memory Stick Interface The gasket includes logic to generate the IO signals for the MS. This logic is included in the gasket so that it does not need to be provided at the chip level. The multiplex logic and signal connections included in the gasket are shown in the Table 26-3. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 26-8 Freescale Semiconductor Memory Stick Host Controller (MSHC) sbs ipp_do_bs pbs srac mssdir ipp_do_mssdir mspdir ipp_do_mspdir mssdo ipp_do_data[0] mspdo[0] mspdo[1] mspdo[2] mspdo[3] ipp_do_data[1] ipp_do_data[2] ipp_do_data[3] Figure 26-3. Gasket Memory Interface Logic MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 26-9 Memory Stick Host Controller (MSHC) 0 ipg_clk ipg_module_en ips_rwb ips_byte_#_# ips_addr ips_wdata ips_rdata ips_xfr_err ips_xfr_wait XCS XWR XRD ADDR DI DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 4'b1111 waddr wdata rdata raddr waddr wdata rdata raddr waddr wdata raddr waddr wdata raddr rdata rdata Figure 26-4. Basic Read/Write Timing Diagram 26.4.2.2.1 Back-to-Back Transfer The Figure 26-5 shows the back-to-back timing for IP bus and the SMSC interface. In the timing diagram there are three write transfers (cycles 1–6) and two read transfers (cycles 8–11). The IP bus sends back-to-back transfers and the gasket inserts one cycle wait states for each data transfer. This allows the SMSC read/write signal to be asserted for one HCKI cycle. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 26-10 Freescale Semiconductor Memory Stick Host Controller (MSHC) 0 ipg_clk ipg_module_en ips_rwb ips_byte_#_# ips_addr ips_wdata ips_rdata ips_xfr_err ips_xfr_wait XCS XWR XRD ADDR DI DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 4'b1111 waddr w1 w2 w3 r1 r2 raddr waddr w1 w2 w3 r1 raddr r2 Figure 26-5. Back-to-Back Write/Read Timing Diagram 26.4.2.3 Transfer Error When the gasket detects a transfer error it generates an interrupt. The IP bus transfer error interrupt is an optional feature that can be enabled by the gasket interrupt enable register. Two transfer error conditions are: • Illegal data access • Illegal transfer The data access error shows if the IP bus transfer is not 32-bit. The gasket checks all four byte enable signals and if any one of these becomes zero during a transfer the gasket will set the interrupt status/clear bit, IDA, and generate the interrupt. The illegal transfer error shows whether the IP bus data transfer direction is correct. The SMSC system register includes the fifo data direction bit that must be set before the transfer is started. If this bit is set to one, the data direction is from AIPI to MSHC. Then the next IP bus transfer must be a write. If the data direction and data transfer direction are not consistent, the gasket updates the interrupt status/clear bit, IXFR, to one and generates the interrupt. Note that this error condition is applied only to transfers to the SMSC data register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 26-11 Memory Stick Host Controller (MSHC) 26.4.2.4 Transfer Wait Condition In normal transfers, a wait state may be inserted for one clock cycle for each 32-bit transfer, because of the read/write timing requirements for the SMSC when the IP bus is dealing with back-to-back type transfers. If the transfer initiator ensures a maximum transfer burst to fill the SMSC FIFO there will be no multiple wait cycles. If IP bus performs a large transfer burst to the MSHC, the SMSC FIFO will fill due to the slow transfer speed between the SMSC and the MS. In this case, the gasket inserts wait states until the FIFO is available for further transfers, that is, one space in the FIFO is available. At this time the gasket will end the wait state and resume the next transfer. The behavior is similar for read transfers when the FIFO is empty. There are two conditions for multiple cycles of wait states: • Write transfers on the IP bus with the SMSC FIFO full • Read transfers on IP bus with the SMSC FIFO empty Exceptional operations can also cause a long wait state. For instance, if one 32-bit data write transfer is performed with the SMSC FIFO empty, the empty flag will remain set. Thus, if the following transfer is a read operation it will not be processed due to the asserted state of the FIFO empty flag. Therefore the gasket will stay in a wait state as long as the read transfer request remains pending on the IP bus. A minimum of two 32-bit write transfers are required to deassert the empty flag. The transfer initiator must make sure that a minimum of two write transfers are made in order to read back the data written to the FIFO. Another unexpected long wait state may happen if the communication between the MSHC and the MS is abnormally terminated. To prevent this behavior, the gasket provides a wait timeout function, with which a timeout value can be used to disable the wait state and generate an interrupt if the transfer wait state goes for too long. This option is available when the interrupt enable bits, INTEN_WFUL and INTEN_REMP, are enabled as described in Section 26.3, “Memory Map and Register Definition.” The timeout counter has no functionality if the INTEN_WFUL and INTEN_REMP interrupts are disabled. In this case the transfer initiator is responsible for disabling the module to end a long wait state. 26.4.2.5 Gasket Interrupt The gasket interrupts are generated from transfer error and wait conditions and is ORed with the SMSC interrupt. Table 26-6 is the flow chart that shows how the gasket inserts wait states and generates an interrupt. The flow chart also shows how the gasket timeout function performs. The interrupt enable bits INTEN_WFUL and INTEN_REMP disable all the gasket status/clear and timeout register functions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 26-12 Freescale Semiconductor Memory Stick Host Controller (MSHC) Start XFR Yes Interrupt error No discard XFR DAT_XFR type COM_XFR, STA_XFR, SYS_XFR End write direction do XFR read End No fifo full No fifo empty Yes do XFR Yes inten_wful No (version # read) inten_remp No Yes do XFR Yes Yes timeout End No No End Interrupt timeout No WAIT No Yes fifo ful Interrupt WAIT discard XFR No WAIT WAIT Yes No discard XFR No End fifo ful fifo empty fifo empty No do XFR xfr disabled End Yes do XFR Yes xfr disabled Yes No xfr disabled do XFR Yes End discard XFR End No xfr disabled Yes discard XFR Yes discard XFR End do XFR End Yes End discard XFR End End End Figure 26-6. Gasket Interrupt Generation MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 26-13 Memory Stick Host Controller (MSHC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 26-14 Freescale Semiconductor Chapter 27 Secured Digital Host Controller (SDHC) The MultiMediaCard (MMC) is a universal low-cost data storage and communication medium that is designed to cover a wide area of applications, such as electronic toys, organizers, PDAs, and smart phones. The MMC communication is based on an advanced 7-pin serial bus designed to operate in a low-voltage range. The Secure Digital Card (SD), is an evolution of MMC technology, with two additional pins in the form factor. It is specifically designed to meet the security, capacity, performance, and environment requirement inherent in newly emerging audio and video consumer electronic devices. The physical form factor, pin assignment, and data transfer protocol are forward-compatible with the MultiMediaCard with some additions. Under SD protocol, it can be categorized into Memory card, I/O card, and Combo card (has both memory and I/O functionality). The memory card invokes a copyright-protection mechanism that complies with the security of the SDMI standard, is faster, and provides the capability for a higher memory capacity. The I/O card provides high-speed data I/O with low-power consumption for mobile electronic devices. The Security Digital Host Controller (SDHC) integrates both MMC support along with SD memory and I/O functions, including SD memory and I/O combo card. See the block diagram of SDHC in Figure 27-1. ipi_irq_b ipd_dreq_b System State Machine and DMA Handler Logic Control CRC CMD/ Data Channel Tx/Rx Handler Channel Control Secure Digital Host Controller SDHC Application Bus IP Gasket ipg_clk_32k (Application Adapter) ipg_perclk ipg_clk_s ipg_clk ipg_clk_en ipg_perclk_en Configuration CMD Channel State Machine CMD DAT3 Register Handler 32*16 FIFO Logic Control DAT2 Data Channel State Machine DAT1 CRC DAT0 Data Access CLK CLK_20M Internal CLK Clock Controller CLK_DIV Internal CLK MMC/SD Bus Clock MMC_SD_CLK Figure 27-1. Secure Digital Host Controller Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-1 Secured Digital Host Controller (SDHC) See Figure 27-2 for the illustration of system interconnection with the SDHC module. Secure Digital Host Controller DMA Interface Transceiver I/O Memory Card IP Bus IP Gasket IP Bus Figure 27-2. System Interconnection with the Secure Digital Host Controller 27.1 Overview The Security Digital Host Controller (SDHC) controls the MMC, SD memory, and I/O cards by sending commands to cards and performing data accesses to/from the cards. Refer to Section 27.4, “Functional Description” for a detailed description. 27.1.1 Features The features of the Secure Digital Host Controller module include the following: • Full compatibility with the MMC system specification, version 3.2 • Compatibility with the SD Memory Card Specification 1.01, and SD I/O Specification 1.1 with 1/4 channel(s) • 100 Mbps maximum data rate in 4-bit mode, SD bus clock up to 25 MHz • Built-in programmable frequency counter for SDHC bus • Maskable hardware interrupt for SDIO Interrupt, Internal status and FIFO status • Built-in dual 16 x 32-bit data FIFO buffer • Plug and play (PnP) support • Single/Multi-block access to the card, including erase operation • Multi-SD function support, including multiple I/O and combined I/O and memory • Up to seven I/O functions, plus one memory supported on single SD I/O card (Combo card) • IRQ supported enable card to interrupt host • Support of SDIO interrupt detection during 1/4-bit access • Support of SDIO Read/Wait and suspend/resume operation • Controller core—Freescale Semiconductor IP bus compatible • Block-based data transfer between MMC card and SDHC (stream mode not supported) • Block length of data transfer capability between host and card of approximately 1 to 2048 bytes MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-2 Freescale Semiconductor Secured Digital Host Controller (SDHC) 27.2 External Signal Description The SDHC has a six-chip I/O. The MMC_SD_CLK is an internally generated clock used by the MMC/SD card. The CMD I/O is used to send commands and receive responses from the card. Four data lines, DAT3–DAT0, are used to perform data transfers between the host controller and the card. See Table 27-1 for the signal properties of the I/Os. Table 27-1. Signal Properties Name MMC_SD_CLK CMD DAT3 Port O I/O I/O Function Clock for MMC/SD/SDIO card CMD line connect to card Card Detect in Power up Data line in 4-bit mode Not used in 1-bit mode Data line or Read wait in 4-bit mode Read wait in 1-bit mode Data line or interrupt in 4-bit mode Interrupt in 1-bit mode Data line both in 1-bit and 4-bit mode Reset State 0 1 0 Pull up Pull down DAT3 if need card detection through this bit, otherwise pull up Pull up Pull up Pull up Pull up DAT2 DAT1 DAT0 I/O I/O I/O 1 1 1 27.3 Memory Map and Register Definition SDHC contains 16 32-bit registers. Section 27.3.3, “Register Descriptions” provides the detailed descriptions for all of the SDHC registers. All the registers can be accessed only in 32-bit sizes. Byte/Half-word access is not allowed. 27.3.1 Memory Map Table 27-3 shows the SDHC memory map. The SDHC memory map space is 4 Kbytes. Only address offsets from 0 x 00 to 0 x 44 are implemented. The address space above the offset of 0 x 44 is reserved. For write access to the reserved address region, the access is ignored by SDHC. For read access to the reserved address region, 0 x 0 will be returned on the IP Bus. The user should not access the reserved region to ensure compatibility with possible future revisions of this module. Table 27-3. SDHC Memory Map Address 0x1001_3000 (STR_STP_CLK1) 0x1001_4000 (STR_STP_CLK2) 0x1001_3004 (STATUS1) 0x1001_4004 (STATUS2) 0x1001_3008 (CLK_RATE1) 0x1001_4008 (CLK_RATE2) 0x1001_300C (CMD_DAT_CONT1) Register SDHC Clock Control register SDHC Status register SDHC Card Clock Rate register SDHC Command Data Control register Access R/W R R/W R/W Reset Value 0x0000_0000 0x3000_0000 0x0000_0008 0x0000_0000 Section/Page 27.3.3.1/27-8 27.3.3.2/27-9 27.3.3.3/27-13 27.3.3.4/27-15 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-3 Secured Digital Host Controller (SDHC) Table 27-3. SDHC Memory Map (continued) Address 0x1001_3010 (RES_TO1) 0x1001_4010 (RES_TO2) 0x1001_3014 (READ_TO1) 0x1001_4014 (READ_TO2) 0x1001_3018 (BLK_LEN1) 0x1001_4018 (BLK_LEN2) 0x1001_301C (NOB1) 0x1001_401C (NOB2) 0x1001_3020 (REV_NO1) 0x1001_4020 (REV_NO2) 0x1001_3024 (INT_CNTR1) 0x1001_4024 (INT_CNTR2) 0x1001_3028 (CMD1) 0x1001_4028 (CMD2) 0x1001_302C (ARG1) 0x1001_402C (ARG2) 0x1001_3034 (RES_FIFO1) 0x1001_4034 (RES_FIFO2) 0x1001_3038 (BUFFER_ACCESS1) 0x1001_4038 (BUFFER_ACCESS2) Register SDHC Response Time-out register SDHC Read Time-out register SDHC Block Length register SDHC Number of Block register SDHC Revision Number register SDHC Interrupt Control register SDHC Command Number register SDHC Command Argument register SDHC Command Response FIFO Access register SDHC Data Buffer Access register Access R/W R/W R/W R/W R R/W R/W R/W R R/W Reset Value 0x0000_0040 0x0000_FFFF 0x0000_0000 0x0000_0000 0x0000_0400 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 27.3.3.5/27-17 27.3.3.6/27-18 27.3.3.7/27-19 27.3.3.8/27-20 27.3.3.9/27-21 27.3.3.10/27-22 27.3.3.11/27-26 27.3.3.12/27-27 27.3.3.13/27-28 27.3.3.14/27-29 Note: The following addresses are reserved: 0x1001_3030 0x1001_330C 0x1001_4030 0x1001_430C 27.3.2 Register Summary Figure 27-3 shows the key to the register fields and Table 27-4 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 27-3. Key to Register Fields Table 27-4. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-4 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-4. Register Figure Conventions (continued) Convention Description Register Field Types r w rw rwm w1c slfclr Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 27-5 shows the SDHC register summary. Table 27-5. SDHC Register Summary Name R W 0x1001_3000 (STR_STP_CLK1) 0x1001_4000 (STR_STP_CLK2) R 0 0 0 0 0 0 0 0 0 0 0 0 slfcl r SD HC Res et 0 STA ST RT_ OP CL _CL K K 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-5 Secured Digital Host Controller (SDHC) Table 27-5. SDHC Register Summary (continued) Name 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 CA RD _IN R SE RTI ON CA YB XB BU XB RD UF_ UF_ YB F_U BU UF_ _R EM EM UF_ ND F_ FUL EM PT PT FUL _R OV L OV Y Y L UN FL AL 0 0 0 0 0 0 0 0 W w1c w1c 0x1001_3004 (STATUS1) 0x1001_4004 (STATUS2) SDI O_I NT_ AC TIV E RE EN WR AD D_ ITE _TR WR_CRC CM _O AN _ERR_C D_ P_ ODE S_ RE DO DO SP NE NE CA RD _BU S_ CL K_ RU N BU RE BU F_R SP_ F_ EA CR WR D_ C_ _R RD ER DY Y R w1c 0 0 0 0 0 RE AD _C RC _E RR WR TIM TIM ITE E_ E_ _C OU OU RC T_R T_R _E ES EA P D RR R 0 0 W R 0x1001_3008 (CLK_RATE1) W 0x1001_4008 (CLK_RATE2) R 0 w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 w1c w1c w1c w1c 0 0 0 0 CLK_PRESCALER[15:4] W R W 0x1001_300C (CMD_DAT_CONT1) 0x1001_400C (CMD_DAT_CONT2) R CM D_ RE W SU ME 0 0 CM D_ RE SP_ LO NG _O FF 0 0 ST STA OP RT_ _R RE EA AD DW WAI AIT T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_DIVIDER[3:0] 0 0 0 0 BUS_WI DTH INIT WR DAT ITE A_E FORMAT_OF_ _R NA RESPONSE EA BLE D R 0x1001_3010 (RES_TO1) 0x1001_4010 (RES_TO2) W R W R 0x1001_3014 (READ_TO1) 0x1001_4014 (READ_TO2) W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE TIME OUT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_READ_TIME_OUT[15:0] W MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-6 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-5. SDHC Register Summary (continued) Name R 0x1001_3018 (BLK_LEN1) 0x1001_4018 (BLK_LEN2) W R W R 0x1001_301C (NOB1) 0x1001_401C (NOB2) W R NOB[15:0] W R 0x1001_3020 (REV_NO1) 0x1001_4020 (REV_NO2) W R W R 0 0 0 0 0 0 0 0 0 0 0 0 0 SDI O_I NT_ WK P_E N CA RD _IN SE RT_ WK P_E N CA RD _R EM OV AL_ WK P_E N RE AD _O P_ DO NE 0 Revision Number[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLOCK LENGTH[11:0] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x1001_3024 (INT_CNTR1) 0x1001_4024 (INT_CNTR2) CA CA RD RD SDI _IN _R O_I DAT SE EM RQ 0_E W RTI OV _E N ON AL_ N _E EN N R 0x1001_3028 (CMD1) 0x1001_4028 (CMD2) W R W R ARG[31:16] 0x1001_302C (ARG1) 0x1001_402C (ARG2) W R ARG[15:0] W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 BU EN WR BU F_ D_ ITE F_R WR CM _O EA ITE D_ P_ D_ _E RE DO EN N S NE 0 0 0 0 0 0 0 0 0 0 0 COMMAND NUMBER MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-7 Secured Digital Host Controller (SDHC) Table 27-5. SDHC Register Summary (continued) Name R 0x1001_3034 (RES_FIFO1) W 0x1001_4034 (RES_FIFO2) R RESPONSE_CONTENT[15:0] W R 0x1001_3038 (BUFFER_ACCESS1) 0x1001_4038 (BUFFER_ACCESS2) FIFO CONTENT[31:16] W R FIFO CONTENT[15:0] W 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27.3.3 Register Descriptions Many of SDHC registers have reserved bits. Reserved bits identified in the registers are read as zero and write to these bits are ignored. However, the user should write zeros to these bits to ensure compatibility with possible future revisions of this module. 27.3.3.1 SDHC Clock Control Register (STR_STP_CLK) The SDHC Clock Control Register allows the user to reset the whole module and to enable or disable the MMC_SD_CLK to card. See Figure 27-4 for an illustration of valid bits in the SDHC Clock Control Register and Table 27-6 for descriptions of the bit fields. 0x1001_3000 (STR_STP_CLK1) 0x1001_4000 (STR_STP_CLK2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 slfclr SDHC Reset 0 STO START P_C _CLK LK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-4. SDHC Clock Control Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-8 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-6. SDHC Clock Control Register Field Descriptions Field 31–4 3 SDHC Reset Reserved SDHC Reset. Writes to the SDHC reset bit triggers the reset logic inside the SDHC. Reads from this bit always return ‘0’. To reduce the power consumption, the clock to the reset logic in SDHC is off in normal operation. When there is one access to this register, the clock will be enabled for one cycle. To complete the entire reset period, it will need at least 8 clock pulses to finish the reset cycle. To reset the SDHC module, it is recommended to write this register with value 0x0008, followed by 0x0009, and then 0x0001 eight times. Refer to Section 27.5.2.2, “Reset” for detailed information on software reset. 0 No effect 1 Reset the SDHC module Reserved Start Clock. Writing a ‘1’ to this bit starts the MMC_SD_CLK clock. Setting a value of 11 on Bits [1:0] of this register is not allowed. Note: The SDHC bus clock does not start immediately after writing to this bit. Polling needs to be done on the status CARD_BUS_CLK_RUN bit to ensure the SDHC clock is running. Refer to Example 27-1 for procedures to start the SD bus clock. 0 No effect 1 To start MMC/SD clock Stop Clock. Stops the MMC_SD_CLK clock when the user writes a value of ‘1’ to this bit. The MMC_SD_CLK should not be stopped by software during a transmission period. Setting a value of 11 on Bits [1:0] of this register is not allowed. Note: A transmission period is defined as the time from when a card data or access related command is submitted to the end of the access operation. Note: The SDHC bus clock does not stop immediately after writing to this bit. Polling needs to be done on the status CARD_BUS_CLK_RUN bit to ensure the SDHC clock is running. Refer to Example 27-1 for procedures to start the SD bus clock. 0 No effect 1 To stop the MMC/SD clock Description 2 1 START_CLK 0 STOP_CLK 27.3.3.2 SDHC Status Register (STATUS) The read-only SDHC Status Register provides the programmer with information about the status of SDHC operations, application FIFO status, error conditions, and interrupt status. There are eight interrupt status bits, which are bit-31 card insertion status bit, bit-30 card removal status bit, bit-14 SDIO card interrupt status bit, bit-13 end command and response status bit, bit-12 write operation done status bit, bit-11 read operation done status bit, bit-7 data buffer read ready status bit, and bit-6 data buffer write ready status bit. When the corresponding interrupt enable is enabled in SDHC interrupt control register for any of these interrupts, the SDHC will generate an interrupt request to the CPU. The user needs to clear the appropriate status bit to clear the corresponding interrupt. The interrupt status bits are cleared by using a write ‘1’ to clear operation except for the data buffer ready status bits which can be cleared only by the read or write operation on the data buffer. See Figure 27-5 for an illustration of valid bits in the SDHC Status Register and Table 27-7 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-9 Secured Digital Host Controller (SDHC) 0x1001_3004 (STATUS1) 0x1001_4004 (STATUS2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R CAR CAR YBUF XBUF XBUF BUF_ D_RE YBUF D_IN _EMP _EMP _FUL UND_ BUF_ MOVA _FUL SERT TY TY L RUN OVFL L L ION w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W w1c Reset 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SDIO END_ WRIT READ CAR _INT_ CMD E_OP _TRA WR_CRC_E D_BU BUF_ BUF_ RESP ACTI _RES _DON NS_D RR_CODE S_CL READ WR_ _CRC VE P E ONE K_RU _RDY RDY _ERR N w1c w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 0 0 0 w1c 0 0 TIM READ WRIT TIME_ E_O _CRC E_CR OUT_ UT_ _ERR C_ER RESP REA R D w1c w1c 0 w1c 0 w1c 0 W Reset 0 0 0 0 Figure 27-5. SDHC Status Register Table 27-7. SDHC Status Register Field Descriptions Field 31 CARD_INSERTION Description Card Insertion. When this bit is set, the SDHC detects a value transition on the SD_DAT[3:0] from 0111 to 1111. This can be used to detect whether a card is inserted to the card socket based on SD_DAT[3] pull-up resistor of the card DAT3. When this bit is set, the SDHC will generate an interrupt request if the card detection interrupt is enabled. This bit is read-only and can be cleared by writing a ‘1’ to this bit. 0 No card insertion detected 1 Card insertion detected based on logic level changed on SD_DAT[3] Card Removal. When this bit is set, the SDHC detects a logic transition on the SD_DAT[3:0] from 1111 to b0111. This can be used to detect whether a card is removed from the card socket based on the SD_DAT[3] pull-up resistor of the card DAT3. When this bit is set, SDHC will generate an interrupt request if the card removal interrupt is enabled. This bit is read-only and can be cleared by writing a ‘1’ to it. The user needs to clear this bit to clear the interrupt request from SDHC when the card detection interrupt is enabled. 0 No card removal detected 1 Card removal detected based on logic level changed on SD_DAT[3] Y Data Buffer Empty. When this is set, it indicates that the Y data buffer is empty during a write transfer. This bit is automatically cleared when the first byte of data is moved into the FIFO. Refer to Section 27.4.1, “Data Buffers” for more information about the data buffers. 0 Y buffer is not empty. 1 Y buffer is empty. 30 CARD_REMOVAL 29 YBUF_EMPTY MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-10 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-7. SDHC Status Register Field Descriptions (continued) Field 28 XBUF_EMPTY Description X Data Buffer Empty. When this is set, it indicates that the X data buffer is empty during a write transfer. This bit is automatically cleared when the first byte of data is moved into the FIFO. Refer to Section 27.4.1, “Data Buffers” for more information about the data buffers. 0 X buffer is not empty. 1 X buffer is empty. Y Data Buffer Full. When this is set, it indicates that the Y data buffer is full during a read transfer. This bit is automatically cleared when the last byte of data is read out from the FIFO. Refer to Section 27.4.1, “Data Buffers” for more information about the data buffers. 0 Y buffer is not full. 1 Y buffer is full. X Data Buffer Empty. When this is set, it indicates that the X data buffer is full during a read transfer. This bit is automatically cleared when the last byte of data is read out from the FIFO. Refer to Section 27.4.1, “Data Buffers” for more information about the data buffers. 0 X buffer is not full. 1 X buffer is full. Buffer Underrun. When this is set, it indicates that both X and Y data buffers are empty during a write transfer. In this case, the card clock MMC_SD_CLK will be stopped automatically by hardware to wait for the DMA or CPU to put data into the buffers. An interrupt is triggered if the corresponding interrupt control bit is enabled. 0 No buffer underrun 1 Buffer underrun during a write operation Buffer Overflow. When this is set, it indicates that both data buffers are full during a read operation. In this case, the card clock MMC_SD_CLK will be stopped automatically by hardware to wait for the DMA or CPU to remove data out of one of the buffers. An interrupt is triggered if the corresponding interrupt control bit is enabled. Excess data will be ignored by the SDHC. 0 No buffer overflow 1 Buffer overflow during a read operation N/A SDIO Interrupt Active. This indicates whether an interrupt from the SDIO card has been detected. When this bit is set, the SDHC generates an interrupt request if the SDIO interrupt is enabled. The user should clear the status to clear the interrupt request. A separate acknowledge command to the card may be required to clear the source of the SDIO interrupt. Writing a ‘1’ to this bit clears it. 0 No interrupt detected 1 Interrupt detected using SDIO card bus End Command Response. This indicates that a command was successfully transmitted to the card and the corresponding response stored in the Response FIFO. This occurs after each command operation. When this bit is set, the SDHC generates an interrupt request if the End_CMD_RESP interrupt is enabled. The user needs to clear this bit to negate the interrupt request. This bit is cleared by using a write ‘1’ to clear operation. 0 Command not successful, incomplete, or not applicable (no response) 1 Command transmitted successfully (response received) Note: When this bit is set, the user also needs to check if the command send and response receive operation completed without error. The user also needs to check the RESP_CRC_ERR (Status[5]) and TIME_OUT_RESP(STATUS[1]) bits to determine if an error occurred. 27 YBUF_FULL 26 XBUF_FULL 25 BUF_UND_RUN 24 BUF_OVFL 23–15 14 SDIO_INT_ACTIVE 13 END_CMD_RESP MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-11 Secured Digital Host Controller (SDHC) Table 27-7. SDHC Status Register Field Descriptions (continued) Field 12 WRITE_OP_DONE Description Write Operation Done. This indicates that a write operation has completed. The FLASH card needs extra idle time for write accesses. This requires the SDHC module to wait until the card writes the buffered data to the inner Flash memory. The SDHC module automatically detects the status. The WRITE_OP_DONE flag indicates the end of the write operation. When this bit is set, the pre-defined data bytes are written to the card. The user needs to send a STOP command to the card if the write command is a MMC/SD card write multi-block command. When this bit is set, SDHC generates an interrupt request if the WRITE_OP_DONE interrupt enable is enabled. The user needs to clear this bit to clear the interrupt. This is accomplished by writing ‘1’ to this bit. 0 Write operation in progress or incomplete 1 Write operation complete Note: When this bit is set, the user also needs to check if the write operation completed without a CRC error. The user needs to check the WR_CRC_ERR_CODE[1:0] (Status[10:9]) and WRITE_CRC_ERR (STATUS[2]) bits to determine if an error has occurred. Read Operation Done. The READ_OP_DONE status bit is activated at the end of a read operation, which means all the data is received from the card. When this bit is set, the pre-defined data bytes are read from the card or a READ TIMEOUT occurs. The software needs to send a STOP command to card if the read command is a MMC or SD card read multi-block command. This bit can be cleared by writing ‘1’ to it. When this bit is set, SDHC generates an interrupt request if the READ_OP_DONE interrupt is enabled. The user needs to clear this bit to clear the interrupt request. Writing ‘1’ to this bit clears the status. 0 Read operation in progress or incomplete 1 Read operation complete Note: When this bit is set, the user also needs to check if the read operation complete without error. The user needs to check the READ_CRC_ERR (Status[3])and TIME_OUT_READ(STATUS[0]) bits to determine if an error has occurred. 11 READ_OP_DONE 10–9 Write CRC Error Code. This indicates the CRC results from the card at the end of write WR_CRC_ERROR_CODE operations. After receiving a block of data, the card checks the CRC bit and sends the CRC status. These two bits reflect the CRC status of the recent written data. If the card returns a negative CRC status, the data is not written to the card. These two bits can be cleared by writing a value of ‘11’ to them. 00 No transmission error, CRC status is 010 (positive) 01 Transmission error, CRC status is 101 (negative) 10 No CRC response 11 Reserved Note: These bits have valid value only when the WRITE_CRC_ERR status bit (STATUS[2]) is set. 8 CARD_BUS_CLK_RUN Card Bus Clock Run. This indicates whether the MMC_SD_CLK clock to the card is running. The clock rate setting and system configuration can be modified when the clock is turned off by setting the STOP_CLK bit in STR_STP_CLK Register. This bit can only be cleared by writing ‘1’ to STOP_CLK bit in STR_STP_CLK clock control register to stop MMC_SD_CLK. 0 MMC/SD clock is stopped. 1 MMC/SD clock is running. Note: Polling needs to be done on this bit to assure the SDHC clock is running or stopped. Refer to Example 27-1. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-12 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-7. SDHC Status Register Field Descriptions (continued) Field 7 BUF_READ_READY Description Buffer Read Ready. This status is set if a buffer (either X buffer or Y buffer) is full during read operations. An interrupt is triggered for non-DMA transfers if BUF_READ_EN is set, or a DMA request is asserted for DMA transfers. Note: The read_op_done status bit will be set once all the data is read from the card. At the end of read, the buffer read ready interrupt occurs the same time as the read done. The user can service the buffer read ready interrupt and then handle the read_op_done interrupt. 0 Not ready to read buffer 1 Ready to read buffer Buffer Write Ready. This status is set if a buffer (either X buffer or Y buffer) is available during write operations. An interrupt is triggered for non-DMA transfers if the BUF_WRITE_EN bit is set, or a DMA request is asserted for DMA transfers. This bit is set only when SDHC performs a write operation to the card. 0 Not ready to write buffer 1 Ready to write buffer Response CRC Error. This indicates that a transmission error occurred on the SD_CMD line during a response transfer. Write ‘1’ to this bit to clear it. 0 No error 1 Response CRC error occurred. N/A Read CRC Error. This indicates that a transmission error occurred on the SD_DAT line during a card read. The user should re-try the transmission. Write ‘1’ to this bit to clear it. 0 No error 1 CRC read error occurred. Write CRC Error. This indicates that a transmission error occurred on the SD_DAT line during a card write operation. The user should check the WR_CRC_ERR_CODE field for more information about the CRC error. Write ‘1’ to this bit to clear it. 0 No error 1 CRC write error occurred. Time Out Response. This indicates that the command response was not received in the time specified in the RES_TO Register. This can be caused by: • An unsupported command was received at the card(s). • Another MMC/SD_OP_COND command submitted after all cards had already sent their voltage ranges and the power-up routine was finished. • An identification command issued when all cards were already in standby state. • No card is on the bus. Write ‘1’ to this bit to clear this condition. 0 No error 1 Time out response error occurred. Time Out Read. Indicates that the expected data from the card was not received in the time specified in the READ_TO Register. The TIME_OUT_READ is cleared by an internal status change or by removing the source of the error. Write ‘1’ to this bit to clear it. 0 No error 1 Time out read data error occurred 6 BUF_WRITE_READY 5 RESP_CRC_ERR 4 3 READ_CRC_ERR 2 WRITE_CRC_ERR 1 TIME_OUT_RESP 0 TIME_OUT_READ 27.3.3.3 SDHC Clock Rate Register (CLK_RATE) Refer to Section 27.4.8, “System Clock Controller” for the clock scheme. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-13 Secured Digital Host Controller (SDHC) The high frequency input clock, IPG_PERCLK, is used to derive the low frequency clock to be used by the card and some of its internal logic. The divide circuitry consists of a 4-bit divider followed by a 12-bit prescaler. The IPG_PERCLK is first divided by the 4-bit divider to derive the signal, CLK_DIV. CLK_DIV is then divided by the 12-bit prescaler to derive CLK_20M, which is the source clock to be gated for internal logic and external cards. CLK_20M is used internally by the SDHC. The MMC_SD_CLK is a buffered and gated version of the CLK_20M clock. See Figure 27-6 for an illustration of valid bits in the SDHC Clock Rate Register and Table 27-8 for descriptions of the bit fields. 0x1001_3008 (CLK_RATE1) 0x1001_4008 (CLK_RATE2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CLK_PRESCALER[15:4] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 CLK_DIVIDER[3:0] Figure 27-6. SDHC Clock Rate Register Table 27-8. SDHC Clock Rate Register Field Descriptions Field 31–16 N/A Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-14 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-8. SDHC Clock Rate Register Field Descriptions (continued) Field 15–4 CLK_PRESCALER Description Clock Prescaler. Specifies the divider value to generate CLK_20M from CLK_DIV. 0x000 CLK_20M is CLK_DIV 0x001 CLK_20M is CLK_DIV/2 0x002 CLK_20M is CLK_DIV/4 0x004 CLK_20M is CLK_DIV/8 0x008 CLK_20M is CLK_DIV/16 0x010 CLK_20M is CLK_DIV/32 0x020 CLK_20M is CLK_DIV/64 0x040 CLK_20M is CLK_DIV/128 0x080 CLK_20M is CLK_DIV/256 0x100 CLK_20M is CLK_DIV/512 0x200 CLK_20M is CLK_DIV/1024 0x400 CLK_20M is CLK_DIV/2048 0x800 CLK_20M is CLK_DIV/4096 Others Reserved Clock Divider. Specifies the divider value to generate CLK_DIV from input clock IPG_PERCLK. 0x1 CLK_DIV is IPG_PERCLK/2 0x2 CLK_DIV is IPG_PERCLK/3 0x3 CLK_DIV is IPG_PERCLK /4 0x4 CLK_DIV is IPG_PERCLK /5 0x5 CLK_DIV is IPG_PERCLK /6 0x6 CLK_DIV is IPG_PERCLK /7 0x7 CLK_DIV is IPG_PERCLK /8 0x8 CLK_DIV is IPG_PERCLK /9 0x9 CLK_DIV is IPG_PERCLK /10 0xa CLK_DIV is IPG_PERCLK /11 0xb CLK_DIV is IPG_PERCLK /12 0xc CLK_DIV is IPG_PERCLK /13 0xd CLK_DIV is IPG_PERCLK /14 0xe CLK_DIV is IPG_PERCLK /15 0xf CLK_DIV is IPG_PERCLK /16 Others Reserved 3–0 CLK_DIVIDER NOTE The maximum frequency of MMC_SD_CLK is IPG_PERCLK /2. 27.3.3.4 SDHC Command and Data Control Register (CMD_DAT_CONT) The SDHC Command and Data Control Register allows the user to specify the format of data and response, and to control the Read/Wait cycle. After configuring this register, enabling the MMC_SD_CLK will cause the command and argument configured in the CMD Number register and the CMD Argument register to be sent out to the card. See Figure 27-7 for an illustration of valid bits in the SDHC Command and Data Control Register and Table 27-9 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-15 Secured Digital Host Controller (SDHC) 0x1001_300C (CMD_DAT_CONT1) 0x1001_400C (CMD_DAT_CONT2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CMD W _RES UME Reset 0 0 0 CMD STOP STAR _RES _REA T_RE P_LO BUS_WIDTH DWAI ADW NG_ T AIT OFF 0 0 0 0 0 0 INIT 0 WRIT DATA FORMAT_OF_RESP E_RE _ENA ONSE AD BLE 0 0 0 0 0 0 0 0 0 0 Figure 27-7. SDHC Command and Data Control Register Table 27-9. SDHC Command and Data Control Register Field Description Field 31–16 15 CMD_RESUME N/A Command Resume. Used to restore Command and Data Control Register after Read/Wait cycle for SDIO card. 0 Issues command to card. 1 Does not issue command to card. N/A Command Response Long Off. Allows STATUS[13] END_CMD_RESP bit to be self cleared when the condition to generate this bit disappears. This is utilized in the Read/Wait cycle. For SD/MMC operation, the user should keep this bit set as ‘0’. 0 Bit was not cleared when read. 1 Allows bit to be cleared. Stop Read/Wait. Ends the Read/Wait cycle for SDIO. When this bit is set, the SDHC will not drive DAT2 output low so that the SDIO card would end the Read/Wait cycle. For operation of SD/MMC, the user should keep this bit set as ‘0’. 0 No effect 1 Ends Read/Wait cycle. Start Read/Wait. Starts the Read/Wait cycle for SDIO. When this bit is set, the SDHC will make the DAT2 output low and force the SDIO card to enter READWAIT cycle. For SD/MMC operation, the user should keep this bit set as ‘0’. 0 No Effect 1 Starts Read/Wait cycle. Bus Width. Specifies the width of the data bus. These two bits must be set according to current SD/SDIO card bit mode. For MMC card, only 1-bit bus mode is supported. 00 1-bit 01 Reserved 10 4-bit 11 Reserved Description 14–13 12 CMD_RESP_LONG_OFF 11 STOP_READWAIT 10 START_READWAIT 9–8 BUS_WIDTH MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-16 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-9. SDHC Command and Data Control Register Field Description (continued) Field 7 INIT Description Initialize. Specifies whether the additional 80-clock cycle prefix (to initialize the card) will occur before every command. INIT enables/disables the additional 80-clock initialization time. 0 Disable 80 initialization clocks. 1 Enable 80 initialization clocks. N/A Write/Read. Specifies whether the data transfer of the current command is a write or read. operation 0 Read 1 Write Data Enable. Specifies whether the current command includes a data transfer. 0 No data transfer included 1 Date transfer included 6–5 4 WRITE_READ 3 DATA_ENABLE 2–0 Format of Response. Sets the expected response format for current command. Refer to the SD FORMAT_OF_RESPONSE I/O Specification 1.0 for detail information of the response format. 000 No response for current command 001 48-bit response with CRC7 check. For example: Format R1/R1b/R5/R6. 010 136-bit, CSD/CID read response. For example: Format R2. 011 48-bit Response without CRC check. For example: Format R3/R4. Others Reserved 27.3.3.5 SDHC Response Time Out Register (RES_TO) The MMC/SD Response Time Out Register defines an interval within which a response must be returned, or a time-out error will occur. After the SDHC sends out a command, if the card does not respond within the specified interval, the RESPONSE TIMEOUT status bit (STATUS[1]) and the END_CMD_RESP status bit (STATUS[13]) will be set. See Figure 27-8 for an illustration of valid bits in the MMC/SD Response Time Out Register and Table 27-10 for descriptions of the bit fields. 0x1001_3010 (RES_TO1) 0x1001_4010 (RES_TO2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 RESPONSE TIME OUT[7:0] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Figure 27-8. MMC/SD Response Time Out Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-17 Secured Digital Host Controller (SDHC) Table 27-10. MMC/SD Response Time Out Register Field Descriptions Field 31–8 N/A Description 7–0 Response Time Out. This value determines the interval by which Response time-out is detected. The RESPONSE TIME OUT clock starts counting when the last bit of the command is sent. The clock counts unit is MMC_SD_CLK to card. 0x01 1 clock count 0x02 2 clock counts ... ... 0xFF 255 clock counts 27.3.3.6 SDHC Read Time Out Register (READ_TO) The MMC/SD Read Time Out Register defines an interval that read data must be returned within or a time out error will occur. After the SDHC sends out the data read command, if no data is returned within the specified interval, the READ TIMEOUT status bit (STATUS[0]) and the READ_OP_DONE status bit (STATUS[11]) will be set. See Figure 27-9 for an illustration of valid bits in the SDHC Read Time Out Register and Table 27-11 for descriptions of the bit fields. 0x1001_3014 (READ_TO1) 0x1001_4014 (READ_TO2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DATA_READ_TIME_OUT[15:0] W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 27-9. SDHC Read Time Out Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-18 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-11. SDHC Read Time Out Register Field Descriptions Field 31–16 15–0 DATA_READ_TIME_OUT N/A Data Read Time Out. This value determines the interval by which Read Data time-outs are detected. The user needs to check the timeout limit of the card and the clock frequency to configure this register. For safety, 0xFFFF is recommended. The timeout clock starts counting when the last bit of the command is sent. The count unit is MMC_SD_CLK/256. The maximum delay the SDHC can tolerate for a data timeout is related to the card clock. If the clock is 25 MHz and this register is 0xFFFF, the maximum delay which the SDHC waits will be about 670ms. If the card does not give data in 670 ms, SDHC will issue a data read time-out error and terminate the current data read operation. This is designed to meet the SD physical layer specification, with typical time-out limit to be 100ms~200ms. But for some SDIO cards, the time-out limit may be up to 1 s. In such case, the user needs to lower the MMC_SD_CLK frequency to accommodate the delay to 1 s, which requires configuring the MMC_SD_CLK to about 16 MHz and setting this register for 0xFFFF. Description 27.3.3.7 SDHC Block Length Register (BLK_LEN) The SDHC Block Length Register defines the number of bytes in a block (block size). Since the stream mode of MMC is not supported, the block length must be set for every transfer. The block length supported by the SDHC ranges from 1 bytes to 2048 bytes, but the user needs to check the block size supported by the card before configuring this register. For the SDIO, the block length must be less than the maximum block size defined in the card’s CCCR. For the SD/MMC, the block length must be less than the maximum block size defined in the card’s CSD register. NOTE The software should write to this register only when no SD bus transaction is executing. See Figure 27-10 for an illustration of valid bits in the SDHC Block Length Register and Table 27-12 for descriptions of the bit fields. 0x1001_3018 (BLK_LEN1) 0x1001_4018 (BLK_LEN2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 BLOCK LENGTH[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-10. SDHC Block Length Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-19 Secured Digital Host Controller (SDHC) Table 27-12. SDHC Block Length Register Field Descriptions Field 31–12 N/A Description 11–0 Block Length. Specifies the number of bytes in a block during data transfer (block size). For the MMC and BLOCK LENGTH SD cards, the value set must keep same as the blk_len set in the CARD. For the SDIO, the IO access is performed through the CMD53 IO_RW_EXTEND command. This command has two modes: • Byte mode. For byte mode, its operation is similar to a single block transfer command for SD where the block length is the byte count in the command argument. • Block mode. For block mode, its operation is similar to a multi-block transfer command for the SD where the block length is the block size defined in the command argument. For multi-block data transfers, a block length that is equal to an integer multiple of the data buffer size is preferred. Otherwise, the buffer utilization would be poor. If the data size that needs to be transferred is not an integer multiple of the buffer size, there are two options to transfer the data: • Option 1: The user needs to split the transaction. The remainder of block size data is transferred by using a single block command for the last transfer. • Option 2: The user needs to add filler data in the last block to fill the block size to be as large as the buffer size. The data buffer size is 64 bytes in 4-bit mode and 16 bytes in 1-bit mode.Refer to Section 27.4.1, “Data Buffers” for more information about data buffers. 0x000 0 byte 0x001 1 byte ... ... 0x7FF 2047 bytes 0x800 2048 bytes 0x801–0XFFF Reserved 27.3.3.8 SDHC Number of Blocks Register (NOB) The SDHC Number of Blocks Register defines the number of blocks in the multi-block transfer mode. This register and the Block Length Register determines the number of bytes to be transferred during one command. The number is decremented every time a block transfer is completed and stops when the count reaches zero. When all data transfers are completed, the STATUS[11] READ_OP_DONE is set if it is a read (from card) transfer, or the STATUS[12] WRITE_OP_DONE is set if it is a write (to card) transfer. The software should write to this register only when no MMC/SD transaction is executing. The NOB and the BLK_LEN defines the maximum data to be transferred in a single data transfer command. Maximum data size to be transferred in bytes = block length x number of blocks. See Figure 27-11 for an illustration of valid bits in the SDHC Number of Blocks Register and Table 27-13 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-20 Freescale Semiconductor Secured Digital Host Controller (SDHC) 0x1001_301C (NOB1) 0x1001_401C (NOB2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NOB[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-11. SDHC Number of Blocks Register Table 27-13. SDHC Number of Blocks Register Field Descriptions Field 31–16 15–0 NOB N/A Specifies the number of blocks in a block transfer. One block should be set if the data transfer command is a single block transfer command or IO_RW_EXTEND (CMD53) in byte mode. For multi-block transfer commands to SD/MMC card and IO_RW_EXTEND (CMD53) in block mode to SDIO card, this register should be set for the block count the software expected. The maximum block number to be transferred for command can be as large as 65535. Blocks can range in length from 0 to 65535 bytes. For SD Memory card or a memory parts of a SDIO combo card, the user will need to send CMD12 to stop the multi-block transfer. For a SDIO CMD53 in block mode and if user needs to abort the transfer earlier, the user needs to use CMD52 IO-Abort to abort the transfer. 0x0000 0 Block 0x0001 1 Block ... ... 0xFFFF 65535 Blocks Note: The maximum transfer blocks is 64 Kbytes. If the user uses infinite transfer command to transfer data, such as multi-block transfer command for memory card or infinite block transfer CMD53 for SDIO card, this register needs to be set to the real number of blocks that the user expected to transfer. The user also needs to abort the transfer through CMD12 or CMD52 IO-Abort to do this. Description 27.3.3.9 SDHC Revision Number Register (REV_NO) The read-only SDHC Revision Number Register is a read-only register that displays the revision number of the module. See Figure 27-12 for an illustration of valid bits in the SDHC Revision Number Register and Table 27-14 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-21 Secured Digital Host Controller (SDHC) 0x1001_3020 (REV_NO1) 0x1001_4020 (REV_NO2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 1 Revision Number[15:0] 0 0 0 0 0 0 0 0 0 0 Figure 27-12. SDHC Revision Number Register Table 27-14. SDHC Revision Number Register Field Descriptions Field 31–16 15–0 REVISION NUMBER N/A Revision Number. Specifies the revision number of the MMC/SD module. This is fixed at 0x0000_0400. Description 27.3.3.10 SDHC Interrupt Control Register (INT_CNTR) When certain events occur in the module, the SDHC has the ability to set an interrupt as well as to set corresponding Status register bits. The SDHC Interrupt Control Register allows the user to control whether these interrupts should occur. See Figure 27-13 for an illustration of valid bits in the SDHC Interrupt Control Register and Table 27-15 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-22 Freescale Semiconductor Secured Digital Host Controller (SDHC) 0x1001_3024 (INT_CNTR1) 0x1001_4024 (INT_CNTR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 SDIO _INT_ WKP _EN CARD _INSE RT_W KP_EN CAR D_R EMO VAL _WK P_E N 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CAR D_IN W SERT ION_ EN Reset 0 CAR SDIO DAT0 D_RE _IRQ _EN MOVA _EN L_EN 0 0 0 0 0 0 0 0 0 0 REA BUF_ BUF_ END_ WRITE D_O READ WRIT CMD _OP_D P_D _EN E_EN _RES ONE ONE 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-13. SDHC Interrupt Control Register Table 27-15. SDHC Interrupt Control Register Field Descriptions Field 31–19 18 SDIO_INT_WKP_EN N/A SDIO Interrupt Wake-Up Enable. When INT_CNTR[13] is set to a ‘1’ (SDIO interrupt enabled), this bit controls whether a SDIO card interrupt is detected synchronously or asynchronously. To set this bit, the SDIO card interrupt is detected asynchronously and the SDIO card interrupt is used as a wake-up event. Set this bit only in low power mode or when all the clocks to SDHC are off. 0 Disable SDIO card interrupt as wake-up event. 1 Enable SDIO card interrupt as wake-up event. 17 CARD_INSERTION_WKP_EN Card Insertion Wake-Up Enable. When INT_CNTR[15] is set to a ‘1’ (card insertion interrupt enabled), this bit controls whether a card insertion interrupt is detected synchronously or asynchronously. To set this bit, the card insertion interrupt is captured asynchronously and the interrupt is used as a wake-up event. Set this bit only in low power mode or when all the clocks to SDHC are off. 0 Disable card insertion as wake-up event. 1 Enable card insertion as wake-up event. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-23 Secured Digital Host Controller (SDHC) Table 27-15. SDHC Interrupt Control Register Field Descriptions (continued) Field 16 CARD_REMOVAL_WKP_EN Description Card Removal Wake-Up Enable. When INT_CNTR[14] is set to a ‘1’ (card removal interrupt enabled), this bit controls whether the card removal interrupt is detected synchronously or asynchronously. To set this bit, the card removal interrupt is detected asynchronously and the interrupt is used as a wake-up event. Set this bit only in low power mode or when all the clocks to SDHC are off. 0 Disable card removal as wake-up event 1 Enable card removal as wake-up event 15 CARD_INSERTION_EN Card Insertion Enable. Setting this bit enables the card insertion interrupt. Since the card detection is through the value of DAT3 data line, if this card is in 4-bit mode, any data transfers in the DAT3 line cause false card insertion interrupts to be generated. The card insertion interrupt should be disabled after the first time the card insertion is detected. To avoid the false status bit generation during data transfer, the card insertion status will be masked by this bit. It should be enabled only after the card is removed from the socket. The default of this bit is to disable the card insertion interrupt. When this interrupt is detected, the user needs to write a ‘1’ to the STATUS[31] bit to clear the card insertion status interrupt. 0 Card insertion interrupt disabled 1 Card insertion interrupt enabled Note: INT_CNTR[17] CARD_INSERTION_WKP_EN controls whether this interrupt is detected asynchronously or synchronously. 14 CARD_REMOVAL_EN Card Removal Enable. Setting this bit enables the card removal interrupt. Since card detection is through the value of the DAT3 data line, if this card is in 4-bit mode, the data transfer through the DAT3 line causes false card removal interrupt to be generated. The card removal interrupt should be enabled only when there are no active data transfers on the DAT3 line. To avoid the false status bit generation during data transfer, the card insertion status will be masked by this bit. The default of this bit is to disable the card removal interrupt. When this interrupt is detected, the user needs to write a ‘1’ to the STATUS[30] bit to clear the card removal status interrupt. 0 Card removal interrupt disabled 1 Card removal interrupt enabled Note: INT_CNTR[16] CARD_REMOVAL_WKP_EN controls whether this interrupt is detected asynchronously or synchronously. 13 SDIO_INT_EN SDIO Interrupt Enable. Masks the interrupt from the SD I/O card to the SDHC module interrupt. 0 SD I/O interrupt disabled 1 SD I/O interrupt enabled Note: INT_CNTR[18] SDIO_INT_WKP_EN controls whether this interrupt is detected asynchronously or synchronously. Data Enable. Identifies how the SD I/O interrupt is detected. An interrupt is determined by SD_DAT [1] low, but this bit is an option setting for the SDIO bit. When SDHC is preforming data transfer and the SD bus mode is 1-bit mode, the user should set this bit to ‘0’. 0 SD I/O’s Interrupt detection based on SD_DAT[3:0] = 110x 1 SD I/O’s Interrupt detection based on SD_DAT[3:0] = 1101 11–5 N/A 12 DAT0_EN MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-24 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-15. SDHC Interrupt Control Register Field Descriptions (continued) Field 4 BUF_READ_EN Description Bus Read Enable. This bit controls the Buffer Read Ready interrupt. If the bit is ‘1’, the interrupt is enabled. When the buffer becomes full during a read operation, an interrupt is generated. The user needs to move the data out of the FIFO and clear the BUF_READ_READY bit to clear the interrupt. 0 Buffer status interrupt is disabled. 1 Buffer status interrupt is enabled. Bus Write Enable. This bit controls the Buffer Write Ready interrupt. If the bit is ‘1’, the interrupt is enabled. When the buffer becomes empty during a write operation, an interrupt will be generated. The user needs to write data to the FIFO and clear the BUF_WRITE_READY bit to clear the interrupt. 0 Buffer status interrupt is disabled. 1 Buffer status interrupt is enabled. End Command Response. This bit controls the interrupt generation on the status at the end of the command response. When this bit is ‘1’, the SDHC generates an interrupt at the end of the command response status. 0 End Command-response interrupt is disabled. 1 End Command-response interrupt is enabled. Write Operation Done. This bit controls the interrupt generation for the status of write operation. When the interrupt enabled, the SDHC generates an interrupt when the configured bytes of data are transferred to the card. 0 Write_OP_DONE interrupt is disabled. 1 Write_OP_DONE interrupt is enabled. Read Operation Done. This bit controls the interrupt generation for the status of read operation completion. When the interrupt is enabled, the SDHC generates an interrupt when the pre-defined bytes of data are transferred from the card. 0 READ_OP_DONE interrupt is disabled. 1 READ_OP_DONE interrupt is enabled. 3 BUF_WRITE_EN 2 END_CMD_RES 1 WRITE_OP_DONE 0 READ_OP_DONE When an interrupt is generated, there may be some error bits in the STATUS register set as well as the interrupt status. The user needs to check the error status bit to make sure there is no error in the SDHC operation. For example, when the READ_OP_DONE (STATUS[11]) status is set or the READ_OP_DONE interrupt is detected, the user needs to check both the STATUS[3] and STATUS[0] bits as well to make sure the read operation completed without a CRC error or a time out error. Another example is a write operation, if both the WRITE_OP_DONE(STATUS[12]) and WRITE_CRC_ERR (STATUS[2]) bits are set. This means the write operation ended with CRC error. See Table 27-16 for a summary of the relationship between the interrupt, interrupt control register, and status registers in the SDHC. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-25 Secured Digital Host Controller (SDHC) Table 27-16. Interrupt Mechanisms Source STATUS Bit Name (Status Bit Number) TIME_OUT_READ (0) Does this status generate interrupt directly? No, alert by using the READ_OP_DONE bit in the SDHC Status Register No, alert by using the END_CMD_RESP bit in the SDHC Status Register No, alert by using the WRITE_OP_DONE bit in the SDHC Status Register No, alert by way of the READ_OP_DONE bit in the SDHC Status Register No, alert by using the END_CMD_RESP bit in the SDHC Status Register Yes Yes Yes Yes Yes Yes Yes Yes INT_Control Register Bit Name (INT_CNTR Bit Number) READ_OP_DONE (0) Interrupt/Status Clear Method Clear status by writing ‘1’. TIME_OUT_RESP (1) END_CMD_RES (2) Clear status by writing ‘1’. WRITE_CRC_ERR (2) WRITE_OP_DONE (1) Clear status by writing ‘1’. READ_CRC_ERR (3) READ_OP_DONE (0) Clear status by writing ‘1’. RESP_CRC_ERR (5) END_CMD_RES (2) Clear status by writing ‘1’. BUF_WR_RDY (6) BUF_READ_RDY (7) READ_OP_DONE(11) WRITE_OP_DONE(12) END_CMD_RESP(13) SDIO_INT_ACTIVE(14) CARD_REMOVAL(30) CARD_INSERTION(31) BUF_WRITE_EN (3) BUF_READ_EN (4) READ_OP_DONE (0) Clear status by writing data to FIFO buffer. Clear status by reading data from FIFO buffer. Clear status by writing ‘1’. WRITE_OP_DONE (1) Clear status by writing ‘1’. END_CMD_RESP (2) SDIO_INT_EN (13) CARD_REMOVAL_EN (14) CARD_INSERTION_E N (15) Clear status by writing ‘1’. Clear status by writing ‘1’. Clear status by writing ‘1’. Clear status by writing ‘1’. 27.3.3.11 SDHC Command Number Register (CMD) The command to the SD card is always 48 bits long. It contains one start bit, one direction bit, six command number bits, 32 argument bits, seven CRC bits, and one end bit. For more details on the format of the command, refer to the SD physical layer specification. Refer to Table 27-21 for MMC/SD/SDIO cards command list and the related card specification for the detailed information about each command. In SDHC, the command start bit, direction bit, CRC7 bits, and end bit are automatically generated by the hardware. Configure the SDHC command number register and SDHC command argument register to issue a command to the card. See Figure 27-14 for an illustration of valid bits in the SDHC Command Number Register and Table 27-17 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-26 Freescale Semiconductor Secured Digital Host Controller (SDHC) 0x1001_3028 (CMD1) 0x1001_4028 (CMD2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 COMMAND NUMBER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-14. SDHC Command Number Register Table 27-17. SDHC Command Number Register Field Descriptions Field 31–6 5–0 COMMAND Number N/A Command Number. The SDHC module communicates with the MMC/SD/SDIO card(s) by sending commands and arguments. The command to send is set in the MMC/SD Command Number Register (CMD) and the argument is defined in SDHC CMD Argument Register (ARG). See Table 27-21 for the brief information of the full list of MMC/SD/SDIO commands. 0x00 CMD0 0x01 CMD1 ... ... 0x3F CMD63 Note: The user should check the detailed information from the related card specification. Description 27.3.3.12 SDHC CMD Argument Register (ARG) This register contains the MMC/SD/SDIO command argument. See Figure 27-15 for an illustration of valid bits in the SDHC Command Argument Register and Table 27-18 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-27 Secured Digital Host Controller (SDHC) 0x1001_302C (ARG1) 0x1001_402C (ARG2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R ARG[31:16] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ARG[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-15. SDHC Command Argument Register Table 27-18. SDHC Command Argument Register Field Descriptions Field 31–0 ARG Description Command Argument. Specifies the argument for the current command. Note: The user should check the detailed command argument information from the related card specification. 27.3.3.13 SDHC Response FIFO Access Register (RES_FIFO) There is an 8 x 16 bit FIFO to store the response from the card in SDHC. This register is used to access this FIFO. The MSB 16 bits of the response is accessed first and the LSB 16 bits is accessed last. See Figure 27-16 for an illustration of valid bits in the SDHC Response FIFO Access Register and Table 27-19 for descriptions of the bit fields. 0x1001_3034 (RES_FIFO1) 0x1001_4034 (RES_FIFO2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 RESPONSE_CONTENT 0 0 0 0 0 0 0 0 0 0 Figure 27-16. SDHC Response FIFO Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-28 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-19. SDHC Response FIFO Register Field Descriptions Field 31–16 15–0 RESPONSE_CONTENT N/A RESPONSE CONTENT FIFO access register. There is a FIFO in the SDHC that is used to store the command response received from card. Every time the Host sends a command to a card, the current contents stored in the FIFO are cleared and new response arguments are stored into the Response FIFO. According to the SD card specification, the command response size can be 48 bits or 136 bits (R2 response). Refer to the SD Memory Card specification for more detailed information about the command response format. The size of Response FIFO is 8 x 16 bits (128 bits). For a 48-bit response, only 48 bits of the FIFO have valid contents. The user must perform three reads to this response FIFO access register to retrieve the entire 48-bit response content. For a 136-bit R2 Response (response for CID[127:0] or CSD[127:0] register), only the contents of the 128-bit CID and CSD register are stored in the Response FIFO. This first byte of the R2 response is not stored in the Response FIFO. The user can retrieve the CIS/CSD register from the Response FIFO through eight accesses to the FIFO access register. All the CRC bits in the response are not stored in the response FIFO. This Response FIFO is read-only. Note: The CRC7 and end bit for response is hardware checked by SDHC and the corresponding field of the response will not be stored in the response FIFOs. Description 27.3.3.14 SDHC Data Buffer Access Register (BUFFER_ACCESS) The SDHC uses two 64-byte data buffers in a ping-pong manner—while one buffer is receiving new transmission information, the other buffer is deleting the previous transmission. Data can be transferred by the DMA and the SD card simultaneously to maximize throughput between the two clock domains (that is, the IP peripheral clock, IPG_PERCLK, and the host clock, CLK_20M). These buffers are used as temporary storage for data being transferred between the host system and the card and vice versa. The user can read or write data to the buffers through this Buffer Access Register. Refer to Section 27.4.1, “Data Buffers” for more information about the data buffers. In the read operation, the SDHC stores the data received from the card into the buffer. The user needs to move the data out of the buffer when the buffer is full. In the write operation, the SDHC fetches data from the buffer and transfers them to the card. The user can then access the data buffer through the SDHC Data buffer Access Register. The user needs to move data into the buffer when the buffer is empty. See Figure 27-17 for an illustration of valid bits in the SDHC Data Buffer Access Register and Table 27-20 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-29 Secured Digital Host Controller (SDHC) 0x1001_3038 (BUFFER_ACCESS1) 0x1001_4038 (BUFFER_ACCESS2) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R FIFO CONTENT[31:16] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FIFO CONTENT[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-17. SDHC Buffer Access Register Table 27-20. SDHC Buffer Access Register Field Descriptions Field 31–0 FIFO CONTENT Description First in/First Out Content. These bits hold 32-bit data upon a read or write transfer. The size of the FIFO is 4 x 32 bits (16 bytes in total) for SD 1-bit mode and 16 x 32 bits (64 bytes in total) for SD 4-bit mode. For reception, the SDHC controller generates a DMA request when the FIFO is full. Upon receiving this request, DMA starts transferring data from the SDHC FIFO to system memory by reading the Data Buffer Access Register for a number of pre-defined bytes. For transmit, the SDHC controller generates a DMA request when the FIFO is empty. Upon receiving this request, DMA starts moving data from the system memory to the SDHC FIFO by writing to the Data Buffer Access Register for a number of pre-defined bytes. 27.4 Functional Description The following sections provide a brief functional description of the major system blocks, including the DMA interface, memory controller, logic/command controller, and system clock controller. 27.4.1 Data Buffers The SDHC uses two data buffers in a ping-pong manner so that data can be transferred by the DMA and the SD card simultaneously to maximize throughput between the two clock domains (that is, the IP peripheral clock, IPG_PERCLCK, and the host clock, CLK_20M). See Figure 27-18 for an illustration of the buffer scheme. These buffers are used as temporary storage for data being transferred between the host system and the card. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-30 Freescale Semiconductor Secured Digital Host Controller (SDHC) dma_req SDHC Registers sdhc_irq IP Bus I/F Buffer Control SD Bus I/F X Buffer Y Buffer Figure 27-18. SDHC Buffer Scheme For a host-read operation, the SDHC automatically transfers data into the next available buffer. It is then read out by the DMA and written to the system memory when the DMA request from SDHC becomes highest priority in the DMA arbiter. Conversely, for a host-write operation, the DMA writes data into the next available buffer. The SDHC then reads the data out of the buffer and writes it to the card through the SD Host interface. 27.4.1.1 Data Buffer Access DMA/CPU accesses the data buffer of SDHC through the 32-bit Data Buffer Access (DBA) register. Internally, the SDHC maintains a pointer into the data buffer. Accesses to the DBA register will increase the address value of the pointer. The pointer value of SDHC is not directly accessible by the software. The pointer refers to a 32-bit port-size FIFO, so all the access to the FIFO must be 32-bit size. Sequential and contiguous access is necessary to increase the pointer address value correctly. Random or skipped access is not allowed. In some cases, when the block length of the data transfer is not a multiple of 32 bits, the last data access to the FIFO may be 24-bit, 16-bit or 8-bit. Since SDHC FIFO allows only 32-bit access sizes, the user must put/get the data bytes on the correct byte lanes of the SDHC 32-bit data bus. The byte arrangement order is little endian format. For an 8-bit data access to the FIFO, it will be in bit[7–0] of the data bus. For 16-bit data access, the data will be in the bit[15–0] of the data bus. For a 24-bit data access, the data will be in the bit[23–0] of the data bus. When data goes to the card, the 32-bit data in the data buffer FIFO will be shifted out to card from the LSB byte to the MSB byte, but for each byte, the bit sequence of the shift will be from MSB bit to LSB bit. When read data leaves the card, the data shifted in will be stored from LSB byte to MSB byte in the data buffer FIFO. See Figure 27-19 for the bytes lane relationship between the card bus and SDHC IP bus. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-31 Secured Digital Host Controller (SDHC) Data on System IP Bus 31–24 23–16 15–8 7–0 Shift out to the Card or shift in from the card 7–0 15–8 23–16 31–24 Figure 27-19. Byte Lanes Relationship Between System IP Bus and SD Card Bus 27.4.1.2 Write Operation Sequence There are two ways to write data to the buffer when the user transfer data to the card. One way is by using DMA through the SDHC DMA request signal. The other way is by using the CPU through the BUF_WR_RDY (STATUS[6]) bit (interrupt or polling). The SDHC asserts a DMA request when the data buffer is empty and ready to receive new data. At the same time, the SDHC would set the BUF_WR_RDY (STATUS[6]) bit. The buffer write ready interrupt will be generated if it is enabled by the software. The buffer accumulates the data written through the data port until the data count reaches the buffer size. The SDHC will not start data transmission until a full buffer size of data is written to the data buffer. The SDHC will start data transmission when the SD bus is ready for new transfer. When the other buffer is empty and more data is to be transferred, the SDHC will assert a new DMA request and set the BUF_WR_RDY bit. In case the DMA does not keep up with moving data into the FIFOs, the SDHC will stop the SD_CLK at the block gap to avoid an data buffer underrun situation. 27.4.1.3 Read Operation Sequence There are two ways to fetch data from the buffer when the user read data from the card. One way is by using DMA through the SDHC DMA request signal. The other way is by using the CPU through the BUF_READ_RDY (STATUS[7]) bit (interrupt or polling). The SDHC asserts a DMA request when data buffer is full and ready for DMA/CPU to fetch the data out of the buffer. At the same time, the SDHC would set the BUF_WR_RDY (STATUS[7]) bit. The buffer write ready interrupt will be generated if it is enabled by the software. The SDHC starts receiving data only when either of the dual data FIFO is empty. The buffer accumulates data read from the card until the data count reaches the buffer size. The SDHC asserts a DMA request when either one of the data buffer is full. For multiple block data transfers, while the DMA/CPU is moving data by reading the DBA register, the SDHC will receive data into the other FIFO if it is empty and the SD bus is ready. In case the DMA/CPU does not keep up with reading data out of the FIFOs, the SDHC will stop the SD_CLK at the block gap to avoid an overflow situation. 27.4.1.4 Data Buffer Size The user needs to know the buffer size for buffer operation during data transfer. In SDHC, both of two data buffers are 64 bytes in size. Each data buffer is divided into four 16 bytes data buffers that correspond to MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-32 Freescale Semiconductor Secured Digital Host Controller (SDHC) the four data lines of SD bus. Thus, each data line in SDHC contains a dual 16-byte buffer. The data buffer size will be 64 bytes in 4-bit SD mode or 16 bytes in 1-bit SD mode. During multi-block data transfer, the block length, which is an integer multiple of the buffer size is preferred. The buffer would be ready to read by CPU/DMA when either of the buffer is full (STATUS[27] or STATUS[26] is set, and STATUS[7] is set) when full buffer data is written to either of the X or Y buffer. The buffer would be ready to write by CPU/DMA (STATUS[29] or STATUS[28] is set, and STATUS[6] is set) when the full buffer of data is fetched out of the buffer. The buffer ready status bit and DMA request would be set accordingly. For single-block data transfer, when the block length is smaller than the buffer size or when the block length is not an integer multiple of the buffer size, it is possible that the data size that needs to be written to the buffer or to be fetched out of the buffer is smaller than the buffer size. In this case, the buffer would be full (SDHC set STATUS[27] or STATUS[26]) when this data is written to the buffer. The buffer would be empty (SDHC set STATUS[29] or STATUS[28]) when this buffer of data is fetched out of the buffer. The buffer ready status bit and DMA request would be set accordingly. From the software aspect, the buffer size become variable and equal to the real data size that needs to be transferred. This will ease the software programming of SDHC. The user does not need to fill dummy data to make the buffer full. 27.4.1.5 Dividing Large Data Transfer This SDIO command CMD53 definition limits the maximum data size of data transfers according to the following formula: Maximum data size = block size x block count The block size can be a multiple of the size of the data buffer. However, it is recommended the block size be set equal to the size of data buffer. This allows the SDHC to stop the SD_CLK during block gaps of an overflow or underrun condition occurs. Stopping the SD_CLK while the DATA lines are active may cause data corruption (when the clock resumes) on some card designs available on the market. If an application or Card Driver is to transfer larger sizes of data, the Host Driver will divide larger data sizes into multiple blocks. The length of a multiple block transfer needs to be in block size units. If the total data length cannot be divided evenly to a multiple of the block size, then there are two ways to transfer the data depending on the function and card design. One way is for the Card Driver to split the transaction. The remainder of block size data is then transferred by using a single block command at the end. Another way is to add dummy data in the last block to fill the block size. In the second method, the card must be able to remove the dummy data. See Figure 27-20 for an example that shows dividing of large data transfers. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-33 Secured Digital Host Controller (SDHC) 544 Bytes WLAN Frame 802.11 MAC Header IV Frame Body ICV FCS WLAN Frame is divided equally into 64-byte blocks plus the remainder 32 bytes Data 64 bytes Data 64 bytes Data 64 bytes Data 32 bytes SDIO Data block #1 SDIO Data block #2 SDIO Data block #8 SDIO Data 32 bytes Eight 64-byte blocks are sent in Block transfer mode and the remainder 32 bytes are sent in Byte Transfer mode SDIO Data block #1 CMD53 SDIO Data block #2 SDIO Data block #8 CMD53 SDIO Data 32 bytes Figure 27-20. Example for Dividing Large Data Transfer 27.4.2 DMA Interface The DMA interface block controls all data routing between the external data bus (DMA access), internal SDHC module data bus, and internal system FIFO access through dedicated state machine. This state machine monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the SDHC module and the application. See Figure 27-21 for an illustration of the DMA interface block. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-34 Freescale Semiconductor Secured Digital Host Controller (SDHC) FIFO Empty/Full Control Byte Counter/ Block Counter ram_addr Host/DMA R/W Access Handler DMA_INF ram_rw Reg File RAM 32x4 EFB/FFB control FIFO Status Data path Multiplexer ram_data R/W from Appl. R/W from Host Handshake to Host Host Status FSM EFB, FFB for Appl. EFB, FFB for Host mmc_dreq_b data_in data_out Figure 27-21. DMA Interface Block In addition, this block also handles the burst request to the external DMA controller, internal register write-error detection, Read/Wait handling of SDIO, and all IP-related output responses. 27.4.2.1 DMA Request If the SDHC is in the data transfer state, the SDHC generates DMA requests according to its buffer status. During read operations, the SDHC generates DMA requests if one of its data buffer is full. During write operations, the SDHC generates DMA requests if one of its data buffers is empty. To avoid buffer under-run conditions during a write operation, the MMC_SD_CLK stops automatically when both buffers are empty. After the DMA or CPU completes writing data into one of the buffers, the MMC_SD_CLK automatically resumes to continue the data transfer. Similarly, to avoid buffer overflow during read operations, the MMC_SD_CLK stops automatically when both buffers are full. After the DMA or CPU moves the data out of the buffer, the MMC_SD_CLK automatically resumes to continue the data transfer. 27.4.3 Memory Controller This controller provides the SDIO-IRQ and Read/Wait service handling, card detection, command response handling, and all SDHC interrupt handling. The memory controller also contains the register table. See Figure 27-22 for an illustration of the block diagram for the memory controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-35 Secured Digital Host Controller (SDHC) Memory Controller Application Bus DATA from Post-Processor SDIO-IRQ Interrupter and Card Detection Circuitry Interrupt Handler sdhc_irq_b Configuration Register Handler IPG_CLK SDIO-Read/Wait logic Data CMD from Post-Processor Operation Operation Pause Resume Command Response Circuitry Figure 27-22. Memory Controller Block Diagram A summary of events when a SDIO card generates an interrupt is detailed in this section. When an SDIO card generates an interrupt request, it sets its interrupt pending bit in the CSR register and asserts the interrupt line, which is shared with DAT[1] line in 4-bit mode. The SDHC detects and steers the card’s interrupt to the selected IRQ line and to the interrupt controller. 27.4.4 27.4.4.1 SDIO Card Interrupt Interrupts in 1-Bit Mode In this case, the SD_DAT[1] pin is dedicated to providing the interrupt function. An interrupt is asserted by pulling the SD_DAT[1] low until the host clears the interrupt. 27.4.4.2 Interrupt in 4-Bit Mode Since the interrupt and data line 1 share pin 8 in 4-bit mode, an interrupt will be sent by the card and recognized by the host only during a specific time. This is known as the interrupt period. The SDHC samples the level on Pin 8 only during the interrupt period. At all other times, the host interrupt controller ignores the level on Pin 8. The definition of the interrupt period is different for operations with single block and multiple block data transfers. In the case of normal single data block transmissions, the interrupt period becomes active two clock cycles after the completion of a data packet. This interrupt period lasts until after the card receives the end bit of the next command that has a data block transfer associated with it. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-36 Freescale Semiconductor Secured Digital Host Controller (SDHC) For multiple block data transfers in 4-bit mode, there is limited time that the interrupt period can be active because of the limited period of data line availability between the multiple blocks of data. This requires a more strict definition of the interrupt period. For this case, the interrupt period is limited to two clock cycles. This period begins two clock cycles after the end bit of the previous data block. During this two-clock cycle interrupt period, if an interrupt is pending, the SD_DAT[1] line is held low for one clock cycle and the last clock cycle pulling SD_DAT[1] high. On completion of the interrupt period, the card releases the SD_DAT[1] line into the high Z state. When in 4-bit mode, the SDHC differentiates a data start bit and the interrupt period by checking that all four data lines are low for the start of new data. In the case of an interrupt, only the DAT[1] should have gone low. After the last data block is sent, the interrupt period starts as normal. The interrupt period ends after the next command with data instead of lasting only two cycles. Refer to SDIO Card Specification v1.0 for further information about SDIO card interrupt. 27.4.4.3 Card Interrupt Handling When the SDIO bit in the Interrupt Control Register is set to 0, the Host Controller clears the interrupt request to the system Interrupt Controller. The SDIO Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to ‘1’. The Host Driver should clear the SDIO Interrupt enable bit before servicing the SDIO Interrupt. The Host Driver should set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. The SDIO Status bit is cleared by resetting the SDIO interrupt. Writing to this bit has no effect in 1-bit mode, as the Host Controller detects the SDIO Interrupt with or without SD clock (to support wake-up). In 4-bit mode, the interrupt signal is sampled during the interrupt period. There are some sample delays between the interrupt signal from the SDIO card and the interrupt to the Host System Interrupt Controller. When the SDIO status has been set and the Host Driver needs to start this interrupt service, the SDIO bit in the Interrupt Control Register is set to ‘0’ to clear the SDIO interrupt status latched in the SDHC and to stop driving the interrupt signal to the System Interrupt Controller. The Host Driver must issue a CMD52 to clear the interrupts at the card. After completion of the card interrupt service, the SDIO Interrupt Enable bit is set to ‘1’. The SDHC starts sampling the interrupt signal again. • Figure 27-23 (a) shows the SDIO card interrupt scheme. • Figure 27-23 (b) shows the sequences of software and hardware events that occur during the card interrupt handling procedure. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-37 Secured Digital Host Controller (SDHC) IP Bus IRQ to CPU Start Enable card IRQ in Host SDHC Registers SDIO IRQ Status SDIO IRQ Enable Command/ Response Handling Detect and steer card IRQ Read IRQ Status Register IRQ Detecting and Steering Disable Card IRQ in Host SD Host SDIO Card Interrogate and service Card IRQ Response Error? SDIO Card IRQ Routing IRQ0 IRQ1 Enable card IRQ in Host Clear IRQ1 End a) b) No Clear Card IRQ in Card Yes Function 0 Clear IRQ0 Function 1 Figure 27-23. a) Card Interrupt Scheme; b) Card Interrupt Detection and Handling Procedure 27.4.5 Card Insertion and Removal Detection SDHC uses the SD_DAT[3] pin to detect card insertion or removal. To utilize this feature of the SDHC, the chip level integration needs to pull down this pad as a default state. When there is no card on the MMC/SD bus, the SD_DAT[3] defaults to a low voltage level. When any card is inserted or removed from the socket, SDHC detects the logic value changes on the SD_DAT[3] pin and generates an interrupt. Since the mechanism is based on the value of the SD_DAT[3] line, only single-card systems can benefit from card detection. To avoid the conflict of card insertion/removal detection and the data value changes on SD_DAT[3] because of data transfer, the user should disable the Card Insertion interrupt when there is a card detected in the socket but enable the interrupt when the card is removed from the socket. The card removal interrupt can be enabled only when there is no bus activity on SD_DAT[3]. To avoid the false status bit generation during data transfer, the card insertion/removal is masked by the corresponding interrupt enable bit in INT_CNTR register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-38 Freescale Semiconductor Secured Digital Host Controller (SDHC) NOTE The user can send a command (ACMD42 for SDMem or CMD52 for SDIO) to the card to disable the card internal pull-up resistor after card detection and identification. Since the SD protocol requires that the DAT line must be pulled up for data transfer, the user must disable the host side of the SD_DAT[3] pull-down feature and configure it as pull-up. In the meantime, if the card internal pull-up resistor is disabled, the card removal interrupt can not be detected through SD_DAT[3]. 27.4.6 Power Management and Wake-Up Events When there is no operation between SDHC and the card through SD bus, the user can disable the ipg_clk and ipg_perclk in chip level clock control module to save power. When the user needs to use SDHC or communicate with the card, he or she can enable the clock and perform the operation. In some circumstances, when the clocks to SDHC are disabled, or when system is in low power mode, there are some events when the user needs to enable the clock and handle the event. These events are called wake-up interrupts. SDHC can generate these interrupts even if there are no clocks enabled. The three interrupts which can be used as wake-up events are: • Card Removal Interrupt • Card Insertion Interrupt • SDIO card interrupt The SDHC offers a power management feature. By clearing the clock-enabled bits in the Clock Control Register, the clocks are gated in the low position to the SDHC. For maximum power saving, the user can disable all the clocks to SDHC when there is no operation in progress. While in this state, it is possible that interrupts can occur that require the SDHC to respond. These interrupts are called wake-up events and are defined as follows: • Wake-Up Event on SD Card Removal through card removal interrupt • Wake-Up Event on SD Card Insertion through card insertion interrupt • Wake-Up Event on Card Interrupt through SDIO interrupt These three wake-up events (or wake-up interrupts) can be also used to wake the system from low-power modes. NOTE To make the interrupt as a wake-up event when all the clocks to SDHC are disabled or when whole system is in low power mode, the corresponding wake-up enabled bit needs to be set. Refer to Section 27.3.3.10, “SDHC Interrupt Control Register (INT_CNTR)” for more information on SDHC Interrupt Control register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-39 Secured Digital Host Controller (SDHC) NOTE According to the SDIO specification, if the user wants the card interrupt to wake up from low power mode (no clock to SDIO card), the card should be set to 1-bit mode through CMD52. 27.4.6.1 Dynamic Voltage/Frequency Scaling (DVFS) Operation Any change in ipg_perclk impacts the MMC/SD/SDIO transfer clock rate. 27.4.6.2 Setting Wake-Up Events For the SDHC to respond to a wake-up event, the software must set the respective wake-up enable bit before the CPU enters sleep mode. Before the software disables the host clock, it should ensure that all of the following conditions have been met: • No Read or Write Transfer is active. • Data and Command lines are not active. • No interrupts are pending. • Internal FIFOs are empty. The software is responsible to ensure that the clock to the SDHC is fully operational before making accesses to the peripheral. 27.4.7 Command/Data Interpreter Command and Data Interpreters are based on similar principles. Both devices consist of three parts: • Inner State Machine • Sub-module controller • CRC hardware accelerator The CMD Interpreter handles everything related to Command Line (CMD). The CMD Interpreter includes Command data sequence generation, Command response extraction, CRC generation and checking, and a Response Time-out detection. To achieve the above functions, a state machine, a logic control, and a CRC accelerator are used. See Figure 27-24 for an illustration of the block diagram for the Command Interpreter. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-40 Freescale Semiconductor Secured Digital Host Controller (SDHC) CRC_IN CMD Sampler CMD OFF CMD port CMD CRC_REG CMD_REG RESP_FIFO CMD_CFG READWAIT_CFG DAT_CFG DAT_FIFO DAT_REG CMD_SR FSM for CMD Packet Route and Content Extraction FSM for DAT DAT_SR IRQ Extractor DAT Sampler DAT OFF CRC_REG DAT Port DAT[3:0] CRC_IN IRQ_CFG Figure 27-24. Block Diagram for Command Interpreter See Figure 27-25 for an illustration of the structure for the Command CRC Shift Register. CLR_CRC ZERO CRC_IN CRC Bus [0] CRC Bus [1] CRC Bus [2] CRC Bus [3] CRC Bus [4] CRC Bus [5] CRC Bus [6] CRC OUT Figure 27-25. Command CRC Shift Register (DATs Has Similar Structure) To minimize the gate count, the internal command shift register is re-used for the CRC shift register. The polynomials for the CMD and the DAT are as follows: For the CMD: Generator polynomial: G(x) = x7 + x3 + 1 M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0 CRC[6:0] = Remainder [(M(x) * x7) / G(x)] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-41 Secured Digital Host Controller (SDHC) For the DAT: Generator polynomial: G(x) = x16 + x12 + x5 +1 M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0 CRC[15:0] = Remainder [(M(x) * x16) / G(x)] 27.4.8 System Clock Controller There are two clock domain in SDHC. One is IPG_PERCLK and the other is IPG_CLK. On the IPG_PERCLK domain, there is one clock divider and one clock prescaler in SDHC to divide the high frequency input clock IPG_PERCLK to a low frequency clock, which can be used by card and most of the logic of SDHC. See Figure 27-26. The input clock first goes through a 4-bit divider and then a 12-bit prescaler to generate a clock named CLK_20M. This clock is used internally by SDHC for DAT line control, CMD line control and almost all the functional logic. The MMC_SD_CLK to the card, which is a gated version of CLK_20M, has the same clock frequency as CLK_20M. CLK_20M is derived from the CLK_DIV by using the 12-bit prescaler. The CLK_DIV is derived from the input clock IPG_PERCLK by using the 4-bit divider. SDHC clock rate register controls the divide rate for both the divider and the prescaler. Refer to Section 27.3.3.3, “SDHC Clock Rate Register (CLK_RATE)” for the clock rate register information. The IPG_CLK is of the MCU clock domain and used for SDHC registers/FIFO read write access. To maximize power-saving during the operation, the SDHC bus clock pauses and resumes according to the SDHC status. For example, when the FIFO is full during the Card Read operation, the bus clock is stopped if no further data is written to the FIFO by the card. The bus clock is resumed when the FIFO empty status is cleared by the user (DMA). Also, there are other conditions where the SDHC stops the clock to save power. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-42 Freescale Semiconductor Secured Digital Host Controller (SDHC) IPG_PERCLK CLOCK DIVIDER CLK_DIV Clock prescaler DMA Handler IPG_CLK CLK_20M Register Table Memory Controller FIFO Gating CMD Controller DAT Controller MMC_SD_CLK DAT/CMD Transceiver Figure 27-26. Clock Used in SDHC The controller controls the rate of the card clock MMC_SD_CLK and checks whether it is on or off. The clock is turned off by setting the bit[0] of the STR_STP_CLK register and is turned on by setting the bit[1] of the STR_STP_CLK. To change the clock rate, the application must write a new value in the CLK_RATE register. 27.4.9 DAT/CMD Transceiver The transceiver unit is designed to do the following: • Control the I/O buffers. • Synchronize the input data to the system clock domain. The bi-directional signals CMD and DAT are each connected by OE, OEB, IN, and OUT. OUT and OEB are used for the high-impedance state output buffer, while OE and IN are used for the input buffer. The use of OE allows the input to be disabled during floating and minimizes the current consumption. The data buffers are in the system clock domain but the input data is in the MMC_SD_CLK clock domain. The transceiver will synchronize the input data to system clock domain. 27.5 Initialization/Application of SDHC This section provides initialization and application information for SDHC. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-43 Secured Digital Host Controller (SDHC) All communication between system and cards are controlled by the host. The host sends commands of two types: broadcast and addressed (point-to-point) commands. Broadcast commands are intended for all cards, such as: “Go_Idle_State”, “Send_Op_Cond”, “All_send_CID” and “Set_relative_Addr”. In Broadcast mode, all cards are in the open-drain mode to avoid bus contention. If the socket support only one card, the broadcast command is similar as the point-to-point command. After the Broadcast command “Set_relative_Addr” is issued, the cards enter standby mode. Addressed type commands are used from this point. In this mode, the CMD/DAT I/O will return to push-pull mode, to have the driving capability for maximum frequency operation. The MMC and the SD are similar products. Other than the 4x bandwidth, they are being programmed similarly. The following example will show how to “initialize” and perform “content access” and “content protection” on the cards. To improve the readability, we are going to use a program-like function for Example 27-1. Example 27-1. MMC_SD_CLK Control The MMC_SD_CLK clock to the card is controlled by STR_STP_CLK register. The clock should be supplied to the card for: • Submitting command to card and receive response • Transferring data between SDHC and the card • Detecting an interrupt from a SD card in 4-bit The steps below show how to start the MMC_SD_CLK to card: 1. Write 0x2 to STR_STP_CLK register. 2. Polling STATUS[8], wait until clock starts. The steps below show how to stop MMC_SD_CLK to card: 1. Write 0x1 to STR_STP_CLK register. 2. Polling STATUS[8], wait until clock is stopped. NOTE The user should not change the ipg_clk_gating_disable and ipg_perclk_gating_disable bits when start and stop MMC_SD_CLK. And if the SDHC clock gating features is used by 27.5.1 Command Submit—Response Receive Basic Operation This section shows the program flow used to submit a command to the card(s). The commands are as follows: • —the targeted command • —the corresponding argument MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-44 Freescale Semiconductor Secured Digital Host Controller (SDHC) • • —the command configuration required —the interrupt control used in the user program. The steps below show how to submit a command to the card: 1. Start MMC_SD_CLK if it is stopped 2. Enable END_CMD_RESP interrupt by write 0 to INT_CNTR[2]. 3. Set command number to CMD register. 4. Set the command argument to ARG register. 5. Set the appropriate value to Command Data control register (CMD_DAT_CONT). 6. Wait for the end command response interrupt and check for the response CRC/time-out status. 7. Read the response from the response FIFO to check the response. Read three or eight times from the response FIFO access register, depending upon whether the response is 48-bit or 136-bit. 8. Stop the MMC_SD_CLK if the clock is not needed (if there is data transfer following the command/response transfer, the clock should not be stopped until the data transfer completes). This following is a function defining command submission. This function will be used in the examples in the following subsection: send_cmd_wait_resp(command_no, arg, cmd_dat_cont, int_cntr_value) { write_reg(STR_STP_CLK, 0x02);//1. to start mmc_sd_clk read_reg(STATUS); while(!STATUS[8]) Read_reg(STATUS); // 2. Wait till the clock has started write_reg(COMMAND, );// 3. configure the CMD write_reg(ARG, );//4. configure the command argument write_reg(CMD_DAT_CONT, );//5. configure the command data control register, writing to this register will trigger SDHC send command to the card. while(irq_status);// 6. Wait interrupt (End Command Response) Write_reg(INT_CNTR, );//7. negate the irq request from SDHC read_reg(STATUS); //8. Check whether the interrupt is an End_CMD_RES or a response time out or a CRC error. write_reg(STR_STP_CLK, 0x001);// 9. Stop the card clock if the clock is not needed any longer for this cmd read_reg(STATUS); while(STATUS[8]) Read_reg(STATUS); // 10. Wait till the clock is stopped, command - response end. read_reg(RES_FIFO); // 11. read the response fifo to determine if the command has a response } 27.5.2 Card Identification Mode When a card is inserted to the socket or the card was reset by the host, the host needs to validate the operation voltage range, identify the cards, and request the cards to publish the Relative Card Address (RCA) or to set the RCA for the MMC cards. All data communications in the Card Identification mode use the command line (CMD) only. 27.5.2.1 Card Detect See Figure 27-27 for flow diagram showing the detection of card using the host controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-45 Secured Digital Host Controller (SDHC) enable card detection irq (1) Wait SDHC interrupt No card present check status[31] Yes, card present write INT_CNTR to disable card detection irq (2) Voltage validation Figure 27-27. Flow Diagram for Card Detection • • Write ‘1’ to INT_CNTR[15] to enable card detection interrupt Write ‘0’ to INT_CNTR[15] to disable card detection interrupt 27.5.2.2 Reset The host consists of three types of reset: • Hardware reset (card and host), which is driven by POR (power on reset). • Software reset (host Only), which is preceded by the write operation on register “STR_STP_CLK”. Follow the recommended sequence as specified in Section 27.3.3.3, “SDHC Clock Rate Register (CLK_RATE).” The reset will reset all the SDHC registers, but will not reset the card. The card reset is through CMD0. Once the user applies the software reset to SDHC, it should also be using CMD0 to reset the card in case the card is in unknown state. • Card reset (card only). The command, Go_Idle_State, CMD0 is the software reset command for both the MMC and the SD Memory Card. This sets each card into Idle State regardless of the current card state. When used as a SD I/O card, CMD52 is used to write IO reset in CCCR. The cards are initialized with a default relative card address (RCA=0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability). After the card is reset, the host needs to validate the voltage range of the card. See Figure 27-28 for the software flow to reset both SDHC and the card. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-46 Freescale Semiconductor Secured Digital Host Controller (SDHC) write 0x08 to STR_STP_CLK write 0x9 to STR_STP_CLK write 0x1 to STR_STP_CLK 8 times write 0x3F to CLK_RATE register send CMD0/CMD52 to card to reset card Voltage Validation Figure 27-28. Flow Chart for Reset of SDHC and SD I/O Card software_reset() { write_reg(STR_STP_CLK, 0x8); write_reg(STR_STP_CLK, 0x9);// 1. reset the SDHC host; write_reg(STR_STP_CLK, 0x1); write_reg(STR_STP_CLK, 0x1); write_reg(STR_STP_CLK, 0x1); write_reg(STR_STP_CLK, 0x1); write_reg(STR_STP_CLK, 0x1); write_reg(STR_STP_CLK, 0x1); write_reg(STR_STP_CLK, 0x1); write_reg(STR_STP_CLK, 0x1);// 2. write 0x1 to STR_STP_CLK 8 times; write_reg(CLK_RATE, 0x3F);// 3. Set the lowest clock for initialization write_reg(READ_TO, 0x2DB4);// 4. set READ timeout register send_cmd_wait_resp(CMD_GO_IDLE_STATE, 0x0,0x80, 0x40); //5. reset the card with CMD0 } 27.5.2.3 Voltage Validation All cards must be able to establish communications with the host using any operation voltage in the maximum allowed voltage range specified in this standard. However, the supported minimum and maximum values for Vdd are defined in Operation Conditions Register (OCR) and might not cover the entire range. Cards that store the CID and CSD data in the preload memory are able to communicate the information only under data transfer Vdd conditions. That means if the host and card have non-compatible Vdd ranges, the card will not be able to complete the identification cycle, nor be able to send CSD data. Commands such as Send_Op_Cont (CMD1 for MMC), SD_Send_Op_Cont (CMD41 for SD Memory), and IO_Send_Op_Cont (CMD5 for SD I/O) are designed to provide a mechanism to identify and reject cards that MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-47 Secured Digital Host Controller (SDHC) do not match the Vdd range desired by the host. This is accomplished by the host sending the required Vdd voltage window as the operand of this command. Cards that can not perform data transfer in the specified range must detach themselves from further bus operations and go into the inactive state. By omitting the voltage range in the command, the host can query each card and determine the common voltage range before sending out-of-range cards into the inactive state. This query should be used if the host is able to select a common voltage range or if a notification to the application of non-usable cards in the stack is desired. The following steps show how to perform voltage validation when a card inserted: voltage_validation(voltage_range_arguement) { send_cmd_wait_resp(IO_SEND_OP_COND, 0x0, 0x04, 0x40); // CMD5, send SDIO operation voltage, command argument is zero if(End Command Response true & No. of IO functions> 0)// it is SDIO and have IO function {IORDY = 0; while(!(IORDY in I/O ORC response)) {// set voltage range for each IO send_cmd_wait_resp(IO_SEND_OP_COND, voltage_range_arguement, 0x04, 0x40);} if(Memory Present flag true) Card = combo; // that is, SDIO + SD Memory, need to set operation voltage to memory portion as well send_cmd_wait_resp(APP_CMD, 0x0, 0x01, 0x40);// CMD55, Application Command follows send_cmd_wait_resp(SD_APP_OP_COND, voltage_range_arguement, 0x01, 0x40);//ACMD41 else Card = sdio; // if No response to CMD5 IO_SEND_OP_COND or No. of IO Function is zero in response else// the card should be SD or MMC {send_cmd_wait_resp(APP_CMD, 0x0, 0x01, 0x40);// CMD55, Application Command follows if(End Command Response true and no response timeout) {send_cmd_wait_resp(SD_APP_OP_COND, voltage_range_arguement, 0x01, 0x40); // ACMD41, SD card found Card = sd; } else // the card have no response to APP_CMD, it is not SD card {send_cmd_wait_resp(SEND_OP_COND, voltage_range_arguement, 0x01, 0x40); //CMD1, MMC card found if(End Command Response true and no response timeout) {Card = mmc;} else{ Card = No card or failed contact;} } } 27.5.2.4 Card Registry Card registry between MMC and SD card is different. For the SD card, the identification process starts at clock rate Fod (below 400 kHz for most of the card) as defined by the card specification. After the bus is activated, the host requests the card to send valid operation conditions. The response to ACMD41 is the operation condition register of the card. The same command is sent to all of the new cards in the system. Incompatible cards are put into the inactive state. The host then issues the command, All_Send_CID (CMD2), to each card to get its unique card MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-48 Freescale Semiconductor Secured Digital Host Controller (SDHC) identification (CID) number. Cards that are currently unidentified (that is, in Ready State), send their CID number as the response. After the CID is sent by the card, the card goes into the identification state. The host then issues Send_Relative_Addr (CMD3), requesting the card to publish a new relative card address (RCA), which is shorter that CID. This ID is used to address the card for future data transfer operations. Once the RCA is received, the card state changes to the stand-by state. At this point, if the host wants the card to have an alternative RCA number, it may ask the card to publish a new number by sending another Send_Relative_Addr command to the card. The last published RCA is the actual RCA of the card. The host repeats the identification process with CMD2 and CMD3 for each card in the system. For the MMC operation, the host starts the card identification process in open-drain mode with the identification clock rate Fod. (Fod is the initialization clock frequency defined by the card specification.) The open-drain driver stages on the CMD line allow parallel card operations during card identification. After the bus is activated, the host requests the cards to send their valid operation conditions (CMD1). The response to CMD1 is the ‘wired OR’ operation on the condition restrictions of all cards in the system. Incompatible cards are sent into inactive state. The host then issues the broadcast command All_Send_CID (CMD2), asking all cards for their unique card identification (CID) number. All unidentified cards (that is, those which are in Ready State) simultaneously start sending their CID numbers serially, while bit-wise is monitoring their outgoing bitstream. These cards, for which outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CIDs immediately. They must wait for the next identification cycle. Since the CID is unique for each card, only one card can successfully send its full CID to the host. This card then goes into identification state. Thereafter, the host issues Set_Relative_Addr (CMD3) to assign a relative card address (RCA) to this card. Once the RCA is received, the card state changes to the stand-by state, does not react to further identification cycles, and its output switches from open-drain to push-pull. The host repeats the process, that is, CMD2 and CMD3, until the host receives the timeout condition to recognize completion of the identification process. card_registry() { while (ResponseTO from STATUS){ if(card==combo or sdio) { send_cmd_wait_resp(SET_RELATIVE_ADDR, 0x00, 0x01, 0x40); //card publish the RCA in response rca = SDIO_RCA = address from response FIFO; } else if(card==sd) { send_cmd_wait_resp(ALL_SEND_CID, 0x00, 0x02, 0x40); send_cmd_wait_resp(SET_RELATIVE_ADDR, 0x00, 0x01, 0x40); //card publish the RCA in response rca = SD_RCA = address from response FIFO; } else if(card==mmc) { send_cmd_wait_resp(ALL_SEND_CID, 0x00, 0x00, 0x02, 0x40); rca = MMC_RCA = 0x1; send_cmd_wait_resp(SET_RELATIVE_ADDR, MMC_RCA_arguement, 0x01, 0x40); } MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-49 Secured Digital Host Controller (SDHC) else exit due to card not identified; } send_cmd_wait_resp(SELECT_CARD, RCA_arguement, 0x41, 0x40); } 27.5.3 27.5.3.1 27.5.3.1.1 Card Access Block Access—Block Write and Block Read Block Write During block write (CMD24–27), one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host. A card supporting block write will always be able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails, the card shall indicate the failure on the DAT line. The transferred data is discarded and not written, and all further transmitted blocks (in multiple-block write mode) will be ignored. If the host uses partial blocks for which accumulated length is not block aligned and block misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card detects the block misalignment error and aborts programming before the beginning of the first misaligned block. The card sets the ADDRESS_ERROR error bit in the status register, and, while ignoring all further data transfer, waits in the Receive-data-State for a stop command. The write operation is aborted if the host tries to write over a write-protected area. In this case, however, the card sets the WP_VIOLATION bit. Programming of the CID and CSD registers does not require a previous block length setting. The transferred data is also CRC-protected. If a part of the CSD or CID register is stored in ROM, this unchangeable part must match the corresponding part of the receive buffer. If this match fails, the card reports an error and does not change any register contents. Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card begins writing and holds the DAT line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, then the card responds with its status. The status bit READY_FOR_DATA indicates whether the card can accept new data or whether the write process is still in progress. The host may deselect the card by issuing CMD7 (to select a different card), which places the card into the disconnect state and releases the DAT line without interrupting the write operation. When re-selecting the card, it reactivates the busy indication by pulling DAT to low if programming is still in progress and the write buffer is unavailable. The software flow to write to the card with DMA enable is: 1. Start MMC_SD_CLK if it is stopped. 2. Check the card status, wait until card is ready for data. 3. For SD/MMC, set the card block length, using SET_BLOCKLEN (CMD16). 4. Set the SDHC block length register to be same as block length set to the card in Step 2. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-50 Freescale Semiconductor Secured Digital Host Controller (SDHC) — For SDIO, if the CMD53 is in byte mode, the SDHC block length register should be set according to bytes count in CMD53; if the CMD53 is in block mode, the SDHC block length register should be set according to the block size in CCCR registers. 5. Set SDHC number block register (NOB), nob is 1 for single block write or CMD53 in byte mode for SDIO. 6. Disable the buffer ready interrupt, configure the DMA setting and enable the SDHC DMA channel: a) Write ‘0’ to bit[3] of INT_CNTR register in SDHC to disable buffer write ready interrupt. b) Set DMA destination to be SDHC_Buffer Access register. c) Set DMA destination port size to be 32-bit. d) Set DMA Burst length to be 16 bytes in 1-bit mode or 64 bytes in 4-bit mode. e) Set DMA transfer count to be number of bytes which is a multiple of the Block_length (nob*blk_len = total number of bytes). 7. Check the card status and wait until the card is ready for data. 8. Set SDHC CMD register to any of the following: — CMD24(WRITE_BLOCK) — CMD25(WRITE_MULTIPLE_BLOCK) — CMD53 in byte mode or block mode 9. Set SDHC CMD Argument register. 10. Set SDHC Command Data Control register. 11. Wait for end command response and check if there any CRC error or timeout error. 12. Wait for DMA done. 13. Check for Write_OP_DONE and check status bit to see if write CRC error occurred. 14. Send STOP_TRANSMISSION command to the card if the write command is WRITE_MULTIPLE_BLOCK (CMD25). 15. Stop the MMC_SD_CLK, finished the write operation. (This step is optional.) If the write operation is without DMA, the system needs to write data to the buffer through buffer write ready interrupt or by polling the buffer write ready status bit (STATUS[6]: BUF_WR_RDY). For high performance, data transfer using DMA is preferred. 27.5.3.1.2 Block Read For block reads, the basic unit of data transfer is a block for which the maximum size is defined in the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks for which the starting and ending addresses are entirely contained within one physical block (as defined by READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block, ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read. After completing the transfer, the card returns to the transfer state. CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Blocks is continuously transferred until a stop command is issued. If the host uses partial blocks for which accumulated length is not block aligned and block misalignment is not allowed, the card detects a block misalignment at the beginning of the first mis-aligned block, sets the ADDRESS_ERROR error bit in the status register, aborts transmission, and waits in the data state for a STOP command. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-51 Secured Digital Host Controller (SDHC) The software flow to write to card with DMA enable is: 1. Start MMC_SD_CLK if it is stopped. 2. Check the card status and wait until the card is ready for data. 3. For SD/MMC, set the card block length, using SET_BLOCKLEN (CMD16). 4. Set the SDHC block length register to be same as block length set to the card in step 3. — For SDIO, if the CMD53 is in byte mode, the SDHC block length register should be set according to bytes count in CMD53; if the CMD53 is in block mode, the SDHC block length register should be set according to the block size in CCCR registers. 5. Set SDHC number block register (NOB) to 1 for single block write or CMD53 in byte mode for SDIO. 6. Disable the buffer ready interrupt, configure the DMA setting, and enable the SDHC DMA channel: a) Write ‘0’ to bit[4] of INT_CNTR register in SDHC to disable the buffer read ready interrupt. b) Set DMA source to be SDHC_Buffer Access register. c) Set DMA source port size to be 32-bit. d) Set DMA burst length to be 16 bytes in 1-bit mode or 64 bytes in 4-bit mode. e) Set DMA transfer count to be number of bytes that is a number of blocks multiple of the Block_length (nob*blk_len). 7. Check the card status and wait until the card is ready for data. 8. Set SDHC CMD register to be CMD17(READ_SINGLE_BLOCK) or CMD18 (READ_MULTIPLE_BLOCK) or CMD53 in byte mode or block mode. 9. Set SDHC CMD Argument register. 10. Set SDHC Command Data Control register. 11. Wait for END_CMD_RESP interrupt and check response FIFO, check CRC error and timeout error. 12. Wait for DMA done. 13. Check for READ_OP_DONE and check status bit to see if read CRC error occurred. 14. Send STOP_TRANSMISSION command to the card if the read command is READ_MULTIPLE_BLOCK (CMD18). 15. Stop the MMC_SD_CLK, finished the read operation. If the read transfer operation does not use DMA, the system will need to fetch data out of the data buffer through utilizing the buffer read ready interrupt or by polling the buffer read ready status bit (STATUS[7]: BUF_READ_RDY). For high performance, data transfer using DMA is preferred. 27.6 Commands for MMC/SD/SDIO See Table 27-21 for the list of commands for MMC/SD/SDIO. Refer to corresponding card specifications for details about the command information. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-52 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-21. Commands for MMC/SD/SDIO CMD INDEX CMD0 CMD1 Type bc bcr Argument [31:0] stuff bits [31:0] OCR without busy R3 Response — Abbreviation GO_IDLE_STATE SEND_OP_COND Description Resets all MMC and SD memory cards to idle state. Asks all MMC and SD Memory cards in idle state to send their operation conditions register contents in the response on the CMD line. Asks all cards to send their CID numbers on the CMD line. CMD2 CMD3 CMD4 CMD5 bcr ac bc bc [31:0] stuff bits [31:6] RCA [15:0] stuff bits [31:0] DSR [15:0] stuff bits [31:0] OCR without busy R2 R1 R6(SDIO) — R4 ALL_SEND_CID SET_RELATIVE_AD Assigns relative address to the DR card. SET_DSR Programs the DSR of all cards. IO_SEND_OP_CON Asks all SD I/O cards in idle state D to send their operation conditions register contents in the response on the CMD line. CMD6 CMD7 Reserved ac [31:6] RCA [15:0] stuff bits R1b SELECT/DESELEC T_CARD Command toggles a card between the stand-by and transfer states or between the programming and disconnect states. In both cases, the card is selected by its own relative address and gets deselected by any other address; address 0 deselects all. CMD8 CMD9 Reserved ac [31:6] RCA [15:0] stuff bits [31:6] RCA [15:0] stuff bits [31:0] data address R2 SEND_CSD Addressed card sends its card-specific data (CSD) on the CMD line. Addressed card sends its card-identification (CID) on the CMD line. CMD10 ac R2 SEND_CID CMD11 adtc R1 READ_DAT_UNTIL_ MMC Reads data stream from STOP the card, starting at the given address, until a STOP_TRANSMISSION follows. STOP_TRANSMISS Forces the MMC/SD Memory ION card to stop transmission. SEND_STATUS Addressed MMC/SD card sends its status register. CMD12 CMD13 CMD14 ac ac Reserved [31:0] stuff bits [31:6] RCA [15:0] stuff bits R1b R1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-53 Secured Digital Host Controller (SDHC) Table 27-21. Commands for MMC/SD/SDIO (continued) CMD INDEX CMD15 Type ac Argument [31:6] RCA [15:0] stuff bits Response — Abbreviation Description GO_INACTIVE_STA Sets the card to inactive state in TE order to protect the card stack against communication breakdowns. SET_BLOCKLEN Sets the block length (in bytes) for all following block commands (read and write). Default block length is specified in the CSD. Reads a block of the size selected by the SET_BLOCKLEN command. CMD16 ac [31:0] block length R1 CMD17 adtc [31:0] data address [31:0] data address R1 READ_SINGLE_BL OCK CMD18 adtc R1 READ_MULTIPLE_B Continuously transfers data LOCK blocks from card to host until interrupted by a stop command. CMD19 CMD20 Reserved adtc [31:0] data address R1 WRITE_DAT_UNTIL MMC card writes data stream _STOP from the host, starting at the given address, until a STOP_TRANSMISION follows. CMD21–23 CMD24 Reserved adtc [31:0] data address [31:0] data address [31:0] stuff bits R1 WRITE_BLOCK Writes a block of the size selected by the SET_BLOCKLEN command. CMD25 adtc R1 WRITE_MULTIPLE_ Continuously writes blocks of BLOCK data until a STOP_TRANSMISSION follows. PROGRAM_CID Programming of the MMC card identification register. This command shall be issued only once per card. The card contains hardware to prevent this operation after the first programming. Normally, this command is reserved for the manufacturer. Programming of the programmable bits of the CSD. If the card has write-protection features, this command sets the write-protection bit of the addressed group. The properties of write-protection are coded in the card specific data (WP_GRP_SIZE). CMD26 adtc R1 CMD27 CMD28 adtc ac [31:0] stuff bits [31:0] data address R1 R1b PROGRAM_CSD SET_WRITE_PROT MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-54 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-21. Commands for MMC/SD/SDIO (continued) CMD INDEX CMD29 Type ac Argument [31:0] data address Response R1b Abbreviation Description CLR_WRITE_PROT If the card provides write-protection features, this command clears the write-protection bit of the addressed group. SEND_WRITE_PRO If the card provides T write-protection features, this command asks the card to send the status of the write-protection bits. CMD30 adtc [31:0] write protect data address R1 CMD31 CMD32 CMD33 Reserved ac ac [31:0] data address [31:0] data address [31:0] data address [31:0] data address [31:0] data address [31:0] data address [31:0] stuff bits [31:0] RCA [15] register write flag [14:8] register address [7:0] register data R1 R1 ERASE_WR_BLK_S Sets the address of the first TART sector of the erase group. ERASE_WR_BLK_E Sets the address of the last ND sector of the continuous range of the erase group. UNTAG_SECTOR Removes one previously selected sector from the erase selection. Sets the address of the first erase group within a range to be selected for erase. Sets the address of the last erase group within a continuous range to be selected for erase. Removes one previously selected erase group from the erase selection. Erases all previously selected sectors. Used to write and read 8-bit (register) data fields. The command address a card and a register and provides the data for writing if the write flag is set. The R4 response contains data read from the address register. This command accesses application dependent registers which are not defined in MMC standard. Sets the system into interrupt mode. CMD34 ac R1 CMD35 ac R1 TAG_ERASE_GRO UP_START TAG_ERASE_GRO UP_END UNTAG_ERASE_G ROUP ERASE FAST_IO CMD36 ac R1 CMD37 ac R1 CMD38 CMD39 ac ac R1b R4 CMD40 CMD41 bcr Reserved [31:0] stuff bits R5 GO_IRQ_STATE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-55 Secured Digital Host Controller (SDHC) Table 27-21. Commands for MMC/SD/SDIO (continued) CMD INDEX CDM42 Type adtc Argument [31:0] stuff bits Response R1b Abbreviation LOCK_UNLOCK Description Used to set/reset the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. CMD43~51 CMD52 Reserved — [31] R/W flag R5 [30:28] Function Number [27] RAW (read after write) flag [26] stuff bit [25:9] Register Address [8] Stuff bit [7:0] Write Data/stuff bits [31] R/W flag R5 [30:28] Function Number [27] Block mode [26] OP Code [25:9] Register Address [8:0] Byte/Block Count IO_RW_DIRECT Used to access a single register within the total 128 Kbytes of register space in any I/O function. CMD53 — IO_RW_EXTENDED Used to access a multiple I/O register with a single command, It allows the reading or writing of a large number of I/O registers. CMD54 CMD55 Reserved ac [31:16] RCA [15:0] stuff bits R1 APP_CMD Indicates to the card that the next command is an application-specific command rather than a standard command. Used either to transfer a data block to the card or to get a data block from the card for general-purpose/applicationspecific commands. The size of the data block is set by the SET_BLOCK_LEN command. CMD56 adtc [31:1] stuff bits [0]: RD/WR R1b GEN_CMD CMD57~63 Reserved ACMDs are preceded with APP_CMD command. (Command listed below are used for SD only. Other unlisted SD commands are not supported in this module.) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-56 Freescale Semiconductor Secured Digital Host Controller (SDHC) Table 27-21. Commands for MMC/SD/SDIO (continued) CMD INDEX ACMD6 Type ac Argument [31:2] stuff bits [1:0] bus width Response R1 Abbreviation SET_BUS_WIDTH Description Defines the SD Memory Card data bus width (‘00’=1-bit or ‘10’=4-bit bus) to be used for data transfer. The allowed data bus widths are given in the SCR register. Sends the SD Memory Card status. ACMD13 ACMD22 adtc adtc [31:0] stuff bits [31:0] stuff bits R1 R1 SD_STATUS SEND_NUM_WR_S Sends the number of the written ECTORS (without errors) sectors. Responds with 32-bit + CRC data block. SET_WR_BLK_ERA Set the number of write blocks to SE_COUNT be pre-erased before writing (to be used for faster Multi-block write command). SD_APP_OP_CON D Asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. ACMD23 ac [31:23] stuff bits R1 [22:0] Number of blocks [31:0] OCR R3 ACMD41 bcr ACMD42 ac [31:1] stuff bits [0] set_cd [31:0] stuff bits R1 SET_CLR_CARD_D Connects/disconnects the 50 ETECT kΩ pull-up resistor on CD/DAT3 of the card. SEND_SCR Reads the SD Configuration Register (SCR). ACMD51 adtc R1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 27-57 Secured Digital Host Controller (SDHC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 27-58 Freescale Semiconductor Chapter 28 Universal Asynchronous Receiver/Transmitters (UART) The Universal Asynchronous Receiver/Transmitter (UART) module is capable of standard RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART provides serial communication capability with external devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. Figure 28-1 shows the UART block diagram. Figure 28-1. UART Block Diagram 28.1 Overview The UART transmits and receives characters that are either 7 or 8 bits in length (program selectable). To transmit, data is written from the peripheral data bus to a 32-byte transmitter FIFO (TxFIFO). This data is passed to the shift register and shifted serially out on the transmitter pin (TXD). To receive, data is received serially from the receiver pin (RXD) and stored in a 32-half-words-deep receiver FIFO (RxFIFO). The MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-1 Universal Asynchronous Receiver/Transmitters (UART) received data is retrieved from the RxFIFO on the peripheral data bus. The RxFIFO and TxFIFO generate maskable interrupts as well as DMA Requests when the data level in each of the FIFO reaches a programmed threshold level. The UART generates baud rates based on a programmable divisor and input clock. The UART also contains programmable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd, even, or no parity. The receiver detects framing errors, idle conditions, BREAK characters, parity errors, and overrun errors. The UART module uses a software interface for control of modem operations and have a serial infrared (IR) module that decodes and encodes IrDA-compatible serial IR data. 28.1.1 Features The UART includes the following features: • High speed TIA/EIA-232-F compatible, up to 4.125Mbit/s • 7 or 8 data bits • 1 or 2 stop bits • Programmable parity (even, odd, and no parity) • Hardware flow control support for request to send (RTS) and clear to send (CTS) signals • Edge selectable RTS and edge detect interrupts • Status flags for various flow control and FIFO states • Serial IR interface low speed, IrDA-compatible (up to 115.2 kbit/s). • Voting logic for improved noise immunity (16x oversampling) • Transmitter FIFO empty interrupt suppression • UART internal clocks enable/disable • Auto baud rate detection (up to 115.2 kbit/s) • Receiver and transmitter enable/disable for power saving • RTS, IrDA asynchronous wake (AIRINT), receive asynchronous wake (AWAKE), interrupts wake the MCU from Sleep Mode • Maskable interrupts • Two DMA Requests (TxFIFO DMA Request and RxFIFO DMA Request) • Escape character sequence detection • Software reset (SRST) • Dedicated BRM clock (ipg_perclk) to allow frequency scaling on main clock (ipg_clk) without reprogramming BRM registers 28.1.2 Modes of Operation The following are the UART modes of operation: • Serial RS-232 NRZ format • IrDA MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-2 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) 28.2 28.2.1 External Signal Description Overview Table 28-1. Interface Signals Signal Name I/O Active state Reset Description Reset State Figure 28-1 provides external signal descriptions. ipg_hard_async_reset_b I Low Asynchronous reset Interrupts ipi_uart_rx_b ipi_uart_tx_b ipi_uart_mint_b ipi_uart_anded_b DMA Requests ipd_uart_rx_dmareq_b ipd_uart_tx_dmareq_b O O Low Low Receiver DMA request Transmitter DMA request High High O O O O Low Low Low Low Receiver interrupt Transmitter interrupt Common interrupt Anded interrupt (see below for comment) High High High High Serial/IrDA Signals ipp_uart_rxd_mux ipp_uart_txd_mux I O Serial/infrared data receive Serial/infrared data transmit Modem Control Signals ipp_uart_cts_b ipp_uart_rts_b O I Low Low Clear to send Request to send Clocks ipg_clk ipg_clk_s ipg_perclk I I I Main clock Bus clock Binary Rate Multiplier (BRM) clock High High 28.3 28.3.1 Memory Map and Register Definition Memory Map and Register Summary The UART supports 8-bit and 16-bit accesses to 32-bit memory-mapped addresses only. All the memory mapped registers are 32 bits wide, however as the 16 MSB are not used: • For 32-bits write access, the 16 MSB will not be taken into account. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-3 Universal Asynchronous Receiver/Transmitters (UART) • For 32-bits read access the 16 MSB will be read as 0. 28.3.2 Memory Map Table 28-2. UART Memory Map Address Register Access R UART Receiver Registers 1–6 W UART Receiver Registers 1–6 R/W UART Control Registers 1_1–1_6 R/W UART Control Registers 2_1–2_6 R/W UART Control Registers 3_1–3_6 R/W UART Control Registers 4_1–4_6 R/W UART FIFO Control Registers 1–6 R/W UART Status Registers 1_1–1_6 R/W UART Status Registers 2_1–2_6 R/W UART Escape Character Registers 1–6 R/W UART Escape Timer Registers 1–6 R/W UART BRM Incremental Registers 1–6 R/W UART BRM Modulator Registers 1–6 0x0000 28.3.4.13/28-24 0x0000 28.3.4.12/28-23 0x0000 28.3.4.11/28-23 0x002B 28.3.4.10/28-22 0x4008 28.3.4.9/28-20 0x2040 28.3.4.8/28-18 0x0801 28.3.4.7/28-17 0x8000 28.3.4.6/28-15 0x0700 28.3.4.5/28-14 0x0001 28.3.4.4/28-11 0x0000 28.3.4.3/28-9 0x00– – 28.3.4.2/28-9 Reset Value 0x8000 Section/Page 28.3.4.1/28-7 Table 28-2 shows the memory map. 0x1000_A000 (URXD1) – 0x1001_C000 (URXD6) 0x1000_A040 (UTXD1) – 0x1001_C040 (UTXD6) 0x1000_A080 (UCR1_1) – 0x1001_C080 (UCR1_6) 0x1000_A084 (UCR2_1) – 0x1001_C084 (UCR2_6) 0x1000_A088 (UCR3_1) – 0x1001_C088 (UCR3_6) 0x1000_A08C (UCR4_1) – 0x1001_C08C (UCR4_6) 0x1000_A090 (UFCR1) – 0x1001_C090 (UFCR6) 0x1000_A094 (USR1) – 0x1001_C094 (USR6) 0x1000_A098 (USR2_1) – 0x1001_C098 (USR2_6) 0x1000_A09C (UESC1) – 0x1001_C09C (UESC6) 0x1000_A0A0 (UTIM1) – 0x1001_C0A0 (UTIM6) 0x1000_A0A4 (UBIR1) – 0x1001_C0A4 (UBIR6) 0x1000_A0A8 (UBMR1) – 0x1001_C0A8 (UBMR6) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-4 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-2. UART Memory Map (continued) Address 0x1000_A0AC (UBRC1) – 0x1001_C0AC (UBRC6) 0x1000_A0B0 (ONEMS1) – 0x1001_C0B0 (ONEMS6) 0x1000_A0B4 (UTS1) – 0x1001_C0B4 (UTS6) Register Access R UART Baud Rate Count Registers 1–6 R/W UART One Millisecond Registers 1–6 R/W UART Test Registers 1–6 0x0060 28.3.4.16/28-26 0x0000 28.3.4.15/28-25 Reset Value 0x0000 Section/Page 28.3.4.14/28-24 28.3.3 Register Summary The conventions in Figure 28-3 and Table 28-3 serve as a key for the register summary and individual register diagrams. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0 bit BIT bit only bit only bit BIT to clear w1c N/A Figure 28-2. Key to Register Fields Table 28-3 provides a key for register figures and tables and the register summary. Table 28-3. Register Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types R W R/W rwm w1c Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit Writing a one has some effect on the module, but it always reads as zero (previously designated slfclr). Reset Values 0 1 — u [signal_name] Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. Reset value is determined by polarity of indicated signal. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-5 Universal Asynchronous Receiver/Transmitters (UART) All registers described in this section are for 16 LSB. Figure 28-3 shows the key to the register fields. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0 bit only bit only bit BIT to clear w1c bit BIT N/A Figure 28-3. Key to Register Fields Table 28-4. UART Register Summary Name 0x1000_A000 (URXD1) – 0x1001_C000 (URXD6) 0x1000_A040 (UTXD1) – 0x1001_C040 (UTXD6) 0x1000_A080 (UCR1_1) – 0x1001_C080 (UCR1_6) 0x1000_A084 (UCR2_1) – 0x1001_C084 (UCR2_6) 0x1000_A088 (UCR3_1) – 0x1001_C088 (UCR3_6) 0x1000_A08C (UCR4_1) – 0x1001_C08C (UCR4_6) 0x1000_A090 (UFCR1) 0x1000_A090 (UFCR1) – 0x1001_C090 (UFCR6) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R W ERR OVRR UN FRM ERR BRK PRE RR 0 0 RX_DATA R W 0 0 0 0 0 0 0 0 TX_DATA R ADE ADB TRDY WN R EN IDEN ICD RR RXD IRE TXM RTS SND TXD DYE MA N PTY DEN BRK MA N EN EN EN 0 DOZ UAR E TEN R W ESC I IRT S CTSC CTS ESC EN RTEC PRE PRO STP N E B WS RTS ATE TXE RXE SRS EN N N N T R W 0 0 0 PARE FRA RRE ERR N EN 0 0 0 ADN RXD AIRI AW IMP SEN NTE AKE N N 0 RXD INV T MU XSE L OR EN ACI EN R W CTSTL INV R ENI RI WK EN 0 IRS C LPB TCE BKE YP N N DRE N R W TXTL RR DY RFDIV AGT IM 0 0 RXTL RXD AIRI AW S NT AKE 0 0 0 0 R PAR RTS TRDY RTSD ESC FRA ITY S F ME ERR RR W MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-6 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-4. UART Register Summary (continued) Name 0x1000_A098 (USR2_1) – 0x1001_C098 (USR2_6) 0x1000_A09C (UESC1) – 0x1001_C09C (UESC6) 0x1000_A0A0 (UTIM1) – 0x1001_C0A0 (UTIM6) 0x1000_A0A4 (UBIR1) – 0x1001_C0A4 (UBIR6) 0x1000_A0A8 (UBMR1) – 0x1001_C0A8 (UBMR6) 0x1000_A0AC (UBRC1) – 0x1001_C0AC (UBRC6) 0x1000_A0B0 (ONEMS1) – 0x1001_C0B0 (ONEMS6) 0x1000_A0B4 (UTS1) – 0x1001_C0B4 (UTS6) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ADE T W TXF E 0 IDLE ACS T 0 0 IRIN T WA KE 0 0 RTS F TXD C BRC D OR E RD R 0 R W 0 0 0 0 0 0 0 ESC_CHAR 0 R W 0 0 0 TIM R W INC R W MOD BCNT R W R W ONEMS R 0 0 FRCP LOOP DBG LOO RXD ERR EN PIR BG 0 0 TXE RXE TXF RXF MPT MPT ULL ULL Y Y 0 0 SOF TRS T W 28.3.4 28.3.4.1 Register Descriptions UART Receiver Register (URXD) Figure 28-4 shows the URXD register, and Table 28-5 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-7 Universal Asynchronous Receiver/Transmitters (UART) 0x1000_A000 (URXD1) 0x1000_B000 (URXD2) 0x1000_C000 (URXD3) 0x1000_D000 (URXD4) 0x1001_B000 (URXD5) 0x1001_C000 (URXD6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read-only 3 2 1 0 R W Reset 0 ERR OVR RUN FRM ERR BRK PRER R 0 0 RX_DATA 1 0 0 0 0 0 0 0 — — — — — — — — Figure 28-4. UART Receiver Register (URXD) Table 28-5. Receiver Register Field Descriptions Name 31–16 15 Reserved Reserved. This bit is reserved and should read 1. Note: Reset value is read at 1 for compatibility with existing software (previously CHARRDY was bit 15 and always read as 1). Error Detect. Indicates whether the character present in the RX_DATA field has an error (OVRRUN, FRMERR, BRK or PRERR) status. The ERR bit is updated and valid for each received character. 0 No error status was detected. 1 An error status was detected. Receiver overrun. This read-only bit, when HIGH, indicates that the corresponding character was stored in the last position (32nd) of the RxFIFO. Even if a 33rd character has not been detected, this bit is set to ‘1’ for the 32nd character. 0 No RxFIFO overrun was detected. 1 A RxFIFO overrun was detected. Frame error. Indicates whether the current character had a framing error (a missing stop bit) and is possibly corrupted. FRMERR is updated for each character read from the RxFIFO. 0 The current character has no framing error. 1 The current character has a framing error. BREAK detect. Indicates whether the current character was detected as a BREAK character. The data bits and the stop bit are all 0. The FRMERR bit is set when BRK is set. When odd parity is selected, PRERR is also set when BRK is set. BRK is valid for each character read from the RxFIFO. 0 The current character is not a BREAK character. 1 The current character is a BREAK character. Parity error. Indicates if the current character was detected with a parity error and is possibly corrupted. PRERR is updated for each character read from the RxFIFO. When parity is disabled, PRERR always reads as 0. 0 No parity error was detected for data in the RX_DATA field. 1 A parity error was detected for data in the RX_DATA field. Description 14 ERR 13 OVRRUN 12 FRMERR 11 BRK 10 PRERR MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-8 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-5. Receiver Register Field Descriptions (continued) Name 9–8 7–0 RX_DATA Reserved Received data. Holds the received character. In 7-bit mode, the most significant bit (MSB) is forced to 0. In 8-bit mode, all bits are active. Description 28.3.4.2 UART Transmitter Register (UTXD) Figure 28-5 shows the UTXD register, and Table 28-6 shows the register’s field descriptions. 0x1000_A040 (UTXD1) 0x1000_B040 (UTXD2) 0x1000_C040 (UTXD3) 0x1000_D040 (UTXD4) 0x1001_B040 (UTXD5) 0x1001_C040 (UTXD6) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User write 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 — — — TX_DATA — — — — — Figure 28-5. UART Transmitter (UTXD) Register Table 28-6. UART Transmitter Register Field Descriptions Field 31–16 15–8 7–0 TX_DATA Reserved Reserved Transmit data. Holds the parallel transmit data inputs. In 7-bit mode, D7 is ignored. In 8-bit mode, all bits are used. Data is transmitted least significant bit (LSB) first. A new character is transmitted when the TX_DATA field is written. The TX_DATA field must be written only when the TRDY bit is high to ensure that corrupted data is not sent. Description 28.3.4.3 UART Control Register 1 (UCR1) Figure 28-6 shows the UCR1 register, and Table 28-7 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-9 Universal Asynchronous Receiver/Transmitters (UART) 0x1000_A080 (UCR1_1) 0x1000_B080 (UCR1_2) 0x1000_C080 (UCR1_3) 0x1000_D080 (UCR1_4) 0x1001_B080 (UCR1_5) 0x1001_C080 (UCR1_6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R W Reset ADEN ADBR 0 0 TRDY IDEN EN 0 0 0 ICD 0 RXD TXD RRDY TXMP RTSD SNDB MAE IREN MAE EN TYEN EN RK N N 0 0 0 0 0 0 0 0 DOZ UAR E TEN 0 0 0 Figure 28-6. UART Control Register 1 (UCR1) Table 28-7. UART Control Register 1 (UCR1) Field Descriptions Field 31–16 15 ADEN Reserved Automatic baud rate detection interrupt enable. Enables/disables the automatic baud rate detect complete (ADET) bit to generate an interrupt (ipi_uart_mint = 0). 0 Disable the automatic baud rate detection interrupt 1 Enable the automatic baud rate detection interrupt Automatic detection of baud rate. Enables/disables automatic baud rate detection. When the ADBR bit is set and the ADET bit is cleared, the receiver detects the incoming baud rate automatically. The ADET flag is set when the receiver verifies that the incoming baud rate is detected properly by detecting an ASCII character “A” or “a” (0x61 or 0x41). 0 Disable the automatic baud rate detection 1 Enable the automatic baud rate detection Transmitter ready interrupt enable. Enables/disables the transmitter ready interrupt (TRDY) when the transmitter has one or more slots available in the TxFIFO. The fill level in the TxFIFO at which an interrupt is generated is controlled by TxTL bits. When TRDYEN is negated, the transmitter ready interrupt is disabled. 0 Disable the transmitter ready interrupt 1 Enable the transmitter ready interrupt Idle condition detected interrupt enable. Enables/disables the IDLE bit to generate an interrupt (ipi_uart_rx = 0). 0 Disable the IDLE bit 1 Enable the IDLE bit Idle condition detect. Controls the number of frames RXD is allowed to be idle before an idle condition is reported. 00 Report idle of more than 4 frames 01 Report idle of more than 8 frames 10 Report idle of more than 16 frames 11 Report idle of more than 32 frames Receiver ready interrupt enable. Enables/disables the RRDY interrupt when the RxFIFO contains data. The fill level in the RxFIFO at which an interrupt is generated is controlled by the RXTL bits. When RRDYEN is negated, the receiver ready interrupt is disabled. 0 Disable the RRDY interrupt 1 Enable the RRDY interrupt Description 14 ADBR 13 TRDYEN 12 IDEN 11–10 ICD 9 RRDYEN MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-10 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-7. UART Control Register 1 (UCR1) Field Descriptions (continued) Field 8 RXDMAEN Description Receive ready DMA enable. Enables/disables the receive DMA request ipd_uart_rx_dmareq when the receiver has data in the RxFIFO. The fill level in the RxFIFO at which a DMA request is generated is controlled by the RXFL bits. When negated, the receive DMA request is disabled. 0 Disable the DMA request 1 Enable the DMA request Infrared interface enable. Enables/disables the IR interface. 0 Disable the IR interface 1 Enable the IR interface Transmitter empty interrupt enable. Enables/disables the transmitter FIFO empty (TXFE) interrupt ipi_uart_tx. When negated, the TXFE interrupt is disabled. 0 Disable the transmitter FIFO empty interrupt 1 Enable the transmitter FIFO empty interrupt RTS delta interrupt enable. Enables/disables the RTSD interrupt. The current status of the ipp_uart_rts pin is read in the RTSS bit. 0 Disable the RTSD interrupt 1 Enable the RTSD interrupt Send BREAK. Forces the transmitter to send a BREAK character. The transmitter finishes sending the character in progress (if any) and sends BREAK characters until SNDBRK is reset. Because the transmitter samples SNDBRK after every bit is transmitted, it is important that SNDBRK is asserted high for a sufficient period of time to generate a valid BREAK. After the BREAK transmission completes, the UART transmits 2 mark bits. The user can continue to fill the TxFIFO. Any characters remaining are transmitted when the BREAK is terminated. 0 Does not send a BREAK character 1 Send a BREAK character (continuous 0s) Transmitter ready DMA enable. Enables/disables the transmit DMA request ipd_uart_tx_dmareq when the transmitter has one or more slots available in the TxFIFO. The fill level in the TxFIFO that generates the ipd_uart_tx_dmareq is controlled by the TXTL bits. 0 Disable the transmit DMA request 1 Enable the transmit DMA request Reserved DOZE. Determines the UART enable condition in the doze state. When ipg_doze input pin is at ‘1’, meaning the CPU executes a doze instruction and the system is placed in the doze state, the DOZE bit affects operation of the UART. While in the doze state, if this bit is asserted, the UART is disabled. Refer to the description in Section 28.4.8, “UART Operation in Low-Power System States.” 0 Enable the UART when it is in doze state 1 Disable the UART when it is in doze state UART Enable. Enables/disables the UART. If UARTEN is negated in the middle of a transmission, the transmitter stops and pulls the TXD line to a logic 1. UARTEN must be set to 1 before any access to UTXD and URXD registers; otherwise, an ipg_xfr_error is returned. Output ipg_uart_clk_en is internally connected to UARTEN and can be used for software controlled clock gating purpose. 0 Disable the UART 1 Enable the UART 7 IREN 6 TXMPTYEN 5 RTSDEN 4 SNDBRK 3 TXDMAEN 2 1 DOZE 0 UARTEN 28.3.4.4 UART Control Register 2 (UCR2) Figure 28-7 shows the UCR2 register, and Table 28-8 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-11 Universal Asynchronous Receiver/Transmitters (UART) 0x1000_A084 (UCR2_1) 0x1000_B084 (UCR2_2) 0x1000_C084 (UCR2_3) 0x1000_D084 (UCR2_4) 0x1001_B084 (UCR2_5) 0x1001_C084 (UCR2_6) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R ESCI IRTS CTSC CTS ESCEN W Reset 0 0 0 0 0 0 0 0 0 0 0 RTEC PREN PROE STPB WS RTSE ATEN TXEN RXEN SRST N 0 0 0 0 1 Figure 28-7. UART Control Register 2 (UCR2) Summary Table 28-8. UART Control Register 2 Field Descriptions Field 15 ESCI 14 IRTS Description Escape Sequence Interrupt Enable. Enables/Disables the ESCF bit to generate an interrupt. 0 Disable the escape sequence interrupt 1 Enable the escape sequence interrupt Ignore RTS Pin. Forces the RTS input signal presented to the transmitter to always be asserted (set to low), effectively ignoring the external pin. When in this mode, the RTS pin serves as a general purpose input. 0 Transmit only when the RTS pin is asserted. 1 Ignore the RTS pin CTS Pin Control. Controls the operation of the ipp_uart_cts_b output pin. When CTSC is asserted, the ipp_uart_cts_b output pin is controlled by the receiver. When the RxFIFO is filled to the level of the programmed trigger level and the start bit of the overflowing character (TRIGGER LEVEL + 1) is validated, the ipp_uart_cts_b output pin is negated to indicate to the far-end transmitter to stop transmitting. When the trigger level is programmed for less than 32, the receiver continues to receive data until the RxFIFO is full. When the CTSC bit is negated, the ipp_uart_cts_b output pin is controlled by the CTS bit. On reset, because CTSC is cleared to 0, the ipp_uart_cts_b pin is controlled by the CTS bit, which again is cleared to 0 on reset. This means that on reset the ipp_uart_cts_b signal is negated. 0 The ipp_uart_cts_b pin is controlled by the CTS bit. 1 The ipp_uart_cts_b pin is controlled by the receiver. Clear to Send. Controls the ipp_uart_cts_b pin when the CTSC bit is negated. CTS has no function when CTSC is asserted. 0 The ipp_uart_cts_b pin is high (inactive). 1 The ipp_uart_cts_b pin is low (active). Escape Enable. Enables/Disables the escape sequence detection logic. 0 Disable escape sequence detection 1 Enable escape sequence detection Request to Send Edge Control. Selects the edge that triggers the RTS interrupt. This has no effect on the RTS delta interrupt. RTEC has an effect only when RTSEN = 1. 00 Trigger interrupt on a rising edge 01 Trigger interrupt on a falling edge 1X Trigger interrupt on any edge 13 CTSC 12 CTS 11 ESCEN 10–9 RTEC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-12 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-8. UART Control Register 2 Field Descriptions (continued) Field 8 PREN Description Parity Enable. Enables/Disables the parity generator in the transmitter and parity checker in the receiver. When PREN is asserted, the parity generator and checker are enabled, and disabled when PREN is negated. 0 Disable parity generator and checker 1 Enable parity generator and checker Parity Odd/Even. Controls the sense of the parity generator and checker. When PROE is high, odd parity is generated and expected. When PROE is low, even parity is generated and expected. PROE has no function if PREN is low. 0 Even parity 1 Odd parity Stop. Controls the number of stop bits transmitted after a character. When STPB is high, 2 stop bits are sent. When STPB is low, 1 stop bit is sent. STPB has no effect on the receiver, which expects 1 or more stop bits. 0 1 stop bit transmitted 1 2 stop bits transmitted Word Size. Controls the character length. When WS is high, the transmitter and receiver are in 8-bit mode. When WS is low, they are in 7-bit mode. The transmitter ignores bit 7 and the receiver sets bit 7 to 0. WS can be changed in-between transmission (reception) of characters, however not when a transmission (reception) is in progress, in which case the length of the current character being transmitted (received) is unpredictable. 0 7-bit transmit and receive character length (not including START, STOP, or PARITY bits) 1 8-bit transmit and receive character length (not including START, STOP, or PARITY bits) Request to Send Interrupt Enable. Controls the RTS edge sensitive interrupt. When RTSEN is asserted and the programmed edge is detected on the ipp_uart_rts_b pin, the RTSF bit is asserted. 0 Disable request to send interrupt 1 Enable request to send interrupt Aging Timer Enable. This bit is used to enable the aging timer interrupt (triggered with AGTIM). 0 AGTIM interrupt is disabled. 1 AGTIM interrupt is enabled. Transmitter Enable. Enables/Disables the transmitter. When TXEN is negated the transmitter is disabled and idle. When the UARTEN and TXEN bits are set the transmitter is enabled. If TXEN is negated in the middle of a transmission, the UART disables the transmitter immediately, and starts marking 1s. The transmitter FIFO cannot be written when this bit is cleared. 0 Disable the transmitter 1 Enable the transmitter Receiver Enable. Enables/Disables the receiver. When the receiver is enabled, if the RXD input is already low, the receiver does not recognize BREAK characters, because it requires a valid 1-to-0 transition before it can accept any character. 0 Disable the receiver 1 Enable the receiver Software Reset. Resets the transmitter and receiver state machines, all FIFOs, and all status registers. Once the software writes 0 to SRST, the software reset remains active for 4 clock cycles of CKIH before the hardware deasserts SRST. The software can only write 0 to SRST. Writing 1 to SRST is ignored. 0 Reset the transmit and receive state machines, all FIFOs and all status registers 1 No reset 7 PROE 6 STPB 5 WS 4 RTSEN 3 ATEN 2 TXEN 1 RXEN 0 SRST MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-13 Universal Asynchronous Receiver/Transmitters (UART) 28.3.4.5 UART Control Register 3 (UCR3) Figure 28-8 shows the UCR3 register, and Table 28-9 shows the register’s field descriptions. 0x1000_A088 (UCR3_1) 0x1000_B088 (UCR3_2) 0x1000_C088 (UCR3_3) 0x1000_D088 (UCR3_4) 0x1001_B088 (UCR3_5) 0x1001_C088 (UCR3_6) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R W Reset 0 0 0 PAR FRAER ERR REN EN 0 0 0 0 0 ADNI RXDS AIRIN AWAK MP EN TEN EN 0 0 0 0 0 RXD MUX SEL 0 INVT 0 ACIE N 0 0 0 0 1 1 1 0 Figure 28-8. UART Control Register 3 (UCR3) Summary Table 28-9. UART Control Register 3 (UCR3) Field Descriptions Field 15–14 13 Reserved. Reserved. Description 12 PARERREN Parity Error Interrupt Enable. Enables/Disables the interrupt. When asserted, PARERREN causes the PARITYERR bit to generate an interrupt. 0 Disable the parity error interrupt 1 Enable the parity error interrupt Frame Error Interrupt Enable. Enables/Disables the interrupt. When asserted, FRAERREN causes the FRAMERR bit to generate an interrupt. 0 Disable the frame error interrupt 1 Enable the frame error interrupt Reserved. 11 FRAERREN 10 9 Reserved. 8 7 ADNIMP Reserved. Autobaud Detection Not Improved. Disables new features of autobaud detection (see Section 28.4.6.2, “Baud Rate Automatic Detection Protocol Improved” for more details). 0 Autobaud detection new features selected 1 Keep old autobaud detection mechanism MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-14 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-9. UART Control Register 3 (UCR3) Field Descriptions (continued) Field 6 RXDSEN Description Receive Status Interrupt Enable. Controls the receive status interrupt (ipi_uart_rx_b). When this bit is enabled and RXDS status bit is set, the interrupt ipi_uart_rx_b will be generated. 0 Disable the RXDS interrupt 1 Enable the RXDS interrupt Asynchronous IR WAKE Interrupt Enable. Controls the asynchronous IR WAKE interrupt. An interrupt is generated when AIRINTEN is asserted and a pulse is detected on the UART_RX pin. 0 Disable the AIRINT interrupt 1 Enable the AIRINT interrupt Asynchronous WAKE Interrupt Enable. Controls the asynchronous WAKE interrupt. An interrupt is generated when AWAKEN is asserted and a falling edge is detected on the RXD pin. 0 Disable the AWAKE interrupt 1 Enable the AWAKE interrupt Reserved RXD Muxed Input Selected. Selects the ipp_uart_rxd_mux input pin for serial and Infrared input signal 0 Serial input pin is ipp_uart_rxd and IrDA input pin is ipp_uart_rxd_ir 1 Input pin is ipp_uart_rxd_mux for serial and IR interfaces In i.MX27, this bit should always be set to 1. Otherwise, UART receiver will not work. 1 INVT Inverted Infrared Transmission. Sets the active level for the transmission. When INVT is cleared, the infrared logic block transmits a positive IR 3/16 pulse for all 0s and 0s are transmitted for 1s. When INVT is set (INVT = 1), the infrared logic block transmits an active low or negative infrared 3/16 pulse for all 0s and 1s are transmitted for 1s. 0 Active low transmission 1 Active high transmission Autobaud Counter Interrupt Enable. This bit is used to enable the autobaud counter stopped interrupt (triggered with ACST (USR2[11]). 0 ACST interrupt disabled 1 ACST interrupt enabled 5 AIRINTEN 4 AWAKEN 3 2 RXDMUXSEL 0 ACIEN 28.3.4.6 UART Control Register 4 (UCR4) Figure 28-9 shows the UCR2 register, and Table 28-10 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-15 Universal Asynchronous Receiver/Transmitters (UART) 0x1000_A08C (UCR4_1) 0x1000_B08C (UCR4_2) 0x1000_C08C (UCR4_3) 0x1000_D08C (UCR4_4) 0x1001_B08C (UCR4_5) 0x1001_C08C (UCR4_6) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R CTSTL W Reset 1 0 0 0 0 0 INV WKE ENIRI R N 0 0 0 0 IRSC LPBYP TCEN BKEN OREN DREN 0 0 0 0 0 0 0 Figure 28-9. UART Control Register 4 (UCR4) Summary Table 28-10. UART Control Register 4 (UCR4) Field Descriptions Field 15–10 CTSTL Description CTS Trigger Level. Controls the threshold at which the ipp_uart_cts_b pin is deasserted by the RxFIFO. After the trigger level is reached and the ipp_uart_cts_b pin is deasserted, the RxFIFO continues to receive data until it is full. The CTSTL bits are encoded as shown in the Settings column. 000000 0 characters received 000001 1 characters in the RxFIFO ... 100000 32 characters in the RxFIFO (maximum) All Other Settings Reserved Inverted Infrared Reception. Determines the logic level for the detection. When cleared, the infrared logic block expects an active low or negative IR 3/16 pulse for 0s and 1s are expected for 1s. When INVR is set (INVR = 1), the infrared logic block expects an active high or positive IR 3/16 pulse for 0s and 0s are expected for 1s. 0 Active low detection 1 Active high detection Serial Infrared Interrupt Enable. Enables/Disables the serial infrared interrupt. 0 Serial infrared Interrupt disabled 1 Serial infrared Interrupt enabled WAKE Interrupt Enable. Enables/Disables the WAKE bit to generate an interrupt. The WAKE bit is set at the detection of a start bit by the receiver. 0 Disable the WAKE interrupt 1 Enable the WAKE interrupt Reserved IR Special Case. Selects the clock for the vote logic. When set, IRSC switches the vote logic clock from the sampling clock to the UART reference clock. The IR pulses are counted a predetermined amount of time depending on the reference frequency. See Section 28.4.7.3, “InfraRed Special Case (IRSC) Bit.” 0 The vote logic uses the sampling clock (16x baud rate) for normal operation 1 The vote logic uses the UART reference clock Low Power Bypass. Allows to bypass the low power new features in UART. To use during debug phase. 0 Low power features enabled 1 Low power features disabled 9 INVR 8 ENIRI 7 WKEN 6 5 IRSC 4 LPBYP MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-16 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-10. UART Control Register 4 (UCR4) Field Descriptions (continued) Field 3 TCEN Description Transmit Complete Interrupt Enable. Enables/Disables the TXDC bit to generate an interrupt (ipi_uart_tx_b = 0). 0 Disable TXDC interrupt 1 Enable TXDC interrupt BREAK Condition Detected Interrupt Enable. Enables/Disables the BRCD bit to generate an interrupt. 0 Disable the BRCD interrupt 1 Enable the BRCD interrupt Receiver Overrun Interrupt Enable. Enables/Disables the ORE bit to generate an interrupt. 0 Disable ORE interrupt 1 Enable ORE interrupt Receive Data Ready Interrupt Enable. Enables/Disables the RDR bit to generate an interrupt. 0 Disable RDR interrupt 1 Enable RDR interrupt 2 BKEN 1 OREN 0 DREN 28.3.4.7 UART FIFO Control Register Summary (UFCR) Figure 28-10 shows the UART FIFO register, and Table 28-11 shows the register’s field descriptions. 0x1000_A090 (UFCR1) 0x1000_B090 (UFCR2) 0x1000_C090 (UFCR3) 0x1000_D090 (UFCR4) 0x1001_B090 (UFCR5) 0x1001_C090 (UFCR6) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read/write 2 1 0 R TXTL W Reset 0 0 0 0 1 0 0 0 0 RFDIV 0 RXTL 0 0 0 0 0 0 1 Figure 28-10. UART FIFO Control Register (UFCR) Summary MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-17 Universal Asynchronous Receiver/Transmitters (UART) Table 28-11. UART FIFO Control Register Description Field 15–10 TXTL Description Transmitter Trigger Level. Controls the threshold at which a maskable interrupt is generated by the TxFIFO. A maskable interrupt is generated whenever the data level in the TxFIFO falls below the selected threshold. The bits are encoded as shown in the Settings column. 000000 = Reserved 000001 = Reserved 000010 = TxFIFO has 2 or fewer characters ... 011111 = TxFIFO has 31 or fewer characters 100000 = TxFIFO has 32 characters (maximum) All Other Settings Reserved Reference Frequency Divider. Controls the divide ratio for the reference clock. The input clock is ipg_perclk. The output from the divider (ref_clk) is used by BRM to create the 16x baud rate oversampling clock. 000 Divide input clock by 6 001 Divide input clock by 5 010 Divide input clock by 4 011 Divide input clock by 3 100 Divide input clock by 2 101 Divide input clock by 1 110 Divide input clock by 7 Reserved. Receiver Trigger Level—Controls the threshold at which a maskable interrupt is generated by the RxFIFO. A maskable interrupt is generated whenever the data level in the RxFIFO reaches the selected threshold. The RXTL bits are encoded as shown in the Settings column. 000000 0 characters received. 000001 RxFIFO has 1 character. ... 011111 RxFIFO has 31 characters. 100000 RxFIFO has 32 characters (maximum). All Other Settings are reserved. 9–7 RFDIV 6 5–0 RXTL 28.3.4.8 UART Status Register 1 Summary (USR1) Figure 28-11 shows the register, and Table 28-12 shows the register’s field descriptions. 0x1000_A094 (USR1) 0x1000_B094 (USR2) 0x1000_C094 (USR3) 0x1000_D094 (USR4) 0x1001_B094 (USR5) 0x1001_C094 (USR6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R PARITY RTS ESC FRAM RTSS TRDY RRDY AGTIM D F ERR W ERR Reset 0 0 1 0 0 0 0 0 0 RXDS AIRINT AWAKE 0 1 0 0 0 0 0 0 0 0 0 0 Figure 28-11. UART Status Register 1 (USR1) Summary MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-18 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-12. UART Status Register 1 (USR1) Field Descriptions Field 15 PARITYERR Description Parity Error Interrupt Flag. Indicates a parity error is detected. PARITYERR is cleared by writing 1 to it. Writing 0 to PARITYERR has no effect. When parity is disabled, PARITYERR always reads 0. At reset, PARITYERR is set to 0. 0 No parity error detected 1 Parity error detected RTS Pin Status. Indicates the current status of the ipp_uart_rts_b pin. A “snapshot” of the pin is taken immediately before RTSS is presented to the data bus. RTSS cannot be cleared because all writes to RTSS are ignored. At reset, RTSS is set to 0. 0 The ipp_uart_rts_b pin is high (inactive). 1 The ipp_uart_rts_b pin is low (active). Transmitter Ready Interrupt/DMA Flag. Indicates that the TxFIFO emptied below its target threshold and requires data. TRDY is automatically cleared when the data level in the TxFIFO goes beyond above the set threshold level by TXFL bits. At reset, TRDY is set to 1. 0 The transmitter does not require data. 1 The transmitter requires data (interrupt posted). RTS Delta. Indicates whether the ipp_uart_rts_b pin changed state. It (RTSD) generates a maskable interrupt. When in Sleep Mode, RTS assertion sets RTSD and can be used to wake the ARM9 core. The current state of the ipp_uart_rts_b pin is available on the RTSS bit. Clear RTSD by writing 1 to it. Writing 0 to RTSD has no effect. At reset, RTSD is set to 0. 0 ipp_uart_rts_b pin did not change state since last cleared. 1 ipp_uart_rts_b pin changed state (write 1 to clear) Escape Sequence Interrupt Flag. Indicates if an escape sequence was detected. ESCF is asserted when the ESCEN bit is set and an escape sequence is detected in the RxFIFO. Clear ESCF by writing 1 to it. Writing 0 to ESCF has no effect. 0 No escape sequence detected 1 Escape sequence detected (write 1 to clear) Frame Error Interrupt Flag. Indicates that a frame error is detected. The ipi_uart_mint_b interrupt generated by this. Clear FRAMERR by writing 1 to it. Writing 0 to FRAMERR has no effect. 0 No frame error detected 1 Frame error detected Receiver Ready Interrupt/DMA Flag. Indicates that the RxFIFO data level is above the threshold set by the RXFL bits. (See the RXFL bits description in Table 28-11 for setting the interrupt threshold.) When asserted, RRDY generates a maskable interrupt or DMA request. In conjunction with the CHARRDY bit in the URXDn_1 or URXDn_2 register, the software can continue to read the RxFIFO in an interrupt service routine until the RxFIFO is empty. RRDY is automatically cleared when data level in the RxFIFO goes below the set threshold level. At reset, RRDY is set to 0. 0 No character ready 1 Character(s) ready (interrupt posted) Aging Timer Interrupt Flag. Indicates that data in the RxFIFO has been idle for a time of 8 character lengths (where a character length consists of 7 or 8 bits, depending on the setting of the WS bit in UCR2, with the bit time corresponding to the baud rate setting) and FIFO data level is less than RxFIFO threshold level (RxTL in the UFCR). Clear by writing a 1 to it. 0 AGTIM is not active. 1 AGTIM is active (write 1 to clear). Reserved. 14 RTSS 13 TRDY 12 RTSD 11 ESCF 10 FRAMERR 9 RRDY 8 AGTIM 7 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-19 Universal Asynchronous Receiver/Transmitters (UART) Table 28-12. UART Status Register 1 (USR1) Field Descriptions (continued) Field 6 RXDS Description Receiver IDLE Interrupt Flag. Indicates that the receiver state machine is in an IDLE state, the next state is IDLE, and the receive pin is high. RXDS is automatically cleared when a character is received. RXDS is active only when the receiver is enabled. 0 Receive is in progress. 1 Receiver is IDLE. Asynchronous IR WAKE Interrupt Flag. Indicates that the IR WAKE pulse was detected on the ipp_uart_rxd_ir pin, or on ipp_uart_rxd_mux if RXDMUXSEL is set to 1. Clear AIRINT by writing 1 to it. Writing 0 to AIRINT has no effect. 0 No pulse was detected on the RXD IrDA pin. 1 A pulse was detected on the RXD IrDA pin. Asynchronous WAKE Interrupt Flag. Indicates that a falling edge was detected on the ipp_uart_rxd pin, or on ipp_uart_rxd_mux if RXDMUXSEL is set to 1. Clear AWAKE by writing 1 to it. Writing 0 to AWAKE has no effect. 0 No falling edge was detected on the RXD Serial pin. 1 A falling edge was detected on the RXD Serial pin. Reserved. 5 AIRINT 4 AWAKE 3–0 28.3.4.9 UART Status Register 2 (USR2) Figure 28-12 shows the register, and Table 28-13 shows the register’s field descriptions. 0x1000_A098 (USR2_1) 0x1000_B098 (USR2_2) 0x1000_C098 (USR2_3) 0x1000_D098 (USR2_4) 0x1001_B098 (USR2_5) 0x1001_C098 (USR2_6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R ADET W Reset 0 TXFE 0 ACS IDLE T 0 0 0 0 IRINT WAKE 0 0 TXD RD C BRC ORE R RTSF D 0 1 0 0 0 1 0 0 0 0 0 0 0 Figure 28-12. UART Status Register 2 (USR2) Summary MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-20 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-13. UART Status Register 2 Field Descriptions Field 15 ADET Description Automatic Baud Rate Detect Complete. Indicates that an “A” or “a” was received and that the receiver detected and verified the incoming baud rate. Clear ADET by writing 1 to it. Writing 0 to ADET has no effect. 0 ASCII “A” or “a” was not received. 1 ASCII “A” or “a” was received (write 1 to clear). Transmit Buffer FIFO Empty. Indicates that the transmit buffer (TxFIFO) is empty. TXFE is cleared automatically when data is written to the TxFIFO. Even though TXFE is high, the transmission might still be in progress. 0 The transmit buffer (TxFIFO) is not empty. 1 The transmit buffer (TxFIFO) is empty. Reserved. 14 TXFE 13 12 IDLE Idle Condition. Indicates that an idle condition has existed for more than a programmed amount frame (see Section 28.4.4.2.1, “Idle Line Detect”). An interrupt can be generated by this IDLE bit if IDEN (UCR1[12]) is enabled. IDLE is cleared by writing 1 to it. Writing 0 to IDLE has no effect. 0 No idle condition is detected. 1 Idle condition is detected (write 1 to clear). Autobaud Counter Stopped. In autobaud detection (ADBR=1), indicates the counter which determines the baudrate was running and is now stopped. This means either START bit is finished (if ADNIMP=1), or Bit0 is finished (if ADNIMP=0). See Section 28.4.6.3.1, “New Autobaud Counter Stopped Bit and Interrupt” for more details. An interrupt can be flagged on ipi_uart_mint_b if ACIEN=1. 0 Measurement of bit length is not finished (in autobaud). 1 Measurement of bit length is finished (in autobaud). (Write a “one” to clear.) Reserved. Reserved. Serial Infrared Interrupt Flag. When an edge is detected on the RX pin during SIR Mode, this flag will be asserted. This flag can cause an interrupt on ipi_uart_mint_b which can be masked using the control bit ENIRI: UCR4 [8]. 0 No edge was detected. 1 Valid edge was detected (write a “one” to clear). Wake. Indicates the start bit is detected. WAKE can generate an interrupt on ipi_uart_mint_b that can be masked using the WKEN bit. Clear WAKE by writing 1 to it. Writing 0 to WAKE has no effect. 0 Start bit was not detected. 1 Start bit was detected (write 1 to clear). Reserved. Reserved. 11 ACST 10 9 8 IRINT 7 WAKE 6 5 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-21 Universal Asynchronous Receiver/Transmitters (UART) Table 28-13. UART Status Register 2 Field Descriptions (continued) Field 4 RTSF Description RTS Edge Triggered Interrupt Flag. Indicates if a programmed edge is detected on the ipp_uart_rts_b pin. The RTEC bits select the edge that generates an interrupt. RTSF can generate an interrupt on ipi_uart_mint_b that can be masked using the RTSEN bit. Clear RTSF by writing 1 to it. Writing 0 to RTSF has no effect. 0 Programmed edge is not detected on ipp_uart_rts_b. 1 Programmed edge is detected on ipp_uart_rts_b (write 1 to clear). Transmitter Complete. Indicates that the transmit buffer (TxFIFO) and Shift Register is empty; therefore the transmission is complete. TXDC is cleared automatically when data is written to the TxFIFO. 0 Transmit is incomplete. 1 Transmit is complete. BREAK Condition Detected. Indicates that a BREAK condition was detected by the receiver. Clear BRCD by writing 1 to it. Writing 0 to BRCD has no effect. 0 No BREAK condition was detected. 1 A BREAK condition was detected (write 1 to clear). Overrun Error. When set to 1, ORE indicates that the receive buffer (RxFIFO) was full (32 chars inside), and a 33rd character has been fully received. This 33rd character has been discarded. Clear ORE by writing 1 to it. Writing 0 to ORE has no effect. 0 No overrun error 1 Overrun error (write 1 to clear) Receive Data Ready. Indicates that at least 1 character is received and written to the RxFIFO. If the URXD register is read and there is only 1 character in the RxFIFO, RDR is automatically cleared. 0 No receive data ready 1 Receive data ready 3 TXDC 2 BRCD 1 ORE 0 RDR 28.3.4.10 UART Escape Character Register Summary (UESC) Figure 28-13 shows the register, and Table 28-14 shows the register’s field descriptions. 0x1000_A09C (UESC1) 0x1000_B09C (UESC2) 0x1000_C09C (UESC3) 0x1000_D09C (UESC4) 0x1001_B09C (UESC5) 0x1001_C09C (UESC6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 ESC_CHAR 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 Figure 28-13. UART Escape Character Register Summary (UESC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-22 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-14. UART Escape Character Register Field Descriptions Name 15–8 7–0 ESC_CHAR Reserved. UART Escape Character. Holds the selected escape character that all received characters are compared against to detect an escape sequence. Description 28.3.4.11 UART Escape Timer Register Summary (UTIM) Figure 28-14 shows the register, and Table 28-15 shows the register’s field descriptions. 0x1000_A0A0 (UTIM1) 0x1000_B0A0 (UTIM2) 0x1000_C0A0 (UTIM3) 0x1000_D0A0 (UTIM4) 0x1001_B0A0 (UTIM5) 0x1001_C0A0 (UTIM6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R W Reset 0 0 0 0 TIM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28-14. UART Escape Timer Register Summary (UTIM) Table 28-15. UART Escape Timer Register (UTIM) Field Descriptions Name 15–12 11–0 TIM Reserved. UART Escape Timer. Holds the maximum interval allowed between escape characters. Description 28.3.4.12 UART BRM Incremental Register (UBIR) Figure 28-15 shows the register, and Table 28-16 shows the register’s field descriptions. 0x1000_A0A4 (UBIR1) 0x1000_B0A4 (UBIR2) 0x1000_C0A4 (UBIR3) 0x1000_D0A4 (UBIR4) 0x1001_B0A4 (UBIR5) 0x1001_C0A4 (UBIR6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R INC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28-15. UART BRM Incremental Register Summary (UBIR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-23 Universal Asynchronous Receiver/Transmitters (UART) Table 28-16. UART BRM Incremental Register Field Descriptions Name 15–0 INC Description Incremental Numerator. Holds the numerator value minus one of the BRM ratio (see Section 28.4.5, “Binary Rate Multiplier (BRM)”). The UBIR register MUST be updated before the UBMR register for the baud rate to be updated correctly. If only one register is written to by software, the BRM will ignore this data until the other register is written to by software. Updating this field using byte accesses is not recommended and is undefined. 28.3.4.13 UART BRM Modulator Register Summary (UBMR) Figure 28-13 shows the register, and Table 28-17 shows the register’s field descriptions. 0x1000_A0A8 (UBMR1) 0x1000_B0A8 (UBMR2) 0x1000_C0A8 (UBMR3) 0x1000_D0A8 (UBMR4) 0x1001_B0A8 (UBMR5) 0x1001_C0A8 (UBMR6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R MOD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28-16. UART BRM Modulator Register Summary (UBMR) Table 28-17. UART BRM Modulator Register Field Descriptions Field 15–0 MOD Description Modulator Denominator. Holds the value of the denominator minus one of the BRM ratio (see Section 28.4.5, “Binary Rate Multiplier (BRM)”). The UBIR register MUST be updated before the UBMR register for the baud rate to be updated correctly. If only one register is written to by software, the BRM will ignore this data until the other register is written to by software. Updating this register using byte accesses is not recommended and undefined. 28.3.4.14 UART Baud Rate Count Register Summary (UBRC) Figure 28-14 shows the register, and Table 28-18 shows the register’s field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-24 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) 0x1000_A0AC (UBRC1) 0x1000_B0AC (UBRC2) 0x1000_C0AC (UBRC3) 0x1000_D0AC (UBRC4) 0x1001_B0AC (UBRC5) 0x1001_C0AC (UBRC6) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User read 2 1 0 R W Reset 0 0 0 0 0 0 0 BCNT 0 0 0 0 0 0 1 0 0 Figure 28-17. UART Baud Rate Count Register Summary (UBRC) Table 28-18. UART Baud Rate Count Register Field Descriptions Field 15–0 BCNT Description Baud Rate Count Register. This read only register is used to count the start bit of the incoming baud rate (if ADNIMP=1), or start bit + bit0 (if ADNIMP=0). When the measurement is done, the Baud Rate Count Register contains the number of UART internal clock cycles (clock after divider) present in an incoming bit. BCNT retains its value until the next Automatic Baud Rate Detection sequence has been initiated. The 16-bit Baud Rate Count register is reset to 4 and stays at hex FFFF in the case of an overflow. 28.3.4.15 UART One Millisecond Register (ONEMS) Figure 28-15 shows the register, and Table 28-19 shows the register’s field descriptions. 0x1000_A0B0 (ONEMS1) 0x1000_B0B0 (ONEMS2) 0x1000_C0B0 (ONEMS3) 0x1000_D0B0 (ONEMS4) 0x1001_B0B0 (ONEMS5) 0x1001_C0B0 (ONEMS6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R ONEMS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28-18. UART One Millisecond Register Summary (ONEMS) Table 28-19. UART One Millisecond Register Field Descriptions Field 15–0 ONEMS Description One Millisecond Register. This 16-bit register must contain the value of the UART internal frequency divided by 1000. The internal frequency is obtained after the UART internal divider. In fact this register contains the value corresponding to the number of UART internal clock cycles are present in one millisecond. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-25 Universal Asynchronous Receiver/Transmitters (UART) 28.3.4.16 UART Test Register (UTS) Figure 28-16 shows the register, and Table 28-20 shows the register’s field descriptions. 0x1000_A0B4 (UTS1) 0x1000_B0B4 (UTS2) 0x1000_C0B4 (UTS3) 0x1000_D0B4 (UTS4) 0x1001_B0B4 (UTS5) 0x1001_C0B4 (UTS6) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 FRCP DBG LOO RXD LOOP ERR EN PIR BG 0 0 TXE RXE TXFU RXF MPT MPT LL ULL Y Y 0 0 SOF TRS T 1 1 0 0 0 0 0 Figure 28-19. UART Test Register Summary (UTS) Table 28-20. UART Test Register Description Field 15–14 13 FRCPERR Description Reserved. These bits are reserved and should read 0. Force Parity Error. Forces the transmitter to generate a parity error if parity is enabled. FRCPERR is provided for system debugging. 0 Generate normal parity 1 Generate inverted parity (error) Loop TX and RX for Test. Controls loopback for test purposes. When LOOP is high, the receiver input is internally connected to the transmitter and ignores the RXD pin. The transmitter is unaffected by LOOP. If RXDMUXSEL (UCR3[2]) is set to 1, the loopback is applied on serial and IrDA signals. If RXDMUXSEL is set to 0, the loopback is only applied on serial signals. 0 Normal receiver operation 1 Internally connect the transmitter output to the receiver input Debug_enable_b. This bit controls whether to respond to the debug_b input signal. 0 UART will go into debug mode when debug_b is LOW. 1 UART will not go into debug mode even if debug_b is LOW. Loop TX and RX for IR Test (LOOPIR). This bit controls loopback from transmitter to receiver in the InfraRed interface. 0 No IR loop 1 Connect IR transmitter to IR receiver RX_fifo_debug_mode. This bit controls the operation of the RX fifo read counter when in debug mode. 0 RX FIFO read pointer does not increment. 1 RX_FIFO read pointer increments as normal. Reserved. These bits are reserved and should read 0. TxFIFO Empty. Indicates that the TxFIFO is empty. 0 The TxFIFO is not empty. 1 The TxFIFO is empty. 12 LOOP 11 DBGEN 10 LOOPIR 9 RXDBG 8–7 6 TXEMPTY MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-26 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-20. UART Test Register Description (continued) Field 5 RXEMPTY 4 TXFULL 3 RXFULL 2–1 0 SOFTRST Description RxFIFO Empty. Indicates the RxFIFO is empty. 0 The RxFIFO is not empty. 1 The RxFIFO is empty. TxFIFO FULL. Indicates the TxFIFO is full. 0 The TxFIFO is not full. 1 The TxFIFO is full. RxFIFO FULL. Indicates the RxFIFO is full. 0 The RxFIFO is not full. 1 The RxFIFO is full. Reserved. These bits are reserved and should read 0. Software Reset. Indicates the status of the software reset (SRST). 0 No software reset 1 Generate software reset 28.4 28.4.1 Functional Description Interrupts and DMA Requests Table 28-21 lists all of the different interrupts signals available on the interrupt pins. See the individual register descriptions for explanation of available enables and status flags. Table 28-21. Interrupts and DMA Interrupt Output ipi_uart_rx_b Interrupt Enable RRDYEN IDEN DREN RXDSEN ATEN TXMPTYEN TRDYEN TCEN Enable Register Location UCR1 (bit 9) UCR1 (bit 12) UCR4 (bit 0) UCR3 (bit 6) UCR2 (bit 3) UCR1 (bit 6) UCR1 (bit 13) UCR4 (bit 3) Interrupt Flag RRDY IDLE RDR RXDS AGTIM TXFE TRDY TXDC Flag Register Location USR1 (bit 9) USR2 (bit 12) USR2 (bit 0) USR1 (bit 6) USR1 (bit 8) USR2 (bit 14) USR1 (bit 13) USR2 (bit 3) ipi_uart_tx_b MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-27 Universal Asynchronous Receiver/Transmitters (UART) Table 28-21. Interrupts and DMA Interrupt Output ipi_uart_mint_b Interrupt Enable OREN BKEN WKEN ADEN ACIEN ESCI ENIRI AIRINTEN AWAKEN FRAERREN PARERREN RTSDEN RTSEN RXDMAEN TXDMAEN Enable Register Location UCR4 (bit 1) UCR4 (bit 2) UCR4 (bit 7) UCR1 (bit 15) UCR3 (bit 0) UCR2 (bit 15) UCR4 (bit 8) UCR3 (bit 5) UCR3 (bit 4) UCR3 (bit 11) UCR3 (bit 12) UCR1 (bit 5) UCR2 (bit 4) UCR1 (bit 8) UCR1 (bit 3) Interrupt Flag ORE BRCD WAKE ADET ACST ESCF IRINT AIRINT AWAKE FRAERR PARITYERR RTSD RTSF RRDY TRDY Flag Register Location USR2 (bit 1) USR2 (bit 2) USR2 (bit 7) USR2 (bit 15) USR2 (bit 11) USR1 (bit 11) USR2 (bit 8) USR1 (bit 5) USR1 (bit 4) USR1 (bit 10) USR1 (bit 15) USR1 (bit 12) USR2 (bit 4) USR1 (bit 9) USR1 (bit 13) ipd_uart_rx_dmareq_b ipd_uart_tx_dmareq_b 28.4.2 28.4.2.1 Clocking Considerations Minimum and Maximum Clock Frequencies UART module receives the following three clocks: • ipg_clk • ipg_clk_s • ipg_perclk ipg_clk is the main clock and must always be running when UART is enabled. There is an exception in Sleep Mode (see Section 28.4.2.2, “Clocking in Low-Power Modes”). ipg_clk_s is the bus clock, it is active only when there a bus access (read/write) to UART registers. ipg_clk and ipg_clk_s are synchronous and have the same frequency. But UART receives also another clock, ipg_perclk. This clock is the Binary Multiplier Clock and it must always be running when UART is sending or receiving characters. This clock has been added in order to allow frequency scaling on ipg_clk (and ipg_clk_s) without changing configuration of BRM (ipg_perclk staying at a fixed frequency). Constraints: • ipg_clk, ipg_clk_s, and ipg_perclk must be synchronous and their clock trees must be balanced. But ipg_perclk frequency is not necessary equal to ipg_clk frequency (and ipg_clk_s).This specific relationship between ipg_perclk and ipg_clk is obtained by extracting those clocks from the same source clock but on which different dividers have been applied. The dividers ratios must always be integer values. With this constraint UART receives either ipg_perclk and ipg_clk rising edges at the same time or separated by at minimum a fixed guard-band. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-28 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) • • For example: Main source clock frequency is 270 MHz. ipg_perclk frequency is fixed at 16.8 MHz (270 MHz/16). ipg_clk (and ipg_clk_s) frequency can vary from 16.8 MHz to a maximum value. This maximum frequency must always comes from an integer division of main source clock (270 MHz/n). It must also be used to constrain the design during synthesis phase. At any moment, ipg_clk (and ipg_clk_s) frequency must be higher or equal to ipg_perclk frequency. See Figure 28-20 for examples of working configurations. Due to the 16x oversampling of the incoming characters, ipg_perclk frequency must always be greater or equal to 16x the maximum baud rate. For example, if max baud rate is 1.875 Mbit/s, ipg_perclk must be greater or equal to 1.875 M x 16 = 30 MHz. NOTE If the architecture of the IC does not require a clock dedicated to BRM, ipg_perclk input pin must receive same clock than ipg_clk. Clock trees between both pins must be balanced. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-29 Universal Asynchronous Receiver/Transmitters (UART) ipg_clk frequency higher than ipg_perclk frequency source clock ipg_clk ipg_perclk ipg_clk and ipg_perclk are equivalent (same frequency and in phase) source clock ipg_clk ipg_perclk ipg_clk and ipg_perclk have the same frequency but are not in phase source clock ipg_clk ipg_perclk Figure 28-20. Examples of Working Relationships Between ipg_clk and ipg_perclk MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-30 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) 28.4.2.2 Clocking in Low-Power Modes The UART supports 2 low-power modes: DOZE and STOP. In Sleep Mode (input pin ipg_stop is at ‘1’), the UART does not need any clock. In this mode the UART can wake-up the MCU with the asynchronous interrupts (see Section 28.4.8, “UART Operation in Low-Power System States”). An application of this feature is when the system must be waken-up by the arrival of a frame of characters. • If before entering in Sleep Mode the software has enabled RTSDEN interrupt, then when RTS will change state (put at ‘0’ by external device started to send), the asynchronous interrupt will wake-up the system, and ipg_clk (and ipg_perclk) will be provided to the UART before first start bit, so that no data will be lost. • If RTS does not change state (already at ‘0’ before entering in Sleep Mode), then wake-up interrupt (AWAKE) will be sent at the arrival of first Start bit (on falling edge). In this case, the UART must receive the ipg_clk and ipg_perclk during the first half of start bit to correctly receive this character (for example, at 115.2 Kbit/s, UART must receive ipg_clk and ipg_perclk at maximum 4.3 microseconds after falling edge of Start bit). If the UART receives ipg_clk and ipg_perclk too late, first character will be lost, and so should be dropped. Also, if autobaud detection is enabled, the first character will not be correctly received and another autobaud detection will need to be initiated. In Doze mode, UART behavior is programmable through DOZE bit (UCR1[1]). If DOZE bit is set to ‘1’, then UART is disabled in Doze mode, and in consequence, UART clocks can be switched-off (after being sure UART is not transmitting nor receiving). On the contrary, if DOZE bit is set to ‘0’, UART is enabled and it must receive ipg_clk and ipg_perclk (and ipg_clk_s during accesses to registers). 28.4.3 General UART Definitions Definitions of terms that occur the following discussions are given in this section. • Bit Time—The period of time required to serially transmit or receive 1 bit of data (1 cycle of the baud rate frequency). • Start bit—The bit time of a logic 0 that indicates the beginning of a data frame. A start bit begins with a 1-to-0 transition, and is preceded by at least 1 bit time of logic 1. • Stop bit—1 bit time of logic 1 that indicates the end of a data frame. • BREAK—A frame in which all of the data bits, including the stop bit, are logic 0. This type of frame is usually sent to signal the end of a message or the beginning of a new message. • Frame—A start bit followed by a specified number of data or information bits and terminated by a stop bit. The number of data or information bits depends on the format specified and must be the same for the transmitting device and the receiving device. The most common frame format is 1 start bit followed by 8 data bits (least significant bit first) and terminated by 1 stop bit. An additional stop bit and a parity bit also can be included. • Framing Error—An error condition that occurs when the stop bit of a received frame is missing, usually when the frame boundaries in the received bit stream are not synchronized with the receiver bit counter. Framing errors can go undetected if a data bit in the expected stop bit time happens to be a logic 1. A framing error is always present on the receiver side when the transmitter is sending MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-31 Universal Asynchronous Receiver/Transmitters (UART) • • • BREAKs. However, when the UART is programmed to expect 2 stop bits and only the first stop bit is received, this is not a framing error by definition. Parity Error—An error condition that occurs when the calculated parity of the received data bits in a frame does not match the parity bit received on the RXD input. Parity error is calculated only after an entire frame is received. Idle—One in NRZ encoding format and selectable polarity in IrDA mode. Overrun Error—An error condition that occurs when the latest character received is ignored to prevent overwriting a character already present in the UART receive buffer (RxFIFO). An overrun error indicates that the software reading the buffer (RxFIFO) is not keeping up with the actual reception of characters on the RXD input. 28.4.3.1 RTS—UART Request To Send The UART Request To Send input controls the transmitter. The modem or other terminal equipment signals the UART when it is ready to receive by setting RTS to ‘0’ on the ipp_uart_rts_b pin. Normally, the transmitter waits until this signal is active (low) before transmitting a character, however when the Ignore RTS (IRTS) bit is set, the transmitter sends a character as soon as it is ready to transmit. An interrupt (RTSD) can be posted on any transition of this pin and can wake the MCU from Sleep Mode on its assertion. When RTS is set to ‘1’ during a transmission, the UART transmitter finishes transmitting the current character and shuts off. The contents of the TxFIFO (characters to be transmitted) remain undisturbed. 28.4.3.2 RTS Edge Triggered Interrupt The input to the ipp_uart_rts_b pin can be programmed to generate an interrupt on a selectable edge. The operation of the RTS edge triggered interrupt (RTSF) is summarized in Table 28-22. To enable the ipp_uart_rts_b pin to generate an interrupt, set the request to send interrupt enable (RTSEN) bit (UCR2[4]) to 1. Writing 1 to the RTS edge triggered interrupt flag (RTSF) bit (USR2[4]) clears the interrupt flag.The interrupt can occur on the rising edge, falling edge, or either edge of the RTS input. The request to send edge control (RTEC) field (UCR2[10:9]) programs the edge that generates the interrupt. When RTEC is set to 0x00 and RTSEN = 1, the interrupt occurs on the rising edge (default). When RTEC is set to 0x01 and RTSEN = 1, the interrupt occurs on the falling edge. When RTEC is set to 0x1X and RTSEN = 1, the interrupt occurs on either edge.This is a synchronous interrupt. The RTSF bit is cleared by writing 1 to it. Writing 0 to RTSF has no effect. Table 28-22. RTS Edge Triggered Interrupt Truth Table RTS X 1–>0 0–>1 1–>0 0–>1 RTSEN 0 1 1 1 1 RTEC [1] X 0 0 0 0 RTEC [0] X 0 0 1 1 RTSF 0 0 1 1 0 Interrupt Occurs On: Interrupt disabled Rising edge Rising edge Falling edge Falling edge ipi_uart_mint_b 1 1 0 0 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-32 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Table 28-22. RTS Edge Triggered Interrupt Truth Table (continued) RTS 1–>0 0–>1 RTSEN 1 1 RTEC [1] 1 1 RTEC [0] X X RTSF 1 1 Interrupt Occurs On: Either edge Either edge ipi_uart_mint_b 0 0 There is another RTS interrupt that is not programmable, however it asserts the RTS Delta (RTSD) bit when the RTS pin changes state. The status bit RTSD asserts the ipi_uart_mint_b interrupt when the RTS delta interrupt enable = 1. This is an asynchronous interrupt. The RTSD bit is cleared by writing 1 to it. Writing 0 to the RTSD bit has no effect. 28.4.3.3 Clear To Send (CTS) This output pin serves two purposes. Normally, the receiver indicates that it is ready to receive data by asserting this pin (low). When the CTS trigger level is programmed to trigger at 32 characters received and the receiver detects the valid start bit of the 33 character, it de-asserts this pin. 28.4.3.4 Programmable CTS Deassertion The CTS output can also be programmed to deassert when the RxFIFO reaches a certain level. Setting the CTS trigger level (UCR4[15:10]) at any value less than 32 deasserts the CTS pin on detection of the valid start bit of the N + 1 character (where N is the trigger level setting). However, the receiver continues to receive characters until the RxFIFO is full. 28.4.3.5 TXD—UART Transmit This is the transmitter serial output. When operating in normal mode, NRZ encoded data is output. When operating in infrared mode, a 3/16 bit-period pulse is output for each 0 bit transmitted, and no pulse is output for each 1 bit transmitted. For RS-232 applications, this pin must be connected to an RS-232 transmitter. 28.4.3.5.1 RXD—UART Receive This is the receiver serial input. When operating in normal mode, NRZ encoded data is expected. When operating in infrared mode, a narrow pulse is expected for each 0 bit received and no pulse is expected for each 1 bit received. External circuitry must convert the IR signal to an electrical signal. RS-232 applications require an external RS-232 receiver to convert voltage levels. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-33 Universal Asynchronous Receiver/Transmitters (UART) RTS RxFIFO Receiver Data Path CTS DCE/DTE Interface IP bus interface TX RX ipg_clk_s ipg_clk ipg_perclk TxFIFO Transmitter Data Path Programmable Divider UART UFCR:RFDIV[2:0] REF_CLK Data Control Binary Rate Multiplier (BRM) To Auto Baud -15- -16- -1REF_CLK BRM_CLK Bit Stream BIT 0 -2- -3- -4- -5- -6- -7- -8- -9- -10- -11- -12- -13- -14- -15- -16- -1- -2- -3- Bit 1 UBIR = 0, UBMR= 1 –> Ratio = 0.5 = 1/2 8-Bit Data Format Possible Parity Bit Bit 5 RXD/TXD Bit 6 Bit 7 STOP BIT Bit 2 Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Next Start Bit Standard Data Figure 28-21. UART Simplified Block and Clock Generation Diagrams 28.4.4 Sub-Block Description The UART module contains seven working registers separated in 2 status registers (USR1 and USR2) and five control registers (UCR1, UCR2, UCR3, UCR4, UFCR). A separate test register is provided for applications (test, verification, and so on) that require it. The binary rate multiplier registers (UBIR, UBMR) control the UART bit rate. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-34 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) There is also a transmitter register (UTXD) and a receiver register (URXD). The registers are optimized for a 16-bit bus. All status bits associated with the received data are accessible along with the data in a single read. Except for the transmit data register (UTXD), all register bits are readable and most are read/write. The UART Baud Rate Count Register (UBRC) performs automatic baud rate detection. There are also two registers for the escape sequence detection, the UART Escape Character Register (UESC) and the UART Escape Timer Register (UTIM). And finally, the One Millisecond register (ONEMS) must be filled with appropriate value when the module needs to measure a duration (Escape detection mode or IR Special Case). The following sections describe the basic functionality of the mains blocks of UART module. 28.4.4.1 Transmitter The transmitter accepts a parallel character from the MCU and transmits it serially. The start, stop, and parity (when enabled) bits are added to the character. When the ignore RTS bit (IRTS) is set, the transmitter sends a character as soon as it is ready to transmit. RTS can be used to provide flow-control of the serial data. When RTS is set to ‘1’, the transmitter finishes sending the character in progress (if any), stops, and waits for RTS to be set to ‘0’ again. Generation of BREAK characters and parity errors (for debugging purposes) is supported. The transmitter operates from the clock provided by the BRM. Normal NRZ encoded data is transmitted when the IR interface is disabled. The transmitter FIFO (TxFIFO) contains 32 bytes. The data is written to TxFIFO by writing to the UTXD register with the byte data to the [7:0] bits. The data is written consecutively if the TxFIFO is not full. It is read (internally) consecutively if the TxFIFO is not empty. If the TxFIFO is full and data is again attempted to be written to the FIFO, a bus xfr_error is generated. 28.4.4.1.1 Transmitter FIFO Empty Interrupt Suppression The transmitter FIFO empty interrupt suppression logic suppresses the TXFE interrupt between writes to the TxFIFO. When TxFIFO is empty, the software can either send one or several characters. If the software sends one character, it writes it into UTXD register and this character is immediately transferred to the transmitter shift register (when the transmitter is enabled). Without interrupt suppression logic, the TXFE interrupt would be set immediately. But, with this logic, the interrupt is set when the last bit of the character has been transmitted, that is, before the transmission of the parity bit (if exists) and the stop bit(s). So, the suppression logic does not immediately send the TXFE interrupt. It allows the software to write another character to the TxFIFO before the interrupt is asserted. When the transmitter shift register empties before another character is written to the TxFIFO, the interrupt is asserted. Writing data (even a single character) to the TxFIFO releases the interrupt. The interrupt is asserted on the following conditions: • System Reset • UART module reset • When a single character has been written to Transmitter FIFO and then the Transmitter FIFO and the Transmitter Shift Register become empty until another character is written to the Transmitter FIFO MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-35 Universal Asynchronous Receiver/Transmitters (UART) • The last character in the TxFIFO is transferred to the shift register, when TxFIFO contains two or more characters. See Figure 28-22. Reset = Peripheral Reset OR Software Reset Assert Transmitter FIFO Empty Flag Y Transmitter FIFO Empty N Deassert Transmitter FIFO Empty Flag Reset Deassert Transmitter FIFO Empty Flag Y Transmitter FIFO Empty Reset Deassert Transmitter FIFO Empty Flag N Deassert Transmitter FIFO Empty Flag N Transmitter Shift Register Empty Reset Y N Y N Transmitter FIFO Contains > 2 Characters Reset Transmitter FIFO Empty Y Reset Figure 28-22. Transmitter FIFO Empty Interrupt Suppression Flow Chart 28.4.4.1.2 Transmitting a Break Condition To send a break, bit 4 of the UCR1 reg (SNDBRK) should be asserted. This bit forces the transmitter to send a break character (continuous zeros). The transmitter will finish sending the character in progress (if any) then send break until this bit is reset. The user is responsible to ensure that this bit is high for long enough to generate a valid BREAK. The transmitter samples SNDBRK after every bit is transmitted. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-36 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) Following completion of the BREAK transmission, the UART will transmit two mark bits. The user can continue to fill the FIFO and any character remaining will be transmitted when the break is terminated. 28.4.4.2 Receiver The receiver accepts a serial data stream and converts it into parallel characters. When enabled, it searches for a start bit, qualifies it, and samples the following data bits at the bit-center. Jitter tolerance and noise immunity are provided by sampling at a 16x rate and using voting techniques to clean up the samples. Once the start bit is found, the data bits, parity bit (if enabled), and stop bits (either 1 or 2 depending on user selection) are shifted in. Parity is checked and its status reported in the URXD register when parity is enabled. Frame errors and BREAKs are also checked and reported. When a new character is ready to be read by the MCU from the RxFIFO, the receive data ready (RDR = USR2[0]) bit is asserted and an interrupt is posted (if DREN = UCR4[0] = 1). If the receiver trigger level is set to 2 (RXTL[5:0] = UFCR[5:0] = 2), and 2 chars have been received into RxFIFO, the receiver ready interrupt flag (RRDY = USR1[9]) is asserted and an interrupt is posted if the receiver ready interrupt enable bit is set (RRDYEN = UCR1[9] = 1). If the UART Receiver Register (URXD) is read once, and in consequence there is only 1 character in the RxFIFO, the interrupt generated by the RRDY bit is automatically cleared. The RRDY bit is cleared when the data in the RxFIFO falls below the programmed trigger level. Normal NRZ encoded data is expected when the IR interface is disabled. The RxFIFO contains 32 half-words. The data is read from the RxFIFO by reading the half-word data in the [15:0] bits in the URXD register. The data is written consecutively if the RxFIFO is not full, or is read consecutively if the RxFIFO is not empty. When additional data is written to the RxFIFO while it is full, the write operation cannot complete unless a read is performed. If a write is performed on the RxFIFO when it is full, the ORE bit (USR2[1]) register is set. The ORE bit is cleared by writing 1 to it. 28.4.4.2.1 Idle Line Detect The receiver logic block includes the ability to detect an idle line. Idle lines indicate the end or the beginning of a message. For an idle condition to occur: • RxFIFO must be empty and • RXD pin must be idle for more than a configured number of frames (ICD[1:0] = UCR1[11:10]). When the idle condition detected interrupt enable (IDEN = UCR1[12]) is set and the line is idle for 4 (default), 8, 16, or 32 (maximum) frames, the detection of an idle condition flags an interrupt. When an idle condition is detected, the IDLE (USR2[12]) bit is set. Clear the IDLE bit by writing 1 to it. Writing 0 to the IDLE bit has no effect. 28.4.4.2.2 Idle Condition Detect Configuration The idle condition detect ICD [1:0] field is located in the UCR1[11:10]. If the bits are set to 00b, RXD must be idle for more than 4 frames before the IDLE bit is asserted. If the bits are set to 01b, RXD must be idle for more than 8 frames before the IDLE bit is asserted. If the bits are set to 10b, RXD must be idle for more than 16 frames before the IDLE bit is asserted. If the bits are set to 11b, RXD must be idle for more than 32 frames before the IDLE bit is asserted (see Table 28-23). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-37 Universal Asynchronous Receiver/Transmitters (UART) Table 28-23. Detection Truth Table IDEN 0 1 1 1 1 ICD [1] X 0 0 1 1 ICD [0] X 0 1 0 1 IDLE 0 asserted after 4 idle frames asserted after 8 idle frames asserted after 16 idle frames asserted after 32 idle frames ipi_uart_rx_b 1 asserted after 4 idle frames asserted after 8 idle frames asserted after 16 idle frames asserted after 32 idle frames Note: This table assumes that no other interrupt is set at the same time this interrupt is set for the ipi_uart_rx_b signal. This table shows how this interrupt affects the ipi_uart_rx_b signal. During a normal message there is no idle time between frames. When all of the information bits in a frame are logic 1s, the start bit ensures that at least one logic 0 bit time occurs for each frame so that the IDLE bit is not asserted. 28.4.4.2.3 Aging Character Detect The receiver block also includes the possibility to detect when at least one character has been sitting into the RxFIFO for a time corresponding to 8 characters. This aging character capability allows the UART to inform the MCU that there is less character into the RxFIFO than the Rx trigger and, no new character has been detected on the RXD line. The aging capability is a timer which starts to count as soon as there is one character in RxFIFO. This counter is reset when either a RxFIFO read is performed or another character has been received in RxFIFO. If none of those two events occurs, the bit AGTIM (USR1[8]) is set when the counter has measured a time corresponding to 8 characters. AGTIM is cleared by writing a 1 to it. AGTIM can flag an interrupt to MCU on ipi_uart_rx_b if ATEN (UCR2[3]) has been set. To summarize, AGTIM is set when: • There is at least one character into RxFIFO. • No read has occurred on RxFIFO and RXD line has stayed high, for a time corresponding to 8 characters. • The RxFIFO trigger is not reached (RRDY=0). 28.4.4.2.4 Receiver Wake The WAKE bit (USR2[7]) is set when the receiver detects a qualified the start bit, that is, which has lasted more than a half-bit duration. When the wake interrupt enable WKEN (UCR4[7]) bit is enabled, the receiver flags an interrupt (ipi_uart_mint_b) if the WAKE status bit is set. The WAKE bit is cleared by writing 1 to it. Writing 0 to the WAKE bit has no effect. When the asynchronous wake interrupt (AWAKE) is enabled (AWAKEN = UCR3[4] = 1), and the MCU is in Sleep Mode, and UART clocks have been shut-off, then a falling edge detected on the receive pin (RXD) asserts the AWAKE bit (USR1[4]) and the ipi_uart_mint_b interrupt to wake the MCU from Sleep Mode. Re-enable UART clocks and clear the AWAKE bit by writing 1 to it. Writing 0 to the AWAKE bit has no effect. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-38 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) If the asynchronous IR WAKE interrupt is enabled (AIRINTEN = UCR3[5] = 1), the UART is configured for IR mode, and if MCU is in Sleep Mode, and UART clocks have been shut-off, and a falling edge is detected on the receive pin (RXD_IR), then this asserts the AIRINT bit (USR1[5]), and the ipi_uart_mint_b interrupt wakes the MCU from Sleep Mode. Re-enable UART clocks and clear the AIRINT bit by writing 1 to it. Writing 0 to the AIRINT bit has no effect. Recommended procedure for programming the asynchronous interrupts is to first clear them by writing 1 to the appropriate bit in the UART Status Register 1 (USR1). Poll or enable the interrupt for the Receiver IDLE Interrupt Flag (RXDS) in the USR1. When asserted, the RXDS bit indicates to the software that the receiver state machine is in the idle state, the next state is idle, and the RXD pin is idle (high). After following this procedure, enable the asynchronous interrupt and enter Sleep Mode. 28.4.4.2.5 Receiving a BREAK Condition A BREAK condition is received when the receiver detects all 0s (including a 0 during the bit time of the stop bit) in a frame. The BREAK condition asserts the BRCD bit (USR2[2]) and writes only the first BREAK character to the RxFIFO. Clear the BRCD bit by writing 1 to it. Writing 0 to the BRCD bit has no effect. When asserted BRCD can generate an interrupt on ipi_uart_mint_b. The interrupt generation can be masked using the control bit BKEN (UCR4[2]). Receiving a break condition will also effect the following bits in the receiver register URXD: URXD(11) = BRK. While high this bit indicates that the current char was detected as a break. URXD(12) = FRMERR. The frame error bit will always be set when BRK is set. URXD(10) = PRERR. If odd parity was selected the parity error bit will also be set when BRK is set. URXD(14) = ERR. The error detect bit indicates that the character present in the rx data field has an error status. This can be asserted by a break. 28.4.4.2.6 Vote Logic The vote logic block provides jitter tolerance and noise immunity by sampling with respect to a 16x clock (BRM_CLK) and using voting techniques to clean up the samples. The voting is implemented by sampling the incoming signal constantly on the rising edge of the BRM_CLK. The receiver is provided with the majority vote value, which is 2 out of the 3 samples. Examples of the majority vote results of the vote logic are shown in Table 28-24. Table 28-24. Majority Vote Results Samples 000 101 001 111 Vote 0 1 0 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-39 Universal Asynchronous Receiver/Transmitters (UART) The vote logic captures a sample on every rising edge of BRM_CLK, however the receiver uses 16x oversampling to take its value in the middle of the sample character. The receiver starts to count when the Start bit is set however it does not capture the contents of the RxFIFO at the time the Start bit is set. The start bit is validated when 0s are received for 7 consecutive 1/16 of bit times following the 1-to-0 transition. Once the counter reaches 0xF, it starts counting on the next bit and captures it in the middle of the sampling frame (see Table 28-24). All data bits are captured in the same manner. Once the stop bit is detected, the receiver shift register (SIPO_OUT) data is parallel shifted to the RxFIFO. I1 I2 I3 I4 I5 I6 I7 S S S S S S S S S S S S S S S S S S S S S S S S S S BRM_CLK NOISE RX_PIN 110 100 000 VOTE_SR [2:0] 110 101 011 111 111 111 111 111 111 110 100 000 000 000 000 000 000 000 000 000 000 000 000 000 001 011 111 110 101 011 111 111 111 111 111 111 VOTE Start Bit Figure 28-23. Majority Vote Results A new feature has been recently implemented, it allows to re-synchronize the counter on each edge of RXD line. This is automatic and allows to improve the immunity of UART against signal distortion. There is a special case when the BRM_CLK frequency is too low and is unable to capture a 0 pulse in IrDA. In this case, the software must set the IRSC bit so that the reference clock (after internal divider) is used for the voting logic. The pulse is validated by counting the length of the pulse. 28.4.5 Binary Rate Multiplier (BRM) The BRM sub-module receives ref_clk (ipg_perclk clock after divider). Form this clock, and with integer and non-integer division, BRM generates all baud rates. The input and output frequency ratio is programmed in the UART BRM Incremental Register (UBIR) and UART BRM MOD Register (UBMR). The output frequency is divided by the input frequency to produce this ratio. For integer division, set the UBIR = 0x000F and write the divisor to the UBMR register. All values written to these registers must be MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-40 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) one less than the actual value to eliminate division by 0 (undefined), and to increase the maximum range of the registers. Updating the BRM registers requires writing to both registers. The UBIR register must be written before writing to the UBMR register. If only one register is written to by the software, the BRM continues to use the previous values. The following examples show how to determine what values are to be programmed into UBIR and UBMR for a given reference frequency and desired baud rate. The following equation can be used to help determine these values: RefFreq BaudRate = ---------------------------------------------⎛ 16 × UBMR + 1⎞ --------------------------⎝ UBIR + 1 ⎠ With RefFreq (Hz): UART Reference Frequency (ipg_perclk after RFDIV divider). BaudRate (bit/s): Desired baudrate. Example 28-1. Integer Division ÷ 21 Reference Frequency = 19.44 MHz UBIR = 0x000F UBMR = 0x0014 Baudrate = 925.7 kbit/s NOTE Notice each value written to the registers is one less than the actual value. Example 28-2. Non-Integer Division Reference Frequency = 16 MHz Desired Baudrate = 920 kbits/s Eqn. 28-1 UBMR + 1 RefFreq 16 ×10 --------------------------- = ----------------------------------------- = ----------------------------------- = 1.087 3 UBIR + 1 16 × BaudRate 16 × 920 ×10 Ratio = 1.087 = 1087 / 1000 UBIR = 999 (decimal)= 0x3E7 UBMR = 1086 (decimal)= 0x43E 6 Example 28-3. Non-Integer Division Reference Frequency = 25 MHz Desired Baudrate = 920 kbit/s MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-41 Universal Asynchronous Receiver/Transmitters (UART) Ratio = 1.69837 = 625 / 368 UBIR = 367 (decimal)= 0x16F UBMR = 624 (decimal)= 0x270 Example 28-4. Non-Integer Division Reference Frequency: 30 MHz Desired Baudrate = 115.2 kbit/s Ratio = 16.276043 = 65153 / 4003 UBIR = 4002 (decimal) = 0x0FA2 UBMR = 65152 (decimal) = 0xFE80 28.4.6 Baud Rate Automatic Detection Logic When the baud rate automatic detection logic is enabled, the UART locks onto the incoming baud rate. To enable this feature, set the automatic detection of baud rate bit (ADBR = UCR1[14] = 1) and write 1 to the ADET bit (USR2[15]) to clear it. When ADET=0 and ADBR =1, the detection starts. Then, once the beginning of start bit (transition from 1-to-0 of RXD) has been detected, UART start a counter (UBRC) working at reference frequency. Once the end of start bit is detected (transition from 0-to-1 of RXD), the value of UBRC - 1 is directly copied into UBMR register. UBIR register is filled with 0x000F. So, at the end of start bit, registers gets following values: UBRC = number of reference clock periods (after divider) during Start bit. UBIR = 0x000F UBMR = UBRC - 1 The updated values of the 3 registers can be read. Table 28-25. Baud Rate Automatic Detection ADBR 0 1 1 ADET X 0 1 Baud Rate Detection Manual Configuration Auto Detection Started Auto Detection Complete ipi_uart_mint_b 1 1 0 Note: This table assumes that no other interrupt is set at the same time this interrupt is set for the ipi_uart_mint_b signal. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-42 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) 1 0 0 0 0 1 1 0 Idle Stop Bit Start Bit Transition from 0-to-1 Note: LSB transmitted first. Figure 28-24. Baud Rate Detection Protocol Diagram If any of the UART BRM registers are written to simultaneously by the baud rate automatic detection logic and peripheral data bus, the peripheral data bus has priority. 28.4.6.1 Baud Rate Automatic Detection Protocol The receiver must receive an ASCII character “A” or “a” to verify proper detection of the incoming baud rate. When an ASCII character “A” (0x41) or “a” (0x61) is received and no error occurs, the Automatic Detect baud rate bit is set (ADET=1) and if the interrupt is enabled (ADEN=UCR1[15]=1), an interrupt ipi_uart_mint_b is generated. When an ASCII character “A” or “a” is not received (because of a bit error or the reception of another character), the auto detection sequence restarts and waits for another 1-to-0 transition. As long as ADET = 0 and ADBR = 1, the UART continues to try to lock onto the incoming baud rate. Once the ASCII character “A” or “a” is detected and the ADET bit is set, the receiver ignores the ADBR bit and continues normal operation with the calculated baudrate. The UART interrupt is active (ipi_uart_mint_b = 0) as long as ADET = 1 and ADBR = 1. This can be disabled by clearing the automatic baud rate detection interrupt enable bit (ADEN = 0). Before starting an automatic baud rate detection sequence, set ADET = 0 and ADBR = 1. The RxFIFO must contain the ASCII character “A” or “a” following the automatic baud rate detection interrupt. The 16-bit UART Baud Rate Count Register (UBRC) is reset to 4 and stays at 0xFFFF when an overflow occurs. The UBRC register counts (measures) the duration of start bit. When the start bit is detected and counted, the UART Baud Rate Count Register retains its value until the next automatic baud rate detection sequence is initiated. The read only Baud Rate Count Register counts only when auto detection is enabled. 28.4.6.2 Baud Rate Automatic Detection Protocol Improved Several issues have been reported for ICs using the autobaud protocol like it is described above, especially for 57.6 kbit/s and 115.2 kbit/s. In consequence this protocol has been improved. The old one is still available in the current UART IP, but several modifications can also be used in order to make this autobaud MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-43 Universal Asynchronous Receiver/Transmitters (UART) detection more reliable. If the user wants to keep with the old method, he has to set the bit ADNIMP (UCR3[7]) to 1. If this bit is not set (default), the autobaud improvements will be used. Those improvements are mainly grouped in two categories: the new baudrate measurement and the new ACST bit (and associated interrupt). 28.4.6.3 New Baudrate Determination In order to fight against the problems caused by the distortion and the noise on the RXD line, the duration of the baudrate measurement has been extended. Previously, as described above, this determination was based on the measurement of the START bit duration. Now, this measurement is based on the duration of START bit + bit0. Bit0 is the first bit following the START bit. In fact, the counter which is started at the falling edge of START bit is no longer stopped at next rising edge (end of START bit), but it is stopped at the next falling edge (end of bit0). As the character sent is always a “A” (41h) or a “a” (61h), this second falling edge will be always be present and it will indicate the end of bit0. Once this counter is stopped, the result is divided by 2 and used by the BRM to determine the incoming baud rate. Note: UBRC register contains the result of this division by two, in consequence it reflects the measurement of the duration of one bit. 28.4.6.3.1 New Autobaud Counter Stopped Bit and Interrupt A new bit has been added in USR2 register: ACST (USR2[11]). This bit is set immediately after the determination of the baud rate, So, • If ADNIMP is not set (default), ACST is set to 1 after the end of bit 0, • If ADNIMP is set to 1, ACST is set to 1 at the end of START bit. If ACIEN (UCR3[0]) is set to 1, ACST will flag an interrupt on ipi_uart_mint_b signal. This interrupt informs the MCU the BRM has just been set with the result of the bit length measurement. If needed, the MCU can perform a read of UBMR (or UBRC) register and determine by itself the baudrate measured. Then the MCU has the possibility to correct the BRM registers with the nearest standardized baudrate. • • NOTE ACST is set only if ADBR is set to 1, that is, the UART is autobauding. Clear the ACST bit by writing 1 to it. Writing 0 to the ACST bit has no effect. 28.4.7 Escape Sequence Detection An escape sequence typically consists of 3 characters entered in rapid succession (such as +++). Because these are valid characters by themselves, the time between characters determines if it is a valid escape sequence. Too much time between two of the “+” characters is interpreted as two “+” characters, and not part of an escape sequence. The software chooses the escape character and writes its value to the UART Escape Character Register (UESC). The software must also enable escape detection feature by setting ESCEN (UCR2[11]) to 1. The hardware compares this value to incoming characters in the RxFIFO. When an escape character is detected, the internal escape timer starts to count. The software specifies a time-out value for the maximum MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-44 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) allowable time between 2 successive escape characters. The escape timer is programmable in intervals of 2 ms to a maximum interval of 8.192 seconds. Table 28-26. Escape Timer Scaling UTIM Register 0x000 0x001 0x002 0x003 0x004 … 0F8 0F9 … 9C3 … FFD FFE FFF Note: Maximum Time Between Specified Escape Characters 2 ms 4 ms 6 ms 8 ms 10 ms … 498 ms 500 ms … 5s … 8.188 s 8.190 s 8.192 s To calculate the time interval: (UTIM_Value + 1) × 0.002 = Time_Interval Example: (09C3 + 1) × 0.002 = 5 sec. The escape sequence detection feature is available for all the reference frequencies. Before using Escape Sequence Detection, the user must fill the ONEMS register. This 16-bit register must contain the value of the UART internal frequency divided by 1000. The internal frequency is obtained after the UART internal divider which is applied on ipg_perclk clock. Example: • If the UART BRM (ipg_perclk) input clock frequency is 66.5 MHz. • And if the UART input clock is divided by 2 with the internal divider: UFCR[9:7] = 3’b100 Eqn. 28-2 66.5 ×10 ONEMS = ----------------------- = 33250 = 81E2h 2 × 1000 6 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-45 Universal Asynchronous Receiver/Transmitters (UART) The escape sequence detection feature asserts the escape sequence interrupt flag (ESCF) bit when the escape sequence interrupt enable (ESCI) bit is set and an escape sequence is detected. Clear the ESCF bit by writing 1 to it. Writing 0 to the ESCF bit has no effect. 28.4.7.1 Generalities The Infrared interface is selected when IREN (UCR1[7]) is set to 1. The Infrared Interface is compatible with IrDA Serial Infrared Physical Layer Specification. In this specification, a “zero” is represented by a positive pulse, and a “one” is represented by no pulse (line remains low). In the UART: In TX: For each “zero” to be transmitted, a narrow positive pulse which is 3/16 of a bit time is generated. For each “one” to be transmitted no pulse is generated (output is low). External circuitry has to be provided to drive an Infrared LED. In RX: When receiving, a narrow negative pulse is expected for each “zero” transmitted while no pulse is expected for each “one” transmitted (input is high). Note that Rx part of IR block expects to receive an inverted signal compared to IrDA specification. Circuitry external to the IC transforms the Infrared signal to an electrical signal. The IR interface has an edge triggered interrupt (IRINT). This interrupt validates a zero bit being received. This interrupt is enabled by writing a “one” to ENIRI bit. The behavior of Infrared Interface is determined by three bits INVT (UCR3[1]), INVR (UCR4[9]), and IRSC (UCR4[5]). 28.4.7.2 Inverted Transmission and Reception Bits (INVT and INVR) The values of INVT and INVR depend of the IrDA transceiver connected on the TXD_IR and RXD_IR pins of the UART. If this transceiver is not inverting on both paths Tx and Rx (like in IrDA specification), that is, a Zero is represented as a positive pulse and a One is represented by no pulse (line remains low) for TX and RX, the bit INVT must be set to 0 and the bit INVR must be set to 1 (because Rx IR block expects an inverted signal). On the contrary user must set INVT=1 and INVR=0 if both paths of the transceiver are inverting (a Zero is represented as a negative pulse and a One is represented by no pulse (line remains high). The transceiver can also be inverting on only one path (Tx or Rx), in this case INVT and INVR must be together equal to 1 or to 0 (depending on which path is inverted). 28.4.7.3 InfraRed Special Case (IRSC) Bit The value to apply to IRSC bit depends essentially of two parameters: the baudrate and the Minimum Pulse Duration (MPD) of the transceiver. As already written, in IrDA a Zero is represented by a positive pulse. The IrDA specification says that for SIR (Serial IR) baudrates (from 2.4 kbit/s to 115.2 kbit/s) this nominal pulse duration is equal to 3/16 of a bit duration (at the selected baudrate). But, for all the baudrates a Minimum Pulse Duration is also specified. For SIR, the MPD is constant and equal to 1.41 us. In order to understand the meaning of bit IRSC, me must have an idea of how works the Rx path in IrDA. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-46 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) When UART is in IrDA mode, a Zero is not only detected by the state of the RXD_IR line, but also with the duration of the pulse. This pulse duration can be measured with 2 different clocks. The choice of the clock is done with IRSC bit. • If IRSC = 0, the clock used is the BRM clock. • If IRSC = 1, the clock used is the UART internal clock (UART clock after the divider (RFDIV)). In normal operation, IRSC=0. This means at any time, the user must be sure the frequency of BRM_clock is high enough to measure the pulse. In the UART and for IRSC=0, the pulse must last at least 2 BRM clock cycles. If this condition is not fulfilled, IRSC must be set to 1. Let’s take two examples, with the Minimum Pulse Duration equals to the MPD of the IrDA specification (in SIR). Example 28-5. Clock Example #1 The user wants to receive IrDA data at 115.2 kbit/s. The UBIR and UBMR registers are set in order to create the BRM_clock with a frequency of 16*baudrate = 16 * 115.2 = 1.843 MHz. But at the same time, in order to correctly detect the pulse, the user must be sure that 2* BRM_clock period is lower than 1.41us. Lets check: BRM_clock period = 1/1843000 = 542 ns So 2*BRM_clock period = 1.09 us < 1.41 us. It is fine. Example 28-6. Clock Example #2 This time the user wants to receive at 19.2 kbit/s. So, the BRM_clock is set to 16*19200 = 307.2 kHz. Let’s check if 2* BRM_clock period < 1.41 us: BRM_clock period =1/307200 = 3.25 us So 2*BRM_clock period = 6.50 us >> 1.41 us. It does not work. So, in this case, the BRM clock can not be used to measure the pulse duration, and the user must select the UART internal clock by setting IRSC =1. NOTE Like for Escape character detection, when IR Special Case is enabled (IRSC=1), the UART must measure a duration. In order to do that, the user must fill the ONEMS register. See Section 28.4.7, “Escape Sequence Detection.” 28.4.7.4 IrDA Interrupt Serial infrared mode (SIR) uses an edge triggered interrupt flag IRINT (USR2[8]). When INVR =0, detection of a falling edge on the UART_RXD pin assets the IRINT bit. When INVR=1, detection of a rising edge on the UART_RXD pin assets the IRINT bit. When IRINT and ENIRI bits are both asserted, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-47 Universal Asynchronous Receiver/Transmitters (UART) the ipi_uart_mint_b interrupt is asserted. Clear the IRINT bit by writing 1 to it. Writing 0 to the IRINT bit has no effect. 28.4.7.5 Conclusion About IrDA Before using the UART in IrDA, the baud rate limit must be calculated. This baud rate limit will inform the user if IRSC bit has to be set or not. Let’s determine this limit: As already written, if IRSC = 0 the following condition must always be fulfilled: 2 × BRMClockPeriod < MinPulseDuration So, 2 BRMClockFrequency > ------------MPD So, knowing BRM_clock frequency = 16 * Baudrate, we get: 1 BaudRate > ------------------------------------------------------------8 × MinPulseDuration So, the user needs to set IRSC = 0 when: If Minimum Pulse Duration = 2.5 us and Baudrate > 50 kbit/s. If Minimum Pulse Duration = 2.0 us and Baudrate > 62.5 kbit/s. If Minimum Pulse Duration = 1.41 us and Baudrate > 88.6 kbit/s. For baud rates lower than the limit, IRSC must be set to 1. 28.4.8 UART Operation in Low-Power System States The UART’s serial interface will operate as long as ipg_clk and ipg_perclk are provided. The RXEN (UCR2[1]), TXEN (UCR2[2]), and UARTEN (UCR1[0]) bits are set by the user and provide software control of low-power modes. The table below shows the UART functionality while in hardware controlled low-power modes. These modes are controlled by the signals ipg_doze and ipg_stop. Table 28-27. UART Low Power State Operation Doze State Normal State DOZE Bit = 0 UART-Clock UART Serial/IrDA ON ON ON ON DOZE Bit = 1 ON OFF OFF OFF Stop State MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 28-48 Freescale Semiconductor Universal Asynchronous Receiver/Transmitters (UART) While in Doze State, the UART behavior depends on the DOZE (UCR1[1]) control bit. While the DOZE bit is negated, the UART serial interface is operational. While the system is in the Doze State, and the DOZE bit is asserted, the UART is disabled. If the Doze State is entered with the DOZE bit asserted while the UART serial interface was receiving or transmitting data, it will complete the receive/transmit of the current character and signal to the far-end transmitter/receiver to stop sending/receiving. The control/status/data registers will not change when getting into/out of low power modes. The following UART interrupts wake the MCU processor from Sleep Mode: • RTS (RTSD) • IrDA Asynchronous WAKE (AIRINT) • Asynchronous WAKE (AWAKE) Setting the UARTEN (UCR1[0]) bit to 0 shuts off the receiver and transmitter logic and the associated clocks. If the UART is used only in transmit mode, UARTEN and TXEN must be set to 1. If the UART is used only in receive mode, UARTEN and RXEN must be set to 1. Setting TXEN or RXEN to 0 allows to save a lot of power. When an asynchronous WAKE interrupt exits the MCU from Sleep Mode, make sure that a dummy character is sent first because the first character may not be received correctly. 28.4.9 UART Operation in System Debug State The bit UTS [11] controls whether the UART will respond to the input signal ipg_debug, or whether it will continue to run as normal. If the UART is programmed to respond to ipg_debug: 1. The UART will halt all operations upon detecting the ipg_debug input. 2. A transfer in progress, either to/from a core (via the IP bus interface) or to/from an external device, will be completed before halting. This means a single byte/word transfer, not an entire FIFO. Reception of any further data from an external device will be disabled. 3. Internal registers will continue to be writable and readable via the IP bus interface. A read will leave the contents unaffected. 4. The RX FIFO is affected in debug mode in the following way: a) All writes into the RX FIFO are prevented. b) The bit RXDBG (UTS[9]) is used to select the readability of the RX FIFO during debug mode: —RXDBG = 0: hold the read pointer at the location it had upon entering debug mode, and URXD register returns only the data value at that location, no matter how many reads attempted. —RXDBG = 1, selectable at any time: Allow to read the characters received in Rx FIFO. It will not be possible to re-read previously read locations, nor will it be possible to readjust the read pointer to the value it had prior to entering debug mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 28-49 Programming IrDA Interface Appendix A Programming IrDA Interface A.1 High Speed As an example, the following sequence can be used to program the IrDA interface in order to send and receive characters at 115.2 kbit/s. Assumptions: • Input UART clock = 90 MHz • Internal clock divider = 3 (divide Input UART clock by 3) • Baud rate = 115.2 kbit/s • IrDA transceiver is not inverting on both channels: for Tx and Rx, a Zero is represented by a positive pulse, and a One is represented by no pulse (line stays low). • Interrupt: Sent to MCU when 1 char is received into the Rx FIFO (RDR) Registers values and Programming orders: UCR1 = 0x0085 UCR1[7] = IREN = 1: Enable IR interface UCR1[0] = UARTEN = 1: Enable UART UTS = 0x0000 UFCR = 0x0981 TXTL[5:0] = 0x02: Default value RFDIV[2:0] = 0x3: Divide Input UART clock by 3 (resulting internal clock is 30 MHz) RXTL[5:0] = 0x01: Default value UBIR = 0x0202 UBMR = 0x20BE Baud rate = 115.2 kbit/s with internal clock = 30 MHz UCR2 = 0x4027 UCR2[14] = IRTS = 1: Ignore level of RTS input signal UCR2[5] = WS = 1: Characters are 8-bit length UCR2[2] = TXEN = 1: Enable Rx path UCR2 [1] = RXEN = 1: Enable Tx path UCR2[0] = SRST_B = 1: No software reset UCR3 = 0x0000 UCR4 = 0x8201 CTSTL[5:0] = 0x20: Default value UCR4[9] = INVR = 1: Inverted Infrared Reception (because IrDA transceiver is not inverting) UCR4[1] = DREN = 1: To enable RDR interrupt (sent when one char is received) The UART is ready to send a character as soon as there is a write into UTXD register. And an interrupt will be sent to MCU when a character is received. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 A-50 Freescale Semiconductor Programming IrDA Interface A.2 Low Speed This time, we keep the same assumptions but the speed is now 9.6 kbit/s. So, this baud rate is below the limit (even with a Min. Pulse Duration of 2.5 us) and thus IRSC and REF30 must be set to 1. Assumptions: • Input UART clock = 90 MHz • Internal clock divider = 3 (divide Input UART clock by 3) • Baud rate = 9.6 kbit/s • IrDA transceiver is not inverting on both channels: for Tx and Rx, a Zero is represented by a positive pulse, and a One is represented by no pulse (line stays low). • Interrupt: Sent to MCU when 1 char is received into the Rx FIFO (RDR) Registers values and Programming orders: UCR1 = 0x0085 UCR1[7] = IREN = 1: Enable IR interface UCR1[0] = UARTEN = 1: Enable UART UFCR = 0x0981 UFCR[15:10] = TXTL[5:0] = 0x02: Default value RFDIV[2:0] = 0x3: Divide Input UART clock by 3 (resulting internal clock is 30 MHz) UFCR[5:0] = RXTL[5:0] = 0x01: Default value UBIR = 0x00FF UBMR = 0xC354 Baud rate = 9.6 kbit/s with internal clock = 30 MHz UCR2 = 0x4027 UCR2[14] = IRTS = 1: Ignore level of RTS input signal UCR2[5] = WS = 1: Characters are 8-bit length UCR2[2] = TXEN = 1: Enable Rx path UCR2 [1] = RXEN = 1: Enable Tx path UCR2[0] = SRST_B = 1: No software reset UCR3 = 0x0004 UCR3[2] = REF30 = 1: Internal UART clock = 30 MHz UCR4 = 0x8221 UCR4[15:10] = CTSTL[5:0] = 0x20: Default value UCR4[9] = INVR = 1: Inverted Infrared Reception (because IrDA transceiver is not inverting) UCR4[5] = IRSC = 1: Because data rate is below the limit and thus the UART internal clock is used to measure the pulse duration. UCR4[1] = DREN = 1: To enable RDR interrupt (sent when one char is received) The UART is now ready to send a character as soon as there is a write into UTXD register. And an interrupt will be sent to MCU when a character is received. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor A-51 Programming IrDA Interface MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 A-52 Freescale Semiconductor Chapter 29 Fast Ethernet Controller (FEC) 29.1 Introduction This chapter provides a feature-set overview, a functional block diagram, and transceiver connection information for both the 10 and 100 Mbps MII (Media Independent Interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included. 29.2 Overview The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface, which uses a subset of the MII pins. 29.2.1 Features The FEC incorporates the following features: • Support for three different Ethernet physical interfaces: — 100-Mbps IEEE 802.3 MII — 10-Mbps IEEE 802.3 MII — 10-Mbps 7-wire interface (industry standard) • IEEE 802.3 full duplex flow control • Programmable max frame length supports IEEE 802.1 VLAN tags and priority • Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of 50MHz • Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25 MHz • Retransmission from transmit FIFO following a collision (no processor bus utilization) • Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization) • Address recognition — Frames with broadcast address may be always accepted or always rejected — Exact match for single 48-bit individual (unicast) address — Hash (64-bit hash) check of individual (unicast) addresses MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-1 Fast Ethernet Controller (FEC) — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode 29.3 Modes of Operation The primary operational modes are described in this section. 29.3.1 Full and Half Duplex Operation Full duplex mode is intended for use on point to point links between switches or end node to switch. Half duplex mode is used in connections between an end node and a repeater or between repeaters. Selection of the duplex mode is controlled by TCR[FDEN]. When configured for full duplex mode, flow control may be enabled. Refer to the TCR[RFC_PAUSE] and TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and Section 29.5.10, “Full Duplex Flow Control,” for more details. 29.3.2 Interface Options The following interface options are supported. A detailed discussion of the interface configurations is provided in Section 29.5.5, “Network Interface Options.” 29.3.2.1 10 Mbps and 100 Mbps MII Interface MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps operation. The MAC-PHY interface may be configured to operate in MII mode by asserting RCR[MII_MODE]. The speed of operation is determined by the FEC_TX_CLK and FEC_RX_CLK pins which are driven by the external transceiver. The transceiver will either auto-negotiate the speed or it may be controlled by software via the serial management interface (FEC_MDC/FEC_MDIO pins) to the transceiver. Refer to the MMFR and MSCR register descriptions as well as the section on the MII for a description of how to read and write registers in the transceiver via this interface. 29.3.2.2 10 Mpbs 7-Wire Interface Operation The FEC supports a 7-wire interface as used by many 10 Mbps ethernet transceivers. The RCR[MII_MODE] bit controls this functionality. If this bit is deasserted, the MII mode is disabled and the 10 Mbps, 7-wire mode is enabled. 29.3.3 Address Recognition Options The address options supported are promiscuous, broadcast reject, individual address (hash or exact match), and multicast hash match. Address recognition options are discussed in detail in Section 29.5.8, “Ethernet Address Recognition.” MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-2 Freescale Semiconductor Fast Ethernet Controller (FEC) 29.3.4 Internal Loopback Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in Section 29.5.13, “Internal and External Loopback.” 29.4 FEC Top-Level Functional Diagram The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. SIF Bus Controller CSR Descriptor Controller (RISC + microcode) RAM RAM I/F FIFO Controller DMA FEC Bus MII MIB Counters Transmit Receive MDO MDEN MDI I/O PAD FEC_TX_EN FEC_TX_CLK FEC_TXD[3:0] FEC_CRS FEC_TX_ER FEC_COL FEC_RX_CLK FEC_RX_DV FEC_RXD[3:0] FEC_RX_ER FEC_MDIO FEC_MDC MII/7-WIRE DATA OPTION Figure 29-1. FEC Block Diagram The descriptor controller is a RISC-based controller that provides the following functions in the FEC: • Initialization (those internal registers not initialized by the user or hardware) • High level control of the DMA channels (initiating DMA transfers) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-3 Fast Ethernet Controller (FEC) • • • Interpreting buffer descriptors Address recognition for receive frames Random number generation for transmit collision back-off timer NOTE For DMA references in this section, refer to the FEC’s DMA engine. This DMA engine is for the transfer of FEC data only, and is not related to the DMA controller described in Chapter 37, “Direct Memory Access Controller (DMAC).” The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block and receive data flows from the receive block into the receive FIFO. The user controls the FEC by writing, through the SIF (Slave Interface) module, into control registers located in each block. The CSR (Control and Status Register) block provides global control (for example, Ethernet reset and enable) and interrupt handling registers. The MII block provides a serial channel for control/status communication with the external physical layer device (transceiver). This serial channel consists of the FEC_MDC (Management Data Clock) and FEC_MDIO (Management Data Input/Output) lines of the MII interface. The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run independently. The Transmit and Receive blocks provide the Ethernet MAC functionality (with some assist from microcode). The Message Information Block (MIB) maintains counters for a variety of network events and statistics. It is not necessary for operation of the FEC but provides valuable counters for network management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3 counters. See Section 29.6.3, “MIB Block Counters Memory Map” for more information. 29.5 Functional Description This section describes the operation of the FEC, beginning with the hardware and software initialization sequence, then a detailed description of the functions of the FEC. 29.5.1 Initialization Sequence This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC, and what locations the user must initialize prior to enabling the FEC. 29.5.1.1 Hardware Controlled Initialization In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware reset deasserts output signals and resets general configuration bits. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-4 Freescale Semiconductor Fast Ethernet Controller (FEC) Other registers reset when the ECR[ETHER_EN] bit is cleared. ECR[ETHER_EN] is deasserted by a hard reset or may be deasserted by software to halt operation. By deasserting ECR[ETHER_EN], the configuration control registers such as the TCR and RCR will not be reset, but the entire data path will be reset. Table 29-1. ECR[ETHER_EN] De-Assertion Effect on FEC Register/Machine XMIT block RECV block DMA block RDAR TDAR Descriptor Controller block Reset Value Transmission is aborted (bad CRC appended) Receive activity is aborted All DMA activity is terminated Cleared Cleared Halt operation 29.5.2 User Initialization (Prior to Asserting ECR[ETHER_EN]) The user needs to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values will depend on the particular application. The sequence is not important. Ethernet MAC registers requiring initialization are defined in Table 29-2. Table 29-2. User Initialization (Before ECR[ETHER_EN]) Description Initialize EIMR Clear EIR (write 0xFFFF_FFFF) TFWR (optional) IALR/IAUR GAUR/GALR PALR/PAUR OPD (only needed for full duplex flow control) RCR TCR MSCR (optional) Clear MIB_RAM (locations $1002_B000+ 0x200-0x2FC) FEC FIFO/DMA registers that require initialization are defined in Table 29-3. Table 29-3. FEC User Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-5 Fast Ethernet Controller (FEC) Table 29-3. FEC User Initialization (Before ECR[ETHER_EN]) (continued) Description Initialize ETDSR Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring 29.5.3 Microcontroller Initialization In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted. After the microcontroller initialization sequence is complete, the hardware is ready for operation. Table 29-4 shows microcontroller initialization operations. Table 29-4. Microcontroller Initialization Description Initialize BackOff Random Number Seed Activate Receiver Activate Transmitter Clear Transmit FIFO Clear Receive FIFO Initialize Transmit Ring Pointer Initialize Receive Ring Pointer Initialize FIFO Count Registers 29.5.4 User Initialization (After Asserting ECR[ETHER_EN]) After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to the TDAR and RDAR. Refer to Section 29.6.5, “Buffer Descriptors” for more details. 29.5.5 Network Interface Options The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode (RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported by the EMAC. These signals are shown in Table 29-5 below. Table 29-5. MII Mode Signal Description Transmit Clock Transmit Enable Transmit Data EMAC pin FEC_TX_CLK FEC_TX_EN FEC_TXD[3:0] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-6 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-5. MII Mode (continued) Signal Description Transmit Error Collision Carrier Sense Receive Clock Receive Data Valid Receive Data Receive Error Management Data Clock Management Data Input/Output EMAC pin FEC_TX_ER FEC_COL FEC_CRS FEC_RX_CLK FEC_RX_DV FEC_RXD[3:0] FEC_RX_ER FEC_MDC FEC_MDIO The 7-wire serial mode interface (RCR[MII_MODE] = 0) operates in what is generally referred to as the “AMD” mode. 7-wire mode connections to the external transceiver are shown in Table 29-6. Table 29-6. 7-Wire Mode Configuration SIGNAL DESCRIPTION Transmit Clock Transmit Enable Transmit Data Collision Receive Clock Receive Data Valid Receive Data EMAC PIN FEC_TX_CLK FEC_TX_EN FEC_TXD[0] FEC_COL FEC_RX_CLK FEC_RX_DV FEC_RXD[0] 29.5.6 FEC Frame Transmission The Ethernet transmitter is designed to work with almost no intervention from software. Once ECR[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet MAC is able to transmit onto the network. When the transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit logic will assert FEC_TX_EN and start transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then the frame information from the FIFO. However, the controller defers the transmission if the network is busy (FEC_CRS asserts). Before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See Section 29.5.14.1, “Transmission Errors” for more details. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-7 Fast Ethernet Controller (FEC) If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they do not have to be retrieved from system memory in case of a collision. This improves bus utilization and latency in case immediate retransmission is necessary. When all the frame data has been transmitted, the FCS (Frame Check Sequence or 32-bit Cyclic Redundancy Check, CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC will be appended to the frame data regardless of the TC bit value. Following the transmission of the CRC, the Ethernet controller writes the frame status information to the MIB block. Short frames are automatically padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of frame buffer = 1). Both buffer (TXB) and frame (TXF) interrupts may be generated as determined by the settings in the EIMR. The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will be asserted, however the entire frame will be transmitted (no truncation). To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the TCR[GTS] is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues transmission until the current frame either finishes or terminates with a collision. After the transmitter has stopped the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with the next frame. The Ethernet controller transmits bytes least significant bit first. 29.5.7 FEC Frame Reception The FEC receiver is designed to work with almost no intervention from the host and can perform address recognition, CRC checking, short frame checking, and maximum frame length checking. When the driver enables the FEC receiver by asserting ECR[ETHER_EN], it will immediately start processing receive frames. When FEC_RX_DV asserts, the receiver will first check for a valid PA/SFD header. If the PA/SFD is valid, it will be stripped and the frame will be processed by the receiver. If a valid PA/SFD is not found, the frame will be ignored. In serial mode, the first 16 bit times of RX_D0 following assertion of FEC_RX_DV are ignored. Following the first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected, the PA/SFD sequence is complete. In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored. After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-8 Freescale Semiconductor Fast Ethernet Controller (FEC) Once a collision window (64 bytes) of data has been received and if address recognition has not rejected the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed on to the DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions, which indicate serious LAN problems. During reception, the Ethernet controller checks for various error conditions and once the entire frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See Section 29.5.14.2, “Reception Errors” for more details. Receive Buffer (RXB) and Frame Interrupts (RXF) may be generated if enabled by the EIMR register. A receive error interrupt is babbling receiver error (BABR). Receive frames are not truncated if they exceed the max frame length (MAX_FL); however, the BABR interrupt will occur and the LG bit in the Receive Buffer Descriptor (RxBD) will be set. See Section 29.6.5.2, “Ethernet Receive Buffer Descriptor (RxBD)” for more details. When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RXF bit in EIR, maskable by RXF bit in EIMR), indicating that a frame has been received and is in memory. The Ethernet controller then waits for a new frame. The Ethernet controller receives serial data LSB first. 29.5.8 Ethernet Address Recognition The FEC filters the received frames based on destination address (DA) type — individual (unicast), group (multicast), or broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames is illustrated in the figures below. Address recognition is accomplished through the use of the receive block and microcode running on the microcontroller. The flowchart shown in Figure 29-2 illustrates the address recognition decisions made by the receive block, while Figure 29-3 illustrates the decisions made by the microcontroller. If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is deasserted, then the frame will be accepted unconditionally, as shown in Figure 29-2. Otherwise, if the DA is not a broadcast address, then the microcontroller runs the address recognition subroutine, as shown in Figure 29-3. If the DA is a group (multicast) address and flow control is disabled, then the microcontroller will perform a group hash table lookup using the 64-entry hash table programmed in GAUR and GALR. If a hash match occurs, the receiver accepts the frame. If flow control is enabled, the microcontroller will do an exact address match check between the DA and the designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines that the received frame is a valid PAUSE frame, then the frame will be rejected. Note the receiver will detect a PAUSE frame with the DA field set to either the designated PAUSE DA or the unicast physical address. If the DA is the individual (unicast) address, the microcontroller performs an individual exact match comparison between the DA and 48-bit physical address that the user programs in the PALR and PAUR MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-9 Fast Ethernet Controller (FEC) registers. If an exact match occurs, the frame is accepted; otherwise, the microcontroller does an individual hash table lookup using the 64-entry hash table programmed in registers, IAUR and IALR. In the case of an individual hash match, the frame is accepted. Again, the receiver will accept or reject the frame based on PAUSE frame detection, shown in Figure 29-2. If neither a hash match (group or individual), nor an exact match occur, then if promiscuous mode is enabled (RCR[PROM] = 1), then the frame will be accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and promiscuous mode is enabled, then the frame will be accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. In general, when a frame is rejected, it is flushed from the FIFO. Accept/Reject Frame True Broadcast Addr ? False Receive Address Recognition False BC_REJ = 1 ? True Hash Match ? False True Receive Frame Set BC bit in RCV BD Receive Frame Set MC bit in RCV BD if multicast True Exact Match ? False Pause Frame ? False PROM = 1 ? True False True Reject Frame Flush from FIFO Receive Frame Reject Frame Flush from FIFO Receive Frame Set M (Miss) bit in Rcv BD Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if broadcast NOTES: BC_REJ - field in RCR register (BroadCast REJect) PROM - field in RCR register Pause Frame - valid PAUSE frame received Figure 29-2. Ethernet Address Recognition—Receive Block Decisions MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-10 Freescale Semiconductor Fast Ethernet Controller (FEC) Receive Address Recognition Group I/G Address ? Individual FCE ? False True False Exact Match ? True False Pause Address ? True Hash Search Individual Table Receive Frame Receive Frame Hash Search Group Table Match ? False True True Match ? False Receive Frame Reject Frame Flush from FIFO Receive Frame Reject Frame Flush from FIFO NOTES: FCE - field in RCR register (Flow Control Enable) I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame) Figure 29-3. Ethernet Address Recognition—Microcode Decisions 29.5.9 Hash Algorithm The hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bit destination address is mapped into one of 64 bits, which are represented by 64 bits stored in GAUR, GALR (group address hash match) or IAUR, IALR (individual address hash match). This mapping is performed by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting the 6 most significant bits of the CRC-encoded result to generate a number between 0 and 63. The MSB of the CRC result selects GAUR (MSB = 1) or GALR (MSB = 0). The least significant 5 bits of the hash result select the bit within the selected register. If the CRC generator selects a bit that is set in the hash table, the frame is accepted; otherwise, it is rejected. For example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-11 Fast Ethernet Controller (FEC) The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the hash is: X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1 A table of example Destination Addresses and corresponding hash values is included below for reference. Table 29-7. Destination Address to 6-Bit Hash 48-bit DA 65:ff:ff:ff:ff:ff 55:ff:ff:ff:ff:ff 15:ff:ff:ff:ff:ff 35:ff:ff:ff:ff:ff b5:ff:ff:ff:ff:ff 95:ff:ff:ff:ff:ff d5:ff:ff:ff:ff:ff f5:ff:ff:ff:ff:ff db:ff:ff:ff:ff:ff fb:ff:ff:ff:ff:ff bb:ff:ff:ff:ff:ff 8b:ff:ff:ff:ff:ff 0b:ff:ff:ff:ff:ff 3b:ff:ff:ff:ff:ff 7b:ff:ff:ff:ff:ff 5b:ff:ff:ff:ff:ff 27:ff:ff:ff:ff:ff 07:ff:ff:ff:ff:ff 57:ff:ff:ff:ff:ff 77:ff:ff:ff:ff:ff f7:ff:ff:ff:ff:ff c7:ff:ff:ff:ff:ff 97:ff:ff:ff:ff:ff a7:ff:ff:ff:ff:ff 99:ff:ff:ff:ff:ff b9:ff:ff:ff:ff:ff 6-bit Hash (in hex) 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Hash Decimal Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-12 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-7. Destination Address to 6-Bit Hash (continued) 48-bit DA f9:ff:ff:ff:ff:ff c9:ff:ff:ff:ff:ff 59:ff:ff:ff:ff:ff 79:ff:ff:ff:ff:ff 29:ff:ff:ff:ff:ff 19:ff:ff:ff:ff:ff d1:ff:ff:ff:ff:ff f1:ff:ff:ff:ff:ff b1:ff:ff:ff:ff:ff 91:ff:ff:ff:ff:ff 11:ff:ff:ff:ff:ff 31:ff:ff:ff:ff:ff 71:ff:ff:ff:ff:ff 51:ff:ff:ff:ff:ff 7f:ff:ff:ff:ff:ff 4f:ff:ff:ff:ff:ff 1f:ff:ff:ff:ff:ff 3f:ff:ff:ff:ff:ff bf:ff:ff:ff:ff:ff 9f:ff:ff:ff:ff:ff df:ff:ff:ff:ff:ff ef:ff:ff:ff:ff:ff 93:ff:ff:ff:ff:ff b3:ff:ff:ff:ff:ff f3:ff:ff:ff:ff:ff d3:ff:ff:ff:ff:ff 53:ff:ff:ff:ff:ff 73:ff:ff:ff:ff:ff 23:ff:ff:ff:ff:ff 13:ff:ff:ff:ff:ff 3d:ff:ff:ff:ff:ff 0d:ff:ff:ff:ff:ff 6-bit Hash (in hex) 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 Hash Decimal Value 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-13 Fast Ethernet Controller (FEC) Table 29-7. Destination Address to 6-Bit Hash (continued) 48-bit DA 5d:ff:ff:ff:ff:ff 7d:ff:ff:ff:ff:ff fd:ff:ff:ff:ff:ff dd:ff:ff:ff:ff:ff 9d:ff:ff:ff:ff:ff bd:ff:ff:ff:ff:ff 6-bit Hash (in hex) 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f Hash Decimal Value 58 59 60 61 62 63 29.5.10 Full Duplex Flow Control Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration. To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] asserted) and flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause frame when the fields of the incoming frame match the pause frame specifications, as shown in the table below. In addition, the receive status associated with the frame should indicate that the frame is valid. 48-bit Destination Address 48-bit Source Address 16-bit Type 16-bit Opcode 16-bit PAUSE Duration 0x0180_c200_0001 or Physical Address Any 0x8808 0x0001 0x0000 to 0xFFFF Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs an address recognition subroutine to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is asserted by the FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to increment. Note that the pause timer makes use of the transmit back-off timer hardware, which is used for tracking the appropriate collision back-off timer in half-duplex mode. The pause timer increments once every slot time, until OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data frame transmission to resume. Note that the receive flow control pause (TCR[RFC_PAUSE]) status bit is asserted while the transmitter is paused due to reception of a pause frame. To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow control pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause (TCR[TFC_PAUSE]), the transmitter asserts TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted. On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are deasserted internally. The user must specify the desired pause duration in the OPD register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-14 Freescale Semiconductor Fast Ethernet Controller (FEC) Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit flow control pause (TCR[TFC_PAUSE]) still may be asserted and will cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt will not be asserted. 29.5.11 Inter-Packet Gap (IPG) Time The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the back-off algorithm completes, the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it will be ignored and a collision will occur. The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an inter-packet gap between receive frames is less than 28 bit times, the following frame may be discarded by the receiver. 29.5.12 Collision Handling If a collision occurs during frame transmission, the Ethernet controller will continue the transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the preamble sequence, the JAM pattern will be sent after the end of the preamble sequence. If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits a random number of slot times. A slot time is 512 bit times. If a collision occurs after 512 bit times, then no retransmission is performed and the end of frame buffer is closed with a Late Collision (LC) error indication. 29.5.13 Internal and External Loopback Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal and external loopback are configured using combinations of the LOOP and DRT bits in the RCR register and the FDEN bit in the TCR register. For both internal and external loopback set FDEN = 1. For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. FEC_TX_EN and FEC_TX_ER will not assert during internal loopback. During internal loopback, the transmit/receive data rate is higher than in normal operation because the internal system clock is used by the transmit and receive blocks instead of the clocks from the external transceiver. This will cause an increase in the required system bus bandwidth for transmit and receive data being DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the frames to prevent transmit FIFO underrun and receive FIFO overflow. For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for loopback. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-15 Fast Ethernet Controller (FEC) 29.5.14 Ethernet Error-Handling Procedure The Ethernet controller reports frame reception and transmission error conditions using the FEC RxBDs, the EIR register, and the MIB block counters. 29.5.14.1 Transmission Errors 29.5.14.1.1 Transmitter Underrun If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed. The UN bit is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame. The “UN” interrupt will be asserted if enabled in the EIMR register. 29.5.14.1.2 Retransmission Attempts Limit Expired When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and the RL bit is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame. The “RL” interrupt will be asserted if enabled in the EIMR register. 29.5.14.1.3 Late Collision When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and the LC bit is set in the EIR register. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame. The “LC” interrupt will be asserted if enabled in the EIMR register. 29.5.14.1.4 Heartbeat Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a good self-test, the transceiver indicates a collision to the FEC within 4 microseconds after completion of a frame transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error on the network, but is rather an indication that the transceiver still seems to be functioning properly. This is called the heartbeat condition. If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the FEC after a frame transmission, then a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets the HB bit in the EIR register, and generates the HBERR interrupt if it is enabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-16 Freescale Semiconductor Fast Ethernet Controller (FEC) 29.5.14.2 Reception Errors 29.5.14.2.1 Overrun Error If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV bit in the RxBD. All subsequent data in the frame will be discarded and subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available. At this point the receive frame/status word is written into the FIFO with the OV bit set. This frame must be discarded by the driver. 29.5.14.2.2 Non-Octet Error (Dribbling Bits) The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error, then the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, then no error is reported. 29.5.14.2.3 CRC Error When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the RxBD. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required. 29.5.14.2.4 Frame Length Violation When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and the LG bit in the end of frame RxBD will be set. The frame is not truncated unless the frame length exceeds 2047 bytes). 29.5.14.2.5 Truncation When the receive frame length exceeds 2047 bytes the frame is truncated and the TR bit is set in the receive BD. 29.6 Memory Map and Register Definition This section gives an overview of the registers, followed by a description of the buffers. The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The CSRs are used for mode control and to extract global status information. The descriptors are used to pass data buffers and related buffer information between the hardware and software. 29.6.1 High-Level Module Memory Map The FEC implementation requires a 1-Kbyte memory map space. This is divided into 2 sections of 512 bytes each. The first is used for control/status registers. The second contains event/statistic counters held in the MIB block. Table 29-8 defines the top level memory map. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-17 Fast Ethernet Controller (FEC) Table 29-8. Module Memory Map Address 0x1002_B + 0x000-1FF 0x1002_B + 0x200-3FF Function Control/Status Registers MIB Block Counters 29.6.2 Detailed Memory Map (Control/Status Registers) Table 29-9. FEC Register Memory Map Table 29-9 shows the FEC register memory map with each register address, name, and a brief description. Address 0x1002_B004 (EIR) 0x1002_B008 (EIMR) 0x1002_B010 (RDAR) 0x1002_B014 (TDAR) 0x1002_B024 (ECR) 0x1002_B040 (MMFR) 0x1002_B044 (MSCR) 0x1002_B064 (MIBC) 0x1002_B084 (RCR) 0x1002_B0C4 (TCR) 0x1002_B0E4 (PALR) 0x1002_B0E8 (PAUR) 0x1002_B0EC (OPD) 0x1002_B118 (IAUR) 0x1002_B11C (IALR) Register Interrupt Event Register Interrupt Mask Register Receive Descriptor Active Register Transmit Descriptor Active Register Ethernet Control Register MII Management Frame Register MII Speed Control Register MIB Control/Status Register Receive Control Register Transmit Control Register Physical Address Low Register Physical Address High Register Opcode/Pause Duration Descriptor Individual Upper Address Register Descriptor Individual Lower Address Register Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0xF000_0000 Undefined 0x0000_0000 0x0000_0000 0x05EE_0001 0x0000_0000 Undefined See Section See Section Undefined Undefined Section/Page 29.6.4.1/29-21 29.6.4.2/29-23 29.6.4.3/29-23 29.6.4.4/29-24 29.6.4.5/29-25 29.6.4.6/29-25 29.6.4.7/29-27 29.6.4.8/29-28 29.6.4.9/29-29 29.6.4.10/29-30 29.6.4.11/29-30 29.6.4.12/29-31 29.6.4.13/29-31 29.6.4.14/29-32 29.6.4.15/29-32 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-18 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-9. FEC Register Memory Map Address 0x1002_B120 (GAUR) 0x1002_B124 (GALR) 0x1002_B144 (TFWR) 0x1002_B14C (FRBR) 0x1002_B150 (FRSR) 0x1002_B180 (ERDSR) 0x1002_B184 (ETDSR) 0x1002_B188 (EMRBR) Register Descriptor Group Upper Address Register Descriptor Group Lower Address Register Transmit FIFO Watermark FIFO Receive Bound Register FIFO Receive FIFO Start Register Pointer to Receive Descriptor Ring Pointer to Transmit Descriptor Ring Maximum Receive Buffer Size Access R/W R/W R/W R R R/W R/W R/W Reset Value Undefined Undefined 0x0000_0001 0x0000_0600 0x0000_0500 Undefined Undefined Undefined Section/Page 29.6.4.16/29-33 29.6.4.17/29-33 29.6.4.18/29-34 29.6.4.19/29-34 29.6.4.20/29-35 29.6.4.21/29-35 29.6.4.22/29-36 29.6.4.23/29-36 29.6.3 MIB Block Counters Memory Map Table 29-10 defines the MIB Counters memory map which defines the locations in the MIB RAM space where hardware maintained counters reside. These fall in the 0x200-0x3FF address offset range. The counters are divided into two groups. RMON counters are included which cover the Ethernet Statistics counters defined in RFC 1757. In addition to the counters defined in the Ethernet Statistics group, a counter is included to count truncated frames as the FEC only supports frame lengths up to 2047 bytes. The RMON counters are implemented independently for transmit and receive to insure accurate network statistics when operating in full duplex mode. IEEE counters are included which support the Mandatory and Recommended counter packages defined in section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The IEEE Basic Package objects are supported by the FEC but do not require counters in the MIB block. In addition, some of the recommended package objects which are supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are included as well. Table 29-10. MIB Counters Memory Map Offset 0x200 0x204 0x208 0x20C Mnemonic RMON_T_DROP RMON_T_PACKETS RMON_T_BC_PKT RMON_T_MC_PKT Description Count of frames not counted correctly RMON Tx packet count RMON Tx Broadcast Packets RMON Tx Multicast Packets MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-19 Fast Ethernet Controller (FEC) Table 29-10. MIB Counters Memory Map (continued) Offset 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C Mnemonic RMON_T_CRC_ALIGN RMON_T_UNDERSIZE RMON_T_OVERSIZE RMON_T_FRAG RMON_T_JAB RMON_T_COL RMON_T_P64 RMON_T_P65TO127 RMON_T_P128TO255 RMON_T_P256TO511 RMON_T_P512TO1023 RMON_T_P1024TO2047 RMON_T_P_GTE2048 RMON_T_OCTETS IEEE_T_DROP IEEE_T_FRAME_OK IEEE_T_1COL IEEE_T_MCOL IEEE_T_DEF IEEE_T_LCOL IEEE_T_EXCOL IEEE_T_MACERR IEEE_T_CSERR IEEE_T_SQE IEEE_T_FDXFC IEEE_T_OCTETS_OK RMON_R_PACKETS RMON_R_BC_PKT RMON_R_MC_PKT RMON_R_CRC_ALIGN RMON_R_UNDERSIZE RMON_R_OVERSIZE RMON_R_FRAG Description RMON Tx Packets w CRC/Align error RMON Tx Packets < 64 bytes, good crc RMON Tx Packets > MAX_FL bytes, good crc RMON Tx Packets < 64 bytes, bad crc RMON Tx Packets > MAX_FL bytes, bad crc RMON Tx collision count RMON Tx 64 byte packets RMON Tx 65 to 127 byte packets RMON Tx 128 to 255 byte packets RMON Tx 256 to 511 byte packets RMON Tx 512 to 1023 byte packets RMON Tx 1024 to 2047 byte packets RMON Tx packets w > 2048 bytes RMON Tx Octets Count of frames not counted correctly Frames Transmitted OK Frames Transmitted with Single Collision Frames Transmitted with Multiple Collisions Frames Transmitted after Deferral Delay Frames Transmitted with Late Collision Frames Transmitted with Excessive Collisions Frames Transmitted with Tx FIFO Underrun Frames Transmitted with Carrier Sense Error Frames Transmitted with SQE Error Flow Control Pause frames transmitted Octet count for Frames Transmitted w/o Error RMON Rx packet count RMON Rx Broadcast Packets RMON Rx Multicast Packets RMON Rx Packets w CRC/Align error RMON Rx Packets < 64 bytes, good crc RMON Rx Packets > MAX_FL bytes, good crc RMON Rx Packets < 64 bytes, bad crc MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-20 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-10. MIB Counters Memory Map (continued) Offset 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 Mnemonic RMON_R_JAB RMON_R_RESVD_0 RMON_R_P64 RMON_R_P65TO127 RMON_R_P128TO255 RMON_R_P256TO511 RMON_R_P512TO1023 RMON_R_P1024TO2047 RMON_R_P_GTE2048 RMON_R_OCTETS IEEE_R_DROP IEEE_R_FRAME_OK IEEE_R_CRC IEEE_R_ALIGN IEEE_R_MACERR IEEE_R_FDXFC IEEE_R_OCTETS_OK RMON Rx 64 byte packets RMON Rx 65 to 127 byte packets RMON Rx 128 to 255 byte packets RMON Rx 256 to 511 byte packets RMON Rx 512 to 1023 byte packets RMON Rx 1024 to 2047 byte packets RMON Rx packets w > 2048 bytes RMON Rx Octets Count of frames not counted correctly Frames Received OK Frames Received with CRC Error Frames Received with Alignment Error Receive Fifo Overflow count Flow Control Pause frames received Octet count for Frames Rcvd w/o Error Description RMON Rx Packets > MAX_FL bytes, bad crc 29.6.4 Register Descriptions The following sections describe each register in detail. 29.6.4.1 Ethernet Interrupt Event Register (EIR) When an event occurs that sets a bit in the EIR, an interrupt will be generated if the corresponding bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is cleared if a one is written to that bit position; writing zero has no effect. This register is cleared upon hardware reset. These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR, BABR, BABT, LC and RL. Interrupts resulting from internal errors are EBERR and UN. Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts since these errors will be visible to network management via the MIB counters. • HBERR - IEEE_T_SQE • BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC) • BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-21 Fast Ethernet Controller (FEC) • • • LATE_COL - IEEE_T_LCOL COL_RETRY_LIM - IEEE_T_EXCOL XFIFO_UN - IEEE_T_MACERR 0x1002_B004 (EIR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R HB BABR BABT GRA ERR w1c 0 14 TXF w1c 0 11 TXB w1c 0 10 RXF w1c 0 9 RXB w1c 0 8 MII w1c 0 7 EB ERR w1c 0 6 LC w1c 0 5 RL w1c 0 4 UN w1c 0 3 0 0 0 W w1c Reset 0 15 w1c 0 13 w1c 0 12 0 2 0 1 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-4. Ethernet Interrupt Event Register (EIR) Table 29-11. EIR Field Descriptions Field Description 31 Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window HBERR following a transmission. 30 BABR 29 BABT 28 GRA Babbling receive error. Indicates a frame was received with length in excess of RCR[MAX_FL] bytes. Babbling transmit error. Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition is caused by a frame that is too long is placed into the transmit data buffer(s). Truncation does not occur. Graceful stop complete. Indicates the graceful stop is complete. During graceful stop the transmitter is placed into a pause state after completion of the frame currently being transmitted. This bit is set by one of three conditions: 1) A graceful stop initiated by the setting of the TCR[GTS] bit is now complete. 2) A graceful stop initiated by the setting of the TCR[TFC_PAUSE] bit is now complete. 3) A graceful stop initiated by the reception of a valid full duplex flow control pause frame is now complete. Refer to Section 29.5.10, “Full Duplex Flow Control.” Transmit frame interrupt. Indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated. Transmit buffer interrupt. Indicates a transmit buffer descriptor has been updated. Receive frame interrupt. Indicates a frame has been received and the last corresponding buffer descriptor has been updated. Receive buffer interrupt. Indicates a receive buffer descriptor not the last in the frame has been updated. MII interrupt. Indicates the MII has completed the data transfer requested. Ethernet bus error. Indicates a system bus error occurred when a DMA transaction is underway. When the EBERR bit is set, ECR[ETHER_EN] is cleared, halting frame processing by the FEC. When this occurs, software needs to insure that the FIFO controller and DMA also soft reset. 27 TXF 26 TXB 25 RXF 24 RXB 23 MII 22 EBERR MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-22 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-11. EIR Field Descriptions (continued) Field 21 LC 20 RL 19 UN 18–0 Description Late collision. Indicates a collision occurred beyond the collision window (slot time) in half duplex mode. The frame truncates with a bad CRC and the remainder of the frame is discarded. Collision retry limit. Indicates a collision occurs on each of 16 successive attempts to transmit the frame. The frame is discarded without being transmitted and transmission of the next frame commences. This error can only occur in half duplex mode. Transmit FIFO underrun. Indicates the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded. Reserved, must be cleared. 29.6.4.2 Interrupt Mask Register (EIMR) The EIMR controls which interrupt events are allowed to generate actual interrupts. All implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the corresponding bits in both the EIR and EIMR are set, the interrupt will be signalled to the CPU. The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit. 0x1002_B008 (EIMR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 HB BABR BABT GRA W ERR Reset 0 15 R TXF 0 11 TXB 0 10 RXF 0 9 RXB 0 8 MII 0 7 EB ERR 0 6 LC 0 5 RL 0 4 UN 0 3 0 0 2 0 0 1 0 0 0 0 14 0 13 0 12 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-5. EIMR Register Table 29-12. EIMR Field Descriptions Field 31–19 See Figure 29-5 and Table 29-11 18–0 Description Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set. 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is not masked. Reserved, must be cleared. 29.6.4.3 Receive Descriptor Active Register (RDAR) RDAR is a command register, written by the user, that indicates that the receive descriptor ring has been updated (empty receive buffers have been produced by the driver with the empty bit set). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-23 Fast Ethernet Controller (FEC) Whenever the register is written, the RDAR bit is set. This is independent of the data actually written by the user. When set, the FEC will poll the receive descriptor ring and process receive frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a receive descriptor whose empty bit is not set, then the FEC will clear the RDAR bit and cease receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors have been placed into the receive descriptor ring. The RDAR is cleared at reset and when ECR[ETHER_EN] is cleared. 0x1002_B010 (RDAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 RDAR 0 000000000000000000000000 000000000000000000000000 Figure 29-6. RDAR Register Table 29-13. RDAR Field Descriptions Field 31–25 24 RDAR 23–0 Reserved, must be cleared. Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared. Reserved, must be cleared. Description 29.6.4.4 Transmit Descriptor Active Register (TDAR) The TDAR is a command register which should be written by the user to indicate that the transmit descriptor ring has been updated (transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor). Whenever the register is written, the TDAR bit is set. This value is independent of the data actually written by the user. When set, the FEC will poll the transmit descriptor ring and process transmit frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a transmit descriptor whose ready bit is not set, then the FEC will clear the TDAR bit and cease transmit descriptor ring polling until the user sets the bit again, signifying additional descriptors have been placed into the transmit descriptor ring. The TDAR is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set. 0x1002_B014 (TDAR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 TDAR 0 000000000000000000000000 000000000000000000000000 Figure 29-7. TDAR Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-24 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-14. TDAR Field Descriptions Field 31–25 24 TDAR 23–0 Reserved, must be cleared. Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared. Reserved, must be cleared. Description 29.6.4.5 Ethernet Control Register (ECR) ECR is a read/write user register, though both fields in this register may be altered by hardware as well. The ECR is used to enable/disable the FEC. 0x1002_B024 (ECR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER RESET _EN W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-8. ECR Register Table 29-15. ECR Field Descriptions Field 31–2 Reserved, must be cleared. Description 1 When this bit is set, FEC is enabled, and reception and transmission are possible. When this bit is cleared, ETHER_EN reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions: • ECR[RESET] is set by software, in which case ETHER_EN is cleared • An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN is cleared 0 RESET When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC. ETHER_EN is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in progress is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The reset sequence takes approximately 8 internal bus clock cycles after RESET is set. 29.6.4.6 MII Management Frame Register (MMFR) The MMFR is accessed by the user and does not reset to a defined value. The MMFR is used to communicate with the attached MII compatible PHY device(s), providing read/write access to their MII registers. Performing a write to the MMFR will cause a management frame to be sourced unless the MSCR has been programmed to 0. In the case of writing to MMFR when MSCR = 0, if the MSCR is then written to a non-zero value, an MII frame will be generated with the data previously written to the MMFR. This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-25 Fast Ethernet Controller (FEC) 0x1002_B040 (MMFR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W ST OP PA RA TA DATA Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-9. MMFR Register Table 29-16. MMFR Field Descriptions Field 31–30 ST 29–28 OP Description Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame. Operation code. 00 Write frame operation, but not MII compliant. 01 Write frame operation for a valid MII management frame. 10 Read frame operation for a valid MII management frame. 11 Read frame operation, but not MII compliant. PHY address. This field specifies one of up to 32 attached PHY devices. Register address. This field specifies one of up to 32 registers within the specified PHY device. Turn around. This field must be programmed to 10 to generate a valid MII management frame. Management frame data. This is the field for data to be written to or read from the PHY register. 27–23 PA 22–18 RA 17–16 TA 15–0 DATA To perform a read or write operation on the MII Management Interface, the MMFR must be written by the user. To generate a valid read or write management frame, the ST field must be written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame will be generated but will not comply with the IEEE 802.3 MII definition. To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR. Writing this pattern will cause the control logic to shift out the data in the MMFR following a preamble generated by the control state machine. During this time the contents of the MMFR will be altered as the contents are serially shifted and will be unpredictable if read by the user. Once the write management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR will match the original value written. To generate an MII Management Interface read frame (read a PHY register) the user must write {01 10 PHYAD REGAD 10 XXXX} to the MMFR (the content of the DATA field is a don’t care). Writing this pattern will cause the control logic to shift out the data in the MMFR following a preamble generated by the control state machine. During this time the contents of the MMFR will be altered as the contents are serially shifted, and will be unpredictable if read by the user. Once the read management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR will match the MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-26 Freescale Semiconductor Fast Ethernet Controller (FEC) original value written except for the DATA field whose contents have been replaced by the value read from the PHY register. If the MMFR is written while frame generation is in progress, the frame contents will be altered. Software should use the MII interrupt to avoid writing to the MMFR while frame generation is in progress. 29.6.4.7 MII Speed Control Register (MSCR) The MSCR provides control of the MII clock (FEC_MDC pin) frequency, and allows a preamble drop on the MII management frame. 0x1002_B044 (MSCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Access: User read/write 6 5 4 3 2 1 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_ PRE 0 MII_SPEED 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000 Figure 29-10. MSCR Register Table 29-17. MSCR Field Descriptions Field 31–8 7 DIS_PRE Reserved, must be cleared. Asserting this bit causes preamble (32 1’s) not to be prepended to the MII management frame. The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require it. Description 6–1 MII_SPEED controls the frequency of the MII management interface clock (FEC_MDC) relative to the internal bus MII_SPEED clock. A value of 0 in this field turns off the FEC_MDC and leaves it in low voltage state. Any non-zero value results in the FEC_MDC frequency of 1/(MII_SPEED × 2) of the internal bus frequency. 0 Reserved, must be cleared. The MII_SPEED field must be programmed with a value to provide an FEC_MDC frequency of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to a non-zero value in order to source a read or write management frame. After the management frame is complete the MSCR may optionally be set to zero to turn off the FEC_MDC. The FEC_MDC generated will have a 50% duty cycle except when MII_SPEED is changed during operation (change will take effect following either a rising or falling edge of FEC_MDC). If the internal bus clock is 25 MHz, programming this register to 0x0000_0005 results in an FEC_MDC as stated the equation below. 1 25 MHz × ------------ = 2.5 MHz 5×2 Eqn. 29-1 A table showing optimum values for MII_SPEED as a function of internal bus clock frequency is provided below. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-27 Fast Ethernet Controller (FEC) Table 29-18. Programming Examples for MSCR System Clock Frequency 25 MHz 33 MHz 40 MHz 50 MHz 66 MHz MII_SPEED (field in reg) 0x5 0x7 0x8 0xA 0xD FEC_MDC frequency 2.5 MHz 2.36 MHz 2.5 MHz 2.5 MHz 2.54 MHz 29.6.4.8 MIB Control Register (MIBC) The MIB control register is a read/write register used to provide control of and to observe the state of the MIB block. This register is accessed by user software if there is a need to disable the MIB block operation. For example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See Table 29-10 for the locations of the MIB counters. 0x1002_B064 (MIBC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W Reset MIB_ MIB_ IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS 1 1 000000000000000000000000000000 Figure 29-11. MIBC Register Table 29-19. MIBC Field Descriptions Field Description 31 A read/write control bit. If set, the MIB logic halts and not update any MIB counters. MIB_DIS 30 A read-only status bit. If set the MIB block is not currently updating any MIB counters. MIB_IDLE 29–0 Reserved. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-28 Freescale Semiconductor Fast Ethernet Controller (FEC) 29.6.4.9 Receive Control Register (RCR) The RCR is programmed by the user. The RCR controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time). 0x1002_B084 (RCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 MAX_FL 1 10 0 9 1 8 1 7 1 6 1 5 0 4 1 3 1 2 1 1 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCE 0 BC_ MII_ PROM DRT LOOP REJ MODE 0 0 0 0 1 Figure 29-12. RCR Register Table 29-20. RCR Field Descriptions Field 31–27 26–16 MAX_FL Reserved, must be cleared. Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive frames longer than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor. The recommended default value to be programmed by the user is 1518 or 1522 (if VLAN Tags are supported). Reserved, must be cleared. Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter will stop transmitting data frames for a given duration. Broadcast frame reject. If asserted, frames with DA (destination address) equals FF_FF_FF_FF_FF_FF are rejected unless the PROM bit is set. If both BC_REJ and PROM equals 1, frames with broadcast DA are accepted and the M (MISS) is set in the receive buffer descriptor. Promiscuous mode. All frames are accepted regardless of address matching. Media independent interface mode. Selects the external interface mode for both transmit and receive blocks. 0 7-wire mode (used only for serial 10 Mbps) 1 MII mode Disable receive on transmit. 0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 Disable reception of frames while transmitting (normally used for half duplex mode). Internal loopback. If set, transmitted frames are looped back internal to the device and transmit output signals are not asserted. The internal bus clock substitutes for the FEC_TXCLK when LOOP is asserted. DRT must be set to 0 when setting LOOP. Description 15–6 5 FCE 4 BC_REJ 3 PROM 2 MII_MODE 1 DRT 0 LOOP MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-29 Fast Ethernet Controller (FEC) 29.6.4.10 Transmit Control Register (TCR) This register is read/write and is written by the user to configure the transmit block. This register is cleared at system reset. Bits 2 and 1 should be modified only when ECR[ETHER_EN] = 0. 0x1002_B0C4 (TCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Access: User read/write 3 2 1 0 R W RFC_ 000000000000000000000000000 PAUSE TFC_ FDEN HBC GTS PAUSE 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-13. TCR Register Table 29-21. TCR Field Descriptions Field 31–5 Reserved, must be cleared. Description 4 Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause frame is RFC_PAUSE received and the transmitter pauses for the duration defined in this pause frame. This bit automatically clears when the pause duration is complete. 3 Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC stops TFC_PAUSE transmission of data frames after the current transmission is complete. At this time, GRA interrupt in the EIR register is asserted. With transmission of data frames stopped, MAC transmits a MAC Control PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, the MAC may continue transmitting a MAC Control PAUSE frame. 2 FDEN 1 HBC 0 GTS Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This bit should only be modified when ETHER_EN is cleared. Heartbeat control. If set, the heartbeat check performs following end of transmission and the HB bit in the status register is set if the collision input does not assert within the heartbeat window. This bit should only be modified when ETHER_EN is cleared. Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently transmitted is complete and GRA interrupt in the EIR register is asserted. If frame transmission is not currently underway, the GRA interrupt will be asserted immediately. Once transmission has completed, a restart can accomplish by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted. If an early collision occurs during transmission when GTS equals 1, transmission stops after the collision. The frame is transmitted again once GTS is cleared. There may be old frames in the transmit FIFO that transmit when GTS is reasserted. To avoid this, clear ECR[ETHER_EN] following the GRA interrupt. 29.6.4.11 Physical Address Low Register (PALR) The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recognition process to compare with the DA (Destination Address) field of receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte Source Address field when transmitting PAUSE frames. This register is not reset and must be initialized by the user. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-30 Freescale Semiconductor Fast Ethernet Controller (FEC) 0x1002_B0E4 (PALR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W PADDR1 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-14. PALR Register Table 29-22. PALR Field Descriptions Field Description 31–0 Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact PADDR1 match and the source address field in PAUSE frames. 29.6.4.12 Physical Address High Register (PAUR) The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition process to compare with the DA (Destination Address) field of receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) used for transmission of PAUSE frames. This register is not reset and bits 31:16 must be initialized by the user. 0x1002_B0E8 (PAUR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W PADDR2 TYPE Reset — — — — — — — — — — — — — — — — 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 Figure 29-15. PAUR Register Table 29-23. PAUR Field Descriptions Field Description 31–16 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address PADDR2 field in PAUSE frames. 15–0 TYPE Type field in PAUSE frames. These 16-bits are a constant value of 0x8808. 29.6.4.13 Opcode/Pause Duration Register (OPD) The OPD register is read/write accessible. This register contains the 16-bit Opcode, and 16-bit pause duration fields used in transmission of a PAUSE frame. The Opcode field is a constant value, 0x0001. When another node detects a PAUSE frame, that node will pause transmission for the duration specified in the pause duration field. This register is not reset and must be initialized by the user. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-31 Fast Ethernet Controller (FEC) 0x1002_B0EC (OPD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W OPCODE PAUSE_DUR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — — Figure 29-16. OPD Register Table 29-24. OPD Field Descriptions Field 31–16 OPCODE Opcode field used in PAUSE frames. These bits are a constant, 0x0001. Description 15–0 Pause Duration field used in PAUSE frames. PAUSE_DUR 29.6.4.14 Descriptor Individual Upper Address Register (IAUR) The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user. 0x1002_B118 (IAUR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W IADDR1 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-17. IAUR Register Table 29-25. IAUR Field Descriptions Field Description 31–0 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast IADDR1 address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. 29.6.4.15 Descriptor Individual Lower Address Register (IALR) The IALR is written by the user. This register contains the lower 32 bits of the 64-bit individual address hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user. 0x1002_B11C (IALR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W IADDR2 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-18. IALR Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-32 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-26. IALR Field Descriptions Field Description 31–0 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast IADDR2 address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. 29.6.4.16 Descriptor Group Upper Address Register (GAUR) The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user. 0x1002_B120 (GAUR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W GADDR1 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-19. GAUR Register Table 29-27. GAUR Field Descriptions Field Description 31–0 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for GADDR1 receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32. 29.6.4.17 Descriptor Group Lower Address Register (GALR) The GALR is written by the user. This register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user. 0x1002_B124 (GALR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access: User read/write 7 6 5 4 3 2 1 0 R W GADDR2 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-20. GALR Register Table 29-28. GALR Field Descriptions Field Description 31–0 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for GADDR2 receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-33 Fast Ethernet Controller (FEC) 29.6.4.18 Transmit FIFO Watermark Register (TFWR) The TFWR is a 2-bit read/write register programmed by the user to control the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value will minimize the risk of transmit FIFO underrun due to contention for the system bus. The byte counts associated with the TFWR field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data DMA channel). 0x1002_B144 (TFWR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Access: User read/write 6 5 4 3 2 1 0 R0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFWR 0 0 Figure 29-21. TFWR Register Table 29-29. TFWR Field Descriptions Field 31–2 1–0 TFWR Reserved, must be cleared. Number of bytes written to transmit FIFO before transmission of a frame begins 00 64 bytes written 01 64 bytes written 10 128 bytes written 11 192 bytes written Description 29.6.4.19 FIFO Receive Bound Register (FRBR) The FRBR is an 8-bit register that the user can read to determine the upper address bound of the FIFO RAM. Drivers can use this value, along with the FRSR to appropriately divide the available FIFO RAM between the transmit and receive data paths. 0x1002_B14C (FRBR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Access: User read-only 6 5 4 3 2 1 0 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 W R_BOUND 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Figure 29-22. FRBR Register Table 29-30. FRBR Field Descriptions Field 31–10 Description Reserved, read as 0 (except bit 10, which is read as 1). 9–2 Read-only. Highest valid FIFO RAM address. R_BOUND 1–0 Reserved, read as 0. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-34 Freescale Semiconductor Fast Ethernet Controller (FEC) 29.6.4.20 FIFO Receive Start Register (FRSR) The FRSR is an 8-bit register programmed by the user to indicate the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive. The FRSR is initialized by hardware at reset. FRSR only needs to be written to change the default value. 0x1002_B150 (FRSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Access: User read/write 6 5 4 3 2 1 0 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 W R_FSTART 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 Figure 29-23. FRSR Register Table 29-31. FRSR Field Descriptions Field 31–11 10 Reserved, must be cleared. Reserved, must be set. Description 9–2 Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper R_FSTART operation, ensure that R_FSTART is set to 0x48 or greater. 1–0 Reserved, must be cleared. 29.6.4.21 Receive Buffer Descriptor Ring Start Register (ERDSR) The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). This register is not reset and must be initialized by the user prior to operation. 0x1002_B180 (ERDSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Access: User read/write 6 5 4 3 2 1 0 R W R_DES_START 0 0 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-24. ERDSR Register Table 29-32. ERDSR Field Descriptions Field Description 31–2 Pointer to start of receive buffer descriptor queue. R_DES_START 1–0 Reserved, must be cleared. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-35 Fast Ethernet Controller (FEC) 29.6.4.22 Transmit Buffer Descriptor Ring Start Register (ETDSR) The ETDSR is written by the user. It provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). Bits 1 and 0 should be written to 0 by the user. Non-zero values in these two bit positions are ignored by the hardware. This register is not reset and must be initialized by the user prior to operation. 0x1002_B184 (ETDSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Access: User read/write 6 5 4 3 2 1 0 R W X_DES_START 0 0 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-25. Transmit Buffer Descriptor Ring Start Register (ETDSR) Field Description 31–2 Pointer to start of transmit buffer descriptor queue. X_DES_START 1–0 Reserved, must be cleared. 29.6.4.23 Receive Buffer Size Register (EMRBR) The EMRBR is a 9-bit register programmed by the user. The EMRBR dictates the maximum size of all receive buffers. Note that because receive frames will be truncated at 2k-1 bytes, only bits 10–4 are used. This value should take into consideration that the receive CRC is always written into the last receive buffer. To allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. The EMRBR must be evenly divisible by 16. To insure this, bits 3-0 are forced low. To minimize bus utilization (descriptor fetches) it is recommended that EMRBR be greater than or equal to 256 bytes. The EMRBR does not reset, and must be initialized by the user. 0x1002_B188 (EMRBR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Access: User read/write 6 5 4 3 2 1 0 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R_BUF_SIZE 000 0 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 29-26. EMRBR Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-36 Freescale Semiconductor Fast Ethernet Controller (FEC) Table 29-33. EMRBR Field Descriptions Field 31–11 Reserved, must be cleared. Description 10–4 Receive buffer size in bytes. R_BUF_SIZE 0x00 0 bytes 0x01 16 bytes 0x02 32 bytes ... 0x7F 2032 bytes 3–0 Reserved, must be cleared. 29.6.5 Buffer Descriptors This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is followed by a detailed description of the receive and transmit descriptor fields. 29.6.5.1 Driver/DMA Operation with Buffer Descriptors The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in one or more buffers. Associated with each buffer is a buffer descriptor (BD) which contains a starting address (pointer), data length, and status/control information (which contains the current state for the buffer). To permit maximum user flexibility, the BDs are also located in external memory and are read in by the FEC DMA engine. Software “produces” buffers by allocating/initializing memory and initializing buffer descriptors. Setting the RxBD[E] or TxBD[R] bit “produces” the buffer. Software writing to either the TDAR or RDAR tells the FEC that a buffer has been placed in external memory for the transmit or receive data traffic, respectively. The hardware reads the BDs and “consumes” the buffers after they have been produced. After the data DMA is complete and the buffer descriptor status bits have been written by the DMA engine, the RxBD[E] or TxBD[R] bit will be cleared by hardware to signal the buffer has been “consumed.” Software may poll the BDs to detect when the buffers have been consumed or may rely on the buffer/frame interrupts. These buffers may then be processed by the driver and returned to the free list. The ECR[ETHER_EN] signal operates as a reset to the BD/DMA logic. When ECR[ETHER_EN] is deasserted the DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The buffer descriptors are not initialized by hardware during reset. At least one transmit and receive buffer descriptor must be initialized by software before the ECR[ETHER_EN] bit is set. The buffer descriptors operate as two separate rings. ERDSR defines the starting address for receive BDs and ETDSR defines the starting address for transmit BDs. The last buffer descriptor in each ring is defined by the Wrap (W) bit. When set, W indicates that the next descriptor in the ring is at the location pointed to by ERDSR and ETDSR for the receive and transmit rings, respectively. NOTE Buffer descriptor rings must start on a 128-bit boundary. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-37 Fast Ethernet Controller (FEC) 29.6.5.1.1 Driver/DMA Operation with Transmit BDs Typically a transmit frame will be divided between multiple buffers. An example is to have an application payload in one buffer, TCP header in a 2nd buffer, IP header in a 3rd buffer, Ethernet/IEEE 802.3 header in a 4th buffer. The Ethernet MAC does not prepend the Ethernet header (Destination Address, Source Address, Length/Type field(s)), so this must be provided by the driver in one of the transmit buffers. The Ethernet MAC can append the Ethernet CRC to the frame. Whether the CRC is appended by the MAC or by the driver is determined by the TC bit in the transmit BD which must be set by the driver. The driver (TxBD software producer) should set up Tx BDs in such a way that a complete transmit frame is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized with pointer, length and control (W, L, TC, ABC) and then the TxBD[R] bits should be set = 1 in reverse order (3rd, 2nd, 1st BD) to insure that the complete frame is ready in memory before the DMA begins. If the TxBDs are set up in order, the DMA Controller could DMA the first BD before the 2nd was made available, potentially causing a transmit FIFO underrun. In the FEC, the DMA is notified by the driver that new transmit frame(s) are available by writing to the TDAR register. When this register is written to (data value is not significant) the FEC RISC will tell the DMA to read the next transmit BD in the ring. Once started, the RISC + DMA will continue to read and interpret transmit BDs in order and DMA the associated buffers, until a transmit BD is encountered with the R bit = 0. At this point the FEC will poll this BD one more time. If the R bit = 0 the second time, then the RISC will stop the transmit descriptor read process until software sets up another transmit frame and writes to TDAR. When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R bit, indicating that the hardware consumer is finished with the buffer. 29.6.5.1.2 Driver/DMA Operation with Receive BDs Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore the driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to the EMRBR register. The driver (RxBD software producer) should set up some number of “empty” buffers for the Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive DMA) will consume these buffers by filling them with data as frames are received and clearing the E bit and writing to the L (1 indicates last buffer in frame) bit, the frame status bits (if L = 1) and the length field. If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For non-last buffers, the length field in the receive BD will be written by the DMA (at the same time the E bit is cleared) with the default receive buffer length value. For end of frame buffers the receive BD will be written with L = 1 and information written to the status bits (M, BC, MC, LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher layers. The frame status/length information is written into the receive FIFO following the end of the frame (as a single 32-bit word) by the receive logic. The length field for the end of frame buffer will be written with the length of the entire frame, not just the length of the last buffer. For simplicity the driver may assign the default receive buffer length to be large enough to contain an entire frame, keeping in mind that a malfunction on the network or out of specification implementation could MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-38 Freescale Semiconductor Fast Ethernet Controller (FEC) result in giant frames. Frames of 2k (2048) bytes or larger are truncated by the FEC at 2047 bytes so software is guaranteed never to see a receive frame larger than 2047 bytes. Similar to transmit, the FEC will poll the receive descriptor ring after the driver sets up receive BDs and writes to the RDAR register. As frames are received the FEC will fill receive buffers and update the associated BDs, then read the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E bit = 0, it will poll this BD once more. If the BD = 0 a second time the FEC will stop reading receive BDs until the driver writes to RDAR. 29.6.5.2 Ethernet Receive Buffer Descriptor (RxBD) In the RxBD, the user initializes the E and W bits in the first longword and the pointer in second longword. When the buffer has been DMA’d, the Ethernet controller will modify the E, L, M, BC, MC, LG, NO, CR, OV, and TR bits and write the length of the used portion of the buffer in the first longword. The M, BC, MC, LG, NO, CR, OV and TR bits in the first longword of the buffer descriptor are only modified by the Ethernet controller when the L bit is set. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E RO1 W RO2 L — — M BC MC LG NO — CR OV TR Data Length Rx Data Buffer Pointer - A[31:16] Rx Data Buffer Pointer - A[15:0] Figure 29-27. Receive Buffer Descriptor (RxBD) Table 29-34. Receive Buffer Descriptor Field Definitions Word Offset + 0 Field 15 E Description Empty. Written by the FEC (=0) and user (=1). 0 The data buffer associated with this BD is filled with received data, or data reception has aborted due to an error condition. The status and length fields have been updated as required. 1 The data buffer associated with this BD is empty, or reception is currently in progress. Receive software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its value affect hardware. Wrap. Written by user. 0 The next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ERDSR. Receive software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its value affect hardware. Last in frame. Written by the FEC. 0 The buffer is not the last in a frame. 1 The buffer is the last in a frame. Reserved, must be cleared. Offset + 0 Offset + 0 14 RO1 13 W 12 RO2 11 L 10–9 Offset + 0 Offset + 0 Offset + 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-39 Fast Ethernet Controller (FEC) Table 29-34. Receive Buffer Descriptor Field Definitions (continued) Word Offset + 0 Field 8 M Description Miss. Written by the FEC. This bit is set by the FEC for frames accepted in promiscuous mode, but flagged as a miss by the internal address recognition. Therefore, while in promiscuous mode, the user can use the M-bit to quickly determine whether the frame was destined to this station. This bit is valid only if the L-bit is set and the PROM bit is set. 0 The frame was received because of an address recognition hit. 1 The frame was received because of promiscuous mode. Set if the DA is broadcast (FF-FF-FF-FF-FF-FF). Set if the DA is multicast and not BC. Rx frame length violation. Written by the FEC. A frame length greater than RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive data is not altered in any way unless the length exceeds 2032 bytes. Receive non-octet aligned frame. Written by the FEC. A frame that contained a number of bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary generated an error. This bit is valid only if the L-bit is set. If this bit is set the CR bit will not be set. Reserved, must be cleared. Receive CRC error. Written by the FEC. This frame contains a CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set. Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and are zero. This bit is valid only if the L-bit is set. Set if the receive frame is truncated (frame length > 2032 bytes). If the TR bit is set, frame must be discarded and the other error bits must be ignored as they may be incorrect. Data length. Written by the FEC. Data length is the number of octets written by the FEC into this BD’s data buffer if L equals 0 (the value will be equal to EMRBR), or the length of the frame including CRC if L equals 1. It is written by the FEC once as the BD is closed. RX data buffer pointer, bits [31:16]1 RX data buffer pointer, bits [15:0] Offset + 0 Offset + 0 Offset + 0 7 BC 6 MC 5 LG 4 NO 3 2 CR 1 OV 0 TR 15–0 Data Length 15–0 A[31:16] 15–0 A[15:0] Offset + 0 Offset + 0 Offset + 0 Offset + 0 Offset + 0 Offset + 2 0ffset + 4 Offset + 6 1 The receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. The Ethernet controller never modifies this value. NOTE Whenever the software driver sets an E bit in one or more receive descriptors, the driver should follow that with a write to RDAR. 29.6.5.3 Ethernet Transmit Buffer Descriptor (TxBD) Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs. The Ethernet controller confirms transmission by clearing the ready bit (R bit) when DMA of the buffer is MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-40 Freescale Semiconductor Fast Ethernet Controller (FEC) complete. In the TxBD the user initializes the R, W, L, and TC bits and the length (in bytes) in the first longword, and the buffer pointer in the second longword. The FEC will set the R bit = 0 in the first longword of the BD when the buffer has been DMA’d. Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 29.6.3, “MIB Block Counters Memory Map” for more details. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset + 0 Offset + 2 Offset + 4 Offset + 6 R TO1 W TO2 L TC ABC — — — — — — — — — Data Length Tx Data Buffer Pointer - A[31:16] Tx Data Buffer Pointer - A[15:0] Figure 29-28. Transmit Buffer Descriptor (TxBD) Table 29-35. Transmit Buffer Descriptor Field Definitions Word Offset + 0 Field 15 R Description Ready. Written by the FEC and the user. 0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 The data buffer, prepared for transmission by the user, has not been transmitted or currently transmits. The user may write no fields of this BD once this bit is set. Transmit software ownership. This field is reserved for software use. This read/write bit will not be modified by hardware, nor will its value affect hardware. Wrap. Written by user. 0 The next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ETDSR. Transmit software ownership. This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware. Last in frame. Written by user. 0 The buffer is not the last in the transmit frame 1 The buffer is the last in the transmit frame Transmit CRC. Written by user (only valid if L is set). 0 End transmission immediately after the last data byte 1 Transmit the CRC sequence after the last data byte Append bad CRC. Written by user (only valid if L is set). 0 No effect 1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value) Reserved, must be cleared. Data length, written by user. Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC. Bits [15:5] are used by the DMA engine; bits[4:0] are ignored. Offset + 0 Offset + 0 14 TO1 13 W 12 TO2 11 L 10 TC 9 ABC 8–0 15–0 Data Length Offset + 0 Offset + 0 Offset + 0 Offset + 0 Offset + 0 Offset + 2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 29-41 Fast Ethernet Controller (FEC) Table 29-35. Transmit Buffer Descriptor Field Definitions (continued) Word Offset + 4 Offset + 6 1 Field 15–0 A[31:16] 15–0 A[15:0] Tx data buffer pointer, bits [31:16]1 Tx data buffer pointer, bits [15:0] Description The transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller. NOTE Once the software driver has set up the buffers for a frame, it should set up the corresponding BDs. The last step in setting up the BDs for a transmit frame should be to set the R bit in the first BD for the frame. The driver should follow that with a write to TDAR which will trigger the FEC to poll the next BD in the ring. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 29-42 Freescale Semiconductor Chapter 30 High-Speed USB On-The-Go (HS USB-OTG) The USB module contains all of the functionality required to support three independent USB ports, compatible with the USB 2.0 specification. In addition to the normal USB functionality, the module also provides support for direct connections to on-board USB peripherals, and supports multiple interface types for serial transceivers. Figure 30-1 shows a block diagram of the USB module. USB Mirror Reg ULPI data and control IP bus IP2 AHB OTG CORE Serial Phy data & control ULPI/ Serial Mux CLK DIR NXT STP DATA0/OEn DATA1/Txdp DATA2/Txdm DATA3/Rxdp DATA4/Rxdm DATA5/rcv DATA6/Speed DATA7/Suspend OEn Txdp Txdm Rxdp Rxdm rcv Speed Suspend CLK DIR NXT STP DATA0/OEn DATA1/Txdp DATA2/Txdm DATA3/Rxdp DATA4/Rxdm DATA5/rcv DATA6/Speed DATA7/Suspend PWR Control Bypass mux and TLL control AHB TMAX HOST1 CORE PWR Control TLL control HOST2 CORE ULPI/ Serial Mux PWR Control IP bus USB Control Register Figure 30-1. USB Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-1 High-Speed USB On-The-Go (HS USB-OTG) 30.1 Overview The USB module provides high performance USB On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement and the ULPI 1.0 Low Pin Count specification. The module consists of 3 independent USB cores, each controlling 1 USB port. In addition to the USB cores, the module provides for a Transceiver-less Link (TLL) operation on host ports 1 and 2 and allows for routing the OTG transceiver interface to HOST port 1 such that this transceiver can be used to communicate with a USB peripheral connected to host port 1. 30.2 Features The USB module includes the following features: • Full Speed/Low speed Host only core (HOST 1) — Transceiverless Link Logic (TLL) for on board connection to a FS/LS USB peripheral — Bypass mode to route Host Port 1 signals to OTG I/O port • High Speed/Full Speed/Low Speed Host Only core (HOST2) — High Speed ULPI 1.0 compliant interface — Full Speed/Low Speed interface for Serial transceiver — TLL function for direct connection to USB peripheral in FS/LS (serial) operation • High speed OTG core — High Speed ULPI 1.0 compliant interface — Software configurable for ULPI or Serial transceiver interface — High Speed (with ULPI transceiver), Full Speed and Low Speed operation in HOST mode — High Speed (with ULPI transceiver), and Full Speed operation in Peripheral mode — Hardware support for OTG signaling, Session Request Protocol and Host Negotiation Protocol — Up to 8 bidirectional endpoints • Low power mode with local and remote wake-up capability • Serial PHY interfaces configurable for Bidirectional/Unidirectional and Differential/Single Ended • Embedded DMA controller 30.3 Modes of Operation The USB module has two main modes of operation; Normal mode and Bypass mode. Furthermore, the USB interfaces can be configured for High Speed operation (480 Mbps) and/or Full/Low speed operation (12/1.5 Mbps). This chapter details the configuration options. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-2 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.3.1 30.3.1.1 Operational Modes Normal Mode In normal mode, each USB core controls its corresponding PORT. Each port can work in 1 or more modes • Host Port 1: This port supports Full/Low speed and is used Serial transceiver only. — PHY mode: In this mode, an external serial transceiver is connected to the port. This is used for off-board USB connections — TLL mode: In TLL mode, internal logic is enabled to emulate the functionality of 2 back-to-back connected transceivers. This mode is typically used for on-board USB connections to USB-capable peripherals • Host Port 2 This port supports ULPI and Serial Transceivers. — Serial Interface mode PHY mode - for connections using transceivers TLL mode - for direct on-board connections to USB peripherals — ULPI interface ULPI is the low-pin count standard for connecting off-chip High-Speed USB transceivers to a USB device. When the port is configured for ULPI mode, only a ULPI compatible transceiver can be used • OTG port: This Port requires a transceiver and is intended for off-board USB connections. — Serial Interface mode In serial mode, a serial OTG transceiver must be connected. The port does not support dedicated signals for OTG signaling. Instead, a transceiver with built-in OTG registers must be used. Typically, the Transceiver registers are accessible over an I2C or SPI interface — ULPI Mode It this mode, a ULPI transceiver is connected to the port pins to support High-speed off board USB connections. ULPI mode is activated by writing the relevant register 30.3.1.2 Bypass Mode Bypass mode affects the operation of the OTG port and HOST port 1. This mode is only available when a serial transceiver is used on the OTG port, and the peripheral device on port 1 is using a TLL connection. Bypass mode is activated by setting the bypass bit in the USBCONTROL register. In this mode, the USB OTG port connections are internally routed to the USB HOST 1 port, such that the transceiver on the OTG port connects to a peripheral USB device on HOST port 1. The OTG core and the HOST 1 core are MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-3 High-Speed USB On-The-Go (HS USB-OTG) disconnected from their ports when bypass is active. The status of the DM and DP inputs for the cores is programmable in the USB Control Register (Table 30-2). 30.3.1.3 Low Power Mode Each of the three USB cores has an associated power control module that is controlled by the USB core and clocked on a 32 KHz clock. When a USB bus is idle, the transceiver can be placed in low power mode (suspend), after which the clocks to the USB core can be stopped. The 32 KHz low power clock must remain active as it is needed for wakeup detection. Either the local CPU or the remote USB Host/Peripheral can initiate a wake-up sequence to resume USB communication. 30.4 30.4.1 External Signal Description Overview See Table 30-3 for the list of signals entering and existing this module to peripherals within the chip. 30.4.2 Detailed Signal Descriptions Detailed signal descriptions for each module lists in Section 30.6, “Functional Description.” 30.5 Memory Map and Register Definitions Table 30-2. USB Module Memory Map Table 30-2 shows the USB module memory map. Address Base + 0x000 Base + 0x004 Base + 0x008 Base + 0x010 Base +0x014 Base +0x080 Base +0x084 Base +0x088 Base +0x08c Base +0x100 Base + 0x102 Base +0x104 Base +0x108 Controller OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG ID (UOG_ID) Use Access R R R R R RW RW RW RW R R R R Hardware General (UOG_HWGENERAL) Host Hardware Parameters (UOG_HWHOST) TX Buffer Hardware Parameters (UOG_HWTXBUF) RX Buffer Hardware Parameters (UOG_HWRXBUF) General Purpose Timer #0 Load(GPTIMER0LD) General Purpose Timer #0 Controller(GPTIMER0CTRL) General Purpose Timer #1 Load(GPTIMER0LD) General Purpose Timer #1 Controller(GPTIMER0CTRL) Capability Register Length (UOG_CAPLENGTH) Host Interface Version (UOG_HCIVERSION) Host Control Structural Parameters (UOG_HCSPARAMS) Control Capability Parameters (UOG_HCCPARAMS) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-4 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-2. USB Module Memory Map (continued) Address Base + 0x120 Base + 0x124 Base +0x140 Base +0x144 Base +0x148 Base + 0x14C Base +0x154 Base +0x158 Base +0x160 Base +0x164 Base + 0x170 Base +0x180 Base +0x184 Base + 0x1A4 Base +0x1A8 Base + 0x1AC Base + 0x1B0 Base + 0x1B4 Base + 0x1B8 Base + 0x1BC Base + 0x1C0 Base + 0x1C4 Base + 0x1C8 Base + 0x1CC Base + 0x1D0 Base + 0x1D4 Base + 0x1D8 Base + 0x1DC Base + 0x200 Base + 0x204 Base + 0x208 Base + 0x210 Base +0x214 Controller OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG OTG Host1 Host1 Host1 Host1 Host1 Use Device Interface Version (UOG_DCIVERSION) Device Controller Capability Parameters (UOG_DCCPARAMS) USB Command Register (UOG_USBCMD) USB Status Register (UOG_USBSTS) Interrupt Enable Register (UOG_USBINTR) USB Frame Index (UOG_FRINDEX) Host Controller Frame List Base Address (UOG_PERIODICLISTBASE) Host Controller Next Asynch. Address (UOG_ASYNCLISTADDR) Access R R RW RW RW RW RW (32-bit only) RW (32-bit only) Host Controller Embedded TT Asynch. Buffer Status (UOG_BURSTSIZE) RW (32-bit only) TX FIFO Fill Tuning (UOG_TXFILLTUNING) ULPI Viewport (ULPIVIEW) Config Flag (UOG_CFGFLAG) Port Status and Control (UOG_PORTSC1) On-The-Go Status and control (UOG_OTGSC USB Device Mode (UOG_USBMODE) Endpoint Setup Status (UOG_ENDPTSETUPSTAT) Endpoint Initialization (UOG_ENDPTPRIME) Endpoint De-Initialize (UOG_ENDPTFLUSH) Endpoint Status (UOG_ENDPTSTAT) Endpoint Complete (UOG_ENDPTCOMPLETE)( Endpoint Control0 (ENDPTCTRL0) Endpoint Control1 (ENDPTCTRL1) Endpoint Control2 (ENDPTCTRL2) Endpoint Control3 (ENDPTCTRL3) Endpoint Control4 (ENDPTCTRL4) Endpoint Control5 (ENDPTCTRL5) Endpoint Control6 (ENDPTCTRL6) Endpoint Control07(ENDPTCTRL7) Host 1 ID (UH1_ID) Hardware General (UH1_HWGENERAL) Host Hardware Parameters (UH1_HWHOST) TX Buffer Hardware Parameters (UH1_HWTXBUF) RX Buffer Hardware Parameters (UH1_HWRXBUF) RW (32-bit only) RW R RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW R R R R R MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-5 High-Speed USB On-The-Go (HS USB-OTG) Table 30-2. USB Module Memory Map (continued) Address Base +0x280 Base +0x284 Base +0x288 Base +0x28c Base +0x300 Base + 0x302 Base +0x304 Base +0x308 Base +0x340 Base +0x344 Base +0x348 Base + 0x34C Base +0x354 Base +0x358 Base +0x360 Base +0x364 Base +0x380 Base +0x384 Base +0x3A8 Base + 0x400 Base + 0x404 Base + 0x408 Base + 0x410 Base +0x414 Base +0x480 Base +0x484 Base +0x488 Base +0x48c Base +0x500 Base + 0x502 Base +0x504 Base +0x508 Base +0x540 Controller Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host1 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Use General Purpose Timer #0 Load(GPTIMER0LD) General Purpose Timer #0 Controller(GPTIMER0CTRL) General Purpose Timer #1 Load(GPTIMER0LD) General Purpose Timer #1 Controller(GPTIMER0CTRL) Capability Register Length (UH1_CAPLENGTH) Host Interface Version (UH1_HCIVERSION) Host Control Structural Parameters (UH1_HCSPARAMS) Control Capability Parameters (UH1_HCCPARAMS) USB Command Register (UH1_USBCMD) USB Status Register (UH1_USBSTS) Interrupt Enable Register (UH1_USBINTR) USB Frame Index (UH1_FRINDEX) Host Controller Frame List Base Address (UH1_PERIODICLISTBASE) Host Controller Next Asynch. Address (UH1_ASYNCLISTADDR) Access RW RW RW RW R R R R RW RW RW RW RW (32-bit only) RW (32-bit only) Host Controller Embedded TT Asynch. Buffer Status (UH1_BURSTSIZE) RW (32-bit only) TX FIFO Fill Tuning (UH1_TXFILLTUNING) Reserved Port Status and Control (UH1_PORTSC1) USB Device Mode (UH1_USBMODE) ID (UH2_ID) Hardware General (UH2_HWGENERAL) Host Hardware Parameters (UH2_HWHOST) TX Buffer Hardware Parameters (UH2_HWTXBUF) RX Buffer Hardware Parameters (UH2_HWRXBUF) General Purpose Timer #0 Load(GPTIMER0LD) General Purpose Timer #0 Controller(GPTIMER0CTRL) General Purpose Timer #1 Load(GPTIMER0LD) General Purpose Timer #1 Controller(GPTIMER0CTRL) Capability Register Length (UH2_CAPLENGTH) Host Interface Version (UH2_HCIVERSION) Host Control Structural Parameters (UH2_HCSPARAMS) Control Capability Parameters (UH2_HCCPARAMS) USB Command Register (UH2_USBCMD) RW (32-bit only) R RW RW R R R R R RW RW RW RW R R R R RW MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-6 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-2. USB Module Memory Map (continued) Address Base +0x544 Base +0x548 Base + 0x54C Base +0x554 Base +0x558 Base +0x560 Base +0x564 Base + 0x570 Base +0x580 Base +0x584 Base +0x5A8 Base + 0x600 Base + 0x604 Controller Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Host2 Use USB Status Register (UH2_USBSTS) Interrupt Enable Register (UH2_USBINTR) USB Frame Index (UH2_FRINDEX) Host Controller Frame List Base Address (UH2_PERIODICLISTBASE) Host Controller Next Asynch. Address (UH2_ASYNCLISTADDR) Access RW RW RW RW (32-bit only) RW (32-bit only) Host Controller Embedded TT Asynch. Buffer Status (UH2_BURSTSIZE) RW (32-bit only) TX FIFO Fill Tuning (UH2_TXFILLTUNING) ULPI Viewport (ULPIVIEW) Reserved Port Status and Control (UH2_PORTSC1) USB Device Mode (UH2_USBMODE) USB Control Register (USB_CTRL) USB OTG Mirror Register (USB_OTG_MIRROR) RW (32-bit only) RW R RW RW RW RW 30.5.1 Register Descriptions The following sections describe the registers used to control the USB module. 30.5.1.1 USBCONTROL—USB Control Register (USB_CTRL) The USB control register controls the integration specific features of the USB module. These features are not directly related to the USB functionality, but control special features, interfacing on the USB ports, as well as power control and wake-up functionality. Base + 0x600 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W Reset: OWIR — P OSIC P OUIE OWIE 0 0 OBPVAL 0 0 H2WI R OPM 0 — H2SIC P P H2UI H2WI E E 0 0 0 — 0 — H2P M 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset: H1WI R — P H1SIC P P 0 — H1WI E 0 H1BPVAL 0 0 H1P M 0 0 — 0 — H2DT H1DT 0 0 0 — 0 0 0 0 BPE 0 = Preset value taken from Preset input signals Figure 30-2. USB Control Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-7 High-Speed USB On-The-Go (HS USB-OTG) Table 30-3. USB Control Register Field Descriptions Field 31 OWIR Description OTG Wake-up Interrupt Request. This bit indicates that a wake-up interrupt request is received on the OTG port. This bit is cleared by disabling the wake-up interrupt. 0 No wake-up detected 1 Wake-up Interrupt Request received OTG Serial Interface Configuration. Controls the interface type of the OTG port when used with a serial transceiver. This bit field allows for configuring the serial interface for Single Ended or Differential operation combined with Bidirectional or Unidirectional operation. The reset value of OSIC depends on the state of the signals “__ADD__” and “__ADD__” during reset. 00 Differential/Unidirectional (6-wire) 01 Differential/Bidirectional (4-wire) 10 Single Ended/Unidirectional (6-wire) 11 Single Ended/Bidirectional (3-wire) OTG ULPI interrupt enable. Controls whether or not interrupts from the ULPI transceiver will trigger the wake-up logic. This bit is only meaningful when a ULPI transceiver is selected. 0 ULPI transceiver interrupts are ignored by the wakeup logic. 1 ULPI transceiver interrupts activate the wake-up logic OTG Wake-up Interrupt Enable. This bit enables or disables the OTG wake-up interrupt. Disabling the interrupt also clears the Interrupt request bit. Wake-up interrupt enable should be turned off after receiving a wake-up interrupt and turned on again prior to going in suspend mode 0 Interrupt Disabled 1 Interrupt Enabled OTG Bypass Value. This field contains the status of the RxDp and RxDm inputs to the OTG core when Bypass mode is enabled. Bit 26 controls RxDp, bit 25 controls RxDm. OTG Power Mask. The power mask bit controls whether or not the external Vbus Power and OverCurrent detection are active for the OTG port. 0 The USBPWR pin will assert with the OTG core’s Vbus power Enable and the assertion of the OC input will be reported to the OTG core. 1 The USBPWR and OC pins are not used by the OTG core. Host 2 Wake-up Interrupt Request. Indicates a pending Wake-up request on Host port 2. This bit is cleared by disabling the interrupt. The interrupt must be disabled for at least 2 clock cycles of the standby clock. 0 No Wake-up interrupt received 1 Wake-up interrupt received Host 2 Serial Interface Configuration. Controls the interface type of the Host 2 port when used with a serial transceiver. This bit field allows for configuring the serial interface for Single Ended or Differential operation combined with Bidirectional or Unidirectional operation. 00 Differential/Unidirectional (6-wire) 01 Differential/Bidirectional (4-wire) 10 Single Ended/Unidirectional (6-wire) 11 Single Ended/Bidirectional (3-wire) Host 2 ULPI interrupt enable. Controls whether or not interrupts from the ULPI transceiver will trigger the wake-up logic. This bit is only meaningful when a ULPI transceiver is selected. 0 ULPI transceiver interrupts are ignored by the wakeup logic. 1 ULPI transceiver interrupts activate the wake-up logic 30–29 OSIC 28 OUIE 27 OWIE 26–25 OBPVAL 24 OPM 23 H2WIR 22–21 H2SIC 20 H2UIE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-8 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-3. USB Control Register Field Descriptions (continued) Field 19 H2WIE Description Host 2 Wake-up Interrupt Enable. This bit enables or disables the Host 2 wake-up interrupt. Disabling the interrupt also clears the Interrupt request bit. Wake-up interrupt enable should be turned off after receiving a wake-up interrupt and turned on again prior to going in suspend mode. 0 Interrupt Disabled 1 Interrupt Enabled Reserved. These bits are reserved and should read 0. Host 2 Power Mask. The power mask bit controls whether or not the external Vbus Power and OverCurrent detection are active for the Host 2 port. 0 The USBPWR pin will assert with the Host 2 core’s Vbus power Enable and the assertion of the OC input will be reported to the Host 2 core. 1 The USBPWR and OC pins are not used by the Host 2 core. Host 1 Wake-up Interrupt Request. Indicates a pending Wake-up request on Host port 1. This bit is cleared by disabling the interrupt. The interrupt must be disabled for at least 2 clock cycles of the standby clock. 0 Wake-up interrupt received 1 No Wake-up interrupt received Host 1 Serial Interface Configuration. Controls the interface type of the Host 1 port when used with a serial transceiver. This bit field allows for configuring the serial interface for Single Ended or Differential operation combined with Bidirectional or Unidirectional operation. 00 Differential/Unidirectional (6-wire) 01 Differential/Bidirectional (4-wire) 10 Single Ended/Unidirectional (6-wire) 11 Single Ended/Bidirectional (3-wire) Reserved. This bit is reserved and should read 0. Host 1 Wake-up Interrupt Enable. This bit enables or disables the Host 1 wake-up interrupt. Disabling the interrupt also clears the Interrupt request bit. Wake-up interrupt enable should be turned off after receiving a wake-up interrupt and turned on again prior to going in suspend mode 0 Interrupt Disabled 1 Interrupt Enabled HOST 1 Bypass Value. This field contains the status of the RxDp and RxDm inputs to the HOST1 core when Bypass mode is enabled. Bit 10 controls RxDp, bit 9 controls RxDm. Host 1 Power Mask. The power mask bit controls whether or not the external Vbus Power and OverCurrent detection are active for the Host 1 port. 0 The USBPWR pin will assert with the Host 1core’s Vbus power Enable and the assertion of the OC input will be reported to the Host 1 core. 1 The USBPWR and OC pins are not used by the Host 1 core. Reserved. These bits are reserved and should read 0. Host 2 TLL Disable. This bit controls whether or not the Transceiver-less Link Logic is enabled for the serial interface of Host Port 2. 0 TLL is enabled 1 TLL is disabled Host 1 TLL disable. This bit controls the TLL logic for Host Port 1 0 TLL is enabled 1 TLL is disabled 18–17 16 H2PM 15 H1WIR 14–13 H1SIC 12 11 H1WIE 10–9 H1BPVAL 8 H1PM 7–6 5 H2DT 4 H1DT MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-9 High-Speed USB On-The-Go (HS USB-OTG) Table 30-3. USB Control Register Field Descriptions (continued) Field 3–1 0 BPE Description Reserved. These bits are reserved and should read 0. Bypass Enable. This bit enables/disables the USB Bypass function. 0 Bypass inactive—Normal mode operation. 1 Bypass active—USB signals from Host port 1 are routed to the OTG port. 30.5.1.2 OTGMIRROR — OTG port Mirror Register The OTG port is designed for operation with an external OTG transceiver. When a ULPI transceiver is in use, all OTG signaling is communicated over the ULPI data bus as described in the ULPI specification. However, when a serial transceiver is used, the interface for OTG signaling is not standardized. Most OTG transceivers use a serial interface like I2C or SPI to transfer the OTG signaling back to the CPU and/or USB core. In this case, the USB CORE has no direct connection the OTG signals in the transceiver. The OTGMIRROR register provides a soft interface between the OTG signals in the transceiver and the OTG signal inputs to the USB core. The USB driver software is responsible for reading the OTG status registers in the transceiver over the serial interface and set the bits accordingly in the OTGMIRROR register (see Figure 30-3), such that the USB controller knows the status of the transceiver. The USB driver should be designed such that the latency requirements as defined in the USB 2.0 OTG supplement specification are met. Base + 0x604 R W Reset: 7 0 — 6 0 — 5 0 — 4 SESEND 0 3 2 1 0 IDDIG 0 VBUSVAL BSESVLD ASESVLD 0 0 0 = Unimplemented or Reserved Figure 30-3. OTG Mirror Register (OTGMIRROR) SESEND—B device Session End This bit is set by the USB driver when the PHY reports a Session End condition. 1 = Session End (0.2V < Vbus < 0.8V) 0 = Session Active VBUSVLD—Vbus Valid The USB driver sets this bit when the transceiver reports Vbus Valid. 1 = Vbus is Valid (Vbus > 4.4V) 0 = Vbus Invalid (Vbus < 4.4V) BSESVLD—B Session Valid B session valid should be set when the transceiver reports B-session Valid. 1 = B Session is Valid (0.8V < Vbus < 4.0V) 0 = B Session is not valid (Vbus < 0.8V) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-10 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) ASESVLD—A session Valid This bit must be set when a valid ‘A-Session’ level is detected on Vbus. 1 = A Session is Valid (0.8V < Vbus < 2.0V) 0 = Session is not valid for A-device. IDIDG—OTG ID-pin Status This bit indicates to the USB core whether it should operate as A-device or as B-device 1 = ID pin is High—Operate as B-device 0 = ID pin is Low—Operate as A-device 30.5.1.3 USB Core Register For detailed registers description of OTG Controller, Host 1 Controller, and Host 2 Controller, refer to Section 30.5.1, “Register Descriptions.” The value of registers that depended on implementation can be found based on the core configuration parameter file (OTG Controller refer to Section 30.6.3, “USB OTG Controller,” Section 30.6.1, “USB HOST Controller 1,” and Section 30.6.2, “USB Host Controller 2.” 30.6 Functional Description This sections describes the functionality and the topology of the different building blocks of the USB module. 30.6.1 30.6.1.1 USB HOST Controller 1 Host Controller 1 to Host Port 1 Interface The Host 1 core USB signals do not connect directly to the HOST1 I/O pins. Instead, the signals pass through the Bypass Mux to allow for additional functionality on Host Port1. See section Section 30.6.6, “USB Bypass Mode” for details. In addition to Bypass Muxing, this mux also provides interface type conversion for Host core 1. This type conversion is independent of the mux state. Table 30-3 details the available type settings. Depending on the selected interface type, the USB port signals have the functionality as described in table Table 30-4. Table 30-4. Host Port 1 Pin Functions Single-Ended Mode Signal OEn TxDp TxDm RxDp Unidir OEn DAT SE0 RxDp DATO DATI Bidir OEn = 0 OEn = 1 Unidir OEn TxDp TxDm RxDp TxDp RxDp Differential Mode Bidir OEn = 0 OEn = 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-11 High-Speed USB On-The-Go (HS USB-OTG) Table 30-4. Host Port 1 Pin Functions (continued) Single-Ended Mode Signal RxDm RCV Unidir RxDm Rcv SE0O — Bidir SE0I — Unidir RxDm Rcv TxDm — Differential Mode Bidir RxDm Rcv NOTE If the RCV signal is not available on the external part (for example, when using a direct connection with TLL mode), the RCV input must be tied to the RxVp input. 30.6.2 USB Host Controller 2 Host controller 2 is configured for operation with a FS/LS serial transceiver or a parallel ULPI transceiver (HS/FS/LS). The selection between transceiver type is software programmable. The module defaults to serial mode. 30.6.2.1 Host Port 2 Signal Connections and Signal Muxing Table 30-5 details the I/O pad connections for the USB Host Port 2. The direction control is logic ‘1’ for output. Table 30-5. Host Port 2 Signal Connections I/O PAD USB2_ULPI_CLK USB2_ULPI_DIR USB2_ULPI_STP USB2_ULPI_NXT USB2_ULPI_DATA0 USB2_ULPI_DATA1 USB2_ULPI_DATA2 USB2_ULPI_DATA3 USB2_ULPI_DATA4 USB2_ULPI_DATA5 USB2_ULPI_DATA6 USB2_ULPI_DATA7 Type I/O IN OUT IN I/O I/O I/O I/O I/O I/O I/O I/O ipp_ind_uh2_nxt ipp_ind_uh2_data0 ipp_ind_uh2_data1 ipp_ind_uh2_data2 ipp_ind_uh2_data3 ipp_ind_uh2_data4 ipp_ind_uh2_data5 ipp_ind_uh2_data6 ipp_ind_uh2_data7 ipp_do_uh2_data0 ipp_do_uh2_data1 ipp_do_uh2_data2 ipp_do_uh2_data3 ipp_do_uh2_data4 ipp_do_uh2_data5 ipp_do_uh2_data6 ipp_do_uh2_data7 ipp_obe_uh2_data0 ipp_obe_uh2_data1 ipp_obe_uh2_data2 ipp_obe_uh2_data3 ipp_obe_uh2_data4 ipp_obe_uh2_data5 ipp_obe_uh2_data6 ipp_obe_uh2_data7 Input ipp_ind_uh2_clk ipp_ind_uh2_dir ipp_do_uh2_stp Output Direction control Host port 2 can support either a ULPI transceiver or a Serial Transceiver. Depending on the selected type, signaling for one or the other is available at the top level. Table 30-6 gives the relation between the top level signal and the USB core signal in both modes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-12 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-6. ULPI/ Serial Muxing USB TOP Input signals From I/O Mux ipp_ind_uh2_data 0 ipp_ind_uh2_data 1 ipp_ind_uh2_data 2 ipp_ind_uh2_data 3 ipp_ind_uh2_rxvp_txdp_dat Serial Mode ipp_ind_uh2_oe_n ULPI Mode To I/O Mux USB TOP Output Signals Serial Mode ipp_do_uh2_oe_n ipp_do_uh2_txdp_dat ipp_do_uh2_txdm_se0 ULPI Mode uuh2_data_out [0] uuh2_data_out [1] uuh2_data_out [2] uuh2_data_in ipp_do_uh2_dat [0] a0 uuh2_data_in ipp_do_uh2_dat [1] a1 uuh2_data_in ipp_do_uh2_dat [2] a2 uuh2_data_in ipp_do_uh2_dat ipp_do_uh2_rxvp_txdp_d uuh2_data_out [3] a3 at [3] ipp_ind_uh2_data ipp_ind_uh2_rxvm_txdm_se0 uuh2_data_in ipp_do_uh2_dat ipp_do_uh2_rxvm_txdm_ uuh2_data_out 4 [4] a4 se0 [4] ipp_ind_uh2_data 5 ipp_ind_uh2_data 6 ipp_ind_uh2_data 7 ipp_ind_uh2_xcvr_ser_rcv uuh2_data_in ipp_do_uh2_dat ipp_do_uh2_xcvr_ser_rcv uuh2_data_out [5] a5 [5] uuh2_data_in ipp_do_uh2_dat [6] a6 uuh2_data_in ipp_do_uh2_dat [7] a7 USB Port 2 Direction Control ipp_obe_uh2_d ata0 ipp_obe_uh2_d ata1 ipp_obe_uh2_d ata2 ipp_obe_uh2_d ata3 ipp_obe_uh2_d ata4 ipp_obe_uh2_d ata5 ipp_obe_uh2_d ata6 ipp_obe_uh2_d ata7 ipp_obe_uh2_oe_n 1'b0 1'b0 uuh2_data_out _enable uuh2_data_out _enable uuh2_data_out _enable ipp_do_uh2_speed ipp_do_uh2_suspend uuh2_data_out [6] uuh2_data_out [7] ipp_obe_uh2_rxvp_txdp_ uuh2_data_out dat _enable ipp_obe_uh2_rxvm_txdm uuh2_data_out _se0 _enable ipp_obe_uh2_xcvr_ser_r cv 1'b0 1'b0 uuh2_data_out _enable uuh2_data_out _enable uuh2_data_out _enable 30.6.3 USB OTG Controller The OTG controller offers HS/FS/LS capabilities in Host mode and HS/FS in device mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-13 High-Speed USB On-The-Go (HS USB-OTG) 30.6.3.1 Host Mode The controller supports direct connection of a FS/LS device (without external hub). Although there is no separate Transaction Translator block in the system. The transaction translator function normally associated with a USB 2.0 high speed hub has been implemented within the DMA and Protocol engine blocks to support connection to full and low speed devices. 30.6.3.2 • • • • Peripheral (Device) Mode Up to 8 bidirectional endpoints High/full speed operation Supports HNP, SRP. Remote wakeup capable 30.6.3.3 Special Considerations The OTG port functions as gateway between the Host 1 Port and the OTG transceiver when in Bypass mode. 30.6.3.4 OTG Port Signal Connections and Signal Muxing Table 30-7. Signal Connections I/O PAD USB_ULPI_CLK USB_ULPI_DIR USB_ULPI_STP USB_ULPI_NXT USB_ULPI_DATA0 USB_ULPI_DATA1 USB_ULPI_DATA2 USB_ULPI_DATA3 USB_ULPI_DATA4 USB_ULPI_DATA5 USB_ULPI_DATA6 USB_ULPI_DATA7 Type I/O IN OUT IN I/O I/O I/O I/O I/O I/O I/O I/O ipp_ind_otg_nxt ipp_ind_otg_data0 ipp_ind_otg_data1 ipp_ind_otg_data2 ipp_ind_otg_data3 ipp_ind_otg_data4 ipp_ind_otg_data5 ipp_ind_otg_data6 ipp_ind_otg_data7 ipp_do_otg_data0 ipp_do_otg_data1 ipp_do_otg_data2 ipp_do_otg_data3 ipp_do_otg_data4 ipp_do_otg_data5 ipp_do_otg_data6 ipp_do_otg_data7 ipp_obe_otg_data0 ipp_obe_otg_data1 ipp_obe_otg_data2 ipp_obe_otg_data3 ipp_obe_otg_data4 ipp_obe_otg_data5 ipp_obe_otg_data6 ipp_obe_otg_data7 Input ipp_ind_otg_clk ipp_ind_otg_dir ipp_do_otg_stp Output Direction Control Table 30-7 describes the Signal connections from the USB core to the OTG port OUTPUT PADS. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-14 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-8. OTG ULPI/Serial Muxing USB TOP Input Signals From I/O Mux ipp_ind_otg_data 0 ipp_ind_otg_data 1 ipp_ind_otg_data 2 ipp_ind_otg_data 3 ipp_ind_otg_data 4 ipp_ind_otg_data 5 ipp_ind_otg_data 6 ipp_ind_otg_data 7 ipp_ind_otg_xcvr_ser_vp Serial Mode ULPI Mode uotg_data_in [0] uotg_data_in [1] uotg_data_in [2] uotg_data_in [3] To I/O Mux ipp_do_otg_data0 ipp_do_otg_data1 ipp_do_otg_data2 ipp_do_otg_data3 ipp_do_otg_data4 ipp_do_otg_data5 ipp_do_otg_data6 ipp_do_otg_data7 ipp_do_otg_speed ipp_do_otg_suspend USB TOP Output Signals Serial Mode ipp_do_otg_oe_n ipp_do_otg_txdp_dat ULPI Mode uotg_data_out [0] uotg_data_out [1] ipp_do_otg_txdm_se0 uotg_data_out [2] ipp_do_otg_xcvr_ser_ uotg_data_out vp [3] ipp_do_otg_xcvr_ser_ uotg_data_out vm [4] uotg_data_out [5] uotg_data_out [6] uotg_data_out [7] ipp_ind_otg_xcvr_ser_vm uotg_data_in [4] ipp_ind_otg_xcvr_ser_rcv uotg_data_in [5] uotg_data_in [6] uotg_data_in [7] OTG Port Direction Control ipp_obe_otg_data0 ipp_obe_otg_data1 ipp_obe_otg_data2 ipp_obe_otg_data3 ipp_obe_otg_data4 ipp_obe_otg_data5 ipp_obe_otg_data6 ipp_obe_otg_data7 1’b1 1'b0 1'b0 uotg_data_out _enable uotg_data_out _enable uotg_data_out _enable ipp_obe_otg_xcvr_ser uotg_data_out _vp _enable ipp_obe_otg_xcvr_ser uotg_data_out _vm _enable 1'b0 1'b0 1'b0 uotg_data_out _enable uotg_data_out _enable uotg_data_out _enable 30.6.4 USB Power Control Module The USB module supports suspend and wakeup functionality, but the circuit is considered application specific and therefore not part of the IP. An external circuit has been designed to place external transceivers in suspend mode, and wake them up either on a local request (CPU initiated) or on remote request by MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-15 High-Speed USB On-The-Go (HS USB-OTG) detecting activity on the USB line. The wake-up logic can optionally wake the CPU when it is in sleep mode at the time of the request. The power control mechanism is described in the VUSB-HS-SPH and VUSB-HS-OTG reference manuals. For details on the power control module, refer to the Power Module creation guide. 30.6.4.1 Entering Suspend Mode Suspend mode is always entered under control of driver software by setting the appropriate bit INT PORTSC register. Once the controller is suspended, the clocks to the USB block can be stopped. 30.6.4.2 Wake-up Events The power control module monitors the USB bus when the USB core is in the suspend state. Depending on whether the core is on Host or Device mode, a number of wakeup conditions are detected. Upon detection of a wakeup condition, an interrupt (asynchronous) is generated on the CPU complex. This interrupt will also re-activate the clocks if these were stopped during the suspend. 30.6.4.2.1 Host Mode Events The Host controller wakes-up on the following events: Remote Wakeup Request A peripheral can request the host to re-activate the bus by driving wake-up signaling on the Dm/Dp lines. The power control module will detect a J-K transition on the Dm/Dp lines and signal the wakeup request to the core. Wake on Over-Current If wake on overcurrent is enabled in the PORTSC registers, the power control module will signal a wakeup condition to the USB core. Wake on Disconnect The Power Control module detects disconnect events by monitoring the Dp/Dm lines. When a disconnect event is detected (Dm = Dp = 0) and the Wake on Disconnect is enabled in the PORTSC register, the core will be notified. Wake on Connect Similar to the Wake on Disconnect, the power control module detects a connect event (Dm or Dp High) and signals this to the USB core by setting the pwrctl_wakeup signal if enabled in the PORTSC register. 30.6.4.2.2 Device mode events When the OTG controller is configured for peripheral operation, the power control module will detected following events: MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-16 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Detection of bus activity Any non-idle condition on the USB bus will activate the wakeup output of the power control module to notify the USB core of the wakeup event. 30.6.5 TLL Mode The Transceiver less Link Logic circuit allows two micro-controllers to use USB for an Inter-processor Communication Link (ICL) without using conventional USB transceivers. The TLL muxes support serial type interfacing only and are available on Host Port 1 and Host Port 2. 30.6.5.1 TLL Functional Description The TLL logic is a logic representation of 2 serial transceivers connected by a USB cable. The USB bus DM/DP states are modeled internally in the TLL function, such that the USB I/O port acts as if it were a transceiver. In a regular USB implementation with serial PHY’s, the speed selection on the USB bus is done by means of a pull-up resistor on the Peripheral side either on the DM (low speed) or the DP (full Speed) line. This Pull-up pulls one of the USB lines high when the bus is idle. This option cannot be modeled in logic as the serial USB interface does not provide for such a signal. The TLL mux is therefore configured for Full Speed only operation. The IDLE condition of the bus is determined by the OEn signals and suspend signals on both sides of the mux. When both OEn signals are high, or when one or both suspend signals are high, the idle condition is assumed. The TLL block then drives TxDp high and TxDm low on both sides of the block. SPEED TxEnb RxDm/SE0I External USB Peripheral RxDm/DATI TxDm/SE0 TxDp/DAT RCV Suspend I/O Port Interface DM/DP Bus State Model SPEED TxENb USB Core Interface Model DAT SE0 RxDm RxDp RCV Suspend TLL MUX USB Host Core Figure 30-4. TLL Mux Functional Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-17 High-Speed USB On-The-Go (HS USB-OTG) 30.6.5.2 Host Port 1 On Host Port1, the TLL function is integrated with the Bypass function (see Section 30.6.6, “USB Bypass Mode”) and the Transceiver Type conversion logic. TLL mode is the default mode for this port. It can be disabled by setting bit 4 in the USBCONTROL register. Table 30-9. Port 1 TLL and PHY Mode Pin Connections TLL mode Pin SPEED TxEnb RxVm RxVp TxDm TxDp RCV Suspend I/O I I I I O O O I External Device Pin speed TxEnb TxDm TxDp RxDm RxDp RCV suspend I/O O O I I O O I O PHY Mode External PHY Pin speed TxEnb RxVm RxVp TxDm TxDp RCV SuspendM 30.6.5.3 Host Port 2 The TLL module on Host Port 2 contains the TLL logic and the Serial Transceiver Type conversion logic. The Interface type conversion is available in both TLL and Non TLL modes. TLL operation is the default mode. It can be turned off for operation with an external transceiver by setting bit 5 in the USBCONTROL register. The USBCONTROL register. Table 30-10. Port 2 TLL and PHY Mode Pin Connections TLL mode Pin SPEED TxEnb RxVm RxVp/ TxDm TxDp RCV Suspend I/O I I I I O O O I External Device Pin speed TxEnb TxDm TxDp RxDm RxDp RCV suspend I/O O O I O O O I O PHY Mode External PHY Pin speed TxEnb RxVm RxVp TxDm TxDp RCV SuspendM MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-18 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.6.6 USB Bypass Mode The USB Bypass mode is a special mode that allows for the transceiver on the OTG port to be used as transceiver for a USB peripheral device connected to host port 1. This mode is only available for full/low speed serial transceivers. The Bypass module is combination of: • the bypass function (Host Port1 - OTG port pass through) • TLL function for Host Port 1 • Serial Transceiver Interface Conversion 30.6.6.1 Bypass Mode operation Bypass mode is enabled by writing a ‘1’ to bit 0 (BPE) in Figure 30-2. Figure 30-5 shows the USB bypass mux functional diagram. Host 1 OTG On Board USB peripheral USB Bypass Mux Tortola Normal Mode Bypass Mode Transceiver Figure 30-5. USB Bypass Mux Functional Diagram In bypass mode, the serial interface signals from Host Port 1 are routed to the Serial Interface pins of the OTG port such that an external USB Peripheral device can use the OTG transceiver to connect to an external USB Host. As this function only works with USB peripherals directly connected to Host Port 1, the port is automatically set for TLL mode. Transceiver Interface Type conversion is available in Bypass mode such that the interface type of the OTG transceiver can be different from the Host 1 interface type. The USB HOST1 core is disconnected from the port and the inputs RxDp, RCV and RxDm from the core are driven by bits 9 and 10 (H1BPVAL) in the Figure 30-2.The OTG core is also disconnected from its port and inputs RxDp, RCV and RxDm are driven by bits 25 and 26 (OBPVAL) from the Figure 30-2. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-19 High-Speed USB On-The-Go (HS USB-OTG) 30.6.6.2 OTG and Host 1 pin functions Table 30-11 list the pin functions of the Host 1 port when Bypass mode is enabled and the associated OTG pin. The Pin functions of the OTG port are not affected by Bypass mode. Table 30-11. HOST1 Bypass Mode Pin Functions Unidirectional Pin RxDm RxDp RCV TxDm TxDp OEb FS Suspend I/O I I O O O I I I SingleEnded RxDm RxDp RCV SE0 DAT OEn Speed Suspend I/O I I O O O I I I Differential RxDm RxDp RCV TxDM TxDP OEb FS Suspend I I I I/O I/O I/O Bidirectional Single- Ended SEOI/SE0O DATI/DATO — — — OEn Speed Suspend I I I I/O I/O I/O O Differential RxDm/TxDm RxDp/TxDP RCV — — OEn Speed Suspend I/O O O I I OTG PORT Pin TxDm TxDP RCV RxDM RxDp OEb Speed Suspend 30.6.7 ULPI/Serial MUX Both Host2 and OTG cores can be configured by software for ULPI or Serial PHY operation. The ULPI/Serial mux selects between ULPI interface signals and Serial PHY interface signals. The mux is controlled by the PHY Select signals from the USB core and is switched when the software selects the interface mode. The default configuration for the mux is Serial mode. Switching to ULPI mode is done by writing the Parallel Transceiver Select (PTS) bits in the PORTSC register with 0b10. 30.6.8 30.6.8.1 Interrupts USB Core Interrupts Each USB core uses one dedicated vector in the Interrupt Table. The vector numbers associated with each of the cores can be found in the Interrupt section. With the exception of the wake-up interrupts, all of the interrupt sources are controlled in the USB Cores. Refer to the USB Core documentation for details. 30.6.8.2 USB Wake-Up Interrupts Each USB Core has an associated wake-up interrupt. The wake-up interrupts are generated outside the USB cores’ but use the same vector as the corresponding Cores’ interrupt. These interrupt are generated by the Power Control Modules which run on the 32KHz standby clock.The wake-up interrupt is designed to work even when the USB and CPU clocks are disabled, such that a wake-up condition on the USB bus MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-20 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) can re-activate the CPU clocks. Therefore, this interrupt request propagates through combinatorial logic to the CPU’s interrupt module. Because the wake-up interrupt is generated and cleared on a 32 KHz clock, this interrupt request will respond very slowly to clear actions. For this reason, the software must disable the wake-up interrupt to clear the request flag. Disabling the interrupt will mask the request instantaneously as this is clocked by the CPU clock. The software should than wait for at least 3 32 KHz clock cycles before re-enabling this interrupt to allow sufficient time for the request flag to clear. As this interrupt is only used during low-power modes of the USB, it is sufficient to enable the wake-up interrupt just prior to enter USB suspend mode. 30.7 Initialization/Application Information This section described the detailed application knowledge for Host1, Host2 and OTG ports. It can be generally divided in two parts, one is for Host and the other is for Device. Host part is applied to three ports, Device part is only applied to OTG port. In following register description, Device related content is just for OTG, and Host related content is for all three ports. 30.7.1 Software Model The Device API provides a framework of routines to control the USB-HS OTG High-Speed USB On-The-Go peripheral in USB device applications. It includes an application to respond to the device framework commands issued by a USB host. The USB-HS OTG High-Speed USB On-The-Go Device API is designed to significantly simplify the software tasks required to develop a USB device application. The API presents a high-level data transfer interface to the user’s application code. All the register, interrupt and DMA interactions with the USB-HS OTG High-Speed USB On-The-Go core are managed by the API. The API also includes routines that handle all the USB device framework commands which are required for all USB devices. The Host Stack provides a layered software architecture to control all aspects of a USB bus system. The Host Controller Device (HCD) interface controls the functions of an embedded EHCI host controller. The USB driver layer provides all the USB driver functions to enumerate, manage and schedule a USB bus system, while the upper layers of the stack support standard USB device class interfaces to the device drives running on your embedded system. For details on the USB-HS OTG High-Speed USB On-The-Go Software Stack refer the documentation provided with the software products. • ANSI-C OTG software Stack provides Host and Device application support. USB software included with the USB-HS OTG High-Speed USB On-The-Go core is tested with the hardware. • OTG Application Program Interface (API) handles OTG protocols. Connect and disconnect events are handled as well as the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) state machines. The OTG code calls the Host or Device API functions based on the connection state of the OTG state machines. • Host API to speed up Host software development. Simple API calls allow direct interaction with USB pipes. Additional layers support bus enumeration, bus management and a growing set of supported USB classes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-21 High-Speed USB On-The-Go (HS USB-OTG) • Device API to speed up peripheral development. USB peripheral characteristics such as endpoints, configurations, interfaces, and alternate settings are controlled by supplied ANSI-C firmware. Device Frame work command set reduces software development time. Simple API interface allows quick coding of USB device applications. 30.7.1.1 Device Data Structure The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller will perform the data transfers. Up to 32 elements Endpoint Transfer Descriptor Transfer Buffer Pointer Transfer Buffer Transfer Buffer Endpoint QH 1 Endpoint QH 0 Endpoint QH 0 – Out – In – Out Transfer Buffer Pointer Transfer Buffer Pointer Transfer Buffer Transfer Buffer Pointer Transfer Buffer Endpoint Queue Heads ENDPOINTLISTADDR Figure 30-6. End Point Queue Head Organization The USB-HS OTG High-Speed USB On-The-Go Device API incorporates and abstracts for the application developer all of the information contained in the device operational model. 30.7.1.2 Host Data Structure The host data structures are used to communicate control, status, and data between software and the Host Controller. The Periodic Frame List is an array of pointers for the periodic schedule. A sliding window on the Periodic Frame List is used. The Asynchronous Transfer List is where all the control and bulk transfers are managed. The USB-HS OTG High-Speed USB On-The-Go Host API incorporates and abstracts for the application developer all of the information contained in the host operational model. 30.7.2 Register Interface Slave accesses from the controlling processor enables access to the configuration, control, and status registers. One function of the system address map is the registers base address, which must begin on a DWord (32-bit) boundary. Register offset definitions are listed in the table below. Configuration, control and status registers are divided into three categories, identification, capability, and operational registers. • Identification registers are used to declare the slave interface presence along with the complete set of the hardware configuration parameters. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-22 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • Static, read only capability registers define the software limits, restrictions, and capabilities of the host/device controller. Operational registers are comprised of dynamic control or status registers that may be read only, read/write, or read/write to clear. The following sections define the use of these registers. EHCI registers are listed alongside device registers to show the complementary nature of host and device control. Note: Host mode EHCI compatibility begins at offset 0x100. If it is necessary to begin the EHCI register set at offset 0x000, the identification registers are disabled from the address map by connecting the upper most address bit of the slave interface to a logic level ‘1’ and adjusting the offsets below accordingly. Table 30-12. Interface Register Sets Offset Register Set Explanation 000h to 0fch Identification Registers Identification registers are used to declare the slave interface presence and include a table of the hardware configuration parameters. 100h to 124h Capability Registers Capability registers specify the limits, restrictions, and capabilities of a host/device controller implementation. These values are used as parameters to the host/device controller driver. Operational registers are used by the system software to control and monitor the operational state of the host/device controller. 140h to 1FCh Operational Registers 30.7.2.1 Configuration, Control and Status Register Set Table 30-13. Configuration, Control, and Status Register Set Offset Size (bytes) 4 4 ID HWGENERAL Mnemonic Register Name Identification Register General Hardware Parameters Host Hardware Parameters Device Hardware ÷ Parameters TX Buffer Hardware Parameters ÷ DEV ÷ ÷ OTG ÷ ÷ SPH ÷ ÷ MPH ÷ ÷ 000h 004h 008h 00Ch 010h 4 4 4 HWHOST HWDEVICE HWTXBUF ÷ ÷ ÷ ÷ ÷ ÷ ÷ MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-23 High-Speed USB On-The-Go (HS USB-OTG) Table 30-13. Configuration, Control, and Status Register Set (continued) Offset 014h Size (bytes) 4 Mnemonic HWRXBUF Register Name RX Buffer Hardware Parameters TT-TX Buffer Hardware Parameters TT-RX Buffer Hardware Parameters N/A General Purpose Timer #0 Load Register General Purpose Timer #0 Control Register General Purpose Timer #1 Load Register General Purpose Timer #1 Control Register Capability Register Length N/A Host Interface Version Number Host Ctrl. Structural Parameters Host Ctrl. Capability Parameters N/A Dev. Interface Version Number N/A Device Ctrl. Capability Parameters N/A ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ DEV ÷ OTG ÷ SPH ÷ MPH ÷ 018h 4 HWTTTXBUF ÷ 01Ch 4 HWTTRXBUF ÷ 020h-0FCh 080h 232 4 Reserved GPTIMER0LD 084h 4 GPTIMER0CTRL 088h 4 GPTIMER1LD 08ch 4 GPTIMER1CTRL 100h 101h 102h 104h 1 1 2 4 CAPLENGTH Reserved HCIVERSION HCSPARAMS 108h 4 HCCPARAMS ÷ ÷ ÷ 10Ch–11Fh 120h 122h 124h 20 2 2 4 Reserved DCIVERSION Reserved DCCPARAMS 128h–13Ch 24 Reserved MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-24 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-13. Configuration, Control, and Status Register Set (continued) Offset 140h 144h 148h 14Ch 150h 154h Size (bytes) 4 4 4 4 4 4 Mnemonic USBCMD USBSTS USBINTR FRINDEX Reserved PERIODICLISTBASE Device Addr 158h 4 ASYNCLISTADDR Register Name USB Command USB Status USB Interrupt Enable DEV ÷ ÷ ÷ OTG ÷ ÷ ÷ ÷ SPH ÷ ÷ ÷ ÷ MPH ÷ ÷ ÷ ÷ USB Frame Index ÷ 4G Segment Selector Frame List Base Address USB Device Address Next Asynchronous List Address Address at Endpoint list in memory Asynchronous Buffer Status For Embedded TT. Programmable Burst Size Host Transmit Pre-Buffer Packet Tuning Host TT Transmit Pre-Buffer Packet Tuning Reserved Reserved Configured Flag Register Port Status/Control 1 Port Status/Control 2 Port Status/Control x Port Status/Control 8 ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ Endpointlist Addr ÷ 15Ch 4 ASYNCTTSTS ÷ 160h 164h 4 4 BURSTSIZE TXFILLTUNING ÷ ÷ ÷ ÷ ÷ ÷ 168h 4 TXTTFILLTUNING ÷ 16Ch 170-17Ch 180h 184h 188h … 1A0h 4 16 4 4 4 4 4 N/A N/A CONFIGFLAG PORTSC1 PORTSC2 PORTSCx PORTSC8 ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-25 High-Speed USB On-The-Go (HS USB-OTG) Table 30-13. Configuration, Control, and Status Register Set (continued) Offset 1A4h Size (bytes) 4 Mnemonic OTGSC Register Name On-The-Go (OTG) Status and Control USB Device Mode Endpoint Setup Status Endpoint Initialization Endpoint De-Initialize Endpoint Status Endpoint Complete Endpoint Control 0 Endpoint Control 1 Endpoint Control x Endpoint Control 15 ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ DEV OTG ÷ SPH MPH 1A8h 1ACh 1B0h 1B4h 1B8h 1BCh 1C0h 1C4h … 1FCh 4 4 4 4 4 4 4 4 4 4 USBMODE ENPDTSETUPSTAT ENDPTPRIME ENDPTFLUSH ENDPTSTATUS ENDPTCOMPLETE ENDPTCTRL0 ENDPTCTRL1 ENDPTCTRLx ENDPTCTRL15 ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ NOTE Italic Text indicates a deviation from EHCI for Device MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-26 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8 Summary of Register Layouts Table 30-14. HS-USB Register Summary 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 000h ID 004h HWGENERAL 008h HWHOST 00Ch HWDEVICE 010h HWTXBUF 014h HWRXBUF 020h Reserved … Reserved 0FCh Reserved 100h CAPLENGTH 101h Reserved 102h HCIVERSION 104h HCSPARAMS 108h HCCPARAMS 10Ch Reserved … Reserved 11Fh Reserved 120h DCIVERSION 122h Reserved reserved REVISION NID ID reserved S M PHYM PHY W B W T CLKC R T TTPER TTASY reserved NPORT H C reserved DEVP D C TXLC reserved TXCHANADD TXADD TXBURST reserved RXADD RXBURST reserved reserved reserved CAPLENGTH reserved HCIVERSION reserved N_TT N_PTT reserved PI N_CC N_PCC reserved P P C N_PORTS reserved EEC{[7:0] IST[7:4] R R P F L A D C reserved reserved reserved DCIVERSION reserved MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-27 High-Speed USB On-The-Go (HS USB-OTG) Table 30-14. HS-USB Register Summary (continued) Name 124h DCCPARAMS 128h Reserved … Reserved 13Ch Reserved 140h USBCMD 144h USBSTS 148h USBINTR 14Ch FRINDEX 150h Reserved 154h PERIODICLISTBA SE Device Addr 158h ASYNCLISTADDR Endpointlist Addr 15Ch ASYNCTTSTS 160h BURSTSIZE 164h TXFILLTUNING 168h TXTTFILLTUNING 16Ch Reserved 170 ULPI Viewport reserved USBADR[31:25] reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 H C 7 D C 6 5 4 3 2 1 0 reserved R R DEN reserved reserved reserved reserved ITC FS 2 R SU TW AT D T W AS PE R A S P 1 A S P 0 S LI S L E L R I A A U R I U R E A S E A A I A A E P S E S E I S E E F S 1 F R I F R E F S 0 P C I P C E R S T U E I U E E R S reserved AS PS R CL H C H reserved S R I S R E U I reserved U E FRINDEX[13:0] reserved PERBASE[31:12] reserved reserved ASYBASE[31:5] reserved EPBASE[31:11] reserved T T A C T T A S reserved reserved TXPBURST RXPBURST TXFIFOTHRES R TXSCHHEALTH TXSCHOH reserved TXTTSCHHEALTH R TXTTSCHOH reserved ULPI Viewport [optional] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-28 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-14. HS-USB Register Summary (continued) Name 174 Reserved … Reserved 17Ch Reserved 180h CONFIGFLAG 184h PORTSC1 188h PORTSC2 … PORTSCx 1A0h PORTSC8 1A4h OTGSC 1A8h USBMODE 1ACh ENPDTSETUPST AT 1B0h ENDPTPRIME 1B4h ENDPTFLUSH 1B8h ENDPTSTATUS 1BCh ENDPTCOMPLET E 1C0h ENDPTCTRL0 1C4h ENDPTCTRL1 reserved ST S PT W PF SC PH C D W K O C W K O C W K O C W K O C DP IS W KD S W KC N 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved reserved set to zero 1 PTS PSPD R PTC PIC P O PP LS H S P P R S U S P S U S P S U S P S U S P F P R O C C O C A P E C P E C S C C C S PTS ST S PT W PSPD R PF SC PH C D W KD S W KC N PTC PIC P O PP LS H S P P R F P R O C C O C A P E C P E C S C C C S PTS ST S PT W PSPD R PF SC PH C D W KD S W KC N PTC PIC P O PP LS H S P P R F P R O C C O C A P E C P E C S C C C S PTS ST S PT W PSPD R PF SC PH C D W KD S 1 ms S W KC N BS EI S BS VI S PTC PIC P O PP LS H S P A V V P R F P R O C C O C A P E C P E C S C C C S R DP IE 1 ms E BS EI E BS VI E AS VI E AV VI E ID IE R AS VI S AV VI S ID IS R DP S 1 ms T BS E BS V AS V I D reserved D P O T S L O M R V C V D reserved SDI S E S CM reserved ENDPTSETUPSTAT PETB[15:0] PERB[15:0] FETB[15:0] FERB[15:0] ETBR[15:0] ERBR[15:0] ETCE[15:0] ERCE[15:0] TX E reserved TXT R TX S reserved R X E R X E reserved RXT R R X S R X S reserved TX E TX R TX I R TXT TX D TX S reserved R X R R X I R RXT R X D MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-29 High-Speed USB On-The-Go (HS USB-OTG) Table 30-14. HS-USB Register Summary (continued) Name … ENDPTCTRLx 1FCh ENDPTCTRL15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TX E TX R TX I TX D TX S 8 7 R X E R X E 6 R X R R X R 5 R X I R X I 4 3 2 1 R X D R X D 0 R X S R X S reserved R TXT reserved R RXT reserved TX E TX R TX I R TXT TX D TX S reserved R RXT 30.8.1 Identification Registers Identification registers are used to declare the slave interface presence and include a table of the hardware configuration parameters. 30.8.1.1 ID Address:Base + 000h Default Value:Implementation Dependent Attribute:Read Only Size:32 bits The Identification register (ID) provides a simple way to determine if the USB-HS OTG High-Speed USB On-The-Go USB 2.0 core is provided in the system. The ID register identifies the USB-HS OTG High-Speed USB On-The-Go USB 2.0 core and its revision. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved REVISION 1 1 NID 00 ID Figure 30-7. ID - Identification Register The register fields are described in the following table. Field ID[5:0] Description Configuration number. This number is set to 0x05 and indicates that the peripheral is the USB-HS OTG High-Speed USB On-The-Go USB 2.0 core. Ones complement version of ID[5:0]. Revision number of the core These bits are reserved and should be set to zero NID[5:0] REVISION[7:0] Reserved 30.8.1.2 HWGENERAL Address:Base + 004h MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-30 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Default Value:Implementation Dependent Attribute:Read Only Size:32 bits General hardware parameters as defined in System Level Issues and Core Configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 4 3 21 0 reserved S PHY BW PHYM M W T CL R KC T Figure 30-8. HWGENERAL—General Hardware Parameters The register fields are described in the following table. Table 30-15. HWGENERAL Field reserved SM PHYM PHYW BWT CLKC RT Description Reserved. These bits are reserved and should be set to zero. VUSB_HS_PHY_SERIAL VUSB_HS_PHY_TYPE VUSB_HS_PHY16_8 Reserved for internal testing. VUSB_HS_CLOCK_CONFIGURATION VUSB_HS_RESET_TYPE 30.8.1.2.1 HWHOST Address:Base + 008h Default Value:Implementation Dependent Attribute:Read Only Size:32 bits Host hardware parameters as defined in System Level Issues and Core Configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTPER TTASY reserved NPOR H T C Figure 30-9. HWHOST—Host Hardware Parameters The register fields are described in the following table. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-31 High-Speed USB On-The-Go (HS USB-OTG) Table 30-16. HWHOST Field Descriptions Field TTPER TTASY reserved NPORT HC Description VUSB_HS_TT_PERIODIC_CONTEXTS VUSB_HS_TT_ASYNC_CONTEXTS Reserved. These bits are reserved and should be set to zero. VUSB_HS_NUM_PORT-1 VUSB_HS_HOST 30.8.1.2.2 HWDEVICE Address:Base + 00Ch Default Value:Implementation Dependent Attribute:Read Only Size:32 bits Device hardware parameters as defined in System Level Issues and Core Configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DEVEP D C Figure 30-10. HWDEVICE—Device Hardware Parameters The register fields are described in the following table. Field Reserved DEVEP DC Description Reserved. These bits are reserved and should be set to zero. VUSB_HS_DEV_EP device capable; [VUSB_HS_DEV /= 0] 30.8.1.2.3 HWTXBUF Address:Base + 010h Default Value:Implementation Dependent Attribute:Read Only Size:32 bits TX buffer hardware parameters as defined in System Level Issues and Core Configuration. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-32 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 876543210 TXLCR reserved TXCHANADD TXADD TCBURST Figure 30-11. HWTXBUF—TX Buffer Hardware Parameters The register fields are described in the following table. Field TXLC reserved TXCHANADD TXADD TCBURST Description VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS Reserved. These bits are reserved and should be set to zero. VUSB_HS_TX_CHAN_ADD VUSB_HS_TX_ADD VUSB_HS_TX_BURST 30.8.1.2.4 HWRXBUF Address:Base + 014h Default Value:Implementation Dependent Attribute:Read Only Size:32 bits RX buffer hardware parameters as defined in System Level Issues and Core Configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 reserved RXADD RXBURST Figure 30-12. WRXBUF—RX Buffer Hardware Parameters The register fields are described in the following table. Field reserved RXADD RXBURST Description Reserved. These bits are reserved and should be set to zero. VUSB_HS_RX_ADD VUSB_HS_RX_BURST MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-33 High-Speed USB On-The-Go (HS USB-OTG) 30.8.1.3 Device/Host Capability Registers Device/Host Capability registers specify the software limits, restrictions, and capabilities of the host/device controller implementation. 30.8.1.3.1 CAPLENGTH—EHCI Compliant Address:Base + 100h Default Value:40h Attribute:Read Only Size:8 bits This register is used to indicate which offset to add to the register base address at the beginning of the Operational Register. 7 6 5 4 3 2 1 0 CAPLENGTH[7:0] Figure 30-13. CAPLENGTH—Capability Register Length 30.8.1.3.2 HCIVERSION—EHCI Compliant Address:Base + 102h Default Value:0100h Attribute:Read Only Size:16 bits This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HCIVERSION[15:0] Figure 30-14. HCIVERSION—Host Interface version number 30.8.1.3.3 HCSPARAMS—EHCI Compliant with extensions Address:Base + 104h Default Value:Implementation Dependent Attribute:Read Only Size:32 bits MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-34 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Port steering logic capabilities are described in this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3210 reserved N_TT N_PTT reserved PI N_CC N_PCC reserv ed P P C N_PORT S Figure 30-15. HCSPARAMS—Host Control Structural Parameters The register fields are described in the following table. Table 30-17. HCSPARAMS Field Descriptions Field Reserved Pi Description Reserved. These bits are reserved and should be set to zero. Port Indicators (P INDICATOR). This bit indicates whether the ports support port indicator control. When set to one, the port status and control registers include a read/writeable field for controlling the state of the port indicator. This field will always be “1”. Number of Transaction Translators (N_TT). This field indicates the number of embedded transaction translators associated with the USB2.0 host controller. For Multi-Port Host this field will always equal “0001”. For all other implementations, N_TT = “0000”. This in a non-EHCI field to support embedded TT. Number of Ports per Transaction Translator (N_PTT). This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. For Multi-Port Host this field will always equal N_PORTS. For all other implementations, N_PTT = “0000”. This in a non-EHCI field to support embedded TT. Number of Companion Controller (N_CC). This field indicates the number of companion controllers associated with this USB2.0 host controller. A zero in this field indicates there are no internal Companion Controllers. Port-ownership hand-off is not supported. A value larger than zero in this field indicates there are companion USB1.1 host controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed devices are supported on the host controller root ports. In this implementation this field will always be “0”. N_TT[3:0] N_PTT[3:0] N_CC[3:0] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-35 High-Speed USB On-The-Go (HS USB-OTG) Table 30-17. HCSPARAMS Field Descriptions (continued) Field N_PCC[3:0] Description Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller. It is used to indicate the port routing configuration to the system software. For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc. In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. The number in this field must be consistent with N_PORTS and N_CC. In this implementation this field will always be “0”. Port Power Control. This field indicates whether the host controller implementation includes port power control. A one indicates the ports have port power switches. A zero indicates the ports do not have port power switches. The value of this field affects the functionality of the Port Power field in each port status and control register. This field will always be “0” for a device only implementation. Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register. Valid values are in the range of 1h to Fh. A zero in this field is undefined. The number of ports for a host implementation is parameterizable from 1 to 8. This field will always be 1 for device only implementation. PPC N_PORTS[3:0] 30.8.1.3.4 HCCPARAMS—EHCI Compliant Address:Base + 108h Default Value:0006h Attribute:Read Only Size:32 bits This register identifies multiple mode control (time-base bit functionality) addressing capability. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EECP[7:0] A IST[7:4] R S P P F L A D C Figure 30-16. HCCPARAMS—Host Control Capability Parameters MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-36 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) The register fields are described in the following table. Table 30-18. HCCPARAMS Field Descriptions Field Reserved EECP[7:0] Description Reserved. These bits are reserved and should be set to zero. EHCI Extended Capabilities Pointer. Default = 0. This optional field indicates the existence of a capabilities list. A value of 00h indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI configuration space of the first EHCI extended capability. The pointer value must be 40h or greater if implemented to maintain the consistency of the PCI header defined for this class of device. For this implementation this field is always “0”. Isochronous Scheduling Threshold. Default = implementation dependent. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame. This field will always be “0”. Reserved. These bits are reserved and should be set to zero. Asynchronous Schedule Park Capability. Default = 1. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. This field will always be “1” Programmable Frame List Flag. If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to zero. If set to a one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-page boundary. This requirement ensures that the frame list is always physically contiguous. This field will always be “1”. 64-bit Addressing Capability. This field will always be “0”. No 64-bit addressing capability is supported. IST[7:4] R ASP PFL ADC DCIVERSION (Non-EHCI) Address:Base + 120h Default Value:Implementation Dependent Attribute:Read Only Size:16 bits MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-37 High-Speed USB On-The-Go (HS USB-OTG) The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCIVERSION[15:0] Figure 30-17. DCIVERSION—Device Interface Version Number 30.8.1.3.5 DCCPARAMS (Non-EHCI) Address:Base + 124h Default Value:Implementation Dependant Attribute:Read Only Size:32 bits These fields describe the overall host/device capability of the controller. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65 432 10 reserved HDRR DEN[4:0] Figure 30-18. DCCPARAMS—Device Control Capability Parameters The register fields are described in the following table. Table 30-19. DCCPARAMS Field Descriptions Field Reserved HC DC R DEN[4:0] Description Reserved. These bits are reserved and should be set to zero. Host Capable. When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2.0 host controller. Device Capable. When this bit is 1, this controller is capable of operating as a USB 2.0 device. Reserved. These bits are reserved and should be set to zero. Device Endpoint Number. This field indicates the number of endpoints built into the device controller. If this controller is not device capable, then this field will be zero. Valid values are 0–16. 30.8.1.4 Device/Host Timer Registers (Non-EHCI) The host/device controller drivers can measure time related activities using these timer registers. These registers are not part of the standard EHCI controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-38 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.1.4.1 GPTIMER0LD (Non-EHCI) Address: Base + 80h Default Value: 00000000h Attribute: Read/Write Size: 32 bits This register contains the timer duration or load value. See the GPTIMER0CTRL (Non-EHCI) for a description of the timer functions. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65 432 10 reserved GPTLD Figure 30-19. GPTIMER0LD-General Purpose Timer #0 Load Register The register fields are described in the following table. Table 30-20. GPTIMER0LD Field Descriptions Field Reserved H\GPTLD Description Reserved. These bits are reserved and should be set to zero. General Purpose Timer Load Value. This field is the value to be loaded into the GPTCNT countdown timer on a reset action. This value represents the time in microseconds minus 1 for the timer duration. 30.8.1.4.2 GPTIMER0CTRL (Non-EHCI) Address: Base + 84h Default Value: 00000000h Attribute: Read Only, Write Only, Read/Write Size: 32 bits This register contains the control for the timer and a data field can be queried to determine the running count value. This timer has granularity on 1 us and can be programmed to a little over 16 seconds. There are two modes supported by this timer, the first is a one shot and the second is a looped count which is described in the register table below. When the timer counter value transitions to zero, an interrupt can be generated though the use of the timer interrupts in the USBSTS and USBINTR registers. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-39 High-Speed USB On-The-Go (HS USB-OTG) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 654 321 0 GPTR GPTR reserved GPT GPTCNT Figure 30-20. GPTIMER0LD-General Purpose Timer #0 Controller The register fields are described in the following table. Table 30-21. GPTIMER0LD Field Descriptions Field GPTRUN Description General Purpose Timer Run (0)-Timer Stop; (1)-Timer Run. This bit enable the GPT to run. Setting or Clearing this bit will not have an effect on the GPTCNT except. General Purpose Timer Reset (0)-No action; (1)-Load Counter Value. This bit will reload the GPTCNT with the value in GPTLD. Reserved. These bits are reserved and should be set to zero. GPTRST reserved GPTMOD General Purpose Timer Mode. (0)-One Shot; (1)-Repeat.In one-shot mode the timer will count to zero, generate an interrupt and stop until the timer is reset by software. In repeat mode the timer will count to zero, generate an interrupt and automatically reload the counter to begin again. GPTCNT General Purpose Timer Counter. This field is the value of running timer. 30.8.1.4.3 GPTIMER1LD (Non-EHCI) Address: Base + 88h Default Value: 00000000h High-Speed USB Controller Core Reference Attribute: Read/Write Size: 32 bits Same as GPTIMER0LD. 30.8.1.4.4 GPTIMER1CTRL (Non-EHCI) Address: Base + 8Ch Default Value: 00000000h Attribute: Read Only, Write Only, Read/Write Size: 32 bits Same as GPTIMER0CTRL. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-40 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.1.5 Device/Host Operational Registers Operational registers are comprised of dynamic control or status registers that may be read only, read/write, or read/write to clear. The following sections define the use of these registers. 30.8.1.5.1 USBCMD Address:Base + 140h Default Value:00080B00h (host mode) 00080000h (device mode) Attribute:Read Only, Read/Write, Write Only (field dependent) Size:32 bits The serial bus host/device controller executes the command indicated in this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ITC[7:0] FS R 2 SUT W ATD TW AS PE R I AS AS L AS PS FS FS RS R A P1 P0 R EE10TS A Figure 30-21. USBCMD—USB Command Register The register fields are described in the following table. Table 30-22. USBCMD—USB Command Register Field Descriptions Field Description R, reserved Reserved. These bits are reserved and should be set to zero. ITC[7:0] Interrupt Threshold Control. Read/Write. Default 08h. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. Value Maximum Interrupt Interval 00h Immediate (no threshold) 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames 10h 16 micro-frames 20h 32 micro-frames 40h 64 micro-frames Setup TripWire. Read/Write [device mode only].This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (See USBMODE) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. For more information on the use of this bit, see the Device Operational Model section of the USB-HS OTG High-Speed USB On-The-Go DEV reference manual. SUTW MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-41 High-Speed USB On-The-Go (HS USB-OTG) Table 30-22. USBCMD—USB Command Register Field Descriptions (continued) Field ATDTW Description Add dTD TripWire. Read/Write[device mode only]. This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. For more information on the use of this bit, see the Device Operational Model section of the USB-HS OTG High-Speed USB On-The-Go DEV reference manual. Asynchronous Schedule Park Mode Enable (OPTIONAL). Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is read-only. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. This field is set to “1” in this implementation. Asynchronous Schedule Park Mode Count (OPTIONAL). Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. See Section 4.10.3.2 for full operational details. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. This field is set to 3h in this implementation. Light Host/Device Controller Reset (OPTIONAL). Read Only. Not Implemented. This field will always be “0”. Interrupt on Async Advance Doorbell. Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. Asynchronous Schedule Enable. Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. Valuesmeaning 0 Do not process the Asynchronous Schedule. 1 Use the ASYNCLISTADDR register to access theAsynchronous Schedule. Only the host controller uses this bit. Periodic Schedule Enable. Read/Write. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. Values meaning 0 Do not process the Periodic Schedule 1 Use the PERIODICLISTBASE register to access the PeriodicSchedule. Only the host controller uses this bit. ASPE ASP[1:0] LR IAA ASE PSE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-42 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-22. USBCMD—USB Command Register Field Descriptions (continued) Field FS[2:0] Description Frame List Size. (Read/Write or Read Only). Default 000b. This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3 and 2. Values meaning 000 1024 elements (4096 bytes) Default value 001 512 elements (2048 bytes) 010 256 elements (1024 bytes) 011 128 elements (512 bytes) 100 64 elements (256 bytes) 101 32 elements (128 bytes) 110 16 elements (64 bytes) 111 8 elements (32 bytes) Only the host controller uses this field. Controller Reset (RESET) — Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Host Controller: When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Device Controller: When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. Run/Stop (RS)—Read/Write. Default 0b. 1=Run. 0=Stop. Host Controller: When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). Device Controller: Writing a one to this bit will cause the device controller to enable a pull-up on D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. Writing a 0 to this will cause a detach event. RST RS 30.8.1.5.2 USBSTS Address:Base + 144h Default Value:00001000h (host mode) 00000000h (device mode) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-43 High-Speed USB On-The-Go (HS USB-OTG) Attribute:Read Only, Read/Write, Read/Write-Clear (field dependant) Size:32 bits This register indicates various states of the Host/Device Controller and any pending interrupts. This register does not indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by writing a 1 to them. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 543 2 10 reserved TI TI 10 reserved A S P S R C L H C H R SS U ASF P U UL U RL R R A E RC E PII I IIIIIIII Figure 30-22. USBSTS—USB Status The register fields are described in the following table. Table 30-23. USBSTS Field Descriptions Field Description Reserved Reserved. These bits are reserved and should be set to zero. TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC. This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this bit will clear it. General Purpose Timer Interrupt 0(GPTINT0)--R/WC. This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this bit will clear it. Reserved. These bits are reserved and should be set to zero. Asynchronous Schedule Status — Read Only. 0=Default. This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used by the host controller. Periodic Schedule Status — Read Only. 0=Default. This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Only used by the host controller. Reclamation — Read Only. 0=Default. This is a read-only status bit used to detect an empty asynchronous schedule. Only used by the host controller. TI0 reserved AS PS RCL MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-44 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-23. USBSTS Field Descriptions (continued) Field HCH Description HCHaIted — Read Only. 1=Default. This bit is a zero whenever the Run/Stop bit is a one. The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (for example, internal error). Only used by the host controller. Reserved. These bits are reserved and should be set to zero. ULPI Interrupt—R/WC. 0=Default. When the ULPI Viewport is present in the design, an event completion will set this interrupt. Used by both host and device controller. Only present in designs where configuration constant VUSB_HS_PHY_ULPI = 1. Reserved. These bits are reserved and should be set to zero. DCSuspend—R/WC. 0=Default. When a device controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used by the device controller. SOF Received—R/WC. 0=Default. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it. This is a non-EHCI status bit. USB Reset Received—R/WC. 0=Default. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used by the device controller. Interrupt on Async Advance — R/WC. 0=Default. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. Only used by the host controller. System Error— R/WC. This bit is not used in this implementation and will always be set to “0”. Frame List Rollover — R/WC. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [1 3] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX [12] toggles. Only used by the host controller. R ULPII R SLI SRI URI AAI SEI FRI MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-45 High-Speed USB On-The-Go (HS USB-OTG) Table 30-23. USBSTS Field Descriptions (continued) Field PCI Description Port Change Detect — R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively. This bit is not EHCI compatible. USB Error Interrupt (USBERRINT) — R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set See Section (Reference Host Operation Model: Transfer/Transaction Based Interrupt—that is, 4.15.1 in EHCI Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation. http://www.intel.com) for a complete list of host error interrupt conditions. See section Device Error Matrix in the USB-HS OTG High-Speed USB On-The-Go DEV reference manual. The device controller detects resume signaling only. USB Interrupt (USBINT)—R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. UEI UI 30.8.1.5.3 USBINTR Address:Base + 148h Default Value:00000000h Attribute:Read/Write Size:32 bits The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TI TI EE 10 reserved S ULP RL IE E S R E UAS RAE EEE F R E P C E U U E E E Figure 30-23. USBINTR—USB Interrupt Enable MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-46 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) The register fields are described in the following table. Table 30-24. USBINTR Field Descriptions Field Reserved TIE1 Interrupt Source Reserved Description These bits are reserved and should be set to zero. GPT Interrupt When this bit is one and the GPTINT1 in USBSTS register is a Enable1 one the controller will issue an interrupt. The interrupt is acknowledge by software clear the GPTINT1 bit. GPT Interrupt When this bit is one and the GPTINT0 in USBSTS register is a Enable0 one the controller will issue an interrupt. The interrupt is acknowledge by software clear the GPTINT0 bit. Reserved. ULPI Enable These bits are reserved and should be set to zero. When this bit is a one, and the ULPI Interrupt bit in the USBSTS register transitions, the controller will issue and interrupt. The interrupt is acknowledged by software writing a one to the ULPI Interrupt bit. Used by both host and device controller. Only present in designs where configuration constant VUSB_HS_PHY_ULPI = 1. These bits are reserved and should be set to zero. TIE0 reserved ULPIE reserved SLE Reserved. Sleep Enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit. Only used by the device controller. SOF Received When this bit is a one, and the SOF Received bit in the USBSTS Enable register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit. USB Reset Enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only used by the device controller. When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. Only used by the host controller. SRE URE AAE Interrupt on Async Advance Enable SEE System Error When this bit is a one, and the System Error bit in the USBSTS Enable register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the System Error bit. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-47 High-Speed USB On-The-Go (HS USB-OTG) Table 30-24. USBINTR Field Descriptions (continued) Field FRE Interrupt Source Frame List Rollover Enable Description When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. Only used by the host controller. PCE Port Change When this bit is a one, and the Port Change Detect bit in the Detect Enable USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit. USB Error Interrupt Enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. UEE UE USB Interrupt When this bit is a one, and the USBINT bit in the USBSTS Enable register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit. 30.8.1.5.4 FRINDEX Address:Base + 14Ch Default Value:Undefined (free running counter) Attribute:Read/Write in host mode, Read in device mode Size:32 bits This register is used by the host controller to index the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Size field in the USBCMD register. This register must be written as a DWord. Byte writes produce-undefined results. This register cannot be written unless the Host Controller is in the 'Halted' state as indicated by the HCHalted bit. A write to this register while the Run/Stop hit is set to a one produces undefined results. Writes to this register also affect the SOF value. In device mode this register is read only and, the device controller updates the FRINDEX [13:3] register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus, FRINDEX [13:3] will be checked against the SOF marker. If FRINDEX [13:3] is different from the SOF marker, FRINDEX [13:3] will be set to the SOF value and FRINDEX [2:0] will be set to zero (that is, SOF for 1 ms frame). If FRINDEX [13:3] is equal to the SOF value, FRINDEX [2:0] will be increment (that is, SOF for 125 us micro-frame.) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-48 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reserved FRINDEX[13:0] Figure 30-24. FRINDEX—USB Frame Index The register fields are described in the following table. Table 30-25. FRINDEX Register Field Descriptions Field Reserved FRINDEX Description Reserved. These bits are reserved and should be set to zero. Frame Index. The value, in this register, increments at the end of each time frame (for example, micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. USBCMD[Frame List Size] Number Elements N 000b (1024)12 001b (512)11 010b (256)10 011b (128)9 100b (64)8 101b (32)7 110b (16)6 111b (8) 5 In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. In either mode bits 2:0 indicate the current microframe. 30.8.1.5.5 CTRLDSSEGMENT Address:Base + 150h Default Value:00000000h Attribute:Read Only Size:32 bits This register is not used in this implementation. 30.8.1.5.6 PERIODICLISTBASE; DEVICEADDR Address:Base + 154h Default Value:00000000h Attribute:Read/Write (Writes must be DWord Writes) Size:32 bits MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-49 High-Speed USB On-The-Go (HS USB-OTG) This register is shared between the host controller and the device controller operation. Host Controller (PERIODICLISTBASE) This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. HCD loads this register prior to starting the schedule execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 4 32 1 0 PERBASE[31:12] reserved Figure 30-25. PERIODICLISTBASE - Host Controller Frame List Base Address The register fields are described in the following table. Table 30-26. PERIODICLISTBASE Register Field Descriptions Field BASEADR Description Base Address (Low). These bits correspond to memory address signals [31:12], respectively. Only used by the host controller. Reserved. Must be written as zeros. During runtime, the values of these bits are undefined. Reserved Device Controller (USB DEVICEADDR) The upper seven bits of this register represent the device address. After any controller reset or a USB reset, the device address is set to the default address (0). The default address will match all incoming addresses. Software shall reprogram the address after receiving a SET_ADDRESS descriptor. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 43 2 1 0 USBADR[31:25] reserved Figure 30-26. DEVICEADDR - Device Controller USB Device Address The register fields are described in the following table. Table 30-27. DEVICEADDR Field Descriptions Field USBADR reserved Description Device Address. These bits correspond to the USB device address Reserved. Must be written as zeros. During runtime, the values of these bits are undefined. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-50 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.1.5.7 ASYNCLISTADDR; ENDPOINTLISTADDR Address:Base + 158h Default Value:00000000h Attribute:Read/Write (Writes must be DWord Writes) Size:32 bits This register is shared between the host controller and the device controller operation. Host Controller (ASYNCLISTADDR) This 32-bit register contains the address of the next asynchronous queue head to be executed by the host. Bits [4:0] of this register cannot be modified by the system software and will always return a zero when read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 4 32 1 0 ASYBASE[31:5] reserved Figure 30-27. ASYNCLISTADDR - Host Controller Next Asynch. Address The register fields are described in the following table. Table 30-28. ASYNCLISTADDR Field Descriptions Field ASYBASE[31:5] Description Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (OH). Only used by the host controller. Reserved. These bits are reserved and their value has no effect on operation. Reserved Device Controller (ENDPOINTLISTADDR) In device mode, this register contains the address of the top of the endpoint list in system memory. Bits [10:0] of this register cannot be modified by the system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed 64-byte. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 43 2 1 0 EPBASE[31:11] reserved Figure 30-28. ENDPOINTLISTADDR - Device Controller Endpoint List Address MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-51 High-Speed USB On-The-Go (HS USB-OTG) The register fields are described in the following table. Table 30-29. ENDPOINTLISTADDR Field Descriptions Field EPBASE[31:11] Description Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (OH) (for example, one queue head per endpoint and direction). Reserved. These bits are reserved and their value has no effect on operation. Reserved 30.8.1.5.8 BURSTSIZE Address:Base + 160h Default Value:Implementation Dependent Attribute:Read/Write (Writes must be DWord Writes) Size:32 bits This register is used to control dynamically change the burst size used during data movement on the initiator (master) interface. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65 4 3 21 0 reserved TXPBURST RXPBURST Figure 30-29. BURSTSIZE - Host Controller Embedded TT Async. Buffer Status The register fields are described in the following table. Table 30-30. BURSTSIZE Field Descriptions Field Reserved TXPBURST Description Reserved. These bits are reserved and their value has no effect on operation. Programmable TX Burst Length. (Read/Write) Default is the constant VUSB_HS_TX_BURST. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus. Programmable RX Burst Length. (Read/Write) Default is the constant VUSB_HS_RX_BURST. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory. RXPBURST 30.8.1.5.9 TXFILLTUNING Address:Base + 164h Default Value:00020000h MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-52 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Attribute:Read/Write (Writes must be DWord Writes) Size:32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved TXFIFOTHRES reserved TXSCHEALTH TXSCHOH Figure 30-30. TXFILLTUNING The fields in this register control performance tuning associated with how the host controller posts data to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target system. Definitions: T0 = Standard packet overhead T1 = Time to send data payload Tff = Time to fetch packet into TX FIFO up to specified level. Ts = Total Packet Flight Time (send-only) packet Ts = T0 + T1 Tp = Total Packet Time (fetch and send) packet Tp = Tff + T0 + T1 Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure Tp remains before the end of the [micro]frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the [micro]frame is < Ts then the packet attempt ceases and the packet is tried at a later time. Although this is not an error condition and the host controller will eventually recover, a mark will be made the scheduler health counter to note the occurrence of a “back-off” event. When a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Back-offs can be minimized with use of the TSCHHEALTH (Tff) described below. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-53 High-Speed USB On-The-Go (HS USB-OTG) The register fields are described in the following table. Table 30-31. TXFILLTUNING Field Descriptions Field Reserved TXFIFOTHRES Description Reserved. These bits are reserved and their value has no effect on operation. FIFO Burst Threshold. (Read/Write) [Default = 2] This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set. Scheduler Health Counter. (Read/Write To Clear) [Default = 0] This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. Reserved. These bits are reserved and their value has no effect on operation. Scheduler Overhead. (Read/Write) [Default = 0] This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode for OTG and SPH. The time unit represented in this register is always 1.267 the MPH product. TXSCHHEALTH Reserved TXSCHOH 30.8.1.5.10 ULPI VIEWPORT (Optional) Address:Base + 170h Default Value:00000000h Attribute:Read/Write Size:32 bits The register provides indirect access to the ULPI PHY register set. Although the core performs access to the ULPI PHY register set, there may be extraordinary circumstances where software may need direct access. • CAUTION: Writes to the ULPI through the VIEWPORT can substantially harm standard USB operations. currently no usage model MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-54 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • has been defined where software should need to execute writes directly to the ULPI. NOTE: Executing read operations though the ULPI Viewport should have no harmful side effects to standard USB operations. Note: the ULPI Viewport is only synthesized in the design if the ULPI option has been purchased and installed and the constant VUSB_HS_PHY_ULPI is set to 1. If the ULPI interface is not enabled, this register will always read zeros. There are two operations that can be performed with the ULPI Viewport, wakeup and read /write operations. The wakeup operation is used to put the ULPI interface into normal operation mode and re-enable the clock if necessary. A wakeup operation is required before accessing the registers when the ULPI interface is operating in low power mode, serial mode, or carkit mode. The ULPI state can be determined by reading the sync. state bit (ULPISS). If this bit is a one, then ULPI interface is running in normal operation mode and can accept read/write operations. If the ULPISS indicates a ‘0’ then read/write operations will not be able execute. Undefined behavior will result if ULPISS = 0 and a read or write operation is performed. To execute a wakeup operation, write all 32-bits of the ULPI Viewport where ULPIPORT is constructed appropriately and the ULPIWU bit is a ‘1’ and ULPIRUN bit is a ‘0’. Poll the ULPI Viewport until ULPIWU is zero for the operation to complete. To execute a read or write operation, write all 32-bits of the ULPI Viewport where ULPIDATWR, ULPIADDR, ULPIPORT, ULPIRW are constructed appropriately and the ULPIRUN bit is a ‘1’. Poll the ULPI Viewport until ULPIRUN is zero for the operation to complete. Once ULPIRUN is zero, the ULPIDATRD will be valid if the operation was a read. The polling method above could also be replaced and interrupt driven using the ULPI interrupt defined in the USBSTS and USBINTR registers. When a wakeup or read/write operation complete, the ULPI interrupt will be set. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-55 High-Speed USB On-The-Go (HS USB-OTG) 31 30 29 2 8 27 2 6 2 5 2 4 222211111111119876543210 32109876543210 ULPI ULPIR ULPIR R ULPI ULPIPO ULPIADDR ULPIDATRD ULPIDATWR Figure 30-31. ULPI VIEWPORT Table 30-32. ULPI VIEWPORT Field Descriptions Field ULPIWU Description ULPI Wakeup—Read/Write. Writing the ‘1’ to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to ‘0’. Note: The driver must never execute a wakeup and a read/write operation at the same time. ULPI Read/Write Run—Read/Write. Writing the ‘1’ to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to ‘0’. Note: The driver must never execute a wakeup and a read/write operation at the same time. ULPI Read/Write Control—Read/Write. (0)—Read; (1)—Write. This bit selects between running a read or write operation. Reserved. This bit is reserved and its value has no effect on operation. ULPI Sync State—Read Only. (1)—Normal Sync. State. (0) In another state (that is, carkit, serial, low power) This bit represents the state of the ULPI interface. Before reading this bit, the ULPIPORT field should be set accordingly if used with the multi-port host. Otherwise, this field should always remain 0. ULPI Port Number—Read/Write. For the wakeup or read/write operation to be executed, this value selects the port number the ULPI PHY is attached to in the multi-port host. The range is 0 to 7. This field should always be written as a 0 for the non-multi port products. ULPI Data Address—Read/Write. When a read or write operation is commanded, the address of the operation is written to this field. ULPI Data Read—Read Only. After a read operation completes, the result is placed in this field. ULPI Data Write—Read/Write. When a write operation is commanded, the data to be sent is written to this field. ULPIRUN ULPIRW reserved ULPISS ULPIPORT ULPIADDR ULPIDATRD ULPIDATWR 30.8.1.5.11 CONFIGFLAG Address:Base + 180h Default Value:00000001h Attribute:Read Only Size:32 bits MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-56 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) This register is not used in this implementation. A read from this register returns a constant of a 00000001h to indicate that all port routines default to this host controller. 30.8.1.5.12 PORTSCx Address:Base + 184h + (4*(Port Number –1)) where Port Number =1,2,3,…8 Default Value: IIII0000000000000000XX0000000000b (host mode) IIII0000000000000001XX0000000100b (device mode) I = Implementation dependent X = Unknown Attribute:RO, Read/Write, R/WC (field dependent) Size:32 bits Host Controller A host controller must implement one to eight port registers. The number of port registers implemented by a particular instantiation of a host controller is documented in the HCSPARAMs register. Software uses this information as an input parameter to determine how many ports need service. This register is only reset when power is initially applied or in response to a controller reset. The initial conditions of a port are: No device connected Port disabled If the port has port power control, this state remains until software applies power to the port by setting port power to one. Device Controller A device controller must implement only port register one and it does not support power control. Port control in device mode is only used for status port reset, suspend, and current connect status. It is also used to initiate test mode or force signaling and allows software to put the PHY into low power suspend mode and disable the PHY clock. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTS SP PSP TT D SW P F R S C P H C D W K O C W K D S W K C N PTC[3:0] PIC PP OP LS S H FOOP CC PU P S PCCE SC RS E P RCAC CS P Figure 30-32. PORTSCx - Port Status Control[1:8] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-57 High-Speed USB On-The-Go (HS USB-OTG) The register fields are described in the following table. Table 30-33. PORTSCx Field Descriptions Field PTS Description Parallel Transceiver Select—Read/Write. This register bit pair is used in conjunction with the configuration constant VUSB_HS_PHY_TYPE to control which parallel transceiver interface is selected. If VUSB_HS_PHY_TYPE is set for 0,1,2, or 3 then this bit is read only. If VUSB_HS_PHY_TYPE is 3,4,5, or 6 then this bit is read/write. This field is reset to: “00” if VUSB_HS_PHY_TYPE = 0,4—UTMI/UTMI+ “01” if VUSB_HS_PHY_TYPE = 1,5—Reserved “10” if VUSB_HS_PHY_TYPE = 2,6—ULPI “11” if VUSB_HS_PHY_TYPE = 3,7—Serial/1.1 PHY (FS Only) This bit is not defined in the EHCI specification. Serial Transceiver Select—Read/Write. This register bit is used in conjunction with the configuration constant VUSB_HS_PHY_SERIAL to control whether the parallel or serial transceiver interface is selected for FS and LS operation. The Serial Interface Engine can be used in combination with the UTMI+ or ULPI physical interface to provide FS/LS signaling instead of the parallel interface. If VUSB_HS_PHY_SERIAL is set for 0 or 1 then this bit is read only. If VUSB_HS_PHY_SERIAL is 3 or 4 then this bit is read/write. This bit has no effect unless Parallel Transceiver Select is set to UTMI+ or ULPI. The Serial/1.1 physical interface will use the Serial Interface Engine for FS/LS signaling regardless of this bit value. Note: This bit is reserved for future operation and is a placeholder adding dynamic use of the serial engine in accord with UMTI+ and ULPI characterization logic. This bit is not defined in the EHCI specification. Parallel Transceiver Width—Read/Write. This register bit is used in conjunction with the configuration constant VUSB_HS_PHY8_16 to control whether the data bus width of the UTMI transceiver interface. If VUSB_HS_PHY8_16 is set for 0 or 1 then this bit is read only. If VUSB_HS_PHY8_16 is 2 or 3 then this bit is read/write. This bit is reset to 1 if VUSB_HS_PHY8_16 selects a default UTMI interface width of 16-bits else it is reset to 0. Writing this bit to 0 selects the 8-bit [60MHz] UTMI interface. Writing this bit to 1 selects the 16-bit [30MHz] UTMI interface. This bit has no effect if the Serial interfaces are selected. This bit is not defined in the EHCI specification. PSPD Port Speed—Read Only. This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 00—Full Speed 01—Low Speed 10—High Speed This bit is not defined in the EHCI specification. Port Force Full Speed Connect—Read/Write. Default = 0b. Writing this bit to a 1b will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. This bit is not defined in the EHCI specification. This bit is for debugging purposes. STS PTW PFSC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-58 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-33. PORTSCx Field Descriptions (continued) Field PHCD Description PHY Low Power Suspend - Clock Disable (PLPSCD)—Read/Write. Default = 0b. Writing this bit to a 1b will disable the PHY clock. Writing a 0b enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend—Clock Disable when the device is not running (USBCMD Run/Stop=0b) or the host has signaled suspend (PORTSC SUSPEND=1b). Low power suspend will be cleared automatically when the host has signaled resume if using a circuit similar to that in. Before forcing a resume from the device, the device controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend—Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. See for more discussion on clock disable and power down issues. This bit is not defined in the EHCI specification. Wake on Over-current Enable (WKOC_E) — Read/Write. Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power(PP) is zero. This bit is output from the controller as signal pwrctl_wake_ovrcurr_en (OTG/host core only) for use by an external power control circuit. Wake on Disconnect Enable (WKDSCNNT_E) — Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. This bit is output from the controller as signal pwrctl_wake_dscnnt_en (OTG/host core only) for use by an external power control circuit. Wake on Connect Enable (WKCNNT_E) — Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. This bit is output from the controller as signal pwrctl_wake_dscnnt_en (OTG/host core only) for use by an external power control circuit. Port Test Control — Read/Write. Default = 0000b. Any other value than zero indicates that the port is operating in test mode. Value Specific Test 0000b TEST_MODE_DISABLE 0001b J_ STATE 0010b K_STATE 0011b SE0 (host)/NAK (device) 0100b Packet 0101b FORCE_ENABLE_HS 0110b FORCE_ENABLE_FS 0111b FORCE_ENABLE_LS 1000b to 1111bReserved Refer to the USB Specification Revision 2.0 Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips. http://www.usb.org for details on each test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Note: Low-speed operations are not supported as a peripheral device. WKOC WKDC WKCN PTC[3:0] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-59 High-Speed USB On-The-Go (HS USB-OTG) Table 30-33. PORTSCx Field Descriptions (continued) Field PIC[1:0] Description Port Indicator Control — Read/Write. Default = Ob. Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is a zero. If P_INDICATOR bit is a one, then the bit is: Bit ValueMeaning 00b Port indicators are off 01b Amber 10b Green 11b Undefined Refer to the USB Specification Revision 2.0 Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips. http://www.usb.org for a description on how these bits are to be used. This field is output from the controller as signals port_ind_ctl_1 and port_ind_ctl_0 for use by an external led driving circuit. Port Owner—Read/Write. Default = 0. This bit unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is zero System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that an internal companion controller owns and controls the port. Port owner handoff is not implemented in this design, therefore this bit will always be 0. Port Power (PP)—Read/Write or Read Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: PPC PP Operation 0b 0b Read Only— A device controller with no OTG capability does not have port power control switches. 1b 1b/0b—RW. Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). This feature is implemented in the host/OTG controller (PPC = 1). In a device only implementation port power control is not necessary, thus PPC and PP = 0. Line Status—Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. The encoding of the bits are: Bits [11:10]Meaning 00b SE0 10b J-state 01b K-state 11b Undefined In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In device mode, the use of linestate by the device controller driver is not necessary. HSP High-Speed Port — Read Only. Default = 0b. When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. Note: HSP is redundant with PSPD(27:26) but will remain in the design for compatibility. This bit is not defined in the EHCI specification. PO PP LS[1:0] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-60 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-33. PORTSCx Field Descriptions (continued) Field PR Description Port Reset This field is zero if Port Power(PP) is zero. In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. Suspend In Host Mode: Read/Write. 1=Port in suspend state. 0=Port not in suspend state. Default=0. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend]Port State 0x Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PP) is zero in host mode. In Device Mode: Read Only. 1=Port in suspend state. 0=Port not in suspend state. Default=0. In device mode this bit is a read only status bit. Force Port Resume —Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected/driven on port. Default = 0. In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This field is zero if Port Power(PP) is zero in host mode. This bit is not-EHCI compatible. In Device mode: After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is also set to one. SUSP FPR MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-61 High-Speed USB On-The-Go (HS USB-OTG) Table 30-33. PORTSCx Field Descriptions (continued) Field OCC Description Over-current Change—R/WC. Default=0. 1=This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position. For host/OTG implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. For device-only implementations this bit shall always be 0. Over-current Active—Read Only. Default 0. 1=This port currently has an over-current condition. 0=This port does not have an over-current condition. This bit will automatically transition from one to zero when the over current condition is removed. For host/OTG implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. For device-only implementations this bit shall always be 0. Port Enable/Disable Change—R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. In Host Mode: For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point. Software clears this by writing a one to it. This field is zero if Port Power(PP) is zero. In Device mode: The device port is always enabled. (This bit will be zero) Port Enabled/Disabled—Read/Write. 1=Enable. 0=Disable. Default 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PP) is zero in host mode. In Device Mode: The device port is always enabled. (This bit will be one) Connect Status Change—R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. In Host Mode: Indicates a change has occurred in the port’s Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ‘setting’ an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. This field is zero if Port Power(PP) is zero in host mode. In Device Mode: This bit is undefined in device controller mode. Current Connect Status—Read Only. In Host Mode: 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PP) is zero in host mode. In Device Mode: 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. OCA PEC PE CSC CCS MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-62 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.1.5.13 OTGSC Address:Base + 1A4h Default Value:00000020h Attribute:RO, Read/Write, R/WC (field dependent) Size:32 bits Host Controller A host controller implements one On-The-Go (OTG) Status and Control register corresponding to Port 0 of the host controller. The OTGSC register has four sections OTG Interrupt enables (Read/Write) OTG Interrupt status (Read/Write to Clear) OTG Status inputs (Read Only) OTG Controls(Read/Write) The status inputs are debounced using a 1Msec time constant. Values on the status inputs that do not persist for more than 1Msec will not cause an update of the status input register, or cause an OTG interrupt. See also USBMODE register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R D P I E 1 m s E B S EI E B S VI E A S VI E A 1 D V ID m R PI VI IE s S E s B S EI S B S VI S A S VI S A 1 D I BBAA V m I DRP SSSV VI s D S IS EVVV S T R I DD PP U O VV R T CD Figure 30-33. OTGSC—OTG Status Control The register fields are described in the following table. Table 30-34. OTGSC Field Descriptions Field DPIE 1msE BSEIE BSVIE ASVIE Data Pulse Interrupt Enable 1 millisecond timer Interrupt Enable—Read/Write B Session End Interrupt Enable—Read/Write. Setting this bit enables the B session end interrupt. B Session Valid Interrupt Enable—Read/Write. Setting this bit enables the B session valid interrupt. A Session Valid Interrupt Enable—Read/Write. Setting this bit enables the A session valid interrupt. Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-63 High-Speed USB On-The-Go (HS USB-OTG) Table 30-34. OTGSC Field Descriptions (continued) Field AVVIE IDIE DPIS Description A VBus Valid Interrupt Enable—Read/Write. Setting this bit enables the A VBus valid interrupt. USB ID Interrupt Enable—Read/Write. Setting this bit enables the USB ID interrupt. Data Pulse Interrupt Status—Read/Write to Clear. This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0).PortPower = Off (0). Software must write a one to clear this bit. 1 millisecond timer Interrupt Status—Read/Write to Clear. This bit is set once every millisecond. Software must write a one to clear this bit. B Session End Interrupt Status—Read/Write to Clear. This bit is set when VBus has fallen below the B session end threshold. Software must write a one to clear this bit B Session Valid Interrupt Status—Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.8 VDC). Software must write a one to clear this bit. A Session Valid Interrupt Status—Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the A session valid threshold (0.8 VDC). Software must write a one to clear this bit. A VBus Valid Interrupt Status—Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the VBus valid threshold (4.4 VDC) on an A device. Software must write a one to clear this bit. USB ID Interrupt Status—Read/Write. This bit is set when a change on the ID input has been detected. Software must write a one to clear this bit. Data Bus Pulsing Status—Read Only. A ‘1’ indicates data bus pulsing is being detected on the port. 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. B Session End—Read Only. Indicates VBus is below the B session end threshold. B Session Valid—Read Only. Indicates VBus is above the B session valid threshold. A Session Valid—Read Only. Indicates VBus is above the A session valid threshold. A VBus Valid—Read Only. Indicates VBus is above the A VBus valid threshold. USB ID—Read Only. 0 = A device, 1 = B device 1msS BSEIS BSVIS ASVIS AVVIS IDIS DPS 1msT BSE BSV ASV AVV ID MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-64 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-34. OTGSC Field Descriptions (continued) Field IDPU Description ID Pullup—Read/Write This bit provide control over the ID pull-up resister; 0 = off, 1 = on [default]. When this bit is 0, the ID input will not be sampled. Data Pulsing—Read/Write. Setting this bit causes the pullup on DP to be asserted for data pulsing during SRP. OTG Termination—Read/Write. This bit must be set when the OTG device is in device mode, this controls the pulldown on DM. VBUS Charge—Read/Write. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. VBUS_Discharge—Read/Write. Setting this bit causes VBus to discharge through a resistor. DP OT VC VD 30.8.1.5.14 USBMODE Address:Base + 1A8h Default Value:00000000h (otg implementation—mode not selected) 00000003h (host mode) 00000002h (device mode)) Attribute:R/WO, Read Only Size:32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved S SL E CM Figure 30-34. USBMODE -USB Device Mode MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-65 High-Speed USB On-The-Go (HS USB-OTG) The register fields are described in the following table. Field reserved SDIS Description Reserved. These bits are reserved and should be set to zero. Stream Disable Mode. (0—Inactive [default]; 1—Active) Device Mode: Setting to a ‘1’ disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active. Host Mode: Setting to a ‘1’ ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for the scheduler when using this feature. Note: The use of this feature substantially limits of the overall USB performance that can be achieved. Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model. 0—Setup Lockouts On (default); 1—Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD) Endian Select—Read/Write. This bit can change the byte alignment of the transfer buffers to match the host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. Bit Meaning 0 Little Endian [Default] 1 Big Endian Controller Mode—R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host and device capability, the controller will default to an idle state and will need to be initialized to the desired operating mode after reset. For combination host/device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. Bit Meaning 00 Idle [Default for combination host/device] 01 Reserved 10 Device Controller [Default for device only controller] 11 Host Controller [Default for host only controller] SLOM ES CM[1:0] 30.8.1.5.15 ENDPTSETUPSTAT Address:Base + 1ACh Default Value:00000000h Attribute:R/WC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-66 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Size:32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65 4 3 21 0 reserved ENDPTSETUPSTAT[15:0] Figure 30-35. ENDPTSETUPSTAT—Endpoint Setup Status The register fields are described in the following table. Field reserved ENDPTSETUPSTAT [15:0] Description Reserved. These bits are reserved and should be set to zero. Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock our mechanism is engaged. See Managing Endpoints in the Device Operational Model. This register is only used in device mode. 30.8.1.5.16 ENDPTPRIME Address:Base + 1B0h Default Value:00000000h Attribute:R/WS Size:32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 54 3 2 1 0 PETB[15:0] PERB[15:0] Figure 30-36. ENDPTPRIME—Endpoint Initialization This register is only used in device mode. The register fields are described in the following table. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-67 High-Speed USB On-The-Go (HS USB-OTG) Field PETB [15:0] Description Prime Endpoint Transmit Buffer—R/WS. For each endpoint a corresponding bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB[15] – Endpoint #15 PETB[1] – Endpoint #1 PETB[0] – Endpoint #0 Prime Endpoint Receive Buffer—R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. Bit 15 – Endpoint #15 Bit 1 – Endpoint #1 Bit 0 – Endpoint #0 PERB [15:0] 30.8.1.5.17 ENDPTFLUSH Address:Base + 1B4h Default Value:00000000h Attribute:R/WS Size:32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 43 2 1 0 FETB[15:0] FERB[15:0] Figure 30-37. ENDPTFLUSH—Endpoint De-Initialize This register is only used in device mode. The register fields are described in the following table. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-68 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Field FETB [15:0] Description Flush Endpoint Transmit Buffer—R/WS. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. FETB[15] – Endpoint #15 FETB[1] – Endpoint #1 FETB[0] – Endpoint #0 Flush Endpoint Receive Buffer—R/WS. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. Bit 15 – Endpoint #15 Bit 1 – Endpoint #1 Bit 0 – Endpoint #0 FERB [15:0] 30.8.1.5.18 ENDPTSTAT Address:Base + 1B8h Default Value:00000000h Attribute:Read Only Size:32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65 4 3 21 0 ETBR[15:0] ERBR[15:0] Figure 30-38. ENDPTSTAT—Endpoint Status This register is only used in device mode. The register fields are described in the following table. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-69 High-Speed USB On-The-Go (HS USB-OTG) Field ETBR [15:0] Description Endpoint Transmit Buffer Ready—Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR[15]– Endpoint #15 ETBR[1]– Endpoint #1 ETBR[0]– Endpoint #0 Endpoint Receive Buffer Ready—Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ERBR[15]– Endpoint #15 ERBR[1]– Endpoint #1 ERBR[0]– Endpoint #0 ERBR [15:0] 30.8.1.5.19 ENDPTCOMPLETE Address:Base + 1BCh Default Value:00000000h Attribute:R/WC Size:32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65 4 3 21 0 ETCE[15:0] ERCE[15:0] Figure 30-39. ENDPTCOMPLETE—Endpoint Compete This register is only used in device mode. The register fields are described in the following table. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-70 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Field ETCE [15:0] Description Endpoint Transmit Complete Event—R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear the corresponding bit in this register. ETCE[15]– Endpoint #15 ETCE[1]– Endpoint #1 ETCE[0]– Endpoint #0 Endpoint Receive Complete Event—RW/C. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear the corresponding bit in this register. ERCE[15]– Endpoint #15 ERCE[1]– Endpoint #1 ERCE[0]– Endpoint #0 ERCE [15:0] 30.8.1.5.20 ENDPTCTRL0 Address:Base + 1C0h Default Value:0080008h Attribute:Read Only, Read/Write, R/WC (field dependent) Size:32 bits Every Device will implement Endpoint0 as a control endpoint. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved T X E reserved TXT T RX S reserved R reserv X ed E R RX RX T S Figure 30-40. ENDPTCTRL0—Endpoint Control 0 The register fields are described in the following table. Field reserved TXE Description Reserved. These bits are reserved and should be set to zero. TX Endpoint Enable 1—Enabled Endpoint0 is always enabled. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-71 High-Speed USB On-The-Go (HS USB-OTG) Field TXT[1:0] TX Endpoint Type—Read/Write 00—Control Description Endpoint0 is fixed as a Control End Point. R TXS Reserved. Bit reserved and should be set to zero. TX Endpoint Stall—Read/Write 0—End Point OK [Default] 1—End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. RX Endpoint Enable 1—Enabled Endpoint0 is always enabled. RX Endpoint Type—Read/Write 00—Control Endpoint0 is fixed as a Control End Point. RXS RX Endpoint Stall—Read/Write 0—End Point OK. [Default] 1—End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. RXE RXT[1:0] 30.8.1.5.21 ENDPTCTRL1—ENDPTCTRL15 Address:Base + 1C0h+(4*(EndPoint Number)) Default Value:00000000h Attribute:Read/Write Size:32 bits There is an ENDPTCTRLx register for each endpoint in a device. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65 4 3 2 1 0 reserved TTT XXXR ERI TXT TT XX DS reserved RR RRR RX XX XXXR T DS ERI Figure 30-41. ENDPTCTRL1—ENDPTCTRL15—Endpoint Control 1 to 15 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-72 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (IE. Bulk-type). leaving an unconfigured endpoint control will cause undefined behavior for the data pid tracking on the active endpoint/direction. The register fields are described in the following table. Field Reserved TXE Description Reserved. These bits are reserved and should be set to zero. TX Endpoint Enable 0—Disabled [Default] 1—Enabled An Endpoint should be enabled only after it has been configured. TX Data Toggle Reset (WS) Write 1—Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID’s between the Host and device. TX Data Toggle Inhibit 0—PID Sequencing Enabled. [Default] 1—PID Sequencing Disabled. This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet. Reserved. Bit reserved and should be set to zero. TX Endpoint Type—Read/Write 00—Control 01—Isochronous 10—Bulk 11—Interrupt TX Endpoint Data Source—Read/Write 0—Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0. TX Endpoint Stall—Read/Write 0—End Point OK 1—End Point Stalled This bit will be set automatically upon receipt of a SETUP request if this Endpoint is not configured as a Control Endpoint. It will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue to returning STALL until this bit is either cleared by software or automatically cleared as above. RX Endpoint Enable 0—Disabled [Default] 1—Enabled An Endpoint should be enabled only after it has been configured. TXR TXI R TXT[1:0] TXD TXS RXE MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-73 High-Speed USB On-The-Go (HS USB-OTG) Field RXR Description RX Data Toggle Reset (WS) Write 1—Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID’s between the host and device. RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packet regardless of their data PID. RX Endpoint Type—Read/Write 00 Control 01 Isochronous 10 Bulk 11 Reserved RX Endpoint Data Sink—Read/Write—TBD 0—Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero. RX Endpoint Stall—Read/Write 0 End Point OK. [Default] 1 End Point Stalled This bit will be set automatically upon receipt of a SETUP request if this Endpoint is not configured as a Control Endpoint. It will be cleared automatically upon receipt a SETUP request if this Endpoint is configured as a Control Endpoint, Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue to returning STALL until this bit is either cleared by software or automatically cleared as above, RXI RXT[1:0] RXD RXS 30.8.1.6 30.8.1.6.1 OTG Operations Register Bits In the previous section, the Register interface has behaviors described for device mode and behaviors described for host mode. However, during OTG operations it is necessary to perform tasks independent of the controller mode. Note also from ENDPTCTRL1—ENDPTCTRL15—Endpoint Control 1 to 1542 that the only way to transition the controller mode out of host or device mode is with the controller reset bit. Therefore, it is also necessary for the OTG tasks to be performed independent of a controller reset as well as independent of the controller mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-74 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Hardware Reset or USBCMD.Reset = 1 Idle (00) Write “10” to USBMODE Write “11” to USBMODE Device (10) Host (11) Figure 30-42. Controller Mode To this end, the listed below are the register bits that are used for OTG operations, which are independent of the controller mode and are also not affected by a write to the reset bit in the USBCMD register: All Identification Registers All Device/Host Capability Registers OTGSC: All bits PORTSC: Physical Interface Select Physical Interface Serial Select Physical Interface Data Width Physical Interface Low Power Physical Interface Wake Signals Port Indicators Port Power 30.8.1.6.2 Hardware Assist The hardware assist provides automated response and sequencing that may not be possible to software with significant interrupt latency response times. The use of this additional circuitry is optional and can be used to assist the 3 sequences below. Auto-Reset When the HAAR is set to one, the host will automatically start a reset after a connect event. This shortcuts the normal process where software is notified of the connect event and starts the reset. Software will still receive notification of the connect event but should not write the reset bit when the HAAR is set. Software will be notified again after the reset is complete via the enable change bit in the PORTSC register which cause a port change interrupt. This assist will ensure the OTG parameter TB_ACON_BSE0_MAX = 1ms is met. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-75 High-Speed USB On-The-Go (HS USB-OTG) Data-Pulse Writing a one to HADP will start a data pulse of approximately 7ms in duration and then automatically cease the data pulsing. During the data pulse, the DP will be set and then cleared. This automation relieves software from accurately controlling the data-pulse duration. During the data pulse, the HCD can poll to see that the HADP and DP bit have returned low to recognize the completion or simply launch the data pulse and wait to see if a VBUS Valid interrupt occurs when the A-side supplies bus power. This assist will ensure data pulsing meets the OTG requirement of > 5ms and < 10ms. B-Disconnect to A-Connect During HNP, the B-disconnect occurs from the OTG A_suspend state and within 3 ms, the device must enable the pullup on the DP leg in the A-peripheral state. When HABA is set, the Host Controller port is in suspend mode, and the device disconnects, then this hardware assist begins. 1. Reset the OTG core. 2. Write the OTG core into device mode. 3. Write the device run bit to a 1 and enable necessary interrupts including: • USB Reset Enable (URE); enables interrupt on USB bus reset to device • Sleep Enable (SLE); enables interrupt on device suspend • Port Change Detect Enable (PCE); enables interrupt on device connect When software has enabled this hardware assist, it must not interfere during the transition and should not write any register in the core until it gets an interrupt from the device controller signifying that a reset interrupt has occurred or at least first verify that the core has entered device mode. HCD/DCD must not activate the core soft reset at any time since this action is performed by hardware. During the transition, the software may see an interrupt from the disconnect and/or other spurious interrupts (i.e. SOF/etc.) that may or may not cascade and my be cleared by the soft reset depending on the software response time. After the core has entered device mode by the hardware assist, the DCD must ensure that the ENDPTLISTADDR is programmed properly before the host sends a setup packet. Since the end of the reset duration, which may be initiated quickly (a few microseconds) after connect, will require at a minimum 50 ms, this is the time for which the DCD must be ready to accept setup packets after having received notification that the reset has been detected or simply that the OTG is in device mode which ever occurs first. In the case where the A-peripheral fails to see a reset after the controller enters device mode and engages the DP-pullup, the device controller interrupt the DCD signifying that a suspend has occurred. This assist will ensure the parameter TA_BDIS_ACON_MAX = 3ms is met. 30.8.2 Host Data Structures This section defines the interface data structures used to communicate control, status, and data between HCD (software) and the Enhanced Host Controller (hardware). The data structure definitions in this chapter support a 32-bit memory buffer address space. The interface consists of a Periodic Schedule, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-76 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Periodic Frame List, Asynchronous Schedule, Isochronous Transaction Descriptors, Split-transaction Isochronous Transfer Descriptors, Queue Heads, and Queue Element Transfer Descriptors. The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for the host controller interface. The asynchronous list is the root for all the bulk and control transfer type support. Isochronous data streams are managed using Isochronous Transaction Descriptors. Isochronous split-transaction data streams are managed with Split-transaction Isochronous Transfer Descriptors. All Interrupt, Control, and Bulk data streams are managed via queue heads and Queue Element Transfer Descriptors. These data structures are optimized to reduce the total memory footprint of the schedule and to reduce (on average) the number of memory accesses needed to execute a USB transaction. Note that software must ensure that no interface data structure reachable by the EHCI host controller spans a 4K-page boundary. The data structures defined in this section are (from the host controller’s perspective) a mix of read-only and read/writeable fields. The host controller must preserve the read-only fields on all data structure writes. 30.8.2.1 Periodic Frame List This schedule is for all periodic transfers (isochronous and interrupt). The periodic schedule is referenced from the operational registers space using the PERIODICLISTBASE address register and the FRINDEX register. The periodic schedule is based on an array of pointers called the Periodic Frame List. The PERIODICLISTBASE address register is combined with the FRINDEX register to produce a memory pointer into the frame list. The Periodic Frame List implements a sliding window of work over time. Figure 30-43. Periodic Schedule Organization 1 Split transaction Interrupt, Bulk and Control are also managed using queue heads and queue element transfer descriptors. The periodic frame list is a 4K-page aligned array of Frame List Link pointers. The length of the frame list may be programmable. The programmability of the periodic frame list is exported to system software via the HCCPARAMS register. If non-programmable, the length is 1024 elements. If programmable, the length can be selected by system software as one of 256, 512, or 1024 elements. An implementation must MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-77 High-Speed USB On-The-Go (HS USB-OTG) support all three sizes. Programming the size (that is, the number of elements) is accomplished by system software writing the appropriate value into Frame List Size field in the USBCMD register. Frame List Link pointers direct the host controller to the first work item in the frame’s periodic schedule for the current micro-frame. The link pointers are aligned on DWord boundaries within the Frame List. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Frame List Link Pointer 0 Typ 03-0 Figure 30-44. Format of Frame List Element Pointer Frame List Link pointers always reference memory objects that are 32-byte aligned. The referenced object may be an isochronous transfer descriptor for high-speed devices, a split-transaction isochronous transfer descriptor (for full-speed isochronous endpoints), or a queue head (used to support high-, full- and low-speed interrupt). System software should not place non-periodic schedule items into the periodic schedule. The least significant bits in a frame list pointer are used to key the host controller as to the type of object the pointer is referencing. The least significant bit is the T-Bit (bit 0). When this bit is set to a one, the host controller will never use the value of the frame list pointer as a physical memory pointer. The Typ field is used to indicate the exact type of data structure being referenced by this pointer. The value encodings are: Table 30-35. Typ Field Value Definitions Value 00b 01b 10b 11b Isochronous Transfer Descriptor Queue Head Meaning Split Transaction Isochronous Transfer Descriptor. Frame Span Traversal Node. 30.8.2.2 Asynchronous List Queue Head Pointer The Asynchronous Transfer List (based at the ASYNCLISTADDR register) is where all the control and bulk transfers are managed. Host controllers use this list only when it reaches the end of the periodic list, the periodic list is disabled, or the periodic list is empty. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-78 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Figure 30-45. Asynchronous Schedule Organization The Asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply pointer to the next queue head. This implements a pure round-robin service for all queue heads linked into the asynchronous list. 30.8.2.3 Isochronous (High-Speed) Transfer Descriptor (iTD) The format of an isochronous transfer descriptor is illustrated in Table 30-36. This structure is used only for high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs must be aligned on a 32-byte boundary. Table 30-36. Isochronous Transfer Descriptor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Link Pointer Status Status Status Status Status Status Status Status Transaction 0 Length Transaction 1 Length Transaction 2 Length Transaction 3 Length Transaction 4 Length Transaction 5 Length Transaction 6 Length Transaction 7 Length Buffer Pointer (Page 0) Buffer Pointer (Page 1) Buffer Pointer (Page 2) Buffer Pointer (Page 3) io io io io io io io io PG* PG* PG* PG* PG* PG* PG* PG* 0 Typ T 03-0 07-0 0B-0 0F-0 13-1 17-1 1B-1 1F-1 23-2 27-2 2B-2 Transaction 0 Offset* Transaction 1 Offset* Transaction 2 Offset* Transaction 3 Offset* Transaction 4 Offset* Transaction 5 Offset* Transaction 6 Offset* Transaction 7 Offset* EndPt I/ R Device Address Maximum Packet Size Reserved Reserved Mult 2F-2 33-3 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-79 High-Speed USB On-The-Go (HS USB-OTG) Table 30-36. Isochronous Transfer Descriptor (continued) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Buffer Pointer (Page 4) Buffer Pointer (Page 5) Buffer Pointer (Page 6) Reserved Reserved Reserved 37-3 3B-3 3F-3 Host Controller Read/Write Host Controller Read Only. Note: *Note: these fields may be modified by the host controller if the I/O field indicates an OUT. 30.8.2.3.1 Next Link Pointer Table 30-37. Next Schedule Element Pointer The first DWord of an iTD is a pointer to the next schedule data structure. Bit 31:5 Description Link Pointer (LP). These bits correspond to memory address signals [31:5], respectively. This field points to another Isochronous Transaction Descriptor (iTD/siTD) or Queue Head (QH). Reserved. These bits are reserved and their value has no effect on operation. Software should initialize this field to zero. QH/(s)iTD Select (Typ). This field indicates to the Host Controller whether the item referenced is an iTD, siTD or a QH. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings are: ValueMeaning 00b iTD (isochronous transfer descriptor) 01b QH (queue head) 10b siTD (split transaction isochronous transfer descriptor 11b FSTN (frame span traversal node) Terminate (T). 1= Link Pointer field is not valid. 0= Link Pointer field is valid. 4:3 2:1 0 30.8.2.3.2 iTD Transaction Status and Control List DWords 1 through 8 are eight slots of transaction control and status. Each transaction description includes: • Status results field • Transaction length (bytes to send for OUT transactions and bytes received for IN transactions). • Buffer offset. The PG and Transaction X Offset fields are used with the buffer pointer list to construct the starting buffer address for the transaction. The host controller uses the information in each transaction description plus the endpoint information contained in the first three DWords of the Buffer Page Pointer list, to execute a transaction on the USB. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-80 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-38. iTD Transaction Status and Control Bit 31:28 Description Status. This field records the status of the transaction executed by the host controller for this slot. This field is a bit vector with the following encoding: Bit 31 Definition Active. Set to one by software to enable the execution of an isochronous transaction by the Host Controller. When the transaction associated with this descriptor is completed, the Host Controller sets this bit to zero indicating that a transaction for this element should not be executed when it is next encountered in the schedule. Data Buffer Error. Set to a one by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). If an overrun condition occurs, no action is necessary. Babble Detected. Set to one by the Host Controller during status update when” babble” is detected during the transaction generated by this descriptor. Transaction Error (XactErr). Set to one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. 30 29 28 27:16 Transaction X Length. For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer. For an IN, the initial value of the endpoint to deliver. During the status update, the host controller writes back the field is the number of bytes the host expects the number of bytes successfully received. The value in this register is the actual byte count (for example, 0‡zero length data, 1‡one byte, 2‡two bytes, etc.). The maximum value this field may contain is 0xC00 (3072). Interrupt On Complete (IOC). If this bit is set to one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold. Page Select (PG). These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6. Transaction X Offset. This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting buffer address for this transaction. 15 14:12 11:0 30.8.2.3.3 iTD Buffer Page Pointer List (Plus) DWords 9-15 of an isochronous transaction descriptor are nominally page pointers (4K aligned) to the data buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous (relative to virtual memory), but allows the physical memory pages to be non-contiguous. Seven page MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-81 High-Speed USB On-The-Go (HS USB-OTG) pointers are provided to support the expression of eight isochronous transfers. The seven pointers allow for 3 (transactions) * 1024 (maximum packet size) * 8 (transaction records) (24576 bytes) to be moved with this data structure, regardless of the alignment offset of the first page. Since each pointer is a 4K aligned page pointer, the least significant 12 bits in several of the page pointers are used for other purposes. Table 30-39. it Buffer Pointer Page 0 (Plus) Bit 31:12 11:8 7 6:0 Description Buffer Pointer (Page 0). This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. Endpoint Number (Endpt). This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. Reserved. Bit reserved for future use and should be initialized by software to zero. Device Address. This field selects the specific device serving as the data source or sink. Table 30-40. iTD Buffer Pointer Page 1 (Plus) Bit 31:12 11 10:0 Description Buffer Pointer (Page 1). This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. Direction (I/O). 0 = OUT; 1 = IN. This field encodes whether the high-speed transaction should use an IN or OUT PID. Maximum Packet Size. This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). This field is used for high-bandwidth endpoints where more than one transaction is issued per transaction description (for example, per micro-frame). This field is used with the Multi field to support high-bandwidth pipes. This field is also used for all IN transfers to detect packet babble. Software should not set a value larger than 1024 (400h). Any value larger yields undefined results. Table 30-41. iTD Buffer Pointer Page 2 (Plus) Bit 31:12 Description Buffer Pointer. This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-82 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Bit 11:2 1:0 Description Reserved. This bit reserved for future use and should be set to zero. Multi. This field is used to indicate to the host controller the number of transactions that should be executed per transaction description (for example, per micro-frame). The valid values are: ValueMeaning 00bReserved. A zero in this field yields undefined results. 01bOne transaction to be issued for this endpoint per microframe 10bTwo transactions to be issued for this endpoint per microframe 11bThree transactions to be issued for this endpoint per micro-frame Table 30-42. iTD Buffer Pointer Page 3-6 Bit 31:12 11:0 Description Buffer Pointer. This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. Reserved. These bits reserved for future use and should be set to zero. 30.8.2.4 Split Transaction Isochronous Transfer Descriptor (siTD) All Full-speed isochronous transfers through the internal transaction translator are managed using the siTD data structure. This data structure satisfies the operational requirements for managing the split transaction protocol. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 Next Link Pointer I/O Port Number R Reserved ioc P Reserved Total Bytes to Transfer Buffer Pointer (Page 0) Buffer Pointer (Page 1) Back Pointer Hub Addr R EndPt 0 Typ T 03-0 07-0 0B-0 0F-0 13-1 T-cou 0 17-1 R Device Address µFrame S-mask Status Current Offset µFrame C-mask µFrame C-prog-mask Reserved TP T 1B-1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-83 High-Speed USB On-The-Go (HS USB-OTG) Host Controller Read/Write Host Controller Read Only. Figure 30-46. Split-Transaction Isochronous Transaction Descriptor (siTD) 30.8.2.4.1 Next Link Pointer Table 30-43. Next Link Pointer DWord0 of a siTD is a pointer to the next schedule data structure. Bit 31:5 Description Next Link Pointer (LP). This field contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively. Reserved. These bits must be written as zeros. QH/(s)iTD Select (Typ). This field indicates to the Host Controller whether the item referenced is an iTD/siTD or a QH. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings are: ValueMeaning 00biTD (isochronous transfer descriptor) 01bQH (queue head) 10bsiTD (split transaction isochronous transfer descriptor 11bFSTN (frame span traversal node) Terminate (T). 1=Link Pointer field is not valid. 0=Link Pointer is valid. 4:3 2:1 0 30.8.2.4.2 siTD Endpoint Capabilities/Characteristics DWords 1 and 2 specify static information about the full-speed endpoint, the addressing of the parent Companion Controller, and micro-frame scheduling control. Table 30-44. Endpoint and Transaction Translator Characteristics Bit 31 30:24 23 22:16 15:12 11:8 Description Direction (I/O).0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. Port Number. This field is the port number of the recipient Transaction Translator. Reserved. Bit reserved and should be set to zero. Hub Address. This field holds the device address of the Companion Controllers’ hub. Reserved. Field reserved and should be set to zero. Endpoint Number (Endpt). This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-84 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Bit 7 6:0 Description Reserved. Bit is reserved for future use. It should be set to zero. Device Address. This field selects the specific device serving as the data source or sink. Table 30-45. Micro-frame Schedule Control Bit 31:16 15:8 Description Reserved. This field reserved for future use. It should be set to zero. Split Completion Mask (µFrame C-Mask). This field (along with the Active and SplitX- state fields in the Status byte) is used to determine during which micro-frames the host controller should execute complete-split transactions. When the criteria for using this field is met, an all zeros value has undefined behavior. The host controller uses the value of the three low-order bits of the FRINDEX register to index into this bit field. If the FRINDEX register value indexes to a position where the µFrame C-Mask field is a one, then this siTD is a candidate for transaction execution. There may be more than one bit in this mask set. Split Start Mask (µFrame S-mask). This field (along with the Active and SplitX-state fields in the Status byte) is used to determine during which micro-frames the host controller should execute start-split transactions. The host controller uses the value of the three low-order bits of the FRINDEX register to index into this bit field. If the FRINDEX register value indexes to a position where the µFrame S-mask field is a one, then this siTD is a candidate for transaction execution. An all zeros value in this field, in combination with existing periodic frame list has undefined results. 7:0 30.8.2.4.3 siTD Transfer State Table 30-46. siTD Transfer Status and Control DWords 3-6 are used to manage the state of the transfer. Bit 31 Description Interrupt On Complete (ioc). 0 = Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete. When the host controller determines that the split transaction has completed it will assert a hardware interrupt at the next interrupt threshold. Page Select (P). Used to indicate which data page pointer should be concatenated with the CurrentOffset field to construct a data buffer pointer (0 selects Page 0 pointer and 1 selects Page 1). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a one to a zero). Reserved. This field reserved for future use and should be set to zero. Total Bytes To Transfer. This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 (3FFh) 30 29:26 25:16 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-85 High-Speed USB On-The-Go (HS USB-OTG) Bit 15:8 7:0 Description µFrame Complete-split Progress Mask (C-prog-Mask). This field is used by the host controller to record which split-completes has been executed. Status. This field records the status of the transaction executed by the host controller for this slot. This field is a bit vector with the following encoding: Bit 7 6 5 Definition Active. Set to one by software to enable the execution of an isochronous split transaction by the Host Controller. ERR. Set to a one by the Host Controller when an ERR response is received from the Companion Controller. Data Buffer Error. Set to a one by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). In the case of an under run, the Host Controller will transmit an incorrect CRC (thus invalidating the data at the endpoint). If an overrun condition occurs, no action is necessary. Babble Detected. Set to a one by the Host Controller during status update when” babble” is detected during the transaction generated by this descriptor. Transaction Error (XactErr). Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit will only be set for IN transactions. Missed Micro-Frame. The host controller detected that a host-induced holdoff caused the host controller to miss a required complete-split transaction. Split Transaction State (SplitXstate). The bit encodings are: ValueMeaning 00bDo Start Split. This value directs the host controller to issue a Start split transaction to the endpoint when a match is encountered in the S-mask. 01bDo Complete Split. This value directs the host controller to issue a Complete split transaction to the endpoint when a match is encountered in the C-mask. Reserved. Bit reserved for future use and should be set to zero. 4 3 2 1 0 30.8.2.4.4 siTD Buffer Pointer List (plus) DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page cross. The most significant 20 bits of each DWord in this section are the 4K (page) aligned buffer pointers. The least significant 12 bits of each DWord are used as additional transfer state. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-86 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-47. Buffer Page Pointer List (plus) Bit 31:12 Description Buffer Pointer List. Bits [31:12] of DWords 4 and 5 are 4K paged aligned, physical memory addresses. These bits correspond to physical address bits [31:12] respectively. The lower 12 bits in each pointer are defined and used as specified below. The field P specifies the current active pointer Page 0: Current Offset. The 12 least significant bits of the Page 0 pointer is the current byte offset for the current page pointer (as selected with the page indicator bit (P field)). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a one to a zero). The least significant bits of Page 1 pointer is split into three sub-fields Page 1: Bits 11:5 4:3 Reserved. Transaction position (TP). This field is used with T-count to determine whether to send all, first, middle, or last with each outbound transaction payload. System software must initialize this field with the appropriate starting value. The host controller must correctly manage this state during the lifetime of the transfer. The bit encodings are: Value Meaning 00b All. The entire full-speed transaction data payload is in this transaction (that is, less than or equal to 188 bytes). 01b Begin. This is the first data payload for a full-speed that is greater than 188 bytes.transaction 10B Mid. This is the middle payload for a full-speed OUT transaction that is larger than 188 bytes. 11b End. This is the last payload for a full-speed OUT transaction that was larger than 188 bytes. 11:0 Description 2:0 Transaction count (T-Count). Software initializes this field with the number of OUT start-splits this transfer requires. Any value larger than 6 is undefined. 30.8.2.4.5 siTD Back Link Pointer DWord 6 of a siTD is simply another schedule link pointer. This pointer is always zero, or references a siTD. This pointer cannot reference any other schedule data structure. Table 30-48. siTD Back Link Pointer Bit 31:5 4:1 0 Description siTD Back Pointer. This field is a physical memory pointer to a siTD. Reserved. This field is reserved for future use. It should be set to zero. Terminate (T). 1 = siTD Back Pointer field is not valid. 0 = siTD Back Pointer field is valid. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-87 High-Speed USB On-The-Go (HS USB-OTG) 30.8.2.5 Queue Element Transfer Descriptor (qTD) This data structure is only used with a queue head. This data structure is used for one or more USB transactions. This data structure is used to transfer up to 20480 (5*4096) bytes. The structure contains two structure pointers used for queue advancement, a DWord of transfer state, and a five-element array of data buffer pointers. This structure is 32 bytes (or one 32-byte cache line). This data structure must be physically contiguous. The buffer associated with this transfer must be virtually contiguous. The buffer may start on any byte boundary. A separate buffer pointer list element must be used for each physical page in the buffer, regardless of whether the buffer is physically contiguous. Host controller updates (host controller writes) to stand-alone qTDs only occur during transfer retirement. References in the following bit field definitions of updates to the qTD are to the qTD portion of a queue head. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next qTD Pointer Alternate Next qTD Pointer dt Total Bytes to Transfer Buffer Pointer (page 0) Buffer Pointer (page 0) Buffer Pointer (page 0) Buffer Pointer (page 0) Buffer Pointer (page 0) io C_Page Cerr PI 0 0 Status T 03-0 T 07-0 0B-0 0F-0 13-1 17-1 1B-1 1F-1 Current Offset Reserved Reserved Reserved Reserved Host Controller Read/Write Host Controller Read Only. Figure 30-47. Queue Element Transfer Descriptor Block Diagram Queue Element Transfer Descriptors must be aligned on 32-byte boundaries. 30.8.2.5.1 Next qTD Pointer The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-88 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-49. D Next Element Transfer Pointer (DWord 0) Bit 31:5 Description Next Transfer Element Pointer. This field contains the physical memory address of the next qTD to be processed. The field corresponds to memory address signals[31:5], respectively. Reserved. These bits are reserved and their value has no effect on operation. Terminate (T). 1= pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates to the Host Controller that there are no more valid entries in the queue. 4:1 0 30.8.2.5.2 Alternate Next qTD Pointer The second DWord of a queue element transfer descriptor is used to support hardware-only advance of the data stream to the next client buffer on short packet. To be more explicit the host controller will always use this pointer when the current qTD is retired due to short packet. Table 30-50. TD Alternate Next Element Transfer Pointer (DWord 1) Bit 31:5 Description Alternate Next Transfer Element Pointer. This field contains the physical memory address of the next qTD to be processed in the event that the current qTD execution encounters a short packet (for an IN transaction). The field corresponds to memory address signals [31:5], respectively. Reserved. These bits are reserved and their value has no effect on operation. Terminate (T). 1= pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates to the Host Controller that there are no more valid entries in the queue. 4:1 0 30.8.2.5.3 qTD Token The third DWord of a queue element transfer descriptor contains most of the information the host controller requires to execute a USB transaction (the remaining endpoint-addressing information is specified in the queue head). NOTE The field descriptions forward reference fields defined in the queue head. Where necessary, these forward references are preceded with a QH notation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-89 High-Speed USB On-The-Go (HS USB-OTG) Table 30-51. qTD Token (DWord 2) Bit 31 30:16 Description Data Toggle. This is the data toggle sequence bit. The use of this bit depends on the setting of the Data Toggle Control bit in the queue head. Total Bytes to Transfer. This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction, only on the successful completion of the transaction. The maximum value software may store in this field is 5 * 4K (5000H). This is the maximum number of bytes 5 page pointers can access. If the value of this field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the host controller executes a zero-length transaction and retires the transfer descriptor. It is not a requirement for OUT transfers that Total Bytes To Transfer be an even multiple of QHD.Maximum Packet Length. If software builds such a transfer descriptor for an OUT transfer, the last transaction will always be less than QHD.Maximum Packet Length. Although it is possible to create a transfer up to 20K this assumes the 1st offset into the first page is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16K**. Therefore, the maximum recommended transfer is 16K(4000H). Interrupt On Complete (IOC). If this bit is set to a one, it specifies that when this qTD is completed, the Host Controller should issue an interrupt at the next interrupt threshold. Current Page (C_Page). This field is used as an index into the qTD buffer pointer list. Valid values are in the range 0H to 4H. The host controller is not required to write this field back when the qTD is retired. Error Counter (CERR). This field is a 2-bit down counter that keeps track of the number of consecutive Errors detected while executing this qTD. If this field is programmed with a non-zero value during set-up, the Host Controller decrements the count and writes it back to the qTD if the transaction fails. If the counter counts from one to zero, the Host Controller marks the qTD inactive, sets the Halted bit to a one, and error status bit for the error that caused CERR to decrement to zero. An interrupt will be generated if the USB Error Interrupt Enable bit in the USBINTR register is set to a one. If HCD programs this field to zero during set-up, the Host Controller will not count errors for this qTD and there will be no limit on the retries of this qTD. Note that write-backs of intermediate execution state are to the queue head overlay area, not the qTD. Error Decrement Counter Transaction Error Yes Data Buffer Error No3 Stalled No1 Babble Detected No1 No Error No2 Error 1 Decrement Counter Error Decrement Counter Detection of Babble or Stall automatically halts the queue head. Thus, count is not decremented 15 14:12 11:10 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-90 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Bit 2 Description If the EPS field indicates a HS device or the queue head is in the Asynchronous Schedule (and PIDCode indicates an IN or OUT) and a bus transaction completes and the host controller does not detect a transaction error, then the host controller should reset CERR to extend the total number of errors for this transaction. For example, CERR should be reset with maximum value (3) on each successful completion of a transaction. The host controller must never reset this field if the value at the start of the transaction is 00b. See section Split Transaction Execution State Machine for Interrupt for CERR adjustment rules when the EPS field indicates a FS or LS device and the queue head is in the Periodic Schedule. See section Asynchronous - Do Complete Split for CERR adjustment rules when the EPS field indicates a FS or LS device, the queue head is in the Asynchronous schedule and the PIDCode indicates a SETUP. Data buffer errors are host problems. They don't count against the device's retries. 3 Note: Software must not program CERR to a value of zero when the EPS field is programmed with a value indicating a Full- or Low-speed device. This combination could result in undefined behavior. 9:8 PID Code. This field is an encoding of the token, which should be used for transactions associated with this transfer descriptor. Encodings are: 00b 01b 10b OUT Token generates token (E1H) IN Token generates token (69H) SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt the queue head is non-zero.) transfer type, for example, µFrame S-mask field in Reserved 11b 7:0 Status. This field is used by the Host Controller to communicate individual command execution states back to HCD. This field contains the status of the last transaction performed on this qTD. The bit encodings are: Bit 7 6 Status Field Description Active. Set to one by software to enable the execution of transactions by the Host Controller. Halted. Set to a one by the Host Controller during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the error counter counting down to zero, or reception of the STALL handshake from the device during a transaction. Any time that a transaction results in the Halted bit being set to a one, the Active bit is also set to zero. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-91 High-Speed USB On-The-Go (HS USB-OTG) Bit 5 Description Data Buffer Error. Set to a one by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). If an overrun condition occurs, the Host Controller will force a timeout condition on the USB, invalidating the transaction at the source. If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. Babble Detected. Set to a one by the Host Controller during status update when” babble” is detected during the transaction. In addition to setting this bit, the Host Controller also sets the Halted bit to a one. Since “babble” is considered a fatal error for the transfer, setting the Halted bit to a one insures that no more transactions occur because of this descriptor. Transaction Error (XactErr). Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. Missed Micro-Frame. This bit is ignored unless the QH.EPS field indicates a full- or low-speed endpoint and the queue head is in the periodic list. This bit is set when the host controller detected that a host-induced hold-off caused the host controller to miss a required complete-split transaction. If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. 4 3 2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-92 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Bit 1 Description Split Transaction State (SplitXstate). This bit is ignored by the host controller unless the QH.EPS field indicates a full- or low-speed endpoint. When a Full- or Low-speed device, the host controller uses this bit to track the state of the split- transaction. The functional requirements of the host controller for managing this state bit and the split transaction protocol depends on whether the endpoint is in the periodic or asynchronous schedule. The bit encodings are: ValueMeaning 0b Do Start Split. This value directs the host controller to issue a Start split transaction to the endpoint. 1b Do Complete Split. This value directs the host controller to issue a Complete split transaction to the endpoint. Ping State (P)/ERR. If the QH.EPS field indicates a High-speed device and the PID_Code indicates an OUT endpoint, then this is the state bit for the Ping protocol. The bit encodings are: ValueMeaning 0b Do OUT. This value directs the host controller to issue an OUT PID to the endpoint. 1b Do Ping. This value directs the host controller to issue a PING PID to the endpoint. If the QH.EPS field does not indicate a High-speed device, then this field is used as an error indicator bit. It is set to a one by the host controller whenever a periodic split-transaction receives an ERR handshake. 0 30.8.2.5.4 qTD Buffer Page Pointer List The last five DWords of a queue element transfer descriptor is an array of physical memory address pointers. These pointers reference the individual pages of a data buffer. System software initializes Current Offset field to the starting offset into the current page, where current page is selected via the value in the C_Page field. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-93 High-Speed USB On-The-Go (HS USB-OTG) Table 30-52. qTD Buffer Pointer(s) (DWords 3-7) Bit 31:12 Description Buffer Pointer List. Each element in the list is a 4K page aligned physical memory address. The lower 12 bits in each pointer are reserved (except for the first one), as each memory pointer must reference the start of a 4K page. The field C_Page specifies the current active pointer. When the transfer element descriptor is fetched, the starting buffer address is selected using C_Page (similar to an array index to select an array element). If a transaction spans a 4K buffer boundary, the host controller must detect the page-span boundary in the data stream, increment C_Page and advance to the next buffer pointer in the list, and conclude the transaction via the new buffer pointer. Current Offset (Reserved). This field is reserved in all pointers except the first one (for example, Page 0). The host controller should ignore all reserved bits. For the page 0 current offset interpretation, this field is the byte offset into the current page (as selected by C_Page). The host controller is not required to write this field back when the qTD is retired. Software should ensure the Reserved fields are initialized to zeros. 11:0 30.8.2.6 Queue Head 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Queue Head Horizontal Link Pointer RL Mult C Maximum Packet Length Hub Addr* Current qTD Pointer Next qTD Pointer Alternate Next qTD pointer dt Total Bytes to Transfer Buffer Pointer (Page 0) Buffer Pointer (Page 1) Buffer Pointer (Page 2) Buffer Pointer (Page 3) Buffer Pointer (Page 4) io C_Page Cerr PI H dt EP EndPt I 0 Typ T 03-0 07-0 0B-0 0F-0 T 13-1 T 17-1 1B-1 1F-1 23-2 Device Address µFrame S-mask* 0 0 Nak Status Port Number* µFrame C-mask* Current Offset Reserved S-bytes* Reserved Reserved C-prog-mask* FrameTa 27-2 2B-2 2F-2 Transfer OverlayTransfer Results MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-94 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Static Endpoint State *These fields are used exclusively to support split transactions to USB 2.0 Hubs Host Controller Read/Write Host Controller Read Only. Figure 30-48. Queue Head Structure Layout Queue Head Horizontal Link Pointer The first DWord of a Queue Head contains a link pointer to the next data object to be processed after any required processing in this queue has been completed, as well as the control bits defined below. This pointer may reference a queue head or one of the isochronous transfer descriptors. It must not reference a queue element transfer descriptor. Table 30-53. Queue Head DWord 0 Bit 31:5 Description Queue Head Horizontal Link Pointer (QHLP). This field contains the address of the next data object to be processed in the horizontal list and corresponds to memory address signals [31:5], respectively. Reserved. These bits must be written as zeros. QH/(s)iTD Select (Typ). This field indicates to the hardware whether the item referenced by the link pointer is an iTD, siTD or a QH. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings are: ValueMeaning 00b iTD (isochronous transfer descriptor) 01b QH (queue head) 10b siTD (split transaction isochronous transfer descriptor) 11b FSTN (frame span traversal node) Terminate (T). 1=Last QH (pointer is invalid). 0=Pointer is valid. If the queue head is in the context of the periodic list, a one bit in this field indicates to the host controller that this is the end of the periodic list. This bit is ignored by the host controller when the queue head is in the Asynchronous schedule. Software must ensure that queue heads reachable by the host controller always have valid horizontal link pointers. 4:3 2:1 0 30.8.2.6.1 Endpoint Capabilities/Characteristics The second and third DWords of a Queue Head specifies static information about the endpoint. This information does not change over the lifetime of the endpoint. There are three types of information in this region: • Endpoint Characteristics. These are the USB endpoint characteristics including addressing, maximum packet size, and endpoint speed. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-95 High-Speed USB On-The-Go (HS USB-OTG) • • Endpoint Capabilities. These are adjustable parameters of the endpoint. They effect how the endpoint data stream is managed by the host controller. Split Transaction Characteristics. This data structure is used to manage full- and low-speed data streams for bulk, control, and interrupt via split transactions to USB2.0 Hub Transaction Translator. There are additional fields used for addressing the hub and scheduling the protocol transactions (for periodic). Table 30-54. Endpoint Characteristics: Queue Head DWord 1 The host controller must not modify the bits in this region. Bit 31:28 27 Description Nak Count Reload (RL). This field contains a value, which is used by the host controller to reload the Nak Counter field. Control Endpoint Flag (C). If the QH.EPS field indicates the endpoint is not a high-speed device, and the endpoint is a control endpoint, then software must set this bit to a one. Otherwise, it should always set this bit to a zero. Maximum Packet Length. This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). The maximum value this field may contain is 0x400 (1024). Head of Reclamation List Flag (H). This bit is set by System Software to mark a queue head as being the head of the reclamation list. Data Toggle Control (DTC). This bit specifies where the host controller should get the initial data toggle on an overlay transition. 0b Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head. 1b Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the queue head from the DT bit in the qTD. Endpoint Speed (EPS). This is the speed of the associated endpoint. Bit combinations are: Value 00b 01b 10b 11b Meaning Full-Speed (12Mbs) Low-Speed (1.5Mbs) High-Speed (480 Mb/s) Reserved 26:16 15 14 13:12 This field must not be modified by the host controller. 11:8 Endpoint Number (Endpt). This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-96 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Bit 7 Description Inactivate on Next Transaction (I). This bit is used by system software to request that the host controller set the Active bit to zero. See Section Rebalancing the Periodic Schedule for full operational details. This field is only valid when the queue head is in the Periodic Schedule and the EPS field indicates a Full or Low-speed endpoint. Setting this bit to a one when the queue head is in the Asynchronous Schedule or the EPS field indicates a high-speed device yields undefined results. Device Address. This field selects the specific device serving as the data source or sink. 6:0 Table 30-55. Endpoint Capabilities: Queue Head DWord 2 Bit 31:30 Description High-Bandwidth Pipe Multiplier (Mult). This field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. The host controller makes the simplifying assumption that software properly initializes this field (regardless of location of queue head in the schedules or other run time parameters). The valid values are: ValueMeaning 00b Reserved. A zero in this field yields undefined results. 01b One transaction to be issued for this endpoint per micro-frame 10b Two transactions to be issued for this endpoint per micro-frame 11b Three transactions to be issued for this endpoint per micro-frame Port Number. This field is ignored by the host controller unless the EPS field indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addr below), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. Hub Addr. This field is ignored by the host controller unless the EPS field indicates a full-or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. 29:23 22:16 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-97 High-Speed USB On-The-Go (HS USB-OTG) Bit 15:8 Description Split Completion Mask (µFrame C-Mask). This field is ignored by the host controller unless the EPS field indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Active and SplitX-state fields) is used to determine during which micro-frames the host controller should execute a complete-split transaction. When the criteria for using this field are met, a zero value in this field has undefined behavior. This field is used by the host controller to match against the three low-order bits of the FRINDEX register. If the FRINDEX register bits decode to a position where the µFrame C- Mask field is a one, then this queue head is a candidate for transaction execution. There may be more than one bit in this mask set. Interrupt Schedule Mask (µFrame S-mask). This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint. The host controller uses the value of the three low-order bits of the FRINDEX register as an index into a bit position in this bit vector. If the µFrame S-mask field has a one at the indexed bit position then this queue head is a candidate for transaction execution. If the EPS field indicates the endpoint is a high-speed endpoint, then the transaction executed is determined by the PID_Code field contained in the execution area. This field is also used to support split transaction types: Interrupt (IN/OUT). This condition is true when this field is non-zero and the EPS field indicates this is either a full- or low-speed device. A zero value in this field, in combination with existing in the periodic frame list has undefined results. 7:0 30.8.2.6.2 Transfer Overlay The nine DWords in this area represent a transaction working space for the host controller. The general operational model is that the host controller can detect whether the overlay area contains a description of an active transfer. If it does not contain an active transfer, then it follows the Queue Head Horizontal Link Pointer to the next queue head. The host controller will never follow the Next Transfer Queue Element or Alternate Queue Element pointers unless it is actively attempting to advance the queue. For the duration of the transfer, the host controller keeps the incremental status of the transfer in the overlay area. When the transfer is complete, the results are written back to the original queue element. The DWord3 of a Queue Head contains a pointer to the source qTD currently associated with the overlay. The host controller uses this pointer to write back the overlay area into the source qTD after the transfer is complete. Table 30-56. Current qTD Link Pointer Bit 31:5 Description Current Element Transaction Descriptor Link Pointer. This field contains the address Of the current transaction being processed in this queue and corresponds to memory address signals [31:5], respectively. Reserved (R). These bits are ignored by the host controller when using the value as an address to write data. The actual value may vary depending on the usage. 4:0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-98 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) The DWords 4-11 of a queue head are the transaction overlay area. This area has the same base structure as a Queue Element Transfer Descriptor. The queue head utilizes the reserved fields of the page pointers to implement tracking the state of split transactions. This area is characterized as an overlay because when the queue is advanced to the next queue element, the source queue element is merged onto this area. This area serves an execution cache for the transfer. Table 30-57. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8 and 9) DWord 5 Bit 4:1 Description Nak Counter (NakCnt)µRW. This field is a counter the host controller decrements whenever a transaction for the endpoint associated with this queue head results in a Nak or Nyet response. This counter is reloaded from RL before a transaction is executed during the first pass of the reclamation list (relative to an Asynchronous List Restart condition). It is also loaded from RL during an overlay. Data Toggle. The Data Toggle Control controls whether the host controller preserves this bit when an overlay operation is performed. Interrupt On Complete (IOC). The IOC control bit is always inherited from the source qTD when the overlay operation is performed. Error Counter (C_ERR). This two-bit field is copied from the qTD during the overlay and written back during queue advancement. Ping State (P)/ERR. If the EPS field indicates a high-speed endpoint, then this field should be preserved during the overlay operation. Split-transaction Complete-split Progress (C-prog-mask). This field is initialized to zero during any overlay. This field is used to track the progress of an interrupt split-transaction. Split-transaction Frame Tag (Frame Tag). This field is initialized to zero during any overlay. This field is used to track the progress of an interrupt split-transaction. S-bytes. Software must ensure that the S-bytes field in a qTD is zero before activating the qTD. This field is used to keep track of the number of bytes sent or received during an IN or OUT split transaction. 6 6 6 6 8 31 15 11:10 0 7:0 9 4:0 9 11:5 30.8.2.7 Periodic Frame Span Traversal Node (FSTN) This data structure is to be used only for managing Full- and Low-speed transactions that span a Host-frame boundary. See section Host Controller Operational Model for FSTNs for full operational details. Software must not use an FSTN in the Asynchronous Schedule. An FSTN in the Asynchronous schedule results in undefined behavior. Software must not use the FSTN feature with a host controller whose HCIVERSION register indicates a revision implementation below 0096h. FSTNs are not defined for implementations before 0.96 and their use will yield undefined results. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-99 High-Speed USB On-The-Go (HS USB-OTG) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Normal Path Link Pointer Back Path Link Pointer 0 0 Typ T 03-0 Typ T 07-0 Host Controller Read/Write Host Controller Read Only. Figure 30-49. Frame Span Traversal Node Structure Layout 30.8.2.7.1 FSTN Normal Path Pointer The first DWord of an FSTN contains a link pointer to the next schedule object. This object can be of any valid periodic schedule data type. Bit 31:5 Description Normal Path Link Pointer (NPLP). This field contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively. Reserved. These bits must be written as 0s. QH/(s)iTD/FSTN Select (Typ). This field indicates to the Host Controller whether the item referenced is a iTD/siTD, a QH or an FSTN. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings are: ValueMeaning 00biTD (isochronous transfer descriptor) 01bQH (queue head) 10bsiTD (split transaction isochronous transfer descriptor) 11bFSTN (Frame Span Traversal Node) Terminate (T). 1=Link Pointer field is not valid. 0=Link Pointer is valid. 4:3 2:1 0 30.8.2.7.2 FSTN Back Path Link Pointer The second DWord of an FTSN node contains a link pointer to a queue head. If the T-bit in this pointer is a zero, then this FSTN is a Save-Place indicator. Its Typ field must be set by software to indicate the target data structure is a queue head. If the T-bit in this pointer is set to a one, then this FSTN is the Restore indicator. When the T-bit is a one, the host controller ignores the Typ field. Bit 31:5 4:3 Description Back Path Link Pointer (BPLP). This field contains the address of a Queue Head. This field corresponds to memory address signals [31:5], respectively. Reserved. These bits must be written as 0s. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-100 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Bit 2:1 0 Description Typ. Software must ensure this field is set to indicate the target data structure is a Queue Head. Any other value in this field yields undefined results. Terminate (T). 1=Link Pointer field is not valid (that is, the host controller must not use bits [31:5] (in combination with the CTRLDSSEGMENT register if applicable) as a valid memory address). This value also indicates that this FSTN is a Restore indicator. 0=Link Pointer is valid (that is, the host controller may use bits [31:5] (in combination with the CTRLDSSEGMENT register if applicable) as a valid memory address). This value also indicates that this FSTN is a Save-Place indicator. 30.8.3 Host Operational Model The general operational model is for the enhanced interface host controller hardware and enhanced interface host controller driver (generally referred to as system software). Each significant operational feature of the EHCI host controller is discussed in a separate section. Each section presents the operational model requirements for the host controller hardware. Where appropriate, recommended system software operational models for features are also presented. 30.8.3.1 Host Controller Initialization When the system boots, the host controller is enumerated, assigned a base address for the register space and BIOS sets the FLADJ register to a system-specific value. After initial power-on or HCReset (hardware or via HCReset bit in the USBCMD register), all of the operational registers will be at their default values, as illustrated in Table 30-58. After a hardware reset, only the operational registers not contained in the Auxiliary power well will be at their default values. Table 30-58. Default Values of Operational Register Space Operational Register USBCMD USBSTS USBINTR FRINDEX CTRLDSSEGMENT PERIODICLISTBASE ASYNCLISTADDR CONFIGFLAG PORTSC Default Value (after Reset) 00080000h (00080B00h if Asynchronous Schedule Park Capability is a one) 00001000h 00000000h 00000000h 00000000h Undefined Undefined 00000000h 00002000h (w/PPC set to one); 00003000h (w/PPC set to a zero) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-101 High-Speed USB On-The-Go (HS USB-OTG) In order to initialize the host controller, software should perform the following steps • Program the CTRLDSSEGMENT register with 4-Gigabyte segment where all of the interface data structures are allocated. • Write the appropriate value to the USBINTR register to enable the appropriate interrupts. • Write the base address of the Periodic Frame List to the PERIODICLIST BASE register. If there are no work items in the periodic schedule, all elements of the Periodic Frame List should have their T-Bits set to a one. • Write the USBCMD register to set the desired interrupt threshold, frame list size (if applicable) and turn the host controller ON via setting the Run/Stop bit. • Write a 1 to CONFIGFLAG register to route all ports to the EHCI controller (see Section Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved, depending on the intended operation. ). At this point, the host controller is up and running and the port registers will begin reporting device connects, etc. System software can enumerate a port through the reset process (where the port is in the enabled state). At this point, the port is active with SOFs occurring down the enabled port enabled High-speed ports, but the schedules have not yet been enabled. The EHCI Host controller will not transmit SOFs to enabled Full- or Low-speed ports. In order to communicate with devices via the asynchronous schedule, system software must write the ASYNDLISTADDR register with the address of a control or bulk queue head. Software must then enable the asynchronous schedule by writing a one to the Asynchronous Schedule Enable bit in the USBCMD register. In order to communicate with devices via the periodic schedule, system software must enable the periodic schedule by writing a one to the Periodic Schedule Enable bit in the USBCMD register. Note that the schedules can be turned on before the first port is reset (and enabled). Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved, depending on the intended operation. 30.8.3.2 Port Routing and Control A USB 2.0 Host controller is comprised of one high-speed host controller, which implements the EHCI programming interface and 0 to N USB 1.1 companion host controllers. Companion host controllers (cHCs) may be implementations of either Universal or Open host controller specifications. This configuration is used to deliver the required full USB 2.0-defined port capability; for example, Low-, Full-, and High-speed capability for every port. Figure 30-50 illustrates a simple block diagram of the port routing logic and its relationship to the high-speed and companion host controllers within a USB 2.0 host controller. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-102 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Figure 30-50. Example USB 2.0 Host Controller Port Routing Block Diagram There exists one transceiver per physical port and each host controller module has its own port status and control registers. The EHCI controller has port status and control registers for every port. Each companion host controller has only the port control and status registers it is required to operate. Each transceiver can be controlled by either the EHCI host controller or one companion host controller. Routing logic lies between the transceiver and the port status and control registers.1 The port routing logic is controlled from signals originating in the EHCI host controller. The EHCI host controller has a global routing policy control field and per-port ownership control fields. The Configured Flag (CF) bit (defined in section BURSTSIZE) is the global routing policy control. At power-on or reset, the default routing policy is to the companion controllers (if they exist). If the system does not include a driver for the EHCI host controller and the host controller includes Companion Controllers, then the ports will still work in Full- and Low-speed mode (assuming the system includes a driver for the companion controllers). In general, when the EHCI owns the ports, the companion host controllers' port registers do not see a connect indication from the transceiver. Similarly, when a companion host controller owns a port, the EHCI controller's port registers do not see a connect indication from the transceiver. The details on the rules for the port routing logic are described in the following sections. The USB 2.0 host controller must be implemented as a multi-function PCI device if the implementation includes companion controllers. The companion host controllers’ function numbers must be less than the EHCI host controller function number. The EHCI host controller must be a larger function number with respect to the companion host controllers associated with this EHCI host controller. If a PCI device implementation contains only an EHCI controller (that is, no companion controllers or other PCI functions), then the EHCI host controller must be function zero, in accordance with the PCI Specification. The N_CC field in the Structural Parameter register (HCSPARAMS) indicates whether the controller implementation includes companion host controllers. When N_CC has a non-zero value there exists companion host controllers. If N_CC has a value of zero, then the host controller implementation does not include companion host controllers. If the host controller root ports are exposed to attachment of full- or low-speed devices, the ports will always fail the high-speed chirp during reset and the ports will not be enabled. System software can notify the user of the illegal condition. This type of implementation requires a USB 2.0 hub be connected to a root port to provide full and low-speed device connectivity. 1.The routing logic should not be implemented in the 480 MHz clock domain of the transceiver. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-103 High-Speed USB On-The-Go (HS USB-OTG) System software uses information in the host controller capability registers to determine how the ports are routed to the companion host controllers. See Section HCSPARAMS—EHCI Compliant with extensions.1 30.8.3.2.1 Port Routing Control via EHCI Configured (CF) Bit Each port in the USB 2.0 host controller can be routed either to a single companion host controller or to the EHCI host controller. The port routing logic is controlled by two mechanisms in the EHCI HC: a host controller global flag and per-port control. The Configured Flag (CF) bit (defined in Section BURSTSIZE), is used to globally set the policy of the routing logic. Each port register has a Port Owner control bit which allows the EHCI Driver to explicitly control the routing of individual ports. Whenever the CF bit transitions from a zero to a one (this transition is only available under program control) the port routing unconditionally routes all of the port registers to the EHCI HC (all Port Owner bits go to zero). While the CF-bit is a one, the EHCI Driver can control individual ports' routing via the Port Owner control bit. Likewise, whenever the CF bit transitions from a one to a zero (as a result of Aux power application, HCRESET, or software writing a zero to CF-bit), the port routing unconditionally routes all of the port registers to the appropriate companion HC. The default value for the EHCI HC’s CF bit (after Aux power application or HCRESET) is zero. Table 30-59 summarizes the default routing for all the ports, based on the value of the EHCI HC’s CF bit. The view of the port depends on the current owner. A Universal or Open companion host controller will see port register bits consistent with the appropriate specification. Port bit definitions that are required for EHCI host controllers are not visible to companion host controllers. Table 30-59. Default Port Routing Depending on EHCI HC CF Bit HS CF Bit 0B Default Port Ownership Companion HCs Explanation The companion host controllers own the ports and only Fulland Low-speed devices are supported in the system. The exact port assignments are implementation dependent. The ports behave only as Full- and Low-speed ports in this configuration The EHCI host controller has default ownership over all of the ports. The routing logic inhibits device connect events from reaching the companion HCs' port status and control registers when the port owner is the EHCI HC.The EHCI HC has access to the additional port status and control bits defined in this specification (see Section PORTSCx). The EHCI HC can temporarily release control of the port to a companion HC by setting the PortOwner bit in the PORTSC register to a one. 1B EHCI HC 1.If an implementation includes more than one set of companion and EHCI host controllers, they are organized as groups of companion host controllers with intermixed EHCI controllers. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-104 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.3.2.2 Port Routing Control via PortOwner and Disconnect Event Manipulating the port routing via the CF-bit is an extreme process and not intended to be used during normal operation. The normal mode of port ownership transferal is on the granularity of individual ports using the Port Owner bit in the EHCI HC’s PORTSC register (for hand-offs from EHCI to companion host controllers). Individual port ownership is returned to the EHCI controller when the port registers a device disconnect. When the disconnect is detected, the port routing logic immediately returns the port ownership to the EHCI controller. The companion host controller port register detects the device disconnect and operates normally. Under normal operating conditions (assuming all HC drivers loaded and operational and the EHCI CF-bit is set to a one), the typical port enumeration sequence proceeds as illustrated below: • Initial condition is that EHCI is port owner. A device is connected causing the port to detect a connect, set the port connect change bit and issue a port-change interrupt (if enabled). • EHCI Driver identifies the port with the new connect change bit asserted and sends a change report to the hub driver. Hub driver issues a GetPortStatus() request and identifies the connect change. It then issues a request to clear the connect change, followed by a request to reset and enable the port. • When the EHCI Driver receives the request to reset and enable the port, it first checks the value reported by the LineStatus bits in the PORTSC register. If they indicate the attached device is a full-speed device (for example, D+ is asserted), then the EHCI Driver sets the PortReset control bit to a one (and sets the PortEnable bit to a zero) which begins the reset-process. Software times the duration of the reset, then terminates reset signaling by writing a zero to the port reset bit. The reset process is actually complete when software reads a zero in the PortReset bit. The EHCI Driver checks the PortOwner bit in the PORTSC register. If set to a one, the connected device is a high-speed device and EHCI Driver (root hub emulator) issues a change report to the hub driver and the hub driver continues to enumerate the attached device. • At the time the EHCI Driver receives the port reset and enable request the LineStatus bits might indicate a low-speed device. Additionally, when the port reset process is complete, the PortEnable field may indicate that a full-speed device is attached. In either case the EHCI driver sets the PortOwner bit in the PORTSC register to a one to release port ownership to a companion host controller. • When the EHCI Driver sets PortOwner bit to a one, the port routing logic makes the connection state of the transceiver available to the companion host controller port register and removes the connection state from the EHCI HC port. The EHCI PORTSC register observes and reports a disconnect event via the disconnect change bit. The EHCI Driver detects the connection status change (either by polling or by port change interrupt) and then sends a change report to the hub driver. When the hub driver requests that port-state, the EHCI Driver responds with a reset complete change set to a one, a connect change set to a one and a connect status set to a zero. This information is derived directly from the EHCI port register. This will allow the hub driver to assume the device was disconnected during reset. It will acknowledge the change bits and wait for the next change event. While the EHCI controller does not own the port, it simply remains in a state where the port reports no device connected. The device-connect evaluation circuitry of the companion HC activates and detects the device, the companion Driver detects the connection and enumerates the port. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-105 High-Speed USB On-The-Go (HS USB-OTG) When a port is routed to a companion HC, it remains under the control of the companion HC until the device is disconnected from the root port (ignoring for now the scenario where EHCI's CF-bit transitions from a 1b to a 0b). When a disconnect occurs, the disconnect event is detected by both the companion HC port control and the EHCI port ownership control. On the event, the port ownership is returned immediately to the EHCI controller. The companion HC stack detects the disconnect and acknowledges as it would in an ordinary standalone implementation. Subsequent connects will be detected by the EHCI port register and the process will repeat. 30.8.3.2.3 Example Port Routing State Machine Figure 30-51 illustrates an example of how the port ownership should be managed. The following sections describe the entry conditions to each state. Figure 30-51. Port Owner Handoff State Machine EHCI HC Owner Entry to this state occurs whenever one of the following events occur: • When the EHCI HC’s Configure Flag (CF) bit in the CONFIGFLAG register transitions from a zero to a one. This signals the fact that the system has a host controller driver for the EHCI HC and that all ports in the USB 2.0 host controller must default route to the EHCI controller. • When the port is owned by a companion HC and the device is disconnected from the port. The EHCI port routing control logic is notified of the disconnect, and returns port routing to the EHCI controller. The connection state of the companion HC goes immediately to the disconnected state (with appropriate side effect to connect change, enable and enable change). The companion HC driver will acknowledge the disconnect by setting the connect status change bit to a zero. This allows the companion HC's driver to interact with the port completely through the disconnect process. • When system software writes a zero to the PortOwner bit in the PORTSC register. This allows software to take ownership of a port from a companion host controller. When this occurs, the routing logic to the companion HC effectively signals a disconnect to the companion HC's port status and control register. Companion HC Owner Entry to this state occurs whenever one of the following events occur: • When the Port Owner field transitions from a zero to a one. • When the HS-mode HC’s Configure Flag (CF) is equal to zero. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-106 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) On entry to this state, the routing logic allows the companion HC port register to detect a device connect. Normal port enumeration proceeds. 30.8.3.2.4 Port Power The Port Power Control (PPC) bit in the HCSPARAMS register indicates whether the USB 2.0 host controller has port power control (See section HCSPARAMS—EHCI Compliant with extensions). When this bit is a zero, then the host controller does not support software control of port power switches. When in this configuration, the port power is always available and the companion host controllers must implement functionality consistent with port power always on. When the PPC bit is a one, then the host controller implementation includes port power switches. Each available switch has an output enable, which is referred to in this discussion as PortPowerOutputEnable (PPE). PPE is controlled based on the state of the combination bits PPC bit, EHCI Configured (CF)-bit and individual Port Power (PP) bits. Table 30-60 illustrates the summary behavioral model. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-107 High-Speed USB On-The-Go (HS USB-OTG) Table 30-60. Port Power Enable Control Rules CF 0 CHC2 (PP) 0 EHC3 (PP) X Owner CHC PPE1 0 Description When the EHCI controller has not been configured, the port is owned by the companion host controller. When the companion HC's port power select is off, then the port power is off. Similar to previous entry. When the companion HC's port power select is on, then the port power is on. Port owner has port power turned off, the power to port is off. Port owner has port power turned off, the power to port is off. Port owner has port power on, so power to port is on. If either HC has port power turned on, the power to the port is on. If either HC has port power turned on, the power to the port is on. Port owner has port power on, so power to port is on. Port owner has port power on, so power to port is on. Port owner has port power on, so power to port is on. 0 1 X CHC 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 CHC EHC EHC CHC EHC CHC CHC EHC 0 0 1 1 1 1 1 1 a) a) a) 30.8.3.2.5 1PPE (Port Power Enable). This bit actually turns on the port power switch (if one exists). (Companion Host Controller). 3 EHC (EHCI Host Controller). 2CHC Port Reporting Over-Current Host controllers are by definition power providers on USB. Whether the ports are considered high- or low-powered is a platform implementation issue. Each EHCI PORTSC register has an over-current status and over-current change bit. The functionality of these bits is specified in the USB Specification Revision 2.0. The over current detection and limiting logic usually resides outside the host controller logic. This logic may be associated with one or more ports. When this logic detects an over-current condition it is made available to both the companion and EHCI ports. The effect of an over-current status on a companion host controller port is beyond the scope of this document. The over-current condition effects the following bits in the PORTSC register on the EHCI port: MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-108 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • • • Over-current Active bits are set to a one. When the over-current condition goes away, the Over-current Active bit will transition from a one to a zero. Over-current Change bits are set to a one. On every transition of the Over-current Active bit the host controller will set the Over-current Change bit to a one. Software sets the Over-current Change bit to a zero by writing a one to this bit. Port Enabled/Disabled bit is set to a zero. When this change bit gets set to a one, then the Port Change Detect bit in the USBSTS register is set to a one. Port Power (PP) bits may optionally be set to a zero. There is no requirement in USB that a power provider shut off power in an over current condition. It is sufficient to limit the current and leave power applied. When the Over-current Change bit transitions from a zero to a one, the host controller also sets the Port Change Detect bit in the USBSTS register to a one. In addition, if the Port Change Interrupt Enable bit in the USBINTR register is a one, then the host controller will issue an interrupt to the system. Refer to Table 30-61 for summary behavior for over-current detection when the host controller is halted (suspended from a device component point of view). 30.8.3.3 Suspend/Resume The EHCI host controller provides an equivalent suspend and resume model as that defined for individual ports in a USB 2.0 Hub. Control mechanisms are provided to allow system software to suspend and resume individual ports. The mechanisms allow the individual ports to be resumed completely via software initiation. Other control mechanisms are provided to parameterize the host controller's response (or sensitivity) to external resume events. In this discussion, host-initiated, or software initiated resumes are called Resume Events/Actions. Bus-initiated resume events are called wake-up events. The classes of wakeup events are: • Remote-wakeup enabled device asserts resume signaling. In similar kind to USB 2.0 Hubs, EHCI controllers must always respond to explicit device resume signaling and wake up the system (if necessary). • Port connect and disconnect and over-current events. Sensitivity to these events can be turned on or off by using the per-port control bits in the PORTSC registers. Selective suspend is a feature supported by every PORTSC register. It is used to place specific ports into a suspend mode. This feature is used as a functional component for implementing the appropriate power management policy implemented in a particular operating system. When system software intends to suspend the entire bus, it should selectively suspend all enabled ports, then shut off the host controller by setting the Run/Stop bit in the USBCMD register to a zero. The EHCI module can then be placed into a lower device state via the PCI power management interface (See Appendix A, Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation. http://www.intel.com). When a wake event occurs the system will resume operation and system software will eventually set the Run/Stop bit to a one and resume the suspended ports. Software must not set the Run/Stop bit to a one until it is confirmed that the clock to the host controller is stable. This is usually confirmed in a system implementation in that all of the clocks in the system are stable before the CPU is restarted. So, by definition, if software is running, clocks in the system are stable and the Run/Stop bit in the USBCMD MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-109 High-Speed USB On-The-Go (HS USB-OTG) register can be set to a one. There are also minimum system software delays defined in the PCI Power Management Specification. Refer to this specification for more information. 30.8.3.3.1 Port Suspend/Resume System software places individual ports into suspend mode by writing a one into the appropriate PORTSC Suspend bit. Software must only set the Suspend bit when the port is in the enabled state (Port Enabled bit is a one) and the EHCI is the port owner (Port Owner bit is a zero). The host controller may evaluate the Suspend bit immediately or wait until a micro-frame or frame boundary occurs. If evaluated immediately, the port is not suspended until the current transaction (if one is executing) completes. Therefore, there may be several micro-frames of activity on the port until the host controller evaluates the Suspend bit. The host controller must evaluate the Suspend bit at least every frame boundary. System software can initiate a resume on a selectively suspended port by writing a one to the Force Port Resume bit. Software should not attempt to resume a port unless the port reports that it is in the suspended state (see Section PORTSCx). If system software sets Force Port Resume bit to a one when the port is not in the suspended state, the resulting behavior is undefined. In order to assure proper USB device operation, software must wait for at least 10 milliseconds after a port indicates that it is suspended (Suspend bit is a one) before initiating a port resume via the Force Port Resume bit. When Force Port Resume bit is a one, the host controller sends resume signaling down the port. System software times the duration of the resume (nominally 20 milliseconds) then sets the Force Port Resume bit to a zero. When the host controller receives the write to transition Force Port Resume to zero, it completes the resume sequence as defined in the USB specification, and sets both the Force Port Resume and Suspend bits to zero. Software-initiated port resumes do not affect the Port Change Detect bit in the USBSTS register nor do they cause an interrupt if the Port Change Interrupt Enable bit in the USBINTR register is a one. An external USB event may also initiate a resume. The wake events are defined above. When a wake event occurs on a suspended port, the resume signaling is detected by the port and the resume is reflected downstream within 100 µsec. The port's Force Port Resume bit is set to a one and the Port Change Detect bit in the USBSTS register is set to a one. If the Port Change Interrupt Enable bit in the USBINTR register is a one the host controller will issue a hardware interrupt. System software observes the resume event on the port, delays a port resume time (nominally 20 msec), then terminates the resume sequence by writing zero to the Force Port Resume bit in the port. The host controller receives the write of zero to Force Port Resume, terminates the resume sequence and sets Force Port Resume and Suspend port bits to zero. Software can determine that the port is enabled (not suspended) by sampling the PORTSC register and observing that the Suspend and Force Port Resume bits are zero. Software must ensure that the host controller is running (that is, HCHalted bit in the USBSTS register is a zero), before terminating a resume by writing a zero to a port's Force Port Resume bit. If HCHalted is a one when Force Port Resume is set to a zero, then SOFs will not occur down the enabled port and the device will return to suspend mode in a maximum of 10 milliseconds. Table 30-61 summarizes the wake-up events. Whenever a resume event is detected, the Port Change Detect bit in the USBSTS register is set to a one. If the Port Change Interrupt Enable bit is a one in the USBINTR register, the host controller will also generate an interrupt on the resume event. Software MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-110 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) acknowledges the resume event interrupt by clearing the Port Change Detect status bit in the USBSTS register. Table 30-61. Behavior During Wake-up Events Port Status and Signaling Type Signaled Port Response Device State D0 Port disabled, resume K-State received No Effect N/A not D0 N/A [2] [1], [2] Port suspended, Resume K-State Resume reflected downstream on signaled received port. Force Port Resume status bit in PORTSC register is set to a one. Port Change Detect bit in USBSTS register set to a one. Port is enabled, disabled or suspended, and the port's WKDSCNNT_E bit is a one. A disconnect is detected. Port is enabled, disabled or suspended, and the port's WKDSCNNT_E bit is a zero. A disconnect is detected. Depending in the initial port state, the PORTSC [1], [2] Connected Enable status bits are set to zero, and the Connect Change status bit is set to a one. Port Change Detect bit in the USBSTS register is set to a one. Depending on the initial port state, the [1], [3] PORTSC Connect and Enable status bits are set to zero, and the Connect Change status bit is set to a one. Port Change Detect bit in the USBSTS register is set to a one. [2] [3] Port is not connected and the PORTSC Connect Status and Connect Status [1], [2] port's WKCNNT_E bit is a one. A Change bits are set to a one. Port Change connect is detected. Detect bit in the USBSTS register is set to a one. Port is not connected and the PORTSC Connect Status and Connect Status [1], [3] port's WKCNNT_E bit is a zero. A Change bits are set to a one. Port Change connect is detected. Detect bit in the USBSTS register is set to a one. Port is connected and the port's WKOC_E bit is a one. An over-current condition occurs. PORTSC Over-current Active, Over-current [1], [2] Change bits are set to a one. If Port Enable/Disable bit is a one, it is set to a zero. Port Change Detect bit in the USBSTS register is set to a one [1], [3] PORTSC Over-current Active, Over-current Change bits are set to a one. If Port Enable/Disable bit is a one, it is set to a zero. Port Change Detect bit in the USBSTS register is set to a one. [2] [3] [2] Port is connected and the port's WKOC_E bit is a zero. An over-current condition occurs. [3] [1] Hardware interrupt issued if Port Change Interrupt Enable bit in the USBINTR register is a one. [2] PME# asserted if enabled (Note: PME Status must always be set to a one). [3] PME# not asserted. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-111 High-Speed USB On-The-Go (HS USB-OTG) 30.8.3.4 Schedule Traversal Rules The host controller executes transactions for devices using a simple, shared-memory schedule. The schedule is comprised of a few data structures, organized into two distinct lists. The data structures are designed to provide the maximum flexibility required by USB, minimize memory traffic and hardware/software complexity. System software maintains two schedules for the host controller: a periodic schedule and an asynchronous schedule. The root of the periodic schedule is the PERIODICLISTBASE register (see Section PERIODICLISTBASE; DEVICEADDR). The PERIODICLISTBASE register is the physical memory base address of the periodic frame list. The periodic frame list is an array of physical memory pointers. The objects referenced from the frame list must be valid schedule data structures as defined in Host Data Structures. In each micro-frame, if the periodic schedule is enabled (see Section Periodic Schedule ) then the host controller must execute from the periodic schedule before executing from the asynchronous schedule. It will only execute from the asynchronous schedule after it encounters the end of the periodic schedule. The host controller traverses the periodic schedule by constructing an array offset reference from the PERIODICLISTBASE and the FRINDEX registers (see Figure 30-52). It fetches the element and begins traversing the graph of linked schedule data structures. The end of the periodic schedule is identified by a next link pointer of a schedule data structure having its T-bit set to a one. When the host controller encounters a T-Bit set to a one during a horizontal traversal of the periodic list, it interprets this as an End-Of-Periodic-List mark. This causes the host controller to cease working on the periodic schedule and transitions immediately to traversing the asynchronous schedule. Once this transition is made, the host controller executes from the asynchronous schedule until the end of the micro-frame. Figure 30-52. Derivation of Pointer into Frame List Array When the host controller determines that it is time to execute from the asynchronous list, it uses the operational register ASYNCLISTADDR to access the asynchronous schedule, see Figure 30-53. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-112 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Figure 30-53. General Format of Asynchronous Schedule List The ASYNCLISTADDR register contains a physical memory pointer to the next queue head. When the host controller makes a transition to executing the asynchronous schedule, it begins by reading the queue head referenced by the ASYNCLISTADDR register. Software must set queue head horizontal pointer T-bits to a zero for queue heads in the asynchronous schedule. See Section Asynchronous Schedule for complete operational details. 30.8.3.4.1 Example—Preserving Micro-Frame Integrity One of the requirements of a USB host controller is to maintain Frame Integrity. This means that the HC must preserve the micro-frame boundaries. For example: SOF packets must be generated on time (within the specified allowable jitter), and High-speed EOF1,2 thresholds must be enforced. The end of micro-frame timing points EOF1 and EOF2 are clearly defined in the USB Specification Revision 2.0. One implication of this responsibility is that the HC must ensure that it does not start transactions that will not be completed before the end of the micro-frame. More precisely, no transactions should be started by the host controller, which cannot be completed in their entirety before the EOF1 point. In order to enforce this rule, the host controller must check each transaction before it starts to ensure that it will complete before the end of the micro-frame. So, what exactly needs to be involved in this check? Fundamentally, the transaction data payload, plus bit stuffing, plus transaction overhead must be taken into consideration. It is possible to be extremely accurate on how much time the next transaction will take. Take OUTs for an example. The host controller must fetch all of the OUT data from memory in order to send it onto the USB bus. A host controller implementation could pre-fetch all of the OUT data, and pre-compute the actual number of bits in the token and data packets. In addition, the system knows the depth of the target endpoint, so it could closely estimate turnaround time for handshake. In addition, the host controller knows the size of a handshake packet. Pre-computing effects of bit stuffing and summing up the other overhead numbers could allow the host controller to know exactly whether there was enough bus time, before EOF1 to complete the OUT transaction. To accomplish this particular approach takes an inordinate amount of time and hardware complexity. The alternative is to make a reasonable guess whether the next transaction can be started. An example approximation algorithm is described below. This example algorithm relies on the EHCI policy that periodic transactions are scheduled first in the micro-frame. It is a reasonable assumption that software will MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-113 High-Speed USB On-The-Go (HS USB-OTG) never over-commit the micro-frame to periodic transactions greater than the specification allowable 80%. In the available remaining 20% bandwidth, the host controller has some ability (in this example) to decide whether or not to execute a transaction. The result of this algorithm is that sometimes, under some circumstances a transaction will not be executed that could have been executed. However, under all circumstances, a transaction will never be started unless there is enough time in the frame to complete the transaction. Transaction Fit - A Best-Fit Approximation Algorithm A curve is calculated which represents the latest start time for every packet size, at which software will schedule the start of a periodic transaction. This curve is the 80% bandwidth curve. Another curve is calculated which is the absolute, latest permitted start time for every packet size. This curve represents the absolute latest time, that a transaction of each packet size can be started and completed, in the micro-frame. A plot of these two curves is illustrated in Figure 30-54. The plot Y-axis represents the number of byte-times left in a frame. The space between the 80% and the Last Start plots is bandwidth reclamation area. In this algorithm the host controller may skip transactions during this time if it is prudent. The Best-Fit Approximation method plots a function (f(x)) between the 80% and Last Start curves. The function f(x) adds a constant to every transaction's maximum packet size and the result compared with the number of bytes left in the frame. The constant represents an approximation of the effects of bit stuffing and protocol overhead. The host controller starts transactions whose results land above the function curve. The host controller will not start transactions whose results land below the function curve. Figure 30-54. Best Fit Approximation The LastStart line was calculated in this example to assume the absolute worst-case bus overhead per transaction. The particular transaction used was a start-split, zero-length OUT transaction with a MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-114 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) handshake. Summaries of the component parts are listed in Figure 30-62. The component times were derived from the protocol timings defined in the USB Specification Revision 2.0. Table 30-62. Example Worse-case Transaction Timing Components Component Split Token Host 2 Host IPG Token Host 2 Host IPG Data Packet (0 data bytes) Turnaround time Bit time 76 88 67 88 66.7 721 Byte Time 9.5 11 8.375 11 8.34 90.125 Explanation Split token as defined in USB core specification. Includes sync, token, eop, etc. Number of bit times required between consecutive host packets. Token as defined in USB core specification. Includes sync, token, eop, etc. Same as above Zero-length data packet. Includes sync, PID, crc16, eop, etc. Time for packet initiator (Host) to see the beginning of a response to a transmitted packet. Handshake packet as defined in USB core specification. Includes sync, PID, eop, etc. Total Handshake packet 48 6 144 The exact details of the function (f(x)) are up to the particular implementation. However, it should be obvious that the goal is to minimize the area under the curve between the approximation function and the Last Start curve, without dipping below the LastStart line, while at the same time keeping the check as simple as possible for hardware implementation. The f(x) in Figure was constructed using the following pseudo-code test on each transaction size data point. This algorithm assumes that the host controller keeps track of the remaining bits in the frame. Algorithm CheckTransactionWillFit (MaximumPacketSize, HC_BytesLeftInFrame) Begin Local Temp = MaximumPacketSize + 192 Local rvalue = TRUE If MaximumPacketSize >= 128 then Temp += 128 End If If Temp > HC_BytesLeftInFrame then Rvalue = FALSE End If MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-115 High-Speed USB On-The-Go (HS USB-OTG) Return rvalue End This algorithm takes two inputs, the current maximum packet size of the transaction and a hardware counter of the number of bytes left in the current micro-frame. It unconditionally adds a simple constant of 192 to the maximum packet size to account for a first-order effect of transaction overhead and bit stuffing. If the transaction size is greater than or equal to 128 bytes, then an additional constant of 128 is added to the running sum to account for the additional worst-case bit stuffing of payloads larger than 128. An inflection point was inserted at 128 because the f(x) plot was getting close to the LastStart line. 30.8.3.5 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame number changes) of the high-speed bus and the full- and low-speed bus(s) below USB 2.0 Hubs be strictly aligned. Super-imposed on this requirement is that USB 2.0 Hubs manage full- and low-speed transactions via a micro-frame pipeline (see start- (SS) and complete- (CS) splits illustrated in Figure 30-55). A simple, direct projection of the frame boundary model into the host controller interface schedule architecture creates tension (complexity for both hardware and software) between the frame boundaries and the scheduling mechanisms required to service the full- and low-speed transaction translator periodic pipelines. Figure 30-55. Frame Boundary Relationship between HS bus and FS/LS Bus The simple projection, as Figure 30-55 illustrates, introduces frame-boundary wrap conditions for scheduling on both the beginning and end of a frame. In order to reduce the complexity for hardware and software, the host controller is required to implement a one micro-frame phase shift for its view of frame boundaries. The phase shift eliminates the beginning of frame and frame-wrap scheduling boundary conditions. The implementation of this phase shift requires that the host controller use one register value for accessing the periodic frame list and another value for the frame number value included in the SOF token. These two values are separate, but tightly coupled. The periodic frame list is accessed via the Frame List Index Register (FRINDEX) documented in Section FRINDEX and initially illustrated in Section Schedule Traversal Rules . Bits FRINDEX[2:0], represent the micro-frame number. The SOF value is coupled to the value of FRINDEX[13:3]. Both FRINDEX[13:3] and the SOF value are increment based on FRINDEX[2:0]. It is required that the SOF value be delayed from the FRINDEX value by one micro-frame. The one micro-frame delay yields host controller periodic schedule and bus frame boundary relationship as illustrated in Figure 30-56. This adjustment allows software to trivially schedule the MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-116 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) periodic start and complete-split transactions for full-and low-speed periodic endpoints, using the natural alignment of the periodic schedule interface. The reasons for selecting this phase-shift are beyond the scope of this specification. Figure 30-56 illustrates how periodic schedule data structures relate to schedule frame boundaries and bus frame boundaries. To aid the presentation, two terms are defined. The host controller's view of the 1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries is called B-Frames. Figure 30-56. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries H-Frame boundaries for the host controller correspond to increments of FRINDEX[13:3]. Micro-frame numbers for the H-Frame are tracked by FRINDEX[2:0]. B-Frame boundaries are visible on the high-speed bus via changes in the SOF token's frame number. Micro-frame numbers on the high-speed bus are only derived from the SOF token's frame number (that is, the high-speed bus will see eight SOFs with the same frame number value). H-Frames and B-Frames have the fixed relationship (that is, B-Frames lag H-Frames by one micro-frame time) illustrated in Figure 30-56 . The host controller's periodic schedule is naturally aligned to H-Frames. Software schedules transactions for full- and low-speed periodic endpoints relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly the right time for the USB 2.0 Hub periodic pipeline. As described in Section FRINDEX, the SOF Value can be implemented as a shadow register (in this example, called SOFV), which lags the FRINDEX register bits [13:3] by one micro-frame count. Table 30-63 illustrates the required relationship between the value of FRINDEX and the value of SOFV. This lag behavior can be accomplished by incrementing FRINDEX[13:3] based on carry-out on the 7 to 0 increment of FRINDEX[2:0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2:0]. Software is allowed to write to FRINDEX. Section FRINDEX provides the requirements that software should adhere when writing a new value in FRINDEX. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-117 High-Speed USB On-The-Go (HS USB-OTG) Table 30-63. Operation of FRINDEX and SOFV (SOF Value Register) Current FRINDEX[F] N N+1 N+1 N+1 N+1 N+1 N+1 N+1 SOFV N N N+1 N+1 N+1 N+1 N+1 N+1 FRINDEX[mF] 111b 000b 001b 010b 011b 100b 101b 110b FRINDEX[F] N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 Next SOFV N N+1 N+1 N+1 N+1 N+1 N+1 N+1 FRINDEX[mF] 000b 001b 010b 011b 100b 101b 110b 111b Where [F] = [13:3]; [µF] = [2:0] 30.8.3.6 Periodic Schedule The periodic schedule traversal is enabled or disabled via the Periodic Schedule Enable bit in the USBCMD register. If the Periodic Schedule Enable bit is set to a zero, then the host controller simply does not try to access the periodic frame list via the PERIODICLISTBASE register. Likewise, when the Periodic Schedule Enable bit is a one, then the host controller does use the PERIODICLISTBASE register to traverse the periodic schedule. The host controller will not react to modifications to the Periodic Schedule Enable immediately. In order to eliminate conflicts with split transactions, the host controller evaluates the Periodic Schedule Enable bit only when FRINDEX[2:0] is zero. System software must not disable the periodic schedule if the schedule contains an active split transaction work item that spans the 000b micro-frame. These work items must be removed from the schedule before the Periodic Schedule Enable bit is written to a zero. The Periodic Schedule Status bit in the USBSTS register indicates status of the periodic schedule. System software enables (or disables) the periodic schedule by writing a one (or zero) to the Periodic Schedule Enable bit in the USBCMD register. Software then can poll the Periodic Schedule Status bit to determine when the periodic schedule has made the desired transition. Software must not modify the Periodic Schedule Enable bit unless the value of the Periodic Schedule Enable bit equals that of the Periodic Schedule Status bit. The periodic schedule is used to manage all isochronous and interrupt transfer streams. The base of the periodic schedule is the periodic frame list. Software links schedule data structures to the periodic frame list to produce a graph of scheduled data structures. The graph represents an appropriate sequence of transactions on the USB. Figure illustrates isochronous transfers (using iTDs and siTDs) with a period of one are linked directly to the periodic frame list. Interrupt transfers (are managed with queue heads) and isochronous streams with periods other than one are linked following the period-one iTD/siTDs. Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates are linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue heads with a poll rate of one, on the very end. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-118 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Figure 30-57. Example Periodic Schedule 30.8.3.7 Managing Isochronous Transfers Using iTDs The structure of an iTD is presented in Isochronous (High-Speed) Transfer Descriptor (iTD). There are four distinct sections to an iTD: • The first field is the Next Link Pointer. This field is for schedule linkage purposes only; • Transaction description array. This area is an eight-element array. Each element represents control and status information for one micro-frame's worth of transactions for a single high-speed isochronous endpoint. • The buffer page pointer array is a 7-element array of physical memory pointers to data buffers. These are 4K aligned pointers to physical memory. • Endpoint capabilities. This area utilizes the unused low-order 12 bits of the buffer page pointer array. The fields in this area are used across all transactions executed for this iTD, including endpoint addressing, transfer direction, maximum packet size and high-bandwidth multiplier. 30.8.3.7.1 Host Controller Operational Model for iTDs The host controller uses FRINDEX register bits [12:3] to index into the periodic frame list. This means that the host controller visits each frame list element eight consecutive times before incrementing to the next periodic frame list element. Each iTD contains eight transaction descriptions, which map directly to FRINDEX register bits [2:0]. Each iTD can span 8 micro-frames worth of transactions. When the host controller fetches an iTD, it uses FRINDEX register bits [2:0] to index into the transaction description array. If the active bit in the Status field of the indexed transaction description is set to zero, the host controller ignores the iTD and follows the Next pointer to the next schedule data structure. When the indexed active bit is a one the host controller continues to parse the iTD. It stores the indexed transaction description and the general endpoint information (device address, endpoint number, maximum MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-119 High-Speed USB On-The-Go (HS USB-OTG) packet size, etc.). It also uses the Page Select (PG) field to index the buffer pointer array, storing the selected buffer pointer and the next sequential buffer pointer. For example, if PG field is a 0, then the host controller will store Page 0 and Page 1. The host controller constructs a physical data buffer address by concatenating the current buffer pointer (as selected using the current transaction description's PG field) and the transaction description's Transaction Offset field. The host controller uses the endpoint addressing information and I/O-bit to execute a transaction to the appropriate endpoint. When the transaction is complete, the host controller clears the active bit and writes back any additional status information to the Status field in the currently selected transaction description. The data buffer associated with the iTD must be virtually contiguous memory. Seven page pointers are provided to support eight high-bandwidth transactions regardless of the starting packet’s offset alignment into the first page. A starting buffer pointer (physical memory address) is constructed by concatenating the page pointer (example: page 0 pointer) selected by the active transaction descriptions’ PG (example value: 00B) field with the transaction offset field. As the transaction moves data, the host controller must detect when an increment of the current buffer pointer will cross a page boundary. When this occurs the host controller simply replaces the current buffer pointer’s page portion with the next page pointer (example: page 1 pointer) and continues to move data. The size of each bus transaction is determined by the value in the Maximum Packet Size field. An iTD supports high-bandwidth pipes via the Mult (multiplier) field. When the Mult field is 1, 2, or 3, the host controller executes the specified number of Maximum Packet sized bus transactions for the endpoint in the current micro-frame. In other words, the Mult field represents a transaction count for the endpoint in the current micro-frame. If the Mult field is zero, the operation of the host controller is undefined. The transfer description is used to service all transactions indicated by the Mult field. For OUT transfers, the value of the Transaction X Length field represents the total bytes to be sent during the micro-frame. The Mult field must be set by software to be consistent with Transaction X Length and Maximum Packet Size. The host controller will send the bytes in Maximum Packet Sized portions. After each transaction, the host controller decrements it's local copy of Transaction X Length by Maximum Packet Size. The number of bytes the host controller sends is always Maximum Packet Size or Transaction X Length, whichever is less. The host controller advances the transfer state in the transfer description, updates the appropriate record in the iTD and moves to the next schedule data structure. The maximum sized transaction supported is 3 x 1024 bytes. For IN transfers, the host controller issues Mult transactions. It is assumed that software has properly initialized the iTD to accommodate all of the possible data. During each IN transaction, the host controller must use Maximum Packet Size to detect packet babble errors. The host controller keeps the sum of bytes received in the Transaction X Length field. After all transactions for the endpoint have completed for the micro-frame, Transaction X Length contains the total bytes received. If the final value of Transaction X Length is less than the value of Maximum Packet Size, then less data than was allowed for was received from the associated endpoint. This short packet condition does not set the USBINT bit in the USBSTS register to a one. The host controller will not detect this condition. If the device sends more than Transaction X Length or Maximum Packet Size bytes (whichever is less), then the host controller will set the Babble Detected bit to a one and set the Active bit to a zero. Note, that the host controller is not required to update the iTD field Transaction X Length in this error scenario. If the Mult field is greater than one, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-120 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) then the host controller will automatically execute the value of Mult transactions. The host controller will not execute all Mult transactions if: • The endpoint is an OUT and Transaction X Length goes to zero before all the Mult transactions have executed (ran out of data), or • The endpoint is an IN and the endpoint delivers a short packet, or an error occurs on a transaction before Mult transactions have been executed. The end of micro-frame may occur before all of the transaction opportunities have been executed. When this happens, the transfer state of the transfer description is advanced to reflect the progress that was made, the result written back to the iTD and the host controller proceeds to processing the next micro-frame. Refer to Appendix D for a table summary of the host controller required behavior for all the high-bandwidth transaction cases. 30.8.3.7.2 Software Operational Model for iTDs A client buffer request to an isochronous endpoint may span 1 to N micro-frames. When N is larger than one, system software may have to use multiple iTDs to read or write data with the buffer (if N is larger than eight, it must use more than one iTD). Figure illustrates the simple model of how a client buffer is mapped by system software to the periodic schedule (that is, the periodic frame list and a set of iTDs). On the right is the client description of its request. The description includes a buffer base address plus additional annotations to identify which portions of the buffer should be used with each bus transaction. In the middle is the iTD data structures used by the system software to service the client request. Each iTD can be initialized to service up to 24 transactions, organized into eight groups of up to three transactions each. Each group maps to one micro-frame's worth of transactions. The EHCI controller does not provide per-transaction results within a micro-frame. It treats the per-micro-frame transactions as a single logical transfer. On the left is the host controller’s frame list. System software establishes references from the appropriate locations in the frame list to each of the appropriate iTDs. If the buffer is large, then system software can use a small set of iTDs to service the entire buffer. System software can activate the transaction description records (contained in each iTD) in any pattern required for the particular data stream. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-121 High-Speed USB On-The-Go (HS USB-OTG) Figure 30-58. Example Association of iTDs to Client Request Buffer As noted above, the client request includes a pointer to the base of the buffer and offsets into the buffer to annotate which buffer sections are to be used on each bus transaction that occurs on this endpoint. System software must initialize each transaction description in an iTD to ensure it uses the correct portion of the client buffer. For example, for each transaction description, the PG field is set to index the correct physical buffer page pointer and the Transaction Offset field is set relative to the correct buffer pointer page (for example, the same one referenced by the PG field). When the host controller executes a transaction it selects a transaction description record based on FRINDEX[2:0]. It then uses the current Page Buffer Pointer (as selected by the PG field) and concatenates to the transaction offset field. The result is a starting buffer address for the transaction. As the host controller moves data for the transaction, it must watch for a page wrap condition and properly advance to the next available Page Buffer Pointer. System software must not use the Page 6 buffer pointer in a transaction description where the length of the transfer will wrap a page boundary. Doing so will yield undefined behavior. The host controller hardware is not required to 'alias' the page selector to page zero. USB 2.0 isochronous endpoints can specify a period greater than one. Software can achieve the appropriate scheduling by linking iTDs into the appropriate frames (relative to the frame list) and by setting appropriate transaction description elements active bits to a one. Periodic Scheduling Threshold The Isochronous Scheduling Threshold field in the HCCPARAMS capability register is an indicator to system software as to how the host controller pre-fetches and effectively caches schedule data structures. It is used by system software when adding isochronous work items to the periodic schedule. The value of this field indicates to system software the minimum distance it can update isochronous data (relative to the current location of the host controller execution in the periodic list) and still have the host controller process them. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-122 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) The iTD and siTD data structures each describe 8 micro-frames worth of transactions. The host controller is allowed to cache one (or more) of these data structures in order to reduce memory traffic. There are three basic caching models that account for the fact the isochronous data structures span 8 micro-frames. The three caching models are: no caching, micro-frame caching and frame caching. When software is adding new isochronous transactions to the schedule, it always performs a read of the FRINDEX register to determine the current frame and micro-frame the host controller is currently executing. Of course, there is no information about where in the micro-frame the host controller is, so a constant uncertainty-factor of one micro-frame has to be assumed. Combining the knowledge of where the host controller is executing with the knowledge of the caching model allows the definition of simple algorithms for how closely software can reliably work to the executing host controller. No caching is indicated with a value of zero in the Isochronous Scheduling Threshold field. The host controller may pre-fetch data structures during a periodic schedule traversal (per micro-frame) but will always dump any accumulated schedule state at the end of the micro-frame. At the appropriate time relative to the beginning of every micro-frame, the host controller always begins schedule traversal from the frame list. Software can use the value of the FRINDEX register (plus the constant 1 uncertainty-factor) to determine the approximate position of the executing host controller. When no caching is selected, software can add an isochronous transaction as near as 2 micro-frames in front of the current executing position of the host controller. Frame caching is indicated with a non-zero value in bit [7] of the Isochronous Scheduling Threshold field. In the frame-caching model, system software assumes that the host controller caches one (or more) isochronous data structures for an entire frame (8 micro-frames). Software uses the value of the FRINDEX register (plus the constant 1 uncertainty) to determine the current micro-frame/frame (assume modulo 8 arithmetic in adding the constant 1 to the micro-frame number). For any current frame N, if the current micro-frame is 0 to 6, then software can safely add isochronous transactions to Frame N + 1. If the current micro-frame is 7, then software can add isochronous transactions to Frame N + 2. Micro-frame caching is indicated with a non-zero value in the least-significant 3 bits of the Isochronous Scheduling Threshold field. System software assumes the host controller caches one or more periodic data structures for the number of micro-frames indicated in the Isochronous Scheduling Threshold field. For example, if the count value were 2, then the host controller keeps a window of 2 micro-frames worth of state (current micro-frame, plus the next) on-chip. On each micro-frame boundary, the host controller releases the current micro-frame state and begins accumulating the next micro-frame state. 30.8.3.8 Asynchronous Schedule The Asynchronous schedule traversal is enabled or disabled via the Asynchronous Schedule Enable bit in the USBCMD register. If the Asynchronous Schedule Enable bit is set to a zero, then the host controller simply does not try to access the asynchronous schedule via the ASYNCLISTADDR register. Likewise, when the Asynchronous Schedule Enable bit is a one, then the host controller does use the ASYNCLISTADDR register to traverse the asynchronous schedule. Modifications to the Asynchronous Schedule Enable bit are not necessarily immediate. Rather the new value of the bit will only be taken into consideration the next time the host controller needs to use the value of the ASYNCLISTADDR register to get the next queue head. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-123 High-Speed USB On-The-Go (HS USB-OTG) The Asynchronous Schedule Status bit in the USBSTS register indicates status of the asynchronous schedule. System software enables (or disables) the asynchronous schedule by writing a one (or zero) to the Asynchronous Schedule Enable bit in the USBCMD register. Software then can poll the Asynchronous Schedule Status bit to determine when the asynchronous schedule has made the desired transition. Software must not modify the Asynchronous Schedule Enable bit unless the value of the Asynchronous Schedule Enable bit equals that of the Asynchronous Schedule Status bit. The asynchronous schedule is used to manage all Control and Bulk transfers. Control and Bulk transfers are managed using queue head data structures. The asynchronous schedule is based at the ASYNCLISTADDR register. The default value of the ASYNCLISTADDR register after reset is undefined and the schedule is disabled when the Asynchronous Schedule Enable bit is a zero. Software may only write this register with defined results when the schedule is disabled. for example, Asynchronous Schedule Enable bit in the USBCMD and the Asynchronous Schedule Status bit in the USBSTS register are zero. System software enables execution from the asynchronous schedule by writing a valid memory address (of a queue head) into this register. Then software enables the asynchronous schedule by setting the Asynchronous Schedule Enable bit is set to one. The asynchronous schedule is actually enabled when the Asynchronous Schedule Status bit is a one. When the host controller begins servicing the asynchronous schedule, it begins by using the value of the ASYNCLISTADDR register. It reads the first referenced data structure and begins executing transactions and traversing the linked list as appropriate. When the host controller “completes” processing the asynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in the ASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the first data structure that will be serviced. This provides round-robin fairness for processing the asynchronous schedule. A host controller “completes” processing the asynchronous schedule when one of the following events occur: • The end of a micro-frame occurs. • The host controller detects an empty list condition (that is, see Section Empty Asynchronous Schedule Detection ) • The schedule has been disabled via the Asynchronous Schedule Enable bit in the USBCMD register. The queue heads in the asynchronous list are linked into a simple circular list as shown in Figure 30-53. Queue head data structures are the only valid data structures that may be linked into the asynchronous schedule. An isochronous transfer descriptor (iTD or siTD) in the asynchronous schedule yields undefined results. The maximum packet size field in a queue head is sized to accommodate the use of this data structure for all non-isochronous transfer types. The USB Specification, Revision 2.0 specifies the maximum packet sizes for all transfer types and transfer speeds. System software should always parameterize the queue head data structures according to the core specification requirements. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-124 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.3.8.1 Adding Queue Heads to Asynchronous Schedule This is a software requirement section. There are two independent events for adding queue heads to the asynchronous schedule. The first is the initial activation of the asynchronous list. The second is inserting a new queue head into an activated asynchronous list. Activation of the list is simple. System software writes the physical memory address of a queue head into the ASYNCLISTADDR register, then enables the list by setting the Asynchronous Schedule Enable bit in the USBCMD register to a one. When inserting a queue head into an active list, software must ensure that the schedule is always coherent from the host controllers' point of view. This means that the system software must ensure that all queue head pointer fields are valid. For example qTD pointers have T-Bits set to a one or reference valid qTDs and the Horizontal Pointer references a valid queue head data structure. The following algorithm represents the functional requirements: InsertQueueHead (pQHeadCurrent, pQueueHeadNew) --- Requirement: all inputs must be properly initialized. --- pQHeadCurrent is a pointer to a queue head that is -- already in the active list -- pQHeadNew is a pointer to the queue head to be added --- This algorithm links a new queue head into a existing -- list -pQueueHeadNew.HorizontalPointer = pQueueHeadCurrent.HorizontalPointer pQueueHeadCurrent.HorizontalPointer = physicalAddressOf(pQueueHeadNew) End InsertQueueHead 30.8.3.8.2 Removing Queue Heads from Asynchronous Schedule This is a software requirement section. There are two independent events for removing queue heads from the asynchronous schedule. The first is shutting down (deactivating) the asynchronous list. The second is extracting a single queue head from an activated list. Software deactivates the asynchronous schedule by setting the Asynchronous Schedule Enable bit in the USBCMD register to a zero. Software can determine when the list is idle when the Asynchronous Schedule Status bit in the USBSTS register is a zero. The normal mode of operation is that software removes queue heads from the asynchronous schedule without MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-125 High-Speed USB On-The-Go (HS USB-OTG) shutting it down. Software must not remove an active queue head from the schedule. Software should first deactivate all active qTDs, wait for the queue head to go inactive, then remove the queue head from the asynchronous list. Software removes a queue head from the asynchronous list via the following algorithm. As illustrated, the unlinking is quite easy. Software merely must ensure all of the link pointers reachable by the host controller are kept consistent. UnlinkQueueHead (pQHeadPrevious, pQueueHeadToUnlink, pQHeadNext) --- Requirement: all inputs must be properly initialized. --- pQHeadPrevious is a pointer to a queue head that -- references the queue head to remove -- pQHeadToUnlink is a pointer to the queue head to be -- removed -- pQheadNext is a pointer to a queue head still in the -- schedule. Software provides this pointer with the -- following strict rules: --------- This algorithm unlinks a queue head from a circular list -pQueueHeadPrevious.HorizontalPointer = pQueueHeadToUnlink.HorizontalPointer pQueueHeadToUnlink.HorizontalPointer = pQHeadNext End UnlinkQueueHead if the host software is one queue head, then pQHeadNext must be the same as QueueheadToUnlink.HorizontalPointer. If the host software is unlinking a consecutive series of queue heads, QHeadNext must be set by software to the queue head remaining in the schedule. If software removes the queue head with the H-bit set to a one, it must select another queue head still linked into the schedule and set its H-bit to a one. This should be completed before removing the queue head. The requirement is that software keep one queue head in the asynchronous schedule, with its H-bit set to a one. At the point software has removed one or more queue heads from the asynchronous schedule, it is unknown whether the host controller has a cached pointer to them. Similarly, it is unknown how long the host controller might retain the cached information, as it is implementation dependent and may be affected by the actual dynamics of the schedule load. Therefore, once software has removed a queue head from the MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-126 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) asynchronous list, it must retain the coherency of the queue head (link pointers, etc.). It cannot disturb the removed queue heads until it knows that the host controller does not have a local copy of a pointer to any of the removed data structures. The method software uses to determine when it is safe to modify a removed queue head is to handshake with the host controller. The handshake mechanism allows software to remove items from the asynchronous schedule, then execute a simple, lightweight handshake that is used by software as a key that it can free (or reuse) the memory associated the data structures it has removed from the asynchronous schedule. The handshake is implemented with three bits in the host controller. The first bit is a command bit (Interrupt on Async Advance Doorbell bit in the USBCMD register) that allows software to inform the host controller that something has been removed from its asynchronous schedule. The second bit is a status bit (Interrupt on Async Advance bit in the USBSTS register) that the host controller sets after it has released all on-chip state that may potentially reference one of the data structures just removed. When the host controller sets this status bit to a one, it also sets the command bit to a zero. The third bit is an interrupt enable (Interrupt on Async Advance bit in the USBINTR register) that is matched with the status bit. If the status bit is a one and the interrupt enable bit is a one, then the host controller will assert a hardware interrupt. Figure 30-59 illustrates a general example. In this example, consecutive queue heads (B and C) are unlinked from the schedule using the algorithm above. Before the unlink operation, the host controller has a copy of queue head A. The unlink algorithm requires that as software unlinks each queue head, the unlinked queue head is loaded with the address of a queue head that will remain in the asynchronous schedule. When the host controller observes that doorbell bit being set to a one, it makes a note of the local reachable schedule information. In this example, the local reachable schedule information includes both queue heads (A and B). It is sufficient that the host controller can set the status bit (and clear the doorbell bit) as soon as it has traversed beyond current reachable schedule information (that is, traversed beyond queue head (B) in this example). Figure 30-59. Generic Queue Head Unlink Scenario MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-127 High-Speed USB On-The-Go (HS USB-OTG) Alternatively, a host controller implementation is allowed to traverse the entire asynchronous schedule list (for example, observed the head of the queue (twice)) before setting the Advance on Async status bit to a one. Software may re-use the memory associated with the removed queue heads after it observes the Interrupt on Async Advance status bit is set to a one, following assertion of the doorbell. Software should acknowledge the Interrupt on Async Advance status as indicated in the USBSTS register, before using the doorbell handshake again. 30.8.3.8.3 Empty Asynchronous Schedule Detection The Enhanced Host Controller Interface uses two bits to detect when the asynchronous schedule is empty. The queue head data structure (see Figure 30-48) defines an H-bit in the queue head, which allows software to mark a queue head as being the head of the reclaim list. The Enhanced Host Controller Interface also keeps a 1-bit flag in the USBSTS register (Reclamation) that is set to a zero when the Enhanced Interface Host Controller observes a queue head with the H-bit set to a one. The reclamation flag in the status register is set to one when any USB transaction from the asynchronous schedule is executed (or whenever the asynchronous schedule starts, see Section Asynchronous Schedule Traversal : Start Event ). If the Enhanced Host Controller Interface ever encounters an H-bit of one and a Reclamation bit of zero, the EHCI controller simply stops traversal of the asynchronous schedule. A example illustrating the H-bit in a schedule is illustrated in Figure 30-60. Figure 30-60. Asynchronous Schedule List w/Annotation to Mark Head of List Software must ensure there is at most one queue head with the H-bit set to a one, and that it is always coherent with respect to the schedule. 30.8.3.8.4 Restarting Asynchronous Schedule Before EOF There are many situations where the host controller will detect an empty list long before the end of the micro-frame. It is important to remember that under many circumstances the schedule traversal has stopped due to Nak/Nyet responses from all endpoints. An example of particular interest is when a start-split for a bulk endpoint occurs early in the micro-frame. Given the EHCI simple traversal rules, the complete-split for that transaction may Nak/Nyet out very MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-128 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) quickly. If it is the only item in the schedule, then the host controller will cease traversal of the Asynchronous schedule very early in the micro-frame. In order to provide reasonable service to this endpoint, the host controller should issue the complete-split before the end of the current micro-frame, instead of waiting until the next micro-frame. When the reason for host controller idling asynchronous schedule traversal is because of empty list detection, it is mandatory the host controller implement a 'waking' method to resume traversal of the asynchronous schedule. An example method is described below. Example Method for Restarting Asynchronous Schedule Traversal The reason for idling the host controller when the list is empty is to keep the host controller from unnecessarily occupying too much memory bandwidth. The question is: how long should the host controller stay idle before restarting? The answer in this example is based on deriving a manifest constant, which is the amount of time the host controller will stay idle before restarting traversal. In this example, the manifest constant is called AsyncSchedSleepTime, and has a value of 10µsec. The value is derived based on the analysis in Section Example Derivation for AsyncSchedSleepTime , The traversal algorithm is simple: • Traverse the Asynchronous schedule until the either an End-Of-micro-Frame event occurs, or an empty list is detected. If the event is an End-of-micro-Frame, go attempt to traverse the Periodic schedule. If the event is an empty list, then set a sleep timer and go to a schedule sleep state. • When the sleep timer expires, set working context to the Asynchronous Schedule start condition and go to schedule active state. The start context allows the HC to reload Nakcnt fields, etc. so the HC has a chance to run for more than one iteration through the schedule. This process simply repeats itself each micro-frame. Figure 30-61 illustrates a sample state machine to manage the active and sleep states of the Asynchronous Schedule traversal policy. There are three states: Actively traversing the Asynchronous schedule, Sleeping, and Not Active. The last two are similar in terms of interaction with the Asynchronous schedule, but the Not Active state means that the host controller is busy with the Periodic schedule or the Asynchronous schedule is not enabled. The Sleeping state is specifically a special state where the host controller is just waiting for a period of time before resuming execution of the Asynchronous schedule. Figure 30-61. Example State Machine for Managing Asynchronous Schedule Traversal MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-129 High-Speed USB On-The-Go (HS USB-OTG) The actions referred to in Figure 30-61 are defined in Table 30-64. Table 30-64. Asynchronous Schedule SM Transition Actions Action A B Action Description Label On detection of the empty list, the host controller sets the AsynchronousTraversalSleepTimer to AsyncSchedSleepTime. When the AsynchronousTraversalSleepTimer expires, the host controller sets the Reclamation bit in the USBSTS register to a one and moves the Nak Counter reload state machine to WaitForListHead (see Section Operational Model for Nak Counter). The host controller cancels the sleep timer (AsynchronousTraversalSleepTimer). C Async Sched Not Active This is the initial state of the traversal state machine after a host controller reset. The traversal state machine will not leave this state when the Asynchronous Schedule Enable bit in the USBCMD register is a zero. This state is entered from Async Sched Active or Async Sched Sleeping states when the end-of-micro-frame event is detected. Async Sched Active This state is entered from the Async Sched Not Active state when the periodic schedule is not active. It is also entered from the Async Sched Sleeping states when the AsyncrhonousTraversalSleepTimer expires. On every transition into this state, the host controller sets the Reclamation bit in the USBSTS register to a one. While in this state, the host controller will continually traverse the asynchronous schedule until either the end of micro-frame or an empty list condition is detected. Async Sched Sleeping The state is entered from the Async Sched Active state when a schedule empty condition is detected. On entry to this state, the host controller sets the AsynchronousTraversalSleepTimer to AsyncSchedSleepTime. Example Derivation for AsyncSchedSleepTime The derivation is based on analysis of what work the host controller could be doing next. It assumes the host controller does not keep any state about what work is possibly pending in the asynchronous schedule. The schedule could contain any mix of the possible combinations of high- full- or low-speed control and bulk requests. Table 30-65 summarizes some of the typical 'next transactions' that could be in the schedule, and the amount of time (for example, footprint or wall clock) the transaction will take to complete. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-130 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-65. Typical Low-/Full-speed Transaction Times Transaction Attributes Speed Size Type Speed Size Type Speed Size Type HS 512 Bulk FS 64 Bulk FS 8 Cntrl Footprint (time) 11.9 ms 9.45 ms Description Maximum foot print for a worst-case, full-sized bulk data transaction. Maximum footprint for an approximate best-case, full-sized bulk data transaction. ~50 ms Approximate typical for full-sized bulk data. An 8-byte low-speed is about 2x, or between 90 and 100 ms. ~12 ms Approximate typical for 8-byte bulk/control (that is, setup) A AsyncSchedSleepTime value of 10 µs provides a reasonable relaxation of the system memory load and still provides a good level of service for the various transfer types and payload sizes. For example, say we detect an empty list after issuing a start-split for a 64-byte full-speed bulk request. Assuming this is the only thing in the list, the host controller will get the results of the full-speed transaction from the hub during the fifth complete-split request. If the full-speed transaction was an IN and it nak'd, the 10µs sleep period would allow the host controller to get the NAK results on the first complete-split. 30.8.3.8.5 Asynchronous Schedule Traversal : Start Event Once the HC has idled itself via the empty schedule detection (Section 0), it will naturally activate and begin processing from the Periodic Schedule at the beginning of each micro-frame. In addition, it may have idled itself early in a micro-frame. When this occurs (idles early in the micro-frame) the HC must occasionally re-activate during the micro-frame and traverse the asynchronous schedule to determine whether any progress can be made. The requirements and method for this restart are described in Section Restarting Asynchronous Schedule Before EOF . Asynchronous schedule Start Events are defined to be: • Whenever the host controller transitions from the periodic schedule to the asynchronous schedule. If the periodic schedule is disabled and the asynchronous schedule is enabled, then the beginning of the micro-frame is equivalent to the transition from the periodic schedule, or • The asynchronous schedule traversal restarts from a sleeping state (see Section Restarting Asynchronous Schedule Before EOF ). 30.8.3.8.6 Reclamation Status Bit (USBSTS Register) The operation of the empty asynchronous schedule detection feature (Section Empty Asynchronous Schedule Detection ) depends on the proper management of the Reclamation bit in the USBSTS register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-131 High-Speed USB On-The-Go (HS USB-OTG) The host controller tests for an empty schedule just after it fetches a new queue head while traversing the asynchronous schedule (See Section Fetch Queue Head ). It is required that the host controller sets the Reclamation bit to a one whenever an asynchronous schedule traversal Start Event, as documented in Section Asynchronous Schedule Traversal : Start Event , occurs. The Reclamation bit is also set to a one whenever the host controller executes a transaction while traversing the asynchronous schedule (see Section Execute Transaction ). The host controller sets the Reclamation bit to a zero whenever it finds a queue head with its H-bit set to a one. Software should only set a queue head's H-bit if the queue head is in the asynchronous schedule. If software sets the H-bit in an interrupt queue head to a one, the resulting behavior is undefined. The host controller may set the Reclamation bit to a zero when executing from the periodic schedule. 30.8.3.9 Operational Model for Nak Counter This section describes the operational model for the NakCnt field defined in a queue head (see Section Queue Head). Software should not use this feature for interrupt queue heads. This rule is not required to be enforced by the host controller. USB protocol has built-in flow control via the Nak response by a device. There are several scenarios, beyond the Ping feature, where an endpoint may naturally Nak or Nyet the majority of the time. An example is the host controller management of the split transaction protocol for control and bulk endpoints. All bulk endpoints (High- or Full-speed) are serviced via the same asynchronous schedule. The time between the Start-split transaction and the first Complete-split transaction could be very short (that is, like when the endpoint is the only one in the asynchronous schedule). The hub NYETs (effectively Naks) the Complete-split transaction until the classic transaction is complete. This could result in the host controller thrashing memory, repeatedly fetching the queue head and executing the transaction to the Hub, which will not complete until after the transaction on the classic bus completes. There are two component fields in a queue head to support the throttling feature: a counter field (NakCnt), and a counter reload field (RL). NakCnt is used by the host controller as one of the criteria to determine whether or not to execute a transaction to the endpoint. There are two operational modes associated with this counter: • Not Used. This mode is set when the RL field is zero. The host controller ignores the NakCnt field for any execution of transactions through a queue head with an RL field of zero. Software must use this selection for interrupt endpoints. • Nak Throttle Mode. This mode is selected when the RL field is non-zero. In this mode, the value in the NakCnt field represents the maximum number of Nak or Nyet responses the host controller will tolerate on each endpoint. In this mode, the HC will decrement the NakCnt field based on the token/handshake criteria listed in Table 30-66 The host controller must reload NakCnt when the endpoint successfully moves data (for example, policy to reward device for moving data). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-132 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-66. NakCnt Field Adjustment Rules Handshake Token Handshake NAK IN/PING OUT Split Complete Split 1 NYET N/A (protocol error) No Action1Start N/A (protocol error) Decrement NakCnt decrement NakCnt decrement NakCnt decrement NakCnt No Action Recommended behavior on this response is to reload NakCnt. In summary, system software enables the counter by setting the reload field (RL) to a non-zero value. The host controller may execute a transaction if NakCnt is non-zero. The host controller will not execute a transaction if NakCnt is zero. The reload mechanism is described in detail in Section Nak Count Reload Control . Note that when all queue heads in the Asynchronous Schedule either exhausts all transfers or all NakCnt's go to zero, then the host controller will detect an empty Asynchronous Schedule and idle schedule traversal (see Section Empty Asynchronous Schedule Detection ). Any time the host controller begins a new traversal of the Asynchronous Schedule, a Start Event is assumed, see Section Asynchronous Schedule Traversal : Start Event . Every time a Start-Event occurs, the Nak Count reload procedure is enabled. 30.8.3.9.1 Nak Count Reload Control When the host controller reaches the Execute Transaction state for a queue head (meaning that it has an active operational state), it checks to determine whether the NakCnt field should be reloaded from RL (see Section Execute Transaction ). If the answer is yes, then RL is copied into NakCnt. After the reload or if the reload is not active, the host controller evaluates whether to execute the transaction. The host controller must reload nak counters (NakCnt see Figure 30-48) in queue heads during the first pass through the reclamation list after an asynchronous schedule Start Event (see Section Asynchronous Schedule Traversal : Start Event for the definition of the Start Event). The Asynchronous Schedule should have at most one queue head marked as the head (see Figure 30-60). Figure 30-62 illustrates an example state machine that satisfies the operational requirements of the host controller detecting the first pass through the Asynchronous Schedule. This state machine is maintained internal to the host controller and is only used to gate reloading of the nak counter during the queue head traversal state: Execute Transaction (Figure 30-62). The host controller does not perform the nak counter reload operation if the RL field (see Figure 30-48) is set to zero. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-133 High-Speed USB On-The-Go (HS USB-OTG) Figure 30-62. Example HC State Machine for Controlling Nak Counter Reloads Wait for List Head This is the initial state. The state machine enters this state from Wait for Start Event when a start event as defined in Section Asynchronous Schedule Traversal : Start Event occurs. The purpose of this state is to wait for the first observation of the head of the Asynchronous Schedule. This occurs when the host controller fetches a queue head whose H-bit is set to a one. Do Reload This state is entered from the Wait for List Head state when the host controller fetches a queue head with the H-bit set to a one. While in this state, the host controller will perform nak counter reloads for every queue head visited that has a non-zero nak reload value (RL) field. Wait for Start Event This state is entered from the Do Reload state when a queue head with the H-bit set to a one is fetched. While in this state, the host controller will not perform nak counter reloads. 30.8.3.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads This section presents an overview of how the host controller interacts with queuing data structures. Queue heads use the Queue Element Transfer Descriptor (qTD) structure. One queue head is used to manage the data stream for one endpoint. The queue head structure contains static endpoint characteristics and capabilities. It also contains a working area from where individual bus transactions for an endpoint are executed (see Overlay area defined in Figure 30-48). Each qTD represents one or more bus transactions, which is defined in the context of this specification as a transfer. The general processing model for the host controller's use of a queue head is simple: • read a queue head, • execute a transaction from the overlay area, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-134 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • write back the results of the transaction to the overlay area move to the next queue head. If the host controller encounters errors during a transaction, the host controller will set one (or more) of the error reporting bits in the queue head's Status field. The Status field accumulates all errors encountered during the execution of a qTD (for example, the error bits in the queue head Status field are 'sticky' until the transfer (qTD) has completed). This state is always written back to the source qTD when the transfer is complete. On transfer (for example, buffer or halt conditions) boundaries, the host controller must auto-advance (without software intervention) to the next qTD. Additionally, the hardware must be able to halt the queue so no additional bus transactions will occur for the endpoint and the host controller will not advance the queue. An example host controller operational state machine of a queue head traversal is illustrated in Figure 30-63. This state machine is a model for how a host controller should traverse a queue head. The host controller must be able to advance the queue from the Fetch QH state in order to avoid all hardware/software race conditions. This simple mechanism allows software to simply link qTDs to the queue head and activate them, then the host controller will always find them if/when they are reachable. Figure 30-63. Host Controller Queue Head Traversal State Machine MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-135 High-Speed USB On-The-Go (HS USB-OTG) This traversal state machine applies to all queue heads, regardless of transfer type or whether split transactions are required. The following sections describe each state. Each state description describes the entry criteria. The Execute Transaction state (Section Execute Transaction ) describes the basic requirements for all endpoints. Sections Split Transactions for Asynchronous Transfers and Split Transaction Interrupt describe details of the required extensions to the Execute Transaction state for endpoints requiring split transactions. Note: Prior to software placing a queue head into either the periodic or asynchronous list, software must ensure the queue head is properly initialized. Minimally, the queue head should be initialized to the following (see Section Queue Head for layout of a queue head): • Valid static endpoint state • For the very first use of a queue head, software may zero-out the queue head transfer overlay, then set the Next qTD Pointer field value to reference a valid qTD. 30.8.3.10.1 Fetch Queue Head A queue head can be referenced from the physical address stored in the ASYNCLISTADDR Register (Section ASYNCLISTADDR; ENDPOINTLISTADDR). Additionally, it may be referenced from the Next Link Pointer field of an iTD, siTD, FSTN or another Queue Head. If the referencing link pointer has the Typ field set to indicate a queue head, it is assumed to reference a queue head structure as defined in Figure 30-48. While in this state, the host controller performs operations to implement empty schedule detection (Section Empty Asynchronous Schedule Detection ) and Nak Counter reloads (Section Operational Model for Nak Counter). After the queue head has been fetched, the host controller conducts the following queries for empty schedule detection: • If queue head is not an interrupt queue head (that is, S-mask is a zero), and • The H-bit is a one, and • The Reclamation bit in the USBSTS register is a zero. When these criteria are met, the host controller will stop traversing the asynchronous list (as described in Section Empty Asynchronous Schedule Detection ). When the criteria are not met, the host controller continues schedule traversal. If the queue head is not an interrupt and the H-bit is a one and the Reclamation bit is a one, then the host controller sets the Reclamation bit in the USBSTS register to a zero before completing this state. The operations for reloading of the Nak Counter are described in detail in Section Operational Model for Nak Counter. This state is complete when the queue head has been read on-chip. 30.8.3.10.2 Advance Queue To advance the queue, the host controller must find the next qTD, adjust pointers, perform the overlay and write back the results to the queue head. This state is entered from the FetchQHD state if the overlay Active and Halt bits are set to zero. On entry to this state, the host controller determines which next pointer to use to fetch a qTD, fetches a qTD and determines whether or not to perform an overlay. Note that if the I-bit is a one and the Active bit is a zero, MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-136 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) the host controller immediately skips processing of this queue head, exits this state and uses the horizontal pointer to the next schedule data structure. If the field Bytes to Transfer is not zero and the T-bit in the Alternate Next qTD Pointer is set to zero, then the host controller uses the Alternate Next qTD Pointer. Otherwise, the host controller uses the Next qTD Pointer. If Next qTD Pointer ’s T-bit is set to a one, then the host controller exits this state and uses the horizontal pointer to the next schedule data structure. Using the selected pointer the host controller fetches the referenced qTD. If the fetched qTD has it’s Active bit set to a one, the host controller moves the pointer value used to reach the qTD (Next or Alternate Next) to the Current qTD Pointer field, then performs the overlay. If the fetched qTD has its Active bit set to a zero, the host controller aborts the queue advance and follows the queue head's horizontal pointer to the next schedule data structure. The host controller performs the overlay based on the following rules: • The value of the data toggle (dt) field in the overlay area depends on the value of the data toggle control (dtc) bit (see Table 30-54). • If the EPS field indicates the endpoint is a high-speed endpoint, the Ping state field is preserved by the host controller. The value of this field is not changed as a result of the overlay. • C-prog-mask field is set to zero (field from incoming qTD is ignored, as is the current contents of the overlay area). • Frame Tag field is set to zero (field from incoming qTD is ignored, as is the current contents of the overlay area). • NakCnt field in the overlay area is loaded from the RL field in the queue head's Static Endpoint State. • All other areas of the overlay are set by the incoming qTD. The host controller exits this state when it has committed the write to the queue head. 30.8.3.10.3 Execute Transaction The host controller enters this state from the Fetch Queue Head state only if the Active bit in Status field of the queue head is set to a one. On entry to this state, the host controller executes a few pre-operations, then checks some pre-condition criteria before committing to executing a transaction for the queue head. The pre-operations performed and the pre-condition criteria depend on whether the queue head is an interrupt endpoint. The host controller can determine that a queue head is an interrupt queue head when the queue head’s S-mask field contains a non-zero value. It is the responsibility of software to ensure the S-mask field is appropriately initialized based on the transfer type. There are other criteria that must be met if the EPS field indicates that the endpoint is a low- or full-speed endpoint, see Sections Split Transactions for Asynchronous Transfers and Split Transaction Interrupt . Interrupt Transfer Pre-condition Criteria If the queue head is for an interrupt endpoint (for example, non-zero S-mask field), then the FRINDEX[2:0] field must identify a bit in the S-mask field that has a one in it. For example, an S-mask value of 00100000b would evaluate to true only when FRINDEX[2:0] is equal to 101b. If this condition is met then the host controller considers this queue head for a transaction. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-137 High-Speed USB On-The-Go (HS USB-OTG) Asynchronous Transfer Pre-Operations and Pre-Condition Criteria If the queue head is not for an interrupt endpoint (for example, a zero S-mask field), then the host controller performs one pre-operation and then evaluates one pre-condition criteria: The pre-operation is: Checks the Nak counter reload state (Section Operational Model for Nak Counter). It may be necessary for the host controller to reload the Nak Counter field. The reload is performed at this time. The pre-condition evaluated is: • Whether or not the NakCnt field has been reloaded, the host controller checks the value of the NakCnt field in the queue head. If NakCnt is non-zero, or if the Reload Nak Counter field is zero, then the host controller considers this queue head for a transaction. Transfer Type Independent Pre-Operations Regardless of the transfer type, the host controller always performs at least one pre-operation and evaluates one pre-condition. The pre-operation is: • A host controller internal transaction (down) counter qHTransactionCounter is loaded from the queue head’s Mult field. A host controller implementation is allowed to ignore this for queue heads on the asynchronous list. It is mandatory for interrupt queue heads. Software should ensure that the Mult field is set appropriately for the transfer type. The pre-conditions evaluated are: • The host controller determines whether there is enough time in the micro-frame to complete this transaction (see Section Transaction Fit - A Best-Fit Approximation Algorithm for an example evaluation method). If there is not enough time to complete the transaction, the host controller exits this state. • If the value of qHTransactionCounter for an interrupt endpoint is zero, then the host controller exits this state. When the pre-operations are complete and pre-conditions are met, the host controller sets the Reclamation bit in the USBSTS register to a one and then begins executing one or more transactions using the endpoint information in the queue head. The host controller iterates qHTransactionCounter times in this state executing transactions. After each transaction is executed, qHTransactionCounter is decremented by one. The host controller will exit this state when one of the following events occurs: • The qHTransactionCounter decrements to zero, or • The endpoint responds to the transaction with any handshake other than an ACK,4 or • The transaction experiences a transaction error, or • The Active bit in the queue head goes to a zero, or • There is not enough time in the micro-frame left to execute the next transaction (see Section Transaction Fit - A Best-Fit Approximation Algorithm for example method for implementing the frame boundary test). 4 Note that for a high-bandwidth interrupt OUT endpoint, the host controller may optionally immediately retry the transaction if it fails. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-138 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) The results of each transaction is recorded in the on-chip overlay area. If data was successfully moved during the transaction, the transfer state in the overlay area is advanced. To advance queue head’s transfer state, the Total Bytes to Transfer field is decremented by the number of bytes moved in the transaction, the data toggle bit (dt) is toggled, the current page offset is advanced to the next appropriate value (for example, advanced by the number of bytes successfully moved), and the C_Page field is updated to the appropriate value (if necessary). See Section Buffer Pointer List Use for Data Streaming with qTDs . Note that the Total Bytes To Transfer field may be zero when all the other criteria for executing a transaction are met. When this occurs, the host controller will execute a zero-length transaction to the endpoint. If the PID_Code field indicates an IN transaction and the device delivers data, the host controller will detect a packet babble condition, set the babble and halted bits in the Status field, set the Active bit to a zero, write back the results to the source qTD, then exit this state. In the event an IN token receives a data PID mismatch response, the host controller must ignore the received data (for example, not advance the transfer state for the bytes received). Additionally, if the endpoint is an interrupt IN, then the host controller must record that the transaction occurred (for example, decrement qHTransactionCounter). It is recommended (but not required) the host controller continue executing transactions for this endpoint if the resultant value of qHTransactionCounter is greater than one. If the response to the IN bus transaction is a Nak (or Nyet) and RL is non-zero, NakCnt is decremented by one. If RL is zero, then no write-back by the host controller is required (for a transaction receiving a Nak or Nyet response and the value of CErr did not change). Software should set the RL field to zero if the queue head is an interrupt endpoint. Host controller hardware is not required to enforce this rule or operation. After the transaction has finished and the host controller has completed the post processing of the results (advancing the transfer state and possibly NakCnt, the host controller writes back the results of the transaction to the queue head’s overlay area in main memory. The number of bytes moved during an IN transaction depends on how much data the device endpoint delivers. The maximum number of bytes a device can send is Maximum Packet Size. The number of bytes moved during an OUT transaction is either Maximum Packet Length bytes or Total Bytes to Transfer, whichever is less. If there was a transaction error during the transaction, the transfer state (as defined above) is not advanced by the host controller. The CErr field is decremented by one and the status field is updated to reflect the type of error observed. Transaction errors are summarized in Section Transaction Error . The following events will cause the host controller to clear the Active bit in the queue head’s overlay status field. When the Active bit transitions from a one to a zero, the transfer in the overlay is considered complete. The reason for the transfer completion (clearing the Active bit) determines the next state. • CErr field decrements to zero. When this occurs the Halted bit is set to a one and Active is set to a zero. This results in the hardware not advancing the queue and the pipe halts. Software must intercede to recover. • The device responds to the transaction with a STALL PID. When this occurs, the Halted bit is set to a one and the Active bit is set to a zero. This results in the hardware not advancing the queue and the pipe halts. Software must intercede to recover. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-139 High-Speed USB On-The-Go (HS USB-OTG) • • The Total Bytes to Transfer field is zero after the transaction completes. Note that for a zero length transaction, it was zero before the transaction was started. When this condition occurs, the Active bit is set to zero. The PID code is an IN, and the number of bytes moved during the transaction is less than the Maximum Packet Length. When this occurs, the Active bit is set to zero and a short packet condition exists. The short-packet condition is detected during the Advance Queue state. Refer to Section Split Transactions for additional rules for managing low- and full-speed transactions. With the exception of a NAK response (when RL field is zero), the host controller always writes the results of the transaction back to the overlay area in main memory. This includes when the transfer completes. For a high-speed endpoint, the queue head information written back includes minimally the following fields: The PID Code field indicates an IN and the device sends more than the expected number of bytes (e.g. Maximum Packet Length or Total Bytes to Transfer bytes, whichever is less) (e.g. a packet babble). This results in the host controller setting the Halted bit to a one. • NakCnt, dt, Total Bytes to Transfer, C_Page, Status, CERR, and Current Offset For a low- or full-speed device the queue head information written back also includes the fields: • C-prog-mask, FrameTag and S-bytes. The duration of this state depends on the time it takes to complete the transaction(s) and the status write to the overlay is committed. Halting a Queue Head A halted endpoint is defined only for the transfer types that are managed via queue heads (control, bulk and interrupt). The following events indicate that the endpoint has reached a condition where no more activity can occur without intervention from the driver: • An endpoint may return a STALL handshake during a transaction, • A transaction had three consecutive error conditions, or • A Packet Babble error occurs on the endpoint. When any of these events occur (for a queue head) the Host Controller halts the queue head and set the USBERRINT status bit in the USBSTS register to a one. To halt the queue head, the Active bit is set to a zero and the Halted bit is set to a one. There may be other error status bits that are set when a queue is halted. The host controller always writes back the overlay area to the source qTD when the transfer is complete, regardless of the reason (normal completion, short packet or halt). The host controller will not advance the transfer state on a transaction that results in a Halt condition (e.g. no updates necessary for Total Bytes to Transfer, C_Page, Current Offset, and dt). The host controller must update CErr as appropriate. When a queue head is halted, the USB Error Interrupt bit in the USBSTS register is set to a one. If the USB Error Interrupt Enable bit in the USBINTR register is set to a one, a hardware interrupt is generated at the next interrupt threshold. Asynchronous Schedule Park Mode Asynchronous Schedule Park mode is a special execution mode that can be enabled by system software, where the host controller is permitted to execute more than one bus transaction from a high-speed queue head in the Asynchronous schedule before continuing horizontal traversal of the Asynchronous schedule. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-140 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) This feature has no effect on queue heads or other data structures in the Periodic schedule. This feature is similar in intent as the Mult feature that is used in the Periodic schedule. Where-as the Mult feature is a characteristic that is tunable for each endpoint; park-mode is a policy that is applied to all high-speed queue heads in the asynchronous schedule. It is essentially the specification of an iterator for consecutive bus transactions to the same endpoint. All of the rules for managing bus transactions and the results of those as defined in Section Execute Transaction apply. This feature merely specifies how many consecutive times the host controller is permitted to execute from the same queue head before moving to the next queue head in the Asynchronous List. This feature should allow the host controller to attain better bus utilization for those devices that are capable of moving data at maximum rate, while at the same time providing a fair service to all endpoints. A host controller exports its capability to support this feature to system software by setting the Asynchronous Schedule Park Capability bit in the HCCPARAMs register to a one. This information keys system software that the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register are modifiable. System software enables the feature by writing a one to the Asynchronous Schedule Park Mode Enable bit. When park-mode is not enabled (e.g. Asynchronous Schedule Park Mode Enable bit in the USBCMD register is a zero), the host controller must not execute more than one bus transaction per high-speed queue head, per traversal of the asynchronous schedule. When park-mode is enabled, the host controller must not apply the feature to a queue head whose EPS field indicates a Low/Full-speed device (i.e. only one bus transaction is allowed from each Low/Full-speed queue head per traversal of the asynchronous schedule). Park-mode may only be applied to queue heads in the Asynchronous schedule whose EPS field indicates that it is a high-speed device. The host controller must apply park mode to queue heads whose EPS field indicates a high-speed endpoint. The maximum number of consecutive bus transactions a host controller may execute on a high-speed queue head is determined by the value in the Asynchronous Schedule Park Mode Count field in the USBCMD register. Software must not set Asynchronous Schedule Park Mode Enable bit to a one and also set Asynchronous Schedule Park Mode Count field to a zero. The resulting behavior is not defined. An example behavioral example describes the operational requirements for the host controller implementing park-mode. This feature does not affect how the host controller handles the bus transaction as defined in Section Execute Transaction . It only effects how many consecutive bus transactions for the current queue head can be executed. All boundary conditions, error detection and reporting applies as usual. This feature is similar in concept to the use of the Mult field for high-bandwidth Interrupt for queue heads in the Periodic Schedule. The host controller effectively loads an internal down-counter PM-Count from Asynchronous Schedule Park Mode Count when Asyncrhonous Schedule Park Mode Enable bit is a one, and a high-speed queue head is first fetched and meets all the criteria for executing a bus transaction. After the bus transaction, PM-Count is decremented. The host controller may continue to execute bus transactions from the current queue head until PM-Count goes to zero, an error is detected, the buffer for the current transfer is exhausted or the endpoint responds with a flow-control or STALL handshake. Table 30-67 summarizes the responses that effect whether the host controller continues with another bus transaction for the current queue head. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-141 High-Speed USB On-The-Go (HS USB-OTG) Table 30-67. Actions for Park Mode, based on Endpoint Response and Residual Transfer State PID Endpoint Response Transfer State after Transaction Action PM-Count Bytes to Transfer Not Zero Zero Don’t care Don’t care Don’t care Don’t care Not Zero Zero Don’t’ care Don’t care Don’t care Not Zero Don’t care Don’t care Allowed to perform another bus transaction.1,2 Retire qTD and move to next QH Move to next QH. Retire qTD and move to next QH. Move to next QH. Move to next QH. Allowed to perform another bus transaction. 2 Retire qTD and move to next QH Move to next QH. Move to next QH. Move to next QH Allowed to perform another bus transaction. 2 Move to next QH Move to next QH IN DATA[0,1] w/Maximum Packet sized data Not zero Not zero Zero DATA[0,1] w/short packet NAK STALL, XactErr OUT ACK Don’t care Don’t care Don’t care Not zero Not zero Zero NYET, NAK STALL, XactErr PING ACK NAK STALL, XactErr 1 Don’t care Don’t care Not Zero Don’t care Don’t care Note, the host controller may continue to execute bus transactions from the current high-speed queue head (if PM-Count is not equal to zero), if a PID mismatch is detected (e.g. expected DATA1 and received DATA0, or visa-versa)., 2 Note, this specification does not require that the host controller execute another bus transaction when PM-Count is non-zero. Implementations are encouraged to make appropriate complexity and performance trade-offs. 30.8.3.10.4 Write Back qTD This state is entered from the Execute Transaction state when the Active bit is set to a zero. The source data for the write-back is the transfer results area of the queue head overlay area (see Figure 30-48). The host controller uses the Current qTD Pointer field as the target address for the qTD. The queue head transfer result area is written back to the transfer result area of the target qTD. This state is also referred to as: qTD retirement. The fields that must be written back to the source qTD include Total Bytes to Transfer, Cerr, and Status. The duration of this state depends on when the qTD write-back has been committed. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-142 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.3.10.5 Follow Queue Head Horizontal Pointer The host controller must use the horizontal pointer in the queue head to the next schedule data structure when any of the following conditions exist: • If the Active bit is a one on exit from the Execute Transaction state, or • When the host controller exits the Write Back qTD state, or • If the Advance Queue state fails to advance the queue because the target qTD is not active, or • If the Halted bit is a one on exit from the Fetch QH state. There is no functional requirement that the host controller wait until the current transaction is complete before using the horizontal pointer to read the next linked data structure. However, it must wait until the current transaction is complete before executing the next data structure. 30.8.3.10.6 Buffer Pointer List Use for Data Streaming with qTDs A qTD has an array of buffer pointers, which is used to reference the data buffer for a transfer. This specification requires that the buffer associated with the transfer be virtually contiguous. This means: if the buffer spans more than one physical page, it must obey the following rules (Figure 30-64 illustrates an example): • The first portion of the buffer must begin at some offset in a page and extend through the end of the page. • The remaining buffer cannot be allocated in small chunks scattered around memory. For each 4K chunk beyond the first page, each buffer portion matches to a full 4K page. The final portion, which may only be large enough to occupy a portion of a page, must start at the top of the page and be contiguous within that page. The buffer pointer list in the qTD is long enough to support a maximum transfer size of 20K bytes. This case occurs when all five buffer pointers are used and the first offset is zero. A qTD handles a 16Kbyte buffer with any starting buffer alignment. The host controller uses the field C_Page field as an index value to determine which buffer pointer in the list should be used to start the current transaction. The host controller uses a different buffer pointer for each physical page of the buffer. This is always true, even if the buffer is physically contiguous. The host controller must detect when the current transaction will span a page boundary and automatically move to the next available buffer pointer in the page pointer list. The next available pointer is reached by incrementing C_Page and pulling the next page pointer from the list. Software must ensure there are sufficient buffer pointers to move the amount of data specified in the Bytes to Transfer field. Figure 30-64 illustrates a nominal example of how System software would initialize the buffer pointers list and the C_Page field for a transfer size of 16383 bytes. C_Page is set to zero. The upper 20-bits of Page 0 references the start of the physical page. Current Offset (the lower 12-bits of queue head Dword 7) holds the offset in the page e.g. 2049 (e.g. 4096-2047). The remaining page pointers are set to reference the beginning of each subsequent 4K page. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-143 High-Speed USB On-The-Go (HS USB-OTG) Figure 30-64. Example Mapping of qTD Buffer Pointers to Buffer Pages For the first transaction on the qTD (assuming a 512-byte transaction), the host controller uses the first buffer pointer (page 0 because C_Page is set to zero) and concatenates the Current Offset field. The 512 bytes are moved during the transaction, the Current Offset and Total Bytes to Transfer are adjusted by 512 and written back to the queue head working area. During the 4th transaction, the host controller needs 511 bytes in page 0 and one byte in page 1. The host controller will increment C_Page (to 1) and use the page 1 pointer to move the final byte of the transaction. After the 4th transaction, the active page pointer is the page 1 pointer and Current Offset has rolled to one, and both are written back to the overlay area. The transactions continue for the rest of the buffer, with the host controller automatically moving to the next page pointer (i.e. C_Page) when necessary. There are three conditions for how the host controller handles C_Page. • The current transaction does not span a page boundary. The value of C_Page is not adjusted by the host controller. • The current transaction does span a page boundary. The host controller must detect the page cross condition and advance to the next buffer while streaming data to/from the USB. • The current transaction completes on a page boundary (i.e. the last byte moved for the current transaction is the last byte in the page for the current page pointer). The host controller must increment C_Page before writing back status for the transaction. Note that the only valid adjustment the host controller may make to C_Page is to increment by one. 30.8.3.10.7 Adding Interrupt Queue Heads to the Periodic Schedule The link path(s) from the periodic frame list to a queue head establishes in which frames a transaction can be executed for the queue head. Queue heads are linked into the periodic schedule so they are polled at the appropriate rate. System software sets a bit in a queue head's S-Mask to indicate which micro-frame with-in a 1 millisecond period a transaction should be executed for the queue head. Software must ensure MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-144 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) that all queue heads in the periodic schedule have S-Mask set to a non-zero value. An S-mask with a zero value in the context of the periodic schedule yields undefined results. If the desired poll rate is greater than one frame, system software can use a combination of queue head linking and S-Mask values to spread interrupts of equal poll rates through the schedule so that the periodic bandwidth is allocated and managed in the most efficient manner possible. Some examples are illustrated in Table 30-68. Table 30-68. Example Periodic Reference Patterns for Interrupt Transfers with 2ms Poll Rate Frame # Reference Sequence 0, 2, 4, 6, 8, etc. S-Mask = 01h Description A queue head for the bInterval of 2 milliseconds (16 micro-frames) is linked into the periodic schedule so that it is reachable from the periodic frame list locations indicated in the previous column. In addition, the S-Mask field in the queue head is set to 01h, indicating that the transaction for the endpoint should be executed on the bus during micro-frame 0 of the frame. Another example of a queue head with a bInterval of 2 milliseconds is linked into the periodic frame list at exactly the same interval as the previous example. However, the S-Mask is set to 02h indicating that the transaction for the endpoint should be executed on the bus during micro-frame 1 of the frame. 0, 2, 4, 6, 8, etc. S-Mask = 02h 30.8.3.10.8 Managing Transfer Complete Interrupts from Queue Heads The host controller will set an interrupt to be signaled at the next interrupt threshold when the completed transfer (qTD) has an Interrupt on Complete (IOC) bit set to a one, or whenever a transfer (qTD) completes with a short packet. If system software needs multiple qTDs to complete a client request (i.e. like a control transfer) the intermediate qTDs do not require interrupts. System software may only need a single interrupt to notify it that the complete buffer has been transferred. System software may set IOC's to occur more frequently. A motivation for this may be that it wants early notification so that interface data structures can be re-used in a timely manner. 30.8.3.11 Ping Control USB 2.0 defines an addition to the protocol for high-speed devices called Ping. Ping is required for all USB 2.0 High-speed bulk and control endpoints. Ping is not allowed for a split-transaction stream. This extension to the protocol eliminates the bad side-effects of Naking OUT endpoints. The Status field has a Ping State bit, which the host controller uses to determine the next actual PID it will use in the next transaction to the endpoint (see Table 30-51). The Ping State bit is only managed by the host controller for queue heads that meet the following criteria: • Queue head is not an interrupt and • EPS field equals High-Speed and • PIDCode field equals OUT MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-145 High-Speed USB On-The-Go (HS USB-OTG) Table 30-69 illustrates the state transition table for the host controller's responsibility for maintaining the PING protocol. Refer to Chapter 8 in the USB Specification Revision 2.0 for detailed description on the Ping protocol. Table 30-69. Ping Control State Transition Table Event Current Do Ping Do Ping Do Ping Do Ping OUT Do OUT Do OUT Do OUT Do OUT 1 2 Host PING PING PING PING OUT OUT OUT OUT OUT Nak Ack Device Do Ping Next Do OUT Do Ping N/C2 Do Do Ping Do Ping Do OUT Do Ping N/C2 XactErr1 Stall Nak Nyet Ack XactErr1 Stall Transaction Error (XactErr) is any time the host misses the handshake. No transition change required for the Ping State bit. The Stall handshake results in the endpoint being halted (e.g. Active set to zero and Halt set to a one). Software intervention is required to restart queue. 3 A Nyet response to an OUT means that the device has accepted the data, but cannot receive any more at this time. Host must advance the transfer state and additionally, transition the Ping State bit to Do Ping. The Ping State bit has the following encoding: Value 0B 1B Meaning Do OUT The host controller will use an OUT PID during the next bus transaction to this endpoint. Do Ping The host controller will use a PING PID during the next bus transaction to this endpoint. The defined ping protocol (see USB 2.0 Specification, Chapter 8) allows the host to be imprecise on the initialization of the ping protocol (i.e. start in Do OUT when we don't know whether there is space on the device or not). The host controller manages the Ping State bit. System software sets the initial value in the queue head when it initializes a queue head. The host controller preserves the Ping State bit across all queue advancements. This means that when a new qTD is written into the queue head overlay area, the previous value of the Ping State bit is preserved. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-146 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.3.12 Split Transactions USB 2.0 defines extensions to the bus protocol for managing USB 1.x data streams through USB 2.0 Hubs. This section describes how the host controller uses the interface data structures to manage data streams with full- and low-speed devices, connected below USB 2.0 hub, utilizing the split transaction protocol. Refer to USB 2.0 Specification for the complete definition of the split transaction protocol. Full- and Low-speed devices are enumerated identically as high-speed devices, but the transactions to the Full- and Low-speed endpoints use the split-transaction protocol on the high-speed bus. The split transaction protocol is an encapsulation of (or wrapper around) the Full- or Low-speed transaction. The high-speed wrapper portion of the protocol is addressed to the USB 2.0 Hub and Transaction Translator below which the Full- or Low-speed device is attached. The EHCI interface uses dedicated data structures for managing full-speed isochronous data streams (see Section Split Transaction Isochronous Transfer Descriptor (siTD)). Control, Bulk and Interrupt are managed using the queuing data structures (see Sections Queue Head). The interface data structures need to be programmed with the device address and the Transaction Translator number of the USB 2.0 Hub operating as the Low-/Full-speed host controller for this link. The following sections describe the details of how the host controller must process and manage the split transaction protocol. 30.8.3.12.1 Split Transactions for Asynchronous Transfers A queue head in the asynchronous schedule with an EPS field indicating a full-or low-speed device indicates to the host controller that it must use split transactions to stream data for this queue head. All full-speed bulk and full-, low-speed control are managed via queue heads in the asynchronous schedule. Software must initialize the queue head with the appropriate device address and port number for the transaction translator that is serving as the full/low-speed host controller for the links connecting the endpoint. Software must also initialize the split transaction state bit (SplitXState) to Do-Start-Split. Finally, if the endpoint is a control endpoint, then system software must set the Control Transfer Type (C) bit in the queue head to a one. If this is not a control transfer type endpoint, the C bit must be initialized by software to be a zero. This information is used by the host controller to properly set the Endpoint Type (ET) field in the split transaction bus token. When the C bit is a zero, the split transaction token's ET field is set to indicate a bulk endpoint. When the C bit is a one, the split transaction token's ET field is set to indicate a control endpoint. Refer to Chapter 8 of USB Specification Revision 2.0 for details. Figure 30-65. Host Controller Asynchronous Schedule Split-Transaction State Machine MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-147 High-Speed USB On-The-Go (HS USB-OTG) Asynchronous - Do Start Split This is the state which software must initialize a full- or low-speed asynchronous queue head. This state is entered from the Do Complete Split state only after a complete-split transaction receives a valid response from the transaction translator that is not a Nyet handshake. For queue heads in this state, the host controller will execute a start-split transaction to the appropriate transaction translator. If the bus transaction completes without an error and PidCode indicates an IN or OUT transaction, then the host controller will reload the error counter (CErr). If it is a successful bus transaction and the PidCode indicates a SETUP, the host controller will not reload the error counter. If the transaction translator responds with a Nak, the queue head is left in this state, and the host controller proceeds to the next queue head in the asynchronous schedule. If the host controller times out the transaction (no response, or bad response) the host controller decrements Cerr and proceeds to the next queue head in the asynchronous schedule. Asynchronous - Do Complete Split This state is entered from the Do Start Split state only after a start-split transaction receives an Ack handshake from the transaction translator. For queue heads in this state, the host controller will execute a complete-split transaction to the appropriate transaction translator. If the transaction translator responds with a Nyet handshake, the queue head is left in this state, the error counter is reset and the host controller proceeds to the next queue head in the asynchronous schedule. When a Nyet handshake is received for a bus transaction where the queue head’s PidCode indicates an IN or OUT, the host controller will reload the error counter (CErr). When a Nyet handshake is received for a complete-split bus transaction where the queue head’s PidCode indicates a SETUP, the host controller must not adjust the value of CErr. Independent of PIDCode, the following responses have the effects: • Transaction Error (XactErr). Timeout or data CRC failure, etc. The error counter (Cerr) is decremented by one and the complete split transaction is immediately retried (if possible). If there is not enough time in the micro-frame to execute the retry, the host controller MUST ensure that the next time the host controller begins executing from the Asynchronous schedule, it must begin executing from this queue head. If another start-split (for some other endpoint) is sent to the transaction translator before the complete-split is really completed, the transaction translator could dump the results (which were never delivered to the host). This is why the core specification states the retries must be immediate. A method to accomplish this behavior is to not advance the asynchronous schedule. When the host controller returns to the asynchronous schedule in the next micro-frame, the first transaction from the schedule will be the retry for this endpoint. If Cerr went to zero, the host controller must halt the queue. • NAK. The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not advanced and the state is exited. If the PidCode is a SETUP, then the Nak response is a protocol error. The XactErr status bit is set to a one and the CErr field is decremented. • STALL. The target endpoint responded with a STALL handshake. The host controller sets the halt bit in the status byte, retires the qTD but does not attempt to advance the queue. • If the PidCode indicates an IN, then any of following responses are expected: MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-148 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • • • DATA0/1. On reception of data, the host controller ensures the PID matches the expected data toggle and checks CRC. If the packet is good, the host controller will advance the state of the transfer, e.g. move the data pointer by the number of bytes received, decrement BytesToTransfer field by the number of bytes received, and toggle the dt bit. The host controller will then exit this state. The response and advancement of transfer may trigger other processing events, such as retirement of the qTD and advancement of the queue. If the data sequence PID does not match the expected, the data is ignored, the transfer state is not advanced and this state is exited. If the PidCode indicates an OUT/SETUP, then any of following responses are expected: ACK. The target endpoint accepted the data, so the host controller must advance the state of the transfer. The Current Offset field is incremented by Maximum Packet Length or Bytes to Transfer, whichever is less. The field Bytes To Transfer is decremented by the same amount and the data toggle bit (dt) is toggled. The host controller will then exit this state. Advancing the transfer state may cause other processing events such as retirement of the qTD and advancement of the queue (see Section Managing Control/Bulk/Interrupt Transfers via Queue Heads). Split Transaction Interrupt 30.8.3.12.2 Split-transaction Interrupt-IN/OUT endpoints are managed via the same data structures used for high-speed interrupt endpoints. They both co-exist in the periodic schedule. Queue heads/qTDs offer the set of features required for reliable data delivery, which is characteristic to interrupt transfer types. The split-transaction protocol is managed completely within this defined functional transfer framework. For example, for a high-speed endpoint, the host controller will visit a queue head, execute a high-speed transaction (if criteria are met) and advance the transfer state (or not) depending on the results of the entire transaction. For low- and full-speed endpoints, the details of the execution phase are different (i.e. takes more than one bus transaction to complete), but the remainder of the operational framework is intact. This means that the transfer advancement, etc. occurs as defined in Section Managing Control/Bulk/Interrupt Transfers via Queue Heads, but only occurs on the completion of a split transaction. Split Transaction Scheduling Mechanisms for Interrupt Full- and low-speed Interrupt queue heads have an EPS field indicating full- or low-speed and have a non-zero S-mask field. The host controller can detect this combination of parameters and assume the endpoint is a periodic endpoint. Low- and full-speed interrupt queue heads require the use of the split transaction protocol. The host controller sets the Endpoint Type (ET) field in the split token to indicate the transaction is an interrupt. These transactions are managed through a transaction translator's periodic pipeline. Software should not set these fields to indicate the queue head is an interrupt unless the queue head is used in the periodic schedule. System software manages the per/transaction translator periodic pipeline by budgeting and scheduling exactly during which micro-frames the start-splits and complete-splits for each endpoint will occur. The characteristics of the transaction translator are such that the high-speed transaction protocol must execute during explicit micro-frames, or the data or response information in the pipeline is lost. Figure illustrates the general scheduling boundary conditions that are supported by the EHCI periodic schedule and queue MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-149 High-Speed USB On-The-Go (HS USB-OTG) head data structure. The S and CX labels indicate micro-frames where software can schedule strt-splits and complete splits (respectively). Figure 30-66. Split Transaction, Interrupt Scheduling Boundary Conditions The scheduling cases are: • Case 1: The normal scheduling case is where the entire split transaction is completely bounded by a frame (H-Frame in this case). • Case 2a through Case 2c: The USB 2.0 Hub pipeline rules states clearly, when and how many complete-splits must be scheduled to account for earliest to latest execution on the full/low-speed link. The complete-splits may span the H-Frame boundary when the start-split is in micro-frame 4 or later. When this occurs, the H-Frame to B-Frame alignment requires that the queue head be reachable from consecutive periodic frame list locations. System software cannot build an efficient schedule that satisfies this requirement unless it uses FSTNs. Figure 30-67 illustrates the general layout of the periodic schedule. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-150 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Figure 30-67. General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading The periodic frame list is effectively the leaf level a binary tree, which is always traversed leaf to root. Each level in the tree corresponds to a 2N poll rate. Software can efficiently manage periodic bandwidth on the USB by spreading interrupt queue heads that have the same poll rate requirement across all the available paths from the frame list. For example, system software can schedule eight poll rate 8 queue heads and account for them once in the high-speed bus bandwidth allocation. When an endpoint is allocated an execution footprint that spans a frame boundary, the queue head for the endpoint must be reachable from consecutive locations in the frame list. An example would be if 80b where such an endpoint. Without additional support on the interface, to get 80b reachable at the correct time, software would have to link 81 to 80b. It would then have to move 41 and everything linked after into the same path as 40. This upsets the integrity of the binary tree and disallows the use of the spreading technique. FSTN data structures are used to preserve the integrity of the binary-tree structure and enable the use of the spreading technique. Section Host Controller Operational Model for FSTNs defines the hardware and software operational model requirements for using FSTNs. The following queue head fields are initialized by system software to instruct the host controller when to execute portions of the split-transaction protocol. • SplitXState. This is a single bit residing in the Status field of a queue head (see Table 30-51). This bit is used to track the current state of the split transaction. • Frame S-mask. This is a bit-field where-in system software sets a bit corresponding to the micro-frame (within an H-Frame) that the host controller should execute a start-split transaction. This is always qualified by the value of the SplitXState bit in the Status field of the queue head. For example, referring to Figure , case one, the S-mask would have a value of 00000001b indicating that if the queue head is traversed by the host controller, and the SplitXState indicates Do_Start, and the current micro-frame as indicated by FRINDEX[2:0] is 0, then execute a start-split transaction. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-151 High-Speed USB On-The-Go (HS USB-OTG) • Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the micro-frames (within an H-Frame) that the host controller should execute complete-split transactions. The interpretation of this field is always qualified by the value of the SplitXState bit in the Status field of the queue head. For example, referring to Figure , case one, the C-mask would have a value of 00011100b indicating that if the queue head is traversed by the host controller, and the SplitXState indicates Do_Complete, and the current micro-frame as indicated by FRINDEX[2:0] is 2, 3, or 4, then execute a complete-split transaction. It is software's responsibility to ensure that the translation between H-Frames and B-Frames is correctly performed when setting bits in S-mask and C-mask Host Controller Operational Model for FSTNs The FSTN data structure is used to manage Low/Full-speed interrupt queue heads that need to be reached from consecutive frame list locations (i.e. boundary cases 2a through 2c). An FSTN is essentially a back pointer, similar in intent to the back pointer field in the siTD data structure (see Section siTD Back Link Pointer). This feature provides software a simple primitive to save a schedule position, redirect the host controller to traverse the necessary queue heads in the previous frame, then restore the original schedule position and complete normal traversal. There are four components to the use of FSTNs: • FSTN data structure. • A Save Place indicator. This is always an FSTN with its Back Path Link Pointer. T-bit set to zero. • A Restore indicator. This is always an FSTN with its Back Path Link Pointer.T-bit set to a one. • Host controller FSTN traversal rules. Host Controller Operational Model for FSTNs When the host controller encounters an FSTN during micro-frames 2 through 7 it simply follows the node’s Normal Path Link Pointer to access the next schedule data structure. Note that the FSTN’s Normal Path Link Pointer.T-bit may set to a one, which the host controller must interpret as the end of periodic list mark. When the host controller encounters a Save-Place FSTN in micro-frames 0 or 1, it will save the value of the Normal Path Link Pointer and set an internal flag indicating that it is executing in Recovery Path mode. Recovery Path mode modifies the host controller’s rules for how it traverses the schedule and limits which data structures will be considered for execution of bus transactions. The host controller continues executing in Recovery Path mode until it encounters a Restore FSTN or it determines that it has reached the end of the micro-frame (see details in the list below). The rules for schedule traversal and limited execution while in Recovery Path mode are: • Always follow the Normal Path Link Pointer when it encounters an FSTN that is a Save-Place indicator. The host controller must not recursively follow Save-Place FSTNs. Therefore, while executing in Recovery Path mode, it must never follow an FSTN’s Back Path Link Pointer. • Do not process an siTD or, iTD data structure. Simply follow its Next Link Pointer. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-152 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • • • Do not process a QH (Queue Head) whose EPS field indicates a high-speed device. Simply follow its Horizontal Link Pointer. When a QH’s EPS field indicates a Full/Low-speed device, the host controller will only consider it for execution if its SplitXState is DoComplete (note: this applies whether the PID Code indicates an IN or an OUT). See Sections Execute Transaction and Tracking Split Transaction Progress for Interrupt Transfers for a complete list of additional conditions that must be met in general for the host controller to issue a bus transaction. Note that the host controller must not execute a Start-split transaction while executing in Recovery Path mode. See Section Periodic Interrupt - Do Complete Split for special handling when in Recovery Path mode. Stop traversing the recovery path when it encounters an FSTN that is a Restore indicator. The host controller unconditionally uses the saved value of the Save-Place FSTN’s Normal Path Link Pointer when returning to the normal path traversal. The host controller must clear the context of executing a Recovery Path when it restores schedule traversal to the Save-Place FSTN’s Normal Path Link Pointer. If the host controller determines that there is not enough time left in the micro-frame to complete processing of the periodic schedule, it abandons traversal of the recovery path, and clears the context of executing a recovery path. The result is that at the start of the next consecutive micro-frame, the host controller starts traversal at the frame list. An example traversal of a periodic schedule that includes FSTNs is illustrated in Figure 30-68. Figure 30-68. Example Host Controller Traversal of Recovery Path via FSTNs In frame N+1 (micro-frames 0 and 1), when the host controller encounters Save-Path FSTN (Save-N), it observes that Save-N.Back Path Link Pointer.T-bit is zero (definition of a Save-Path indicator). The host controller saves the value of Save-N.Normal Path Link Pointer and follows Save-N.Back Path Link Pointer. At the same time, it sets an internal flag indicating that it is now in Recovery Path mode (the recovery path is annotated in Figure 30-9 with a large dashed line). The host controller continues traversing data structures on the recovery path and executing only those bus transactions as noted above, on the recovery path until it reaches Restore FSTN (Restore-N). Restore-N.Back Path Link Pointer.T-bit is set to a one (definition of a Restore indicator), so the host controller exits Recovery Path mode by clearing the internal Recovery Path mode flag and commences (restores) schedule traversal using the MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-153 High-Speed USB On-The-Go (HS USB-OTG) saved value of the Save-Place FSTN’s Normal Path Link Pointer (e.g. Save-N.Normal Path Link Pointer). The nodes traversed during these micro-frames include: {83.0, 83.1, 83.2, Save-A, 82.2, 82.3, 42, 20, Restore-N, 43, 21, Restore-N, 10 …}. The nodes on the recovery-path are bolded.In frame N (micro-frames 0-7), for this example, the host controller will traverse all of the schedule data structures utilizing the Normal Path Link Pointers in any FSTNs it encounters. This is because the host controller has not yet encountered a Save-Place FSTN so it not executing in Recovery Path mode. When it encounters the Restore FSTN, (Restore-N), during micro-frames 0 and 1, it uses Restore-N.Normal Path Link Pointer to traverse to the next data structure (i.e. normal schedule traversal). This is because the host controller must use a Restore FSTN’s Normal Path Link Pointer when not executing in a Recovery-Path mode. The nodes traversed during frame N include: {82.0, 82.1, 82.2, 82.3, 42, 20, Restore-N, 10 …}. In frame N+1 (micro-frames 2-7), when the host controller encounters Save-Path FSTN Save-N, it will unconditionally follow Save-N.Normal Path Link Pointer. The nodes traversed during these micro-frames include: {83.0, 83.1, 83.2, Save-A, 43, 21, Restore-N, 10 …}. Software Operational Model for FSTNs Software must create a consistent, coherent schedule for the host controller to traverse. When using FSTNs, system software must adhere to the following rules: • Each Save-Place indicator requires a matching Restore indicator. — The Save-Place indicator is an FSTN with a valid Back Path Link Pointer and T-bit equal to zero. Note that Back Path Link Pointer.Typ field must be set to indicate the referenced data structure is a queue head. The Restore indicator is an FSTN with its Back Path Link Pointer.T-bit set to a one. — A Restore FSTN may be matched to one or more Save-Place FSTNs. For example, if the schedule includes a poll-rate 1 level, then system software only needs to place a Restore FSTN at the beginning of this list in order to match all possible Save-Place FSTNs. • If the schedule does not have elements linked at a poll-rate level of one, and one or more Save-Place FSTNs are used, then System Software must ensure the Restore FSTN’s Normal Path Link Pointer ’s T-bit is set to a one, as this will be use to mark the end of the periodic list. • When the schedule does have elements linked at a poll rate level of one, a Restore FSTN must be the first data structure on the poll rate one list. All traversal paths from the frame list converge on the poll-rate one list. System software must ensure that Recovery Path mode is exited before the host controller is allowed to traverse the poll rate level one list. • A Save-Place FSTN’s Back Path Link Pointer must reference a queue head data structure. The referenced queue head must be reachable from the previous frame list location. In other words, if the Save-Place FSTN is reachable from frame list offset N, then the FSTN’s Back Path Link Pointer must reference a queue head that is reachable from frame list offset N-1. Software should make the schedule as efficient as possible. What this means in this context is that software should have no more than one Save-Place FSTN reachable in any single frame. Note there will be times when two (or more, depending on the implementation) could exist as full/low-speed footprints change with bandwidth adjustments. This could occur, for example when a bandwidth rebalance causes system software to move the Save-Place FSTN from one poll rate level to another. During the transition, software must preserve the integrity of the previous schedule until the new schedule is in place. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-154 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Tracking Split Transaction Progress for Interrupt Transfers To correctly maintain the data stream, the host controller must be able to detect and report errors where data is lost. For interrupt-IN transfers, data is lost when it makes it into the USB 2.0 hub, but the USB 2.0 host system is unable to get it from the USB 2.0 Hub and into the system before it expires from the transaction translator pipeline. When a lost data condition is detected, the queue must be halted, thus signaling system software to recover from the error. A data-loss condition exists whenever a start-split is issued, accepted and successfully executed by the USB 2.0 Hub, but the complete-splits get unrecoverable errors on the high-speed link, or the complete-splits do not occur at the correct times. One reason complete-splits might not occur at the right time would be due to host-induced system hold-offs that cause the host controller to miss bus transactions because it cannot get timely access to the schedule in system memory. The same condition can occur for an interrupt-OUT, but the result is not an endpoint halt condition, but rather effects only the progress of the transfer. The queue head has the following fields to track the progress of each split transaction. These fields are used to keep incremental state about which (and when) portions have been executed. • C-prog-mask. This is an eight-bit bit-vector where the host controller keeps track of which complete-splits have been executed. Due to the nature of the Transaction Translator periodic pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when the complete-splits have not been executed in order. This can only occur due to system hold-offs where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple bit-vector that the host controller sets one of the C-prog-mask bits for each complete-split executed. The bit position is determined by the micro-frame number in which the complete-split was executed. The host controller always checks C-prog-mask before executing a complete-split transaction. If the previous complete-splits have not been executed then it means one (or more) have been skipped and data has potentially been lost. • FrameTag. This field is used by the host controller during the complete-split portion of the split transaction to tag the queue head with the frame number (H-Frame number) when the next complete split must be executed. • S-bytes. This field can be used to store the number of data payload bytes sent during the start-split (if the transaction was an OUT). The S-bytes field must be used to accumulate the data payload bytes received during the complete-splits (for an IN). Split Transaction Execution State Machine for Interrupt In the following presentation, all references to micro-frame are in the context of a micro-frame within an H-Frame. As with asynchronous Full- and Low-speed endpoints, a split-transaction state machine is used to manage the split transaction sequence. Aside from the fields defined in the queue head for scheduling and tracking the split transaction, the host controller calculates one internal mechanism that is also used to manage the split transaction. The internal calculated mechanism is: • cMicroFrameBit. This is a single-bit encoding of the current micro-frame number. It is an eight-bit value calculated by the host controller at the beginning of every micro-frame. It is calculated from the three least significant bits of the FRINDEX register (i.e. cMicroFrameBit = (1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-155 High-Speed USB On-The-Go (HS USB-OTG) shifted-left(FRINDEX[2:0]))). The cMicroFrameBit has at most one bit asserted, which always corresponds to the current micro-frame number. For example, if the current micro-frame is 0, then cMicroFrameBit will equal 00000001b. The variable cMicroFrameBit is used to compare against the S-mask and C-mask fields to determine whether the queue head is marked for a start- or complete-splt transaction for the current micro-frame. Figure 30-69 illustrates the state machine for managing a complete interrupt split transaction. There are two phases to each split transaction. The first is a single start-split transaction, which occurs when the SplitXState is at Do_Start and the single bit in cMicroFrameBit has a corresponding bit active in QH.S-mask. The transaction translator does not acknowledge the receipt of the periodic start-split, so the host controller unconditionally transitions the state to Do_Complete. Due to the available jitter in the transaction translator pipeline, there will be more than one complete-split transaction scheduled by software for the Do_Complete state. This translates simply to the fact that there are multiple bits set to a one in the QH.C-mask field. The host controller keeps the queue head in the Do_Complete state until the split transaction is complete (see definition below), or an error condition triggers the three-strikes-rule (e.g. after the host tries the same transaction three times, and each encounters an error, the host controller will stop retrying the bus transaction and halt the endpoint, thus requiring system software to detect the condition and perform system-dependent recovery). Figure 30-69. Split Transaction State Machine for Interrupt **See Previous Section for the frame tag management rules. Periodic Interrupt - Do Start Split This is the state software must initialize a full- or low-speed interrupt queue head StartXState bit. This state is entered from the Do_Complete Split state only after the split transaction is complete. This occurs when one of the following events occur: The transaction translator responds to a complete-split transaction with one of the following: • NAK. A NAK response is a propagation of the full- or low-speed endpoint's NAK response. • ACK. An ACK response is a propagation of the full- or low-speed endpoint's ACK response. Only occurs on an OUT endpoint. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-156 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • • DATA 0/1. Only occurs for INs. Indicates that this is the last of the data from the endpoint for this split transaction. ERR. The transaction on the low-/full-speed link below the transaction translator had a failure (e.g. timeout, bad CRC, etc.). NYET (and Last). The host controller issued the last complete-split and the transaction translator responded with a NYET handshake. This means that the start-split was not correctly received by the transaction translator, so it never executed a transaction to the full- or low-speed endpoint, see Section Periodic Interrupt - Do Complete Split for the definition of ‘Last’. Each time the host controller visits a queue head in this state (once within the Execute Transaction state), it performs the following test to determine whether to execute a start-split. • QH.S-mask is bit-wise anded with cMicroFrameBit. If the result is non-zero, then the host controller will issue a start-split transaction. If the PIDCode field indicates an IN transaction, the host controller must zero-out the QH.S-bytes field. After the split-transaction has been executed, the host controller sets up state in the queue head to track the progress of the complete-split phase of the split transaction. Specifically, it records the expected frame number into QH.FrameTag field (see Section Managing QH.FrameTag Field ), set C-prog-mask to zero (00h), and exits this state. Note that the host controller must not adjust the value of CErr as a result of completion of a start-split transaction. Periodic Interrupt - Do Complete Split This state is entered unconditionally from the Do Start Split state after a start-split transaction is executed on the bus. Each time the host controller visits a queue head in this state (once within the Execute Transaction state), it checks to determine whether a complete-split transaction should be executed now. There are four tests to determine whether a complete-split transaction should be executed. • Test A. cMicroFrameBit is bit-wise anded with QH.C-mask field. A non-zero result indicates that software scheduled a complete-split for this endpoint, during this micro-frame. • Test B. QH.FrameTag is compared with the current contents of FRINDEX[7:3]. An equal indicates a match. • Test C. The complete-split progress bit vector is checked to determine whether the previous bit is set, indicating that the previous complete-split was appropriately executed. An example algorithm for this test is provided below: Algorithm Boolean CheckPreviousBit(QH.C-prog-mask, QH.C-mask, cMicroFrameBit) Begin -- Return values: -- TRUE - no error -- FALSE - error -Boolean rvalue = TRUE; previousBit = cMicroframeBit logical-rotate-right(1) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-157 High-Speed USB On-The-Go (HS USB-OTG) -- Bit-wise anding previousBit with C-mask indicates -- whether there was an intent -- to send a complete split in the previous micro-frame. So, -- if the -- 'previous bit' is set in C-mask, check C-prog-mask to -- make sure it -- happened. If (previousBit bitAND QH.C-mask)then If not(previousBit bitAND QH.C-prog-mask) then rvalue = FALSE; End if End If -- If the C-prog-mask already has a one in this bit position, -- then an aliasing -- error has occurred. It will probably get caught by the -- FrameTag Test, but -- at any rate it is an error condition that as detectable here -- should not allow -- a transaction to be executed. If (cMicroFrameBit bitAND QH.C-prog-mask) then rvalue = FALSE; End if return (rvalue) End Algorithm • Test D. Check to see if a start-split should be executed in this micro-frame. Note this is the same test performed in the Do Start Split state (see Section Periodic Interrupt - Do Start Split ). Whenever it evaluates to TRUE and the controller is NOT processing in the context of a Recovery Path mode, it means a start-split should occur in this micro-frame. Test D and Test A evaluating to TRUE at the same time is a system software error. Behavior is undefined. If (A .and. B .and. C .and. not(D)) then the host controller will execute a complete-split transaction. When the host controller commits to executing the complete-split transaction, it updates QH.C-prog-mask by bit-ORing with cMicroFrameBit. On completion of the complete-split transaction, the host controller records the result of the transaction in the queue head and sets QH.FrameTag to the expected H-Frame number (see Section Managing QH.FrameTag Field ). The effect to the state of the queue head and thus the state of the transfer depends on the response by the transaction translator to the complete-split MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-158 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) transaction. The following responses have the effects (note that any responses that result in decrementing of the CErr will result in the queue head being halted by the host controller if the result of the decrement is zero): • NYET (and Last). On each NYET response, the host controller checks to determine whether this is the last complete-split for this split transaction. Last is defined in this context as the condition where all of the scheduled complete-splits have been executed. If it is the last complete-split (with a NYET response), then the transfer state of the queue head is not advanced (never received any data) and this state exited. The transaction translator must have responded to all the clompete-splits with NYETs, meaning that the start-split issued by the host controller was not received. The start-split should be retried at the next poll period. • The test for whether this is the Last complete split can be performed by XOR QH.C-mask with QH.C-prog-mask. If the result is all zeros then all complete-splits have been executed. When this condition occurs, the XactErr status bit is set to a one and the CErr field is decremented. • NYET (and not Last). See above description for testing for Last. The complete-split transaction received a NYET response from the transaction translator. Do not update any transfer state (except for C-prog-mask and FrameTag) and stay in this state. The host controller must not adjust CErr on this response. • Transaction Error (XactErr). Timeout, data CRC failure, etc. The CErr field is decremented and the XactErr bit in the Status field is set to a one. The complete split transaction is immediately retried (if Cerr is non-zero).If there is not enough time in the micro-frame to complete the retry and the endpoint is an IN, or CErr is decremented to a zero from a one, the queue is halted. If there is not enough time in the micro-frame to complete the retry and the endpoint is an OUT and CErr is not zero, then this state is exited (i.e. return to Do Start Split). This results in a retry of the entire OUT split transaction, at the next poll period. Refer to Chapter 11 Hubs (specifically the section full- and low-speed Interrupts) in the USB Specification Revision 2.0 for detailed requirements on why these errors must be immediately retried. • ACK. This can only occur if the target endpoint is an OUT. The target endpoint ACK'd the data and this response is a propagation of the endpoint ACK up to the host controller. The host controller must advance the state of the transfer. The Current Offset field is incremented by Maximum Packet Length or Bytes to Transfer, whichever is less. The field Bytes To Transfer is decremented by the same amount. And the data toggle bit (dt) is toggled. The host controller will then exit this state for this queue head. The host controller must reload CErr with maximum value on this response. Advancing the transfer state may cause other process events such as retirement of the qTD and advancement of the queue (see Section Managing Control/Bulk/Interrupt Transfers via Queue Heads). • MDATA. This response will only occur for an IN endpoint. The transaction translator responded with zero or more bytes of data and an MDATA PID. The incremental number of bytes received is accumulated in QH.S-bytes. The host controller must not adjust CErr on this response. • DATA0/1. This response may only occur for an IN endpoint. The number of bytes received is added to the accumulated byte count in QH.S-bytes. The state of the transfer is advanced by the result and the host controller will exit this state for this queue head. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-159 High-Speed USB On-The-Go (HS USB-OTG) • • • • • Advancing the transfer state may cause other processing events such as retirement of the qTD and advancement of the queue (see Section Managing Control/Bulk/Interrupt Transfers via Queue Heads). If the data sequence PID does not match the expected, the entirety of the data received in this split transaction is ignored, the transfer state is not advanced and this state is exited. NAK. The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not advanced, and this state is exited. The host controller must reload CErr with maximum value on this response. ERR. There was an error during the full- or low-speed transaction. The ERR status bit is set to a one, Cerr is decremented, the state of the transfer is not advanced, and this state is exited. STALL. The queue is halted (an exit condition of the Execute Transaction state). The status field bits: Active bit is set to zero and the Halted bit is set to a one and the qTD is retired. Responses which are not enumerated in the list or which are received out of sequence are illegal and may result in undefined host controller behavior. The other possible combinations of tests A, B, C, and D may indicate that data or response was lost. Table 30-70 lists the possible combinations and the appropriate action. Table 30-70. Interrupt IN/OUT Do Complete Split State Execution Criteria Condition not(A) not(D) A not(C) Action Ignore QHD Description Neither a start nor complete-split is scheduled for the current micro-frame.Host controller should continue walking the schedule. Progress bit check failed. These means a complete-split has been missed. There is the possibility of lost data. If PIDCode is an IN, then the Queue head must be halted. If PIDCode is an OUT, then the transfer state is not advanced and the state exited (e.g. start-split is retried). This is a host-induced error and does not effect CERR. In either case, set the Missed Micro-frame bit in the status field to a one. QH.FrameTag test failed. This means that exactly one or more H-Frames have been skipped. This means complete-splits and have missed. There is the possibility of lost data. If PIDCode is an IN, then the Queue head must be halted. If PIDCode is an OUT, then the transfer state is not advanced and the state exited (e.g. start-split is retried). This is a host-induced error and does not effect CERR. In either case, set the Missed Micro-frame bit in the status field to a one. If PIDCode = IN Halt QHD If PIDCode = OUT Retry start-split A not(B) C If PIDCode = IN Halt QHD If PIDCode = OUT Retry start-split MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-160 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Condition A B C not(D) D Action Execute complete-split Description This is the non-error case where the host controller executes a complete-split transaction. If PIDCode = IN Halt QHD If PIDCode = OUT Retry start-split This is a degenerate case where the start-split was issued, but all of the complete-splits were skipped and all possible intervening opportunities to detect the missed data failed to fire. If PIDCode is an IN, then the Queue head must be halted. If PIDCode is an OUT, then the transfer state is not advanced and the state exited (e.g. start-split is retried). This is a host-induced error and does not effect CERR. In either case, set the Missed Micro-frame bit in the status field to a one. Note: When executing in the context of a Recovery Path mode, the host controller is allowed to process the queue head and take the actions indicated above, or it may wait until the queue head is visited in the normal processing mode. Regardless, the host controller must not execute a start-split in the context of a executing in a Recovery Path mode. Managing QH.FrameTag Field The QH.FrameTag field in a queue head is completely managed by the host controller. The rules for setting QH.FrameTag are simple: • Rule 1: If transitioning from Do Start Split to Do Complete Split and the current value of FRINDEX[2:0] is 6 QH.FrameTag is set to FRINDEX[7:3] + 1. This accommodates split transactions whose start-split and complete-splits are in different H-Frames (case 2a, see Figure 30-70). • Rule 2: If the current value of FRINDEX[2:0] is 7, QH.FrameTag is set to FRINDEX[7:3] + 1. This accommodates staying in Do Complete Split for cases 2a, 2b, and 2c (Figure 30-70). • Rule 3: If transitioning from Do_Start Split to Do Complete Split and the current value of FRINDEX[2:0] is not 6, or currently in Do Complete Split and the current value of (FRINDEX[2:0]) is not 7, FrameTag is set to FRINDEX[7:3]. This accommodates all other cases (Figure 30-70). Rebalancing the Periodic Schedule System software must occasionally adjust a periodic queue head’s S-mask and C-mask fields during operation. This need occurs when adjustments to the periodic schedule create a new bandwidth budget and one or more queue head’s are assigned new execution footprints (i.e. new S-mask and C-mask values). It is imperative that System software must not update these masks to new values in the midst of a split transaction. In order to avoid any race conditions with the update, the EHCI host controller provides a simple assist to system software. System software sets the Inactivate-on-next-Transaction (I) bit to a one to signal the host controller that it intends to update the S-mask and C-mask on this queue head. System MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-161 High-Speed USB On-The-Go (HS USB-OTG) software will then wait for the host controller to observe the I-bit is a one and transition the Active bit to a zero. The rules for how and when the host controller sets the Active bit to zero are enumerated below: • If the Active bit is a zero, no action is taken. The host controller does not attempt to advance the queue when the I-bit is a one. • If the Active bit is a one and the SplitXState is DoStart (regardless of the value of S-mask), the host controller will simply set Active bit to a zero. The host controller is not required to write the transfer state back to the current qTD. Note that if the S-mask indicates that a start-split is scheduled for the current micro-frame, the host controller must not issue the start-split bus transaction. It must set the Active bit to zero. System software must save transfer state before setting the I-bit to a one. This is required so that it can correctly determine what transfer progress (if any) occurred after the I-bit was set to a one and the host controller executed it’s final bus-transaction and set Active to a zero. After system software has updated the S-mask and C-mask, it must then reactivate the queue head. Since the Active bit and the I-bit cannot be updated with the same write, system software needs to use the following algorithm to coherently re-activate a queue head that has been stopped via the I-bit. 4. Set the Halted bit to a one, then 5. Set the I-bit to a zero, then 6. Set the Active bit to a one and the Halted bit to a zero in the same write. Setting the Halted bit to a one inhibits the host controller from attempting to advance the queue between the time the I-bit goes to a zero and the Active bit goes to a one. 30.8.3.12.3 Split Transaction Isochronous Full-speed isochronous transfers are managed using the split-transaction protocol through a USB 2.0 transaction translator in a USB2.0 Hub. The EHCI controller utilizes siTD data structure to support the special requirements of isochronous split-transactions. This data structure uses the scheduling model of isochronous TDs (iTD, Section Isochronous (High-Speed) Transfer Descriptor (iTD)) (see Section Managing Isochronous Transfers Using iTDs for the operational model of iTDs) with the contiguous data feature provided by queue heads. This simple arrangement allows a single isochronous scheduling model and adds the additional feature that all data received from the endpoint (per split transaction) must land into a contiguous buffer. Split Transaction Scheduling Mechanisms for Isochronous Full-speed isochronous transactions are managed through a transaction translator's periodic pipeline. As with full- and low-speed interrupt, system software manages each transaction translator's periodic pipeline by budgeting and scheduling exactly during which micro-frames the start-splits and complete-splits for each full-speed isochronous endpoint occur. The requirements described in Section Split Transaction Scheduling Mechanisms for Interrupt apply. Figure 30-70 illustrates the general scheduling boundary conditions that are supported by the EHCI periodic schedule. The SX and CX labels indicate micro-frames where software can schedule start- and complete-splits (respectively). The H-Frame boundaries are marked with a large, solid bold vertical line. The B-Frame boundaries are marked with a large, bold, dashed line. The bottom of the figure illustrates the relationship of an siTD to the H-Frame. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-162 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Figure 30-70. Split Transaction, Isochronous Scheduling Boundary Conditions When the endpoint is an isochronous OUT, there are only start-splits, and no complete-splits. When the endpoint is an isochronous IN, there is at most one start-split and one to N complete-splits. The scheduling boundary cases are: • Case 1: The entire split transaction is completely bounded by an H-Frame. For example: the start-splits and complete-splits are all scheduled to occur in the same H-Frame. • Case 2a: This boundary case is where one or more (at most two) complete-splits of a split transaction IN are scheduled across an H-Frame boundary. This can only occur when the split transaction has the possibility of moving data in B-Frame, micro-frames 6 or 7 (H-Frame micro-frame 7 or 0). When an H-Frame boundary wrap condition occurs, the scheduling of the split transaction spans more than one location in the periodic list.(e.g. it takes two siTDs in adjacent periodic frame list locations to fully describe the scheduling for the split transaction). • Although the scheduling of the split transaction may take two data structures, all of the complete-splits for each full-speed IN isochronous transaction must use only one data pointer. For this reason, siTDs contain a back pointer, the use of which is described below. • Software must never schedule full-speed isochronous OUTs across an H-Frame boundary. • Case 2b: This case can only occur for a very large isochronous IN. It is the only allowed scenario where a start-split and complete-split for the same endpoint can occur in the same micro-frame. Software must enforce this rule by scheduling the large transaction first. Large is defined to be anything larger than 579 byte maximum packet size. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-163 High-Speed USB On-The-Go (HS USB-OTG) A subset of the same mechanisms employed by full- and low-speed interrupt queue heads are employed in siTDs to schedule and track the portions of isochronous split transactions. The following fields are initialized by system software to instruct the host controller when to execute portions of the split transaction protocol. • SplitXState. This is a single bit residing in the Status field of an siTD (see Table 30-46). This bit is used to track the current state of the split transaction. The rules for managing this bit are described in Section In the following presentation, all references to micro-frame are in the context of a micro-frame within an H-Frame.Split Transaction Execution State Machine for Isochronous . • Frame S-mask. This is a bit-field where-in system software sets a bit corresponding to the micro-frame (within an H-Frame) that the host controller should execute a start-split transaction. This is always qualified by the value of the SplitXState bit. For example, referring to the IN example in Figure 30-70, case one, the S-mask would have a value of 00000001b indicating that if the siTD is traversed by the host controller, and the SplitXState indicates Do Start Split, and the current micro-frame as indicated by FRINDEX[2:0] is 0, then execute a start-split transaction. • Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the micro-frames (within an H-Frame) that the host controller should execute complete-split transactions. The interpretation of this field is always qualified by the value of the SplitXState bit. For example, referring to the IN example in Figure 30-70, case one, the C-mask would have a value of 00111100b indicating that if the siTD is traversed by the host controller, and the SplitXState indicates Do Complete Split, and the current micro-frame as indicated by FRINDEX[2:0] is 2, 3, 4, or 5, then execute a complete-split transaction. • Back Pointer. This field in a siTD is used to complete an IN split-transaction using the previous H-Frame's siTD. This is only used when the scheduling of the complete-splits span an H-Frame boundary. There exists a one-to-one relationship between a high-speed isochronous split transaction (including all start- and complete-splits) and one full-speed isochronous transaction. An siTD contains (amongst other things) buffer state and split transaction scheduling information. An siTD's buffer state always maps to one full-speed isochronous data payload. This means that for any full-speed transaction payload, a single siTD's data buffer must be used. This rule applies to both IN an OUTs. An siTD's scheduling information usually also maps to one high-speed isochronous split transaction. The exception to this rule is the H-Frame boundary wrap cases mentioned above. The siTD data structure describes at most, one frame's worth of high-speed transactions and that description is strictly bounded within a frame boundary. Figure 30-71 illustrates some examples. On the top are examples of the full-speed transaction footprints for the boundary scheduling cases described above. In the middle are time-frame references for both the B-Frames (HS/FS/LS Bus) and the H-Frames. On the bottom is illustrated the relationship between the scope of an siTD description and the time references. Each H-Frame corresponds to a single location in the periodic frame list. The implication is that each siTD is reachable from a single periodic frame list location at a time. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-164 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Figure 30-71. siTD Scheduling Boundary Examples Each case is described below: • Case 1: One siTD is sufficient to describe and complete the isochronous split transaction because the whole isochronous split transaction is tightly contained within a single H-Frame. • Case 2a, 2b: Although both INs and OUTs can have these footprints, OUTs always take only one siTD to schedule. However, INs (for these boundary cases) require two siTDs to complete the scheduling of the isochronous split transaction. siTDX is used to always issue the start-split and the first N complete-splits. The full-speed transaction (for these cases) can deliver data on the full-speed bus segment during micro-frame 7 of H-FrameY+1, or micro-frame 0 of H-FrameY+2. The complete splits are scheduled using siTDX+2 (not shown). The complete-splits to extract this data must use the buffer pointer from siTDX+1. The only way for the host controller to reach siTDX+1 from H-FrameY+2 is to use siTDX+2's back pointer. The host controller rules for when to use the back pointer are described is Section Periodic Isochronous - Do Complete Split . Software must apply the following rules when calculating the schedule and linking the schedule data structures into the periodic schedule: • Software must ensure that an isochronous split-transaction is started so that it will complete before the end of the B-Frame. • Software must ensure that for a single full-speed isochronous endpoint, there is never a start-split and complete-split in H-Frame, micro-frame 1. This is mandated as a rule so that case 2a and case 2b can be discriminated. According to the core USB specification, the long isochronous transaction illustrated in Case 2b, could be scheduled so that the start-split was in micro-frame 1 of H-Frame N and the last complete-split would need to occur in micro-frame 1 of H-Frame N+1. However, it is impossible to discriminate between cases 2a and case 2b, which has significant impact on the complexity of the host controller. Tracking Split Transaction Progress for Isochronous Transfers To correctly maintain the data stream, the host controller must be able to detect and report errors where device to host data is lost. Isochronous endpoints do not employ the concept of a halt on error, however the host is required to identify and report per-packet errors observed in the data stream. This includes schedule traversal problems (skipped micro-frames), timeouts and corrupted data received. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-165 High-Speed USB On-The-Go (HS USB-OTG) In similar kind to interrupt split-transactions, the portions of the split transaction protocol must execute in the micro-frames they are scheduled. The queue head data structure used to manage full- and low-speed interrupt has several mechanisms for tracking when portions of a transaction have occurred. Isochronous transfers use siTDs, for their transfers, and the data structures are only reachable via the schedule in the exact micro-frame in which they are required (so all the mechanism employed for tracking in queue heads is not required for siTDs). Software has the option of reusing siTD several times in the complete periodic schedule. However, it must ensure that the results of split transaction N are consumed and the siTD reinitialized (activated) before the host controller gets back to the siTD (in a future micro-frame). Split-transaction isochronous OUTs utilize a low-level protocol to indicate which portions of the split transaction data have arrived. Control over the low-level protocol is exposed in an siTD via the fields Transaction Position (TP) and Transaction Count (T-count). If the entire data payload for the OUT split transaction is larger than 188 bytes, there will be more than one start-split transaction, each of which require proper annotation. If host hold-offs occur, then the sequence of annotations received from the host will not be complete, which is detected and handled by the transaction translator. See Section Periodic Isochronous - Do Start Split for a description on how these fields are used during a sequence of start-split transactions. The fields siTD.T-Count and siTD.TP are used by the host controller to drive and sequence the transaction position annotations. It is the responsibility of system software to properly initialize these fields in each siTD. Once the budget for a split-transaction isochronous endpoint is established, S-mask, T-Count, and TP initialization values for all the siTD associated with the endpoint are constant. They remain constant until the budget for the endpoint is recalculated by software and the periodic schedule adjusted. For IN-endpoints, the transaction translator simply annotates the response data packets with enough information to allow the host controller to identify the last data. As with split transaction Interrupt, it is the host controller's responsibility to detect when it has missed an opportunity to execute a complete-split. The following field in the siTD is used to track and detect errors in the execution of a split transaction for an IN isochronous endpoint. • C-prog-mask. This is an eight-bit bit-vector where the host controller keeps track of which complete-splits have been executed. Due to the nature of the Transaction Translator periodic pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when the complete-splits have not been executed in order. This can only occur due to system hold-offs where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple bit-vector that the host controller sets a bit for each complete-split executed. The bit position is determined by the micro-frame (FRINDEX[2:0]) number in which the complete-split was executed. The host controller always checks C-prog-mask before executing a complete-split transaction. If the previous complete-splits have not been executed, then it means one (or more) have been skipped and data has potentially been lost. System software is required to initialize this field to zero before setting an siTD's Active bit to a one. If a transaction translator returns with the final data before all of the complete-splits have been executed, the state of the transfer is advanced so that the remaining complete-splits are not executed. Refer to Section Periodic Isochronous - Do Complete Split for a description on how the state of the transfer is advanced. It is important to note that an IN siTD is retired based solely on the responses from the Transaction Translator to the complete-split transactions. This means, for example, that it is possible for a transaction translator to respond to a complete-split with an MDATA PID. The number of bytes in the MDATA's data MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-166 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) payload could cause the siTD field Total Bytes to Transfer to decrement to zero. This response can occur, before all of the scheduled complete-splits have been executed. In other interface, data structures (e.g. high-speed data streams through queue heads), the transition of Total Bytes to Transfer to zero signals the end of the transfer and results in setting of the Active bit to zero. However, in this case, the result has not been delivered by the Transaction Translator and the host must continue with the next complete-split transaction to extract the residual transaction state. This scenario occurs because of the pipeline rules for a Transaction Translator (see Chapter 11 of the Universal Serial Bus Revision 2.0). In summary the periodic pipeline rules require that on a micro-frame boundary, the Transaction Translator will hold the final two bytes received (if it has not seen an End Of Packet (EOP)) in the full-speed bus pipe stage and give the remaining bytes to the high-speed pipeline stage. At the micro-frame boundary, the Transaction Translator could have received the entire packet (including both CRC bytes) but not received the packet EOP. In the next micro-frame, the Transaction Translator will respond with an MDATA and send all of the data bytes (with the two CRC bytes being held in the full-speed pipeline stage). This could cause the siTD to decrement it's Total Bytes to Transfer field to zero, indicating it has received all expected data. The host must still execute one more (scheduled) complete-split transaction in order to extract the results of the full-speed transaction from the Transaction Translator (for example, the Transaction Translator may have detected a CRC failure, and this result must be forwarded to the host). If the host experiences hold-offs that cause the host controller to skip one or more (but not all) scheduled split transactions for an isochronous OUT, then the protocol to the transaction translator will not be consistent and the transaction translator will detect and react to the problem. Likewise, for host hold-offs that cause the host controller to skip one or more (but not all) scheduled split transactions for an isochronous IN, the C-prog-mask is used by the host controller to detect errors. However, if the host experiences a hold-off that causes it to skip all of an siTD, or an siTD expires during a host hold off (e.g. a hold-off occurs and the siTD is no longer reachable by the host controller in order for it to report the hold-off event), then system software must detect that the siTDs have not been processed by the host controller (e.g. state not advanced) and report the appropriate error to the client driver. In the following presentation, all references to micro-frame are in the context of a micro-frame within an H-Frame.Split Transaction Execution State Machine for Isochronous If the Active bit in the Status byte is a zero, the host controller will ignore the siTD and continue traversing the periodic schedule. Otherwise the host controller will process the siTD as specified below. A split transaction state machine is used to manage the split-transaction protocol sequence. The host controller uses the fields defined in Section Tracking Split Transaction Progress for Isochronous Transfers , plus the variable cMicroFrameBit defined in Section Split Transaction Execution State Machine for Interrupt to track the progress of an isochronous split transaction. Figure 30-72 illustrates the state machine for managing an siTD through an isochronous split transaction. Bold, dotted circles denote the state of the Active bit in the Status field of a siTD. The Bold, dotted arcs denote the transitions between these states. Solid circles denote the states of the split transaction state machine and the solid arcs denote the transitions between these states. Dotted arcs and boxes reference actions that take place either as a result of a transition or from being in a state. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-167 High-Speed USB On-The-Go (HS USB-OTG) Figure 30-72. Split Transaction State Machine for Isochronous Periodic Isochronous - Do Start Split Isochronous split transaction OUTs use only this state. An siTD for a split-transaction isochronous IN is either initialized to this state, or the siTD transitions to this state from Do Complete Split when a case 2a (IN) or 2b scheduling boundary isochronous split-transaction completes. Each time the host controller reaches an active siTD in this state, it checks the siTD.S-mask against cMicroFrameBit. If there is a one in the appropriate position, the siTD will execute a start-split transaction. By definition, the host controller cannot reach an siTD at the wrong time. If the I/O field indicates an IN, then the start-split transaction includes only the extended token plus the full-speed token. Software must initialize the siTD.Total Bytes To Transfer field to the number of bytes expected. This is usually the maximum packet size for the full-speed endpoint. The host controller exits this state when the start-split transaction is complete. The remainder of this section is specific to an isochronous OUT endpoint (i.e. the I/O field indicates an OUT). When the host controller executes a start-split transaction for an isochronous OUT it includes a data payload in the start-split transaction. The memory buffer address for the data payload is constructed by concatenating siTD.Current Offset with the page pointer indicated by the page selector field (siTD.P). A zero in this field selects Page 0 and a 1 selects Page 1. During the start-split for an OUT, if the data transfer crosses a page boundary during the transaction, the host controller must detect the page cross, update the siTD.P-bit from a zero to a one, and begin using the siTD.Page 1 with siTD.Current Offset as the memory address pointer. The field siTD.TP is used to annotate each start-split transaction with the indication of which part of the split-transaction data the current payload represents (ALL, BEGIN, MID, END). In all cases the host controller simply uses the value in siTD.TP to mark the start-split with the correct transaction position code. T-Count is always initialized to the number of start-splits for the current frame. TP is always initialized to the first required transaction position identifier. The scheduling boundary case (see Figure 30-71) is used to determine the initial value of TP. The initial cases are summarized in Table 30-71. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-168 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-71. Initial Conditions for OUT siTD's TP and T-count Fields Case 1, 2a T-count =1 TP ALL Description When the OUT data payload is less than (or equal to) 188 bytes, only one start-split is required to move the data. The one start-split must be marked with an ALL. When the OUT data payload is greater than 188 bytes more than one start-split must be used to move the data. The initial start-split must be marked with a BEGIN. 1, 2a !=1 BEGIN After each start-split transaction is complete, the host controller updates T-Count and TP appropriately so that the next start-split is correctly annotated. Table 30-72 illustrates all of the TP and T-count transitions, which must be accomplished by the host controller. Table 30-72. Transaction Position (TP)/Transaction Count (T-Count) Transition Table TP ALL BEGIN BEGIN MID 0 1 T-count next TP next N/A END MID MID Description Transition from ALL, to done. Transition from BEGIN to END. Occurs when T-count starts at 2. Transition from BEGIN to MID. Occurs when T-count starts at greater than 2. TP stays at MID while T-count is not equal to 1 (e.g. greater than 1). This case can occur for any of the scheduling boundary cases where the T-count starts greater than 3. Transition from MID to END. This case can occur for any of the scheduling boundary cases where the T-count starts greater than 2. !=1 !=1 MID 1 END The start-split transactions do not receive a handshake from the transaction translator, so the host controller always advances the transfer state in the siTD after the bus transaction is complete. To advance the transfer state the following operations take place: • • • The siTD.Total Bytes To Transfer and the siTD.Current Offset fields are adjusted to reflect the number of bytes transferred. The siTD.P (page selector) bit is updated appropriately. The siTD.TP and siTD.T-count fields are updated appropriately as defined in Table 30-72. These fields are then written back to the memory based siTD. The S-mask is fixed for the life of the current budget. As mentioned above, TP and T-count are set specifically in each siTD to reflect the data to be sent from this siTD. Therefore, regardless of the value of S-mask, the actual number of start-split transactions depends on T-count (or equivalently, Total Bytes to Transfer). The host controller must set the Active bit to a zero when it detects that all of the schedule data has been sent to the bus. The preferred method is to detect when T-Count decrements to zero as a result of a start-split bus transaction. Equivalently, the host MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-169 High-Speed USB On-The-Go (HS USB-OTG) controller can detect when Total Bytes to Transfer decrements to zero. Either implementation must ensure that if the initial condition is Total Bytes to Transfer equal to zero and T-count is equal to a one, then the host controller will issue a single start-split, with a zero-length data payload. Software must ensure that TP, T-count and Total Bytes to Transfer are set to deliver the appropriate number of bus transactions from each siTD. An inconsistent combination will yield undefined behavior. If the host experiences hold-offs that cause the host controller to skip start-split transactions for an OUT transfer, the state of the transfer will not progress appropriately. The transaction translator will observe protocol violations in the arrival of the start-splits for the OUT endpoint (i.e. the transaction position annotation will be incorrect as received by the transaction translator). Example scenarios are described in Section Split Transaction for Isochronous - Processing Examples . A host controller implementation can optionally track the progress of an OUT split transaction by setting appropriate bits in the siTD.C-prog-mask as it executes each scheduled start-split. The checkPreviousBit() algorithm defined in Section Periodic Isochronous - Do Complete Split can be used prior to executing each start-split to determine whether start-splits were skipped. The host controller can use this mechanism to detect missed micro-frames. It can then set the siTD’s Active bit to zero and stop execution of this siTD. This saves on both memory and high-speed bus bandwidth. Periodic Isochronous - Do Complete Split This state is only used by a split-transaction isochronous IN endpoint. This state is entered unconditionally from the Do Start State after a start-split transaction is executed for an IN endpoint. Each time the host controller visits an siTD in this state, it conducts a number of tests to determine whether it should execute a complete-split transaction. The individual tests are listed below. The sequence they are applied depends on which micro-frame the host controller is currently executing which means that the tests might not be applied until after the siTD referenced from the back pointer has been fetched. • Test A. cMicroFrameBit is bit-wise anded with siTD.C-mask field. A non-zero result indicates that software scheduled a complete-split for this endpoint, during this micro-frame. This test is always applied to a newly fetched siTD that is in this state. • Test B. The siTD.C-prog-mask bit vector is checked to determine whether the previous complete splits have been executed. An example algorithm is below (this is slightly different than the algorithm used in Section Periodic Interrupt - Do Complete Split ). The sequence in which this test is applied depends on the current value of FRINDEX[2:0]. If FRINDEX[2:0] is 0 or 1, it is not applied until the back pointer has been used. Otherwise it is applied immediately. Algorithm Boolean CheckPreviousBit(siTD.C-prog-mask, siTD.C-mask, cMicroFrameBit) Begin Boolean rvalue = TRUE; previousBit = cMicroFrameBit rotate-right(1) -- Bit-wise anding previousBit with C-mask indicates whether there was an intent -- to send a complete split in the previous micro-frame. So, if the -- 'previous bit' is set in C-mask, check C-prog-mask to make sure it -- happened. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-170 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) if previousBit bitAND siTD.C-mask then if not (previousBit bitAND siTD.C-prog-mask) then rvalue = FALSE End if End if Return rvalue End Algorithm If Test A is true and FRINDEX[2:0] is zero or one, then this is a case 2a or 2b scheduling boundary (see Figure 30-70). See Section Periodic Isochronous - Do Complete Split for details in handling this condition. If Test A and Test B evaluate to true, then the host controller will execute a complete-split transaction using the transfer state of the current siTD. When the host controller commits to executing the complete-split transaction, it updates QH.C-prog-mask by bit-ORing with cMicroFrameBit. The transfer state is advanced based on the completion status of the complete-split transaction. To advance the transfer state of an IN siTD, the host controller must: • Decrement the number of bytes received from siTD.Total Bytes To Transfer, • Adjust siTD.Current Offset by the number of bytes received, • Adjust siTD.P (page selector) field if the transfer caused the host controller to use the next page pointer, and • Set any appropriate bits in the siTD.Status field, depending on the results of the transaction. Note that if the host controller encounters a condition where siTD.Total Bytes To Transfer is zero, and it receives more data, the host controller must not write the additional data to memory. The siTD.Status.Active bit must be set to zero and the siTD.Status.Babble Detected bit must be set to a one. The fields siTD.Total Bytes To Transfer, siTD.Current Offset, and siTD.P (page selector) are not required to be updated as a result of this transaction attempt. The host controller must accept (assuming good data packet CRC and sufficient room in the buffer as indicated by the value of siTD.Total Bytes To Transfer) MDATA and DATA0/1 data payloads up to and including 192 bytes. A host controller implementation may optionally set siTD.Status Active to a zero and siTD.Status.Babble Detected to a one when it receives and MDATA or DATA0/1 with a data payload of more than 192 bytes. The following responses have the noted effects: • ERR. The full-speed transaction completed with a time-out or bad CRC and this is a reflection of that error to the host. The host controller sets the ERR bit in the siTD.Status field and sets the Active bit to a zero. • Transaction Error (XactErr). The complete-split transaction encounters a Timeout, CRC16 failure, etc. The siTD.Status field XactErr field is set to a one and the complete-split transaction must be retried immediately. The host controller must use an internal error counter to count the number of retries as a counter field is not provided in the siTD data structure. The host controller will not retry MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-171 High-Speed USB On-The-Go (HS USB-OTG) • • • • • more than two times. If the host controller exhausts the retries or the end of the micro-frame occurs, the Active bit is set to zero. DATAx (0 or 1). This response signals that the final data for the split transaction has arrived. The transfer state of the siTD is advanced and the Active bit is set to a zero. If the Bytes To Transfer field has not decremented to zero (including the reception of the data payload in the DATAx response), then less data than was expected, or allowed for was actually received. This short packet event does not set the USBINT status bit in the USBSTS register to a one. The host controller will not detect this condition. NYET (and Last). On each NYET response, the host controller also checks to determine whether this is the last complete-split for this split transaction. Last was defined in Section Periodic Interrupt - Do Complete Split . If it is the last complete-split (with a NYET response), then the transfer state of the siTD is not advanced (never received any data) and the Active bit is set to a zero. No bits are set in the Status field because this is essentially a skipped transaction. The transaction translator must have responded to all the scheduled clompete-splits with NYETs, meaning that the start-split issued by the host controller was not received. This result should be interpreted by system software as if the transaction was completely skipped. The test for whether this is the last complete split can be performed by XORing C-mask with C-prog-mask. A zero result indicates that all complete-splits have been executed. MDATA (and Last). See above description for testing for Last. This can only occur when there is an error condition. Either there has been a babble condition on the full-speed link, which delayed the completion of the full-speed transaction, or software set up the S-mask and/or C-masks incorrectly. The host controller must set XactErr bit to a one and the Active bit is set to a zero. NYET (and not Last). See above description for testing for Last. The complete-split transaction received a NYET response from the transaction translator. Do not update any transfer state (except for C-prog-mask) and stay in this state. MDATA (and not Last). The transaction translator responds with an MDATA when it has partial data for the split transaction. For example, the full-speed transaction data payload spans from micro-frame X to X+1 and during micro-frame X, the transaction translator will respond with an MDATA and the data accumulated up to the end of micro-frame X. The host controller advances the transfer state to reflect the number of bytes received. If Test A succeeds, but Test B fails, it means that one or more of the complete-splits have been skipped. The host controller sets the Missed Micro-Frame status bit and sets the Active bit to a zero. Complete-Split for Scheduling Boundary Cases 2a, 2b Boundary cases 2a and 2b (INs only) (see Figure 30-70) require that the host controller use the transaction state context of the previous siTD to finish the split transaction. Table 30-73 enumerates the transaction state fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-172 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Table 30-73. Summary siTD Split Transaction State Buffer State Total Bytes To Transfer P (page select) Current Offset TP (transaction position) T-count (transaction count) Status All bits in the status field Execution Progress C-prog-mask Note: TP and T-count are used only for Host to Device (OUT) endpoints. If software has budgeted the schedule of this data stream with a frame wrap case, then it must initialize the siTD.Back Pointer field to reference a valid siTD and will have the siTD.Back Pointer.T-bit in the siTD.Back Pointer field set to a zero. Otherwise, software must set the siTD.Back Pointer.T-bit in the siTD.Back Pointer field to a one. The host controller's rules for interpreting when to use the siTD.Back Pointer field are listed below. These rules apply only when the siTD's Active bit is a one and the SplitXState is Do Complete Split. • When cMicroFrameBit is a 1h and the siTDX.Back Pointer.T-bit is a zero, or • If cMicroFrameBit is a 2h and siTDX.S-mask[0] is a zero When either of these conditions apply, then the host controller must use the transaction state from siTDX-1. In order to access siTDX-1, the host controller reads on-chip the siTD referenced from siTDX.Back Pointer. The host controller must save the entire state from siTDX while processing siTDX-1. This is to accommodate for case 2b processing. The host controller must not recursively walk the list of siTD.Back Pointers. If siTDX-1 is active (Active bit is a one and SplitXStat is Do Complete Split), then both Test A and Test B are applied as described above. If these criteria to execute a complete-split are met, the host controller executes the complete split and evaluates the results as described above. The transaction state (see Table 30-73) of siTDX-1 is appropriately advanced based on the results and written back to memory. If the resultant state of siTDX-1's Active bit is a one, then the host controller returns to the context of siTDX, and follows its next pointer to the next schedule item. No updates to siTDX are necessary. If siTDX-1 is active (Active bit is a one and SplitXStat is Do Start Split), then the host controller must set Active bit to a zero and Missed Micro-Frame status bit to a one and the resultant status written back to memory. If siTDX-1's Active bit is a zero, (because it was zero when the host controller first visited siTDX-1 via siTDX's back pointer, it transitioned to zero as a result of a detected error, or the results of siTDX-1's complete-split transaction transitioned it to zero), then the host controller returns to the context of siTDX and transitions its SplitXState to Do Start Split. The host controller then determines whether the case 2b start split boundary condition exists (i.e. if cMicroframeBit is a 1b and siTDX.S-mask[0] is a 1b). If this criterion is met the host controller immediately executes a start-split transaction and appropriately MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-173 High-Speed USB On-The-Go (HS USB-OTG) advances the transaction state of siTDX, then follows siTDX.Next Pointer to the next schedule item. If the criterion is not met, the host controller simply follows siTDX.Next Pointer to the next schedule item. Note that in the case of a 2b boundary case, the split-transaction of siTDX-1 will have its Active bit set to zero when the host controller returns to the context of siTDX. Also, note that software should not initialize an siTD with C-mask bits 0 and 1 set to a one and an S-mask with bit zero set to a one. This scheduling combination is not supported and the behavior of the host controller is undefined. Split Transaction for Isochronous - Processing Examples There is an important difference between how the hardware/software manages the isochronous split transaction state machine and how it manages the asynchronous and interrupt split transaction state machines. The asynchronous and interrupt split transaction state machines are encapsulated within a single queue head. The progress of the data stream depends on the progress of each split transaction. In some respects, the split-transaction state machine is sequenced via the Execute Transaction queue head traversal state machine (see Figure 30-63). Isochronous is a pure time-oriented transaction/data stream. The interface data structures are optimized to efficiently describe transactions that need to occur at specific times. The isochronous split-transaction state machine must be managed across these time-oriented data structures. This means that system software must correctly describe the scheduling of split-transactions across more than one data structure. Then the host controller must make the appropriate state transitions at the appropriate times, in the correct data structures. For example, Table 30-74 illustrates a couple of frames worth of scheduling required to schedule a case 2a full-speed isochronous data stream. Table 30-74. Example Case 2a - Software Scheduling siTDs for an IN Endpoint siTDX # X Micro-Frames 0 1 2 3 4 1 1 1 1 1 1 1 1 1 Repeats previous pattern 1 1 1 1 1 1 Masks S-Mask C-Mask 5 6 7 Initial SplitXState Do Start Split X+1 S-Mask C-Mask Do Complete Split Do Complete Split Do Complete Split X+2 S-Mask C-Mask X+3 S-Mask C-Mask This example shows the first three siTDs for the transaction stream. Since this is the case-2a frame-wrap case, S-masks of all siTDs for this endpoint have a value of 10h (a one bit in micro-frame 4) and C-mask value of C3h (one-bits in micro-frames 0,1, 6 and 7). Additionally, sofware ensures that the Back Pointer field of each siTD references the appropriate siTD data structure (and the Back Pointer T-bits are set to zero). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-174 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) The initial SplitXState of the first siTD is Do Start Split. The host controller will visit the first siTD eight times during frame X. The C-mask bits in micro-frames 0 and 1 are ignored because the state is Do Start Split. During micro-frame 4, the host controller determines that it can run a start-split (and does) and changes SplitXState to Do Complete Split. During micro-frames 6 and 7, the host controller executes complete-splits. Notice the siTD for frame X+1 has it's SplitXState initialized to Do Complete Split. As the host controller continues to traverse the schedule during H-Frame X+1, it will visit the second siTD eight times. During micro-frames 0 and 1 it will detect that it must execute complete-splits. During H-Frame X+1, micro-frame 0, the host controller detects that siTDX+1's Back Pointer.T-bit is a zero, saves the state of siTDX+1 and fetches siTDX. It executes the complete split transaction using the transaction state of siTDX. If the siTDX split transaction is complete, siTD's Active bit is set to zero and results written back to siTDX. The host controller retains the fact that siTDX is retired and transitions the SplitXState in the siTDX+1 to Do Start Split. At this point, the host controller is prepared to execute the start-split for siTDX+1 when it reaches micro-frame 4. If the split-transaction completes early (transaction-complete is defined in Section Periodic Isochronous - Do Complete Split ), i.e. before all the scheduled complete-splits have been executed, the host controller will transition siTDX.SplitXState to Do Start Split early and naturally skip the remaining scheduled complete-split transactions. For this example, siTDX+1 does not receive a DATA0 response until H-Frame X+2, micro-frame 1. During H-Frame X+2, micro-frame 0, the host controller detects that siTDX+2's Back Pointer.T-bit is a zero, saves the state of siTDX+2 and fetches siTDX+1. As described above, it executes another split transaction, receives an MDATA response, updates the transfer state, but does not modify the Active bit. The host controller returns to the context of siTDX+2, and traverses it's next pointer without any state change updates to siTDX+2. S During H-Frame X+2, micro-frame 1, the host controller detects siTDX+2's S-mask[0] is a zero, saves the state of siTDX+2 and fetches siTDX+1. It executes another complete-split transaction, receives a DATA0 response, updates the transfer state and sets the Active bit to a zero. It returns to the state of siTDX+2 and changes its SplitXState to Do Start Split. At this point, the host controller is prepared to execute start-splits for siTDX+2 when it reaches micro-frame 4. maximum packet size) OR (total bytes received > total bytes specified). *** This is an error condition. The device controller will discard the remaining packet, and set the Buffer Error bit in the dTD. In addition, the endpoint will be flushed and the USBERR interrupt will become active. On the successful completion of the packet(s) described by the dTD, the active bit in the dTD will be cleared and the next pointer will be followed when the Terminate bit is clear. When the Terminate bit is set, the device controller will flush the endpoint/direction and cease operations for that endpoint/direction. On the unsuccessful completion of a packet (see long packet above), the dQH will be left pointing to the dTD that was in error. In order to recover from this error condition, the DCD must properly reinitialize the dQH by clearing the active bit and update the nextTD pointer before attempting to re-prime the endpoint. Note: All packet level errors such as a missing handshake or CRC error will be retried automatically by the device controller. There is no required interaction with the DCD for handling such errors. Interrupt/Bulk Endpoint Bus Response Matrix Table 30-91. Interrupt/Bulk Endpoint Bus Response Matrix Stall Setup In Out Ping Invalid Ignore STALL STALL STALL Ignore Not Primed Ignore NAK NAK NAK Ignore Primed Ignore Transmit Receive + NYET/ACK ACK Ignore Underflow N/A BS Error N/A N/A Ignore Overflow N/A N/A NAK N/A Ignore BS Error = Force Bit Stuff Error NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. SYSERR—System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-204 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) 30.8.6.3.2 Setup Phase Control Endpoint Operation Model All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase. The device controller will always accept the setup phase unless the setup lockout is engaged. The setup lockout will engage so that future setup packets are ignored. Lockout of setup packets ensures that while software is reading the setup packet stored in the queue head, that data is not written as it is being read potentially causing an invalid setup packet. In hardware versions 2.3 and later, the setup lockout mechanism can be disabled and a new tripwire type semaphore will ensure that the setup packet payload is extracted from the queue head without being corrupted be an incoming setup packet. This is the preferred behavior because ignoring repeated setup packets due to long software interrupt latency would be a compliance issue. Setup Packet Handling (Pre-2.3 hardware) • After receiving an interrupt and inspecting USBMODE to determine that a setup packet was received on a particular pipe: — 1. Duplicate contents of dQH.SsetupBuffer into local software byte array. — 2. Write '1' to clear corresponding ENDPTSETUPSTAT bit and thereby disabling Setup Lockout. (i.e. the Setup Lockout activates as soon as a setup arrives. By writing to the ENDPTSETUPSTAT, the device controller will accept new setup packets.) — 3. Process setup packet using local software byte array copy and execute status/handshake phases. • Note: After receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. These should be flushed & deallocated before linking a new status and/or handshake dTD for the most recent setup packet. Note: To limit the exposure of setup packets to the setup lockout mechanism (if used), the DCD should designate the priority of responding to setup packets above responding to other packet completions. Setup Packet Handling (2.3 hardware and later) • Disable Setup Lockout by writing ‘1’ to Setup Lockout Mode (SLOM) in USBMODE. (once at initialization). Setup lockout is not necessary when using the tripwire as described below. Note: leaving the Setup Lockout Mode As ‘0’ will result in pre-2.3 hardware behavior. • After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet was received on a particular pipe: — 1. Write '1' to clear corresponding bit ENDPTSETUPSTAT. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-205 High-Speed USB On-The-Go (HS USB-OTG) — — — — — 2. Write ‘1’ to Setup Tripwire (SUTW) in USBCMD register. 3. Duplicate contents of dQH.SetupBuffer into local software byte array. 4. Read Setup TripWire (SUTW) in USBCMD register. (if set - continue; if cleared - goto 2) 5. Write '0' to clear Setup Tripwire (SUTW) in USBCMD register. 6. Process setup packet using local software byte array copy and execute status/handshake phases. Note: Note: After receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. These should be flushed & deallocated before linking a new status and/or handshake dTD for the most recent setup packet. Data Phase Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime the transfer. After priming the packet, the DCD must verify a new setup packet has not been received by reading the ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTAT register is a one. If a prime fails, ie. The ENDPTPRIME bit goes to zero and the ENDPTSTAT bit is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet. Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime status (ENDPTSTAT) to enforce data coherency with the setup packet. Note: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints. Note: Error handling of data phase packets is the same as bulk packets described previously. Status Phase Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT as described above in the data phase. Note: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control endpoints. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-206 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Note: Error handling of data phase packets is the same as bulk packets described previously. Control Endpoint Bus Response Matrix Shown in the following table is the device controller response to packets on a control endpoint according to the device controller state. Table 30-92. Control Endpoint Bus Response Matrix Endpoint State Token Type Stall Setup In Out Ping Invalid ACK STALL STALL STALL Ignore Not Primed ACK NAK NAK NAK Ignore Primed ACK Transmit Receive + NYET/ACK ACK Ignore Underflow N/A BS Error N/A N/A Ignore Overflow SYSERR N/A NAK N/A Ignore Setup Lockout N/A N/A N/A Ignore BS Error = Force Bit Stuff Error NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. SYSERR—System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 30.8.6.3.3 Isochronous Endpoint Operational Model Isochronous endpoints are used for real-time scheduled delivery of data and their operational model is significantly different than the host throttled Bulk, Interrupt, and Control data pipes. Real time delivery by the device controller will is accomplished by the following: • Exactly MULT Packets per (micro)Frame are transmitted/received. Note: MULT is a two-bit field in the device Queue Head. The variable length packet protocol is not used on isochronous endpoints. • NAK responses are not used. Instead, zero length packets and sent in response to an IN request to an unprimed endpoints. For unprimed RX endpoints, the response to an OUT transaction is to ignore the packet within the device controller. • Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If the ISO-dTD is still active after that frame, then the ISO-dTD will be held ready until executed or canceled by the DCD. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-207 High-Speed USB On-The-Go (HS USB-OTG) An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to Isochronous endpoints. The operational model for device mode does not use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints. The difference is in the handling of the dTD. The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a delayed operation such that an endpoint will become primed only after a SOF is received. After the DCD writes the prime bit, the prime bit will be cleared as usual to indicate to software that the device controller completed a priming the dTD for transfer. Internal to the design, the device controller hardware masks that prime start until the next frame boundary. This behavior is hidden from the DCD but occurs so that the device controller can match the dTD to a specific (micro)frame. Another difference with isochronous endpoints is that the transaction must wholly complete in a (micro)frame. Once an ISO transaction is started in a (micro)frame it will retire the corresponding dTD when MULT transactions occur or the device controller finds a fulfillment condition. The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire the ISO-dTD and move to the next ISO-dTD. It is important to note that fulfillment errors are only caused due to partially completed packets. If no activity occurs to a primed ISO-dTD, the transaction will stay primed indefinitely. This means it is up to software discard transmit ISO-dTDs that pile up from a failure of the host to move the data. Finally, the last difference with ISO packets is in the data level error handling. When a CRC error occurs on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is noted by setting the Transaction Error bit and the data is stored as usual for the application software to sort out. • TX Packet Retired — MULT counter reaches zero. — Fulfillment Error [Transaction Error bit is set] – # Packets Occurred > 0 AND # Packets Occurred < MULT Note: For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD Multiplier Override field in hardware versions 2.3 and later. If the Multiplier Override is zero, the MULT Counter is initialized to the Multiplier in the QH. • RX Packet Retired: — MULT counter reaches zero. — Non-MDATA Data PID is received** – ** Exit criteria only valid in hardware version 2.3 or later. Previous to hardware version 2.3, any PID sequence that did not match the MULT field exactly would be flagged as a transaction error due to PID mismatch or fulfillment error. — Overflow Error: – Packet received is > maximum packet length. [Buffer Error bit is set] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-208 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) – Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set] — Fulfillment Error [Transaction Error bit is set] – # Packets Occurred > 0 AND # Packets Occurred < MULT — CRC Error [Transaction Error bit is set ] Note: For ISO, when a dTD is retired, the next dTD is primed for the next frame. For continuous (micro)frame to (micro)frame operation the DCD should ensure that the dTD linked-list is out ahead of the device controller by at least two (micro)frames. Isochronous Pipe Synchronization When it is necessary to synchronize an isochroous data pipe to the host, the (micro)frame number (FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro)frame number [N], the DCD should interrupt on SOF during frame N-1. When the FRINDEX=N–1, the DCD must write the prime bit. The device controller will prime the isochronous endpoint in (micro)frame N–1 so that the device controller will execute delivery during (micro)frame N. CAUTION Priming an endpoint towards the end of (micro)frame N-1 will not guarantee delivery in (micro)frame N. The delivery may actually occur in (micro)frame N+1 if device controller does not have enough time to complete the prime before the SOF for packet N is received. Isochronous Endpoint Bus Response Matrix Table 30-93. Isochronous Endpoint Bus Response Matrix Stall Setup In Out Ping Invalid STALL NULL Packet Ignore Ignore Ignore Not Primed STALL NULL Packet Ignore Ignore Ignore Primed STALL Transmit Receive Ignore Ignore Underflow N/A BS Error N/A Ignore Ignore Overflow N/A N/A Drop Packet Ignore Ignore BS Error = Force Bit Stuff Error NULL Packet = Zero Length Packet MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-209 High-Speed USB On-The-Go (HS USB-OTG) 30.8.6.4 Managing Queue Heads E ndp oint Q ueue H eads T rans fer B uffer P ointer T ran sfer B uffer E ndp oint Q H 0 – O ut T rans fer B uffer P ointer E ndp oint Q H 0 – In E ndp oint Q H 1 – O ut T rans fer B uffer P ointer Tran sfer B uffer T rans fer B uffer P oin te r T ran sfer B uffer Tran sfer B uffer U p to 32 elem ents E ndpoint T ransfer D escriptor E N D P O IN T L IS T A D D R Figure 30-76. End Point Queue Head Diagram The device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device Transfer Descriptor (dTD). An area of memory pointed to by ENDPOINTLISTADDR contains a group of all dQH’s in a sequential list as shown in Figure 30-76. The even elements in the list of dQH’s are used for receive endpoints (OUT/SETUP) and the odd elements are used for transmit endpoints (IN/INTERRUPT). Device transfer descriptors are linked head to tail starting at the queue head and ending at a terminate bit. Once the dTD has been retired, it will no longer be part of the linked list from the queue head. Therefore, software is required to track all transfer descriptors since pointers will no longer exist within the queue head once the dTD is retired (see section Software Link Pointers). In addition to the current and next pointers and the dTD overlay examined in section Operational Model For Packet Transfers, the dQH also contains the following parameters for the associated endpoint: Multipler, Maximum Packet Length, Interrupt On Setup. The complete initialization of the dQH including these fields is demonstrated in the next section. 30.8.6.4.1 Queue Head Initialization One pair of device queue heads must be initialized for each active endpoint. To initialize a device queue head: • Write the wMaxPacketSize field as required by the USB Chapter 9 or application specific protocol. • Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO endpoints, set the multiplier to 1,2, or 3 as required bandwidth an in conjuction with the USB Chapter 9 protocol. Note: In FS mode, the multiplier field can only be 1 for ISO endpoints. • Write the next dTD Terminate bit field to “1”. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-210 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • • Write the Active bit in the status field to “0”. Write the Halt bit in the status field to “0”. Note: The DCD must only modify dQH if the associated endpoint is not primed and there are no outstanding dTD’s. 30.8.6.4.2 Operational Model For Setup Transfers As discussed in section Control Endpoint Operation Model, setup transfer requires special treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH. Upon receiving notification of the setup packet, the DCD should handle the setup transfer as demonstrated here: 1. Copy setup buffer contents from dQH - RX to software buffer. 2. Acknowledge setup backup by writing a “1” to the corresponding bit in ENDPTSETUPSTAT. Note: The acknowledge must occur before continuing to process the setup packet. Note: After the acknowledge has occurred, the DCD must not attempt to access the setup buffer in the dQH–RX. Only the local software copy should be examined. 3. Check for pending data or status dTD’s from previous control transfers and flush if any exist as discussed in section Flushing/De-priming an Endpoint. 4. Decode setup packet and prepare data phase [optional] and status phase transfer as required by the USB Chapter 9 or application specific protocol. Note: It is possible for the device controller to receive setup packets before previous control transfers complete. Existing control packets in progress must be flushed and the new control packet completed. 30.8.6.5 30.8.6.5.1 Managing Transfers with Transfer Descriptors Software Link Pointers It is necessary for the DCD software to maintain head and tail pointers to the for the linked list of dTDs for each respective queue head. This is necessary because the dQH only maintains pointers to the current working dTD and the next dTD to be executed. The operations described in next section for managing dTD will assume the DCD can use reference the head and tail of the dTD linked list. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-211 High-Speed USB On-The-Go (HS USB-OTG) Note: To conserve memory, the reserved fields at the end of the dQH can be used to store the Head & Tail pointers but it still remains the responsibility of the DCD to maintain the pointers. H ead P o inter current E ndpoint QH n ext T ail P ointer C o m pleted dT D s Q ueued dT D s Figure 30-77. Software Link Pointers 30.8.6.5.2 Building a Transfer Descriptor Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. Use the following procedure for building dTDs. Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit address 4:0 would be equal to “00000” Write the following fields: 1. Initialize first 7 DWords to 0. 2. Set the terminate bit to “1”. 3. Fill in total bytes with transfer size. 4. Set the interrupt on complete if desired. 5. Initialize the status field with the active bit set to “1” and all remaining status bits set to “0”. 6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. 7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointer. 30.8.6.5.3 Executing A Transfer Descriptor To safely add a dTD, the DCD must be follow this procedure which will handle the event where the device controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list. Determine whether the link list is empty: — Check DCD driver to see if pipe is empty (internal representation of linked-list should indicate if any packets are outstanding) • Case 1: Link list is empty — 1. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation. — 2. Clear active & halt bit in dQH (in case set from a previous error). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-212 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) • — 3. Prime endpoint by writing ‘1’ to correct bit position in ENDPTPRIME. Case 2: Link list is not empty — 1. Add dTD to end of linked list. — 2. Read correct prime bit in ENDPTPRIME—if ‘1’ DONE. — 3. Set ATDTW bit in USBCMD register to ‘1’. — 4. Read correct tatus bit in ENDPTSTAT. (store in tmp. variable for later) — 5. Read ATDTW bit in USBCMD register. — If ‘0’ goto 3. — If ‘1’ continue to 6. — 6. Write ATDTW bit in USBCMD register to ‘0’. — 7. If status bit read in (3) is ‘1’ DONE. — 8. If status bit read in (3) is ‘0’ then Goto Case 1: Step 1. Transfer Completion 30.8.6.5.4 After a dTD has been initialized and the associated endpoint primed the device controller will execute the transfer upon the host-initiated request. The DCD will be notified with a USB interrupt if the Interrupt On Complete bit was set or alternately, the DCD can poll the endpoint complete register to find when the dTD had been executed. After a dTD has been executed, DCD can check the status bits to determine success or failure. Multiple dTD can be completed in a single endpoint complete notification. After clearing the notification, DCD must search the dTD linked list and retire all dTDs that have finished (Active bit cleared). CAUTION By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed successfully. Success is determined with the following combination of status bits: • Active = 0 • Halted = 0 • Transaction Error = 0 • Data Buffer Error = 0 Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in the Device Error Matrix. In addition to checking the status bit the DCD must read the Transfer Bytes field to determine the actual bytes transferred. When a transfer is complete, the Total Bytes transferred is by decremented by the actual bytes transferred. For Transmit packets, a packet is only complete after the actual bytes reaches zero, but for receive packets, the host may send fewer bytes in the transfer according the USB variable length packet protocol. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-213 High-Speed USB On-The-Go (HS USB-OTG) 30.8.6.5.5 Flushing/De-priming an Endpoint It is necessary for the DCD to flush to de-prime one more endpoints on a USB device reset or during a broken control transfer. There may also be application specific requirements to stop transfers in progress. The following procedure can be used by the DCD to stop a transfer in progress: 1. Write a ‘1’ to the corresponding bit(s) in ENDPTFLUSH. 2. Wait until all bits in ENDPTFLUSH are ‘0’. — Software note: this operation may take a large amount of time depending on the USB bus activity. It is not desirable to have this wait loop within an interrupt service routine. 3. Read ENDPTSTAT to ensure that for all endpoints commanded to be flushed, that the corresponding bits are now ‘0’. If the corresponding bits are ‘1’ after step #2 has finished, then the flush failed as described in the following: — Explanation: In very rare cases, a packet is in progress to the particular endpoint when commanded flush using ENDPTFLUSH. A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully. The DCD may need to repeatedly flush any endpoints that fail to flush be repeating steps 1-3 until each endpoint is successfully flushed. 30.8.6.5.6 Device Error Matrix Table 30-94. Device Error Matrix The following table summarizes packet errors that are not automatically handled by the Device Controller. Error Overflow ** ISO Packet Error ISO Fulfillment Error Direction RX RX Both Packet Type Any ISO ISO 1 0 0 Data Buffer Error Bit 0 1 1 Transaction Error Bit Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a data buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as indicated. Error Descriptions: Error Overflow Description Number of bytes received exceeded max. packet size or total buffer length. ** This error will also set the Halt bit in the dQH and if there are dTDs remaining in the linked list for the endpoint, then those will not be executed. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-214 Freescale Semiconductor High-Speed USB On-The-Go (HS USB-OTG) Error ISO Packet Error ISO Fulfillment Error Description CRC Error on received ISO packet. Contents not guaranteed to be correct. Hst failed to complete the number of packets defined in the dQH mult field within the given (micro)frame. For scheduled data delivery the DCD may need to readjust the data queue because a fulfillment error will cause Device Controller to cease data transfers on the pipe for one (micro)frame. During the “dead” (micro)frame, the Device Controller reports error on the pipe and primes for the following frame. 30.8.6.6 Servicing Interrupts The interrupt service routine must consider that there are high-frequency, low-frequency operations, and error operations and order accordingly. 30.8.6.6.1 High-Frequency Interrupts High frequency interrupts in particular should be handed in the order below. The most important of these is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible. Table 30-95. High Frequency Interrupt Events Execution Order 1a Interrupt USB Interrupt ** ENDPTSETUPSTATUS Action Copy contents of setup buffer and acknowledge setup packet (as indicated in section Managing Queue Heads). Process setup packet according to USB 2.0 Chapter 9 or application specific protocol. Handle completion of dTD as indicated in section Managing Queue Heads. Action as deemed necessary by application. This interrupt may not have a use in all applications. 1b 2 USB Interrupt ** ENDPTCOMPLETE SOF Interrupt ** It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service Routine. 30.8.6.6.2 Low-Frequency Interrupts The low frequency events include the following interrupts. These interrupt can be handled in any order since they don’t occur often in comparison to the high-frequency interrupts. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 30-215 High-Speed USB On-The-Go (HS USB-OTG) Table 30-96. Low Frequency Interrupt Events Interrupt Port Change Sleep Enable (Suspend) Reset Received Action Change software state information. Change software state information. Low power handling as necessary. Change software state information. Abort pending transfers. 30.8.6.6.3 Error Interrupts Table 30-97. Error Interrupt Events Error interrupts will be least frequent and should be placed last in the interrupt service routine. Interrupt USB Error Interrupt. Action This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt (w/ ENDPTCOMPLETE). Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD. System Error MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 30-216 Freescale Semiconductor Book II, Part 5: Timer Peripherals Introduction The i.MX27 processor provides a variety of timers for timing and scheduling of software applications, as well as peripherals and audio waveform generation. The timers covered in this part are as follows: Chapter 31, “General Purpose Timer (GPT),” on page 31-1 Chapter 32, “Pulse-Width Modulator (PWM),” on page 32-1 Chapter 33, “Real Time Clock (RTC),” on page 33-1 Chapter 34, “Watchdog Timer (WDOG),” on page 34-1 General Purpose Timer (GPT) The General Purpose Timer (GPT) has a 32 bit up-counter. The timer counter value can be captured in a register using an event on an external pin. The capture trigger can be programmed to be a rising or/and falling edge. The GPT can also generate an event on ipp_do_cmpout pins and an interrupt when the timer reaches a programmed value. It has a 12-bit prescaler providing a programmable clock frequency derived from multiple clock sources. The GPT has one 32 bit up-counter with clock source selection, including external clock, two input capture channels with programmable trigger edge, and three output compare channels with programmable output mode. The GPT can perform a forced compare and can configured to be programmed to be active in low power and debug modes Interrupt generation can be programmed for capture, compare, rollover events and the timers offers both restart or free-run modes of operation. Pulse-Width Modulation Module (PWM) While the Pulse-Width Modulation Module (PWM) is a timer/counter, its primary use is for sound and melody generation. The PWM of the i.MX27 uses a 16-bit counter which is optimized to generate sound from stored sample audio images and it can also generate tones. It uses the 16-bit resolution and a 4 × 16 data FIFO to generate sound. The PWM follows IP Bus protocol for interfacing with the ARM9 processor core. It does not have any interface signals with any other module inside the chip except for clock and reset inputs from the Clock and Reset Controller module and interrupt signals to the processor interrupt handler. There is a single output signal going to a pin in the i.MX27. The PWM module of the i.MX27 offers the following features: • Pulse-width modulation (PWM) module has the following features: • 4 x 16 FIFO to minimize interrupt overhead MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 • • • 16-bit resolution Sound and melody generation Secondary Display contrast control Real Time Clock (RTC) The Real Time Clock (RTC) module provides a current stamp of seconds, minutes, hours and days. Alarm and Timer functions are also available for programming. RTC support dates from the year 1980 to 2050. The RTC module includes the following features: • Full clock—days, hours, minutes, seconds • Minute countdown timer with interrupt • Programmable daily alarm with interrupt • Sampling timer with interrupt • Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts • Operation at 32.768 kHz or 32 kHz, or 38.4 kHz (determined by reference clock crystal) Watchdog Timer (WDOG) The Watchdog (WDOG) timer module protects the i.MX27 against system failures by providing a method of escaping from unexpected events or programming errors. Once the WDOG module is activated, it must be serviced by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the WDOG Timer module either asserts the wdog signal or a system reset signal wdog_rst depending on software configuration. The WDOG Timer module also generates a system reset via a software write to the Watchdog Control Register (WCR) a detection of a clock monitor event, an external reset, an external JTAG reset signal, or if a power-on-reset has occurred. The wdog signal is asserted via a software write to the WCR, a detection of a clock monitor event, or upon a watchdog time-out. In case of a Time-out Even, the following actions can be programmed: • Interrupt to the ARM9 • Internal Reset (can follow the interrupt after a predefined time-out) • External pin toggle for external devices reset (issued together with the Internal Reset) The WDOG module can continue/suspend the timer operation in the low power modes (WAIT, DOZE and STOP). For ARM (DOZE and STOP), it emulates these modes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Chapter 31 General Purpose Timer (GPT) 31.1 Introduction The i.MX27 device contains six identical 32-bit general-purpose timers (GPT) with programmable prescalers and compare and capture registers. Each timer’s counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. Each GPT can also generate an interrupt when the timer reaches a programmed value. Each GPT has an11-bit prescaler providing a programmable clock frequency derived from multiple clock sources. Figure 31-1 illustrates the general-purpose timer block diagram for one of the timers. The General-Purpose Timers have the following features: • Programmable sources for the clock input, including external clock • Input capture capability with programmable trigger edge • Output compare with programmable mode • Free-run and restart modes • Software reset function MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 31-1 General Purpose Timer (GPT) 1/4 Prescaler mclk IPG_CLK_PERCLK IPG_CLK_32K 11bit 1... 2048 FRR pclk Timer Counter register TIN sync Input Capture Logic Timer Input Capture register Module Interrupt Line IRQEN IP-Bus REG r/w comp status Timer Output Compare register cmp Output Control Logic TOUT Figure 31-1. General-Purpose Timer Block Diagram 31.2 Operation After a hardware reset the Counter, Control, Prescaler, Status and Capture registers of the GPT are reset. The Compare value is set to 0xFFFFFFFF. The output pin (TOUT) is also reset. The GPT is enabled when the TEN bit in the GPT Control Register (TCTL) is set and the counter starts running. It is recommended that all the registers be set to appropriate values first before enabling the GPT. When the TEN bit is cleared the counter value freezes or clears depending on CC bit in GPT Control Register (TCTL). All other register values are retained. There is a Software Reset bit (SWR) in the TCTL register. When this bit is set the GPT generates a reset signal for 3 IPG_CLK periods and this bit clears after 5 IPG_CLK periods. The software reset results in all the registers in the GPT being reset except for the TEN bit which is not cleared by software reset if set. The software reset can be asserted with the TEN bit off, however, the IPG_CLK clock (module clock) signals to GPT must be on for the software reset to be functional. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 31-2 Freescale Semiconductor General Purpose Timer (GPT) 31.2.1 Clocks The clock that feeds the prescaler can be selected from the following: • ipg_clk_perclk (divided by 1 or by 4). The frequency of ipg_clk_perclk is constant and is independent of changes to the IPG_CLK. The module internally synchronizes PERCLK to the IPG_CLK. This clock is synchronized inside the module to IPG_CLK. Hence the frequency of this clock has to be at least 1/4 that of IPG_CLK if the prescaler is programmed to divide by 1. • GPT I/O pin (IPP_GPT_TIN). External clock from outside the chip. • 32 kHz clock (IPG_CLK_32K). This is the 32 kHZ low reference clock which is provided by CRM. This clock is supposed to be on in low power mode when the ipg_clk is turned off. Thus the GPT can be run on this clock in low power mode. The CRM is expected to provide this clock after synchronizing it to ahb_clk in normal functional mode and switch to the unsynchronized version in the low power mode. The clock input source is determined by the CLKSOURCE field of the GPT control register. The CLKSOURCE value should only be changed when the GPT is disabled. The external clock coming from the IPP_GPT_TIN pin is not synchronized with IPG_CLK. The GPT prescaler register (TPRER) selects the divide ratio of the input clock that drives the main counter (TCN). The prescaler can divide the input clock by a value between 1 and 2048. 31.2.2 Operation During Low-Power Mode In low-power mode when the IPG_CLK (module clock used for register accesses) and IPG_CLK_PERCLK clocks are switched off, the GPT can also work only if the ipg_clk_32k is available. The counter continues to run, when it reaches the value contained in the compare register, the compare interrupt will occur. The capture interrupt can also be produced in low-power mode if the capture function is enable. When the capture interrupt or compare interrupt occurs, the status register can be written on the positive edge of mclk. 31.2.3 Capture Event Each GPT have a 32-bit capture register that takes a snapshot of the counter when a defined transition of TIN is detected by the capture edge detector. The type of transition that triggers this capture is selected by the CAP field of the GPT Control Register (TCTL). Because the capture event is triggered by mclk, so each transition must be valid for at least two mclk periods to ensure a capture event is triggered. When a capture event occurs, the corresponding status bit is set in the GPT status register (TSTAT) and an interrupt is posted if the capture function is enabled and if the CAPTEN bit of the GPT control register is set. If another capture event occurs the new count value will still be captured in the capture register even if the interrupt is not serviced and capture status bit is set. 31.2.4 Compare Event Each GPT have a 32-bit compare register. When the value in this register matches with the value of the counter register a compare event occurs. On a compare event the appropriate GPT output pin (TOUT) is MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 31-3 General Purpose Timer (GPT) toggled or an active low pulse (for one count period) is generated on it according to the setting of Output Mode (OM) bit in the GPT control register. When in toggle mode the toggling takes place at the end of the count period in which the match has occurred. The corresponding status bit is set in the status register and an interrupt is posted if the COMPEN bit of the GPT control register is set. The GPT output pin continues to produce an output on a compare event even if the interrupt is not serviced and compare status bit is set. 31.2.5 Modes of Operation The GPT can be configured for free-run or restart modes by programming the Free-run/Restart bit (FRR) of the GPT control register. • Restart mode: In restart mode, when a compare event occurs, the counter resets to 0x00000000. Subsequently it resumes counting up. • Freerun mode: In free-run mode, when a compare event occurs, it has no effect on the counter value. The counter continues counting until 0xFFFFFFFF is reached and then it is reset to 0x00000000 and resumes counting. 31.3 Programming Model The General-Purpose Timer modules each have six user-accessible 32-bit registers. They are shown with offsets from their respective base addresses in the detailed register descriptions. Table 31-1 summarizes the general-purpose timer registers and their addresses. Figure 31-2 provides the detailed register summary. Table 31-1. GPT Register Summary Description GPT Control Register 1 GPT Control Register 2 GPT Control Register 3 GPT Control Register 4 GPT Control Register 5 GPT Control Register 6 GPT Prescaler Register 1 GPT Prescaler Register 2 GPT Prescaler Register 3 GPT Prescaler Register 4 GPT Prescaler Register 5 GPT Prescaler Register 6 GPT Compare Register 1 Name TCTL1 TCTL2 TCTL3 TCTL4 TCTL5 TCTL6 TPRER1 TPRER2 TPRER3 TPRER4 TPRER5 TPRER6 TCMP1 Address 0x10003000 0x10004000 0x10005000 0x10019000 0x1001a000 0x1001f000 0x10003004 0x10004004 0x10005004 0x10019004 0x1001a004 0x1001f004 0x10003008 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 31-4 Freescale Semiconductor General Purpose Timer (GPT) Table 31-1. GPT Register Summary (continued) Description GPT Compare Register 2 GPT Compare Register 3 GPT Compare Register 4 GPT Compare Register 5 GPT Compare Register 6 GPT Capture Register 1 GPT Capture Register 2 GPT Capture Register 3 GPT Capture Register 4 GPT Capture Register 5 GPT Capture Register 6 GPT Counter Register 1 GPT Counter Register 2 GPT Counter Register 3 GPT Counter Register 4 GPT Counter Register 5 GPT Counter Register 6 GPT Status Register 1 GPT Status Register 2 GPT Status Register 3 GPT Status Register 4 GPT Status Register 5 GPT Status Register 6 Name TCMP2 TCMP3 TCMP4 TCMP5 TCMP6 TCR1 TCR2 TCR3 TCR4 TCR5 TCR6 TCN1 TCN2 TCN3 TCN4 TCN5 TCN6 TSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5 TSTAT6 Address 0x10004008 0x10005008 0x10019008 0x1001a008 0x1001f008 0x1000300C 0x1000400C 0x1000500C 0x1001900C 0x1001a00C 0x1001f00C 0x10003010 0x10004010 0x10005010 0x10019010 0x1001a010 0x1001f010 0x10003014 0x10004014 0x10005014 0x10019014 0x1001a014 0x1001f014 Table 31-2. General Purpose Timer Register Summary Name 0x1000_3000 (TCTL1)– 0x1000_F000 (TCTL6) R W R 0 0 0 0 0 CC W SWR OM FRR CAP CAP COM T EN P EN CLK SOURCE TEN 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 31-5 General Purpose Timer (GPT) Table 31-2. General Purpose Timer Register Summary (continued) Name 0x1000_3004 (TPRER1)– 0x1000_F004 (TPRER6) R W R W 0x1000_3008 (TCMP1)– 0x1000_F008 (TCMP6) R COMPARE VALUE W R COMPARE VALUE W 0x1000_300C (TCR1)– 0x1000_F00C (TCR6) R W R W 0x1000_3010 (TCN1)– 0x1000_F010 (TCN6) R W R W 0x1000_3014 (TSTAT1)– 0x1000_F014 (TSTAT6) R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP T CO MP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER VALUE COUNTER VALUE CAPTURE VALUE CAPTURE VALUE 0 0 0 0 0 PRESCALER 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W1C W1C 31.3.1 GPT Control Registers The GPT control (TCTL) register controls the overall operation of the timer. Figure 31-2 shows field assignments for this register and Table 31-3 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 31-6 Freescale Semiconductor General Purpose Timer (GPT) 0x1000_3000 (TCTL1) 0x1000_4000 (TCTL2) 0x1000_5000 (TCTL3) 0x1000_9000 (TCTL4) 0x1000_A000 (TCTL5) 0x1000_F000 (TCTL6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SWR W Reset 0 0 0 0 0 CC OM 0 FRR 0 0 CAP 0 CAPT COM EN P EN 0 0 CLK SOURCE 0 0 0 TEN 0 0 0 0 0 0 Figure 31-2. GPT Control Register Table 31-3. GPT Control Registers Field Descriptions Name 31–16 SWR 15 Reserved. SOFTWARE RESET. GPT is reset when this bit is set to 1. This bit is set when the module is in reset state and is cleared when the reset procedure is over. The reset signal is asserted 2 clock cycles (IPG_CLK) after this bit is set and the reset remains asserted for 3 clock cycles. The whole reset procedure is complete 5 clock cycles after this bit is asserted This software reset does not reset the TEN bit. 0 GPT is not reset. 1 GPT is reset. Reserved. These bits are reserved and should not be used. Counter Clear. This bit determines whether the counter is to be cleared when TEN=0 (timer disabled). 0 Counter is halted at the current count when TEN = 0. 1 Counter will be reset when TEN=0. Output Mode. This bit controls the output mode of the timer after compare event occurs. 0 Active-low pulse for one clock period. 1 Toggle output. Free-Run/Restart. This bit controls how the timer operates after a compare event occurs. In free-run mode, the timer continues counting till 0xffffffff. In restart mode, the counter resets to 0x00000000 and resumes counting. 0 Restart mode 1 Free-run mode Description 14–11 10 CC 9 OM 8 FRR MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 31-7 General Purpose Timer (GPT) Table 31-3. GPT Control Registers Field Descriptions (continued) Name 7–6 CAP Description Capture Edge. This field controls the operation of the capture function. The value in the counter is loaded into the Capture register on the detection of an event on the TIN pin. The event which will trigger this capture is determined by this field. 00 Capture function disabled 01 Capture on rising edge and generate interrupt 10 Capture on falling edge and generate interrupt 11 Capture on rising or falling edge and generate interrupt Capture Interrupt Enable. This bit enables the capture interrupt. 0 Capture interrupt is disabled. 1 Capture interrupt is enabled. Compare Interrupt Enable. This bit enables the compares interrupt. 0 Compare interrupt disabled. 1 Compare interrupt enabled. Clock Source. This field controls the source of the clock to the prescaler. The stop-count freezes the timer at its current value. Note: This field value should only be changed when the GPT is disabled. 000 Stop count (clock disabled). 001 PERCLK1 to prescaler. 010 PERCLK1 divided by 4 to prescaler. 011 TIN to prescaler. 1xx 32 kHz clock to prescaler. Timer Enable. TEN bit enables the general-purpose timer. The bit can be cleared either by writing 0 or by a hardware reset. The bit cannot be cleared by asserting the software reset. 0 Timer is disabled 1 Timer is enabled. 5 CAPT EN 4 COMP EN 3–1 CLKSOURCE 0 TEN 31.3.2 GPT Prescaler Register The GPT prescaler register (TPRER) controls the divide value of the prescaler. Figure 31-3 shows field assignments for this register and Table 31-4 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 31-8 Freescale Semiconductor General Purpose Timer (GPT) 0x1000_3004 (TPRER1) 0x1000_4004 (TPRER2) 0x1000_5004 (TPRER3) 0x1000_9004 (TPRER4) 0x1000_A004 (TPRER5) 0x1000_F004 (TPRER6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SWR W Reset 0 0 0 0 0 PRESCALER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 31-3. GPT Control Register . Table 31-4. GPT Prescaler Register Description Name 31–11 10–0 PRESCALER Reserved. Counter Clock Prescaler. This field determines the division value of the prescaler between 1 and 2048. 0x00 divides by 1 and 0x7FF divides by 2048.Note: When ipg_clk_perclk freq.= IPG_CLK FREQ. the minimum value to be programmed in PRESCALER field should be > 2 to get proper functioning of the module. 0x00 = Divide by 1 ... 0x7ff = Divide by 2048 Description 31.3.3 GPT Compare Register The GPT compare (TCMP) register contains the value that is compared with the free-running counter. A compare event is generated when the counter matches the value in this register. This register reset to 0xFFFFFFFF. Figure 31-4 shows field assignments for this register and Table 31-5 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 31-9 General Purpose Timer (GPT) 0x1000_3008 (TCMP1) 0x1000_4008 (TCMP2) 0x1000_5008 (TCMP3) 0x1000_9008 (TCMP4) 0x1000_A008 (TCMP5) 0x1000_F008 (TCMP6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R COMPARE VALUE W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R COMPARE VALUE W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 31-4. GPT Compare Register Table 31-5. GPT Compare Registers Descriptions Name 31–0 COMPARE Description Compare Value. A compare event occurs when the counter value matches the value in this field. 31.3.4 GPT Capture Register This register is read only, and resets to 0x00000000. The GPT capture register (TCR) stores the counter value when a capture event occurs. Figure 31-5 shows field assignments for this register and Table 31-6 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 31-10 Freescale Semiconductor General Purpose Timer (GPT) 0x1000_300C (TCR1) 0x1000_400C (TCR2) 0x1000_500C (TCR3) 0x1000_900C (TCR4) 0x1000_A00C (TCR5) 0x1000_F00C (TCR6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R W Reset 0 0 0 0 0 0 0 CAPTURE VALUE 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 CAPTURE VALUE 0 0 0 0 0 0 0 0 0 Figure 31-5. GPT Capture Register Table 31-6. GPT Capture Registers Description Name 31–0 CAPTURE Description Capture Value. This field stores the counter value at the time of a capture event. 31.3.5 GPT Counter Register The read-only GPT counter (TCN) register can be read at anytime without disturbing the current count. Figure 31-6 shows field assignments for this register and Table 31-7 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 31-11 General Purpose Timer (GPT) 0x1000_3010 (TCN1) 0x1000_4010 (TCN2) 0x1000_5010 (TCN3) 0x1000_9010 (TCN4) 0x1000_A010 (TCN5) 0x1000_F010 (TCN6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R W Reset 0 0 0 0 0 0 0 COUNTER VALUE 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 COUNTER VALUE 0 0 0 0 0 0 0 0 0 Figure 31-6. GPT Counter Register Table 31-7. GPT Counter Register Field Descriptions Name 31–0 COUNT Description Count Value. This field contains the current count value. Whenever there is an update of compare register the counter is reset to zero and the count starts afresh. 31.3.6 GPT Status Register The GPT status (TSTAT) register (write 1 to clear) indicates the GPT’s status. When a capture event occurs, the CAPT bit is set. When a compare event occurs, the COMP bit is set. These bits can only be cleared by writing 1 to clear the interrupt status. Figure 31-6 shows field assignments for this register and Table 31-7 provides the field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 31-12 Freescale Semiconductor General Purpose Timer (GPT) 0x1000_3014 (TSTAT1) 0x1000_4014 (TSTAT2) 0x1000_5014 (TSTAT3) 0x1000_9014 (TSTAT4) 0x1000_A014 (TSTAT5) 0x1000_F014 (TSTAT6) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPT COMP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w1c w1c Figure 31-7. GPT Status Register Table 31-8. GPT Status Register Field Descriptions Name 31–2 1 CAPT 0 COMP Reserved. Capture Event. This bit indicates that a capture event has occurred. 0 No capture event 1 A capture event has occurred Compare Event. This bit indicates that a compare event has occurred. 0 No compare event 1 A compare event has occurred Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 31-13 General Purpose Timer (GPT) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 31-14 Freescale Semiconductor Chapter 32 Pulse-Width Modulator (PWM) The Pulse-Width Modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 x 16 data FIFO to generate sound. 32.1 Overview This section presents an overview of the PWM. Figure 32-1 illustrates the PWM block diagram. Clock Off ipg_clk 12-Bit Prescaler System Peripheral Bus ipg_clk_highfreq ipg_clk_32k IRQ_B PWM Interrupts CLKSRC Prescaler Clock Output (PCLK) 16-Bit Counter Register CMPIE CMP POUTC PWMO 16-Bit Period Register CMP S CMP R ROV POUTC 16-Bit Sample Register ROVIE 4x16-Bit FIFO IRQEN Figure 32-1. Pulse-Width Modulator Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-1 Pulse-Width Modulator (PWM) The following features characterize the PWM: • 16-bit up-counter with clock source selection • 4 x 16 FIFO to minimize interrupt overhead • 12-bit prescaler for division of clock • Sound and melody generation • Active high or active low configurable output • Can be programmed to be active in low power and debug modes • Interrupts at compare and rollover 32.2 Signal Description The PWM follows IP bus protocol for interfacing with the processor core. It does not have any interface signals with any other module inside the chip except for clock and reset inputs from the Clock Control module (CCM) and interrupt signals to the processor interrupt handler. There is a single output signal going outside the chip boundary. Figure 32-2 shows the PWM signals at the module boundary. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-2 Freescale Semiconductor Pulse-Width Modulator (PWM) ipg_hard_async_reset ipg_clk_highfreq ipg_clk ipg_enable_clk ipg_clk_32k ipg_clk_s ips_module_en ips_addr[13:2] ips_rwb ips_byte_31_24 ips_byte_23_16 ips_byte_15_8 ips_byte_7_0 ips_wdata[31:0] resp_sel ipg_debug ipg_doze ipg_wait ipg_stop ipt_se_gatedclk ipt_se_async ipt_mode ipt_reset ipi_int_pwm_rovi ipi_int_pwm_cmpi ipi_int_pwm_fifoi ipi_int_pwm Pulse Width Modulator ips_rdata[31:0] ips_xfr_err ips_xfr_wait ipp_do_pwmo ipp_obe_pwmo Figure 32-2. PWM Module Signals 32.2.1 External Signals PWM has a single output signal to the i.MX27 chip boundary named PWMO. Table 32-1 describes the external signals for the i.MX27 device. Table 32-1. i.MX27 External Signals Name PWMO Direction Output Function This is the functional output of the PWM. The modulated signal of the module is observed at this pin Reset State 0 Pull-Up — MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-3 Pulse-Width Modulator (PWM) 32.2.1.1 PWMO Signal The PWMO is the modulated output signal of the PWM. This signal can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the PWM. The smallest period can be two ipg_clk clock periods with duty cycle of 50%. 32.3 Memory Map and Register Definition The PWM module includes 6 user-accessible 32-bit registers. Section 32.3.2, “Register Descriptions” provides the detailed descriptions for all of the PWM registers. Table 32-2. PWM Memory Map Address 0x1000_6000 (PWMCR) 0x1000_6004 (PWMSR) 0x1000_6008 (PWMIR) 0x1000_600C (PWMSAR) 0x1000_6010 (PWMPR) 0x1000_6014 (PWMCNR) Register PWM Control Register (PWMCR) PWM Status Register (PWMSR) PWM Interrupt Register (PWMIR) PWM Sample Register (PWMSAR) PWM Period Register (PWMPR) PWM Counter Register (PWMCNR) Access R/W R/W R/W R/W R/W R Reset Value 0x0000_0000 0x0000_0008 0x0000_0000 0x0000_0000 0x0000_FFFE 0x0000_0000 Section/Page 32.3.2.1/32-6 32.3.2.2/32-8 32.3.2.3/32-9 32.3.2.4/32-10 32.3.2.5/32-11 32.3.2.6/32-11 32.3.1 Register Summary Figure 32-3. Key to Register Fields Figure 32-3 shows the key to the register fields, and Table 32-3 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0 bit only bit only bit BIT to clear w1c bit BIT N/A Table 32-3. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-4 Freescale Semiconductor Pulse-Width Modulator (PWM) Table 32-3. Register Figure Conventions (continued) Convention 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. Description [signal_name] Reset value is determined by polarity of indicated signal. Table 32-4 shows the PWM register summary. Table 32-4. PWM Register Summary Name R 0x1000_6000 (PWMCR) W R PRESCALER W R W 0x1000_6004 (PWMSR) R W R 0x1000_6008 (PWMIR) W R W R 0x1000_600C (PWMSAR) W R SAMPLE[15:0] W R 0x1000_6010 (PWMPR) W R PERIOD[15:0] W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIE RIE FIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FW E w1c 0 CM ROV P w1c 0 w1c 0 FE w1c 0 0 0 0 FIFOAV 0 0 0 0 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 FWM STO DOZ WAI PEN EN TEN DB GE N BCT HCT R R POUTC CLKSRC SW R 0 REPEAT 0 0 EN 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-5 Pulse-Width Modulator (PWM) Table 32-4. PWM Register Summary (continued) Name R 0x1000_6014 (PWMCNR) W R W COUNT[15:0] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32.3.2 Register Descriptions This section contains the detailed register descriptions for the PWM registers. 32.3.2.1 PWM Control Register (PWMCR) The PWM control register (PWMCR) is used to configure the operating settings of the PWM. It contains the prescaler for the clock division. Figure 32-4 shows the register; Table 32-5 provides its field descriptions. 0x1000_6000 (PWMCR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 FWM STOP DOZ WAIT DBG EN EN EN EN 0 0 0 0 0 BCT R 0 HCT R 0 POUTC 0 0 CLKSRC 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PRESCALER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR REPEAT EN Figure 32-4. PWM Control Register (PWMCR) Table 32-5. PWMCR Field Descriptions Field 31–28 Reserved 27–26 Description Reserved. These reserved bits are always read as zero. FIFO Water Mark. These bits are used to set the data level at which the FIFO empty flag will be set and the corresponding interrupt generated 00 FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO. 01 FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO. 10 FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO. 11 FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-6 Freescale Semiconductor Pulse-Width Modulator (PWM) Table 32-5. PWMCR Field Descriptions (continued) Field 25 STOPEN Description Sleep Mode Enable. This bit keeps the PWM functional while in Sleep Mode. When this bit is cleared, the input clock is gated off in Sleep Mode. This bit is not affected by software reset. It is cleared by hardware reset. 0 Inactive in Sleep Mode 1 Active in Sleep Mode Doze Mode Enable. This bit keeps the PWM functional in doze mode. When this bit is cleared, the input clock is gated off in doze mode. This bit is not affected by software reset. It is cleared by hardware reset. 0 Inactive in doze mode 1 Active in doze mode Wait Mode Enable. This bit keeps the PWM functional in wait mode. When this bit is cleared, the input clock is gated off in wait mode. This bit is not affected by software reset. It is cleared by hardware reset. 0 Inactive in wait mode 1 Active in wait mode Debug Mode Enable. This bit keeps the PWM functional in debug mode. When this bit is cleared, the input clock is gated off in debug mode. This bit is not affected by software reset. It is cleared by hardware reset. 0 Inactive in debug mode 1 Active in debug mode Byte Data Swap Control. This bit determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register. 0 Byte ordering remains the same. 1 Byte ordering is reversed. Halfword Data Swap Control. This bit determines which halfword data from the 32-bit IP-Bus interface is written into the lower 16 bits of the sample register. 0 Halfword swapping does not take place. 1 Halfwords from write data bus are swapped. PWM Output Configuration. This bit field determines the mode of PWM output on the output pin. 00 Output pin is set at rollover and cleared at comparison 01 Output pin is cleared at rollover and set at comparison 10 PWM output is disconnected. 11 PWM output is disconnected. Select Clock Source. These bits determine which clock input will be selected for running the counter. After reset the system functional clock is selected. The input clock can also be turned off if these bits are set to 00. This field value should only be changed when the PWM is disabled 00 Clock is off 01 ipg_clk 10 ipg_clk_highfreq 11 ipg_clk_32k 24 DOZEN 23 WAITEN 22 DBGEN 21 BCTR 20 HCTR 19–18 POUTC 17–16 CLKSRC 15–4 Counter Clock Prescaler Value. This bit field determines the value by which the clock will be divided before it PRESCALER goes to the counter. 0x000 Divide by 1 0x001 Divide by 2 ... 0xFFF Divide by 4096 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-7 Pulse-Width Modulator (PWM) Table 32-5. PWMCR Field Descriptions (continued) Field 3 SWR Description Software Reset. PWM is reset when this bit is set to 1. It is a self clearing bit. A write 1 to this bit is a single wait state write cycle. When the module is in reset state this bit is set and is cleared when the reset procedure is over. Setting this bit resets all the registers to their reset values except for the STOPEN, DOZEN, WAITEN, and DBGEN bits in this control register. 0 PWM is out of reset. 1 PWM is undergoing reset. Sample Repeat. This bit field determines the number of times each sample from the FIFO is to be used. 00 Use each sample once 01 Use each sample twice 10 Use each sample four times 11 Use each sample eight times PWM Enable. This bit enables the PWM. If this bit is not enabled, the clock prescaler and the counter is reset. When the PWM is enabled, it begins a new period, the output pin is set to start a new period while the prescaler and counter are released and counting begins. 0 PWM is disabled. 1 PWM is enabled. 2–1 REPEAT 0 EN 32.3.2.2 PWM Status Register (PWMSR) The PWM status register (PWMSR) contains seven bits which display the state of the FIFO and the occurrence of rollover and compare events. The FIFOAV bit is read-only but the other four bits can be cleared by writing 1 to them. FE, ROV, and CMP bits are associated to FIFO-Empty, Roll-over, and Compare interrupts, respectively. Figure 32-5 shows the register; Table 32-6 provides its field descriptions. 0x1000_6004 (PWMSR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 FWE CMP ROV w1c w1c 0 w1c 0 FE w1c 1 0 FIFOAV 0 0 0 0 0 0 0 0 0 0 0 0 Figure 32-5. PWM Status Register (PWMSR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-8 Freescale Semiconductor Pulse-Width Modulator (PWM) Table 32-6. PWMSR Field Descriptions Field 31–7 Reserved 6 FWE 5 CMP 4 ROV 3 FE Description Reserved. These reserved bits are always read as zero. FIFO Write Error Status. This bit shows that an attempt has been made to write FIFO when it is full. 0 FIFO write error has not occurred. 1 FIFO write error has occurred. Compare Status. This bit shows that a compare event has occurred. 0 Compare event has not occurred. 1 Compare event has occurred. Roll-over Status. This bit shows that a roll-over event has occurred. 0 Roll-over event has not occurred. 1 Roll-over event has occurred. FIFO Empty Status Bit. This bit indicates the FIFO data level in comparison to the water level set by FWM field in the control register. 0 Data level is above water mark. 1 The data level falls below the mark set by the FWM field. FIFO Available. These read-only bits indicate the data level remaining in the FIFO. An attempted write to these bits will not affect their value and no transfer error is generated. 000 No data available 001 1 word of data in FIFO 010 2 words of data in FIFO 011 3 words of data in FIFO 100 4 words of data in FIFO 101 Unused 110 Unused 111 Unused 2–0 FIFOAV 32.3.2.3 PWM Interrupt Register (PWMIR) The PWM Interrupt register (PWMIR) contains three bits that control the generation of the compare, rollover and FIFO empty interrupts. Figure 32-6 shows the register; Table 32-7 provides its field descriptions. 0x1000_6008 (PWMIR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 CIE RIE 0 FIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 32-6. PWM Interrupt Register (PWMIR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-9 Pulse-Width Modulator (PWM) Table 32-7. PWMIR Field Descriptions Field 31–3 Reserved 2 CIE 1 RIE 0 FIE Description Reserved. These reserved bits are always read as zero. Compare Interrupt Enable. This bit controls the generation of the Compare interrupt. 0 Compare Interrupt is not enabled. 1 Compare Interrupt is enabled. Roll-over Interrupt Enable. This bit controls the generation of the Rollover interrupt. 0 Roll-over interrupt is not enabled. 1 Roll-over Interrupt is enabled. FIFO Empty Interrupt Enable. This bit controls the generation of the FIFO Empty interrupt. 0 FIFO Empty is interrupt disabled. 1 FIFO Empty is interrupt enabled. 32.3.2.4 PWM Sample Register (PWMSAR) The PWM sample register (PWMSAR) is the input to the FIFO. 16-bit words are loaded into the FIFO. The FIFO can be written and read when the PWM is disabled. The PWM runs at the last set duty-cycle setting if all the values of the FIFO has been utilized, until the FIFO is reloaded or the PWM is disabled. When a new value is written, the duty cycle changes after the current period is over. A value of zero in the sample register will result in the ipp_pwm_pwmo output signal being always low/high (POUTC =00 it will be low and POUTC = 01 it will be high), and hence no output waveform will be produced. If the value in this register is higher than the PERIOD + 1, the output will never be reset/set depending on POUTC value. Figure 32-7 shows the register; Table 32-8 provides its field descriptions. 0x1000_600C (PWMSAR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SAMPLE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 32-7. PWM Sample Register (PWMSAR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-10 Freescale Semiconductor Pulse-Width Modulator (PWM) Table 32-8. PWMSAR Field Descriptions Field 31–16 Reserved 15–0 SAMPLE Description These are reserved bits and writing a value will not affect the functionality of PWM and are always read as zero. Sample Value. This is the input to the 4x16 FIFO. The value in this register denotes the value of the sample being currently used. 32.3.2.5 PWM Period Register (PWMPR) The PWM period register (PWMPR) determines the period of the PWM output signal. After the counter value matches PERIOD + 1, the counter is reset to start another period. PWMO (Hz) = PCLK(Hz)/(period +2) A value of zero in the PWMPR results in a period of two clock cycles for the output signal. Writing 0xFFFF to this register achieves the same result as writing 0xFFFE. A change in the period value due to a write in PWMPR results in the counter being reset to zero and the start of a new count period. Figure 32-8 shows the register; Table 32-9 provides its field descriptions. 0x1000_6010 (PWMPR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PERIOD W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Figure 32-8. PWM Period Register (PWMPR) Table 32-9. PWMPR Field Descriptions Field 31–16 Reserved 15–0 PERIOD Description These are reserved bits and writing a value will not affect the functionality of PWM and are always read as zero. Period Value. These bits determine the Period of the count cycle. The counter counts up to [Period Value] +1 and is then reset to 0x0000. 32.3.2.6 PWM Counter Register (PWMCNR) The read-only pulse-width modulator counter register (PWMCNR) contains the current count value and can be read at any time without disturbing the counter. Figure 32-9 shows the register; Table 32-10 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-11 Pulse-Width Modulator (PWM) 0x1000_6014 (PWMCNR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read-only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 Figure 32-9. PWM Counter Register (PWMCNR) Table 32-10. PWMCNR Field Descriptions Field 31–16 Reserved 15–0 COUNT Description These are reserved bits and writing a value will not affect the functionality of PWM and are always read as zero. Counter Value. These bits are the counter register value and denotes the current count state the counter register is in. 32.4 Functional Description The following sections detail the PWM operation and function. 32.4.1 Operation The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by programming the appropriate registers. It has a 16-bit up counter which counts from 0x0000 until the counter value equals the [Value in Period register] + 1. After this match occurs the Counter is reset to 0x0000. At the beginning of a count period cycle, the PWMO pin is set to one (default) and the counter begins counting up from 0x0000. The sample value in the sample FIFO is compared on each count of prescaler clock. When the sample and count values match, the PWMO signal is cleared to zero (default). The counter continues counting until the period match occurs and subsequently another period cycle begins. When the PWM is enabled the counter starts running and generates an output with the reset values in the period and sample registers. It is recommended that the programming of these registers be done before PWM is enabled. A hardware reset results in all the PWM count and sample registers begin cleared and the FIFO being flushed. The control register shows that FIFO is empty and it can be written into, and the PWM is disabled. A software reset has the same results, however the state of the STOPEN, DOZEN, WAITEN, and DBGEN MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-12 Freescale Semiconductor Pulse-Width Modulator (PWM) bits in the control register are not affected. Software reset can be asserted even when the PWM is in disabled state. 32.4.1.1 Clocks The clock that feeds the prescaler can be selected from the following: • High Frequency Clock (ipg_clk_highfreq) pat_ref or ckih This is a high frequency clock provided by the Clock Control Module (CCM). This clock is supposed to be on in the low power mode when the ipg_clk is turned off. Thus the PWM can be run on this clock in the low power mode. The CRM is expected to provide this clock after synchronizing it to ahb_clk in the normal functional mode and switch to the unsynchronized version in the low power mode. • Low Reference Clock (ipg_clk_32k) ckil This is the 32 KHz low reference clock which is provided by the CCM. This clock is supposed to be on in the low power mode when ipg_clk is turned off. Thus PWM can be run on this clock in the low power mode. The CRM is expected to provide this clock after synchronizing it to ahb_clk in the normal functional mode and switch to the unsynchronized version in the low power mode. • Global Functional Clock (ipg_clk) This clock is supposed to be on in normal operations. In low power modes it can be switched off. The clock input source is determined by the CLKSRC field of the PWM control register. The CLKSRC value should only be changed when the PWM is disabled. The PWM input clock can be divided from 1 to 4096 by using a prescaler by appropriately setting the PRESCALER field in the control register. A change in the value of the PRESCALER field is immediately reflected on its output clock frequency. 32.4.1.2 FIFO Digital sample values can be loaded into the pulse-width modulator as 16-bit words. The Endianness can be changed using the BCTR and HCTR bits of the control register. A 4-word (16-bit) FIFO minimizes interrupt overhead. A maskable interrupt is generated when the number of data words fall below the water level set by the FWM field in the control register. A write in the sample register results in the value being stored into the FIFO if it is not full. A write when the FIFO is full sets FWE (FIFO write error) bit in the status register and the FIFO contents remain unchanged. The FIFO can be written into when the PWM is disabled. The FIFOAV field shows how many data words are currently contained in the FIFO and if it can be written into. A read on the sample register yields the current FIFO value being used or will be used by the PWM for generation on the output signal. Therefore a write and a subsequent read on the sample register may result in different values being obtained. 32.4.1.3 Rollover and Compare Event The counter is reset to 0x0000 after its value equals the PERIOD + 1 and resumes counting thereafter. This event is referred to as a rollover. When PERIOD = 0x0000, the counter is reset after count reaches 0x0001. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-13 Pulse-Width Modulator (PWM) Therefore PERIOD = 0xFFFF or 0xFFFE results in the counter value being reset after count till 0xFFFF. During a rollover event the output is either set (default), reset or has no effect according to the programming of the POUTC field in the control register. This event can also generate an interrupt if the respective interrupt enable bit is set in the control register. When the counter value reaches the sample value the output of the PWM is reset (default), set or has no effect according to the programming of the POUTC field of control register. This event is referred to as a compare event. This event can also generate an interrupt if the respective interrupt enable bit is set in the control register. If the rollover event sets the PWM output signal the compare event will reset it and vice versa for a particular programming configuration of POUTC field. 32.4.1.4 Low Power Mode Behavior In low power modes if the clock from the selected clock source is available, the PWM counter continues to run and an output is produced depending on whether the control bit for that mode is set. In the absence of the clock itself or if the corresponding low power bit in the control register is 0, the counter is reset and resumes counting when it exits the low power mode. 32.4.1.5 Debug Mode Behavior In debug mode, PWM has the option of continuing to run or be halted. If the DBGEN bit is not set in the PWMCR, the PWM is halted. If the DBGEN bit is set, then the PWM will continue to run in the debug mode. 32.5 PWM Clocking Figure 32-10 shows the relationship of clocks used by the PWM. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-14 Freescale Semiconductor Pulse-Width Modulator (PWM) ipg_clk_highfreq ipg_clk_32k AIPI PWM Clock MUX and Counter CCM LPG Low Power Gate ips_module_en Clock Gating ipg_clk Cell ipg_clk_s Registers crm_module_en Clock Gating Cell ipg_clk ipg_enable_clk Figure 32-10. PWM Clocking 32.5.1 PWM Clock Inputs Figure 32-11 shows the clock that feeds the prescaler (sys_clk). pclk is used for FIFO read flag update ipg_clk_s is used for write into sample register and update its associated flags pwm_fifo pclk is used to run the PWM main counter and generate output pwm_outputgen ipg_clk ipg_clk_32k ipg_clk_highfreq Clock Selection and Division Unit pwm_crm pclk pclk is used in interrupt generation ipg_clk_s ipg_clk_s is used for register R/W pwm_reg Figure 32-11. Clock Distribution Inside PWM MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 32-15 Pulse-Width Modulator (PWM) The clock that feeds the prescaler shown in Figure 32-11 can be selected from the following clock inputs: • High frequency Clock (ipg_clk_highfreq) pat_ref or ckih • Low Reference Clock (ipg_clk_32k) ckil • Global Functional Clock (ipg_clk) The selected clock sys_clk is prescaled with a 12-bit prescaler value. The sys_clk is gated with an enable signal that is generated from a prescaler counter and PWM enable to get the pclk. The main PWM counter runs on pclk. pclk is used to generate the output signal of PWM and also the interrupts. ipg_clk_s is the clock used for register read/write. The only hand instantiated clock gating inside the module is done inside pwm_crm submodule for division of sys_clk to generate the pclk. Figure 32-12 shows an overview of the clock selection and division unit. CLKSRC Clock off ipg_clk ipg_clk_32k ipf_clk_highfreq sys_clk pclk pclk enable 12-bit prescaler Figure 32-12. Clock Selection and Division Unit 32.5.2 ipg_enable_clk Generation Whenever the module is enabled and ipg_clk is selected, this signal is asserted. Figure 32-13 shows the ipg_enable_clk generation logic. clksrc[0] clksrc[1] pwm_enable_bit ipg_enable_clk Figure 32-13. ipg_enable_clk Generation Logic MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 32-16 Freescale Semiconductor Chapter 33 Real Time Clock (RTC) 33.1 Introduction See Figure 33-1 for a block diagram of the functional organization of the Real Time Clock (RTC) block. The block consists of the following blocks: • Prescaler • Time-of-day (TOD) clock counter • Alarm • Sampling timer • Minute stopwatch • Associated control and bus interface hardware 32.768K OR 32K OR 38.4K CLK2HZ CLK32HZ PRESCALER SECOND TOD CLOCK MINUTE HOUR DAY SAMPLING TIMER 1 PPS 1 PPM 1 PPH 1 PPD RTC_INT INTERRUPT CONTROL CLOCK CONTROL INTERRUPT ENABLE INTERRUPT STATUS HOUR LATCH ALARM COMPARATOR HOUR-MINUTE LATCH SECOND LATCH IP BUS IPBUS DECODE MINUTE STOPWATCH Figure 33-1. Real Time Clock Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-1 Real Time Clock (RTC) 33.2 Overview This section discusses how to operate and program the real-time clock (RTC) module that maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the features described in Section 33.2.1, “Features.” 33.2.1 Features The RTC module includes the following features: • Full clock: days, hours, minutes, seconds • Minute countdown timer with interrupt • Programmable daily alarm with interrupt • Sampling timer with interrupt • Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts • Operation at 32.768 kHz or 32 kHz, or 38.4 kHz (determined by reference clock crystal) 33.2.2 Modes of Operation The prescaler converts the incoming crystal reference clock to a 1 Hz signal that is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on minute boundaries. • Prescaler and Counter The prescaler divides the reference clock down to 1 Hz. The reference frequencies of 32.768 kHz, 38.4 kHz and 32 kHz are supported. The counter portion of the RTC module consists of four groups of counters that are physically located in three registers: — The 6-bit seconds counter is located in the SECONDS register — The 6-bit minutes counter and the 5-bit hours counter are located in the HOURMIN register — The 16-bit day counter is located in the DAYR register • Alarm There are three alarm registers that mirror the three counter registers. An alarm is set by accessing the real-time clock alarm registers (ALRM_HM, ALRM_SEC, and DAYALARM) and loading the exact time that the alarm should generate an interrupt. When the TOD clock value and the alarm value coincide, an interrupt occurs. • Sampling Timer The sampling timer is designed to support application software. The sampling timer generates a periodic interrupt with the frequency specified by the SAMx bits of the RTCIENR register. This timer can be used for digitizer sampling, keyboard debouncing, or communication polling. The sampling timer operates only if the real-time clock is enabled. See Table 33-15 for the list of the interrupt frequencies of the sampling timer for the possible reference clocks. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-2 Freescale Semiconductor Real Time Clock (RTC) • Minute Stopwatch The minute stopwatch performs a countdown with a one minute resolution. It can be used to generate an interrupt on a minute boundary. 33.3 External Signal Description The RTC has no external signals. 33.3.1 Overview There are no signals connected off the chip. See Table 33-1 for a complete list of RTC block level signal names. 33.4 Memory Map and Register Definition The RTC module has ten 32-bit registers. Section 33.4.3, “Register Descriptions” provides the detailed descriptions for all of the RTC registers. 33.4.1 Memory Map Table 33-2. RTC Register Memory Map Address Register RTC Hours and Minutes Counter Register (HOURMIN) RTC Seconds Counter Register (SECONDS) RTC Hours and Minutes Alarm Register (ALRM_HM) RTC Seconds Alarm Register (ALRM_SEC) RTC Control Register (RCCTL) RTC Interrupt Status Register (RTCISR) RTC Interrupt Enable Register (RTCIENR) Stopwatch Minutes Register (STPWCH) RTC Days Counter Register (DAYR) RTC Days Alarm Register (DAYALARM) Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Values 0x0000_– – – – 0x0000_00 – – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_– – – – 0x0000_0000 Section/Page 33.4.3.1/33-6 33.4.3.2/33-7 33.4.3.3/33-7 33.4.3.4/33-8 33.4.3.5/33-9 33.4.3.6/33-10 33.4.3.7/33-13 33.4.3.8/33-14 33.4.3.9/33-15 33.4.3.10/33-16 Table 33-2 shows the RTC memory map. 0x1000_7000 (HOURMIN) 0x1000_7004 (SECONDS) 0x1000_7008 (ALRM_HM) 0x1000_700C (ALRM_SEC) 0x1000_7010 (RTCCTL) 0x1000_7014 (RTCISR) 0x1000_7018 (RTCIENR) 0x1000_701C (STPWCH) 0x1000_7020 (DAYR) 0x1000_7024 (DAYALARM) 33.4.2 Register Summary Figure 33-2 shows the key to the register fields and Table 33-3 shows the register figure conventions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-3 Real Time Clock (RTC) Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 33-2. Key to Register Fields Table 33-3. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 33-4 shows the RTC register summary. Table 33-4. RTC Register Summary Name R 0x1000_7000 (HOURMIN) W R W R 0x1000_7004 (SECONDS) W R W 0 0 0 0 0 0 0 0 0 0 SECONDS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOUR 0 0 MINUTES 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-4 Freescale Semiconductor Real Time Clock (RTC) Table 33-4. RTC Register Summary (continued) Name R 0x1000_7008 (ALRM_HM) W R W R 0x1000_700C (ALRM_SEC) W R W R 0x1000_7010 (RTCCTL) W R W R 0x1000_7014 (RTCISR) W SA W M7 R 0x1000_7018 (RTCIENR) W SA W M7 R 0x1000_701C (STPWCH) W R W R 0x1000_7020 (DAYR) W R DAYS W R 0x1000_7024 (DAYALARM) W R DAYSAL W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT 0 R SA M6 0 SA M5 0 SA M4 0 SA M3 0 SA M2 0 SA M1 0 SA 2HZ M0 0 0 0 HR 1HZ DAY 0 0 0 0 AL M 0 MIN SW 0 0 0 R SA M6 0 SA M5 0 SA M4 0 SA M3 0 SA M2 0 SA M1 0 SA 2HZ M0 0 0 0 HR 1HZ DAY 0 0 0 0 AL M 0 MIN SW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN XTL 0 0 0 GE N 0 SW R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECONDS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOUR 0 0 MINUTES 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-5 Real Time Clock (RTC) 33.4.3 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bits and field functions follow the register diagrams in their bit order. 33.4.3.1 RTC Hours and Minutes Counter Register (HOURMIN) The real-time clock hours and minutes counter register (HOURMIN) is used to program the hours and minutes for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset since the real-time clock is always enabled at reset. See Figure 33-3 for an illustration of valid bits in the Hours and Minutes Counter Register and Table 33-5 for descriptions of the bit fields. 0x1000_7000 (HOURMIN) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 HOUR 0 0 MINUTES 0 0 0 — — — — — 0 0 — — — — — — Figure 33-3. RTC Hours and Minutes Counter Register Table 33-5. RTC Hours and Minutes Counter Register Field Descriptions Field 31–13 12–8 HOUR Reserved Hour setting indicates the current hour that can be set to any value between 0 and 23. 00000 current hour is 0. 00001 current hour is 1. ...... ...... 10111 current hour is 23: Indicates the current hour that can be set to any value between 0 and 23. Reserved Minutes setting indicates the current minutes that can be set to any value between 0 and 59. 000000 current minute is 0. 000001 current minute is 1. ...... ...... 111011 current minute is 59. Description 7–5 5–0 MINUTES MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-6 Freescale Semiconductor Real Time Clock (RTC) The HOURS and MINUTES are not affected by any of the hardware or software reset, their RESET values are “Not unknown” but we just do not know the exact values to put into the table. 33.4.3.2 RTC Seconds Counter Register (SECONDS) The real-time clock seconds register (SECONDS) is used to program the seconds for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset since the real-time clock is always enabled at reset. See Figure 33-4 for an illustration of valid bits in the RTC Seconds Counter Register and Table 33-6 for descriptions of the bit fields. 0x1000_7004 (SECONDS) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 SECONDS 0 0 0 0 0 0 0 0 0 0 — — — — — — Figure 33-4. RTC Seconds Counter Register Table 33-6. RTC Seconds Counter Register Field Descriptions Field 31–6 5–0 SECONDS Reserved Seconds setting indicates the current seconds that can be set to any value between 0 and 59. 000000 current second is 0. 000001 current second is 1. ...... ...... 111011 current second is 59. Description The SECONDS are not affected by any of the hardware or software reset, their RESET values are “Not unknown,” but we just do not know the exact values to put into the table. 33.4.3.3 RTC Hours and Minutes Alarm Register (ALRM_HM) The real-time clock hours and minutes alarm (ALRM_HM) register is used to configure the hours and minutes setting for the alarm. The alarm settings can be read or written at any time. See Figure 33-5 for an illustration of valid bits in the RTC Hours and Minutes Alarm Register and Table 33-7 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-7 Real Time Clock (RTC) 0x1000_7008 (ALRM_HM) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 HOUR 0 0 MINUTES 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-5. RTC Hours and Minutes Alarm Register Table 33-7. RTC Hours and Minutes Alarm Register Field Descriptions Field 31–13 12–8 HOURS Reserved Hour setting of the alarm hours that can be set to any value between 0 and 23. 00000 current hour is 0. 00001 current hour is 1. ...... ...... 10111 current hour is 23. Reserved Minutes setting of the alarm minutes that can be set to any value between 0 and 59. 000000 current minute is 0. 000001 current minute is 1. ...... ...... 111011 current minute is 59. Description 7–6 5–0 MINUTES 33.4.3.4 RTC Seconds Alarm Register (ALRM_SEC) The real-time clock seconds alarm (ALRM_SEC) register is used to configure the seconds setting for the alarm. The alarm settings can be read or written at any time. See Figure 33-6 for an illustration of valid bits in the RTC Seconds Alarm Register and Table 33-8 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-8 Freescale Semiconductor Real Time Clock (RTC) 0x1000_700C (ALRM_SEC) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 SECONDS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-6. RTC Seconds Alarm Register Table 33-8. RTC Seconds Alarm Register Field Descriptions Field 31–6 5–0 SECONDS Reserved Seconds setting of the alarm seconds, can be set to any value between 0 and 59. 000000 current second is 0. 000001 current second is 1. ...... ...... 111011 current second is 59. Description 33.4.3.5 RTC Control Register (RTCCTL) The real-time clock control (RTCCTL) register is used to enable the real-time clock module and specify the reference frequency information for the prescaler. See Figure 33-7 for an illustration of valid bits in the RTC Control Register and Table 33-9 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-9 Real Time Clock (RTC) 0x1000_7010 (RTCCTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 EN XTL 0 0 0 0 0 GEN SWR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-7. RTC Control Register Table 33-9. RTC Control Register Field Descriptions Field 31–8 7 EN 6–5 XTL Reserved Enables/Disables the real-time clock. The software reset bit (SWR) has no effect on this bit. 0 Disables the real-time clock 1 Enables the real-time clock Crystal Selection. Selects the proper input crystal frequency. It is important to set these bits correctly or the real-time clock will be inaccurate. 00 Input crystal frequency is 32.768 kHz. 01 Input crystal frequency is 32 kHz. 10 Input crystal frequency is 38.4 kHz. 11 Input crystal frequency is 32.768 kHz. Reserved GEN — IPG_CLK gating enable. Decides whether to enable or disable the ipg_clk gating. Upon reset the ipg_clk gating is enabled. 0 Enables ipg_clk gating 1 Disables ipg_clk gating Software reset. Resets the module to its default state. However, a software reset will have no effect on the RTC enable (EN) bit. 0 No effect 1 Reset the module to its default state Description 4–2 1 GEN 0 SWR 33.4.3.6 RTC Interrupt Status Register (RTCISR) The real-time clock interrupt status register (RTCISR) indicates the status of the various real-time clock interrupts. When an event of the types included in this register occurs, then the bit will be set in this register regardless of its corresponding interrupt enable bit.These bits are cleared by writing a value of 1, which also clears the interrupt. Interrupts may occur while the system clock is idle or in sleep mode. Every interrupt status bit is independent of each other. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-10 Freescale Semiconductor Real Time Clock (RTC) See Figure 33-8 for an illustration of valid bits in the RTC Interrupt Status Register and Table 33-10 for descriptions of the bit fields. 0x1000_7014 (RTCISR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 2HZ W Reset 0 0 0 0 0 0 0 0 0 0 HR 0 0 1HZ 0 DAY 0 ALM 0 MIN 0 SW 0 Figure 33-8. RTC Interrupt Status Register Table 33-10. RTC Interrupt Status Register Field Descriptions Field 31–16 15 SAM7 Reserved Sampling Timer Interrupt Flag at SAM7 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 512, 500, or 600 Hz depending on different input clock. 0 No SAM7 interrupt has occurred. 1 A SAM7 interrupt has occurred. Sampling Timer Interrupt Flag at SAM6 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 256, 250, or 300 Hz depending on different input clock. 0 No SAM6 interrupt has occurred. 1 A SAM6 interrupt has occurred. Sampling Timer Interrupt Flag at SAM5 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 128, 125, or 150 Hz depending on different input clock. 0 No SAM5 interrupt has occurred. 1 A SAM5 interrupt has occurred. Sampling Timer Interrupt Flag at SAM4 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 64, 62.5, or 75 Hz depending on different input clock. 0 No SAM4 interrupt has occurred. 1 A SAM4 interrupt has occurred. Sampling Timer Interrupt Flag at SAM3 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 32, 31.25, or 37.5 Hz depending on different input clock. 0 No SAM3 interrupt has occurred. 1 A SAM3 interrupt has occurred. Description 14 SAM6 13 SAM5 12 SAM4 11 SAM3 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-11 Real Time Clock (RTC) Table 33-10. RTC Interrupt Status Register Field Descriptions (continued) Field 10 SAM2 Description Sampling Timer Interrupt Flag at SAM2 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 16, 15.625, or 18.75 Hz depending on different input clock. 0 No SAM2 interrupt has occurred. 1 A SAM2 interrupt has occurred. Sampling Timer Interrupt Flag at SAM1 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 8, 7.8125, or 9.375 Hz depending on different input clock. 0 No SAM1 interrupt has occurred. 1 A SAM1 interrupt has occurred. Sampling Timer Interrupt Flag at SAM0 Frequency. Indicates that an interrupt has occurred. If enabled, this bit is periodically set at a rate of 4, 3.90625, or 4.6875 Hz depending on different input clock. 0 No SAM0 interrupt has occurred. 1 A SAM0 interrupt has occurred. 2 Hz Flag. Indicates that an interrupt has occurred. If enabled, this bit is set at every 2 Hz frequency. 0 No 2 Hz interrupt has occurred. 1 A 2 Hz interrupt has occurred. Reserved Hour Flag. Indicates that the hour counter has increment. If enabled, this bit is set on every increment of the hour counter in the time-of-day clock. 0 No 1-hour interrupt has occurred. 1 A 1-hour interrupt has occurred. 1 Hz Flag. Indicates that the second counter has increment. If enabled, this bit is set on every increment of the second counter of the time-of-day clock. 0 No 1 Hz interrupt has occurred. 1 A 1 Hz interrupt has occurred. Day Flag. indicates that the day counter has increment. If enabled, this bit is set on every increment of the day counter of the time-of-day clock. 0 No 24-hour rollover interrupt has occurred. 1 A 24-hour rollover interrupt has occurred. Alarm Flag. Indicates that the real-time clock matches the value in the alarm registers. The alarm will reoccur every 65536 days. For a single alarm, clear the interrupt enable for this bit in the interrupt service routine. 0 No alarm interrupt has occurred. 1 An alarm interrupt has occurred. Minute Flag. Indicates that the minute counter has increment. If enabled, this bit is set on every increment of the minute counter in the time-of-day clock. 0 No 1-minute interrupt has occurred. 1 A 1-minute interrupt has occurred. Stopwatch Flag. Indicates that the stopwatch countdown timed out. 0 The stopwatch did not time out. 1 The stopwatch timed out. 9 SAM1 8 SAM0 7 2 Hz 6 5 HR 4 1 Hz 3 DAY 2 ALM 1 MIN 0 SW MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-12 Freescale Semiconductor Real Time Clock (RTC) 33.4.3.7 RTC Interrupt Enable Register (RTCIENR) The real-time clock interrupt enable register (RTCIENR) is used to enable/disable the various real-time clock interrupts. Masking an interrupt bit has no effect on its corresponding status bit. Every interrupt enable bit is independent of each other. See Figure 33-9 for an illustration of valid bits in the RTC Interrupt Enable Register and Table 33-11 for descriptions of the bit fields. 0x1000_7018 (RTCIENR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 2HZ W Reset 0 0 0 0 0 0 0 0 0 0 HR 0 0 1HZ 0 DAY 0 ALM 0 MIN 0 SW 0 Figure 33-9. RTC Interrupt Enable Register Table 33-11. RTC Interrupt Enable Register Field Descriptions Field 31–16 15 SAM7 Reserved Sampling Timer Interrupt Flag at SAM7 Interrupt. Enables/Disables the real-time sampling timer interrupt 7. 0 The SAM7 interrupt is disabled. 1 The SAM7 interrupt is enabled. Sampling Timer interrupt Flag at SAM 6 Interrupt. Enables/Disables the real-time sampling timer interrupt 6. 0 The SAM6 interrupt is disabled. 1 The SAM6 interrupt is enabled. Sampling Timer Interrupt Flag at SAM5 Interrupt. Enables/Disables the real-time sampling timer interrupt 5. 0 The SAM5 interrupt is disabled. 1 The SAM5 interrupt is enabled. Sampling Timer Interrupt Flag at SAM4 Interrupt. Enables/Disables the real-time sampling timer interrupt 4. 0 The SAM4 interrupt is disabled. 1 The SAM4 interrupt is enabled. Sampling Timer Interrupt Flag at SAM3 Interrupt. Enables/Disables the real-time sampling timer interrupt 3. 0 The SAM3 interrupt is disabled. 1 The SAM3 interrupt is enabled. Description 14 SAM6 13 SAM5 12 SAM4 11 SAM3 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-13 Real Time Clock (RTC) Table 33-11. RTC Interrupt Enable Register Field Descriptions (continued) Field 10 SAM2 Description Sampling Timer Interrupt Flag at SAM2 Interrupt. Enables/Disables the real-time sampling timer interrupt 2. 0 The SAM2 interrupt is disabled. 1 The SAM2 interrupt is enabled. Sampling Timer Interrupt Flag at SAM1 Interrupt. Enables/Disables the real-time sampling timer interrupt 1. 0 The SAM1 interrupt is disabled. 1 The SAM1 interrupt is enabled. Sampling Timer Interrupt Flag at SAM0 Interrupt. Enables/Disables the real-time sampling timer interrupt 0. 0 The SAM0 interrupt is disabled. 1 The SAM0 interrupt is enabled. 2 Hz Interrupt Enable. Enables/Disables an interrupt at a 2 Hz rate. 0 The 2-Hz interrupt is disabled. 1 The 2-Hz interrupt is enabled. Reserved Hour Interrupt Enable. Enables/Disables an interrupt whenever the hour counter of the real-time clock increments. 0 The 1-hour interrupt id disabled. 1 The 1-hour interrupt is enabled. 1 Hz Interrupt Enable. Enables/Disables an interrupt whenever the second counter of the real-time clock increments. 0 The 1-Hz interrupt is disabled. 1 The 1-Hz interrupt is enabled. Day Interrupt Enable. Enables/Disables an interrupt whenever the hours counter rolls over from 23 to 0. (midnight rollover) 0 The 24-hour interrupt is disabled. 1 The 24-hour interrupt is enabled. Alarm Interrupt Enable. Enables/Disables the alarm interrupt. 0 The alarm interrupt is disabled. 1 The alarm interrupt is enabled. Minute Interrupt Enable. Enables/Disables an interrupt whenever the minute counter of the real-time clock increments. 0 The 1-minute interrupt is disabled. 1 The 1-minute interrupt is enabled. Stopwatch Interrupt Enable. Enables/Disables the stopwatch interrupt. Note: The stopwatch counts down and remains at decimal -1 until it is reprogrammed. If this bit is enabled with -1 (decimal) in the STPWCH register, an interrupt will be posted on the next minute tick. 0 Stopwatch interrupt is disabled. 1 Stopwatch interrupt is enabled. 9 SAM1 8 SAM0 7 2 Hz 6 5 HR 4 1HZ 3 DAY 2 ALM 1 MIN 0 SW 33.4.3.8 RTC Stopwatch Minutes Register (STPWCH) The stopwatch minutes (STPWCH) register contains the current stopwatch countdown value. When the minute counter of the TOD clock increments, the value in this register decrements. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-14 Freescale Semiconductor Real Time Clock (RTC) See Figure 33-10 for an illustration of valid bits in the Stopwatch Minutes Counter Register and Table 33-12 for descriptions of the bit fields. 0x1000_701C (STPWCH) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-10. RTC Stopwatch Minutes Register Table 33-12. RTC Stopwatch Minutes Register Field Descriptions Field 31–6 5-0 CNT Reserved Stopwatch Count. Contains the stopwatch countdown value. Note: The stopwatch counter is decremented by the minute (MIN) tick output from the real-time clock, so the average tolerance of the count is 0.5 minutes. For better accuracy, enable the stopwatch by polling the MIN bit of the RTCISR register or by polling the minute interrupt service routine. 000000 stopwatch countdown value is 0. 000001 stopwatch countdown value is 1. ...... ...... 111111 stopwatch countdown value is 63. Description 33.4.3.9 RTC Days Counter Register (DAYR) The real-time clock days counter register (DAYR) is used to program the day for the TOD clock. When the HOUR field of the HOURMIN register rolls over from 23 to 00, the day counter increments. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset since the real-time clock is always enabled at reset. See Figure 33-11 for an illustration of valid bits in the Counter Register and Table 33-13 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-15 Real Time Clock (RTC) 0x1000_7020 (DAYR) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DAYS W Reset — — — — — — — — — — — — — — — — Figure 33-11. RTC Days Counter Register Table 33-13. RTC Days Counter Register Field Descriptions Field 31–16 15–0 DAYS Reserved Day Setting. Indicates the current day count, can be set to any values between 0 and 65535. 0x0000 current day count is 0. 0x0001 current day count is 1. ...... ...... 0xFFFF current day count is 65535. Description The DAYS are not affected by any of the hardware or software reset, their reset values are “Not unknown,” but we just do not know the exact values to put into the table. 33.4.3.10 RTC Day Alarm Register (DAYALARM) The real-time clock day alarm (DAYALARM) register is used to configure the day for the alarm. The alarm settings can be read or written at any time. See Figure 33-12 for an illustration of valid bits in the RTC Day Alarm Register and Table 33-14 for descriptions of the bit fields. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-16 Freescale Semiconductor Real Time Clock (RTC) 0x1000_7024 (DAYALARM) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read/write 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DAYSAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-12. RTC Day Alarm Register Table 33-14. RTC Day Alarm Register Field Descriptions Field 31–16 15–0 DAYSAL Reserved Day Setting of the Alarm. Indicates the current day setting of the alarm. It can be set to any value between 0 and 65535. 0x0000 current day setting of alarm is 0. 0x0001 current day setting of alarm is 1. ...... ...... 0xFFFF current day setting of alarm is 65535. Description 33.5 Functional Description The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on minute boundaries. 33.5.1 Prescaler and Counter The prescaler divides the reference clock down to 1 Hz. The reference frequencies of 32.768 kHz, 38.4 kHz, and 32 kHz are supported. The prescaler stages are tapped to support the sampling timer. The counter portion of the RTC module consists of four groups of counters that are physically located in three registers: • The 6-bit seconds counter is located in the SECONDS register. • The 6-bit minutes counter and the 5-bit hours counter are located in the HOURMIN register. • The 16-bit day counter is located in the DAYR register. These counters cover a 24-hour clock over 65536 days. All three registers can be read or written at any time. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-17 Real Time Clock (RTC) Interrupts signal when each of the four counters increments, and can be used to indicate when a counter rolls over. For example, each tick of the seconds counter causes the 1 Hz interrupt flag to be set. When the seconds counter rolls from 59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute counter with the HR signal, and the hour counter with the DAY signal. 33.5.2 Alarm There are three alarm registers that mirror the three counter registers: • ALRM_HM • ALRM_SEC • DAYALARM An alarm is set by accessing the three real-time clock alarm registers and loading the exact time that the alarm should generate an interrupt. When the TOD clock value and the alarm value coincide, if the ALM bit in the real-time clock interrupt enable register (RTCIENR) is set, an interrupt occurs. NOTE If the alarm is not disabled, it will reoccur every 65536 days. If a single alarm is desired, the alarm function must be disabled through the RTC Interrupt Enable Register (RTCIENR). 33.5.3 Sampling Timer The sampling timer is designed to support application software. The sampling timer generates a periodic interrupt with the frequency specified by the SAMx bits of the RTCIENR register. This timer can be used for digitizer sampling, keyboard debouncing, or communication polling. The sampling timer operates only if the real-time clock is enabled. See Table 33-15 for the list of the interrupt frequencies of the sampling timer for the possible reference clocks. Multiple SAMx bits may be set in the RTC Interrupt Enable Register (RTCIENR). The corresponding bits in the RTC Interrupt Status Register (RTCISR) will be set at the noted frequencies. Table 33-15. Sampling Timer Frequencies Sampling Frequency SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 32.768 kHz Reference Clock 512 Hz 256 Hz 128 Hz 64 Hz 32Hz 16 Hz 8 Hz 4 Hz 32 kHz Reference Clock 500 Hz 250 Hz 125 Hz 62.5 Hz 31.25 Hz 15.625 Hz 7.8125 Hz 3.90625 Hz 38.4 kHz Reference Clock 600 Hz 300 Hz 150 Hz 75 Hz 37.5 Hz 18.75 Hz 9.375 Hz 4.6875 Hz MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-18 Freescale Semiconductor Real Time Clock (RTC) 33.5.4 Minute Stopwatch The minute stopwatch performs a countdown with a one minute resolution. It can be used to generate an interrupt on a minute boundary. For example, to turn off the LCD controller after five minutes of inactivity, program a value of 0x04 into the Stopwatch Count (CNT) field of the Stopwatch Minutes (STPWCH) register. At each minute, the value in the stopwatch is decremented. When the stopwatch value reaches –1, the interrupt occurs. The value of the register does not change until it is reprogrammed. NOTE The actual delay includes the seconds from setting the stopwatch to the next minute tick. 33.6 33.6.1 Initialization/Application Information Flowchart of RTC Operation See Figure 33-13 for the illustration of the flowchart of a typical RTC operation. Refer to Example 33-1 for the code example of ARM instruction for configuring RTC. Configure RTC Control Register Config RTC Days Counter Register Config RTC Seconds Counter Reg Config RTC Hr/Min Counter Register Config RTC Alarm Registers Config RTC Interrupt Enable Reg Check RTC Interrupt Status Register Figure 33-13. Flowchart of RTC Operation MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 33-19 Real Time Clock (RTC) 33.6.2 Code Example of ARM Instruction Example 33-1. Code Example of ARM Instruction LDR LDR ORR STR r1,=RTC_BASE_ADDR r2,[r1,#0x10] r2,r2,#0x21 r2,[r1,#0x10] ; Software reset and 32k crystal LDR STR LDR STR LDR STR LDR STR LDR STR LDR STR LDR ORR STR ALARM_STATUS_3 LDR TST BNE r3,=0x0000 r3,[r1,#0x20] r3,=0x00038 r3,[r1,#0x04] r3,=0x173B r3,[r1] r3,=0x0001 r3,[r1,#0x24] r3,=0x0000 r3,[r1,#0x08] r3,=0x01 r3,[r1,#0x0C] r2,[r1,#0x18] r2,r2,#0x4 r2,[r1,#0x18] ;DAY ;SECOND ;HR, MIN ;Alarm Day ;Alarm hour, minute ;Alarm seconds ;set ALARM interrupt r2,[r1,#0x18] r2,#0x04 ALARM_STATUS_3 ;check ALARM STATUS FLAG MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 33-20 Freescale Semiconductor Chapter 34 Watchdog Timer (WDOG) The Watchdog (WDOG) timer module protects against system failures by providing a method of escaping from unexpected events or programming errors. Figure 34-1 shows the WDOG block diagram. Watchdog Reset Status Register (WRSR) Watchdog Service Register (WSR) Watchdog Control Register (WCR) WDBG WDZST Low Power WAIT mode WDW Low Power STOP/DOZE mode WDZST WDBG DEBUG Logic 8-bit counter Logic (time-out) Logic WDE WDW ~32KHz Prescaler (div by 4) ~8KHz Prescaler (div by 4096) ~2Hz Figure 34-1. WDOG Block Diagram 34.1 Overview Once the WDOG module is activated, it must be serviced by the software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the WDOG Timer module either asserts the WDOG signal or a system reset signal, wdog_rst, depending on the software configuration. The WDOG Timer module also generates a system reset via a software write to the Watchdog Control Register (WCR). The WDOG signal is asserted via a software write to the WCR, a detection of a clock monitor event, or upon a watchdog time-out. A state machine of the counter operation is shown in Figure 34-6, which demonstrates the time-out operation. The WDOG module cannot be deactivated again after activation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 34-1 Watchdog Timer (WDOG) The input clocks to the WDOG module (ipg_clk_32k, ipg_clk, and ipg_clk_s) must be synchronized with each other. NOTE ipg_clk_32k is the synchronized version of the input ~32k clock (CKIL) on the IP global functional clock. Because the synchronized version is not available (the IP global functional clock is off) in low-power mode, it will receive the raw CKIL (ipg_clk_32k) clock from the CRM. These synchronizers will be bypassed while going into low power modes in CRM. The WDOG module can continue or suspend the timer operation in the low power modes (WAIT and STOP). 34.1.1 Features The WDOG features are as follows: • Time-out periods from 0.5 seconds up to 128 seconds • Time resolution of 0.5 seconds • Configurable counters that can be programed to run or stop during low-power modes • Configurable counters that can be programed to run or stop during DEBUG mode 34.2 External Signal Description Table 34-2. Signal Properties Name IPP_WDOG IPP_WDOG_OE Port — — Function Asserted by software timeout event WDOG output enable at pin Reset State 1 0 Pull-Up — — The WDOG module port signals going to pins are listed in Table 34-2. 34.2.1 34.2.1.1 Detailed External Signal Descriptions IPP_WDOG, IPP_WDOG_OE The IPP_WDOG signal can be provided externally to the IC. It is asserted by a software request (setting the WCR bits) or a clock monitor event. The IPP_WDOG_OE signal is the output enable for the pin. 34.2.2 Internal Port Signals The WDOG internal port signals are listed in Table 34-3. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 34-2 Freescale Semiconductor Watchdog Timer (WDOG) Table 34-3. WDOG Module Port List Port Name ipg_enable_clk ipg_clk ipg_clk_s ipg_clk_32k Direction Description Output (O) IP global clock gating signal. It is available to the Clock Controller to gate off the clock to the WDOG module for power saving. Input (I) I I IP Global functional clock. All functionality inside the WDOG module is synchronized to this clock. IP slave bus clock. This clock is synchronized to ipg_clk and is only used for register read/write operations. Low frequency (32.768 kHz) clock that continues to run in low-power mode. It is assumed that the Clock Controller will provide this clock signal synchronized to ipg_clk in the normal mode, and switch to a non-synchronized signal in low-power mode when the ipg_clk is off. IP global hardware reset (active low) Power-on-reset signal (active low) IP global signal indicating that WDOG should enter debug mode operation IP global signal indicating that WDOG should enter low-power Sleep Mode operation IP global signal indicating that WDOG should enter low-power wait mode operation IP slave bus read data line IP slave bus transfer wait indicator IP slave bus transfer error indicator IP slave bus module enable signal. This signal indicates when a module bus transaction is occurring. IP slave bus read/write signal. Shows whether a bus transaction is read or write. IP slave bus address signal. Denotes the register being accessed during a bus transaction. IP slave bus write date line IP slave bus byte enable signal for bits 15 to 8 IP slave bus byte enable signal for bits 7 to 0 IP scan reset signal used to work in place of generated resets in scan mode (active low) IP scan signal for bypassing generated resets and making latches transparent in scan mode IP scan mode signal IP scan mode clock gating signal Watchdog Timer reset (active low) Indicates if the error response needs to be generated on access on unimplemented registers or not. Refer to Section 34.5.4, “Generation of Transfer Error on the IP Bus” for details. ipg_hard_async_reset ipg_por ipg_debug ipg_stop ipg_wait ips_rdata[15:0] ips_xfr_wait ips_xfr_err ips_module_en ips_rwb ips_addr[13:1] ips_wdata[15:0] ips_byte_15_8 ips_byte_7_0 ipt_reset ipt_se_async ipt_scan_mode ipt_se_gatedclk wdog_rst resp_sel I I I I I O O O I I I I I I I I I I O I MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 34-3 Watchdog Timer (WDOG) 34.3 Memory Map and Register Definitions The WDOG module has three, user-accessible, 16-bit registers used to configure, operate, and monitor the state of the Watchdog Timer. Section 34.4, “Register Descriptions” provides the detailed descriptions for all of the WDOG registers. 34.3.1 Watchdog Timer Memory Map Table 34-4. WDOG Memory Map Table 34-4 shows the WDOG memory map. Address 0x1000_2000 (WCR) 0x1000_2002 (WSR) 0x1000_2004 (WRSR) Register Watchdog Control Register Watchdog Status Register Watchdog Reset Status Register Access R/W R/W R Reset Value 0x0030 0x0010 0x00– – Section/Page 34.4.1/34-5 34.4.2/34-6 34.5.6/34-10 34.3.2 Register Summary Figure 34-2. Key to Register Fields Figure 34-2 shows the key to the register fields, and Table 34-5 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0 bit only bit only bit BIT to clear w1c bit BIT N/A Table 34-5. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — Resets to zero. Resets to one. Undefined at reset. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 34-4 Freescale Semiconductor Watchdog Timer (WDOG) Table 34-5. Register Figure Conventions (continued) Convention u Unaffected by reset. Description [signal_name] Reset value is determined by polarity of indicated signal. Table 34-6 shows the WDOG register summary. Table 34-6. WDOG Register Summary Name 0x1000_2000 R (WCR) W 0x1000_2002 R (WSR) W 0x1000_2004 R (WRSR) W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WT WSR 0 WOE WDA SRS WRE WDE WDB WDZS G T 0 0 JRST PWR EXT CMO TOUT SFTW N 34.4 34.4.1 Register Descriptions Watchdog Control Register (WCR) The Watchdog Control Register (WCR) is a 16-bit read/write register. It controls the WDOG operation. All bits except for bits[5:4] are cleared during reset. Bits[5:4] are set to 1 during reset. Figure 34-3 shows the register; Table 34-7 provides its field descriptions. 0x1000_2000 (WCR) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R WT W Reset 0 0 0 0 0 0 0 0 0 0 WDA SRS 1 WRE WDE 0 0 WDB WDZ G ST 0 0 0 0 1 Figure 34-3. Watchdog Control Register Table 34-7. WCR Register Descriptions Field 15–8 WT 7–6 5 WDA Description Watchdog Timeout Field. This 8-bit field contains the time-out value that is loaded into the Watchdog counter after the service routine has been performed. After reset, WT[7:0] must have a value written to it before enabling the Watchdog. Reserved WDOG Assertion. Controls the software assertion of the WDOG signal. 0 Assert WDOG output. 1 No effect on system. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 34-5 Watchdog Timer (WDOG) Table 34-7. WCR Register Descriptions (continued) Field 4 SRS Description Software Reset Signal. Controls the software assertion of the WDOG-generated reset signal. This bit automatically resets to “1” after it has been asserted to “0”. Note: This bit does not generate the software reset to the module. The ipg_clk must be on to write to this bit. 0 Assert system reset signal 1 No effect on the system wdog/wdog_rst Enable. Determines if the Watchdog generates a reset signal or a WDOG signal upon a Watchdog timeout. This is a write once-only bit. 0 Generate a reset signal 1 Generate a WDOG signal Watchdog Enable. Enables or disables the WDOG module. Software can only write “1” in this bit. It is not possible to reset this bit by a software write, once the bit is set. Note: This bit can be set/reset as per the IP writes in debug mode (exception). 0 Disable the Watchdog 1 Enable the Watchdog Watchdog DEBUG Enable. Determines the operation of the WDOG module during DEBUG mode. This bit is write once-only. 0 Continue WDOG timer operation 1 Suspend the watchdog timer Watchdog Low Power. Determines the operation of the WDOG module during low-power modes. This bit is write once-only. Note: The WDOG module can continue/suspend the timer operation in the low-power modes (WAIT and STOP). 0 Continue timer operation 1 Suspend the watchdog timer 3 WRE 2 WDE 1 WDBG 0 WDZST 34.4.2 Watchdog Service Register (WSR) When enabled, the WDOG requires that a service sequence be written to the Watchdog Service Register (WSR). Figure 34-4 shows the register; Table 34-8 provides its field descriptions. 0x1000_2002 (WSR) 15 14 13 12 11 10 9 8 7 6 5 4 Access: User Read/Write 3 2 1 0 R WSR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34-4. Watchdog Service Register (WSR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 34-6 Freescale Semiconductor Watchdog Timer (WDOG) Table 34-8. Watchdog Service Register Description Field 15–0 WSR Description Watchdog Service Register. This 15-bit field contains the Watchdog service sequence. Both writes must occur in the order listed prior to the time-out, but any number of instructions can be executed between the two writes. The service sequence must be performed as follows: Write 0x 5555 to the Watchdog Service Register (WSR) Write 0x AAAA to the Watchdog Service Register (WSR) 34.4.2.1 Watchdog Reset Status Register (WRSR) The WRSR is a read-only register that records the source of the output reset assertion. It is not cleared by a hard reset. It records the source of the output reset assertion. Therefore, only one bit in the WRSR will always be asserted high. The register will always indicate the source of the last reset. A reset can be generated by the following sources, as listed in priority from highest to lowest: • Power-on reset • External reset • Watchdog Time-out • Software reset Figure 34-5 shows the register; Table 34-8 provides its field descriptions. NOTE Do not write to this register. Attempting to write to the WRSR register generates a bus error. 0x1000_2004 (WRSR) 15 14 13 12 11 10 9 8 7 6 5 4 3 Access: User Read-only 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 PWR EXT 0 TOUT SFTW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34-5. Watchdog Reset Status Register (WRSR) Table 34-9. Watchdog Reset Status Register Field Descriptions Field 15–5 4 PWR 3 EXT 2 Reserved—These bits are read as 0 Power-On Reset. Indicates whether the reset was a result of a power-on reset. 0 Reset is not a result of a power-on reset 1 Reset is a result of a power-on reset External Reset. Indicates whether the reset was a result of an external reset. 0 Reset is not a result of an external reset 1 Reset is a result of an external reset Reserved—This bit reads 0 Description MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 34-7 Watchdog Timer (WDOG) Table 34-9. Watchdog Reset Status Register Field Descriptions (continued) Field 1 TOUT 0 SFTW Description Time-out. Indicates whether the reset was a result of WDOG time-out. 0 Reset is not the result of WDOG time-out 1 Reset is the result of a WDOG time-out Software Reset. Indicates whether the reset was a result of a software reset. 0 Reset is not a result of a software reset 1 Reset is a result of a software reset 34.5 Functional Description This section describes the timing information for the WDOG module. 34.5.1 Timing Specifications The WDOG provides time-out periods from 0.5 seconds up to 128 seconds with a time resolution of 0.5 seconds. It uses the ipg_clk_32k clock (32.768 kHz frequency clock) as an input to prescalers. The prescalers divide the clock by a fixed value of 16384 (divide by 4 and divide by 4096) to achieve a resolution of 0.5 seconds at a frequency of 2 Hz. The output of the prescaler circuitry is connected to the input of an 8-bit counter to obtain a range of 0.5 to 128 seconds. The user can determine the time-out period by writing a time-out value to the WDOG Time-out field (WT[7:0]) in the WDOG Control Register (WCR). 34.5.2 Watchdog During Reset A system reset resets all registers (except the WRSR) to their initial default values, and places the counter in the idle state until the WDOG is enabled. The Watchdog Reset Status Register (WRSR) contains the source of the reset event and is not reset by a system reset. 34.5.3 Watchdog After Reset The following subsections define the WDOG Timer state after reset. 34.5.3.1 Initial Load The Watchdog Control Register (WCR) field WT[7:0] must have a time-out value written to it before the Watchdog can be enabled. The WDOG is enabled by setting the Watchdog Enable (WDE) bit in the WCR. The time-out value is loaded into the counter after the service sequence is written to the Watchdog Service Register (WSR), or after the WDOG has been enabled. The service sequence is described in Section 34.5.3.3, “Reloading the Counter.” (The counter state machine is shown in Figure 34-6.) 34.5.3.2 Timer Countdown The counter is activated and begins to count down from its initial programmed value after the WDOG is enabled. If any system errors occur that prevent the software from servicing the Watchdog Service Register (WSR), the timer will time-out when the counter reaches zero. If the WSR is serviced prior to the counter MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 34-8 Freescale Semiconductor Watchdog Timer (WDOG) reaching zero, the WDOG reloads its counter to the time-out value indicated by bits WT[7:0] of the WCR, and it re-starts the countdown. A system reset will reset the counter and place it in the idle state at any time during the countdown. (The counter state machine is shown in Figure 34-6.) 34.5.3.3 Reloading the Counter The proper service sequence to write a time-out value to the counter begins by writing 0x 5555 followed by 0x AAAA to the WSR. To reload the counter, the writes must take place within the time-out value indicated by bits WT[7:0] of the WCR. Any number of instructions can be executed between the two writes. This service sequence is also used to activate the counter during the initial load. See Section 34.5.3.1, “Initial Load.” If the WSR is not loaded with 0x 5555 prior to writing 0x AAAA to the WSR, the counter is not reloaded. If any value other than 0x AAAA is written to the WSR after 0x 5555, the counter is not reloaded. 34.5.3.4 Time-Out If the counter reaches zero, the WDOG outputs either a system reset or the WDOG signal, depending on the state of the WRE bit in the WCR. A “0” written to the WRE bit configures the WDOG to generate a system reset. A “1” causes the WDOG to generate the WDOG signal. (The counter state machine is shown in Figure 34-6.) 34.5.4 Generation of Transfer Error on the IP Bus The WDOG module asserts a transfer error signal (IPS_XFR_ERROR) on the IP bus in the following cases: • Receiving an IP access to an address that is not implemented • A write access to the WRSR register that is a read-only register An error on an unimplemented address is generated only if the input pin resp_sel is low. Otherwise, an error is only asserted on a write access to the WRSR register (a read-only register). 34.5.5 Low-Power and DEBUG Modes The WDOG module can either continue or suspend the timer operation during low-power modes (WAIT and STOP) and DEBUG mode. 34.5.5.1 Low-Power Mode (WAIT, STOP) While in low-power mode, the WDOG Timer can be configured for continual operation or its operation can be suspended. If the WDOG low-power Enable (WDZST) bit in the WCR is set to “0”, the WDOG continues to operate using the ipg_clk_32k clock (32.768 kHz frequency clock) as its source. If the low-power enable (WDZST) bit is set to “1”, then the WDOG operation is suspended during low-power mode. Upon exiting low-power mode, the WDOG returns to the operational mode it was in prior to entering low-power mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 34-9 Watchdog Timer (WDOG) 34.5.5.2 DEBUG Mode The WDOG Timer can be configured for continual operation, or the operation can be suspended during debug mode. If the WDOG debug enable (WDBG) bit is set to “1” in the Watchdog Control Register (WCR), the WDOG module operation is suspended in debug mode. At this point, the counter is stopped, but register read and write accesses continue to function normally. Also, while in DEBUG mode, the WDE bit can be enabled-disabled directly. NOTE If the WDE bit is cleared while in DEBUG mode, it will remain cleared upon exiting DEBUG mode. If the WDE bit is not cleared while in DEBUG mode, the WDOG count will continue from its value before DEBUG mode was entered. 34.5.6 Watchdog Reset Control The WDOG generated reset signal wdog_rst can be asserted by a software write to the Software Reset Signal (SRS) bit of the WCR. It can also be generated by the following event: • WDOG time-out The wdog_rst is generated for 0.5 seconds for a time-out, but is deasserted early if a system reset is detected. In case of a software reset, the wdog_rst is asserted after three clocks of resetting the SRS bit and remains asserted for three IPG clocks (IP global functional clock). If a system reset is asserted in between, it deasserts before three IPG clocks have elapsed. . The watchdog-generated reset signal wdog_rst is an output to the (CCM) for system reset generation. NOTE The CCM of the IC generates the system reset signal on assertion of wdog_rst. 34.5.7 WDOG Operation WDOG can be asserted through software writes to the WDOG Assertion (WDA) bit of the WCR. It can also be generated as a result of a WDOG time-out. If asserted by a software write to the WDA bit, it remains asserted as long as the WDA bit is “0”. The counter timeout asserts it for 0.5 seconds. Both a system reset and a power-on reset can deassert it in between. WDOG is applied to the WDOG pin. After reset, the WOE bit in the WCR register controls the direction of this pin. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 34-10 Freescale Semiconductor Watchdog Timer (WDOG) 34.6 34.6.1 Initialization/Application Information State Machine The watchdog state machine is shown in Figure 34-6. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 34-11 Watchdog Timer (WDOG) idle no no resets negated ? timeout value? no watchdog enabled ? yes yes yes start counter no yes decrement counter yes yes STOP or DOZE exited? no Low Power mode? no DEBUG mode? no counter suspended yes suspend watchdog ? no no suspend watchdog ? yes DEBUG exited? no yes counter suspended watchdog enabled ? yes yes reload counter WSR serviced? no count = 0? yes assert timeout indication (From “system reset asserted?”) (Continued) no MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 34-12 Freescale Semiconductor Watchdog Timer (WDOG) (To “idle” state) yes system reset asserted ? no (From “assert timeout indication”) yes assert WDOG signal assert WDOG ? no assert reset Clock Reset Module (CRM) NOTE: A system reset will force the state machine to “idle” at any time during countdown. Figure 34-6. Counter State Machine MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 34-13 Watchdog Timer (WDOG) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 34-14 Freescale Semiconductor Book II, Part 6: System Control Peripherals Introduction The transfer of data between modules are controlled by the following system control peripherals: Chapter 35, “AHB-Lite IP Interface (AIPI) Module,” on page 35-1 Chapter 36, “Multi-Layer AHB Crossbar Switch (MAX),” on page 36-1 Chapter 37, “Direct Memory Access Controller (DMAC),” on page 37-1 AHB-Lite to IPS (AIPI) The AHB-Lite to IPS (AIPI) interfaces—AIPI1 and AIPI2—facilitate proper communication between the ARM-11 platform and devices that use AHB-Lite with peripherals that are IPS-compliant. Each AIPI in this device handles a separate MCU peripheral bus: AIPI1 interfaces to the MCU Peripheral Bus 1, which supports 16 on-platform peripherals; AIPI2 interfaces to the MCU Peripheral Bus 2, which also supports 32 on-platform peripherals). The AIPI provides all of the necessary bus structure and handshaking signals to allow high-speed communication between these peripheral devices and the internal bus structure of the ARM-11. Multi-Layer AHB Crossbar Switch (MAX) The purpose of the MAX is to concurrently support up to five simultaneous connections between master ports and slave ports. The MAX supports a 32-bit address bus width, and a 32-bit data bus width at all master and slave ports. Direct Memory Access Controller (DMAC) The Direct Memory Access Controller (DMAC) of i.MX27 device provides 16 DMA channels supporting linear memory, 2D memory and FIFO transfers to provide support for a wide variety of DMA operations. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Chapter 35 AHB-Lite IP Interface (AIPI) Module This chapter provides an overview of the AHB-Lite to IP bus interface (AIPI) module. The AIPI acts as an interface between the advanced ARM High-performance Bus “Lite” (AHB-Lite) and lower bandwidth peripherals conforming to the Freescale IP Bus Specification. There are two AIPI modules in i.MX27—AIPI1 and AIPI2. The following list summarizes the key features of the AIPI: • All peripheral read transactions require a minimum of 2 system clocks (R-AHB side) and all write transactions require a minimum of 3 system clocks (R-AHB side). • The AIPI supports 8-bit, 16-bit and 32-bit IP bus peripherals. (Byte, half word and word reads and write are supported to each.) • The AIPI supports multi-cycle accesses (16-bit operations to 8-bit peripherals and 32-bit operations to 16-bit and 8-bit peripherals). • The AIPI supports 31 external IP bus peripherals each with a 4 Kbyte memory map (a slot). Table 35-1. AHB-Lite To IP Bus V2.0 Interface Operation (Little Endian) Transfer Size Byte haddr [1] 0 0 1 1 0 0 1 1 0 0 1 1 [0] 0 1 0 1 0 1 0 1 0 1 0 1 X X 32 bit X X 1 X 16 bit IP Bus Size 8 bit ips_addr [1] 0 0 1 1 0 [0] 0 1 0 1 X R-AHB[31:24] — — — ips_data[7:0] — — — ips_data[15:8] — — — ips_data[31:24] Active Bus Section (R-AHB to IP Bus) R-AHB[23:16] — — ips_data[7:0] — — — ips_data[7:0] — — — ips_data[23:16] — R-AHB[15:8] — ips_data[7:0] — — — ips_data[15:8] — — — ips_data[15:8] — — R-AHB[7:0] ips_data[7:0] — — — ips_data[7:0] — — — ips_data[7:0] — — — MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 35-1 AHB-Lite IP Interface (AIPI) Module Table 35-1. AHB-Lite To IP Bus V2.0 Interface Operation (Little Endian) (continued) Transfer Size Half Word haddr [1] 0 [0] NA IP Bus Size 8 bit ips_addr [1] 0 [0] 0 1 1 1 0 1 0 1 0 1 Word NA NA 8 bit 32 bit 16 bit 0 1 X X 0 X X X X 0 1 1 0 1 16 bit 0 1 32 bit X X X X R-AHB[31:24] — — — ips_data[7:0] — ips_data[15:8] — ips_data[31:24] — — — ips_data[7:0] — ips_data[15:8] ips_data[31:24] Active Bus Section (R-AHB to IP Bus) R-AHB[23:16] — — ips_data[7:0] — — ips_data[7:0] — ips_data[23:16] — — ips_data[7:0] — — ips_data[7:0] ips_data[23:16] R-AHB[15:8] — ips_data[7:0] — — ips_data[15:8] — ips_data[15:8] — — ips_data[7:0] — — ips_data[15:8] — ips_data[15:8] R-AHB[7:0] ips_data[7:0] — — — ips_data[7:0] — ips_data[7:0] — ips_data[7:0] — — — ips_data[7:0] — ips_data[7:0] 35.1 Programming Model There are three registers that reside inside the AIPI. These registers correspond to the first slot (4 Kbyte memory region) of each of the 2 AIPIs in i.MX21 at 0x1000_0000 and 0x1002_0000, respectively. All three registers are 32-bit registers and can only be accessed in supervisor mode. Additionally, these registers can only be read from or written to by a 32-bit access. Two system clocks are required for read accesses and three system clocks are required for write accesses to the AIPI registers. CAUTION Writing to reserved register locations within the 4 Kbyte memory map of the AIPI register space (other than the three AIPI registers) will result in unknown behavior and an abort exception. Access to Reserved or Unoccupied locations in the AIPI space will result in an abort exception. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 35-2 Freescale Semiconductor AHB-Lite IP Interface (AIPI) Module 35.1.1 Peripheral Size Registers[1:0] These registers are used to tell the AIPI what size of IP bus peripheral is in each IP bus peripheral location. Peripheral locations that are not occupied should have their corresponding bits in the peripheral size registers (PSRs) programmed to 1 in each register. The least significant bit in the PSRs is a read-only bit as it governs the AIPI registers themselves. They are set and cleared appropriately to indicate the registers are 32-bit. PSR0 Bit Type Reset Peripheral Size Register 0 Addr 0x1000_0000 0x1002_0000 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 23 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 Bit Type Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 r 1 PSR1 Bit Type Reset Peripheral Size Register 1 Addr 0x1000_0004 0x1002_0004 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 23 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 Bit Type Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 r 1 The PSRs work together to indicate the size of the IP bus peripheral occupying the corresponding location, or to indicate there is no IP bus peripheral occupying the corresponding location. Table 35-2 shows how to program the PSR registers based on the size or availability of an IP bus peripheral. Table 35-2. PSR 1–0 Data Bus Size Encoding PSR 1–0 00 01 10 11 IP Bus Peripheral SIZE [x] 8-bit 16-bit 32-bit Unoccupied MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 35-3 AHB-Lite IP Interface (AIPI) Module 35.1.2 Peripheral Access Register The peripheral access register (PAR) tells the AIPI whether the IP bus peripheral corresponding to the bit location in this register may be accessed in user mode. If the peripheral may be accessed in supervisor mode only and a user mode access is attempted, an abort is generated and no IP bus activity occurs. The least significant bit in the PAR is a read-only bit as it governs the AIPI registers themselves. It is set to indicate supervisor access only. PAR Peripheral Access Register1 Addr 0x1000_0008 0x1002_0008 21 20 19 18 17 16 Bit Type Reset 31 30 29 28 27 26 25 24 23 22 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 Bit Type Reset 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 rw 1 r 1 A “1” indicates the corresponding peripheral is a supervisor access only peripheral. A “0” indicates the decision is left up to the peripheral (the AIPI allows user accesses). 35.2 AIPI1 and AIPI2 Peripheral Widths and PSR Setting Table 35-5 shows the data bus widths of the peripherals on the AIPI1 and the AIPI2 interfaces. System software should make use of information in the column, “Data Bus Width” to configure the PSR registers, accordingly. Table 35-3 and Table 35-4 show PSR settings for AIPI1 and AIPI2. Table 35-5 shows the peripheral sizes for the occupied, reserved and unoccupied locations. All reserved locations must be programmed as 32-bit locations. Table 35-3. AIPI1 PSR Setting PSR PSR[1] PSR[0] Setting 0xFFFB_FCFB 0x0004_0304 Table 35-4. AIPI2 PSR Setting PSR PSR[1] PSR[0] Setting 0xFFFF_FFFF 0x3FFC_0000 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 35-4 Freescale Semiconductor AHB-Lite IP Interface (AIPI) Module Table 35-5. i.MX21 AIPI Peripheral Access Sizes and IP Access Types Location Peripheral PSR[1] PSR[0] Data Bus Width 16-bit Read Write Read 8-bit Write AIPI1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23-31 AIPI1 Control DMA WDOG GPT1 GPT2 GPT3 PWM RTC KPP 1-Wire UART1 UART2 UART3 UART4 CSPI1 CSPI2 SSI1 SSI2 I2C SDHC1 SDHC2 GPIO AUDMUX CSPI3 Reserved 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 AIPI2 0 1 2 3 AIPI2 LCDC SLCDC Reserved 1 1 1 1 0 0 0 0 32-bit 32-bit 32-bit 32-bit N N N N N N — N N N N N N 32-bit 32-bit 16-bit 32-bit 32-bit 32-bit 32-bit 32-bit 16-bit 16-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 16-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit N N N N N N N N N N N N N N — N N N N N N N N N N Y — — Y Y Y Y N N N N — Y — N N N N Y — Y — Y Y N N N N Y N N N N N N N N N N Y N N N N N N — Y Y N N N N Y N N Y Y Y Y N N N N Y N N N N N N MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 35-5 AHB-Lite IP Interface (AIPI) Module Table 35-5. i.MX21 AIPI Peripheral Access Sizes and IP Access Types (continued) Location Peripheral PSR[1] PSR[0] Data Bus Width 32-bit 32-bit 32-bit 32-bit 32-bit — 32-bit — 16-bit Read N N N Y Y — N N Write N N N Y Y — N N Read Y N N Y Y — N N 8-bit Write Y N N Y Y — N N 4 5 6 7 8 9 10-17 18-29 USB OTG USB OTG EMMA CRM FIRI Reserved Reserved Unoccupied 1 1 1 1 1 — 1 1 0 0 0 0 0 — 0 1 35.3 Interface Timing This section describes AIPI interface timing characteristics. 35.3.1 Read Cycles Two clock read accesses are possible with the AIPI when the requested access size is equal to or smaller than the size of the targeted IP bus peripheral. If the requested access size is larger than that of the targeted IP bus peripheral (for example, a 32-bit access to a 16 bit peripheral) then a minimum of three clocks are required to complete the access. 35.3.2 Write Cycles Three clock write accesses are possible with the AIPI when the requested access size is equal to or smaller than the size of the targeted IP bus peripheral. If the requested access size is larger than that of the targeted IP bus peripheral (for example, a 32-bit access to a 16 bit peripheral) then a minimum of four clocks are required to complete the access. 35.3.3 Aborted Cycles The AIPI follows a standard procedure when a cycle is aborted and the abort is initiated by the AIPI itself or the targeted IP bus peripheral. The AIPI either fails to initiate or immediately terminates any IP bus activity that is ongoing. There are several conditions that can cause the AIPI to abort the current operation and report an error. The first is the case in which the targeted IP bus peripheral asserts its internal error signal. In this case the AIPI immediately terminates access to the targeted IP bus peripheral. Whether the current IP bus access is a multi-cycle access or a single cycle access has no bearing on the behavior of the AIPI. The AIPI responds identically in both cases. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 35-6 Freescale Semiconductor AHB-Lite IP Interface (AIPI) Module The second case that can cause an error response to the AHB-Lite is when a user-mode access is attempted to an IP bus peripheral whose corresponding PAR bit indicates it is a supervisor-only peripheral. In this case the AIPI does not initiate any IP bus activity but instead responds immediately by following the abort procedure described above. The third case that can cause an error response to the AHB-Lite is when an access is attempted to a location at which the PSRs indicate there is no IP bus peripheral. In this case the AIPI does not initiate any IP bus activity but instead responds immediately by following the abort procedure described above. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 35-7 AHB-Lite IP Interface (AIPI) Module MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 35-8 Freescale Semiconductor Chapter 36 Multi-Layer AHB Crossbar Switch (MAX) This chapter provides an overview of Multi-Layer AHB Crossbar Switch (MAX). The purpose of MAX is to concurrently support up to three simultaneous connections between 6 master ports and 3 slave ports. 36.1 Features The MAX module has the ability to gain control of all the slave ports and prevent any masters from making accesses to the slave ports. This feature is useful when the user wishes to turn off the clocks to the system and needs to ensure that no bus activity will be interrupted. MAX can put each slave port into a low power park mode so that slave port will not dissipate any power transitioning address, control or data signals when not being actively accessed by a master port. Each slave port can also support multiple master priority schemes. Each slave port has a hardware input which selects the master priority scheme so the user can dynamically change master priority levels on a slave port by slave port basis. The MAX allows concurrent transactions to occur from any master port to any slave port. It is possible for three master ports and all slave ports to be in use at the same time as a result of independent master requests. If a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting that slave port will stalled until the higher priority master completes its transactions. 36.2 Overview The MAX module routes bus transactions initiated on the master ports to the appropriate slave ports. There is no provision included to route transactions initiated on the slave ports to other slave ports or to master ports. Simply put, the slave ports do not support the bus request/bus grant protocol, the MAX assumes it is the sole master of each slave port. Since the MAX does not support the bus request/bus grant protocol, if multiple masters are to be connected to a single master port an external arbiter will need to be used.,Each master and slave port is fully AHB-Lite + AMBA V6 extensions compliant. The ports are not fully AHB compliant because the MAX does not support SPLITs or RETRYs. NOTE i.MX27 ARM9 platform implements a 6 master by 3 slave configuration. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-1 Multi-Layer AHB Crossbar Switch (MAX) Master Port 0 IP cntrl IP wdata IP rdata IP term Slave Port 0 Mstr port(s) request Mstr port(s) addr Mstr port(s) cntrl Mstr port(s) wdata Hready to mstr(s) Hresp0 to mstr(s) Mstr addr Mstr control Mstr Port request Mstr Port addr Mstr Port cntrl Mstr hready Mstr hresp0 Mstr read data Slv port hready(s) Slv port hresp0(s) Slv port hrdata(s) IP cntrl IP wdata Slv addr Slv cntrl Slv wdata Master 0 write data IP rdata IP term Slv hready Slv hresp0 halt request Master Port 5 IP cntrl IP wdata IP rdata IP term Mstr addr Mstr control Mstr Port request Mstr Port addr Mstr Port cntrl Mstr hready Mstr hresp0 Mstr read data Slv port hready(s) Slv port hresp0(s) Slv port hrdata(s) Master 5 write data Max halt request General Purpose Logic IP cntrl IP wdata IP rdata IP term Max_halted Slv IP cntrl IP wdata(s) IP rdata(s) halt request IP term(s) halt grant(s) Slave 2 read data halt grant Slave Port 2 Mstr port(s) request Mstr port(s) addr Mstr port(s) cntrl Mstr port(s) wdata Hready to mstr(s) Hresp0 to mstr(s) halt grant Slave 0 read data IP cntrl IP wdata Slv addr Slv cntrl Slv wdata IP rdata IP term Slv hready Slv hresp0 Figure 36-1. MAX Block Diagram 36.3 General Operation When a master makes an access to the MAX, access will be immediately taken by the MAX. If the targeted slave port of the access is available then the access will be immediately presented on the slave port. It is possible to make single clock (zero wait state) accesses through the MAX. If the targeted slave port of the MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-2 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) access is busy or parked on a different master port the requesting master will simply see wait states inserted (hready held negated) until the targeted slave port can service the master’s request. Latency in servicing the request will depend on each master’s priority level and the responding peripheral’s access time. Since MAX appears to be just another slave to the master device, master device will have no knowledge of whether or not it actually owns the slave port it is targeting. When the master does not have control of the slave port it is targeting, it will simply be wait stated. A master will be given control of the targeted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from occurring when a master has an outstanding request to one slave port that has a long response time, has a pending access to a different slave port, and a lower priority master is also making a request to the same slave port as the pending access of the higher priority master. Once the master has control of the slave port it is targeting the master will remain in control of that slave port until it gives up the slave port by running an IDLE cycle or by leaving that slave port for its next access. The master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is running a locked or fixed length burst transfer it will retain control of the slave port until that transfer is completed. Based on the AULB bit in the MGPCR (Master General Purpose Control Register) the master will either retain control of the slave port when doing undefined length incrementing burst transfers or will lose the bus to a higher priority master. The MAX terminates all master IDLE transfers (as opposed to allowing the termination to come from one of the slave busses). Additionally, when no master is requesting access to a slave port, MAX will drive IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When MAX is controlling the slave bus (that is, during low power park or halt mode), hmaster field will indicate 4’b0000. When a slave bus is being IDLEd by the MAX, it can park the slave port on the master port indicated by the PARK bits in the SGPCR or ASGPCR. This can be done in an attempt to save the initial clock of arbitration delay that would otherwise be seen if the master had to arbitrate to gain control of the slave port. The slave port can also be put into low power park mode in attempt to save power. 36.4 Memory Map and Register Definition This section provides the register programming information for the MAX registers. 36.4.1 Register Summary There are four registers that reside in each slave port of the MAX and one register that resides in each master port of the MAX. These registers are IP bus compliant registers. Read and write transfers both require two IP bus clock cycles. The registers can only be read from and written to in privileged mode. Additionally, these registers can only be read from or written to by 32-bit accesses. The registers are fully decoded and an error response is returned if an unimplemented location is accessed within the MAX. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-3 Multi-Layer AHB Crossbar Switch (MAX) The slave registers also feature a bit, which when written with a 1, will make it readable, and future write attempts will have no effect on the registers, thus resulting in an error response. Memory map for the MAX program-visible registers is shown in Table 36-1. 36.4.2 Memory Map Table 36-1. MAX Memory Map Address Register Master Priority Register for Slave Port 0 Master Priority Register for Slave Port 1 Master Priority Register for Slave Port 2 Alternate Master Priority Register for Slave Port 0 Alternate Master Priority Register for Slave Port 1 Alternate Master Priority Register for Slave Port 2 General Purpose Control Register for Slave Port 0 General Purpose Control Register for Slave Port 1 General Purpose Control Register for Slave Port 2 Alternate SGPCR for Slave Port 0 Alternate SGPCR for Slave Port 1 Alternate SGPCR for Slave Port 2 General Purpose Control Register for Master Port 0 – General Purpose Control Register for Master Port 5 Access Reset Value R/W 0x0054_3210 Section/Page 36.4.5/36-6 Table 36-1 shows the MAX memory map. 0x1003_F000 (MPR0) 0x1003_F100 (MPR1) 0x1003_F200 (MPR2) 0x1003_F004 (AMPR0) 0x1003_F104 (AMPR1) 0x1003_F204 (AMPR2) 0x1003_F010 (SGPCR0) 0x1003_F110 (SGPCR1) 0x1003_F210 (SGPCR2) 0x1003_F014 (ASGPCR0) 0x1003_F114 (ASGPCR1) 0x1003_F214 (ASGPCR2) 0x1003_F800 (MGPCR0) – 0x1003_FD00 (MGPCR5) R/W 0x0000_0000 36.4.6/36-7 R/W 0x0000_0000 36.4.7/36-9 R/W 0x0000_0000 36.4.8/36-11 R/W 0x0054_3210 36.4.5/36-6 36.4.3 Register Summary Figure 36-2. Key to Register Fields Figure 36-2 shows the key to the register fields, and Table 36-2 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Table 36-2. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-4 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) Table 36-2. Register Figure Conventions (continued) Convention w1c Self-clearing bit Description Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 36-3. MAX Detailed Register Summary Name 0x1003_F000 (MPR0) 0x1003_F100 (MPR1) 0x1003_F200 (MPR2) 0x1003_F004 (AMPR0) 0x1003_F104 (AMPR1) 0x1003_F204 (AMPR2) 0x1003_F010 (SGPCR0) 0x1003_F110 (SGPCR1) 0x1003_F210 (SGPCR2) 0x1003_F014 (ASGPCR0) 0x1003_F114 (ASGPCR1) 0x1003_F214 (ASGPCR2) 0x1003_F800 (MGPCR0) – 0x1003_FD00 (MGPCR5) R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 AULB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARB 0 0 PCTL 0 PARK 0 HLP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARB 0 0 PCTL 0 PARK RO HLP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTR_3 0 MSTR_2 0 MSTR_1 0 MSTR_0 0 0 0 0 0 0 0 0 0 MSTR_5 0 MSTR_4 0 MSTR_3 0 MSTR_2 0 MSTR_1 0 MSTR_0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 MSTR_5 0 MSTR_4 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-5 Multi-Layer AHB Crossbar Switch (MAX) 36.4.4 MAX Register Descriptions This section contains the detailed register descriptions for the MAX registers. 36.4.5 Master Priority Registers (MPR0–MPR2) The Master Priority Register (MPR) sets the priority of each master port on a per slave port basis and resides in each slave port. The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO (Read Only) bit has been set in the Slave General Purpose Control Register the Master Priority Register can only be read from, attempts to write to it will have no effect on the MPR and result in an error response. Additionally, no two available master ports may be programmed with the same priority level. Attempts to program two or more available masters with the same priority level will result in an error response and the MPR will not be updated. 0x1003_F000 (MPR0) 0x1003_F100 (MPR1) 0x1003_F200 (MPR2) 31 30 29 28 27 26 25 24 23 22 21 Access: Supervisor Read/Write 20 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 MSTR_5 0 MSTR_4 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 MSTR_3 0 MSTR_2 0 MSTR_1 0 MSTR_0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Table 36-4. Master Priority Register (MPR0–MPR2) Table 36-5. Master Priority Register Field Descriptions Field 31–23 22–20 MSTR_5 Description Reserved. They are read as zero and should be written with zero for upward compatibility. Master 5 Priority. These bits set the arbitration priority for master port 5 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 4 Priority. These bits set the arbitration priority for master port 4 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. 19 18–16 MSTR_4 15 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-6 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) Table 36-5. Master Priority Register Field Descriptions (continued) Field 14–12 MSTR_3 Description Master 3 Priority. These bits set the arbitration priority for master port 3 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 2 Priority. These bits set the arbitration priority for master port 2 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 1 Priority. These bits set the arbitration priority for master port 1 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 0 Priority. These bits set the arbitration priority for master port 0 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. 11 10–8 MSTR_2 7 6–4 MSTR_1 3 2–0 MSTR_0 36.4.6 Alternate Master Priority Register for Slave Port 0–2 (AMPR0–2) The Alternate Master Priority register AMPR sets alternate priorities of each master port on a per slave port basis. AMPR has identical function like MPR. AMPR purpose is to allow the user to set up an alternate set of priorities in the event they want to do some sort of context switching. A hardware input to the MAX controls (on a slave port by slave port basis) whether or not the slave port uses MPR or AMPR. Refer Table 36-5 for AMPR bit descriptions as they are identical to MPR. AMPR can only be accessed in privileged mode with 32-bit accesses. Once the RO (Read Only) bit is set in the General Purpose Control Register, AMPR can only be read from, attempts to write to it will result in an error response. Additionally, no two available master ports may be programmed with the same priority level. Attempts to program two or more available masters with the same priority level will result in an error response and the AMPR will not be updated. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-7 Multi-Layer AHB Crossbar Switch (MAX) 0x1003_F004 (AMPR0) 0x1003_F104 (AMPR1) 0x1003_F204 (AMPR2) 31 30 29 28 27 26 25 24 23 22 21 Access: Supervisor Read/Write 20 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 MSTR_5 0 MSTR_4 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 MSTR_3 0 MSTR_2 0 MSTR_1 0 MSTR_0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Table 36-6. Alternate Priority Register (MPR0–MPR2) Table 36-7. Alternate Priority Register Field Descriptions Field 31–23 22–20 MSTR_5 Description Reserved. They are read as zero and should be written with zero for upward compatibility. Master 5 Priority. These bits set the arbitration priority for master port 5 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 4 Priority. These bits set the arbitration priority for master port 4 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 3 Priority. These bits set the arbitration priority for master port 3 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 2 Priority. These bits set the arbitration priority for master port 2 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. Reserved. They are read as zero and should be written with zero for upward compatibility. Master 1 Priority. These bits set the arbitration priority for master port 1 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. 19 18–16 MSTR_4 15 14–12 MSTR_3 11 10–8 MSTR_2 7 6–4 MSTR_1 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-8 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) Table 36-7. Alternate Priority Register Field Descriptions (continued) Field 3 2–0 MSTR_0 Description Reserved. They are read as zero and should be written with zero for upward compatibility. Master 0 Priority. These bits set the arbitration priority for master port 0 on the associated slave port. These bits are initialized by hardware reset. 000 This master has the highest priority when accessing the slave port. 111 This master has the lowest priority when accessing the slave port. 36.4.7 General Purpose Control Register for Slave Port 0–2 (SGPCR0–2) The Slave General Purpose Control Register (SGPCR) controls several features of each slave port. The Read Only (RO) bit will prevent any registers associated with this slave port from being written to once set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only a reset condition will allow it to be written again. The Halt Low Priority (HLP) bit will set the priority of the max_halt_request input to the lowest possible priority for initial arbitration of the slave ports. By default it is the highest priority. NOTE Setting this bit will not effect the max_halt_request from attaining highest priority once it has control of the slave ports. The PCTL bits determine how the slave port will park when no master is actively making a request. The available options are to park on the master defined by the PARK bits, park on the last master to use the slave port, or go into a low power park mode which will force all the outputs of the slave port to inactive states when no master is requesting an access. The low power park feature can result in an overall power savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any master tries to access it when it is not in use because it will not be parked on any master. The PARK bits determine which master the slave will park on when no master is making an active request and the max_halt_request input is negated. CAUTION Only select master ports that are actually present in the i.MX27. If you program the PARK bits to a master not present in the i.MX27 undefined behavior will result. See Figure 36-3 for an illustration of valid bits in the SGPCR, and Table 36-8 for its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-9 Multi-Layer AHB Crossbar Switch (MAX) 0x1003_F010 (SGPCR0) 0x1003_F110 (SGPCR1) 0x1003_F210 (SGPCR2) 31 30 29 28 27 26 25 24 23 22 21 Access: Supervisor Read/Write 20 19 18 17 16 R W Reset RO1 HLP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 ARB 0 0 PCTL 0 PARK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 36-3. Slave General Purpose Control Register (SGPCR0-2) 1 Once this bit is written to a 1, then only hardware reset will return it to a 0. Table 36-8. Slave General Purpose Control Register Field Descriptions Field 31 RO Description Read Only. This bit is used to force all of a slave port’s registers to be read only. Once written to 1 it can only be cleared by hardware reset. This bit is initialized by hardware reset. 0 All of this slave port’s registers can be written. 1 All of this slave port’s registers are read only and cannot be written (attempted writes have no effect and result in an error response). Halt Low Priority. This bit is used to set the initial arbitration priority of the max_halt_request input. This bit is initialized by hardware reset. 0 The max_halt_request input has the highest priority for arbitration on this slave port 1 The max_halt_request input has the lowest initial priority for arbitration on this slave port. Reserved. They read as zero and should be written with zero for upward compatibility. Arbitration Mode. These bits are used to select the arbitration policy for the slave port. These bits are initialized by hardware reset. 00 Fixed Priority. 01 Round Robin (rotating) Priority 10 Reserved 11 Reserved Reserved. They read as zero and should be written with zero for upward compatibility. Parking Control.These bits determine the parking control used by this slave port. These bits are initialized by hardware reset. 00 When no master is making a request the arbiter will park the slave port on the master port defined by the PARK bit field. 01 When no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10 When no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11 Reserved 30 HLP 29–10 9–8 ARB 7–6 5–4 PCTL MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-10 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) Table 36-8. Slave General Purpose Control Register Field Descriptions (continued) Field 3 2–0 PARK Description Reserved. They read as zero and should be written with zero for upward compatibility. Park. These bits are used to determine which master port this slave port parks on when no masters are actively making requests and the PCTL bits are set to 00. These bits are initialized by hardware reset. 000 Park on Master Port 0 001 Park on Master Port 1 010 Park on Master Port 2 011 Park on Master Port 3 100 Park on Master Port 4 101 Park on Master Port 5 110 Reserved 111 Reserved NOTE: Reserved bits are for future expansion. It is read as zero and should be written with zero for upward compatibility 36.4.8 Alternate SGPCR for Slave Port 0–2 (ASGPCR0–2) The ASGPCR has identical function as the SGPCR with the notable exception that it lacks the RO (Read Only) bit contained in the SGPCR. ASGPCR purpose is same as AMPR, to allow the user to set up an alternate set of general control fields in the event they want to do some sort of context switching. A hardware input to the MAX controls (on a slave port by slave port basis) whether or not the slave port uses the SGPCR or ASGPCR. Refer Table 36-8 for descriptions of bit fields in ASGPCR as they are identical except for the RO bit. ASGPCR can only be accessed in privileged mode with 32-bit accesses. Once the RO (Read Only) bit has been set in the SGPCR the ASGPCR can only be read from, attempts to write to it will have no effect on the ASGPCR and result in an error response. NOTE ASGPCR does not contain a RO (Read Only) bit. RO bit in SGPCR has control over the ASGPCR’s ability to be written. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-11 Multi-Layer AHB Crossbar Switch (MAX) ) 0x1003_F014 (ASGPCR0) 0x1003_F114 (ASGPCR1) 0x1003_F214 (ASGPCR2) 31 30 29 28 27 26 25 24 23 22 21 Access: Supervisor Read/Write 20 19 18 17 16 R W Reset 0 HLP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 ARB 0 0 PCTL 0 PARK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 36-4. Alternate SGPCR for Slave Port0–2 (ASGPCR0-2) Table 36-9. Alternate Slave General Purpose Control Register Field Descriptions Field 31 30 HLP Description Reserved. They read as zero and should be written with zero for upward compatibility. Halt Low Priority. This bit is used to set the initial arbitration priority of the max_halt_request input. This bit is initialized by hardware reset. 0 The max_halt_request input has the highest priority for arbitration on this slave port 1 The max_halt_request input has the lowest initial priority for arbitration on this slave port. Reserved. They read as zero and should be written with zero for upward compatibility. Arbitration Mode. These bits are used to select the arbitration policy for the slave port. These bits are initialized by hardware reset. 00 Fixed Priority. 01 Round Robin (rotating) Priority 10 Reserved 11 Reserved Reserved. They read as zero and should be written with zero for upward compatibility. Parking Control.These bits determine the parking control used by this slave port. These bits are initialized by hardware reset. 00 When no master is making a request the arbiter will park the slave port on the master port defined by the PARK bit field. 01 When no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10 When no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11 Reserved 29–10 9–8 ARB 7–6 5–4 PCTL MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-12 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) Table 36-9. Alternate Slave General Purpose Control Register Field Descriptions (continued) Field 3 2–0 PARK Description Reserved. They read as zero and should be written with zero for upward compatibility. Park. These bits are used to determine which master port this slave port parks on when no masters are actively making requests and the PCTL bits are set to 00. These bits are initialized by hardware reset. 000 Park on Master Port 0 001 Park on Master Port 1 010 Park on Master Port 2 011 Park on Master Port 3 100 Park on Master Port 4 101 Park on Master Port 5 110 Reserved 111 Reserved 36.4.8.1 General Purpose Control Register for Master Port 0–5 (MGPCR0–5) The Master General Purpose Control Register (MGPCR) presently controls only whether or not the master’s undefined length burst accesses will be allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters. The AULB (Arbitrate on Undefined Length Bursts) bit field determines whether (and when) or not the MAX will arbitrate away the slave port the master owns when the master is performing undefined length burst accesses. See Figure 36-5 for an illustration of valid bits in the MGPCR, and Table 36-10 for its field descriptions. 0x1003_F800 (MGPCR0) 0x1003_F900 (MGPCR1) 0x1003_FA00 (MGPCR2) 0x1003_FB00 (MGPCR3) 0x1003_FC00 (MGPCR4) 0x1003_FD00 (MGPCR5) 31 30 29 28 27 26 25 24 23 22 21 Access: Supervisor Read/Write 20 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 AULB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 36-5. Master General Purpose Control Registers (MGPCR0-5) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-13 Multi-Layer AHB Crossbar Switch (MAX) Table 36-10. Master General Purpose Control Register Field Descriptions Field 31–3 2–0 AULB Description Reserved. They read as zero and should be written with zero for upward compatibility. Arbitrate on Undefined Length Bursts. These bits are used to select the arbitration policy during undefined length bursts by this master. These bits are initialized by hardware reset. 000 No arbitration will be allowed during an undefined length burst. 001 Arbitration will be allowed at any time during an undefined length burst. 010 Arbitration will be allowed after four beats of an undefined length burst. 011 Arbitration will be allowed after eight beats of an undefined length burst. 100 Arbitration will be allowed after 16 beats of an undefined length burst. 101 Reserved 110 Reserved 111 Reserved 36.5 Function This section describes the functionality of the MAX in greater detail. 36.5.1 Arbitration MAX supports two arbitration schemes; a simple fixed-priority comparison algorithm, and a simple round-robin fairness algorithm. Arbitration schemes are independently programmable for each slave port. 36.5.1.1 Arbitration During Undefined Length Bursts Arbitration points during an undefined length burst are defined by the current master’s MGPCR AULB field setting. When a defined length is imposed on the burst via the AULB bits the undefined length burst will be treated as a single or series of single back to back fixed length burst accesses. Example: A master runs an undefined length burst and AULB bits in MGPCR indicate arbitration will occur after fourth beat of the burst. Master runs two sequential beats and then starts what will be an 12 beat undefined length burst access to a new address within the same slave port region as the previous access. MAX will not allow an arbitration point until the fourth overall access (second beat of second burst). At that point all remaining accesses will be open for arbitration until the master loses control of the slave port. Assume master loses control of the slave port after fifth beat of the second burst. Once the master regains control of the slave port, no arbitration point will be available until master has run four more beats of its burst. After fourth beat of the (now continued) burst (9th beat of second burst from master’s perspective) is taken, all beats of the burst will once again be open for arbitration until the master loses control of the slave port. Assume the master again loses control of the slave port on the fifth beat of the third (now continued) burst (10th beat of second burst from master’s perspective). Once the master regains control of the slave port it will be allowed to complete its final two beats of its burst without facing arbitration. NOTE Fixed length burst accesses will not be affected by AULB bits. All fixed length burst accesses will lock out arbitration until the last beat of the fixed length burst. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-14 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) 36.5.1.2 Fixed Priority Operation When operating in fixed-priority mode, each master is assigned a unique priority level in the MPR and AMPR. If two masters both request access to a slave port the master with the highest priority in the selected priority register will gain control over the slave port. Any time a master makes a request to a slave port the slave port checks to see if the new requesting master’s priority level is higher than that of the master that currently has control over the slave port (unless the slave port is in a parked state). The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. If the new requesting master’s priority level is higher than that of the current master that has control of the slave port, the new requesting master will be granted control over the slave port at the next clock edge. The exception to this rule is if the master that currently has control over the slave port is running a fixed length burst transfer or a locked transfer. In this case the new requesting master will have to wait until the end of the burst transfer or locked transfer before it will be granted control of the slave port. If the master is running an undefined length burst transfer, the new requesting master must wait until an arbitration point for the undefined length burst transfer before it will be granted control of the slave port. Arbitration points for an undefined length burst are defined in MGPCR for each master. If the new requesting master’s priority level is lower than that of the current master that has control of the slave port, the new requesting master will be forced to wait until the current master has control of the slave port either runs an IDLE cycle or runs a non IDLE cycle to a location other than the current slave port. 36.5.1.3 Round-Robin Priority Operation When operating in round-robin mode, each master is assigned a relative priority based on the master number. This relative priority is compared to the ID of the last master to perform a transfer on the slave bus. The highest priority requesting master will become owner of the slave bus as the next transfer boundary (accounting for locked and fixed-length burst transfers). Priority is based on how far ahead the ID of the requesting master is to the ID of the last master (ID is defined by master port number, not hmaster field). Once granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line will be granted access to the slave port at the next assertion of sX_hready, or possibly on the next clock cycle if the current master has no pending access request. As an example of arbitration in round-robin mode, assume the MAX is implemented with master ports 0, 1, 2, 3, 4 and 5. If the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, (master ports 2 and 3 make no requests), they will be serviced in the order 4, 5 and then 0. Parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the parked master actually performs a transfer. Hand-off will occur to the next master in line after one cycle of arbitration. If the slave port is put into low power park mode the round-robin pointer will be reset to point at master port 0, giving it the highest priority. 36.5.2 Priority Assignment Each master port needs to be assigned a unique 3 bit priority level. If an attempt is made to program multiple master ports with the same priority level within a register (MPR or AMPR) the MAX will respond with an error and the registers will not be updated. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-15 Multi-Layer AHB Crossbar Switch (MAX) 36.5.2.1 Context Switching The MAX has a hardware input per slave port (sX_ampr_sel) which is used to select which registers the master priority levels and general purpose control bits will be taken from. When sX_ampr_sel is 0, MPR and SGPCR will be selected and when sX_ampr_sel is 1, AMPR and ASGPCR will be selected. This hardware input is useful for context switching so the user does not have to rewrite the MPR or SGPCR if a particular slave port would temporarily benefit from modifying the master priority levels or functions affected by the bits in the SGPCR. 36.5.3 36.5.3.1 Master Port Functionality General Each master port consists of two decoders, a capture unit, a register slice, a mux and a small state machine. The first decoder is used to decode haddr and control signals coming directly from the master, telling the state machine where the master’s next access will be and if it is in fact a legal access. The second decoder gets its input from the capture unit, so it may be looking directly at the signals coming from the master or it may be looking at captured signals coming from the master, depending entirely on the targeted slave port state. The second decoder is then used to generate the access requests that go to the slave ports. Capture unit is used to capture the address and control information coming from the master in the event that the targeted slave port cannot immediately service the master. Capture unit is controlled by outputs from the state machine which tell it to either pass through the original master signals or the captured signals Register slice contains the registers associated with the specific master port. The registers have a quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine. The mux is used simply to select which slave’s read data is sent back to the master. The mux is controlled by the state machine. The state machine controls all aspects of the master port. It knows which slave port the master wants to make a request to and controls when that request is made. It also has knowledge of each slave port, knowing whether or not the slave port is ready to accept an access from the master port. This will determine whether or not the master may immediately have its request taken by the slave port or whether the master port will have to capture the master’s request and queue it at the slave port boundary. A block diagram of the master port can be seen in Figure 36-6. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-16 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) Capture Unit Addr/Ctrl Async/Flopped_sel Addr/Ctrl Addr/Ctrl Slave_port_rqst[2:0] Request_enable Decoder Decoder Addr/Ctrl Next_slave_port[2:0] Illegal_access State Machine Next_slave_port[2:0] Illegal_access Hready_in Slv_hresp0[2:0] Hready_out Slv_is_mine[2:0] Hresp0 Control_bits Rdata_sel Async/Flopped_sel Request_enable Slv_hready[2:0] Registers Read_sel Write_sel Wdata Xfr_wait Xfr_error Rdata Control_bits Mux Hrdata Sel Slv_hrdata[2:0] Figure 36-6. MAX Master Port Block Diagram 36.5.3.2 Decoders Decoders are very simple as they ensure an access request is allowed to be made and that the slave port targeted is actually present in the design. The decoders feeding the state machine are always enabled. The decoders that select the slave are enabled only when the master port controlling state machine wants to make a request to a slave port. This is necessary so that if a master port is making an access to a slave port and is being wait stated, and its next access is to a different slave port, the request to the second slave port can be held off until the access to the first slave port is terminated. The decoders also output a “hole MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-17 Multi-Layer AHB Crossbar Switch (MAX) decode” or illegal access signal which tells the state machine that the master is trying to access a slave port that does not exist. 36.5.3.3 Capture Unit The capture unit simply captures the state of the master’s address and control signals if the MAX cannot immediately pass the master’s request through to the proper slave port. The capture unit consists of a set of flops and a mux which selects either the asynchronous path from address and control or the flopped (captured) address and control information. 36.5.3.4 Registers Registers in the master port are only those registers associated with this particular master port. The read and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level because not all the IP bus signals are routed this deep in the design. There is a register control block at the same level of the master port and slave port instantiations in the MAX. This control block ensures that all accesses are 32-bit privileged accesses before passing them on to the master ports. The register outputs are connected directly to the state machine. 36.5.3.5 36.5.3.5.1 State Machine States The master side state machine’s main function is to monitor the master port activities. There are six states: busy, idle, stalled, steady state, first cycle error response and second cycle error response. The busy state is used when the master runs a BUSY cycle to the master port. The master port maintains its request to the slave port if it currently owns the slave port; however, if it loses control of the slave port it will no longer maintain its request. If the master port loses control of the slave port it will not be allowed to make another request to the slave port until it runs a NSEQ or SEQ cycle. The idle state is used when the master runs a valid IDLE cycle to the master port. The master port makes no requests to the slave ports (disables the slave port decoder) and terminates the IDLE cycle. The stalled state is used when the master makes a request to a slave port that is not immediately ready to receive the request. In this case the state machine will direct the capture unit to send out the captured address and control signals and will enable the slave port decoder to indicate a pending request to the appropriate slave port. The steady state is used when the master port and slave port are in fully asynchronous mode, making the MAX completely transparent in the access. The state machine selects the appropriate slave’s hresp0, hready and hrdata to pass back to the master. The first cycle error response and second cycle error response states are self explanatory. The MAX will respond with an error response to the master if the master tries to access an unimplemented memory location through the MAX (that is, a slave port that does not exist). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-18 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) 36.5.3.5.2 Slave Swapping The design of the master side state machine is fairly straight forward. The one real decision to be made is how to handle the master moving from one slave port access to another slave port access. The approach that was taken was to minimize or eliminate, when possible, any “bubbles” that would get inserted into the access due to switching slave ports. The state machine will not allow the master to request access to another slave port until the current access being made is terminated. This prevents a single master from owning two slave ports at the same time (the slave port it is currently accessing and the slave port it wishes to access next). The state machine also maintains watch on the slave port the master is accessing as well as the slave port the master wishes to switch to. If the new slave port is parked on the master then the master will be able to make the switch without incurring any delays. The termination of the current access will also act as the launch of the new access on the new slave port. If the new slave port is not parked on the master then the master will incur a minimum one clock delay before it can launch its access on the new slave port. This is the same for switching from the busy or idle state to actively accessing a slave port. If the slave port is parked on the master the state machine will go to the steady state and the access will begin immediately. If the slave port is not parked on the master (serving another master, parked on another master or in low power park mode) then the state machine will transition to the stalled state and at least a one clock penalty will be paid. 36.5.4 36.5.4.1 Slave Port Functionality General Each slave port consists of a register slice, a bank of muxes and a state machine. The register slice contains the registers associated with the specific slave port. The registers have a quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine. A block diagram of a slave port can be seen in Figure 36-7. 36.5.4.2 Muxes Figure 36-7 shows only one block for all the muxes. In reality that block instantiates many 6 to 1 muxes, one for each master-to-slave signal in fact. All the muxes are designed in an AND - OR fashion, so that if no master is selected the output of the muxes will be zero. (This is an important feature for low power park mode.) The muxes also have an override signal which is used by the slave port to asynchronously force IDLE cycles onto the slave bus. When the state machine forces an IDLE cycle it zeros out htrans and hmastlock, making sure the slave bus sees a valid IDLE cycle being run by the MAX. The mux controlling htrans also contains an additional control signal from the state machine so that a NSEQ transaction can be forced. This is done at any time when the slave port switches masters to ensure that no IDLE-SEQ, BUSY-SEQ or NSEQ-SEQ transactions are seen on the slave port when they shouldn’t be. If the state machine indicates to run both IDLE and NSEQ cycle, the IDLE directive will have priority. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-19 Multi-Layer AHB Crossbar Switch (MAX) NOTE IDLE-SEQ is in fact an illegal access, but a possible scenario given the multi-master environment in the MAX unless corrected by the MAX. Registers Read_sel Write_sel Wdata Control_bits Xfr_wait Xfr_error Rdata ampr_sel State Machine Master_requests[5:0] m[5:0]_high_priority halt_request slave_halted Current_master[5:0] Master_hready[5:0] Master_hresp0[5:0] Control_bits Slv_hready Slv_hresp0 Master_sel[5:0] Force_idle Force_nseq Muxes Force_nseq Force_idle Master_addr[5:0] Master_cntrl[5:0] Master_wdata[5:0] Master_sel[5:0] Slv_addr_signals Slv_cntrl_signals Slv_wdata Figure 36-7. MAX Slave Port Block Diagram 36.5.4.3 Registers There is a register control block at the same level of the master port and slave port instantiations in the MAX. This control block ensures that all accesses are 32-bit privileged accesses before passing them on to the master and slave ports. The registers in the slave port are only those registers associated with this particular slave port. The read and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level because not all the IP bus signals are routed this deep in the design. The register outputs are connected directly to the slave state machine with the sX_ampr_sel input determining which priority register values, halt priority value, arbitration algorithm and parking control bits are passed to the state machine. The registers can be read from an unlimited number of times. The registers can only MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-20 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) be written to as long as the RO bit is written to 0 in the SGPCR, once it is written to a 1 only a hardware reset will allow the registers to be written again. 36.5.4.4 36.5.4.4.1 State Machine States At the heart of the slave port is the state machine. The state machine is simplicity itself, requiring only four states—steady state, transition state, transition hold state and hold state. Either the slave port is owned by the same master it was in the last clock cycle (either by active use or by parking), it is transitioning to a new master (either for active use or parking), it is transitioning to a new master during wait states or it is being held on the same master pending a transition to a new master. 36.5.4.4.2 Arbitration The real work of the state machine is to determine which master port will be in control of the slave port in the next clock cycle. Each master is programmed with a fixed 3 bit priority level. The MAX uses these bits in determining priority levels when programmed for fixed priority mode of operation. Arbitration always occurs on a clock edge, but only occurs on edges when a change in mastership will not violate AHB-Lite protocols. Valid arbitrations points include any clock cycle in which sX_hready is asserted (provide the master is not performing a burst or locked cycle) and any wait state in which the master owning the bus indicates a transfer type of IDLE (provided the master is not performing a locked cycle). Since arbitration can occur on every clock cycle the slave port masks off all master requests if the current master is performing a locked transfer or a protected burst transfer, guaranteeing that no matter how low its priority level it will be allowed to finish its locked or protected portion of a burst sequence. 36.5.4.4.3 Master Hand-Off The only times slave port will switch masters when programmed for fixed priority mode of operation is when a higher priority master makes a request or when the current master is the highest priority and it gives up the slave port by either running and IDLE cycle to the slave port or running a valid access to a location other than the slave port. If the current master loses control of the slave port because a higher priority master takes it away the slave port will not incur any wasted cycles. The current master will get its current cycle terminated by the slave port at the same time the new master’s address and control information will be recognized by the slave port. This will look like a seamless transition on the slave port. If the current master is being wait stated when the higher priority master makes its request, then the current master will be allowed to make one more transaction on the slave bus before giving it up to the new master. Figure 36-8 illustrates the effect of a higher priority master taking control of the bus when the slave port is programmed for a fixed priority mode of operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-21 Multi-Layer AHB Crossbar Switch (MAX) 1 hclk m2 request m3 request m4 request m5 request Highest Priority Requester Address/Cntrl owner htrans hready Master 5 MAX IDLE 2 3 4 5 6 7 8 9 10 Master 5 Master 5 NSEQ Master 4 Master 3 Master 5 NSEQ Master 2 Master 3 Master 2 NSEQ Master 4 Master 3 NSEQ None Master 4 NSEQ MAX IDLE Figure 36-8. Low to High Priority Mastership Change 1 hclk 2 3 4 5 6 7 8 9 m0 request m2 request m4 request Highest Priority Requester Address/Cntrl owner htrans MAX Master 0 Master 2 None Master 4 None Master 0 MAX Master 2 MAX Master 4 MAX IDLE NSEQ IDLE NSEQ IDLE NSEQ IDLE hready Figure 36-9. High to Low Priority Mastership Change If current master is the highest priority master and it gives up the slave port by running an IDLE cycle or a valid cycle to another location other than the slave port, the next highest priority master will gain control of the slave port. If the current access incurs any wait states then the transition will be seamless and no bandwidth will be lost; however, if the current transaction is terminated without wait states, then one IDLE cycle will be forced onto the slave bus by the MAX before the new master will be able to take control of MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-22 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) the slave port. If no other master is requesting the bus then IDLE cycles will be run by the MAX but no bandwidth will be lost since no master is making a request. Figure 36-9 illustrates the effect of a higher priority master giving up control of the bus. When the slave port is programmed for round-robin mode of arbitration, then it will switch masters at any time there is more than one master actively making a request to it. This will happen because any master other than the one which presently owns the bus will be considered to have higher priority. Figure 36-10 shows an example of round-robin mode of operation. 1 hclk m0 request m1 request m4 request m5 request Highest Priority Requester Address/Cntrl owner htrans hready Master 1 Master 4 MAX IDLE Master 1 NSEQ Master 5 Master 4 NSEQ Master 0 Master 5 NSEQ Master 4 Master 0 NSEQ Master 5 None MAX IDLE 2 3 4 5 6 7 8 9 10 Master 4 Master 5 NSEQ NSEQ Figure 36-10. Round-Robin Mastership Change 36.5.4.4.4 Parking If no master is currently making a request to the slave port then the slave port will be parked. It will park in one of four places, dictated by the PCTL and PARK bits in the GPCR or AGPCR (depending on the state of the sX_ampr_sel) and the locked state of the last master to access it. If the last master to access the slave port ran a locked cycle and continues to run locked cycles even after leaving the slave port, the slave port will park on that master irrespective of GPCR bit settings and without regard to pending requests from other masters. This is done so that a master can run a locked transfer to the slave port, leave it, and return to it and be guaranteed that no other master accessed it. If locking is not an issue for parking the GPCR bits will dictate the parking method. If PCTL bits are set for “low power park” mode then the slave port will enter low power park mode. It will not recognize any master as being in control of it and it will not select any master’s signals to pass through to the slave bus. In this case all slave bus activity will effectively halt because all slave bus signals being driven from the MAX will be 0. This of course can save quite a bit of power if the slave port will not be in use for some time. The down side is that when a master does make a request to the slave port it will be delayed by one clock since it will have to arbitrate to acquire ownership of the slave port. If PCTL bits are set to “park on last” mode then the slave port will park on the last master to access it, passing all that masters signals through to the slave bus. MAX will asynchronously force htrans[1:0], hmaster[3:0], hburst[2:0] and hmastlock to 0 for all access that the master does not run to the slave port. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-23 Multi-Layer AHB Crossbar Switch (MAX) When that master access the slave port again it will not pay any arbitration penalty; however, if any other master wishes to access the slave port a one clock arbitration penalty will be imposed. Figure 36-11 illustrates parking on the last master. Note that in cycle 6 simultaneous requests are made by master 2 and master 4. Although master 2 has higher priority, the slave bus is parked on master 4 so master 4’s access will be taken first. The slave port parks on master 2 once it has given control to master 2. This same situation can occur when parking on a specific master as well. 1 hclk 2 3 4 5 6 7 8 9 m0 request m2 request m4 request Last Master Master 0 Master 4 Master 2 Park Highest Priority Requester Address/Cntrl owner htrans Master 0 None Master 4 None Master 2 None MAX Master 0 MAX Master 4 MAX Master 4 Master 2 MAX IDLE NSEQ IDLE NSEQ IDLE NSEQ NSEQ IDLE hready Figure 36-11. Parking on Last Master MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-24 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) 1 hclk 2 3 4 5 6 7 8 9 m0 request m2 request m4 request Master 2 Park Highest Priority Requester Address/Cntrl owner htrans Master 0 None Master 2 None Master 4 None Master 2 None MAX Master 0 Master 2 MAX MAX Master 4 Master 2 MAX IDLE NSEQ NSEQ IDLE IDLE NSEQ NSEQ IDLE hready Figure 36-12. Parking on a Specific Master If PCTL bits are set to “use PARK/APARK” mode, then the slave port will park on the master designated by the PARK bits. The behavior here is the same as for the “park on last” mode with the exception that a specific master will be parked on instead of the last master to access the slave port. If the master designated by the PARK bits tries to access the slave port it will not pay an arbitration penalty while any other master will pay a one clock penalty. Figure 36-12 illustrates parking on a specific master. 36.5.4.4.5 Halt Mode If max_halt_request input is asserted, slave port will eventually halt all slave bus activity and go into halt mode, which is almost identical to low power park mode. HLP bit in GPCR controls the priority level of max_halt_request in arbitration algorithm. If HLP bit is cleared, then max_halt_request will have the highest priority of any master and will gain control of the slave port at the next arbitration point (most likely the next bus cycle, unless current master is running a locked or fixed length burst transfer). If HLP bit is set, then the slave port will wait until no masters are actively making requests before moving to halt mode. Regardless of HLP bit state, once slave port has gone into halt mode as a result of max_halt_request being asserted, it will remain in halt mode until max_halt_request is negated, regardless of the priority level of any masters that may make requests. In halt mode no master is selected to own the slave port so all the outputs of the slave port are set to 0. 36.6 Initialization/Application Information No initialization is required by or for MAX. Hardware reset ensures all register bits used by MAX are properly initialized. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-25 Multi-Layer AHB Crossbar Switch (MAX) 36.7 Interface MAX main goal is to increase overall system performance by allowing multiple masters to communicate in parallel with multiple slaves. In order to maximize data throughput, it is essential to keep arbitration delays to a minimum. This section examines data throughput from the point of view of masters and slaves, detailing when MAX will stall the masters or insert bubbles on the slave side. Master accesses will receive one of four responses from MAX. They will either be terminated, taken, stalled or responded to an error. 36.7.1 Master Ports Master accesses will receive one of four responses from the MAX. They will either be terminated, taken, stalled or responded to with an error. Terminated Accesses: A master access will be terminated if the transfer type is IDLE. MAX will terminate the access and it will not be allowed to pass through the MAX. Taken Accesses: A master access will be taken if the transfer type is non IDLE and the slave port to which the access decodes is either currently servicing the master or is parked on the master. In this case MAX will be completely transparent and the master’s access will be immediately seen on the slave bus and no arbitration delays will be incurred. Stalled Accesses: A master access will be stalled if transfer type is non IDLE and access decodes to a slave port that is busy serving another master, parked on another master or is in low power park mode. MAX will indicate to the master that address phase of the access has been taken but will then queue the access to appropriate slave port to enter into arbitration for access to that slave port. If the slave port is currently parked on another master or is in low power park mode and no other master is requesting access to it, then only one clock of arbitration will be incurred. If the slave port is currently serving another master of a lower priority and the master has a higher priority than all other requesting masters then the master will gain control over the slave port as soon as the data phase of the current access is completed (burst and locked transfers excluded). If the slave port is currently servicing another master of a higher priority then the master will gain control of the slave port once the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. Error Response Terminated Accesses: A master access will be responded to with an error if the transfer type is non IDLE and the access decodes to a location not occupied by a slave port. This is the only time the MAX will respond with an error response. All other error responses received by the master are result of error responses on the slave ports being passed through MAX. 36.7.2 Slave Ports The goal of MAX with respect to the slave ports is to keep them 100% saturated when masters are actively making requests. In order to do this, MAX must not insert any bubbles onto the slave bus unless absolutely MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-26 Freescale Semiconductor Multi-Layer AHB Crossbar Switch (MAX) necessary. There is only one instance when MAX will force a bubble onto the slave bus when a master is actively making a request. This occurs when a higher priority master has control of the slave port and is running single clock (zero wait state) access while a lower priority master is stalled waiting for control of the slave port. When higher priority master either leaves the slave port or runs an IDLE cycle to the slave port, MAX will take control of the slave bus and run a single IDLE cycle before giving the slave port to the lower priority master that was waiting for control of the slave port. The only other times, MAX will have control of the slave port is when MAX is halting or when no masters are making access requests to the slave port and the MAX is forced to either park the slave port on a specific master or put the slave port into low power park mode. In most instances when MAX has control of slave port, it will indicate IDLE for the transfer type, negate all control signals and indicate ownership of the slave bus via the hmaster encoding of 4’b0000. One exception to this rule is when a master running locked cycles has left the slave port but continues to run locked cycles. In this case, MAX will control the slave port and will indicate IDLE for the transfer type but it will not affect any other signals. NOTE When a master runs a locked cycle through the MAX, master will be guaranteed ownership of all slave ports it accesses while running locked cycles for one cycle beyond when the master finishes running locked cycles. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 36-27 Multi-Layer AHB Crossbar Switch (MAX) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 36-28 Freescale Semiconductor Chapter 37 Direct Memory Access Controller (DMAC) The Direct Memory Access Controller (DMAC) of i.MX27 device provides 16 DMA channels supporting linear memory, 2D memory and FIFO transfers to provide support for a wide variety of DMA operations. Figure 37-1 shows a simplified block diagram of the DMAC. AHB Bus AHB Crossbar Switch (MAX) IP Bus AHB Bus DMA IP Bus DMA_REQ[63:0], DMA_ACK, UART I2S IP Bus AIPI CSI CSPI AHB Figure 37-1. Block Diagram of DMAC 37.1 • • • • • • • • • • • Features Sixteen channels support linear memory, 2D Memory, FIFO for both source and destination. DMA chaining for variable length buffer exchanges and high allowable interrupt latency requirement. Increment, decrement, and no-change support for source and destination addresses. Each channel is configurable to respond to any of the 64 DMA request signals. Supports 8, 16, or 32-bit FIFO and memory port size data transfers. DMA burst length configurable up to a maximum of 16 words, 32 half-words, or 64 bytes for each channel. Bus utilization control for the channel that is not trigger by a DMA request. Burst time-out errors terminates the DMA cycle when the burst cannot be completed within a programmed time count. Buffer overflow error terminates the DMA cycle when the internal buffer receives more than 64 bytes of data. Transfer error terminates the DMA cycle when a transfer error is detected during a DMA burst. DMA request time-out errors are generated for channels that are triggered by DMA requests to interrupt the CPU when a DMA burst does not start on that channel after a programmed time count. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-1 Direct Memory Access Controller (DMAC) • • • • • Interrupts are provided to the interrupt controller (and subsequently to the core) on bulk data transfer complete or transfer error. Each peripheral that supports DMA transfer generates a DMA_REQ signal to the DMA controller, assuming that each FIFO has a unique system address and generates a dedicated dma_req signal to the DMA controller. For example, a USB device with 8 end-points has 8 DMA request signals to the DMA if they all support DMA transfer. DMA controller provides an acknowledge signal to the peripheral after DMA burst is complete. This signal is sometimes used by the peripheral to clear the status bits. Repeat data transfer function supports automatic USB–host–USB device bulk/iso data stream transfer. Dedicated external DMA request signal. DMA has a FIFO for storing data read from AHB Bus. This FIFO is 32-bits wide and 16 deep to store up to 64 bytes. This FIFO is common for all channels and is used by the active channel. 37.2 DMA Request and Acknowledge Initiation of a DMA cycle can be done through software control (setting CEN = 1 and REN =0 in channel control register) or by DMA request assertion (setting CEN = 1 and REN =1 in channel control register). A DMA cycle consists of a number of DMA bursts depending on burst length and count register settings. Table 37-1 contains the DMA request map. 37.2.1 DMA Request A typical DMA request is an active low signal asserted by the peripheral. The sampling of this signal is done when REN and CEN bits in Channel Control register are set and there is no other ongoing DMA transfer on the AHB bus. There is no configurable priority associated with any request. However, the 16 channels have a fixed priority; channel 15 has the highest priority and channel 0 has the lowest priority. The priority of any request depends on the channel number to which the request is mapped (through Request Source Select register settings). DMAC does not store DMA request inputs, it processes on the highest priority channel request out of the asserted channel requests (when no other transfer is taking place). A peripheral must keep the request asserted until it is serviced by DMAC. There are 64 input DMA request signals available. 1 DMA request will initiate 1 DMA burst. Once a DMA burst has started, DMA request can be de-asserted by the peripheral. The peripheral should de-assert the DMA request based on data read from or written into it. If the request is not de-asserted till the end of the DMA burst, it can initiate another DMA burst. 37.2.2 External DMA Request and Grant After assertion of External DMA Request, the DMA burst will start when the corresponding DMA channel becomes the highest priority channel. External DMA Request should be kept asserted until it is serviced by the DMAC. One External request will initiate at least one DMA burst. The output External Grant signal from the DMAC is an active-low signal. This signal will be asserted during the time when a DMA burst is ongoing for an External DMA Request, when the following conditions are true: MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-2 Freescale Semiconductor Direct Memory Access Controller (DMAC) — The DMA channel for which the DMA burst is ongoing has requested source as external DMA Request (as per RSSR settings). — REN and CEN bit of this channel are set — External DMA Request is asserted Once the grant is asserted, External DMA Request will not be sampled until completion of the DMA burst. The priority of external request will become low for the next consecutive burst, if another DMA request signal is asserted. The waveforms are shown for the worst case, that is, smallest burst (1 byte read/write). Minimum and maximum timings for External request and External grant signal are present in the data sheet. Figure 37-2 shows the minimum time for which the External Grant signal remains asserted if External DMA request is de-asserted immediately after sensing grant signal active. Ext_DMAReq Ext_DMAGrant tmin_assert Figure 37-2. Assertion of DMA External Grant Signal Figure 37-3 shows the safe max time for which External DMA request can be kept asserted, after sensing grant signal active as if a new burst is not initiated. Ext_DMAReq Ext_DMAGrant tmax_req_assert Data read from External device Data written to External device tmax_read tmax_write NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform. Figure 37-3. Safe Maximum Timings for External Request De-Assertion 37.3 DMA Request Mapping Table 37-1 shows requests connection from various modules in the i.MX27 to DMA Request input of DMAC Table 37-1. DMA Request Mapping DMA Request Number DMA_REQ[63:38] DMA_REQ[37] Module Assigned Reserved EMI Channel Name Reserved NFC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-3 Direct Memory Access Controller (DMAC) Table 37-1. DMA Request Mapping (continued) DMA Request Number DMA_REQ[36] DMA_REQ[35] DMA_REQ[34] DMA_REQ[33] DMA_REQ[32] DMA_REQ[31] DMA_REQ[30] DMA_REQ[29] DMA_REQ[28] DMA_REQ[27] DMA_REQ[26] DMA_REQ[25] DMA_REQ[24] DMA_REQ[23] DMA_REQ[22] DMA_REQ[21] DMA_REQ[20] DMA_REQ[19] DMA_REQ[18] DMA_REQ[17] DMA_REQ[16] DMA_REQ[15] DMA_REQ[14] DMA_REQ[13] DMA_REQ[12] DMA_REQ[11] DMA_REQ[10] DMA_REQ[9] DMA_REQ[8] DMA_REQ[7] DMA_REQ[6] DMA_REQ[5] DMA_REQ[4] Module Assigned SDHC3 UART6 UART6 UART5 UART5 CSI CSI ATA ATA UART1 UART1 UART2 UART2 UART3 UART3 UART4 UART4 CSPI1 CSPI1 CSPI2 CSPI2 SSI1 SSI1 SSI1 SSI1 SSI2 SSI2 SSI2 SSI2 SDHC1 SDHC2 Reserved MSHC Channel Name SDHC3 UART6_RX_FIFO UART6_TX_FIFO UART5_RX_FIFO UART5_TX_FIFO CSI_RX_FIFO CSI_STAT_FIFO ATA_RCV_FIFO ATA_TX_FIFO UART1_TX_FIFO UART1_RX_FIFO UART2_TX_FIFO UART2_RX_FIFO UART3_TX_FIFO UART3_RX_FIFO UART4_TX_FIFO UART4_RX_FIFO CSPI1_TX_FIFO CSPI1_RX_FIFO CSPI2_TX_FIFO CSPI2_RX_FIFO SSI1_TX1_FIFO SSI1_RX1_FIFO SSI1_TX0_FIFO SSI1_RX0_FIFO SSI2_TX1_FIFO SSI2_RX1_FIFO SSI2_TX0_FIFO SSI2_RX0_FIFO SDHC1 SDHC2 Reserved MSHC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-4 Freescale Semiconductor Direct Memory Access Controller (DMAC) Table 37-1. DMA Request Mapping (continued) DMA Request Number DMA_REQ[3] DMA_REQ[2] DMA_REQ[1] DMA_REQ[0] Module Assigned External DMA request CSPI3 CSPI3 Reserved Channel Name — CSPI3_TX_FIFO CSPI3_RX_FIFO — 37.4 Memory Map and Register Definition The DMAC module contains 158 32-bit registers. The registers are divided into four groups according to the register functions as follows: • General registers for all functional blocks (see Section 37.4.3, “General Registers”). • 2D memory registers to control display width and x and y of the window (see Section 37.4.4, “2D Memory Registers (A and B)”). • Channel registers to control and configure channels 0–15 (see Section 37.4.5, “Channel Registers”). • Test Registers. The base address of DMA Controller for i.MX27 is 0x10001000. Table 37-4 summarizes the registers and offset addresses. Section 37.4, “Memory Map and Register Definition” provides detailed descriptions of the DMAC registers. 37.4.1 DMAC Memory Map Table 37-2. DMAC Memory Map Address Use DMA Control Register DMA Interrupt Status Register DMA Interrupt Mask Register DMA Burst Time-Out Status Register DMA Request Time-Out Status Register DMA Transfer Error Status Register DMA Buffer Overflow Status Register DMA Burst Time-Out Control Register W-Size Register A W-Size Register B X-Size Register A X-Size Register B Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 37.4.3.1/37-10 37.4.3.2/37-11 37.4.3.3/37-12 37.4.3.4/37-13 37.4.3.5/37-13 37.4.3.6/37-14 37.4.3.7/37-15 37.4.3.8/37-15 37.4.4.1/37-17 37.4.4.2/37-18 Table 37-2 shows the DMAC memory map. 0x1000_1000 (DCR) 0x1000_1004 (DISR) 0x1000_1008 (DIMR) 0x1000_100C (DBTOSR) 0x1000_1010 (DRTOSR) 0x1000_1014 (DSESR) 0x1000_1018 (DBOSR) 0x1000_101C (DBTOCR) 0x1000_1040 (WSRA) 0x1000_104C (WSRB) 0x1000_1044 (XSRA) 0x1000_1050 (XSRB) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-5 Direct Memory Access Controller (DMAC) Table 37-2. DMAC Memory Map (continued) Address 0x1000_1048 (YSRA) 0x1000_1054 (YSRB) 0x1000_1080 (SAR0) – 0x1000_1440 (SAR15) 0x1000_1084 (DAR0) – 0x1000_1444 (DAR15) 0x1000_1088 (CNTR0) – 0x1000_1448 (CNTR15) 0x1000_108C (CCR0) – 0x1000_144C (CCR15) 0x1000_1090 (RSSR0) – 0x1000_1450 (RSSR15) 0x1000_1094 (BLR0) – 0x1000_1454 (BLR15) 0x1000_1098 (RTOR0) – 0x1000_1458 (RTOR15)1 0x1000_1098 (BUCR0) – 0x1000_1458 (BUCR15)2 0x1000_109C (CCNR0) – 0x1000_145C (CCNR15) 1 2 Use Y-Size Register A Y-Size Register B Channel 0 Source Address Register – Channel 15 Source Address Register Channel 0 Destination Address Register – Channel 15Destination Address Register Channel 0 Count Register – Channel 15 Count Register Channel 0 Control Register – Channel 15 Control Register Channel 0 Request Source Select Register – Channel 15 Request Source Select Register Channel 0 Burst Length Register – Channel 15Burst Length Register Channel 0 Request Time-Out Register/ – Channel 15 Request Time-Out Register/ Channel 0 Bus Utilization Control Register – Channel 15 Bus Utilization Control Register Channel 0 Channel Counter Register – Channel 15Channel Counter Register Access R/W R/W Reset Value 0x0000_0000 0x0000_0000 Section/Page 37.4.4.3/37-19 37.4.5.1/37-20 R/W 0x0000_0000 37.4.5.2/37-20 R/W 0x0000_0000 37.4.5.3/37-21 R/W 0x0000_0000 37.4.5.4/37-22 R/W 0x0000_0000 37.4.5.5/37-25 R/W 0x0000_0000 37.4.5.6/37-26 R/W 0x0000_0000 0x0000_0000 37.4.5.7/37-26 R/W 0x0000_0000 0x0000_0000 37.4.5.8/37-27 R/W 0x0000_0000 37.4.5.9/37-28 The RTOR registers use the same memory addresses as the BUCR registers. he BUCR registers use the same memory addresses as the RTOR registers. 37.4.2 Register Summary Figure 37-4 shows the key to the register fields, and Table 37-3 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 37-4. Key to Register Fields MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-6 Freescale Semiconductor Direct Memory Access Controller (DMAC) Table 37-3. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 37-4 shows the DMAC register summary. Table 37-4. DMAC Register Summary Name 0x1000_1000 (DCR) R W R W 0x1000_1004 (DISR) R W R W1 C CH1 CH1 CH1 CH1 CH1 CH1 CH9 CH8 CH7 5 4 3 2 1 0 W1 C W1 C W1 C W1 C W1 C W1 C W1 C W1 C W1 C CH 6 W1 C CH5 CH4 CH3 CH2 CH1 CH0 W1 C W1 C W1 C W1 C W1 C W1 C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA M 0 0 DRS DEN T 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-7 Direct Memory Access Controller (DMAC) Table 37-4. DMAC Register Summary (continued) Name 0x1000_1008 (DIMR) R W R W 0x1000_100C (DBTOSR) R W R W1 C 0x1000_1010 (DRTOSR) R W R W1 C 0x1000_1014 (DSESR) R W R W1 C 0x1000_1018 (DBOSR) R W R W1 C 0x1000_101C (DBTOCR) R W R W EN CNT [14: 0] CH1 CH1 CH1 CH1 CH1 CH1 CH9 CH8 CH7 5 4 3 2 1 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH 6 W1 C 0 CH5 CH4 CH3 CH2 CH1 CH0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH1 CH1 CH1 CH1 CH1 CH1 CH9 CH8 CH7 5 4 3 2 1 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH 6 W1 C 0 CH5 CH4 CH3 CH2 CH1 CH0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH1 CH1 CH1 CH1 CH1 CH1 CH9 CH8 CH7 5 4 3 2 1 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH 6 W1 C 0 CH5 CH4 CH3 CH2 CH1 CH0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH1 CH1 CH1 CH1 CH1 CH1 CH9 CH8 CH7 5 4 3 2 1 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH 6 W1 C 0 CH5 CH4 CH3 CH2 CH1 CH0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 W1 C 0 CH1 CH1 CH1 CH1 CH1 CH1 CH9 CH8 CH7 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 CH 6 0 CH5 CH4 CH3 CH2 CH1 CH0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-8 Freescale Semiconductor Direct Memory Access Controller (DMAC) Table 37-4. DMAC Register Summary (continued) Name 0x1000_1040 (WSRA) 0x1000_104C (WSRB) R W R WS [15: 0] W 0x1000_1044 (XSRA) 0x1000_1050 (XSRB) R W R XS [15: 0] W 0x1000_1048 (YSRA) 0x1000_1054 (YSRB) R W R YS [15: 0] W 0x1000_1080 (SAR0) – 0x1000_1440 (SAR15) 0x1000_1084 (DAR0) – 0x1000_1444 (DAR15) 0x1000_1088 (CNTR0) – 0x1000_1448 (CNTR15) 0x1000_108C (CCR0) – 0x1000_144C (CCR15) R SA [31: 16] W R SA [15: 0] W R DA [31: 16] W R DA [15: 0] W R W R CNT [15: 0] W R W R W 0 ACR PT DMOD SMOD MDI R MS EL 0 DSIZ SSIZ REN RPT FRC CEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT [23: 16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-9 Direct Memory Access Controller (DMAC) Table 37-4. DMAC Register Summary (continued) Name 0x1000_1090 (RSSR0) – 0x1000_1450 (RSSR15) R W R W 0x1000_1094 (BLR0) – 0x1000_1454 (BLR15)) 0x1000_1098 (RTOR0) – 0x1000_1458 (RTOR15)) 0x1000_1098 (BUCR0) – 0x1000_1458 (BUCR15)) 0x1000_109C (CCNR0) – 0x1000_145C (CCNR15) R W R W R W R EN W R W R BU_CNT [15: 0] W R W R W CCNR [15: 0] 0 0 0 0 0 0 0 0 CCNR[23:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK PSC CNT [12: 0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BL [5: 0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSS [5: 0] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37.4.3 37.4.3.1 General Registers DMA Control Register (DCR) The DMA Control Register (DCR) controls the input of the system clock, enabling, disabling, and resetting of the DMA module. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-10 Freescale Semiconductor Direct Memory Access Controller (DMAC) 0x1000_1000 (DCR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 DAM 0 DEN DRST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-5. DMA Control Register (DCR) Table 37-5. DMA Control Register Field Descriptions Field 31–3 2 DAM 1 DRST Description Reserved. These bits are reserved and should read 0. DMA Access Mode. Specifies user or privileged access to be performed by DMA. 0 Privileged access 1 User access DMA Soft Reset. Generates a 3-cycle reset pulse that resets the entire DMA module, bringing the module to its reset condition. DRST always reads 0. 0 No effect 1 Generates a 3-cycle reset pulse DMA Enable. Enables/Disables the system clock to the DMA module. However the bit is not used for clock gating in i.MX27 as the clock is controlled from CRM in the i.MX27 processor. 0 DMA disable 1 DMA enable 0 DEN 37.4.3.2 DMA Interrupt Status Register (DISR) The DISR contains interrupt status of each channel in the DMAC. The status bit is set whenever the corresponding DMA channel data transfer is complete. When any bit in DISR is set and the corresponding bit in the interrupt mask register is cleared, dma_int is asserted to the interrupt controller (AITC). When an interrupt occurs, an interrupt service routine must check DISR to determine the interrupting channel. Clear each bit by writing a value 1 to it. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-11 Direct Memory Access Controller (DMAC) 0x1000_1004 (DISR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 W w1c Reset 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 CH8 w1c 0 CH7 w1c 0 CH6 w1c 0 CH5 w1c 0 CH4 w1c 0 CH3 w1c 0 CH2 w1c 0 CH1 w1c 0 CH0 w1c 0 Figure 37-6. DMA Interrupt Status Register Table 37-6. DMA Interrupt Status Register Field Descriptions Field 31–16 15–0 CH15–CH0 Description Reserved. These bits are reserved and should read 0. Channel 15 to 0 Interrupt Status. Indicates interrupt status for each DMA channel. 0 No interrupt 1 Interrupt is pending 37.4.3.3 DMA Interrupt Mask Register (DIMR) DIMR masks both normal interrupts and error interrupts generated by the corresponding channel. There is one control bit for each channel. When an interrupt is masked, the interrupt controller does not generate an interrupt request to the AITC, however the status of the interrupt can be observed from the interrupt status register, burst time-out status register, request time-out status register, or the transfer error status register. At reset, all the interrupts are masked and all the bits in this register are set to 1. 0x1000_1008 (DIMR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Figure 37-7. DMA Interrupt Status Register (DIMR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-12 Freescale Semiconductor Direct Memory Access Controller (DMAC) Table 37-7. DMA Interrupt Mask Register Field Descriptions Field 31–16 15–0 CH15–CH0 Description Reserved. These bits are reserved and should read 0. Channel 15 to 0 Interrupt Mask. Controls the interrupts for each DMA channel. 0 Enables interrupts 1 Disables interrupts 37.4.3.4 DMA Burst Time-Out Status Register (DBTOSR) A burst time-out is set when a DMA burst cannot be completed within the number of clock cycles specified in the DMA Burst Time-Out Control Register (DBTOCR) of the channel. When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA Error interrupt is asserted to the interrupt controller (AITC). DBTOSR indicates the channel, if any, that is currently being serviced and whether a burst time-out was detected. Each bit is cleared by writing 1 to it. 0x1000_100C (DBTOSR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 W w1c Reset 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 CH8 w1c 0 CH7 w1c 0 CH6 w1c 0 CH5 w1c 0 CH4 w1c 0 CH3 w1c 0 CH2 w1c 0 CH1 w1c 0 CH0 w1c 0 Figure 37-8. DMA Burst Time-Out Status Register (DBTOSR) Table 37-8. DMA Burst Time-Out Status Register Description Field 31–16 15–0 CH15–CH0 Description Reserved. These bits are reserved and should read 0. Channel 15 to 0. Indicates the burst time-out status of each DMA channel. 0 No burst time-out 1 Burst time-out 37.4.3.5 DMA Request Time-Out Status Register (DRTOSR) A DMA request time-out is set when there is no DMA burst started on the channel (when REN =1, either due to no DMA Request or DMA channel not acquiring the bus) within the pre-assigned number of clock cycles specified in the Request Time-Out control register (RTOR) for the channel. When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA Error Interrupt is asserted to the interrupt controller (AITC). DRTOSR indicates the enabled channel, if any, that detected a DMA request time-out. Clear each bit by writing 1 to it. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-13 Direct Memory Access Controller (DMAC) 0x1000_1010 (DRTOSR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 W w1c Reset 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 CH8 w1c 0 CH7 w1c 0 CH6 w1c 0 CH5 w1c 0 CH4 w1c 0 CH3 w1c 0 CH2 w1c 0 CH1 w1c 0 CH0 w1c 0 Figure 37-9. DMA Request Time-Out Status Register (DRTOSR) Table 37-9. DMA Request Time-Out Status Register Field Descriptions Field 31–16 15–0 CH15–CH0 Description Reserved. These bits are reserved and should read 0. Channel 15 to 0. Indicates the request time-out status of each DMA channel. 0 No DMA request time-out 1 DMA request time-out 37.4.3.6 DMA Transfer Error Status Register (DSESR) A DMA transfer error is set when DMA data transfer results in an error. When any bit is set in this register and the corresponding bit in the interrupt mask register is cleared, a DMA Error Interrupt is asserted to the interrupt controller (AITC). DSESR indicates the channel, if any, the detected transfer error during a DMA burst. Clear each bit by writing 1 to it. 0x1000_1014 (DSESR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 W w1c Reset 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 CH8 w1c 0 CH7 w1c 0 CH6 w1c 0 CH5 w1c 0 CH4 w1c 0 CH3 w1c 0 CH2 w1c 0 CH1 w1c 0 CH0 w1c 0 Figure 37-10. DMA Transfer Error Status Register (DSESR) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-14 Freescale Semiconductor Direct Memory Access Controller (DMAC) Table 37-10. DMA Transfer Error Status Register Field Descriptions Field 31–16 15–0 CH15–CH0 Description Reserved. These bits are reserved and should read 0. Channel 15 to 0. Indicates the DMA transfer error status of each DMA channel. 0 No transfer error 1 Transfer error 37.4.3.7 DMA Buffer Overflow Status Register (DBOSR) The DBOSR indicates whether DMA Controller’s internal FIFO buffer overflowed during a data transfer. Before a channel can be enabled for DMA, the corresponding bit in this register must be cleared. When any bit in this register is set and the corresponding bit in the interrupt mask register is cleared, a DMA Error Interrupt is asserted to the interrupt controller (AITC). 0x1000_1018 (DBOSR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 W w1c Reset 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 w1c 0 CH8 w1c 0 CH7 w1c 0 CH6 w1c 0 CH5 w1c 0 CH4 w1c 0 CH3 w1c 0 CH2 w1c 0 CH1 w1c 0 CH0 w1c 0 Figure 37-11. DMA Buffer Overflow Status Register (DBOSR) Table 37-11. DMA Buffer Overflow Status Register Field Descriptions Field 31–16 15–0 CH15–CH0 Description Reserved. These bits are reserved and should read 0. Channel 15 to 0. Indicates the buffer overflow error status of each DMA channel. 0 No buffer overflow occurred 1 Buffer overflow occurred 37.4.3.8 DMA Burst Time-Out Control Register (DBTOCR) This register sets the DMA burst time-out (common for all DMA channels), so that DMAC can release the AHB and IP buses in the event of an error. An internal counter starts counting when a DMA burst starts, and resets to zero when the burst is completed. When the counter reaches the count value set in the register, it asserts an interrupt and sets the corresponding error bit in the DMA Burst Time-Out Status Register (DBTOSR). The system clock is used as the input clock to the counter. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-15 Direct Memory Access Controller (DMAC) 0x1000_101C (DBTOCR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT Figure 37-12. DMA Burst Time-Out Control Register (DBTOCR) Table 37-12. DMA Burst Time-Out Control Register Field Descriptions Field 31–16 15 EN 14–0 CNT Description Reserved. These bits are reserved and should read 0. Enable. Enables/Disables the burst time-out. 0 Disables burst time-out 1 Enables burst time-out Count. This count is the number of system clock cycles to be used for the time-out value 37.4.4 2D Memory Registers (A and B) There are two sets of 2D memory registers that allow every channel to select any register set to define the respective 2D memory size. Each data transfer performed by DMA is strictly as per Source and destination sizes specified in Channel Control Register (this is valid for Linear memory, 2D memory, and FIFO mode). In the case of a transfer to/from 2D Memory, the Channel Count register value is ignored and number of bytes transferred is equal to 2D Memory size. 2D Memory Size is computed as follows. Size (in number of bytes) = No of bytes per row (value in X register) * No. of rows (Value in Y Register) At a time any number of channels can be programmed for 2D Memory (even all 16 Channels). 2D Memory can be selected for a channel as source or destination or even both. In the last condition, only selected set of 2D Registers (selected as per MSEL bit setting in the Channel Control Register) is used for both source and destination. The advantage of having 2 sets of registers, which are usable by all DMA channels, is that this allows the developer to have two different window size settings for 2D memory. Each channel can be programmed to use any one of the 2 settings. In Figure 37-13, shaded portion shows the data transfer zone in the 2D memory for X= 4, Y = 4, and W (display size) = 6 with memory increment option and starting address 0x001. In Figure 37-14, shaded portion shows the data transfer zone in 2D memory for X= 4, Y = 5, and W = 6 with memory decrement option and starting address as 0x11C. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-16 Freescale Semiconductor Direct Memory Access Controller (DMAC) W Starting Address (SSA) X 001 007 Y 00D 013 002 008 00E 014 003 009 00F 015 004 00A 010 016 005 00B 011 017 006 00C 012 018 Figure 37-13. 2D Memory Increment Diagram W X 116 110 10A 104 0FE 117 111 10B 105 0FF 118 112 10C 106 100 119 113 10D 107 101 11A 114 10E 108 102 11B 115 Y 10F 109 103 11C Starting Address Figure 37-14. 2D Memory Decrement Diagram 37.4.4.1 W-Size Registers (WSRA, WSRB) The W-Size registers (WSRA, WSRB) define the number of bytes that make up the display width. This allows the DMAC to calculate the next starting address of another row by adding the source/destination address to the W-Size register content. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-17 Direct Memory Access Controller (DMAC) 0x1000_1040 (WSRA) 0x1000_104C (WSRB) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R WS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-15. W-Size Registers (WSRA, WSRB) Table 37-13. W-Size Registers Field Descriptions Field 31–16 15–0 WS Description Reserved. These bits are reserved and should read 0. W-Size. Contains the number of bytes that makes up the display width. W and X must follow the relation: W ≥ X W and Access Size must follow the relation: W ≥ access size. Wsize needs to be a multiple of Source or Destination Access size whichever is a 2D memory. 37.4.4.2 X-Size Registers (XSRA, XSRB) X-Size registers (XSRA, XSRB) contain the number of bytes per row of the window. The value of this register is used by the DMA controller to determine when to jump to the next row. 0x1000_1044 (XSRA) 0x1000_1050 (XSRB) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-16. X-Size Registers (XSRA, XSRB) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-18 Freescale Semiconductor Direct Memory Access Controller (DMAC) Table 37-14. X-Size Registers Field Descriptions Field 31–16 15–0 XS Description Reserved. These bits are reserved and should read 0. X-Size. Contains the number of bytes per row that defines the X-Size of 2D memory. The value in the X Register should follow the following 2 rules: • X ≥ Burst Length (BL) • X/ BL = Whole number. 37.4.4.3 Y-Size Registers (YSRA, YSRB) The Y-Size registers (YSRA, YSRB) contain the number of rows in the 2D memory window. This setting is used by the DMA controller to calculate the total size of transfer. 0x1000_1048 (YSRA) 0x1000_1054 (YSRB) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R YS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-17. Y Size Registers (YSRA, YSRB) Table 37-15. Y-Size Registers Field Descriptions Field 31–16 15–0 YS Description Reserved. These bits are reserved and should read 0. Y-Size. Contains the number of rows that makes up the 2D memory window. 37.4.5 Channel Registers Channels 0 to 15 supports linear memory, 2D memory, FIFO transfer. The DMA request (dma_req [63:0]) signals do not have any configurable priority. The only priority available is the priority that is defined for each channel: channel 15 has the highest priority and channel 0 has the lowest priority. The channel priority is used only when more than one request occurs at the same time. Otherwise, channels are serviced on a first come, first serve basis. Each channel generates a normal interrupt to the interrupt handler when the data count reaches the selected value. Each channel generates an error interrupt to the interrupt handler when any of the following conditions exist: MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-19 Direct Memory Access Controller (DMAC) • • • • A DMA request time-out is true A DMA burst time-out is true during a burst cycle The internal buffer overflows during a burst cycle A transfer error acknowledge is asserted during a burst cycle 37.4.5.1 Channel Source Address Registers (SAR0–SAR15) Each of the SAR contains the DMA cycle source address. The implementation must ensure that SAR’s value is stored internally before use, to allow software to modify the register value for DMA chaining (see Section 37.5, “DMA Chaining). The value should be stored when CEN bit is set or at the end of the transfer when RPT bit is found set (before initiating the new transfer). If the memory direction bit (MDIR) in the channel control register (CCR) is clear (indicating a memory address increment), then SAR contains memory block start address. If MDIR is set (indicating a memory address decrement), then SAR contains the memory block end address. 0x1000_1080 (SAR0) – 0x1000_1440 (SAR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R SA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-18. Channel Source Address Register (SAR0–SAR15) Table 37-16. Channel Source Address Register Field Description Field 31–0 SA Description Source Address. Contains source address from where data is read during a DMA transfer. DMA will not perform misaligned accesses. That is to say, for 32-bit transfers, the lower two bits of this address are ignored. 8-bit accesses begins from the address in this register. Software must take care if the system does not support non-word aligned accesses in this case. 37.4.5.2 Destination Address Registers (DAR0–DAR15) Each of the DAR contains the DMA cycle destination address. The implementation needs to ensure that DAR’s value is stored internally before use, to allow software to modify the register value for DMA Chaining (see Section 37.5, “DMA Chaining”). The value should be stored when CEN bit is set or at the end of the transfer when RPT bit is found set (before initiating the new transfer). If the memory direction bit (MDIR) in the channel control register (CCR) is clear (indicating a memory address increment), then MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-20 Freescale Semiconductor Direct Memory Access Controller (DMAC) DAR contains memory block start address. If MDIR is set (indicating a memory address decrement), then DAR contains the memory block end address. 0x1000_1084 (DAR0) – 0x1000_1444 (DAR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R DA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-19. Channel Destination Address Registers (DAR0–DAR15) Table 37-17. Channel Destination Address Registers Field Descriptions Field 31–0 DA Description Destination Address. Contains destination address to which data is written to during a DMA transfer. DMAC will not perform misaligned accesses. That is, for a 32-bit transfers, the lower two bits of this address are ignored. 8-bit accesses begin from the address in this register. Software must take care if the system does not support non-word aligned accesses in this case. 37.4.5.3 Channel Count Registers (CNTR0–CNTR15) The DEN bit in DCR should be set to enable writes to this register. The implementation needs to ensure that CNTR’s value is stored internally before use, to allow software to modify the register value for DMA Chaining (see Section 37.5, “DMA Chaining”). The value should be stored in an Internal Count Register when CEN bit is set or at the end of the transfer when RPT bit is found set (before initiating new transfer). Each of the CNTR contain the number of bytes of data to be transferred. There is an internal counter that counts up (number of bytes: 4 for word, 2 for half-word and 1 for byte) for every DMA transfer. The internal counter is compared with the Internal Count Register after every transfer. When the counter value matches with the register value, the channel is disabled until the CEN bit is cleared and set again, or the RPT bit in the corresponding channel control register is set to 1. The internal counter is reset to 0 when the channel is enabled again. The length of the last DMA burst can be shorter than the regular burst length specified in the burst length register. However, when data is transferred out from an I/O FIFO and the last burst is less than BL, the I/O device must generate a DMA request for the last transfer. When data is transferred to an I/O FIFO and the last burst is less than BL, only the remaining number of data is transferred. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-21 Direct Memory Access Controller (DMAC) 0x1000_1088 (CNTR0) – 0x1000_1448 (CNTR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-20. Channel Count Registers (CNTR0–CNTR15) Table 37-18. Channel Count Registers Field Descriptions Field 31–24 23–0 CNT Description Reserved. These bits are reserved and should read 0. Count. Contains the number of bytes of data to be transferred during a DMA cycle. 37.4.5.4 Channel Control Registers (CCR0–CCR15) Each of the CCR controls and displays the status of that DMA channel operation. DMAC has the capability to perform burst transfers of byte and half word data types while SDRAM controller and EIM support is restricted to burst transfers of word (32-bit) data types. Therefore, while using the DMA in conjunction with SDRAM controller and EIM, ensure that all burst transfers to/from SDRAM controller and EIM are of word data types. This is configured in the DMA Channel Control Register. While choosing SDRAM memory as the source or destination address, set SDRAMC and EIM as a 32-bit port. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-22 Freescale Semiconductor Direct Memory Access Controller (DMAC) 0x1000_108C (CCR0) – 0x1000_144C (CCR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 ACR PT 0 DMOD 0 0 SMOD 0 0 MDIR 0 MSEL 0 0 DSIZ 0 0 SSIZ 0 REN 0 RPT 0 FRC 0 CEN 0 0 Figure 37-21. Channel Control Registers (CCR0–CCR15) Table 37-19. Channel Control Registers Field Descriptions Field 31–15 14 ACRPT Description Reserved. These bits are reserved and should read 0. Auto Clear RPT. This bit is to be sampled at the end of the transfer along with the RPT bit. When this bit and RPT are set, a new transfer is initiated and RPT is reset before issuing any interrupts. 0 Do not modify RPT 1 Reset RPT at end of current transfer. Destination Mode. Selects the destination transfer mode. 00 Linear memory 01 2D memory 10 FIFO 11 Reserved Source Mode. Selects the source transfer mode. 00 Linear memory 01 2D memory 10 FIFO 11 Reserved Memory Direction. Selects the memory address direction. Note: When address increment is chosen, data transfer starts from the values in SAR and DAR. When address decrement is chosen, data transfer will be done till the addresses mentioned in SAR and DAR, that is, no data read or write will be done at the address mentioned in SAR and DAR. 0 Memory address increment 1 Memory address decrement Memory Select. Selects 2D memory register set when source and/or destination is programmed to 2D memory mode. 0 2D memory register set A selected 1 2D memory register set B selected 13–12 DMOD 11–10 SMOD 9 MDIR 8 MSEL MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-23 Direct Memory Access Controller (DMAC) Table 37-19. Channel Control Registers Field Descriptions Field 7–6 DSIZ Description Destination Size. Selects the destination size of a data transfer. If number of bytes to be written is less than the DSIZ setting, then only that many bytes will be valid in the DMA write cycle to AHB. However all DMA write cycles to the destination will be of DSIZ size. DMA always writes data as per DSIZ in all modes, that is, Linear memory, 2D memory and FIFO mode. 00 32-bit destination port 01 8-bit destination port 10 16-bit destination port 11 Reserved Source Size. Selects the source size of data transfer. 1. SSIZ1:SSIZ0 always reads/writes 00 when source mode is programmed as end-of-burst enable FIFO, because end of burst operation only works for 32-bit FIFO. 21. If the number of bytes to be read is less than the SSIZ setting, then only that many bytes will be used by the DMA. However, all DMA read cycles to the source will be of “SSIZ” size. 32. DMA always reads data as per SSIZ in all modes, that is, EOBE mode, Linear memory, 2D memory and FIFO mode. 00 32-bit source port 01 8-bit source port 10 16-bit source port 11 Reserved Request Enable. Enables/Disables the DMA request signal. When REN bit is set, DMA burst is initiated by the dma_req signal from the I/O FIFO. When REN is cleared, DMA transfer is initiated by CEN. 0 Disables the DMA request signal (when the peripheral asserts a DMA request, no DMA transfer is triggered); DMA transfer is initiated by CEN only 1 Enables the DMA request signal (when the peripheral asserts a DMA request, a DMA transfer is triggered) Repeat. This is a status/control bit. Software has a priority and can write to this bit at any time. This bit Enables/ Disables the data transfer repeat function. When enabled and when the counter reaches the value set in Internal Count Register: a. Source address, Destination address and Count Register values are stored (reloaded) for the next DMA Burst. b. If ACRPT bit is set, RPT bit is cleared. c. Next DMA cycle is enabled. After this an interrupt is asserted, if the corresponding channel bit in the Interrupt Mask Register is cleared. Data transfer is carried out continuously until the channel is disabled or it completes the last DMA burst after RPT is cleared. The status information in this bit is that it gets cleared when ACRPT is set as described above. Note: Implementation must ensure that RPT bit is sampled only at the time the counter reaches the value in the Internal Count Register before asserting the interrupt. RPT bit should be allowed to be modified at all other times by the software (for example in the interrupt subroutine). 0 Disables repeat function 1 Enables repeat function 5–4 SSIZ 3 REN 2 RPT MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-24 Freescale Semiconductor Direct Memory Access Controller (DMAC) Table 37-19. Channel Control Registers Field Descriptions Field 1 FRC Description Force a DMA Cycle. Forces a DMA burst to occur when DMA cycle is software enabled or DMA Request is Enabled. When FRC bit is set, it will remain set till a DMA burst for this channel starts as per channel priority, and will get cleared after the DMA burst for the channel starts. When set, software will read this bit as’1’ till it gets cleared automatically or cleared by software. 0 No effect 1 Force DMA cycle DMA Channel Enable. Enables/Disables the DMA channel. Note: To re-program a particular channel after completion of a DMA cycle refer Section 37.8, “Application Note.” Note: Disabling CEN during an ongoing burst on the AHB will stop the burst in between the transfer 0 Disables the DMA channel 1 Enables the DMA channel 0 CEN 37.4.5.5 Channel Request Source Select Registers (RSSR0–RSSR15) Each of the 64-bit RSSR selects one of the 64 DMA request signals (DMA_REQ [63:0]) to initiate a DMA transfer for the corresponding channel. 0x1000_1090 (RSSR0) – 0x1000_1450 (RSSR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 RSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-22. Channel Request Source Select Registers (RSSR0–RSSR15) Table 37-20. Channel Request Source Select Registers Field Descriptions Field 31–6 5–0 RSSR Description Reserved. These bits are reserved and should read 0. Request Source Select. Selects 1 of the 64 dma_req signals that initiates DMA transfer cycle for the channel. 000000 select dma_req[0] 000001 select dma_req [1] ... 011111 select dma_req [31] .... 111111 select dma_req [63] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-25 Direct Memory Access Controller (DMAC) 37.4.5.6 Channel Burst Length Registers (BLR0–BLR15) The BLR controls burst length of a DMA cycle. For a FIFO channel setting, burst length is normally assigned according to FIFO size of the selected I/O device, or by FIFO level at which its dma_req signal is asserted. For example, when UART RxD FIFO is 12x8, and it asserts dma_req when it receives more than 8 bytes of data, BL is 8. When memory port size also is 8-bit, DMA burst is 8-byte read followed by 8-byte write. When memory port access size is smaller than I/O port access size, burst length of the byte write is doubled. For example, if I/O port is 32-bit and memory port is 16-bit, then burst length is set to 32. In this configuration, DMA performs 8 word burst reads and 16 half-word burst writes for I/O to memory transfer. When burst length is not programmed as a multiple of access sizes of source and destination, refer Section 37.9, “DMA Burst Termination” for behavior of DMA. 0x1000_1094 (BLR0) – 0x1000_1454 (BLR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 BL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-23. Channel Burst Length Registers (BLR0–BLR15) Table 37-21. Channel Burst Length Registers Field Descriptions Field 31–6 5–0 BL Description Reserved. These bits are reserved and should read 0. Burst Length. Contains the number of data bytes that are transferred in a DMA burst. 000000 64 bytes read follow 64 bytes write 000001 1byte read follow 1 byte write 000010 2 bytes read follow 2 bytes write .... 111111 63 bytes read follow 63 bytes write 37.4.5.7 Channel Request Time-Out Registers (RTOR0–RTOR15) RTOR set the time-out for DMA Request from the channel’s selected request source, which detects any discontinuity of data transfer. The request time-out takes effect only when the corresponding request enable (REN) bit in the Channel Control Register (CCR) is set. An Internal Request Time-out Counter starts counting when DMA channel is enabled and burst on that channel ends. Internal Request Time-out Counter is reset to zero when another burst for that channel starts. When counter reaches the count value set in this register, it asserts an interrupt (if it is not masked) and set its error bit in the DMA request MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-26 Freescale Semiconductor Direct Memory Access Controller (DMAC) time-out status register (RTOSR). The input clock of the counter is selectable either from the system clock (HCLK) or input crystal (CLK32K). Internal Request Time-out Counter will not generate an error status (or count) for the first burst of a DMA cycle. It can be programmed to count (and can generate an error status as described above) for all other bursts in the DMA cycle. NOTE This register shares the same address as the bus utilization control register. 0x1000_1098 (RTOR0) – 0x1000_1458 (RTOR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK PSC CNT Figure 37-24. Channel Request Time-Out Registers (RTOR0–RTOR15) Table 37-22. Channel Request Time-Out Registers Field Descriptions Field 31–16 15 EN 14 CLK 13 PSC 12–0 CNT Description Reserved. These bits are reserved and should read 0. Enable. Enables/Disables the DMA request time-out. 0 Disables DMA request time-out 1 Enables DMA request time-out Clock Source. Selects the counter of input clock source. 0 HCLK 1 32.768 kHz Prescaler Count. Sets the prescaler of input clock. 0 Divide by 1 1 Divide by 256 Request Time-Out Count. Contains time-out count down value for internal counter in number of clocks. This value remains unchanged through out the DMA cycle. 37.4.5.8 Channel Bus Utilization Control Registers (BUCR0–BUCR15) BUCR controls the bus utilization of an enabled channel when REN bit in Channel Control Register (CCR) is cleared. The channel does not request a DMA transfer until the internal bus_untilization_counter reaches MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-27 Direct Memory Access Controller (DMAC) the count value set in this register except for the very first burst. This counter is cleared when the channel burst is started. When this count value is set to zero, DMA carries on burst transfers one after another until it reaches the value set in Channel Count Register (CNTR). In this case, user must be careful not to violate the maximum bus request latency of other devices. NOTE The BUCR0–BUCR15 registers share the same address as the Channel Request Time-Out (RTOR0–RTOR15) Registers. 0x1000_1098 (BUCR0) – 0x1000_1458 (BUCR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BU_CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-25. Channel Bus Utilization Control Register (BUCR0–BUCR15) Table 37-23. Channel Bus Utilization Control Register Field Descriptions Field 31–16 15–0 BU_CNT Description Reserved. These bits are reserved and should read 0. Bus Utilization Clock Count. Sets the number of system clocks that must occur before the channel starts the next burst. 37.4.5.9 Channel Counter Registers (CCNR0–CCNR15) The CCNR indicates the number of bytes transferred for the channel. It is reset to zero after channel is enabled and keeps incrementing for each transfer during the DMA burst. This counter will retain its value after the channel is disabled, till it is enabled again. If RPT bit is found set at the end of last burst of the DMA cycle, this counter retains its value and will be reset to zero only at the start of another DMA burst, that is, the first burst of new DMA cycle. If a DMA channel is disabled before completion of DMA cycle, this counter will retain the value of the number of data transferred in that DMA cycle. When the peripheral responds with a error response during a DMA data transfer, CCNR value will not be increment for that AHB cycle as no data was transferred in that cycle. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-28 Freescale Semiconductor Direct Memory Access Controller (DMAC) 0x1000_109C (CCNR0) – 0x1000_145C (CCNR15) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 CCNR[23:16] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CCNR[15:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37-26. Channel Counter Register (CCNR0–CCNR15) Table 37-24. Channel Counter Register Field Descriptions Field 31–24 23–0 CCNR Description Reserved. These bits are reserved and should read 0. Channel Counter. Indicates the number of bytes transferred for the channel. 37.5 DMA Chaining DMA chaining refers to using the same DMA Channel to automatically transfer a second data buffer (possibly of a different length) between another two sets of Source and Destination addresses, with an increase in the allowable value of interrupt service time. This is possible because the ISR execution (that is, the setup for next transfer) can occur in parallel to the next buffer transfer from the DMA (when RPT bit is set). To achieve DMA Chaining: the SAR, DAR and CNTR for each Channel are double buffered internally. With this, the Host can update these three register values during an ongoing DMA Transfer for the same channel in preparation for the next DMA transfer. With the use of RPT and ACRPT bits, the second transfer can occur for different source, destination addresses and different amount of data. As an example, consider a Data Transfer of 14 Kbytes from memory to a FIFO using 4 Kbyte buffers. • Driver writes 4 Kbyte of data into buffer 1, sets source register to buffer 1 and count to 4 Kbyte, sets ACRPT, then enables the transfer. DMA hardware will immediately latch the registers and start the transfer. • Driver immediately writes 4 Kbyte of data into buffer 2, sets the same source register to buffer 2, count to 4 Kbyte, and sets the RPT bit. • Transfer of buffer 1 completes, DMA hardware samples the RPT bit, finds it set, latches the register (now set for buffer 2), clears the RPT bit because ACRPT is set, and starts the next transfer. • It then generates the 1st interrupt. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-29 Direct Memory Access Controller (DMAC) • • • • • • • • • • Driver ISR writes 4 Kbyte of new data to buffer 1, sets the source register to buffer 1 and count to 4 Kbyte, and sets the RPT bit again. Transfer of buffer 2 completes, DMA hardware samples RPT bit, finds it set, latches the registers (now set for buffer 1), clears the RPT bit because ACRPT is still set, and starts the next transfer. It then generates the 2nd interrupt. Driver ISR writes 2 Kbyte of new data to buffer 2, sets the source register to buffer 2 and count to 2 Kbyte, and sets the RPT bit again. Transfer of buffer 1 completes, DMA hardware samples the RPT bit, finds it set, latches the register (now set for buffer 2), clears the RPT bit because ACRPT is still set, and starts the next transfer. It then generates the 3rd interrupt. Driver ISR has no more data to send so does nothing. Transfer of buffer 2 completes, DMA hardware samples the RPT bit, finds it clear so it stops the transfer. It then generates the 4th interrupt. Driver ISR disables the DMA and the transfer is complete. 37.6 Special Cases of Burst Length and Access Size Settings DMA burst length should normally be programmed as a multiple of source and destination access sizes. The following sections discuss the behavior that occurs when burst length is not a multiple of access size. 37.6.1 Memory Increment The following are the possible adverse effects: 1. Unknown data can be written at some locations, however, there is no data loss. 2. Number of bytes transferred can be more than the count value set. These effects are explained in the examples below: Example 1: Source is Linear memory with access size of 1 byte. Destination is linear memory with access size of 2 bytes. Burst Length is programmed as 3 bytes with memory increment. Source Address Register: 0x0000_1000. Destination Address Reg: 0x0000_2000. For the first burst, DMA would read 3 bytes from addresses: 1000, 1001, and 1002. During the write cycle of first burst, DMA would write 2 bytes each at addresses 2000 and 2002. One extra memory location (0x2003) is written with unknown data from the DMA internal FIFO (8’h00 after hardware reset). Example 2: Source is Linear Memory with access size of 2 bytes. Destination is linear memory with access size of 2 bytes. Burst Length is programmed as 3 bytes with memory increment. Source Address Register: 0x0000_1000. Destination Address Reg: 0x0000_2000. For the first burst, DMA would read 2 bytes each from addresses 1000 and 1002. During the write cycle of first burst, DMA would write 2 bytes each at addresses 2000 and 2002. One extra data byte is transferred per burst. When programmed with a count of say 9 bytes, DMA would perform data transfer of 12 bytes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-30 Freescale Semiconductor Direct Memory Access Controller (DMAC) 37.6.2 Memory Decrement Possible Adverse Effects: 1. Unknown data can be written at some locations. In certain cases there can be data loss. Example: Source is linear memory with access size of 1 byte. Destination is linear memory with access size of 2 bytes. Burst Length is programmed as 3 bytes with memory decrement. Source Address Register: 0x0000_1000. Destination Address Reg: 0x0000_2000. For the first burst, DMA would read 3 bytes from addresses: 0FFD, 0FFE, and 0FFF. During write cycle of the first burst, DMA would write 2 bytes each at addresses 1FFC and 1FFE. An extra byte is written at the address 1FFF with unknown data from the DMA internal FIFO (8’h00 after hardware reset). For the second burst, DMA would read 3 bytes from the addresses: 0FFA, 0FFB, and 0FFC. During write cycle of the second burst, DMA would write 2 bytes each at addresses 1FFA and 1FFC. In this case data written at 1FFC and 1FFD in the first burst have been overwritten. Data written at 1FFD will be unknown data from the DMA internal FIFO (8’h00 after hardware reset). NOTE In the case of 2D Memory writing extra bytes would mean writing beyond the limits of X-Size programmed in a row. Similarly for linear memory, this can lead data overflowing the allocated buffer for DMA. 37.7 Special Cases When CCNR and CNTR Values Differ There are two combinations of events that can cause the values of CCNR and CNTR to differ. This situations are discussed in detail in the following sections. 37.7.1 CNTR Not A Multiple of Destination Access Size If CNTR register value is not a multiple of destination access size, then CCNR value will not match the value programmed in CNTR after completion of the DMA cycle for the channel. Table 37-25 illustrates the values of CCNR with different combinations of source and destination access sizes when CNTR = 5 bytes. This table holds good when BL = 3 bytes or BL = 4 bytes. Table 37-25. CNNR Value Combinations No. of Bytes Read by DMA Source Size (Bytes) Destination Size (Bytes) Memory Increment 6 8 6 8 5 5 Memory Decrement 6 8 6 8 5 5 No. of Bytes Written by DMA Memory Increment 6 8 8 6 6 8 Memory Decrement 6 8 8 6 6 8 CCNR (Bytes) 2 4 2 4 1 1 2 4 4 2 2 4 6 8 8 6 6 8 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-31 Direct Memory Access Controller (DMAC) 37.7.2 BL is Not a Multiple of Destination Access Size, CNTR Is If BL register value is not a multiple of destination access size but CNTR is, then the value of CCNR will not match the value programmed in CNTR after completion of DMA cycle for the channel. Table 37-26 illustrates the values of CCNR with different combinations of source and destination access sizes when BL = 3 bytes and CNTR = 4 bytes. Table 37-26. CCNR Value Combinations No. of Bytes Read by DMA Source Size (Bytes) Destination Size (Bytes) Memory Increment 6 8 6 8 4 4 Memory Decrement 6 8 6 8 4 4 No. of Bytes Written by DMA Memory Increment 6 8 8 6 6 8 Memory Decrement 6 8 8 6 6 8 CCNR (Bytes) 2 4 2 4 1 1 2 4 4 2 2 4 6 8 8 6 6 8 NOTE In case of memory decrement there might be some cases where DMA overwrites data written by itself so the number of bytes seen by the user can be different than those mentioned in the tables above. 37.8 Application Note Following is the sequence to re-program a channel for data transfer: 1. Clear the status register bit corresponding to that channel (DISR, DBTOSR, DSESR, DRTOSR, DBOSR) after the DMA cycle is completed. 2. Change SMOD (source mode) to 2’b00 and clear CEN. 3. Re-program all registers corresponding to that particular channel, except CCR. 4. Program CCR and set CEN bit to 1. NOTE This sequence applies to all 16 channels in all modes: Linear memory, 2D memory, and FIFO. 37.9 DMA Burst Termination DMA Controller needs to terminate its burst in case of: • Transfer error response from slave • Burst time-out error. • Buffer overflow error. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-32 Freescale Semiconductor Direct Memory Access Controller (DMAC) • Channel disable (by software using CEN bit). CAUTION DMA burst termination may not occur immediately. Burst termination occurs immediately in DMAC only on occurrence of Transfer Error response from the Slave. In other cases, Burst time-out, Buffer overflow and Channel disable (by software using CEN bit) takes about 2 more AHB transfers to terminate the burst after these are sensed. The burst termination is not done immediately to avoid AHB protocol violation. In case the burst hangs and hready is not asserted for a large number of cycles, then this must be handled by the watchdog timer in the ABCD Module in i.MX27 device or by the system software. 37.10 Glossary of Terms Used DMA burst DMA cycle This refers to the burst cycles on the AHB Bus performed by the DMA. DMA cycle can consists of a number of DMA bursts depending on the Channel Burst Length and Channel Count register settings. for example, if BL = 4 and CNTR = 8, then DMA cycle will consist of 2 DMA bursts. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 37-33 Direct Memory Access Controller (DMAC) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 37-34 Freescale Semiconductor Book II, Part 7: Multimedia Peripherals Introduction Chapter 38, “Digital Audio MUX (AUDMUX),” on page 38-1 Chapter 39, “CMOS Sensor Interface (CSI)”, on page 39-1 Chapter 40, “Video Codec (Video_Codec),” on page 40-1 Chapter 41, “enhanced Multimedia Accelerator Light (eMMA_lt),” on page 41-1 Chapter 42, “Synchronous Serial Interface (SSI),” on page 42-1 Chapter 43, “Liquid Crystal Display Controller (LCDC),” on page 43-1 Chapter 44, “Smart Liquid Crystal Display Controller (SLCDC),” on page 44-1 CMOS Sensor Interface (CSI) This section presents the CMOS Sensor Interface (CSI) on the architecture, operation principles, and programming model. The CSI is a logic interface which enables the i.MX27 to directly connect to external CMOS sensors and CCIR656 video source. Digital Audio MUX (AUDMUX) The Digital Audio MUX (AUDMUX) provides a programmable interconnect fabric for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI or SAP) and peripheral serial interfaces (for example, audio and voice CODECs). The AUDMUX allows the audio system connectivity to be modified through programming (as opposed to altering the PCB schematics of the system). The Digital Audio MUX is configured by software. With the AUDMUX, resources do not need to be hard-wired and can be effectively shared in different configurations. The AUDMUX interconnections allow multiple, simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. The AUDMUX includes two types of interfaces. Internal ports connect to the processor serial interfaces and external ports connect to off-chip audio devices and serial interfaces of other processors. A desired connectivity is achieved by configuring the appropriate internal and external ports. enhanced Multimedia Accelerator light (eMMA_lt) The enhanced Multimedia Accelerator light (eMMA_lt) consists of the video Pre-Processor (PrP) and Post-Processor (PP), similar functionalities with original eMMA which also includes Mpeg4 Encoder MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 1 (EN) and Decoder (DE). These blocks work together to provide video acceleration and off-load the CPU from computation intensive tasks. The PrP and PP can be used for generic video pre and post processing such as scaling, resizing, and color space conversions. Synchronous Serial Interface (SSI) The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices. These serial devices can be standard CODECs, Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio CODECs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard. SSI is typically used to transfer samples in a periodic manner. The SSI consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. The SSI contains independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. The SSI can work in normal mode operation using frame sync and in Network mode operation allowing multiple devices to share the port with as many as thirty-two time slots. The SSI provides 2 sets of Transmit and Receive FIFOs. Each of the four FIFOs is 8x24 bits. The two sets of Tx/Rx FIFOs can be used in Network mode to provide 2 independent channels for transmission and reception. It also has programmable data interface modes such like I2S, LSB, MSB aligned and programmable word lengths. Other program options include frame sync and clock generation and programmable I2S modes (Master, Slave or Normal). Oversampling clock, ccm_ssi_clk available as output from SRCK in I2S Master mode. In addition to AC97 support the SSI has completely separate clock and frame sync selections for the receive and transmit sections. In AC97 standard, the clock is taken from an external source and frame sync is generated internally. the SSI also has a programmable internal clock divider and Time Slot Mask. Liquid Crystal Display Controller (LCDC) The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive color or CSTN), and active-matrix color (active color or TFT) LCD panels. Smart Liquid Crystal Display Controller (SLDC) The Smart Liquid Crystal Display Controller module transfers data from the display memory buffer to the external display device. Direct Memory Access (DMA) transfers the data transparently with minimal software intervention. Bus utilization of the DMA is controllable and deterministic. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 2 Freescale Semiconductor Chapter 38 Digital Audio MUX (AUDMUX) The Digital Audio MUX (AUDMUX) provides a programmable interconnect fabric for voice, audio, and synchronous data routing between the i.MX27 device SSI modules and an external SSI, or between audio and voice codecs. With the AUDMUX, resources do not need to be hard-wired and can be effectively shared in different configurations. The AUDMUX interconnections allow multiple simultaneous separate audio/voice/data flows between the ports in a point-to-point or point-to-multipoint configuration. 38.1 Features The Digital Audio MUX offers the following features: • Three host interfaces (two internal and one external) • Three peripheral interfaces (All external) • Full 6-wire SSI interfaces for asynchronous receive and transmit • Configurable 4-wire, synchronous or 6-wire asynchronous Rx and Tx external host and peripheral interfaces • Independent Frame sync and clock direction selection for host or peripheral. Clock direction selection to function as master of the flow • Each host interface can be connected to any other host or peripheral interface in a point-to-point or point-to-multipoint (network mode) • Transmit and Receive Data switching to support external network mode 38.2 Overview Figure 38-1 shows the block diagram of the AUDMUX. On the left of the illustration are the internal interfaces and on the right, the external interfaces. Port 1 and Port 2 are internally connected to SSI-1 and SSI-2, respectively, and Port 3 has special muxes allowing connection to an external SSI, such as a synchronous audio port (SAP) commonly found on a baseband modem. Ports 4–6 are identical and can be connected to any 4-wire or 6-wire SSI, voice, I2S or AC97 codec. Ports 1–3 are also known as host ports, and Ports 4–6 as peripheral ports. Port 1–Port 6 have configurable 4-wire or 6-wire interfaces. When configured as a 6-wire interface, the additional RFS and RCLK signals of the interface enable the SSIs to be used in asynchronous mode with separate receive and transmit clocks. In this mode, a device at one port can be connected to two ports (internal or external) configured as input only (simplex) and output only (simplex). Ports 1–3 have muxing arrangements to support internal network mode. Ports 3–6 have a Tx/Rx switch to support external network mode. The Tx/Rx switch enables the Da and Db lines to be swapped so that more than one master connected to any of Ports 1–3 can communicate to more than one slave externally attached at the external ports. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-1 Digital Audio MUX (AUDMUX) Bit Clock selection direction enables each port to be configured as a master or slave in the flow. Possible scenarios are as follows: 1. SSI1 (Internal host port) drives voice codec and BT (on External Peripheral Port 6) and the Bottom Connector (on External Peripheral Port 5) simultaneously using network mode. SSI1 is the master. 2. SAP (External audio port from Baseband) drives voice codec and BT (on Port 6) and the Bottom Connector (on Port 5) simultaneously using network mode. SAP is the master. NOTE The first scenario supports External Network mode when SSI1 provides the corresponding Output Enables for TxData, and the Slave devices receiving the data must be configured to only receive in their corresponding time slot. In the second case, any slave devices attached locally to the SAP in network mode must be disabled to access slave devices on the other ports (for example, SSI, voice codec, and/or BT). Frame Sync and Bit Clock selections enable each port to be configured as a master or slave in the flow. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-2 Freescale Semiconductor Digital Audio MUX (AUDMUX) FSns, CLKns TxDn, RxDn RFCSEL6[3:0] FS6, CLK6 Port 1 TFS1, TCLK1 TFCSEL2[3:0] RXDSEL6[3:0] TXRXEN6 TxDn_obe Da6 TxDn_in RxD_in X Db6 Port 6 RFS1, RCLK1 TxD1 RxD1 RFCSEL2[3:0] RFCSEL5[3:0] FS5, CLK5 RXDSEL5[3:0] TXRXEN5 TxDn_obe Da5 TxDn_in X Db5 Port 5 Port 2 TFS2, TCLK2 INMEN RXDSEL2[3:0] RxD_in RFCSEL4[3:0] TFCSEL2[3:0] FS4, CLK4 RXDSEL4[3:0] TXRXEN4 TxDn_obe Da4 TxDn_in RxD_in X Db4 RFS2, RCLK2 TxD2 RxD2 RFCSEL2[3:0] Port 4 RFCSEL3[3:0] FS3, CLK3 RXDSEL3[3:0] TxDn_obe TxDn_in TxD_out X RxD_in TXRXEN3 Da3 Db3 Port 3 INMEN RXDSEL2[3:0] TxD_obe mux for PORT3 1 TxD_obe1 1 0 TxD_obe 5 RXDSEL[3:0] INMEN TxD_obe to Tx/Rx Switch Figure 38-1. AUDMUX Block Diagram MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-3 Digital Audio MUX (AUDMUX) 38.3 Internal Network Mode Figure 38-2 shows the internal network mode selection logic. Network mode is where a master SSI is connected to more than one slave SSI device and communication occurs on a time-slotted frame. Though network mode allows communication between master-slave and slave-slave, the internal network mode supports only master-slave network mode. In internal network mode (INMEN=1), the output of the AND gate is routed to the output of the port and to the RxD signal of the SSI. The INMMASK bit vector selects the transmit signals of the ports that are to be connected in network mode. The transmit signals (TxD_in from SSI and RxD_in from external ports) are ANDed together to form the output. In network mode, only one device can be transmitting in its predesignated timeslot and all other transmit signals will remain high (tri-stated and pulled-up), hence non-active signals in the selection will be high and do not influence the output of the AND gate. In normal mode (INMEN=0), the SSI is connected in point to point (as a master or slave) and the RXDSEL[2:0] settings select the transmit signal from the other ports. Internal network mode can be used with external network as long as slave-only devices are attached in external network mode at a port or in. Internal network mode can also be used with external network mode if all slave devices connected to a master in external network mode are disabled. Figure 38-2 shows the connections for Port 1. 1 TxD2_in/RxDn_in internal network mode selection matrix AUDMUX boundary 1 0 INMMASK[n] INMMASK[4:0] 1 RxD (Port1) 0 TxD2_in RxD3_in RxD4_in RxD5_in RxD6_in INMEN RXDSEL1[2:0] Figure 38-2. Internal Network Mode 38.4 Tx/Rx Switch and External Network Mode External network mode is the traditional network mode connection. It is called external network mode to differentiate from the internal network mode. In external network mode, devices are connected to the external ports in a star or multidrop configuration. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-4 Freescale Semiconductor Digital Audio MUX (AUDMUX) In network mode, there can be only one master (frame sync and clock source) and the other devices are configured in normal slave mode or network slave mode. Unlike internal network mode, in external network mode both master-slave and slave-slave communication can take place. Codec devices transmit on a single timeslot and SSIs in network master (for example SAP) or slave mode (SSI-2) can process more than one timeslot of data. Figure 38-3 shows the Tx/Rx switch. TxD_obe is the output buffer enable signal and TxD_out is the data transmit signal from the internal SSI. The RxD_in signal is the receive data signal going towards the RXDSEL and TXDSEL muxes of the SSI ports and external ports. In normal mode and network slave mode, TXRXEN is disabled (TXRXEN=0) and TxD_out is routed to Da (Da_out) and Db (Db_in) is routed to RxD_in. In normal mode, the output buffer enable, Da_obe is always enabled (asserted) and TxD_out is routed to Da_out. In network mode, the TxD_obe signal is enabled during the SSI’s timeslot(s) and the Da output is tri-stated in other timeslots. In network mode (SSIx as master), the Tx/Rx switch is enabled (TXRXEN=1) and TxD_out is routed to Db_out and Da_in is routed to RxD_in. The TxD_obe signal is enabled during the SSI’s timeslot(s) and the Db output is tristated in other timeslots. AUDMUX boundary Pin Interface Boundary TXRXEN TxD_obe 0 1 Da_obe IOPAD TxD_out 0 1 Da_out Da_in Db_obe IOPAD Db_out RxD_in 0 1 TXRX SWITCH Db_in Db Da Figure 38-3. Tx/Rx Switch 38.5 Frame Sync and Clocks The routing of frame syncs and interface clocks are shown in Figure 38-4. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-5 Digital Audio MUX (AUDMUX) TFCSELy[3:0] AUDMUX Boundary PORTx TFS_obe TFS_in FS_obe TFS_out FS_out FS_in IOPAD RFCSELx[3:0] RFS_obe RFS_in TxFS AUDMUX Boundary PORTy Pin Boundary RFS_out RFCSELx[3:0] TFSn_obe, TFSn_in, RFSn_obe, RFSn_in and FSn_in to/from other ports TFCSELy[3:0] TCLK_obe TCLK_in CLK_obe TCLK_out CLK_out CLK_in IOPAD RFCSELx[3:0] RCLK_obe RCLK_in RCLK_out TxCLK RFCSELx[3:0] TCLKn_obe, TCLKn_in, RCLKn_obe RCLKn_in and CLKn_in to/from other ports Figure 38-4. Frame Sync and Clock Routing when Peripheral Port is 4-Wire 38.6 Synchronous Mode (4-Wire Interface) In Synchronous mode the port will have a 4-wire interface—that is, RXD,TXD,TxCLK,TxFS.The Receive clock and the receive frame sync will be the same as Transmit clock (TxCLK) and Transmit frame sync (TxFS), respectively. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-6 Freescale Semiconductor Digital Audio MUX (AUDMUX) As shown in Figure 38-4, PORTx signals can be routed to PORTy, showing a 6-wire to 4-wire port connectivity. TFS_in, RFS_in, TCLK_in, and RCLK_in are input Frame Sync and Bit Clocks from the SSI with their corresponding output buffer enable signals (_obe). TFS_out, RFS_out, TCLK_out, and RCLK_out are the Frame Sync and Bit Clocks that are transmitted to the SSI from the other ports. TFS_out and TCLK_out are selected by the TFCSEL MUX settings and RFS_out and RCLK_out are selected by the RFCSEL MUX settings. Similarly, in the external direction, the TFCSEL selects the FS_obe and FS_out signals. In this mode RFCSEL is not used. 38.7 Asynchronous Mode (6-Wire Interface) In Asynchronous mode the port will have a 6-wire interface—that is, RXD, TXD, TxCLK, TxFS, RxCLK, RxFS. There will be additional Receive clock (RxCLK) and the frame sync (RxFS) pins as compared to the Synchronous or 4-wire interface. Refer to Figure 38-5 and Figure 38-6, PORTx signals can be routed to PORTy, depicting a 6-wire to 6-wire port connectivity. TFS_in, RFS_in, TCLK_in and RCLK_in are input Frame Sync and Bit Clocks from the SSI (PORTx) with their corresponding output buffer enable signals (_obe). TFS_out, RFS_out, TCLK_out, and RCLK_out are the Frame Sync and Bit Clocks that are transmitted to the SSI from the other ports. TFS_out and TCLK_out are selected by the TFCSEL MUX settings and RFS_out and RCLK_out are selected by the RFCSEL MUX settings. Similarly, in the external direction, the TFCSEL selects the TxFS_obe, TxFS_out and TxCLK_obe, TxClk_out signals. The RFCSEL selects the RxFS_obe and RxFS_out and RxCLK_obe, RxCLK_out. NOTE Noticed that because FS_in and CLK_in from external interfaces are also routed to the TFCSEL muxes of the external ports, these signals do not have corresponding buffer enable signals. Consequently, their corresponding inputs to the TFCSEL MUX of the external ports must be tied high. 38.8 SSI to Peripheral Connection The Figure 38-7 shows the data path interconnections between an internal SSI port and a peripheral port. TxD_obe is the buffer enable signal from the SSI, TxD_in, the input transmit data from the SSI and RxD_out, the receive data output from the AUDMXUX to the SSI. TXDSEL[2:0] of the peripheral port, selects the buffer enable signal (TxD_obe) and transmit data output (TxD_out) signal from the TxD_obe and TxD_in and RxD_in signals. TXDSEL[2:0] is a common signal to both selection muxes. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-7 Digital Audio MUX (AUDMUX) NOTE Because RxD_in signals from external interfaces do not have their buffer enable signals, their corresponding buffer enable signals into the selection MUX should be tied to high. This will ensure that selection of RxD_in as TxD_out will also drive the TxD_obe output high. Transmit Data from the SSI goes into the TXDSEL data MUX and comes out as TxD_out and is routed to Da_out when TXRXEN is disabled and to Db_out when TXRXEN is enabled. Similarly, Db_in is routed to RxD_in when TXRXEN is disabled and Da_in is routed to RxD_in when TXRXEN is enabled. If The routing of frame syncs are shown in Figure 38-5 and the routing of interface clocks are shown in Figure 38-6. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-8 Freescale Semiconductor Digital Audio MUX (AUDMUX) TFCSELy[3:0] AUDMUX Boundary PORTx TFS_obe TFS_in TFS_obe TFS_out TFS_out TFS_in IOPAD TFCSELx[3:0] RFS_obe RFS_in TxFS AUDMUX Boundary PORTy Pin Boundary RFS_out RFCSELx[3:0] TFSn_obe, TFSn_in, RFSn_obe, RFSn_in and FSn_in to/from other ports RFCSELy[3:0] TFS_obe TFS_in RFS_obe TFS_out RFS_out RFS_in IOPAD TFCSELx[3:0] RFS_obe RFS_in RFS_out RxFS RFCSELx[3:0] TFSn_obe, TFSn_in, RFSn_obe RFSn_in and FSn_in to/from other ports Figure 38-5. Frame Sync Routing when Peripheral Port is 6-Wired MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-9 Digital Audio MUX (AUDMUX) TFCSELy[3:0] AUDMUX Boundary PORTx TCLK_obe TCLK_in TCLK_obe TCLK_out TCLK_out TCLK_in IOPAD TFCSELx[3:0] RCLK_obe RCLK_in RCLK_out TxCLK AUDMUX Boundary PORTy Pin Boundary RFCSELx[3:0] TClkn_obe, TClkn_in, RClkn_obe, RClkn_in and Clkn_in to/from other ports RFCSELy[3:0] TCLK_obe TCLK_in RCLK_obe TCLK_out RCLK_out RCLK_in IOPAD TFCSELx[3:0] RCLK_obe RCLK_in RCLK_out RxCLK RFCSELx[3:0] TCLKn_obe, TCLKn_in, RCLKn_obe RCLKn_in and CLKn_in to/from other ports Figure 38-6. Clock Routing when Peripheral Port is 6-Wired If internal network mode is disabled, then RXDSEL selects the RxD_in which is then output from the AUDMUX to the SSI. When internal network mode is selected, the RxD_in is ANDed with other TxD_in and RxD_in signals from other ports before output as RxD_out to the SSI. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-10 Freescale Semiconductor Digital Audio MUX (AUDMUX) If there are more than one device attached to the external port at Da and Db interfaces and one of the devices is a network master, then two conditions have to be noted: a) When the external master is enabled in network mode, then the SSI must be configured as slave (normal or network mode). No Tx/Rx switching is required. b) When the external master is disabled and the SSI and other slave devices require to communicate, then the SSI must be configured as network mode master and the Tx/Rx switch must be enabled (TXRXEN=1). This ensures that the transmit and receive paths are connected appropriately. To communicate with more than one port, internal network mode must be enabled at the SSI port. In internal network mode, it is possible to communicate with any device attached to the other ports. Internal network mode must be enabled at the port that is the SSI network mode master. 38.9 SSI to SAP The Figure 38-8 shows the detailed interconnection of a SSI port to a SAP port. The SSI and SAP port can act as masters or slaves and be configured in normal or network mode. The SAP port can communicate with more than one external device attached to its own interface in external network mode and additionally with one device attached to another AUDMUX port. If the SAP must communicate with more than one port, then the internal network mode must be enabled. 38.10 Peripheral Port to Peripheral Port Peripherals attached to the AUDMUX can communicate with each other in 2 ways: a) One peripheral acts is configured as master and which sources the clock and/or the frame sync and the other peripheral is configured as slave. b) Both peripherals are configured as slaves but with data routing established from external port to external port with one additional port configured as master (SSI or SAP), which sources the frame sync and clock to the two ports. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-11 38-12 PORTx PORTy RXDSELy[2:0] TXRXENy AUDMUX Boundary Pin Boundary TxD_obe 1 1 IOPAD TxD_out 1 INMENx INMMASKx[7:0] Db_out RxD_in 0 1 TxDn_in, RxDn_in, TxDn_obe to/from other ports TXRX SWITCH Db_in RXDSELx[3:0] 0 Da_out Da_in Db_obe IOPAD Db Da 0 0 Da_obe Digital Audio MUX (AUDMUX) AUDMUX Boundary TxD_obe TxD_in Figure 38-7. SSI to Peripheral Port Interconnection MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 RxD_out Freescale Semiconductor Freescale Semiconductor PORTx TXRXENy RXDSELy[2:0] PORTy AUDMUX Boundary Pin Boundary TxD_obe 1 0 1 INMENy 0 1 Da_out Da_in Db_obe IOPAD Db_out INMMASKy[7:0] RxD_in 0 1 TXRX SWITCH TxDn_in, RxDn_in, TxDn_obe to/from other ports Db_in Db IOPAD Da 0 Da_obe INMENx RXDSELx[3:0] INMMASKx[7:0] TxD_out 0 1 AUDMUX Boundary TxD_obe TxD_in Figure 38-8. SSI to SAP Interconnection MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 RxD_out Digital Audio MUX (AUDMUX) 38-13 Digital Audio MUX (AUDMUX) 38.11 Memory Map and Register Definition There is one configuration register per host port and per peripheral port. The AUDMUX has a total of 6 registers. Table 38-3 shows the control register summary and address mapping for AUDMUX. The base address is 0x1001 6000. 38.11.1 AUDMUX Memory Map Table 38-1 shows the AUDMUX memory map. Table 38-1. AUDMUX Memory Map Address 0x1001_6000 (HPCR1) 0x1001_6004 (HPCR2) 0x1001_6008 (HPCR3) 0x1001_6010 (PPCR1) 0x1001_6014 (PPCR2) 0x1001_601C (PPCR3) Use Host Port Configuration Register 1 Host Port Configuration Register 2 Host Port Configuration Register 3 Peripheral Port Configuration Register 1 Peripheral Port Configuration Register 2 Peripheral Port Configuration Register 3 Access R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_1000 0x0000_1000 0x0000_1000 Section/Page 38.11.3/38-16 38.11.3/38-16 38.11.3/38-16 38.11.4/38-18 38.11.4/38-18 38.11.4/38-18 38.11.2 Register Summary Figure 38-9 shows the key to the register fields, and Table 38-2 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 38-9. Key to Register Fields Table 38-2. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Self-clearing bit Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Writing a one has some effect on the module, but it always reads as zero. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-14 Freescale Semiconductor Digital Audio MUX (AUDMUX) Table 38-2. Register Figure Conventions (continued) Convention Description Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 38-3 shows the AUDMUX register summary. Table 38-3. AUDMUX Register Summary Name 0x1001_6000 (HPCR1) R 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 TC TFS LK W DIR DIR R RXDSEL[2:0] W TFCSEL[3:0] 0 0 RFS DIR 0 RCLKDI R 0 RFCSEL[3:0] 0 0 0 SY N INMEN INMMASK[7:0] 0 RFCSEL[3:0] 0 0 0 0x1001_6004 (HPCR2) TC TFS LK W DIR DIR R RXDSEL[2:0] W R TFCSEL[3:0] 0 0 RFS DIR 0 RCLKDI R SY N INMEN RFS DIR 0 INMEN RFS DIR 0 INMMASK[7:0] 0 RFCSEL[3:0] 0 0 0 0x1001_6008 (HPCR3) TC TFS LK W DIR DIR R R RXDSEL[2:0] W TFCSEL[3:0] 0 RCLKDI R SY N TXR XEN INMMASK[7:0] 0 RFCSEL[3:0] 0 0 0 0 0 0 0 0 0 0 0 0x1001_6010 (PPCR1) TC TFS LK W DIR DIR R RXDSEL[2:0] W R TFCSEL[3:0] 0 RCLKDI R 0 SY N TXR XEN 0x1001_6014 (PPCR2) TC TFS LK W DIR DIR R RXDSEL[2:0] W R TFCSEL[3:0] 0 RFS DIR TXR XEN 0 RCLKDI R 0 0 0 RFCSEL[3:0] 0 0 0 0 0 0 0 SY N 0 0 0 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-15 Digital Audio MUX (AUDMUX) Table 38-3. AUDMUX Register Summary (continued) Name 0x1001_601C (PPCR3) R 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 TC TFS LK W DIR DIR R RXDSEL[2:0] W TFCSEL[3:0] 0 RFS DIR 0 RCLKDI R 0 0 0 RFCSEL[3:0] 0 0 0 0 0 0 0 SY N TXR XEN 0 0 0 38.11.3 Host Port Configuration Register (HPCR1–2) There is one Host Port Configuration Register (HPCR) for each host port. 0x1001_6000 (HPCR1) 0x1001_6004 (HPCR2) 0x1001_6008 (HPCR3) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read/write 19 18 17 16 R TFS W DIR Reset 0 TCLK DIR 0 0 TFCSEL 0 0 0 RFS RCLK DIR DIR 0 0 0 0 RFCSEL 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RXDSEL W Reset 0 0 0 0 SYN 0 TXRX EN 0 0 INME N 0 0 0 0 INMMASK 0 0 0 0 0 0 0 Figure 38-10. Host Port Configuration Register (HPCR1–2) Table 38-4. Host Port Configuration Register Field Descriptions Field 31 TFSDIR Description Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as output or input.When set as input, the TFCSEL settings are ignored.When set as output, the TFCSEL settings determine the source port of the Frame Sync. 0 TxFS is input pin. 1 TxFS is output. Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as output or input.When set as input, the TFCSEL settings are ignored.When set as output, the TFCSEL settings determine the source port of the Clock. 0 TxClk is input pin. 1 TxClk is output. 30 TCLKDIR MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-16 Freescale Semiconductor Digital Audio MUX (AUDMUX) Table 38-4. Host Port Configuration Register Field Descriptions (continued) Field 29–26 TFCSEL Description Transmit Frame Sync and Clock Select. Selects the source port from which TxFS and TxClk are sourced. 0xxx Selects TxFS and TxClk from port 1xxx Selects RxFS and RxClk from port 000 101 Port 1–Port 6 110 Reserved 111 Reserved Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as output or input.When set as input, the RFCSEL settings are ignored.When set as output, the RFCSEL settings determine the source port of the Frame Sync. 0 RxFS is input pin. 1 RxFS is output. Receive Clock Direction Control. This bit sets the direction of the RxClk pin of the interface as output or input.When set as input, the RFCSEL settings are ignored.When set as output, the RFCSEL settings determine the source port of the Clock. 0 RxClk is input pin. 1 RxClk is output. Receive Frame Sync and Clock Select. Selects the source port from which RxFS and RxClk are sourced. RxFS and RxClk can be sourced from TxFS and TxClk, respectively, from other ports. 0xxx Selects TxFS and TxClk from port 1xxx Selects RxFS and RxClk from port 000–101 Port 1–Port 6 110 Reserved 111 Reserved Reserved. These bits are reserved and should read 0. Receive Data Select. Selects the source port for the RxD data. RXDSEL is ignored if INMEN is enabled. xxx Port number for RxD, ignored if equal to self port number 000–101 Port 1–Port 6 110 Reserved 111 Reserved Synchronous/Asynchronous Select. When SYN is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. That is, the port is a 4-wire interface. When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sections. That is, the port is a 6-wire interface. 0 Asynchronous mode 1 Synchronous mode (default) Reserved. This bit is reserved and should read 0. Transmit/Receive Switch Enable. Swaps the transmit and receive signals from (Da-TxD, Db-RxD) to (Da-RxD, Db-TxD) Note: Present only in Port 3 0 No switch 1 Switch Reserved. This bit is reserved and should be read as 0. 25 RSFDIR 24 RCLKDIR 23–20 RFCSEL 19–16 15–13 RXDSEL 12 SYN 11 10 TXRXEN 9 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-17 Digital Audio MUX (AUDMUX) Table 38-4. Host Port Configuration Register Field Descriptions (continued) Field 8 INMEN Description Internal Network Mode Enable. RxD from ports in internal network mode are ANDed together. RXDSEL is ignored. INMMASK determines which RxD signals are ANDed together. When internal network mode is enabled at Port 3, then RXDSEL3[3:0] for TxDn_obe selection is ignored and TxD_obe is always driven high. That is, asserted for all timeslots. This places a restriction on slave devices connected in external network mode such that these slave devices have all to be disabled. See Figure 38-16. 0 Disable 1 Enable internal network mode Internal Network Mode Mask. Bit mask that selects which of the RxD signals from ports are to be ANDed together for internal network mode. Bit 7 represents RxD from Port 8 and Bit 0 represents RxD from Port 1. Note: Bit in self port position should be set as 1. 0 Include RxDn for ANDing. 1 Excludes the RxDn from ANDing. 7–0 INMMASK 38.11.4 Peripheral Port Configuration Registers (PPCR1–2) There is one Peripheral Port Configuration Register (PPCR) for each peripheral port. 0x1001_6010 (PPCR1) 0x1001_6014 (PPCR2) 0x1001_601C (PPCR3) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read/write 19 18 17 16 R TFS W DIR Reset 0 TCLK DIR 0 0 0 TFCSEL 0 0 RFS RCLK DIR DIR 0 0 0 0 RFCSEL 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RXDSEL W Reset 0 0 0 1 0 0 SYN TXRXEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 38-11. Peripheral Port Configuration Registers (PPCR1–2) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-18 Freescale Semiconductor Digital Audio MUX (AUDMUX) Table 38-5. Peripheral Port Configuration Register Field Descriptions Field 31 TFSDIR Description Transmit Frame Sync Direction Control. This bit sets the direction of the TxFS pin of the interface as output or input.When set as input, the TFCSEL settings are ignored.When set as output, the TFCSEL settings determine the source port of the Frame Sync. 0 TxFS is input pin. 1 TxFS is output. Transmit Clock Direction Control. This bit sets the direction of the TxClk pin of the interface as output or input.When set as input, the TFCSEL settings are ignored.When set as output, the TFCSEL settings determine the source port of the Clock. 0 TxClk is input pin. 1 TxClk is output. Transmit Frame Sync and Clock Select. Selects the source port from which FS_obe, FS_out, CLK_obe, and CLK_out are sourced. 0xxx Selects TxFS and TxClk from port 1xxx Selects RxFS and RxClk from port xxx Selection ignored if self-port number 110 Reserved 111 Reserved Receive Frame Sync Direction Control. This bit sets the direction of the RxFS pin of the interface as output or input.When set as input, the RFCSEL settings are ignored.When set as output, the RFCSEL settings determine the source port of the Frame Sync. 0 RxFS is input pin. 1 RxFS is output. Receive Clock Direction Control. This bit sets the direction of the Waxlike pin of the interface as output or input.When set as input, the RFCSEL settings are ignored.When set as output, the RFCSEL settings determine the source port of the Clock. 0 RxClk is input pin. 1 RxClk is output. Receive Frame Sync and Clock Select. Selects the source port from which RxFS and RxClk are sourced. RxFS and RxClk can be sourced from TxFS and TxClk, respectively, from other ports. 0xxx Selects TxFS and TxClk from port 1xxx Selects RxFS and RxClk from port 000–101 Port 1–Port 6 110 Reserved 111 Reserved Reserved Receive Data Select. selects the source port for the RxD data (TxD_in or RxD_in). RXDSEL is ignored if INMEN is enabled. xxx Port number for TxD_in or RxD_in, ignored if equal to self port number 110 Reserved 111 Reserved Synchronous/Asynchronous Select. SYN controls whether the receive and transmit functions of the port occur synchronously or asynchronously with respect to each other. When SYN is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. That is, the port is a 4-wire interface.When SYN is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sections; that is, the port is a 6-wire interface. 0 Asynchronous mode 1 Synchronous mode (default) 30 TCLKDIR 29–26 TFCSEL 25 RSFDIR 24 RCLKDIR 23–20 RFCSEL 19–16 15–13 RXDSEL 12 SYN MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-19 Digital Audio MUX (AUDMUX) Table 38-5. Peripheral Port Configuration Register Field Descriptions (continued) Field 11 10 TXRXEN Description Reserved. These bits are reserved and should read 0. Transmit/Receive Switch Enable. Swaps the transmit and receive signals from (Da-TxD, Db-RxD) to (Da-RxD, Db-TxD). 0 No switch 1 Switch Reserved. These bits are reserved and should read 0. 9–0 38.12 Peripheral Connectivity Through AUDMUX Configuration This section describes some of the peripheral connectivity scenarios through AUDMUX configuration and some limitations. 38.12.1 Generic Configuration Figure 38-12 shows a general configuration of the AUDMUX. It does not show what paths are enabled or possible. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-20 Freescale Semiconductor Digital Audio MUX (AUDMUX) Figure 38-12. SAP as Master to SSI2 as Slave Interconnection Only Ports 1, 2, 3 are capable of internal network mode. Only Ports 3, 4, 5, 6 are capable of Tx/Rx switch. Where internal network mode is enabled, for example at Port 1, then Port 1 is referred to as the egress port. Therefore, Ports 1, 2, and 3 become egress ports when internal network mode is enabled at that port. — Config1: only slave devices are connected in network mode. — Config2: one master/slave capable device with slave only devices. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-21 Digital Audio MUX (AUDMUX) AUDMUX Module SSI-1 Port 1 Port 5, 6 Slave Slave Port 4 Slave SSI-2 (SLAVE) Port 2 Port 3 Slave Slave SAP Slave Slave Slave Only Device Internal Network Mode MASTER/ SLAVE Device capable of Master or Slave mode TX/RX Switch Figure 38-13. Configuration Overview 38.12.2 AUDMUX Configuration with SSI1 and SAP as Master Figure 38-14 shows two possible audio paths that can be configured simultaneously. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-22 Freescale Semiconductor Digital Audio MUX (AUDMUX) Figure 38-14. SSI1 as Master in Internal Network Mode Audio Path 1: • • The above configuration shows, SS1-1 configured as master communicating to slaves on Ports 4, 5, and 6. Port 1 internal network mode is enabled hence it is the egress port. Audio Path 2: • The SAP (Audio port from the Baseband) is connected to slave ports and SSI-2. Tx/Rx switch is not enabled, neither is internal network mode. • SSI-2 (Internal to the i.MX27 device) is connected as slave. 38.12.3 Tx-Rx Switch Enabled Figure 38-15 AUDMUX configuration with SSI-1 as the master of the flow. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-23 Digital Audio MUX (AUDMUX) Figure 38-15. Tx-Rx Switch Restriction Flow: • SSI-1 is the master that is connected to all peripheral ports. • Internal network mode is enabled at Port 1 to receive data from Ports 3, 4, 5, 6. • Tx/Rx Switch is enabled only at Port 3 to maintain signal directions to be consistent for slaves on Port 3. • The SAP (Audio port from the Baseband) master must be disabled because its Tx and Rx signals will not be consistent. • Though disabling the SAP master, apparently, makes Config2 into Config1, signal directions are not the same as config1, hence the requirement for the Tx/Rx switch. 38.12.4 Internal/External Network Mode Figure 38-16 shows the limitation posed by Internal network mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-24 Freescale Semiconductor Digital Audio MUX (AUDMUX) Figure 38-16. Internal and External Mode Restriction • • • • In this flow, the SAP (Audio port from the baseband) is now the master and internal network mode is enabled at Port 3. Port 3 is now an egress port for receive data coming from the other ports. The locally attached slave devices have to be disabled because the internal network mode will ALWAYS drive the output at the egress port regardless of timeslots that will cause a multiple driver conflict with slave transmission at Port 3, otherwise. Disabling of slave devices in config2 effectively removes external network mode at Port 3. This is what is meant by internal network mode cannot be used with external network mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 38-25 Digital Audio MUX (AUDMUX) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 38-26 Freescale Semiconductor Chapter 39 CMOS Sensor Interface (CSI) This chapter presents the CMOS Sensor Interface (CSI) architecture, operation principles, and programming model. The CSI enables the i.MX21 to connect directly to external CMOS image sensors. CMOS image sensors are separated into two classes, dumb and smart. Dumb sensors are those that support only traditional sensor timing (Vertical SYNC and Horizontal SYNC) and output only Bayer and statistics data, while smart sensors support CCIR656 video decoder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats). The capabilities of the CSI include: • Configurable interface logic to support most commonly available CMOS sensors. • Support for CCIR656 video interface as well as traditional sensor interface. • 8-bit data port for YCC, YUV, Bayer, or RGB data input. • Full control of 8-bit and 16-bit data to 32-bit FIFO packing. • 32 × 32 FIFO to store received image pixel data that can be read through programmed IO or DMA. • Direct interface to eMMA Preprocessing block (PrP). • Single interrupt source to interrupt controller from maskable sensor interrupt sources: Start of Frame, End of Frame, Change of Field, FIFO full. • Configurable master clock frequency output to sensor. • Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the camera (for Bayer data only). 39.1 CSI Architecture Figure 39-5 shows the block diagram of the CMOS Sensor Interface. It consists of 2 control registers (Control Register 1 and 3) to set up the interface timing and interrupt generation, a control register (Control Register 2) for statistic data generation, a status register, interface logic, data packing logic, CCIR timing decoder, interrupt controller, master clock generator, statistical data generator, 32 × 32 image data receive FIFO (RxFIFO), and a 16 × 32 statistic data FIFO (StatFIFO). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-1 CMOS Sensor Interface (CSI) csi_sof csi_line_strobe csi_rxfull csi_rxff_level[1:0] csi_rxdata[31:0] To eMMA Pre-Processor RxFIFO_DMAREQ_b STATFIFO_DMAREQ_b CSI_INT_b Control Reg 3 Control Reg 1 AHB Bus AHB interface Gasket Master Clock Generator Interrupt Control csi_mclk CSI Status Reg csi_pixclk Interface signal Timing Logic Control csi_vsync csi_hsync RxFIFO(32x32) 16-bit Swap Dummy Zero Packing 8-bit to 32-bit Data Packing Debug Reg Statistic Data Generation Data sampling Logic csi_d[7:0] 16-bit to 32-bit Data Packing CCIR656 Timing Decoder StatFIFO(16x32) Control Reg 2 Figure 39-1. CSI Block Diagram 39.2 CSI Interface Signal Description Table 39-1 provides a listing of the input and output signals between the CSI module of the i.MX27 device and an external CMOS sensor. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-2 Freescale Semiconductor CMOS Sensor Interface (CSI) Table 39-1. Signals Between CSI and Sensor CSI Signals CSI_VSYNC CSI_HSYNC CSI_D[7:0] CSI_MCLK CSI_PIXCLK Direction Input Input Input Output Input Vertical Sync (Start Of Frame) Horizontal Sync (Blank Signal) 8-bit Sensor Data Bus (Bayer, YUV, YCrCb, RGB) Sensor Master Clock Pixel Clock Description 39.2.1 Signals from CSI to eMMA Pre-Processor Block (PrP) There is a dedicated bus from CSI RxFIFO to the eMMA Pre-Processor Block (PrP) for fast data transfer. The bus can be enabled or disabled. When it is enabled, the RxFIFO is detached from the AHB bus and connected to the PrP. Any CPU read or DMA access to the RxFIFO register is ignored. All CSI Interrupts are also masked to prevent software access to the FIFO and status registers. Users select the RxFIFO full level according to the data format and line width, each of the burst from CSI RxFIFO to PrP must use a size that equal to the RxFIFO full level. To ensure complete transfer of the whole frame, the size of the image (in words) must be integer multiples of the RxFIFO full level. A simple calculation is shown in Table 39-2. Table 39-2. Integer Multiples of RxFIFO Full Levels Data Format YUV422 YCC422 RGB565 RGB888 Bayer Byte Per Pixel 2 2 2 4 1 Pixel Per Word 2 2 2 1 4 Options for RxFIFO Full Level (Words) 4 / 8 / 16 Requirement on Line Width (Pixels) Multiple of 8 / 16 / 32 Multiple of 8 / 16 / 32 Multiple of 8 / 16 / 32 Multiples of 4 / 8 / 16 Multiple of 16 / 32 / 64 NOTE FIFO full level of 24 words is not supported in the CSI-PrP interface. If a 24-word full setting is used the internal logic will regard it as 8 words. 39.3 Principles of Operation This section describes the modes of operation of the sensor interface. The CSI is designed to support generic sensor interface timing as well as CCIR656 video interface timing. Traditional CMOS sensors typically use SOF, HSYNC (BLANK), and PIXCLK signals to output Bayer or YUV data. Smart CMOS sensors, that come with on-chip imaging processing, usually support video MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-3 CMOS Sensor Interface (CSI) mode transfer. They use an embedded timing codec to replace the SOF and BLANK signal. The timing codec is defined by the CCIR656 standard. 39.3.1 Gated Clock Mode VSYNC, HSYNC, and PIXCLK signals are used in gated clock mode. A frame starts with a rising edge on VSYNC, then HSYNC goes to HIGH and holds for the entire line. The Pixel clock is valid as long as HSYNC is HIGH. Data is latched at the rising edge of the valid pixel clocks. HSYNC goes to LOW at the end of line. Pixel clocks then become invalid and CSI stops receiving data from the stream. For the next line the HSYNC timing repeats. For the next frame the VSYNC timing repeats. 39.3.2 Non-Gated Clock Mode Start of Frame nth Frame VSYNC n+1th Frame In non-gated clock mode, only the VSYNC and PIXCLK signals are used; the HSYNC signal is ignored. PIXCLK D(7:0) invalid invalid 1st Byte 1st Byte Figure 39-2. Non-Gated Clock Mode Timing Diagram The overall timing of non-gated mode is the same as the gated-clock mode, except for the HSYNC signal. HSYNC signal is ignored by the CSI. All incoming pixel clocks are valid and cause data to be latched into RxFIFO. The PIXCLK signal is inactive (states low) until valid data is ready to be transmitted over the bus. Figure 39-2 shows the timing using a typical sensor, other sensors may have the slightly different timing from that shown. The CSI should be programed to support rising/falling-edge triggered VSYNC; active-high/low HSYNC; and rising/falling-edge triggered PIXCLK. 39.3.3 CCIR656 Interlace Mode In CCIR656 mode, only the PIXCLK and DATA[7:0] signals are used. The start of frame and blank signals are replaced by a timing codec which is embedded in the data stream. Each active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering VSYNC and HSYNC signals for internal use, such as statistical block control and CSI-to-PrP interconnection. Data is forwarded to the data receive and packing block in a sequential manner without re-ordering—that is, field 1 followed by field 2. The fields must be re-ordered in software to get back the original image. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-4 Freescale Semiconductor CMOS Sensor Interface (CSI) Change Of Field interrupt (COF) is triggered upon every field change. The interrupt service routine reads the status register to check for the current field. According to the CCIR656 specification, the image must be in 625/50 PAL or 525/60 NTSC format. In addition, the image is interlaced into odd and even fields, with vertical and horizontal blank data being filled into certain lines. Data must be in YCC422 format, each pixel contains 2 bytes, either Y + Cr or Y + Cb. These requirements are set for TV systems. The CSI module supports PAL and NTSC format only. Figure 39-3 shows the frame structure in PAL system, showing vertical blanking and horizontal blanking. EAV (H,V,F) (1,1,1) (1,1,0) SOF SOV1 (1,0,0) Blanking SAV (H,V,F) (0,1,1) (0,1,0) (0,0,0) Active Video 1 Field 1 (F = 0) Field 2 (F = 1) (1,1,0) (1,1,1) (1,0,1) SOV2 (0,1,0) (0,1,1) (0,0,1) Active Video 2 Field 2 (F = 1) 4 268 4 1440 Bytes Figure 39-3. CCIR656 Interlace Mode (PAL) Figure 39-4 shows the general timing for a single line, showing SAV and EAV. Start of Line Start of Active Pixel Next Line F00X8181 F00Y0000 EAV H-Blanking 8181F00XCYCY 0000F00YB R SAV Pixel Data CYCY B R Figure 39-4. CCIR656 General Line Timing The coding tables recommended by the CCIR656 specification are shown in Table 39-3, Table 39-4 and Table 39-5. It is used in the CCIR656 mode to decode the video stream. An interrupt is generated for SOF, which is decoded from the embedded timing codec. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-5 CMOS Sensor Interface (CSI) . Table 39-3. Coding for SAV and EAV Data Bit Number 7 (MSB) 6 5 4 3 2 1 0 1st Byte 0xFF 1 1 1 1 1 1 1 1 2nd Byte 0x00 0 0 0 0 0 0 0 0 3rd Byte 0x00 0 0 0 0 0 0 0 0 4th Byte 0xXY 1 F V H P3 P2 P1 P0 Table 39-4. Coding for Protection Bits F 0 0 0 0 1 1 1 1 V 0 0 1 1 0 0 1 1 H 0 1 0 1 0 1 0 1 P3 0 1 1 0 0 1 1 0 P2 0 1 0 1 1 0 1 0 P1 0 0 1 1 1 1 0 0 P0 0 1 1 0 1 0 0 1 Table 39-5. Representations by F-Bit F-Bit 0 1 Representations ODD FIELD (FIELD 1) EVEN FIELD (FIELD 2) 39.3.4 CCIR656 Progressive Mode For a CMOS camera system of VGA or CIF resolution, strict adherence to the interlace requirements stated in the CIR standard is not required. The image is considered to have only 1 active field which is scanned in a progressive manner. This active field is regarded as field 1 and the F-bit in the timing codec is ignored by the decoder. Most sensors support CCIR timing in this mode (progressive) by default. Figure 39-5 shows the typical flow of progressive mode. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-6 Freescale Semiconductor CMOS Sensor Interface (CSI) EAV EAV_B EAV_B Single Line Blanking Blanking SAV SAV_B SAV_B Blanking Blanking EAV_B EAV_A EAV_A SOF Blanking Blanking Blanking SAV_B SAV_A SAV_A Blanking Data Data Field 1 (F = 0) EAV_A Blanking SAV_A Data 4 Undefined 4 Configurable Figure 39-5. CCIR656 Progressive Mode (General Case) An interrupt is generated for SOF but not for COF. In the general case, when SOF information is retrieved from the embedded coding, it is known as internal VSYNC mode. In other cases, when the VSYNC signal is provided by the sensor, it is known as external VSYNC mode. The CSI can be operated in internal or external VSYNC mode. 39.3.5 Error Correction for CCIR656 Coding According to the algorithm for CCIR coding, protection bits in the SAV and EAV are encoded in the way that allows a 1-bit error to be corrected, or a 2-bit error to be detected by the decoder. This feature is supported by the CCIR decoder in CSI, for interlace mode only. For the 1-bit error case, users can select the error to be corrected automatically, or simply shown as a status flag instead. For the 2-bit error case, because the decoder is unable to make a correction, the error would be shown as a status flag only. An interrupt can be generated upon the detection of an error. This signal can be enabled or disabled without affecting the operation of the status bit. 39.4 Interrupt Generation This section describes CSI events that generate interrupts. 39.4.1 Start Of Frame Interrupt (SOF_INT) The source of an SOF interrupt is dependent on the mode of operation. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-7 CMOS Sensor Interface (CSI) In traditional mode, VSYNC signal is taken from sensor and SOF_INT is generated at the rising or falling edge (programmable) of VSYNC. In CCIR interlace mode, the SOF interrupt information is retrieved from the embedded coding and SOF_INT is generated. In CCIR progressive mode, there are two sources of an SOF interrupt: • In internal VSYNC mode, SOF is retrieved from the embedded coding. • In external VSYNC mode, VSYNC is taken from the sensor and SOF is generated at the rising edge of VSYNC. 39.4.2 End Of Frame Interrupt (EOF_INT) An EOF interrupt is generated when the frame ends and the complete frame data in RXFIFO is read. The EOF interrupt does not work in CSI PreProcessing mode. The EOF event triggering works with the RX count register (CSIRXCNT). Software sets the RX count register to the frame size (in bytes). The CSI RX logic then counts the number of pixel data being received and compares it with the RX count. If the preset value is reached, then an EOF interrupt is generated and the data in the RXFIFO are read. If an SOF event is detected before this happens, then the EOF interrupt is not generated. 39.4.3 Change Of Field Interrupt (COF_INT) The Change of Field interrupt is only valid in CCIR Interlace mode. The COF interrupt is generated when the field toggles, either from field 1 to field 2, or field 2 to field 1. Software should first check on COF_INT bit in the CSI Status Register (CSISTAT), before checking that F1_INT or F2_INT is turned on. In PAL systems, the field changes at the beginning of the frame and coincides with SOF. For the first field, a COF interrupt is not generated, only an SOF is generated. The COF interrupt is generated for the second field. 39.4.4 CCIR Error Interrupt (ECC_INT) The CCIR Error Interrupt is only valid for CCIR Interlace mode. An ECC interrupt is generated when an error is found on the SAV or EAV codes in the incoming stream. When this happens, the ECC_INT status bit is set. 39.4.5 Data Packing Style Owing to different port sizes at different stages of the image capture path, the endianess of data is important. To enable flexible packing of image data, the CSI module provides data swapping through the PACK_DIR and the SWAP16_EN bits in CSI Control Register 1 (CSICR1) which enables data swapping before it is presented to the FIFOs. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-8 Freescale Semiconductor CMOS Sensor Interface (CSI) Data is packed from 8-bit to 32-bit according to the setting of PACK_DIR bit, and then put into the RX FIFO according to the setting of the SWAP16_EN bit. 39.4.6 RX FIFO Path Bayer data is a type of raw data from the image sensor. This byte-wide data must be converted to the RGB space or YUV space by software. The data path for Bayer data is from the CSI to memory. If the system is in little endian, then the PACK_DIR bit should be set to 0. Doing so results in the data being packed to 32-bit as P3P2P1P0, where P0 is the pixel coming in time slot 0 (first data), while P3 is the pixel coming in time slot 3 (last data). When the data is addressed as bytes by software, P0 goes out first, and ends up with P3. 39.4.6.1 RGB565 Data RGB565 data is processed data from the image sensor, which can be put directly into the display buffer. The data is 16 bits wide. The data path is from CSI to memory, memory to LCDC. On the sensor side, data must be output as P0 first, followed by P1, and so on. Within each pixel, either MSB or LSB will come out first. This is controlled by the endian style of the sensor. Data is 16 bits wide with the MSB labeled RG, and the LSB labeled GB. So for P0, it is represented as RG0, GB0, and so on for P1. CSI receives data in one of the following sequence: • RG0, GB0, RG1, GB1, while RG0 comes out at time slot 0 (first data), and GB1 comes out at time slot 3 (last data), or • GB0, RG0, GB1, RG1. Using the first sequence as an example, and assuming the system is running in little endian the data is presented as: • 8-bit data from sensor: RG0, GB0, RG1, GB1, … • 32-bit data before CSI RX FIFO (PACK_DIR bit = 1): RG0GB0RG1GB1 • 32-bit data in CSI RX FIFO (SWAP16_EN bit enabled): RG1GB1RG0GB0 • 32-bit transfer to system memory: RG1GB1RG0GB0 • 16-bit read by LCDC: RG0GB0, RG1GB1 39.4.6.2 RGB888 Data This is another kind of processed data from image sensor, which can be used for further image processing directly. Each of the data consist of 8-bit Red, 8-bit Green, and 8-bit Blue data. An example of a possible timing scheme is shown in Figure 39-6. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-9 CMOS Sensor Interface (CSI) Input Data Timing Pixclk FORMAT 1 Data[7:0] FORMAT 2 Data[7:0] R0 G0 B0 R1 G1 B1 B0 G0 R0 B1 G1 R1 Figure 39-6. Sample Timing Diagram for RGB888 Data The 3-byte per pixel structure is not an optimum choice for a CSI to PRP path. To improve the data transfer from CSI to PRP, an optional dummy byte packing scheme is provided. For every group of 3 bytes data, a dummy zero is packed to form a 32-bit word as shown in Figure 39-7. The dummy zero is always packed at the LSB position. This byte will be ignored by the PRP FORMAT 1 with Pack direction = ‘1’ (MSB first) FORMAT 2 with Pack Direction = ‘0’ (LSB first) Output Data Format R0 R1 G0 G1 B0 B1 Zero Zero Figure 39-7. Optional Dummy Byte Packing Scheme 39.4.7 STAT FIFO Path Statistics only works for Bayer data. It generates 16-bit statistical output from the 8-bit Bayer input. The outputs are Sum of Green (G), Sum of Red (R), Sum of Blue (B), and Auto Focus (F). Each output is 16-bits wide. The settings of PACK_DIR and SWAP16_EN bits in the CSICR1 register have no effect on the input path. The PACK_DIR only controls how the 16-bit stat output is packed into the 32-bit STAT FIFO. When the PACK_DIR bit = 1, the stat data is packed as: First 32-bit: RG Second 32-bit: BF … When the PACK_DIR bit = 0, the stat data is packed as: First 32-bit GR Second 32-bit: FB … MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-10 Freescale Semiconductor CMOS Sensor Interface (CSI) 39.5 Memory Map and Register Definition The CSI module contains six 32-bit registers which are summarized in Table 39-6. The base address of the CSI module for i.MX27 is 0x1000 8000. Table 39-8 summarizes the registers and offset addresses. Section 39.5, “Memory Map and Register Definition” provides detailed descriptions of the DMAC register. 39.5.1 CSI Memory Map Table 39-6. CSI Memory Map Address 0x8000_00000 (CSICR1) 0x8000_00004 (CSICR2) 0x8000_0001C (CSICR3) 0x8000_00008 (CSISR) 0x8000_0000C (CSISTATFIFO) 0x8000_00010 (CSIRFIFO) 0x8000_00014 (CSIRXCNT) Use CSI Control Register 1 CSI Control Register 2 CSI Control Register 3 CSI Status Register CSI Statistic FIFO Register CSI RX FIFO Register CSI RX Count Register Access R/W R/W R/W R/W R R R/W Reset Value 0x4000_0800 0x0000_0000 0x0000_0000 0x0000_4000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 39.5.3/39-14 39.5.4/39-17 39.5.5/39-19 39.5.6/39-20 39.5.7/39-22 39.5.8/39-22 39.5.9/39-23 Table 39-6 shows the CSI memory map. 39.5.2 Register Summary Figure 39-8 shows the key to the register fields, and Table 39-7 shows the register figure conventions. Always reads 1 1 Always reads 0 0 R/W BIT Read- BIT Writebit only bit only bit Write 1 BIT Self-clear 0 to clear bit BIT w1c BIT N/A Figure 39-8. Key to Register Fields Table 39-7. Register Figure Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types r w rw rwm w1c Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-11 CMOS Sensor Interface (CSI) Table 39-7. Register Figure Conventions (continued) Convention Self-clearing bit Description Writing a one has some effect on the module, but it always reads as zero. Reset Values 0 1 — u Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Table 39-8 shows the CSI register summary. Table 39-8. CSI Register Summary Name 0x8000_00000 (CSICR1) R W 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 STATFF_LEVEL STATFF_INTEN RF_OR_INTEN SF_OR_INTEN COF_INT_EN EOF_INT_EN RxFF_LEVEL CCIR_MODE RxFF_INTEN EXT_VSYNC SWAP16_EN GCLK_MODE HSYNC_POL CLR_RxFIFO R MCLKDIV W CLR_STATFIFO PACK_DIR INV_PCLK INV_DATA CCIR_EN MCLKEN 0x8000_00004 (CSICR2) R W R 0 0 0 0 0 DR M 0 AFS SCE 0 BTS LVRM VSC W 0x8000_0001C (CSICR3) R W FRMCNT_RST R W 0 0 0 0 0 0 FRMCNT HSC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-12 Freescale Semiconductor ECC_AUTO_EN ECC_INT_EN 0 0 0 0 0 CSI_SUP ZERO_PACK_EN REDGE FCC SOF_INTEN 0 PrP_IF_EN SOF_POL CMOS Sensor Interface (CSI) Table 39-8. CSI Register Summary (continued) Name 0x8000_00008 (CSISR) R W 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 RFF_OR_INT SFF_OR_INT STATFF_INT RxFF_INT EOF_INT ECC_ INT F2_INT F1_INT W 0x8000_0000C (CSISTATFIFO) R W R W 0x8000_00010 (CSIRFIFO) R W R W 0x8000_00014 (CSIRXCNT) R W R STAT STAT IMAGE IMAGE 0 0 0 0 0 0 0 0 0 0 RXCNT RXCNT W MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-13 DRDY R COF_INT 0 0 0 0 0 0 0 0 0 0 0 SOF_INT 0 0 0 0 0 0 0 0 0 0 CMOS Sensor Interface (CSI) 39.5.3 CSI Control Register 1 (CSICR1) This register controls the sensor interface timing, CSI-to-PrP bus interface and interrupt generation. The CSI module is enabled through the Peripheral Clock Control Register 0 (PCCR0). The interrupt enable bits in this register control the interrupt signals and the status bits. That means status bits will only function when the corresponding interrupt bits are enabled. 0x8000_00000 (CSICR1) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read/write 19 18 17 16 STATFF_LEVEL COF_INT_EN EOF_INT_EN RxFF_LEVEL CCIR_MODE RxFF_INTEN SWAP16_EN EXT_VSYNC W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GCLK_MODE CLR_RxFIFO HSYNC_POL PACK_DIR INV_PCLK INV_DATA R MCLKDIV W CLR_STATFIFO CCIR_EN MCLKEN Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 REDGE 0 0 Figure 39-9. CSPI Control Register 1 (CSICR1) Table 39-9. CSI Control Register 1 Field Descriptions Field 31 SWAP16_EN Description SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit to 32-bit first (according to the setting of PACK_DIR and then swapped as 16-bit words before putting into the RX FIFO. The action of the bit only affects the RX FIFO and has no affect on the STAT FIFO. Note: Example of swapping enabled: Data input to FIFO = 0x11223344 Data in RX FIFO = 0x 33441122 Note: Example of swapping disabled: Data input to FIFO = 0x11223344 Data in RX FIFO = 0x11223344 0 Disable swapping 1 Enable swapping External VSYNC Enable. This bit controls the operational VSYNC mode. Note: This only works when the CIS is in CCIR progressive mode. 0 Internal VSYNC mode 1 External VSYNC mode End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. 0 EOF interrupt is disabled. 1 EOF interrupt is generated when RX count value is reached. 30 EXT_VSYNC 29 EOF_INT_EN MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-14 Freescale Semiconductor FCC SOF_INTEN 0 0 PrP_IF_EN SOF_POL R STATFF_INTEN RF_OR_INTEN SF_OR_INTEN 0 CMOS Sensor Interface (CSI) Table 39-9. CSI Control Register 1 Field Descriptions (continued) Field 28 PrP_IF_EN Description CSI—PrP Interface Enable. This bit controls the CSI to Prp bus. When enabled the RxFIFO is detached from the AHB bus and connected to PrP. All CPU reads or DMA accesses to the RxFIFO register are ignored. All CSI interrupts are also masked. 0 CSI to PrP bus is disabled 1 CSI to PrP bus is enabled CCIR Mode Select. This bit controls the CCIR mode of operation. This bit only works in CCIR interface mode. 0 Progressive mode is selected 1 Interlace mode is selected Change Of Image Field (COF) Interrupt Enable. This bit enables the COF interrupt. This bit works only in CCIR interlace mode which is when CCIR_EN = 1 and CCIR_MODE = 1. 0 COF interrupt is disabled 1 COF interrupt is enabled 27 CCIR_MODE 26 COF_INT_E 25 STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt. SF_OR_INTEN 0 STATFIFO overrun interrupt is disabled 1 STATFIFO overrun interrupt is enabled 24 RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. RF_OR_INTEN 0 RxFIFO overrun interrupt is disabled 1 RxFIFO overrun interrupt is enabled 23–22 STATFIFO Full Level. When the number of data in STATFIFO reach this level, STATFIFO full interrupt is STATFF_LEVEL generated, or STATFIFO DMA request is sent. 00 4 Words 01 8 Words 10 12 Words 11 16 Words 21 STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt. STATFF_INTEN 0 STATFIFO full interrupt disable 1 STATFIFO full interrupt enable 20–19 RXFF_LEVEL RxFIFO Full Level. When the number of data in RxFIFO reach this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent, or CSI-PrP burst cycle is issued. 00 4 Words 01 8 Words 10 16 Words 11 24 Words Note: In the case when PrP I/F is enabled, 24-words option is not supported, internal logic will regard it as 8-word. This is not reflected in the register value. 18 RXFF_INTEN 17 SOF_POL 16 SOF_INTEN RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt. 0 RxFIFO full interrupt disable 1 RxFIFO full interrupt enable SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. 0 SOF interrupt is generated on SOF falling edge 1 SOF interrupt is generated on SOF rising edge Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. 0 SOF interrupt disable 1 SOF interrupt enable MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-15 CMOS Sensor Interface (CSI) Table 39-9. CSI Control Register 1 Field Descriptions (continued) Field 15–12 MCLKDIV Description Sensor Master Clock (MCLK) Divider. This field contains the divisor MCLK. The MCLK is derived from the PERCLK4. 0000 Divided by 2 0001 Divided by 4 0010 Divided by 6 ... 1111 Divided by 32 HSYNC Polarity Select. This bit controls the polarity of HSYNC. Note: This bit only works in gated-clock—that is, GCLK_MODE = 1 and CCIR_EN = 0. 0 HSYNC is active low 1 HSYNC is active high CCIR656 Interface Enable. This bit selects the type of interface used. When the CCIR656 timing decoder is enabled, it replaces the function of timing interface logic. 0 Traditional interface is selected. Timing interface logic is used to latch data. 1 CCIR656 interface is selected. Sensor Master Clock (MCLK) Enable. This bit enables or disables the MCLK input to the sensor. 0 MCLK disable 1 MCLK enable FIFO Clear Control. This bit determines how the RXFIFO and STATFIFO are cleared. When Synchronous FIFO clear is selected the RXFIFO and STATFIFO are cleared, and STAT block is reset, on every SOF. FIFOs and STAT block restarts immediately after reset. For information on the operation when Asynchronous FIFO clear is selected, refer to the descriptions for the CLR_RXFIFO and CLR_STATFIFO bits. 0 Asynchronous FIFO clear is selected. 1 Synchronous FIFO clear is selected. Data Packing Direction. This bit Controls how 8-bit image data is packed into 32-bit RX FIFO, and how 16-bit statistical data is packed into 32-bit STAT FIFO. 0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. 1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. 11 HSYNC_POL 10 CCIR_EN 9 MCLKEN 8 FCC 7 PACK_DIR 6 Asynchronous STATFIFO Clear. This bit clears the STATFIFO and Reset STAT block. CLR_STATFIFO Note: This bit works only in async FIFO clear mode—that is, FCC = 0. Otherwise this bit is ignored. Writing 1 will clear STATFIFO and reset STAT block immediately, STATFIFO and STAT block then wait and restart after the arrival of next SOF. The bit is restored to 0 automatically after finish. Normally reads 0.fffffffff 5 CLR_RXFIFO Asynchronous RXFIFO Clear. This bit clears the RXFIFO. This bit works only in async FIFO clear mode—that is, FCC = 0. Otherwise this bit is ignored. Writing 1 clears the RXFIFO immediately, RXFIFO restarts immediately after that. The bit is restore to 0 automatically after finish. Normally reads 0. 4 GCLK_MODE Gated Clock Mode Enable. Controls if CSI is working in gated or non-gated mode. Note: This bit works only in traditional mode—that is, CCIR_MODE = 0. Otherwise this bit is ignored. 0 Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. 1 Gated clock mode. Pixel clock signal is valid only when HSYNC is high. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-16 Freescale Semiconductor CMOS Sensor Interface (CSI) Table 39-9. CSI Control Register 1 Field Descriptions (continued) Field 3 INV_DATA 2 INV_PCLK Description Invert Data Input. This bit enables or disables internal inverters on the data lines. 0 CSI_D[7:0] data lines are directly applied to internal circuitry 1 CSI_D[7:0] data lines are inverted before applied to internal circuitry Invert Pixel Clock Input. This bit determines if the Pixel Clock (CSI_PIXCLK) is inverted before it is applied to the CSI module. 0 CSI_PIXCLK is directly applied to internal circuitry 1 CSI_PIXCLK is inverted before applied to internal circuitry Valid Pixel Clock Edge Select. Selects which edge of the CSI_PIXCLK is used to latch the pixel data. 0 Pixel data is latched at the falling edge of CSI_PIXCLK 1 Pixel data is latched at the rising edge of CSI_PIXCLK Reserved. This bit is reserved and should read 0. 1 REDGE 0 39.5.4 CSI Control Register 2 (CSICR2) This register provides the statistic block with data about which live view resolution is being used, and the starting sensor pixel of the Bayer pattern. It also contains the horizontal and vertical count used to determine the number of pixels to skip between the 64 × 64 blocks of statistics when generating statistics on live view image that are greater than 512 × 384. 0x8000_00004 (CSICR2) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read/write 19 18 17 16 R W Reset 0 0 0 0 0 DRM AFS 0 0 SCE 0 0 0 BTS LVRM 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R VSC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSC Figure 39-10. CSI Control Register 2 (CSICR2) Table 39-10. CSI Control Register 2 Description Field 31–27 26 DRM Description Reserved. These bits are reserved and should read 0. Double Resolution Mode. Controls size of statistics grid. 0 Stats grid of 8 × 6 1 Stats grid of 8 × 12 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-17 CMOS Sensor Interface (CSI) Table 39-10. CSI Control Register 2 Description (continued) Field 25–24 AFS Description Auto Focus Spread. Selects which green pixels are used for auto-focus. 00 Abs Diff on consecutive green pixels 01 Abs Diff on every third green pixels 1x Abs Diff on every four green pixels Skip Count Enable. Enables or disables the skip count feature. 0 Skip count disable 1 Skip count enable Reserved. These bits are reserved and should read 0. Bayer Tile Start. Controls the Bayer pattern starting point. 00 GR 01 RG 10 BG 11 GB Live View Resolution Mode. Selects the grid size used for live view resolution. 0 512 × 384 1 448 × 336 2 384 × 288 3 384 × 256 4 320 × 240 5 288 × 216 6 400 × 300 Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored. 0–255 Number of rows to skip minus 1 Horizontal Skip Count. Contains the number of pixels to skip. SCE must be 1, otherwise HSC is ignored. 0–255 Number of pixels to skip minus 1 23 SCE 22–21 20–19 BTS 18–16 LVRM 15–8 VSC 7–0 HSC MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-18 Freescale Semiconductor CMOS Sensor Interface (CSI) 39.5.5 CSI Control Register 3 (CSICR3) This read/write register acts as an extension of the functionality of the CSI Control register 1 adding additional control and features. 0x8000_0001C (CSICR3) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read/write 19 18 17 16 R FRMCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZERO_PACK_EN FRMCNT_RST W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC_INT_EN 0 R 0 0 0 0 0 0 0 0 0 0 0 CSI_SUP Figure 39-11. CSI Control Register 3 (CSICR3) Table 39-11. CSI Control Register 3 Field Descriptions Field 31–16 FRMCNT 15 FRMCNT_RST 14–4 3 CSI_SVR Description Frame Counter. This is a 16-bit Frame Counter (Wrap around automatically after reaching the maximum) Frame Count Reset. Resets the Frame Counter. 0 Do not reset 1 Reset frame counter immediately Reserved. These bits are reserved and should read 0. Supervisor Mode Access Control. This bit enables and disables ARM9 supervisor mode access. 0 Module can be accessed in any ARM9 mode 1 Module can only be accessed in ARM9 supervisor mode. Accessing the module in non-supervisor mode will cause a Data Abort exception. Dummy Zero Packing Enable. This bit causes a dummy zero to be packed with every 3 incoming bytes, forming a 32-bit word. The dummy zero is always packed to the LSB position. 0 Zero packing disabled 1 Zero packing enabled 2 ZERO_PACK_EN MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-19 ECC_AUTO_EN 0 CMOS Sensor Interface (CSI) Table 39-11. CSI Control Register 3 Field Descriptions Field 1 ECC_INT_EN Description Error Detection Interrupt Enable. This bit enables and disables the error detection interrupt. This feature only works in CCIR interlace mode. 0 No interrupt is generated when error is detected. Only the status bit ECC_INT is set. 1 Interrupt is generated when error is detected. Automatic Error Correction Enable. This bit enables and disables the automatic error correction. If an error occurs and error correction is disabled only the ECC_INT status bit is set. This feature only works in CCIR interlace mode. 0 Auto Error correction is disabled. 1 Auto Error correction is enabled. 0 ECC_AUTO_EN 39.5.6 CSI Status Register (CSISR) This read/write register shows sensor interface status, and which kind of interrupt is being generated. The corresponding interrupt bits must be set for the status bit to function. Status bits should function normally even if the corresponding interrupt enable bits are not enabled. 0x8000_00008 (CSISR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User read/write 19 18 17 16 RFF_OR_INT SFF_OR_INT RxFF_INT EOF_INT 0 1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 F2_INT F1_INT W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 39-12. CSI Status Register (CSISR) Table 39-12. CSI Status Register Field Descriptions Field 31–26 25 SF_OR_INT Description Reserved. These bits are reserved and should read 0. STATFIFO Overrun Interrupt Status. Indicates the overflow status of the STATFIFO register. 0 STATFIFO has not overflowed. 1 STATFIFO has overflowed. (Cleared by writing 1) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-20 Freescale Semiconductor DRDY 0 ECC_ INT R COF_INT 0 0 0 0 0 0 0 0 0 0 0 SOF_INT 0 0 R 0 0 0 0 0 0 0 0 STATFF_INT 0 0 CMOS Sensor Interface (CSI) Table 39-12. CSI Status Register Field Descriptions (continued) Field 24 RF_OR_INT Description RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. 0 RXFIFO has not overflowed. 1 RXFIFO has overflowed. (Cleared by writing 1) Reserved. These bits are reserved and should read 0. STATFIFO Full Interrupt Status. Indicates whether the STATFIFO condition is either full or not full /overflowed. 0 STATFIFO is not full, or has overflowed. 1 STATFIFO is full. (this bit is cleared automatically by reading the STATFIFO) Reserved. These bits are reserved and should read 0. RXFIFO Full Interrupt Status. Indicates whether the RxFIFO condition is either full or not full /overflowed. 0 RxFIFO is not full, or has overflowed. 1 RxFIFO is full. (this bit is cleared automatically by reading the RxFIFO) End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. 0 EOF is not detected. 1 EOF is detected. (Cleared by writing 1) Start of Frame Interrupt Status. Indicates when SOF is detected. 0 SOF is not detected. 1 SOF is detected. (Cleared by writing 1) CCIR Field 2 Interrupt Status. Indicates the presence of field 2 of video in CCIR mode. Note: Only works in CCIR Interlace mode. 0 Field 2 of video is not detected 1 Field 2 of video is about to start (Cleared automatically when current field does not match) CCIR Field 1 Interrupt Status. Indicates the presence of field 1 of video in CCIR mode. Note: Only works in CCIR Interlace mode. 0 Field 1 of video is not detected. 1 Field 1 of video is about to start. (Cleared automatically when current field does not match) Change Of Field Interrupt Status. Indicates that a change of the video field has been detected. Only works in CCIR Interlace mode. Software should read this bit first and then dispatch the new field from F1_INT and F2_INT. 1 Change of video field is detected. 0 Video field has no change. (Cleared by writing 1) Reserved. These bits are reserved and should read 0. 23–22 21 STATFF_INT 20–19 18 RxFF_INT 17 EOF_INT 16 SOF_INT 15 F2_INT 14 F1_INT 13 COF_INT 12– 2 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-21 CMOS Sensor Interface (CSI) Table 39-12. CSI Status Register Field Descriptions (continued) Field 1 ECC_INT Description CCIR Error Interrupt. This bit indicates an error has occurred. This only works in CCIR Interlace mode. 0 No error detected (Cleared by writing 1) 1 Error is detected in CCIR coding RXFIFO Data Ready. Indicates the presence of data that is ready for transfer in the RxFIFO. 0 No data (word) is ready 1 At least 1 data (word) is ready in RXFIFO. (Cleared automatically by reading FIFO) 0 DRDY 39.5.7 CSI STATFIFO Register (CSISTATFIFO) The StatFIFO is a read-only register containing statistic data from the sensor. Writing to this register has no effect. 0x8000_0000C (CSISTATFIFO) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-0nly 18 17 16 R W Reset 0 0 0 0 0 0 0 0 STAT 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 STAT 0 0 0 0 0 0 0 0 Figure 39-13. CSI STATFIFO Register (CSISTATFIFO) 39.5.8 CSI RxFIFO Register (CSIRFIFO) This read-only register contains received image data. Writing to this register has no effect. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-22 Freescale Semiconductor CMOS Sensor Interface (CSI) 0x8000_00010 (CSIRFIFO) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-0nly 18 17 16 R W Reset 0 0 0 0 0 0 0 0 IMAGE 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 IMAGE 0 0 0 0 0 0 0 0 Figure 39-14. CSI RxFIFO Register (CSIRFIFO) Because the incoming image data is 8-bit while the FIFO size is 32-bit, the incoming byte size data will be packed into 32-bit in the following sequence. 39.5.9 CSI RX Count Register (CSIRXCNT) This register works for EOF interrupt generation. It should be set to the number of words to receive that would generate an EOF interrupt. There is an internal counter that counts the number of words read from the RX FIFO. Whenever the RX FIFO is being read, by either the CPU or DMA, the counter value is updated and compared with this register. If the values match, then an EOF interrupt is triggered. 0x8000_00014 (CSIRXCNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User read-0nly 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 RXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RXCNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 39-15. CSI RX Count Register (CSIRXCNT) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 39-23 CMOS Sensor Interface (CSI) Table 39-13. CSI RX Count Register Field Descriptions Field 31–22 21–0 RXCNT Description Reserved. These bits are reserved and should read 0. RxFIFO Count. This 22-bit counter for RXFIFO is updated each time the RXFIFO is read by CPU or DMA.This counter should be set to the expected number of words to receive that would generate an EOF interrupt. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 39-24 Freescale Semiconductor Chapter 40 Video Codec (Video_Codec) The Video Codec module is the multimedia video processing module in the i.MX27 device. Figure 40-1 shows the top-level diagram for Video Codec. MPEG4 H.263P3 IP bus Video Codec Gasket APB bus APB3 I/F BIT Processor Core Program Mem Data Mem Host I/F Internal per bus interface AXI bus I/F Main controller (Macroblock Sequencer) H/W accelerator for bitstream packing/unpacking H.264 Reset Controller shared AHB bus AHB bus AHB bus DMAC Rotation (source image) AHB bus for search RAM Motion Estimation Cur Mem Video Codec Gasket AXI Bus Internal Peripheral Bus Internal AXI Bus Inter Prediction Intra Prediction Coefficient Buffer DMAC deblock filter and Rotation (decoded image) residual Reconstruction Video Codec Processor AVC Transform/ Quant MPEG Transform/ Quant AC/DC Prediction Figure 40-1. Video Codec Block Architecture Diagram 40.1 Features Video Codec module support following multimedia video stream processing features: • Multi-standard video codec — MPEG-4 part-II simple profile encoding/decoding — H.264/AVC baseline profile encoding/decoding — H.263 P3 encoding/decoding — Multi-party call: max processing 4 image/bitstream encoding and/or decoding simultaneously. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-1 Video Codec (Video_Codec) — Multi-format: encodes MPEG4 bitstream, and decodes H.264 bitstream simultaneously. • Coding tools — high-performance motion estimation. – Single reference frame for both MPEG4 and H.264 encoding. – Support 16 reference frame for H264 decoding – Quarter-pel and half-pel accuracy motion estimation – [+/–16, +/–16] Search range – Unrestricted motion vector — MPEG-4 AC/DC prediction and H.264 Intra prediction. — All variable block sizes are supported (in case of encoding, 8x4, 4x8, and 4x4 block sizes are not supported). — H.263 Annex I, J, K (RS = 0 and ASO =0), and T are supported. In case of encoding, Annex I and K (RS=1 or ASO=1) are not supported. — CIR (Cyclic Intra Refresh)/AIR (Adaptive Intra Refresh) — Error resilience tools. – MPEG-4 re-synchronize marker and data-partitioning with RVLC (fixed number of bits/macroblocks between macroblocks) – H.264/AVC FMO and ASO – H.263 slice structured mode — Bit-rate control (CBR and VBR) Pre/post rotation/mirroring — 8 rotation/mirroring modes for image to be encoded — 8 rotation/mirroring modes for image to be displayed Programmability — Embeds 16-bit DSP processor that is dedicated to process bitstream and drive codec hardware — General purpose registers and interrupt generation for communication between the system and the Video Codec module • • 40.2 Overview The Video Codec module in i.MX27 device supports full duplex video codec processing and multi-party calls. It integrates multiple video processing standard together, including H264 BP, MPEG4 SP, and H263 P3 (including annex I, J, K, and T). The Video Codec uses two bus interface protocols: the IP bus for register access control and the AHB bus for data throughput. The Video Codec module uses three memory components: embedded memory, system internal memory and system external memory. Embedded memories include dual-port register files, single-port register file, dual-port SRAM, and single-port SRAM. System internal memory is used by motion estimation to increase codec performance. System external memory is used to store input/output image pixel data and bit-stream data. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-2 Freescale Semiconductor Video Codec (Video_Codec) Video Codec module mainly includes two hardware components: • Video Codec Processor: It is the heart of video codec processing. It supports multiple video processing standard, and integrates encoding and decoding function together with 32-bit AXI interface. • Video Codec Interface: Composed of two parts, one responds to bus protocol transfers between 32-bit AXI bus interface and three 32-bit AHB-Lite master bus interfaces (two read channels and one write channel). The other responds to bus protocol transfers between 32-bit APB bus and IP bus. Encoder and decoder processing share data-paths in the Video Codec module. There is an embedded BIT processor which is used to control the hardware sequence and as well as bitstream processing. The whole encoding or decoding is controlled by the firmware running on BIT processor in Video Codec. The host processor only need to access the Video Codec registers for initializing the Video Codec or setting frame parameters during the encoding/decoding frame gap. The Video Codec module has 3 clock domains: IP bus clock, video codec core clock, and the AHB bus clock. The Video Codec Processing IP core clock is asynchronous to AHB clock and IP clock. All sequential logic use only rising edge of clocks. 40.3 40.3.1 Clock Domain and Reset Clocks There are three clock domains in Video Codec: • AHB bus clock domain (hclk): Controls all AHB or AXI bus related functions. Maximum frequency is 133 MHz. The hclk is derived from PLL Clock Reset module. • Codec core clock domain (cclk): This is the master clock for the video codec. It controls all video codec encoding/decoding functionality, at a maximum frequency of 133 MHz. The actual value of core clock is dependent upon application use case. • IP bus clock domain (ipg_clk_s): Controls Video Codec registers read/write function, with a maximum frequency of 66.5 MHz. ipg_clk_s is a gated clock of IP clock (ipg_clk) with ips_module_en, it is turned off when there is no registers read/write for power saving. Only positive edge clocks is used in Video Codec design. All clock domains are asynchronous to the others. The Video Codec Processor uses all the three clock domains because it is needed for AXI signal generation, functional calculation, and APB bus configuration. The Video Codec interface clock belongs to AHB clock domain and IP bus clock domain, because they are related to AHB and AXI, IP and APB bus protocol transfers. 40.3.2 Reset Corresponding to the three clock domains, there are three reset signals in Video Codec module, active low. • AHB bus reset: used in AHB bus interface. Corresponding clock is hclk. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-3 Video Codec (Video_Codec) • • Codec core reset: used in codec accelerating hardware. Corresponding clock is cclk. IP bus reset: used in IP bus interface. Corresponding clock is ipg_clk. The number of cycles for each reset signal must be at least 8 cycles. The Video Codec uses an internal reset controller for feature software reset from the BIT processor. If any of the Video Codec blocks, with the exception of BIT processor is needed to reset (software reset), the host processor can enable this software reset by setting the software reset register through Video Codec API. The BIT processor cannot be reset by this software reset scheme, because the reset signal of BIT processor is connected directly to an external reset signal. If reset occurs when the Video Codec is processing a transaction through AHB bus, there is no guarantee that AHB bus will complete the transaction normally, since the Video Codec will be reset. If there are any corrupted data in memory, it can be discarded by software. Basically, if the host processor needs to issue a reset, it must check to ensure that there is no transaction on AHB bus between Video Codec and external AHB bus interface. In general, the AHB bus is free of Video Codec transactions after one frame of decoding/encoding is completed. The start of next frame processing requires software initiation. NOTE Both AHB read channels only allows read access, its corresponding AHB master bus has no hwdata signal, and hwrite is connected to ‘0’. Similarly, AHB write channel only allow write access, its corresponding AHB master bus has no hrdata signal, and hwrite is connected to ‘1’. 40.4 Memory Map and Register Definition The Video Codec registers are all 32-bit wide and only support 32-bit aligned read/write operations. Video Codec registers are grouped into several regions corresponding to different codec processing stages. The registers are used for codec processing configuration and control. They can only be accessed through IP bus interface. 40.4.1 Memory Map Video Codec module includes several internal register address map space, as shown in Table 40-1. The Video Codec module uses 0x10023000–0x10023FFF memory space as register mapping in i.MX27 system. The Video Codec module registers are divided into two categories. • Address 0x1002_3000–0x1002_30FC (64 registers address space) are hardware registers. These registers have reset values and their functions are fixed (can not be configurable). • Address 0x1002_3100–0x1002_31FC (64 registers address space) are software registers. They have no reset values and are configurable by internal BIT processor. So their definitions are not provided here. They can be used as general parameter registers between host and BIT processor. — The first 32 parameter registers (address 0x1002_3100–0x1002_317C) are used as static parameters. The meaning and functions of these registers are not changed regardless of the run commands used. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-4 Freescale Semiconductor Video Codec (Video_Codec) — The second 32 parameter registers (address 0x1002_3180–0x1002_31FC) are used as temporal parameters. The meaning and functions of these registers may be changed for each run commands. The memory map for the hardware registers of Video Codec is shown in Table 40-1. Table 40-1. Video Codec Hardware Register Memory Map Address 0xBASE_3000 (CodeRun) 0xBASE_3004 (CodeDown) 0xBASE_3008 (HostIntReq) 0xBASE_300C (BitIntClear) 0xBASE_3010 (BitIntSts) 0xBASE_3014 (BitCodeReset) 0xBASE_3018 (BitCurPc) Register BIT Processor run start BIT Boot Code Download Data register Host Interrupt Request to BIT BIT Interrupt Clear BIT Interrupt Status BIT Code Reset BIT Current PC Access W W W W R W R — Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 — Section/Page 40.4.3.1/40-7 40.4.3.2/40-8 40.4.3.3/40-8 40.4.3.4/40-9 40.4.3.5/40-10 40.4.3.6/40-10 40.4.3.7/40-11 — 0xBASE_301C–0xBASE_30FC Reserved 40.4.2 Register Summary The conventions in Figure 40-2 and Figure 40-2 serve as a key for the register summary and individual register diagrams. Always reads 1 1 Always reads 0 0 Write 1 BIT Self-clear 0 R/W BIT Read- BIT Writebit BIT bit only bit only bit BIT to clear w1c N/A Figure 40-2. Key to Register Fields Table 40-2 provides a key for register figures and tables and the register summary. Table 40-2. Register Conventions Convention Description Depending on its placement in the read or write row, indicates that the bit is not readable or not writable. FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written. Register Field Types R W R/W rwm w1c Read only. Writing this bit has no effect. Write only. Standard read/write bit. Only software can change the bit’s value (other than a hardware reset). A read/write bit that may be modified by a hardware in some fashion other than by a reset. Write one to clear. A status bit that can be read, and is cleared by writing a one. Self-clearing bit Writing a one has some effect on the module, but it always reads as zero. (Previously designated slfclr) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-5 Video Codec (Video_Codec) Table 40-2. Register Conventions (continued) Convention Description Reset Values 0 1 — u [signal_name] Resets to zero. Resets to one. Undefined at reset. Unaffected by reset. Reset value is determined by polarity of indicated signal. The brief Video Codec hardware register summary is shown in Table 40-3. Table 40-3. Video Codec Hardware Register Summary Name R 0xBASE_3000 W (CodeRun) R W R 0xBASE_3004 W (CodeDown) R W R 0xBASE_3008 W (HostIntReq) R W R 0xBASE_300C W (BitIntClear) R W R 0xBASE_3010 W (BitIntSts) R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CodeAddr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CodeRun CodeData 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntReq 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntClear 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntSts MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-6 Freescale Semiconductor Video Codec (Video_Codec) Table 40-3. Video Codec Hardware Register Summary (continued) Name R 0xBASE_3014 W (BitCodeReset) R W R 0xBASE_3018 W (BitCurPc) R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CodeReset 0 0 0 CurPc 40.4.3 Register Descriptions This section consists of Video Codec hardware register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. 40.4.3.1 Video Codec Code Run Register (CodeRun) See Figure 40-3 for an illustration of valid bits in Video Codec Code Run Register and Table 40-4 for descriptions of the bit fields in the register. 0xBASE_3000 (CodeRun) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Write-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Code Run 0 Figure 40-3. Video Codec Code Run Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-7 Video Codec (Video_Codec) Table 40-4. Video Codec Code Run Register Field Descriptions Field 31–1 0 Reserved CodeRun. BIT processor run start bit. 0 BIT Processor stop execution 1 BIT Processor start execution Description 40.4.3.2 Video Codec BIT Boot Code Download Data Register (CodeDown) See Figure 40-4 for an illustration of valid bits in Video Codec BIT Boot Code Download Data Register and Table 40-5 for descriptions of the bit fields in the register. 0xBASE_3004 (CodeDown) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Write-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 CodeAddr 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 CodeData 0 0 0 0 0 0 0 0 0 Figure 40-4. Video Codec BIT Boot Code Download Data Register Table 40-5. Video Codec BIT Boot Code Download Data Register Field Descriptions Field 31–29 28–16 15–0 Reserved CodeAddr[12:0]. Download address of Video Codec BIT boot code, which is Video Codec internal address of BIT processor. CodeData[15:0]. Download data of Video Codec BIT boot code. Description 40.4.3.3 Video Codec Host Interrupt Request Register (HostIntReq) See Figure 40-5 for an illustration of valid bits in Video Codec Host Interrupt Request Register and Table 40-6 for descriptions of the bit fields in the register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-8 Freescale Semiconductor Video Codec (Video_Codec) 0xBASE_3008 (HostIntReq) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Write-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntReq 0 Figure 40-5. Video Codec Host Interrupt Request Register Table 40-6. Video Codec Host Interrupt Request Register Field Descriptions Field 31–1 0 Reserved IntReq. The host interrupt request bit. 0 No host interrupt is requested. 1 The host processor request interrupt to the BIT processor. Description 40.4.3.4 Video Codec BIT Interrupt Clear Register (BitIntClear) See Figure 40-6 for an illustration of valid bits in Video Codec BIT Interrupt Clear Register and Table 40-7 for descriptions of the bit fields in the register. 0xBASE_300C (BitIntClear) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User Write-Only 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntClear 0 Figure 40-6. Video Codec BIT Interrupt Clear Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-9 Video Codec (Video_Codec) Table 40-7. Video Codec BIT Interrupt Clear Register Field Descriptions Field 31–1 0 Reserved IntClear. BIT interrupt clear bit. 0 No operation is issued. 1 Clear the BIT interrupt to the host. Description 40.4.3.5 Video Codec BIT Interrupt Status Register (BitIntSts) See Figure 40-7 for an illustration of valid bits in Video Codec BIT Interrupt Status Register and Table 40-8 for descriptions of the bit fields in the register. 0xBASE_3010 (BitIntSts) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User Read-Only 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IntSts 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 40-7. Video Codec BIT Interrupt Status Register Table 40-8. Video Codec BIT Interrupt Status Register Field Descriptions Field 31–1 0 Reserved IntSts. BIT interrupt status bit. 0 No BIT interrupt is asserted. 1 The BIT interrupt is asserted to the host. It is cleared when the host processor write “1” to BitIntClear register. Description 40.4.3.6 Video Codec BIT Code Reset Register (BitCodeReset) See Figure 40-8 for an illustration of valid bits in Video Codec BIT Code Reset Register and Table 40-9 for descriptions of the bit fields in the register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-10 Freescale Semiconductor Video Codec (Video_Codec) 0xBASE_3014 (BitCodeReset) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Write-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Code Reset 0 Figure 40-8. Video Codec BIT Code Reset Register Table 40-9. Video Codec BIT Code Reset Register Field Descriptions Field 31–1 0 Reserved CodeReset. BIT code reset bit. 0 No operation is issued. 1 The program counter of BIT processor is set to “0”, BIT processor restart at initial routine. Description 40.4.3.7 Video Codec BIT Current PC Register (BitCurPc) See Figure 40-9 for an illustration of valid bits in Video Codec BIT Current PC Register and Table 40-10 for descriptions of the bit fields in the register. 0xBASE_3018 (BitCurPc) 31 30 29 28 27 26 25 24 23 22 21 20 19 Access: User Read-Only 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 CurPc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 40-9. Video Codec BIT Current PC Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-11 Video Codec (Video_Codec) Table 40-10. Video Codec BIT Current PC Register Field Descriptions Field 31–14 13–0 Reserved CurPc[13:0]. BIT current PC value. Returns the current program counter of BIT processor by reading this register. Description 40.5 Functional Description The Video Codec module is a high-performance multi-standard video processing unit in the system which supports H.263P3, MPEG-4 SP, and H.264 BP. 40.5.1 Video Codec Architecture The Video Codec module mainly includes two hardware components: Video Codec Processing IP and Vide Codec Gasket. Video Codec Processing IP is optimized to reduce logic gate count with many sharing parts of sub-modules for multi-standard. It is responsible for bitstream parsing and frame data coding. It mainly consists an embedded 16bit BIT processor, codec hardware accelerator,and bus arbiter/interface. BIT processor is in charge of parsing/coding the bitstream/image, controlling video codec process. Hardware accelerators are designed to speed up bitstream/image processing. Video Codec Gasket converts AMBA APB3 bus to IP Sky Blue bus and AXI bus to AHB bus. Refer to Figure 40-1 for the block diagram of Video Codec. Below sections describe the main function of Video Codec Processing IP components. 40.5.1.1 Embedded BIT processor The embedded BIT processor is 16-bit programmable processor which is highly optimized to handle bitstream data. It is used for parsing or forming bitstream. It includes some hardware accelerators to speed up the bitstream processing. In addition to handling bitstream, the BIT processor controls video codec hardware and communicates with host processor through IP Sky Blue bus and AXI bus interface. Before running codec, BIT firmware common routine should be downloaded into embedded program memory through system level control. For codec programing data, BIT processor read it from a specified region of system external memory through AHB bus interface. The region is specified by application settings. 40.5.1.2 Codec Hardware Accelerator All video codec processing, except handling coefficients for VLC and VLD, are implemented in hardware accelerator. Codec hardware accelerator is designed to reduce logic gate count by sharing parts of sub-modules for multi-standard video encoding and decoding. Codec hardware accelerator supports rotation/mirroring function. In case of rotating/mirroring source image during encoding, rotated image is encoded directly without writing it to any memory space. So no additional bandwidth is needed for the processing. However, the rotation/mirroring process in decoding process requires additional bandwidth because decoding has to re-use the un-rotated image for decoding the next image. So the rotated image is written to other memory space. In this scheme, the display I/F has MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-12 Freescale Semiconductor Video Codec (Video_Codec) not to change memory space for displaying the decoded image because subsequent rotated image is written to the same space. The rotator modules support 8-types mode of 90 x n degree (n=0, 1, 2, 3) rotating and mirroring. Table 40-11 shows the supported rotating/mirroring lists and some possible combinations of rotating and mirroring. Figure 40-10 gives architecture diagram of pre/post rotation/mirroring module. Table 40-11. Rotation and Mirroring Mode Image Description Original Image (No rotating/mirroring) Example Image Size: 720x480 Rotate Left 90 (Rotate Right 270) Example Image Size: 480x720 Rotate Left 180 (Rotate Right180) Example Image Size: 720x480 Rotate Left 270 (Rotate Right 90) Example Image Size: 480x720 Horizontal mirroring Example Image Size: 720x480 Vertical mirroring Example Image Size: 720x480 Horizontal mirroring and rotate right 90 Example Image Size: 480x720 Horizontal mirroring and rotate left 90 Example Image Size: 480x720 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-13 Video Codec (Video_Codec) Table 40-11. Rotation and Mirroring Mode Image Description Rotate right 90 and horizontal mirroring Example image size: 480x720 Rotate left 90 and horizontal mirroring Example image size: 480x720 External Pre-Processor Source Frame Buffer Pre-Rotation/ Mirroring Reconstruction Frame Buffer External Memory Video Codec Reference Frame Buffer Video Codec Reconstruction Frame Buffer External Pre-Processor Display Frame Buffer Post-Rotation/ Mirroring External Memory Figure 40-10. Rotation and Mirroring Data Flow 40.5.2 Interrupts There is one interrupt signal output from Video Codec. Basically, this interrupt is used to indicate encoding/decoding processing state. It is generated when Video Codec interrupt is enabled and as well as the interrupt condition is met. The interrupt signal is active high and retains till the host processor clears it by writing “1” to the interrupt clear register. This signal is synchronized to the positive edge of hclk. When getting frame completion interrupt, the software needs to set the parameters for the processing of the next frame and start the BIT processor again. The parameters mainly include source/destination frame MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-14 Freescale Semiconductor Video Codec (Video_Codec) buffer base address. It can be different from previous frame buffer since the previous completed frame of data may be needed for other image block like display module or post-processing module in system. Basically, operation responding to interrupt is dependent upon the application. For example, software can send the decoded frame to EMMA for post-processing, or transfer the encoded bitstream for storage, at the same time software could store the next bitstream to be processed to the external memory before starting a new encoding processing. 40.6 Initialization Information Video Codec module embedded BIT processor is 16-bit programmable processor, which is highly optimized to handle bitstream/image data. In addition to processing bitstream/pixel data, BIT processor also controls the communicates between Video Codec module and system. 40.7 Application Information Figure 40-11 shows roles of BIT processor and codec hardware accelerator, and how to interface with application software. At the frame level, a host processor communicates with Video Codec through provided APIs. To give Video Codec more flexibility and debugging capability, all processes related to the bitstream are assigned to the BIT processor. Host Processor Through Video Codec APIs Host interface (IP bus) Receiving parameters and command from host processor. Sending status to host processor. Parsing/forming bitstream (VLD/VLC)/w hardware acceleration. Bit-rate control, Video codec control BIT Processor External Memory AHB bus codec except bitstream parsing processing Codec hardware accelerator Figure 40-11. Video Codec Interface with Application Software Diagram 40.7.1 Video Codec Processing Control This section describes how BIT processor controls video codec processing and communicates with the host. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-15 Video Codec (Video_Codec) 40.7.1.1 Video Codec Processing Flow The Video Codec can handle a maximum of 4 processes simultaneously. Each process can have a different format—MPEG-4, H.263P3, H.264, and different codec process—encoding or decoding. Figure 40-12 shows a simplified state diagram for running the codec process. Idle Create and initialize N processes, process[0–N-1] If process[j] is available? Where j=0...N-1 Yes Yes Run process[j] No No Wait till the process[j] for 1 frame is finished Yes Users want to quit process[j]? Yes Quit process[j] All processes are closed? Figure 40-12. Codec Process State Diagram Each codec process consists of three categories: • Create processes: Software creates and configures processes. • Running processes: At a proper time instance, software will begin a specific process. The proper time instance means when the codec is in idle state and image to be encoded or bitstream to be decoded is ready in the external memory. • Quit Processes: Software can quit a specific process MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-16 Freescale Semiconductor Video Codec (Video_Codec) If more than one process are ready to run, each process must be assigned to different process ID—RunIndex, which is range from 0 to 3. Basically, the ID is assigned based on the order of creation. For example, when 1 MPEG-4 Decoding + 1 H.264 Decoding + 1 H.263 Decoding + 1 H.264 Encoding are running simultaneously, MPEG-4 Decoding is assigned to process index “0”, H.264 Decoding is assigned to process index “1”, H.263 Decoding is assigned to index “2”, and H.264 Encoding is assigned to process index “3”. There is no priority rules for executing processes, after creating all processes at the initialization step, host enables BIT processor to execute process specified with the RunIndex. All processes are executed in time-division like mechanism, after one process finishes encoding or decoding a frame, another process then can be executed. In conjunction with the process ID, RunCodStd needs to be set, to define which coding standard is used with the created process and whether the created process will encode an image or decode a bitstream. Table 40-12 shows the dedicated RunCodStd value for each coding standard. All this can be done through Video Codec API. Table 40-12. RunCodStd Register Value for Coding Standard Coding Standard MPEG-4/H.263 P3 Decoding MPEG-4/H.263 P3 Encoding H.264 Decoding H.264 Encoding RunCodStd 0 1 2 3 40.7.1.2 Video Codec Processing Finish Detection The Video Codec module raises interrupt signal or busy state when frame processing command is finished. So there are three ways of detecting whether decoding/encoding of a frame is finished: • Polling Video Codec interrupt status register. Interrupt status register indicates interrupt is generated. • Polling Video Codec busy status register. During decoding/encoding process, as soon as the busy status becomes 0, decoding/encoding processing is finished. • Capture interrupt signal from system level, respond to interrupt request within the system interrupt service routine. NOTE Interrupt status can be cleared by writing 1 to interrupt clear register. Busy state is self cleared after read out. 40.7.1.3 Video Codec Processing Flow Example Figure 40-13 shows a process flow example for decoding an H.264 bitstream and encoding images as H.264 format simultaneously. At first both decoding and encoding process are created and initialized, then each process is executed with PICTURE_RUN command alternately. More details are described as below. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-17 Video Codec (Video_Codec) Start BIT Code Download Set Initial Parameters Set SEQ_INIT Parameters Set PICTURE_RUN Parameters SEQ_INIT Command RunIndex = 1 RunCodStd = 3(AVC_ENC) RunCommand = 1 Wait BusyFlag = 0 PICTURE_RUN Command RunIndex = 1 RunCodStd = 3 RunCommand = 3 BIT Run Start Wait BusyFlag = 0 Wait BusyFlag = 0 SEQ_END Command RunIndex = 0 SEQ_INIT Command RunIndex = 0 RunCodStd = 2(AVC_DEC) RunCommand = 1 PICTURE_RUN Command RunIndex = 0 RunCodStd = 2 RunCommand = 3 RunCodStd = 2 RunCommand = 2 Set SEQ_INIT Parameters Set PICTURE_RUN Parameters Wait BusyFlag = 0 Wait BusyFlag = 0 Read Return Parameters Wait BusyFlag = 0 Check Return Status SEQ_END Command RunIndex = 1 RunCodStd = 3 RunCommand = 2 Wait BusyFlag = 0 End Figure 40-13. H.264 Codec Process Flow Example *RunCommand = 1 (SEQ_INIT); RunCommand = 2 (SEQ_END); RunCommand = 3 (PICTURE_RUN) 1. Initialize the Video Codec — BIT Code Download: Load BIT Processor firmware to memory. — Set Initial Parameters: General configuration for BIT processor, setting working buffer base address, BIT Code memory address, bitstream buffer control and so on. — BIT Run Start: Run BIT processor to initialize Video Codec. 2. Create and initialize an H.264 decoding process — Set SEQ_INIT parameters: Configure base address and size of bitstream buffer, base address of frame buffers and so on. — Run SEQ_INIT command: Initiate an H.264 decoding process. — Wait BusyFlag=0: Wait BIT processor completes SEQ_INIT command execution. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-18 Freescale Semiconductor Video Codec (Video_Codec) 3. 4. 5. 6. 7. — Read Return Parameters: Read the features of decoded bitstream, such as the picture resolution and number of reference frames through the Video Codec API. In this way, the host can prepare the required frame buffers. Create and initialize an H.264 encoding process — The flow is similar to the H.264 decoding process except the stage of Read Return Parameters, the encoding frame buffer size can be configured according to the feature of video clips. Run the H.264 decoding process — Set PICTURE_RUN Parameters: Configure the frame destination address. — Run PICTURE_RUN command: Start the H.264 decoding process. — Wait BusyFlag=0: Wait the BIT processor completes PICTURE_RUN command execution. It also means one frame process is finished. The decoded frame can be sent to the EMMA for post-processing. The actual operation is dependant on the application. Run the H.264 encoding process — The flow is similar to the H.264 decoding process. The encoding process should configure frame source address in addition to destination address. Execute step 4 and step 5 alternately. — Before running decoding process, the host should load new bitstream to the bitstream buffer if it is empty, and update the frame destination address according to the application. As for encoding, the next frame should be ready in external memory before the process is run. Stop the codec process — Run SEQ_END command to each process to terminate it. Basically, the process flow for encoding and decoding is similar, though it may have minor change for different firmware version. 40.7.1.4 Frame Buffer This section describes the memory map of the frame buffer and size requirement. Frame buffer is specified with the base address and stride line. A complete image consists of Y, U and V component. Therefore, an image frame has 3 component buffers for each component. Stride line is the width of the luminance component buffer in pixel unit and must be multiple of 8. Stride line for chrominance component buffer is a half of the luminance component. Video Codec module supports 11-bit stride line configuration which can be larger or equal to the width of image frame. The relationship between image size and stride line is shown in Figure 40-14. YUV components are stored line-by-line. U component in one image frame is stored adjoining Y component of the same frame. V component follows U component. Next frame data follows previous frame YUV component data. The relationship between image size and stride line also decides the memory map distribution of codec image data in external memory space. Between every YUV component line data, there is some optional unused memory space which size is (Stride_Line - Image_Width) Byte. It is greater than or equal to ZERO byte, and can not be larger than (2^11 - Image_Width) (because Stride_Line is 11bit width). MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-19 Video Codec (Video_Codec) Stride Line - SL bytes Base Address for Y frame Frame Width - FW Frame Height - FH unused Y memory space SL/2 Base Address for U frame FW/2 Base Address for V frame SL/2 FW/2 FH/2 U FH/2 V Figure 40-14. Frame Buffer Configuration Figure 40-15 shows the memory map of frame buffer. For V frame buffer, memory map is the same as U frame buffer except the base address. Video Codec supports both little and big endian system. It means Y(0,0) in Figure 40-15 could be located in the bit[31:24]. User can specify the endianness through Video Codec API. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-20 Freescale Semiconductor Video Codec (Video_Codec) 31 Y(0,3) Y(0,7) 24 23 Y(0,2) Y(0,6) 16 15 Y(0,1) Y(0,5) 8 7 Y(0,0) Y(0,4) 0 Y Frame Buffer Base Address: EBA_Y start of Y frame row 0 Other Y data in the current row Y(0,FW-1) Y(0,FW-2) Y(0,FW-3) Y(0,FW-4) end of valid data in Y frame row 0 EBA_Y+SL Optional unused memory Y(1,3) Y(1,2) Y(1,1) Y(1,0) start of Y frame row 1 Other Y data in the current frame EBA_Y+SL*(FH-1)+(FW-4) Y(FH-1,FW-1) Y(FH-1,FW-2) Y(FH-1,FW-3) Y(FH-1,FW-4) Optional unused memory end of valid data in Y frame row FH U Frame Buffer Base Address: EBA_U U(0,3) U(0,2) U(0,1) U(0,0) start of U frame, start of row 0 Other U data in the current row U(0,FW/2-1) U(0,FW/2-2) U(0,FW/2-3) U(0,FW/2-4) end of valid data in U frame row 0 EBA_U+SL/2 U(1,0) start of U frame row 1 EBA_U+SL/2*(FH/2-1)+(FW/2-4) U(FH/2-1, FW/2-4) end of valid data in U frame row FH/2 Optional unused memory U(1,3) U(1,2) U(1,1) Other U data in the current frame U(FH/2-1, FW/2-1) U(FH/2-1, FW/2-2) U(FH/2-1, FW/2-3) Optional unused memory FH: Frame Height SL: Stride Line FW: Frame Width Figure 40-15. Frame Buffer Address Map in Little Endian Table 40-13 also shows the memory requirement in case of QCIF/CIF/VGA resolution image. In the case of H.264, the required size for the reference frame is dependent on the level being supported. Video Codec supports up to H.264 level 3.0, which the maximum decoded picture buffer size is defined as 3037.5 MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-21 Video Codec (Video_Codec) Kbytes in the standard. To support H.264 CIF at level 3.0, 2524 Kbyte is needed if 16 reference frames are used. Table 40-13. Frame Buffer Requirement MPEG-4 Encoder QCIF Reference Frames Current Frames Reconstruction Frames Display Frame Total Frames Picture Size1 Total Frame Size CIF Reference Frames Current Frames Reconstruction Frames Display Frame Total Frames Picture Size Total Frame Size VGA Reference Frames Current Frames Reconstruction Frames Display Frame Total Frames Picture Size Total Frame Size 1 1 1 0 3 37 Kbyte 111 Kbyte 1 1 1 0 3 148 Kbyte 444 Kbytes 1 1 1 0 3 450 Kbytes 1350 Kbytes MEPG-4 Decoder 1 0 1 1 3 37 Kbyte 111 Kbyte 1 0 1 1 3 148 Kbyte 444 Kbytes 1 0 1 1 3 450 Kbytes 1350 Kbytes H.264 Encoder 1 1 2 0 4 37 Kbyte 148 Kbyte 1 1 2 0 4 148 Kbyte 592 Kbytes 1 1 2 0 4 450 Kbytes 1800 Kbytes H.264 Decoder 16 0 1 1 18 37 Kbyte 666 Kbyte 2376 Kbyte 0 1 1 2 148 Kbyte 2672 Kbytes 3037.5 Kbytes 0 1 1 2 450 Kbytes 3937.5 Kbytes 1 The Picture Size is the minimum size of one frame buffer with assumption that the picture is YUV 4:2:0 format and the stride line is equal to frame width. 40.7.1.5 BIT Processor Program Memory At the initialization stage of Video Codec, host processor must download common routine to BIT processor. After initialization, BIT processor loads a program corresponding to the activated standard. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-22 Freescale Semiconductor Video Codec (Video_Codec) There are total 65 Kbyte size for current version of BIT firmware to support three standards (MPEG-4, H.263 P3 and H.264), including 1 Kbyte common routine. 40.7.1.6 Working Buffer Besides buffers for frames and firmware, additional working buffer for intermediate data from BIT processor and codec processing is needed. The buffers are such as the reconstructed pixel row buffer for MPEG-4 AC/DC prediction or H.264 intra prediction, context saving buffer for running multiple processes, bitstream re-ordering buffer for MPEG-4 data partition or H.264 FMO/ASO and so on. The required working buffer size varies according to codec size, standard and capability. For example, AC/DC prediction buffer size is determined by picture width and the maximum bitstream re-ordering buffer for data partition is determined by the maximum bitstream size of one picture. Working buffer size may change for different firmware version. The current version of firmware requires 256 Kbytes for working buffer when decodes/encodes 720 x 576 (D1 size) up to 10 Mbps. Its size can be set through Video Codec API. The detailed working buffer is organized as Table 40-14. Table 40-14. Working Buffer Organization Working Buffer static Buffer Description Size Used commonly in whole processes/codecs 48 Kbytes 16 Kbytes 16 Kbytes 208 Kbytes 72 Kbytes temp_pic for MPEG4 AC/DC prediction buffer and bitstream decoding reordering buffer for data partition. temp_pic for MPEG4 AC/DC prediction buffer and bitstream encoding reordering buffer for data partition. temp_pic for AVC decoding temp_pic for AVC encoding Intra-prediction buffer, FMO grout status buffer, and slice information buffer Intra-prediction buffer 40.7.1.7 Bitstream Buffer Host processor has to assign buffers for bitstream on a per instance basis. If Video Codec handles N-bitstreams simultaneously in an application, the host should assign N bitstream buffers, and specify the base address and size. The External bitstream buffer is “ring buffer” type. Start address of ring buffer and buffer size must be written by host to BIT processor. The current read or write address of ring buffer is automatically wrapped-around by firmware. In decoding case, host writes bitstream to be decoded then BIT processor reads the bitstream. In this case, the bitstream overwriting or underflow may occur and if it occurs, decoding will fail. To prevent overwriting or underflow, current bitstream read/write pointer must be exchanged between the host and BIT processor. BIT processor writes current read pointer of ring buffer to internal register and host must write current write pointer of ring buffer to internal register. BIT processor checks the bit buffer empty (underflow) status by comparing current read pointer and write pointer. If no more bitstream data is available to be decoded (buffer empty status), BIT processor stops bitstream decoding to prevent mis-reading the MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-23 Video Codec (Video_Codec) bitstream and waits until host writes more bitstream data and updates write pointer. Host must check the current read pointer and write pointer before writing more bitstream data to ring buffer to prevent overwriting bitstream data. Bitstream data is read from the external bitstream buffer by 512 bytes. The read pointer or write pointer is increased by 512 bytes. 40.7.1.8 Buffer Requirement Summary Table 40-15 shows a summary of buffer requirement for each decoding instance, where bitstream buffer size is not considered because the size is not limited. The total size may change for different firmware version. Except BIT processor program memory, other kinds of buffer has to be assigned on a per instance basis. The overall buffer size for a multi-party call application is nearly the sum of each instanced decoding. Table 40-15. Summary of Buffer Requirement MPEG-4 Encoder QCIF Frames Size Program Size Working Buffer Total CIF Frames Size Program Size Working Buffer Total VGA Frames Size Program Size Working Buffer Total 64 Kbytes 1479 Kbytes 64 Kbytes 573 Kbytes 1350 Kbytes 64 Kbytes 240 Kbytes 444 Kbytes 111 Kbytes MEPG-4 Decoder 111 Kbytes H.264 Encoder 148 Kbytes H.264 Decoder 666 Kbytes 65 Kbytes 64 Kbytes 240 Kbytes 444 Kbytes 120 Kbytes 333 Kbytes 592 Kbytes 256 Kbytes 987 Kbytes 2672 Kbytes 65 Kbytes 64 Kbytes 573 Kbytes 1350 Kbytes 120 Kbytes 777 Kbytes 1800 Kbytes 256 Kbytes 2993 Kbytes 3937.5 Kbytes 65 Kbytes 64 Kbytes 1479 Kbytes 120 Kbytes 1985 Kbytes 256 Kbytes 4258.5 Kbytes Except the BIT processor program memory, other kinds of buffer has to be assigned on a per instance basis. Therefore the overall buffer size for a multi-party call application is nearly the sum of each instanced codec. 40.7.2 Application Using Cases Video Codec module allows 4 channels to encode/decode simultaneously. That extends i.MX27 video processing application fields, and make it possible for multi-channel bitstream/image processing. For example, it can encode captured image in one channel, and decode other 3 channels bitstream at the same time, as shown in Figure 40-16. In Figure 40-16, gray rectangle represents the bitstream data. All codec channels image/bitstream can be encoded/decoded by different codec standard, like one image is encoded MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-24 Freescale Semiconductor Video Codec (Video_Codec) to H264/AVC bitstream, and one channel H264/AVC bitstream, one channel MPEG4 bitstream, one channel H263 bitstream are decoded separately. Video Codec Module External Memory Image after PrP External Memory Bitstream1 External Memory Bitstream2 External Memory Bitstream3 Mirror veri. External memory Image before PP Decode Rotate right 90 degree External memory Image before PP Can be combined during display Decode Mirror hori. External memory Image before PP Rotate left 90 degree External memory for Transfer for display Encode Decode Figure 40-16. One of Application Using Case: One Channel Encoding and Three Channels Decoding MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 40-25 Video Codec (Video_Codec) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 40-26 Freescale Semiconductor Chapter 41 enhanced Multimedia Accelerator Light (eMMA_lt) 41.1 Introduction The enhanced MultiMedia Accelerator Light (eMMA_lt) consists of the video Pre-Processor (PrP) and Post-Processor (PP), which provide video acceleration and off-load the CPU from computation intensive tasks. The PrP and PP can be used for generic video pre- and post-processing, such as scaling, resizing, and color space conversions. 41.1.1 • Features • Pre-Processor: — Data input: – System memory – Private DMA between CMOS Sensor Interface module and Pre-Processor — Data input formats: – Arbitrarily formatted RGB pixels (16 or 32 bits) – YUV 4:2:2 (Pixel interleaved) – YUV 4:2:0 (IYUV, YV12) — Input image size: 32 × 32 to 2044 × 2044 — Image scaling: – Programmable independent CH-1 and CH-2 resizer. Can program to be in cascade or parallel. – Each resizer supports downscaling ratios from 1:1 to 8:1 in fractional steps. — Channel-1 output data format – Channel 1 – RGB 16 and 32 bpp – YUV 4:2:2 (YUYV, YVYU, UYVY, VYUY) — Channel-2 output data format – YUV 4:2:2 (YUYV) – YUV 4:4:4 – YUV 4:2:0 (IYUV, YV12) – RGB data and YUV data format can be generated concurrently — 32/64-bit AHB bus Post-Processor MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-1 enhanced Multimedia Accelerator Light (eMMA_lt) — Input data: – From system memory — Input format: – YUV 4:2:0 (IYUV, YV12) — Image Size: 32 × 32 to 2044 × 2044 — Output format: – YUV 4:2:2 (YUYV) – RGB16 and RGB32 bpp — Image Resize – Upscaling ratios ranging from 1:1 to 1:4 in fractional steps – Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1 – Ratios provide scaling between QCIF, CIF, QVGA (320 × 240, 240 × 320) 41.2 eMMA_lt Architecture Figure 41-1 shows the block diagram of eMMA_lt. The eMMA_lt consists of the Pre-Processor and Post-Processor modules. Each module has individual control and configuration registers which are accessed via the IP interface and are capable of bus mastering the AMBA bus to independently access system memory without any CPU intervention. This allows each module to be used independently of each other and enables the Pre-Processor and Post-Processor modules to provide acceleration features for other software codec implementations and image processing software. A 32 bit to 64 bit AHB gasket is used to convert AHB bus from 32-bit to 64-bit protocol. A bypass function is implemented to bypass this 64 bit gasket if it is not needed. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-2 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) CSI CSI-PrP Dedicated Link 32 I P B U S 32 32 Pre-Processor 64bit_gasket 32 or 64 Register and Control Configuration I N T E R F A C E Image Memory Access 32 Post-Processor 32 Figure 41-1. eMMA_lt Block Diagram 41.2.1 Pre-Processor (PrP) The Pre-Processor (PrP) module accepts input from main memory via a 64-bit AHB port directly from EMI or from the dedicated link that connects it to camera input via the CMOS Sensor Interface (CSI) module. The PrP can be operated in two modes; single or continuous frame (loop) mode. In single frame mode, a single frame is processed either from memory or from the dedicated CSI-PrP link. In this mode, the PrP must be re-enabled each time a frame is to be processed. This mode is suitable for still image capture, processing and display and for very low frame rate operation. In continuous frame or loop mode, the PrP processes input frames from the dedicated CSI-PrP link continuously until it is disabled or an error occurs. The PrP has two output channels (Channel-1 and Channel-2) and both channels store processed frames to main memory. The output from Channel-1 is dedicated for display purposes and the output from Channel-2 for input to a hardware encoder (MPEG-4 Encoder module) or a software encoder or image compressor. The PrP resizes input frames from memory of from the CSI and performs color space conversion. 41.2.2 Post-Processor (PP) The Post-Processor module takes decoded frames from memory and performs additional processing to de-block, de-ring, resize, and color space convert the decoded frames for display. The decoded input can be either from the Decoder module or a software decoder module. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-3 enhanced Multimedia Accelerator Light (eMMA_lt) 41.2.3 64-Bit Gasket In order to connect PrP to a 64-bit AHB port of EMI, a 32-bit to 64-bit AHB protocol gasket is used to manage AHB signals between 32-bit master (PrP) and 64-bit AHB bus. In the event where 64 bit transfer is not required, a bypass function is implemented in the gasket to allow the PrP to ignore this 64 bit gasket and work as the original 32 bit AHB protocol. Figure 1-2 shows the basic structure of the eMMA-lt AHB 64-bit gasket with a bypass function. When the ahb64_sel signal is low the gasket is avoided. 0 eMMA_ahb64_Gasket From 32 bit Master To 32/64 bit bus 1 ahb64_sel 1 To 32 bit Master 0 From 32/64 bit bus ahb64_sel Figure 41-2. eMMA AHB 64-Bit Gasket with Bypass MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-4 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) 41.3 Post-Processor (PP) Data from Memory Quantizer Data to Memory Y Buffer (116x32) De-block CSC RGB BUFFER (128 × 32) UV Buffer (68x32) RGB BUFFER (128 × 32) YUV to RGB De-ring RESIZE BUFFER (64 x 24) Resize Coefficients Image Resize Programmable from 2:1 to 1:4, fixed 4:1. RESIZE BUFFER (64 × 24) Figure 41-3. Post-Processor (PP) Block Diagram The Post-Processor (PP) performs postprocessing functions after video decoding. The key modules in the PP are: De-block—Removes blocking artifacts while preserving natural edges in the images. Deblock processing is bypassed if not selected. De-ring—Removes ringing artifacts from decoded images caused by the truncation of high spatial frequencies. Subjective tests have shown that performing both de-ringing and de-blocking improves slightly the visual quality than performing de-blocking alone. De-ring processing is bypassed if not selected. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-5 enhanced Multimedia Accelerator Light (eMMA_lt) Image Resize—Scales input image to a different size—for example, from QCIF (176 × 144) to QVGA (320 × 240) to match the size of the display or to scale from one aspect ratio to another ratio—for example, from 1:1 to 4:3. It supports programmable resize ratios from 2:1 to 1:4, and a fixed 4:1. Horizontal resizing and vertical resizing are independent and can be set to different resizing ratios. Bilinear interpolation algorithm is implemented and used for both upscaling and downscaling—that is, two adjacent pixels are loaded and multiplied by respective weighting coefficients to produce an output pixel. The weighting coefficients for a particular resize ratio are calculated by software and preloaded into the resize coefficient table of the PP from which the resize block reads the coefficients to use. For example, the output samples for 3:5 bilinear interpolation can be calculated as follows: out[0] = in[0] out[1] = 2/5 * in[0] + 3/5 * in[1] out[2] = 4/5 * in[1] + 1/5 * in[2] out[3] = 1/5 * in[1] + 4/5 * in[2] out[4] = 3/5 * in[2] + 2/5 * in[3] The output samples for the 5:3 bilinear interpolation can be calculated as follows: out[0] = 2/3 * in[0] + 1/3 * in[1] out[1] = 0/3 * in[1] + 3/3 * in[2] out[2] = 1/3 * in[3] + 2/3 * in[4] A programmable resize engine is implemented in hardware, which reads instructions from the resize coefficient table (Register eMMA PP RESIZE COEF TABLE). An output pixel will be generated with the value (w1 * in1 + w2 * in2)/32 and the resize engine will then read in n new input pixels, where in1 and in2 are two adjacent pixels. If n is zero, then no new pixels are read and the in1 and in2 pixel values are reused. Each instruction in the table is in the form of (w1, n,o) where each coefficient (w1) is represented with 5 bits and n with 2 bits and ‘o’ in 1-bit. w2 is calculated as 32-w1. NOTE Coefficient value of 31 (5’b11111) is treated as 32 (6’b100000), consequently, coefficient values of 1 and 31 are not possible. The Table 41-1 and Table 41-2 show some example resize coefficients. Table 41-1. Resize Coefficients for 3:5 w1 1 2/5 4/5 w2 0 3/5 1/5 n 0 1 1 Right Coefficient 5’b11111 (32) 5’b01101 (13) 5’b11010 (26) Left Coefficient 5’b00000 (0) 5’b10011 (19) 5’b00110 (6) in1 in[0] in[0] in[1] in2 – in[1] in[2] Out in[0] 13/32 * in[0] + 19/32 * in[1] 26/32 * in[1] + 6/32 * in[2] MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-6 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-1. Resize Coefficients for 3:5 (continued) w1 1/5 3/5 w2 4/5 2/5 n 0 1 Right Coefficient 5’b00110 (6) 5’b10011 (19) Left Coefficient 5’b11010 (26) 5’b01101 (13) in1 in[1] in[2] in2 in[2] in[3] Out 6/32 * in[1] + 26/32 * in[2] 19/32 * in[2] + 13/32 * in[3] Table 41-2. Resize Coefficients for 5:3 w1 2/3 0 1/3 w2 1/3 1 2/3 n 1 2 2 Left Coefficient 5’b10101 (21) 5’b00000 (0) 5’b01011 (11) Right Coefficient 5’b01011 (11) 5’b11111 (32) 5’b10101 (21) in1 in[0] in[1] in[3] in2 in[1] in[2] in[4] Out 21/32 * in[0] + 11/32 * in[1] 0 * in[0] + 1 * in[1] 11/32 * in[0] + 21/32 * in[1] Table 41-3. Resize Coefficients for 4:1 w1 1/2 0 0 0 w2 1/2 0 0 0 n 1 1 1 1 Left Coefficient 5’b10000 (16) 5’b00000 (0) 5’b00000 (0) 5’b00000 (0) Right Coefficient 5’b10000 (16) 5’b00000 (0) 5’b00000 (0) 5’b00000 (0) in1 in[0] in[1] in[2] in[3] in2 in[1] in[2] in[3] in[4] Out 1/2 * in[0]+ 1/2 * in[1] — — — 41.3.1 Color Space Conversion (CSC) The color space conversion block converts input images from YUV to RGB color space needed for display. The CSC block is fully programmable. Equation used for YCbCr to RGB calculation: R = C0*(Y - X0) + C1*(Cr-128) G = C0*(Y - X0) - C2*(Cb-128) - C3*(Cr-128) B = C0*(Y - X0) + C4*(Cb-128) Equation used for YUV to RGB calculation: R = C0*(Y - X0) + C1*(U-128) G = C0*(Y - X0) - C2*(U-128) - C3*(V-128) B = C0*(Y - X0) + C4*(U-128) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-7 enhanced Multimedia Accelerator Light (eMMA_lt) X0, C0, C1, C2, C3 and C4 are coefficients that can be programmed through registers PP_CSC_COEF_0123 and PP_CSC_COEF_4X. C0[7:0] Range from 0 to 1.9921875 in steps of (1/128). C1[7:0] Range from 0 to 1.9921875 in steps of (1/128). C2[7:0] Range from 0 to 1.9921875 in steps of (1/128). C3[7:0] Range from 0 to 1.9921875 in steps of (1/128). C4[8:0] Range from 0 to 3.9921875 in steps of (1/128). X0 1 - 16, 0 - 0. All the 10 formats defined by MPEG-4, including YUV to RGB, YCbCr to RGB and ITU-R BT 709 to RGB are supported through this programmable CSC block. The MPEG-4 standard allows for a number of conversion scenarios. The particular type of color space used by an MPEG-4 encoder is signaled in the bit stream syntax and is determined by two fields, matrix_coefficients and video_range. 5 color space conversion equations (matrix coefficients) and 2 video ranges for each equation (matrix) are defined in MPEG-4. This gives a total of 10 (5x2) color space conversion possibilities. The 5 matrix coefficients can be categorized into two sets. The matrices represented by matrix_coefficients field values of 4, 5, and 6 are similar and can be grouped together into one set (Set A). The two remaining matrices, represented by matrix_coefficients field values of 1 and 7, are similar and hence can be grouped together into a second set (Set B). Set A and Set B represent CSC matrices in accordance with Recommendation ITU-R BT.470 and Recommendation ITU-R BT.709, respectively. For each CSC matrix, there are two possible video ranges, indicated by the video_range field which is set to either 1 or 0. Therefore there are now two video ranges x 2 sets = 4 CSC scenarios and each of these are summarized in Table 41-4. Table 41-4. YUV to RGB CSC Equations Eqn Matrix CoEfficient 4,5 or 6 (Set A) Video Range 1 Input to CSC and Notation YUV Y ranges from 0-255 U ranges from 0-255 V ranges from 0-255 YCrCb Y ranges from 16-235 Cr ranges from 16-240 Cb ranges from 16-240 Matrix Register Values A1 R = Y + 1.4026 * (V-128) G = Y – 0.3444 * (U-128) – 0.7144 * (V-128) B = Y + 1.7730 * (U-128) C0 = 8’b1000 0000 C1 = 8’b1011 0011 C2 = 8’b0010 1100 C3 = 8’b0101 1011 C4 = 9’b0 1110 0010 X0 = 1’b0 C0 = 8’b1001 0100 C1 = 8’b1100 1100 C2 = 8’b0011 0010 C3 = 8’b0110 1000 C4 = 9’b1 0000 0010 X0 = 1’b1 A0 4,5 or 6 (Set A) 0 R = 1.164*(Y – 16) + 1.596*(Cr-128) G = 1.164*(Y – 16) – 0.813*(Cr-128) – 0.391*(Cb-128) B = 1.164*(Y – 16) + 2.018*(Cb-128) MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-8 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-4. YUV to RGB CSC Equations (continued) Eqn Matrix CoEfficient 1 or 7 (Set B) Video Range 1 Input to CSC and Notation Y’U’V’ Y’ ranges from 0-255 U’ ranges from 0-255 V’ ranges from 0-255 Y’Cr’Cb’ Y’ ranges from 16-235 Cr’ ranges from 16-240 Cb’ ranges from 16-240 Matrix Register Values B1 R = Y’ + 1.5749 * (V’-128) G = Y’ – 0.1875 * (U’-128) – 0.4682 * (V’-128) B = Y’ + 1.8554 * (U’-128) C0 = 8’b1000 0000 C1 = 8’b1100 1001 C2 = 8’b0001 1000 C3 = 8’b0011 1100 C4 = 9’b0 1110 1101 X0 = 1’b0 C0 = 8’b1001 0100 C1 = 8’b1110 0110 C2 = 8’b0001 1011 C3 = 8’b0100 0100 C4 = 9’b1 0000 1110 X0 = 1’b1 B0 1 or 7 (Set B) 0 R = 1.164(Y’-16) + 1.793 * (Cr’-128) G = 1.164(Y’-16) – 0.533 * (Cr’-128) – 0.213 * (Cb’-128) B = 1.164(Y’-16) + 2.112 * (Cb’-128) The correct matrix has to be selected based on the video_range and matrix_coefficient for color space conversion. 41.3.2 Input Interface The PP reads IYUV or YV12 data from external memory. Quantization Parameter (QP) data is required if Deblock and/or De-ring operations are selected. Figure 41-4 shows an example layout for QCIF frames to be processed by the PP. The input Y, U, V, and QP data are expected in 4 sections of memory. The first data in every row starts with a new word. When the row size is not a multiple of 4 bytes, the last few pixels in a row will not occupy a full word and the extra bytes, if any, in the last word are ignored. The PP expects one QP byte per macroblock (MB). Only the lower 5 bits of a QP byte are used and the 3 most significant bits must be set to 0. The first QP in every row starts with a new word and four QP bytes from 4 adjacent MBs in a row are packed into one word. When the number of MBs in a row is not a multiple of 4, then the extra QP bytes in the last word of a QP row are ignored. Data is stored in the memory in the order of natural scan lines. For Y, U, and V data, it is permitted that the distance between the start of two neighboring lines (line stride) is greater than the number of pixels in a line—that is, there could be fixed number of unused words between the end and the beginning of every two neighboring lines. However, unused words are not permitted for QP data. Each row in Figure 41-4 represents a word in memory. Y(j,i) denotes Y data of pixel row j and column i. Layout of U and V data is similar to that of Y data. The figure shows there can be unused space in memory between rows. This parameter is controlled by the Input Line Stride parameter and applies only to Y, U, and V data in the frame. The start of Y, U, and V data can be anywhere in addressable memory. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-9 enhanced Multimedia Accelerator Light (eMMA_lt) In a QCIF image, there are 11 × 9 = 99 MBs, representing all the QPs for a QCIF image. However, due to the packing constraints specified above, the 11 QPs of a row are packed into 3 words with one unused byte in the last word. This is repeated for each row and there can be no optional space between QP rows. LSB MSB Y(0,0) Y(0,4) Y(0,1) Y(0,5) Y(0,2) Y(0,6) Y(0,3) Y(0,7) Start of frame, start of line 0 Other Y data in current row Y(0,172) Y(0,173) Y(0,174) Y(0,175) End of valid data in line 0 Optional unused memory Y(1,172) Y(1,173) Y(1,174) Y(1,175) Start of line 1 Other Y data in current frame Y(143,172) Y(143,173) Y(143,174) Y(143,175) End of valid data in line 143 Optional unused memory Optional gap U frame buffer Optional gap V frame buffer Optional gap QP0 QP4 QP8 QP11 QP1 QP5 QP9 End of Y frame buffer QP2 QP6 QP10 QP13 QP3 QP7 unused QP14 Start of QP frame; start of row 0 of MB End of row 0 of MB Start of row 1 of MB QP12 Other QP data in current frame QP96 QP97 QP98 unused End of QP frame buffer Figure 41-4. PP Input Data Layout (QCIF) 41.3.3 Output Interface The output of the PP is selectable between RGB and YUV 4:2:2 (YUYV). RGB data is internally represented with 24 bits resolution (8 bits per color component) and color bits are truncated according to the programmed color widths. This truncation is done at the last stage of color space MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-10 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) conversion by discarding the least significant bits. For 8 bpp output only 1:1 resize ratio is supported. Table 41-5 shows some examples for 16 bpp and unpacked 24 bpp settings. Table 41-5. RGB Color Width and Offsets Pixel Format Packed 16-bit RGB565 bpp 16 RGB Width RedWidth = 5 GreenWidth = 6 BlueWidth = 5 RedWidth = 8 GreenWidth = 8 BlueWidth = 8 RGB Offset RedOffset = 11 GreenOffset = 5 BlueOffset = 0 RedOffset = 16 GreenOffset = 8 BlueOffset = 0 Unpacked 32-bit RGB888 32 41.3.4 Data Flow The Post-Processing block reads YUV 4:2:0 data from external memory and writes processed RGB or YUYV 4:2:2 data into external memory. A typical use case of the PP in i.MX27 device is as follows: 1. Software or hardware decoder decodes one frame 2. PP is programmed with frame buffer address and other ancillary information 3. Software enables PP 4. For every MB read from memory, PP performs Deblock, Dering, Resize, and CSC and writes to output buffer for display 5. When all MBs of the current frame are processed, PP signals frame completion to the core 6. When PP completes frame processing, it sets the frame completion status and interrupts the CPU. 41.3.5 Relationship of Register Fields Related to the Input Frame Figure 41-5 shows how the Input Line Stride affects the area of frame that is processed by the PP. There are two rectangular areas in the diagram. The inner rectangle shows the frame area to be processed and the outer rectangle indicates the actual memory allocated for the total frame. PP_Y_SOURCE, PP_CR_SOURCE, and PP_CB_SOURCE are pointers to the start addresses of frame data. The Input Line Stride, Width, and Height parameters are automatically divided by 2 when processing the Cr and Cb frame components. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-11 enhanced Multimedia Accelerator Light (eMMA_lt) PP_Y_SOURCE PROCESS_FRAME_PARA.WIDTH PROCESS_FRAME_PARA.HEIGHT Y_INPUT_LINE_STRIDE PP_CB_SOURCE PROCESS_FRAME_WIDTH/2 PROCESS_FRAME_HEIGHT/2 Y_INPUT_LINE_STRIDE/2 Figure 41-5. Input Line Stride 41.3.6 Relationship of Register Fields Related to Output Frame Figure 41-6 shows the effect of the Output Line Stride parameter on the output frame. The Output Line Stride can be used to select a smaller area of the processed and resized frame. The figure shows two rectangular areas. The outer rectangle shows the memory allocated for display. The inner rectangle shows the size of the final output image. The output image size is defined by the Output Line Stride, IMAGE_WIDTH, and IMAGE_HEIGHT parameters. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-12 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) DEST_START_ADDRESS IMAGE_WIDTH IMAGE_HEIGHT OUTPUT_LINE_STRIDE Figure 41-6. Output Line Stride NOTE Output Line Stride is specified in bytes while IMAGE_WIDTH and IMAGE_HEIGHT are specified in pixels. 41.4 Post Processor (PP) Programming Model Only 32-bit accesses (read/write) is supported. All reserved bits should always be written with 0 and all registers are R/W unless specified. Table 41-6 shows the memory map. Table 41-6. PP Register Memory Map Address 0x1002_6000 (PP_CNTL) 0x1002_6004 (PP_INTRCNTL) 0x1002_6008 (PP_INTRSTATUS) 0x1002_600C (PP_SOURCE_Y_PTR) 0x1002_6010 (PP_SOURCE_CB_PTR) 0x1002_6014 (PP_SOURCE_CR_PTR) 0x1002_6018 (PP_DEST_RGB_PTR) Description PP Control Register PP Interrupt Control PP Interrupt Status PP Source Y Frame data Pointer PP Source CB Frame data Pointer PP Source CR Frame data Pointer PP Destination RGB Frame start address Access R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 0x0000_0876 0x0000_0000 0x0000_0–0– 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 41.4.1/41-14 41.4.2/41-15 41.4.3/41-16 41.4.4/41-17 41.4.5/41-18 41.4.6/41-19 41.4.7/41-19 41.4.8/41-20 41.4.9/41-21 0x1002_601C (PP_QUANTIZER_PTR) PP Quantizer start address 0x1002_6020 (PP_PROCESS_PARA) PP Process frame parameter, width and height MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-13 enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-6. PP Register Memory Map (continued) Address 0x1002_6024 (PP_FRAME_WIDTH) 0x1002_6028 (PP_DISPLAY_WIDTH) 0x1002_602C (PP_IMAGE_SIZE) Description PP Source Frame width PP Destination Display width PP Destination Image Size Access R/W R/W R/W R/W R/W R/W R/W W Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Section/Page 41.4.10/41-21 41.4.11/41-22 41.4.12/41-23 41.4.13/41-24 41.4.14/41-25 41.4.15/41-26 41.4.16/41-27 41.4.17/41-28 0x1002_6030 PP Destination Frame Format (PP_DEST_FRAME_FORMAT_CNTL) Control 0x1002_6034 (PP_RESIZE_INDEX) 0x1002_6038 (PP_CSC_COEF_123) 0x1002_603C (PP_CSC_COEF_4) 0x1002_6000–0x1002_607C (PP_RESIZE_COEF_TBL) PP Resize Table Index PP CSC coefficients PP CSC coefficients PP Resize Coefficient Table 41.4.1 PP Control Register Figure 41-7 shows the register; Table 41-7 provides its field descriptions. 0x1002_6000 (PP_CNTL) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W 0 0 0 BSDI CSC_OUT MB_ SWR MOD ST E 0 0 0 CSC TABLE CSCE SEL N 0 1 1 1 0 DE DE BLOC PP_E RING K N EN EN 1 1 0 Reset 0 0 0 0 1 0 0 Figure 41-7. PP Control Register Table 41-7. PP Control Register Field Descriptions Name 31–13 12 BSDI Description Reserved—These bits are reserved and should read 0. Byte Swap Input Data. The input data word from memory is byte swapped (32-bit little endian to big endian or vice versa) before use. 0 Swap disabled 1 Swap enabled MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-14 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-7. PP Control Register Field Descriptions (continued) Name 11–10 CSC_OUT Description CSC Output. Sets RGB output resolution. 00 32-bit (unpacked RGB888) 01 Reserved 10 16-bit 11 32-bit (unpacked RGB888) Reserved—This bit should always read 0 Software Reset. Resets entire module, all registers return to their reset default values. 0 No reset 1 Reset Reserved. This bit is reserved and should read 0. CSC Table Select. Selects one of the 4 CSC matrices. Refer to Table 41-4 for more information. 00 A1 01 A0 10 B1 11 B0 CSC Enable. Enables CSC to output RGB data else YUV 4:2:2 data when disabled. YUV 4:2:2 output is in YUYV interleaved format. 0 YUV 4:2:2 1 RGB Reserved. This bit is reserved and should read 0. De-ring Enable. Enable or disable Dering operation. 0 No Dering 1 Enable Dering De-block Enable. Enable or disable Deblock operation. 0 No Deblock 1 Enable Deblock PP Enable. Start frame processing. Bit has no effect if the LOCK_BIT was not previously read successfully with IDLE status. Once enabled, this bit cannot be reset unless one of the following has occurred; Frame is completely processed or SWRST is set or Data abort error. 0 Not enabled 1 Enabled (self-clearing) 9 8 SWRST 7 Reserved 6–5 CSC_TABLE_SEL 4 CSCEN 3 2 DERINGEN 1 DEBLOCKEN 0 PP_EN 41.4.2 PP Interrupt Control Register Figure 41-8 shows the register; Table 41-8 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-15 enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_6004 (PP_INTRCNTL) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR INTR _EN 0 FRA ME COM P INTR EN 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-8. PP Interrupt Control Register Table 41-8. PP Interrupt Control Register Description Name 31–3 2 ERR_INTR_EN 1 0 FRAME_COMP_INTR_EN Description Reserved. This bit is reserved and should read 0. Error Interrupt Enable. If set, enables interrupt on error. 0 interrupt disabled 1 interrupt enabled Reserved. This bit is reserved and should read 0 Frame Complete Interrupt Enable. If set and in Frame mode (MB_MODE=0), enables interrupt on completion of frame processing. 0 Interrupt disabled 1 Interrupt enabled 41.4.3 PP Interrupt Status Register Figure 41-9 shows the register; Table 41-9 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-16 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_6008 (PP_INTRSTATUS) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR INTR _EN 0 FRA ME COM P INTR EN w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 w1c 0 Figure 41-9. PP Interrupt Status Register Table 41-9. PP Interrupt Status Register Field Descriptions Name 31–3 2 ERR_INTR 1 0 FRAME_COMP_INTR Description Reserved. These bits are reserved and should be set to 0. Error Interrupt Status. If set an error has occurred. The PP has to be reset (SWRST = 1) before further operations can be initiated. Reserved. Frame Complete Interrupt Status. If set, a frame has been processed. 41.4.4 PP Source Y Address Register Figure 41-10 shows the register; Table 41-10 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-17 enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_600C (PP_SOURCE_Y_PTR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R PP_Y_SOURCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PP_Y_SOURCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-10. PP Source Y Address Register Table 41-10. PP Source Y Address Register Field Descriptions Name 31–0 PP_Y_SOURCE Description PP_SOURCE_Y_PTR. 32-bit frame start address of Y data (Luminance). Bits 1–0 are always set to 0 (word aligned) 41.4.5 PP Source Cb Address Register Figure 41-11 shows the register; Table 41-11 provides its field descriptions. 0x1002_6010 (PP_SOURCE_CB_PTR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R PP_CB_SOURCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PP_CB_SOURCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-11. PP Source Cb Address Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-18 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-11. PP Source Cb Address Register Field Descriptions Name 31–0 PP_CB_SOURCE Description PP_SOURCE_CB_PTR. 32-bit frame start address of Cb data (U or Chrominance). Bit 1–0 are always set to 0 (word aligned) 41.4.6 PP Source Cr Address Register Figure 41-12 shows the register; Table 41-12 provides its field descriptions. 0x1002_6014 (PP_SOURCE_CR_PTR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R PP_CR_SOURCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PP_CR_SOURCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-12. PP Source Cr Address Register Table 41-12. PP Source Cr Address Register Field Descriptions Name 31–0 PP_CR_SOURCE Description PP_SOURCE_CR_PTR. 32-bit frame start address of Cr data (V or Chrominance). Bits 1–0 are always set to 0 (word aligned) 41.4.7 PP Destination RGB Frame Start Address Register Figure 41-13 shows the register; Table 41-13 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-19 enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_6018 (PP_DEST_RGB_PTR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R RGB_START_ADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RGB_START_ADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-13. PP Destination RGB Frame Start Address Register Table 41-13. PP Destination RGB Frame Start Address Register Description Name 31–0 RGB_START_ADDR Description RGB Start Address. Sets the destination frame start address. If CSCEN = 0, then these bits point to the start of YUV 4:2:2 (YUYV interleaved) data, else it points to RGB data. Bit 1–0 are always set to 0 (word aligned). 41.4.8 PP Quantizer Start Address Register Figure 41-14 shows the register; Table 41-14 provides its field descriptions. 0x1002_601C (PP_QUANTIZER_PTR) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R QUANTIZER_PTR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R QUANTIZER_PTR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-14. PP Quantizer Start Address Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-20 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-14. PP Quantizer Start Address Register Description Name 31–0 QUANTIZER_PTR Description QUANTIZER_PTR. Sets the start address of the Quantization Parameter in memory. This register is ignored if Deblock and De-ring are both disabled. Bits 1–0 are always set to 0 (word aligned) 41.4.9 PP Process Frame Parameter Register Figure 41-15 shows the register; Table 41-15 provides its field descriptions. 0x1002_6020 (PP_PROCESS_PARA) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 PROCESS_FRAME_WIDTH[9:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 PROCESS_FRAME_HEIGHT[9:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-15. PP Process Parameter Register Table 41-15. PP Process Parameter Register Description Name 31–26 25–16 PROCESS_FRAME_WIDTH Description Reserved. These bits are reserved and should read 0. Process Frame Width. Sets the input window width to be processed based on Y frame pixel count. PROCESS_FRAME_WIDTH/2 is used for Cb and Cr window width. PROCESS_FRAME_WIDTH must always be less than or equal to INPUT_LINE_STRIDE. This value should be a multiple of 8 pixels. Reserved. These bits are reserved and should read 0. Process Frame Height. Sets the input window height to be processed based on Y frame line count. PROCESS_FRAME_HEIGHT/2 is used for Cb and Cr window height. This value should be a multiple of 8 lines. 15–10 9–0 PROCESS_FRAME_HEIGHT 41.4.10 PP Source Frame Width Register Figure 41-16 shows the register; Table 41-16 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-21 enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_6024 (PP_FRAME_WIDTH) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 QUANTIZER_FRAME_WIDTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 Y_INPUT_LINE_STRIDE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-16. PP Source Frame Width Register Table 41-16. PP Source Frame Width Register Field Descriptions Name 31–24 23–16 QUANTIZER_FRAME_WIDTH Description Reserved. These bits are reserved and should read 0. Quantizer Frame Width. These bits set the number of bytes used to represent quantizers from all the MB in a row. QP data is packed into words with possibly unused bytes in the last word when the number of MB in a row in not a multiple of 4. In such cases, QUANTIZER_FRAME_WIDTH is rounded up to the nearest 4-byte multiple (word) that represents all the QP data for one row of MBs. For example, if there are 7 MBs in a row, then 2 words are required to represent the 7 QP data bytes with one unoccupied byte. The QUANTIZER_FRAME_WIDTH in this example is set as 8 (7 bytes rounded up to the nearest multiple of 4). This value should be a multiple of 4 bytes. Reserved. These bits are reserved and should read 0. Y Input Line Stride. These bits set the number of pixels between adjacent rows of pixels for Y input data. Y_INPUT_LINE_STRIDE/2 is used for Cb and Cr input data. This value must be a multiple of 8 pixels. 15–12 11–0 Y_INPUT_LINE_STRIDE 41.4.11 PP Destination Display Width Register Figure 41-17 shows the register; Table 41-17 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-22 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_6028 (PP_DISPLAY_WIDTH) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 OUTPUT_LINE_STRIDE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-17. PP Destination Display Width Register Table 41-17. PP Destination Display Width Register Description Name 31–13 12–0 OUTPUT_LINE_STRIDE Description Reserved. These bits are reserved and should read 0. Output Line Stride. These bits set the distance in bytes between the start addresses of adjacent lines in the output frame. If the stride is equal to the OUT_IMAGE_WIDTH, then the stride should be calculated as: OUT_IMAGE_WIDTH * Bytes Per Pixel. This value should be a multiple of 4 bytes. 41.4.12 PP Destination Image Size Register Figure 41-18 shows the register; Table 41-18 provides its field descriptions. 0x1002_602C (PP_IMAGE_SIZE) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 OUT_IMAGE_WIDTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 OUT_IMAGE_HEIGHT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-18. PP Destination Image Size Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-23 enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-18. PP Destination Image Size Register Description Name 31–28 27–16 OUT_IMAGE_WIDTH 15–12 11–10 OUT_IMAGE_HEIGHT Description Reserved. These bits are reserved and should read 0. Out Image Width. These bits set the width of the output in pixels (not bytes). This value must always be a multiple of 2. OUT_IMAGE_WIDTH[0] is read-only and always 0. Reserved. These bits are reserved and should read 0. Out Image Height. These bits set the number of lines in the output. This value must always be a multiple of 2. OUT_IMAGE_HEIGHT[0] is read-only and always 0. 41.4.13 PP Destination Frame Format Control Register Figure 41-19 shows the register; Table 41-19 provides its field descriptions. 0x1002_6030 (PP_DEST_FRAME_FORMAT_CNTL) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 RED_OFFSET 0 0 0 0 0 0 0 GREEN_OFFSET 0 0 0 0 0 BLUE_OFFSET 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 RED_WIDTH GREEN_WIDTH 0 0 0 0 0 0 BLUE_WIDTH 0 0 0 0 0 0 0 0 0 0 Figure 41-19. PP Destination Frame Format Control Register NOTE This register is used only when the output is in RGB format. Table 41-19. PP Destination Frame Format Control Register Description Name 31 30–26 RED_OFFSET 25–21 GREEN_OFFSET 20–16 BLUE_OFFSET 15–12 Description Reserved. These bits are reserved and should read 0. Red Offset. Specifies the bit offset of the Red color or Luminance component in the output pixel The offset is specified with respect to Bit 0. Green Offset. Specifies the bit offset of the Green color or Chrominance (U) component in the output pixel. The offset is specified with respect to Bit 0. Blue Offset. Specifies the bit offset of the Blue color or Chrominance (V) component in the output pixel. The offset is specified with respect to Bit 0. Reserved. These bits are reserved and should read 0. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-24 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-19. PP Destination Frame Format Control Register Description (continued) Name 11–8 RED_WIDTH 7–4 GREEN_WIDTH 3–0 BLUE_WIDTH Description Red Width. Specifies the number of bits in the Red color component in the output pixel. The width of the Luminance component is fixed at 8 bits, always. Allowed values are 0 to 8. Any value greater than 8 is fixed to 8 internally. Green Width. Specifies the number of bits in the Green color component in the output pixel. The width of the Chrominance (Cb or U) component is fixed at 8 bits, always. Allowed values are 0 to 8. Any value greater than 8 is fixed to 8 internally. Blue Width. Specifies the number of bits in the Blue color component in the output pixel.The width of the Chrominance (Cr or V) component is fixed at 8 bits, always. Allowed values are 0 to 8. Any value greater than 8 is fixed to 8 internally. The following table shows some example configurations for the YUV 4:2:2 combinations. Table 41-20. YUV 4:2:2 Configuration Settings YUV Format YUYV Offsets RED_OFFSET=24 GREEN_OFFSET=16 BLUE_OFFSET=0 RED_OFFSET=24 GREEN_OFFSET=0 BLUE_OFFSET=16 RED_OFFSET=16 GREEN_OFFSET=24 BLUE_OFFSET=8 RED_OFFSET=16 GREEN_OFFSET=8 BLUE_OFFSET=24 Width RED_WIDTH=8 GREEN_WIDTH=8 BLUE_WIDTH=8 Settings 0x6200_0888 YVYU 0x6010_0888 UYVY 0x4308_0888 VYUY 0x4118_0888 41.4.14 PP Resize Table Index Register This register sets the start and end indices of horizontal and vertical resize tables. The two resize tables share a memory of 40 locations. The minimum start index is 0 and the maximum end index is 39. If the horizontal and vertical resize ratios are the same, then one resize table can be used and the horizontal and vertical start and end indices can be set to the same value. However, if the resize ratios are different, the horizontal and vertical resize tables need to be programmed differently. Either the horizontal resize table or the vertical resize table can start from address 0. Figure 41-20 shows the register; Table 41-21 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-25 enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_6034 (PP_RESIZE_INDEX) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 HORI_TBL_START_INDEX 0 0 HORI_TBL_END_INDEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 VERT_TBL_START_INDEX 0 0 VERT_TBL_END_INDEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-20. PP Resize Table Index Register Table 41-21. PP Resize Table Index Register Field Descriptions Name 31–30 29–24 HORI_TBL_START_INDEX 23–22 21–16 HORI_TBL_END_INDEX 15–14 13–8 VERT_TBL_START_INDEX 7–6 5–0 VERT_TBL_END_INDEX Description Settings Reserved. These bits are reserved and should read 0. Horizontal Table Start Index. Start index of horizontal resize table. Valid values: 0–39 Reserved. These bits are reserved and should read 0. Horizontal Table End Index. End index of horizontal resize table. Valid values: 0–39 Reserved. These bits are reserved and should read 0. Vertical Table Start Index. Start index of vertical resize table. Valid values: 0–39 Reserved. These bits are reserved and should read 0. Vertical Table End Index. End index of vertical resize table. Valid values: 0–39 41.4.15 PP CSC COEF 123 Register Figure 41-21 shows the register; Table 41-22 provides its field descriptions. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-26 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) 0x1002_6038 (PP_CSC_COEF_123) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R C0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R C2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3 Figure 41-21. PP CSC Coefficient_123 Register Table 41-22. PP Lock Bit Register Field Descriptions Name 31–24 C0[7:0] 23–16 C1[7:0] 15–8 C2[7:0] 7–0 C3[7:0] Description CSC Coefficient 0 Range from 0 to 1.9921875 in steps of (1/128) CSC Coefficient 1 Range from 0 to 1.9921875 in steps of (1/128) CSC Coefficient 2 Range from 0 to 1.9921875 in steps of (1/128) CSC Coefficient 3 Range from 0 to 1.9921875 in steps of (1/128) 41.4.16 PP CSC COEF_4 Register Figure 41-22 shows the register; Table 41-23 provides its field descriptions. 0x1002_603C (PP_CSC_COEF_4) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Read/Write 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 X0 C4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41-22. PP CSC Coefficient_4 Register MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-27 enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-23. PP CSC COEF_4 Register Field Descriptions Name 31–10 9 X0 8–0 C4 Description Reserved. These bits are reserved and should read 0 X0. Luminance Component Offset 1 = 16 0=0 CSC Coefficient 4. Range from 0 to 3.9921875 in steps of 1/128 Table 41-24. CSC Coefficient Usage YUV Format YCbCr YUV/RGB Conversions R = C0*(Y – X0) + C1*(Cr-128) G = C0*(Y – X0) – C2*(Cb-128) – C3*(Cr-128) B = C0*(Y – X0) + C4*(Cb-128) R = C0*(Y – X0) + C1*(V-128) G = C0*(Y – X0) – C2*(U-128) – C3*(V-128) B = C0*(Y – X0) + C4*(U-128) YUV 41.4.17 PP Resize Coefficient Table Figure 41-23 shows the register; Table 41-25 provides its field descriptions. 0x1002_6000–0x1002_607C (PP_RESIZE_COEF_TBL) 31 30 29 28 27 26 25 24 23 22 21 20 Access: User Write-Only 19 18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R w[4:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n[1:0] OP Figure 41-23. PP Resize Coefficient Table (Array of 32 Resize Coefficients) NOTE This is a write-only register. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-28 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) Table 41-25. PP Resize Coefficient Table Register Field Descriptions Name 31–8 7–4 w Description Reserved. These bits are reserved and should read 0. Weighting Coefficient. These bits set the weighting coefficient applied to the older of the two pixels used in the resize equation. Valid values for weight are 0, 2 to 30, and 31. A value of 31 is treated as 32 and therefore 31 is an invalid co-efficient. The resizing algorithm uses w as the Weighting Coefficient 1, w1. w1 = w Weighting coefficient 2, w2, is calculated as: w2 = 32–w1 2–1 n Number of pixels to read. These bits set the number of new pixels to read. 00 No pixels are read. 01 1 new pixel is read. 10 2 new pixels are read. 11 3 new pixels are read. Output Pixels. This bit controls if pixels are output 1 Pixels are output. 0 No pixels are output. 0 OP MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-29 enhanced Multimedia Accelerator Light (eMMA_lt) 41.5 Pre-Processor CHANNEL-1 Line Buffer (128X48) From CSI or memory YUV4:2:2 YUV4:2:0 RGB16/32 CH-1 RESIZE CSC CSC_CH1 BUFFER (64 x 32) YUV-ACC BUFF (400 x 33) Supports: RGB to YUV YUV to RGB CSC_CH1 BUFFER (64 x32) Line Buffer (128x48) CH-2 RESIZE CHANNEL-2 CSC_CH 2 BUFFER (64 x 32) To Memory YUV Supports: RGB to YUV 4:2:0 YUV 4:2:2 (YUYV) YUV 4:4:4 CSC_CH2 BUFFER (64 x 32) YUV-ACC BUFF (400 x 33) CSC NOTE: Channel-1 meant for Display Channel-2 meant for Video encoder Table 41-26. Pre-Processing Block Diagram The Pre-Processor receives input from main memory or from the camera sensor via the CMOS Sensor Interface (CSI) module and outputs two channels of data, one for video encoding and another for video display. Input data undergoes resize in a Channel-1 and Channel-2 resize block which provides programmable downscaling. The Channel-1 resize can be connected in cascade or parallel to Channel-2 resize. This is followed by programmable Color Space Conversion. The CSC block provides conversion from YUV to RGB and RGB to YUV for CH-1 and RGB to YUV for Channel-2. After CSC, the data is channelled into memory. Channel-1 output is meant for display and both RGB and YUV 4:2:2 (interleaved) formats are supported. Data output on Channel-2 is meant for video encoding and various YUV formats are supported in this path. Namely, the YUV 4:2:0 (planar) format matches most MPEG-4 video encoder inputs and is required by the on-chip MPEG-4 encoder. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-30 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) 41.5.1 41.5.2 Features Input Data Formats Table 41-27. Input Data Formats Source CSI Format RGB RGB YUV 4:2:2 YUV 4:4:4 Memory RGB RGB YUV 4:2:2 YUV 4:2:0 YUV 4:4:4 Resolution 16 bpp 32 bpp (unpacked RGB888) Pixel interleaved 32 bpp—pixel interleaved 16 bpp 32 bpp (unpacked RGB888) Pixel interleaved Band interleaved (IYUV and YV12) 32 bpp—pixel interleaved Table 41-27 shows the input data formats for the Pre-Processor. 41.5.2.1 Input Size The Pre-Processor can accept frames as small as 32 × 32 pixels to as large as 2044 × 2044 pixels. For YUV 4:2:0, the maximum frame size is limited to 2040 × 2040 pixels. 41.5.2.2 Resize Ratios There are two independent and identical resize blocks in the Pre-Processor, called the Channel-1 Resize block and the Channel-2 Resize block. The Channel-1 resize block can either work in parallel to the Channel-2 resize block, that is, both blocks connect to the input, or in cascade to the output of the Channel-2 resize. Each resize block supports two resize algorithms: bilinear and averaging. For each resize block, a user needs select one of the algorithms through register bit before starting resizing. Table 41-28. Resize Ratios Resize Block Channel-1 Resize 1:1 Programmable from 1:1 to 8:1 or when cascaded, from 8:1 to 64:1 Channel-2 Resize 1:1 Programmable from 1:1 to 8:1 Resize Ratio Description Data is copied from input to output. No resize is effected. Downscaling Data is copied from input to output. No resize is effected. Downscaling MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 Freescale Semiconductor 41-31 enhanced Multimedia Accelerator Light (eMMA_lt) 41.5.2.3 Output Formats Table 41-29. Output Formats Table 41-29 shows the output formats supported on Channel-1 and Channel-2. Channel Channel-1 Output Format RGB Resolution 8 bpp 16 bpp 32 bpp Description 4 pixels in an output word 2 pixels in an output word Unpacked RGB888—1 pixel in an output word Pixel interleaved—2 pixels in an output word Pixel interleaved—2 pixels in an output word Band interleaved Pixel interleaved—1 pixel in an output word YUV 4:2:2 Channel-2 YUV 4:2:2 YUV 4:2:0 YUV 4:4:4 YUYV,YVYU,UYVY, VYUY YUYV IYUV, YV12 YUV0 41.5.2.4 Output Data Output data is always written to memory pointed to by the destination pointers of Channel-1 and Channel-2. 41.5.2.5 Output Size Minimum output size on Channel-1 and Channel-2 is 32 × 32 pixels and resize ratios must be calculated accordingly to prevent data truncation at the output. 41.5.3 Resize The Channel-1 Resize and Channel-2 Resize modules are primarily used to resize captured sensor images and suitably format them to match the viewfinder display and video encoder input requirements. For example, an image or live video input from a 640 x 480 camera sensor can be resized to fit an LCD display of 240 x 320 or 320 x 320. The resizer can also prepare data for video encoding (Channel-2). Each resize module implements two resize algorithms: bilinear and averaging, and one of the algorithms can be enabled at any single time. 41.5.3.1 Bilinear Resize in PrP Bilinear interpolation algorithm is implemented and recommended for resize ratios between 1:1 and 2:1. Here two adjacent pixels are loaded and multiplied by respective weighting coefficients to produce an output pixel. The weighting coefficients for a particular resize ratio are calculated by software and preloaded into the resize coefficient registers (eg. Register eMMA PrP_CH1_RZ_HORI_COEF1) of the PrP from which the resize block reads the coefficients to use. MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.2 41-32 Freescale Semiconductor enhanced Multimedia Accelerator Light (eMMA_lt) For example, the output samples for the 5:3 bilinear interpolation can be calculated as follows: out[0] = 5/8 * in[0] + 3/8 * in[1] out[1] = 0/8 * in[1] + 8/8 * in[2] out[2] = 3/8 * in[3] + 5/8 * in[4] the entries should be (5,1),(0,1),(X,0),(3,1),(X,0). A programmable resize engine has been implemented in hardware, which reads instructions from the PRP resize coefficient registers (Register eMMA PrP_CH1_RZ_HORI_COEF1, PrP_CH1_RZ_HORI_COEF2, PrP_CH1_RZ_VERT_COEF1, PrP_CH1_RZ_VERT_COEF2, PrP_CH2_RZ_HORI_COEF1, PrP_CH2_RZ_HORI_COEF2, PrP_CH2_RZ_VERT_COEF1, PrP_CH2_RZ_VERT_COEF2). An output pixel will be generated with the value (w1 * in1 + w2 * in2)/8 where in1 and in2 are two adjacent pixels. The resize engine will then read in one new input pixel, if the corresponding VOn bit in the corresponding registers (Register eMMA PrP_CH1_RZ_HORI_VALID, PrP_CH1_RZ_VERT_VALID, PrP_CH2_RZ_HORI_VALID, or PrP_CH2_RZ_VERT_VALID) is true “1”. Therefore, each resize instruction is in the form of (w1, n) where each coefficient (w1) is represented with 3 bits and n with 1-bit, and stored in 2 registers, one for w1 coefficient, and one for n valid. w2 is calculated as 8-w1. • Allowed values of w1 are 0,1,2,3,4,5,6 and 7. w1 coefficient value of 7 (3’b111) is treated as 8 (4’b1000), consequently, w1 coefficient value of 7 is not possible. • PrP resize weighting coefficients only have 3 bits, not 5 bits as in PP resize. 41.5.3.2 Averaging Resize in PrP This is a special convolution filter where a weighted average of every N input pixels will produce an output pixel, when the resize ratio is N:1. Suppose in[0], in[1], ... in[N] are input pixels, w[i] are weighting coefficients, and out[0] is the corresponding output pixel, then out[0] = w[0] * in[0] + w[1] * in[1] +... + w[N] * in[N]. The resize instruction for PRP averaging is also in the form of (w, n) where each coefficient (w) is represented with 3 bits and n with 1-bit. The averaging resizer is also implemented as a programmable resize engine. One pixel is loaded every cycle to the resize engine and a multiplication and accumulate operation is applied. A temporary register, T is used to store the interim result. On reset or at the beginning of a line (for horizontal resize) or a row (for vertical resize), T is reset to 0. Then the process is as follows in every cycle: 1. Load a new input pixel value into the “in” register 2. T=T+ w*in; where 0