MCIMX280CVM4B

Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX28CEC Rev. 1, 04/2011 i.MX28 Applications Processors Data Sheet for Consumer Products Silicon Version 1.2 i.MX28 Package Information Plastic package Case 5284 14 x 14 mm, 0.8 mm Pitch 1 Introduction Ordering Information See Table 1 on page 3 for ordering information. The i.MX28 is a low-power, high-performance applications processor optimized for the general embedded industrial and consumer markets.The core of the i.MX28 is Freescale's fast, power-efficient implementation of the ARM926EJ-S™ core, with speeds of up to 454 MHz. The device is suitable for a wide range of applications, including the following: • Human-machine interface (HMI) panels: industrial, home • Industrial drive, PLC, I/O control display, factory robotics display, graphical remote controls • Handheld scanners and printers • Patient-monitoring, portable medical devices • Smart energy meters, energy gateways • Media phones, media gateways The integrated power management unit (PMU) on the i.MX28 is composed of a triple output DC-DC switching converter and multiple linear regulators. These provide power sequencing for the device and its I/O peripherals such as memories and SD cards, as well as provide battery charging capability for Li-Ion batteries. Contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Ordering Information & Functional Part Differences 3 1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1. Special Signal Considerations . . . . . . . . . . . . . . . 10 3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. i.MX28 Device-Level Conditions . . . . . . . . . . . . . . 11 3.2. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 19 3.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4. I/O AC Timing and Parameters . . . . . . . . . . . . . . . 24 3.5. Module Timing and Electrical Parameters . . . . . . 28 4. Package Information and Contact Assignments . . . . . . . 60 4.1. 289-Ball MAPBGA—Case 14 x 14 mm, 0.8 mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2. Ground, Power, Sense, and Reference Contact Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3. Signal Contact Assignments . . . . . . . . . . . . . . . . . 62 4.4. i.MX287 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5. i.MX286 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6. i.MX283 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.7. i.MX280 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 68 5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 © Freescale Semiconductor, Inc., 2011. All rights reserved. The i.MX28 processor includes an additional 128-Kbyte on-chip SRAM to make the device ideal for eliminating external RAM in applications with small footprint RTOS. The i.MX28 supports connections to various types of external memories, such as mobile DDR, DDR2 and LV-DDR2, SLC and MLC NAND Flash. The i.MX28 can be connected to a variety of external devices such as high-speed USB2.0 OTG, CAN, 10/100 Ethernet, and SD/SDIO/MMC. 1.1 Device Features The following lists the features of the i.MX28: • ARM926EJ-S CPU running at 454 MHz: — 16-Kbyte instruction cache and 32-Kbyte data cache — ARM embedded trace macrocell (CoreSight™ ETM9™) — Parallel JTAG interface • 128 KBytes of integrated low-power on-chip SRAM • 128 KBytes of integrated mask-programmable on-chip ROM • 1280 bits of on-chip one-time-programmable (OCOTP) ROM • 16-bit mobile DDR (mDDR) (1.8 V), DDR2 (1.8 V) and LV-DDR2 (1.5 V), up to 205 MHz DDR clock frequency with voltage overdrive • Support for up to eight NAND flash memory devices with up to 20-bit BCH ECC • Four synchronous serial ports (SSP) for SDIO/MMC/MS/SPI. Two can be used for SDIO/MMC/MS interfaces (supports SD2.0, eMMC4.4 and MSPro), and all can be used for the SPI interface. • 10/100-Mbps Ethernet MAC compatible with IEEE Std 802.3™, supporting IEEE Std 1588™-compatible hardware timestamp. Also supports 50-MHz/25-MHz clock output for external Ethernet PHY. • Two 2.0B protocol-compatible Controller Area Network (CAN) interfaces • One USB2.0 OTG device/host controller and PHY • One USB2.0 host controller and PHY • LCD controller, up to 24-bit RGB (DOTCK) modes and 24-bit system-mode • Pixel-processing pipeline (PXP) supports full path from color-space conversion, scaling, alpha-blending to rotation without intermediate memory access. • SPDIF transmitter • Dual serial audio interface (SAIF) to support full-duplex transmit and receive operations; each SAIF supports three stereo pairs • Five application Universal Asynchronous Receiver-Transmitters (UARTs), up to 3.25 Mbps with hardware flow control • One debug UART operating at up to 115 Kb/s using programmed I/O • Two I2C master/slave interfaces, up to 400 kbps • Four 32-bit timers and a rotary decoder i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 2 Freescale Semiconductor • • • • • • • • • • Eight Pulse Width Modulators (PWMs) Real-time clock (RTC) GPIO with interrupt capability Power Management Unit (PMU) supports a triple output DC-DC switching converter, multiple linear regulators, battery charger, and detector. 16-channel Low-Resolution A/D Converter (LRADC) 4/5-wire touchscreen controller Up to 8X8 keypad matrix with button-detect circuit Single channel High Speed A/D Converter (HSADC), up to 2 Msps data rate Security features: — Read-only unique ID for Digital Rights Management (DRM) algorithms — Secure boot using 128-bit AES hardware decryption — SHA-1 and SHA256 hashing hardware — High assurance boot (HAB4) Offered in 289-pin Ball Grid Array (BGA) 1.2 Ordering Information & Functional Part Differences Table 1. Ordering Information Part Number MCIMX280DVM4B MCIMX280CVM4B MCIMX283DVM4B MCIMX283CVM4B MCIMX286DVM4B MCIMX286CVM4B MCIMX287CVM4B Projected Temperature Range (°C) –20 to +70 –40 to +85 –20 to +70 –40 to +85 –20 to +70 –40 to +85 –40 to +85 Package 14 x 14 mm, 0.8mm pitch, MAPBGA-289 14 x 14 mm, 0.8mm pitch, MAPBGA-289 14 x 14 mm, 0.8 mm pitch, MAPBGA-289 14 x 14 mm, 0.8 mm pitch, MAPBGA-289 14 x 14 mm, 0.8 mm pitch, MAPBGA-289 14 x 14 mm, 0.8 mm pitch, MAPBGA-289 14 x 14 mm, 0.8 mm pitch, MAPBGA-289 Table 1 provides the ordering information for the i.MX28. Table 2 provides the functional differences between the i.MX280, i.MX283, i.MX286, and the i.MX287. Table 2. i.MX28 Functional Differences Function LCD Interface Touch Screen Ethernet L2 Switch CAN 12-bit ADC i.MX280 — — x1 — — x8 i.MX283 Yes Yes x1 — — x8 i.MX286 Yes Yes x1 — x2 x8 i.MX287 Yes Yes x2 Yes x2 x8 i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 3 Table 2. i.MX28 Functional Differences (continued) Function High-speed ADC USB 2.0 i.MX280 x1 OTG HS with HS PHY x1 HS Host with HS PHY x1 SDIO SPI Application UART Debug UART PWM S/PDIF Tx Securtiy x4 x4 x6 x1 — — Yes i.MX283 x1 OTG HS with HS PHY x1 HS Host with HS PHY x1 x4 x4 x5 x1 x8 — Yes i.MX286 x1 OTG HS with HS PHY x1 HS Host with HS PHY x1 x4 x4 x5 x1 x8 Yes Yes i.MX287 x1 OTG HS with HS PHY x1 HS Host with HS PHY x1 x4 x4 x5 x1 x8 Yes Yes i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 4 Freescale Semiconductor 1.3 Block Diagram Figure 1 shows the simplified interface block diagram. Figure 1. i.MX28 Simplified Interface Block Diagram 2 Features Table 3. i.MX28 Functions Function BGA289 Yes Table 3 shows the device functions. External Memory Interface (EMI) (1.5 V LV-DDR2, 1.8 V DDR2, 1.8 V LP-DDR1) General-Purpose Media Interface (GPMI): • NAND data width • Number of external NANDs supported Pulse Width Modulator (PWM) 8-bit 4 dedicated / 8 with muxing 5 dedicated / 8 with muxing i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 5 Table 3. i.MX28 Functions (continued) Function Application UART (AUART): Interfaces supported Synchronous Serial Port (SSP): Supported through dedicated pins IC SPDIF SAIF FlexCAN LCD interface High-speed ADC LRADC (touchscreen, keypad...) Ethernet MAC and switch Universal Serial Bus (USB) 2 BGA289 4 dedicated / 5 with muxing 3 dedicated / 4 with muxing 1 dedicated / 2 with muxing 1 2 2 24 bits Yes Yes 2 MACs with switch 2 Table 4 describes the digital and analog modules of the device. Table 4. i.MX28 Digital and Analog Modules Block Mnemonic APBHDMA Block Name Subsystem Brief Description The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for memory-mapped I/O to the APB devices, as well a central DMA facility for devices on this bus. The bridge provides a peripheral attachment bus running on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.) The DMA controller transfers read and write data to and from each peripheral on APBH bridge. The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for memory-mapped I/O to the APB devices, as well a central DMA facility for devices on this bus. The AHB-to-APBX bridge provides a peripheral attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that the APBX runs on a crystal-derived clock, as compared to APBH, which is synchronous to HCLK.) The DMA controller transfers read and write data to and from each peripheral on APBX bridge. The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM real-time debug modules. It contains the 16-Kbyte L1 instruction cache, 32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM. Each of the UART modules supports the following serial data transmit/receive protocols and configurations: • 7- or 8-bit data words, one or two stop bits, programmable parity (even, odd, or none) • Programmable baud rates up to 3.25 MHz. This is a higher maximum baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard and previous Freescale UART modules. 16-byte FIFO on Tx and 16-byte FIFO on Rx supporting auto-baud detection AHB to APBH System control Bridge with DMA APBXDMA AHB to APBX System control Bridge with DMA ARM9 or ARM926 AUART(5) ARM926EJ-S ARM® CPU Application UART interface Connectivity peripherals i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 6 Freescale Semiconductor Table 4. i.MX28 Digital and Analog Modules (continued) Block Mnemonic BCH Block Name Subsystem Brief Description The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable of correcting from 2 to 20 single bit errors within a block of data no larger than about 900 bytes (512 bytes is typical) in applications such as protecting data and resources stored on modern NAND flash devices. The boundary scan interface is provided to enable board level testing. There are five pins on the device which is used to implement the IEEE Std 1149.1™ boundary scan protocol. The clock control module, or CLKCTRL, generates the clock domains for all components in the i.MX28 system. The crystal clock or PLL clock are the two fundamental sources used to produce most of the clock domains. For lower performance and reduced power consumption, the crystal clock is selected. The PLL is selected for higher performance requirements but requires increased power consumption. In most cases, when the PLL is used as the source, a Phase Fractional Divider (PFD) can be programmed to reduce the PLL clock frequency by up to a factor of 2. This module provides support for general encryption and hashing functions typically used for security functions. Because its basic job is moving data from memory to memory, it also incorporates a memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the DMA-based approach. The DFLPT provides a unique method of implementing the ARM MMU first-level page table (L1PT) using a hardware-based approach. The digital control module includes sections for controlling the SRAM, the performance monitors, high-entropy pseudo-random number seed, free-running microseconds counter, and other chip control functions. The Debug UART performs the following data conversions: • Serial-to-parallel conversion on data received from a peripheral device • Parallel-to-serial conversion on data transmitted to the peripheral device The i.MX28 supports off-chip DRAM storage through the EMI controller, which is connected to the four internal AHB/AXI busses. The EMI supports multiple external memory types, including: • 1.8-V Mobile DDR1 (LP-DDR1) • Standard 1.8-V DDR2 • Low Voltage 1.5-V DDR2 (LV-DDR2) Ethernet MAC controller connected to the uDMA (unified DMA). Supports 10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also supports RMII or MII connectivity. The Controller Area Network (CAN) protocol is a message based protocol used for serial data. It was designed specifically for automotive but is also used in industrial control and medical applications. The serial data bus runs at 1 Mbps. The General-Purpose Media Interface (GPMI) controller is a flexible NAND flash controller with 8-bit data width, up to 50-MBps I/O speed and individual chip select and DMA channels for up to 8 NAND devices. It also provides a interface to 20-bit BCH for ECC. Bit-correcting Connectivity ECC peripherals accelerator Boundary Connectivity Scan Interface peripherals Clock control module Clocks BSI CLKCTRL DCP Data co-processor Security DFLPT System control Default first-level page table Digital control System control and on-chip RAM Debug UART Connectivity peripherals External memory interface Connectivity peripherals DIGCTL DUART EMI ENET Ethernet MAC Connectivity Controller peripherals Controller area network module General-purpose media interface Connectivity peripherals FlexCAN(2) GPMI Connectivity peripherals i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 7 Table 4. i.MX28 Digital and Analog Modules (continued) Block Mnemonic HSADC Block Name High-speed ADC Subsystem Connectivity peripherals Brief Description The high-speed ADC block is designed to sample an analog input with 12-bit resolution and a sample rate of up to 2 Msps. The output of the HSADC block can be moved to the external memory through APBH-DMA. A typical user case of the HSADC is to work with the PWM block to drive an external linear image scanner sensor. The I2C is a standard two-wire serial interface used to connect the chip with peripherals or host controllers. The I2C operates up to 400 kbps in either I2C master or I2C slave mode. Each I2C has a dedicated DMA channel and can also controlled by CPU in PIO or PIO queue modes. It supports both 7-bit and 10-bit device address in master mode, and has programmable 7-bit address in slave mode. The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. The interrupt collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or IRQ line of the ARM9 CPU. I2C(2) I2C module Connectivity peripherals ICOLL Interrupt Collector 3-Port L2 Switch System control L2 Switch LCDIF Network Control Programmable 3-Port Ethernet Switch with QOS The LCDIF provides display data for external LCD panels from simple text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF supports all of these different interfaces by providing fully programmable functionality and sharing register space, FIFOs, and ALU resources at the same time. The LCDIF supports RGB (DOTCLK) modes as well as system mode including both VSYNC and WSYNC modes. The sixteen-channel 12-bit low-resolution ADC (LRADC) block is used for voltage measurement. Channels 0 – 6 measure the voltage on the seven application-dependent LRADC pins. The auxiliary channels can be used for a variety of uses, including a resistor-divider-based wired remote control, external temperature sensing, touch-screen, and other measurement functions. The on-chip one-time-programmable (OCOTP) ROM serves the functions of hardware and software capability bits, Freescale operations and unique-ID, the customer-programmable cryptography key, and storage of various ROM configuration bits. Used for general purpose input/output to external ICs. Each GPIO bank supports 32 bits of I/O. LCD Interface Multimedia peripherals LRADC Low resolution Connectivity ADC module peripherals OCOTP Controller On-chip OTP controller Security PINCTRL Pin control and GPIO System control peripherals i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 8 Freescale Semiconductor Table 4. i.MX28 Digital and Analog Modules (continued) Block Mnemonic PMU Block Name Subsystem Brief Description The i.MX28 integrates a comprehensive power supply subsystem, including the following features: • One integrated DC-DC converter that supports Li-Ion battery. • Four linear regulators directly power the supply rails from 5-V. • Linear battery charger for Li-Ion cells. • Battery voltage and brownout detection monitoring for VDDD, VDDA, VDDIO, VDD4P2 and 5-V supplies. • Integrated current limiter from 5-V power source. • Reset controller. • System monitors for temperature and speed. • Generates USB-Host 5-V from Li-Ion battery (using PWM). • Support for on-the-fly transitioning between 5-V and battery power. • VDD4P2, a nominal 4.2-V supply, is available when the i.MX28 is connected to a 5-V source and allows the DCDC to run from a 5-V source with a depleted battery. • The 4.2-V regulated output also allows for programmable current limits: – Battery Charge current + DCDC input current < the 5-V current limit – DCDC input current (which ultimately provides current to the on-chip and off-chip loads) as the priority and battery charge current is automatically reduced if the 5-V current limit is reached There are eight PWM output controllers that can be used in place of GPIO pins. Applications include HSADC driving signals and LED & backlight brightness control. Independent output control of each phase allows 0, 1, or high-impedance to be independently selected for the active and inactive phases. Individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. The pixel pipeline (PXP) is used to perform alpha blending of graphic or video buffers with graphics data before sending to an LCD display. The PXP also supports image rotation for hand-held devices that require both portrait and landscape image support. The real-time clock (RTC) and alarm share a one-second pulse time domain. The watchdog reset and millisecond counter run on a one-millisecond time domain. The RTC, alarm, and persistent bits reside in a special power domain (crystal domain) that remains powered up even when the rest of the chip is in its powered-down state. SAIF provides a half-duplex serial port for communication with a variety of serial devices, including industry-standard codecs and DSPs. It supports a continuous range of sample rates from 8 kHz–192 kHz using a high-resolution fractional divider driven by the PLL. Samples are transferred to/from the FIFO through the APBX DMA interface, a FIFO service interrupt, or software polling. The Sony-Philips Digital Interface Format (SPDIF) transmitter module transmits data according to the SPDIF digital audio interface standard (IEC-60958). Power Power management management Unit (DC-DC) system PWM(8) Pulse width modulation Connectivity peripherals PXP Pixel Pipeline Multimedia RTC Real-time clock, alarm, watchdog Clocks SAIF(2) Serial audio interface Connectivity peripherals SPDIF SPDIF Connectivity peripherals i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 9 Table 4. i.MX28 Digital and Analog Modules (continued) Block Mnemonic SSP(4) Block Name Synchronous serial port Subsystem Connectivity peripherals Brief Description The synchronous serial port is a flexible interface for inter-IC and removable media control and communication. The SSP supports master operation of SPI, Texas Instruments SSI; 1-bit, 4-bit, and 8-bit SD/SDIO/MMC and 1-bit and 4-bit MS modes. The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP also supports slave operation for the SPI and SSI modes. The SSP has a dedicated DMA channel in the bridge and can also be controlled directly by the CPU through PIO registers. Each of the four SSP modules is independent of the other and can have separate SSPCLK frequencies. This module implements four timers and a rotary decoder. The timers and decoder can take their inputs from any of the pins defined for PWM, rotary encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM pins can be inputs or outputs, depending on the application. The USB module provides high-performance USB On-The-Go (OTG) and host functionality (up to 480 Mbps), compliant with the USB 2.0 specification and the OTG supplement. The module has DMA capabilities for handling data transfer between internal buffers and system memory. When the OTG controller works in device mode, it can only work in FS or HS mode. Two USB2.0 PHYs are also integrated (one for the OTG port, another for the host port.) The integrated USB 2.0 PHY macrocells are capable of connecting to USB host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed (FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps. The integrated PHYs provide a standard UTM interface. The USB_DP and USB_DN pins connect directly to a USB connector. TIMROT Timers and Rotary Decoder High-speed USB on-the-go Timer peripherals USBOTG USBHOST Connectivity peripherals USBPHY Integrated USB PHY Connectivity peripherals 2.1 Special Signal Considerations Special signal considerations are listed in Table 5. The package contact assignment is found in Section 4, “Package Information and Contact Assignments.” Signal descriptions are provided in the reference manual. Table 5. Signal Considerations Signal PSWITCH Descriptions The pin is used for chip power on or recovery. VDDIO can be applied to PSWITCH through a 10 kΩ resistor. This is necessary in order to enter the chip’s firmware recovery. The on-chip circuitry prevents the actual voltage on the pin from exceeding acceptable levels. This pin is an output of i.MX28. Should be coupled to ground with a 0.1 uF capacitor. User should not supply external power to this pin. This pin should be connected to the battery with minimal resistance. It provides charging current to the battery. See the “Power Supply” section of the reference manual for details. VDDXTAL BATTERY i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 10 Freescale Semiconductor Table 5. Signal Considerations (continued) Signal DCDC_BATTERY Descriptions This pin is an input of i.MX28 that provides supply to the DCDC converter. It should be connected to the battery with minimal resistance. See the “Power Supply” section of the reference manual for details. These analog pins are connected to an external 24 MHz crystal circuit. This crystal provides the clock source for on-chip PLLs. These analog pins are connected to an external 32.768/32.0 kHz crystal circuit. This crystal provides clock source to the on-chip real-time counter circuits. This pin resets the chip if it is low. This pin is pulled up to VDDIO33 with an internal 10 kohm resistor. No external pull up resistors are needed. This pin is used for JTAG interface. DEBUG=0: JTAG interface works for boundary scan. DEBUG=1: JTAG interface works for ARM debugging. For Freescale factory use only. Must be externally connected to GND for normal operation. XTALI XTALO RTC_XTALO RTC_XTALI RESETN DEBUG TESTMODE 3 3.1 Electrical Characteristics i.MX28 Device-Level Conditions This section provides the device-level and module-level electrical characteristics for the i.MX28. This section provides the device-level electrical characteristics for the IC. 3.1.1 DC Absolute Maximum Ratings CAUTION Stresses beyond those listed under Table 7 may cause permanent damage to the device. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 6 gives stress ratings only—functional operation of the device is not implied beyond the conditions indicated in Table 8. Table 6. DC Absolute Maximum Ratings Parameter Symbol BATT, VDD4P2V VDD5V VDD5V — Min. –0.3 –0.3 –0.3 –0.3 Max. 4.242 7.00 6.00 BATT/2 Units V V V V Table 7 provides the DC absolute maximum operating conditions. • • • Battery Pin 5-Volt Source Pin - transient, t300 kΩ) when the voltage applied to it is less than 1.5V. However, above 1.5V it becomes lower impedance. To simplify design, it is recommended that a 10 kΩ resistor to VDDIO be applied to PSWITCH to set the HIGH LEVEL state (the PSWITCH input can tolerate voltages greater than 2.45 V as long as there is a 10 kΩ resistor in series to limit the current). Table 12 shows the power consumption. Table 12. Power Consumption Parameter Power Consumption: Conditions - TBD Min — Typ TBD Max — Units mW i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 14 Freescale Semiconductor Table 13 illustrates the power supply characteristics. Table 13. Power Supply Characteristics Parameter Linear Regulators Output Voltage Accuracy (VDDIO, VDDA, VDDM, VDDD)1 VDDIO Maximum Output Current (VDDIO = 3.30 V, VDD5V = 4.75 V)2, 3 VDDIO Maximum Output Current (VDDIO = 3.30 V, VDD5V = 4.40 V)2, 3 VDDM Maximum Output Current (VDDM = 1.5 V)2 VDDA Maximum Output Current (VDDA = 1.8 V)2, 3 VDDD Maximum Output Current (VDDD = 1.2 V)2, 3 DCDC Converters Output Voltage Accuracy (DCDC_VDDIO, DCDC_VDDA, DCDC_VDDD)1 DCDC_VDDD Maximum Output Current (VDDD = 1.55 V)4, 5 DCDC_VDDA Maximum Output Current (VDDA = 1.8 V)4, 5 –3 250 200 250 — — — — +3 — — — % mA mA mA –3 270 200 160 225 200 — — — — — — +3 — — — — — % mA mA mA mA mA Min Typ Max Units DCDC_VDDIO Maximum Output Current (VDDIO = 3.15 V, 3.3 V < BATT < 4.242 V)4, 5, 6 VDD4P2 Regulated Output VDD4P2 Output Voltage Accuracy (TARGET=4.2V)1 VDD4P2 Output Current Limit Accuracy (VDD5V = 4.75 V, ILIMIT=480 mA)7 VDD4P2 Output Current Limit Accuracy (VDD5V=4.75 V, ILIMIT=100 mA)7 Battery Charger Final Charge Voltage Accuracy (TARGET=4.2 V) 1 2 3 –3 TBD TBD — 480 100 +3 TBD TBD % mA mA -2 — +1 % 4 5 6 No load. Maximum output current measured when output voltage droops 100 mV from the programmed target voltage with no load present. Because the internal linear regulators are cascaded, it is not possible to simultaneously operate the VDDIO, VDDA, VDDM, and VDDD linear regulators at the maximum specified load current. For example, the VDDIO linear regulator provides current to both the VDDIO 3.3 V supply rail as well as the VDDM and VDDA linear regulator inputs. Likewise, the VDDA linear regulator provides current to both the 1.8 V supply rail as well as the VDDD linear regulator input. The application designer should ensure the following two conditions are met: (VDDIO Load Current + VDDM Load Current + VDDA Load Current) < VDDIO Maximum Output Current (VDDA Load Current + VDDD Load Current) < VDDA Maximum Output Current DCDC Double FETs Enabled, Inductor Value = 15 μH. The DCDC Converter is a triple output buck converter. The maximum output current capability of each output of the converter is dependent on the loads on the other two outputs. For a given output, it may be possible to achieve a maximum output current higher than that specified by ensuring the load on the other outputs is well below the maximum. Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 mA@1.8 V. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 15 7 Untuned. 3.1.2.1 Recommended Operating Conditions for Specific Clock Targets Table 14. System Clocks Table 14 through Table 18 provide the recommended operating conditions for specific clock targets. Name clk_gpmi clk_ssp Min. Freq. (MHz) — — Max. Freq. (MHz) TBD TBD Description General purpose memory interface clock domain SSP interface clock domain Table 15. Recommended Operating States—289-Pin BGA Package HW_ DIGCTRL ARMCACH E1 CPUCLK / clk_p Frequency (MHz) HW_ CLKCTRL CPU_DIV_CP U HW_ CLKCTRL FRAC_ CPUFRC / PFD AHBCLK / clk_h Frequency (MHz) HW_ CLKCTRL HBUS_DI V EMICLK / clk_emi Frequency (MHz) HW_ HW_ CLKCTRL CLKCTRL EMI_ DIV_EMI FRAC_ EMIFRAC VDDD (V) VDDD Brown-out (V) Supported DRAM TBD 1.350 1.350 1.450 1.550 1 TBD 1.250 1.250 1.350 1.450 00 00 00 00 00 64 261.81 360 392.72 454.73 5 1 1 1 1 27 33 24 22 19 64 130.91 120.00 130.91 151.57 1 2 3 3 3 130.91 130.91 130.91 160.00 205.71 2 2 2 2 2 33 33 33 27 21 DDR2 mDDR DDR2 mDDR DDR2 mDDR DDR2 mDDR DDR2 mDDR All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 16. Recommended Operating Conditions—CPU Clock (clk_p) Minimum VDDD (V) TBD 1.350 1.450 1.550 1 Minimum VDDDBrown-out (V) TBD 1.250 1.350 1.450 HW_DIGCTRL ARMCACHE1 00 00 00 00 HW_CLKCTRL CPUCLK / clk_p FRAC_CPUFRC / PFD Frequency max (MHz) 27 - 35 18 - 35 18 - 35 18 - 35 TBD 360 392.72 454.73 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 16 Freescale Semiconductor Table 17. Recommended Operating Conditions—AHB Clock (clk_h) Minimum VDDD (V) TBD 1.350 1.450 1.550 1 Minimum VDDDBrown-out (V) TBD 1.250 1.350 1.45 HW_DIGCTRL ARMCACHE1 00 00 00 00 HW_CLKCTRL AHBCLK / clk_h FRAC_CPUFRC / PFD Frequency max (MHz) 27 - 35 18 - 35 18 - 35 18 - 35 TBD 160 196 206 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 18. Frequency vs. Voltage for EMICLK—289-Pin BGA Package Minimum VDDD (V) 1.550 1.450 1.350 Minimum VDDDBrownout (V) 1.450 1.350 1.250 EMICLK Fmax (MHz) DDR2 205.71 196.36 196.36 mDDR 205.71 196.36 196.36 3.1.3 Fusebox Supply Current Parameters Table 19. Fusebox Supply Current Parameters Parameter Symbol Iprogram Min 21.39 Typ 25.05 Max 33.54 Units mA Table 19 lists the fusebox supply current parameters. eFuse Program Current1 Current to program one eFuse bit efuse_vddq=2.5V eFuse Read Current2 Current to read an 8-bit eFuse word vdd_fusebox = 3.3 V 1 2 Iread — — 4.07 mA The current Iprogram is during program time. The current Iread is present for approximately 10 ns of the read access to the 8-bit word. 3.1.4 Interface Frequency Limits Table 20. Interface Frequency Limits Parameter JTAG: TCK Frequency of Operation OSC24M_XTAL Oscillator OSC32K_XTAL Oscillator Min. — — — Typ. — 24.000 32.768/32.0 Max. 10 — — Units MHz MHz KHz Table 20 provides information for interface frequency limits. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 17 3.1.5 Power Modes Table 21. Power Mode Settings Core/Clock/Module ARM Core USB0 PLL (System PLL) OSC24M OSC32K DCDC RTC Other Modules Deep-Sleep Off Off Off On Off On Off Standby Off Off On On On On On/Off Run On On On On On On On/Off Table 21 describes the core, clock, and module settings for the different power modes of the processor. 3.1.6 Supply Power-Up/Power-Down Requirements There is no special power-up sequence. After applying 5 V or battery in any order, the rest of the power supplies are internally generated and automatically come up in a safe way. There is no special power-down sequence. 5 V or the battery can be removed at any time. 3.1.7 Reset Timing Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing requirement on external pins. The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting RESETN. If the reset occurs while the device is only powered by the battery, then the reset kills all of the power supplies and the system reboots on the assertion of PSWITCH. If auto-restart is set up ahead of time, the system reboots immediately. If the chip is powered by 5 V, then the reset serves to reset the digital sections of the chip. If the DCDC is operating at the time of the reset, then power switches back to the default linear regulators powered by 5 V. RESETN At least 100ms Figure 2. RESETN Timing i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 18 Freescale Semiconductor 3.2 Thermal Characteristics The thermal resistance characteristics for the device are given in Table 22. These values are measured under the following conditions: • Two layer Substrate • Substrate solder mask thickness: 0.025 mm • Substrate metal thicknesses: 0.016 mm • Substrate core thickness: 0.160 mm • Core via I.D: 0.068 mm, Core via plating 0.016 mm • Flag: trace style with ground balls under the die connected to the flag • Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K • Mold Compound: generic mold compound, k = 0.9 W/m K Table 22. Thermal Resistance Data Rating Junction to ambient1 natural convection Junction to ambient1 natural convection Junction to ambient1 (@200 ft/min) Junction to ambient1 (@200 ft/min) Junction to boards2 Junction to case (top)3 Natural Convection Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) RθJA RθJA RθJMA RθJMA RθJB RθJCtop ΨJT Value 62 36 53 33 24 15 3 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Junction to package top4 1 Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-2 and JESD51-6. Thermal test board meets JEDEC specification for this package. 2 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 3 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3.3 I/O DC Parameters This section includes the DC parameters of the following I/O types: • DDR I/O: Mobile DDR (LPDDR1), standard 1.8 V DDR2, and low-voltage 1.5 V DDR2 (LVDDR2) • General purpose I/O (GPIO) i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 19 3.3.1 DDR I/O DC Parameters NOTE The current values and the I-V curves of the I/O DC characteristics are estimated based on an overly conservative device model. They are updated upon the measurement results of the first silicon. Table 23. EMI Digital Pin DC Characteristics Parameter Symbol VIH VIL VOH VOL IOH 1—Low Table 23 shows the EMI digital pin DC characteristics. Min. VREF + 0.125 0.3 0.8 * VDDIO_EMI TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max. VDDIO_EMI + 0.3 VREF – 0.125 — 0.2 * VDDIO_EMI TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Units V V V V mA mA mA mA mA mA mA mA mA mA mA mA Input voltage high (dc) Input voltage low (dc) Output voltage high (dc) Output voltage low (dc) Output source current (dc) LVDDR2 Mode IOH—Medium IOH—High Output sink current (dc) LVDDR2 Mode IOL2—Low IOL—Medium IOL—High Output source current (dc) mDDR, DDR2 Mode IOH—Low IOH—Medium IOH—High Output sink current (dc) mDDR, DDR2 Mode IOL—Low IOL—Medium IOL—High 1 2 IOH is the output current at which the VOH specification is met. IOL is the output current at which the VOL specification is met. Table 24 shows the ON impedance of EMI drivers for different drive strengths. Table 24. ON Impedance of EMI Drivers for Different Drive Strengths Mode 1.5 LVDDR2 Drive Low Medium High Min. (Ω) TBD TBD TBD Typ. (Ω) TBD TBD TBD Max. (Ω) TBD TBD TBD i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 20 Freescale Semiconductor Table 24. ON Impedance of EMI Drivers for Different Drive Strengths (continued) Mode 1.8 DDR2/mDDR Drive Low Medium High Min. (Ω) TBD TBD TBD Typ. (Ω) TBD TBD TBD Max. (Ω) TBD TBD TBD Table 25 shows the external devices supported by the EMI. Table 25. External Devices Supported by the EMI DRAM Device DDR2 mDDR LVDDR2 1 2 Max Load1, 2 15 pF 15 pF 15 pF Pad Voltage 1.8 V 1.8 V 1.5 V Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. Setting is for worst case. Freescale’s EMI interface uses less powerful drivers than those typically used in mDDR devices. A possible transmission-line effect on the PC board must be suppressed by minimizing the trace length combined with Freescale’s slower edge-rate drivers. The i.MX28 provides up to 16 mA programmable drive strength. However, the 16-mA mode is an experimental mode. With the 16-mA mode, the EMI function may be impaired by Simultaneous Switching Output (SSO) noise. In general, the stronger the driver mode, the noisier the on-chip power supply. Freescale recommends not using a stronger driver mode than is required. Because on-chip power and ground noise is proportional to the inductance of its return path, users should make their best effort to reduce inductance between the EMI power and ground balls and the PC board power and ground planes. 3.3.2 GPIO I/O DC Parameters Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. For the internal pull up setting of each pad, see the “Pin Control and GPIO” section of the reference manual. Table 26 shows the digital pin DC characteristics for GPIO in 3.3-V mode. Measurements are valid for eight pins loaded using the 4mA driver, four pins loaded using the 8mA driver, and two pins loaded using either the 12mA or 16mA driver. Table 26. Digital Pin DC Characteristics for GPIO in 3.3-V Mode Parameter Input voltage high (dc) Input voltage low (dc) Output voltage high (dc) Output voltage low (dc) Output source current1 (dc) gpio Symbol VIH VIL VOH VOL IOH – Low IOH – Medium IOH – High Min 2 — 0.8 × VDDIO — -5.0 -9.5 -11.4 Max VDDIO 0.8 — 0.4 — — — Units V V V V mA mA mA i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 21 Table 26. Digital Pin DC Characteristics for GPIO in 3.3-V Mode (continued) Parameter Output sink current1 (dc) gpio Symbol IOL – Low IOL – Medium IOL – High Output source current1 (dc) gpio_clk Output sink current1 (dc) gpio_clk 10-K pull-up resistance2 47-K pull-up resistance2 1 Min 3.8 7.7 9.0 -9.2 -15.2 7.6 12.0 8 39 Max — — — — — — — 12 56 Units mA mA mA mA mA mA mA KΩ KΩ IOH – Low IOH – High IOL – Low IOL – High Rpu10k Rpu47k The conditions of the current measurements for all different drives are as follows: IOL: at 0.4 V IOH: at VDDIO * 0.8 V Maximum corner for 3.3 V mode: 3.6 V, -40°C, fast process. Minimum corner for 3.3 V mode: 3.0 V, 105°C, slow process 8 gpio pins (LCD_D0-D7) and 2 gpio_clk pins (LCD_DOTCLK and LCD_WR_RWN) simultaneously loaded. 2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 22 Freescale Semiconductor Table 27 shows the digital pin DC characteristics for GPIO in 1.8 V mode. Table 27. Digital Pin DC Characteristics for GPIO in 1.8 V Mode Symbol Input voltage high (DC) Input voltage low (DC) Output voltage high (DC) Output voltage low (DC) Output source current (DC) gpio Output sink current1 (DC) gpio current1 1 Min 0.7 × VDDIO18 — 0.8 * VDDIO18 — -2.2 -3.5 -4.0 3.3 7.0 7.5 -4.2 -6.0 6.8 11.5 8 39 Max VDDIO18 0.3 × VDDIO18 — 0.2 × VDDIO18 — — — — — — — — — — 12 56 Units V V V V mA mA mA mA mA mA mA mA mA mA KΩ KΩ VIH VIL VOH VOL IOH – low IOH – medium IOH – high IOL – low IOL – medium IOL – high Output source (DC) gpio_clk IOH – low IOH – high IOL – low IOL – high Rpu10k Rpu47k Output sink current1 (DC) gpio_clk 10-K pull-up resistance2 47-K pull-up resistance2 1 The condition of the current measurements for all different drives are as follows: Maximum corner for 1.8 V mode: 1.9 V, -40°C, Fast process. Minimum corner for 1.8 V mode: 1.7 V, 105°C, Slow process. 1 gpio pin (GPMI_D0) and 1 gpio_clk pin (GPMI_WRN) simultaneously loaded. 2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 23 3.4 I/O AC Timing and Parameters Figure 3 and Figure 4 show the Driver Used for AC Simulation Testpoint and the Output Pad Transition Waveform. Driver Used for AC simulation Testpoint Figure 3. Driver Used for AC Simulation Testpoint Output Pad Transition Waveform VDDIO 80% 20% Figure 4. Output Pad Transition Waveform Table 28 shows the base GPIO AC timing and parameters. Table 28. Base GPIO Parameters Duty cycle Output pad transition times (maximum drive) Symbol Fduty tpr Test Voltage — 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Test Capacitance — 10pF 20pF 50pF 10pF 20pF 50pF 0.82 1.18 2.11 1.04 1.42 2.46 Min Rise/Fall — 0.91 1.22 2.03 1.08 1.5 2.61 1.93 2.69 4.62 2.46 3.29 5.34 MaxRise/Fall — 1.97 2.71 4.44 2.18 3 5.12 Units % ns Notes — — — — — — — i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 24 Freescale Semiconductor Table 28. Base GPIO (continued) Parameters Output pad transition times (medium drive) Symbol tpr Test Voltage 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad transition times (low drive) tpr 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad slew rate (maximum drive) tps 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad slew rate (medium drive) tps 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad slew rate (low drive) tps 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Input pad average hysteresis tih 1.7 V–1.9 V 3.0 V–3.6 V Test Capacitance 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF — — Min Rise/Fall 1.02 1.51 2.91 1.26 1.8 3.3 1.62 2.55 5.42 1.95 2.96 5.89 1.39 0.97 0.54 2.08 1.52 0.88 1.12 0.75 0.39 1.71 1.20 0.65 1.17 0.75 0.35 1.11 0.73 0.37 1.08 1.5 2.62 1.29 1.88 3.46 1.68 2.45 4.62 2.12 3.21 6.39 1.25 0.93 0.56 2.00 1.44 0.83 1.06 0.76 0.44 1.67 1.15 0.62 1.13 0.78 0.41 1.02 0.67 0.34 MaxRise/Fall 2.34 3.34 6.24 2.9 4 6.91 3.65 5.59 2.38 3.28 5.67 2.6 3.67 6.64 3.68 5.37 ns Units ns Notes — — — — — — — — — — — — V/ns — — — — — — V/ns — — — — — — V/ns — — — — — — mV — — 11.46 10.01 4.43 6.36 4.25 6.25 12.02 12.18 0.53 0.38 0.22 0.73 0.55 0.34 0.44 0.31 0.16 0.62 0.45 0.26 0.47 0.30 0.15 0.41 0.28 0.15 75 50 0.52 0.38 0.23 0.83 0.60 0.35 0.43 0.31 0.18 0.69 0.49 0.27 0.46 0.32 0.17 0.42 0.29 0.15 100 100 i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 25 Table 29 shows the F-type GPIO AC timing and parameters. Table 29. F-type GPIO Parameters Duty cycle Output pad transition times (maximum drive) Symbol Fduty tpr Test Voltage — 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad transition times (medium drive) tpr 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad transition times (low drive) tpr 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad slew rate (maximum drive) tps 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad slew rate (medium drive) tps 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Test Capacitance Min Rise/Fall Max Rise/Fall — 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 0.58 0.89 1.83 0.71 1.02 1.98 0.76 1.23 2.66 0.9 1.36 2.85 1.32 2.27 5.23 1.46 2.46 5.56 1.97 1.28 0.62 3.04 2.12 1.09 1.50 0.93 0.43 2.40 1.59 0.76 — 0.61 0.88 1.59 0.68 1.04 2.09 0.76 1.13 2.18 0.88 1.4 3.02 1.26 1.98 4.13 1.55 2.62 5.96 1.87 1.30 0.72 3.18 2.08 1.03 1.50 1.01 0.52 2.45 1.54 0.72 1.29 1.94 3.88 1.47 2.11 3.97 1.68 2.63 5.61 1.84 2.76 5.59 2.88 4.84 10.95 3.05 4.92 10.78 0.79 0.53 0.26 1.22 0.85 0.45 0.61 0.39 0.18 0.98 0.65 0.32 — 1.33 1.88 3.39 1.34 1.99 3.96 1.61 2.38 4.6 1.7 2.67 5.67 2.72 4.23 8.8 3 5.02 11.22 0.77 0.54 0.30 1.34 0.90 0.45 0.63 0.43 0.22 1.06 0.67 0.32 ns ns ns ns Units % ns Notes — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 26 Freescale Semiconductor Table 29. F-type GPIO (continued) Parameters Output pad slew rate (low drive) Symbol tps Test Voltage 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Input pad average hysteresis tih 1.7 V–1.9 V 3.0 V–3.6 V Test Capacitance Min Rise/Fall Max Rise/Fall 10pF 20pF 50pF 10pF 20pF 50pF — — 1.44 0.84 0.36 1.48 0.88 0.39 1.51 0.96 0.46 1.39 0.82 0.36 0.59 0.35 0.16 0.59 0.37 0.17 75 50 0.63 0.40 0.19 0.60 0.36 0.16 mV Units ns Notes — — — — — — — — 100 100 Table 30 shows the CLK-type GPIO AC timing and parameters. Table 30. CLK-Type GPIO Parameters Duty cycle Output pad transition times (maximum drive) Symbol Fduty tpr Test Voltage Test Capacitance — 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad transition times (medium drive) tpr 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Output pad slew rate (maximum drive) tps 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V — 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 10pF 20pF 50pF 0.48 0.72 1.41 0.61 0.85 1.56 0.76 1.22 2.66 0.9 1.37 2.85 2.38 1.58 0.81 3.54 2.54 1.38 Min Rise/Fall — 0.52 0.74 1.28 0.57 0.85 1.63 0.76 1.14 2.2 0.89 1.41 3.03 2.19 1.54 0.89 3.79 2.54 1.33 1.08 1.56 3.04 1.25 1.73 3.13 1.67 2.64 5.61 1.83 2.77 5.59 0.94 0.65 0.34 1.44 1.04 0.58 Max Rise/Fall — 1.12 1.56 2.7 1.12 1.63 3.08 1.62 2.41 4.62 1.72 2.69 5.72 0.91 0.65 0.38 1.61 1.10 0.58 ns ns units % ns Notes — — — — — — — — — — — — — — — — — — — i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 27 Table 30. CLK-Type GPIO (continued) Parameters Output pad slew rate (medium drive) Symbol tps Test Voltage Test Capacitance 1.7~1.9V 1.7~1.9V 1.7~1.9V 3.0~3.6V 3.0~3.6V 3.0~3.6V Input pad average hysteresis tih 1.7 V–1.9 V 3.0 V–3.6 V 10pF 20pF 50pF 10pF 20pF 50pF — — Min Rise/Fall 1.50 0.93 0.43 2.40 1.58 0.76 100 100 1.50 1.00 0.52 2.43 1.53 0.71 Max Rise/Fall 0.61 0.39 0.18 0.98 0.65 0.32 75 50 0.63 0.42 0.22 1.05 0.67 0.31 mV units ns Notes — — — — — — — — 3.5 3.5.1 Module Timing and Electrical Parameters ADC Electrical Specifications This section describes the electrical specifications, including DC and AC information, of Low-Resolution ADC (LRADC) and High-Speed ADC (HSADC). 3.5.1.1 LRADC Electrical Specifications Table 31. LRADC Electrical Specifications Table 31 shows the electrical specifications for the LRADC. Parameter Conditions AC Electrical Specification Min. Typ. Max. Unit Input capacitance (Cp) Resolution Maximum sampling rate1 (fs) Power-up time2 No pin/pad capacitance included — — — DC Electrical Specification — 0.5 12 — pF bits — — 1 428 kHz sample cycles DC input voltage Current consumption VDDA VDDD 3 0 — — TBD 1.85 — V mA mA Touchscreen Interface Expected plate resistance 1 — 200 — 50000 Ω There is no sample and hold circuit in LRADC, so it is only for DC input voltage or ones with very small slope. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 28 Freescale Semiconductor 2 3 This comprises only the required initial dummy conversion cycle, NOT including the Analog part power-up time. This value only includes the ADC and the driver switches, but it does not take into account the current consumption in the touchscreen plate. For example, if the plate resistance is 200 ohm, the total current consumption is about 11 mA. 3.5.1.2 HSADC Electrical Specification Table 32. HSADC Electrical Specification Table 32 shows the electrical specifications for the HSADC Parameter Conditions AC Electrical Specification Min. Typ. Max. Unit Input sampling capacitance (Cs) Resolution Maximum sampling rate (fs) Power-up time No pin/pad capacitance included — — — — 0.5 12 — pF bits — — 1 2 MHz sample cycles DC Electrical Specification DC input voltage Current Consumption VDDA VDDD DNL INL fin = 1 kHz fin = 1kHz — — 0.5 — — TBD VDDA-0.5 — V mA mA LSB LSB — — — — TBD TBD 3.5.2 DPLL Electrical Specifications This section includes descriptions of the USB PLL electrical specifications and Ethernet PLL electrical specifications. 3.5.2.1 USB PLL Electrical Specifications The i.MX28 integrates a high-frequency USB PLL that provides the 480-MHz clock for the USB and other system blocks. Table 33 lists the USB PLL output electrical specifications. Table 33. USB PLL Specifications Parameter PLL lock time Test Conditions — Min — Typ — Max 10 Unit µs i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 29 3.5.2.2 Ethernet PLL Electrical Specifications i.MX28 provides a 50-MHz/25-MHz output clock, called the Ethernet PLL output. Table 34 lists the Ethernet PLL output electrical specifications. Table 34. Ethernet PLL Specifications Parameter Output Duty Cycle PLL lock time Cycle to cycle jitter Clock output frequency tolerance1 1 Test Conditions — — — — Min 45 — — — Typ 50 — 25 — Max 55 10 — +/-20 Unit % µs ps ppm This Ethernet output clock tolerance specification is the contribution from the PLL only and assumes a perfect 24 MHz clock/crystal source with 0 ppm deviation. The 24 MHz crystal frequency tolerance/deviation should be added to this number for the total Ethernet clock output frequency tolerance. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 30 Freescale Semiconductor 3.5.3 EMI AC Timing This section includes descriptions of the electrical specifications of EMI module which interfaces external DDR2 and Mobile-DDR1 (LP-DDR1) memory devices. 3.5.3.1 EMI Command & Address AC Timing Figure 5 and Table 35 specify the timing related to the address and command pins that interfaces DDR2 and Mobile-DDR1 memory devices. DDR2 EMI_CLKN EMI_CLK DDR1 EMI_CE0N DDR4 EMI_RASN DDR5 DDR3 EMI_CASN DDR4 EMI_WEN DDR4 EMI_ADDR bank row bank column DDR5 DDR5 Figure 5. EMI Command/Address AC Timing Table 35. EMI Command/Address AC Timing ID DDR1 DDR2 Description CK cycle time CK high level width Symbol tCK tCH Min. 4.86 0.5 tCK –0.5 Max. — 0.5 tCK + 0.5 Unit ns ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 31 Table 35. EMI Command/Address AC Timing (continued) ID DDR3 DDR4 DDR5 Description CK low level width Address and control output setup time Address and control output hold time Symbol tCL tIS tIH Min. 0.5 tCK –0.5 0.5 tCK – 1 0.5 tCK – 1 Max. 0.5 tCK + 0.5 0.5 tCK + 0.5 0.5 tCK + 0.5 Unit ns ns ns 3.5.3.2 DDR Output AC Timing Figure 6 and Table 36 show the DDR output AC timing defined for all DDR types: LPDDR1, standard DDR2 (1.8 V), and LVDDR2 (1.5 V) EMI_CLKN EMI_CLK DDR10 DDR11 EMI_DQSN EMI_DQS DDR13 DDR14 DDR12 EMI_DQ & EMI_DQM d0 d1 d2 DDR15 d3 DDR16 Figure 6. DDR Output AC Timing Table 36. DDR Output AC Timing ID DDR10 DDR11 Description Positive DQS latching edge to associated CK edge DQS falling edge from CK rising edge—hold time Symbol tDQSS tDSH Min –0.5 0.5 tCK –0.5 0.5 tCK –0.5 0.5 0.5 tCK + 0.5 0.5 tCK + 0.5 Max ns ns Unit DDR12 DQS falling edge to CK rising edge—setup time tDSS ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 32 Freescale Semiconductor Table 36. DDR Output AC Timing (continued) ID DDR13 Description DQS output high pulse width Symbol tDQSH Min 0.5 tCK –0.5 0.5 tCK –0.5 1/4 tCK –0.8 1/4 tCK –0.8 Max 0.5 tCK + 0.5 0.5 tCK + 0.5 1/4 tCK –0.5 1/4 tCK –0.5 ns Unit DDR14 DQS output low pulse width tDQSL ns DDR15 DQ & DQM output setup time relative to DQS tDS ns DDR16 DQ & DQM output hold time relative to DQS tDH ns 3.5.3.3 DDR2 Input AC Timing Figure 7 and Table 37 show input AC timing for standard DDR2 and LVDDR2. EMI_CLKN EMI_CLK DDR20 EMI_DQSN EMI_DQS DDR22 DDR21 EMI_DQ d0 d1 d2 d3 Figure 7. DDR2 Input AC Timing Table 37. DDR2 Input AC Timing ID DDR20 DDR21 DQS to DQ input skew DDR22 DQS to DQ input hold time tQH Description Positive DQS latching edge to associated CK edge Symbol tDQSCK tDQSQ Min –0.5 0.25 tCK –0.85 0.25 tCK +0.75 0.5 0.25 tCK –0.5 0.25 tCK +1 Max ns ns Unit ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 33 3.5.3.4 LPDDR1 Input AC Timing Figure 8 and Table 38 show input AC timing for LPDDR1. EMI_CLKN EMI_CLK DDR20 EMI_DQSN EMI_DQS DDR22 DDR21 EMI_DQ d0 d1 d2 d3 Figure 8. LPDDR1 Input AC Timing Table 38. DDR2 Input AC Timing ID DDR20 DDR21 Description Positive DQS latching edge to associated CK edge DQS to DQ input skew Symbol tDQSCK tDQSQ 2 0.25 tCK –0.85 0.25 tCK +0.75 Min 6 0.25 tCK –0.5 0.25 tCK +1 Max ns ns Unit DDR22 DQS to DQ input hold time tQH ns 3.5.4 Ethernet MAC Controller (ENET) Timing The ENET is designed to support both 10- and 100-Mbps Ethernet networks compliant with IEEE 802.3. An external transceiver interface and transceiver function are required to complete the interface to the media. The ENET supports 10/100-Mbps MII (18 pins altogether), 10/100-Mbps RMII (10 pins, including serial management interface), for connection to an external Ethernet transceiver. All signals are compatible with transceivers operating at a voltage of 3.3 V. The following subsections describe the timing for MII and RMII modes. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 34 Freescale Semiconductor 3.5.4.1 ENET MII Mode Timing This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings. 3.5.4.1.1 MII Receive Signal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER, and ENET0_RX_CLK) The receiver functions correctly up to an ENET0_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET0_RX_CLK frequency. Figure 9 shows MII receive signal timings. Table 39 describes the timing parameters (M1–M4) shown in the figure. M3 ENET0_RX_CLK (input) M4 ENET0_RXD[3:0] (inputs) ENET0_RX_DV ENET0_RX_ER M1 M2 Figure 9. MII Receive Signal Timing Diagram Table 39. MII Receive Signal Timing ID M1 M2 M3 M4 Characteristic1 ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER to ENET0_RX_CLK setup ENET0_RX_CLK to ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER hold ENET0_RX_CLK pulse width high ENET0_RX_CLK pulse width low Min. 5 5 35% 35% Max. — — 65% 65% Unit ns ns ENET0_RX_CLK period ENET0_RX_CLK period 1 ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode. 3.5.4.1.2 MII Transmit Signal Timing (ENET0_TXD[3:0], ENET0_TX_EN, ENET0_TX_ER, and ENET0_TX_CLK) The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET0_TX_CLK frequency. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 35 Figure 10 shows MII transmit signal timings. Table 40 describes the timing parameters (M5–M8) shown in the figure. M7 ENET0_TX_CLK (input) M5 M8 ENET0_TXD[3:0] (outputs) ENET0_TX_EN ENET0_TX_ER M6 Figure 10. MII Transmit Signal Timing Diagram Table 40. MII Transmit Signal Timing ID M5 M6 M7 M8 Characteristic1 ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN, ENET0_TX_ER invalid ENET0_TX_CLK to ENET0_TXD[3:0], ENET0_TX_EN, ENET0_TX_ER valid ENET0_TX_CLK pulse width high ENET0_TX_CLK pulse width low Min. 5 — 35% 35% Max. — 20 65% 65% Unit ns ns ENET0_TX_CLK period ENET0_TX_CLK period 1 ENET0_TX_EN, ENET0_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode. 3.5.4.1.3 MII Asynchronous Inputs Signal Timing (ENET0_CRS and ENET0_COL) Figure 11 shows MII asynchronous input timings. Table 41 describes the timing parameter (M9) shown in the figure. ENET0_CRS, ENET0_COL M9 Figure 11. MII Async Inputs Timing Diagram Table 41. MII Asynchronous Inputs Signal Timing ID M91 1 Characteristic ENET0_CRS to ENET0_COL minimum pulse width Min. 1.5 Max. — Unit ENET0_TX_CLK period ENET0_COL has the same timing in 10-Mbit 7-wire interface mode. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 36 Freescale Semiconductor 3.5.4.1.4 MII Serial Management Channel Timing (ENET0_MDIO and ENET0_MDC) The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 12 shows MII asynchronous input timings. Table 42 describes the timing parameters (M10–M15) shown in the figure. M14 M15 ENET0_MDC (output) M10 ENET0_MDIO (output) M11 ENET0_MDIO (input) M12 M13 Figure 12. MII Serial Management Channel Timing Diagram Table 42. MII Serial Management Channel Timing ID M10 M11 M12 M13 M14 M15 Characteristic ENET0_MDC falling edge to ENET0_MDIO output invalid (min. propagation delay) ENET0_MDC falling edge to ENET0_MDIO output valid (max. propagation delay) ENET0_MDIO (input) to ENET0_MDC rising edge setup ENET0_MDIO (input) to ENET0_MDC rising edge hold ENET0_MDC pulse width high ENET0_MDC pulse width low Min. 0 — 18 0 40% 40% Max. — 5 — — 60% 60% Unit ns ns ns ns ENET0_MDC period ENET0_MDC period 3.5.4.2 RMII Mode Timing In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. ENET0_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 37 Figure 13 shows RMII mode timings. Table 43 describes the timing parameters (M16–M21) shown in the figure. M16 M17 ENET_CLK (input) M18 ENET0_TXD[1:0] (output) ENET0_TX_EN M19 CRS_DV (input) ENET0_RXD[1:0] ENET0_RX_ER M20 M21 Figure 13. RMII Mode Signal Timing Diagram Table 43. RMII Signal Timing ID M16 M17 M18 M19 M20 M21 ENET_CLK pulse width high ENET_CLK pulse width low ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN invalid ENET_CLK to ENET0_TXD[1:0], ENET0_TX_EN valid ENET0_RXD[1:0], CRS_DV(ENET0_RX_DV), ENET0_RX_ER to ENET_CLK setup ENET_CLK to ENET0_RXD[1:0], ENET0_RX_DV, ENET0_RX_ER hold Characteristic Min. 35% 35% 3 — 2 2 Max. 65% 65% — 12 — — Unit ENET_CLK period ENET_CLK period ns ns ns ns 3.5.5 Coresight ETM9 AC Interface Timing The following timing specifications are given as a guide for a TPA that supports TRACECLK frequencies up to 80 MHz. 3.5.5.1 TRACECLK Timing This section describes TRACECLK timings. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 38 Freescale Semiconductor Figure 14 shows TRACECLK signal timings. Table 44 describes the timing parameters shown in the figure. Figure 14. TRACECLK Signal Timing Diagram Table 44. MII Receive Signal Timing ID Tr Tf Twh Twl Tcyc Clock and data raise time Clock and data fall time High pulse wide Low pulse wide Clock period Characteristic1 Min. 3 3 2 2 12.5 Max. — — — — — Unit ns ns ns ns ns 3.5.5.2 Trace Data Signal Timing Figure 15 shows the setup and hold requirements of the trace data pins with respect to TRACECLK. Table 45 describes the timing parameters shown in the figure. Figure 15. MII Transmit Signal Timing Diagram Table 45. MII Transmit Signal Timing ID Ts Th Data setup Data hold Characteristic1 Min. 2 2 Max. — — Unit ns ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 39 3.5.6 FlexCAN AC Timing Table 46. Tx Pin Characteristics Parameter High-level output voltage Low-level output voltage Symbol VOH VOL Table 46 and Table 47 show voltage requirements for the FlexCAN transceiver Tx and Rx pins. Min. 2 — Typ. — 0.8 Max. Vcc1 + 0.3 — Units V V 1 Vcc = +3.3 V ± 5% Table 47. Rx Pin Characteristics Parameter High-level input voltage Low-level input voltage 1 Symbol VIH VIL Min. 0.8 × Vcc1 — Typ. — 0.4 Max. Vcc1 — Units V V Vcc = +3.3 V ± 5% Figure 16 through Figure 19 show the FlexCAN timing, including timing of the standby and shutdown signals. TXD VCC/2 VCC/2 tOFFTXD 0.9V tONTXD VDIFF tONRXD RXD VCC/2 0.5V tOFFRXD VCC/2 Figure 16. FlexCAN Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 40 Freescale Semiconductor VCC x 0.75 RS Bus Externally Driven 1.1V VDIFF tSBRXDL tDRXDL RXD VCC/2 VCC/2 Figure 17. Timing Diagram for FlexCAN Standby Signal SHDN VCC/2 tOFFSHDN VCC/2 tONSHDN VDIFF 0.5V Bus Externally Driven RXD VCC/2 Figure 18. Timing Diagram for FlexCAN Shutdown Signal SHDN tSHDNSB VCC/2 0.75 x VCC RS Figure 19. Timing Diagram for FlexCAN Shutdown-to-Standby Signal i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 41 3.5.7 General-Purpose Media Interface (GPMI) Timing The i.MX28 GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 50MB/s I/O speed and individual chip select. It supports normal timing mode, using two Flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 20, Figure 21, Figure 22 and Figure 23 depict the relative timing between GPMI signals at the module level for different operations under normal mode. Table 48 describes the timing parameters (NF1–NF17) that are shown in the figures. CLE NF1 NF3 CEn NF5 WE NF6 ALE NF8 NF9 IO[7:0] Command NF7 NF2 NF4 Figure 20. Command Latch Cycle Timing Diagram CLE NF1 NF3 CEn NF10 NF11 NF5 WE NF6 ALE NF8 NF9 IO[7:0] Address NF7 NF4 Figure 21. Address Latch Cycle Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 42 Freescale Semiconductor CLE NF1 NF3 CEn NF10 NF11 NF5 WE NF6 ALE NF8 NF9 IO[7:0] Data to NF NF7 Figure 22. Write Data Latch Cycle Timing Diagram CLE CEn NF14 NF15 NF13 RE NF16 RB NF12 IO[7:0] Data from NF NF17 Figure 23. Read Data Latch Cycle Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 43 Table 48. NFC Timing Parameters1 Timing T = GPMI Clock Cycle Min. NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NF10 NF11 NF12 NF13 NF14 NF15 NF16 NF17 1 ID Parameter Symbol Example Timing for GPMI Clock ≈ 100MHz T = 10ns Min. 10 20 10 20 10 Max. — — — — Unit Max. — — — — DS*T CLE setup time CLE hold time CEn setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write cycle time WE hold time Ready to RE low RE pulse width READ cycle time RE high hold time Data setup on read Data hold on read tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR (AS+1)*T (DH+1)*T (AS+1)*T (DH+1)*T ns ns ns ns ns (AS+1)*T (DH+1)*T DS*T DH*T (DS+DH)*T DH*T (AS+1)*T DS*T (DS+DH)*T DH*T N/A N/A — — — — 10 20 10 10 20 10 — — — — ns ns ns ns ns ns — — — 10 10 20 10 10 10 — — — — — — ns ns ns ns ns ns The Flash clock maximum frequency is 100 MHz. 2)GPMI’s output timing could be controlled by module’s internal register, say HW_GPMI_TIMING0_ADDRESS_SETUP,HW_GPMI_TIMING0_DATA_SETUP,HW_GPMI_TIMING0_DATA_HOLD, this AC timing depends on these registers’ setting. In the above table we use AS/DS/DH representing these settings each. 3)AS minimum value could be 0, while DS/DH minimum value is 1. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 44 Freescale Semiconductor 3.5.8 LCD AC Output Electrical Specifications Figure 24 depicts the AC output timing for the LCD module. Table 49 lists the LCD module timing parameters. T PAD_LCD_DOTCK Falling edge capture tSF tHF PAD_LCD_DOTCK Rising edge capture tSR tHR tDW PAD_LCD_D[17:0], PAD_LCD_VSYNC, etc DATA/CTRL Notes: T = LCD interface clock period I/O Drive Strength = 4mA I/O Voltage = 3.3V Cck = Capacitance load on DOTCK pad Cd = Capacitance load on DATA/CTRL pad Figure 24. LCD AC Output Timing Diagram Table 49. LCD AC Output Timing Parameters ID tSF tHF tSR tHR tDW Parameter Data setup for falling edge Data hold for falling edge Data setup for rising edge Data hold for rising edge Data valid window Description DOTCK = T/2 – 1.97ns + 0.15*Cck – 0.19*Cd DOTCK = T/2 + 0.29ns + 0.09*Cd – 0.10*Cck DOTCK = T/2 – 2.09ns + 0.18*Cck – 0.19*Cd DOTCK = T/2 + 0.40ns + 0.09*Cd – 0.10*Cck tDW = T – 1.45ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 45 3.5.9 Inter IC (I2C) Timing The I2C module is designed to support up to 400-Kbps I2C connection compliant with I2C bus protocol. The following section describes I2C SDA and SCL signal timings. Figure 25 shows the timing of the I2C module. Table 50 describes the I2C module timing parameters (IC1–IC11) shown in the figure. I2C_SDA IC10 IC11 IC9 I2C_SCL IC2 IC8 IC4 IC7 IC3 START IC10 IC6 IC1 IC5 IC11 START STOP START Figure 25. I2C Module Timing Diagram Table 50. I2C Module Timing Parameters: 1.8 V – 3.6 V Standard Mode ID IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 1 Fast Mode Unit Min. 2.5 0.6 0.6 01 0.6 1.3 0.6 1003 1.3 20+0.1Cb 4 Parameter Min. I2C_SCL cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2C_SCL clock LOW Period of the I2C_SCL clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both I2C_SDA and I2C_SCL signals Fall time of both I2C_SDA and I2C_SCL signals Capacitive load for each bus line (Cb) 10 4.0 4.0 0 1 Max. — — — 3.452 — — — — — 1000 300 400 Max. — — — 0.92 — — — — — 300 300 400 μs μs μs μs μs μs μs ns μs ns ns pF 4.0 4.7 4.7 250 4.7 — — — 20+0.1Cb4 — A device must internally provide a hold time of at least 300 ns for the I2C_SDA signal in order to bridge the undefined region of the falling edge of I2C_SCL. 2 The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal. 3 A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line max_rise_time (ID No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the I2C_SCL line is released. 4 Cb = total capacitance of one bus line in pF. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 46 Freescale Semiconductor 3.5.10 JTAG Interface Timing Figure 26 through Figure 29 show respectively the test clock input, boundary scan, test access port, and TRST timings for the SJC. Table 51 describes the SJC timing parameters (SJ1–SJ13) indicated in the figures. SJ1 SJ2 TCK (Input) VIH VIL SJ3 SJ3 VM SJ2 VM Figure 26. Test Clock Input Timing Diagram TCK (Input) VIL SJ4 Data Inputs SJ6 Data Outputs SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Output Data Valid Input Data Valid SJ5 VIH Figure 27. Boundary Scan (JTAG) Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 47 TCK (Input) VIL SJ8 TDI TMS (Input) SJ10 TDO (Output) SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Output Data Valid Input Data Valid VIH SJ9 Figure 28. Test Access Port Timing Diagram TCK (Input) SJ13 TRST (Input) SJ12 Figure 29. TRST Timing Diagram Table 51. SJC Timing Parameters All Frequencies ID SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8 SJ9 TCK cycle time TCK clock pulse width measured at VM1 TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time Parameter Min. 100 40 — 10 50 — — 10 50 Max. — — 3 — — 50 50 — — ns ns ns ns ns ns ns ns ns Unit i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 48 Freescale Semiconductor Table 51. SJC Timing Parameters (continued) All Frequencies ID SJ10 SJ11 SJ12 SJ13 1 Parameter Min. TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low — — 100 40 Max. 44 44 — — Unit ns ns ns ns VM – mid point voltage 3.5.11 Pulse Width Modulator (PWM) Timing Figure 30 depicts the timing of the PWM, and Table 52 lists the PWM timing characteristics. The PWM can be programmed to select one of two clock signals as its source frequency: xtal clock or hsadc clock. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse width modulator output (PWMO) external pin. PWM also supports MATT mode. In this mode, it can be programmed to select one of two clock signals as its source frequency, 24-MHz or 32-KHz crystal clock. For a 32-KHz source clock input, the PWM outputs the 32-KHz clock directly to PAD. 2a PWM Source Clock 2b 3a 4a PWM Output 4b 1 3b Figure 30. PWM Timing Table 52. PWM Output Timing Parameter: Xtal clock Ref No. 1 2a 2b 3a 3b 4a 4b 1 Parameter System CLK frequency1 Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time Minimum 0 21 21 — — — 15.77 Maximum 24MHz — — 0.3 0.3 15.08 — Unit MHz ns ns ns ns ns ns CL of PWMO = 30 pF i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 49 2a PWM Source Clock 2b 3a 4a PWM Output 1 3b 4b Figure 31. PWM Timing Table 53. PWM Output Timing Parameter: HSADC clock Ref No. 1 2a 2b 3a 3b 4a 4b 1 Parameter System CLK frequency1 Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time Minimum 0 6.813 24.432 — — — 15.71 Maximum 32 — — 0.3 0.3 14.93 — Unit MHz ns ns ns ns ns ns CL of PWMO = 30 pF 2a 3b PWM Source Clock 3a 2b 4a 4b PWM Output Figure 32. PWM Timing i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 50 Freescale Semiconductor Table 54. PWM Output Timing Parameter: MATT Mode 24 MHz Crystal Clock Ref No. 1 2a 2b 3a 3b 4a 4b 1 Parameter System CLK frequency Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time 1 Minimum 24 20.99 21.01 — — — 15.92 Maximum 24 — — 0.3 0.3 15.23 — Unit MHz ns ns ns ns ns ns CL of PWMO = 30 pF 3.5.12 Serial Audio Interface (SAIF) AC Timing The following subsections describe SAIF timing in two cases: • Transmitter • Receiver 3.5.12.1 SAIF Transmitter Timing Figure 33 shows the timing for SAIF transmitter with internal clock, and Table 55 describes the timing parameters (SS1–SS13). SS1 SS2 BITCLK SS5 SS4 SS3 SS6 LRCLK SS8 SS11 SS9 SS10 SS13 SS12 SS7 SDATA0-2 Figure 33. SAIF Transmitter Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 51 Table 55. SAIF Transmitter Timing ID SS1 SS2 SS3 SS4 SS5 SS6 SS7 SS8 SS9 SS10 SS11 SS12 SS13 BITCLK period BITCLK high period BITCLK rise time BITCLK low period BITCLK fall time BITCLK high to LRCLK high BITCLK high to LRCLK low LRCLK rise time LRCLK fall time BITCLK high to SDATA valid from high impedance BITCLK high to SDATA high/low BITCLK high to SDATA high impedance SDATA rise/fall time Parameter Min. 81.4 36.0 — 36.0 — — — — — — — — — Max. — — 6.0 — 6.0 15.0 15.0 6.0 6.0 15.0 15.0 15.0 6.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 3.5.12.1.5 SAIF Receiver Timing Figure 34 shows the timing for the SAIF receiver with internal clock. Table 56 describes the timing parameters (SS1–SS17) shown in the figure. SS1 SS5 SS2 BITCLK SS4 SS3 SS14 LRCLK SS16 SS17 SDATA0-2 SS15 Figure 34. SAIF Receiver Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 52 Freescale Semiconductor Table 56. SAIF Receiver Timing with Internal Clock ID SS1 SS2 SS3 SS4 SS5 SS14 SS15 SS16 SS17 BITCLK period BITCLK high period BITCLK rise time BITCLK low period BITCLK fall time BITCLK high to LRCLK high BITCLK high to LRCLK low SDATA setup time before BITCLK high SDATA hold time after BITCLK high Parameter Min. 81.4 36.0 — 36.0 — — — 10.0 0.0 Max. — — 6.0 — 6.0 15.0 15.0 — — Unit ns ns ns ns ns ns ns ns ns 3.5.13 SPDIF AC Timing SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. The following Table 57 shows SPDIF timing parameters, including the timing of the modulating Tx clock (spdif_clk) in SPDIF transmitter as shown in the Figure 35. Table 57. SPDIF Timing Timing Parameter Range Characteristics Symbol Min SPDIFOUT output (Load = 30pf) • Skew • Transition Rising • Transition Falling Modulating Tx clock (spdif_clk) period spdif_clk high period spdif_clk low period — — — spclkp spclkph spclkpl Max ns — — — 81.4 65.1 65.1 1.5 13.6 18.0 — — — ns ns ns Unit spclkp spclkpl spclkph spdif_clk (Input) Figure 35. spdif_clk Timing i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 53 3.5.14 Synchronous Serial Port (SSP) AC Timing This section describes the electrical information of the SSP, which includes SD/MMC4.3 (Single Data Rate) timing, MMC4.4 (Dual Date Rate) timing, MS (Memory Stick) timing, and SPI timing. 3.5.14.1 SD/MMC4.3 (Single Data Rate) AC Timing Figure 36 depicts the timing of SD/MMC4.3, and Table 58 lists the SD/MMC4.3 timing characteristics. SD4 SD2 SD5 SD1 SCK SD3 CMD DAT0 DAT1 ...... DAT7 CMD DAT0 DAT1 ...... DAT7 SD6 output from SSP to card SD7 SD8 input from card to SSP Figure 36. SD/MMC4.3 Timing Table 58. SD/MMC4.3 Interface Timing Specification ID Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) Clock Frequency (Identification Mode) SD2 SD3 SD4 SD5 Clock Low Time Clock High Time Clock Rise Time Clock Fall Time fPP1 fPP2 fPP3 fOD tWL tWH tTLH tTHL 0 0 0 100 7 7 — — 400 25/50 20/52 400 — — 3 3 kHz MHz MHz kHz ns ns ns ns Parameter Symbols Min Max Unit SSP Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SSP Output Delay tOD -5 5 ns SSP Input / Card Outputs CMD, DAT (Reference to CLK) i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 54 Freescale Semiconductor Table 58. SD/MMC4.3 Interface Timing Specification (continued) ID SD7 SD8 1 2 Parameter SSP Input Setup Time SSP Input Hold Time Symbols tISU tIH4 Min 2.5 2.5 Max — — Unit ns ns In low speed mode, the card clock must be lower than 400 kHz, and the voltage ranges from 2.7 to 3.6 V. In normal speed mode for the SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In high speed mode, clock frequency can be any value between 0 ~ 50 MHz. 3 In normal speed mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In high speed mode, clock frequency can be any value between 0 ~ 52MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns. 3.5.14.2 MMC4.4 (Dual Data Rate) AC Timing Figure 37 depicts the timing of MMC4.4, and Table 59 lists the MMC4.4 timing characteristics. Be aware that only DATA0–DATA7 are sampled on both edges of the clock (not applicable to CMD). SD1 SCK SD2 SD2 ...... SD3 DAT0 DAT1 ...... DAT7 SD4 output from SSP to card DAT0 DAT1 ...... DAT7 input from card to SSP ...... Figure 37. MMC4.4 Timing Table 59. MMC4.4 Interface Timing Specification ID Card Input Clock SD1 Clock Frequency (MMC Full Speed/High Speed) fPP 0 52 MHz Parameter Symbols Min Max Unit SSP Output / Card Inputs CMD, DAT (Reference to CLK) SD2 SSP Output Delay tOD –5 5 ns SSP Input / Card Outputs CMD, DAT (Reference to CLK) SD3 SD4 SSP Input Setup Time SSP Input Hold Time tISU tIH 2.5 2.5 — — ns ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 55 3.5.14.3 MS (Memory Stick) AC Timing The SSP module, which also has the function of a memory stick host controller, is compatible with the Sony Memory Stick version 1.x and Memory Stick PRO. Figure 38, Figure 39 and Table 40 show the timing of the Memory Stick. Table 60 and Table 61 list the Memory Stick timing characteristics. MS1 80% 50% 20% MS2 MS4 MS5 80% 50% 20% MS3 80% 50% 20% SCK Figure 38. MS Clock Time Waveforms MS1 SCK BS(CMD) MS6 MS8 DATA (Output) MS7 MS9 MS10 DATA (Input) Figure 39. MS Serial Transfer Mode Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 56 Freescale Semiconductor MS1 SCK BS(CMD) MS11 MS13 DATA (Output) MS12 MS14 MS15 DATA (Input) Figure 40. MS Parallel Transfer Mode Timing Diagram Table 60. MS Serial Transfer Timing Parameters ID MS1 MS2 MS3 MS4 MS5 MS6 MS7 MS8 MS9 MS10 Parameter SCK Cycle Time SCK High Pulse Time SCK Low Pulse Time SCK Rise Time SCK Fall Time BS Setup Time BS Hold Time DATA Setup Time DATA Hold Time DATA Input Delay Time Symbol tCLKc tCLKwh tCLKwl tCLKr tCLKf tBSsu tBSh tDsu tDh tDd Min 50 15 15 — — 5 5 5 5 — Max — — — 10 10 — — — — 15 Units ns ns ns ns ns ns ns ns ns ns Table 61. MS Parallel Transfer Timing Parameters ID MS1 MS2 MS3 Parameter SCK Cycle Time SCK High Pulse Time SCK Low Pulse Time Symbol tCLKc tCLKwh tCLKwl Min 25 5 5 Max — — — Units ns ns ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 57 Table 61. MS Parallel Transfer Timing Parameters (continued) ID MS4 MS5 MS11 MS12 MS13 MS14 MS15 Parameter SCK Rise Time SCK Fall Time BS Setup Time BS Hold Time DATA Setup Time DATA Hold Time DATA Input Delay Time Symbol tCLKr tCLKf tBSsu tBSh tDsu tDh tDd Min — — 8 1 8 1 — Max 10 10 — — — — 15 Units ns ns ns ns ns ns ns 3.5.14.4 SPI AC Timing Figure 41 depicts the master mode and slave mode timings of the SPI, and Table 62 lists the timing parameters. SSn CS1 SCK CS9 MISO CS7 MOSI CS8 CS10 CS3 CS2 CS3 CS2 CS6 CS4 CS5 Figure 41. SPI Interface Timing Diagram Table 62. SPI Interface Timing Parameters ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 SCK cycle time SCK high or low time SCK rise or fall SSn pulse width SSn lead time (CS setup time) SSn lag time (CS hold time) MOSI setup time MOSI hold time MISO setup time MISO hold time Parameter Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi tSmiso tHmiso Min. 50 25 — 25 25 25 5 5 5 5 Max. — — 7.6 — — — — — — — Units ns ns ns ns ns ns ns ns ns ns i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 58 Freescale Semiconductor 3.5.15 UART (UARTAPP and DebugUART) AC Timing This section describes the UART module AC timing which is applicable to both UARTAPP and DebugUART. 3.5.15.1 UART Transmit Timing Figure 39 shows the UART transmit timing, showing only eight data bits and one stop bit. Table 63 describes the timing parameter (UA1) shown in the figure. UA1 Start Bit UA1 Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT TXD (output) Bit 0 Bit 1 Bit 2 Bit 3 Next Start Bit UA1 UA1 Figure 42. UART Transmit Timing Diagram Table 63. UART Transmit Timing Parameters ID UA1 1 Parameter Transmit Bit Time Symbol tTbit Min. 1/Fbaud_rate1 – Tref_clk 2 Max. 1/Fbaud_rate + Tref_clk Units — Fbaud_rate: Baud rate frequency. The maximum baud rate the UARTAPP can support is 3.25 Mbps. The maximum baud rate of DebugUART is 115.2 kbps. 2T ref_clk: The period of UART reference clock ref_clk (which is APBX clock = 24 MHz). 3.5.15.2 UART Receive Timing Figure 43 shows the UART receive timing, showing only eight data bits and one stop bit. Table 64 describes the timing parameter (UA2) shown in the figure. – UA2 Start Bit UA2 Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT RXD (input) Bit 0 Bit 1 Bit 2 Bit 3 Next Start Bit UA2 UA2 Figure 43. UART Receive Timing Diagram i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 59 Table 64. UART Receive Timing Parameters ID UA2 1 Parameter Receive bit time 1 Symbol tRbit Min. 1/Fbaud_rate2 – 1/(16 × Fbaud_rate) Max. 1/Fbaud_rate + 1/(16 × Fbaud_rate) Units — The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16 × Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UARTAPP can support is 3.25 Mbps. The maximum baud rate of DebugUART is 115 kbps. 4 4.1 Package Information and Contact Assignments 289-Ball MAPBGA—Case 14 x 14 mm, 0.8 mm Pitch The following notes apply to Figure 44: • All dimensions are in millimeters. • Dimensioning and tolerancing per ASME Y14.5M-1994. • Maximum solder bump diameter measured parallel to datum A. • Datum A, the seating plane, is determined by the spherical crowns of the solder bumps. • Parallelism measurement excludes any effect of mark on top surface of package. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 60 Freescale Semiconductor Figure 44 shows the i.MX28 production package. Figure 44. i.MX28 Production Package zzxz 4.2 Ground, Power, Sense, and Reference Contact Assignments Table 65. MAPBGA Power and Ground Contact Assignments Contact Name Contact Assignment C13 G12,G11,F10,F11,K12,F12,G10 G8,F9,F8,G9 H8,J8,N3,G3,E6,J9,J10,A7,E16 N17 P11,R13,N13,N15,G17,M12,M10,G13,M11,L13,G15 Table 65 shows power and ground contact assignments for the MAPBGA package. VDDA1 VDDD VDDIO18 VDDIO33 VDDIO33_EMI VDDIO_EMI i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 61 Table 65. MAPBGA Power and Ground Contact Assignments (continued) Contact Name VDDIO_EMIQ VDDXTAL VSS VSSA1 VSSA2 VSSIO_EMI K15,J13,R15 C12 E15,L11,A1,K10,K11,J11,M14,H11,U1,H9,H12,H3,K9,C16,L10,H16,J12,H10,B7,E5,J15,A9,N4 B13 B11 F16,R10,H14,M16,F14,L12,P16,U17,T14,P14,R12 Contact Assignment 4.3 Signal Contact Assignments Table 66. MAPBGA Contact Assignments Table 66 lists the i.MX287 MAPBGA package signal contact assignments. Contact Assignment J6 J7 G5 H5 K5 J5 L4 K4 H6 H7 F6 F5 L6 K6 M5 L5 A15 B15 A17 B17 A16 Contact Assignment J16 R17 T17 R16 R14 K13 T15 J4 J3 G4 H4 H1 H2 J1 J2 Contact Assignment R3 U4 T4 R4 U5 T5 R5 N1 N5 M1 P4 M6 M4 L1 K1 C15 C9 C8 D9 D13 D15 Signal Name AUART0_CTS AUART0_RTS AUART0_RX AUART0_TX AUART1_CTS AUART1_RTS AUART1_RX AUART1_TX AUART2_CTS AUART2_RTS AUART2_RX AUART2_TX AUART3_CTS AUART3_RTS AUART3_RX AUART3_TX BATTERY DCDC_BATT DCDC_GND DCDC_LN1 DCDC_LP Signal Name EMI_DQS1N EMI_ODT0 EMI_ODT1 EMI_RASN EMI_VREF0 EMI_VREF1 EMI_WEN ENET0_COL ENET0_CRS ENET0_MDC ENET0_MDIO ENET0_RXD0 ENET0_RXD1 ENET0_RXD2 ENET0_RXD3 Signal Name LCD_D17 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23 LCD_DOTCLK LCD_ENABLE LCD_HSYNC LCD_RD_E LCD_RESET LCD_RS LCD_VSYNC LCD_WR_RWN LRADC0 LRADC1 LRADC2 LRADC3 LRADC4 LRADC5 ENET0_RX_CLK F3 ENET0_RX_EN ENET0_TXD0 ENET0_TXD1 ENET0_TXD2 ENET0_TXD3 E4 F1 F2 G1 G2 i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 62 Freescale Semiconductor Table 66. MAPBGA Contact Assignments (continued) Signal Name DCDC_VDDA DCDC_VDDD DCDC_VDDIO DEBUG EMI_A00 EMI_A01 EMI_A02 EMI_A03 EMI_A04 EMI_A05 EMI_A06 EMI_A07 EMI_A08 EMI_A09 EMI_A10 EMI_A11 EMI_A12 EMI_A13 EMI_A14 EMI_BA0 EMI_BA1 EMI_BA2 EMI_CASN EMI_CE0N EMI_CE1N EMI_CKE EMI_CLK EMI_CLKN EMI_D00 EMI_D01 EMI_D02 EMI_D03 Contact Assignment B16 D17 C17 B9 U15 U12 U14 T11 U10 R11 R9 N11 U9 P10 U13 T10 U11 T9 N10 T16 T12 N12 U16 P12 P9 T13 L17 L16 N16 M13 P15 N14 Signal Name Contact Assignment Signal Name LRADC6 PSWITCH PWM0 PWM1 PWM2 PWM3 PWM4 RESETN RTC_XTALI RTC_XTALO SAIF0_BITCLK SAIF0_LRCLK SAIF0_MCLK SAIF0_SDATA0 SAIF1_SDATA0 SPDIF SSP0_CMD SSP0_DATA0 SSP0_DATA1 SSP0_DATA2 SSP0_DATA3 SSP0_DATA4 SSP0_DATA5 SSP0_DATA6 SSP0_DATA7 SSP0_DETECT SSP0_SCK SSP1_CMD SSP1_DATA0 SSP1_DATA3 SSP1_SCK SSP2_MISO Contact Assignment C14 A11 K7 L7 K8 E9 E10 A14 D11 C11 F7 G6 G7 E7 E8 D7 A4 B6 C6 D6 A5 B5 C5 D5 B4 D10 A6 C1 D1 E1 B1 B3 ENET0_TX_CLK E3 ENET0_TX_EN ENET_CLK GPMI_ALE GPMI_CE0N GPMI_CE1N GPMI_CE2N GPMI_CE3N GPMI_CLE GPMI_D00 GPMI_D01 GPMI_D02 GPMI_D03 GPMI_D04 GPMI_D05 GPMI_D06 GPMI_D07 GPMI_RDN GPMI_RDY0 GPMI_RDY1 GPMI_RDY2 GPMI_RDY3 GPMI_RESETN GPMI_WRN HSADC0 I2C0_SCL I2C0_SDA JTAG_RTCK JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS F4 E2 P6 N7 N9 M7 M9 P7 U8 T8 R8 U7 T7 R7 U6 T6 R6 N6 N8 M8 L8 L9 P8 B14 C7 D8 E14 E11 E12 E13 D12 i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 63 Table 66. MAPBGA Contact Assignments (continued) Signal Name EMI_D04 EMI_D05 EMI_D06 EMI_D07 EMI_D08 EMI_D09 EMI_D10 EMI_D11 EMI_D12 EMI_D13 EMI_D14 EMI_D15 EMI_DDR_OPE N EMI_DDR_OPE N_FB EMI_DQM0 EMI_DQM1 EMI_DQS0 EMI_DQS0N EMI_DQS1 Contact Assignment P13 P17 L14 M17 G16 H15 G14 J14 H13 H17 F13 F17 K14 L15 M15 F15 K17 K16 J17 Signal Name JTAG_TRST LCD_CS LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 Contact Assignment D14 P5 K2 K3 L2 L3 M2 M3 N2 P1 P2 P3 R1 R2 T1 T2 U2 U3 T3 Signal Name SSP2_MOSI SSP2_SCK SSP2_SS0 SSP2_SS1 SSP2_SS2 SSP3_MISO SSP3_MOSI SSP3_SCK SSP3_SS0 TESTMODE USB0DM USB0DP USB1DM USB1DP VDD1P5 VDD4P2 VDD5V XTALI XTALO Contact Assignment C3 A3 C4 D3 D4 B2 C2 A2 D2 C10 A10 B10 B8 A8 D16 A13 E17 A12 B12 i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 64 Freescale Semiconductor 4.4 1 i.MX287 Ball Map 2 SSP3 _SCK SSP3 _MIS O 3 SSP2 _SCK SSP2 _MIS O 4 SSP0 _CMD SSP0 _DAT A7 SSP2 _SS0 SSP2 _SS2 ENET 0_RX _EN ENET 0_TX _EN ENET 0_MD C ENET 0_MD IO ENET 0_CO L 5 SSP0 _DAT A3 SSP0 _DAT A4 SSP0 _DAT A5 SSP0 _DAT A6 VSS 6 SSP0 _SCK SSP0 _DAT A0 SSP0 _DAT A1 SSP0 _DAT A2 VDDI O33 7 VDDI O33 8 USB1 DP USB1 DM LRAD C2 I2C0_ SDA 9 10 USB0 DM USB0 DP TEST MOD E SSP0 _DET ECT PWM 4 11 PSWI TCH VSSA 2 RTC_ XTAL O RTC_ XTALI JTAG _TCK 12 13 VDD4 P2 VSSA 1 14 RESE TN HSAD C0 LRAD C6 JTAG _TRS T JTAG _RTC K 15 BATT ERY 16 17 Figure 45 shows the i.MX287 MAPBGA Ball Map. A VSS VSS XTALI DCDC DCDC _LP _GND A B SSP1 _SCK VSS DEBU G LRAD C1 LRAD C3 PWM 3 VDDI O18 VDDI O18 XTAL O DCDC DCDC DCDC _BAT _VDD _LN1 T A LRAD C0 LRAD C5 VSS DCDC _VDD IO DCDC _VDD D VDD5 V EMI_ D15 VDDI O_EM I EMI_ D13 EMI_ DQS1 EMI_ DQS0 B C SSP3 SSP2 SSP1 _MOS _MOS _CMD I I SSP1 _DAT A0 SSP1 _DAT A3 ENET 0_TX D0 ENET 0_TX D2 ENET 0_RX D0 ENET 0_RX D2 LCD_ WR_ RWN LCD_ VSYN C LCD_ HSYN C LCD_ DOTC LK LCD_ D07 LCD_ D10 LCD_ D12 SSP3 _SS0 ENET _CLK ENET 0_TX D1 ENET 0_TX D3 ENET 0_RX D1 ENET 0_RX D3 LCD_ D00 SSP2 _SS1 ENET 0_TX _CLK ENET 0_RX _CLK VDDI O33 I2C0_ SCL SPDI F VDDX VDDA TAL 1 JTAG _TMS JTAG _TDI LRAD C4 JTAG _TDO EMI_ D14 C D VDD1 P5 VDDI O33 D E SAIF0 SAIF1 _SDA _SDA TA0 TA0 VDDI O18 VDDI O18 VDDI O33 VDDI O33 PWM 2 GPMI _RDY 3 GPMI _RDY 2 GPMI _RDY 1 GPMI _WR N GPMI _D02 GPMI _D01 GPMI _D00 8 VSS E F AUAR AUAR SAIF0 T2_T T2_R _BITC X X LK AUAR SAIF0 SAIF0 T0_R _LRC _MCL X LK K AUAR AUAR AUAR T0_T T2_C T2_R X TS TS AUAR AUAR AUAR T1_R T0_C T0_R TS TS TS PWM 0 VDDD VDDD VDDD VSSI VSSI EMI_ O_EM O_EM DQM1 I I EMI_ D10 VSSI O_EM I EMI_ D11 VDDI O_EM I EMI_ D09 EMI_ D08 F G VDDI VDDD VDDD VDDD O_EM I VSS VSS VSS EMI_ D12 VDDI O_EM IQ EMI_ VREF 1 G H VSS ENET 0_CR S LCD_ D01 VSS VSS EMI_ DQS1 N EMI_ DQS0 N H J VDDI O33 VDDI O33 VSS VSS VSS J K AUAR AUAR AUAR T1_T T1_C T3_R X TS TS AUAR AUAR AUAR T1_R T3_T T3_C X X TS LCD_ RS AUAR LCD_ T3_R RESE X T LCD_ ENAB LE LCD_ CS LCD_ D23 LCD_ D22 LCD_ D21 5 GPMI _RDY 0 GPMI _ALE GPMI _RDN GPMI _D07 GPMI _D06 6 VSS VSS VSS VDDD EMI_ VDDI DDR_ O_EM OPEN IQ EMI_ D06 K L LCD_ D02 LCD_ D03 PWM 1 GPMI _CE2 N GPMI _CE0 N GPMI _CLE GPMI _D05 GPMI _D04 GPMI _D03 7 GPMI _RES ETN GPMI _CE3 N GPMI _CE1 N EMI_ CE1N EMI_ A06 EMI_ A13 EMI_ A08 9 VSS VSS VSSI VDDI O_EM O_EM I I EMI_ D01 VDDI O_EM I EMI_ D04 EMI_ DDR_ EMI_ OPEN CLKN _FB VSSI EMI_ O_EM DQM0 I VDDI O_EM I EMI_ D02 EMI_ D00 VSSI O_EM I EMI_ CLK L M LCD_ D04 LCD_ D06 LCD_ D08 LCD_ D11 LCD_ D13 LCD_ D14 2 LCD_ D05 VDDI O33 LCD_ D09 LCD_ D17 LCD_ D16 LCD_ D15 3 VDDI VDDI VDDI O_EM O_EM O_EM I I I EMI_ A14 EMI_ A09 VSSI O_EM I EMI_ A11 EMI_ A04 10 EMI_ A07 VDDI O_EM I EMI_ A05 EMI_ A03 EMI_ A12 11 EMI_ BA2 EMI_ CE0N VSS EMI_ D07 VDDI O33_ EMI EMI_ D05 EMI_ ODT0 EMI_ ODT1 M N VSS EMI_ D03 VSSI O_EM I EMI_ VREF 0 VSSI O_EM I EMI_ A02 14 N P LCD_ RD_E LCD_ D20 LCD_ D19 LCD_ D18 4 P R VSSI VDDI O_EM O_EM I I EMI_ BA1 EMI_ A01 12 EMI_ CKE EMI_ A10 13 VDDI EMI_ O_EM RASN IQ EMI_ WEN EMI_ A00 15 EMI_ BA0 R T T U VSS VSSI EMI_ O_EM CASN I 16 17 U 1 Figure 45. 289-pin i.MX287 MAPBGA Ball Map i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 65 4.5 1 i.MX286 Ball Map 2 3 SSP2 _SCK SSP2 _MIS O SSP2 _MOS I SSP2 _SS1 NC 4 SSP0 _CMD SSP0 _DAT A7 SSP2 _SS0 SSP2 _SS2 ENET 0_RX _EN ENET 0_TX _EN ENET 0_MD C ENET 0_MD IO NC AUAR T1_T X AUAR T1_R X LCD_ RS 5 SSP0 _DAT A3 SSP0 _DAT A4 SSP0 _DAT A5 SSP0 _DAT A6 VSS 6 SSP0 _SCK SSP0 _DAT A0 SSP0 _DAT A1 SSP0 _DAT A2 VDDI O33 NC 7 VDDI O33 8 USB1 DP USB1 DM LRAD C2 I2C0_ SDA 9 10 USB0 DM USB0 DP TEST MOD E SSP0 _DET ECT PWM 4 11 PSWI TCH VSSA 2 RTC_ XTAL O RTC_ XTALI JTAG _TCK 12 13 VDD4 P2 VSSA 1 14 RESE TN HSAD C0 LRAD C6 JTAG _TRS T JTAG _RTC K 15 BATT ERY 16 17 Figure 46 shows the i.MX286 MAPBGA ball map. A VSS NC VSS XTALI DCDC DCDC _LP _GND A B NC NC VSS DEBU G LRAD C1 LRAD C3 PWM 3 VDDI O18 VDDI O18 XTAL O DCDC DCDC DCDC _BAT _VDD _LN1 T A LRAD C0 LRAD C5 VSS DCDC _VDD IO DCDC _VDD D VDD5 V EMI_ D15 VDDI O_EM I EMI_ D13 EMI_ DQS1 EMI_ DQS0 B C NC NC I2C0_ SCL SPDI F VDDX VDDA TAL 1 JTAG _TMS JTAG _TDI LRAD C4 JTAG _TDO EMI_ D14 C D NC NC VDD1 P5 VDDI O33 D E NC ENET 0_TX D0 NC ENET 0_RX D0 NC LCD_ WR_ RWN NC ENET _CLK ENET 0_TX D1 NC ENET 0_RX D1 NC SAIF0 SAIF1 _SDA _SDA TA0 TA0 SAIF0 _BITC LK VDDI O18 VDDI O18 VDDI O33 VDDI O33 PWM 2 GPMI _RDY 3 GPMI _RDY 2 GPMI _RDY 1 GPMI _WR N GPMI _D02 GPMI _D01 GPMI _D00 8 VSS E F NC NC VDDD VDDD VDDD VSSI VSSI EMI_ O_EM O_EM DQM1 I I EMI_ D10 VSSI O_EM I EMI_ D11 VDDI O_EM I EMI_ D09 EMI_ D08 F G VDDI O33 AUAR SAIF0 SAIF0 T0_R _LRC _MCL X LK K AUAR T0_T X NC NC NC VDDI VDDD VDDD VDDD O_EM I VSS VSS VSS EMI_ D12 VDDI O_EM IQ EMI_ VREF 1 G H VSS VSS VSS EMI_ DQS1 N EMI_ DQS0 N H J NC AUAR AUAR T0_C T0_R TS TS NC PWM 0 VDDI O33 VDDI O33 VSS VSS VSS J K LCD_ D00 LCD_ D01 NC VSS VSS VSS VDDD EMI_ VDDI DDR_ O_EM OPEN IQ EMI_ D06 K L LCD_ D02 LCD_ D03 NC NC PWM 1 GPMI _CE2 N GPMI _CE0 N GPMI _CLE GPMI _D05 GPMI _D04 GPMI _D03 7 GPMI _RES ETN GPMI _CE3 N GPMI _CE1 N EMI_ CE1N EMI_ A06 EMI_ A13 EMI_ A08 9 VSS VSS VSSI VDDI O_EM O_EM I I EMI_ D01 VDDI O_EM I EMI_ D04 EMI_ DDR_ EMI_ OPEN CLKN _FB VSSI EMI_ O_EM DQM0 I VDDI O_EM I EMI_ D02 EMI_ D00 VSSI O_EM I EMI_ CLK L M NC LCD_ D04 LCD_ D06 LCD_ D08 LCD_ D11 LCD_ D13 LCD_ D14 2 LCD_ D05 VDDI O33 LCD_ D09 LCD_ D17 LCD_ D16 LCD_ D15 3 NC LCD_ RESE T GPMI _RDY 0 GPMI _ALE GPMI _RDN GPMI _D07 GPMI _D06 6 VDDI VDDI VDDI O_EM O_EM O_EM I I I EMI_ A14 EMI_ A09 VSSI O_EM I EMI_ A11 EMI_ A04 10 EMI_ A07 VDDI O_EM I EMI_ A05 EMI_ A03 EMI_ A12 11 EMI_ BA2 EMI_ CE0N VSS EMI_ D07 VDDI O33_ EMI EMI_ D05 EMI_ ODT0 EMI_ ODT1 M N NC VSS NC EMI_ D03 VSSI O_EM I EMI_ VREF 0 VSSI O_EM I EMI_ A02 14 N P LCD_ D07 LCD_ D10 LCD_ D12 LCD_ RD_E LCD_ D20 LCD_ D19 LCD_ D18 4 LCD_ CS LCD_ D23 LCD_ D22 LCD_ D21 5 P R VSSI VDDI O_EM O_EM I I EMI_ BA1 EMI_ A01 12 EMI_ CKE EMI_ A10 13 VDDI EMI_ O_EM RASN IQ EMI_ WEN EMI_ A00 15 EMI_ BA0 R T T U VSS VSSI EMI_ O_EM CASN I 16 17 U 1 Figure 46. 289-pin i.MX286 MAPBGA Ball Map i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 66 Freescale Semiconductor 4.6 1 A B C D E F G H J K L M N P R T U i.MX283 Ball Map 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A B C D E F G H J K L M N P R T U Figure 47 shows the i.MX283 MAPBGA ball map. SSP2_S SSP0_C SSP0_D SSP0_S VDDIO3 USB0D PSWITC BATTER DCDC_L DCDC_ USB1DP VSS XTALI VDD4P2 RESETN CK MD ATA3 CK 3 M H Y P GND SSP2_M SSP0_D SSP0_D SSP0_D USB1D DCDC_BDCDC_V DCDC_L NC NC VSS DEBUG USB0DP VSSA2 XTALO VSSA1 HSADC0 ISO ATA7 ATA4 ATA0 M ATT DDA N1 SSP2_M SSP2_S SSP0_D SSP0_D I2C0_SC TESTM RTC_XT VDDXT DCDC_V NC NC LRADC2 LRADC1 VDDA1 LRADC6 LRADC0 VSS OSI S0 ATA5 ATA1 L ODE ALO AL DDIO SSP2_S SSP2_S SSP0_D SSP0_D I2C0_SD SSP0_D RTC_XT JTAG_T JTAG_T DCDC_V NC NC NC LRADC3 LRADC4 LRADC5 VDD1P5 S1 S2 ATA6 ATA2 A ETECT ALI MS RST DDD ENET_C ENET0_ VDDIO3 SAIF0_S SAIF1_S JTAG_T JTAG_T JTAG_T JTAG_R VDDIO3 NC NC VSS PWM3 PWM4 VSS VDD5V LK RX_EN 3 DATA0 DATA0 CK DI DO TCK 3 ENET0_ ENET0_ ENET0_ SAIF0_B VDDIO1 VDDIO1 EMI_D1 VSSIO_ EMI_D VSSIO_ EMI_D1 NC NC NC VDDD VDDD VDDD TXD0 TXD1 TX_EN ITCLK 8 8 4 EMI QM1 EMI 5 VDDIO3 ENET0_ AUART SAIF0_L SAIF0_ VDDIO1 VDDIO1 VDDIO_ EMI_D1 VDDIO_ EMI_D0 VDDIO_ NC NC VDDD VDDD VDDD 3 MDC 0_RX RCLK MCLK 8 8 EMI 0 EMI 8 EMI ENET0_ ENET0_ ENET0_ AUART VDDIO3 EMI_D1 VSSIO_ EMI_D0 EMI_D1 VSS NC NC VSS VSS VSS VSS VSS RXD0 RXD1 MDIO 0_TX 3 2 EMI 9 3 AUART AUART VDDIO3 VDDIO3 VDDIO3 VDDIO_ EMI_D1 EMI_D EMI_D NC NC NC NC NC VSS VSS VSS 0_CTS 0_RTS 3 3 3 EMIQ 1 QS1N QS1 LCD_W LCD_D0 LCD_D0 AUART EMI_VR EMI_DD VDDIO_ EMI_D EMI_D NC NC PWM0 PWM2 VSS VSS VSS VDDD R_RWN 0 1 1_TX EF1 R_OPE EMIQ QS0N QS0 LCD_D0 LCD_D0 AUART GPMI_R VSSIO_ VDDIO_ EMI_D0 EMI_DD EMI_CL EMI_CL NC NC NC PWM1 NC VSS VSS R_OPE KN 2 3 1_RX ESETN EMI EMI 6 K LCD_D0 LCD_D0 LCD_RE VDDIO_ VDDIO_ VDDIO_ EMI_D0 EMI_D VSSIO_ EMI_D0 NC LCD_RS NC NC NC NC VSS 4 5 SET EMI EMI EMI 1 QM0 EMI 7 LCD_D0 VDDIO3 GPMI_R GPMI_C GPMI_R GPMI_C EMI_A1 EMI_A0 EMI_BA VDDIO_ EMI_D0 VDDIO_ EMI_D0 VDDIO3 NC VSS NC 6 3 DY0 E0N DY1 E1N 4 7 2 EMI 3 EMI 0 3_EMI LCD_D0 LCD_D0 LCD_D0 LCD_RD GPMI_A GPMI_C GPMI_ EMI_CE EMI_A0 VDDIO_ EMI_CE EMI_D0 VSSIO_ EMI_D0 VSSIO_ EMI_D0 LCD_CS 7 8 9 _E LE LE WRN 1N 9 EMI 0N 4 EMI 2 EMI 5 LCD_D1 LCD_D1 LCD_D1 LCD_D2 LCD_D2 GPMI_R GPMI_ GPMI_ EMI_A0 VSSIO_ EMI_A0 VSSIO_ VDDIO_ EMI_VR VDDIO_ EMI_RA EMI_O 0 1 7 0 3 DN D05 D02 6 EMI 5 EMI EMI EF0 EMIQ SN DT0 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D2 GPMI_ GPMI_ GPMI_ EMI_A1 EMI_A1 EMI_A0 EMI_BA EMI_CK VSSIO_ EMI_W EMI_BA EMI_O 2 3 6 9 2 D07 D04 D01 3 1 3 1 E EMI EN 0 DT1 LCD_D1 LCD_D1 LCD_D1 LCD_D2 GPMI_ GPMI_ GPMI_ EMI_A0 EMI_A0 EMI_A1 EMI_A0 EMI_A1 EMI_A0 EMI_A0 EMI_CA VSSIO_ VSS 4 5 8 1 D06 D03 D00 8 4 2 1 0 2 0 SN EMI VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 47. 289-pin i.MX283 MAPBGA Ball Map i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 67 4.7 i.MX280 Ball Map Figure 48 shows the i.MX280 MAPBGA ball map. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A VSS NC SSP2_S SSP0_C SSP0_D SSP0_S VDDIO3 USB1D CK MD ATA3 CK 3 P SSP2_ SSP0_D SSP0_D SSP0_D VSS MISO ATA7 ATA4 ATA0 VSS USB0D PSWITC VDD4P BATTER DCDC_L DCDC_ XTALI RESETN M H 2 Y P GND A B NC NC USB1D USB0D HSADC DCDC_ DCDC_ DCDC_L DEBUG VSSA2 XTALO VSSA1 M P 0 BATT VDDA N1 DCDC_ VDDIO B C NC NC SSP2_ SSP2_S SSP0_D SSP0_D I2C0_SC TESTM RTC_XT VDDXT LRADC2 LRADC1 VDDA1 LRADC6 LRADC0 VSS MOSI S0 ATA5 ATA1 L ODE ALO AL SSP2_S SSP2_S SSP0_D SSP0_D S1 S2 ATA6 ATA2 NC NC C D NC NC ENET_C LK I2C0_S SSP0_D RTC_XT JTAG_T JTAG_T VDD1P DCDC_ LRADC3 LRADC4 LRADC5 DA ETECT ALI MS RST 5 VDDD D E NC ENET0_ VDDIO3SAIF0_S SAIF1_S JTAG_T JTAG_T JTAG_T JTAG_R VDDIO3 VSS PWM3 PWM4 VSS VDD5V RX_EN 3 DATA0 DATA0 CK DI DO TCK 3 ENET0_ TX_EN NC NC SAIF0_ VDDIO1VDDIO1 EMI_D1 VSSIO_ EMI_D VSSIO_ EMI_D1 VDDD VDDD VDDD BITCLK 8 8 4 EMI QM1 EMI 5 E F ENET0_ ENET0_ TXD0 TXD1 NC NC NC F G VDDIO3 ENET0_ AUART SAIF0_L SAIF0_ VDDIO1VDDIO1 VDDIO_ EMI_D1 VDDIO_ EMI_D0 VDDIO_ VDDD VDDD VDDD 3 MDC 0_RX RCLK MCLK 8 8 EMI 0 EMI 8 EMI NC NC VDDIO3 VSS 3 VSS VSS VSS EMI_D1 VSSIO_ EMI_D0 EMI_D1 VSS 2 EMI 9 3 VDDIO_ EMI_D1 VSS EMIQ 1 EMI_D EMI_D QS1N QS1 G H ENET0_ ENET0_ ENET0_ AUART VSS RXD0 RXD1 MDIO 0_TX NC NC NC NC NC H J AUART AUART VDDIO3VDDIO3VDDIO3 VSS 0_CTS 0_RTS 3 3 3 NC PWM0 PWM2 VSS VSS VSS VSS J K ETM_T ETM_D ETM_D AUART CLK A0 A1 1_TX NC ETM_D ETM_D AUART A2 A3 1_RX ETM_D ETM_D GPIO_B A4 A5 1P26 ETM_D VDDIO3 VSS A6 3 NC NC ETM_T CTL NC NC L NC NC PWM1 NC GPMI_ VSS RESETN NC VSS EMI_D EMI_VR VDDIO_ EMI_D EMI_D DR_OP EF1 EMIQ QS0N QS0 EN EMI_D VSSIO_ VDDIO_ EMI_D0 EMI_CL EMI_CL DR_OP EMI EMI 6 KN K EN_FB VDDD EMI_D VSSIO_ EMI_D0 QM0 EMI 7 K L M NC NC NC NC NC VDDIO_VDDIO_ VDDIO_ EMI_D0 VSS EMI EMI EMI 1 M N NC ETM_D A7 NC NC GPMI_ GPMI_ GPMI_ GPMI_ EMI_A1 EMI_A0 EMI_BAVDDIO_ EMI_D0 VDDIO_ EMI_D0 VDDIO3 RDY0 CE0N RDY1 CE1N 4 7 2 EMI 3 EMI 0 3_EMI GPMI_ GPMI_ GPMI_ EMI_CE EMI_A0 VDDIO_ EMI_CE EMI_D0 VSSIO_ EMI_D0 VSSIO_ EMI_D0 ALE CLE WRN 1N 9 EMI 0N 4 EMI 2 EMI 5 GPMI_ GPMI_ GPMI_ EMI_A0 VSSIO_ EMI_A0 VSSIO_ VDDIO_ EMI_VRVDDIO_EMI_RA EMI_O RDN D05 D02 6 EMI 5 EMI EMI EF0 EMIQ SN DT0 GPMI_ GPMI_ GPMI_ EMI_A1 EMI_A1 EMI_A0 EMI_BA EMI_CK VSSIO_ EMI_W EMI_BA EMI_O D07 D04 D01 3 1 3 1 E EMI EN 0 DT1 GPMI_ GPMI_ GPMI_ EMI_A0 EMI_A0 EMI_A1 EMI_A0 EMI_A1 EMI_A0 EMI_A0 EMI_CA VSSIO_ D06 D03 D00 8 4 2 1 0 2 0 SN EMI 6 7 8 9 10 11 12 13 14 15 16 17 N P NC P R NC NC NC R T NC NC NC NC NC T U VSS NC NC NC NC U 1 2 3 4 5 Figure 48. 289-pin i.MX280 MAPBGA Ball Map i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 68 Freescale Semiconductor 5 Revision History Table 67. Revision History Rev. # Rev. 1 Date 04/2011 • • • • • • • • • • • • • • Rev. 0 Revision Updated Section 1.1, “Device Features.” Added Section 3.2, “Thermal Characteristics.” In Table 1, "Ordering Information," on page 3, added two rows. Updated Table 2, "i.MX28 Functional Differences," on page 3. Updated Table 4, "i.MX28 Digital and Analog Modules," on page 6. In Table 8, "Recommended Power Supply Operating Conditions," on page 13, updated BATT row. Updated Table 9, "Operating Temperature Conditions," on page 13. Replaced the term “DC Characteristics” with “Power Consumption” in the title and introduction of Table 12, "Power Consumption," on page 14. Also changed Dissipation to Consumption in first row. Updated Table 26, "Digital Pin DC Characteristics for GPIO in 3.3-V Mode," on page 21. Updated Table 27, "Digital Pin DC Characteristics for GPIO in 1.8 V Mode," on page 23. Updated and added a footnote to Table 34, "Ethernet PLL Specifications," on page 30. Updated DDR1 row of Table 35, "EMI Command/Address AC Timing," on page 31. In Section 4.6, “i.MX283 Ball Map,” replaced Figure 47. Added Section 4.7, “i.MX280 Ball Map.” Table 67 summarizes revisions to this document. 09/2010 Initial release. i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 Freescale Semiconductor 69 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM926EJ-S, CoreSight, and ETM9 are trademarks of ARM Limited. IEEE 1588 and IEEE 1149 are trademarks and IEEE 802.3 is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. © Freescale Semiconductor, Inc., 2011. All rights reserved. Document Number: IMX28CEC Rev. 1 04/2011