MCIMX353CVM5B

Freescale Semiconductor Data Sheet: Technical Data Document Number: MCIMX35SR2CEC Rev. 8, 04/2010 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. MCIMX35 i.MX35 Applications Processors for Industrial and Consumer Products Silicon Revisions 2.0 and 2.1 Package Information Plastic package Case 5284 17 x 17 mm, 0.8 mm Pitch Ordering Information See Table 1 on page 3 for ordering information. 1 Introduction The i.MX353 and the i.MX357 multimedia applications processors represent the next generation of ARM11 products with the right performance and integration to address applications within the industrial and consumer markets for applications such as HMI and display controllers. Unless otherwise specified, the material in this data sheet is applicable to both the i.MX353 and i.MX357 devices and referred to singularly throughout this document as i.MX35 or MCIMX35. The i.MX353 devices do not include a graphics processing unit (GPU). For information on i.MX35 devices for automotive applications, please refer to document number, MCIMX35SR2AEC. The i.MX35 processor takes advantage of the ARM1136JF-S™ core running at 532 MHz that is boosted by a multi-level cache system and integrated features such as LCD controller, Ethernet, and graphics acceleration for creating rich user interfaces. 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Functional Description and Application Information . . . . . 4 2.1. Application Processor Domain Overview . . . . . . . . 4 2.2. Shared Domain Overview . . . . . . . . . . . . . . . . . . . . 5 2.3. Advanced Power Management Overview . . . . . . . . 5 2.4. ARM11 Microprocessor Core . . . . . . . . . . . . . . . . . 5 2.5. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Signal Descriptions: Special Function Related Pins . . . . 11 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. i.MX35 Chip-Level Conditions . . . . . . . . . . . . . . . . 11 4.2. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3. Supply Power-Up/Power-Down Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 17 4.6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 18 4.7. I/O Pin DC Electrical Characteristics . . . . . . . . . . 19 4.8. I/O Pin AC Electrical Characteristics . . . . . . . . . . 22 4.9. Module-Level AC Electrical Specifications . . . . . . 28 5. Package Information and Pinout . . . . . . . . . . . . . . . . . 129 5.1. MAPBGA Production Package 1568-01, 17 × 17 mm, 0.8 Pitch . . . . . . . . . . . . . . . . . . . . . 130 5.2. MAPBGA Signal Assignments . . . . . . . . . . . . . . 131 6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . 143 7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 © Freescale Semiconductor, Inc., 2010. All rights reserved. 1.1 Features It provides low-power solutions for applications demanding high-performance multimedia and graphics. The i.MX35 is based on the ARM1136 platform, which has the following features: • ARM1136JF-S processor, version r1p3 • 16-Kbyte L1 instruction cache • 16-Kbyte L1 data cache • 128-Kbyte L2 cache, version r0p4 • 128 Kbytes of internal SRAM • Vector floating point unit (VFP11) To boost multimedia performance, the following hardware accelerators are integrated: • Image processing unit (IPU) • OpenVG 1.1 graphics processing unit (GPU) The MCIMX35 provides the following interfaces to external devices (some of these interfaces are muxed and not available simultaneously): • 2 controller area network (CAN) interfaces • 2 SDIO/MMC interfaces, 1 SDIO/CE-ATA interface • 32-bit mobile DDR, DDR2 (4-bank architecture), and SDRAM (up to 133 MHz) • 2 configurable serial peripheral interfaces (CSPI) (up to 52 Mbps each) • Enhanced serial audio interface (ESAI) • 2 synchronous serial interfaces (SSI) • Ethernet MAC 10/100 Mbps • 1 USB 2.0 host with ULPI interface or internal full-speed PHY. Up to 480 Mbps if external HS PHY is used. • 1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY • Flash controller—MLC/SLC NAND and NOR • GPIO with interrupt capabilities • 3 I2C modules (up to 400 Kbytes each) • JTAG • Key pin port • Asynchronous sample rate converter (ASRC) • 1-Wire • Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 Mpixels/s) • Parallel display (primary up to 24-bit, 1024 x 1024) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The i.MX35 supports connections to various types of external memories, such as SDRAM, mobile DDR, and DDR2, SLC and MCL NAND Flash, NOR Flash and SRAM. The devices can be connected to a variety of external devices such as USB 2.0 OTG, ATA, MMC/SDIO, and Compact Flash. 1.2 Ordering Information Table 1 provides the ordering information for the i.MX35 processors for consumer and industrial applications. Table 1. Ordering Information Part Number1 Silicon Revision 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 Package2 Operating Temperature Range (°C) –40 to 85 –20 to 70 –40 to 85 –20 to 70 -40 to 85 -20 to 70 -40 to 85 -20 to 70 Signal Ball Map Locations Table 90 Table 90 Table 90 Table 90 Table 91 Table 91 Table 91 Table 91 Description Speed Ball Map i.MX353 i.MX353 i.MX357 i.MX357 i.MX353 i.MX353 i.MX357 i.MX357 1 MCIMX353CVM5B! MCIMX353DVM5B! MCIMX357CVM5B! MCIMX357DVM5B! MCIMX353CJQ5C MCIMX353DJQ5C MCIMX357CJQ5C MCIMX357DJQ5C 5284 5284 5284 5284 5284 5284 5284 5284 532 MHz 532 MHz 532 MHz 532 MHz 532MHz 532MHz 532MHz 532MHz Table 92 Table 92 Table 92 Table 92 Table 93 Table 93 Table 93 Table 93 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: Indicated by the Icon (!) 2 Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1. The ball map for silicon revision 2.1 is different than the ballmap for silicon revision 2.0. The layout for each revision is not compatible, so it is important that the correct ballmap be used to implement the layout. See Section 5, “Package Information and Pinout.” i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. • • • • Parallel ATA (up to 66 Mbytes) PWM SPDIF transceiver 3 UART (up to 4.0 Mbps each) 1.3 Block Diagram Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 1 is the i.MX35 simplified interface block diagram. DDR2/SDDR RAM NOR Flash/ PSRAM NAND Flash Camera Sensor LCD Display 1 External Graphics Accelerator LCD Display 2 External Memory Interface (EMI) Image Processing Unit (IPU) Smart DMA ARM11 Platform ARM1136JF-S VFP L1 I/D cache L2 cache AVIC MAX AIPS (2) ETM ARM1136 Platform Peripherals SSI AUDMUX I2C(3) UART(2) CSPI eSDHC(3) CAN(2) ECT IOMUX IIM RTICv3 RNGC SCC KPP PWM Timers RTC WDOG GPT GPIO(3) EPIT HS USBOTG HS USBOTGPHY SPBA HS USBHost FS USBPHY GPU 2D Peripherals MSHC ESAI SPDIF SSI ASRC UART CSPI ATA FEC Internal Memory 3 FuseBox OWIRE Audio/Power Management JTAG Bluetooth MMC/SDIO or WLAN Keypin Connectivity Access Figure 1. i.MX35 Simplified Interface Block Diagram 2 Functional Description and Application Information The i.MX35 consists of the following major subsystems: • ARM1136 Platform—AP domain • SDMA Platform and EMI—Shared domain 2.1 Application Processor Domain Overview The applications processor (AP) and its domain are responsible for running the operating system and applications software, providing the user interface, and supplying access to integrated and external peripherals. The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and data L1 caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced debug and trace interfaces. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 4 Freescale Semiconductor The functionality of AP Domain peripherals includes the user interface; the connectivity, display, security, and memory interfaces; and 128 Kbytes of multipurpose SRAM. 2.2 Shared Domain Overview The shared domain is composed of the shared peripherals, a smart DMA engine (SDMA) and a number of miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA engine. The i.MX35 has a hierarchical memory architecture including L1 caches and a unified L2 cache. This reduces the bandwidth demands for the external bus and external memory. The external memory subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and mobile DDR) and NAND Flash. 2.3 Advanced Power Management Overview To address the continuing need to reduce power consumption, the following techniques are incorporated in the i.MX35: • Clock gating • Power gating • Power-optimized synthesis • Well biasing The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Because static CMOS logic consumes only leakage power, significant power savings can be realized. “Well biasing” is applying a voltage that is greater than VDD to the nwells, and one that is lower than VSS to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage. For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to 1.22 V. 2.4 ARM11 Microprocessor Core The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports the ARM Thumb® instruction sets, features Jazelle® technology (which enables direct execution of Java byte codes) and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The ARM1136JF-S processor core features are as follows: • Integer unit with integral EmbeddedICE™ logic • Eight-stage pipeline i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The i.MX35 core is intended to operate at a maximum frequency of 532 MHz to support the required multimedia use cases. Furthermore, an image processing unit (IPU) is integrated into the AP domain to offload the ARM11 core from performing functions such as color space conversion, image rotation and scaling, graphics overlay, and pre- and post-processing. • • • • • • • Table 2 summarizes information about the i.MX35 core. Table 2. i.MX35 Core Core Acronym ARM11 or ARM1136 Core Name ARM1136 Platform Brief Description The ARM1136™ platform consists of the ARM1136JF-S core, the ETM real-time debug modules, a 6 × 5 multi-layer AHB crossbar switch (MAX), and a vector floating processor (VFP). The i.MX35 provides a high-performance ARM11 microprocessor core and highly integrated system functions. The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. Integrated Memory Features • 16-Kbyte instruction cache • 16-Kbyte data cache • 128-Kbyte L2 cache • 32-Kbyte ROM • 128-Kbyte RAM 2.5 Module Inventory Table 3 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the modules, see the MCIMX35 reference manual. Table 3. Digital and Analog Modules Block Mnemonic 1-WIRE Block Name 1-Wire interface Asynchronous sample rate converter Domain 1 ARM Subsystem ARM1136 platform peripherals Connectivity peripherals Brief Description 1-Wire provides the communication line to a 1-Kbit add-only memory. the interface can send or receive 1 bit at a time. The ASRC is designed to convert the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. It supports a concurrent sample rate conversion of about –120 dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. ASRC SDMA i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. • • • Branch prediction with return stack Low-interrupt latency Instruction and data memory management units (MMUs), managed using micro TLB structures backed by a unified main TLB Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss Virtually indexed/physically addressed L1 caches 64-bit interface to both L1 caches Write buffer (bypassable) High-speed Advanced Micro Bus Architecture (AMBA)™ L2 interface Vector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other floating-point applications ETM™ and JTAG-based debug support Table 3. Digital and Analog Modules (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Block Mnemonic ATA Block Name ATA module Domain 1 SDMA Subsystem Connectivity peripherals Multimedia peripherals Brief Description The ATA block is an AT attachment host interface. Its main use is to interface with IDE hard disk drives and ATAPI optical disk drives. It interfaces with the ATA device over a number of ATA signals. The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (SSIs) and peripheral serial interfaces (audio codecs). The AUDMUX has two sets of interfaces: internal ports to on-chip peripherals and external ports to off-chip audio devices. Data is routed by configuring the appropriate internal and external ports. The CAN protocol is primarily designed to be used as a vehicle serial data bus running at 1 Mbps. This block generates all clocks for the peripherals in the SDMA platform. The CCM also manages ARM1136 platform low-power modes (WAIT, STOP), disabling peripheral clocks appropriately for power conservation, and provides alternate clock sources for the ARM1136 and SDMA platforms. This module is a serial interface equipped with data FIFOs; each master/slave-configurable SPI module is capable of interfacing to both serial port interface master and slave devices. The CSPI ready (SPI_RDY) and slave select (SS) control signals enable fast data communication with fewer software interrupts. ECT (embedded cross trigger) is an IP for real-time debug purposes. It is a programmable matrix allowing several subsystems to interact with each other. ECT receives signals required for debugging purposes (from cores, peripherals, buses, external inputs, and so on) and propagates them (propagation programmed through software) to the different debug resources available within the SoC. The EMI module provides access to external memory for the ARM and other masters. It is composed of the following main submodules: M3IF—provides arbitration between multiple masters requesting access to the external memory. SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture type), and SDR interfaces. NANDFC—provides an interface to NAND Flash memories. WEIM—interfaces to NOR Flash and PSRAM. Each EPIT is a 32-bit “set-and-forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler to adjust the input clock frequency to the required time setting for the interrupts, and the counter value can be programmed on the fly. AUDMUX Digital audio mux ARM CAN(2) CCM CAN module Clock control module ARM ARM Connectivity peripherals Clocks CSPI(2) Configurable serial peripheral interface Embedded cross trigger SDMA, ARM Connectivity peripherals ECT SDMA, ARM Debug EMI External memory interface SDMA External memory interface EPIT(2) Enhanced periodic interrupt timer ARM Timer peripherals i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 7 Table 3. Digital and Analog Modules (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Block Mnemonic ESAI Block Name Enhanced serial audio interface Domain 1 SDMA Subsystem Connectivity peripherals Brief Description The enhanced serial audio interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other DSPs. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. The eSDHCv2 consists of four main modules: CE-ATA, MMC, SD and SDIO. CE-ATA is a hard drive interface that is optimized for embedded applications of storage. The MultiMediaCard (MMC) is a universal, low-cost, data storage and communication media to applications such as electronic toys, organizers, PDAs, and smart phones. The secure digital (SD) card is an evolution of MMC and is specifically designed to meet the security, capacity, performance, and environment requirements inherent in emerging audio and video consumer electronic devices. SD cards are categorized into Memory and I/O. A memory card enables a copyright protection mechanism that complies with the SDMI security standard. SDIO cards provide high-speed data I/O (such as wireless LAN via SDIO interface) with low power consumption. Note: The Ethernet media access controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media Used for general purpose input/output to external ICs. Each GPIO module supports 32 bits of I/O. Each GPT is a 32-bit free-running or set-and-forget mode timer with a programmable prescaler and compare and capture registers. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in set-and-forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. This module accelerates OpenVG and GDI graphics. Note: eSDHCv2 (3) Enhanced secure digital host controller ARM Connectivity peripherals FEC Ethernet SDMA Connectivity peripherals GPIO(3) General purpose I/O modules ARM Pins GPT General ARM purpose timers Timer peripherals GPU2D Graphics ARM processing unit 2Dv1 Multimedia peripherals i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 8 Freescale Semiconductor Table 3. Digital and Analog Modules (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Block Mnemonic I2C(3) Block Name I2C module Domain 1 ARM Subsystem ARM1136 platform peripherals Brief Description Inter-integrated circuit (I2C) is an industry-standard, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. I2C is suitable for applications requiring occasional communications over a short distance among many devices. The interface operates at up to 100 kbps with maximum bus loading and timing. The I2C system is a true multiple-master bus, with arbitration and collision detection that prevent data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring a fixed value. Each I/O multiplexer provides a flexible, scalable multiplexing solution with the following features: • Up to eight output sources multiplexed per pin • Up to four destinations for each input pin • Unselected input paths held at constant levels for reduced power consumption The IPU supports video and graphics processing functions. It also provides the interface for image sensors and displays. The IPU performs the following main functions: • Preprocessing of data from the sensor or from the external system memory • Postprocessing of data from the external system memory • Post-filtering of data from the system memory with support of the MPEG-4 (both deblocking and deringing) and H.264 post-filtering algorithms • Displaying video and graphics on a synchronous (dumb or memory-less) display • Displaying video and graphics on an asynchronous (smart) display • Transferring data between IPU sub-modules and to/from the system memory with flexible pixel reformatting Can be used for either keypin matrix scanning or general purpose I/O. The OSCAUDIO oscillator provides a stable frequency reference for the PLLs. This oscillator is designed to work in conjunction with an external 24.576-MHz crystal. The signal from the external 24-MHz crystal is the source of the CLK24M signal fed into USB PHY as the reference clock and to the real time clock (RTC). IIM IC identification module ARM Security modules IOMUX ARM External signals and pin multiplexing Pins IPUv1 Image ARM processing unit Multimedia peripherals KPP OSCAUD Keypin port OSC audio reference oscillator OSC24M 24-MHz reference oscillator ARM Analog Connectivity peripherals Clock OSC24M Analog Clock i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 9 Table 3. Digital and Analog Modules (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Block Mnemonic MPLL PPLL Block Name Digital phase-locked loops Pulse-width modulator Real-time clock Smart DMA engine Domain 1 SDMA Subsystem Clocks Brief Description DPLLs are used to generate the clocks: MCU PLL (MPLL)—programmable Peripheral PLL (PPLL)—programmable The pulse-width modulator (PWM) is optimized to generate sound from stored sample audio images; it can also generate tones. Provides the ARM1136 platform with a clock function (days, hours, minutes, seconds) and includes alarm, sampling timer, and minute stopwatch capabilities. The SDMA provides DMA capabilities inside the processor. It is a shared module that implements 32 DMA channels and has an interface to connect to the ARM1136 platform subsystem, EMI interface, and the peripherals. The secure JTAG controller (SJC) provides debug and test control with maximum security. The SPBA controls access to the SDMA peripherals. It supports shared peripheral ownership and access rights to an owned peripheral. Sony/Philips digital transceiver interface The SSI is a full-duplex serial port that allows the processor connected to it to communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the I2C sound (I2S) bus standard. The SSIs interface to the AUDMUX for flexible audio routing. Each UART provides serial communication capability with external devices through an RS-232 cable using the standard RS-232 non-return-to-zero (NRZ) encoding format. Each module transmits and receives characters containing either 7 or 8 bits (program-selectable). Each UART can also provide low-speed IrDA compatibility through the use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission). The USB module provides high performance USB on-the-go (OTG) functionality (up to 480 Mbps), compliant with the USB 2.0 specification, the OTG supplement, and the ULPI 1.0 low pin count specification. The module has DMA capabilities handling data transfer between internal buffers and system memory. Each module protects against system failures by providing a method of escaping from unexpected events or programming errors. Once activated, the timer must be serviced by software on a periodic basis. If servicing does not take place, the watchdog times out and then either asserts a system reset signal or an interrupt request signal, depending on the software configuration. PWM ARM ARM1136 platform peripherals Clocks RTC ARM SDMA SDMA System controls SJC SPBA Secure JTAG controller SDMA peripheral bus arbiter Serial audio interface ARM SDMA Pins System controls Connectivity peripherals Connectivity peripherals S/PDIF SSI(2) SDMA Synchronous SDMA, serial interface ARM(2) UART(3) Universal asynchronous receiver/trans mitters Connectivity ARM (UART1,2) peripherals SDMA (UART3) USBOH SDMA High-speed USB on-the-go Connectivity peripherals WDOG Watchdog modules ARM Timer peripherals i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 10 Freescale Semiconductor 1 ARM = ARM1136 platform, SDMA = SDMA platform 3 Signal Descriptions: Special Function Related Pins Table 4. Special Function Related Pins Function Name Pin Name EXT_ARMCLK I2C1_CLK CAPTURE CSPI1_SS1 Mux Mode ALT0 ALT6 ALT4 ALT2 ALT0 ALT1 ALT1 ALT6 Detailed Description External clock input for ARM clock. External peripheral clock source. External clock input of 32 kHz, used when the internal 24M Oscillator is powered off, which could be configured either from CAPTURE or CSPI1_SS1. Clock-out pin from CCM, clock source is controllable and can also be used for debug. PMIC power-ready signal, which can be configured either from GPIO1_0 or TX1. Tamper-detect logic is used to issue a security violation. This logic is activated if the tamper-detect input is asserted. Tamper-detect logic is enabled by the bit of IOMUXC_GPRA[2]. After enabling the logic, it is impossible to disable it until the next reset. Some special functional requirements are supported in the device. The details about these special functions and the corresponding pin names are listed in Table 4. External ARM Clock External Peripheral Clock External 32-kHz Clock Clock Out Power Ready CLKO GPIO1_0 TX1 Tamper Detect GPIO1_1 4 Electrical Characteristics The following sections provide the device-level and module-level electrical characteristics for the i.MX35 processor. 4.1 i.MX35 Chip-Level Conditions This section provides the device-level electrical characteristics for the IC. See Table 5 for a quick reference to the individual tables and sections. Table 5. i.MX35 Chip-Level Conditions Characteristics Absolute Maximum Ratings i.MX35 Operating Ranges Interface Frequency Table/Location Table 6 on page 12 Table 7 on page 12 Table 8 on page 13 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 6. Absolute Maximum Ratings Parameter Supply voltage (core) Supply voltage (I/O) Input voltage range Storage temperature ESD damage immunity: Human Body Model (HBM) Charge Device Model (CDM) 1 2 Symbol VDDmax1 NVCCmax VImax Tstorage Vesd Min. –0.5 –0.5 –0.5 –40 Max. 1.47 3.6 3.6 125 Units V V V oC V — — 2000 2 5003 VDD is also known as QVCC. HBM ESD classification level according to the AEC-Q100-002 standard 3 Corner pins max. 750 V 4.1.1 i.MX35 Operating Ranges Table 7 provides the recommended operating ranges. The term NVCC in this section refers to the associated supply rail of an input or output. Table 7. i.MX35 Operating Ranges Parameter Core Operating Voltage 0 < fARM < 400 MHz Core Operating Voltage 0 < fARM < 532 MHz State Retention Voltage EMI1 WTDG, Timer, CCM, CSPI1 NANDF ATA, USB generic eSDHC1 CSI, SDIO2 JTAG LCDC, TTM, I2C1 NVCC_EMI1,2,3 NVCC_CRM NVCC_NANDF NVCC_ATA NVCC_SDIO NVCC_CSI NVCC_JTAG NVCC_LCDC VDD Symbol Min. 1.22 1.33 1 1.7 1.75 1.75 1.75 1.75 1.75 1.75 1.75 Typical — — — — — — — — — — — Max. 1.47 1.47 — 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 Units V V V V V V V V V V V i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. CAUTION Stresses beyond those listed in Table 6 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Table 7 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 7. i.MX35 Operating Ranges (continued) Parameter I2Sx2,ESAI, I2C2, UART2, UART1, FEC MLB USB OTG PHY USB OTG PHY USB OTG PHY USB HOST PHY OSC24M OSC_AUDIO MPLL PPLL Fusebox program supply voltage Operating Ambient Temperature Range Operating Ambient Temperature Range 1 Symbol NVCC_MISC NVCC_MLB 2 Min. 1.75 1.75 3.17 3.17 3.17 3.0 3.0 3.0 1.4 1.4 3.0 –20 –40 Typical — — 3.3 3.3 3.3 3.3 3.3 3.3 — — 3.6 — — Max. 3.6 3.6 3.43 3.43 3.43 3.6 3.6 3.6 1.65 1.65 3.6 70 85 Units V V V V V V V V V V V oC oC PHY1_VDDA USBPHY1_VDDA_BIAS USBPHY1_UPLLVDD PHY2_VDD OSC24M_VDD OSC_AUDIO_VDD MVDD PVDD FUSE_VDD 3 TA TA EMI I/O interface power supply should be set up according to external memory. For example, if using SDRAM then NVCC_EMI1,2,3 should all be set at 3.3 V (typ.). If using MDDR or DDR2, NVC_EMI1,2,3 must be set at 1.8 V (typ.). 2 MLB Interface I/O pins can be programmed to function as GPIO for the consumer and industrial parts by setting NVCC_MLB to 1.8 or 3.3 V. NVCC_MLB can be left floating. 3 The Fusebox read supply is connected to supply of the full speed USB PHY. FUSE_VDD is only used for programming. It is recommended that FUSE_VDD be connected to ground when not being used for programming. FUSE_VDD should be supplied by following the power up sequence given in Section 4.3.1, “Powering Up.” 4.1.2 Interface Frequency Limits Table 8. Interface Frequency Table 8 provides information on interface frequency limits. ID 1 Parameter JTAG TCK Frequency Symbol fJTAG Min. DC Typ. 5 Max. 10 Units MHz i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 4.2 Power Modes Table 9. i.MX35 Power Modes QVCC (ARM/L2 Peripheral) Typ. Max. MVDD/PVDD Typ. Max. OSC24M_VDD OSC_AUDO_VDD Typ. Max. Power Mode Description Wait VDD1,2,3,4 = 1.1 V (min.) ARM is in wait for interrupt mode. MAX is active. L2 cache is kept powered. MCU PLL is on (400 MHz) PER PLL is off (can be configured) (default: 300 MHz) Module clocks are gated off (can be configured by CGR register). OSC 24M is ON. OSC audio is off (can be configured). RNGC internal osc is off. VDD1,2,3,4 = 1.1 V (min.) ARM is in wait for interrupt mode. MAX is halted. L2 cache is kept powered. L2 cache control logic off. AWB enabled. MCU PLL is on(400 MHz) PER PLL is off (can be configured). (300 Mhz). Module clocks are gated off (can be configured by CGR register). OSC 24M is ON. OSC audio is off (can be configured) RNGC internal osc is off VDD1,2,3,4 = 1.1 V (min.) ARM is in wait for interrupt mode. MAX is halted L2 cache is kept powered. L2 cache control logic off. AWB enabled. MCU PLL is off. PER PLL is off. All clocks are gated off. OSC 24 MHz is on OSC audio is off RNGC internal osc is off 16 mA — 7.2 mA — 1.2 mA — Doze 12.4 mA — 7.2 mA — 1.2 mA — Stop 1.1 mA — 400 µA — 1.2 mA — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 9 provides descriptions of the power modes of the i.MX35 processor. Table 9. i.MX35 Power Modes (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 15 QVCC (ARM/L2 Peripheral) Typ. Static VDD1,2,3,4 = 1.1 V (min.) ARM is in wait for interrupt mode. MAX is halted L2 cache is kept powered. L2 cache control logic off. AWB enabled. MCU PLL is off. PER PLL is off. All clocks are gated off. OSC 24MHz is on OSC audio is off RNGC internal osc is off Max. MVDD/PVDD Typ. Max. OSC24M_VDD OSC_AUDO_VDD Typ. Max. Power Mode Description 820 µA — 50 µA — 24 µA — Note: Typical column: TA = 25 °C 4.3 Supply Power-Up/Power-Down Requirements and Restrictions CAUTION Any i.MX35 board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences can result in irreversible damage to the i.MX35 processor (worst-case scenario). NOTE Deviation from these sequences may also result in one or more of the following: • • • Excessive current during power-up phase Prevent the device from booting Programming of unprogrammed fuses This section provides power-up and power-down sequence guidelines for the i.MX35 processor. 4.3.1 Powering Up The power-up sequence should be completed as follows: 1. Assert Power on Reset (POR). 2. Turn on digital logic domain and IO power supply: VDDn, NVCCx 3. Wait until VDDn and NVCCx power supplies are stable + 32 μs. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Figure 2 shows the power-up sequence and timing. Figure 2. i.MX35 Power-Up Sequence and Timing 4.3.2 Powering Down The power-up sequence in reverse order is recommended for powering down. However, all power supplies can be shut down at the same time. 4.4 Reset Timing There are two ways of resetting the i.MX35 using external pins: • Power On Reset (using the POR_B pin) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 4. Turn on all other power supplies: PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, FUSEVDD. (Always FUSE_VDD should be connected to ground, except when eFuses are to be programmed.) 5. Wait until PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, (FUSEVDD, optional). Power supplies are stable + 100 μs. 6. Deassert the POR signal. • System Reset (using the RESET_IN_B pin) 4.4.1 Power On Reset POR_B is normally connected to a power management integrated circuit (PMIC). The PMIC asserts POR_B while the power supplies are turned on and negates POR_B after the power up sequence is finished. See Figure 2. Assuming the i.MX35 chip is already fully powered; it is still possible to reset all of the modules to their default reset by asserting POR_B for at least 4 CKIL cycles and later de-asserting POR_B. This method of resetting the i.MX35 can also be supported by tying the POR_B and RESET_IN_B pins together. POR_B At least 4 CKIL cycles CKIL Figure 3. Timing Between POR_B and CKIL for Complete Reset of i.MX35 4.4.2 System Reset System reset can be achieved by asserting RESET_IN_B for at least 4 CKIL cycles and later negating RESET_IN_B. The following modules are not reset upon system reset: RTC, PLLs, CCM, and IIM. POR_B pin must be deasserted all the time. RESET_IN_B At least 4 CKIL cycles CKIL Figure 4. Timing Between RESET_IN_B and CKIL for i.MX35 System Reboot 4.5 Power Characteristics The table shows values representing maximum current numbers for the i.MX35 under worst case voltage and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 10. Power Consumption Power Supply QVCC MVDD, PVDD NVCC_EMI1, NVCC_EMI2, NVCC_EMI3, NVCC_LCDC, NVCC_NFC FUSE_VDD1 NVCC_MISC, NVCC_CSI, NVCC_SDIO, NVCC_CRM, NVCC_ATA, NVCC_MLB, NVCC_JTAG OSC24M_VDD, OSC_AUDIO_VDD, PHY1_VDDA, PHY2_VDD, USBPHY1_UPLLVDD, USBPHY1_VDDA_BIAS 1 Voltage (V) 1.47 1.65 1.9 3.6 3.6 3.6 Max Current (mA) 400 20 90 62 60 25 This rail is connected to ground; it only needs a voltage if eFuses are to be programmed. FUSE_VDD should be supplied by following the power up sequence given in Section 4.3.1, “Powering Up.” The method for obtaining max current is as follows: 1. Measure worst case power consumption on individual rails using directed test on i.MX35. 2. Correlate worst case power consumption power measurements with worst case power consumption simulations. 3. Combine common voltage rails based on power supply sequencing requirements 4. Guard band worst case numbers for temperature and process variation. Guard band is based on process data and correlated with actual data measured on i.MX35. 5. The sum of individual rails is greater than real world power consumption, as a real system does not typically maximize power consumption on all peripherals simultaneously. 4.6 Thermal Characteristics The thermal resistance characteristics for the device are given in Table 11. These values were measured under the following conditions: • Two-layer substrate • Substrate solder mask thickness: 0.025 mm • Substrate metal thicknesses: 0.016 mm • Substrate core thickness: 0.200 mm • Core via I.D: 0.168 mm, Core via plating 0.016 mm. • Full array map design, but nearly all balls under die are power or ground. • Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K • Mold compound: k = 0.9 W/m K i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 532 MHz. Common supplies have been bundled according to the i.MX35 power-up sequence requirements. Peak numbers are provided for system designers so that the i.MX35 power supply requirements will be satisfied during startup and transient conditions. Freescale recommends that system current measurements be taken with customer-specific use-cases to reflect normal operating conditions in the end system. Table 11. Thermal Resistance Data Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Rating Junction to ambient1 natural convection Junction to ambient1 natural convection Junction to ambient1 (at 200 ft/min) Junction to ambient1 (at 200 ft/min) Junction to boards2 Junction to case (top)3 Junction to package top4 1 Condition Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection Symbol ReJA ReJA ReJMA ReJMA ReJB ReJCtop ΨJT Value 53 30 44 27 19 10 2 Unit ºC/W ºC/W ºC/W ºC/W ºC/W ºC/W ºC/W Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 2 Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for this package. 3 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written as Psi-JT. 4.7 I/O Pin DC Electrical Characteristics I/O pins are of two types: GPIO and DDR. DDR pins can be configured in three different drive strength modes: mobile DDR, SDRAM, and DDR2. The SDRAM and mobile DDR modes can be further customized at three drive strength levels: normal, high, and max. Table 12 shows currents for the different DDR pin drive strength modes. Table 12. DDR Pin Drive Strength Mode Current Levels Drive Mode Mobile DDR (1.8 V) SDRAM (1.8 V) SDRAM (3.3 V) DDR2 (1.8 V) Normal 3.6 mA — 4 mA — High 7.2 mA — 8 mA — Max. 10.8 mA 6.5 mA 12 mA 13.4 mA i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 19 Table 13. I/O Pin DC Electrical Characteristics Pin GPIO DC Electrical Characteristics Symbol High-level output voltage Low-level output voltage High-level output current for slow mode (Voh = 0.8 × NVCC) High-level output current for fast mode (Voh = 0.8 × NVCC) Low-level output current for slow mode (Voh = 0.2 × NVCC) Low-level output current for fast mode (Voh = 0.2 × NVCC) High-level DC Input Voltage with 1.8 V, 3.3 V NVCC (for digital cells in input mode) Low-level DC Input Voltage with 1.8 V, 3.3 V NVCC (for digital cells in input mode Input Hysteresis Schmitt trigger VT+ Schmitt trigger VT– Pull-up resistor (22 kΩ PU) Pull-up resistor (47 kΩ PU) Pull-up resistor (100 kΩ PU) Pull-down resistor (100 kΩ PD) External resistance to pull keeper up when enabled External resistance to pull keeper down when enabled Voh Vol Ioh Test Condition Ioh = –1 mA Ioh = specified drive Iol = 1 mA Iol = specified drive Standard drive High drive Max. drive Standard drive High drive Max. drive Standard drive High drive Max. drive Standard drive High drive Max. drive — Min. NVCC – 0.15 0.8 × NVCC — –2.0 –4.0 –8.0 –4.0 –6.0 –8.0 2.0 4.0 8.0 4.0 6.0 8.0 0.7 × NVCC Typ. — — — Max. — 0.15 0.2 × NVCC — Unit V V mA Ioh — — mA Iol — — mA Iol — — mA VIH — NVCC V VIL — –0.3 V — 0.3 × NVCC V VHYS VT+ VT– Rpu Rpu Rpu Rpd Rkpu Rkpd OVDD = 3.3 V OVDD = 1.8 V — — Vi = 0 Vi = 0 Vi = 0 Vi = NVCC Ipu > 620μA @ min Vddio = 3.0 V Ipu > 510μA @min Vddio = 3.0 V — 0.5 × NVCC — — — — — — — 410 330 — — 22 47 100 100 — — — mV V 0.5 × NVCC — — — — 4.8 5.9 V kΩ kΩ kΩ kΩ kΩ kΩ i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 13 shows the DC electrical characteristics for GPIO, DDR2, mobile DDR, and SDRAM pins. The term NVCC refers to the power supply voltage that feeds the I/O of the module in question. For example, NVCC for the SD/MMC interface refers to NVCC_SDIO. Table 13. I/O Pin DC Electrical Characteristics (continued) Pin DDR2 DC Electrical Characteristics Symbol High-level output voltage Low-level output voltage Output min. source current Output min. sink current DC input logic high DC input logic low DC input signal voltage (for differential signal) DC differential input voltage Termination voltage Voh Vol Ioh Iol VIH(dc) VIL(dc) Vin(dc) Vid(dc) Vtt Test Condition — — — — — — — — — –13.4 13.4 NVCC ÷ 2 + 0.125 –0.3 V –0.3 0.25 NVCC ÷ 2 – 0.04 — — NVCC – 0.08 0.8 × NVCC — –3.6 –7.2 –10.8 3.6 7.2 10.8 0.7 × NVCC –0.3 — –100 — — Min. NVCC – 0.28 Typ. — — — — — — — — NV CC ÷2 — — — — — Max. — 0.28 — — NVCC + 0.3 NVCC ÷ 2 – 0.125 NVCC + 0.3 NVCC + 0.6 NVCC ÷ 2 + 0.04 ±1 ±1 — 0.08 0.2 × NVCC — Unit V V mA mA V V V V V Input current (no pull-up/down) Tri-state I/O supply current Mobile DDR High-level output voltage Low-level output voltage High-level output current (Voh = 0.8 × NVCCV) Low-level output current (Vol = 0.2 × NVCCV) High-Level DC CMOS input voltage Low-Level DC CMOS input voltage Differential receiver VTH+ Differential receiver VTH– Input current (no pull-up/down) Tri-state I/O supply current IIN Icc – N VCC — — — — — IOH = –1mA IOH = specified drive IOL = 1mA IOL = specified drive Standard drive High drive Max. drive Standard Drive High Drive Max. Drive — — — — VI = 0 VI = NVCC VI = NVCC or 0 μA μA V V mA — — — mA VIH VIL VTH+ VTH– IIN Icc – N VCC — — — — — — NVCC + 0.3 0.2 × NVCC 100 V V mV mV ±1 ±1 μA μA i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 13. I/O Pin DC Electrical Characteristics (continued) Pin SDR (1.8 V) DC Electrical Characteristics Symbol High-level output voltage Low-level output voltage High-level output current Low-level output current High-level DC Input Voltage Low-level DC Input Voltage Input current (no pull-up/down) Tri-state I/O supply current Tri-state core supply current SDR (3.3 V) High-level output voltage Voh Vol Ioh Iol VIH VIL IIN Icc (NVCC) Icc (NVCC) Voh Test Condition loh = 5.7 mA loh = 5.7 mA Max. drive Max. drive — — VI = 0 VI=NVCC VI = OVDD or 0 VI = VDD or 0 Ioh=specified drive (Ioh = –4, –8, –12, –16 mA) Ioh=specified drive (Ioh = 4, 8, 12, 16 mA) Standard drive High drive Max. drive Standard drive High drive Max. drive — — VI = 0 VI = NVCC Tri-state I/O supply current Icc (NVCC) VI = NVCC or 0 — — ±1 μA Min. OVDD – 0.28 — 5.7 7.3 1.4 –0.3 — — — 2.4 Typ. — — — — — — — — — — Max. — 0.4 — — 1.98 0.8 150 80 1180 1220 — Unit V V mA mA V V μA μA μA V Low-level output voltage High-level output current Vol Ioh — –4.0 –8.0 –12.0 4.0 8.0 12.0 2.0 –0.3V — — — 0.4 — V mA Low-level output current Iol — — mA High-level DC Input Voltage Low-level DC Input Voltage Input current (no pull-up/down) VIH VIL IIN — — — 3.6 0.8 ±1 V V μA 4.8 I/O Pin AC Electrical Characteristics From Output Under Test Test Point CL Figure 5 shows the load circuit for output pins. CL includes package, probe and jig capacitance Figure 5. Load Circuit for Output Pin i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 6 shows the output pin transition time waveform. 80% Output (at pin) 20% PA1 PA1 80% 20% 0V Figure 6. Output Pin Transition Time Waveform 4.8.1 AC Electrical Test Parameter Definitions AC electrical characteristics in Table 14 through Table 19 are not applicable for the output open drain pull-down driver. The dI/dt parameters are measured with the following methodology: • The zero voltage source is connected between pin and load capacitance. • The current (through this source) derivative is calculated during output transitions. Table 14. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode [NVCC = 3.0 V–3.6 V] Parameter Duty cycle Output pin slew rate (max. drive) Output pin slew rate (high drive) Output pin slew rate (standard drive) Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) Symbol Fduty tps tps tps tdit tdit tdit Test Condition — 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 40 0.79/1.12 0.49/0.73 0.48/0.72 0.27/0.42 0.25/0.40 0.14/0.21 15 16 8 9 4 4 Typ. Rise/Fall — 1.30/1.77 0.84/1.23 0.76/1.10 0.41/0.62 0.40/0.59 0.21/0.32 36 38 20 21 10 10 Max. Rise/Fall 60 2.02/2.58 1.19/1.58 1.17/1.56 0.63/0.86 0.60/0.83 0.32/0.44 76 80 45 47 22 23 Units % V/ns V/ns V/ns mA/ns mA/ns mA/ns Table 15. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode [NVCC = 1.65 V–1.95 V] Parameter Duty cycle Output pin slew rate (max. drive) Symbol Fduty tps Test Condition — 25 pF 50 pF Min. Rise/Fall 40 0.30/0.42 0.20/0.29 Typ. — 0.54/0.73 0.35/0.50 Max. Rise/Fall 60 0.91/1.20 0.60/0.80 Units % V/ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. NVCC Table 15. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode [NVCC = 1.65 V–1.95 V] (continued) Parameter Output pin slew rate (high drive) Output pin slew rate (standard drive) Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) Symbol tps tps tdit tdit tdit Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 0.19/0.28 0.12/0.18 0.12/0.18 0.07/0.11 7 7 5 5 2 2 Typ. 0.34/0.49 0.34/0.49 0.20/0.30 0.11/0.17 21 22 14 15 7 7 Max. Rise/Fall 0.58/0/79 0.36/0.49 0.34/0.47 0.20/0.27 56 58 38 40 18 19 Units V/ns V/ns mA/ns mA/ns mA/ns Table 16. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode for [NVCC = 3.0 V–3.6 V] Parameter Duty cycle Output pin slew rate (max. drive) Output pin slew rate (high drive) Output pin slew rate (standard drive) Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) Symbol Fduty tps tps tps tdit tdit tdit Test Condition — 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. rise/fall 40 0.96/1.40 0.54/0.83 0.76/1.10 0.41/0.64 0.52/0.78 0.28/0.44 46 49 35 37 22 23 Typ. — 1.54/2.10 0.85/1.24 1.19/1.71 0.63/0.95 0.80/1.19 0.43/0.64 108 113 82 86 52 55 Max. Rise/Fall 60 2.30/3.00 1.26/1.70 1.78/2.39 0.95/1.30 1.20/1.60 0.63/0.87 250 262 197 207 116 121 Units % V/ns V/ns V/ns mA/ns mA/ns mA/ns Table 17. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode [NVCC = 1.65 V–1.95 V] Parameter Duty cycle Output pin slew rate (max. drive) Output pin slew rate (high drive) Symbol Fduty tps tps Test Condition — 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 40 0.40/0.57 0.25/0.36 0.38/0.48 0.20/0.30 Typ. — 0.72/0.97 0.43/0.61 0.59/0.81 0.34/0.50 Max. Rise/Fall 60 1.2/1.5 0.72/0.95 0.98/1.27 0.56/0.72 Units % V/ns V/ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 24 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 17. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode [NVCC = 1.65 V–1.95 V] (continued) Parameter Output pin slew rate (standard drive) Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) Symbol tps tdit tdit tdit Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 0.23/0.32 0.13/0.20 7 7 11 12 9 10 Typ. 0.40/0.55 0.23/0.34 43 46 31 33 27 28 Max. Rise/Fall 0.66/0.87 0.38/0.52 112 118 81 85 71 74 Units V/ns mA/ns mA/ns mA/ns Table 18. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode [NVCC = 2.25 V–2.75 V] Parameter Duty cycle Output pin slew rate (max. drive) Symbol Fduty tps Test Condition — 25 pF 40 pF 50 pF 25 pF 40 pF 50 pF 25 pF 40 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 40 0.63/0.85 0.52/0.67 0.41/0.59 0.40/0.58 0.33/0.43 0.25/0.37 0.24/0.36 0.19/0.25 0.13/0.21 22 23 15 16 7 8 Typ. — 1.10/1.40 0.90/1.10 0.73/0.99 0.71/0.98 0.56/0.70 0.43/0.60 0.41/0.59 0.32/0.35 0.23/0.33 62 65 42 44 21 22 Max. Rise/Fall 60 1.86/2.20 1.53/1.73 1.20/1.50 1.16/1.40 0.93/1.07 0.68/0.90 0.66/0.87 0.51/0.59 0.36/0.48 148 151 102 107 52 54 Units % V/ns Output pin slew rate (high drive) tps V/ns Output pin slew rate (standard drive) tps V/ns Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) tdit tdit tdit mA/ns mA/ns mA/ns Table 19. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode [NVCC = 2.25 V–2.75 V] Parameter Duty cycle Symbol Fduty Test Min. Condition Rise/Fall — 40 Typ. — Max. Units Notes Rise/Fall 60 % — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 19. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode [NVCC = 2.25 V–2.75 V] (continued) Parameter Output pin slew rate (max. drive) Symbol tps Test Min. Condition Rise/Fall 25 pF 40 pF 50 pF 25 pF 40 pF 50 pF 25 pF 40 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Typ. Max. Units Notes Rise/Fall V/ns 2 0.84/1.10 1.45/1.80 2.40/2.80 0.68/0.83 1.14/1.34 1.88/2.06 0.58/0.72 0.86/1.10 1.40/1.70 0.69/0.96 1.18/1.50 1.90/2.30 0.55/0.69 0.92/1.10 1.49/1.67 0.40/0.59 0.67/0.95 1.10/1.30 0.24/0.36 0.80/1.00 1.30/1.60 0.37/0.47 0.62/0.76 1.00/1.14 0.13/0.21 0.45/0.65 0.70/0.95 46 49 33 35 28 29 124 131 89 94 75 79 310 324 290 304 188 198 Output pin slew rate (high drive) tps V/ns Output pin slew rate (standard drive) tps V/ns Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) tdit tdit tdit mA/ns mA/ns mA/ns 3 4.8.2 AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM Modes) Table 20. AC Electrical Characteristics of DDR Type IO Pins in DDR2 Mode Parameter Symbol Fduty f tps tdit Test Condition — — 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 45 — 0.86/0.98 0.46/054 65 70 Typ. 50 133 1.35/1.5 0.72/0.81 157 167 Max. Rise/Fall 55 — 2.15/2.19 1.12/1.16 373 396 Units % MHz V/ns mA/ns Duty cycle Clock frequency Output pin slew rate Output pin di/dt Table 21. AC Requirements of DDR2 Pins Parameter1 AC input logic high AC input logic low AC differential cross point voltage for output2 1 Symbol VIH(ac) VIL(ac) Vox(ac) Min. NVCC ÷ 2 + 0.25 –0.3 NVCC ÷ 2 – 0.125 Max. NVCC + 0.3 NVCC ÷ 2 – 0.25 NVCC ÷ 2 + 0.125 Units V V V The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in this document. 2 The typical value of Vox(ac) is expected to be about 0.5 × NVCC and Vox(ac) is expected to track variation in NVCC. Vox(ac) indicates the voltage at which the differential output signal must cross. Cload = 25 pF. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 26 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 22. AC Electrical Characteristics of DDR Type IO Pins in mDDR Mode Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 27 Parameter Duty cycle Clock frequency Output pin slew rate (max. drive) Output pin slew rate (high drive) Output pin slew rate (standard drive) Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) Symbol Fduty f tps tps tps tdit tdit tdit Test Condition — — 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 45 — 0.80/0.92 0.43/0.50 0.37/0.43 0.19/0.23 0.18/0.22 0.10/0.12 64 69 37 39 18 20 Typ. 50 133 1.35/1.50 0.72/0.81 0.62/0.70 0.33/0.37 0.31/0.35 0.16/0.18 171 183 100 106 50 52 Max. Rise/Fall 55 — 2.23/2.27 1.66/1.68 1.03/1.05 0.75/0.77 0.51/0.53 0.38/0.39 407 432 232 246 116 123 Units % MHz V/ns V/ns V/ns mA/ns mA/ns mA/ns Table 23. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Parameter Clock frequency Output pin slew rate (max. drive) Output pin slew rate (high drive) Output pin slew rate (standard drive) Output pin di/dt (max. drive) Output pin di/dt (high drive) Output pin di/dt (standard drive) Symbol f tps tps tps tdit tdit tdit Test Condition — 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall — 1.11/1.20 0.97/0.65 0.76/0.80 0.40/0.43 0.38/0.41 0.20/0.22 89 94 59 62 29 31 Min. Clock Frequency 125 1.74/1.75 0.92/0.94 1.16/1.19 0.61/0.63 0.59/0.60 0.31/0.32 198 209 132 139 65 69 Max. Rise/Fall — 2.42/2.46 1.39/1.30 1.76/1.66 0.93/0.87 0.89/0.82 0.47/0.43 398 421 265 279 132 139 Units MHz V/ns V/ns V/ns mA/ns mA/ns mA/ns Table 24. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V) Parameter Clock frequency Output pin slew rate (max. drive)1 Symbol f tps Test Condition — 25 pF 50 pF Min. Rise/Fall 125 2.83/2.68 1.59/1.49 Typ. — 1.84/1.85 1.03/1.05 Max. Rise/Fall — 1.21/1.40 0.70/0.75 Units MHz V/ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Table 24. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V) (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Parameter Output pin di/dt (max. drive)2 Input pin transition times3 Input pin propagation delay, 50%–50% Input pin propagation delay, 40%–60% 1 Symbol didt trfi tpi tpi Test Condition 25 pF 50 pF 1.0 pF 1.0 pF 1.0 pF Min. Rise/Fall 89 95 0.07/0.08 0.35/1.17 1.18/1.99 Typ. 202 213 0.11/0.12 0.63/1.53 1.45/2.35 Max. Rise/Fall 435 456 0.16/0.20 1.16/2.04 1.97/2.85 Units mA/ns ns ns ns Min. condition for tps: wcs model, 1.1 V, IO 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Max. condition for tdit: bcs model, 1.3 V, IO 1.95 V, and –40 °C. 3 Max. condition for tpi and trfi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Min. condition for tpi and trfi: bcs model, 1.3 V, IO 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). 4.9 Module-Level AC Electrical Specifications This section contains the AC electrical information (including timing specifications) for the modules of the i.MX35. The modules are listed in alphabetical order. 4.9.1 AUDMUX Electrical Specifications The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. See the electrical specification for SSI. 4.9.2 CSPI AC Electrical Specifications The i.MX35 provides two CSPI modules. CSPI ports are multiplexed in the i.MX35 with other pins. See the “External Signals and Multiplexing” chapter of the reference manual for more details. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 28 Freescale Semiconductor Figure 7 and Figure 8 depict the master mode and slave mode timings of the CSPI, and Table 25 lists the timing parameters. SPI_RDY CS11 SSn[3:0] CS1 CS3 CS2 CS3 CS6 CS4 CS5 SCLK CS7 CS8 MOSI CS9 MISO CS10 CS2 Figure 7. CSPI Master Mode Timing Diagram SSn[3:0] CS1 SCLK CS9 MISO CS7 MOSI CS8 CS10 CS3 CS2 CS3 CS2 CS6 CS4 CS5 Figure 8. CSPI Slave Mode Timing Diagram Table 25. CSPI Interface Timing Parameters ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 SCLK cycle time SCLK high or low time SCLK rise or fall SSn[3:0] pulse width SSn[3:0] lead time (CS setup time) SSn[3:0] lag time (CS hold time) MOSI setup time MOSI hold time MISO setup time Parameter Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi tSmiso Min. 60 30 — 30 30 30 5 5 5 Max. — — 7.6 — — — — — — Units ns ns ns ns ns ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 29 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 25. CSPI Interface Timing Parameters (continued) ID CS10 CS11 MISO hold time SPI_RDY setup time Parameter Symbol tHmiso tSDRY Min. 5 5 Max. — — Units ns ns 4.9.3 DPLL Electrical Specifications There are three PLLs inside the i.MX35, all based on the same PLL design. The reference clock for these PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via EXTAL24M and XTAL24 pins. It is also possible to connect an external 24-MHz clock directly to EXTAL24M, bypassing the internal oscillator. DPLL specifications are listed in Table 26. Table 26. DPLL Specifications Parameter Reference clock frequency Max. allowed reference clock phase noise Min. Typ. Max. 10 — 24 — 100 Unit MHz Comments 0.03 2 Tdck1 Fmodulation < 50 kHz 0.01 50 kHz < Fmodulation 300 Hz 0.15 Fmodulation > 300 KHz 80 100 150 100 150 μs μs mV — — Fmodulation < 50 kHz 50 kHz < Fmodulation 300 Hz Fmodulation > 300 KHz Frequency lock time (FOL mode or non-integer MF) Phase lock time Max. allowed PL voltage ripple — — — — — — 1 There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design. 4.9.4 Embedded Trace Macrocell (ETM) Electrical Specifications ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point access (TPA) that supports TRACECLK frequencies up to 133 MHz. Figure 9 depicts the TRACECLK timings of ETM, and Table 27 lists the timing parameters. Figure 9. ETM TRACECLK Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 30 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 27. ETM TRACECLK Timing Parameters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID Tcyc Twl Twh Tr Tf Clock period Low pulse width High pulse width Clock and data rise time Clock and data fall time Parameter Min. Frequency dependent 2 2 — — Max. — — — 3 3 Unit ns ns ns ns ns Figure 10 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and Table 28 lists the timing parameters. Figure 10. Trace Data Timing Diagram Table 28. ETM Trace Data Timing Parameters ID Ts Th Data setup Data hold Parameter Min. 2 1 Max. — — Unit ns ns 4.9.4.1 Half-Rate Clocking Mode When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10. The same Ts and Th parameters from Table 28 still apply with respect to the falling edge of the TRACECLK signal. 4.9.5 EMI Electrical Specifications This section provides electrical parametrics and timing for the EMI module. 4.9.5.1 NAND Flash Controller Interface (NFC) The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 11, Figure 12, i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 31 Figure 13, and Figure 14 depict the relative timing requirements among different signals of the NFC at module level for normal mode. Table 29 lists the timing parameters. NFCLE NF1 NF3 NFCE NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Command NF7 NF2 NF4 Figure 11. Command Latch Cycle Timing DIagram NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Address NF7 NF4 Figure 12. Address Latch Cycle Timing DIagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 32 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[15:0] Data to NF NF7 Figure 13. Write Data Latch Cycle Timing DIagram NFCLE NFCE NF14 NF15 NF13 NFRE NF16 NFRB NF12 NFIO[15:0] Data from NF NF17 Figure 14. Read Data Latch Cycle Timing DIagram Table 29. NFC Timing Parameters1 Timing T = NFC Clock Cycle2 Min. NF1 NF2 NF3 NF4 NFCLE setup time NFCLE hold time NFCE setup time NFCE hold time tCLS tCLH tCS tCH T – 1.0 ns T – 2.0 ns T – 1.0 ns T – 2.0 ns Max. — — — — Example Timing for NFC Clock ≈ 33 MHz T = 30 ns Min. 29 25 29 209 Max. — — — — ns ns ns ns ID Parameter Symbol Unit i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 33 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 29. NFC Timing Parameters1 (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Timing T = NFC Clock Cycle2 Min. NF5 NF6 NF7 NF8 NF9 NF10 NF11 NF12 NF13 NF14 NF15 NF16 NF17 1 2 ID Parameter Symbol Example Timing for NFC Clock ≈ 33 MHz T = 30 ns Min. 29.5 Max. Unit Max. NF_WP pulse width NFALE setup time NFALE hold time Data setup time Data hold time Write cycle time NFWE hold time Ready to NFRE low NFRE pulse width READ cycle time NFRE high hold time Data setup on READ Data hold on READ tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR 6T T T – 1.5 ns — — — — 2T T – 2.5 ns — — — 8400 44.5 58 11 9 52 30 27.5 30 106 ns — — — — ns ns ns ns ns ns — — — — — — ns ns ns ns ns ns T – 3.0 ns T T – 5.0 ns 59 27 1.5T 2T 0.5T – 2.5 ns N/A N/A The flash clock maximum frequency is 50 MHz. Subject to DPLL jitter specification listed in Table 26, "DPLL Specifications," on page 30. NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not NFC clock related. 4.9.5.2 Wireless External Interface Module (WEIM) All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK rising edge or falling edge according to the corresponding assertion or negation control fields. The address always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. Output data begins related to BCLK rising edge except in muxed mode where both rising and falling edge may be used according to control register configuration. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 34 Freescale Semiconductor Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 15 depicts the timing of the WEIM module, and Table 30 lists the timing parameters. WE1 BCLK WE4 Address CSx_B RW_B OE_B WE10 WE12 EBy_B LBA_B WE14 WE16 Output Data WE15 WE17 WE11 WE13 WE6 WE8 WE7 WE9 WEIM Output Timing WE2 WE3 ... WE5 WEIM Input Timing BCLK WE18 Input Data WE20 WE22 ECB_B WE24 WE26 DTACK_B WE27 Figure 15. WEIM Bus Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 35 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 30. WEIM Bus Timing Parameters1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID WE1 WE2 WE3 WE4 WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE18 WE20 WE22 WE24 WE26 WE27 1 2 Parameter BCLK cycle time2 BCLK low-level width2 BCLK high-level width2 Clock fall to address valid Clock rise/fall to address invalid Clock rise/fall to CSx_B valid Clock rise/fall to CSx_B invalid Clock rise/fall to RW_B valid Clock rise/fall to RW_B invalid Clock rise/fall to OE_B valid Clock rise/fall to OE_B invalid Clock rise/fall to EBy_B valid Clock rise/fall to EBy_B invalid Clock rise/fall to LBA_B valid Clock rise/fall to LBA_B invalid Clock rise/fall to Output Data valid Clock rise to Output Data invalid Input Data Valid to Clock rise3 Clock rise to Input Data invalid3 ECB_B setup time3 ECB_B hold time3 DTACK_B setup time DTACK_B hold time Min. 14.5 7 7 15 22 15 3.6 8 3 7 3.8 6 6 17.5 0 5 0 1 1 5 0 5.4 –3.2 Max. — — — 21 25 19 5 12 8 12 5.5 11.5 10 20 1 10 2.5 — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns “High” is defined as 80% of signal value, and “low” is defined as 20% of signal value. BCLK parameters are measured from the 50% point. For example, “high” is defined as 50% of signal value and “low” is defined as 50% of signal value. 3 Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0. NOTE Test conditions: load capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is set to maximum drive. Recommended drive strength for all controls, address and BCLK is set to maximum drive. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 36 Freescale Semiconductor Figure 16 through Figure 21 depict some examples of basic WEIM accesses to external memory devices with the timing parameters mentioned in Table 30 for specific control parameter settings. BCLK WE4 ADDR CS [x] RW WE14 LBA WE10 WE15 Last Valid Address WE6 V1 WE5 Next Address WE7 OE WE11 EB[y] WE12 WE13 WE20, WE21 DATA V1 WE18, WE 19 Figure 16. Synchronous Memory Timing Diagram for Read Access—WSC = 1 BCLK WE4 ADDR CS[x] Last Valid Address WE6 WE8 RW LBA OE WE12 EB[y] WE13 WE17 DATA WE16 V1 WE14 WE15 V1 WE7 WE9 WE5 Next Address Figure 17. Synchronous Memory Timing Diagram for Write Access— WSC = 1, EBWA = 1, EBWN = 1, LBN = 1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 37 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. BCLK ADDR Last Valid Addr CS[x] RW WE14 WE15 WE11 WE6 Address V1 Address V2 WE7 LBA OE EB[y] WE10 WE12 WE24, WE25 WE24, WE25 WE13 ECB WE22, WE23 WE20, WE21 DATA WE18, WE19 WE22, WE23 WE20, WE21 V2 Halfword V2+2 Halfword V1 V1+2 Halfword Halfword WE18, WE19 Figure 18. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses— WSC = 2, SYNC = 1, DOL = 0 BCLK WE4 ADDR Last Valid Addr CS[x] WE6 Address V1 WE7 WE5 RW WE8 WE14 WE15 WE9 LBA OE EB[y] WE12 WE13 WE24, WE25 ECB WE22, WE23 WE17 DATA WE16 V1 WE16 WE17 V1+4 V1+8 V1+12 Figure 19. Synchronous Memory TIming Diagram for Burst Write Access— BCS = 1, WSC = 4, SYNC = 1, DOL = 0, PSR = 1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 38 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. WE4 WE5 Address V1 WE16 Write Data WE7 CS [x] WE6 RW WE8 Write WE14 WE15 WE9 LBA OE EB[y] WE12 WE13 Figure 20. Muxed A/D Mode Timing Diagram for Synchronous Write Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1 BCLK WE4 ADDR/ Last Valid Addr M_DATA WE6 CS[x] WE5 Address V1 WE18, WE19 WE20, WE21 Read Data WE7 RW WE14 LBA WE15 OE EB[y] WE12 WE10 WE11 WE13 Figure 21. Muxed A/D Mode Timing Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 39 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. WE4 ADDR/ Last Valid Addr M_DATA BCLK WE5 WE17 CS [x] WE31 ADDR RW WE39 LBA WE35 OE WE37 EB[y] DATA WE43 V1 WE38 WE44 WE36 WE40 Last Valid Address Address V1 WE32 Next Address Figure 22. Asynchronous Memory Read Access CS[x] WE31 ADDR/ M_DATA Addr. V1 WE32A MAXDI D(V1) WE44 WE40 WE39 WE35A OE WE37 BE[y] MAXCO WE38 WE36 WE LBA Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5) i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 40 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 22 through Figure 26, and Table 31 help to determine timing parameters relative chip select (CS) state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing parameters mentioned above. CS[x] WE31 ADDR RW WE39 LBA OE WE45 BE[y] WE42 DATA WE41 D(V1) WE46 WE40 Last Valid Address WE33 Address V1 WE34 WE32 Next Address Figure 24. Asynchronous Memory Write Access CS[x] WE31 ADDR/ M_DATA WE33 RW WE40A LBA OE WE45 BE[y] WE42 WE46 WE39 Addr. V1 WE32A WE34 WE41 D(V1) WE42 Figure 25. Asynchronous A/D Mux Write Access i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 41 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. CS [x] WE31 ADDR RW WE39 LBA WE35 OE WE37 EB[y] DATA WE43 WE48 DATA WE47 V1 WE38 WE44 WE36 WE40 Last Valid Address Address V1 WE32 Next Address Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 26. DTACK Read Access Table 31. WEIM Asynchronous Timing Parameters Relative Chip Select Table Determination By Synchronous Measured Parameters1 Max (If 133 MHz is supported by SoC) Ref No. Parameter Min Unit WE31 WE32 WE32A( muxed A/D WE33 WE34 WE35 WE35A (muxed A/D) WE36 WE37 WE38 WE39 WE40 CS[x] valid to Address valid Address invalid to CS[x] invalid CS[x] valid to address invalid WE4 – WE6 – CSA2 WE7 – WE5 – CSN3 — — 3 – CSA 3 – CSN — ns ns ns WE4 – WE7 + (LBN + LBA + 1 –3 + (LBN + LBA + – CSA2) 1 – CSA) WE8 – WE6 + (WEA – CSA) WE7 – WE9 + (WEN – CSN) WE10 – WE6 + (OEA – CSA) WE10 – WE6 + (OEA + RLBN + RLBA + ADH + 1 – CSA) WE7 – WE11 + (OEN – CSN) — — — –3 + (OEA + RLBN + RLBA + ADH + 1 – CSA) — — — — — CS[x] valid to WE valid WE invalid to CS[x] invalid CS[x] valid to OE valid CS[x] valid to OE valid 3 + (WEA – CSA) 3 – (WEN_CSN) 3 + (OEA – CSA) 3 + (OEA + RLBN + RLBA + ADH + 1 – CSA) 3 – (OEN – CSN) 3 + (RBEA4 – CSA) 3 – (RBEN5 – CSN) 3 + (LBA – CSA) 3 – CSN ns ns ns ns OE invalid to CS[x] invalid ns ns ns ns ns CS[x] valid to BE[y] valid (read WE12 – WE6 + (RBEA – CSA) access) BE[y] invalid to CS[x] invalid (read access) CS[x] valid to LBA valid LBA invalid to CS[x] invalid WE7 – WE13 + (RBEN – CSN) WE14 – WE6 + (LBA – CSA) WE7 – WE15 – CSN i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 42 Freescale Semiconductor Table 31. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Determination By Synchronous Measured Parameters1 Max (If 133 MHz is supported by SoC) Ref No. Parameter Min Unit WE40A (muxed A/D) WE41 CS[x] valid to LBA invalid WE14 – WE6 + (LBN + LBA + 1 –3 + (LBN + LBA + 3 + (LBN + LBA + 1 – – CSA) 1 – CSA) CSA) WE16 – WE6 – WCSA WE16 – WE6 + (WLBN + WLBA + ADH + 1 – WCSA) WE17 – WE7 – CSN — — 3 – WCSA 3 + (WLBN + WLBA + ADH + 1 – WCSA) 3 – CSN — ns CS[x] valid to Output Data valid ns ns WE41A CS[x] valid to Output Data valid (muxed A/D) WE42 WE43 Output Data invalid to CS[x] Invalid — MAXCO6 – MAXCSO7 + MAXDI8 0 — — MAXCO6 – MAXCSO7 + MAXDTI9 0 ns ns Input Data valid to CS[x] invalid MAXCO – MAXCSO + MAXDI WE44 WE45 WE46 WE47 CS[x] invalid to Input Data invalid 0 — 3 + (WBEA – CSA) –3 + (WBEN – CSN) — ns ns ns ns CS[x] valid to BE[y] valid (write WE12 – WE6 + (WBEA – CSA) access) BE[y] invalid to CS[x] invalid (write access) DTACK valid to CS[x] invalid WE7 – WE13 + (WBEN – CSN) MAXCO – MAXCSO + MAXDTI WE48 1 2 CS[x] Invalid to DTACK invalid 0 — ns For the value of parameters WE4–WE21, see column BCD = 0 in Table 30. CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles. 3 CS Negation. This bit field determines when the CS signal is negated during read/write cycles. 4 BE Assertion. This bit field determines when the BE signal is asserted during read cycles. 5 BE Negation. This bit field determines when the BE signal is negated during read cycles. 6 Output maximum delay from internal driving ADDR/control FFs to chip outputs. 7 Output maximum delay from CS[x] internal driving FFs to CS[x] out. 8 DATA maximum delay from chip input data to its internal FF. 9 DTACK maximum delay from chip dtack input to its internal FF. Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 43 4.9.5.3 ESDCTL Electrical Specifications Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 27 through Figure 36 depict the timings pertaining to the ESDCTL module, which interfaces with mobile DDR or SDR SDRAM. Table 32 through Table 41 list the timing parameters. SD1 SDCLK SDCLK SD4 CS SD5 RAS SD4 SD2 SD3 SD5 CAS SD4 SD4 SD5 WE SD6 SD7 ADDR ROW/BA SD5 COL/BA SD8 SD10 SD9 Data DQ DQM SD4 Note: CKE is high during the read/write cycle. SD5 Figure 27. SDRAM Read Cycle Timing Diagram Table 32. DDR/SDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD1 SD2 SD3 SD4 SD5 SD6 SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address setup time tCH tCL tCK tCMS tCMH tAS 3.4 3.4 7.0 2.0 1.8 2.0 4.1 4.1 — — — — ns ns ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 44 Freescale Semiconductor Table 32. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID Parameter Symbol Min. Max. Unit SD7 SD8 SD9 SD10 1 Address hold time SDRAM access time Data out hold time1 Active to read/write command period tAH tAC tOH tRC 1.8 — 1.2 10 — 6.47 — — ns ns ns clock Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 40 and Table 41. NOTE SDR SDRAM CLK parameters are measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 32 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 45 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD4 CAS SD5 SD4 SD4 WE SD5 SD7 SD6 ADDR BA ROW / BA SD13 DQ DATA COL/BA SD5 SD14 DQM Figure 28. SDR SDRAM Write Cycle Timing Diagram Table 33. SDR SDRAM Write Timing Parameters ID Parameter Symbol Min. Max. Unit SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD13 SD14 SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address setup time Address hold time Data setup time Data hold time tCH tCL tCK tCMS tCMH tAS tAH tDS tDH 0.45 0.45 7.0 2.4 1.4 2.4 1.4 2.4 1.4 0.55 0.55 — — — — — — — ns ns ns ns ns ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 46 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. SDR SDRAM CLK parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value, and “low” is defined as 50% of signal value. tCH + tCL will not exceed 7.5 ns for 133 MHz. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock). The timing parameters are similar to the ones used in SDRAM data sheets. Table 33 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. SD1 SDCLK SDCLK SD2 SD3 CS RAS SD11 CAS SD10 WE SD10 SD7 SD6 ADDR BA ROW/BA Figure 29. SDRAM Refresh Timing Diagram Table 34. SDRAM Refresh Timing Parameters ID Parameter Symbol Min. Max. Unit SD1 SD2 SD3 SD6 SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time tCH tCL tCK tAS 3.4 3.4 7.5 1.8 4.1 4.1 — — ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 47 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. NOTE Test conditions are: pin voltage 1.7 V–1.95 V, capacitance 15 pF for all pins (both DDR and non-DDR pins), drive strength is high (7.2 mA). “High” is defined as 80% of signal value and “low” is defined as 20% of signal value. Table 34. SDRAM Refresh Timing Parameters (continued) ID Parameter Symbol Min. Max. Unit SD7 SD10 SD11 1 Address hold time Precharge cycle period1 Auto precharge command period1 tAH tRP tRC 1.8 1 2 — 4 20 ns clock clock SD10 and SD11 are determined by SDRAM controller register settings. NOTE SDR SDRAM CLK parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value and “low” is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets. Table 34 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. SDCLK CS RAS CAS WE ADDR BA CKE SD16 SD16 Don’t care Figure 30. SDRAM Self-Refresh Cycle Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 48 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 35. SDRAM Self-Refresh Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD16 CKE output delay time tCKS 1.8 — ns DDR1 SDCLK SDCLK DDR4 CS DDR2 DDR3 DDR4 RAS DDR5 DDR5 DDR4 CAS DDR4 DDR5 WE DDR5 CKE DDR6 ADDR ROW/BA DDR4 DDR7 COL/BA Figure 31. DDR2 SDRAM Basic Timing Parameters Table 36. DDR2 SDRAM Timing Parameter Table DDR2-400 ID PARAMETER Symbol Min Max Unit DDR1 DDR2 DDR3 DDR4 SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, CKE, WE setup time tCH tCL tCK tIS1 0.45 0.45 7.0 0.35 0.55 0.55 8.0 — tCK tCK ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 49 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. NOTE The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. Table 36. DDR2 SDRAM Timing Parameter Table DDR2-400 ID PARAMETER Symbol Min Max Unit DDR5 DDR6 DDR7 CS, RAS, CAS, CKE, WE hold time Address output setup time Address output hold time tIH1 tIS1 tIH1 0.475 0.35 0.475 — — — ns ns ns NOTE These values are for command/address slew rate of 1 V/ns and SDCLK, SDCLK_B differential slew rate of 2 V/ns. For different values, use the derating table. Table 37. Derating Values for DDR2–400, DDR2–533 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 50 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. SDCLK_B DDR21 DDR22 DDR18 Data Data DQS (output) DDR17 DDR17 Data DDR23 DDR18 DDR20 DDR19 DQ (output) DQM (output) DDR17 Data Data Data Data Data DM DM DM DM DM DM DM DM DDR18 DDR17 DDR18 Figure 32. DDR2 SDRAM Write Cycle Timing Diagram Figure 33. DDR2 SDRAM Write Cycle Parameters DDR2-400 ID PARAMETER Symbol Min Max Unit DDR17 DQ and DQM setup time to DQS (single-ended strobe) DDR18 DQ and DQM hold time to DQS (single-ended strobe) DDR19 Write cycle DQS falling edge to SDCLK output setup time. DDR20 Write cycle DQS falling edge to SDCLK output hold time. DDR21 DQS latching rising transitions to associated clock edges DDR22 DQS high level width DDR23 DQS low level width tDS1(base) tDH1(base) tDSS tDSH tDQSS tDQSH tDQSL 0.025 0.025 0.2 0.2 –0.25 0.35 0.35 — — — — 0.25 — — ns ns tCK tCK tCK tCK tCK NOTE These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of 1 V/ns. For different values use the derating table. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 51 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. SDCLK Table 38. DDR Single-ended Slew Rate Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. NOTE SDR SDRAM CLK parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value and “low” is defined as 50% of signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock). Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strength is Medium for SDCLK and High for Address and controls. SDCLK SDCLK_B DQS (input) DDR26 DDR25 DDR24 DQ (input) DATA DATA DATA DATA DATA DATA DATA DATA Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 52 Freescale Semiconductor Table 39. DDR2 SDRAM Read Cycle Parameter Table Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. DDR2-400 ID PARAMETER Symbol Min Max Unit DDR24 DDR25 DDR26 1 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS). DQS DQ in HOLD time from DQS1 DQS output access time from SDCLK posedge tDQSQ tQH tDQSCK — 2.925 –0.5 0.35 — 0.5 ns ns ns The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS = 0.45 × tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns. NOTE SDRAM CLK and DQS-related parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value and “low” is defined as 50% of signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock). Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strength is Medium for SDCLK and High for Address and controls. SDCLK SDCLK SD19 DQS (output) SD17 DQ (output) Data Data SD20 SD18 SD17 Data Data SD18 Data Data Data Data DQM (output) SD17 DM DM DM SD17 DM DM SD18 DM DM DM SD18 Figure 35. Mobile DDR SDRAM Write Cycle Timing Diagram Table 40. Mobile DDR SDRAM Write Cycle Timing Parameters1 ID Parameter Symbol Min. Max. Unit SD17 SD18 SD19 SD20 1 DQ and DQM setup time to DQS DQ and DQM hold time to DQS Write cycle DQS falling edge to SDCLK output delay time. Write cycle DQS falling edge to SDCLK output hold time. tDS tDH tDSS tDSH 0.95 0.95 1.8 1.8 — — — — ns ns ns ns Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 53 The timing parameters are similar to the ones used in SDRAM data sheets. Table 40 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. SDCLK SDCLK SD23 DQS (input) SD22 SD21 DQ (input) Data Data Data Data Data Data Data Data Figure 36. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 41. Mobile DDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS). SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge tDQSQ tQH tDQSCK — 2.3 — 0.85 — 6.7 ns ns ns NOTE SDRAM CLK and DQS-related parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value, and “low” is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets. Table 41 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 54 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. NOTE SDRAM CLK and DQS-related parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value and “low” is defined as 50% of signal value. 4.9.6 Enhanced Serial Audio Interface (ESAI) Timing Specifications Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 42 shows the interface timing values. The number field in the table refers to timing signals found in Figure 37 and Figure 38. Table 42. Enhanced Serial Audio Interface Timing No. Characteristics1,2 Symbol Expression2 Min. Max. Condition 3 Unit 62 63 Clock cycle4 Clock high period • For internal clock • For external clock tSSICC 4 × Tc 4 × Tc 2 × Tc − 9.0 2 × Tc 2 × Tc − 9.0 2 × Tc — — — — — — — — — — — — — — — — — — — — — — — — — — 30.0 30.0 6 15 6 15 — — — — — — — — — — — — 12.0 19.0 3.5 9.0 2.0 12.0 2.0 12.0 2.5 8.5 — — — — — — — — — — 17.0 7.0 17.0 7.0 19.0 9.0 19.0 9.0 16.0 6.0 17.0 7.0 — — — — — — — — — — 18.0 8.0 20.0 10.0 i ck i ck — — ns ns — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 64 Clock low period • For internal clock • For external clock ns — — x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns 65 66 67 68 69 70 71 72 73 74 75 78 79 SCKR rising edge to FSR out (bl) high SCKR rising edge to FSR out (bl) low SCKR rising edge to FSR out (wr) high5 SCKR rising edge to FSR out (wr) low5 SCKR rising edge to FSR out (wl) high SCKR rising edge to FSR out (wl) low Data in setup time before SCKR (SCK in synchronous mode) falling edge Data in hold time after SCKR falling edge FSR input (bl, wr) high before SCKR falling edge5 FSR input (wl) high before SCKR falling edge FSR input hold time after SCKR falling edge SCKT rising edge to FST out (bl) high SCKT rising edge to FST out (bl) low i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 55 Table 42. Enhanced Serial Audio Interface Timing (continued) No. Characteristics1,2 Symbol Expression2 Min. Max. Condition 3 Unit 80 81 82 83 84 86 87 89 90 91 1 SCKT rising edge to FST out (wr) high5 SCKT rising edge to FST out (wr) low5 SCKT rising edge to FST out (wl) high SCKT rising edge to FST out (wl) low SCKT rising edge to data out enable from high impedance SCKT rising edge to data out valid SCKT rising edge to data out high impedance 67 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 2.0 18.0 2.0 18.0 4.0 5.0 20.0 10.0 22.0 12.0 19.0 9.0 20.0 10.0 22.0 17.0 18.0 13.0 21.0 16.0 — — — — — — x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns FST input (bl, wr) setup time before SCKT falling edge5 FST input (wl) setup time before SCKT falling edge FST input hold time after SCKT falling edge 2 3 4 5 6 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) bl = bit length wl = word length wr = word length relative SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame. Periodically sampled and not 100% tested. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 56 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Freescale Semiconductor FST (Word) Out Data Out FST (Bit) Out FST (Bit) In FST (Word) In 89 78 82 84 79 86 91 90 91 86 First Bit SCKT (Input/Output) 63 62 64 Figure 37. ESAI Transmitter Timing Last Bit 83 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 87 57 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 62 63 SCKR (Input/Output) 65 FSR (Bit) Out 69 FSR (Word) Out 72 71 Data In First Bit 73 FSR (Bit) In 74 FSR (Word) In 75 75 Last Bit 70 64 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 66 Figure 38. ESAI Receiver Timing 4.9.7 eSDHCv2 AC Electrical Specifications Figure 39 depicts the timing of eSDHCv2, and Table 43 lists the eSDHCv2 timing characteristics. The following definitions apply to values and signals described in Table 43: • LS: low-speed mode. Low-speed card can tolerate a clock up to 400 kHz. • FS: full-speed mode. For a full-speed MMC card, the card clock can reach 20 MHz; a full-speed SD/SDIO card can reach 25 MHz. • HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO can reach 50 MHz. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 58 Freescale Semiconductor SD4 SD2 SD5 SD1 SDHCx_CLK SD3 output from eSDHCv2 to card SDHCx_CMD SDHCx_DAT_0 SDHCx_DAT_1 SDHCx_DAT_7 SD7 SDHCx_CMD SDHCx_DAT_0 SDHCx_DAT_1 SDHCx_DAT_7 SD8 SD6 output from card to eSDHCv2 Figure 39. eSDHCv2 Timing Table 43. eSDHCv2 Interface Timing Specification ID Card Input Clock Parameter Symbols Min. Max. Unit SD1 Clock frequency (Low Speed) Clock frequency (SD/SDIO Full Speed/High Speed) Clock frequency (MMC Full Speed/High Speed) Clock frequency (Identification Mode) SD2 Clock Low time SD3 Clock high time SD4 Clock rise time SD5 Clock fall time eSDHC Output/Card Inputs CMD, DAT (Reference to CLK) fPP1 fPP2 fPP3 fOD tWL tWH tTLH tTHL 0 0 0 100 7 7 — — 400 kHz 25/50 MHz 20/52 MHz 400 — — 3 3 kHz ns ns ns ns SD6 eSDHC output delay eSDHC Input/Card Outputs CMD, DAT (Reference to CLK) tOD –3 3 ns SD7 eSDHC input setup time SD8 eSDHC input hold time 1 2 3 4 tISU tIH4 5 2.5 — — ns ns In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal-speed mode for the SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock frequency can be any value between 0–50 MHz. In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock frequency can be any value between 0–52 MHz. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 59 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 4.9.8 Fast Ethernet Controller (FEC) AC Electrical Specifications Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. This section describes the electrical information of the FEC module. The FEC is designed to support both 10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data rate uses seven of the MII pins for connection to an external Ethernet transceiver. 4.9.8.1 FEC AC Timing This section describes the AC timing specifications of the FEC. The MII signals are compatible with transceivers operating at a voltage of 3.3 V. 4.9.8.2 MII Receive Signal Timing The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the FEC_RX_CLK frequency. Table 44 lists MII receive channel timings. Table 44. MII Receive Signal Timing Num. Characteristic1 Min. Max. Unit M1 M2 M3 M4 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold FEC_RX_CLK pulse width high FEC_RX_CLK pulse width low 5 5 35% 35% — — 65% 65% ns ns FEC_RX_CLK period FEC_RX_CLK period 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode. Figure 40 shows the MII receive signal timings listed in Table 44. M3 FEC_RX_CLK (input) M4 FEC_RXD[3:0] (inputs) FEC_RX_DV FEC_RX_ER M1 M2 Figure 40. MII Receive Signal Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 60 Freescale Semiconductor 4.9.8.3 MII Transmit Signal Timing Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the FEC_TX_CLK frequency. Table 45 lists MII transmit channel timings. Table 45. MII Transmit Signal Timing Num Characteristic1 Min. Max. Unit M5 M6 M7 M8 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid FEC_TX_CLK pulse width high FEC_TX_CLK pulse width low 5 — 35% 35% — 20 65% 65% ns ns FEC_TX_CLK period FEC_TX_CLK period 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode. Figure 41 shows the MII transmit signal timings listed in Table 45. M7 FEC_TX_CLK (input) M5 M8 FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER M6 Figure 41. MII Transmit Signal Timing Diagram 4.9.8.4 MII Asynchronous Inputs Signal Timing The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 46 lists MII asynchronous inputs signal timing. Table 46. MII Asynch Inputs Signal Timing Num Characteristic Min. Max. Unit M91 1 FEC_CRS to FEC_COL minimum pulse width 1.5 — FEC_TX_CLK period FEC_COL has the same timing in 10 Mbit 7-wire interface mode. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 61 Figure 42 shows MII asynchronous input timings listed in Table 46. FEC_CRS, FEC_COL M9 Figure 42. MII Asynch Inputs Timing Diagram 4.9.8.5 MII Serial Management Channel Timing Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 47 lists MII serial management channel timings. The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz. Table 47. MII Transmit Signal Timing Num Characteristic Min. Max. Units M10 M11 M12 M13 M14 M15 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) FEC_MDC falling edge to FEC_MDIO output valid (max. propagation delay) FEC_MDIO (input) to FEC_MDC rising edge setup FEC_MDIO (input) to FEC_MDC rising edge hold FEC_MDC pulse width high FEC_MDC pulse width low 0 — 18 0 40% 40% — 5 — — 60% 60% ns ns ns ns FEC_MDC period FEC_MDC period i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 62 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 43 shows MII serial management channel timings listed in Table 47. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. M14 M15 FEC_MDC (output) M10 FEC_MDIO (output) M11 FEC_MDIO (input) M12 M13 Figure 43. MII Serial Management Channel Timing Diagram 4.9.9 FIR Electrical Specifications FIR implements asynchronous infrared protocols (FIR, MIR) defined by IrDA® (Infrared Data Association). Refer to the IrDA® website for details on FIR and MIR protocols. 4.9.10 FlexCAN Module AC Electrical Specifications The electrical characteristics are related to the CAN transceiver outside the chip. The i.MX35 has two CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor Reference Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 63 4.9.11 I2C AC Electrical Specifications Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. This section describes the electrical characteristics of the I2C module. 4.9.11.1 I2C Module Timing Figure 44 depicts the timing of the I2C module. Table 48 lists the I2C module timing parameters. I2DAT IC10 IC11 IC9 I2CLK IC2 IC8 IC4 IC7 IC3 START IC10 IC6 IC1 IC5 IC11 START STOP START Figure 44. I2C Bus Timing Diagram Table 48. I2C Module Timing Parameters Standard Mode ID Parameter Min. Max. Min. Max. Fast Mode Unit IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 I2CLK cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2CLK Clock LOW Period of the I2CLK Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition 10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 — — — — — — 3.452 — — — — — 1000 300 400 2.5 0.6 0.6 01 0.6 1.3 0.6 1003 1.3 — — — — — — 0.92 — — — — — 300 300 400 μs μs μs μs μs μs μs ns μs IC10 Rise time of both I2DAT and I2CLK signals IC11 Fall time of both I2DAT and I2CLK signals IC12 Capacitive load for each bus line (Cb) 1 2 3 ns ns pF A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 64 Freescale Semiconductor 4.9.12 IPU—Sensor Interfaces Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. This section contains a list of supported camera sensors, a functional description, and the electrical characteristics. 4.9.12.1 Supported Camera Sensors Table 49. Supported Camera Sensors1 Vendor Model Table 49 lists the known supported camera sensors at the time of publication. Conexant Agilant Toshiba ICMedia iMagic Transchip Fujitsu Micron Matsushita STMicro OmniVision Sharp Motorola National Semiconductor 1 2 CX11646, CX204902, CX204502 HDCP–2010, ADCS–10212, ADCS–10212 TC90A70 ICM202A, ICM1022 IM8801 TC5600, TC5600J, TC5640, TC5700, TC6000 MB86S02A MI-SOC–0133 MN39980 W6411, W6500, W65012, W66002, W65522, STV09742 OV7620, OV6630, OV2640 LZ0P3714 (CCD) MC30300 (Python)2, SCM200142, SCM201142, SCM221142, SCM200272 LM96182 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. These sensors have not been validated at the time of publication. 4.9.12.2 Functional Description There are three timing modes supported by the IPU. 4.9.12.2.1 Pseudo BT.656 Video Mode Smart camera sensors, which typically include image processing capability, support video mode transfer operations. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656 standard. This operation mode follows the recommendations of the ITU BT.656 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with an EAV code. In some cases, digital blanking is i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 65 inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. 4.9.12.2.2 Gated Clock Mode Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 45. Start of Frame nth frame Active Line n+1th frame SENSB_VSYNC SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[9:0] invalid invalid 1st byte 1st byte Figure 45. Gated Clock Mode Timing Diagram A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame, the SENSB_VSYNC timing repeats. 4.9.12.2.3 Non-Gated Clock Mode The timing is the same as the gated-clock mode (described in Section 4.9.12.2.2, “Gated Clock Mode”), except for the SENSB_HSYNC signal, which is not used. See Figure 46. All incoming pixel clocks are valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus. Start of Frame nth frame n+1th frame SENSB_VSYNC SENSB_PIX_CLK SENSB_DATA[7:0] invalid invalid 1st byte 1st byte Figure 46. Non-Gated Clock Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 66 Freescale Semiconductor 4.9.12.3 Electrical Characteristics Figure 47 depicts the sensor interface timing, and Table 50 lists the timing parameters. 1/IP1 SENSB_MCLK (Sensor Input) SENSB_PIX_CLK (Sensor Output) IP3 SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC IP2 1/IP4 Figure 47. Sensor Interface Timing Diagram Table 50. Sensor Interface Timing Parameters ID Parameter Symbol Min. Max. Units IP1 IP2 IP3 IP4 Sensor input clock frequency Data and control setup time Data and control holdup time Sensor output (pixel) clock frequency Fmck Tsu Thd Fpck 0.01 5 3 0.01 133 — — 133 MHz ns ns MHz 4.9.13 IPU—Display Interfaces This section describes the following types of display interfaces: • Section 4.9.13.1, “Synchronous Interfaces” • Section 4.9.13.2, “Interface to Sharp HR-TFT Panels” • Section 4.9.13.3, “Synchronous Interface to Dual-Port Smart Displays” • Section 4.9.13.4, “Asynchronous Interfaces” • Section 4.9.13.5, “Serial Interfaces, Functional Description” i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 67 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The timing described in Figure 46 is that of a Motorola sensor. Some other sensors may have slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK. 4.9.13.1 Synchronous Interfaces Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart displays. 4.9.13.1.4 Interface to Active Matrix TFT LCD Panels, Functional Description Figure 48 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure, signals are shown with negative polarity. The sequence of events for active matrix interface timing is as follows: • DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, DISPB_D3_CLK runs continuously. • DISPB_D3_HSYNC causes the panel to start a new line. • DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. • DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted to the display. When disabled, the data is invalid and the trace is off. DISPB_D3_VSYNC DISPB_D3_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n – 1 LINE n DISPB_D3_HSYNC DISPB_D3_DRDY 1 DISPB_D3_CLK DISPB_D3_DATA 2 3 m–1 m Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels 4.9.13.1.5 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics Figure 49 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 68 Freescale Semiconductor of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals. IP7 IP9 IP8 Start of line IP5 IP6 IP10 DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_DATA Figure 49. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 50 depicts the vertical timing (timing of one frame). All figure parameters shown are programmable. Start of frame IP13 DISPB_D3_VSYNC End of frame DISPB_D3_HSYNC DISPB_D3_DRDY IP11 IP14 IP12 IP15 Figure 50. TFT Panels Timing Diagram—Vertical Sync Pulse Table 51 shows timing parameters of signals presented in Figure 49 and Figure 50. Table 51. Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter Symbol Value Units IP5 IP6 IP7 IP8 Display interface clock period Display pixel clock period Screen width HSYNC width Tdicp Tdpcp Tsw Thsw Tdicp1 (DISP3_IF_CLK_CNT_D + 1) × Tdicp (SCREEN_WIDTH + 1) × Tdpcp (H_SYNC_WIDTH + 1) × Tdpcp ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 69 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 51. Synchronous Display Interface Timing Parameters—Pixel Level (continued) ID Parameter Symbol Value Units IP9 IP10 IP11 IP12 IP13 Horizontal blank interval 1 Horizontal blank interval 2 HSYNC delay Screen height VSYNC width Thbi1 Thbi2 Thsd Tsh Tvsw BGXP × Tdpcp (SCREEN_WIDTH – BGXP – FW) × Tdpcp H_SYNC_DELAY × Tdpcp (SCREEN_HEIGHT + 1) × Tsw if V_SYNC_WIDTH_L = 0 than (V_SYNC_WIDTH + 1) × Tdpcp else (V_SYNC_WIDTH + 1) × Tsw BGYP × Tsw (SCREEN_HEIGHT – BGYP – FH) × Tsw ns ns ns ns ns IP14 IP15 1 Vertical blank interval 1 Vertical blank interval 2 Tvbi1 Tvbi2 ns ns Display interface clock period immediate value Display interface clock period average value. DISP3_IF_CLK_PER_WR Tdicp = T HSP_CLK ⋅ ----------------------------------------------------------------HSP_CLK_PERIOD Figure 51 depicts the synchronous display interface timing for access level, and Table 52 lists the timing parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the DI_DISP3_TIME_CONF Register. DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY other controls DISPB_D3_CLK IP20 IP16 DISPB_DATA IP17 IP19 IP18 Figure 51. Synchronous Display Interface Timing Diagram—Access Level i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 70 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 52. Synchronous Display Interface Timing Parameters—Access Level Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID Parameter Symbol Min. Typ.1 Max. Units IP16 Display interface clock low time IP17 Display interface clock high time IP18 Data setup time IP19 Data holdup time IP20 Control signals setup time to display interface clock 1 2 Tckl Tckh Tdsu Tdhd Tcsu Tdicd – Tdicu – 1.5 Tdicp – Tdicd + Tdicu – 1.5 Tdicd – 3.5 Tdicp – Tdicd – 3.5 Tdicd – 3.5 Tdicd2 – Tdicu3 Tdicp – Tdicd + Tdicu Tdicu Tdicp – Tdicu Tdicu Tdicd – Tdicu + 1.5 Tdicp – Tdicd + Tdicu + 1.5 — — — ns ns ns ns ns The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. Display interface clock down time 2 ⋅ DISP3_IF_CLK_DOWN_WR 1 Tdicd = -- T HSP_CLK ⋅ ceil -------------------------------------------------------------------------------HSP_CLK_PERIOD 2 3 Display interface clock up time 2 ⋅ DISP3_IF_CLK_UP_WR 1 ⋅ ceil --------------------------------------------------------------------Tdicu = -- T HSP_CLK_PERIOD 2 HSP_CLK where CEIL(X) rounds the elements of X to the nearest integers toward infinity. 4.9.13.2 Interface to Sharp HR-TFT Panels Figure 52 depicts the Sharp HR-TFT panel interface timing, and Table 53 lists the timing parameters. The CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY, REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 71 Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing images correspond to straight polarity of the Sharp signals. Horizontal timing DISPB_D3_CLK DISPB_D3_DATA D1 D2 D320 DISPB_D3_SPL IP21 1 DISPB_D3_CLK period DISPB_D3_HSYNC IP23 IP22 DISPB_D3_CLS IP24 DISPB_D3_PS IP25 IP26 DISPB_D3_REV Example is drawn with FW + 1 = 320 pixel/line, FH + 1 = 240 lines. SPL pulse width is fixed and aligned to the first data of the line. REV toggles every HSYNC period. Figure 52. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level Table 53. Sharp Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter Symbol Value Units IP21 IP22 IP23 IP24 IP25 IP26 SPL rise time CLS rise time CLS fall time CLS rise and PS fall time PS rise time REV toggle time Tsplr Tclsr Tclsf Tpsf Tpsr Trev (BGXP – 1) × Tdpcp CLS_RISE_DELAY × Tdpcp CLS_FALL_DELAY × Tdpcp PS_FALL_DELAY × Tdpcp PS_RISE_DELAY × Tdpcp REV_TOGGLE_DELAY × Tdpcp ns ns ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 72 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 4.9.13.3 Synchronous Interface to Dual-Port Smart Displays Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are identical to parameters of the synchronous interface. See Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” 4.9.13.3.6 Interface to a TV Encoder—Functional Description The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 53 depicts the interface timing. • The frequency of the clock DISPB_D3_CLK is 27 MHz. • The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low. • The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It remains low for a single clock cycle. • The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC signal. It remains low for at least one clock cycle. — At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide. — At a transition to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 73 DISPB_D3_CLK D ISPB_DATA Cb Y Cr Y Cb Y Cr Pixel Data Timing DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 523 524 525 1 2 3 4 5 6 10 Even Field 261 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 262 263 264 265 266 267 Odd Field 268 269 273 Odd Field Even Field Line and Field Timing - NTSC DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 621 622 623 624 625 1 2 3 4 23 Odd Field 308 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC 309 310 311 312 313 314 315 316 336 Odd Field Line and Field Timing - PAL Even Field Figure 53. TV Encoder Interface Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 74 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. DISPB_D3_HSYNC DISPB_D3_VSYNC DISPB_D3_DRDY 4.9.13.3.7 Interface to a TV Encoder, Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The timing characteristics of the TV encoder interface are identical to the synchronous display characteristics. See Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” 4.9.13.4 Asynchronous Interfaces This section discusses the asynchronous parallel and serial interfaces. 4.9.13.4.8 Parallel Interfaces, Functional Description The IPU supports the following asynchronous parallel interfaces: • System 80 interface — Type 1 (sampling with the chip select signal) with and without byte enable signals. — Type 2 (sampling with the read and write signals) with and without byte enable signals. • System 68k interface — Type 1 (sampling with the chip select signal) with or without byte enable signals. — Type 2 (sampling with the read and write signals) with or without byte enable signals. For each of four system interfaces, there are three burst modes: 1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters of the IDMAC (when data is transferred from the system memory) or by the HBURST signal (when the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type 1 interfaces, data is sampled by the CS signal and other control signals change only when transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals (system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during the whole burst. 2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. The CS signals and other controls move to non-active state after burst has been completed. 3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The data is sampled with CS or other controls according to the interface type as described above. All controls (including CS) become non-active for one display interface clock after each access. This mode corresponds to the ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 54, Figure 55, Figure 56, and Figure 57. These timing images correspond to active-low DISPB_Dn_CS, DISPB_Dn_WR and DISPB_Dn_RD signals. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 75 DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 76 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles. DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by WR/RD signals DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 77 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) D ISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 78 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by ENABLE signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram Display read operation can be performed with wait states when each read access takes up to 4 display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 79 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. DI_DISPn_TIME_CONF_3 registers (n = 0,1,2). Figure 58 shows the timing of the parallel interface with read wait states. WRITE OPERATION DISP0_RD_WAIT_ST=00 READ OPERATION DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=01 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=10 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA Figure 58. Parallel Interface Timing Diagram—Read Wait States 4.9.13.4.9 Parallel Interfaces, Electrical Characteristics Figure 59, Figure 61, Figure 60, and Figure 62 depict timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 54 lists the timing parameters at display access level. All i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 80 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. timing images are based on active low control signals (signal polarity is controlled via the DI_DISP_SIG_POL register). IP28, IP27 DISPB_PAR_RS DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) IP35, IP33 DISPB_D#_CS IP36, IP34 DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 read point IP37 DISPB_DATA (Input) Read Data IP38 IP32, IP30 IP39 DISPB_DATA (Output) IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 81 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35, IP33 DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38 IP36, IP34 IP32, IP30 IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 82 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. IP28, IP27 DISPB_PAR_RS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) IP35,IP33 DISPB_D#_CS IP36, IP34 DISPB_WR (READ/WRITE) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38 IP32, IP30 IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 83 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35,IP33 DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_WR (READ/WRITE) IP31, IP29 read point IP37 DISPB_DATA (Input) IP39 DISPB_DATA (Output) Read Data IP38 IP36, IP34 IP32, IP30 IP40 IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 62. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 54. Asynchronous Parallel Interface Timing Parameters—Access Level ID Parameter Symbol Min. Typ.1 Max. Units IP27 Read system cycle time IP28 Write system cycle time IP29 Read low pulse width IP30 Read high pulse width IP31 Write low pulse width IP32 Write high pulse width IP33 Controls setup time for read IP34 Controls hold time for read Tcycr Tcycw Trl Trh Twl Twh Tdcsr Tdchr Tdicpr – 1.5 Tdicpw – 1.5 Tdicdr – Tdicur – 1.5 Tdicpr – Tdicdr + Tdicur – 1.5 Tdicdw – Tdicuw – 1.5 Tdicpw – Tdicdw + Tdicuw – 1.5 Tdicur – 1.5 Tdicpr – Tdicdr – 1.5 Tdicpr2 Tdicpw 3 Tdicpr + 1.5 Tdicpw + 1.5 Tdicur5 Tdicdr – Tdicur + 1.5 ns ns ns ns ns ns ns ns Tdicdr – 4 Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur Tdicur + 1.5 Tdicdw6 – Tdicuw7 Tdicdw – Tdicuw + 1.5 Tdicpw – Tdicdw Tdicpw – Tdicdw + + Tdicuw Tdicuw + 1.5 Tdicur Tdicpr – Tdicdr — — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 84 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 54. Asynchronous Parallel Interface Timing Parameters—Access Level (continued) ID Parameter Symbol Min. Typ.1 Max. Units IP35 Controls setup time for write IP36 Controls hold time for write IP37 Slave device data delay8 IP38 Slave device data hold time8 IP39 Write data setup time IP40 Write data hold time IP41 Read period2 Tdcsw Tdchw Tracc Troh Tds Tdh Tdicpr Tdicuw – 1.5 Tdicpw – Tdicdw – 1.5 0 Tdrp – Tlbd – Tdicdr + 1.5 Tdicdw – 1.5 Tdicpw – Tdicdw – 1.5 Tdicpr – 1.5 Tdicuw Tdicpw – Tdicdw — — Tdicdw Tdicpw – Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp — — Tdrp9 – Tlbd10 – Tdicur – 1.5 Tdicpr – Tdicdr – 1.5 — — Tdicpr + 1.5 Tdicpw + 1.5 Tdicdr + 1.5 Tdicur + 1.5 Tdicdw + 1.5 Tdicuw + 1.5 Tdrp + 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns IP42 Write period3 IP43 Read down time4 IP44 Read up time IP45 Write down 5 Tdicpw Tdicpw – 1.5 Tdicdr Tdicur Tdicdr – 1.5 Tdicur – 1.5 time6 7 Tdicdw Tdicdw – 1.5 Tdicuw Tdicuw – 1.5 Tdrp Tdrp – 1.5 IP46 Write up time IP47 Read time point9 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device-specific. 2 Display interface clock period value for read: DISP#_IF_CLK_PER_RD Tdicpr = T HSP_CLK ⋅ cei l --------------------------------------------------------------HSP_CLK_PERIOD 3 Display interface clock period value for write: DISP#_IF_CLK_PER_WR Tdicpw = THSP_CLK ⋅ ceil ----------------------------------------------------------------HSP_CLK_PERIOD 4 Display interface clock down time for read: 2 ⋅ DISP#_IF_CLK_DOWN_RD 1 ⋅ cei l ------------------------------------------------------------------------------Tdicdr = -- T HSP_CLK_PERIOD 2 HSP_CLK 5 Display interface clock up time for read: 2 ⋅ DISP#_IF_CLK_UP_RD 1 ⋅ ce il -------------------------------------------------------------------Tdicur = -- T HSP_CLK_PERIOD 2 HSP_CLK 6 Display interface clock down time for write: 1 2 ⋅ DISP#_IF_CLK_DOWN_WR Tdicdw = -- T HSP_CLK ⋅ ceil -------------------------------------------------------------------------------2 HSP_CLK_PERIOD 7 Display interface clock up time for write: 1 2 ⋅ DISP#_IF_CLK_UP_WR Tdi cuw = -- T ⋅ cei l --------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD 8 This parameter is a requirement to the display connected to the IPU i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 85 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 9 Data read point Tdrp = T HSP_CLK DISP#_READ_EN ⋅ ceil -------------------------------------------------HSP_CLK_PERIOD 10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device – level output delay, board delays, a device – level input delay, an IPU input delay. This value is device specific. The following parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers: • DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD • HSP_CLK_PERIOD • DISP#_IF_CLK_DOWN_WR • DISP#_IF_CLK_UP_WR • DISP#_IF_CLK_DOWN_RD • DISP#_IF_CLK_UP_RD • DISP#_READ_EN 4.9.13.5 Serial Interfaces, Functional Description The IPU supports the following types of asynchronous serial interfaces: • 3-wire (with bidirectional data line) • 4-wire (with separate data input and output lines) • 5-wire type 1 (with sampling RS by the serial clock) • 5-wire type 2 (with sampling RS by the chip select signal) Figure 63 depicts timing of the 3-wire serial interface. The timing images correspond to active-low DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal. For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux connects the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. Each data transfer can be preceded by an optional preamble with programmable length and contents. The preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word or of a whole burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers (n = 1, 2). i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 86 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0 Preamble Input or output data Figure 63. 3-Wire Serial Interface Timing Diagram Figure 64 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the device. Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) RW RS D7 D6 D5 D4 D3 D2 D1 D0 Output data Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 Input data Figure 64. 4-Wire Serial Interface Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 87 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) DISPB_SER_RS RW D7 D6 D5 D4 D3 D2 D1 D0 Output data Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW Input data DISPB_SER_RS Figure 65. 5-Wire Serial Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 88 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 65 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is added. When a burst is transmitted within a single active chip select interval, the RS can be changed at boundaries of words. Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 D4 D3 D2 D1 D0 Preamble DISPB_SD_D (Input) 1 display IF clock cycle Output data DISPB_SER_RS Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW DISPB_SER_RS 1 display IF clock cycle Input data Figure 66. 5-Wire Serial Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 89 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 66 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is added. When a burst is transmitted within a single active chip select interval, the RS can be changed at boundaries of words. 4.9.13.5.10 Serial Interfaces, Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 67 depicts timing of the serial interface. Table 55 lists the timing parameters at display access level. IP49, IP48 DISPB_SER_RS IP56,IP54 IP57, IP55 DISPB_SD_D_CLK IP50, IP52 read point IP58 DISPB_DATA (Input) IP60 DISPB_DATA (Output) Read Data IP59 IP51, IP53 IP61 IP67,IP65 IP47 IP64, IP66 IP62, IP63 Figure 67. Asynchronous Serial Interface Timing Diagram Table 55. Asynchronous Serial Interface Timing Parameters—Access Level ID Parameter Symbol Min. Typ.1 Max. Units IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width IP51 Read clock high pulse width IP52 Write clock low pulse width IP53 Write clock high pulse width IP54 Controls setup time for read Tcycr Tcycw Trl Trh Twl Twh Tdcsr Tdicpr – 1.5 Tdicpw – 1.5 Tdicdr – Tdicur – 1.5 Tdicpr – Tdicdr + Tdicur – 1.5 Tdicdw – Tdicuw – 1.5 Tdicpw – Tdicdw + Tdicuw – 1.5 Tdicur – 1.5 Tdicpr2 Tdicpw 3 Tdicpr + 1.5 Tdicpw + 1.5 ns ns ns ns ns ns ns Tdicdr4 – Tdicur5 Tdicdr – Tdicur + 1.5 Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur Tdicur + 1.5 Tdicdw6 – Tdicuw7 Tdicdw – Tdicuw + 1.5 Tdicpw – Tdicdw Tdicpw – Tdicdw + + Tdicuw Tdicuw + 1.5 Tdicur — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 90 Freescale Semiconductor Table 55. Asynchronous Serial Interface Timing Parameters—Access Level (continued) ID Parameter Symbol Min. Typ.1 Max. Units IP55 Controls hold time for read IP56 Controls setup time for write IP57 Controls hold time for write IP58 Slave device data delay 8 Tdchr Tdcsw Tdchw Tracc Troh Tds Tdh Tdicpr Tdicpr – Tdicdr – 1.5 Tdicuw – 1.5 Tdicpw – Tdicdw – 1.5 0 Tdrp – Tlbd – Tdicdr + 1.5 Tdicdw – 1.5 Tdicpw – Tdicdw – 1.5 Tdicpr – 1.5 Tdicpr – Tdicdr Tdicuw Tdicpw – Tdicdw — — Tdicdw Tdicpw – Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp Tdrp9 – 1.5 – — — — Tlbd10 – Tdicur ns ns ns ns ns ns ns ns ns ns ns ns ns ns IP59 Slave device data hold time8 IP60 Write data setup time IP61 Write data hold time IP62 Read period2 IP63 Write period3 IP64 Read down time IP65 Read up time5 6 4 Tdicpr – Tdicdr – 1.5 — — Tdicpr + 1.5 Tdicpw + 1.5 Tdicdr + 1.5 Tdicur + 1.5 Tdicdw + 1.5 Tdicuw + 1.5 Tdrp + 1.5 Tdicpw Tdicpw – 1.5 Tdicdr Tdicur Tdicdr – 1.5 Tdicur – 1.5 IP66 Write down time IP67 Write up time7 IP68 Read time point 1 2 Tdicdw Tdicdw – 1.5 Tdicuw Tdicuw – 1.5 9 Tdrp Tdrp – 1.5 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. Display interface clock period value for read: Tdicpr = T HSP_CLK DISP#_IF_CLK_PER_RD ⋅ c eil --------------------------------------------------------------HSP_CLK_PERIOD 3 Display interface clock period value for write: Tdi cpw = T HSP_CLK DISP#_IF_CLK_PER_WR ⋅ ce il ----------------------------------------------------------------HSP_CLK_PERIOD 4 Display interface clock down time for read: 1 2 ⋅ DISP#_IF_CLK_DOWN_RD Tdicdr = -- T HSP_CLK ⋅ cei l ------------------------------------------------------------------------------2 HSP_CLK_PERIOD 5 Display interface clock up time for read: 1 2 ⋅ DISP#_IF_CLK_UP_RD Tdi cur = -- T HSP_CLK ⋅ cei l -------------------------------------------------------------------2 HSP_CLK_PERIOD 6 Display interface clock down time for write: 1 2 ⋅ DISP#_IF_CLK_DOWN_WR Tdi cdw = -- T HSP_CLK ⋅ cei l -------------------------------------------------------------------------------2 HSP_CLK_PERIOD 7 Display interface clock up time for write: 1 2 ⋅ DISP#_IF_CLK_UP_WR Tdi cuw = -- T ⋅ ce il --------------------------------------------------------------------2 HSP_CLK HSP_CLK_PERIOD 8 This parameter is a requirement to the display connected to the IPU. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 91 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 9 Data read point: HSP_CLK DISP#_READ_EN ⋅ cei l ------------------------------------------------HSP_CLK_PERIOD 10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, and an IPU input delay. This value is device specific. The following parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers: • DISP#_IF_CLK_PER_WR • DISP#_IF_CLK_PER_RD • HSP_CLK_PERIOD • DISP#_IF_CLK_DOWN_WR • DISP#_IF_CLK_UP_WR • DISP#_IF_CLK_DOWN_RD • DISP#_IF_CLK_UP_RD • DISP#_READ_EN 4.9.14 Memory Stick Host Controller (MSHC) Figure 68, Figure 69, and Figure 70 depict the MSHC timings, and Table 56 and Table 57 list the timing parameters. tSCLKc tSCLKwh tSCLKwl MSHC_SCLK tSCLKr tSCLKf Figure 68. MSHC_CLK Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 92 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Tdrp = T Freescale Semiconductor MSHC_BS MSHC_DATA (Output) MSHC_SCLK MSHC_DATA tBSsu tDsu tDd tDh (Intput) tSCLKc Figure 69. Transfer Operation Timing Diagram (Serial) tBSh i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 93 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. tSCLKc MSHC_SCLK tBSsu tBSh MSHC_BS tDsu MSHC_DATA (Output) tDh tDd MSHC_DATA (Input) Figure 70. Transfer Operation Timing Diagram (Parallel) NOTE The memory stick host controller is designed to meet the timing requirements per Sony's Memory Stick Pro Format Specifications. Tables in this section detail the specifications’ requirements for parallel and serial modes, and not the i.MX35 timing. Table 56. Serial Interface Timing Parameters1 Standards Signal Parameter Symbol Min. Max. Unit MSHC_SCLK Cycle H pulse length L pulse length Rise time Fall time tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu tBSh 50 15 15 — — 5 5 — — — 10 10 — — ns ns ns ns ns ns ns MSHC_BS Setup time Hold time i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 94 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 56. Serial Interface Timing Parameters1 (continued) Standards Signal Parameter Symbol Min. Max. Unit MSHC_DATA Setup time Hold time Output delay time tDsu tDh tDd 5 5 — — — 15 ns ns ns 1 Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC restrictions described in Table 57. Table 57. Parallel Interface Timing Parameters1 Standards Signal Parameter Symbol Min. Max. Unit MSHC_SCLK Cycle H pulse length L pulse length Rise time Fall time tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu tBSh tDsu tDh tDd 25 5 5 — — 8 1 8 1 — — — — 10 10 — — — — 15 ns ns ns ns ns ns ns ns ns ns MSHC_BS Setup time Hold time MSHC_DATA Setup time Hold time Output delay time 1 Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See the NVCC restrictions described in Table 7. 4.9.15 MediaLB Controller Electrical Specifications Table 58. MLB 256/512 Fs Timing Parameters Parameter Symbol Min Typ Max Units Comment This section describes the electrical information of the MediaLB Controller module. MLBCLK operating frequency1 fmck 11.264 12.288 24.576 24.6272 25.600 MHz Min: 256 × Fs at 44.0 kHz Typ: 256 × Fs at 48.0 kHz Typ: 512 × Fs at 48.0 kHz Max: 512 × Fs at 48.1 kHz Max: 512 × Fs PLL unlocked VIL TO VIH MLBCLK rise time tmckr — — 3 ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 95 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 58. MLB 256/512 Fs Timing Parameters (continued) Parameter Symbol Min Typ Max Units Comment MLB fall time MLBCLK cycle time MLBCLK low time tmckf tmckc tmckl — — — 31.5 30 14.5 14 — 81 40 37 35.5 17 16.5 38 36.5 17 16.5 — — — — — 3 — — — — — — — — — — 2 — — tmckl — ns ns ns ns ns ns ns pp ns ns ns ns VIH TO VIL 256 × Fs 512 × Fs 256 × Fs 256 × Fs PLL unlocked 512 × Fs 512 × Fs PLL unlocked 256 × Fs 256 × Fs PLL unlocked 512 × Fs 512 × Fs PLL unlocked Note2 — — — Note3 MLBCLK high time tmckh 31.5 30 14.5 14 MLBCLK pulse width variation MLBSIG/MLBDAT input valid to MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK low MLBSIG/MLBDAT output high impedance from MLBCLK low Bus Hold Time 1 2 3 tmpwv tdsmcf tdhmcf tmcfdz tmdzh — 1 0 0 4 The MLB controller can shut off MLBCLK to place MediaLB in a low-power state. Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp) The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as listed below unless otherwise noted. Table 59. MLB Device 1024Fs Timing Parameters Parameter Symbol Min Typ Max Units Comment MLBCLK Operating Frequency1 fmck 45.056 49.152 49.2544 51.200 MHz Min: 1024 × Fs at 44.0 kHz Typ: 1024 × Fs at 48.0 kHz Max: 1024 × Fs at 48.1 kHz Max: 1024 × Fs PLL unlocked VIL TO VIH VIH TO VIL — PLL unlocked MLBCLK rise time MLB fall time MLBCLK cycle time MLBCLK low time tmckr tmckf tmckc tmckl — — — 6.5 6.1 — — 20.3 7.7 7.3 1 1 — — ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 96 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 59. MLB Device 1024Fs Timing Parameters (continued) Parameter Symbol Min Typ Max Units Comment MLBCLK high time MLBCLK pulse width variation MLBSIG/MLBDAT input valid to MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK low MLBSIG/MLBDAT output high impedance from MLBCLK low Bus Hold Time 1 2 3 tmckh tmpwv tdsmcf tdhmcf tmcfdz tmdzh 9.7 9.3 — 1 0 0 2 10.6 10.2 — — — — — — — 0.7 — — tmckl — ns ns pp ns ns ns ns PLL unlocked Note2 — — — Note3 The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state. Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp) The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. 4.9.16 1-Wire Timing Specifications Figure 71 depicts the RPP timing, and Table 60 lists the RPP timing parameters. 1-WIRE Tx “Reset Pulse” 1-Wire bus (BATT_LINE) DS2502 Tx “Presence Pulse” OW2 OW1 OW3 OW4 Figure 71. Reset and Presence Pulses (RPP) Timing Diagram Table 60. RPP Sequence Delay Comparisons Timing Parameters ID Parameters Symbol Min. Typ. Max. Units OW1 OW2 OW3 OW4 Reset time low Presence detect high Presence detect low Reset time high tRSTL tPDH tPDL tRSTH 480 15 60 480 511 — — 512 — 60 240 — µs µs µs µs i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 97 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 72 depicts write 0 sequence timing, and Table 61 lists the timing parameters. 1-Wire bus (BATT_LINE) OW5 Figure 72. Write 0 Sequence Timing Diagram Table 61. WR0 Sequence Timing Parameters ID Parameter Symbol Min. Typ. Max. Units OW5 OW6 Write 0 low time Transmission time slot tWR0_low tSLOT 60 OW5 100 117 120 120 µs µs Figure 73 shows write 1 sequence timing, and Figure 74 depicts the read sequence timing. Table 62 lists the timing parameters. OW8 1-Wire bus (BATT_LINE) OW7 Figure 73. Write 1 Sequence Timing Diagram OW8 1-Wire bus (BATT_LINE) OW7 OW9 Figure 74. Read Sequence Timing Diagram Table 62. WR1/RD Timing Parameters ID Parameter Symbol Min. Typ. Max. Units OW7 OW8 OW9 Write 1/read low time Transmission time slot Release time tLOW1 tSLOT tRELEASE 1 60 15 5 117 — 15 120 45 µs µs µs 4.9.17 Parallel ATA Module AC Electrical Specifications The parallel ATA module can work on PIO/multiword DMA/ultra-DMA transfer modes. Each transfer mode has a different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MBps. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 98 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. OW6 4.9.17.1 General Timing Requirements Table 63. AC Characteristics of All Interface Signals Table 63 and Figure 75 define the AC characteristics of the interface signals on all data transfer modes. ID Parameter Symbol Min. Max. Unit SI1 SI2 SI3 1 Rising edge slew rate for any signal on the ATA interface1 Falling edge slew rate for any signal on the ATA interface1 Host interface signal capacitance at the host connector Srise1 Sfall1 Chost — — — 1.25 1.25 20 V/ns V/ns pF SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value. ATA Interface Signals SI2 SI1 Figure 75. ATA Interface Signals Timing Diagram 4.9.17.2 ATA Electrical Specifications (ATA Bus, Bus Buffers) This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification. Level shifters are required for 3.3-V or 5.0-V compatibility on the ATA interface. The use of bus buffers introduces delays on the bus and introduces skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. Use of bus buffers is not recommended if fast UDMA mode is required. The ATA specification imposes a slew rate limit on the ATA bus. According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Few vendors of bus buffers specify the slew rate of the outgoing signals. When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention on the host and device tri-state buses is always avoided. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 99 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. The parallel ATA module interface consists of a total of 29 pins. Some pins have different functions in different transfer modes. There are various requirements for timing relationships among the function pins, in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA module registers. 4.9.17.3 Timing Parameters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 64 shows the parameters used in the timing equations. These parameters depend on the implementation of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew. Table 64. ATA Timing Parameters Name Description Value/ Contributing Factor1 T ti_ds Bus clock period (ipg_clk_ata) Set-up time ata_data to ata_iordy edge (UDMA-in only) UDMA0 UDMA1 UDMA2, UDMA3 UDMA4 UDMA5 Peripheral clock frequency 15 ns 10 ns 7 ns 5 ns 4 ns 5.0 ns 4.6 ns 12.0 ns ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only) UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 UDMA5 Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en Set-up time ata_data to bus clock L-to-H Set-up time ata_iordy to bus clock H-to-L Hold time ata_iordy to bus clock H to L tco tsu tsui thi 8.5 ns 8.5 ns 2.5 ns 7 ns tskew1 Maximum difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en tskew2 Maximum difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en tskew3 Maximum difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) tbuf Maximum buffer propagation delay Transceiver Transceiver Transceiver Cable Cable Cable Cable Cable tcable1 Cable propagation delay for ata_data tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack tskew4 Maximum difference in cable propagation delay between ata_iordy and ata_data (read) tskew5 Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) tskew6 Maximum difference in cable propagation delay without accounting for ground bounce 1 Values provided where applicable. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 100 Freescale Semiconductor 4.9.17.4 PIO Mode Timing Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 76 shows timing for PIO read, and Table 65 lists the timing parameters for PIO read. Figure 76. PIO Read Timing Diagram Table 65. PIO Read Timing Parameters ATA Parameter from Parameter Figure 76 Value Controlling Variable t1 t2 t9 t5 t6 tA trd t1 t2r t9 t5 t6 tA trd1 t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5) t2 min.) = time_2r × T – (tskew1 + tskew2 + tskew5) t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6) t5 (min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 0 tA (min.) = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf) trd1 (max.) = (–trd) + (tskew3 + tskew4) trd1 (min.) = (time_pio_rdx – 0.5) × T – (tsu + thi) (time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4 t0 (min.) = (time_1 + time_2 + time_9) × T time_1 time_2r time_3 If not met, increase time_2 — time_ax time_pio_rdx t0 — time_1, time_2r, time_9 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 101 Figure 77 shows timing for PIO write, and Table 66 lists the timing parameters for PIO write. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 77. PIO Write Timing Diagram Table 66. PIO Write Timing Parameters ATA Parameter Parameter from Figure 77 Controlling Variable Value t1 t2 t9 t3 t4 tA t0 — — t1 t2w t9 — t4 tA — — — t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5) t2 (min.) = time_2w × T – (tskew1 + tskew2 + tskew5) t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6) t3 (min.) = (time_2w – time_on) × T – (tskew1 + tskew2 +tskew5) t4 (min.) = time_4 × T – tskew1 tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) t0(min.) = (time_1 + time_2 + time_9) × T Avoid bus contention when switching buffer on by making ton long enough. Avoid bus contention when switching buffer off by making toff long enough. time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 102 Freescale Semiconductor Figure 78 shows timing for MDMA read, and Figure 79 shows timing for MDMA write. Table 67 lists the timing parameters for MDMA read and write. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 78. MDMA Read Timing Diagram Figure 79. MDMA Write Timing Diagram Table 67. MDMA Read and Write Timing Parameters Parameter from Figure 78, Figure 79 ATA Parameter Value Controlling Variable tm, ti td tk t0 tg(read) tf(read) tg(write) tf(write) tL tm td, td1 tk — tgr tfr — — — tm (min.) = ti (min.) = time_m × T – (tskew1 + tskew2 + tskew5) td1.(min.) = td (min.) = time_d × T – (tskew1 + tskew2 + tskew6) tk.(min.) = time_k × T – (tskew1 + tskew2 + tskew6) t0 (min.) = (time_d + time_k) × T tgr (min. – read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min. – drive) = td – te(drive) tfr (min. – drive) = 0 tg (min. – write) = time_d × T – (tskew1 + tskew2 + tskew5) tf (min. – write) = time_k × T – (tskew1 + tskew2 + tskew6) tL (max.) = (time_d + time_k–2) × T – (tsu + tco + 2 × tbuf + 2 × tcable2) time_m time_d time_k time_d, time_k time_d — time_d time_k time_d, time_k i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 103 Table 67. MDMA Read and Write Timing Parameters (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Parameter from Figure 78, Figure 79 ATA Parameter Value Controlling Variable tn, tj — tkjn ton toff tn = tj = tkjn = (max.(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6) ton = time_on × T – tskew1 toff = time_off × T – tskew1 time_jn — 4.9.17.5 UDMA-In Timing Figure 80 shows timing when the UDMA-in transfer starts, Figure 81 shows timing when the UDMA-in host terminates transfer, Figure 82 shows timing when the UDMA-in device terminates transfer, and Table 68 lists the timing parameters for the UDMA-in burst. Figure 80. UDMA-In Transfer Starts Timing Diagram Figure 81. UDMA-In Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 104 Freescale Semiconductor Figure 82. UDMA-In Device Terminates Transfer Timing Diagram Table 68. UDMA-In Burst Timing Parameters Parameters from Figure 80, Figure 81, Figure 82 ATA Parameter Description Controlling Variable tack tenv tds tdh tcyc trp — tmli tzah tdzfs tcvh — 1 tack tenv tds1 tdh1 tc1 trp tx1 1 tack (min.) = (time_ack × T) – (tskew1 + tskew2) tenv (min.) = (time_env × T) – (tskew1 + tskew2) tenv (max.) = (time_env × T) + (tskew1 + tskew2) tds – (tskew3) – ti_ds > 0 tdh – (tskew3) – ti_dh > 0 (tcyc – tskew > T trp (min.) = time_rp × T – (tskew1 + tskew2 + tskew6) (time_rp × T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive) tmli1 (min.) = (time_mlix + 0.4) × T tzah (min.) = (time_zah + 0.4) × T tdzfs = (time_dzfs × T) – (tskew1 + tskew2) tcvh = (time_cvh × T) – (tskew1 + tskew2) ton = time_on × T – tskew1 toff = time_off × T – tskew1 time_ack time_env tskew3, ti_ds, ti_dh should be low enough T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh — tmli1 tzah tdzfs tcvh ton toff There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff large enough to avoid bus contention. i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 105 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 4.9.17.6 UDMA-Out Timing Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 83 shows timing when the UDMA-out transfer starts, Figure 84 shows timing when the UDMA-out host terminates transfer, Figure 85 shows timing when the UDMA-out device terminates transfer, and Table 69 lists the timing parameters for the UDMA-out burst. Figure 83. UDMA-Out Transfer Starts Timing Diagram Figure 84. UDMA-Out Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 106 Freescale Semiconductor Figure 85. UDMA-Out Device Terminates Transfer Timing Diagram Table 69. UDMA-Out Burst Timing Parameters Parameter from Figure 83, Figure 84, Figure 85 ATA Parameter Value Controlling Variable tack tenv tdvs tdvh tcyc t2cyc trfs1 — tss tmli tli tli tli tcvh — tack tenv tdvs tdvh tcyc — trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff tack (min.) = (time_ack × T) – (tskew1 + tskew2) tenv (min.) = (time_env × T) – (tskew1 + tskew2) tenv (max.) = (time_env × T) + (tskew1 + tskew2) tdvs = (time_dvs ×T) – (tskew1 + tskew2) tdvs = (time_dvh × T) – (tskew1 + tskew2) tcyc = time_cyc × T – (tskew1 + tskew2) t2cyc = time_cyc × 2 × T trfs = 1.6 × T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs × T – (tskew1) tss = time_ss × T – (tskew1 + tskew2) tdzfs_mli = max. (time_dzfs, time_mli) × T – (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh × T) – (tskew1 + tskew2) ton = time_on × T – tskew1 toff = time_off × T – tskew1 time_ack time_env time_dvs time_dvh time_cyc time_cyc — time_dzfs time_ss — — — — time_cvh — i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 107 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 4.9.18 Parallel Interface (ULPI) Timing Table 70. Signal Definitions—Parallel Interface Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Electrical and timing specifications of the parallel interface are presented in the subsequent sections. Name Direction Signal Description USB_Clk USB_Data[7:0] USB_Dir USB_Stp USB_Nxt In I/O In Out In Interface clock. All interface signals are synchronous to the clock. Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir. Direction. Control the direction of the data bus. Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. Next. The PHY asserts this signal to throttle the data. USB_Clk US15 USB_Stp US15 USB_Data US16 US16 US17 USB_Dir/Nxt US17 Figure 86. USB Transmit/Receive Waveform in Parallel Mode Table 71. USB Timing Specification in VP_VM Unidirectional Mode ID Parameter Min. Max. Unit Conditions / Reference Signal US15 US16 US17 USB_TXOE_B USB_DAT_VP USB_SE0_VM — — — 6.0 0.0 9.0 ns ns ns 10 pF 10 pF 10 pF 4.9.19 PWM Electrical Specifications This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 108 Freescale Semiconductor 4.9.20 SJC Electrical Specifications This section details the electrical characteristics for the SJC module. Figure 87 depicts the SJC test clock input timing. Figure 88 depicts the SJC boundary scan timing, Figure 89 depicts the SJC test access port, Figure 90 depicts the SJC TRST timing, and Table 72 lists the SJC timing parameters. SJ1 SJ2 TCK (Input) SJ3 VIH VIL SJ3 VM SJ2 VM Figure 87. Test Clock Input Timing Diagram TCK (Input) VIL SJ4 Data Inputs SJ6 Data Outputs SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Output Data Valid SJ5 VIH Input Data Valid Figure 88. Boundary Scan (JTAG) Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 109 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. pin. The modulated signal of the module is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the PWM. The smallest period is two ipg_clk periods with duty cycle of 50 percent. TCK (Input) VIL SJ8 TDI TMS (Input) SJ10 TDO (Output) SJ11 TDO (Output) SJ10 TDO (Output) VIH SJ9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Input Data Valid Output Data Valid Output Data Valid Figure 89. Test Access Port Timing Diagram TCK (Input) SJ13 TRST (Input) SJ12 Figure 90. TRST Timing Diagram Table 72. SJC Timing Parameters All Frequencies ID Parameter Min. Max. Unit SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8 SJ9 SJ10 TCK cycle time TCK clock pulse width measured at VM 2 TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid 1001 40 — 10 50 — — 10 50 — — — 3 — — 50 50 — — 44 ns ns ns ns ns ns ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 110 Freescale Semiconductor Table 72. SJC Timing Parameters (continued) All Frequencies ID Parameter Min. Max. Unit SJ11 SJ12 SJ13 1 2 TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low — 100 40 44 — — ns ns ns On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock. VM = mid point voltage 4.9.21 SPDIF Timing SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Figure 91 shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode. Table 73. SPDIF Timing Parameters Timing Parameter Range Parameters Symbol Min. Max. Units SPDIFIN Skew: asynchronous inputs, no specs apply SPDIFOUT output (Load = 50 pf) • Skew • Transition rising • Transition falling SPDIFOUT1 output (Load = 30 pf) • Skew • Transition rising • Transition falling Modulating Rx clock (SRCK) period SRCK high period SRCK low period Modulating Tx clock (STCLK) period STCLK high period STCLK low period — — — — — — — — 0.7 1.5 24.2 31.3 ns ns — — — srckp srckph srckpl stclkp stclkph stclkpl — — — 40.0 16.0 16.0 40.0 16.0 16.0 1.5 13.6 18.0 — — — — — — ns ns ns ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 111 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. srckpl SRCK (Output) VM srckph VM Figure 91. SRCK Timing stclkp stclkpl STCLK (Input) VM stclkph VM Figure 92. STCLK Timing 4.9.22 SSI Electrical Specifications NOTE All of the timing for the SSI is given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timing is on AUDMUX signals when SSI is being used for data transfer. “Tx” and “Rx” refer to the transmit and receive sections of the SSI, respectively. For internal frame sync operations using the external clock, the FS timing will be the same as that of Tx Data (for example, during AC97 mode of operation). This section describes electrical characteristics of the SSI. • • • • i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 112 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. srckp 4.9.22.1 SSI Transmitter Timing with Internal Clock Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 93 depicts the SSI transmitter timing with internal clock, and Table 74 lists the timing parameters. SS1 SS2 AD1_TXC (Output) SS6 AD1_TXFS (bl) (Output) SS10 AD1_TXFS (wl) (Output) SS16 AD1_TXD (Output) SS43 SS42 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS1 SS2 SS19 SS14 SS15 SS17 SS18 SS12 SS8 SS5 SS4 SS3 SS5 SS4 SS3 DAM1_T_CLK (Output) SS6 DAM1_T_FS (bl) (Output) SS10 DAM1_T_FS (wl) (Output) SS16 DAM1_TXD (Output) SS43 SS42 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only SS19 SS14 SS15 SS17 SS18 SS12 SS8 Figure 93. SSI Transmitter with Internal Clock Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 113 Table 74. SSI Transmitter with Internal Clock Timing Parameters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID Parameter Internal Clock Operation Min. Max. Unit SS1 SS2 SS3 SS4 SS5 SS6 SS8 SS10 SS12 SS14 SS15 SS16 SS17 SS18 SS19 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx/Rx) Internal FS rise time (Tx/Rx) Internal FS fall time (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance STXD rise/fall time Synchronous Internal Clock Operation 81.4 36.0 — 36.0 — — — — — — — — — — — — — 6 — 6 15.0 15.0 15.0 15.0 6 6 15.0 15.0 15.0 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SS42 SS43 SS52 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling Loading 10.0 0 — — — 25 ns ns pF i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 114 Freescale Semiconductor 4.9.22.2 SSI Receiver Timing with Internal Clock Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 94 depicts the SSI receiver timing with internal clock. Table 75 lists the timing parameters shown in Figure 94. SS1 SS2 AD1_TXC (Output) SS7 AD1_TXFS (bl) (Output) AD1_TXFS (wl) (Output) SS20 SS21 AD1_RXD (Input) SS47 SS48 AD1_RXC (Output) SS1 SS5 SS2 DAM1_T_CLK (Output) SS7 DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) SS20 SS21 DAM1_RXD (Input) SS47 SS48 DAM1_R_CLK (Output) SS51 SS50 SS9 SS4 SS51 SS50 SS49 SS9 SS5 SS4 SS3 SS11 SS13 SS3 SS11 SS13 SS49 Figure 94. SSI Receiver with Internal Clock Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 115 Table 75. SSI Receiver with Internal Clock Timing Parameters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID Parameter Internal Clock Operation Min. Max. Unit SS1 SS2 SS3 SS4 SS5 SS7 SS9 SS11 SS13 SS20 SS21 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low Oversampling Clock Operation 81.4 36.0 — 36.0 — — — — — 10.0 0 — — 6 — 6 15.0 15.0 15.0 15.0 — — ns ns ns ns ns ns ns ns ns ns ns SS47 SS48 SS49 SS50 SS51 Oversampling clock period Oversampling clock high period Oversampling clock rise time Oversampling clock low period Oversampling clock fall time 15.04 6 — 6 — — — 3 — 3 ns ns ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 116 Freescale Semiconductor 4.9.22.3 SSI Transmitter Timing with External Clock Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 95 depicts the SSI transmitter timing with external clock, and Table 76 lists the timing parameters. SS22 SS23 SS25 SS26 SS24 AD1_TXC (Input) AD1_TXFS (bl) (Input) SS27 SS29 SS31 AD1_TXFS (wl) (Input) SS37 AD1_TXD (Output) SS45 SS44 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS38 SS33 SS39 SS22 SS23 DAM1_T_CLK (Input) SS27 DAM1_T_FS (bl) (Input) SS31 DAM1_T_FS (wl) (Input) SS37 DAM1_TXD (Output) SS29 SS26 SS25 SS24 SS33 SS39 SS38 SS44 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only SS45 SS46 Figure 95. SSI Transmitter with External Clock Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 117 Table 76. SSI Transmitter with External Clock Timing Parameters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID Parameter External Clock Operation Min. Max. Unit SS22 SS23 SS24 SS25 SS26 SS27 SS29 SS31 SS33 SS37 SS38 SS39 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance Synchronous External Clock Operation 81.4 36.0 — 36.0 — –10.0 10.0 –10.0 10.0 — — — — — 6.0 — 6.0 15.0 — 15.0 — 15.0 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns SS44 SS45 SS46 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling SRXD rise/fall time 10.0 2.0 — — — 6.0 ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 118 Freescale Semiconductor 4.9.22.4 SSI Receiver Timing with External Clock Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Figure 96 depicts the SSI receiver timing with external clock, and Table 77 lists the timing parameters. SS22 SS26 SS23 AD1_TXC (Input) SS28 AD1_TXFS (bl) (Input) AD1_TXFS (wl) (Input) AD1_RXD (Input) SS30 SS25 SS24 SS32 SS35 SS41 SS40 SS36 SS34 SS22 SS26 SS23 DAM1_T_CLK (Input) SS28 DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) DAM1_RXD (Input) SS30 SS25 SS24 SS32 SS35 SS41 SS40 SS36 SS34 Figure 96. SSI Receiver with External Clock Timing Diagram Table 77. SSI Receiver with External Clock Timing Parameters ID Parameter External Clock Operation Min. Max. Unit SS22 SS23 SS24 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time 81.4 36.0 — — — 6.0 ns ns ns i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 119 Table 77. SSI Receiver with External Clock Timing Parameters (continued) ID Parameter Min. Max. Unit SS25 SS26 SS28 SS30 SS32 SS34 SS35 SS36 SS40 SS41 (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low (Tx/Rx) External FS rise time (Tx/Rx) External FS fall time SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 36.0 — –10.0 10.0 –10.0 10.0 — — 10.0 2.0 — 6.0 15.0 — 15.0 — 6.0 6.0 — — ns ns ns ns ns ns ns ns ns ns 4.9.23 UART Electrical This section describes the electrical information of the UART module. 4.9.23.1 UART RS-232 Serial Mode Timing The following subsections give the UART transmit and receive timings in RS-232 serial mode. 4.9.23.1.11 UART Transmitter Figure 97 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format. Table 78 lists the UART RS-232 serial mode transmit timing characteristics. UA1 Start Bit UA1 Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT TXD (output) Bit 0 Bit 1 Bit 2 Bit 3 Next Start Bit UA1 UA1 Figure 97. UART RS-232 Serial Mode Transmit Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 120 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 78. RS-232 Serial Mode Transmit Timing Parameters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID Parameter Symbol Min. Max. Units UA1 1 2 Transmit Bit Time tTbit 1/Fbaud_rate1 – Tref_clk2 1/Fbaud_rate + Tref_clk — Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). 4.9.23.1.12 UART Receiver Figure 98 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 79 lists serial mode receive timing characteristics. UA2 Start Bit UA2 Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT RXD (input) Bit 0 Bit 1 Bit 2 Bit 3 Next Start Bit UA2 UA2 Figure 98. UART RS-232 Serial Mode Receive Timing Diagram Table 79. RS-232 Serial Mode Receive Timing Parameters ID Parameter Symbol Min. Max. Units UA2 1 2 Receive Bit Time1 tRbit 1/Fbaud_rate2 – 1/(16 × Fbaud_rate) 1/Fbaud_rate + 1/(16 × Fbaud_rate) — The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16 × Fbaud_rate). Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16. 4.9.23.2 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. 4.9.23.2.13 UART IrDA Mode Transmitter Figure 99 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 80 lists the transmit timing characteristics. UA3 UA3 UA4 UA3 UA3 TXD (output) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT Figure 99. UART IrDA Mode Transmit Timing Diagram i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 121 Table 80. IrDA Mode Transmit Timing Parameters Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. ID Parameter Symbol Min. Max. Units UA3 UA4 1 2 Transmit bit time in IrDA mode Transmit IR pulse duration tTIRbit tTIRpulse 1/Fbaud_rate1 – Tref_clk2 1/Fbaud_rate + Tref_clk — — (3/16) × (1/Fbaud_rate) (3/16) × (1/Fbaud_rate) – Tref_clk + Tref_clk Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). 4.9.23.2.14 UART IrDA Mode Receiver Figure 100 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 81 lists the receive timing characteristics. UA5 UA5 UA6 UA5 UA5 RXD (input) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT Figure 100. UART IrDA Mode Receive Timing Diagram Table 81. IrDA Mode Receive Timing Parameters ID Parameter Symbol Min. Max. Units UA5 UA6 1 2 Receive bit time1 in IrDA mode Receive IR pulse duration tRIRbit tRIRpulse 1/Fbaud_rate2 – 1/(16 × Fbaud_rate) 1.41 us 1/Fbaud_rate + 1/(16 × Fbaud_rate ) (5/16) × (1/Fbaud_rate) — — The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16 × Fbaud_rate). Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16. 4.9.24 USB Electrical Specifications In order to support four different serial interfaces, the USB serial transceiver can be configured to operate in one of four modes: • DAT_SE0 bidirectional, 3-wire mode • DAT_SE0 unidirectional, 6-wire mode • VP_VM bidirectional, 4-wire mode • VP_VM unidirectional, 6-wire mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 122 Freescale Semiconductor 4.9.24.1 DAT_SE0 Bidirectional Mode Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 82 defines the signals for DAT_SE0 bidirectional mode. Figure 101 and Figure 102 show the transmit and receive waveforms respectively. Table 82. Signal Definitions—DAT_SE0 Bidirectional Mode Name Direction Signal Description USB_TXOE_B USB_DAT_VP Out Out In Out In Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 Rx indicator when USB_TXOE_B is high USB_SE0_VM Transmit US3 USB_TXOE_B USB_DAT_VP USB_SE0_VM US1 US4 US2 Figure 101. USB Transmit Waveform in DAT_SE0 Bidirectional Mode Receive USB_TXOE_B USB_DAT_VP US7 US8 USB_SE0_VM Figure 102. USB Receive Waveform in DAT_SE0 Bidirectional Mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 123 Table 83 describes the port timing specification in DAT_SE0 bidirectional mode. Table 83. Port Timing Specification in DAT_SE0 Bidirectional Mode No. Parameter Signal Name Direction Min. Max. Unit Conditions/Reference Signal US1 US2 US3 US4 US7 US8 Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Rx rise/fall time Rx rise/fall time USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_DAT_VP USB_SE0_VM Out Out Out Out In In — — — 49.0 — — 5.0 5.0 5.0 51.0 3.0 3.0 ns ns ns % ns ns 50 pF 50 pF 50 pF — 35 pF 35 pF 4.9.24.2 DAT_SE0 Unidirectional Mode Table 84 defines the signals for DAT_SE0 unidirectional mode. Figure 103 and Figure 104 show the transmit and receive waveforms respectively. Table 84. Signal Definitions—DAT_SE0 Unidirectional Mode Name Direction Signal Description USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV Transmit Out Out Out In In In Transmit enable, active low Tx data when USB_TXOE_B is low SE0 drive when USB_TXOE_B is low Buffered data on DP when USB_TXOE_B is high Buffered data on DM when USB_TXOE_B is high Differential Rx data when USB_TXOE_B is high US11 USB_TXOE_B USB_DAT_VP USB_SE0_VM US9 US12 US10 Figure 103. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 124 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Receive USB_TXOE_B USB_VP1 USB_RCV US15/US17 US16 USB_VM1 Figure 104. USB Receive Waveform in DAT_SE0 Unidirectional Mode Table 85 describes the port timing specification in DAT_SE0 unidirectional mode. Table 85. USB Port Timing Specification in DAT_SE0 Unidirectional Mode No. Parameter Signal Name Signal Source Min. Max. Unit Condition/ Reference Signal US9 US10 US11 US12 US15 US16 US17 Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Rx rise/fall time Rx rise/fall time Rx rise/fall time USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_VP1 USB_VM1 USB_RCV Out Out Out Out In In In — — — 49.0 — — — 5.0 5.0 5.0 51.0 3.0 3.0 3.0 ns ns ns % ns ns ns 50 pF 50 pF 50 pF — 35 pF 35 pF 35 pF 4.9.24.3 VP_VM Bidirectional Mode Table 86 defines the signals for VP_VM bidirectional mode. Figure 105 and Figure 106 show the transmit and receive waveforms respectively. Table 86. Signal Definitions—VP_VM Bidirectional Mode Name Direction Signal Description USB_TXOE_B USB_DAT_VP Out Out (Tx) In (Rx) Out (Tx) In (Rx) In Transmit enable, active low Tx VP data when USB_TXOE_B is low Rx VP data when USB_TXOE_B is high Tx VM data when USB_TXOE_B low Rx VM data when USB_TXOE_B high Differential Rx data USB_SE0_VM USB_RCV i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 125 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM US18 US21 US19 US22 US22 Figure 105. USB Transmit Waveform in VP_VM Bidirectional Mode Receive US26 USB_DAT_VP USB_SE0_VM US28 US27 USB_RCV US29 Figure 106. USB Receive Waveform in VP_VM Bidirectional Mode Table 87 describes the port timing specification in VP_VM bidirectional mode. Table 87. USB Port Timing Specification in VP_VM Bidirectional Mode No. Parameter Signal Name Direction Min. Max. Unit Condition/ Reference Signal US18 US19 US20 US21 US22 US26 US27 Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Tx overlap Rx rise/fall time Rx rise/fall time USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_SE0_VM Out Out Out Out Out In In — — — 49.0 –3.0 — — 5.0 5.0 5.0 51.0 +3.0 3.0 3.0 ns ns ns % ns ns ns 50 pF 50 pF 50 pF — USB_DAT_VP 35 pF 35 pF i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 126 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. US20 Table 87. USB Port Timing Specification in VP_VM Bidirectional Mode (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. No. Parameter Signal Name Direction Min. Max. Unit Condition/ Reference Signal US28 US29 Rx skew Rx skew USB_DAT_VP USB_RCV In In –4.0 –6.0 +4.0 +2.0 ns ns USB_SE0_VM USB_DAT_VP 4.9.24.4 VP_VM Unidirectional Mode Table 88 defines the signals for VP_VM unidirectional mode. Figure 107 and Figure 108 show the transmit and receive waveforms respectively. Table 88. Signal Definitions—VP_VM Unidirectional Mode Name Direction Signal Description USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV Out Out Out In In In Transmit enable, active low Tx VP data when USB_TXOE_B is low Tx VM data when USB_TXOE_B is low Rx VP data when USB_TXOE_B is high Rx VM data when USB_TXOE_B is high Differential Rx data Transmit US32 USB_TXOE_B USB_DAT_VP USB_SE0_VM US30 US33 US31 US34 US34 Figure 107. USB Transmit Waveform in VP_VM Unidirectional Mode i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 127 Receive USB_TXOE_B USB_VP1 US38 USB_VM1 US40 US39 USB_RCV US41 Figure 108. USB Receive Waveform in VP_VM Unidirectional Mode Table 89 describes the port timing specification in VP_VM unidirectional mode. Table 89. USB Timing Specification in VP_VM Unidirectional Mode No. Parameter Signal Direction Min. Max. Unit Conditions/Reference Signal US30 US31 US32 US33 US34 US38 US39 US40 US41 Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Tx overlap Rx rise/fall time Rx rise/fall time Rx skew Rx skew USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_VP1 USB_RCV Out Out Out Out Out In In In In — — — 49.0 –3.0 — — –4.0 –6.0 5.0 5.0 5.0 51.0 +3.0 3.0 3.0 +4.0 +2.0 ns ns ns % ns ns ns ns ns 50 pF 50 pF 50 pF — USB_DAT_VP 35 pF 35 pF USB_VM1 USB_VP1 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 128 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 5 Freescale Semiconductor This section includes the following: • Mechanical package drawing • Pin/contact assignment information Package Information and Pinout i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 129 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 130 5.1 See Figure 109 for the package drawing and dimensions of the production package. Figure 109. Production Package: Mechanical Drawing MAPBGA Production Package 1568-01, 17x17 mm, 0.8 Pitch i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 5.2 MAPBGA Signal Assignments Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 90 and Table 91 list MAPBGA signals, alphabetized by signal name, for silicon revisions 2.0 and 2.1, respectively. Table 92 and Table 93 show the signal assignment on the i.MX35 ball map for silicon revisions 2.0 and 2.1, respectively. The ball map for silicon revision 2.1 is different than the ballmap for silicon revision 2.0. The layout for each revision is not compatible, so it is important that the correct ballmap be used to implement the layout. Table 90. Silicon Revision 2.0 Signal Ball Map Locations Signal ID Ball Location Signal ID Ball Location A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A3 A4 A5 A6 A7 A8 A9 ATA_BUFF_EN ATA_CS0 ATA_CS1 ATA_DA0 ATA_DA1 ATA_DA2 ATA_DATA0 ATA_DATA1 ATA_DATA10 ATA_DATA11 ATA_DATA12 A5 D7 F15 D5 F6 B3 D14 D15 D13 D12 E11 D11 E7 D10 E10 D9 E9 D8 E8 C6 D6 B5 C5 A4 B4 A3 T5 V7 T7 R4 V1 R5 Y5 W5 V3 Y2 U3 ATA_DATA7 ATA_DATA8 ATA_DATA9 ATA_DIOR ATA_DIOW ATA_DMACK ATA_DMARQ ATA_INTRQ ATA_IORDY ATA_RESET_B BCLK BOOT_MODE0 BOOT_MODE1 CAPTURE CAS CLK_MODE0 CLK_MODE1 CLKO COMPARE CONTRAST CS0 CS1 CS2 CS3 CS4 CS5 CSI_D10 CSI_D11 CSI_D12 CSI_D13 CSI_D14 CSI_D15 CSI_D8 CSI_D9 CSI_HSYNC CSI_MCLK CSI_PIXCLK Y3 U4 W3 Y6 W6 V6 T3 V2 U6 T6 E14 W10 U9 V12 E16 Y10 T10 V10 T12 L16 F17 E19 B20 C19 E18 F19 V16 T15 W16 V15 U14 Y16 U15 W17 V14 W15 Y15 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 131 Table 90. Silicon Revision 2.0 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location ATA_DATA13 ATA_DATA14 ATA_DATA15 ATA_DATA2 ATA_DATA3 ATA_DATA4 ATA_DATA5 ATA_DATA6 CTS2 D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D3_CLS D3_DRDY D3_FPSHIFT D3_HSYNC D3_REV D3_SPL D3_VSYNC D4 D5 D6 D7 D8 D9 DE_B DQM0 DQM1 DQM2 DQM3 EB0 EB1 ECB EXT_ARMCLK EXTAL_AUDIO EXTAL24M FEC_COL FEC_CRS FEC_MDC W2 W1 T4 V5 U5 Y4 W4 V4 G5 A2 D4 D2 E6 E3 F5 D1 E2 B2 E5 L17 L20 L15 L18 M17 M18 M19 C3 B1 D3 C2 C1 E4 W19 B19 D17 D16 C18 F18 F16 D19 V8 W20 T20 P3 N5 R1 CSI_VSYNC CSPI1_MISO CSPI1_MOSI CSPI1_SCLK CSPI1_SPI_RDY CSPI1_SS0 CSPI1_SS1 CTS1 FEC_TDATA0 FEC_TDATA1 FEC_TDATA2 FEC_TDATA3 FEC_TX_CLK FEC_TX_EN FEC_TX_ERR FSR FST FUSE_VDD FUSE_VSS GPIO1_0 GPIO1_1 GPIO2_0 GPIO3_0 HCKR HCKT I2C1_CLK I2C1_DAT I2C2_CLK I2C2_DAT LBA LD0 LD1 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD2 LD20 LD21 LD22 T14 V9 W9 W8 T8 Y8 U8 R3 P5 M4 M5 L6 P4 T1 N4 K5 J1 P13 M11 T11 Y11 U11 V11 K2 J5 M20 N17 L3 M1 D20 F20 G18 H20 J18 J16 J19 J17 J20 K14 K19 K18 K20 G17 K16 K17 K15 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 132 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 90. Silicon Revision 2.0 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location FEC_MDIO FEC_RDATA0 FEC_RDATA1 FEC_RDATA2 FEC_RDATA3 FEC_RX_CLK FEC_RX_DV FEC_RX_ERR MA10 MGND MLB_CLK MLB_DAT MLB_SIG MVDD NF_CE0 NFALE NFCLE NFRB NFRE_B NFWE_B NFWP_B NGND_ATA NGND_ATA NGND_ATA NGND_CRM NGND_CSI NGND_EMI1 NGND_EMI1 NGND_EMI1 NGND_EMI2 NGND_EMI3 NGND_EMI3 NGND_JTAG NGND_LCDC NGND_LCDC NGND_MISC NGND_MISC NGND_MLB NGND_NFC NGND_SDIO NVCC_ATA NVCC_ATA NVCC_ATA NVCC_ATA NVCC_CRM NVCC_CSI P1 P2 N2 M3 N1 R2 T2 N3 C4 N11 W13 Y13 W12 P11 G3 F2 E1 F3 F1 G2 F4 M9 P9 L10 L11 N10 H8 H10 J10 J11 J12 K12 M13 K11 L12 M7 K8 M10 K9 N12 N6 P6 P7 P8 R9 R11 LD23 LD3 LD4 LD5 LD6 LD7 LD8 LD9 NVCC_EMI2 NVCC_EMI2 NVCC_EMI2 NVCC_EMI3 NVCC_JTAG NVCC_LCDC NVCC_LCDC NVCC_LCDC NVCC_LCDC NVCC_MISC NVCC_MISC NVCC_MISC NVCC_MLB NVCC_NFC NVCC_NFC NVCC_NFC NVCC_SDIO OE OSC_AUDIO_VDD OSC_AUDIO_VSS OSC24M_VDD OSC24M_VSS PGND PHY1_VDDA PHY1_VDDA PHY1_VSSA PHY1_VSSA PHY2_VDD PHY2_VSS POR_B POWER_FAIL PVDD RAS RESET_IN_B RTCK RTS1 RTS2 RW L19 G16 G19 H16 H18 G20 H17 H19 G12 F13 F14 G14 P16 H14 J14 L14 M14 K6 K7 L8 R10 G6 H6 H7 P14 E20 V20 U19 T19 T18 M12 M15 N20 N16 P20 R13 P12 W11 Y9 N13 E15 U10 U18 U1 G1 C20 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 133 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 90. Silicon Revision 2.0 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 SD2 SD2_CLK SD2_CMD SD2_DATA0 SD2_DATA1 SD2_DATA2 SD2_DATA3 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD30 SD31 SD4 SD5 G7 G8 G9 H9 F10 G10 F11 G11 V18 Y19 R14 U16 W18 V17 A15 B15 C13 B14 A14 B13 C12 C11 A12 B12 B18 W14 U13 V13 T13 Y14 U12 B11 A11 C10 B10 A9 C9 B9 A8 B8 C8 C16 A7 B7 A18 C15 RXD1 RXD2 SCK4 SCK5 SCKR SCKT SD0 SD1 SDCLK SDCLK_B SDQS0 SDQS1 SDQS2 SDQS3 SDWE SJC_MOD SRXD4 SRXD5 STXD4 STXD5 STXFS4 STXFS5 TCK TDI TDO TEST_MODE TMS TRSTB TTM_PIN TX0 TX1 TX2_RX3 TX3_RX2 TX4_RX1 TX5_RX0 TXD1 TXD2 USBOTG_OC USBOTG_PWR USBPHY1_DM USBPHY1_DP USBPHY1_RREF USBPHY1_UID USBPHY1_UPLLGND USBPHY1_UPLLVDD USBPHY1_UPLLVDD U2 H3 L4 L5 K3 J4 C17 A19 E12 E13 B17 A13 A10 C7 G15 U17 L1 K4 M2 K1 L2 J6 R17 P15 R15 Y7 R16 T16 M16 G4 H1 H5 J2 H4 J3 R6 H2 U7 W7 N19 P19 R19 N18 N14 N15 P17 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 134 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 90. Silicon Revision 2.0 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location SD6 SD7 SD8 SD9 SDBA0 SDBA1 SDCKE0 SDCKE1 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS A17 B16 C14 A16 A6 B6 D18 E17 L7 N7 R7 F8 R8 F9 F12 R12 G13 H15 J15 A1 Y1 J8 M8 N8 J9 USBPHY1_VBUS USBPHY1_VDDA_BIAS USBPHY1_VSSA_BIAS USBPHY2_DM USBPHY2_DP VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSTBY WDOG_RST XTAL_AUDIO XTAL24M P18 R20 R18 Y17 Y18 M6 F7 J7 L9 N9 K10 P10 H11 H12 H13 J13 K13 L13 T17 A20 Y20 T9 Y12 V19 U20 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 135 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 91. Silicon Revision 2.1 Signal Ball Map Locations Signal ID Ball Location Signal ID Ball Location A0 A1 A10 A11 A12 A13 A14 A15 A16 A18 SDQS1 A19 A2 A21 SDQS2 A22 SDQS3 A24 A25 A3 A4 A5 A6 A7 A8 A9 ATA_BUFF_EN ATA_CS0 ATA_CS1 ATA_DA0 ATA_DA1 ATA_DA2 ATA_DATA0 ATA_DATA1 ATA_DATA10 ATA_DATA11 ATA_DATA12 ATA_DATA13 ATA_DATA14 ATA_DATA15 ATA_DATA2 ATA_DATA3 ATA_DATA4 ATA_DATA5 ATA_DATA6 A5 D7 F15 D5 F6 B3 D14 D15 D13 D12 E11 D11 E7 D10 E10 D9 E9 D8 E8 C6 D6 B5 C5 A4 B4 A3 T5 V7 T7 R4 V1 R5 Y5 W5 V3 Y2 U3 W2 W1 T4 V5 U5 Y4 W4 V4 ATA_DATA7 ATA_DATA8 ATA_DATA9 ATA_DIOR ATA_DIOW ATA_DMACK ATA_DMARQ ATA_INTRQ ATA_IORDY ATA_RESET_B SDQS0 BOOT_MODE0 BOOT_MODE1 CAPTURE RAS CLK_MODE0 CLK_MODE1 CLKO COMPARE CONTRAST CS0 CS1 CS2 CS3 CS4 CS5 CSI_D10 CSI_D11 CSI_D12 CSI_D13 CSI_D14 CSI_D15 CSI_D8 CSI_D9 CSI_HSYNC CSI_MCLK CSI_PIXCLK CSI_VSYNC CSPI1_MISO CSPI1_MOSI CSPI1_SCLK CSPI1_SPI_RDY CSPI1_SS0 CSPI1_SS1 CTS1 Y3 U4 W3 Y6 W6 V6 T3 V2 U6 T6 E14 W10 U9 V12 E16 Y10 T10 V10 T12 L16 F17 E19 B20 C19 E18 F19 V16 T15 W16 V15 U14 Y16 U15 W17 V14 W15 Y15 T14 V9 W9 W8 T8 Y8 U8 R3 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 136 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 91. Silicon Revision 2.1 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location CTS2 D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D3_CLS D3_DRDY D3_FPSHIFT D3_HSYNC D3_REV D3_SPL D3_VSYNC D4 D5 D6 D7 D8 D9 DE_B DQM0 SDCKE1 DQM2 DQM3 EB0 EB1 ECB EXT_ARMCLK EXTAL_AUDIO EXTAL24M FEC_COL FEC_CRS FEC_MDC FEC_MDIO FEC_RDATA0 FEC_RDATA1 FEC_RDATA2 FEC_RDATA3 FEC_RX_CLK FEC_RX_DV FEC_RX_ERR G5 A2 D4 D2 E6 E3 F5 D1 E2 B2 E5 L17 L20 L15 L18 M17 M18 M19 C3 B1 D3 C2 C1 E4 W19 B19 D17 D16 C18 F18 F16 D19 V8 W20 T20 P3 N5 R1 P1 P2 N2 M3 N1 R2 T2 N3 FEC_TDATA0 FEC_TDATA1 FEC_TDATA2 FEC_TDATA3 FEC_TX_CLK FEC_TX_EN FEC_TX_ERR FSR FST FUSE_VDD FUSE_VSS GPIO1_0 GPIO1_1 GPIO2_0 GPIO3_0 HCKR HCKT I2C1_CLK I2C1_DAT I2C2_CLK I2C2_DAT LBA LD0 LD1 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD2 LD20 LD21 LD22 LD23 LD3 LD4 LD5 LD6 LD7 LD8 LD9 P5 M4 M5 L6 P4 T1 N4 K5 J1 P13 M11 T11 Y11 U11 V11 K2 J5 M20 N17 L3 M1 D20 F20 G18 H20 J18 J16 J19 J17 J20 K14 K19 K18 K20 G17 K16 K17 K15 L19 G16 G19 H16 H18 G20 H17 H19 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 137 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 91. Silicon Revision 2.1 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location MA10 MGND MLB_CLK MLB_DAT MLB_SIG MVDD NF_CE0 NFALE NFCLE NFRB NFRE_B NFWE_B NFWP_B NGND_ATA NGND_ATA NGND_ATA NGND_CRM NGND_CSI NGND_EMI1 NVCC_EMI1 NGND_EMI1 NGND_EMI2 NGND_EMI3 NGND_EMI3 NGND_JTAG NGND_LCDC NGND_LCDC NGND_MISC NGND_MISC NGND_MLB NGND_NFC NGND_SDIO NVCC_ATA NVCC_ATA NVCC_ATA NVCC_ATA NVCC_CRM NVCC_CSI NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NGND_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 C4 N11 W13 Y13 W12 P11 G3 F2 E1 F3 F1 G2 F4 M9 P9 L10 L11 N10 H8 H10 J10 J11 J12 K12 M13 K11 L12 M7 K8 M10 K9 N12 N6 P6 P7 P8 R9 R11 G7 G8 G9 H9 F10 G10 F11 G11 NVCC_EMI2 NVCC_EMI2 VSS NVCC_EMI3 NVCC_JTAG NVCC_LCDC NVCC_LCDC NVCC_LCDC NVCC_LCDC NVCC_MISC NVCC_MISC NVCC_MISC NVCC_MLB NVCC_NFC NVCC_NFC NVCC_NFC NVCC_SDIO OE OSC_AUDIO_VDD OSC_AUDIO_VSS OSC24M_VDD OSC24M_VSS PGND PHY1_VDDA PHY1_VDDA PHY1_VSSA PHY1_VSSA PHY2_VDD PHY2_VSS POR_B POWER_FAIL PVDD BCLK RESET_IN_B RTCK RTS1 RTS2 RW RXD1 RXD2 SCK4 SCK5 SCKR SCKT DQM1 SD1 G12 F13 F14 G14 P16 H14 J14 L14 M14 K6 K7 L8 R10 G6 H6 H7 P14 E20 V20 U19 T19 T18 M12 M15 N20 N16 P20 R13 P12 W11 Y9 N13 E15 U10 U18 U1 G1 C20 U2 H3 L4 L5 K3 J4 C17 A19 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 138 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 91. Silicon Revision 2.1 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD10 SD11 A17 SD13 SD14 SD12 SD16 SD17 SD18 SD19 SD2 SD2_CLK SD2_CMD SD2_DATA0 SD2_DATA1 SD2_DATA2 SD2_DATA3 SD20 SD21 A20 SD22 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD30 SD31 SD4 SD5 SD6 SD7 SD8 SD9 SDBA0 SDBA1 SDCKE0 CAS V18 Y19 R14 U16 W18 V17 A15 B15 C13 B14 A14 B13 C12 C11 A12 B12 B18 W14 U13 V13 T13 Y14 U12 B11 A11 C10 B10 A9 C9 B9 A8 B8 C8 C16 A7 B7 A18 C15 A17 B16 C14 A16 A6 B6 D18 E17 SDCLK SDCLK_B SD0 SD15 SD23 A23 SDWE SJC_MOD SRXD4 SRXD5 STXD4 STXD5 STXFS4 STXFS5 TCK TDI TDO TEST_MODE TMS TRSTB TTM_PIN TX0 TX1 TX2_RX3 TX3_RX2 TX4_RX1 TX5_RX0 TXD1 TXD2 USBOTG_OC USBOTG_PWR USBPHY1_DM USBPHY1_DP USBPHY1_RREF USBPHY1_UID USBPHY1_UPLLGND USBPHY1_UPLLVDD USBPHY1_UPLLVDD USBPHY1_VBUS USBPHY1_VDDA_BIAS USBPHY1_VSSA_BIAS USBPHY2_DM USBPHY2_DP VDD VDD VDD E12 E13 B17 A13 A10 C7 G15 U17 L1 K4 M2 K1 L2 J6 R17 P15 R15 Y7 R16 T16 M16 G4 H1 H5 J2 H4 J3 R6 H2 U7 W7 N19 P19 R19 N18 N14 N15 P17 P18 R20 R18 Y17 Y18 M6 F7 J7 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 139 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 91. Silicon Revision 2.1 Signal Ball Map Locations (continued) Signal ID Ball Location Signal ID Ball Location VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS L7 N7 R7 F8 R8 F9 F12 R12 G13 H15 J15 A1 Y1 J8 M8 N8 J9 VSS VSS VSS VSS VSS VSS NVCC_EMI2 VSS VSS VSS VSS VSS VSS VSTBY WDOG_RST XTAL_AUDIO XTAL24M L9 N9 K10 P10 H11 H12 H13 J13 K13 L13 T17 A20 Y20 T9 Y12 V19 U20 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 140 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 92. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch 1 A B C D E VSS D5 D8 D14 NFC LE NFR E_B RTS 2 TX1 2 D0 D2 D7 D10 D15 3 A9 A13 D4 D6 D12 4 A7 A8 MA1 0 D1 D9 5 A0 A5 A6 A11 D3 6 SDB A0 SDB A1 A3 A4 D11 7 SD3 0 SD3 1 SDQ S3 A1 A2 8 SD2 7 SD2 8 SD2 9 A24 A25 9 SD2 4 SD2 6 SD2 5 A22 A23 10 SDQ S2 SD2 3 SD2 2 A20 A21 11 SD2 1 SD2 0 SD1 7 A19 A18 12 SD1 8 SD1 9 SD1 6 A17 SDC LK VDD 13 SDQ S1 SD1 5 SD1 2 A16 SDC LK_ B NVC C_E MI2 VDD 14 SD1 4 SD1 3 SD8 A14 BCL K NVC C_E MI2 NVC C_E MI3 NVC C_L CDC NVC C_L CDC 15 SD1 0 SD1 1 SD5 A15 RAS 16 SD9 SD7 SD3 17 SD6 SDQ S0 SD0 18 SD4 SD2 DQM 3 SDC KE0 CS4 19 SD1 DQM 0 CS3 ECB CS1 20 VSS CS2 RW LBA OE A B C D E DQM DQM 2 1 CAS SDC KE1 CS0 F NFA LE NFW E_B TXD 2 NFR B NF_ CE0 RXD 2 NFW P_B TX0 D13 A12 VDD VDD VDD NVC C_E MI1 NVC C_E MI1 NGN D_E MI1 NGN D_E MI1 VSS NVC C_E MI1 NVC C_E MI1 VSS A10 EB1 EB0 CS5 LD0 F G CTS 2 NVC C_N FC NVC C_N FC STX FS5 NVC C_E MI1 NVC C_N FC VDD NVC C_E MI1 NGN D_E MI1 VSS NVC C_E MI1 NVC C_E MI1 VSS NVC C_E MI2 VSS SDW E VDD LD3 LD2 LD1 LD4 LD7 G H TX4_ TX2_ RX1 RX3 SCK T SRX D5 SCK 4 HCK T FSR VSS LD5 LD8 LD6 LD9 LD10 H J FST TX3_ TX5_ RX2 RX0 HCK R STX FS4 STX D4 FEC _RD ATA1 SCK R I2C2 _CL K FEC _RD ATA2 FEC _RX _ER R FEC _CO L NGN D_E MI2 NGN D_L CDC NGN D_C RM FUS E_V SS MGN D NGN D_E MI3 NGN D_E MI3 NGN D_L CDC VSS VDD LD12 LD14 LD11 LD13 LD15 J K STX D5 SRX D4 I2C2 _DAT FEC _RD ATA3 NVC NVC NGN NGN C_MI C_MI D_MI D_N SC SC SC FC FEC _TD ATA3 VDD VDD NVC C_MI SC VSS VSS VSS LD16 LD22 LD20 LD21 LD18 LD17 LD19 K L SCK 5 NGN D_A TA NGN D_M LB NGN D_C SI VSS NVC C_L CDC NVC C_L CDC USB PHY 1_U PLL GND NVC C_S DIO D3_ FPS HIFT PHY 1_V DDA USB PHY 1_U PLLV DD TDI CON TRA ST TTM _PIN PHY 1_V SSA D3_ CLS D3_ REV I2C1 _DAT D3_ HSY NC D3_ SPL USB PHY 1_UI D USB PHY 1_V BUS USB PHY 1_V SSA _BIA S OSC 24M _VS S RTC K LD23 D3_ DRD Y I2C1 _CL K PHY 1_V DDA L M FEC FEC _TD _TD ATA1 ATA2 FEC _TX_ ERR FEC _CR S NGN D_MI SC VDD NGN D_A TA VSS PGN NGN D D_JT AG NGN D_S DIO PVD D D3_ VSY NC USB PHY 1_D M USB PHY 1_D P USB PHY 1_R REF M N NVC C_A TA VSS N P FEC FEC _MDI _RD O ATA0 FEC FEC _TX_ _TD CLK ATA0 NVC C_A TA NVC C_A TA NVC C_A TA NGN D_A TA VSS MVD D PHY 2_V SS FUS E_V DD NVC C_JT AG USB PHY 1_U PLLV DD TCK PHY 1_V SSA P R FEC _MD C FEC _RX _CL K CTS 1 ATA_ ATA_ DA0 DA2 TXD 1 VDD VDD NVC C_C RM NVC C_M LB NVC C_C SI VDD PHY 2_V DD SD1 _DAT A0 TDO TMS USB PHY 1_V DDA _BIA S EXT AL24 M R T FEC _TX_ EN RTS 1 FEC _RX _DV RXD 1 ATA_ ATA_ ATA_ DMA DATA BUF RQ 15 F_E N ATA_ ATA_ CSPI RES CS1 1_S ET_ PI_R B DY USB OTG _OC VST BY CLK _MO DE1 RES ET_I N_B GPI O1_ 0 GPI O2_ 0 COM SD2 CSI_ PAR _DAT VSY E A1 NC SD2 _DAT A3 SD2 _CM D CSI_ D14 CSI_ D11 TRS TB VSS OSC 24M _VD D T U ATA_ ATA_ ATA_ ATA_ DATA DATA DATA IOR 12 8 3 DY CSPI BOO 1_S T_M S1 ODE 1 CSI_ SD1 D8 _DAT A1 SJC _MO D OSC XTAL _AU 24M DIO_ VSS U i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 141 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 92. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch (continued) 1 V 2 3 4 5 6 7 8 EXT _AR MCL K 9 CSPI 1_MI SO 10 CLK O 11 GPI O3_ 0 POR _B 12 CAP TUR E MLB _SIG 13 14 15 CSI_ D13 16 17 18 SD1 _CL K 19 20 V ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ DA1 INTR DATA DATA DATA DMA CS0 Q 10 6 2 CK USB OTG _PW R TES T_M ODE SD2 CSI_ _DAT HSY A0 NC MLB _CL K SD2 _CL K CSI_ SD1 D10 _DAT A3 CSI_ D12 XTAL OSC _AU _AU DIO DIO_ VDD DE_ B W ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ DATA DATA DATA DATA DATA DIO 14 13 9 5 1 W Y VSS ATA_ ATA_ ATA_ ATA_ ATA_ DATA DATA DATA DATA DIO 11 7 4 0 R CSPI CSPI BOO 1_S 1_M T_M CLK OSI ODE 0 CSPI POW 1_S ER_ S0 FAIL CLK _MO DE0 CSI_ MCL K CSI_ SD1 D9 _DAT A2 USB PHY 2_D M USB PHY 2_D P EXT W AL_ AUDI O VSS Y GPI O1_ 1 WD OG_ RST MLB SD2 CSI_ _DAT _DAT PIXC A2 LK CSI_ D15 SD1 _CM D Table 93. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch 1 A GND 2 D0 3 A9 4 A7 5 A0 6 SDB A0 SDB A1 A3 7 8 9 10 11 12 13 14 15 16 SD9 17 SD6 18 SD4 19 SD1 20 GND A SD30 SD27 SD24 SD23 SD21 SD18 SD15 SD14 SD10 B D5 D2 A13 A8 A5 SD31 SD28 SD26 SD22 SD20 SD19 SD12 SD13 SD11 SD7 SD0 SD2 DQM 0 CS3 CS2 B C D8 D7 D4 MA1 0 D1 A6 A23 SD29 SD25 A20 SD17 SD16 A17 SD8 SD5 SD3 DQM 1 SDC KE1 CAS DQM 3 SDC KE0 CS4 RW C D D14 D10 D6 A11 A4 A1 A24 A22 A21 A19 A18 A16 A14 A15 DQM 2 RAS ECB LBA D E NFC LE NFR E_B D15 D12 D9 D3 D11 A2 A25 SDQ S3 VDD 7 SDQ S2 GND SDQ S1 NVC C_E MI1 NVC C_E MI1 GND SDC LK VDD 7 SDC LK_B NVC C_E MI2 VDD 6 SDQ S0 GND BCL K A10 CS1 OE E F NFAL E NFR B NFW P_B D13 A12 VDD 7 VDD 7 EB1 CS0 EB0 CS5 LD0 F G RTS 2 NFW E_B NF_ CE0 TX0 CTS 2 NVC C_N FC NVC C_N FC STX FS5 NVC C_E MI1 NVC C_N FC VDD 1 NVC C_E MI1 GND NVC C_E MI1 NVC C_E MI1 GND NVC C_E MI1 NVC C_E MI1 GND NVC C_E MI2 GND NVC C_E MI3 NVC C_L CDC NVC C_L CDC SDW E LD3 LD2 LD1 LD4 LD7 G H TX1 TXD 2 RXD 2 TX4_ TX2_ RX1 RX3 NVC C_E MI2 GND VDD 5 LD5 LD8 LD6 LD9 LD10 H J FST TX3_ TX5_ RX2 RX0 SCK T HCK T GND GND GND VDD 5 LD12 LD14 LD11 LD13 LD15 J K STX D5 HCK R SCK R SRX D5 FSR NVC NVC C_MI C_MI SC SC FEC _TDA TA3 VDD 2 VDD 2 GND GND GND GND GND GND LD16 LD22 LD20 LD21 LD18 LD17 LD19 K L SRX D4 STX FS4 I2C2 _CLK SCK 4 SCK 5 NVC C_MI SC GND GND GND GND GND GND NVC C_L CDC NVC C_L CDC D3_F PSHI FT CON TRA ST D3_ CLS D3_ HSY NC LD23 D3_ DRD Y L M I2C2 _DAT STX D4 FEC FEC FEC _RD _TDA _TDA ATA2 TA1 TA2 FEC _CR S GND GND GND FUS E_V SS MGN D PGN D GND PHY TTM 1_VD _PAD DA D3_ REV D3_S D3_V I2C1 PL SYN _CLK C USB PHY 1_UI D USB PHY 1_D M PHY 1_VD DA M N FEC _RD ATA3 FEC FEC FEC _RD _RX_ _TX_ ATA1 ERR ERR NVC C_AT A VDD 3 GND GND GND GND PVD D USB USB PHY I2C1 PHY PHY 1_VS _DAT 1_UP 1_UP SA LLG LLVD ND D NVC C_S DIO TDI N P FEC _MDI O FEC _RD ATA0 FEC _CO L FEC FEC NVC NVC NVC _TX_ _TDA C_AT C_AT C_AT CLK TA0 A A A GND GND MVD D PHY 2_VS S FUS E_V DD NVC USB USB USB PHY C_JT PHY PHY PHY 1_VS AG 1_UP 1_VB 1_DP SA LLVD US D P i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 142 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 93. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch (continued) 1 R FEC _MD C 2 FEC _RX_ CLK 3 CTS 1 4 ATA_ DA0 5 ATA_ DA2 6 TXD 1 7 VDD 3 8 VDD 3 9 NVC C_C RM 10 NVC C_M LB 11 NVC C_C SI 12 VDD 4 13 14 15 TDO 16 TMS 17 TCK 18 USB PHY 1_VS SA_ BIAS 19 USB PHY 1_R REF 20 USB PHY 1_VD DA_ BIAS R PHY SD1_ 2_VD DATA D 0 T FEC FEC ATA_ _TX_ _RX_ DMA EN DV RQ ATA_ DATA 15 ATA_ BUF F_E N ATA_ RES ET_B ATA_ CSPI CS1 1_SP I_RD Y USB OTG _OC CSPI 1_SS 1 VST BY CLK_ GPIO COM SD2_ CSI_ MOD 1_0 PAR DATA VSY E1 E 1 NC CSI_ D11 TRS TB GND OSC OSC EXTA 24M_ 24M_ L24M VSS VDD T U RTS 1 RXD 1 ATA_ DATA 12 ATA_ ATA_ ATA_ DATA DATA IORD 8 3 Y BOO T_M ODE 1 RES ET_I N_B GPIO SD2_ SD2_ CSI_ 2_0 DATA CMD D14 3 CSI_ D8 SD1_ SJC_ DATA MOD 1 RTC K OSC _AU DIO_ VSS XTAL 24M U V ATA_ DA1 ATA_ INTR Q ATA_ DATA 10 ATA_ ATA_ DATA DATA 6 2 ATA_ DMA CK ATA_ EXT_ CSPI CS0 ARM 1_MI CLK SO CLK O GPIO 3_0 CAP TUR E SD2_ CSI_ DATA HSY 0 NC CSI_ D13 CSI_ D10 SD1_ SD1_ XTAL DATA CLK _AU DIO 3 OSC _AU DIO_ VDD EXTA L_AU DIO V W ATA_ DATA 14 ATA_ ATA_ DATA DATA 13 9 ATA_ ATA_ DATA DATA 5 1 ATA_ DIO W USB OTG _PW R TES T_M ODE CSPI CSPI 1_SC 1_M LK OSI BOO T_M ODE 0 POR _B MLB _SIG MLB SD2_ _CLK CLK CSI_ MCL K CSI_ D12 CSI_ D9 SD1_ DATA 2 DE_ B W Y GND ATA_ ATA_ DATA DATA 11 7 ATA_ ATA_ ATA_ DATA DATA DIOR 4 0 CSPI POW CLK_ GPIO WDO MLB SD2_ CSI_ 1_SS ER_ MOD 1_1 G_R _DAT DATA PIXC LK 0 FAIL E0 ST 2 CSI_ D15 USB PHY 2_D M 17 USB SD1_ PHY CMD 2_DP GND Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 6 7 Product Documentation Revision History Table 94. i.MX35 Data Sheet Revision History All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx. Table 94 shows the revision history of this document. Revision Number Date Substantive Change(s) 8 7 6 04/2010 • Updated Table 13, “I/O Pin DC Electrical Characteristics.” 12/18/2009 • Updated Table 1, “Ordering Information.” 10/21/2009 • • • • 08/06/2009 • • • • Added information for silicon rev. 2.1 Updated Table 1, “Ordering Information.” Added Table 91, “Silicon Revision 2.1 Signal Ball Map Locations.” Added Table 93, “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.” Added a line for TA = –40 to 85 oC in Table 13, “I/O Pin DC Electrical Characteristics” Filled in TBDs in Table 13. Revised Figure 15 and Table 30 by removing FCE = 0 and FCE = 1. Added footnote 3 to the table. Added Table 24, “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V).” 5 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor 143 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Table 94. i.MX35 Data Sheet Revision History (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Revision Number Date Substantive Change(s) 4 04/30/2009 • Added Section 4.4, “Reset Timing.” • In Section 4.8.2, “AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM Modes),” removed Slow Slew rate tables, relabeled Table 22, “AC Electrical Characteristics of DDR Type IO Pins in mDDR Mode,” and Table 23, “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode,” to exclude mention of slew rate. • In Section 4.9.5.2, “Wireless External Interface Module (WEIM),” modified Figure 16, “Synchronous Memory Timing Diagram for Read Access—WSC = 1,” through Figure 21, “Muxed A/D Mode Timing Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7.” • In Section 4.9.6, “Enhanced Serial Audio Interface (ESAI) Timing Specifications,” modified Figure 37, “ESAI Transmitter Timing,” and Figure 38, “ESAI Receiver Timing,” to remove extraneous signals. Removed a note from Figure 37, “ESAI Transmitter Timing.” 03/2009 02/2009 • In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6. • Added the following parts to Table 1, “Ordering Information”: PCIMX357CVM5B, MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Throughout consumer data sheet: Removed or updated information related to Media Local Bus interface.Updated Section 4.3.1, “Powering Up.” • Updated values in Table 9, “i.MX35 Power Modes.” • Updated Section 4.3.1, “Powering Up.” • Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR SDRAM timing. Inserted DDR2 SDRAM timing. Initial public release 3 2 1 12/2008 0 10/2008 i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 144 Freescale Semiconductor Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 145 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. 146 THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 8 147 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Document Number: MCIMX35SR2CEC Rev. 8 04/2010 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B.