MCIMX53XA

Freescale Semiconductor Data Sheet: Advance Information Document Number: IMX53AEC Rev. 1, 3/2011 MCIMX53xA This document contains information on a new product. Specifications and information herein are subject to change without notice. i.MX53xA Automotive and Infotainment Applications Processors 1 Introduction 1. Package Information Plastic Package Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch Ordering Information See Table 1 on page 3 The MCIMX53xA (i.MX53xA) automotive infotainment processor is Freescale Semiconductor’s latest addition to a growing family of multimedia-focused products offering high performance processing with a high degree of functional integration aimed at the growing automotive infotainment, telematics, HMI, and display-based cluster markets. This device includes 3D and 2D graphics processors, 1080i/p video processing, and dual display, and provides a variety of interfaces. The i.MX53xA processor features Freescale’s advanced implementation of the ARM™ core, which operates at clock speeds as high as 800 MHz and interfaces with DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800 DRAM memories. This device is well-suited for graphics rendering for HMI and navigation, high performance speech processing with large databases, video processing and display, audio playback, and many other applications. The flexibility of the i.MX53xA architecture allows for its use in a wide variety of applications. As the heart of the application chipset, the i.MX53xA processor 2. 3. 4. 5. 6. 7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3 1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17 4.2. Power Supplies Requirements and Restrictions . 24 4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4. Output Buffer Impedance Characteristics . . . . . . 34 4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36 4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 43 4.7. External Peripheral Interfaces Parameters . . . . . . 64 4.8. XTAL and CKIL Electricals . . . . . . . . . . . . . . . . . 151 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 152 5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 152 5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 153 5.3. Power setup during Boot . . . . . . . . . . . . . . . . . . 154 Package Information and Contact Assignments . . . . . 155 6.1. 19x19 mm Package Information . . . . . . . . . . . . . 155 6.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 174 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2011 Freescale Semiconductor, Inc. All rights reserved. Introduction provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, camera sensors, and dual displays. Features of the i.MX53xA processor include the following: • Multilevel memory system—The multilevel memory system of the i.MX53xA is based on the L1 instruction and data caches, L2 cache, internal and external memory. The i.MX53xA supports many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3, NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND including eMMC up to rev 4.4. • Smart speed technology—The i.MX53xA device has power management throughout the IC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart Speed Technology enables the designer to deliver a feature-rich product requiring levels of power far lower than industry expectations. • Multimedia powerhouse—The multimedia performance of the i.MX53xA processor ARM core is boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision floating point support) and vector floating point coprocessors. The system is further enhanced by a multistandard hardware video codec, autonomous image processing unit (IPU), and a programmable smart DMA (SDMA) controller. • Powerful graphics acceleration— The i.MX53xA processors provide two independent, integrated graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator (200 Mpix/s). • Interface flexibility—The i.MX53xA processor supports connection to a variety of interfaces, including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed MMC/SDIO host and other), 10/100 Ethernet controller, and a variety of other popular interfaces (PATA, UART, I2C, and I2S serial audio, among others). • Automotive environment support—Includes interfaces such as two CAN ports, an MLB port, an ESAI audio interface, and an asynchronous sample rate converter for multichannel/multisource audio. • Advanced security—The i.MX53xA processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. For detailed information about the i.MX53xA security features contact a Freescale representative. The i.MX53xA application processor is a follow-on to the i.MX51xA, with improved performance, power efficiency, and multimedia capabilities. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 2 Freescale Semiconductor Introduction 1.1 Ordering Information Table 1. Ordering Information Part Number Mask Set N78C Features 800 MHz, full feature set — Package1 19 x 19 mm, 0.8 mm pitch BGA Case TEPBGA-2 Table 1 provides ordering information. PCIMX536AVV8B 1 Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3. 1.2 Features The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the following features: • MMU, L1 instruction and L1 data cache • Unified L2 cache • Target frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz • Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite) coprocessor supporting VFPv3 • TrustZone The memory system consists of the following components: • Level 1 cache: — Instruction (32 Kbyte) — Data (32 Kbyte) • Level 2 cache: — Unified instruction and data (256 Kbyte) • Level 2 (internal) memory: — Boot ROM, including HAB (64 Kbyte) — Internal multimedia/shared, fast access RAM (128 Kbyte) — Secure/non-secure RAM (16 Kbyte) • External memory interfaces: — 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte — 32bit LPDDR2 — 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC — 8,16-bit NOR Flash, PSRAM & cellular RAM. — 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM. — 8-bit Asynchronous (DTACK mode) EIM interface. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 3 Introduction — All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM port, as primary muxing at system boot. — Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O mode) The i.MX53xA system is built around the following system on chip interfaces: • 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU, GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz. • 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz. • 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz. The i.MX53xA makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks. The i.MX53xA incorporates the following hardware accelerators: • VPU, version 3—video processing unit • GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance, 256 Kbyte RAM memory • GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance, • IPU, version 3M—image processing unit • ASRC—asynchronous sample rate converter The i.MX53xA includes the following interfaces to external devices: NOTE Not all interfaces are available simultaneously, depending on I/O multiplexer configuration. • Hard disk drives: — PATA, up to U-DMA mode 5, 100 MByte/s — SATA I, 1.5 Gbps Displays: — Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two interfaces may be active at once. — Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example, UXGA @ 60 Hz). — LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports up to 85 MP/s (for example, WXGA @ 60 Hz) each. — TV-out/VGA port up to 150 Mpix/s (for example, 1080p60). Camera sensors: — Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up to 120-MHz peak clock frequency. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 4 Freescale Semiconductor • • Introduction • • • • Expansion cards: — Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port supporting 832 Mbps (8-bit, eMMC 4.4). USB — High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – High-speed host with integrated on-chip high-speed PHY – Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB Automotive environment interfaces: — Two controller area network (FlexCAN) interfaces, 1 Mbps each — Media local bus or MediaLB (MLB) provides interface to most networks (50 Mbps) — Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel Miscellaneous interfaces: — One-wire (OWIRE) port — Three I2S/SSI/AC97ports, supporting up to 1.4 Mbps, each connected to audio multiplexer (AUDMUX) providing four external ports. — Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support 4-wire. — Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port — Three I2C ports, supporting 400 kbps — Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps — Sony Phillips Digital Interface (SPDIF), Rx and Tx — Key pad port (KPP) — Two pulse-width modulators (PWM) — GPIO with interrupt capabilities — Secure JTAG controller (SJC) The system supports efficient and smart power control and clocking: • Power gating SRPG (State Retention Power Gating) for ARM core and Neon • Support for various levels of system power modes • Flexible clock gating control scheme • On-chip temperature monitor • On-chip oscillator amplifier supporting 32.768 kHz external crystal • On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 5 Architectural Overview • • • • • • • Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator (TRNG) Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure RAM and support for multiple keys as well as TZ/non-TZ separation Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is configured during boot by e-fuses, and determines the security level operation mode as well as the TrustZone (TZ) policy Advanced High Assurance Boot (A-HAB)—HAB with the next embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization NOTE The actual feature set depends on the part number as described in Table 1. Functions such as video hardware acceleration, 2D and 3D hardware graphics acceleration, and MacrovisionTM video copy protection may not be enabled for specific part numbers. 2 Architectural Overview The following subsections provide an architectural overview of the i.MX53xA processor system. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 6 Freescale Semiconductor Architectural Overview 2.1 Block Diagram Figure 1 shows the functional modules in the i.MX53xA processor system. Composite CVBS/ S-Video Component RGB, YCC (HD TV-Out / VGA) DDR2/DDR3/ LPDDR2 NOR/NAND Battery Ctrl Flash Device Camera Camera (2) (2) LVDS (WSXGA+) LCD LCD Display-1,2 Display (2) Digital Audio External Memory I/F (EXTMC) Application Processor Domain (AP) Internal RAM 144 KB Boot ROM 64 KB Debug DAP CTI (2) AXI and AHB Switch Fabric TPIU LDB TV-Encoder Temperature Sensor SATA / P-ATA HDD Smart DMA (SDMA) Image Processing Subsystem (IPU) ARM Cortex A8 Platform ARM Cortex A8 Neon, VFPv3 L1 I/D cache L2 cache 256 KB ETM, CTI0,1 Clock and Reset PLL (4) CCM GPC SRC XTALOSC (2) CAMP (2) AP Peripherals ECSPI CSPI UART (4) AUDMUX I2C (3) OWIRE PWM (2) IIM IOMUXC KPP GPIOx32 (7) SSI (2) FIRI FlexCAN (2) FEC(IEEE1588) MLB CAN i/f SPBA GPS Shared Peripherals eSDHCv2 (3) eSDHCv3 SSI ECSPI ESAI P-ATA SATA + Temp Mon SJC RF/IF UART SPDIF Rx/Tx ASRC Security SAHARAv4 Lite RTICv3 SCCv2 SRTC CSU TZIC Video Proc. Unit (VPU) 3D Graphics Proc. Unit (GPU3D) G-Memory 256 KB RF / IF IC’s Audio, Power Mngmnt. Ethernet 10/100 Mbps Fuse Box Timers WDOG (2) GPT EPIT (2) 2D Graphics Proc. Unit (GPU2D) USB PHY1 USB PHY2 USB OTG + 3 HS Ports IrDA XVR Keypad Bluetooth WLAN JTAG (IEEE1149.1) MMC/SD eMMC/eSD USB OTG (dev/host) Access. Conn. Figure 1. i.MX53xA System Block Diagram NOTE The numbers in brackets indicate number of module instances. For example, PWM (2) indicates two separate PWM peripherals. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 7 Modules List 3 Modules List Table 2. i.MX53xA Digital and Analog Blocks The i.MX53xA processor contains a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Block Mnemonic ARM Block Name ARM Platform Subsystem ARM Brief Description The ARM Cortex A8TM Platform consists of the ARM processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a 256 Kbyte L2 cache. The platform also contains an event monitor and debug modules. It also has a NEON coprocessor with SIMD media processing architecture, a register file with 32/64-bit general-purpose registers, an integer execute pipeline (ALU, Shift, MAC), dual single-precision floating point execute pipelines (FADD, FMUL), a load/store and permute pipeline and a non-pipelined vector floating point (VFP Lite) coprocessor supporting VFPv3. The asynchronous sample rate converter (ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about –120 dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs. The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The AUDMUX has seven ports (three internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports. ASRC Asynchronous Sample Rate Converter Multimedia Peripherals AUDMUX Digital Audio Multiplexer Multimedia Peripherals CAMP-1 CAMP-2 CCM GPC SRC CSPI ECSPI-1 ECSPI-2 CSU Clock Amplifier Clocks, Clock amplifier Resets, and Power Control Clocks, These modules are responsible for clock and reset distribution in the Resets, and system, as well as for system power management. Power Control The system includes four PLLs. Clock Control Module Global Power Controller System Reset Controller Configurable SPI, Enhanced CSPI Central Security Unit Connectivity Peripherals Security Full-duplex enhanced synchronous serial interface, with data rates 16-60 Mbit/s. It is configurable to support master/slave modes. In Master mode it supports four slave selects for multiple peripherals. The central security unit (CSU) is responsible for setting comprehensive security policy within the i.MX53xA platform, and for sharing security information between the various security modules. The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 8 Freescale Semiconductor Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic DEBUG Block Name Debug System Subsystem System Control Brief Description The debug system provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). Real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, three cross-system triggers (CTI), counters, and sequencers. debug access port (DAP) —The DAP provides real-time access for the debugger without halting the core to system memory, peripheral register, debug configuration registers and JTAG scan chains. The EXTMC is an external and internal memory interface. It performs arbitration between multi-AXI masters to multi-memory controllers, divided into four major channels, fast memories (DDR2/DDR3/LPDDR2) channel, slow memories (NOR-FLASH / PSRAM / NAND-FLASH etc.) channel, internal memory (RAM, ROM) channel and graphical memory (GMEM) channel. In order to increase the bandwidth performance, the EXTMC separates the buffering and the arbitration between different channels so parallel accesses can occur. By separating the channels, slow accesses do not interfere with fast accesses. EXTMC Features: • 64-bit and 32-bit AXI ports • Enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (read or write) was the last access • Flexible bank interleaving • Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2. • Support up to 2 GByte DDR memories. • Support NFC, EIM signal muxing scheme. • Support 8/16/32-bit Nor-Flash/PSRAM memories (sync and async operating modes), at slow frequency. (8-bit is not supported on D[23]-D[16]). • Support 4/8/14/16-bit ECC, page sizes of 512-B, 2-KB and 4-KB Nand-Flash (including MLC) • Multiple chip selects (up to 4). • Enhanced DDR memory controller, supporting access latency hiding • Support watermark for security (internal and external memories) Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. The enhanced serial audio interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. The ESAI has 12 pins for data and clocking connection to external devices. EXTMC External Memory Connectivity Controller Peripherals EPIT-1 EPIT-2 Enhanced Timer Periodic Interrupt Peripherals Timer ESAI Enhanced Serial Audio Interface Connectivity Peripherals i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 9 Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic Block Name Subsystem Connectivity Peripherals Brief Description Ultra high-speed eMMC / SD host controller, enhanced to support eMMC 4.4 standard specification, for 832 MBps. • Port 3 is specifically enhanced to support eMMC 4.4 specification, for double data rate (832 Mbps, 8-bit port). ESDHCV3 is backward compatible to ESDHCV2 and supports all the features of ESDHCV2 as described below. Enhanced multimedia card / secure digital host controller • Ports 1, 2, and 4 are compatible with the “MMC System Specification” version 4.3, full support and supporting 1, 4 or 8-bit data. The generic features of the eSDHCv2 module, when serving as SD / MMC host, include the following: • Can be configured either as SD / MMC controller • Supports eSD and eMMC standard, for SD/MMC embedded type cards • Conforms to SD Host Controller Standard Specification, version 2.0, full support. • Compatible with the SD Memory Card Specification, version 1.1 • Compatible with the SDIO Card Specification, version 1.2 • Designed to work with SD memory, miniSD memory, SDIO, miniSDIO, SD Combo, MMC and MMC RS cards • Configurable to work in one of the following modes: - SD/SDIO 1-bit, 4-bit - MMC 1-bit, 4-bit, 8-bit • Full/high speed mode. • Host clock frequency variable between 32 kHz to 52 MHz • Up to 200 Mbps data transfer for SD/SDIO cards using 4 parallel data lines • Up to 416 Mbps data transfer for MMC cards using 8 parallel data lines Connectivity Peripherals The Ethernet media access controller (MAC) is designed to support both 10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The i.MX53xA also consists of HW assist for IEEE1588™ standard. See, TSU and CE_RTC (IEEE1588) section for more details. Fast infrared interface The controller area network (CAN) protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus. Meets the following specific requirements of this application: real-time processing, reliable operation in the EXTMC environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN is a full implementation of the CAN protocol specification, Version 2.0 B (ISO 11898), which supports both standard and extended message frames at 1 Mbps. ESDHCV3-3 Ultra-HighSpeed eMMC / SD Host Controller ESDHCV2-1 Enhanced ESDHCV2-2 Multi-Media Card ESDHCv2-4 / Secure Digital Host Controller FEC Fast Ethernet Controller FIRI FLEXCAN-1 FLEXCAN-2 Fast Infrared Interface Flexible Controller Area Network Connectivity Peripherals Connectivity Peripherals i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 10 Freescale Semiconductor Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPIO-5 GPIO-6 GPIO-7 GPT Block Name Subsystem Brief Description These modules are used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. General Purpose System I/O Modules Control Peripherals General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register. A timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. The GPU, version 3, provides hardware acceleration for 2D and 3D graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution. It supports color representation up to 32 bits per pixel. GPU enables high-performance mobile 3D and 2D vector graphics at rates up to 33 Mtriangles/s, 200 Mpix/s, 800 Mpix/s (z). The GPU2D version 1, provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution. I2C provides serial interface for controlling peripheral devices. Data rates of up to 400 kbps are supported. The IC identification module (IIM) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. IIM interfaces to the electrical fuse array (split to banks). Enables to set up boot modes, security levels, security keys and many other system parameters. i.MX53A consists of 4 x 256-bit + 1x 128-bit fuse-banks (total 1152 bits) through IIM interface. GPU3D Graphics Processing Unit Multimedia Peripherals GPU2D Graphics Processing Unit-2D I2C Controller Multimedia Peripherals Connectivity Peripherals Security I2C-1 I2C-2 I2C-3 IIM IC Identification Module i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 11 Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic IOMUXC Block Name IOMUX Control Subsystem System Control Peripherals Multimedia Peripherals Brief Description This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. Version 3M IPU enables connectivity to displays, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces: • Legacy parallel interfaces • Single/dual channel LVDS display interface • Analog TV or VGA interfaces The processing includes: • Image enhancement—color adjustment and gamut mapping, gamma correction and contrast enhancement • Video/graphics combining • Support for display backlight reduction • Image conversion—resizing, rotation, inversion and color space conversion • Hardware de-interlacing support • Synchronization and control capabilities, allowing autonomous operation. The KPP supports an 8 × 8 external keypad matrix. The KPP features are as follows: • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection LVDS display bridge is used to connect the IPU (image processing unit) to external LVDS display interface. LDB supports two channels; each channel has following signals: • 1 clock pair • 4 data pairs On-chip differential drivers are provided for each pair. The MLB interface module provides a link to a MOST® data network, using the standardize MediaLB protocol (up to 50 Mbps). One-wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example, Dallas DS2502. The PATA block is a AT attachment host interface. Its main use is to interface with hard disk drives and optical disc drives. It interfaces with the ATA-6 compliant device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side. The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound. IPU Image Processing Unit KPP Keypad Port Connectivity Peripherals LDB LVDS Display Bridge Connectivity Peripherals MLB Media local bus—MediaLB One-Wire Interface Parallel ATA Connectivity/ Multimedia Peripherals Connectivity Peripherals Connectivity Peripherals OWIRE PATA PWM-1 PWM-2 Pulse Width Modulation Connectivity Peripherals i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 12 Freescale Semiconductor Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic INTRAM Block Name Internal RAM Subsystem Internal Memory Brief Description Internal RAM, shared with VPU. The on-chip memory controller (OCRAM) module, is an interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. Supports secure and regular boot modes. The ROM controller supports ROM patching. Protecting read only data from modification is one of the basic elements in trusted platforms. The run-time integrity checker, version 3 (RTIC) block is a data-monitoring device responsible for ensuring that the memory content is not corrupted during program execution. The RTIC mechanism periodically checks the integrity of code or data sections during normal OS run-time execution without interfering with normal operation. The purpose of the RTIC is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement and assist with boot authentication. SAHARA (symmetric/asymmetric hashing and random accelerator), version 4, is a security coprocessor. It implements symmetric encryption algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and a hardware true random number generator. It has a slave IP Bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an AHB bus interface, to reduce the burden on the host to move the required data to and from memory. SATA HDD interface, includes the SATA controller and the PHY. It is a complete mixed-signal IP solution for SATA HDD connectivity. The security controller is a security assurance hardware module designed to safely hold sensitive data, such as encryption keys, digital right management (DRM) keys, passwords and biometrics reference data. The SCCv2 monitors the system’s alert signal to determine if the data paths to and from it are secure, that is, it cannot be accessed from outside of the defined security perimeter. If not, it erases all sensitive data on its internal RAM. The SCCv2 also features a key encryption module (KEM) that allows non-volatile (external memory) storage of any sensitive data that is temporarily not in use. The KEM utilizes a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data. BOOTROM RTIC Boot ROM Internal Memory Real Time Security Integrity Checker SAHARA SAHARA Security Accelerator Security SATA SCCv2 Serial ATA Security Controller, ver. 2 Connectivity Peripherals Security i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 13 Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic SDMA Block Name Smart Direct Memory Access Subsystem System Control Peripherals Brief Description The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off loading various cores in dynamic data routing. The SDMA features list is as follows: • Powered by a 16-bit instruction-set micro-RISC engine • Multi-channel DMA supports up to 32 time-division multiplexed DMA channels • 48 events with total flexibility to trigger any combination of channels • Memory accesses including linear, FIFO, and 2D addressing • Shared peripherals between ARM and SDMA • Very fast context-switching with two-level priority-based preemptive multi-tasking • DMA units with auto-flush and prefetch capability • Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) • DMA ports can handle unidirectional and bidirectional flows (copy mode) • Up to 8-word buffer for configurable burst transfers to / from the EXTMC • Support of byte swapping and CRC calculations • A library of scripts and API is available Secure / non-secure Internal RAM, controlled by SCC. JTAG manipulation is a known hacker’s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The JTAG port provides a debug access to several hardware blocks including the ARM processor and the system bus. The JTAG port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. However, in order to properly secure the system, unauthorized JTAG usage should be strictly forbidden. In order to prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the i.MX53xA processor incorporates a mechanism for regulating JTAG access. SJC provides four different JTAG security modes that can be selected through an e-fuse configuration. SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP bus) arbiter. A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Both transmitter and receiver functionalists are supported. SECRAM SJC Secure / Internal Non-secure RAM Memory Secure JTAG Interface System Control Peripherals SPBA Shared Peripheral Bus Arbiter Sony Philips Digital Interface System Control Peripherals Multimedia Peripherals SPDIF i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 14 Freescale Semiconductor Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic SRTC Block Name Secure Real Time Clock Subsystem Security Brief Description The SRTC incorporates a special system state retention register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized separately even if all other supply rails are shut down. The power for this block comes from NVCC_SRTC_POW supply. When this supply is driven by the MC13892 power management controller, this block can be power backed up through the coin-cell feature of the MC13892. This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR mark the event (security violation indication). The SSI is a full-duplex synchronous interface used on the i.MX53A processor to provide connectivity with off-chip audio peripherals. The SSI interfaces connect internally to the AUDMUX for mapping to external ports. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options. Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two time slots are being used simultaneously. The IEEE 1588-2002 (version 1) standard defines a precision time protocol (PTP) - which is a time-transfer protocol that enables synchronization of networks (for example, Ethernet), to a high degree of accuracy and precision. The IEEE1588 hardware assist is composed of the two blocks: time stamp unit and real time clock, which provide the timestamping protocol’s functionality, generating and reading the needed timestamps. The hardware-assisted implementation delivers more precise clock synchronization at significantly lower CPU load compared to purely software implementations. The temperature sensor is an internal module to the i.MX53xA that monitors the die temperature. The monitor is capable in generating SW interrupt, or trigger the CCM, to reduce the core operating frequency. The TV encoder, version 2.1 is implemented in conjunction with the image processing unit (IPU) allowing handheld devices to display captured still images and video directly on a TV or LCD projector. It supports composite PAL/NTSC, VGA, S-video, and component up to HD1080p analog video outputs. The TrustZone interrupt controller (TZIC) collects interrupt requests from all i.MX53xA sources and routes them to the ARM core. Each interrupt can be configured as a normal or a secure interrupt. Software Force Registers and software Priority Masking are also supported. SSI-1 SSI-2 SSI-3 I2S/SSI/AC97 Interface Connectivity Peripherals IPTP IEEE1588 Precision Time Protocol Connectivity Peripherals Temperature Monitor TVE (Part of SATA Block) TV Encoder System Control Peripherals Multimedia TZIC TrustZone Aware ARM/Control Interrupt Controller i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 15 Modules List Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic UART-1 UART-2 UART-3 UART-4 UART-5 Block Name UART Interface Subsystem Connectivity Peripherals Brief Description Each of the UART blocks supports the following serial data transmit/receive protocols and configurations: • 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) • Programmable bit-rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F standard. • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud • IrDA 1.0 support (up to SIR speed of 115200 bps) • Option to operate as 8-pins full UART, DCE, or DTE USB supports USB2.0 480 MHz, and contains: • One high-speed OTG sub-block with integrated HS USB PHY • One high-speed host sub-block with integrated HS USB PHY • Two identical high-speed Host modules The high-speed OTG module, which is internally connected to the HS USB PHY, is equipped with transceiver-less logic to enable on-board USB connectivity without USB transceivers All the USB ports are equipped with standard digital interfaces (ULPI, HS IC-USB) and transceiver-less logic to enable onboard USB connectivity without USB transceivers. A high-performing video processing unit (VPU) version 3, which covers many SD-level video decoders and SD-level encoders as a multi-standard video codec engine as well as several important video processing such as rotation and mirroring. VPU Features: • MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit rate • MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps bit rate • H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate • Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate • H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit rate • VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit rate • RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate • DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate • MJPEG decode, Baseline profile, up to 8192 x 8192 resolution, 40 Mpixel/s bit rate for 4:4:4 format • MPEG21 encode, Main-Main profile, up to D1 resolution, 15 Mbps bit rate • MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate2 • H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate2 • H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate2 • MJPEG encode, Baseline profile, up to 8192 x 8192 resolution, 80 Mpixel/s bit rate for 4:2:2 format The watch dog timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line. USB USB Controller Connectivity Peripherals VPU Video Processing Multimedia Unit Peripherals WDOG-1 Watch Dog Timer Peripherals i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 16 Freescale Semiconductor Electrical Characteristics Table 2. i.MX53xA Digital and Analog Blocks (continued) Block Mnemonic WDOG-2 (TZ) Block Name Watch Dog (TrustZone) Subsystem Timer Peripherals Brief Description The TrustZone watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. This situation should be avoided, as it can compromise the system’s security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. If it is still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW. Provides a crystal oscillator amplifier that supports a 24-MHz external crystal Provides a crystal oscillator amplifier that supports a 32.768-kHz external crystal. XTALOSC XTALOSC_ 32K 1 2 24 MHz Crystal Oscillator Clocking Clocking 32.768 KHz Crystal Oscillator I/F Video partially performed in hardware accelerator (70%) and partially in software. VPU can generate higher bit rate than the maximum specified by the corresponding standard. 3.1 Special Signal Considerations Special signal consideration information is contained in Chapter 1 of i.MX53 System Development User's Guide. The package contact assignments can be found in Section 6, “Package Information and Contact Assignments.” Signal descriptions are defined in i.MX53xA Reference Manual. 4 Electrical Characteristics NOTE This electrical specification is preliminary. These specifications are not fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after thorough characterization and device qualifications have been completed. This section provides the device and module-level electrical characteristics for the i.MX53xA processor. 4.1 Chip-Level Conditions This section provides the device-level electrical characteristics for the IC. See Table 3 for a quick reference to the individual tables and sections. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 17 Electrical Characteristics Table 3. i.MX53xA Chip-Level Conditions For these characteristics, … Absolute Maximum Ratings Package Thermal Resistance Data i.MX53xA Operating Ranges External Clock Sources Maximal Supply Currents USB Interface Current Consumption Topic appears … Table 4 on page 18 Table 5 on page 19 Table 6 on page 19 Table 7 on page 22 Table 8 on page 22 Table 9 on page 24 4.1.1 Absolute Maximum Ratings CAUTION Stresses beyond those listed under Table 4 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Table 6 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 4. Absolute Maximum Ratings Parameter Description Symbol VCC VDDGP Supplies denoted as I/O Supply Supplies denoted as I/O Supply VBUS USB_DP/USB_DN Vin/Vout Vesd — — TSTORAGE –40 2000 500 150 V oC Min –0.3 –0.3 –0.5 –0.5 — –0.3 –0.5 Max 1.35 1.35 3.6 3.3 5.25 3.631 OVDD +0.32 Unit V V V V V V V Peripheral Core Supply Voltage ARM Core Supply Voltage Supply Voltage UHVIO Supply Voltage for non UHVIO USB VBUS Input voltage on USB_OTG_DP, USB_OTG_DN, USB_H1_DP, USB_H1_DN pins Input/Output Voltage Range ESD Damage Immunity: Human Body Model (HBM) Charge Device Model (CDM) Storage Temperature Range 1 2 USB_DN and USB_DP can tolerate 5 V for up to 24 hours. The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in Table 112 on page 159. The maximum range can be superseded by the DC tables. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 18 Freescale Semiconductor Electrical Characteristics 4.1.2 Thermal Resistance Table 5. Package Thermal Resistance Data Rating Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — — Symbol RθJA RθJA RθJMA RθJMA RθJB RθJC ΨJT Value 28 16 21 13 6 4 4 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Table 5 provides the package thermal resistance data. Junction to Ambient (natural convection)1, 2 Junction to Ambient (natural convection)1, 2, 3 Junction to Ambient (@200 ft/min)1, 3 Junction to Ambient (@200 ft/min)1, 3 Junction to Board4 Junction to Case5 Junction to Package Top (natural convection)6 1 2 3 4 5 6 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 4.1.3 Operating Ranges Table 6 provides the operating ranges of i.MX53xA processor. Table 6. i.MX53xA Operating Ranges Symbol Parameter ARM core supply voltage fARM ≤ 800 MHz ARM core supply voltage Stop mode Peripheral supply voltage VCC VDDA3 Peripheral supply voltage—Stop mode Memory arrays voltage Memory arrays voltage—Stop mode Minimum1 Nominal2 Maximum1 1.05 0.8 1.25 0.9 1.25 0.9 1.1 0.85 1.3 0.95 1.30 0.95 1.15 1.15 1.35 1.35 1.35 1.35 Unit V V V V V V VDDGP i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 19 Electrical Characteristics Table 6. i.MX53xA Operating Ranges (continued) Symbol VDDAL13 VDD_DIG_PLL 4 Parameter L1 Cache Memory arrays voltage L1 Cache Memory arrays voltage—Stop mode PLL Digital supplies—external regulation option PLL Analog supplies—external regulator option ESD protection of the CKIH pins, FUSE read Supply and 1.8V bias for the UHVIO pads GPIO digital power supplies LVDS interface Supply LVDS Band Gap Supply DDR Supply DDR2 range DDR Supply LPDDR2 range Minimum1 Nominal2 Maximum1 1.25 0.9 1.25 1.75 1.65 1.65 2.25 2.25 1.7 1.14 1.47 1.30 0.95 1.3 1.8 1.8 1.8 or 2.775 2.5 2.5 1.8 1.2 1.55 1.5 1.5 — 1.35 1.35 1.35 1.95 1.95 3.1 2.75 2.75 1.9 1.3 1.63 1.58 1.58 3.3 Unit V V V V V V V V VDD_ANA_PLL5 NVCC_CKIH NVCC_LCD NVCC_JTAG NVCC_LVDS NVCC_LVDS_BG NVCC_EMI_DRAM DDR Supply LV-DDR2 range V 1.42 DDR Supply DDR3 range VDD_FUSE6 NVCC_NANDF NVCC_SD1 NVCC_SD2 NVCC_PATA NVCC_KEYPAD NVCC_GPIO NVCC_FEC NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_CSI Fusebox Program Supply (Write Only) Ultra High voltage I/O (UHVIO) supplies UHVIO_L UHVIO_H 1.65 2.5 1.42 3.0 V 1.8 2.775 1.95 3.1 V UHVIO_UH 3.0 3.3 3.6 TVDAC_DHVDD7 TVDAC_AHVDDRGB7 TVE digital and analog power supply, TVE-to-DAC level shifter supply, cable detector supply, analog power supply to RGB channel For GPIO use only, when TVE is not in use 2.69 2.75 2.91 V 1.65 1.25 1.65 2.25 1.8 or 2.775 1.3 1.8 or 2.775 2.5 3.1 1.35 3.1 2.75 V V V V NVCC_SRTC_POW NVCC_RESET USB_H1_VDDA25 USB_OTG_VDDA25 NVCC_XTAL USB_H1_VDDA33 USB_OTG_VDDA33 SRTC Core and slow I/O Supply (GPIO)8 LVIO USB_PHY analog supply, oscillator amplifier analog supply9 USB PHY I/O analog supply 3.0 3.3 3.6 V i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 20 Freescale Semiconductor Electrical Characteristics Table 6. i.MX53xA Operating Ranges (continued) Symbol VBUS VDD_REG10 VP VPH TJ 1 Parameter See Table 4 on page 18 and Table 104 on page 151 for details. Note that this is not a power supply. Power supply input for the integrated linear regulators SATA PHY core power supply. SATA PHY I/O supply voltage Junction Temperature Minimum1 Nominal2 Maximum1 — 2.37 1.25 2.25 –40 — 2.5 1.3 2.5 10511 — 2.63 1.35 2.75 125 Unit — V V V o C Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design must allow for supply tolerances and system voltage drops. 2 The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings. 3 VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this configuration, the regulator is still operating at the default 1.2V, as bootup start. This is acceptable for boot modes when connecting any or all of these supplies to the internal on-die LDO regulator. During bootup initialization, software should increase this regulator voltage to match VCC (1.3V nominal) in order to reduce internal leakage current. 4 By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide. 5 By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide. 6 In case the VDD_FUSE is kept powered on during Fuse Read mode, the efuse_prog_supply_gate bit in CCM_CGPR register should be kept low, to avoid the possibility of inadvertently blowing fuses. Alternately, VDD_FUSE can be ground or left floating, when not in Fuse Write mode. 7 If not using TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain floating. 8 GPIO pad operational at low frequency 9 The analog supplies should be isolated in the application design. Use of series inductors is recommended. 10 VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source. 11 Lifetime of 43,800 hours based on 105 C junction temperature at nominal supply voltages. 4.1.4 External Clock Sources The i.MX53xA device has four external input system clocks, a low frequency (CKIL), a high frequency (XTAL), and two general purpose CKIH1 and CKIH2 clocks. The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 21 Electrical Characteristics The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and accurate frequencies. Table 7 shows the interface frequency requirements. Table 7. External Input Clock Frequency Parameter Description CKIL Oscillator1 CKIH1, CKIH2 Operating Frequency XTAL Oscillator 1 2 Symbol fckil fckih1, fckih2 fxtal Min — Typ 32.7682/32.0 Max — Unit kHz MHz MHz See Table 31, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 44 22 24 27 External oscillator or a crystal with internal oscillator amplifier. Recommended nominal frequency 32.768 kHz. 4.1.5 Maximal Supply Currents Table 8 represents the maximal momentary current transients on power lines, and should be used for power supply selection. Maximal currents higher by far than the average power consumption of typical use cases. For typical power consumption information, see i.MX53xA power consumption application note. Table 8. Maximal Supply Currents Power Line VDDGP VCC VDDA+VDDAL1 VDD_DIG_PLL VP VDD_ANA_PLL MVCC_XTAL VDD_REG VDD_FUSE Fuse Write Mode operation 1.8v (DDR2) NVCC_EMI_DRAM 1.5v (DDR3) 1.2v (LPDDR2) TVDAC_DHVDD + TVDAC_AHVDDRGB Conditions 800MHz ARM clock. Max Current 1450 800 100 10 20 10 25 325 60 800 650 250 200 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 22 Freescale Semiconductor Electrical Characteristics Table 8. Maximal Supply Currents (continued) Power Line NVCC_SRTC_POW USB_H1_VDDA25 + USB_OTG_VDDA25 USB_H1_VDDA33 + USB_OTG_VDDA33 VPH NVCC_CKIH NVCC_CSI NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_EMI_DRAM NVCC_FEC NVCC_GPIO NVCC_JTAG NVCC_KPAD NVCC_LCD NVCC_LVDS NVCC_LVDS_BG NVCC_NANDF NVCC_PATA NVCC_REST NVCC_SD1 NVCC_SD2 NVCC_XTAL 1 Conditions Max Current 0 NVCC_CKIH IO Supplies below or equal to 2.8 V nom./3.1 V max. (in any order, after NVCC_CKIH ramp up start, if needed) Δt > 0 IO Supplies above 2.8 V nom./3.1 V max (in any order, if needed) Δt > 0 VDD_REG 90% 90% 90% 90% 90% Δt > 0 90% Δt > 0 Δt > 0 NVCC_EMI_DRAM 90% Δt > 0 VDDA,VDDAL1,VDDGP (in any order) 90% Δt > 0 VP, VPH (in any order) POR_B pin released by Power Management IC 90% Δt > 0 Figure 2. Power Up Detailed Sequence 1 NOTE Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the parts that use both 1.8 V and the 3.3 V supply). 1. If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 26 Freescale Semiconductor Electrical Characteristics 4.2.2 Power-Down Sequence Power-down sequence should follow one of the following two options: Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few microseconds of actual power-down of the different power rails is acceptable. Option 2: Switch down supplies, in any order, keeping the following rules: • NVCC_CKIH must be powered down at the same time or after the UHVIO IO cell supplies. A deviation of few microseconds of actual power-down of the different power rails is acceptable. • VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A deviation of few microseconds of actual power-down of the different power rails is acceptable. • If all of the following conditions are met: — 1. VDD_REG is powered down to 0V (Not Hi-Z) — 2. VDD_DIG_PLL and VDD_ANA_PLL are provided externally, — 3. VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL Then the following rule should be kept: VDD_REG output impedance must be higher than 1 kΩ, when inactive. 4.2.3 • Power Supplies Usage All IO pins should not be externally driven while the IO power supply for the pin (NVCC_xxx) is off. This can cause internal latch-up and malfunctions due to reverse current flows. For information about IO power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package Information and Contact Assignments.” If not using SATA interface and the embedded thermal sensor, the VP and VPH should be grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not recommended and might lead to excessive power consumption. When internal clock source is used for SATA temperature monitor the USB_PHY supplies and PLL need to be active because they are providing the clock. If not using TVE the module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain floating. If only the GPIO pads in TVDAC_AHVDDRGB domain are in use, the supplies can be set to GPIO pad voltage range (1.65 V to 3.1 V). • • • 4.3 I/O DC Parameters This section includes the DC parameters of the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes • Low Voltage I/O (LVIO) • Ultra High Voltage I/O (UHVIO) • LVDS I/O i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 27 Electrical Characteristics NOTE The term ‘OVDD’ in this section refers to the associated supply rail of an input or output. The association is shown in Table 112. Figure 3. Circuit for Parameters Voh and Vol for IO Cells 4.3.1 General Purpose I/0 (GPIO) DC Parameters The parameters in Table 10 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Table 10 shows DC parameters for GPIO pads, operating at two supply ranges: • 1.1 V to 1.3 V • 1.65 V to 3.1 V Table 10. GPIO I/O DC Electrical Characteristics Parameter High-level output voltage1 Low-level output voltage1 High-level output current (1.1-1.3V OVDD) Symbol Voh Vol Ioh Test Conditions Iout = –1 mA Iout= specified Ioh Drive Iout = 1 mA Iout= specified Iol Drive Vout = 0.8×OVDD Low drive Medium drive High drive Max drive Vout = 0.2×OVDD Low drive Medium drive High drive Max drive Vout = 0.8×OVDD Low drive Medium drive High drive Max drive Min OVDD – 0.15 0.8*OVDD — Typ — — Max — 0.15 0.2 × OVDD Unit V V –0.85 –1.7 –2.5 –3.4 0.9 1.9 2.9 3.8 –2.1 –4.2 –6.3 –8.4 — — mA Low-level output current (1.1-1.3V OVDD) Iol — — mA High-level output current (1.65-3.1V OVDD) Ioh — — mA i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 28 Freescale Semiconductor Electrical Characteristics Table 10. GPIO I/O DC Electrical Characteristics (continued) Parameter Low-level output current (1.65-3.1V OVDD) Symbol Iol Test Conditions Vout = 0.2×OVDD Low drive Medium drive High drive Max drive — — OVDD = 1.875 V OVDD = 2.775 V — — VI = 0 V VI = OVDD VI = 0 V VI = OVDD VI = 0 V VI = OVDD VI = 0 V V I= OVDD VI = 0 V VI = OVDD Min Typ Max Unit 2.1 4.2 6.3 8.4 0.7 × OVDD 0 0.25 0.5 × OVDD — 1.7 — — — — — — — mA High-Level DC input voltage1, 2 Low-Level DC input voltage1, 2 Input Hysteresis Schmitt trigger VT+2, 3 Schmitt trigger VT–2, 3 Input current (no pull-up/down) Input current (22 kΩ Pull-up) Input current (47 kΩ Pull-up) Input current (100 kΩ Pull-up) Input current (100 kΩ Pull-down) Keeper Circuit Resistance 1 VIH VIL VHYS VT+ VT– IIN IIN IIN IIN IIN — — 0.34 0.45 — — — — — — — 1254 OVDD 0.3 × OVDD — — 0.5 × OVDD 250 120 161 0.12 76 0.12 36 0.12 0.25 36 — V V V V V nA μA μA μA μA kΩ Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. 3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. 4 Use an off-chip pull resistor of less than 60kΩ to override this keeper. 4.3.2 LPDDR2 I/O DC Parameters The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes. 4.3.2.1 DDR2 Mode I/O DC Parameters The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 29 Electrical Characteristics Table 11. DDR2 I/O DC Electrical Parameters1 Parameters High-level output voltage2 Low-level output voltage Output minimum Source Current3 Output min Sink Current4 Input Reference Voltage DC input High Voltage (data pins) DC input Low Voltage (data pins) DC Input voltage range of each differential input5 Symbol Voh Vol Ioh Iol Vref Vihd (dc) Vild (dc) Vin (dc) — — — — Vtt VI = 0 V VI=OVDD — — Test Conditions — — OVDD=1.7 V, Vout=1.42 V OVDD=1.7 V, Vout=280 mV Min 0.9*OVDD — –13.4 13.4 0.49*OVDD Vref+0.125V –0.3 –0.3 0.25 Vref – 0.04 — — — Typ — — — — 0.5*OVDD — — — — Vref 0.07 2 1258 Max — 0.1*OVDD — — 0.51*OVDD OVDD+0.3 Vref-0.125V OVDD+0.3 OVDD+0.6 Vref + 0.04 5 360 — V V V V V nA kΩ Unit V V mA mA DC Differential input voltage required for Vid(dc) switching 6 Termination Voltage Input current (no pull-up/down)7 Keeper Circuit Resistance 1 2 3 4 5 6 7 8 Vtt Iin Note that the JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any specification in this document. OVDD is the I/O power supply (1.7 V–1.9 V for DDR2) (Vout - OVDD) / Ioh must be less than 21 Ω for values of Vout between OVDD and OVDD-0.28 V. Vout / Iol must be less than 21 Ω for values of Vout between 0 V and 280 mV. Vin(dc) specifies the allowable DC voltage exertion of each differential input. Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input level and Vcp is the “complementary” input level. The minimum value is equal to Vih(dc) -Vil(dc). Typ condition: 1.8 V, and 25 °C. Max condition: 1.9 V, and 105 °C. Use an off-chip pull resistor of less than 60kΩ to override this keeper. 4.3.2.2 LPDDR2 Mode I/O DC Parameters The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009. Table 12. LPDDR2 I/O DC Electrical Parameters1 Parameters High-level output voltage Low-level output voltage Input Reference Voltage DC input High Voltage Symbol Voh Vol Vref Vih(dc) — Test Conditions — — Min 0.9*OVDD — 0.49*OVDD Vref+0.13V Typ — — 0.5*OVDD — Max — 0.1*OVDD 0.51*OVDD OVDD V Unit V V i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 30 Freescale Semiconductor Electrical Characteristics Table 12. LPDDR2 I/O DC Electrical Parameters1 (continued) DC input Low Voltage Differential Input Logic High Differential Input Logic Low Input current (no pull-up/down) Pull-up/Pull-down impedance Mismatch 240 Ohm unit calibration resolution Keeper Circuit Resistance 1 2 Vil(dc) Vih(diff) Vil(diff) Iin — OVSS 0.26 See Note2 — Vref-0.13V See Note2 -0.26 V VI = 0 V VI=OVDD — — -15 0.02 1.5 12.8 290 +15 10 nA % Ohm kΩ — — — 1253 — Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. 3 Use an off-chip pull resistor of less than 60kΩ to override this keeper. 4.3.2.3 DDR3 Mode I/O DC Parameters The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Table 13. DDR3 I/O DC Electrical Parameters Parameters High-level output voltage Low-level output voltage DC input Logic High DC input Logic Low Differential input Logic High Differential input Logic Low Over/undershoot peak Over/undershoot area (above OVDD or below OVSS) Termination Voltage Input current (no pull-up/down) Pull-up/Pull-down impedance mismatch 240 Ω unit calibration resolution Keeper Circuit Resistance 1 2 Symbol Voh Vol VIH(dc) VIL(dc) VIH(diff) VIL(diff) Vpeak Varea Vtt Iin — — — Test Conditions — — — — — — — — Vtt tracking OVDD/2 VI = 0 V VI=OVDD Minimum impedance configuration — — Min 0.8*OVDD1 — Vref 2+0.1 Typ — — — — — — — — Vref 0.09 1.75 — — 125 4 Max — 0.2*OVDD OVDD Vref-0.1 See Note3 Unit V V V V V V V Vx nS V nA Ω Ω kΩ OVSS 0.2 See Note3 — — 0.49*OVDD — — — — — -0.2 0.4 0.67 0.51*OVDD 15 320 3 10 — OVDD – I/O power supply (1.425 V–1.575 V for DDR3) Vref – DDR3 external reference voltage i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 31 Electrical Characteristics 3 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. 4 Use an off-chip pull resistor of less than 60kΩ to override this keeper. 4.3.3 Low Voltage I/O (LVIO) DC Parameters The parameters in Table 14 are guaranteed per the operating ranges in Table 6, unless otherwise noted. The LVIO pads operate only as inputs. Table 14. LVIO DC Electrical Characteristics DC Electrical Characteristics High-Level DC input voltage1, 2 Low-Level DC input voltage Input Hysteresis Schmitt trigger VT+2, 3 Schmitt trigger VT–2, 3 Input current (no pull-up/down) Input current (22 kΩ Pull-up) Input current (47 kΩ Pull-up) Input current (100 kΩ Pull-up) Input current (100 kΩ Pull-down) Keeper Circuit Resistance 1 1, 2 Symbol VIH VIL VHYS VT+ VT– IIN IIN IIN IIN IIN — Test Conditions — — OVDD = 1.875 V OVDD = 2.775 V — — VI = 0 V VI = OVDD VI = 0 V VI = OVDD VI = 0 V VI = OVDD VI = 0 V VI = OVDD VI = 0 V VI = OVDD OVDD = 1.875 V OVDD = 2.775 V Min 0.7 × OVDD 0 0.35 0.5 × OVDD — — — — — — — — Typ — — 0.62 1.27 — — 1.7 — — — — 1254 125 Max OVDD 0.3 × OVDD — — 0.5 × OVDD 250 120 161 0.12 76 0.12 36 0.12 0.25 36 — — Unit V V V V V nA μA μA μA μA kΩ Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply when hysteresis is enabled. 3 Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled. 4 Use an off-chip pull resistor of less than 60kΩ to override this keeper. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 32 Freescale Semiconductor Electrical Characteristics 4.3.4 Ultra-High Voltage I/O (UHVIO) DC Parameters Table 15. UHVIO DC Electrical Characteristics DC Electrical Characteristics Symbol Voh Test Conditions Iout = –1mA Iout= specified Ioh Drive Iout = 1mA Iout= specified Ioh Drive Vout = 0.8 × OVDD Low Drive Medium Drive High Drive Vout = 0.8 × OVDD Low Drive Medium Drive High Drive Vout = 0.2 × OVDD Low Drive Medium Drive High Drive Vout = 0.2 × OVDD Low Drive Medium Drive High Drive — — low voltage mode high voltage mode — — VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD — Min OVDD–0.15 0.8 * OVDD — Typ — Max — Unit V The parameters in Table 15 are guaranteed per the operating ranges in Table 6, unless otherwise noted. High-level output voltage1 Low-level output voltage1 Vol — 0.15 0.2 * OVDD V High-level output current, low voltage mode Ioh_lv –2.2 –4.4 –6.6 –5.1 –10.2 –15.3 2.2 4.4 6.6 5.1 10.2 15.3 0.7 × OVDD 0 0.38 0.95 0.5 × OVDD — — — — — — — — — mA High-level output current, high voltage mode Ioh_hv — — mA Low-level output current, low voltage mode Iol_lv — — mA Low-level output current, high voltage mode Iol_hv — — mA High-Level DC input voltage1, 2 Low-Level DC input Input Hysteresis Schmitt trigger VT+2, 3 Schmitt trigger VT–2, 3 Input current (no pull-up/down) Input current (22 kΩ Pull-up) Input current (75 kΩ Pull-up) Input current (100 kΩ Pull-up) Input current (360 kΩ Pull-down) Keeper Circuit Resistance voltage1, 2 VIH VIL VHYS VT+ VT– IIN IIN IIN IIN IIN — — — — — — — — — — — 125 OVDD 0.3 × OVDD 0.43 1.33 — 0.5 × OVDD 300 63 202 0.06 61 0.06 47 0.06 0.3 5.7 — V V V V V nA μA μA μA μA kΩ i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 33 Electrical Characteristics 1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply when hysteresis is enabled. 3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. 4.3.5 LVDS I/O DC Parameters The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details. Table 16 shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics. Table 16. LVDS DC Electrical Characteristics DC Electrical Characteristics Output Differential Voltage Output High Voltage Output Low Voltage Offset Voltage Symbol VOD VOH VOL VOS Test Conditions Rload=100Ω padP, –padN Min 250 1.25 0.9 1.125 Typ 350 1.375 1.025 1.2 Max 450 1.6 1.25 1.375 V Unit mV 4.4 Output Buffer Impedance Characteristics This section defines the I/O Impedance parameters of the i.MX53xA processor for the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes • Ultra High Voltage I/O (UHVIO) • LVDS I/O NOTE Output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 4). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 34 Freescale Semiconductor Electrical Characteristics OVDD PMOS (Rpu) Ztl Ω, L = 20 inches ipp_do predriver pad Cload = 1p NMOS (Rpd) OVSS Vin (do) VDD U,(V) t,(ns) 0 U,(V) Vout (pad) OVDD Vref1 Vref Vref2 t,(ns) 0 Rpu = Vovdd – Vref1 Vref1 × Ztl Rpd = Vref2 Vovdd – Vref2 × Ztl Figure 4. Impedance Matching Load for Measurement i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 35 Electrical Characteristics 4.4.1 GPIO Output Buffer Impedance Table 17. GPIO Output Buffer Impedance Typ Table 17 shows the GPIO output buffer impedance. Parameter Symbol Test Conditions Low Drive Strength, Ztl = 150 Ω Medium Drive Strength, Ztl = 75 Ω High Drive Strength, Ztl = 50 Ω Max Drive Strength, Ztl = 37.5 Ω Low Drive Strength, Ztl = 150 Ω Medium Drive Strength, Ztl = 75 Ω High Drive Strength, Ztl = 50 Ω Max Drive Strength, Ztl = 37.5 Ω Min OVDD 2.775 V OVDD 1.875 V 150 75 51 38 134 66 44 34 Max Unit Output Driver Impedance Rpu 80 40 27 20 64 32 21 16 104 52 35 26 88 44 30 22 250 125 83 62 243 122 81 61 Ω Output Driver Impedance Rpd Ω 4.4.2 LPDDR2 I/O Output Buffer Impedance The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. 4.4.3 xAUHVIO Output Buffer Impedance Table 18. UHVIO Output Buffer Impedance Min Typ OVDD 3.3 V 135 67 45 154 77 51 Max OVDD 1.65 V 198 99 66 179 89 60 OVDD 3.6 V 206 103 69 217 109 72 Unit Table 18 shows the UHVIO output buffer impedance. Parameter Symbol Test Conditions OVDD OVDD OVDD 1.95 V 3.0 V 1.875 V 98 49 32 97 49 32 114 57 38 118 59 40 124 62 41 126 63 42 Output Driver Impedance Output Driver Impedance Rpu Low Drive Strength, Ztl = 150 Ω Medium Drive Strength, Ztl = 75 Ω High Drive Strength, Ztl = 50 Ω Low Drive Strength, Ztl = 150 Ω Medium Drive Strength, Ztl = 75 Ω High Drive Strength, Ztl = 50 Ω Ω Rpd Ω 4.4.4 LVDS I/O Output Buffer Impedance The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details. 4.5 I/O AC Parameters This section includes the AC parameters of the following I/O types: • General Purpose I/O (GPIO) • Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 36 Freescale Semiconductor Electrical Characteristics • • • Low Voltage I/O (LVIO) Ultra High Voltage I/O (UHVIO) LVDS I/O The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6. From Output Under Test Test Point CL CL includes package, probe and fixture capacitance Figure 5. Load Circuit for Output OVDD 80% Output (at pad) 20% tr tf 80% 20% 0V Figure 6. Output Transition Time Waveform 4.5.1 GPIO I/O AC Electrical Characteristics AC electrical characteristics for GPIO I/O in slow and fast modes are presented in the Table 19 and Table 20, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit in the IOMUXC control registers. Table 19. GPIO I/O AC Parameters Slow Mode Parameter Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) Output Pad Slew Rate (Max Drive)1 Output Pad Slew Rate (High Drive)1 Output Pad Slew Rate (Medium Drive)1 Output Pad Slew Rate (Low Drive)1 Symbol Test Condition tr, tf tr, tf tr, tf tr, tf tps tps tps tps 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF Min — — — — 0.5/0.65 0.32/0.37 0.43/0.54 0.26/0.41 0.34/0.41 0.18/0.2 0.20/0.22 0.09/0.1 Typ — — — — — — — — Max 1.91/1.52 3.07/2.65 2.22/1.81 3.81/3.42 2.88/2.42 5.43/5.02 4.94/4.50 10.55/9.70 — — V/ns — — Unit ns ns ns ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 37 Electrical Characteristics Table 19. GPIO I/O AC Parameters Slow Mode (continued) Parameter Output Pad di/dt (Max Drive) Output Pad di/dt (High Drive) Output Pad di/dt (Medium drive) Output Pad di/dt (Low drive) Input Transition Times2 1 2 Symbol Test Condition tdit tdit tdit tdit trm — — — — — Min — — — — — Typ — — — — — Max 30 23 Unit mA/ns 15 7 25 ns tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 20. GPIO I/O AC Parameters Fast Mode Parameter Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) Output Pad Slew Rate (Max Drive)1 Output Pad Slew Rate (High Drive)1 Output Pad Slew Rate (Medium Drive)1 Output Pad Slew Rate (Low Drive)1 Output Pad di/dt (Max Drive) Output Pad di/dt (High Drive) Output Pad di/dt (Medium drive) Output Pad di/dt (Low drive) Input Transition Times 1 2 2 Symbol tr, tf tr, tf tr, tf tr, tf tps tps tps tps tdit tdit tdit tdit trm Test Condition 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF — — — — — Min — — — Typ — — — Max 1.45/1.24 2.76/2.54 1.81/1.59 3.57/3.33 2.54/2.29 5.25/5.01 4.82/4.5 10.54/9.95 — — — — 70 53 35 18 25 Unit ns ns ns ns V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns mA/ns ns — 0.69/0.78 0.36/0.39 0.55/0.62 0.28/0.30 0.39/0.44 0.19/0.20 0.21/0.22 0.09/0.1 — — — — — — — — — — — — — — — tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. Hysteresis mode is recommended for inputs with transition time greater than 25 ns. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 38 Freescale Semiconductor Electrical Characteristics 4.5.2 LPDDR2 I/O AC Electrical Characteristics The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. Table 21 shows the AC parameters for LPDDR2 I/O operating in DDR2 mode. Table 21. LPDDR2 I/O DDR2 mode AC Characteristics1 Parameter Symbol Test Condition Min Typ — — — — — — — Max — Unit V V V V V V/ns ns AC input logic high AC input logic low AC differential input voltage2 Input AC differential cross point voltage3 Output AC differential cross point voltage4 Single output slew rate Skew between pad rise/fall asymmetry + skew caused by SSN 1 Vih(ac) Vil(ac) Vid(ac) Vix(ac) Vox(ac) tsr tSKD — — — — — At 25 Ω to Vref clk=266Mhz clk=400Mhz Vref+0.25 — 0.5 Vref-0.25 OVDD Vref + 0.175 Vref + 0.125 2 0.2 0.1 Vref – 0.175 Vref – 0.125 0.4 — Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this document. 2 Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac). 3 The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross. 4 The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross. Table 22 shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode. Table 22. LPDDR2 I/O LPDDR2 mode AC Characteristics1 Parameter AC input logic high AC input logic low AC differential input high voltage2 Symbol Vih(ac) Vil(ac) Vidh(ac) Vidl(ac) voltage3 Vix(ac) Vpeak Varea Test Condition — — — — Relative to OVDD/2 — 266MHz Min Vref + 0.22 0 0.44 — -0.12 — — Typ — — — — — — — Max OVDD Vref – 0.22 — 0.44 0.12 0.35 0.6 Unit V V V V V V V*ns AC differential input low voltage Input AC differential cross point Over/undershoot peak Over/undershoot area (above OVDD or below OVSS) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 39 Electrical Characteristics Table 22. LPDDR2 I/O LPDDR2 mode AC Characteristics1 (continued) Parameter Single output slew rate Symbol tsr Test Condition 50Ohm to Vref. 5pF load. Drive impedance= 40Ohm +-30% 50Ohm to Vref. 5pF load.Drive impedance= 60Ohm +-30% Skew between pad rise/fall asymmetry + skew caused by SSN 1 2 Min 1.5 Typ — Max 3.5 Unit V/ns 1 — 2.5 tSKD clk=266MHz clk=400MHz — — 0.2 0.1 ns Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac). 3 The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross. Table 23 shows the AC parameters for LPDDR2 I/O operating in DDR3 mode. Table 23. LPDDR2 I/O DDR3 mode AC Characteristics1 Parameter AC input logic high AC input logic low AC differential input voltage2 Input AC differential cross point voltage 3 Symbol Test Condition Vih(ac) Vil(ac) Vid(ac) Vix(ac) Vox(ac) tsr tSKD — — — — — At 25 Ω to Vref clk=266MHz clk=400MHz Min Vref + 0.175 0 0.35 Typ — — — — — — — Max OVDD Unit V V V V V V/ns ns Vref – 0.175 — Vref + 0.15 Vref + 0.15 5 0.2 0.1 Vref – 0.15 Vref – 0.15 2.5 — Output AC differential cross point voltage4 Single output slew rate Skew between pad rise/fall asymmetry + skew caused by SSN 1 2 Note that the JEDEC JESD79_3C specification supersedes any specification in this document. Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac). 3 The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross. 4 The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross. 4.5.3 LVIO I/O AC Electrical Characteristics AC electrical characteristics for LVIO I/O in slow and fast modes are presented in the Table 24 and Table 25, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit in the IOMUXC control registers. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 40 Freescale Semiconductor Electrical Characteristics Table 24. LVIO I/O AC Parameters in Slow Mode Parameter Input Transition Times1 1 Symbol Test Condition trm — Min — Typ — Max 25 Unit ns Hysteresis mode is recommended for inputs with transition times greater than 25 ns. 4.5.4 UHVIO I/O AC Electrical Characteristics Table 25. LVIO I/O AC Parameters in Fast Mode Parameter Symbol trm Test Condition — Min — Typ — Max 25 Unit ns Input Transition Times1 1 Hysteresis mode is recommended for inputs with transition time greater than 25 ns. Table 26 shows the AC parameters for UHVIO I/O operating in low output voltage mode. Table 27 shows the AC parameters for UHVIO I/O operating in high output voltage mode. Table 26. AC Electrical Characteristics of UHVIO Pad (Low Output Voltage Mode) Parameter Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) Output Pad Slew Rate (High Drive)1 Output Pad Slew Rate (Medium Drive)1 Output Pad Slew Rate (Low Drive)1 Output Pad di/dt (High Drive) Output Pad di/dt (Medium drive) Output Pad di/dt (Low drive) Input Transition Times2 1 2 Symbol Test Condition tr, tf tr, tf tr, tf tps tps tps tdit tdit tdit trm 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF — — — — Min — — — 0.63/0.59 0.33/0.30 0.46/0.42 0.22/0.21 0.25/0.23 0.11/0.11 — — — — Typ — — — — — — — — — — Max 1.59/1.69 3.05/3.30 2.16/2.35 4.45/4.84 4.06/4.42 8.79/9.55 — — — 43.6 32.3 18.24 25 Unit ns V/ns mA/ns ns tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. Hysteresis mode is recommended for inputs with transition times greater than 25 ns. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 41 Electrical Characteristics Table 27. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode) Parameter Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) Output Pad Slew Rate (High Drive)1 Output Pad Slew Rate (Medium Drive)1 Output Pad Slew Rate (Low Drive)1 Output Pad di/dt (High Drive) Output Pad di/dt (Medium drive) Output Pad di/dt (Low drive) Input Transition Times2 1 2 Symbol Test Condition tr, tf tr, tf tr, tf tps tps tps tdit tdit tdit trm 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF — — — — Min — — — 1.05/0.94 0.52/0.49 0.76/0.71 0.36/0.34 0.40/0.93 0.18/0.18 — — — — Typ — — — — — — — — — — Max 1.72/1.92 3.46/3.70 2.38/2.56 5.07/5.25 4.55/4.58 10.04/9.94 — — — 82.8 65.6 43.1 25 Unit ns V/ns mA/ns ns tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. Hysteresis mode is recommended for inputs with transition times greater than 25 ns. 4.5.5 LVDS I/O AC Electrical Characteristics The differential output transition time waveform is shown in Figure 7. Figure 7. Differential LVDS Driver Transition Time Waveform Table 28 shows the AC parameters for LVDS I/O. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 42 Freescale Semiconductor Electrical Characteristics Table 28. AC Electrical Characteristics of LVDS Pad Parameter Differential pulse skew1 Transition Low to High Time2 Transition High to Low Time2 Operating Frequency Offset voltage imbalance 1 Symbol Test Condition tSKD tTLH tTHL f Vos — — Rload = 100 Ω, Cload = 2 pF Min — 0.26 0.26 — — Typ — — — 300 — Max 0.25 0.5 0.5 — 150 Unit ns MHz mV tSKD = | tPHLD – tPLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 2 Measurement levels are 20-80% from output voltage. 4.6 System Modules Timing This section contains the timing and electrical parameters for the modules in the i.MX53xA processor. 4.6.1 Reset Timings Parameters Figure 8 shows the reset timing and Table 29 lists the timing parameters. RESET_IN (Input) CC1 Figure 8. Reset Timing Diagram Table 29. Reset Timing Parameters ID CC1 Parameter Duration of RESET_IN to be qualified as valid (input slope = 5 ns) Min 50 Max — Unit ns 4.6.2 WDOG Reset Timing Parameters Figure 9 shows the WDOG reset timing and Table 30 lists the timing parameters. WATCHDOG_RST (Input) CC5 Figure 9. WATCHDOG_RST Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 43 Electrical Characteristics Table 30. WATCHDOG_RST Timing Parameters ID CC5 Parameter Duration of WATCHDOG_RESET Assertion Min 1 Max — Unit TCKIL NOTE CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs. 4.6.3 Clock Amplifier Parameters (CKIH1, CKIH2) The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave or sinusoidal frequency source. No external series capacitors are required. Table 31 shows the electrical parameters of CAMP. Table 31. CAMP Electrical Parameters (CKIH1, CKIH2) Parameter Input frequency VIL (for square wave input) VIH (for square wave input)1 Min 8.0 0 NVCC_CKIH – 0.25 0.4 45 Typ — — — — 50 Max 40.0 0.3 NVCC_CKIH VDD 55 Unit MHz V V Vp-p % Sinusoidal input amplitude2 Output duty cycle 1 2 NVCC_CKIH is the supply voltage of CAMP. Minimum value of the sinusoidal input will be determined during characterization. 4.6.4 DPLL Electrical Parameters Table 32. DPLL Electrical Parameters Parameter Test Conditions/Remarks — — — — — Should be less than denominator — — Min 10 10 300 1 5 –67108862 1 48.5 Typ — — — — — — — 50 Max 100 40 1025 16 15 67108862 67108863 51.5 Unit MHz MHz MHz — — — — % Table 32 shows the electrical parameters of digital phase-locked loop (DPLL). Reference clock frequency range1 Reference clock frequency range after pre-divider Output clock frequency range (dpdck_2) Pre-division factor2 Multiplication factor integer part Multiplication factor numerator 3 Multiplication factor denominator2 Output Duty Cycle i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 44 Freescale Semiconductor Electrical Characteristics Table 32. DPLL Electrical Parameters (continued) Parameter Frequency lock time4 (FOL mode or non-integer MF) Phase lock time Frequency jitter (peak value) Phase jitter (peak value) Power dissipation 5 Test Conditions/Remarks — — — FPL mode, integer and fractional MF fdck = 300 MHz @ avdd = 1.8 V, dvdd = 1.2 V fdck = 650 MHz @ avdd = 1.8 V, dvdd = 1.2 V Min — — — — — Typ — — 0.02 2.0 — Max 398 100 0.04 3.5 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) Unit Tdpdref µs Tdck ns mW 1 2 Device input range cannot exceed the electrical specifications of the CAMP, see Table 31. The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user. Therefore, the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD. 3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must be zero. 4T dpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL mode is 398 cycles of divided reference clock when DPLL starts after full reset. 5 Tdck is the time period of the output clock, dpdck_2. 4.6.5 NAND Flash Controller (NFC) Parameters This section provides the relative timing requirements among various signals of NFC at the module level, in each operational mode. Timing parameters in Figure 10, Figure 11, Figure 12, Figure 13, Figure 15, and Table 34 show the default NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing parameters in Figure 10, Figure 11, Figure 12, Figure 14, Figure 15, and Table 34 show symmetric NFC mode using one Flash clock cycle per one access of RE_B and WE_B. With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20% of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20 pF (except for NF16 - 40 pF) and there is maximum drive strength on all contacts. All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The clock is derived from emi_slow_clk after single divider. Table 33 demonstrates several examples of clock frequency settings. Table 33. NFC Clock Settings Examples emi_slow_clk (MHz) 100 (Boot mode) nfc_podf (Division Factor) 71 32 enfc_clk (MHz) 14.29 33.33 T-Clock Period (ns) 70 30 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 45 Electrical Characteristics Table 33. NFC Clock Settings Examples (continued) emi_slow_clk (MHz) 133 nfc_podf (Division Factor) 4 3 2 1 2 enfc_clk (MHz) 33.33 44.333 66 3 T-Clock Period (ns) 30 22.5 15 Boot value NFC_FREQ_SEL Fuse High (burned) Boot value NFC_FREQ_SEL Fuse Low 3 For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the Reference Manual for details. NOTE A potential limitation for minimum clock frequency may exist for some devices. When the clock frequency is too low, the data bus capturing might occur after the specified trhoh (RE_B high to output hold) period. Setting the clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper operation for devices having trhoh > 15 ns. It is also recommended that the NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with 33.33 MHz clock. Lower frequency operation can be supported for most available devices in the market, relying on data lines Bus-Keeper logic. This depends on device behavior on the data bus in the time interval between data output valid to data output high-Z state. In NAND device parameters this period is marked between trhoh and trhz (RE_B high to output high-Z). In most devices, the data transition from valid value to high-Z occurs without going through other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC registers, keeps the data bus valid internally after the specified hold time, allowing proper capturing with slower clock. NFCLE NF1 NF3 NF2 NF4 NFCE_B NF5 NFWE_B NF8 NFIO[7:0] command NF9 Figure 10. Command Latch Cycle Timing i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 46 Freescale Semiconductor Electrical Characteristics NF3 NFCE_B NF10 NF4 NF11 NF5 NFWE_B NF6 NFALE NF8 NFIO[7:0] Address NF9 NF7 Figure 11. Address Latch Cycle Timing NF3 NFCE_B NF10 NF11 NF5 NFWE_B NF8 NFIO[15:0] Data to NF NF9 Figure 12. Write Data Latch Timing NFCE_B NF14 NF15 NF13 NFRE_B NF16 NFRB_B NF12 NFIO[15:0] Data from NF NF17 Figure 13. Read Data Latch Timing, Asymmetric Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 47 Electrical Characteristics NFCE_B NF14 NF15 NF13 NFRE_B NF16 NFRB_B NF12 NFIO[15:0] Data from NF NF18 Figure 14. Read Data Latch Timing, Symmetric Mode NF19 NFCLE NF20 NFCE_B NFWE_B NF22 NFRE_B NF21 NFRB_B Figure 15. Other Timing Parameters i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 48 Freescale Semiconductor Electrical Characteristics Table 34. NFC—Timing Characteristics ID NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NF10 NF11 NF12 NF13 NF14 NF15 NF161 NF173 NF184 NF19 NF20 NF21 NF22 1 Parameter NFCLE setup Time NFCLE Hold Time NFCE_B Setup Time NFCE_B Hold Time NFWE_B Pulse Width NFALE Setup Time NFALE Hold Time Data Setup Time Data Hold Time Write Cycle Time NFWE_B Hold Time Ready to NFRE_B Low NFRE_B Pulse Width READ Cycle Time NFRE_B High Hold Time Data Setup on READ Data Hold on READ Data Hold on READ CLE to RE delay CE to RE delay WE high to RE low WE high to busy Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR tDHR tCLR tCRE tWHR tWB Asymmetric Mode Min 2T + 0.1 T – 4.45 3T + 0.95 3T – 5.55 T – 1.4 2T + 0.1 T – 4.45 T – 0.9 T – 5.55 2T T – 1.15 9T + 8.9 1.5T 2T 0.5T – 1.15 11.2 + 0.5T – 0 — 13T + 1.5 T – 3.45 14T – 5.45 — Tdl2 Symmetric Mode Min 2T + 0.1 T – 4.45 3T+0.95 3T – 5.55 0.5T – 1.4 2T + 0.1 T – 4.45 0.5T – 0.9 0.5T – 5.55 T 0.5T – 1.15 9T + 8.9 0.5T T 0.5T – 1.15 11.2 – Tdl — Tdl2 – 11.2 2 Max — — — — — — — — — — — — — — — — 2Taclk + T 2Taclk + T — T + 0.3 — 6T 13T + 1.5 T – 3.45 14T – 5.45 — tDSR is calculated by the following formula: Asymmetric mode: tDSR = tREpd + tDpd + 1/2T – Tdl2 Symmetric mode: tDSR = tREpd + tDpd – Tdl2 tREpd + tDpd = 11.2 ns (including clock skew) where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to EXTMC including I/O pad delay. tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T – tDSR. 2 Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (Taclk). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is “emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz). 3 NF17 is defined only in asymmetric operation mode. NF17 max value is equivalent to max tRHZ value that can be used with NFC. Taclk is “emi_slow_clk” of the system. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 49 Electrical Characteristics 4 NF18 is defined only in Symmetric operation mode. tDHR (MIN) is calculated by the following formula: Tdl2 – (tREpd + tDpd) where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to EXTMC including I/O pad delay. NF18 max value is equivalent to max tRHZ value that can be used with NFC. Taclk is “emi_slow_clk” of the system. 4.6.6 External Interface Module (EIM) The following subsections provide information on the EIM. 4.6.6.1 EIM Signal Cross Reference Table 35 is a guide intended to help the user identify signals in the External Interface Module Chapter of the Reference Manual which are identical to those mentioned in this data sheet. Table 35. EIM Signal Cross Reference Reference Manual EIM Chapter Nomenclature BCLK CSx WE_B OE_B BEy_B ADV ADDR ADDR/M_DATA DATA WAIT_B Data Sheet Nomenclature, Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUXC Controller Chapter Nomenclature EIM_BCLK EIM_CSx EIM_RW EIM_OE EIM_EBx EIM_LBA EIM_A[25:16], EIM_DA[15:0] EIM_DAx (Addr/Data muxed mode) EIM_NFC_D (Data bus shared with NAND Flash) EIM_Dx (dedicated data bus) EIM_WAIT i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 50 Freescale Semiconductor Electrical Characteristics 4.6.6.2 EIM Interface Pads Allocation EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some of the modes the EIM and the NAND FLASH have shared data bus. Table 37 provides EIM interface pads allocation in different modes. Table 36. EIM Internal Module Multiplexing Non Multiplexed Address/Data Mode Setup 8 Bit MUM = 0, DSZ = 111 A[15:0] A[25:16] D[7:0], EIM_EB0 D[15:8], EIM_EB1 D[23:16], EIM_EB2 D[31:24], EIM_EB3 EIM_DA[15:0] EIM_A[25:16] — — — EIM_D[31:24] 16 Bit MUM = 0, DSZ = 010 EIM_DA[15:0] EIM_A[25:16] — — EIM_D[23:16] EIM_D[31:24] Multiplexed Address/Data mode 16 Bit MUM = 1, DSZ = 001 EIM_DA[15:0] EIM_A[25:16] EIM_DA[7:0] EIM_DA[15:8] — — i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 51 Electrical Characteristics Table 37. Revision 2.0 EIM Internal Module Multiplexing Non Multiplexed Address/Data Mode 8 Bit MUM = 0, DSZ = 11 1 A[15:0] A[25:16] EIM_DA[1 5:0] EIM_A[25: 16] NANDF_D [7:0]2 — MUM = 0, DSZ = 111 EIM_DA[1 5:0] EIM_A[25: 16] — MUM = 0, DSZ = 11 1 EIM_DA[ 15:0] EIM_A[25 :16] — 16 Bit MUM = 0, DSZ = 001 EIM_DA[15: 0] EIM_A[25:1 6] NANDF_D[7 :0]2 NANDF_D[1 5:8]3 — MUM = 0, DSZ = 01 0 EIM_DA[1 5:0] EIM_A[25 :16] — 32 Bit MUM = 0, DSZ = 011 EIM_DA[15: 0] EIM_A[24:1 6]1 NANDF_D[ 7:0] NANDF_D[ 15:8] EIM_D[23:1 6] Multiplexed Address/Data mode 16 Bit MUM = 1, DSZ = 00 1 EIM_DA[1 5:0] EIM_A[25 :16] EIM_DA[7 :0] EIM_DA[1 5:8] — 32 Bit MUM = 1, DSZ = 011 EIM_DA[15 :0] NANDF_D[ 8:0]1 EIM_DA[7: 0] EIM_DA[15 :8] NANDF_D[ 7:0] Setup D[7:0], EIM_EB 0 D[15:8], EIM_EB 1 D[23:16] , EIM_EB 2 D[31:24] , EIM_EB 3 1 2 3 NANDF_D[ 15:8]3 — — — — — EIM_D[23 :16] — — EIM_D[31 :24] — EIM_D[31 :24] EIM_D[31:2 4] — NANDF_D[ 15:8] For 32-bit mode, the address range is A[24:0], due to address space allocation in memory map. NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0] NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8] i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 52 Freescale Semiconductor Electrical Characteristics 4.6.6.3 General EIM Timing-Synchronous Mode Figure 16, Figure 17, and Table 38 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge according to corresponding assertion/negation control fields. , WE2 BCLK ... WE3 WE5 WE7 WE9 WE4 Address WE1 WE6 CSx_B WE8 WE_B WE10 OE_B WE11 WE12 BEy_B WE13 WE14 ADV_B WE15 WE17 WE16 Output Data Figure 16. EIM Outputs Timing Diagram BCLK WE18 Input Data WE19 WE20 WAIT_B WE21 Figure 17. EIM Inputs Timing Diagram Table 38. EIM Bus Timing Parameters 1 BCD = 0 ID Parameter Min WE1 BCLK Cycle time2 WE2 BCLK Low Level Width t 0.4*t Max Min 2*t 0.8*t Max Min 3*t 1.2*t Max Min 4*t 1.6*t Max BCD = 1 BCD = 2 BCD = 3 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 53 Electrical Characteristics Table 38. EIM Bus Timing Parameters (continued)1 BCD = 0 ID Parameter Min WE3 BCLK High Level Width WE4 Clock rise to address valid3 WE5 Clock rise to address invalid WE6 Clock rise to CSx_B valid WE7 Clock rise to CSx_B invalid WE8 Clock rise to WE_B Valid WE9 Clock rise to WE_B Invalid 0.4*t -0.5*t-1.25 0.5*t-1.25 -0.5*t-1.25 0.5*t-1.25 -0.5*t-1.25 0.5*t-1.25 -0.5*t+1.75 0.5*t+1.75 -0.5*t+1.75 0.5*t+1.75 -0.5*t+1.75 0.5*t+1.75 -0.5*t+1.75 0.5*t+1.75 -0.5*t+1.75 0.5*t+1.75 -0.5*t+1.75 0.5*t+1.75 -0.5*t+1.75 0.5*t+1.75 Max Min 0.8*t -t-1.25 t-1.25 -t-1.25 t-1.25 -t-1.25 t-1.25 -t-1.25 t-1.25 -t-1.25 t-1.25 -t-1.25 t-1.25 -t-1.25 t-1.25 -t+1.75 t+1.75 -t+1.75 t+1.75 -t+1.75 t+1.75 -t+1.75 t+1.75 -t+1.75 t+1.75 -t+1.75 t+1.75 -t+1.75 t+1.75 Max Min 1.2*t -1.5*t-1.2 5 -1.5*t +1.75 Max Min 1.6*t -2*t-1.25 2*t-1.25 -2*t-1.25 2*t-1.25 -2*t-1.25 2*t-1.25 -2*t-1.25 2*t-1.25 -2*t-1.25 2*t-1.25 -2*t-1.25 2*t-1.25 -2*t-1.25 2*t-1.25 -2*t+1.75 2*t+1.75 -2*t+1.75 2*t+1.75 -2*t+1.75 2*t+1.75 -2*t+1.75 2*t+1.75 -2*t+1.75 2*t+1.75 -2*t+1.75 2*t+1.75 -2*t+1.75 2*t+1.75 Max BCD = 1 BCD = 2 BCD = 3 1.5*t-1.2 1.5*t +1.75 5 -1.5*t-1.2 5 -1.5*t +1.75 1.5*t-1.2 1.5*t +1.75 5 -1.5*t-1.2 5 -1.5*t +1.75 1.5*t-1.2 1.5*t +1.75 5 -1.5*t-1.2 5 -1.5*t +1.75 WE10 Clock rise to OE_B -0.5*t-1.25 Valid WE11 Clock rise to OE_B Invalid WE12 Clock rise to BEy_B Valid WE13 Clock rise to BEy_B Invalid WE14 Clock rise to ADV_B Valid WE15 Clock rise to ADV_B Invalid WE16 Clock rise to Output Data Valid WE17 Clock rise to Output Data Invalid WE18 Input Data setup time to Clock rise WE19 Input Data hold time from Clock rise WE20 WAIT_B setup time to Clock rise WE21 WAIT_B hold time from Clock rise 0.5*t-1.25 -0.5*t-1.25 0.5*t-1.25 -0.5*t-1.25 0.5*t-1.25 -0.5*t-1.25 0.5*t-1.25 1.5*t-1.2 1.5*t +1.75 5 -1.5*t-1.2 5 -1.5*t +1.75 1.5*t-1.2 1.5*t +1.75 5 -1.5*t-1.2 5 -1.5*t +1.75 1.5*t-1.2 1.5*t +1.75 5 -1.5*t-1.2 5 -1.5*t +1.75 1.5*t-1.2 1.5*t +1.75 5 — — — — 2 2 — — 4 2 — — — — — — 2 2 — — 4 2 — — — — — — — — — — i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 54 Freescale Semiconductor Electrical Characteristics 1 t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be ≤ 104 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 104 MHz, other busses are impacted which are clocked from this source. See the CCM chapter of the i.MX53 Reference Manual for a detailed clock tree description. 2 BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined as 50% as signal value. 3 For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value. 4.6.6.4 Examples of EIM Synchronous Accesses Figure 18 to Figure 21 provide few examples of basic EIM accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. BCLK WE4 WE5 ADDR CSx_B WE_B Last Valid Address WE6 Address v1 WE7 WE14 ADV_B WE10 WE15 WE11 WE13 WE18 OE_B WE12 BEy_B DATA D(v1) WE19 Figure 18. Synchronous Memory Read Access, WSC=1 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 55 Electrical Characteristics BCLK WE4 WE5 ADDR CSx_B Last Valid Address WE6 WE8 Address V1 WE7 WE9 WE_B WE14 ADV_B OE_B WE12 WE15 WE13 BEy_B WE16 DATA WE17 D(V1) Figure 19. Synchronous Memory, Write Access, WSC=1, WBEA=1 and WADVN=0 BCLK ADDR/ M_DATA CSx_B WE8 WE9 WE15 WE4 Valid Addr Last WE6 WE5 Address V1 WE16 WE17 Write Data WE7 WE_B ADV_B OE_B WE14 WE10 WE11 BEy_B Figure 20. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6,ADVA=1, ADVN=1, and ADH=1 NOTE In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 56 Freescale Semiconductor Electrical Characteristics BCLK ADDR/ M_DATA CSx_B WE7 WE4 Last Valid Addr WE6 WE5 Address V1 WE19 Data WE18 WE_B ADV_B OE_B WE14 WE15 WE10 WE11 WE12 WE13 BEy_B Figure 21. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=2 4.6.6.5 General EIM Timing-Asynchronous Mode Figure 22 through Figure 26, and Table 39 help to determine timing parameters relative to the chip select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing parameters mentioned above. Asynchronous read & write access length in cycles may vary from what is shown in Figure 22 through Figure 25 as RWSC, OEN & CSN is configured differently. See i.MX53xA RM for the EIM programming model. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 57 Electrical Characteristics start of access end of access INT_CLK MAXCSO CSx_B ADDR/ M_DATA WE_B ADV_B OE_B WE37 WE38 WE44 MAXCO WE39 WE35 WE40 WE36 WE31 WE32 Last Valid Address Address V1 Next Address BEy_B DATA[7:0] WE43 MAXDI D(V1) Figure 22. Asynchronous Memory Read Access (RWSC = 5, OEN=CSN=0) start of access end of access INT_CLK MAXCSO CSx_B WE31 MAXDI ADDR/ M_DATA WE_B ADV_B OE_B WE37 WE39 WE35A Addr. V1 WE32A D(V1) WE44 WE40A WE36 WE38 BEy_B MAXCO Figure 23. Asynchronous A/D Muxed Read Access (RWSC = 5, OEN=CSN=0) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 58 Freescale Semiconductor Electrical Characteristics CSx_B WE31 ADDR WE_B WE39 ADV_B OE_B WE45 BEy_B WE42 DATA WE41 D(V1) WE46 WE40 Last Valid Address WE33 Address V1 WE34 WE32 Next Address Figure 24. Asynchronous Memory Write Access (RWSC = 5, OEN=CSN=0) CSx_B WE31 WE41 ADDR/ M_DATA WE33 Addr. V1 WE32A D(V1) WE34 WE42 WE_B WE40A ADV_B OE_B WE39 WE45 WE46 WE42 BEy_B Figure 25. Asynchronous A/D Muxed Write Access (RWSC = 5, OEN=CSN=0) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 59 Electrical Characteristics CSx_B WE31 WE32 ADDR WE_B Last Valid Address Address V1 Next Address WE39 WE40 WE36 WE38 WE44 ADV_B WE35 OE_B WE37 BEy_B DATA[7:0] WE43 D(V1) WE48 DTACK WE47 Figure 26. DTACK Read Access(DAP=0) Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select Determination by Synchronous measured parameters 12 WE4 - WE6 - CSA3 WE7 - WE5 - CSN4 t5 + WE4 - WE7 + (ADVN + ADVA + 1 - CSA3) Max (If 133 Mhz is supported by SOC) 3 - CSA 3 - CSN Ref No. Parameter Min Unit WE31 WE32 CSx_B valid to Address Valid Address Invalid to CSx_B invalid CSx_B valid to Address Invalid — — ns ns WE32 A(mux ed A/D WE33 WE34 -3 + (ADVN + ADVA + 1 - CSA) — ns CSx_B Valid to WE_B Valid WE_B Invalid to CSx_B Invalid CSx_B Valid to OE_B Valid CSx_B Valid to OE_B Valid WE8 - WE6 + (WEA - CSA) WE7 - WE9 + (WEN - CSN) — — 3 + (WEA - CSA) 3 - (WEN_CSN) ns ns WE35 WE35 A (muxe d A/D) WE36 WE10 - WE6 + (OEA - CSA) WE10 - WE6 + (OEA + RADVN + RADVA + ADH + 1 - CSA) — -3 + (OEA + RADVN+RADVA +ADH+1-CSA) 3 + (OEA - CSA) 3 + (OEA + RADVN+RADVA+A DH+1-CSA) ns ns OE_B Invalid to CSx_B Invalid WE7 - WE11 + (OEN - CSN) — 3 - (OEN - CSN) ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 60 Freescale Semiconductor Electrical Characteristics Table 39. EIM Asynchronous Timing Parameters Table (continued)Relative Chip Select Determination by Synchronous measured parameters 12 WE12 - WE6 + (RBEA - CSA) Max (If 133 Mhz is supported by SOC) 3 + (RBEA6 - CSA) 3 - (RBEN7- CSN) Ref No. Parameter Min Unit WE37 CSx_B Valid to BEy_B Valid (Read access) BEy_B Invalid to CSx_B Invalid (Read access) CSx_B Valid to ADV_B Valid ADV_B Invalid to CSx_B Invalid (ADVL is asserted) CSx_B Valid to ADV_B Invalid — ns WE38 WE7 - WE13 + (RBEN - CSN) — ns WE39 WE40 WE14 - WE6 + (ADVA - CSA) WE7 - WE15 - CSN — — 3 + (ADVA - CSA) 3 - CSN ns ns WE40 A (muxe d A/D) WE41 WE14 - WE6 + (ADVN + ADVA + 1 - CSA) -3 + (ADVN + ADVA + 1 - CSA) 3 + (ADVN + ADVA + 1 - CSA) ns CSx_B Valid to Output Data Valid CSx_B Valid to Output Data Valid WE16 - WE6 - WCSA — 3 - WCSA ns WE41 A (muxe d A/D) WE42 WE16 - WE6 + (WADVN + WADVA + ADH + 1 - WCSA) — 3 + (WADVN + WADVA + ADH + 1 WCSA) ns Output Data Invalid to CSx_B Invalid Output max. delay from internal driving ADDR/control FFs to chip outputs. Output max. delay from CSx internal driving FFs to CSx out. DATA MAXIMUM delay from chip input data to its internal FF Input Data Valid to CSx_B Invalid WE17 - WE7 - CSN — 3 - CSN ns MAXC O 10 — — ns MAXC SO 10 — — MAXDI 5 — — WE43 MAXCO - MAXCSO + MAXDI MAXCO MAXCSO + MAXDI 0 — ns WE44 CSx_B Invalid to Input Data invalid CSx_B Valid to BEy_B Valid (Write access) BEy_B Invalid to CSx_B Invalid (Write access) 0 — ns WE45 WE12 - WE6 + (WBEA - CSA) — 3 + (WBEA - CSA) ns WE46 WE7 - WE13 + (WBEN CSN) — -3 + (WBEN - CSN) ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 61 Electrical Characteristics Table 39. EIM Asynchronous Timing Parameters Table (continued)Relative Chip Select Determination by Synchronous measured parameters 12 Max (If 133 Mhz is supported by SOC) — Ref No. Parameter Min Unit MAXD TI DTACK MAXIMUM delay from chip dtack input to its internal FF + 2 cycles for synchronization Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI — — WE47 MAXCO MAXCSO + MAXDTI 0 — ns WE48 1 2 3 4 5 6 7 CSx_B Invalid to Dtack invalid 0 — ns Parameters WE4... WE21 value see column BCD = 0 in Table 38 All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units. CS Assertion. This bit field determines when CS signal is asserted during read/write cycles. CS Negation. This bit field determines when CS signal is negated during read/write cycles. t is axi_clk cycle time. BE Assertion. This bit field determines when BE signal is asserted during read cycles. BE Negation. This bit field determines when BE signal is negated during read cycles. 4.6.7 DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2 and DDR3) The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008, supporting DDR2-800 and LVDDR2-800. The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting DDR3-800. The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 62 Freescale Semiconductor Electrical Characteristics Figure 27 shows the basic timing parameters. DDR1 SDCLK SDCLK DDR2 DDR4 CS DDR5 RAS DDR5 DDR4 CAS DDR4 DDR5 WE DDR5 ODT/CKE DDR6 DDR7 ADDR ROW/BA COL/BA DDR4 Figure 27. DDR SDRAM Basic Timing Parameters Figure 28 shows the write timing parameters. SDCLK SDCLK_B DDR21 DQS (output) DDR18 DDR17 DQ (output) Data Data DDR17 Data Data DDR22 DDR23 DDR18 Data Data Data Data DQM (output) DDR17 DM DM DDR18 DM DDR17 DM DM DDR18 DM DM DM Figure 28. DDR SDRAM Write Cycle i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 63 Electrical Characteristics NOTE To receive the reported setup/hold values, write calibration should be perform to locate the DQS in the middle of DQ window. Figure 29 shows the read timing parameters. SDCLK SDCLK_B DQS (input) DDR27 DQ (input) DATA DATA DATA DATA DATA DATA DATA DATA DDR26 Figure 29. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle 4.7 External Peripheral Interfaces Parameters The following subsections provide information on external peripheral interfaces. 4.7.1 AUDMUX Timing Parameters The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI electrical specifications found within this document. 4.7.2 CSPI and ECSPI Timing Parameters This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI modules and the respective routing of these signals is shown in Table 40. Table 40. CSPI Nomenclature and Routing Block Instance ECSPI-1 ECSPI-2 CSPI I/O Access GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC DISP0_DAT, CSI0_DAT and EIM through IOMUXC DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 64 Freescale Semiconductor Electrical Characteristics 4.7.2.1 CSPI Master Mode Timing Figure 30 depicts the timing of CSPI in master mode. Table 41 lists the CSPI master mode timing characteristics. RDY SSx CS10 CS1 CS3 CS2 CS2 CS6 CS4 CS5 SCLK CS7 MOSI CS8 MISO CS9 CS3 Figure 30. CSPI/ECSPI Master Mode Timing Diagram Table 41. CSPI Master Mode Timing Parameters ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 1 2 Parameter SCLK Cycle Time SCLK High or Low Time SCLK Rise or Fall1 SSx pulse width SSx Lead Time (Slave Select setup time) SSx Lag Time (SS hold time) MOSI Propagation Delay (CLOAD = 20 pF) MISO Setup Time MISO Hold Time RDY to SSx Time2 Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tPDmosi tSmiso tHmiso tSDRY Min 60 26 — 26 26 26 –1 5 5 5 Max — — — — — — 21 — — — Unit ns ns ns ns ns ns ns ns ns ns See specific I/O AC parameters Section 4.5, “I/O AC Parameters” SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 65 Electrical Characteristics 4.7.2.2 CSPI Slave Mode Timing Figure 31 depicts the timing of CSPI in slave mode. Table 42 lists the CSPI slave mode timing characteristics. SSx CS1 CS2 CS2 CS6 CS4 CS5 SCLK CS9 MISO CS7 MOSI CS8 Figure 31. CSPI/ECSPI Slave Mode Timing Diagram Table 42. CSPI Slave Mode Timing Parameters ID CS1 CS2 CS4 CS5 CS6 CS7 CS8 CS9 SCLK Cycle Time SCLK High or Low Time SSx pulse width SSx Lead Time (SS setup time) SSx Lag Time (SS hold time) MOSI Setup Time MOSI Hold Time MISO Propagation Delay (CLOAD = 20 pF) Parameter Symbol tclk tSW tCSLH tSCS tHCS tSmosi tHmosi tPDmiso 0 Min 100 Max — — — — — — — Unit ns ns ns ns ns ns ns ns 4.7.2.3 ECSPI Master Mode Timing Figure 30 depicts the timing of ECSPI in master mode. Table 43 lists the ECSPI master mode timing characteristics. Table 43. ECSPI Master Mode Timing Parameters ID CS1 CS2 CS3 CS4 Parameter SCLK Cycle Time–Read SCLK Cycle Time–Write SCLK High or Low Time–Read SCLK High or Low Time–Write SCLK Rise or Fall1 SSx pulse width Symbol tclk tSW tRISE/FALL tCSLH Min 30 15 14 7 — Half SCLK period Max — — — — Unit ns ns ns ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 66 Freescale Semiconductor Electrical Characteristics Table 43. ECSPI Master Mode Timing Parameters (continued) ID CS5 CS6 CS7 CS8 CS9 CS10 1 2 Parameter SSx Lead Time (CS setup time) SSx Lag Time (CS hold time) MOSI Propagation Delay (CLOAD = 20 pF) MISO Setup Time MISO Hold Time RDY to SSx Time2 Symbol tSCS tHCS tPDmosi tSmiso tHmiso tSDRY Min 5 5 -0.5 8.5 0 5 Max — — 2.5 — — — Unit ns ns ns ns ns ns See specific I/O AC parameters Section 4.5, “I/O AC Parameters” SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. 4.7.2.4 ECSPI Slave Mode Timing Figure 31 depicts the timing of ECSPI in slave mode. Table 44 lists the ECSPI slave mode timing characteristics. Table 44. ECSPI Slave Mode Timing Parameters ID CS1 CS2 CS4 CS5 CS6 CS7 CS8 CS9 Parameter SCLK Cycle Time–Read SCLK Cycle Time–Write SCLK High or Low Time–Read SCLK High or Low Time–Write SSx pulse width SSx Lead Time (CS setup time) SSx Lag Time (CS hold time) MOSI Setup Time MOSI Hold Time MISO Propagation Delay (CLOAD = 20 pF) Symbol tclk tSW tCSLH tSCS tHCS tSmosi tHmosi tPDmiso Min 15 40 7 20 Half SCLK period 5 5 4 4 4 Max — — — — — — — 17 Unit ns ns ns ns ns ns ns ns 4.7.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 45 shows the interface timing values. The number field in the table refers to timing signals found in Figure 32 and Figure 33. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 67 Electrical Characteristics Table 45. Enhanced Serial Audio Interface (ESAI) Timing No. 62 63 Clock cycle5 Clock high period • For internal clock • For external clock 64 Clock low period • For internal clock • For external clock 65 66 67 68 69 70 71 72 73 74 75 78 79 80 81 SCKR rising edge to FSR out (bl) high SCKR rising edge to FSR out (bl) low SCKR rising edge to FSR out (wr) high6 SCKR rising edge to FSR out (wr) low6 SCKR rising edge to FSR out (wl) high SCKR rising edge to FSR out (wl) low Data in setup time before SCKR (SCK in synchronous mode) falling edge Data in hold time after SCKR falling edge FSR input (bl, wr) high before SCKR falling edge6 FSR input (wl) high before SCKR falling edge FSR input hold time after SCKR falling edge SCKT rising edge to FST out (bl) high SCKT rising edge to FST out (bl) low SCKT rising edge to FST out (wr) high6 SCKT rising edge to FST out (wr) low6 Characteristics1’2,3 Symbol tSSICC Expression3 4 × Tc 4 × Tc 2 × Tc − 9.0 2 × Tc 2 × Tc − 9.0 2 × Tc — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Min 30.0 30.0 6 15 6 15 — — — — — — — — — — — — 12.0 19.0 3.5 9.0 2.0 12.0 2.0 12.0 2.5 8.5 — — — — — — — — Max — — — — — — 17.0 7.0 17.0 7.0 19.0 9.0 19.0 9.0 16.0 6.0 17.0 7.0 — — — — — — — — — — 18.0 8.0 20.0 10.0 20.0 10.0 22.0 12.0 Condition4 Unit i ck i ck — — ns — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns — — i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 68 Freescale Semiconductor Electrical Characteristics Table 45. Enhanced Serial Audio Interface (ESAI) Timing (continued) No. 82 83 84 86 87 89 90 91 95 96 97 1 Characteristics1’2,3 Symbol — — — — — — — — — — — — — — — — — — — Expression3 — — — — — — — — — — — — — — — — 2 x TC — — Min — — — — — — — — — — 2.0 18.0 2.0 18.0 4.0 5.0 15 — — Max 19.0 9.0 20.0 10.0 22.0 17.0 18.0 13.0 21.0 16.0 — — — — — — — 18.0 18.0 Condition4 Unit x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck — — — ns ns ns ns ns ns ns ns ns ns ns SCKT rising edge to FST out (wl) high SCKT rising edge to FST out (wl) low SCKT rising edge to data out enable from high impedance SCKT rising edge to data out valid SCKT rising edge to data out high impedance 77 FST input (bl, wr) setup time before SCKT falling edge6 FST input (wl) setup time before SCKT falling edge FST input hold time after SCKT falling edge HCKR/HCKT clock cycle HCKT input rising edge to SCKT output HCKR input rising edge to SCKR output 2 3 4 5 6 7 VCORE_VDD= 1.00 +- 0.10V Tj = -40C to 125C CL=50pF i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) bl = bit length wl = word length wr = word length relative SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame. Periodically sampled and not 100% tested. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 69 Electrical Characteristics 62 63 SCKT (Input/Output) 78 FST (Bit) Out 82 FST (Word) Out 83 79 64 86 84 86 87 First Bit Last Bit Data Out 89 91 FST (Bit) In 90 FST (Word) In 91 Figure 32. ESAI Transmitter Timing i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 70 Freescale Semiconductor Electrical Characteristics 62 63 SCKR (Input/Output) 65 FSR (Bit) Out 69 FSR (Word) Out 72 71 Data In 73 FSR (Bit) In 74 FSR (Word) In Figure 33. ESAI Receiver Timing 75 75 First Bit Last Bit 70 64 66 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 71 Electrical Characteristics 4.7.4 Enhanced Secured Digital Host Controller(eSDHCv2/v3) AC timing This section describes the electrical information of the eSDHCv2/v3, which includes SD/eMMC4.3 (Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing. 4.7.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing Figure 34 depicts the timing of SD/eMMC4.3, and Table 46 lists the SD/eMMC4.3 timing characteristics. SD4 SD2 SD5 SD1 SCK SD3 CMD DAT0 DAT1 output from eSDHCv2 to card ...... DAT7 CMD DAT0 DAT1 input from card to eSDHCv2 ...... DAT7 SD6 SD7 SD8 Figure 34. SD/eMMC4.3 Timing Table 46. SD/eMMC4.3 Interface Timing Specification ID Parameter Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) Clock Frequency (Identification Mode) SD2 SD3 SD4 SD5 Clock Low Time Clock High Time Clock Rise Time Clock Fall Time fPP1 fPP2 fPP3 fOD tWL tWH tTLH tTHL 0 0 0 100 7 7 — — 400 25/50 20/52 400 — — 3 3 kHz MHz MHz kHz ns ns ns ns Symbols Min Max Unit eSDHC Output/Card Inputs CMD, DAT (Reference to CLK) SD6 eSDHC Output Delay tOD –5 5 ns eSDHC Input/Card Outputs CMD, DAT (Reference to CLK) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 72 Freescale Semiconductor Electrical Characteristics Table 46. SD/eMMC4.3 Interface Timing Specification (continued) ID SD7 SD8 1 2 Parameter eSDHC Input Setup Time eSDHC Input Hold Time4 Symbols tISU tIH Min 2.5 2.5 Max — — Unit ns ns In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock frequency can be any value between 0–50 MHz. 3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock frequency can be any value between 0–52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 4.7.4.2 eMMC4.4 (Dual Data Rate) eSDHCv3 AC Timing Figure 35 depicts the timing of eMMC4.4. Table 47 lists the eMMC4.4 timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD). SD1 SCK SD2 SD2 ...... SD3 DAT0 DAT1 input from card to eSDHCv3 ...... DAT7 SD4 DAT0 DAT1 output from eSDHCv3 to card ...... DAT7 ...... Figure 35. eMMC4.4 Timing Table 47. eMMC4.4 Interface Timing Specification ID Parameter Symbols Card Input Clock SD1 Clock Frequency (MMC Full Speed/High Speed) fPP 0 52 MHz Min Max Unit eSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD2 eSDHC Output Delay tOD –5 5 ns eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 73 Electrical Characteristics Table 47. eMMC4.4 Interface Timing Specification (continued) ID SD3 SD4 Parameter eSDHC Input Setup Time eSDHC Input Hold Time Symbols tISU tIH Min 2.5 2.5 Max — — Unit ns ns 4.7.5 FEC AC Timing Parameters This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps MII (18 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the MII pins), for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see the i.MX53 Reference Manual. This section describes the AC timing specifications of the FEC. The MII signals are compatible with transceivers operating at a voltage of 3.3 V. 4.7.5.1 MII Receive Signal Timing The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must exceed twice the FEC_RX_CLK frequency. Table 48 lists the MII receive channel signal timing parameters and Figure 36 shows MII receive signal timings. . Table 48. MII Receive Signal Timing No. M1 M2 M3 M4 Characteristics1 2 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold FEC_RX_CLK pulse width high FEC_RX_CLK pulse width low Min 5 5 35% 35% Max — — 65% 65% Unit ns ns FEC_RX_CLK period FEC_RX_CLK period 1 2 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode. Test conditions: 25pF on each output signal. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 74 Freescale Semiconductor Electrical Characteristics M3 FEC_RX_CLK (input) M4 FEC_RXD[3:0] (inputs) FEC_RX_DV FEC_RX_ER M1 M2 Figure 36. MII Receive Signal Timing Diagram 4.7.5.2 MII Transmit Signal Timing The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TX_CLK frequency. Table 49 lists MII transmit channel timing parameters. Figure 37 shows MII transmit signal timing diagram for the values listed in Table 49. Table 49. MII Transmit Signal Timing Num M5 M6 M7 M8 1 2 Characteristic1 2 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid FEC_TX_CLK pulse width high FEC_TX_CLK pulse width low Min 5 — 35% 35% Max — 20 65% 65% Unit ns ns FEC_TX_CLK period FEC_TX_CLK period FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode. Test conditions: 25pF on each output signal. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 75 Electrical Characteristics . M7 FEC_TX_CLK (input) M5 M8 FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER M6 Figure 37. MII Transmit Signal Timing Diagram 4.7.5.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL) Table 50 lists MII asynchronous inputs signal timing information. Figure 38 shows MII asynchronous input timings listed in Table 50. Table 50. MII Async Inputs Signal Timing Num M92 1 2 Characteristic 1 FEC_CRS to FEC_COL minimum pulse width Min 1.5 Max — Unit FEC_TX_CLK period Test conditions: 25pF on each output signal. FEC_COL has the same timing in 10 Mbit 7-wire interface mode. . FEC_CRS, FEC_COL M9 Figure 38. MII Async Inputs Timing Diagram 4.7.5.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 51 lists MII serial management channel timings. Figure 39 shows MII serial management channel timings listed in Table 51. The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC frequency of 15 MHz. Table 51. MII Transmit Signal Timing ID Characteristics1 Min Max 0 — 18 — 5 — Unit ns ns ns M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay) M12 FEC_MDIO (input) to FEC_MDC rising edge setup i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 76 Freescale Semiconductor Electrical Characteristics Table 51. MII Transmit Signal Timing (continued) ID Characteristics1 Min Max 0 40 % 40 % — Unit ns M13 FEC_MDIO (input) to FEC_MDC rising edge hold M14 FEC_MDC pulse width high M15 FEC_MDC pulse width low 1 60% FEC_MDC period 60% FEC_MDC period Test conditions: 25pF on each output signal. M14 M15 FEC_MDC (output) M10 FEC_MDIO (output) M11 FEC_MDIO (input) M12 M13 Figure 39. MII Serial Management Channel Timing Diagram 4.7.5.5 RMII Mode Timing In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ±50 ppm continuous reference clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER. The RMII mode timings are shown in Table 52 and Figure 40. Table 52. RMII Signal Timing No. M16 M17 M18 M19 Characteristics1 REF_CLK(FEC_TX_CLK) pulse width high REF_CLK(FEC_TX_CLK) pulse width low REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid Min 35% 35% 2 — Max 65% 65% — 16 Unit REF_CLK period REF_CLK period ns ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 77 Electrical Characteristics Table 52. RMII Signal Timing (continued) No. M20 M21 1 Characteristics1 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold Min 4 2 Max — — ns ns Unit Test conditions: 25pF on each output signal. M16 M17 REF_CLK (input) M18 FEC_TXD[1:0] (output) FEC_TX_EN M19 CRS_DV (input) FEC_RXD[1:0] FEC_RX_ER M20 M21 Figure 40. RMII Mode Signal Timing Diagram 4.7.6 Flexible Controller Area Network (FLEXCAN) AC Electrical Specifications The electrical characteristics are related to the CAN transceiver external to i.MX53xA such as MC33902 from Freescale.The i.MX53xA has two CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the i.MX53 reference manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 78 Freescale Semiconductor Electrical Characteristics 4.7.7 I2C Module Timing Parameters This section describes the timing parameters of the I2C module. Figure 41 depicts the timing of I2C module, and Table 53 lists the I2C module timing characteristics. IC10 IC11 IC9 I2DAT IC2 IC8 I2CLK IC4 IC7 IC3 START IC10 IC6 IC1 IC5 IC11 START STOP START Figure 41. I2C Bus Timing Table 53. I2C Module Timing Parameters Standard Mode Fast Mode Supply Voltage = Supply Voltage = 1.65 V–1.95 V, 2.7 V–3.3 V 2.7 V–3.3 V Unit Min IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 1 ID Parameter Max — — — 3.452 — — — — — 1000 300 400 Min 2.5 0.6 0.6 0 1 Max — — — 0.92 — — — — — 4 I2CLK cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2CLK Clock LOW Period of the I2CLK Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both I2DAT and I2CLK signals Fall time of both I2DAT and I2CLK signals Capacitive load for each bus line (Cb) 10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 — — — µs µs µs µs µs µs µs ns 0.6 1.3 0.6 100 3 1.3 20 + 0.1Cb µs ns ns pF 300 300 400 20 + 0.1Cb4 — A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal. 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 79 Electrical Characteristics 4.7.8 Image Processing Unit (IPU) Module Parameters The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. This support covers all aspects of these activities: • Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders. • Related image processing and manipulation: sensor image signal processing, display processing, image conversions, and other related functions. • Synchronization and control capabilities, such as avoidance of tearing artifacts. 4.7.8.1 IPU Sensor Interface Signal Mapping The IPU supports a number of sensor input formats. Table 54 defines the mapping of the Sensor Interface Pins used for various supported interface formats. Table 54. Camera Input Signal Cross Reference, Format and Bits per Cycle Signal Name1 CSIx_DAT0 CSIx_DAT1 CSIx_DAT2 CSIx_DAT3 CSIx_DAT4 CSIx_DAT5 CSIx_DAT6 CSIx_DAT7 CSIx_DAT8 CSIx_DAT9 CSIx_DAT10 CSIx_DAT11 CSIx_DAT12 CSIx_DAT13 CSIx_DAT14 CSIx_DAT15 CSIx_DAT16 CSIx_DAT17 CSIx_DAT18 CSIx_DAT19 1 RGB565 8 bits 2 cycles — — — — — — — — — — — — B[0], G[3] B[1], G[4] B[2], G[5] B[3], R[0] B[4], R[1] G[0], R[2] G[1], R[3] G[2], R[4] RGB5652 8 bits 3 cycles — — — — — — — — — — — — R[2],G[4],B[2] R[3],G[5],B[3] R[4],G[0],B[4] R[0],G[1],B[0] R[1],G[2],B[1] R[2],G[3],B[2] R[3],G[4],B[3] R[4],G[5],B[4] RGB6663 8 bits 3 cycles — — — — — — — — — — — — R/G/B[4] R/G/B[5] R/G/B[0] R/G/B[1] R/G/B[2] R/G/B[3] R/G/B[4] R/G/B[5] RGB888 8 bits 3 cycles — — — — — — — — — — — — R/G/B[0] R/G/B[1] R/G/B[2] R/G/B[3] R/G/B[4] R/G/B[5] R/G/B[6] R/G/B[7] YCbCr 8 bits 2 cycles — — — — — — — — — — — — Y/C[0] Y/C[1] Y/C[2] Y/C[3] Y/C[4] Y/C[5] Y/C[6] Y/C[7] RGB5654 16 bits 2 cycles — — — — B[0] B[1] B[2] B[3] B[4] G[0] G[1] G[2] G[3] G[4] G[5] R[0] R[1] R[2] R[3] R[4] YCbCr5 16 bits 1 cycle — — — — C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] YCbCr6 16 bits 1 cycle 0 0 C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] 0 0 Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] YCbCr7 20 bits 1 cycle C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] CSIx stands for CSI1 or CSI2 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 80 Freescale Semiconductor Electrical Characteristics 2 3 4 5 6 7 The MSB bits are duplicated on LSB bits implementing color extension The two MSB bits are duplicated on LSB bits implementing color extension RGB 16 bits – supported in two ways: (1) As a “generic data” input – with no on-the-fly processing; (2) With on-the-fly processing, but only under some restrictions on the control protocol. YCbCr 16 bits - supported as a “generic-data” input – with no on-the-fly processing. YCbCr 16 bits - supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol). YCbCr, 20 bits, supported only within the BT.1120 protocol (syncs embedded within the data stream). 4.7.8.2 Sensor Interface Timings There are three camera timing modes supported by the IPU. 4.7.8.2.1 BT.656 and BT.1120 Video Mode Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656/BT.1120 standards. This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are received over the SENSB_DATA bus. 4.7.8.2.2 Gated Clock Mode The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 42. Start of Frame nth frame Active Line n+1th frame SENSB_VSYNC SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[19:0] invalid invalid 1st byte 1st byte Figure 42. Gated Clock Mode Timing Diagram A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 81 Electrical Characteristics SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats. 4.7.8.2.3 Non-Gated Clock Mode The timing is the same as the gated-clock mode (described in Section 4.7.8.2.2, “Gated Clock Mode,”) except for the SENSB_HSYNC signal, which is not used (see Figure 43). All incoming pixel clocks are valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus. Start of Frame nth frame n+1th frame SENSB_VSYNC SENSB_PIX_CLK SENSB_DATA[19:0] invalid invalid 1st byte 1st byte Figure 43. Non-Gated Clock Mode Timing Diagram The timing described in Figure 43 is that of a typical sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK. 4.7.8.3 Electrical Characteristics Figure 44 depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by the IPU. Table 55 lists the sensor interface timing characteristics. SENSB_PIX_CLK (Sensor Output) IP3 SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC IP2 1/IP1 Figure 44. Sensor Interface Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 82 Freescale Semiconductor Electrical Characteristics Table 55. Sensor Interface Timing Characteristics ID IP1 IP2 IP3 Parameter Sensor output (pixel) clock frequency Data and control setup time Data and control holdup time Symbol Fpck Tsu Thd Min 0.01 2 1 Max 180 — — Unit MHz ns ns 4.7.8.4 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Table 56 defines the mapping of the Display Interface Pins used during various supported video interface formats. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 83 Electrical Characteristics Table 56. Video Signal Cross-Reference i.MX53xA LCD RGB/TV Signal Allocation (Example) RGB, Signal Name 16-bit 18-bit 24 Bit 8-bit 16-bit 20-bit (General) RGB RGB RGB YCrCb2 YCrCb YCrCb DAT[0] DAT[1] DAT[2] DAT[3] DAT[4] DAT[5] DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] DAT[16] DAT[17] DAT[18] DAT[19] DAT[20] DAT[21] B[0] B[1] B[2] B[3] B[4] G[0] G[1] G[2] G[3] G[4] G[5] R[0] R[1] R[2] R[3] R[4] — — — — — — B[0] B[1] B[2] B[3] B[4] B[5] G[0] G[1] G[2] G[3] G[4] G[5] R[0] R[1] R[2] R[3] R[4] R[5] — — — — B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] R[0] R[1] R[2] R[3] R[4] R[5] Y/C[0] Y/C[1] Y/C[2] Y/C[3] Y/C[4] Y/C[5] Y/C[6] Y/C[7] — — — — — — — — — — — — — — C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] — — — — — — C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] — — Smart Signal Name DAT[0] DAT[1] DAT[2] DAT[3] DAT[4] DAT[5] DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] — — — — — — The restrictions are as follows: a) There are maximal three continuous groups of bits that could be independently mapped to the external bus. Groups should not be overlapped. b) The bit order is expressed in each of the bit groups, for example B[0] = least significant blue pixel bit Comment1 Port Name (x=0, 1) DISPx_DAT0 DISPx_DAT1 DISPx_DAT2 DISPx_DAT3 DISPx_DAT4 DISPx_DAT5 DISPx_DAT6 DISPx_DAT7 DISPx_DAT8 DISPx_DAT9 DISPx_DAT10 DISPx_DAT11 DISPx_DAT12 DISPx_DAT13 DISPx_DAT14 DISPx_DAT15 DISPx_DAT16 DISPx_DAT17 DISPx_DAT18 DISPx_DAT19 DISPx_DAT20 DISPx_DAT21 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 84 Freescale Semiconductor Electrical Characteristics Table 56. Video Signal Cross-Reference (continued) i.MX53xA LCD RGB/TV Signal Allocation (Example) RGB, Signal 16-bit 20-bit Name 16-bit 18-bit 24 Bit 8-bit (General) RGB RGB RGB YCrCb2 YCrCb YCrCb DAT[22] DAT[23] — — — — R[6] R[7] PixCLK — — — — — — — Smart Signal Name — — — — — — Comment1 Port Name (x=0, 1) DISPx_DAT22 DISPx_DAT23 DIx_DISP_CLK DIx_PIN1 VSYNC_IN May be required for anti-tearing DIx_PIN2 DIx_PIN3 DIx_PIN4 DIx_PIN5 DIx_PIN6 DIx_PIN7 DIx_PIN8 DIx_D0_CS DIx_D1_CS DIx_PIN11 DIx_PIN12 DIx_PIN13 DIx_PIN14 DIx_PIN15 DIx_PIN16 DIx_PIN17 1 2 HSYNC VSYNC — — — — — — — — — — — DRDY/DV — Q — — — — — — — CS0 CS1 WR RD RS1 RS2 DRDY — — — VSYNC out Additional frame/row synchronous signals with programmable timing — Alternate mode of PWM output for contrast or brightness control — — Register select signal Optional RS2 Data validation/blank, data enable Additional data synchronous signals with programmable features/timing Signal mapping (both data and control/synchronization) is flexible. The table provides examples. This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 85 Electrical Characteristics NOTE Table 56 provides information for both the Disp0 and Disp1 ports. However, Disp1 port has reduced pinout depending on IOMUXC configuration and therefore may not support all the above configurations. See the IOMUXC table for details. 4.7.8.5 IPU Display Interface Timing The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There are two groups of external interface pins to provide synchronous and asynchronous controls accordantly. 4.7.8.5.1 Synchronous Controls The synchronous control changes its value as a function of a system or of an external clock. This control has a permanent period and a permanent wave form. There are special physical outputs to provide synchronous controls: • The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display (component, pixel) clock for a display. • The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide HSYNC, VSYNC, DRDY or any else independent signal to a display. The IPU has a system of internal binding counters for internal events (such as HSYNC/VSYCN and so on) calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control starts from the local start point with predefined UP and DOWN values to calculate control’s changing points with half DI_CLK resolution. A full description of the counters system can be found in the IPU chapter of the i.MX53 Reference Manual. 4.7.8.5.2 Asynchronous Controls The asynchronous control is a data-oriented signal that changes its value with an output data according to additional internal flags coming with the data. There are special physical outputs to provide asynchronous controls, as follows: • The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays. • The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide WR. RD, RS or any other data oriented signal to display. NOTE The IPU has independent signal generators for asynchronous signals toggling. When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 86 Freescale Semiconductor Electrical Characteristics 4.7.8.6 4.7.8.6.1 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels IPU Display Operating Signals The IPU uses four control signals and data to operate a standard synchronous interface: • IPP_DISP_CLK—Clock to display • HSYNC—Horizontal synchronization • VSYNC—Vertical synchronization • DRDY—Active data All synchronous display controls are generated on the base of an internally generated “local start point”. The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative to the local start point. 4.7.8.6.2 LCD Interface Functional Description Figure 45 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is: • DI_CLK internal DI clock, used for calculation of other controls. • IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously. • HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.) • VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. (Usually IPP_PIN_3 is used as VSYNC.) • DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. (DRDY can be used either synchronous or asynchronous generic purpose pin as well.) VSYNC HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n HSYNC DRDY 1 IPP_DISP_CLK IPP_DATA 2 3 m–1 m Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 87 Electrical Characteristics 4.7.8.6.3 TFT Panel Sync Pulse Timing Diagrams Figure 46 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All the parameters shown in the figure are programmable. All controls are started by corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals. IP13o IP5o IP8o IP8 IP7 IP5 DI clock IPP_DISP_CLK VSYNC HSYNC DRDY IPP_DATA IP9 local start point local start point local start point IP9o IP6 D0 D1 Dn IP10 Figure 46. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 47 depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable. Start of frame End of frame IP13 VSYNC HSYNC DRDY IP11 IP14 IP12 IP15 Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 88 Freescale Semiconductor Electrical Characteristics Table 57 shows timing characteristics of signals presented in Figure 46 and Figure 47. Table 57. Synchronous Display Interface Timing Characteristics (Pixel Level) ID IP5 IP6 Parameter Display interface clock period Display pixel clock period Symbol Tdicp Tdpcp Value (1) Description Display interface clock. IPP_DISP_CLK Unit ns ns DISP_CLK_PER_PIXEL Time of translation of one pixel to display, × Tdicp DISP_CLK_PER_PIXEL—number of pixel components in one pixel (1.n). The DISP_CLK_PER_PIXEL is virtual parameter to define Display pixel clock period. The DISP_CLK_PER_PIXEL is received by DC/DI one access division to n components. (SCREEN_WIDTH) × Tdicp SCREEN_WIDTH—screen width in, interface clocks. horizontal blanking included. The SCREEN_WIDTH should be built by suitable DI’s counter2. HSYNC_WIDTH—Hsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI’s counter. BGXP—width of a horizontal blanking before a first active data in a line (in interface clocks). The BGXP should be built by suitable DI’s counter. Width a horizontal blanking after a last active data in a line (in interface clocks) FW—with of active line in interface clocks. The FW should be built by suitable DI’s counter. SCREEN_HEIGHT— screen height in lines with blanking. The SCREEN_HEIGHT is a distance between 2 VSYNCs. The SCREEN_HEIGHT should be built by suitable DI’s counter. VSYNC_WIDTH—Vsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI’s counter BGYP—width of first Vertical blanking interval in line.The BGYP should be built by suitable DI’s counter. Width of second Vertical blanking interval in line.The FH should be built by suitable DI’s counter. IP7 Screen width time Tsw ns IP8 HSYNC width time Thsw (HSYNC_WIDTH) ns IP9 Horizontal blank interval 1 Thbi1 BGXP × Tdicp ns IP10 Horizontal blank interval 2 Thbi2 (SCREEN_WIDTH – BGXP – FW) × Tdicp ns IP12 Screen height Tsh (SCREEN_HEIGHT) × Tsw ns IP13 VSYNC width Tvsw VSYNC_WIDTH ns IP14 Vertical blank interval 1 Tvbi1 BGYP × Tsw ns IP15 Vertical blank interval 2 Tvbi2 (SCREEN_HEIGHT – BGYP – FH) × Tsw ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 89 Electrical Characteristics Table 57. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued) ID IP5o Parameter Offset of IPP_DISP_CLK Symbol Todicp Value DISP_CLK_OFFSET × Tdiclk Description DISP_CLK_OFFSET—offset of IPP_DISP_CLK edges from local start point, in DI_CLK×2 (0.5 DI_CLK Resolution) Defined by DISP_CLK counter VSYNC_OFFSET—offset of Vsync edges from a local start point, when a Vsync should be active, in DI_CLK×2 (0.5 DI_CLK Resolution).The VSYNC_OFFSET should be built by suitable DI’s counter. HSYNC_OFFSET—offset of Hsync edges from a local start point, when a Hsync should be active, in DI_CLK×2 (0.5 DI_CLK Resolution).The HSYNC_OFFSET should be built by suitable DI’s counter. DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLK×2 (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI’s counter. Unit ns IP13o Offset of VSYNC Tovs VSYNC_OFFSET × Tdiclk ns IP8o Offset of HSYNC Tohs HSYNC_OFFSET × Tdiclk ns IP9o Offset of DRDY Todrdy DRDY_OFFSET × Tdiclk ns 1 Display interface clock period immediate value. ⎧ DISP_CLK_PERIOD ⎪ T diclk × --------------------------------------------------- , DI_CLK_PERIOD ⎪ Tdicp = ⎨ DISP_CLK_PERIOD ⎪T ⎛ ⎞ --------------------------------------------------⎪ diclk ⎝ floor DI_CLK_PERIOD + 0.5 ± 0.5⎠ , ⎩ for integer DISP_CLK_PERIOD --------------------------------------------------DI_CLK_PERIOD for fractional DISP_CLK_PERIOD --------------------------------------------------DI_CLK_PERIOD DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK. DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency Display interface clock period average value. DISP_CLK_PERIOD Tdicp = T diclk × --------------------------------------------------DI_CLK_PERIOD 2 DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH. The maximal accuracy of UP/DOWN edge of controls is: Accuracy = ( 0.5 × T diclk ) ± 0.62ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 90 Freescale Semiconductor Electrical Characteristics The maximal accuracy of UP/DOWN edge of IPP_DATA is: Accuracy = T diclk ± 0.62ns The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed through the registers. Figure 48 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and DISP_CLK_UP parameters are set through the Register. Table 58 lists the synchronous display interface timing characteristics. IP20o IP20 VSYNC HSYNC DRDY other controls IPP_DISP_CLK Tdicu IPP_DATA IP16 IP17 IP19 IP18 Tdicd local start point Figure 48. Synchronous Display Interface Timing Diagram—Access Level Table 58. Synchronous Display Interface Timing Characteristics (Access Level) ID IP16 IP17 IP18 IP19 IP20o Parameter Symbol Min Tdicd-Tdicu–1.24 Tdicp–Tdicd+Tdicu–1.24 Tdicd–1.24 Tdicp–Tdicd–1.24 Tocsu–1.24 Typ1 Tdicd2–Tdicu3 Tdicp–Tdicd+Tdicu Tdicu Tdicp–Tdicu Tocsu Max Tdicd–Tdicu+1.24 Tdicp–Tdicd+Tdicu+1.2 — — Tocsu+1.24 Unit ns ns ns ns ns Display interface clock Tckl low time Display interface clock Tckh high time Data setup time Data holdup time Tdsu Tdhd Control signals offset Tocsu times (defines for each pin) Control signals setup time to display interface clock (defines for each pin) Tcsu IP20 Tdicd–1.24–Tocsu%Tdicp Tdicu — ns The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 1 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 91 Electrical Characteristics 2 Display interface clock down time 2 × DISP_CLK_DOWN 1 Tdicd = -- ⎛ T diclk × ceil ---------------------------------------------------------- ⎞ ⎠ DI_CLK_PERIOD 2⎝ 3 Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity. 2 × DISP_CLK_UP Tdicu = 1 ⎛ T diclk × ceil ----------------------------------------------- ⎞ -- ⎝ DI_CLK_PERIOD ⎠ 2 4.7.8.7 Interface to a TV Encoder (TVDAC) The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of the interface is described in Figure 49. • • • • • NOTE The frequency of the clock DISP_CLK is 27 MHz (within 10%) The HSYNC, VSYNC signals are active low. The DRDY signal is shown as active high. The transition to the next row is marked by the negative edge of the HSYNC signal. It remains low for a single clock cycle. The transition to the next field/frame is marked by the negative edge of the VSYNC signal. It remains low for at least one clock cycles. — At a transition to an odd field (of the next frame), the negative edges of VSYNC and HSYNC coincide. — At a transition is to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the HSYNC signal being high. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 92 Freescale Semiconductor Electrical Characteristics DISP_CLK HSYNC VSYNC DRDY IPP_DATA Cb Y Cr Y Cb Y Cr Pixel Data Timing HSYNC DRDY VSYNC Even Field HSYNC DRDY VSYNC 261 262 263 264 265 266 267 Odd Field 268 269 273 523 524 525 1 2 3 4 5 6 10 Odd Field Line and Field Timing - NTSC HSYNC DRDY VSYNC Even Field 621 622 623 624 625 1 2 3 Even Field 4 23 Odd Field HSYNC DRDY VSYNC 308 309 310 311 312 313 314 315 316 336 Odd Field Line and Field Timing - PAL Even Field Figure 49. TV Encoder Interface Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 93 Electrical Characteristics 4.7.8.7.1 TVEv2 TV Encoder Performance Specifications The TV encoder output specifications are shown in Table 59. All the parameters in the table are defined under the following conditions: • Rset = 1.05 kΩ ±1%, resistor on TVDAC_VREF pin to GND • Rload = 37.5 Ω ±1%, output load to the GND Table 59. TV Encoder Video Performance Specifications Parameter DAC STATIC PERFORMANCE Resolution1 Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL) 2 Conditions Min Typ Max Unit — — — — Rset = 1.05 kΩ ±1% Rload = 37.5 Ω ±1% — — — — 1.24 10 1 0.6 2 1.306 — 2 1 — 1.37 Bits LSBs LSBs % V Channel-to-channel gain matching2 Full scale output voltage2 DAC DYNAMIC PERFORMANCE Spurious Free Dynamic Range (SFDR) Spurious Free Dynamic Range (SFDR) VIDEO PERFORMANCE IN SD MODE2 Short Term Jitter (Line to Line) Long Term Jitter (Field to Field) Frequency Response 0-4.0 MHz 5.75 MHz Luminance Nonlinearity Differential Gain Differential Phase Signal-to-Noise Ratio (SNR) Hue Accuracy Color Saturation Accuracy Chroma AM Noise Chroma PM Noise Chroma Nonlinear Phase Chroma Nonlinear Gain Chroma/Luma Intermodulation Chroma/Luma Gain Inequality — — — Flat field full bandwidth — — — — — — — — — — — — –0.1 –0.7 — — — — — — — — — — — — 2.5 3.5 — — 0.5 0.35 0.6 75 0.8 1.5 –70 –47 0.5 2.5 0.1 1.0 — — 0.1 0 — — — — — — — — — — — — ±ns ±ns dB dB ±% % Degrees dB ±Degrees ±% dB dB ±Degrees ±% ±% ±% Fout = 3.38 MHz Fsamp = 216 MHz Fout = 9.28 MHz Fsamp = 297 MHz — — 59 54 — — dBc dBc i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 94 Freescale Semiconductor Electrical Characteristics Table 59. TV Encoder Video Performance Specifications (continued) Parameter Chroma/Luma Delay Inequality VIDEO PERFORMANCE IN HD MODE2 Luma Frequency Response Chroma Frequency Response Luma Nonlinearity Chroma Nonlinearity Luma Signal-to-Noise Ratio Chroma Signal-to-Noise Ratio 1 2 Conditions — Min — Typ 1.0 Max — Unit ±ns 0-30 MHz 0-15 MHz, YCbCr 422 mode — — 0-30 MHz 0-15 MHz –0.2 –0.2 — — — — — — 3.2 3.4 62 72 0.2 0.2 — — — — dB dB % % dB dB Guaranteed by design. Guaranteed by characterization. 4.7.8.8 Asynchronous Interfaces The following sections describes the types of asynchronous interfaces. 4.7.8.8.1 Standard Parallel Interfaces The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s internal control levels (0 or 1) by UP and DOWN that are defined in registers. Each asynchronous pin has a dynamic connection with one of the signal generators. This connection is redefined again with a new display access (pixel/component). The IPU can generate control signals according to system 80/68 requirements. The burst length is received as a result from predefined behavior of the internal signal generator machines. The access to a display is realized by the following: • CS (IPP_CS) chip select • WR (IPP_PIN_11) write strobe • RD (IPP_PIN_12) read strobe • RS (IPP_PIN_13) Register select (A0) Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 50, Figure 51, Figure 52, and Figure 53. The timing images correspond to active-low IPP_CS, WR and RD signals. Each asynchronous access is defined by an access size parameter. This parameter can be different between different kinds of accesses. This parameter defines a length of windows, when suitable controls of the current access are valid. A pause between two different display accesses can be guaranteed by programing suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control signal can be switched at any time during access size. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 95 Electrical Characteristics IPP_CS RS WR RD IPP_DATA Burst access mode with sampling by CS signal IPP_CS RS WR RD IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 50. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 96 Freescale Semiconductor Electrical Characteristics IPP_CS RS WR RD IPP_DATA Burst access mode with sampling by WR/RD signals IPP_CS RS WR RD IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 51. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 97 Electrical Characteristics IPP_CS RS WR (READ/WRITE) RD (ENABLE) IPP_DATA Burst access mode with sampling by CS signal IPP_CS RS WR (READ/WRITE) RD (ENABLE) IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 98 Freescale Semiconductor Electrical Characteristics IPP_CS RS WR (READ/WRITE) RD (ENABLE) IPP_DATA Burst access mode with sampling by ENABLE signal IPP_CS RS WR (READ/WRITE) RD (ENABLE) IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 53. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 54 shows timing of the parallel interface with IPP_WAIT control. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 99 Electrical Characteristics DI clock IPP_CS IPP_DATA WR RD IPP_WAIT IPP_DATA_IN IP39 waiting waiting Figure 54. Parallel Interface Timing Diagram—Read Wait States 4.7.8.8.2 Asynchronous Parallel Interface Timing Parameters Figure 55 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 61 shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 100 Freescale Semiconductor Electrical Characteristics IP29 IP35 IP33 IP32 IP36 IP34 IP47 IP30 IP31 DI clock IPP_CS RS WR RD IPP_DATA PP_DATA_IN IP28a local start point local start point local start point IP28d local start point IP27 local start point A0 D0 D1 D2 IP37 D3 IP38 Figure 55. Asynchronous Parallel Interface Timing Diagram Table 60. Asynchronous Display Interface Timing Parameters (Pixel Level) ID IP27 IP28a IP28d IP29 IP30 IP31 IP32 IP33 Parameter Read system cycle time Symbol Tcycr Value ACCESS_SIZE_# ACCESS_SIZE_# ACCESS_SIZE_# UP# UP# DOWN# DOWN# UP# Description predefined value in DI REGISTER predefined value in DI REGISTER predefined value in DI REGISTER RS strobe switch, predefined value in DI REGISTER CS strobe switch, predefined value in DI REGISTER CS strobe release, predefined value in DI REGISTER RS strobe release, predefined value in DI REGISTER read strobe switch, predefined value in DI REGISTER Unit ns ns ns ns ns — — ns Address Write system cycle time Tcycwa Data Write system cycle time RS start CS start CS hold RS hold Read start Tcycwd Tdcsrr Tdcsc Tdchc Tdchrr Tdcsr i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 101 Electrical Characteristics Table 60. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued) ID IP34 IP35 IP36 IP37 Read hold Write start Controls hold time for write Slave device data delay1 Parameter Symbol Tdchr Tdcsw Tdchw Tracc Value DOWN# UP# DOWN# Delay of incoming data Description read strobe release signal, predefined value in DI REGISTER write strobe switch, predefined value in DI REGISTER write strobe release, predefined value in DI REGISTER Physical delay of display’s data, defined from Read access local start point Unit ns ns ns ns IP38 IP47 1This Slave device data hold time Read time point Troh Tdrp Hold time of data on the buss Time that display read data is valid in input bus Data sampling point Point of input data sampling by DI, predefined in DC Microcode ns — parameter is a requirement to the display connected to the IPU. Table 61. Asynchronous Parallel Interface Timing Parameters (Access Level) ID Parameter Symbol Tcycr Tcycw Tdcsrr Tdcsc Tdchc Tdchrr Tdcsr Tdchr Tdcsw Tdchw Tracc Troh Min Tdicpr – 1.24 Tdicpw – 1.24 Tdicurs – 1.24 Tdicucs – 1.24 Tdicdcs – Tdicucs – 1.2 4 Tdicpr2 Tdicpw3 Tdicurs Tdicur Tdicdcs4–Tdicucs5 Typ1 Max Tdicpr+1.24 Tdicpw+1.24 Tdicurs+1.24 Tdicucs+1.24 Tdicdcs – Tdicucs+1.24 Tdicdrs – Tdicurs+1.24 Tdicur+1.24 Tdicdr – Tdicur+1.24 Tdicuw+1.24 Unit ns ns ns ns ns ns ns ns ns ns ns ns IP27 Read system cycle time IP28 Write system cycle time IP29 RS start IP30 CS start IP31 CS hold IP32 RS hold IP33 Controls setup time for read IP34 Controls hold time for read IP35 Controls setup time for write IP36 Controls hold time for write IP37 Slave device data delay12 IP38 Slave device data hold time8 Tdicdrs – Tdicurs – 1.24 Tdicdrs6–Tdicurs7 Tdicur – 1.24 Tdicdr – Tdicur – 1.24 Tdicuw – 1.24 Tdicur Tdicdr8–Tdicur9 Tdicuw Tdicdw – Tdicuw – 1.24 Tdicpw10–Tdicuw11 Tdicdw–Tdicuw+1.24 0 Tdrp – Tlbd – Tdicdr+1. 24 — — Tdrp13 – Tlbd14 –Tdicur–1. 24 Tdicpr – Tdicdr – 1.24 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 102 Freescale Semiconductor Electrical Characteristics Table 61. Asynchronous Parallel Interface Timing Parameters (Access Level) (continued) ID Parameter Symbol Min — Tdrp – 1.24 Tdrp Typ1 — Tdrp+1.24 Max — Unit — ns IP39 Setup time for wait signal Tswait IP47 Read time point 1 Tdrp The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display period value for read DI_ACCESS_SIZE_# Tdicpr = T DI_CLK × ceil ---------------------------------------------------DI_CLK_PERIOD ACCESS_SIZE is predefined in REGISTER. 3 Display period value for write DI_ACCESS_SIZE_# Tdicpw = T DI_CLK × ceil ---------------------------------------------------DI_CLK_PERIOD ACCESS_SIZE is predefined in REGISTER. 4Display control down for CS 2 × DISP_DOWN_# Tdicdcs = 1 ⎛ T DI_CLK × ceil ------------------------------------------------- ⎞ -- ⎝ DI_CLK_PERIOD ⎠ 2 DISP_DOWN is predefined in REGISTER. 5Display control up for CS 2 × DISP_UP_# Tdicucs = 1 ⎛ T DI_CLK × ceil --------------------------------------------- ⎞ -DI_CLK_PERIOD ⎠ 2⎝ DISP_UP is predefined in REGISTER. 6Display control down for RS 2 × DISP_DOWN_# Tdicdrs = 1 ⎛ T DI_CLK × ceil ------------------------------------------------- ⎞ -DI_CLK_PERIOD ⎠ 2⎝ DISP_DOWN is predefined in REGISTER. 7Display control up for RS 2 × DISP_UP_# Tdicurs = 1 ⎛ T DI_CLK × ceil --------------------------------------------- ⎞ -- ⎝ DI_CLK_PERIOD ⎠ 2 DISP_UP is predefined in REGISTER. 8 Display control down for read 2 × DISP_DOWN_# Tdicdr = 1 ⎛ T DI_CLK × ceil ------------------------------------------------- ⎞ -DI_CLK_PERIOD ⎠ 2⎝ DISP_DOWN is predefined in REGISTER. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 103 Electrical Characteristics 9 Display control up for read 2 × DISP_UP_# 1 Tdicur = -- ⎛ T DI_CLK × ceil --------------------------------------------- ⎞ DI_CLK_PERIOD ⎠ 2⎝ DISP_UP is predefined in REGISTER. 10 Display control down for read 2 × DISP_DOWN_# Tdicdrw = 1 ⎛ T DI_CLK × ceil ------------------------------------------------- ⎞ -- ⎝ DI_CLK_PERIOD ⎠ 2 DISP_DOWN is predefined in REGISTER. 11 Display control up for write 2 × DISP_UP_# Tdicuw = 1 ⎛ T DI_CLK × ceil --------------------------------------------- ⎞ -DI_CLK_PERIOD ⎠ 2⎝ DISP_UP is predefined in REGISTER. 12This parameter is a requirement to the display connected to the IPU. 13Data read point DISP#_READ_EN Tdrp = T DI_CLK × ceil --------------------------------------------DI_CLK_PERIOD Note: DISP#_READ_EN—operand of DC’s MICROCDE READ command to sample incoming data. 14Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific. 4.7.8.9 Standard Serial Interfaces The IPU supports the following types of asynchronous serial interfaces: 1. 3-wire (with bidirectional data line). 2. 4-wire (with separate data input and output lines). 3. 5-wire type 1 (with sampling RS by the serial clock). 4. 5-wire type 2 (with sampling RS by the chip select signal). The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire interfaces. Figure 56 depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal. For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 104 Freescale Semiconductor Electrical Characteristics DISPB_D#_CS programed delay programed delay DISPB_SD_D_CLK DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0 Preamble Input or output data Figure 56. 3-Wire Serial Interface Timing Diagram Figure 57 depicts timing diagram of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the chip. Write DISPB_D#_CS programed delay programed delay DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) RW RS D7 D6 D5 D4 D3 D2 D1 D0 Output data Read DISPB_D#_CS programed delay programed delay DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 Input data Figure 57. 4-Wire Serial Interface Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 105 Electrical Characteristics Figure 58 depicts timing of the 5-wire serial interface. For this interface, a separate RS line is added. Write DISPB_D#_CS programed delay programed delay DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 D4 D3 D2 D1 D0 Preamble DISPB_SD_D (Input) programed delay Output data DISPB_SER_RS Read DISPB_D#_CS programed delay programed delay DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW DISPB_SER_RS programed delay Input data Figure 58. 5-Wire Serial Interface Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 106 Freescale Semiconductor Electrical Characteristics 4.7.8.9.1 Asynchronous Serial Interface Timing Parameters Figure 59 depicts timing of the serial interface. Table 62 shows timing characteristics at display access level. IP73 IP72 DI clock IPP_DISPB_DO_SD_D IPP_DO_DISPB_SER_CS IP71 IP70 IPP_DO_DISPB_SER_RS IP68 IP58 IPP_IND_DISPB_SD_D IP59 IP60, IP64, IP66 IP69 IP50, IP52 IP55, IP57, IP61 IP54, IP56, IP65, IP67 IPP_DO_DISPB_SD_D_CLK local start point IP51,53 IP48, IP49, IP62, IP63 Figure 59. Asynchronous Serial Interface Timing Diagram Table 62. Asynchronous Serial Interface Timing Characteristics (Access Level) ID Parameter Symbol Tcycr Tcycw Trl Min Tdicpr–1.24 Tdicpw–1.24 Tdicdr–Tdicur–1.24 Tdicpr–Tdicdr+Tdicur– 1.24 Typ1 Tdicpr2 Tdicpw 3 Max Tdicpr+1.24 Tdicpw+1.24 Tdicdr–Tdicur+1.24 Tdicpr–Tdicdr+Tdicur+ 1.24 Unit ns ns ns ns IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width Tdicdr4–Tdicur5 Tdicpr–Tdicdr+ Tdicur IP51 Read clock high pulse width Trh i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 107 Electrical Characteristics Table 62. Asynchronous Serial Interface Timing Characteristics (Access Level) (continued) ID Parameter Symbol Twl Twh Tdcsr Tdchr Min Tdicdw – Tdicuw – 1.24 Tdicpw – Tdicdw + Tdicuw – 1.24 Tdicur–1.24 Tdicpr – Tdicdr – 1.24 Tdicuw – 1.24 Tdicpw – Tdicdw – 1.24 0 7 Typ1 Max Unit ns ns ns ns ns ns ns IP52 Write clock low pulse width IP53 Write clock high pulse width IP54 Controls setup time for read IP55 Controls hold time for read Tdicdw6 –Tdicuw Tdicdw – Tdicuw+1.24 Tdicpw–Tdicdw+ Tdicpw – Tdicdw+ Tdicuw Tdicuw+1.24 Tdicur Tdicpr – Tdicdr Tdicuw Tdicpw–Tdicdw — — — — — Tdrp9 – Tlbd10 – Tdicur – 1.24 Tdicpr – Tdicdr – 1.24 — — Tdicpr+1.24 Tdicpw+1.24 Tdicdr+1.24 Tdicur+1.24 Tdicdw+1.24 Tdicuw+1.24 Tdrp+1.24 Toclk+1.24 Tdicurs+1.24 Tdicdrs+1.24 Tdicucs+1.24 Tdicdcs+1.24 IP56 Controls setup time for write Tdcsw IP57 Controls hold time for write IP58 Slave device data delay8 Tdchw Tracc IP59 Slave device data hold time8 Troh IP60 Write data setup time IP61 Write data hold time IP62 Read period IP63 Write period IP64 Read down time IP65 Read up time IP66 Write down time IP67 Write up time IP68 Read time point IP69 Clock offset11 IP70 RS up time12 IP71 RS down time13 IP72 CS up time14 Tds Tdh Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp Toclk Tdicurs Tdicdrs Tdrp – Tlbd – Tdicdr+1.24 Tdicdw – 1.24 Tdicpw – Tdicdw – 1.24 Tdicpr – 1.24 Tdicpw – 1.24 Tdicdr – 1.24 Tdicur – 1.24 Tdicdw – 1.24 Tdicuw – 1.24 Tdrp – 1.24 Toclk – 1.24 Tdicurs– 1.24 Tdicdrs – 1.24 Tdicdw — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Tdicpw – Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp Toclk Tdicurs Tdicdrs Tdicucs Tdicdcs Tdicucs Tdicucs – 1.24 Tdicdcs Tdicdcs – 1.24 IP73 CS down time15 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2Display interface clock period value for read DISP#_IF_CLK_PER_RD Tdicpr = T DI_CLK × ceil --------------------------------------------------------------DI_CLK_PERIOD 3 Display interface clock period value for write DISP#_IF_CLK_PER_WR Tdicpw = T DI_CLK × ceil ----------------------------------------------------------------DI_CLK_PERIOD i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 108 Freescale Semiconductor Electrical Characteristics 4 Display interface clock down time for read 2 × DISP_DOWN_# 1 Tdicdr = -- ⎛ T DI_CLK × ceil ------------------------------------------------- ⎞ DI_CLK_PERIOD ⎠ 2⎝ 5 Display interface clock up time for read 2 × DISP_UP_# Tdicur = 1 ⎛ T DI_CLK × ceil --------------------------------------------- ⎞ -- ⎝ DI_CLK_PERIOD ⎠ 2 6 Display interface clock down time for write 2 × DISP_DOWN_# Tdicdw = 1 ⎛ T DI_CLK × ceil ------------------------------------------------- ⎞ -DI_CLK_PERIOD ⎠ 2⎝ 7 Display interface clock up time for write 2 × DISP_UP_# Tdicuw = 1 ⎛ T DI_CLK × ceil --------------------------------------------- ⎞ -- ⎝ DI_CLK_PERIOD ⎠ 2 8This 9Data parameter is a requirement to the display connected to the IPU. read point DISP_READ_ENTdrp = T DI_CLK × ceil --------------------------------------------DI_CLK_PERIOD DISP_RD_EN is predefined in REGISTER. 10Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific. 11Display interface clock offset value DISP_CLK_OFFSET Toclk = T DI_CLK × ceil --------------------------------------------------DI_CLK_PERIOD CLK_OFFSET is predefined in REGISTER. 12Display RS up time DISP_RS_UP_# Tdicurs = T DI_CLK × ceil --------------------------------------------DI_CLK_PERIOD DISP_RS_UP is predefined in REGISTER. 13 Display RS down time DISP_RS_DOWN_# Tdicdrs = T DI_CLK × ceil -------------------------------------------------DI_CLK_PERIOD DISP_RS_DOWN is predefined in REGISTER. 14Display RS up time DISP_CS_UP_# Tdicucs = T DI_CLK × ceil --------------------------------------------DI_CLK_PERIOD DISP_CS_UP is predefined in REGISTER. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 109 Electrical Characteristics 15 Display RS down time DISP_CS_DOWN_# Tdicdcs = ( T DI_CLK × ceil ) -------------------------------------------------DI_CLK_PERIOD DISP_CS_DOWN is predefined in REGISTER. 4.7.9 LVDS Display Bridge (LDB) Module Parameters The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”. 4.7.10 MediaLB (MLB) Controller AC Timing Electrical Specifications This section describes the timing electrical information of the MediaLB Controller module. Figure 60 and Figure 61 show the timing of MediaLB Controller, and Table 63 and Table 64 lists the MediaLB controller timing characteristics. Figure 60. MediaLB Timing Figure 61. MediaLB Pulse Width Variation Timing i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 110 Freescale Semiconductor Electrical Characteristics Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted. Table 63. MLB 256/512 Fs Timing Parameters Parameter MLBCLK operating frequency1 Symbol fmck Min 11.264 12.288 24.576 24.6272 25.600 MLBCLK rise time MLB fall time MLBCLK cycle time MLBCLK low time tmckr tmckf tmckc tmckl — — — — 31.5 30 14.5 14 MLBCLK high time tmckh 31.5 30 14.5 14 MLBCLK pulse width variation MLBSIG/MLBDAT input valid to MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK low MLBSIG/MLBDAT output high impedance from MLBCLK low Bus Hold Time 1 2 Typ Max Units MHz Comment Min: 256*fs at 44.0 kHz Typ: 256*fs at 48.0 kHz Typ: 512*fs at 48.0 kHz Max: 512*fs at 48.1 kHz Max: 512*fs PLL unlocked VIL TO VIH VIH TO VIL 256*Fs 512*Fs 256*Fs 256*Fs PLL unlocked 512*Fs 512*Fs PLL unlocked 256*Fs 256*Fs PLL unlocked 512*Fs 512*Fs PLL unlocked Note2 — — — Note3 — — 81 40 37 35.5 17 16.5 38 36.5 17 16.5 — — — — — 3 3 — — — — — — — — — — 2 — — tmckl — ns ns ns ns ns ns ns ns pp ns ns ns ns tmpwv tdsmcf tdhmcf tmcfdz tmdzh — 1 0 0 4 The MLB controller can shut off MLBCLK to place MediaLB in a low-power state. Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp) 3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as listed in Table 64; unless otherwise noted. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 111 Electrical Characteristics Table 64. MLB Device 1024 Fs Timing Parameters Parameter MLBCLK Operating Frequency1 Symbol fmck Min 45.056 49.152 49.2544 51.200 MLBCLK rise time MLB fall time MLBCLK cycle time MLBCLK low time MLBCLK high time MLBCLK pulse width variation MLBSIG/MLBDAT input valid to MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK low MLBSIG/MLBDAT output high impedance from MLBCLK low Bus Hold Time 1 2 Typ Max Units MHz Comment Min: 1024*fs at 44.0 kHz Typ: 1024*fs at 48.0 kHz Max: 1024fs*fs at 48.1 kHz Max: 1024*fs PLL unlocked VIL TO VIH VIH TO VIL — PLL unlocked tmckr tmckf tmckc tmckl tmckh tmpwv tdsmcf tdhmcf tmcfdz tmdzh — — — 6.5 6.1 9.7 9.3 — 1 0 0 2 — — 20.3 7.7 7.3 10.6 10.2 — — — — — 1 1 — — — — 0.7 — — tmckl — ns ns ns ns ns PLL unlocked ns pp ns ns ns ns Note2 — — — Note3 The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state. Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp). 3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. 4.7.11 One-Wire (OWIRE) Timing Parameters Figure 62 depicts the RPP timing, and Table 65 lists the RPP timing parameters. One-WIRE Tx “Reset Pulse” One-Wire bus (BATT_LINE) One Wire Device Tx “Presence Pulse” OW2 OW1 tR OW3 OW4 Figure 62. Reset and Presence Pulses (RPP) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 112 Freescale Semiconductor Electrical Characteristics Table 65. RPP Sequence Delay Comparisons Timing Parameters ID OW1 OW2 OW3 OW4 1 Parameters Reset Time Low Presence Detect High Presence Detect Low Reset Time High (includes recovery time) Symbol tRSTL tPDH tPDL tRSTH Min 480 15 60 480 Typ 511 — — 512 Max —1 60 240 — Unit µs µs µs µs In order not to mask signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 µs. Figure 63 depicts Write 0 Sequence timing, and Table 66 lists the timing parameters. OW6 One-Wire bus (BATT_LINE) tREC OW5 Figure 63. Write 0 Sequence Timing Diagram Table 66. WR0 Sequence Timing Parameters ID OW5 OW6 Parameter Write 0 Low Time Transmission Time Slot Recovery time Symbol tLOW0 tSLOT tREC Min 60 OW5 1 Typ 100 117 — Max 120 120 — Unit µs µs µs Figure 64 depicts Write 1 Sequence timing, Figure 65 depicts the Read Sequence timing, and Table 67 lists the timing parameters. OW8 One-Wire bus (BATT_LINE) OW7 Figure 64. Write 1 Sequence Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 113 Electrical Characteristics OW8 One-Wire bus (BATT_LINE) tSU OW9 OW10 OW11 Figure 65. Read Sequence Timing Diagram Table 67. WR1 /RD Timing Parameters ID OW7 OW8 Parameter Write 1 Low Time Transmission Time Slot Read Data Setup OW9 OW10 OW11 Read Low Time Read Data Valid Release Time Symbol tLOW1 tSLOT tSU tLOWR tRDV tRELEASE Min 1 60 — 1 — 0 Typ 5 117 — 5 15 — Max 15 120 1 15 — 45 Unit µs µs µs µs µs µs 4.7.12 Pulse Width Modulator (PWM) Timing Parameters This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Figure 66 depicts the timing of the PWM, and Table 68 lists the PWM timing parameters. 2a System Clock 2b 3a 4a PWM Output 1 3b 4b Figure 66. PWM Timing i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 114 Freescale Semiconductor Electrical Characteristics Table 68. PWM Output Timing Parameter Ref. No. 1 2a 2b 3a 3b 4a 4b 1 Parameter System CLK frequency1 Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time Min 0 12.29 9.91 — — — 8.71 Max ipg_clk — — 0.5 0.5 9.37 — Unit MHz ns ns ns ns ns ns CL of PWMO = 30 pF 4.7.13 PATA Timing Parameters This section describes the timing parameters of the Parallel ATA module which are compliant with ATA/ATAPI-6 specification. Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA module interface consist of a total of 29 pins. Some pins act on different function in different transfer mode. There are different requirements of timing relationships among the function pins conform with ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers. Table 69 and Figure 67 define the AC characteristics of all the PATA interface signals in all data transfer modes. ATA Interface Signals SI2 SI1 Figure 67. PATA Interface Signals Timing Diagram Table 69. AC Characteristics of All Interface Signals ID SI1 SI2 SI3 1 Parameter Rising edge slew rate for any signal on ATA interface1 Falling edge slew rate for any signal on ATA interface1 Host interface signal capacitance at the host connector Symbol Srise Sfall Chost Min — — — Max 1.25 1.25 20 Unit V/ns V/ns pF SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with all capacitive loads from 15–40 pF where all signals have the same capacitive load value. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 115 Electrical Characteristics The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xA PATA interface is 3.3 V compatible. The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided. In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX53xA PATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 70 shows ATA timing parameters. Table 70. PATA Timing Parameters Name T ti_ds Description Bus clock period (AHB_CLK_ROOT) Set-up time ata_data to ata_iordy edge (UDMA-in only) UDMA0 UDMA1 UDMA2, UDMA3 UDMA4 UDMA5 ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only) UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 UDMA5 Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en Set-up time ata_data to bus clock L-to-H Set-up time ata_iordy to bus clock H-to-L Hold time ata_iordy to bus clock H to L Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals: ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) 15 ns 10 ns 7 ns 5 ns 4 ns 5.0 ns 4.6 ns 12.0 ns Value/ Contributing Factor1 Peripheral clock frequency (7.5 ns for 133 MHz clock) tco tsu tsui thi tskew1 8.5 ns 8.5 ns 2.5 ns 7 ns tskew2 Transceiver tskew3 Transceiver i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 116 Freescale Semiconductor Electrical Characteristics Table 70. PATA Timing Parameters (continued) Name tbuf tcable1 tcable2 tskew4 tskew5 tskew6 1 Description Max buffer propagation delay Cable propagation delay for ata_data Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack Max difference in cable propagation delay between ata_iordy and ata_data (read) Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) Max difference in cable propagation delay without accounting for ground bounce Value/ Contributing Factor1 Transceiver Cable Cable Cable Cable Cable Values provided where applicable. 4.7.13.1 PIO Mode Read Timing Figure 68 shows timing for PIO read. Table 71 lists the timing parameters for PIO read. Figure 68. PIO Read Timing Diagram Table 71. PIO Read Timing Parameters ATA Parameter Parameter from Figure 68 t1 t2 (read) t9 t5 t6 tA trd t1 t2r t9 t5 t6 tA trd1 Value t1(min) = time_1 * T – (tskew1 + tskew2 + tskew5) t2(min) = time_2r * T – (tskew1 + tskew2 + tskew5) t9(min) = time_9 * T – (tskew1 + tskew2 + tskew6) t5(min) = tco + tsu + tbuf + tbuf+ tcable1 + tcable2 0 tA(min) = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) trd1(max) = (–trd)+ (tskew3 + tskew4) trd1(min) = (time_pio_rdx – 0.5)*T – (tsu + thi) (time_pio_rdx – 0.5) * T > tsu + thi + tskew3 + tskew4 t0(min) = (time_1 + time_2r+ time_9) * T Controlling Variable time_1 time_2r time_9 time_2 (affects tsu and tco) — time_ax time_pio_rdx t0 — time_1, time_2r, time_9 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 117 Electrical Characteristics Figure 69 shows timing for PIO write. Table 72 lists the timing parameters for PIO write. Figure 69. Multi-word DMA (MDMA) Timing Table 72. PIO Write Timing Parameters ATA Parameter Paramete from Figure 69 r t1 t2 (write) t9 t3 t4 tA t0 — — t1 t2w t9 — t4 tA — — — Value Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — t1(min) = time_1 * T – (tskew1 + tskew2 + tskew5) t2(min) = time_2w * T – (tskew1 + tskew2 + tskew5) t9(min) = time_9 * T – (tskew1 + tskew2 + tskew6) t3(min) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5) t4(min) = time_4 * T – tskew1 tA = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) t0(min) = (time_1 + time_2 + time_9) * T Avoid bus contention when switching buffer on by making ton long enough Avoid bus contention when switching buffer off by making toff long enough i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 118 Freescale Semiconductor Electrical Characteristics Figure 70 shows timing for MDMA read, Figure 71 shows timing for MDMA write, and Table 73 lists the timing parameters for MDMA read and write. Figure 70. MDMA Read Timing Diagram Figure 71. MDMA Write Timing Diagram Table 73. MDMA Read and Write Timing Parameters ATA Parameter tm, ti td tk t0 tg(read) tf(read) tg(write) tf(write) tL Parameter from Figure 70 (Read), Figure 71 (Write) tm td, td1 tk1 — tgr tfr — — — Value Controlling Variable time_m time_d time_k time_d, time_k time_d — time_d time_k time_d, time_k2 tm(min) = ti(min) = time_m * T – (tskew1 + tskew2 + tskew5) td1(min) = td(min) = time_d * T – (tskew1 + tskew2 + tskew6) tk(min) = time_k * T – (tskew1 + tskew2 + tskew6) t0(min) = (time_d + time_k) * T tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min-drive) = td – te(drive) tfr(min) = 5 ns tg(min-write) = time_d * T – (tskew1 + tskew2 + tskew5) tf(min-write) = time_k * T – (tskew1 + tskew2 + tskew6) tL (max) = (time_d + time_k – 2)×T – (tsu + tco + 2×tbuf + 2×tcable2) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 119 Electrical Characteristics Table 73. MDMA Read and Write Timing Parameters (continued) ATA Parameter tn, tj — 1 2 Parameter from Figure 70 (Read), Figure 71 (Write) tkjn ton toff Value Controlling Variable time_jn — tn= tj= tkjn = time_jn * T – (tskew1 + tskew2 + tskew6) ton = time_on × T – tskew1 toff = time_off × T – tskew1 tk1 in the MDMA figures (Figure 70 and Figure 71) equals (tk – 2*T). tk1 in the MDMA figures equals (tk – 2*T). 4.7.13.2 Ultra DMA (UDMA) Input Timing Figure 72 shows timing when the UDMA in transfer starts, Figure 73 shows timing when the UDMA in host terminates transfer, Figure 74 shows timing when the UDMA in device terminates transfer, and Table 74 lists the timing parameters for UDMA in burst. Figure 72. UDMA in Transfer Starts Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 120 Freescale Semiconductor Electrical Characteristics Figure 73. UDMA in Host Terminates Transfer Timing Diagram Figure 74. UDMA in Device Terminates Transfer Timing Diagram Table 74. UDMA in Burst Timing Parameters Parameter from Figure 72, Figure 73, Figure 74 tack tenv tds1 tdh1 ATA Parameter Description Controlling Variable tack tenv tds tdh tack (min) = (time_ack × T) – (tskew1 + tskew2) tenv (min) = (time_env × T) – (tskew1 + tskew2) tenv (max) = (time_env × T) + (tskew1 + tskew2) tds – (tskew3) – ti_ds > 0 tdh – (tskew3) – ti_dh > 0 time_ack time_env tskew3, ti_ds, ti_dh should be low enough i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 121 Electrical Characteristics Table 74. UDMA in Burst Timing Parameters (continued) Parameter from Figure 72, Figure 73, Figure 74 tc1 trp tx11 tmli1 tzah tdzfs tcvh ton toff2 (tcyc – tskew) > T trp (min) = time_rp × T – (tskew1 + tskew2 + tskew6) (time_rp × T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive) tmli1 (min) = (time_mlix + 0.4) × T tzah (min) = (time_zah + 0.4) × T tdzfs = (time_dzfs × T) – (tskew1 + tskew2) tcvh = (time_cvh ×T) – (tskew1 + tskew2) ton = time_on × T – tskew1 toff = time_off × T – tskew1 ATA Parameter Description Controlling Variable tcyc trp — tmli tzah tdzfs tcvh — 1 T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh — There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2 Make ton and toff big enough to avoid bus contention. 4.7.13.3 UDMA Output Timing Figure 75 shows timing when the UDMA out transfer starts, Figure 76 shows timing when the UDMA out host terminates transfer, Figure 77 shows timing when the UDMA out device terminates transfer, and Table 75 lists the timing parameters for UDMA out burst. Figure 75. UDMA Out Transfer Starts Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 122 Freescale Semiconductor Electrical Characteristics Figure 76. UDMA Out Host Terminates Transfer Timing Diagram Figure 77. UDMA Out Device Terminates Transfer Timing Diagram Table 75. UDMA Out Burst Timing Parameters Parameter from Figure 75, Figure 76, Figure 77 tack tenv tdvs tdvh tcyc — ATA Parameter Value Controlling Variable tack tenv tdvs tdvh tcyc t2cyc tack (min) = (time_ack × T) – (tskew1 + tskew2) tenv (min) = (time_env × T) – (tskew1 + tskew2) tenv (max) = (time_env × T) + (tskew1 + tskew2) tdvs = (time_dvs × T) – (tskew1 + tskew2) tdvs = (time_dvh × T) – (tskew1 + tskew2) tcyc = time_cyc × T – (tskew1 + tskew2) t2cyc = time_cyc × 2 × T time_ack time_env time_dvs time_dvh time_cyc time_cyc i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 123 Electrical Characteristics Table 75. UDMA Out Burst Timing Parameters (continued) Parameter from Figure 75, Figure 76, Figure 77 trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff ATA Parameter Value Controlling Variable trfs1 — tss tmli tli tli tli tcvh — trfs = 1.6 × T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs × T – (tskew1) tss = time_ss × T – (tskew1 + tskew2) tdzfs_mli =max (time_dzfs, time_mli) × T – (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh ×T) – (tskew1 + tskew2) ton = time_on × T – tskew1 toff = time_off × T – tskew1 — time_dzfs time_ss — — — — time_cvh — 4.7.14 SATA PHY Parameters This section describes SATA PHY electrical specifications. 4.7.14.1 Reference Clock Electrical and Jitter Specifications The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and 125 MHz are common frequencies). The frequency is pin-selectable (for more information about the signal, see “Per-Transceiver Control and Status Signals” in the SATA PHY chapter in the Reference Manual). Table 76 provides the SATA PHY reference clock specifications. Table 76. Reference Clock Specifications Parameters Differential peak voltage (typically 0.71 V) Common mode voltage (refclk_p + refclk_m) / 2 Total phase jitter Test Conditions — — For information about total phase jitter, see following section — — Min 350 Max 850 2,000 3 Unit mV mV ps RMS 175 — Minimum/maximum duty cycle Frequency range 40 25 60 156.25 % UI MHz i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 124 Freescale Semiconductor Electrical Characteristics 4.7.14.1.1 Reference Clock Jitter Measurement The total phase jitter on the reference clock is specified at 3 ps RMS. There are numerous ways to measure the reference clock jitter, one of which is as follows. Using a high-speed sampling scope (20 GSamples/s), 1 million samples of the differential reference clock are taken, and the zero-crossing times of each rising edge are calculated. From the zero-crossing data, an average reference clock period is calculated. This average reference clock period is subtracted from each sequential, instantaneous period to find the difference between each reference clock rising edge and the ideal placement to produce the phase jitter sequence. The power spectral density (PSD) of the phase jitter is calculated and integrated after being weighted with the transfer function shown in Figure 78. The square root of the resultant integral is the RMS total phase jitter. Figure 78. Weighting Function for RMS Phase Jitter Calculation 4.7.14.2 Transmitter and Receiver Characteristics The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA specification. The following subsections provide values obtained from a combination of simulations and silicon characterization. NOTE The tables in the following sections indicate any exceptions to the SATA specification or aspects of the SATA PHY that exceed the standard, as well as provide information about parameters not defined in the standard. 4.7.14.2.1 SATA PHY Transmitter Characteristics Table 77. SATA2 PHY Transmitter Characteristics Parameters Transmit common mode voltage Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) VCTM — Symbol Min 0.4 –0.5 Typ — — Max 0.6 0.5 Unit V dB Table 77 provides specifications for SATA PHY transmitter characteristics. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 125 Electrical Characteristics 4.7.14.2.2 SATA PHY Receiver Characteristics Table 78 provides specifications for SATA PHY receiver characteristics. Table 78. SATA PHY Receiver Characteristics Parameters Symbol Min — –400 Typ — — Max 175 400 Unit mV ppm Minimum Rx eye height (differential peak-to-peak) VMIN_RX_EYE_HEIGHT Tolerance PPM 4.7.14.3 SATA_REXT Reference Resistor Connection The impedance calibration process requires connection of reference resistor 191 Ω. 1% precision resistor on SATA_REXT pad to ground. Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT pin. The calibration register value is then supplied to all Tx and Rx termination resistors. During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor. 4.7.14.4 SATA Connectivity When Not in Use NOTE The Temperature Sensor is part of the SATA module. If SATA IP is disabled, the Temperature Sensor will not work as well. Temperature Sensor functionality is important in supporting high performance applications without overheating the device (at high ambient temp). When both SATA and thermal sensor are not required, connect VP and VPH supplies to ground. The rest of the ports, both inputs and outputs (SATA_REFCLKM, SATA_REFCLKP, SATA_REXT, SATA_RXM, SATA_RXP, SATA_TXM) can be left floating. It is not recommended to turn off the VPH while the VP is active. When SATA is not in use but thermal sensor is still required, both VP and VPH supplies must be powered on according to their nominal voltage levels. The reference clock input frequency must fall within the specified range of 25 MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the termination impedance is not of consequence. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 126 Freescale Semiconductor Electrical Characteristics 4.7.15 SCAN JTAG Controller (SJC) Timing Parameters Figure 79 depicts the SJC test clock input timing. Figure 80 depicts the SJC boundary scan timing. Figure 81 depicts the SJC test access port. Signal parameters are listed in Table 79. SJ1 SJ2 TCK (Input) SJ3 VIH VIL SJ3 VM SJ2 VM Figure 79. Test Clock Input Timing Diagram TCK (Input) VIL SJ4 Data Inputs SJ6 Data Outputs SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Output Data Valid SJ5 VIH Input Data Valid Figure 80. Boundary Scan (JTAG) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 127 Electrical Characteristics TCK (Input) VIL SJ8 TDI TMS (Input) SJ10 TDO (Output) SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Output Data Valid Input Data Valid SJ9 VIH Figure 81. Test Access Port Timing Diagram TCK (Input) SJ13 TRST (Input) SJ12 Figure 82. TRST Timing Diagram Table 79. JTAG Timing All Frequencies ID Parameter1,2 Min SJ0 SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8 TCK frequency of operation 1/(3•TDC)1 TCK cycle time in crystal mode TCK clock pulse width measured at VM2 TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time 0.001 45 22.5 — 5 24 — — 5 Max 22 — — 3 — — 40 40 — MHz ns ns ns ns ns ns ns ns Unit i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 128 Freescale Semiconductor Electrical Characteristics Table 79. JTAG Timing (continued) All Frequencies ID Parameter1,2 Min SJ9 SJ10 SJ11 SJ12 SJ13 1 2 Unit Max — 44 44 — — ns ns ns ns ns TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low 25 — — 100 40 TDC = target frequency of SJC VM = mid-point voltage 4.7.16 SPDIF Timing Parameters The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 80 shows SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK) for SPDIF in Tx mode. Table 80. SPDIF Timing Parameters Timing Parameter Range Characteristics Symbol Min SPDIFIN Skew: asynchronous inputs, no specs apply SPDIFOUT output (Load = 50pf) • Skew • Transition rising • Transition falling SPDIFOUT1 output (Load = 30pf) • Skew • Transition rising • Transition falling Modulating Rx clock (SRCK) period SRCK high period SRCK low period Modulating Tx clock (STCLK) period STCLK high period STCLK low period — — — — — — — — Max 0.7 1.5 24.2 31.3 ns ns Units — — — srckp srckph srckpl stclkp stclkph stclkpl — — — 40.0 16.0 16.0 40.0 16.0 16.0 1.5 13.6 18.0 — — — — — — ns ns ns ns ns ns ns i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 129 Electrical Characteristics srckp srckpl SRCK (Output) VM srckph VM Figure 83. SPDIF Timing Diagram stclkp stclkpl STCLK (Input) VM stclkph VM Figure 84. STCLK Timing 4.7.17 SSI Timing Parameters This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces are summarized in Table 81. Table 81. AUDMUX Port Allocation Port AUDMUX port 1 AUDMUX port 2 AUDMUX port 3 AUDMUX port 4 AUDMUX port 5 AUDMUX port 6 AUDMUX port 7 Signal Nomenclature SSI 1 SSI 2 AUD3 AUD4 AUD5 AUD6 SSI 3 Internal Internal External – AUD3 I/O External – EIM or CSPI1 I/O through IOMUXC External – EIM or SD1 I/O through IOMUXC External – EIM or DISP2 through IOMUXC Internal Type and Access • • NOTE The terms WL and BL used in the timing diagrams and tables refer to Word Length (WL) and Bit Length (BL). The SSI timing diagrams use generic signal names wherein the names used in the i.MX53 reference manual are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 130 Freescale Semiconductor Electrical Characteristics 4.7.17.1 SSI Transmitter Timing with Internal Clock Figure 85 depicts the SSI transmitter internal clock timing and Table 82 lists the timing parameters for the SSI transmitter internal clock. . SS1 SS2 TXC SS6 TXFS (bl) (Output) TXFS (wl) (Output) TXD SS16 SS10 SS8 SS5 SS4 SS3 SS12 SS14 SS15 SS17 SS18 SS43 SS42 RXD SS19 Note: SRXD input in synchronous mode only Figure 85. SSI Transmitter Internal Clock Timing Diagram Table 82. SSI Transmitter Timing with Internal Clock ID Parameter Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS6 SS8 SS10 SS12 SS14 SS15 SS16 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx/Rx) Internal FS rise time (Tx/Rx) Internal FS fall time (Tx) CK high to STXD valid from high impedance 81.4 36.0 — 36.0 — — — — — — — — — — 6.0 — 6.0 15.0 15.0 15.0 15.0 6.0 6.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 131 Electrical Characteristics Table 82. SSI Transmitter Timing with Internal Clock (continued) ID SS17 SS18 SS19 Parameter (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance STXD rise/fall time Synchronous Internal Clock Operation SS42 SS43 SS52 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling Loading 10.0 0.0 — — — 25.0 ns ns pF Min — — — Max 15.0 15.0 6.0 Unit ns ns ns • • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. The terms WL and BL refer to Word Length (WL) and Bit Length (BL). “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 132 Freescale Semiconductor Electrical Characteristics 4.7.17.2 SSI Receiver Timing with Internal Clock Figure 86 depicts the SSI receiver internal clock timing and Table 83 lists the timing parameters for the receiver timing with the internal clock SS1 SS2 TXC (Output) TXFS (bl) (Output) TXFS (wl) (Output) RXD SS47 SS48 RXC SS51 SS50 SS49 SS7 SS9 SS5 SS4 SS3 SS11 SS13 SS20 SS21 Figure 86. SSI Receiver Internal Clock Timing Diagram Table 83. SSI Receiver Timing with Internal Clock ID Parameter Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS7 SS9 SS11 SS13 SS20 SS21 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 81.4 36.0 — 36.0 — — — — — 10.0 0.0 — — 6.0 — 6.0 15.0 15.0 15.0 15.0 — — ns ns ns ns ns ns ns ns ns ns ns Min Max Unit i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 133 Electrical Characteristics Table 83. SSI Receiver Timing with Internal Clock (continued) ID Parameter Oversampling Clock Operation SS47 SS48 SS49 SS50 SS51 Oversampling clock period Oversampling clock high period Oversampling clock rise time Oversampling clock low period Oversampling clock fall time 15.04 6.0 — 6.0 — — — 3.0 — 3.0 ns ns ns ns ns Min Max Unit • • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. The terms WL and BL refer to Word Length (WL) and Bit Length (BL). For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 134 Freescale Semiconductor Electrical Characteristics 4.7.17.3 SSI Transmitter Timing with External Clock Figure 87 depicts the SSI transmitter external clock timing and Table 84 lists the timing parameters for the transmitter timing with the external clock SS22 SS23 SS25 SS26 SS24 TXC (Input) TXFS (bl) (Input) TXFS (wl) (Input) TXD SS45 SS44 RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS37 SS39 SS38 SS31 SS33 SS27 SS29 Figure 87. SSI Transmitter External Clock Timing Diagram Table 84. SSI Transmitter Timing with External Clock ID Parameter External Clock Operation SS22 SS23 SS24 SS25 SS26 SS27 SS29 SS31 SS33 SS37 SS38 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low 81.4 36.0 — 36.0 — –10.0 10.0 –10.0 10.0 — — — — 6.0 — 6.0 15.0 — 15.0 — 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns Min Max Unit i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 135 Electrical Characteristics Table 84. SSI Transmitter Timing with External Clock (continued) ID SS39 Parameter (Tx) CK high to STXD high impedance Synchronous External Clock Operation SS44 SS45 SS46 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling SRXD rise/fall time 10.0 2.0 — — — 6.0 ns ns ns Min — Max 15.0 Unit ns • • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. The terms WL and BL refer to Word Length (WL) and Bit Length (BL). For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 136 Freescale Semiconductor Electrical Characteristics 4.7.17.4 SSI Receiver Timing with External Clock Figure 88 depicts the SSI receiver external clock timing and Table 85 lists the timing parameters for the receiver timing with the external clock. SS22 SS26 SS23 SS25 SS24 TXC SS28 TXFS (bl) SS32 SS35 TXFS (wl) SS40 RXD SS41 SS36 SS34 SS30 Figure 88. SSI Receiver External Clock Timing Diagram Table 85. SSI Receiver Timing with External Clock ID Parameter External Clock Operation SS22 SS23 SS24 SS25 SS26 SS28 SS30 SS32 SS34 SS35 SS36 SS40 SS41 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low (Tx/Rx) External FS rise time (Tx/Rx) External FS fall time SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 81.4 36 — 36 — –10 10 –10 10 — — 10 2 — — 6.0 — 6.0 15.0 — 15.0 — 6.0 6.0 — — ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 137 Electrical Characteristics • • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. The terms WL and BL refer to Word Length (WL) and Bit Length (BL). For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). 4.7.18 4.7.18.1 UART I/O Configuration and Timing Parameters UART RS-232 I/O Configuration in Different Modes The i.MX53xA UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0 – DCE mode). Table 86 shows the UART I/O configuration based on the enabled mode. Table 86. UART I/O Configuration vs. Mode DTE Mode Port Direction RTS CTS DTR DSR DCD RI TXD_MUX RXD_MUX Output Input Output Input Input Input Input Output Description RTS from DTE to DCE CTS from DCE to DTE DTR from DTE to DCE DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Serial data from DTE to DCE Direction Input Output Input Output Output Output Output Input Description RTS from DTE to DCE CTS from DCE to DTE DTR from DTE to DCE DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Serial data from DTE to DCE DCE Mode 4.7.18.2 UART RS-232 Serial Mode Timing The following sections describe the electrical information of the UART module in the RS-232 mode. 4.7.18.2.1 UART Transmitter Figure 89 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 87 lists the UART RS-232 serial mode transmit timing characteristics. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 138 Freescale Semiconductor Electrical Characteristics Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT UA1 Start Bit UA1 TXD (output) Bit 0 Bit 1 Bit 2 Bit 3 Next Start Bit UA1 UA1 Figure 89. UART RS-232 Serial Mode Transmit Timing Diagram Table 87. RS-232 Serial Mode Transmit Timing Parameters ID UA1 1 2 Parameter Transmit Bit Time Symbol tTbit Min 1/Fbaud_rate1 – Tref_clk2 Max 1/Fbaud_rate + Tref_clk Units — Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). 4.7.18.2.2 UART Receiver Figure 90 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 88 lists serial mode receive timing characteristics. UA2 Start Bit UA2 Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT RXD (input) Bit 0 Bit 1 Bit 2 Bit 3 Next Start Bit UA2 UA2 Figure 90. UART RS-232 Serial Mode Receive Timing Diagram Table 88. RS-232 Serial Mode Receive Timing Parameters ID UA2 1 Parameter Receive Bit Time1 Symbol tRbit Min 1/Fbaud_rate2 – 1/(16*Fbaud_rate) Max 1/Fbaud_rate + 1/(16*Fbaud_rate) Units — The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16*Fbaud_rate). 2F baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 139 Electrical Characteristics 4.7.18.3 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. 4.7.18.3.3 UART IrDA Mode Transmitter Figure 91 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 89 lists the transmit timing characteristics. UA3 UA3 UA4 UA3 UA3 TXD (output) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT Figure 91. UART IrDA Mode Transmit Timing Diagram Table 89. IrDA Mode Transmit Timing Parameters ID UA3 UA4 1 2 Parameter Transmit Bit Time in IrDA mode Transmit IR Pulse Duration Symbol tTIRbit tTIRpulse Min 1/Fbaud_rate1 – Tref_clk2 (3/16)*(1/Fbaud_rate) – Tref_clk Max 1/Fbaud_rate + Tref_clk (3/16)*(1/Fbaud_rate) + Tref_clk Units — — Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). 4.7.18.3.4 UART IrDA Mode Receiver Figure 92 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 90 lists the receive timing characteristics. UA5 UA5 UA6 UA5 UA5 RXD (input) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT Figure 92. UART IrDA Mode Receive Timing Diagram Table 90. IrDA Mode Receive Timing Parameters ID UA5 UA6 Parameter Receive Bit Time1 in IrDA mode Receive IR Pulse Duration Symbol tRIRbit tRIRpulse Min 1/Fbaud_rate2 – 1/(16*Fbaud_rate) 1.41 us Max 1/Fbaud_rate + 1/(16*Fbaud_rate) (5/16)*(1/Fbaud_rate) Units — — i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 140 Freescale Semiconductor Electrical Characteristics 1 The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16*Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 4.7.19 USB-OH-3 Parameters This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip USB PHY parameters see Section 4.7.20, “USB PHY Parameters.” 4.7.19.1 Serial Interface In order to support four serial different interfaces, the USB serial transceiver can be configured to operate in one of four modes: • • • • DAT_SE0 bidirectional, 3-wire mode DAT_SE0 unidirectional, 6-wire mode VP_VM bidirectional, 4-wire mode VP_VM unidirectional, 6-wire mode DAT_SE0 Bidirectional Mode Table 91. Signal Definitions - DAT_SE0 Bidirectional Mode Name USB_TXOE_B USB_DAT_VP USB_SE0_VM Out Out In Out In Direction Signal Description Transmit enable, active low TX data when USB_TXOE_B is low Differential RX data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 RX indicator when USB_TXOE_B is high 4.7.19.1.1 Transmit USB_TXOE_B US3 USB_DAT_VP USB_SE0_VM US4 US1 US2 Figure 93. USB Transmit Waveform in DAT_SE0 Bidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 141 Electrical Characteristics Receive USB_TXOE_B USB_DAT_VP USB_SE0_VM US7 US8 USB_SE0_VM Figure 94. USB Receive Waveform in DAT_SE0 Bidirectional Mode Table 92. Definitions of USB Waveform in DAT_SE0 Bi-Directional Mode No. US1 US2 US3 US4 US7 US8 Parameter TX Rise/Fall Time TX Rise/Fall Time TX Rise/Fall Time TX Duty Cycle RX Rise/Fall Time RX Rise/Fall Time Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_DAT_VP USB_SE0_VM Direction Out Out Out Out In In Min -— — — 49.0 — — Max 5.0 5.0 5.0 51.0 3.0 3.0 Unit ns ns ns % ns ns Conditions / Reference Signal 50 pF 50 pF 50 pF — 35 pF 35 pF i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 142 Freescale Semiconductor Electrical Characteristics 4.7.19.1.2 DAT_SE0 Unidirectional Mode Table 93. Signal Definitions - DAT_SE0 Unidirectional Mode Direction Out Out Out In In Signal Description Transmit enable, active low TX data when USB_TXOE_B is low SE0 drive when USB_TXOE_B is low Buffered data on DP when USB_TXOE_B is high Buffered data on DM when USB_TXOE_B is high Name USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 Transmit USB_TXOE_B US11 USB_DAT_VP USB_SE0_VM US9 US12 US10 Figure 95. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 143 Electrical Characteristics Receive USB_TXOE_B USB_DAT_VP US15 US16 USB_SE0_VM Figure 96. USB Receive Waveform in DAT_SE0 Unidirectional Mode Table 94. USB Port Timing Specification in DAT_SE0 Unidirectional Mode No. US9 US10 US11 US12 US15 US16 Parameter TX Rise/Fall Time TX Rise/Fall Time TX Rise/Fall Time TX Duty Cycle RX Rise/Fall Time RX Rise/Fall Time Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_VP1 USB_VM1 Signal Source Out Out Out Out In In Min — — — 49.0 — — Max 5.0 5.0 5.0 51.0 3.0 3.0 Unit ns ns ns % ns ns Condition / Reference Signal 50 pF 50 pF 50 pF — 35 pF 35 pF i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 144 Freescale Semiconductor Electrical Characteristics 4.7.19.1.3 VP_VM Bidirectional Mode Table 95. Signal Definitions - VP_VM Bidirectional mode Name Direction Out Out (Tx) In (Rx) Out (Tx) In (Rx) Signal Description Transmit enable, active low TX VP data when USB_TXOE_B is low RX VP data when USB_TXOE_B is high TX VM data when USB_TXOE_B low RX VM data when USB_TXOE_B high USB_TXOE_B USB_DAT_VP USB_SE0_VM Transmit US20 USB_TXOE_B USB_DAT_VP USB_SE0_VM US18 US21 US22 US22 US19 Figure 97. USB Transmit Waveform in VP_VM Bidirectional Mode Receive US26 USB_DAT_VP USB_SE0_VM US28 US27 Figure 98. USB Receive Waveform in VP_VM Bidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 145 Electrical Characteristics Table 96. USB Port Timing Specification in VP_VM Bidirectional Mode No. Parameter TX Rise/Fall Time TX Rise/Fall Time TX Rise/Fall Time TX Duty Cycle TX Overlap RX Rise/Fall Time RX Rise/Fall Time RX Skew Signal Name Direction Min — — — Max Unit Condition / Reference Signal US18 US19 US20 US21 US22 US26 US27 US28 USB_DAT_V P USB_SE0_V M USB_TXOE _B USB_DAT_V P USB_SE0_V M USB_DAT_V P USB_SE0_V M USB_DAT_V P Out Out Out Out Out In In In 5.0 5.0 5.0 51.0 +3.0 3.0 3.0 +4.0 ns ns ns % ns ns ns ns 50 pF 50 pF 50 pF — 49.0 -3.0 — — USB_DAT_VP 35 pF 35 pF USB_SE0_VM -4.0 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 146 Freescale Semiconductor Electrical Characteristics 4.7.19.1.4 VP_VM Unidirectional Mode Table 97. Signal Definitions - VP_VM Unidirectional mode Direction Out Out Out In In Signal Description Transmit enable, active low TX VP data when USB_TXOE_B is low TX VM data when USB_TXOE_B is low RX VP data when USB_TXOE_B is high RX VM data when USB_TXOE_B is high Name USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 Transmit US32 USB_TXOE_B USB_DAT_VP USB_SE0_VM US30 US33 US31 US34 Figure 99. USB Transmit Waveform in VP_VM Unidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 147 Electrical Characteristics Receive USB_TXOE_B USB_VP1 US38 USB_VM1 US40 US39 Figure 100. USB Receive Waveform in VP_VM Unidirectional Mode Table 98. USB Timing Specification in VP_VM Unidirectional Mode No. US30 US31 US32 US33 US34 US38 US39 US40 Parameter TX Rise/Fall Time TX Rise/Fall Time TX Rise/Fall Time TX Duty Cycle TX Overlap RX Rise/Fall Time RX Rise/Fall Time RX Skew Signal USB_DAT_VP USB_SE0_V M USB_TXOE_ B USB_DAT_VP USB_SE0_V M USB_VP1 USB_VM1 USB_VP1 Direction Out Out Out Out Out In In In Min — — — 49.0 -3.0 — — -4.0 Max 5.0 5.0 5.0 51.0 3.0 3.0 3.0 +4.0 Unit ns ns ns % ns ns ns ns Conditions / Reference Signal 50 pF 50 pF 50 pF — USB_DAT_VP 35 pF 35 pF USB_VM1 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 148 Freescale Semiconductor Electrical Characteristics 4.7.19.2 Parallel Interface (Normal ULPI) Timing Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are presented in the subsequent sections. Table 99. Signal Definitions - Parallel Interface (Normal ULPI) Name USB_Clk USB_Data[7:0] USB_Dir USB_Stp USB_Nxt Direction Signal Description Interface clock. All interface signals are synchronous to Clock. Bi-directional data bus, driven low by the link during idle. Bus ownership is determined by Dir. Direction. Control the direction of the Data bus. Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. Next. The PHY asserts this signal to throttle the data. In I/O In Out In USB_Clk US15 USB_Dir/Nxt US15 USB_Data US16 US16 US17 USB_Stp US17 Figure 101. USB Transmit/Receive Waveform in Parallel Mode Table 100. USB Timing Specification for Normal ULPI mode ID US15 US16 US17 Parameter Setup Time(Dir&Nxt in, Data in) Hold Time(Dir&Nxt in, Data in) Output delay Time(Stp out, Data out Min — — — Max 6.0 0.0 9.0 Unit ns ns ns Conditions / Reference Signal 10 pF 10 pF 10 pF 4.7.20 USB PHY Parameters This section describes the USB-OTG PHY and the USB Host port PHY parameters. 4.7.20.1 USB PHY AC Parameters Table 101 lists the AC timing parameters for USB PHY. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 149 Electrical Characteristics Table 101. USB PHY AC Timing Parameters Parameter trise Conditions 1.5 Mbps 12 Mbps 480 Mbps 1.5 Mbps 12 Mbps 480 Mbps 1.5 Mbps 12 Mbps 480 Mbps Min 75 4 0.5 75 4 0.5 — Typ — Max 300 20 300 20 10 1 0.2 Unit ns tfall — ns Jitter — ns 4.7.20.2 USB PHY Additional Electrical Parameters Table 102. Additional Electrical Characteristics for USB PHY Parameter Conditions HS Mode LS/FS Mode LS Mode FS Mode < 160 MHz < 1.2 MHz > 1.2 MHz All conditions Min –0.05 0.8 1.3 1.3 –50 –10 –50 –50 Typ — — 0 0 0 0 Max 0.5 2.5 2 2 50 10 50 50 Unit V V mV mV mV Table 102 lists the parameters for additional electrical characteristics for USB PHY. Vcm DC (dc level measured at receiver connector) Crossover Voltage Power supply ripple noise (analog 3.3 V) Power supply ripple noise (analog 2.5 V) Power supply ripple noise (Digital 1.2 V) 4.7.20.3 USB PHY System Clocking (SYSCLK) Table 103. USB PHY System Clocking Parameters Table 103 lists the USB PHY system clocking parameters. Parameter Clock deviation Rise/fall time Jitter (peak-peak) Jitter (peak-peak) Duty-cycle Conditions Reference Clock frequency 24 MHz — < 1.2 MHz > 1.2 MHz Reference Clock frequency 24 MHz Min –150 — 0 0 40 Typ — — — — — Max 150 200 50 100 60 Unit ppm ps ps ps % i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 150 Freescale Semiconductor Electrical Characteristics 4.7.20.4 USB PHY Voltage Thresholds Table 104. VBUS Comparators Thresholds Parameter Conditions — — — — Min 0.8 0.8 0.2 4.4 Typ 1.4 1.4 0.45 4.6 Max 2.0 4.0 0.8 4.75 Unit V V V V Table 104 lists the USB PHY voltage thresholds. A-Device Session Valid B-Device Session Valid B-Device Session End VBUS Valid Comparator Threshold1 1 For VBUS maximum rating, see Table 4 on page 18 4.7.20.5 USB PHY Termination USB driver impedance in FS and HS modes is 45 Ω ±10% (steady state). No external resistors required. 4.8 XTAL and CKIL Electricals Table 105. XTALOSC Electrical Specifications Parameter Min 22 Typ 24 Max 27 Units MHz Table 105 shows the XTALOSC electrical specifications. Frequency WARNING Due to XTALOSC automatic level controller, the power consumption depends heavily on the working frequency, C-load and crystal quality. The above results are achieved at a frequency 24 MHz, 10 pF load capacitor, 7 pF crystal shunt capacitor and 80 Ω ESR. Table 106 shows the XTALOSC_32K electrical specifications. Table 106. XTALOSC_32K Electrical Specifications Parameter Frequency 1 Min -- Typ 32.768/32.01 Max -- Units kHz Recommended nominal frequency 32.768 kHz. Table 107 shows the CKIL electrical specifications. Table 107. CKIL Electrical Specifications Parameter Frequency Min 16 Typ 32.768 Max 50 Units kHz i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 151 Boot Mode Configuration 4.9 Integrated LDO Voltage Regulators Parameters The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage regulator (default case). In this case VDD_REG is used as internal regulator’s power source. The regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1. Table 108 shows the VDD_DIG_PLL and VDD_ANA_PLL Integrated Voltage Regulators Parameters. Table 108. LDO Voltage Regulators Electrical Specifications Parameter VDD_DIG_PLL functional Voltage Range1 VDD_ANA_PLL functional Voltage Range1 VDD_DIG_PLL and VDD_ANA_PLL accuracy VDD_DIG_PLL power-supply rejection ratio2 VDD_ANA_PLL power-supply rejection ratio2 Output current3 1 Symbol VVID_DIG_PLL VVDD_ANA_PLL — — — IVID_DIG_PLL+ IVDD_ANA_PLL Min 1.15 1.7 — — — — Typ 1.2 1.8 — –18 –15 — Max 1.3 1.95 +/–3 — — 125 Units V V % dB dB mA VDD_DIG_PLL and VDD_ANA_PLL voltages are programmable, but should not be set outside the target functional range for proper PLL operation. 2 The gain or attenuation from the input supply variation to the output of the LDO (by design). 3 The limitation is for sum of the VDD_DIG_PLL and VDD_ANA_PLL current. 5 Boot Mode Configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot Mode Configuration Pins Table 109 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the boot mode pins, see i.MX53 Fuse Map document and System Boot chapter in i.MX53 Reference Manual. Table 109. Fuses and Associated Pins Used for Boot Pin BOOT_MODE[1] BOOT_MODE[0] Direction at Reset Input Input E-Fuse Name N/A Details Boot Mode selection i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 152 Freescale Semiconductor Boot Mode Configuration Table 109. Fuses and Associated Pins Used for Boot (continued) Pin EIM_A22 EIM_A21 EIM_A20 EIM_A19 EIM_A18 EIM_A17 EIM_A16 EIM_LBA EIM_EB0 EIM_EB1 EIM_DA0 EIM_DA1 EIM_DA2 EIM_DA3 EIM_DA4 EIM_DA5 EIM_DA6 EIM_DA7 EIM_DA8 EIM_DA9 EIM_DA10 Direction at Reset Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input E-Fuse Name BOOT_CFG1[7]/Test Mode Selection Details Boot Options, Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’. BOOT_CFG1[6]/Test Mode Selection Signal Configuration as Fuse Override BOOT_CFG1[5]/Test Mode Selection Input at Power Up. These are special I/O lines that control the boot up configuration BOOT_CFG1[4] during product development. In production, the boot configuration can be controlled by BOOT_CFG1[3] fuses. BOOT_CFG1[2] BOOT_CFG1[1] BOOT_CFG1[0] BOOT_CFG2[7] BOOT_CFG2[6] BOOT_CFG2[5] BOOT_CFG2[4] BOOT_CFG2[3] BOOT_CFG2[2] BOOT_CFG3[7] BOOT_CFG3[6] BOOT_CFG3[5] BOOT_CFG3[4] BOOT_CFG3[3] BOOT_CFG3[2] BOOT_CFG3[1] 5.2 Boot Devices Interfaces Allocation Table 109 lists the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation, which are configured during boot when appropriate. Table 110. Interfaces Allocation During Boot Interface SPI SPI SPI IP Instance CSPI ECSPI-1 ECSPI-2 Allocated Pads During Boot EIM_A25, EIM_D21, EIM_D22, EIM_D28 EIM_D[19:16] CSI_DAT[10:8], EIM_LBA Comment Only SS1 is supported Only SS1 is supported Only SS1 is supported i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 153 Boot Mode Configuration Table 110. Interfaces Allocation During Boot (continued) Interface EIM IP Instance EIM EIM Allocated Pads During Boot Comment • Lower 16 bit data bus A/D multiplexed or upper 16 bit data bus non multiplexed • Only CS0 is supported. • 8/16 bit • NAND data can be muxed either over EIM data or PATA data • Only CS0 is supported 1, 4 or 8 bit 1, 4 or 8 bit 1, 4 or 8 bit 1, 4 or 8 bit — — — — NAND Flash EXTMC NAND SD/MMC SD/MMC SD/MMC SD/MMC I2C I2C I2C PATA eSDHCv2-1 eSDHCv2-2 eSDHCv3-3 eSDHCv2-4 I2C-1 I2C-2 I2C-3 PATA PATA_DATA[11:8], SD1_DATA[3:0], SD1_CMD, SD1_CLK PATA_DATA[15:12], SD2_CLK, SD2_CMD, SD2_DATA[3:0] PATA_RESET_B, PATA_IORDY, PATA_DA_0, PATA_DATA[3:0], PATA_DATA[11:8] PATA_DA1, PATA_DA_2, PATA_DATA[7:4], PATA_DATA[15:12] EIM_D21, EIM_D28 EIM_D16, EIM_EB2 EIM_D[18:17] PATA_DIOW, PATA_DMACK, PATA_DMARQ, PATA_BUFFER_EN, PATA_INTRQ, PATA_DIOR, PATA_RESET_B, PATA_IORDY, PATA_DA_[2:0], PATA_CS_[1:0], PATA_DATA[15:0] SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM, SATA_REXT, SATA_REFCLKM, SATA_REFCLKP CSI0_DAT[11:10] PATA_DMARQ, PATA_BUFFER_EN EIM_D24, EIM_D25 CSI0_DAT[13:12] CSI0_DAT[15:14] USB_H1_GPANAIO USB_H1_RREFEXT USB_H1_DP USB_H1_DN USB_H1_VBUS SATA UART UART UART UART UART USB SATA_PHY UARTv2-1 UARTv2-2 UARTv2-3 UARTv2-4 UARTv2-5 USB-OTG PHY — RXD/TXD only RXD/TXD only RXD/TXD only RXD/TXD only RXD/TXD only — 5.3 Power setup during Boot By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to achieve the standard operating mode (see VDD_DIG_PLL on Table 6), LDO output to VDD_DIG_PLL should be configured by software by boot code after power-up to 1.3 V output. This is done by programming the PLL1P2_VREG bits. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 154 Freescale Semiconductor Package Information and Contact Assignments 6 6.1 Package Information and Contact Assignments 19x19 mm Package Information This section includes the contact assignment information and mechanical package drawing. This section contains the outline drawing, signal assignment map, ground/power reference ID (by ball grid location) for the 19 × 19 mm, 0.8 mm pitch package. 6.1.1 Case TEPBGA-2, 19 x 19 mm, 0.8 mm Pitch, 23 x 23 Ball Matrix Figure 102 shows the top view of the 19×19 mm package, Figure 103 shows the bottom view and the ball location (529 solder balls) of the 19×19 mm package, and Figure 104 shows the side view of the 19×19 mm package. Figure 102. 19 x 19 mm Package Top View i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 155 Package Information and Contact Assignments Figure 103. 19 x 19 mm Package, 529 Solder Balls, Bottom View Figure 104. 19 x 19 mm Package Side View i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 156 Freescale Semiconductor Package Information and Contact Assignments The following notes apply to Figure 102, Figure 103, and Figure 104. 1. All dimensions are in milimeters. 2. Dimensions and tolerencing per ASME Y14.5M1–994. 6.1.2 19 x 19 mm Signal Assignments, Power Rails, and I/O Table 111 shows the device connection list for ground, power, sense, and reference contact signals. Table 112 displays an alpha-sorted list of the signal assignments including associated power supplies. The table also includes out of reset pad state. Table 113 shows the package ball map. 6.1.2.1 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments Table 111 shows the device connection list for ground, power, sense, and reference contact signals alpha-sorted by name. Table 111. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments Package Pin Name DDR_VREF GND L17 A1, A11, A13, A18, A2, A22, A23, AA11, AA15, AA20, AA21, AB1, AB18, AB2, AB22, AB23, AC1, AC18, AC2, AC22, AC23, B1, B11, B13, B18, B23, C12, C20, C21, D19, E19, F19, F20, F21, F22, G19, G7, H10, H12, H8, J11, J13, J15, J17, J20, J9, K10, K12, K14, K16, K21, K8, L11, L13, L15, L7, L9, M10, M12, M14, M16, M8, N11, N13, N15, N9, P10, P12, P14, P16, P21, P7, P8, R11, R13, R15, R17, R20, R9, T10, T14, T16, T8, U15, U19, V15, V18, V19, V20, V21, V22, W19, Y14, Y15, Y19 G17 R7 U10, U9 U7 H18, K17, N17, P17, T18 F11 F8 G9 F7 J6, J7 U13 U14 T12 N7 H16 H15 Package Pin Assignment(s) NVCC_CKIH NVCC_CSI NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_EMI_DRAM NVCC_FEC NVCC_GPIO NVCC_JTAG NVCC_KEYPAD NVCC_LCD NVCC_LVDS NVCC_LVDS_BG NVCC_NANDF NVCC_PATA NVCC_RESET NVCC_SD1 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 157 Package Information and Contact Assignments Table 111. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued) Package Pin Name NVCC_SD2 NVCC_SRTC_POW NVCC_XTAL SVCC SVDDGP TVDAC_AHVDDRGB TVDAC_DHVDD USB_H1_VDDA25 USB_H1_VDDA33 USB_OTG_VDDA25 USB_OTG_VDDA33 VCC VDDA VDDAL1 VDD_ANA_PLL VDD_DIG_PLL VDD_FUSE VDDGP VDD_REG VP VPH H14 V11 V12 B22 B2 U17, V16 U16 F13 G13 F14 G14 H13, J14, J16, K13, K15, L14, L16, M11, M13, M15, M9, N10, N12, N14, N16, N8, P11, P13, P15, P9, R10, R12, R14, R16, R8, T11, T13, T15, T17, T7, T9, U18, U8 G12, M17, M7, U12 F9 G16 H17 G15 G10, G11, G8, H11, H7, H9, J10, J12, J8, K11, K7, K9, L10, L12, L8 G18 A15, B15 A9, B9 Package Pin Assignment(s) Table 112 displays an alpha-sorted list of the signal assignments including power rails. The table also includes out of reset pad state. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 158 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value BOOT_MODE C18 0 BOOT_MODE B20 1 CKIH1 CKIH2 CKIL CSI0_DAT10 CSI0_DAT11 CSI0_DAT12 CSI0_DAT13 CSI0_DAT14 CSI0_DAT15 CSI0_DAT16 CSI0_DAT17 CSI0_DAT18 CSI0_DAT19 CSI0_DAT4 CSI0_DAT5 CSI0_DAT6 CSI0_DAT7 CSI0_DAT8 CSI0_DAT9 B21 D18 AB10 R5 T2 T3 T6 U1 U2 T4 T5 U3 U4 R1 R2 R6 R3 T1 R4 NVCC_RESET NVCC_RESET NVCC_CKIH NVCC_CKIH NVCC_SRTC_POW NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI LVIO LVIO ANALOG ANALOG ANALOG UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO ALT0 ALT0 ALT0 ALT0 — ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 SRC SRC CAMP1 CAMP2 SRCT src_BOOT_MOD E[0] src_BOOT_MOD E[1] camp1_CKIH camp2_CKIH CKIL Input Input Input Input — Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input 100 KΩ PD 100 KΩ PD Analog Analog — 100 KΩ PU 100 KΩ PU 360 KΩ PD 360 KΩ PD 360 KΩ PD 360 KΩ PD 360 KΩ PD 360 KΩ PD 360 KΩ PD 360 KΩ PD 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU GPIO-5 gpio5_GPIO[28] GPIO-5 gpio5_GPIO[29] GPIO-5 gpio5_GPIO[30] GPIO-5 gpio5_GPIO[31] GPIO-6 gpio6_GPIO[0] GPIO-6 gpio6_GPIO[1] GPIO-6 gpio6_GPIO[2] GPIO-6 gpio6_GPIO[3] GPIO-6 gpio6_GPIO[4] GPIO-6 gpio6_GPIO[5] GPIO-5 gpio5_GPIO[22] GPIO-5 gpio5_GPIO[23] GPIO-5 gpio5_GPIO[24] GPIO-5 gpio5_GPIO[25] GPIO-5 gpio5_GPIO[26] GPIO-5 gpio5_GPIO[27] GPIO-5 gpio5_GPIO[20] GPIO-5 gpio5_GPIO[19] GPIO-5 gpio5_GPIO[18] GPIO-5 gpio5_GPIO[21] CSI0_DATA_E P3 N CSI0_MCLK CSI0_PIXCLK CSI0_VSYNC P2 P1 P4 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 159 Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value DI0_DISP_CL K DI0_PIN15 DI0_PIN2 DI0_PIN3 DI0_PIN4 DISP0_DAT0 DISP0_DAT1 H4 E4 D3 C2 D2 J5 J4 NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 GPIO-4 gpio4_GPIO[16] GPIO-4 gpio4_GPIO[17] GPIO-4 gpio4_GPIO[18] GPIO-4 gpio4_GPIO[19] GPIO-4 gpio4_GPIO[20] GPIO-4 gpio4_GPIO[21] GPIO-4 gpio4_GPIO[22] GPIO-4 gpio4_GPIO[31] GPIO-5 gpio5_GPIO[5] GPIO-5 gpio5_GPIO[6] GPIO-5 gpio5_GPIO[7] GPIO-5 gpio5_GPIO[8] GPIO-5 gpio5_GPIO[9] GPIO-5 gpio5_GPIO[10] GPIO-5 gpio5_GPIO[11] GPIO-5 gpio5_GPIO[12] GPIO-5 gpio5_GPIO[13] GPIO-4 gpio4_GPIO[23] GPIO-5 gpio5_GPIO[14] GPIO-5 gpio5_GPIO[15] GPIO-5 gpio5_GPIO[16] GPIO-5 gpio5_GPIO[17] GPIO-4 gpio4_GPIO[24] GPIO-4 gpio4_GPIO[25] GPIO-4 gpio4_GPIO[26] GPIO-4 gpio4_GPIO[27] GPIO-4 gpio4_GPIO[28] GPIO-4 gpio4_GPIO[29] Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PD 100 KΩ PD 100 KΩ PU 100 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PD 100 KΩ PD 100 KΩ PD 100 KΩ PD 100 KΩ PD 100 KΩ PU DISP0_DAT10 G3 DISP0_DAT11 H5 DISP0_DAT12 H1 DISP0_DAT13 E1 DISP0_DAT14 F2 DISP0_DAT15 F3 DISP0_DAT16 D1 DISP0_DAT17 F5 DISP0_DAT18 G4 DISP0_DAT19 G5 DISP0_DAT2 H2 DISP0_DAT20 F4 DISP0_DAT21 C1 DISP0_DAT22 E3 DISP0_DAT23 C3 DISP0_DAT3 DISP0_DAT4 DISP0_DAT5 DISP0_DAT6 DISP0_DAT7 DISP0_DAT8 F1 G2 H3 G1 H6 G6 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 160 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value DISP0_DAT9 DRAM_A0 DRAM_A1 DRAM_A10 DRAM_A11 DRAM_A12 DRAM_A13 DRAM_A14 DRAM_A15 DRAM_A2 DRAM_A3 DRAM_A4 DRAM_A5 DRAM_A6 DRAM_A7 DRAM_A8 DRAM_A9 E2 M19 L21 K19 L22 L20 L23 N18 M18 M20 N20 K20 N21 M22 N22 N23 M21 NVCC_LCD NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM GPIO DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 special ALT1 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 — GPIO-4 gpio4_GPIO[30] EXTMC emi_DRAM_A[0] EXTMC emi_DRAM_A[1] EXTMC emi_DRAM_A[10 ] EXTMC emi_DRAM_A[11 ] EXTMC emi_DRAM_A[12 ] EXTMC emi_DRAM_A[13 ] EXTMC emi_DRAM_A[14 ] EXTMC emi_DRAM_A[15 ] EXTMC emi_DRAM_A[2] EXTMC emi_DRAM_A[3] EXTMC emi_DRAM_A[4] EXTMC emi_DRAM_A[5] EXTMC emi_DRAM_A[6] EXTMC emi_DRAM_A[7] EXTMC emi_DRAM_A[8] EXTMC emi_DRAM_A[9] — (used in DRAM driver calibration. See Special Signal Considerations {add xref} above) Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input 100 KΩ PU Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low — DRAM_CALIB M23 RATION DRAM_CAS DRAM_CS0 DRAM_CS1 L18 K18 P19 NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM DDR3 DDR3 DDR3 ALT0 ALT0 ALT0 EXTMC emi_DRAM_CAS EXTMC emi_DRAM_CS[ 0] EXTMC emi_DRAM_CS[ 1] Output Output Output High High High i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 161 Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value DRAM_D0 DRAM_D1 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D13 DRAM_D14 DRAM_D15 DRAM_D16 DRAM_D17 DRAM_D18 DRAM_D19 DRAM_D2 DRAM_D20 DRAM_D21 DRAM_D22 DRAM_D23 DRAM_D24 DRAM_D25 H20 G21 E22 D20 E23 C23 F23 C22 U20 T21 U21 R21 J21 U23 R22 U22 R23 Y20 W21 NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 EXTMC emi_DRAM_D[0] EXTMC emi_DRAM_D[1] EXTMC emi_DRAM_D[10 ] EXTMC emi_DRAM_D[11 ] EXTMC emi_DRAM_D[12 ] EXTMC emi_DRAM_D[13 ] EXTMC emi_DRAM_D[14 ] EXTMC emi_DRAM_D[15 ] EXTMC emi_DRAM_D[16 ] EXTMC emi_DRAM_D[17 ] EXTMC emi_DRAM_D[18 ] EXTMC emi_DRAM_D[19 ] EXTMC emi_DRAM_D[2] EXTMC emi_DRAM_D[20 ] EXTMC emi_DRAM_D[21 ] EXTMC emi_DRAM_D[22 ] EXTMC emi_DRAM_D[23 ] EXTMC emi_DRAM_D[24 ] EXTMC emi_DRAM_D[25 ] Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output High High High High High High High High High High High High High High High High High High High i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 162 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value DRAM_D26 DRAM_D27 DRAM_D28 DRAM_D29 DRAM_D3 DRAM_D30 DRAM_D31 DRAM_D4 DRAM_D5 DRAM_D6 DRAM_D7 DRAM_D8 DRAM_D9 Y21 W22 AA23 V23 G20 AA22 W23 J23 G23 J22 G22 E21 D21 NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 EXTMC emi_DRAM_D[26 ] EXTMC emi_DRAM_D[27 ] EXTMC emi_DRAM_D[28 ] EXTMC emi_DRAM_D[29 ] EXTMC emi_DRAM_D[3] EXTMC emi_DRAM_D[30 ] EXTMC emi_DRAM_D[31 ] EXTMC emi_DRAM_D[4] EXTMC emi_DRAM_D[5] EXTMC emi_DRAM_D[6] EXTMC emi_DRAM_D[7] EXTMC emi_DRAM_D[8] EXTMC emi_DRAM_D[9] EXTMC emi_DRAM_DQ M[0] EXTMC emi_DRAM_DQ M[1] EXTMC emi_DRAM_DQ M[2] EXTMC emi_DRAM_DQ M[3] EXTMC emi_DRAM_RAS EXTMC emi_DRAM_RES ET EXTMC emi_DRAM_SDB A[0] EXTMC emi_DRAM_SDB A[1] Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output High High High High High High High High High High High High High Low Low Low Low High Low Low Low DRAM_DQM0 H21 DRAM_DQM1 E20 DRAM_DQM2 T20 DRAM_DQM3 W20 DRAM_RAS DRAM_RESE T DRAM_SDBA 0 DRAM_SDBA 1 J19 P18 R19 P20 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 163 Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value DRAM_SDBA 2 DRAM_SDCK E0 DRAM_SDCK E1 DRAM_SDCL K_0 DRAM_SDCL K_0_B DRAM_SDCL K_1 DRAM_SDCL K_1_B N19 H19 T19 K23 K22 P22 P23 NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM DDR3 DDR3 DDR3 DDR3CLK DDR3CLK DDR3CLK DDR3CLK DDR3 DDR3 DDR3CLK DDR3CLK DDR3CLK DDR3CLK DDR3CLK DDR3CLK DDR3CLK DDR3CLK DDR3 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 EXTMC emi_DRAM_SDB A[2] EXTMC emi_DRAM_SDC KE[0] EXTMC emi_DRAM_SDC KE[1] EXTMC emi_DRAM_SDC LK0 EXTMC emi_DRAM_SDC LK0_B EXTMC emi_DRAM_SDC LK1 EXTMC emi_DRAM_SDC LK1_B EXTMC emi_DRAM_ODT [0] EXTMC emi_DRAM_ODT [1] EXTMC emi_DRAM_SDQ S[0] EXTMC emi_DRAM_SDQ S_B[0] EXTMC emi_DRAM_SDQ S[1] EXTMC emi_DRAM_SDQ S_B[1] EXTMC emi_DRAM_SDQ S[2] EXTMC emi_DRAM_SDQ S_B[2] EXTMC emi_DRAM_SDQ S[3] EXTMC emi_DRAM_SDQ S_B[3] EXTMC emi_DRAM_SD WE Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Output Low Low Low Floating Floating Floating Floating Low Low Low High Low High Low High Low High High DRAM_SDOD J18 T0 DRAM_SDOD R18 T1 DRAM_SDQS 0 DRAM_SDQS 0_B DRAM_SDQS 1 DRAM_SDQS 1_B DRAM_SDQS 2 DRAM_SDQS 2_B DRAM_SDQS 3 DRAM_SDQS 3_B H23 H22 D23 D22 T22 T23 Y22 Y23 DRAM_SDWE L19 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 164 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value ECKIL AC10 NVCC_SRTC_POW ANALOG — SRTC ECKIL {no block I/O by this name in RM} — — EIM_A16 EIM_A17 EIM_A18 EIM_A19 EIM_A20 EIM_A21 EIM_A22 EIM_A23 EIM_A24 EIM_A25 EIM_BCLK EIM_CS0 EIM_CS1 EIM_D16 EIM_D17 EIM_D18 EIM_D19 EIM_D20 EIM_D21 EIM_D22 EIM_D23 EIM_D24 EIM_D25 EIM_D26 EIM_D27 EIM_D28 EIM_D29 AA5 V7 AB3 W7 Y6 AA4 AA3 V6 Y5 W6 W11 W8 Y7 U6 U5 V1 V2 W1 V3 W2 Y1 Y2 W3 V5 V4 AA1 AA2 NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_SEC UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 EXTMC emi_EIM_A[16] EXTMC emi_EIM_A[17] EXTMC emi_EIM_A[18] EXTMC emi_EIM_A[19] EXTMC emi_EIM_A[20] EXTMC emi_EIM_A[21] EXTMC emi_EIM_A[22] EXTMC emi_EIM_A[23] EXTMC emi_EIM_A[24] EXTMC emi_EIM_A[25] EXTMC emi_EIM_BCLK EXTMC emi_EIM_CS[0] EXTMC emi_EIM_CS[1] GPIO-3 gpio3_GPIO[16] GPIO-3 gpio3_GPIO[17] GPIO-3 gpio3_GPIO[18] GPIO-3 gpio3_GPIO[19] GPIO-3 gpio3_GPIO[20] GPIO-3 gpio3_GPIO[21] GPIO-3 gpio3_GPIO[22] GPIO-3 gpio3_GPIO[23] GPIO-3 gpio3_GPIO[24] GPIO-3 gpio3_GPIO[25] GPIO-3 gpio3_GPIO[26] GPIO-3 gpio3_GPIO[27] GPIO-3 gpio3_GPIO[28] GPIO-3 gpio3_GPIO[29] Output2 Output2 Output2 Output2 Output2 Output2 Output2 Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input — — — — — — — — — — — — — 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 165 Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value EIM_D30 EIM_D31 EIM_DA0 EIM_DA1 EIM_DA10 EIM_DA11 EIM_DA12 EIM_DA13 EIM_DA14 EIM_DA15 EIM_DA2 EIM_DA3 EIM_DA4 EIM_DA5 EIM_DA6 EIM_DA7 EIM_DA8 EIM_DA9 EIM_EB0 W4 W5 Y8 AC4 AB7 AC6 V10 AC7 Y10 AA9 AA7 W9 AB6 V9 Y9 AC5 AA8 W10 AC3 NVCC_EIM_SEC NVCC_EIM_SEC NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO ALT1 ALT1 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 GPIO-3 gpio3_GPIO[30] GPIO-3 gpio3_GPIO[31] EXTMC emi_NAND_EIM _DA[0] EXTMC emi_NAND_EIM _DA[1] EXTMC emi_NAND_EIM _DA[10] EXTMC emi_NAND_EIM _DA[11] EXTMC emi_NAND_EIM _DA[12] EXTMC emi_NAND_EIM _DA[13] EXTMC emi_NAND_EIM _DA[14] EXTMC emi_NAND_EIM _DA[15] EXTMC emi_NAND_EIM _DA[2] EXTMC emi_NAND_EIM _DA[3] EXTMC emi_NAND_EIM _DA[4] EXTMC emi_NAND_EIM _DA[5] EXTMC emi_NAND_EIM _DA[6] EXTMC emi_NAND_EIM _DA[7] EXTMC emi_NAND_EIM _DA[8] EXTMC emi_NAND_EIM _DA[9] EXTMC emi_EIM_EB[0] Input Input Input2 Input2 Input2 Input Input Input Input Input Input2 Input2 Input2 Input2 Input2 Input2 Input2 Input2 Output2 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU — i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 166 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value EIM_EB1 EIM_EB2 EIM_EB3 EIM_LBA EIM_OE EIM_RW EIM_WAIT EXTAL FASTR_ANA FASTR_DIG AB5 Y3 Y4 AA6 V8 AB4 AB9 AB11 E18 E17 NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_XTAL NVCC_CKIH NVCC_CKIH NVCC_FEC NVCC_FEC NVCC_FEC NVCC_FEC NVCC_FEC NVCC_FEC NVCC_FEC NVCC_FEC NVCC_FEC NVCC_FEC NVCC_GPIO NVCC_GPIO TVDAC_AHVDDRG B TVDAC_AHVDDRG B TVDAC_AHVDDRG B UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO ANALOG ANALOG ANALOG UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO GPIO GPIO GPIO ALT0 ALT1 ALT1 ALT0 ALT0 ALT0 ALT0 — — — ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT0 ALT0 ALT0 EXTMC emi_EIM_EB[1] GPIO-2 gpio2_GPIO[30] GPIO-2 gpio2_GPIO[31] EXTMC emi_EIM_LBA EXTMC emi_EIM_OE EXTMC emi_EIM_RW EXTMC emi_EIM_WAIT EXTAL OSC — — EXTAL (reserved, tie to ground) (reserved, tie to ground) Output2 Input Input Output 2 — 100 KΩ PU 100 KΩ PU — — — — — — — 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 360 KΩ PD 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU Output Output Output — — — Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input FEC_CRS_DV D11 FEC_MDC FEC_MDIO E10 D12 GPIO-1 gpio1_GPIO[25] GPIO-1 gpio1_GPIO[31] GPIO-1 gpio1_GPIO[22] GPIO-1 gpio1_GPIO[23] GPIO-1 gpio1_GPIO[24] GPIO-1 gpio1_GPIO[27] GPIO-1 gpio1_GPIO[26] GPIO-1 gpio1_GPIO[28] GPIO-1 gpio1_GPIO[30] GPIO-1 gpio1_GPIO[29] GPIO-1 gpio1_GPIO[0] GPIO-1 gpio1_GPIO[1] GPIO-4 gpio4_GPIO[0] GPIO-4 gpio4_GPIO[1] GPIO-4 gpio4_GPIO[2] FEC_REF_CL E12 K FEC_RX_ER FEC_RXD0 FEC_RXD1 FEC_TX_EN FEC_TXD0 FEC_TXD1 GPIO_0 GPIO_1 GPIO_10 GPIO_11 GPIO_12 F12 C11 E11 C10 F10 D10 C8 B7 W16 V17 W17 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 167 Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value GPIO_13 GPIO_14 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 JTAG_MOD JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRSTB KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3 KEY_COL4 KEY_ROW0 KEY_ROW1 KEY_ROW2 AA18 W18 C6 A3 D7 B4 C7 A6 D8 A5 B6 A4 B5 E8 C9 D9 B8 A7 A8 E9 C5 E7 C4 F6 E5 B3 D6 D5 TVDAC_AHVDDRG B TVDAC_AHVDDRG B NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_KEYPAD NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_KEYPAD NVCC_KEYPAD NVCC_KEYPAD NVCC_KEYPAD NVCC_KEYPAD NVCC_KEYPAD NVCC_KEYPAD NVCC_KEYPAD GPIO GPIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO GPIO GPIO GPIO GPIO GPIO GPIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO ALT0 ALT0 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 GPIO-4 gpio4_GPIO[3] GPIO-4 gpio4_GPIO[4] GPIO-7 gpio7_GPIO[11] GPIO-7 gpio7_GPIO[12] GPIO-7 gpio7_GPIO[13] GPIO-4 gpio4_GPIO[5] GPIO-1 gpio1_GPIO[2] GPIO-1 gpio1_GPIO[3] GPIO-1 gpio1_GPIO[4] GPIO-1 gpio1_GPIO[5] GPIO-1 gpio1_GPIO[6] GPIO-1 gpio1_GPIO[7] GPIO-1 gpio1_GPIO[8] GPIO-1 gpio1_GPIO[9] SJC SJC SJC SJC SJC SJC sjc_MOD sjc_TCK sjc_TDI sjc_TDO sjc_TMS sjc_TRSTB Input Input Input Input Input Input3 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input4 Input Input Input Input Input Input Input 100 KΩ PU 100 KΩ PU 360 KΩ PD 360 KΩ PD 360 KΩ PD 100 KΩ PU 360 KΩ PD 360 KΩ PD 100 KΩ PU 360 KΩ PD 360 KΩ PD 360 KΩ PD 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PD 47 KΩ PU Keeper 47 KΩ PU 47 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU GPIO-4 gpio4_GPIO[6] GPIO-4 gpio4_GPIO[8] GPIO-4 gpio4_GPIO[10] GPIO-4 gpio4_GPIO[12] GPIO-4 gpio4_GPIO[14] GPIO-4 gpio4_GPIO[7] GPIO-4 gpio4_GPIO[9] GPIO-4 gpio4_GPIO[11] i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 168 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value KEY_ROW3 KEY_ROW4 D4 E6 NVCC_KEYPAD NVCC_KEYPAD NVCC_LVDS_BG NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS NVCC_LVDS UHVIO UHVIO ANALOG LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS ALT1 ALT1 — ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 ALT0 GPIO-4 gpio4_GPIO[13] GPIO-4 gpio4_GPIO[15] LDB LVDS_BG_RES Input Input — Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input 100 KΩ PU 360 KΩ PD — Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating LVDS_BG_RE AA14 S LVDS0_CLK_ N LVDS0_CLK_ P LVDS0_TX0_ N AB16 AC16 Y17 GPIO-7 gpio7_GPI[25] GPIO-7 gpio7_GPI[24] GPIO-7 gpio7_GPI[31] GPIO-7 gpio7_GPI[30] GPIO-7 gpio7_GPI[29] GPIO-7 gpio7_GPI[28] GPIO-7 gpio7_GPI[27] GPIO-7 gpio7_GPI[26] GPIO-7 gpio7_GPI[23] GPIO-7 gpio7_GPI[22] GPIO-6 gpio6_GPI[27] GPIO-6 gpio6_GPI[26] GPIO-6 gpio6_GPI[31] GPIO-6 gpio6_GPI[30] GPIO-6 gpio6_GPI[29] GPIO-6 gpio6_GPI[28] GPIO-6 gpio6_GPI[25] GPIO-6 gpio6_GPI[24] LVDS0_TX0_P AA17 LVDS0_TX1_ N AB17 LVDS0_TX1_P AC17 LVDS0_TX2_ N Y16 LVDS0_TX2_P AA16 LVDS0_TX3_ N AB15 LVDS0_TX3_P AC15 LVDS1_CLK_ N LVDS1_CLK_ P LVDS1_TX0_ N AA13 Y13 AC14 LVDS1_TX0_P AB14 LVDS1_TX1_ N AC13 LVDS1_TX1_P AB13 LVDS1_TX2_ N AC12 LVDS1_TX2_P AB12 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 169 Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value LVDS1_TX3_ N AA12 NVCC_LVDS NVCC_LVDS NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_EIM_MAIN NVCC_EIM_MAIN NVCC_NANDF NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA LVDS LVDS UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO ALT0 ALT0 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 GPIO-6 gpio6_GPI[23] GPIO-6 gpio6_GPI[22] GPIO-6 gpio6_GPIO[8] GPIO-6 gpio6_GPIO[7] GPIO-6 gpio6_GPIO[11] GPIO-6 gpio6_GPIO[14] GPIO-6 gpio6_GPIO[15] GPIO-6 gpio6_GPIO[16] GPIO-6 gpio6_GPIO[10] GPIO-6 gpio6_GPIO[13] GPIO-6 gpio6_GPIO[12] GPIO-6 gpio6_GPIO[9] GPIO-7 gpio7_GPIO[1] GPIO-7 gpio7_GPIO[9] GPIO-7 gpio7_GPIO[10] GPIO-7 gpio7_GPIO[6] GPIO-7 gpio7_GPIO[7] GPIO-7 gpio7_GPIO[8] GPIO-2 gpio2_GPIO[0] GPIO-2 gpio2_GPIO[1] GPIO-2 gpio2_GPIO[10] GPIO-2 gpio2_GPIO[11] GPIO-2 gpio2_GPIO[12] GPIO-2 gpio2_GPIO[13] GPIO-2 gpio2_GPIO[14] GPIO-2 gpio2_GPIO[15] Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Floating Floating 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU LVDS1_TX3_P Y12 NANDF_ALE NANDF_CLE NANDF_CS0 NANDF_CS1 NANDF_CS2 NANDF_CS3 NANDF_RB0 Y11 AA10 W12 V13 V14 W13 U11 NANDF_RE_B AC8 NANDF_WE_ B NANDF_WP_ B PATA_BUFFE R_EN PATA_CS_0 PATA_CS_1 PATA_DA_0 PATA_DA_1 PATA_DA_2 PATA_DATA0 PATA_DATA1 PATA_DATA10 PATA_DATA11 PATA_DATA12 PATA_DATA13 PATA_DATA14 PATA_DATA15 AB8 AC9 K4 L5 L2 K6 L3 L4 L1 M1 N4 M6 N5 N6 P6 P5 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 170 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value PATA_DATA2 PATA_DATA3 PATA_DATA4 PATA_DATA5 PATA_DATA6 PATA_DATA7 PATA_DATA8 PATA_DATA9 PATA_DIOR PATA_DIOW L6 M2 M3 M4 N1 M5 N2 N3 K3 J3 NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_PATA NVCC_SRTC_POW NVCC_SRTC_POW NVCC_RESET NVCC_RESET VPH VPH VPH VPH VPH VPH VPH UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO GPIO GPIO LVIO LVIO ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT0 ALT0 ALT0 ALT0 — — — — — — — GPIO-2 gpio2_GPIO[2] GPIO-2 gpio2_GPIO[3] GPIO-2 gpio2_GPIO[4] GPIO-2 gpio2_GPIO[5] GPIO-2 gpio2_GPIO[6] GPIO-2 gpio2_GPIO[7] GPIO-2 gpio2_GPIO[8] GPIO-2 gpio2_GPIO[9] GPIO-7 gpio7_GPIO[3] GPIO-6 gpio6_GPIO[17] GPIO-6 gpio6_GPIO[18] GPIO-7 gpio7_GPIO[0] GPIO-7 gpio7_GPIO[2] GPIO-7 gpio7_GPIO[5] GPIO-7 gpio7_GPIO[4] SRTC CCM SRC SRC SATA SATA SATA SATA SATA SATA SATA srtc_SRTCALAR M ccm_PMIC_VST BY_REQ src_POR_B src_RESET_B SATA_REFCLKM SATA_REFCLKP SATA_REXT SATA_RXM SATA_RXP SATA_TXM SATA_TXP Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Input Input — — — — — — — 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU — — 100 KΩ PU 100 KΩ PU — — — — — — — PATA_DMACK J2 PATA_DMARQ J1 PATA_INTRQ PATA_IORDY PATA_RESET _B K5 K1 K2 PMIC_ON_RE W14 Q PMIC_STBY_ REQ POR_B RESET_IN_B SATA_REFCL KM SATA_REFCL KP SATA_REXT SATA_RXM SATA_RXP SATA_TXM SATA_TXP W15 C19 A21 A14 B14 C13 A12 B12 B10 A10 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 171 Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD2_CLK SD2_CMD SD2_DATA0 SD2_DATA1 SD2_DATA2 SD2_DATA3 TEST_MODE TVCDC_IOB_ BACK E16 F18 A20 C17 F17 F16 E14 C15 D13 C14 D14 E13 D17 AB19 NVCC_SD1 NVCC_SD1 NVCC_SD1 NVCC_SD1 NVCC_SD1 NVCC_SD1 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_RESET TVDAC_AHVDDRG B TVDAC_AHVDDRG B TVDAC_AHVDDRG B TVDAC_AHVDDRG B TVDAC_AHVDDRG B TVDAC_AHVDDRG B TVDAC_AHVDDRG B TVDAC_AHVDDRG B USB_H1_VDDA25, USB_H1_VDDA33 UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO LVIO ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT1 ALT0 — — — — — — — — GPIO-1 gpio1_GPIO[20] GPIO-1 gpio1_GPIO[18] GPIO-1 gpio1_GPIO[16] GPIO-1 gpio1_GPIO[17] GPIO-1 gpio1_GPIO[19] GPIO-1 gpio1_GPIO[21] GPIO-1 gpio1_GPIO[10] GPIO-1 gpio1_GPIO[11] GPIO-1 gpio1_GPIO[15] GPIO-1 gpio1_GPIO[14] GPIO-1 gpio1_GPIO[13] GPIO-1 gpio1_GPIO[12] tcu_TEST_MOD E TVE TVE TVE TVE TVE TVE TVE TVE USB TVCDC_IOB_BA CK TVCDC_IOG_BA CK TVCDC_IOR_BA CK TVDAC_COMP TVDAC_IOB TVDAC_IOG TVDAC_IOR TVDAC_VREF USB_H1_DN Input Input Input Input Input Input Input Input Input Input Input Input Input — — — — — — — — — 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PD — — — — — — — — — TVCDC_IOG_ AC20 BACK TVCDC_IOR_ BACK TVDAC_COM P TVDAC_IOB TVDAC_IOG TVDAC_IOR AB21 AA19 AC19 AB20 AC21 TVDAC_VREF Y18 USB_H1_DN B17 ANALOG50 — i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 172 Freescale Semiconductor Package Information and Contact Assignments Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued) Out of Reset Condition1 Package Pin Name I/O Buffer Type Block Instance Package Pin Assign ment Power Rail Alt. Mode Block I/O Directio n Config./ Value USB_H1_DP A17 USB_H1_VDDA25, USB_H1_VDDA33 USB_H1_VDDA25, USB_H1_VDDA33 USB_H1_VDDA25, USB_H1_VDDA33 USB_H1_VDDA25, USB_H1_VDDA33 ANALOG50 — ANALOG25 — ANALOG25 — ANALOG50 — USB USB USB USB USB USB USB USB USB USB XTALO SC USB_H1_DP USB_H1_GPANA IO USB_H1_RREFE XT USB_H1_VBUS USB_OTG_DN USB_OTG_DP USB_OTG_GPA NAIO USB_OTG_ID USB_OTG_RRE FEXT USB_OTG_VBU S XTAL — — — — — — — — — — — — — — — — — — — — — — USB_H1_GPA A16 NAIO USB_H1_RRE B16 FEXT USB_H1_VBU D15 S USB_OTG_D N A19 USB_OTG_VDDA25, ANALOG50 — USB_OTG_VDDA33 USB_OTG_VDDA25, ANALOG50 — USB_OTG_VDDA33 USB_OTG_VDDA25, ANALOG25 — USB_OTG_VDDA33 USB_OTG_VDDA25, ANALOG25 — USB_OTG_VDDA33 USB_OTG_VDDA25, ANALOG25 — USB_OTG_VDDA33 USB_OTG_VDDA25, ANALOG50 — USB_OTG_VDDA33 NVCC_XTAL ANALOG — USB_OTG_DP B19 USB_OTG_G PANAIO USB_OTG_ID USB_OTG_R REFEXT F15 C16 D16 USB_OTG_VB E15 US XTAL 1 2 AC11 The state immediately after reset and before ROM firmware or software has executed. During power-on reset this port acts as input for fuse override, ~33KΩ PU/PD recommended to set the value. See Section 5.1, “Boot Mode Configuration Pins” for details. 3 During power-on reset this port acts as output for diagnostic signal INT_BOOT 4 During power-on reset this port acts as output for diagnostic signal ANY_PU_RST NOTE KEY_COL0 and GPIO_19 act as output for diagnostic signals during power-on reset. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 173 174 6.2 E DISP0_DAT13 1 2 3 4 5 6 7 8 VPH SATA_TXP GND SATA_RXM GND SATA_REFCLKP VP USB_H1_RREFEXT USB_H1_DN SD1_DATA1 BOOT_MODE0 POR_B GND GND DRAM_D15 DRAM_SDQS1_B DRAM_SDQS1 D DRAM_D13 C GND USB_OTG_DP BOOT_MODE1 CKIH1 SVCC GND B GND SATA_REFCLKM VP USB_H1_GPANAIO USB_H1_DP GND USB_OTG_DN SD1_DATA0 RESET_IN_B GND GND A 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DISP0_DAT9 DISP0_DAT22 DI0_PIN15 KEY_COL4 KEY_ROW4 KEY_COL1 GPIO_9 JTAG_TRSTB FEC_MDC FEC_RXD1 FEC_REF_CLK FEC_MDIO SD2_DATA0 SD2_DATA2 USB_H1_VBUS USB_OTG_RREFEXT TEST_MODE CKIH2 GND DRAM_D11 DRAM_D9 SD2_CMD USB_OTG_ID SD2_DATA1 SATA_REXT GND SD2_DATA3 SD2_CLK USB_OTG_VBUS SD1_CLK FASTR_DIG FASTR_ANA GND DRAM_DQM1 DRAM_D8 DRAM_D10 DRAM_D12 E FEC_CRS_DV FEC_RXD0 GND SATA_RXP FEC_TXD1 FEC_TX_EN SATA_TXM JTAG_TCK JTAG_MOD VPH GPIO_4 GPIO_0 JTAG_TDI GPIO_18 GPIO_2 GPIO_1 JTAG_TDO JTAG_TMS KEY_ROW1 GPIO_16 GPIO_6 GPIO_3 KEY_ROW2 KEY_COL0 GPIO_8 GPIO_5 KEY_ROW3 KEY_COL2 GPIO_19 GPIO_7 DI0_PIN2 DISP0_DAT23 KEY_ROW0 GPIO_17 DI0_PIN4 DI0_PIN3 SVDDGP GND DISP0_DAT16 DISP0_DAT21 GND GND D C B A 1 2 3 4 5 6 7 8 Package Information and Contact Assignments 9 10 Table 113 shows the 19 × 19 mm, 0.8 pitch ball map. 11 19 x 19 mm, 0.8 Pitch Ball Map 12 13 14 15 Table 113. 19 × 19 mm, 0.8 Pitch Ball Map 16 17 18 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 19 20 21 22 Freescale Semiconductor 23 L K PATA_IORDY 1 2 3 4 5 6 NVCC_KEYPAD NVCC_GPIO VDDAL1 FEC_TXD0 VDDGP VDDGP VDDA USB_H1_VDDA33 USB_OTG_VDDA33 VDD_FUSE NVCC_SD1 NVCC_RESET VDD_DIG_PLL NVCC_EMI_DRAM DRAM_SDCKE0 GND DRAM_D2 DRAM_D6 DRAM_D4 K J DRAM_D0 DRAM_DQM0 DRAM_SDQS0_B DRAM_SDQS0 H VDD_ANA_PLL NVCC_CKIH VDD_REG GND DRAM_D3 DRAM_D1 DRAM_D7 DRAM_D5 G NVCC_FEC FEC_RX_ER USB_H1_VDDA25 USB_OTG_VDDA25 USB_OTG_GPANAIO SD1_DATA3 SD1_DATA2 SD1_CMD GND GND GND GND DRAM_D14 F 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PATA_RESET_B PATA_DIOR PATA_BUFFER_EN PATA_INTRQ PATA_DA_0 VDDGP GND VDDGP GND VDDGP GND VCC GND VCC GND NVCC_EMI_DRAM DRAM_CS0 DRAM_A10 DRAM_A4 GND DRAM_SDCLK_0_B DRAM_SDCLK_0 GND DRAM_SDODT0 DRAM_RAS VCC GND VCC NVCC_SD2 GND VCC VDDGP GND GND VDDGP VDDGP GND GND VDDGP NVCC_JTAG VDDGP GND VDDGP NVCC_LCD VDDGP GND NVCC_LCD DISP0_DAT7 DISP0_DAT8 DISP0_DAT0 DISP0_DAT11 DISP0_DAT19 DISP0_DAT1 DI0_DISP_CLK DISP0_DAT18 DISP0_DAT20 DISP0_DAT17 KEY_COL3 PATA_DIOW DISP0_DAT5 DISP0_DAT10 DISP0_DAT15 PATA_DMACK DISP0_DAT2 DISP0_DAT4 DISP0_DAT14 PATA_DMARQ DISP0_DAT12 DISP0_DAT6 DISP0_DAT3 J H G F 1 PATA_DATA0 2 PATA_CS_1 3 PATA_DA_1 Freescale Semiconductor GND GND GND GND VCC GND VCC 4 PATA_DA_2 5 PATA_CS_0 6 PATA_DATA2 7 8 VDDGP 9 10 VDDGP 11 12 VDDGP 13 14 15 16 17 DDR_VREF Table 113. 19 × 19 mm, 0.8 Pitch Ball Map (continued) 18 DRAM_CAS i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 L 19 DRAM_SDWE 20 DRAM_A12 21 DRAM_A1 22 DRAM_A11 23 DRAM_A13 Package Information and Contact Assignments 175 176 T CSI0_DAT8 1 2 3 4 5 6 VDDA GND VCC GND VCC GND VCC GND VCC GND VCC GND NVCC_EMI_DRAM DRAM_RESET DRAM_CS1 GND DRAM_D19 DRAM_D21 DRAM_D23 T R DRAM_SDBA1 GND DRAM_SDCLK_1 DRAM_SDCLK_1_B P VCC NVCC_EMI_DRAM DRAM_A14 DRAM_SDBA2 DRAM_A3 DRAM_A5 DRAM_A7 DRAM_A8 N VCC GND VCC GND VCC GND VDDA DRAM_A15 DRAM_A0 DRAM_A2 DRAM_A9 DRAM_A6 DRAM_CALIBRATION M 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CSI0_DAT11 CSI0_DAT12 CSI0_DAT16 CSI0_DAT17 CSI0_DAT13 VCC GND VCC GND VCC NVCC_NANDF VCC GND VCC GND VCC NVCC_EMI_DRAM DRAM_SDCKE1 DRAM_DQM2 DRAM_D17 DRAM_SDQS2 DRAM_SDQS2_B GND DRAM_SDODT1 DRAM_SDBA0 VCC GND VCC GND GND VCC VCC GND GND VCC VCC GND GND VCC GND VCC GND VCC NVCC_CSI GND NVCC_PATA CSI0_DAT6 PATA_DATA14 PATA_DATA13 CSI0_DAT10 PATA_DATA15 PATA_DATA12 CSI0_DAT9 CSI0_VSYNC PATA_DATA10 PATA_DATA5 PATA_DATA7 PATA_DATA11 CSI0_DAT7 CSI0_DATA_EN PATA_DATA9 PATA_DATA4 CSI0_DAT5 CSI0_MCLK PATA_DATA8 PATA_DATA3 CSI0_DAT4 CSI0_PIXCLK PATA_DATA6 PATA_DATA1 R P N M U 1 CSI0_DAT14 2 CSI0_DAT15 3 CSI0_DAT18 4 CSI0_DAT19 5 EIM_D17 6 EIM_D16 7 NVCC_EIM_SEC 8 VCC Package Information and Contact Assignments 9 NVCC_EIM_MAIN 10 NVCC_EIM_MAIN 11 NANDF_RB0 12 VDDA 13 NVCC_LVDS 14 NVCC_LVDS_BG 15 GND 16 TVDAC_DHVDD 17 TVDAC_AHVDDRGB Table 113. 19 × 19 mm, 0.8 Pitch Ball Map (continued) 18 VCC i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 19 GND 20 DRAM_D16 21 DRAM_D18 22 DRAM_D22 23 DRAM_D20 Freescale Semiconductor U AC GND 1 2 3 4 5 6 EIM_A17 EIM_OE EIM_DA5 EIM_DA12 EIM_DA9 EIM_BCLK NANDF_CS0 NANDF_CS3 PMIC_ON_REQ GND GND LVDS0_TX2_N LVDS0_TX0_N TVDAC_VREF GND TVDAC_COMP GND GND DRAM_D30 GND GND AB DRAM_D28 AA DRAM_D24 DRAM_D26 DRAM_SDQS3 DRAM_SDQS3_B Y PMIC_STBY_REQ GPIO_10 GPIO_12 GPIO_14 GND DRAM_DQM3 DRAM_D25 DRAM_D27 DRAM_D31 W NVCC_SRTC_POW NVCC_XTAL NANDF_CS1 NANDF_CS2 GND TVDAC_AHVDDRGB GPIO_11 GND GND GND GND GND DRAM_D29 V 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 GND EIM_A18 EIM_RW EIM_EB1 EIM_DA4 EIM_DA10 NANDF_WE_B EIM_WAIT CKIL EXTAL LVDS1_TX2_P LVDS1_TX1_P LVDS1_TX0_P LVDS0_TX3_N LVDS0_CLK_N LVDS0_TX1_N GND TVCDC_IOB_BACK TVDAC_IOG TVCDC_IOR_BACK LVDS0_TX0_P GPIO_13 LVDS0_TX2_P GND LVDS_BG_RES LVDS1_CLK_N LVDS1_CLK_P LVDS1_TX3_N LVDS1_TX3_P GND NANDF_ALE NANDF_CLE EIM_DA14 EIM_DA15 EIM_DA6 EIM_DA3 EIM_DA8 EIM_DA0 EIM_CS0 EIM_DA2 EIM_CS1 EIM_A19 EIM_LBA EIM_A20 EIM_A25 EIM_A16 EIM_A24 EIM_D31 EIM_A21 EIM_EB3 EIM_D30 EIM_D27 EIM_D26 EIM_A23 EIM_A22 EIM_EB2 EIM_D25 EIM_D21 GND EIM_D29 EIM_D24 EIM_D22 EIM_D19 GND EIM_D28 EIM_D23 EIM_D20 EIM_D18 AB AA Y W V 1 2 3 EIM_EB0 Freescale Semiconductor ECKIL XTAL 4 EIM_DA1 5 EIM_DA7 6 EIM_DA11 7 EIM_DA13 8 NANDF_RE_B 9 NANDF_WP_B 10 11 12 LVDS1_TX2_N 13 LVDS1_TX1_N 14 LVDS1_TX0_N 15 LVDS0_TX3_P 16 LVDS0_CLK_P 17 GND Table 113. 19 × 19 mm, 0.8 Pitch Ball Map (continued) LVDS0_TX1_P 18 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 GND GND AC 19 TVDAC_IOB 20 TVCDC_IOG_BACK 21 TVDAC_IOR 22 23 Package Information and Contact Assignments 177 Revision History 7 Revision History Table 114. i.MX53xA Data Sheet Document Revision History Rev. Number Rev 1 Date 3/2011 Substantive Change(s) • Updated the first sentence of Section 3.1, “Special Signal Considerations.” • Deleted two tables, “Special Signal Considerations” and “JTAG Controller Interface Summary,” in Section 3.1, “Special Signal Considerations.” • Updated Table 6, "i.MX53xA Operating Ranges," on page 19. • Changed VDDGP voltages as follows: — 800 MHz from 1.0/1.05/1.1 to 1.05/1.1/1.15 V minimum/nominal/maximum. — Stop mode from 0.9/0.95/1.1 to 0.8/0.85/1.15 V minimum/nominal/maximum. Added statements to footnotes 4 and 5. Table 114 provides a revision history for this data sheet. • Rev 0 02/2011 Initial release. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 178 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 179 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM Cortex A8 is a trademark of ARM Limited. © Freescale Semiconductor, Inc., 2011. All rights reserved. Document Number: IMX53AEC Rev. 1 3/2011