MM908E622

Freescale Semiconductor Technical Data MM908E622 Rev 1.0, 09/2005 Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror The 908E622 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOSTM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator module. The analog control die provides four half-bridge and three high-side outputs with diagnostic functions, an EC glass driver circuit, a Hall-Effect sensor input, analog inputs, voltage regulator, window watchdog, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive high-end mirrors. Features • • • • • • • • • • • • • High-Performance M68HC908EY16 Core 16 K Bytes of On-Chip Flash Memory, 512 Bytes of RAM Internal Clock Generator Module (ICG) Two 16-Bit, 2-Channel Timers 10-Bit Analog-to-Digital Converter (ADC) LIN Physical Layer Interface Autonomous MCU Watchdog / MCU Supervision One Analog Input with Switchable Current Source Four Low RDS(ON) Half-Bridge Outputs Three Low RDS(ON) High-Side Outputs EC glass driver circuitry Wake-Up Input One 2/3-Pin Hall-Effect Sensor Input • 12 Microcontroller I/Os 908E622 >2 2µF 100nF 908E622 QUAD HALF-BRIDGE, TRIPLE HIGH-SIDE SWITCH AND EC GLASS CIRCUITRY WITH EMBEDDED MCU AND LIN DWB SUFFIX 98ARL10519D 54-TERMINAL SOICW-EP ORDERING INFORMATION Device MM908E622ACDWB/R2 Temperature Range (TA) -40°C to 85°C Package 54 SOICW-EP LIN VSUP[1:8] L0 Wake Up Input 100nF 7 4. µF VDDA/VREFH EVDD VDD VSSA/VREFL EVSS VSS RST_A RST IRQ_A IRQ PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTC2/MCLK PTC3/OSC2 PTC4/OSC1 HB1 HB2 M M 4 x Half Bridge Outputs HB3 M HB4 HS1 HS2 HS3 High Side Output 1 High Side Output 2 High Side Output 3 µC PortA µC PortB ECR EC EC - Glas Control µC PortC HVDD A0 A0CST H0 GND[1:4] EP TESTMODE Switched 5V output Analog Input with current source Analog Input current source trim 2-/3-pin hall sensor input Pull to ground for user mode Internally connected µC PortD µC PortE PTD0/TACH0 PTD1/TACH1 PTE1/RxD Internally connected Figure 1. 908E622 Simplified Application Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. 2 VSSA/VREFL EVSS IRQ GND[1:4] VSUP[1:8] TESTMODE RST_A IRQ_A PTD0/TACH0 PTE1/RXD RST LIN 908E622 Single Breakpoint Break Module Voltage Regulator PTE1/RXD PTE0/TXD TXD LIN Physical Layer Switched VDD Driver & Diagnostic Wakeup Port Reset Control High Side Driver & Diagnostic High Side Driver & Diagnostic High Side Driver & Diagnostic RXD 5-Bit Keyboard Interrupt Module 2-channel Timer Interface Module A 2-channel Timer Interface Module B Enhanced Serial Communication Interface Module Autonomous Watchdog Computer Operating Properly Module Serial Peripheral Interface Module Configuration Register Module Periodic Wake-up Timebase Module Arbiter Module Prescaler Module BEMF Module PTC1/MOSI PTA5/SPSCK PTC0/MISO PTA6/SS SS MISO MOSI SPSCK SPI & CONTROL PTD0/TACH0 PWM VSS VDD HVDD L0 HS1[a:b] HS2 HS3 HB1 Internal Bus EVDD Internal Block Diagram VDDA/VREFH M68HC08 CPU CPU ALU Registers PTA0/KBD0 Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), 1024 Bytes PTA1/KBD1 User Flash Vector Space, 36 Bytes PTA2/KBD2 OSC2 Internal Clock OSC1 Generator Module PTA3/KBD3 Single External IRQ Module RST 24 Internal System Integration Module PTA4/KBD4 IRQ Half Bridge Driver & Diagnostic PTB3/AD3 PTB4/AD4 INTERNAL BLOCK DIAGRAM HB2 PTB5/AD5 Power-ON Reset Module Security Module VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS Half Bridge Driver & Diagnostic PTC2/MCLK Half Bridge Driver & Diagnostic HB3 PTC3/OSC2 PORT C DDRC Half Bridge Driver & Diagnostic HB4 ECR EC glass Driver & Diagnostic Hallport EC H0 DDRA PORT A PTC4/OSC1 PTD1/TACH1 PTD1/TACH1 PTD0/TACH0 PTE1/RXD PTE0/TXD PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO FLSVPP DDRB PORT B PTB0/AD0 ADOUT PORT D PORT E DDRD DDRE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 Analog Multiplexer A0 A0CST Analog Port with Current Source Analog Integrated Circuit Device Data Freescale Semiconductor Figure 2. 908E622 Simplified Internal Block Diagram Terminal Connections TERMINAL CONNECTIONS Transparent Top View of Package PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 (PTD0/TACH0/BEMF -> PWM) PTD1/TACH1 RST_A IRQ_A LIN A0CST A0 GND1 HB4 VSUP1 GND2 HB3 VSUP2 EC ECR TESTMODE GND3 HB2 VSUP3 Exposed Pad 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VDDA/VREFH EVDD EVSS VSSA/VREFL (PTE1/RXD PWM) MCU MCU / Analog 10 44 PTD1/TACH1 (PTE1/RXD 20V Normal Mode Total Output Current Load Regulation - IOUT = 60 mA, VSUP = 9V, TJ = 125°C STOP Mode Output Voltage (14) STOP Mode Total Output Current VDDRUN1 VDDRUN2 IOUTRUN VLR VDDSTOP IOUTSTOP 4.75 4.75 – – 4.75 150 5.0 5.0 120 – 5.0 500 5.25 5.25 150 100 5.25 850 mA mV V uA V TRON TIH 155 5.0 – – 180 10.0 TION TIH 125 5.0 – – 150 10.0 °C VHVION VHVI_HYS 20 0.5 – – 24 1.5 °C VLVION VLVI_HYS 6.0 0.3 – – 7.5 0.8 V VLVRON VLVR_HYS 3.8 50 4.2 – 4.65 300 V mV V Symbol Min Typ Max Unit Notes 12. This parameter is guaranteed by process monitoring but is not production tested. 13. Specification with external low ESR ceramic capacitor 1.0 µF< C < 4.7 µF and 200 mΩ ≤ ESR ≤ 10 Ω. Its not recommended to use capacitor values above 4.7 µF 14. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Static Electrical Characteristics Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LIN Physical Layer LIN Transceiver Output Voltage Recessive State, TXD HIGH, IOUT = 1.0 µA Dominant State, TXD LOW, 500 Ω External Pullup Resistor Normal Mode Pullup Resistor to VSUP Stop, Sleep Mode Pullup Current Source Output Current Shutdown Threshold Output Current Shutdown Timing Leakage Current to GND VSUP Disconnected, VBUS at 18V Recessive state, 8V ≤ VSUP ≤ 18V, 8V ≤ VBUS ≤ 18V, VBUS ≥ VSUP GND Disconnected, VGND = VSUP, VBUS at -18V LIN Receiver Receiver Threshold Dominant Receiver Threshold Recessive Receiver Threshold Center Receiver Threshold Hysteresis VBUS_DOM VBUS_REC VBUS_CNT VBUS_HYS – 0.6 0.475 – – – 0.5 – 0.4 – 0.525 0.175 IBUS IBUS-PAS-REC IBUS-NOGND – 0.0 -1.0 1.0 3.0 – 10 20 1.0 µA µA mA VSUP V LIN_REC V LIN_DOM R PU IPU IBLIM IBLS VSUP -1 — 20 — 100 5.0 — — 30 20 230 – — 1.4 47 — 280 40 kΩ µA mA µs V Symbol Min Typ Max Unit 908E622 10 Analog Integrated Circuit Device Data Freescale Semiconductor Static Electrical Characteristics Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic High-Side Output HS1 Switch On Resistance TJ = 25°C, ILOAD = 1.0 A Overcurrent Shutdown Overcurrent Shutdown blanking time (15) Current to Voltage Ratio (16) Symbol Min Typ Max Unit mΩ RDS(ON)-HS1 IHSOC1 tOCB CRRATIOHS1 – 6.0 – 0.84 185 – 4-8 1.2 225 9.0 – 1.56 A µs V/A VADOUT [V] / IHS [A], (measured and trimmed IHS = 2 A) High-Side Switching Frequency (15) High-Side Free-Wheeling Diode Forward Voltage TJ = 25°C, ILOAD = 1 A Leakage Current High-Side Outputs HS2 and HS3(17) Switch On Resistance TJ = 25°C, ILOAD = 1.0 A Overcurrent Shutdown Overcurrent Shutdown blanking time (15) Current to Voltage Ratio (16) fPWMHS VHSF – – – 0.9 25 – kHz V ILeakHS – P0 = 0. The parity bit is only evaluated during a write operations and ignored for read operations. Bit X A4 - A0 include the address of the desired register. not used Master Address Byte 908E622 48 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Device Operation Logic Commands and Registers Master Data Byte This byte includes data to be written or no valid data during a read operation. Slave Status Byte This byte includes always the contents of the system status register ($0C) independent if it is a write or read operation or which register was selected. Slave Data Byte This byte includes the contents of selected register, during write operation in includes the register content prior to write operation. 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 49 Functional Device Operation Logic Commands and Registers SPI REGISTER OVERVIEW Table 13. SPI Register Overview Addr Register Name R/W TABLE 13 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER. Bit 7 6 5 4 3 2 1 0 $00 System Control (SYSCTL) Half-Bridge Output (HBOUT) High-Side Output (HSOUT) Half-Bridge Status and Control (HBSCTL) High-Side Status and Control (HSSCTL) EC Status and Control (ECSCTL) EC Digital to Analog Control (ECDACC) H0/L0 Status and Control (HLSCTL) A0 and Multiplexer Control (A0MUCTL) Interrupt Mask (IMR) Interrupt Flag (IFR) Watchdog Control (WDCTL) System Status (SYSSTAT) Reset Status (RSR) System Test (SYSTEST) System Trim 1 (SYSTRIM1) System Trim 2 (SYSTRIM2) System Trim 3 (SYSTRIM3) R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W HVDDT1 0 POR WDRE LINCL L0IF CSON L0F ECON 0 HVDDOCF CRM HVDDON PSON 0 STOP HB4_L 0 0 SLEEP HB3_H HTIS1 HTIS0 VIS SRS1 SRS0 $01 HB4_H HB3_L HB2_H HB2_L HB1_H HB1_L $02 HS3PWM 0 HS2PWM 0 HS1PWM HS3ON HS2ON HS1ON $03 0 HB4OCF 0 HB3OCF HB2OCF HB1OCF $04 0 0 0 HS3OCF 0 HS2OCF HS1OCF $05 ECOLT 0 ECRON 0 0 ECOCF ECOLF $06 ECDAC5 0 ECDAC4 ECDAC3 H0F ECDAC2 ECDAC1 ECDAC0 0 $07 H0OCF H0EN H0PD H0MS $08 CSSEL1 CSSEL0 CSA SS3 SS2 SS1 SS0 $09 L0IE H0IE LINIE HTRD HTIE LVIE HVIE PSFIE PSFIF $0A H0IF LINIF 0 0 HTIF 0 LVIF 0 HVIF 0 $0B WDP1 HTIF WDP0 VF 0 WDRST $0C H0F HVDDF HSF HBF ECF $0D PINR WDR HTR LVR 0 LINWF L0WF $0E $0F reserved HVDDT0 0 reserved 0 CRHB5 0 CRHS5 reserved 0 CRHB4 0 CRHS4 itrim3 0 CRHB3 0 CRHS3 itrim2 0 CRHB2 0 CRHS2 itrim1 0 CRHB1 0 CRHS1 itrim0 0 CRHB0 0 CRHS0 $10 CRHBHC1 CRHBHC0 0 0 $11 CRHBHC3 CRHBHC2 908E622 50 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Device Operation Logic Commands and Registers FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E622, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” ($FF) state: • $FD80:$FDDF Trim and Calibration Values • $FFFE:$FFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate this dependencies a ICG trim values is located at address $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) VDD = 5V, TAmbient~25°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to copied after every reset. Table 14. Window Clear Interval Window Period Range Select bits $FDCF WDP1:0 Watchdog Period t_wd min. max. Unit Effective Open Window t_open t_closed Unit Optimal Clear Interval t_opt Unit max. variation Watchdog Period Range Value (AWD Trim) The window watchdog supervises device recover from e.g. code runaways. The application software has to clear the watchdog within the open window. Due to the high variation of the watchdog period - and therefore the reduced width of the watchdog window - a value is stored at address $FDCF. This value classifies the watchdog period into 3 ranges (Range 0, 1, 2). This allows the application software to select one out of three time intervals to clear the watchdog based on the stored value. The classification is done in a way that the application software can have up to ±19% variation of the of optimal clear interval, e.g. caused by ICG variation. Effective Open Window Having a variation in the watchdog period in conjunction with a 50% open window results in effective open window, which can be calculated by: latest window open time: t_open = t_wd max / 2 earliest window closed time: t_closed = t_wd min Optimal Clear Interval The optimal clear interval - meaning the clear interval with the biggest possible variation to latest window open time and to the earliest window closed time can be calculated with the following formula: t_opt = t_open + (t_open+t_closed) / 2 See Table 14 to select the optimal clear interval for the watchdog based on the Window No. and chosen period. 00 0 01 10 11 00 1 01 10 11 00 2 01 10 11 68 34 17 8.5 92 46 23 11.5 52 26 13 6.5 92 46 23 11.5 124 62 31 15.5 68 34 17 8.5 ms ms ms 46 23 11.5 5.75 62 31 15.5 7.75 34 17 8.5 4.25 68 34 17 8.5 92 46 23 11.5 52 26 13 6.5 ms ms ms 57 28.5 14.25 7.125 77 38.5 19.25 9.625 43 21.5 10.75 5.375 ms ±20.9% ms ±19.5% ms ±19.3% 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 51 Functional Device Operation Logic Commands and Registers Analog Die System Trim Values For improved application performance and to ensure the outlined datasheet values the analog die needs to be trimmed. For this purpose 3 trim values are stored in the Flash memory at address $FDC4 - $FDC6. These values have to be copied into the analog die SPI registers: • copy $FDC4 into SYSTRIM1 register $0F • copy $FDC5 into SYSTRIM2 register $10 • copy $FDC6 into SYSTRIM3 register $11 Note: This values have to be copied to the respective SPI register after a reset to ensure proper trimming of the device. HVDDT1 HVDDT0 typical Delay 1 1 78us ITRIM3:0 - IRef Trim Bits These write only bits are for trimming of the internal current references IRef (also A0, A0CST). The provided trim values have to be copied into these bits after every reset. Reset clears the ITRIM3:0 bits. System Test Register (SYSTEST) Register Name and Address: SYSTEST - $0E Table 16. IRef Trim Bits itrim3 itrim2 itrim2 itrim0 Adjustment 0 Bit0 reserved 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 2% 4% 8% 12% -2% -4% -8% -12% Bit7 Read reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Note: do not write to the reserved bits The System Test Register is reserved for production testing and is not allowed to be written to. 0 0 System Trim Register 1 (SYSTRIM1) Register Name and Address: IBIAS - $0F 1 System Trim Register 2 (SYSTRIM2) 1 Bit0 ITRIM0 Bit7 Read HVDDT1 6 HVDDT0 5 0 reserved 4 0 reserved 3 ITRIM3 2 ITRIM2 Write Reset 0 0 ITRIM1 Register Name and Address: IFBHBTRIM - $10 Bit7 0 0 0 0 Read Write Reset 0 CRHBHC1 6 0 CRHBHC0 5 0 CRHB5 4 0 CRHB4 3 0 CRHB3 2 0 CRHB2 1 0 Bit0 0 0 0 Note: do not change (set) the reserved bits CRHB1 CRHB0 0 0 0 0 0 0 0 0 HVDDT1:0 - HVDD Overcurrent Shutdown Delay Bits These read/write bits allow to change the filter time (for capacitive load) for the HVDD over current detection. Reset clears the HVDDT1:0 bits an sets the delay to the maximum value. Table 15. HVDD Overcurrent Shutdown Selection Bits HVDDT1 HVDDT0 typical Delay CRHBHC1:0 - Current Recopy HB1:2 Trim Bits These write only bits are for trimming of the current recopy of the half-bridge HB1 and HB2 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC1:0 bits. Table 17. Current Recopy Trim for HB1:2 (CSA=0) CRHBHC1 CRHBHC0 Adjustment 0 0 1 0 1 0 950us 536us 234us 0 0 0 1 0 -10% 908E622 52 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Device Operation Logic Commands and Registers CRHBHC1 CRHBHC0 Adjustment 1 1 0 1 5% 10% System Trim Register 3 (SYSTRIM3) Register Name and Address: IFBHSTRIM - $11 CRHB5:3 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming of the current recopy of the half-bridge HB3 and HB4 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB5:3 bits. Table 18. Current Recopy Trim for HB3:4 (CSA=1) CRHB5 CRHB4 CRHB3 Adjustment Bit7 Read Write Reset 0 CRHBH C3 6 0 CRHBH C2 5 0 CRHS5 4 0 CRHS4 3 0 CRHS3 2 0 CRHS2 1 0 CRHS1 Bit0 0 CRHS0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -5% -10% -15% reserved 5% 10% 15% CRHBHC3:2 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming of the current recopy of the half-bridge HB3 and HB4 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC3:2 bits. Table 20. Current Recopy Trim for HB3:4 (CSA=0) CRHBHC3 CRHBHC2 Adjustment 0 0 1 1 0 1 0 1 0 -10% 5% 10% CRHB2:0 - Current Recopy HB1:2 Trim Bits These write only bits are for trimming of the current recopy of the half-bridge HB1 and HB2 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB2:0 bits. Table 19. Current Recopy Trim for HB1:2 (CSA=1) CRHB2 CRHB1 CRHB0 Adjustment CRHS5:3 - Current Recopy HS2:3 Trim Bits These write only bits are for trimming of the current recopy of the high-side HS2 and HS3. The provided trim values have to be copied into these bits after every reset. Reset clears the CRHS5:3 bits. Table 21. Current Recopy Trim for HS2:3 CRHS5 CRHS4 CRHS3 Adjustment 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -5% -10% -15% reserved 5% 10% 15% 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -5% -10% -15% reserved 5% 10% 15% 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 53 Functional Device Operation Logic Commands and Registers CRHS2:0 - Current Recopy HS1 Trim Bits These write only bits are for trimming of the current recopy of the high-side HS1. The provided Trim values have to be copied into these bits after every reset. Reset clears the CRHS2:0 bits. Current Recopy Trim for HS1 CRHS2 CRHS1 CRHS0 Adjustment CRHS2 CRHS1 CRHS0 Adjustment 0 1 1 1 1 0 0 1 1 1 0 1 0 1 -15% reserved 5% 10% 15% 0 0 0 0 0 1 0 1 0 0 1 -5% -10% 908E622 54 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications TYPICAL APPLICATIONS DEVELOPMENT SUPPORT As the 908E622 has the MC68HC908EY16 MCU embedded, typically all the development tools available for the MCU also apply for this device. However, due to the additional analog die circuitry and the nominal +12V supply voltage, some additional items have to be considered: • nominal 12V rather than 5V or 3V supply • high voltage VTST might be applied not only to IRQ terminal, but IRQ_A terminal • MCU monitoring (Normal request time-out) has to be disabled For a detailed information on the MCU related development support see the MC68HC908EY16 datasheet section development support. The programming is principally possible at two stages in the manufacturing process - first on chip level, before the IC is soldered onto a pcb board, and second after the IC is soldered onto the pcb board. Chip level programming At the Chip level, the easiest way is to only power the MCU with +5V (see Figure 32), and not to provide the analog chip with VSUP. In this setup all the analog terminal should be left open (e.g. VSUP[1:8]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 datasheet - section development support. VSUP[1:8] GND[1:4] VDD VSS +5V VDDA/VREFH RST EVDD RST_A +5V 1 1µF + 3 4 1µF + 5 C2C1C2+ GND V+ 15 2 6 1µF 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 5 R2OUT 9 2 1 3 6 4 5 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK +5V + CLK PTC4/OSC1 PTB4/AD4 10k TESTMODE 10k C1+ VCC 16 + 1µF 1µF VTST IRQ IRQ_A VSSA/VREFL 100nF 4.7µF MM908E622 EVSS +5V MAX232 V- RS232 DB-9 2 Figure 32. Normal Monitor Mode Circuit (MCU only) Of course its also possible to supply the whole system with Vsup instead (12V) as described in Figure 33, page 56. 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 55 Typical Applications PCB level programming If the IC is soldered onto the pcb board, its typically not possible to separately power the MCU with +5V. The whole system has to be powered up providing VSUP (see Figure 33).. VDD VSUP 47µF + 100nF VSUP[1:8] GND[1:4] VDD VSS VDDA/VREFH RST EVDD RST_A VDD 1 1µF + 3 4 1µF + 5 C2C1C2+ GND V+ 15 2 6 1µF 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 5 R2OUT 9 2 1 3 6 4 5 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK VDD + CLK PTC4/OSC1 PTB4/AD4 10k 10k TESTMODE 10k C1+ VCC 16 + 1µF 1µF VTST IRQ IRQ_A VSSA/VREFL 100nF 4.7µF MM908E622 EVSS VDD MAX232 V- RS232 DB-9 2 Figure 33. Normal Monitor Mode Circuit Table 22 summarizes the possible configurations and the necessary setups. Table 22. Monitor Mode Signal Requirements and Options Reset Vector Serial Communication PTA0 Normal Monitor Mode IRQ RST TESTMODE Mode Selection PTB3 0 ICG COP PTA1 0 PTB4 1 OFF OFF disabled disabled disabled Communication Speed Normal Request Baud Bus Time-out External Clock Frequency Rate disabled disabled disabled 9.8304 MHz 9.8304 MHz — 2.4576 MHz 2.4576 MHz Nominal 1.6MHz Nominal 1.6MHz 9600 9600 Nominal 6300 Nominal 6300 VTST VDD VDD 1 X 1 Forced Monitor VDD GND 1 $FFFF (blank) 1 0 X X ON User VDD VDD 0 not $FFFF (not blank) X X X X ON enabled enabled — Notes 1. PTA0 must have a pullup resistor to VDD in monitor mode 2. 3. 4. 5. External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don’t care VTST is a high voltage VDD + 3.5V ≤ VTST ≤ VDD + 4.5V 908E622 56 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications EMC/EMI RECOMMENDATIONS This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be e.g. found on the Freescale web site www.freescale.com. VSUP terminals (VSUP[1:8]) Its recommended to place a high quality ceramic decoupling capacitor close to the VSUP terminals to improve EMC/EMI behavior. LIN terminal For DPI (Direct Power Injection) and ESD (Electrostatic Discharge) its recommended to place a high quality ceramic decoupling capacitor near the LIN terminal. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. Voltage regulator output terminals (VDD and VSS) Use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. D1 VSUP C1 + C2 VSUP[1:8] MCU digital supply terminals (EVDD and EVSS) Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high quality ceramic decoupling capacitor be placed between these terminals. MCU analog supply terminals (VREFH/VDDA and VREFL/ VSSA) To avoid noise on the analog supply terminals, its important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. Figure 34 and Figure 35 show the recommendations on schematics and layout level and Table 23 indicates recommended external components and layout considerations. VDD VSS L1 LIN V1 C5 LIN VDDA/VREFH EVDD C3 C4 MM908E622 GND[1:4] EVSS VSSA/VREFL Figure 34. EMC/EMI recommendations 908E622 Analog Integrated Circuit Device Data Freescale Semiconductor 57 Typical Applications 1 2 3 4 5 6 7 8 9 10 11 12 13 LIN 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VSUP3 VSUP4 GND3 VSUP6 VSUP5 GND4 VSUP2 VSUP1 GND2 VSUP7 VSUP8 GND1 VSS VDD VDDA/VREFH EVDD EVSS VSSA/VREFL 54 53 52 51 50 49 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 32 30 29 28 31 C5 908E622 C4 46 C3 GND C2 C1 D1 VBAT V1 L1 LIN Figure 35. PCB Layout Recommendations . Table 23. Component Value Recommendation Component Recommended Value(1) Comments / Signal routing D1 C1 C2 C3 Bulk Capacitor 100nF, SMD Ceramic, Low ESR 100nF, SMD Ceramic, Low ESR reverse battery protection Close to VSUP terminals with good ground return Close (