MM912F634CV2AE

Freescale Semiconductor Advanced Information Document Number: MM912F634 Rev. 5.0, 11/2010 Integrated S12 Based Relay Driver with LIN The MM912F634 is an integrated single package solution that integrates an HCS12 microcontroller with a SMARTMOS analog control IC. The Die to Die Interface (D2D) controlled analog die combines system base chip and application specific functions, including a LIN transceiver. Features • • • • • • • • • • • 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM Background Debug (BDM) & Debug Module (DBG) Die to Die bus interface for transparent memory mapping On-chip oscillator & two independent watchdogs LIN 2.1 Physical Layer Interface with integrated SCI Six digital MCU GPIOs shared with SPI (PA5…0) 10-Bit, 15 Channel - Analog to Digital Converter (ADC) 16-Bit, 4 Channel - Timer Module (TIM16B4C) 8-Bit, 2 Channel - Pulse width modulation module (PWM) Six high voltage / Wake-up inputs (L5.0) Three low voltage GPIOs (PB2.0) VSENSE1 VS1 VS2 LIN interface LIN LGND ADC2p5 ADC Supply AGND 2.5V Supply 5V Supply VDD EVDD VDDX EVDDX DGND EVSS EVSSX RESET RESET_A PA0/MISO PA1/MOSI PA2/SCK PA3/SS PA4 PA5 BKGD/MODC EXTAL XTAL TEST 1) MM912F634 48-PIN LQFP-EP, 7.0 mm x 7.0 mm AE SUFFIX: Exposed Pad Option 48-PIN LQFP, 7.0 mm x 7.0 mm AP SUFFIX: Non-exposed Pad Option ORDERING INFORMATION See Page 2. • • • • • • • • Low Power Modes with cyclic sense & forced wake-up Current Sense Module with selectable gain Reverse Battery protected Voltage Sense Module Two protected low side outputs to drive inductive loads Two protected high side outputs Chip temperature sensor Hall sensor supply Integrated voltage regulator(s) Battery Sense Power Supply MM912F634 LS1 PGND LS2 ISENSEH1 Current Sense Module ISENSEL1 HSUP Hall Sensor supply Low-Side Drivers M Hall Sensor Hall Sensor PTB0/AD0/RX/TIM0CH0 PTB1/AD1/TX/TIM0CH1 PTB2/AD2/PWM/TIM0CH2 HS1 Digital Ground 5V GPI/O with optional pull-up (shared with ADC, PWM, Timer, SCI) Reset HS21 12V Light/LED and switch supply 5V digital I/O Debug and external Oscillator MCU Test L0 L1 L21 L31 L41 L51 TCLK TEST_A Analog/Digital Inputs (High Voltage- and Wake Up capable) Analog Test Feature not available in all Analog Options Figure 1. Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved.. All rights reserved. Ordering Information 1 ‘ Ordering Information Table 1. Ordering Information Device MM912F634CV1AE MM912F634CV2AE MM912F634CV2AP Note: 1. See Table 2. -40 to 105 °C Temperature Range (TA) Package 98ASA00173D 48-PIN LQFP-EP 98ASH00962A 48-PIN LQFP Max. Bus Frequency (MHz) (fBUSMAX) 20 16 Flash (kB) 32 RAM (kB) Analog Option(1) 1 2 32 2 Table 2. Analog Options(2) Feature Current Sense Module Wake-up Inputs (Lx) Option 1 YES L0…L5 Option 2 NO L0…L3 Note: 2. This table only highlights the analog die differences between the derivatives. See Section 4.2.3, “Analog Die Options" for detailed information. The device part number is following the standard scheme below: MM 9 12 f Memory Size A – 1k B – 2k C – 4k D – 8k E – 16k F – 32k G – 48k H – 64k I – 96k J – 128k xxx r t a PP RR Product Category Memory Type MM – Qualified Standard 9 – FLASH, OTP SM – Custom Device Blank - ROM PM – Prototype Device MCU Core 08 – HC08 12 – HC12 Analog Core/ Target Revision (default A) TA Temperature Range I = 0°C to 85°C C = -40°C to 85°C V = -40°C to 105°C M = -40°C to 125°C Analog Die Option (default 1) Package Designator AE – LQFP48-EP AP – LQFP48 Tape & Reel Indicator Figure 2. Part Number Scheme MM912F634 Freescale Semiconductor 2 Ordering Information Table of Contents 1 2 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 MM912F634 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 MCU Die Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Thermal Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.8 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.9 Additional Test Information ISO7637-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Functional Description and Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 MM912F634 - Analog Die Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 Die to Die Interface - Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8 Wake-up / Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.9 Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.10 Hall Sensor Supply Output - HSUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.11 High Side Drivers - HS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.12 Low Side Drivers - LSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.13 PWM Control Module (PWM8B2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.14 LIN Physical Layer Interface - LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.15 Serial Communication Interface (S08SCIV4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.16 High Voltage Inputs - Lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.17 General Purpose I/O - PTB[0…2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.18 Basic Timer Module - TIM (TIM16B4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.19 Analog Digital Converter - ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.20 Current Sense Module - ISENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 4.21 Temperature Sensor - TSENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.22 Supply Voltage Sense - VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.23 Internal Supply Voltage Sense - VS1SENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.24 Internal Bandgap Reference Voltage Sense - BANDGAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.25 MM912F634 - Analog Die Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.26 MM912F634 - MCU Die Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.27 Port Integration Module (9S12I32PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.28 Memory Mapping Control (S12SMMCV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 4.29 Interrupt Module (S12SINTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.30 Background Debug Module (S12SBDMV1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.31 S12S Debug (S12SDBGV1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.32 S12S Clocks and Reset Generator (S12SCRGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 4.33 External Oscillator (S12SS12SCRGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 4.34 Real Time Interrupt (S12SRTIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 4.35 Computer Operating Properly (S12SCOPV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.36 32 kbyte Flash Module (S12SFTSR32KV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 4.37 Die-to-Die Initiator (D2DIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 4.38 Serial Peripheral Interface (S12SPIV4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 5.1 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 4 5 6 MM912F634 Freescale Semiconductor 3 BKGD/MODC RESET_A ISENSEH ISENSEL TEST_A RESET PGND TCLK LS2 Test Interface Internal Bus Current Sense Module Low Side Control Module LS1 L5 EXTAL Reset Control Module 2 Channel PWM Module L4 L3 Lx Input Module Reset Generation and Test Entry Single-Wire Background Debug Module COP Watchdog Real Time Interrupt Interrupt Module Interrupt Control Module L1 OSC (trimmable) Chip Temp Sense Module TEST Full Swing Pierce Oscillator Internal Reference Clock OSC Clock Monitor L0 PA5 M68HCS12 CPU PA4 ALU CPU Register Debug Module include 64 byte Trace Buffer RAM AGND D2DCLK Analog Multiplexer ADC 10bit Control and Status Register D2DDAT0 D2DDAT1 D2DI ADC2p5 PA3 RAM 2k Byte Flash 32k Bytes PA2 PTA DDRA D2DDAT2 D2DDAT3 Die To Die Interface PTB2/AD2/PWM/TIMCH2 SS SCK MOSI MISO PA1 SPI 4 Channel Timer Module GPIO PTB1/AD1/TX/TIMCH1 D2DINT PA0 MCU Die SCI PTB0/AD0/RX/TIMCH0 EVSSX Cascaded Voltage Regulators VDD = 2.5V VDDX = 5V High Side Control Module VBAT Sense Module 18V clamped Output Module LIN Physical Layer EVDDX LGND Figure 3. Device Block Diagram XTAL Internal Bus Window Watchdog Module Wake Up Module L2 MM912F634 HSUP HS2 LIN Analog Die Freescale Semiconductor EVSS VSENSE VDDX VS1 VS2 DGND EVDD VDD HS1 Ordering Information 4 Pin Assignment 2 Pin Assignment RESET_A ISENSEH ISENSEL TEST_A RESET PGND BKGD TCLK LS1 LS2 NC NC 48 47 46 45 44 43 42 41 40 39 38 37 NC EXTAL XTAL TEST PA5 PA4 PA3 PA2 PA1 PA0 EVSSX EVDDX 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 L5 L4 L3 L2 L1 L0 AGND ADC2p5 PTB2 PTB1 PTB0 LGND The device exposed pad (package option AE only) is recommended to be connected to GND. Not all pins are available for analog die option 2. See Section 4.2.3, “Analog Die Options" for details. 13 EVSS 14 EVDD 15 VDD Figure 4. MM912F634 Pin Out 16 VDDX 17 DGND 18 VSENSE NOTE 19 VS1 20 VS2 21 HS1 22 HS2 23 HSUP 24 LIN MM912F634 Freescale Semiconductor 5 Pin Assignment MM912F634 Pin Description 2.1 MM912F634 Pin Description The following table gives a brief description of all available pins on the MM912F634 package. Refer to the highlighted chapter for detailed information. Table 3. MM912F634 Pin Description Pin # 1 2 Pin Name NC EXTAL Formal Name Not connected Pin MCU Oscillator Pin Description This pin is reserved for alternative function and should be left floating or connected to GND. EXTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock. See Section 4.33, “External Oscillator (S12SS12SCRGV1)". XTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock. See Section 4.33, “External Oscillator (S12SS12SCRGV1)". This input only pin is reserved for test. This pin has a pull-down device. The TEST pin must be tied to EVSS in user mode. General purpose port A input or output pin 5. See Section 4.27, “Port Integration Module (9S12I32PIMV1)" General purpose port A input or output pin 4. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". General purpose port A input or output pin 3, shared with the SS signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". General purpose port A input or output pin 2, shared with the SCLK signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". General purpose port A input or output pin 1, shared with the MOSI signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". General-purpose port A input or output pin 0, shared with the MISO signal of the integrated SPI Interface. See Section 4.27, “Port Integration Module (9S12I32PIMV1)". Ground for the MCU 5.0 V power supply. MCU 5.0 V - I/O buffer supply. See Section 4.26, “MM912F634 - MCU Die Overview". Ground for the MCU 2.5 V power supply. MCU 2.5 V - MCU Core- and Flash power supply. See Section 4.26, “MM912F634 - MCU Die Overview". +2.5 V main voltage regulator output pin. External capacitor (CVDD) needed. See Section 4.4, “Power Supply". +5.0 V main voltage regulator output pin. External capacitor (CVDDX) needed. See Section 4.4, “Power Supply". This pin is the device digital ground connection for the 5.0 V and 2.5 V logic. DGND, LGND, and AGND are internally connected to PGND via a back to back diode. Battery voltage sense input. This pin can be connected directly to the battery line for voltage measurements. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC via the analog multiplexer.The pin is self-protected against reverse battery connections. An external resistor (RVSENSE) is needed for protection(3). See Section 4.22, “Supply Voltage Sense - VSENSE". 3 XTAL MCU Oscillator Pin 4 5 6 7 TEST PA5 PA4 PA3 MCU Test Pin MCU PA5 Pin MCU PA4 Pin MCU PA3 / SS Pin 8 PA2 MCU PA2 / SCK Pin 9 PA1 MCU PA1 / MOSI Pin 10 PA0 MCU PA0 / MISO Pin 11 12 13 14 15 16 17 18 EVSSX EVDDX EVSS EVDD VDD VDDX DGND VSENSE MCU 5.0 V Ground Pin MCU 5.0 V Supply Pin MCU 2.5 V Ground Pin MCU 2.5 V Supply Pin Voltage Regulator Output 2.5 V Voltage Regulator Output 5.0 V Digital Ground Pin Voltage Sense Pin MM912F634 Freescale Semiconductor 6 Pin Assignment Table 3. MM912F634 Pin Description (continued) Pin # 19 Pin Name VS1 Formal Name Power Supply Pin 1 Description MM912F634 Pin Description This pin is the device power supply pin 1. VS1 is primarily supplying the VDDX Voltage regulator and the Hall Sensor Supply Regulator (HSUP). VS1 can be sensed via a voltage divider through the AD converter. Reverse battery protection diode is required. See Section 4.4, “Power Supply" This pin is the device power supply pin 2. VS2 supplies the High Side Drivers (HSx). Reverse battery protection diode required. See Section 4.4, “Power Supply" This pin is the first High Side output. It is supplied through the VS2 pin. It is designed to drive small resistive loads with optional PWM. In cyclic sense mode, this output will activate periodically during low power mode. See Section 4.11, “High Side Drivers - HS". This pin is the second High Side output. It is supplied through the VS2 pin. It is designed to drive small resistive loads with optional PWM. In cyclic sense mode, this output will activate periodically during low power mode. See Section 4.11, “High Side Drivers - HS". 20 21 VS2 HS1 Power Supply Pin 2 High Side Output 1 22 HS2 High Side Output 2 23 HSUP Hall Sensor Supply Output This pin is designed as an 18 V Regulator to drive Hall Sensor Elements. It is supplied through the VS1 pin. An external capacitor (CHSUP) is needed. See Section 4.10, “Hall Sensor Supply Output - HSUP". LIN Bus I/O LIN Ground Pin General Purpose I/O 0 This pin represents the single-wire bus transmitter and receiver. See Section 4.14, “LIN Physical Layer Interface - LIN". This pin is the device LIN Ground connection. DGND, LGND, and AGND are internally connected to PGND via a back to back diode. This is the General Purpose I/O pin 0 based on VDDX with the following shared functions: • PTB0 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD0 - Analog Input Channel 0, 0…2.5 V (ADC2p5) analog input • TIM0CH0 - Timer Channel 0 Input/Output • Rx - Selectable connection to LIN / SCI See Section 4.17, “General Purpose I/O - PTB[0…2]". This is the General Purpose I/O pin 1 based on VDDX with the following shared functions: • PTB1 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD1 - Analog Input Channel 1, 0…2.5 V (ADC2p5) analog input • TIM0CH1 - Timer Channel 1 Input/Output • Tx - Selectable connection to LIN / SCI See Section 4.17, “General Purpose I/O - PTB[0…2]". This is the General Purpose I/O pin 2 based on VDDX with the following shared functions: • PTB2 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD2 - Analog Input Channel 2, 0…2.5 V (ADC2p5) analog input • TIM0CH2 - Timer Channel 2 Input/Output • PWM - Selectable connection to PWM Channel 0 or 1 See Section 4.17, “General Purpose I/O - PTB[0…2]". This pin represents the ADC reference voltage and has to be connected to a filter capacitor. See Section 4.19, “Analog Digital Converter - ADC" This pin is the device Analog to Digital Converter ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode. 24 25 26 LIN LGND PTB0 27 PTB1 General Purpose I/O 1 28 PTB2 General Purpose I/O 2 29 30 ADC2p5 AGND ADC Reference Voltage Analog Ground Pin MM912F634 Freescale Semiconductor 7 Pin Assignment Table 3. MM912F634 Pin Description (continued) Pin # 31 Pin Name L0 Formal Name High Voltage Input 0 Description MM912F634 Pin Description This pins is the High Voltage Input 0 with the following shared functions: • L0 - Digital High Voltage Input 0. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4) • AD3 - Analog Input 3 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU0 - Selectable Wake-up input 0 for wake up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx" This pins is the High Voltage Input 1 with the following shared functions: • L1 - Digital High Voltage Input 1. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4) • AD4 - Analog Input 4 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU1 - Selectable Wake-up input 1 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx" This pins is the High Voltage Input 2 with the following shared functions: • L2 - Digital High Voltage Input 2. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4) • AD5 - Analog Input 5 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU2 - Selectable Wake-up input 2 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". This pins is the High Voltage Input 3 with the following shared functions: • L3 - Digital High Voltage Input 3. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4) • AD6 - Analog Input 6 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU3 - Selectable Wake-up input 3 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". This pins is the High Voltage Input 4 with the following shared functions: • L4 - Digital High Voltage Input 4. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4) • AD7 - Analog Input 7 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU4 - Selectable Wake-up input 4 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available on all device configurations. This pins is the High Voltage Input 5 with the following shared functions: • L5 - Digital High Voltage Input 5. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4) • AD8 - Analog Input 8 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU5 - Selectable Wake-up input 5 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available on all device configurations. Low Side output 1 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.12, “Low Side Drivers - LSx" This pin is the device Low Side Ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode. 32 L1 High Voltage Input 1 33 L2 High Voltage Input 2 34 L3 High Voltage Input 3 35 L4 High Voltage Input 4 36 L5 High Voltage Input 5 37 LS1 Low Side Output 1 38 PGND Power Ground Pin MM912F634 Freescale Semiconductor 8 Pin Assignment Table 3. MM912F634 Pin Description (continued) Pin # 39 Pin Name LS2 Formal Name Low Side Output 2 Description MM912F634 Pin Description Low Side output 2 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.12, “Low Side Drivers - LSx" Current Sense differential input “Low”. This pin is used in combination with ISENSEH to measure the voltage drop across a shunt resistor. See Section 4.20, “Current Sense Module - ISENSE". Note: This pin function is not available on all device configurations. Current Sense differential input “High”. This pin is used in combination with ISENSEL to measure the voltage drop across a shunt resistor. Section 4.20, “Current Sense Module - ISENSE". Note: This pin function is not available on all device configurations. This pin is reserved for alternative function and should be left floating. Analog die Test Mode pin for Test Mode only. This pin must be grounded in user mode! Test Mode Clock Input pin for Test Mode only. The pin can be used to disable the internal watchdog for development purpose in user mode. See Section 4.9, “Window Watchdog". The pin is recommended to be grounded in user mode. Bidirectional Reset I/O pin of the analog die. Active low signal. Internal pull-up. VDDX based. See Section 4.7, “Resets". To be externally connected to the RESET pin. The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device to EVDDX. The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pull-up device. This pin is reserved for alternative function and should be left floating or connected to GND. 40 ISENSEL Current Sense Pins L 41 ISENSEH Current Sense Pins H 42 43 44 NC TEST_A TCLK Not connected Pin Test Mode Pin Test Clock Input 45 46 RESET_A RESET Reset I/O MCU Reset Pin 47 BKGD MCU Background Debug and Mode Pin 48 NC Not connected Pin Note: 3. An optional filter capacitor CVSENSE is recommended to be placed between the board connector and RVSENSE to GND for increased ESD performance. 4. An optional filter capacitor CLx is recommended to be placed between the board connector and RLx to GND for increased ESD performance. MM912F634 Freescale Semiconductor 9 Pin Assignment MCU Die Signal Properties 2.2 MCU Die Signal Properties This section describes the external MCU signals. It includes a table of signal properties. Table 4. Signal Properties Summary Pin Name Function 1 EXTAL XTAL RESET TEST BKGD PA5 PA4 PA3 PA2 PA1 PA0 Pin Name Function 2 — — — — MODC — — SS SCK MOSI MISO Internal Pull Resistor Description CTRL VDD VDD VDDX N.A. VDDX VDDX VDDX VDDX VDDX VDDX VDDX NA NA Pull-up RESET pin Always on NA NA NA NA NA NA Down UP NA NA NA NA NA NA Reset State NA NA External reset Test input Background debug Port A I/O Port A I/O Port A I/O, SPI Port A I/O, SPI Port A I/O, SPI Port A I/O, SPI Oscillator pins Power Supply MM912F634 Freescale Semiconductor 10 Electrical Characteristics General 3 3.1 Electrical Characteristics General This supplement contains electrical information for the embedded MC9S12I32 microcontroller die, as well as the MM912F634 analog die. 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. All voltages are with respect to ground unless otherwise noted. Table 5. Absolute Maximum Electrical Ratings - Analog Die Ratings Supply Voltage at VS1 and VS2 Normal Operation (DC) Transient Conditions (load dump) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) Symbol VSUP(SS) VSUP(PK) VSUP(TR) Value -0.3 to 27 -0.3 to 40 see Section 3.9, “Additional Test Information ISO7637-2" V VLxDC VLxTR -27 to 40 see Section 3.9, “Additional Test Information ISO7637-2" V VBUSDC VBUSTR -33 to 40 see Section 3.9, “Additional Test Information ISO7637-2" -0.3 to 5.5 -0.3 to 2.75 Internally Limited Internally Limited -0.3 to 10 -0.3 to VDDx+0.3 -0.3 to VDDx+0.3 -0.3 to VS2+0.3 -0.3 to 45 -0.3 to 40 -0.3 to VS1+0.3 -27 to 40 V V A A V V V V V V V V Unit V L0…L5 - Pin Voltage Normal Operation with a series RLX resistor (DC) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) LIN Pin Voltage Normal Operation (DC) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) Supply Voltage at VDDX Supply Voltage at VDD VDD output current VDDX output current TCLK Pin Voltage RESET_A Pin Voltage Input / Output Pins PTB[0:2] Voltage HS1 and HS2 Pin Voltage (DC) LS1 and LS2 Pin Voltage (DC) ISENSEH and ISENSEL Pin Voltage (DC) HSUP Pin Voltage (DC) VSENSE Pin Voltage (DC) VDDX VDD IVDD IVDDX VTCLK VIN VIN VHS VLS VISENSE VHSUP VVSENSE MM912F634 Freescale Semiconductor 11 Electrical Characteristics Table 6. Maximum Electrical Ratings - MCU Die Ratings 5.0 V Supply Voltage 2.5 V Supply Voltage Digital I/O input voltage (PA0...PA7, PE0, PE1) EXTAL, XTAL TEST input Instantaneous maximum current Single pin limit for all digital I/O pins Instantaneous maximum current Single pin limit for EXTAL, XTAL Symbol VEDDX VEDD VIN VILV VTEST I I D Operating Conditions Value -0.3 to 6.0 -0.3 to 2.75 -0.3 to 6.0 -0.3 to 2.16 -0.3 to 10.0 -25 to 25 -25 to 25 Unit V V V V V mA mA DL Table 7. Maximum Thermal Ratings Ratings Storage Temperature Package (98ASA00173D), Thermal Resistance Peak Package Reflow Temperature During Reflow(5),(6) Symbol TSTG RθJA TPPRT Value -55 to 150 max. 48 300 Unit °C k/W °C Notes 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC34xxxD enter 34xxx), and review parametrics. 3.3 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. Table 8. Operating Conditions Ratings Analog Die Nominal Operating Voltage Analog Die Functional Operating Voltage - Device is fully functional. All features are operating. MCU I/O and supply voltage(7) MCU Digital logic supply voltage MCU External Oscillator MCU Bus frequency Operating Ambient Temperature MM912x634xVxxx Operating Junction Temperature - Analog Die Operating Junction Temperature - MCU Die Note: 7. During power up and power down sequence always VDD < VDDX 8. fBUSMAX frequency ratings differ by device and is specified in Table 1 (7) Symbol VSUP VSUPOP VEDDX VEDD fOSC fBUS TA TJ_A TJ_M Value 5.5 to 18 5.5 to 27 4.5 to 5.5 2.25 to 2.75 4.0 to 16 fBUSMAX(8) -40 to 105 -40 to 150 -40 to 140 Unit V V V V MHz MHz °C °C °C MM912F634 Freescale Semiconductor 12 Electrical Characteristics Supply Currents 3.4 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. 3.4.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted, the currents are measured in MCU special single chip mode and the CPU code is executed from RAM. Table 9. Supply Currents Ratings Normal Mode analog die only, excluding external loads, LIN Recessive State (5.5 V ≤ VSUP ≤ 18 V, 2.25 V ≤ EVDD ≤ 2.75 V, 4.5 V ≤ EVDDX ≤ 5.5 V, -40 °C ≤ TJ_A ≤ 150 °C). Normal Mode MCU die only (TJ_M = 140 °C; VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(13))(10) Stop Mode internal analog die only, excluding external loads, LIN Recessive State, Lx enabled, measured at VS1+VS2 (5.5 V ≤ VSUP ≤ 18 V, 2.25 V ≤ EVDD ≤ 2.75 V, 4.5 V ≤ EVDDX ≤ 5.5 V) -40 °C ≤ TJ_A ≤ 125 °C 125 °C < TJ_A ≤ 140 °C Stop Mode MCU die only (VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(13); MCU in STOP; RTI and COP off)(11) TJ_M = 140 °C TJ_M = 105 °C TJ_M = 25 °C Stop Mode MCU die only (VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(13); MCU in STOP; RTI and COP on)(11) TJ_M = 140 °C TJ_M = 105 °C TJ_M = 25 °C Wait Mode MCU die only (TJ_M = 140 °C; VDD = 2.75 V, VDDX = 5.5 V, fOSC = 4.0 MHz, fBUS = fBUSMAX(13); All modules except RTI disabled)(12) Sleep Mode (VDD = VDDX = OFF; 5.5 V ≤ VSUP ≤ 18 V; -40 °C ≤ TJ_A ≤ 150 °C; 3.0 V < LX < 1.0 V). Cyclic Sense Supply Current Adder (5.0 ms Cycle) Note: 9. 10. 11. 12. 13. Symbol IRUN_A Min Typ(9) 5.0 Max 8.0 Unit mA IRUN_M ISTOP_A - 12.5 15 mA µA ISTOP_M ISTOP_M IWAIT_M ISLEEP ICS - 20 - 40 50 mA 0.135 0.035 0.010 0.400 0.200 0.030 mA 0.205 0.104 0.079 7.0 15 15 0.500 0.300 0.110 12 28 20 mA µA µA Typical values noted reflect the approximate parameter mean at TA = 25 °C IRUN_M denotes the sum of the currents flowing into VDD and VDDX. ISTOP_M denotes the sum of the currents flowing into VDD and VDDX. IWAIT_M denotes the sum of the currents flowing into VDD and VDDX. fBUSMAX frequency ratings differ by device and is specified in Table 1. MM912F634 Freescale Semiconductor 13 Electrical Characteristics Static Electrical Characteristics 3.5 Static Electrical Characteristics Static electrical characteristics noted under conditions 5.5V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 105 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted. 3.5.1 Static Electrical Characteristics Analog Die Table 10. Static Electrical Characteristics - Power Supply Ratings Power-On Reset (POR) Threshold (measured on VS1) Low Voltage Warning (LVI) Threshold (measured on VS1, falling edge) Hysteresis (measured on VS1) High Voltage Warning (HVI) Threshold (measured on VS2, rising edge) Hysteresis (measured on VS2) Low Battery Warning (LBI) Threshold (measured on VSENSE, falling edge) Hysteresis (measured on VSENSE) J2602 Under-voltage threshold Low VDDX Voltage (LVRX) Threshold Low VDD Voltage Reset (LVR) Threshold Normal Mode Low VDD Voltage Reset (LVR) Threshold Stop Mode VDD Over-voltage Threshold (VROV) VDDX Over-voltage Threshold (VROVX) Symbol VPOR VLVI VLVI_H VHVI VHVI_H VLBI VLBI_H VJ2602UV VLVRX VLVR VLVRS VVDDOV VVDDXOV Min 1.5 5.55 18 5.55 5.5 2.7 2.30 1.6 2.575 5.25 Typ 6.0 1.0 19.25 1.0 6.0 1.0 5.7 3.0 2.35 1.85 2.7875 5.675 Max 3.5 6.6 V 20.5 V 6.6 6.2 3.3 2.4 2.1 3.0 6.1 V V V V V V Unit V V Table 11. Static Electrical Characteristics - Resets Ratings Low-state Output Voltage IOUT = 2.0 mA Pull-up Resistor Low-state Input Voltage High-state Input Voltage Reset Release Voltage (VDDX) RESET_A pin Current Limitation Symbol VOL RRPU VIL VIH VRSTRV Min 25 0.7VDDX 5.0 Typ 1.5 7.5 Max 0.8 50 0.3VDDX 10 Unit V kOhm V V V mA Table 12. Static Electrical Characteristics - Window Watchdog Ratings Watchdog Disable Voltage (fixed voltage) Watchdog Enable Voltage (fixed voltage) Symbol VTST VTSTEN Min 7.0 Typ Max 10 5.5 Unit V V Table 13. Static Electrical Characteristics - Voltage Regulator 5V (VDDX) Ratings Normal Mode Output Voltage 1.0 mA < IVDDX + IVDDXinternal < 80 mA; 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation (IVDDX) Stop Mode Output Voltage (IVDDX < 500 µA for TJ ≥ 25 °C; IVDDX < 400 µA for TJ < 25 °C) Stop Mode Output Current Limitation (IVDDX) Symbol VDDXRUN IVDDXLIMRUN VDDXSTOP IVDDXLIMSTOP Min 4.75 80 Typ 5.00 130 5.0 Max 5.25 200 5.5 20 mA V mA Unit V MM912F634 Freescale Semiconductor 14 Electrical Characteristics Table 13. Static Electrical Characteristics - Voltage Regulator 5V (VDDX) (continued) Ratings Line Regulation Normal Mode, IVDDX = 80 mA Stop Mode, IVDDX = 500 µA Load Regulation Normal Mode, 1.0 mA < IVDDX < 80 mA Normal Mode, VSUP = 3.6 V, 1.0 mA < IVDDX < 40 mA Stop Mode, 100 µA < IVDDX < 500 µA External Capacitor External Capacitor ESR Symbol LRXRUN LRXSTOP LDXRUN LDXCRK LDXSTOP CVDDX CVDDX_R Min 1.0 - Static Electrical Characteristics Typ 20 15 - Max 25 200 Unit mV mV 80 200 250 10 10 µF Ohm Table 14. Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD) Ratings Normal Mode Output Voltage 1.0 mA < IVDD 18 V) Hall Supply Capacitor Range External Capacitor ESR Symbol IHSUP RDS(ON) Min 40 16 0.22 Typ 70 17.5 Max 90 10 12 18 500 10 10 V mV µF Ohm Unit mA Ohm VHSUPmax LDHSUP CHSUP CHSUP_R MM912F634 Freescale Semiconductor 15 Electrical Characteristics (continued) Table 16. Static Electrical Characteristics - High Side Drivers - HS Ratings Output Drain-to-Source On resistance TJ = 25 °C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150 °C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150 °C, ILOAD = 30 mA; 5.5V < VSUP < 9.0 V Output Current Limitation (0 V < VOUT < VSUP - 2.0 V) Open Load Current Detection Leakage Current (-0.2 V < VHSx < VS2 + 0.2 V) Current Limitation Flag Threshold (5.5 V < VSUP < 27 V) Symbol RDS(ON) Min 60 VSUP -2 Static Electrical Characteristics Typ 110 5.0 - Max 7.0 10 14 250 7.5 10 - Unit Ohm ILIMHSX IOLHSX ILEAK VTHSC mA mA µA V Table 17. Static Electrical Characteristics - Low Side Drivers - LS Ratings Output Drain-to-Source On resistance TJ = 25 °C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 150 °C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 150 °C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V Output Current Limitation (2.0 V < VOUT < VSUP) Open Load Current Detection Leakage Current (-0.2 V < VOUT < VS1) Active Output Energy Clamp (IOUT = 150 mA) Coil Series Resistance (IOUT = 150 mA) Coil Inductance (IOUT = 150 mA) Current Limitation Flag Threshold (5.5 V < VSUP < 27 V) Symbol RDS(ON) Min – – – 180 40 120 2.0 Typ – – – 275 8.0 400 Max 2.5 4.5 10 380 12 10 45 mA mA µA V Ohm mΗ V Unit Ohm ILIMLSX IOLLSX ILEAK VCLAMP RCOIL RCOIL VTHSC Table 18. Static Electrical Characteristics - LIN Physical Layer Interface - LIN Ratings Current Limitation for Driver dominant state. VBUS = 18 V Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE; Driver OFF; VBUS = 0 V; VBAT = 12 V Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE; Driver OFF; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT Input Leakage Current; GND Disconnected; GNDDEVICE = VSUP; 0 < VBUS < 18 V; VBAT = 12 V Input Leakage Current; VBAT disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V Receiver Input Voltage; Receiver Dominant State Receiver Input Voltage; Receiver Recessive State Receiver Threshold Center (VTH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) Voltage Drop at the serial Diode LIN Pull-up Resistor Bus Wake-up Threshold from Stop or Sleep(14) Bus Dominant Voltage Symbol IBUSLIM IBUS_PAS_DOM IBUS_PAS_REC Min 40 -1.0 Typ 120 Max 200 20 Unit mA mA µA IBUS_NO_GND IBUS_NO_BAT VBUSDOM VBUSREC VBUS_CNT VBUS_HYS DSER_INT RSLAVE VWUP VDOM -1.0 0.6 0.475 0.4 20 4.5 - 0.5 0.7 30 5.0 - 1.0 100 0.4 0.525 0.175 1.0 60 6.0 2.5 mA µA VSUP VSUP VSUP VSUP V kOhm V V Note: 14. Considering drop from VBAT to LIN, at very low VBAT level, the internal logic will detect a dominant as the threshold will not decrease with VSUP. MM912F634 Freescale Semiconductor 16 Electrical Characteristics Table 19. Static Electrical Characteristics - High Voltage Inputs - Lx Ratings Low Detection Threshold 7.0 V ≤ VSUP ≤ 27 V 5.5 V ≤ VSUP ≤ 7 V High Detection Threshold 7.0 V ≤ VSUP ≤ 27 V 5.5 V ≤ VSUP ≤ 7 V Hysteresis 5.5 V ≤ VSUP ≤ 27 V Input Current Lx (-0.2 V < VIN < VS1) Analog Input Impedance Lx Lx Series Resistor Lx Capacitor (optional) (15) Static Electrical Characteristics Symbol VTHL Min 2.2 1.5 2.6 2.0 0.25 -10 9.5 -5.5 - Typ 2.5 2.5 3.0 3.0 0.45 10 100 2.0 7.2 - Max 3.4 4.0 Unit V VTHH V 3.7 4.5 V 1.0 10 1.2 10.5 5.5 5.0 5.0 % % µA MOhm kOhm nF VHYS IIN RLxIN RLx CLx RATIOLx Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0) LXDS (Lx Divider Select) = 0 LXDS (Lx Divider Select) = 1 Analog Input Divider Ratio Accuracy Analog Inputs Channel Ratio - Mismatch LXDS (Lx Divider Select) = 0 LXDS (Lx Divider Select) = 1 RATIOLX LxMATCH Note: 15. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" are guaranteed without the optional capacitor. Table 20. Static Electrical Characteristics - General Purpose I/O - PTB[0…2] Ratings Input high voltage Input low voltage Input hysteresis Input high voltage (VS1 = 3.7 V) Input low voltage (VS1 = 3.7 V) Input hysteresis (VS1 = 3.7 V) Input leakage current (pins in high-impedance input mode) (VIN = VDDX or VSSX) Output high voltage (pins in output mode) Full drive IOH = –10 mA Output low voltage (pins in output mode) Full drive IOL = +10 mA Internal pull-up resistance (VIH min > Input voltage > VIL max) Input capacitance Clamp Voltage when selected as analog input Analog Input impedance = 10 kOhm max, Capacitance = 12 pF Analog Input Capacitance = 12 pF Maximum current all PTB combined (VDDX capability!) Output Drive strength at 10 MHz Symbol VIH VIL VHYS VIH3.7 VIL3.7 VHYS3.7 IIN VOH VOL RPUL CIN VCL_AIN RAIN CAIN IBMAX COUT Min 0.7VDDX VSS-0.3 2.1 VSS-0.3 100 -1.0 VDDX-0.8 26.25 VDD -15 Typ 140 200 37.5 6.0 12 Max VDDX+0.3 0.35VDDX VDDX+0.3 1.4 300 1.0 0.8 48.75 10 15 100 Unit V V mV V V mV µA V V kOhm pF V kOhm pF mA pF MM912F634 Freescale Semiconductor 17 Electrical Characteristics Table 21. Static Electrical Characteristics - Analog Digital Converter - ADC(16) Ratings ADC2p5 Reference Voltage 5.5 V < VSUP < 27 V ADC2p5 Reference Stop Mode Output Voltage Line Regulation, Normal Mode External Capacitor External Capacitor ESR Scale Factor Error Differential Linearity Error Integral Linearity Error Zero Offset Error Quantization Error Total Error with offset compensation Bandgap measurement Channel (CH14) Valid Result Range (including ±7.0% bg1p25 sleep accuracy + high-impedance measurement error of ±5.0% at fADC)(17) Note: 16. No external load allowed on the ADC2p5 pin. 17. Reduced ADC frequency will lower measurement error. Symbol VADC2p5RUN VADC2p5STO P Static Electrical Characteristics Min 2,45 0.1 -1 -1.5 -1.5 -2.0 -0.5 -5.0 1.1 Typ 2.5 10 1.25 Max 2,55 100 12.5 1.0 10 1 1.5 1.5 2.0 0.5 5.0 1.4 Unit V mV mV µF Ohm LSB LSB LSB LSB LSB LSB V LRRUNA CADC2p5 CVDD_R ESCALE EDNL EINL EOFF EQ TE ADCH14 Table 22. Static Electrical Characteristics - Current Sense Module - ISENSE Ratings Gain CSGS (Current Sense Gain Select) = 000 CSGS (Current Sense Gain Select) = 001 CSGS (Current Sense Gain Select) = 010 CSGS (Current Sense Gain Select) = 011 CSGS (Current Sense Gain Select) = 100 CSGS (Current Sense Gain Select) = 101 CSGS (Current Sense Gain Select) = 110 CSGS (Current Sense Gain Select) = 111 Gain Accuracy Offset Resolution(18) ISENSEH, ISENSEL Input Common Mode Voltage Range Current Sense Module - Normal Mode Current Consumption Adder (CSE = 1) Note: 18. RES = 2.44 mV/(GAIN*RSHUNT) RES VIN IISENSE Symbol G -3.0 -1.5 -0.2 7.0 9.0 10 12 14 18 24 36 51 600 3.0 1.5 3.0 % % mA/LSB V µA Min Typ Max Unit MM912F634 Freescale Semiconductor 18 Electrical Characteristics Table 23. Static Electrical Characteristics - Temperature Sensor - TSENSE Ratings Internal Chip Temperature Sense Gain (19) Static Electrical Characteristics Symbol TSG TSErr T0.15V T1.984V (19) Min –5.0 -55 145 Typ 9.17 -50 150 Max 5.0 -45 155 Unit mV/k °C °C °C Internal Chip Temperature Sense Error at the end of conversion(19) Temperature represented by a ADCIN Voltage of 0.150 V Note: 19. Guaranteed by design and characterization. Temperature represented by a ADCIN Voltage of 1.984 V(19) Table 24. Static Electrical Characteristics - Supply Voltage Sense - VSENSE and VS1SENSE Ratings VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / ADCIN) 5.5 V < VSUP < 27 V VSENSE error - whole path (VSENSE pin to Digital value) VS1SENSE Input Divider Ratio (RATIOVS1SENSE = VVS1SENSE / ADCIN) 5.5 V < VSUP < 27 V VS1SENSE error - whole path (VS1 pin to Digital value) VSENSE Series Resistor VSENSE Capacitor (optional)(20) Symbol RATIOVSENS E Min Typ 10.8 Max Unit ERVSENSE RATIOVS1SE NSE - 10.8 5.0 % ERVS1SENSE RVSENSE CVSENSE 9.5 - 10 100 5.0 10.5 - % kOhm nF Note: 20. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" is guaranteed without the optional capacitor. MM912F634 Freescale Semiconductor 19 Electrical Characteristics Static Electrical Characteristics 3.5.2 3.5.2.1 Static Electrical Characteristics MCU Die I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Table 25. 5.0 V I/O Characteristics for PTA, RESET and BKGD Pins Ratings Input high voltage Input high voltage Input low voltage Input low voltage Input hysteresis Input leakage current (pins in high-impedance input mode) Vin = VDDX or VSSX Output high voltage (pins in output mode) Partial Drive IOH = -2.0 mA Output high voltage (pins in output mode) Full Drive IOH = -10 mA Output low voltage (pins in output mode) Partial drive IOL = +2.0 mA Output low voltage (pins in output mode) Full Drive IOL = +10 mA Internal pull-up resistance (VIHmin > input voltage > VILmax) Internal pull-down resistance (VIHmin > input voltage > VILmax) Input capacitance Injection current Single pin limit Total device Limit, sum of all injected currents (21) Symbol V IH Min 0.65*VDD VSS - 0.3 -1.0 VDD – 0.8 VDD – 0.8 25 25 -2.5 -25 Typ 250 6.0 - Max VDD + 0.3 0.35*VDD 1.0 0.8 0.8 50 50 2.5 25 Unit V V V V mV μA V V V V kΩ kΩ pF mA VIH VIL VIL VHYS I V V IN OH OH VOL VOL RPUL RPDH Cin IICS IICP Note: 21. Refer to Section 3.8, “ESD Protection and Latch-up Immunity"” for more details. MM912F634 Freescale Semiconductor 20 Electrical Characteristics Dynamic Electrical Characteristics 3.6 Dynamic Electrical Characteristics Dynamic electrical characteristics noted under conditions 5.5V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 105 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted. 3.6.1 Dynamic Electrical Characteristics Analog Die Table 26. Dynamic Electrical Characteristics - Modes of Operation Ratings VDD Short Timeout Analog Base Clock Reset Delay Symbol tVTO fBASE tRST Min 110 140 Typ 150 100 200 Max 205 280 Unit ms kHz µs Table 27. Dynamic Electrical Characteristics - Power Supply Ratings Glitch Filter Low Battery Warning (LBI)(22) (22) Symbol tLB tLV tHV Min - Typ 2.0 2.0 2.0 Max - Unit µs µs µs Glitch Filter Low Voltage Warning (LVI)(22) Glitch Filter High Voltage Warning (HVI) Note: 22. Guaranteed by design. Table 28. Dynamic Electrical Characteristics - Die to Die Interface - D2D Ratings Operating Frequency (D2DCLK, D2D[0:3]) Note: 23. fBUSMAX frequency ratings differ by device and is specified in Table 1 Symbol fD2D Min fADC(MIN) Typ Max fBUSMAX (23) Unit MHz Table 29. Dynamic Electrical Characteristics - Resets Ratings Reset Deglitch Filter Time Reset Low Level Duration Symbol tRSTDF tRSTLOW Min 1.2 140 Typ 2.0 200 Max 3.0 280 Unit µs µs Table 30. Dynamic Electrical Characteristics - Wake-up / Cyclic Sense Ratings Lx Wake-up Filter Time Cyclic Sense / Forced Wake-up Timing Accuracy - not trimmed Cyclic Sense / Forced Wake-up Timing Accuracy - trimmed(24) Time between HSx on and Lx sense during cyclic sense HSx ON duration during Cyclic Sense HSx ON duration during Cyclic Sense - trimmed(24) Note: 24. Trimming parameters are not available in Sleep mode. Symbol tWUF CSAC CSACT tS tHSON tHSONT Min -35 -5.0 140 180 Typ 20 200 200 35 5.0 280 220 Max Unit μs % % μs μs same as tHSON / tHSONT MM912F634 Freescale Semiconductor 21 Electrical Characteristics Table 31. Dynamic Electrical Characteristics - Window Watchdog Ratings Initial Non-window Watchdog Timeout Watchdog Timeout Accuracy - not trimmed Watchdog Timeout Accuracy - trimmed Symbol tIWDTO WDAC WDACT Min 110 -35 -5.0 Dynamic Electrical Characteristics Typ 150 - Max 190 35 5.0 Unit ms % % Table 32. Dynamic Electrical Characteristics - High Side Drivers - HS Ratings High Side Operating Frequency Load Condition: CLOAD ≤ 2.2 nF; RLOAD ≥ 500 Ω Note: 25. Guaranteed by design. (25) Symbol fHS Min - Typ - Max 50 Unit kHz Table 33. Dynamic Electrical Characteristics - Low Side Drivers - LS Ratings Low Side Operating Frequency Symbol fLS Min Typ Max 10 Unit kHz Table 34. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN Ratings Bus Wake-up Deglitcher (Sleep and Stop Mode) Fast Bit Rate (Programming Mode) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)(26) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR Symbol tPROPWL BRFAST tREC_PD tREC_SYM Min 60 -2.0 Typ 80 Max 100 100 6.0 2.0 Unit µs kBit/s µs µs LIN Driver - 20.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 kΩ / 6,8 nF;660 Ω / 10 nF;500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 6. Duty Cycle 1: THREC(MAX) = 0.744 x VSUP THDOM(MAX) = 0.581 x VSUP 7.0 V ≤ VSUP ≤ 18 V; tBit = 50 µs; D1 = tBUS_REC(MIN)/(2 x tBit) Duty Cycle 2: THREC(MIN) = 0.422 x VSUP THDOM(MIN) = 0.284 x VSUP 7.6 V ≤ VSUP ≤ 18 V; tBIT = 50 µs D2 = tBUS_REC(MAX)/(2 x tBIT) D1 0.396 - D2 - - 0.581 LIN Driver - 10.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 kΩ / 6,8 nF;660 Ω / 10 nF;500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 7. Duty Cycle 3: THREC(MAX) = 0.778 x VSUP THDOM(MAX) = 0.616 x VSUP 7.0 V ≤ VSUP ≤ 18 V; tBIT = 96 µs D3 = TBUS_REC(MIN)/(2 x tBIT) Duty Cycle 4: THREC(MIN) = 0.389 x VSUP THDOM(MIN) = 0.251 x VSUP 7.6 V ≤ VSUP ≤ 18 V; tBIT = 96 µs D4 = tBUS_REC(MAX)/(2 x tBIT) D3 0.417 - D4 - - 0.590 MM912F634 Freescale Semiconductor 22 Electrical Characteristics Dynamic Electrical Characteristics Table 34. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN (continued) Ratings Transmitter Symmetry tTRAN_SYM < MAX(tTRAN_SYM60%, tTRAN_SYM40%) tran_sym60% = ttran_pdf60% - ttran_pdr60% tran_sym40% = ttran_pdf40% - ttran_pdr40% Symbol tTRAN_SYM Min -7.25 Typ 0 Max 7.25 Unit µs Note: 26. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 8. 27. LIN Transmitter Timing, (VSUP from 7.0 to 18 V) - See Figure 9 VSU VSU TXD LIN RXD CO GND RO Note: Rn and Cn: 1.0kΩ/1.0nF, 660Ω/6.8 Figure 5. Test Circuit for Timing Measurements Figure 6. LIN Timing Measurements for Normal Baud Rate MM912F634 Freescale Semiconductor 23 Electrical Characteristics Dynamic Electrical Characteristics Figure 7. LIN Timing Measurements for Slow Baud Rate Figure 8. LIN Receiver Timing TX BUS 60% 40% ttran_pdf60% ttran_pdf40% ttran_pdr40% ttran_pdr60% Figure 9. LIN Transmitter Timing MM912F634 Freescale Semiconductor 24 Electrical Characteristics Table 35. Dynamic Electrical Characteristics - General Purpose I/O - PTB[0…2] Ratings GPIO Digital Frequency (28) Dynamic Electrical Characteristics Symbol fPTB tPDR tRISE tPDF tFALL Min - Typ - Max 10 20 17.5 20 17.5 Unit MHz ns ns ns ns Propagation Delay - Rising Edge(28), (29) Rise Time - Rising Edge (28) Propagation Delay - Falling Edge(28) Rise Time - Falling Edge(28) Note: 28. Guaranteed by design. 29. Load PTBx = 100 pF. Table 36. Dynamic Electrical Characteristics - Analog Digital Converter - ADC Ratings ADC Operating Frequency(30) Conversion Time (from ACCR write to CC Flag) Sample Frequency Channel 14 (Bandgap)(30) Note: 30. Guaranteed by design. (30) Symbol fADC tCONV fCH14 Min 1.6 - Typ 2.0 26 - Max 2.4 2.5 Unit MHz clk kHz 3.6.2 3.6.2.1 Dynamic Electrical Characteristics MCU Die NVM Timing The time base for all NVM program or erase operations is derived from the bus block. A minimum bus frequency fNVMBUS is required for performing program or erase operations. The NVM module do not has any means to monitor the frequency and will not prevent a program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency, a full program, or erase transition is not assured. The Flash program and erase operations are timed using a clock derived from the bus clock using the FCLKDIV and register. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table 37 are calculated for maximum fNVMOP and maximum fBUS. The maximum times are calculated for minimum fNVMOP and a fBUS of 2.0 MHz. 3.6.2.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP, and can be calculated according to the following formula. t swpgm 1 1= 9 ⋅ ------------------------ + 25 ⋅ ---------f f NVMOP bus MM912F634 Freescale Semiconductor 25 Electrical Characteristics Dynamic Electrical Characteristics 3.6.2.1.2 Burst Programming This applies only to the Flash, where up to 64 words in a row can be programmed consecutively, using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: t bwpgm 1 1= 4 ⋅ ------------------------ + 9 ⋅ ---------f f NVMOP bus The time to program a whole row is: t brpgm =t swpgm + 63 ⋅ t bwpgm Burst programming is more than 2 times faster than single word programming. 3.6.2.1.3 Sector Erase NOTE The sector erase cycle is divided into 16 individual erase pulses to achieve faster system response during the erase flow. The given erase time (tERA) specifies the time considering consecutive pulses. Erasing a 512-byte Flash sector takes: t 1 ≈ 4000 ⋅ -----------------------f NVMOP era The setup time can be ignored for this operation. 3.6.2.1.4 Mass Erase 1 ≈ 20000 Þ -----------------------f NVMOP Erasing a NVM block takes: t mass The setup time can be ignored for this operation. MM912F634 Freescale Semiconductor 26 Electrical Characteristics Dynamic Electrical Characteristics 3.6.2.1.5 Blank Check The time it takes to perform a blank check on the Flash is dependant on the location of the first non-blank word, starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ª location Þ t cyc + 10 Þ t cyc Table 37. NVM Timing Characteristics Rating Bus frequency for programming or erase operations Operating frequency Single word programming time Flash burst programming consecutive word Flash burst programming time for 64 words(34) Sector erase time(32) Mass erase time Blank check time Flash per block Symbol fNVMBUS fNVMOP tSWPGM tBWPGM tBRPGM tERA tMASS tCHECK Min 1.0 150 46(31) 20.4(31) 1331.2(31) 20(33) 100(35) 11(34) Typ Max 200 74.5(31) 31(32) 2027.5(32) 26.7(32) 133(32) 65546(35) Unit MHz kHz μs μs μs ms ms tCYC Note: 31. Minimum programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fBUS. 32. The sector erase cycle is divided into 16 individual erase pulses to achieve faster system response during the erase flow. The given erase time (tERA) specifies the time considering consecutive pulses. 33. Minimum erase times are achieved under maximum NVM operating frequency, fNVMOP. 34. Minimum time, if first word in the array is not blank. 35. Maximum time to complete check on an erased block. MM912F634 Freescale Semiconductor 27 Electrical Characteristics Dynamic Electrical Characteristics 3.6.2.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress tests during qualification, constant process monitors, and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table 38. NVM Reliability Characteristics Rating Data retention after 10,000 program/erase cycles for TJAVG ≤ 85 °C(36), Data retention with VLVRX the MM912F634 analog die enters in Normal mode. To avoid short-circuit conditions being present for a long time, a tVTO timeout is implemented. Once VDD < VLVR or VDDX < VLVRX with VS1 > (VLVRI+ VLVR _H) for more than tVTO, the MM912F634 analog die will transit directly to Sleep mode. The Reset Status Register (RSR) will indicate the source of the reset by individual flags. • • • • • • POR - Power On Reset LVR - Low Voltage Reset VDD LVRX - Low Voltage Reset VDDX WDR - Watchdog Reset EXR - External Reset WUR - Wake-up Sleep Reset See also Section 4.7, “Resets". 4.3.3 Normal Mode In Normal mode, all MM912F634 analog die user functions are active and can be controlled by the D2D Interface. Both regulators (VDD and VDDX) are active and operate with full current capability. Once entered in Normal mode, the Watchdog will operate as a simple non-window watchdog with an initial timeout (tIWDTO) to be reset via the D2D Interface. After the initial reset, the watchdog will operate in standard window mode. See Section 4.9, “Window Watchdog" for details. 4.3.4 Stop Mode NOTE To avoid any pending analog die interrupts prevent the MCU from entering MCU stop resulting in unexpected system behavior, the analog die IRQ sources should be disabled and the corresponding flags be cleared before entering stop. The Stop mode will allow reduced current consumption with fast startup time. In this mode, both voltage regulators (VDD and VDDX) are active, with limited current drive capability. In this condition, the MCU is supposed to operate in Low Power mode (STOP or WAIT). The device can enter in Stop mode by configuring the Mode Control Register (MCR) via the D2D Interface. The MCU has to enter a Low Power mode immediately afterwards executing the STOP or WAIT instruction. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. While in Stop mode, the MM912F634 analog die will wake up on the following sources: • • • • Lx - Wake-up (maskable with selectable cyclic sense) Forced Wake-up (configurable timeout) LIN Wake-up D2D Wake-up (special command) After Wake-up from the sources listed above, the device will transit to Normal mode. Reset will wake up the device directly to Reset mode. See Section 4.8, “Wake-up / Cyclic Sense" for details. MM912F634 Freescale Semiconductor 56 Functional Description and Application Information Modes of Operation 4.3.5 Sleep Mode The Sleep mode will allow very low current consumption. In this mode, both voltage regulators (VDD and VDDX) are inactive. The device can enter into Sleep mode by configuring the Mode Control Register (MCR) via the D2D- Interface. During Sleep mode, all unused internal blocks are deactivated to allow the lowest possible consumption. Power consumption will decrease further if the Cyclic Sense or Forced Wake-up feature are disabled. While in Sleep mode, the MM912F634 analog die will wake up on the following sources: • • • Lx - Wake-up (maskable with selectable cyclic sense) Forced Wake-up (configurable timeout) LIN Wake-up After Wake-up from the sources listed above or a reset condition, the device will transit to Reset mode. See Section 4.8, “Wake-up / Cyclic Sense" for details. 4.3.6 Analog Die Functionality by Operation Mode Table 71. Operation Mode Overview Function VDD/VDDX HSUP LSx HSx ADC D2D Lx PTBx LIN Watchdog VSENSE CSENSE Cyclic Sense Note: 57. If configured. 58. Special init through non window watchdog. OFF Reset full Normal full full full full full full full full full full(58) full full not active Stop stop OFF OFF Cyclic Sense(57) OFF functional Wake-up(57) OFF Wake-up(57) OFF OFF OFF Cyclic Sense(57) Sleep OFF OFF OFF Cyclic Sense(57) OFF OFF Wake-up(57) OFF Wake-up(57) OFF OFF OFF Cyclic Sense(57) MM912F634 Freescale Semiconductor 57 Functional Description and Application Information Modes of Operation 4.3.7 4.3.7.1 Register Definition Mode Control Register (MCR) Table 72. Mode Control Register (MCR) Offset(59) 0x16 7 6 5 4 3 2 Access: User read/write 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE 0 Note: 59. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 73. MCR - Register Field Descriptions Field 1-0 MODE Description Mode Select - These bits will issue a transition from to the selected Operating Mode. 00 - Normal Mode. Only with effect in Stop Mode. Will issue Wake Up and transition to Normal Mode. 01 - Stop Mode. Will initiate transition to Stop Mode.(60) 10 - Sleep Mode. Will initiate transition to Sleep Mode. 11 - Normal Mode. Note: 60. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. MM912F634 Freescale Semiconductor 58 Functional Description and Application Information Power Supply 4.4 Power Supply The MM912F634 analog die supplies VDD (2.5 V), VDDX (5.0 V), and HSUP, based on the supply voltage applied to the VS1 pin. VDD is cascaded of the VDDX regulator. To separate the High Side outputs from the main power supply, the VS2 pin does only power the High Side drivers. Both supply pins have to be externally protected against reverse battery conditions. To supply external Hall Effect Sensors, the HSUP pin will supply a switchable regulated supply. See Section 4.10, “Hall Sensor Supply Output - HSUP". A reverse battery protected input (VSENSE) is implemented to measure the Battery Voltage directly. A serial resistor (RVSENSE) is required on this pin. See Section 4.22, “Supply Voltage Sense - VSENSE". In addition, the VS1 supply can be routed to the ADC (VS1SENSE) to measure the VS1 pin voltage directly. See Section 4.23, “Internal Supply Voltage Sense - VS1SENSE". To have an independent ADC verification, the internal sleep mode bandgap voltage can be routed to the ADC (BANDGAP). As this node is independent from the ADC reference, any out of range result would indicate malfunctioning ADC or Bandgap reference. See Section 4.24, “Internal Bandgap Reference Voltage Sense - BANDGAP". To stabilize the internal ADC reference voltage for higher precision measurements, the current limited ADC2p5 pin needs to be connected to an external filter capacitor (CADC2p5). It is not recommended to connect additional loads to this pin. See Section 4.19, “Analog Digital Converter - ADC". The following safety features are implemented: • • • • • • • • LBI - Low Battery Interrupt, internally measured at VSENSE LVI - Low Voltage Interrupt, internally measured at VS1 HVI - High Voltage Interrupt, internally measured at VS2 VROVI - Voltage Regulator Over-voltage Interrupt internally measured at VDD and VDDX LVR - Low Voltage Reset, internally measured at VDD LVRX - Low Voltage Reset, internally measured at VDDX HTI - High Temperature Interrupt measured between the VDD and VDDX regulators Over-temperature Shutdown measured between the VDD and VDDX regulators MM912F634 Freescale Semiconductor 59 Functional Description and Application Information Power Supply VSENSE LBI VS2 HVI HS1 HS2 VS1 HS1 & HS2 LVI ÷ ADC bg1p25sleep HSUP CHSUP HSUP (18V) Regulator VDDX (5V) Regulator VDDXINTERNAL VROV LVRX VDDX CVDDX ADC2p5 CADC ADC 2.5V Reference VDD (2.5V) Regulator VDD VDDINTERNAL LVR CVDD Figure 17. MM912F634 Power Supply 4.4.1 Voltage Regulators VDD (2.5 V) & VDDX (5.0 V) To supply the MCU die and minor additional loads two cascaded voltage regulators have been implemented, VDDX (5.0 V) and VDD (2.5 V). External capacitors (CVDD) and (CVDDX) are required for proper regulation. 4.4.2 Power Up Behavior / Power Down Behavior To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 18 shows a standard power up and power down sequence. MM912F634 Freescale Semiconductor 60 Functional Description and Application Information Power Supply MCU_POR MCU_POR RESET_A Normal Operating Range (not to scale) VLBI / VLVI VROVX 5V VLVRX VROX VLVR VPOR_A VPOR_MCU VSUP 1 4 5 2 3 6 VDDX VDD Figure 18. Power Up / Down Sequence To avoid any critical behavior, it is essential to have the MCU Power On Reset (POR) active when the analog die reset (RESET_A) is not fully active. As the RESET_A circuity is supplied by VDDX, VDD needs to be below the POR threshold when VDDX is to low to guarantee RESET_A active (3;6). This is achieved with the following implementation. Power Up: • • • • The VDD regulator is enabled after VDDX has reached the VLVRX threshold (1). Once VDD reaches VLRV, the RESET_A is released (2). Once VDDX has reached the VLVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well. The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. Power Down: MM912F634 Freescale Semiconductor 61 Functional Description and Application Information Power Supply 4.4.3 Power Up Behavior / Power Down Behavior - I64 NOTE The behavior explained is essential for the MC9S12I64 MCU die used, as this MCU does have an internal regulator stage, but the LVR function is only active in normal mode MC9S12I64. The shutdown behavior should be considered when sizing the external capacitors CVDD and CVDDX for extended low voltage operation. To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 19 shows a standard power up and power down sequence. MCU_POR RESET_A Normal Operating Range (not to scale) VLBI / VLVI VROVX 5V VLVRX / VLVR_MCU VROX VLVR VPOR_A VPOR_MCU 1 4 5 2 3 6 VSUP VDDX VDD Figure 19. Power Up / Down Sequence To avoid any critical behavior, it is essential to have the MCU Power On Reset (POR) active when the analog die reset (RESET_A) is not fully active. As the RESET_A circuity is supplied by VDDX, VDD needs to be below the POR threshold when VDDX is to low to guarantee RESET_A active (3;6). This is achieved with the following implementation. Power Up: • • • • • The VDD regulator is enabled after VDDX has reached the VLVRX threshold (1). Once VDD reaches VLRV, the RESET_A is released (2). The MCU is also protected by the MCU_LVR. Once VDDX has reached the VLVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well. The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. Power Down: MCU_POR MCU_LVR MCU_LVR MM912F634 Freescale Semiconductor 62 Functional Description and Application Information Power Supply 4.4.4 4.4.4.1 Register Definition Voltage Control Register (VCR) Table 74. Voltage Control Register (VCR) Offset(61) R W Reset 0 0 0 0x04 7 6 5 4 3 2 Access: User read/write 1 0 0 0 0 VROVIE 0 HTIE 0 HVIE 0 LVIE 0 LBIE 0 Note: 61. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 75. VCR - Register Field Descriptions Field 4 VROVIE 3 HTIE 2 HVIE 1 LVIE 0 LBIE Description Voltage Regulator Over-voltage Interrupt Enable — Enables the interrupt for the Regulator Over-voltage Condition. 0 - Voltage Regulator Over-voltage Interrupt is disabled 1 - Voltage Regulator Over-voltage Interrupt is enabled High Temperature Interrupt Enable — Enables the interrupt for the Voltage Regulator (VDD/VDDX) Temperature Warning. 0 - High Temperature Interrupt is disabled 1 - High Temperature Interrupt is enabled High Voltage Interrupt Enable — Enables the interrupt for the VS2 - High Voltage Warning. 0 - High Voltage Interrupt is disabled 1 - High Voltage Interrupt is enabled Low Voltage Interrupt Enable — Enables the interrupt for the VS1 - Low Voltage Warning. 0 - Low Voltage Interrupt is disabled 1 - Low Voltage Interrupt is enabled Low Battery Interrupt Enable — Enables the interrupt for the VSENSE - Low Battery Voltage Warning. 0 - Low Battery Interrupt is disabled 1 - Low Battery Interrupt is enabled MM912F634 Freescale Semiconductor 63 Functional Description and Application Information Power Supply 4.4.4.2 Voltage Status Register (VSR) Table 76. Voltage Status Register (VSR) Offset(62) 0x05 7 6 5 4 3 2 1 Access: User read 0 R W Reset 0 0 0 0 0 0 VROVC 0 HTC 0 HVC 0 LVC 0 LBC 0 Note: 62. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 77. VSR - Register Field Descriptions Field 4 VROVC Description Voltage Regulator Over-voltage Condition - This status bit indicates an over-voltage warning is present for at least one of the main voltage regulators (VDD or VDDX). Reading the register will clear the VROVI flag if present. See Section 4.6, “Interrupts" for details. Note: This feature requires the trimming of Section 4.25.1.2.3, “Trimming Register 2 (CTR2)" to be done to be effective. Untrimmed devices may issue the VROVC condition including the LS turn off at normal operation! 0 - No Voltage Regulator Over-voltage Condition present. 1 - Voltage Regulator Over-voltage Condition present. High Temperature Condition - This status bit indicates a high temperature warning is present for the Voltage regulators (VDD/VDDX). Reading the register will clear the HTI flag if present. See Section 4.6, “Interrupts" for details. 0 - No High Temperature Condition present. 1 - High Temperature Condition present. High Voltage Condition - This status bit indicates a high voltage warning for VS2 is present. Reading the register will clear the HVI flag if present. See Section 4.6, “Interrupts" for details. 0 - No High Voltage Condition present. 1 - High Voltage Condition present. Low Voltage Condition - This status bit indicates a low voltage warning for VS1 is present. Reading the register will clear the LVI flag if present. See Section 4.6, “Interrupts" for details. 0 - No Low Voltage Condition present. 1 - Low Voltage Condition present. Low Battery Condition - This status bit indicates a low voltage warning for VSENSE is present. Reading the register will clear the LBI flag if present. See Section 4.6, “Interrupts" for details. 0 - No Low Battery Condition present. 1 - Low Battery Condition present. 3 HTC 2 HVC 1 LVC 0 LBC MM912F634 Freescale Semiconductor 64 Functional Description and Application Information Die to Die Interface - Target 4.5 Die to Die Interface - Target The D2D Interface is the bus interface to the Microcontroller. Access to the MM912F634 analog die is controlled by the D2D Interface module. This section describes the functionality of the die-to-die target block (D2D). 4.5.1 Overview The D2D is the target for a data transfer from the target to the initiator (MCU). The initiator provides a set of configuration registers and two memory mapped 256 Byte address windows. When writing to a window, a transaction is initiated sending a write command, followed by an 8-bit address, and the data byte or word is received from the initiator. When reading from a window, a transaction is received with the read command, followed by an 8-bit address. The target then responds with the data. The basic idea is that a peripheral located on the MM912F634 analog die, can be addressed like an on-chip peripheral. Features: • • • • • • • software transparent register access to peripherals on the MM912F634 analog die 256 Byte address window supports blocking read or write, as well as non-blocking write transactions 4 bit physical bus width automatic synchronization of the target when initiator starts driving the interface clock generates transaction and error status as well as EOT acknowledge providing single interrupt interface to D2D Initiator 4.5.2 Low Power Mode Operation The D2D module is disabled in SLEEP mode. In Stop mode, the D2DINT signal is used to wake-up a powered down MCU. As the MCU could wake up without the MM912F634 analog die, a special command will be recognized as a wake-up event during Stop mode. See Section 4.3, “Modes of Operation". 4.5.2.1 Normal Mode / Stop Mode NOTE The maximum allowed clock speed of the interface is limited to fD2D. While in Normal or Stop mode, D2DCLK acts as input only with pull present. D2D[3:0] operates as an input/output with pull-down always present. D2DINT acts as output only. 4.5.2.2 Sleep Mode While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption. MM912F634 Freescale Semiconductor 65 Functional Description and Application Information Interrupts 4.6 Interrupts Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. While in Stop mode, the interrupt signal is used to signal Wake-up events. The interrupts are signaled by an active high level of the D2DINT pin, which will remain high until the interrupt is acknowledged via the D2D-Interface. Interrupts are only asserted while in Normal mode. 4.6.1 Interrupt Source Identification Once an Interrupt is signalized, there are two options to identify the corresponding source(s). 4.6.1.1 Interrupt Source Mirror NOTE The VSI - Voltage Status Interrupt combines the five status flags for the Low Battery Interrupt, Low Voltage Interrupt, High Voltage Interrupt, Voltage Regulator Over-voltage Interrupt, and the Voltage Regulator High Temperature Interrupt. The specific source can be identified by reading the Voltage Status Register - VSR. All Interrupt sources in MM912F634 analog die are mirrored to a special Interrupt Source Register (ISR). This register is read only and will indicate all currently pending Interrupts. Reading this register will not acknowledge any interrupt. An additional D2D access is necessary to serve the specific module. 4.6.1.1.1 Interrupt Source Register (ISR) Table 78. Interrupt Source Register (ISR) Offset(63) 0x00 (0x00 and 0x01 for 8Bit access) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Access: User read 1 0 R W 0 0 HOT LSOT HSOT LINOT SCI RX TX ERR TOV CH3 CH2 CH1 CH0 VSI Note: 63. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912F634 Freescale Semiconductor 66 Functional Description and Application Information Table 79. ISR - Register Field Descriptions Field 0 - VSI Description VSI - Voltage Status Interrupt combining the following sources: • Low Battery Interrupt • Low Voltage Interrupt • High Voltage Interrupt • Voltage Regulator Over-voltage Interrupt • Voltage Regulator High Temperature Interrupt CH0 - TIM Channel 0 Interrupt CH1 - TIM Channel 1 Interrupt CH2 - TIM Channel 2 Interrupt CH3 - TIM Channel 3 Interrupt TOV - Timer Overflow Interrupt ERR - SCI Error Interrupt TX - SCI Transmit Interrupt RX - SCI Receive Interrupt SCI - ADC Sequence Complete Interrupt LINOT - LIN Driver Over-temperature Interrupt HSOT - High Side Over-temperature Interrupt LSOT - Low Side Over-temperature Interrupt HOT - HSUP Over-temperature Interrupt Interrupts 1 - CH0 2 - CH1 3 - CH2 4 - CH3 5 - TOV 6 - ERR 7 - TX 8 - RX 9 - SCI 10 - LINOT 11 - HSOT 12 - LSOT 13 - HOT 4.6.1.2 Interrupt Vector Emulation by Priority To allow a vector based interrupt handling by the MCU, the number of the highest prioritized interrupt pending is returned in the Interrupt Vector Register. To allow an offset based vector table, the result is pre-shifted (multiple of 2). Reading this register will not acknowledge an interrupt. An additional D2D access is necessary to serve the specific module. 4.6.1.2.1 Interrupt Vector Register (IVR) Table 80. Interrupt Vector Register (IVR) Offset(64) 0x02 7 6 5 4 3 2 1 Access: User read 0 R W 0 0 IRQ Note: 64. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 81. IVR - Register Field Descriptions Field 5:0 IRQ Description Represents the highest prioritized interrupt pending. See Table 82 In case no interrupt is pending, the result will be 0. The following table is listing all MM912F634 analog die interrupt sources with the corresponding priority. MM912F634 Freescale Semiconductor 67 Functional Description and Application Information Table 82. Interrupt Source Priority Interrupt Source no interrupt pending or wake-up from Stop mode LVI - Low Voltage Interrupt HTI - Voltage Regulator High Temperature Interrupt LBI - Low Battery Interrupt CH0 - TIM Channel 0 Interrupt CH1 - TIM Channel 1 Interrupt CH2 - TIM Channel 2 Interrupt CH3 - TIM Channel 3 Interrupt TOV - Timer Overflow Interrupt ERR - SCI Error Interrupt TX - SCI Transmit Interrupt RX - SCI Receive Interrupt SCI - ADC Sequence Complete Interrupt LINOT - LIN Driver Over-temperature Interrupt HSOT - High Side Over-temperature Interrupt LSOT - Low Side Over-temperature Interrupt HOT - HSUP Over-temperature Interrupt HVI - High Voltage Interrupt VROVI - Voltage Regulator Over-voltage Interrupt IRQ 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 Priority 1 (highest) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 (lowest) Interrupts 4.6.2 4.6.2.1 Interrupt Sources Voltage Status Interrupt (VSI) The Voltage Status Interrupt - VSI combines the five interrupt sources of the Voltage Status Register. It is only available in the Interrupt Source Register (ISR). Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.2 Low Voltage Interrupt (LVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.3 Voltage Regulator High Temperature Interrupt (HTI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.4 Low Battery Interrupt (LBI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.6.2.5 TIM Channel 0 Interrupt (CH0) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". MM912F634 Freescale Semiconductor 68 Functional Description and Application Information Interrupts 4.6.2.6 TIM Channel 1 Interrupt (CH1) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.7 TIM Channel 2 Interrupt (CH2) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.8 TIM Channel 3 Interrupt (CH3) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.9 TIM Timer Overflow Interrupt (TOV) See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". 4.6.2.10 SCI Error Interrupt (ERR) See Section 4.15, “Serial Communication Interface (S08SCIV4)". 4.6.2.11 SCI Transmit Interrupt (TX) See Section 4.15, “Serial Communication Interface (S08SCIV4)". 4.6.2.12 SCI Receive Interrupt (RX) See Section 4.15, “Serial Communication Interface (S08SCIV4)". 4.6.2.13 LIN Driver Over-temperature Interrupt (LINOT) Acknowledge the interrupt by reading the LIN Register - LINR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.14, “LIN Physical Layer Interface - LIN" for details on the LIN Register including masking information. 4.6.2.14 High Side Over-temperature Interrupt (HSOT) Acknowledge the interrupt by reading the High Side Status Register - HSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.11, “High Side Drivers - HS" for details on the High Side Status Register including masking information. 4.6.2.15 Low Side Over-temperature Interrupt (LSOT) Acknowledge the interrupt by reading the Low Side Status Register - LSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.12, “Low Side Drivers - LSx" for details on the Low Side Status Register including masking information. 4.6.2.16 HSUP Over-temperature Interrupt (HOT) Acknowledge the interrupt by reading the Hall Supply Register - HSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.10, “Hall Sensor Supply Output - HSUP" for details on the Hall Supply Register including masking information. 4.6.2.17 High Voltage Interrupt (HVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. MM912F634 Freescale Semiconductor 69 Functional Description and Application Information Resets 4.6.2.18 Voltage Regulator Over-voltage Interrupt (VROVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information. 4.7 Resets To protect the system during critical events, the MM912F634 analog die will drive the RESET_A pin low during the presence of the reset condition. In addition, the RESET_A pin is monitored for external reset events. To match the MCU, the RESET_A pin is based on the VDDX voltage level. After an internal reset condition has gone, the RESET_A will stay low for an additional time tRST before being released. Entering reset mode will cause all MM912F634 analog die registers to be initialized to their RESET default. The only registers with valid information are the Reset Status Register (RSR) and the Wake-up Source Register (WUS). 4.7.1 Reset Sources In the MM912F634 six reset sources exist. 4.7.1.1 POR - Analog Die Power On Reset To indicate the device power supply (VS1) was below VPOR or the MM912F634 analog die was powered up, the POR condition is set. See Section 4.3, “Modes of Operation". 4.7.1.2 LVR - Low Voltage Reset - VDD With the VDD voltage regulator output voltage falling below VLVR, the Low Voltage Reset condition becomes present. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. See Section 4.4, “Power Supply". 4.7.1.3 LVRX - Low Voltage Reset - VDDX With the VDDX voltage regulator output voltage falling below VLVRX, the Low Voltage Reset condition becomes present. See Section 4.4, “Power Supply". 4.7.1.4 WUR - Wake-up Reset While in Sleep mode, any active wake-up event will cause a MM912F634 analog die transition from Sleep to Reset Mode. To determine the wake-up source, refer to Section 4.8, “Wake-up / Cyclic Sense". 4.7.1.5 EXR - External Reset Any low level voltage at the RESET_A pin with a duration > tRSTDF will issue an External Reset event. This reset source is also active in Stop mode. 4.7.1.6 WDR - Watchdog Reset Any incorrect serving if the MM912F634 analog die Watchdog will result in a Watchdog Reset. Please refer to the Section 4.9, “Window Watchdog" for details. MM912F634 Freescale Semiconductor 70 Functional Description and Application Information Resets 4.7.2 4.7.2.1 Register Definition Reset Status Register (RSR) Table 83. Reset Status Register (RSR) Offset(65) 0x15 7 6 5 4 3 2 1 Access: User read 0 R W 0 0 WDR EXR WUR LVRX LVR POR Note: 65. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 84. RSR - Register Field Descriptions Field 5 - WDR 4 - EXR 3 - WUR 2 - LVRX 1 - LVR 0 - POR Description Watchdog Reset - Reset caused by an incorrect serving of the watchdog. External Reset - Reset caused by the RESET_A pin driven low externally for > tRSTDF Wake-up Reset - Reset caused by a wake-up from Sleep mode. To determine the wake-up source, refer to Section 4.8, “Wake-up / Cyclic Sense". Low Voltage Reset VDDX - Reset caused by a low voltage condition monitored at the VDDX output. Low Voltage Reset VDD - Reset caused by a low voltage condition monitored at the VDD output.(66) Power On Reset - Supply Voltage was below VPOR. Note: 66. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. Reading the Reset Status register will clear the information inside. Writing has no effect. LVR and LVRX are masked when POR or WUR are set. MM912F634 Freescale Semiconductor 71 Functional Description and Application Information Wake-up / Cyclic Sense 4.8 Wake-up / Cyclic Sense To wake-up the MM912F634 analog die from Stop or Sleep mode, several wake-up sources are implemented. As described in Section 4.3, “Modes of Operation", a wake-up from Stop mode will result in an interrupt (D2DINT) to the MCU combined with a transition to Normal mode. A wake-up from Sleep mode will result in a transition to Reset mode. In any case, the source of the wake-up can be identified by reading the Wake-up Source Register (WSR). The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between the WSR read and MCR write. In general, there are the following seven main wake-up sources: • • • • • • • Wake-up by a state change of one of the Lx inputs Wake-up by a state change of one of the Lx inputs during a cyclic sense Wake-up due to a forced wake-up Wake-up by the LIN module Wake-up by D2D interface (Stop mode only) Wake-up due to internal / external Reset (Stop mode only) Wake-up due to loss of supply voltage (Sleep mode only) VSUP HS1 HS2 D2DINT D2DCLK D2D3 D2D2 D2D1 L3 D2D0 Cyclic Wake Up Lx – Wake Up L4 L5 LIN LIN Bus D2D Wake Up Wake Up Module Forced Wake Up Cyclic Sense / Forced Wake Up Timer L0 L1 L2 LIN Wake Up Figure 20. Wake-up Sources 4.8.1 4.8.1.1 Wake-up Sources Lx - Wake-up (Cyclic Sense Disabled) Any state digital change on a Wake-up Enabled Lx input will issue a wake-up. In order to select and activate a Wake-up Input (Lx), the Wake-up Control Register (WCR) must be configured with appropriate LxWE inputs enabled or disabled before entering low power mode. The Lx - Wake-up may be combined with the Forced Wake-up. Note: Selecting a Lx Input for wake-up will disable a selected analog input once entering low power mode. MM912F634 Freescale Semiconductor 72 Functional Description and Application Information Wake-up / Cyclic Sense 4.8.1.2 Lx - Cyclic Sense Wake-up NOTE Once Cyclic Sense is configured (CSSEL!=0), the state change is only recognized from one cyclic sense event to the next. The additional accuracy of the cyclic sense cycle by the WD clock trimming is only active during STOP mode. There is no trimmed clock available during SLEEP mode. To reduce external power consumption during low power mode a cyclic wake-up has been implemented. Configuring the Timing Control Register (TCR) a specific cycle time can be selected to implement a periodic switching of the HS1 or HS2 output with the corresponding detection of an Lx state change. Any configuration of the HSx in the High Side Control Register (HSCR) will be ignored when entering low power mode. The Lx - Cyclic Sense Wake-up may be combined with the Forced Wake-up. In case both (forced and Lx change) events are present at the same time, the Forced Wake-up will be indicated as Wake-up source. 4.8.1.3 Forced Wake-up Configuring the Forced Wake-up Multiplier (FWM) in the Timing Control Register (TCR) will enable the forced wake-up based on the selected Cyclic Sense Timing (CST). Forced Wake-up can be combined with all other wake-up sources considering the timing dependencies. 4.8.1.4 LIN - Wake-up While in Low-Power mode the MM912F634 analog die monitors the activity on the LIN bus. A dominant pulse longer than tPROPWL followed by a dominant to recessive transition will cause a LIN Wake-up. This behavior protects the system from a short-to-ground bus condition. 4.8.1.5 D2D - Wake-up (Stop Mode only) Receiving a Normal mode request via the D2D interface (MODE=0, Mode Control Register (MCR)) will result in a wake-up from stop mode. As this condition is controlled by the MCU, no wake-up status bit does indicate this wake-up source. 4.8.1.6 Wake-up Due to Internal / External Reset (STOP Mode Only) While in Stop mode, a Reset due to a VDD low voltage condition or an external Reset applied on the RESET_A pin will result in a Wake-up with immediate transition to Reset mode. In this case, the LVR or EXR bits in the Reset Status Register will indicate the source of the event. 4.8.1.7 Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only) While in Sleep mode, a supply voltage VS1 < VPOR will result in a transition to Power On mode. MM912F634 Freescale Semiconductor 73 Functional Description and Application Information Wake-up / Cyclic Sense 4.8.2 4.8.2.1 Register Definition Wake-up Control Register (WCR) Table 85. Wake-up Control Register (WCR) Offset(67) 0x12 7 6 5 4 3 2 Access: User read/write 1 0 R W Reset 0 CSSEL 0 L5WE 1 L4WE 1 L3WE 1 L2WE 1 L1WE 1 L0WE 1 Note: 67. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 86. WCR - Register Field Descriptions Field 7-6 CSSEL Description Cyclic Sense Select - Configures the HSx output for the cyclic sense event. Note, with no LxWE selected - only the selected HSx output will be switched periodically, no Lx state change would be detected. For all configurations, the Forced Wake-up can be activated in parallel in Section 4.8.2.2, “Timing Control Register (TCR)" 00 - Cyclic Sense Off 01 - Cyclic Sense with periodic HS1on 10 - Cyclic Sense with periodic HS2 on 11 - Cyclic Sense with periodic HS1 and HS2 on. Wake-up Input 5 Enabled - L5 Wake-up Select Bit. 0 - L5 Wake-up Disabled 1 - L5 Wake-up Enabled Wake-up Input 4 Enabled - L4 Wake-up Select Bit. 0 - L4 Wake-up Disabled 1 - L4 Wake-up Enabled Wake-up Input 3 Enabled - L3 Wake-up Select Bit. 0 - L3Wake-up Disabled 1 - L3 Wake-up Enabled Wake-up Input 2 Enabled - L2 Wake-up Select Bit. 0 - L2 Wake-up Disabled 1 - L2 Wake-up Enabled Wake-up Input 1 Enabled - L1 Wake-up Select Bit. 0 - L1 Wake-up Disabled 1 - L1 Wake-up Enabled Wake-up Input 0 Enabled - L0 Wake-up Select Bit. 0 - L0 Wake-up Disabled 1 - L0 Wake-up Enabled 5 - L5WE 4 - L4WE 3 - L3WE 2- L2WE 1 - L1WE 0 - L0WE MM912F634 Freescale Semiconductor 74 Functional Description and Application Information Wake-up / Cyclic Sense 4.8.2.2 Timing Control Register (TCR) Table 87. Timing Control Register (TCR) Offset(68) 0x13 7 6 5 4 3 2 Access: User read/write 1 0 R W Reset 0 0 FWM 0 0 0 0 CST 0 0 Note: 68. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 88. TCR - Register Field Descriptions Field 7-4 FWM Description Forced Wake-up Multiplicator - Configures the multiplicator for the forced wake-up. The selected multiplicator (FWM!=0) will force a wake-up every FWM x CST ms. With this implementation, Forced and Cyclic wake-up can be performed in parallel with the cyclic sense period Addmax Two types of matches — Tagged — This matches just before a specific instruction begins execution — Force — This is valid on the first instruction boundary after a match occurs Two types of breakpoints — CPU breakpoint entering BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) Trigger mode independent of comparators — TRIG Immediate software trigger MM912F634 Freescale Semiconductor 211 Functional Description and Application Information • S12S Debug (S12SDBGV1) Module • Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 4.31.4.5.3, “Normal Mode") for change of flow definition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Pure PC: All program counter addresses are stored 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin and End alignment of tracing to trigger 4.31.1.4 Modes of Operation The DBG module can be used in all MCU functional modes. During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already armed, remains armed. The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated Table 258. Mode Dependent Restriction Summary BDM Enable x 0 0 1 1 BDM Active x 0 1 0 1 MCU Secure 1 0 0 0 0 Yes No Comparator Matches Enabled Yes Yes Breakpoints Possible Yes Only SWI Yes No Tagging Possible Yes Yes Yes No Tracing Possible No Yes Yes No Active BDM not possible when not enabled 4.31.1.5 TAGHITS Block Diagram TAGS BREAKPOINT REQUESTS SECURE COMPARATOR A MATCH0 TRANSITION TO CPU BUS INTERFACE CPU BUS COMPARATOR MATCH CONTROL COMPARATOR B MATCH1 TAG & MATCH CONTROL LOGIC STATE STATE SEQUENCER STATE COMPARATOR C MATCH2 TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 69. Debug Module Block Diagram MM912F634 Freescale Semiconductor 212 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.2 External Signal Description There are no external signals associated with this module. 4.31.3 4.31.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the DBG sub-block is shown in Table 259. Detailed descriptions of the registers and bits are given in the subsections that follow. Table 259. Quick Reference to DBG Registers Address 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0027 0x0028(171) 0x0028(172) 0x0028(173) 0x0029 0x002A 0x002B 0x002C Name DBGC1 DBGSR DBGTCR DBGC2 DBGTBH DBGTBL DBGCNT DBGSCRX DBGMFR DBGACTL DBGBCTL DBGCCTL DBGXAH DBGXAM DBGXAL DBGADH R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 15 Bit 7 Bit 15 14 6 14 13 5 13 12 4 12 11 3 11 10 2 10 0 0 SZE 0 0 NDB SZ 0 TAG TAG TAG 0 BRK BRK BRK 0 RW RW RW 0 RWE RWE RWE 0 0 0 0 COMPE COMPE COMPE Bit 16 Bit 8 Bit 0 Bit 8 0 0 0 0 0 0 0 0 0 0 SC2 MC2 SC1 MC1 SC0 MC0 TBF 0 CNT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0 0 TSOURCE 0 0 0 0 0 0 TRCMOD 0 0 TALIGN ABCM Bit 8 Bit 7 ARM TBF(170) 6 0 TRIG 0 0 5 0 4 BDM 0 3 DBGBRK 0 2 0 SSF2 1 COMRV SSF1 SSF0 Bit 0 Bit 17 9 1 9 MM912F634 Freescale Semiconductor 213 Functional Description and Application Information Table 259. Quick Reference to DBG Registers (continued) Address 0x002D 0x002E 0x002F Note: 170. 171. 172. 173. Name DBGADL DBGADHM DBGADLM R W R W R W Bit 7 Bit 7 Bit 15 Bit 7 6 6 14 6 5 5 13 5 4 4 12 4 3 3 11 3 S12S Debug (S12SDBGV1) Module 2 2 10 2 1 1 9 1 Bit 0 Bit 0 Bit 8 Bit 0 This bit is visible at DBGCNT[7] and DBGSR[7] This represents the contents if the Comparator A control register is blended into this address. This represents the contents if the Comparator B control register is blended into this address. This represents the contents if the Comparator C control register is blended into this address. 4.31.3.2 Register Descriptions This section consists of the DBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, TRIG, and COMRV[1:0] 4.31.3.2.1 Debug Control Register 1 (DBGC1) NOTE When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. Table 260. Debug Control Register (DBGC1) Address: 0x0020 7 6 5 4 3 2 1 0 R W Reset ARM 0 0 TRIG 0 0 0 BDM 0 DBGBRK 0 0 0 0 COMRV 0 Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 4:3 anytime DBG is not armed. Table 261. DBGC1 Field Descriptions Field 7 ARM Description Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. 0 Debugger disarmed 1 Debugger armed MM912F634 Freescale Semiconductor 214 Functional Description and Application Information Table 261. DBGC1 Field Descriptions (continued) Field 6 TRIG Description S12S Debug (S12SDBGV1) Module Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of comparator status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session. 0 Do not trigger until the state sequencer enters the Final State. 1 Enter Final State immediately and issue forced breakpoint request on tracing completion Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI S12SDBGV1 Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. 0 No Breakpoint generated 1 Breakpoint generated Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore, these bits determine which register is visible at the address 0x0027. See Table 262. 4 BDM 3 DBGBRK 1–0 COMRV Table 262. COMRV Encoding COMRV 00 01 10 11 Visible Comparator Comparator A Comparator B Comparator C None Visible Register at 0x0027 DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR 4.31.3.2.2 Debug Status Register (DBGSR) Table 263. Debug Status Register (DBGSR) Address: 0x0021 7 6 5 4 3 2 1 0 R W Reset POR TBF — 0 0 0 0 0 0 0 0 0 0 0 0 0 SSF2 0 0 SSF1 0 0 SSF0 0 0 Read: Anytime Write: Never Table 264. DBGSR Field Descriptions Field 7 TBF Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit. This bit is also visible at DBGCNT[7]. MM912F634 Freescale Semiconductor 215 Functional Description and Application Information Table 264. DBGSR Field Descriptions (continued) Field 2–0 SSF[2:0] Description S12S Debug (S12SDBGV1) Module State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is in currently. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state 0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 265. Table 265. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] 000 001 010 011 100 101,110,111 Current State State0 (disarmed) State1 State2 State3 Final State Reserved 4.31.3.2.3 Debug Trace Control Register (DBGTCR) Table 266. Debug Trace Control Register (DBGTCR) Address: 0x0022 7 6 5 4 3 2 1 0 R W Reset 0 0 TSOURCE 0 0 0 0 0 0 TRCMOD 0 0 0 TALIGN 0 Read: Anytime Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed. Table 267. DBGTCR Field Descriptions Field 6 TSOURCE Description Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is secured, this bit cannot be set and tracing is inhibited. This bit must be set to read the trace buffer. 0 Debug session without tracing requested 1 Debug session with tracing requested Trace Mode Bits — See Section 4.31.4.5.2, “Trace Modes" for detailed Trace Mode descriptions. In Normal mode, change of flow information is stored. In Loop1 mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail mode, address and data for all memory and register accesses is stored. In Pure PC mode the program counter value for each instruction executed is stored. See Table 268. Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session. 0 Trigger at end of stored data 1 Trigger before storing data 3–2 TRCMOD 0 TALIGN Table 268. TRCMOD Trace Mode Bit Encoding TRCMOD 00 Description Normal MM912F634 Freescale Semiconductor 216 Functional Description and Application Information Table 268. TRCMOD Trace Mode Bit Encoding (continued) TRCMOD 01 10 11 Description Loop1 Detail Pure PC S12S Debug (S12SDBGV1) Module 4.31.3.2.4 Debug Control Register2 (DBGC2) Table 269. Debug Control Register2 (DBGC2) Address: 0x0023 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 ABCM 0 Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching. Table 270. DBGC2 Field Descriptions Field 1–0 ABCM[1:0] Description A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 271. Table 271. ABCM Encoding ABCM 00 01 10 11 Description Match0 mapped to comparator A match: Match1 mapped to comparator B match. Match 0 mapped to comparator A/B inside range: Match1 disabled. Match 0 mapped to comparator A/B outside range: Match1 disabled. Reserved(174) Note: 174. Currently defaults to Comparator A, Comparator B disabled. 4.31.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL) Table 272. Debug Trace Buffer Register (DBGTB) Address: R W 0x0024, 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 X — Bit 14 X — Bit 13 X — Bit 12 X — Bit 11 X — Bit 10 X — Bit 9 X — Bit 8 X — Bit 7 X — Bit 6 X — Bit 5 X — Bit 4 X — Bit 3 X — Bit 2 X — Bit 1 X — Bit 0 X — POR Other Resets Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set. MM912F634 Freescale Semiconductor 217 Functional Description and Application Information S12S Debug (S12SDBGV1) Module Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. Table 273. DBGTB Field Descriptions Field 15–0 Bit[15:0] Description Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is written to 1, the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed and for reads with the TSOURCE bit clear. The POR state is undefined. Other resets do not affect the trace buffer contents. 4.31.3.2.6 Debug Count Register (DBGCNT) Table 274. Debug Count Register (DBGCNT) Address: 0x0026 7 6 5 4 3 2 1 0 R W Reset POR TBF — 0 0 — 0 — 0 — 0 — 0 CNT — 0 — 0 — 0 Read: Anytime Write: Never Table 275. DBGCNT Field Descriptions Field 7 TBF Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit. This bit is also visible at DBGSR[7] Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer. Table 276 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization, but is not cleared by other system resets. Thus, should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer. 5–0 CNT[5:0] Table 276. CNT Decoding Table TBF 0 0 CNT[5:0] 000000 000001 000010 000100 000110 … 111111 000000 Description No data valid 1 line valid 2 lines valid 4 lines valid 6 lines valid … 63 lines valid 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 1 MM912F634 Freescale Semiconductor 218 Functional Description and Application Information Table 276. CNT Decoding Table (continued) TBF 1 CNT[5:0] 000001 … … 111110 Description S12S Debug (S12SDBGV1) Module 64 lines valid, oldest data has been overwritten by most recent data 4.31.3.2.7 Debug State Control Registers There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 277. State Control Register Access Encoding COMRV 00 01 10 11 Visible State Control Register DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR 4.31.3.2.7.1 Debug State Control Register 1 (DBGSCR1) Table 278. Debug State Control Register 1 (DBGSCR1) Address: 0x0027 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 SC2 0 SC1 0 SC0 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the match channels of the comparator match control logic as depicted in Figure 69 and described in Section 4.31.3.2.8.1, “Debug Comparator Control Register (DBGXCTL)"”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 279. DBGSCR1 Field Descriptions Field 2–0 SC[2:0] Description These bits select the targeted next state whilst in State1, based upon the match event. MM912F634 Freescale Semiconductor 219 Functional Description and Application Information Table 280. State1 Sequencer Next State Selection SC[2:0] 000 001 010 011 100 101 110 111 Description Any match to Final State Match1 to State3 Match2 to State2 Match1 to State2 S12S Debug (S12SDBGV1) Module Match0 to State2....... Match1 to State3 Match1 to State3....... Match0 Final State Match0 to State2....... Match2 to State3 Either Match0 or Match1 to State2........... Match2 has no effect The priorities described in Table 311 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches. 4.31.3.2.7.2 Debug State Control Register 2 (DBGSCR2) Table 281. Debug State Control Register 2 (DBGSCR2) Address: 0x0027 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 SC2 0 SC1 0 SC0 0 Read: If COMRV[1:0] = 01 Write: If COMRV[1:0] = 01 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2. The matches refer to the match channels of the comparator match control logic as depicted in Figure 69 and described in Section 4.31.3.2.8.1, “Debug Comparator Control Register (DBGXCTL)"”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 282. DBGSCR2 Field Descriptions Field 2–0 SC[2:0] Description These bits select the targeted next state whilst in State2, based upon the match event. Table 283. State2 —Sequencer Next State Selection SC[2:0] 000 001 010 011 100 101 110 111 Description Match0 to State1....... Match2 to State3. Match1 to State3 Match2 to State3 Match1 to State3....... Match0 Final State Match1 to State1........ Match2 to State3 Match2 Final State Match2 to State1..... Match0 to Final State Match2 has no affect, all other matches (M0,M1) to Final State The priorities described in Table 311 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches MM912F634 Freescale Semiconductor 220 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.3.2.7.3 Debug State Control Register 3 (DBGSCR3) Table 284. Debug State Control Register 3 (DBGSCR3) Address: 0x0027 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 SC2 0 SC1 0 SC0 0 Read: If COMRV[1:0] = 10 Write: If COMRV[1:0] = 10 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3. The matches refer to the match channels of the comparator match control logic as depicted in Figure 69 and described in Section 4.31.3.2.8.1, “Debug Comparator Control Register (DBGXCTL)"”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 285. DBGSCR3 Field Descriptions Field 2–0 SC[2:0] Description These bits select the targeted next state whilst in State3, based upon the match event. Table 286. State3 — Sequencer Next State Selection SC[2:0] 000 001 010 011 100 101 110 111 Description Match0 to State1 Match2 to State2........ Match1 to Final State Match0 to Final State.......Match1 to State1 Match1 to Final State....... Match2 to State1 Match1 to State2 Match1 to Final State Match2 to State2....... Match0 to Final State Match0 to Final State The priorities described in Table 311 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches. MM912F634 Freescale Semiconductor 221 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.3.2.7.4 Debug Match Flag Register (DBGMFR) Table 287. Debug Match Flag Register (DBGMFR) Address: 0x0027 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 MC2 0 MC1 0 MC0 0 Read: If COMRV[1:0] = 11 Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly to a channel. Should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag. 4.31.3.2.8 Comparator Register Descriptions Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparator B consists of four register bytes (three address bus compare registers and a control register). Comparator C consists of four register bytes (three address bus compare registers and a control register). Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs from those of comparators A and C. Table 288. Comparator Register Layout 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F CONTROL ADDRESS HIGH ADDRESS MEDIUM ADDRESS LOW DATA HIGH COMPARATOR DATA LOW COMPARATOR DATA HIGH MASK DATA LOW MASK Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Comparators A,B and C Comparators A,B and C Comparators A,B and C Comparators A,B and C Comparator A only Comparator A only Comparator A only Comparator A only MM912F634 Freescale Semiconductor 222 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.3.2.8.1 Debug Comparator Control Register (DBGXCTL) The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. Table 289. Debug Comparator Control Register DBGACTL (Comparator A) Address: 0x0028 7 6 5 4 3 2 1 0 R W Reset 0 0 NDB 0 TAG 0 BRK 0 RW 0 RWE 0 0 0 COMPE 0 Table 290. Debug Comparator Control Register DBGBCTL (Comparator B) Address: 0x0028 7 6 5 4 3 2 1 0 R W Reset SZE 0 SZ 0 TAG 0 BRK 0 RW 0 RWE 0 0 0 COMPE 0 Table 291. Debug Comparator Control Register DBGCCTL (Comparator C) Address: 0x0028 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 TAG 0 BRK 0 RW 0 RWE 0 0 0 COMPE 0 Read: DBGACTL if COMRV[1:0] = 00 DBGBCTL if COMRV[1:0] = 01 DBGCCTL if COMRV[1:0] = 10 Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed DBGBCTL if COMRV[1:0] = 01 and DBG not armed DBGCCTL if COMRV[1:0] = 10 and DBG not armed Table 292. DBGXCTL Field Descriptions Field 7 SZE (Comparator B) 6 NDB (Comparator A) Description Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator. This bit is ignored if the TAG bit in the same register is set. 0 Word/Byte access size is not used in comparison 1 Word/Byte access size is used in comparison Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same register is set. This bit is only available for comparator A. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. This bit is only featured in comparator B. 0 Word access size will be compared 1 Byte access size will be compared 6 SZ (Comparator B) MM912F634 Freescale Semiconductor 223 Functional Description and Application Information Table 292. DBGXCTL Field Descriptions (continued) Field 5 TAG Description S12S Debug (S12SDBGV1) Module Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 Allow state sequencer transition immediately on match 1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition Break— This bit controls whether a comparator match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit DBGBRK. 0 The debug session termination is dependent upon the state sequencer and trigger conditions. 1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set. 0 Write cycle will be matched 1 Read cycle will be matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator.This bit is ignored if the TAG bit in the same register is set 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled 4 BRK 3 RW 2 RWE 0 COMPE Table 293 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue. Table 293. Read or Write Comparison Logic Table RWE Bit 0 0 1 1 1 1 RW Bit x x 0 0 1 1 RW Signal 0 1 0 1 0 1 Comment RW not used in comparison RW not used in comparison Write data bus No match No match Read data bus 4.31.3.2.8.2 Debug Comparator Address High Register (DBGXAH) Table 294. Debug Comparator Address High Register (DBGXAH) Address: 0x0029 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Bit 17 0 Bit 16 0 The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F. Table 295. Comparator Address Register Visibility COMRV 00 Visible Comparator DBGAAH, DBGAAM, DBGAAL MM912F634 Freescale Semiconductor 224 Functional Description and Application Information S12S Debug (S12SDBGV1) Module Table 295. Comparator Address Register Visibility (continued) COMRV 01 10 11 Visible Comparator DBGBAH, DBGBAM, DBGBAL DBGCAH, DBGCAM, DBGCAL None Read: Anytime. See Table 296 for visible register encoding. Write: If DBG not armed. See Table 296 for visible register encoding. Table 296. DBGXAH Field Descriptions Field 1–0 Bit[17:16] Description Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator will compare the address bus bits [17:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 4.31.3.2.8.3 Address: 0x002A 7 Debug Comparator Address Mid Register (DBGXAM) 6 5 4 3 2 1 0 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Table 297. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 297 for visible register encoding. Write: If DBG not armed. See Table 297 for visible register encoding. Table 298. DBGXAM Field Descriptions Field 7–0 Bit[15:8] Description Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the selected comparator will compare the address bus bits [15:8] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MM912F634 Freescale Semiconductor 225 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.3.2.8.4 Debug Comparator Address Low Register (DBGXAL) Table 299. Debug Comparator Address Low Register (DBGXAL) Address: 0x002B 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Read: Anytime. See Table 300 for visible register encoding. Write: If DBG not armed. See Table 300 for visible register encoding. Table 300. DBGXAL Field Descriptions Field 7–0 Bits[7:0] Description Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator will compare the address bus bits [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 4.31.3.2.8.5 Debug Comparator Data High Register (DBGADH) Table 301. Debug Comparator Data High Register (DBGADH) Address: 0x002C 7 6 5 4 3 2 1 0 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 302. DBGADH Field Descriptions Field 7–0 Bits[15:8] Description Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one MM912F634 Freescale Semiconductor 226 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.3.2.8.6 Debug Comparator Data Low Register (DBGADL) Table 303. Debug Comparator Data Low Register (DBGADL) Address: 0x002D 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 304. DBGADL Field Descriptions Field 7–0 Bits[7:0] Description Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one 4.31.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM) Table 305. Debug Comparator Data High Mask Register (DBGADHM) Address: 0x002E 7 6 5 4 3 2 1 0 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 306. DBGADHM Field Descriptions Field 7–0 Bits[15:8] Description Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Do not compare corresponding data bit. Any value of corresponding data bit allows match. 1 Compare corresponding data bit MM912F634 Freescale Semiconductor 227 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.3.2.8.8 Debug Comparator Data Low Mask Register (DBGADLM) Table 307. Debug Comparator Data Low Mask Register (DBGADLM) Address: 0x002F 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 308. DBGADLM Field Descriptions Field 7–0 Bits[7:0] Description Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Do not compare corresponding data bit. Any value of corresponding data bit allows match 1 Compare corresponding data bit 4.31.4 Functional Description This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can generate breakpoints, but tracing is not possible. 4.31.4.1 S12SDBGV1 Operation Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer, and generation of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity. Comparator A can also be configured to monitor databus activity and mask out individual data bus bits during a compare. Comparators can be configured to use R/W and word/byte access qualification in the comparison. A match with a comparator register value can initiate a state sequencer transition to another state (see Figure 71). Either forced or tagged matches are possible. Using a forced match, a state sequencer transition can occur immediately on a successful match of system busses and comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue, can a state sequencer transition occur. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated. A state sequencer transition to Final State (with associated breakpoint, if enabled) can be initiated by writing to the TRIG bit in the DBGC1 control register. The trace buffer is visible through a 2-byte window in the register address map, and must be read out using standard 16-bit word reads. MM912F634 Freescale Semiconductor 228 Functional Description and Application Information S12S Debug (S12SDBGV1) Module TAGHITS TAGS BREAKPOINT REQUESTS SECURE COMPARATOR A MATCH0 TRANSITION TO CPU BUS INTERFACE CPU BUS COMPARATOR MATCH CONTROL COMPARATOR B MATCH1 TAG & MATCH CONTROL LOGIC STATE STATE SEQUENCER STATE COMPARATOR C MATCH2 TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 70. DBG Overview 4.31.4.2 Comparator Modes The DBG contains three comparators, A, B, and C. Each comparator compares the system address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH and DBGADL, and allows masking of individual data bus bits. All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (see Figure 70) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. A match can initiate a transition to another state sequencer state (see Section 4.31.4.4, “State Sequence Control"”). The comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare. Only comparator B features SZE and SZ. The TAG bit in each comparator control register is used to determine the match condition. By setting TAG, the comparator will qualify a match with the output of opcode tracking logic and a state sequencer transition occurs when the tagged instruction reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE, and SZ bits and the comparator data registers are ignored; the comparator address register must be loaded with the exact opcode address. If the TAG bit is clear (forced type match), a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory, which precedes the instruction execution by an indefinite number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data value when a subsequent match occurs. MM912F634 Freescale Semiconductor 229 Functional Description and Application Information S12S Debug (S12SDBGV1) Module Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see Section 4.31.3.2.4, “Debug Control Register2 (DBGC2)"”). Comparator channel priority rules are described in the priority section (Section 4.31.4.3.4, “Channel Priorities"”). 4.31.4.2.1 Exact Address Comparator Match (Comparators A and C) With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the comparator address/data registers. Further qualification of the type of access (R/W, word/byte) is possible. Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. The exact address is compared, thus with the comparator address register loaded with address (n) a word access of address (n–1) also accesses (n) but does not cause a match. Table 310 lists access considerations without data bus compare. Table 309 lists access considerations with data bus comparison. To compare byte accesses DBGADH must be loaded with the data byte and the low byte must be masked out using the DBGADLM mask register. On word accesses the data byte of the lower address is mapped to DBGADH. Table 309. Comparator A Data Bus Considerations Access Word Byte Word Word Address ADDR[n] ADDR[n] ADDR[n] ADDR[n] DBGADH Data[n] Data[n] Data[n] x DBGADL Data[n+1] x x Data[n+1] DBGADHM $FF $FF $FF $00 DBGADLM $FF $00 $00 $FF Example Valid Match MOVW #$WORD ADDR[n] MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] MOVW #$WORD ADDR[n] Comparator A features an NDB control bit to determine if a match occurs when the data bus differs to comparator register contents, or when the data bus is equivalent to the comparator register contents. 4.31.4.2.2 Exact Address Comparator Match (Comparator B) Comparator B features SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the same as for comparators A and C. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified type of access causes a match. Thus if configured for a byte access of a particular address, a word access covering the same address does not lead to match. Table 310. Comparator Access Size Considerations Comparator Comparators A and C Comparator B Address ADDR[n] SZE — SZ8 — Condition For Valid Match Word and byte accesses of ADDR[n](175) MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word and byte accesses of ADDR[n](175) MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word accesses of ADDR[n](175) MOVW #$WORD ADDR[n] Byte accesses of ADDR[n] MOVB #$BYTE ADDR[n] ADDR[n] 0 X Comparator B Comparator B ADDR[n] ADDR[n] 1 1 0 1 Note: 175. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address used in the code. MM912F634 Freescale Semiconductor 230 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.2.3 Range Comparisons Using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A TAG bit is used to tag range comparisons. The comparator B TAG bit is ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is ignored in range mode. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 4.31.4.2.3.1 Inside Range (CompA_Addr ≤ address ≤ CompB_Addr) In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons. This configuration depends upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary is valid only if the aligned address is inside the range. 4.31.4.2.3.2 Outside Range (address < CompA_Addr or address > CompB_Addr) In the outside range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid only if the aligned address is outside the range. Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an unexpected range. In forced match mode the outside range match would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or lower range limit to $00000 respectively. 4.31.4.3 Match Modes (Forced or Tagged) Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register TAG bits select the match mode. The modes are described in the following sections. 4.31.4.3.1 Forced Match When configured for forced matching, a comparator channel match can immediately initiate a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state. Forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent of comparator RWE/RW settings. Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an opcode address typically precedes a tagged match at the same address. 4.31.4.3.2 Tagged Match If a CPU taghit occurs a transition to another state, sequencer state is initiated, and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition. 4.31.4.3.3 Immediate Trigger Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint, by writing to the TRIG bit in DBGC1. This forces the state sequencer into the Final State and issues a forced breakpoint request to the CPU. MM912F634 Freescale Semiconductor 231 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.3.4 Channel Priorities In case of simultaneous matches, the priority is resolved according to Table 311. The lower priority is suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described in Table 311 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches independent of current state sequencer state. When configured for range mode on Comparators A/B, match0 has priority whilst match2 is suppressed if a simultaneous range and Comparator C match occur. Table 311. Channel Priorities Priority Highest Source TRIG Match0 (force or tag hit) Match1 (force or tag hit) Lowest Match2 (force or tag hit) Action Enter Final State Transition to next state as defined by state control registers Transition to next state as defined by state control registers Transition to next state as defined by state control registers 4.31.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 ARM = 0 Session Complete (Disarm) Final State ARM = 0 State3 State2 Figure 71. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and channel matches. The only permitted transition from Final State is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, the Final State is entered and tracing starts immediately if the TSOURCE bit is configured for tracing. Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. MM912F634 Freescale Semiconductor 232 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.4.1 Final State On entering Final State, a trigger may be issued to the trace buffer according to the trace alignment control, as defined by the TALIGN bit (see Section 4.31.3.2.3, “Debug Trace Control Register (DBGTCR)"”). If the TSOURCE bit in DBGTCR is clear then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case, or upon completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed. 4.31.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next read will receive fresh information. Data is stored in the format shown in Table 312. After each store, the counter register DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer, whilst the DBG is armed, returns invalid data and the trace buffer pointer is not incremented. 4.31.4.5.1 Trace Trigger Alignment Using the TALIGN bit (see Section 4.31.3.2.3, “Debug Trace Control Register (DBGTCR)"”) it is possible to align the trigger with the end or the beginning of a tracing session. If End tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State signals the end of the tracing session. Tracing with Begin Trigger starts at the opcode of the trigger. Using End Trigger, or when the tracing is initiated by writing to the TRIG bit whilst configured for Begin-Trigger, tracing starts at the second opcode after writing to DBGC1 4.31.4.5.1.1 Storing with Begin Trigger Storing with Begin Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the DBG module will remain armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction, the change of flow associated with the trigger will be stored in the Trace Buffer. Using Begin Trigger together with tagging, if the tagged instruction is about to be executed, then the trace is started. Upon completion of the tracing session, the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 4.31.4.5.1.2 Storing with End Trigger Storing with End Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module will become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event will not be stored in the Trace Buffer. 4.31.4.5.2 Trace Modes Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections. The trace buffer organization is shown in Table 312. MM912F634 Freescale Semiconductor 233 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.5.3 Normal Mode In Normal mode, change of flow (COF) program counter (PC) addresses will be stored. COF addresses are defined as follows: • • • • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) Destination address of indexed JMP, JSR, and CALL instruction Destination address of RTI, RTS, and RTC instructions Vector address of interrupts, except for BDM vectors LBRA, BRA, BSR, BGND, as well as non-indexed JMP, JSR, and CALL instructions, are not classified as change of flow and are not stored in the trace buffer. Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. NOTE When a COF instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously, then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets executed after the interrupt service routine. In the following example, an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine, but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place. MARK1 MARK2 SUB_1 LDX JMP NOP BRN NOP DBNE LDAB STAB RTI LDX JMP LDAB STAB RTI BRN NOP DBNE #SUB_1 0,X ; IRQ interrupt occurs during execution of this ; ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ; ; Source address TRACE BUFFER ENTRY 4 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 * ADDR1 IRQ_ISR A,PART5 #$F0 VAR_C1 ; The execution flow taking into account the IRQ is as follows #SUB_1 0,X #$F0 VAR_C1 * A,PART5 ; ; ; ; ; MARK1 IRQ_ISR SUB_1 ADDR1 MM912F634 Freescale Semiconductor 234 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.5.3.1 Loop1 Mode NOTE In certain very tight loops, the source address will have already been fetched again before the background comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below: Loop1 mode, similarly to Normal mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches. Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. LOOP INX BRCLR ; 1-byte instruction fetched by 1st P-cycle of BRCLR ; the BRCLR instruction also will be fetched by 1st ; P-cycle of BRCLR ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE CMPTMP,#$0c,LOOP LOOP2 BRN NOP DBNE * A,LOOP2 4.31.4.5.3.2 Detail Mode In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes, where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information bit storage to the trace buffer, for each address byte storage. The information bits indicates the size of access (word or byte) and the type of access (read or write). When tracing in Detail mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle. 4.31.4.5.3.3 Pure PC Mode NOTE: When tracing is terminated using forced breakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoint can be stored to the trace buffer. The number of opcodes is dependent on program flow. This should be avoided by using tagged breakpoints. In Pure PC mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal opcodes are stored. MM912F634 Freescale Semiconductor 235 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.5.4 Trace Buffer Organization ADRH, ADRM, and ADRL denote address high, middle, and low byte respectively. CRW and CSZ indicate R/W and size access information. The numerical suffix refers to the tracing count. The information format for Loop1, Pure PC and Normal modes is identical. In Detail mode, the address and data for each entry are stored on consecutive lines. Thus, the maximum number of entries is 32. In this case, DBGCNT bits are incremented twice, once for the address line and once for the data line, on each trace buffer entry. Single byte data accesses in Detail mode is always stored to the low byte of the trace buffer (DATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte1, and the byte at the higher address is stored to byte0. Table 312. Trace Buffer Organization(20-bit wide buffer) 4-bits Mode Entry Number Field 2 Entry 1 Detail Mode Entry 2 Other Modes Entry 1 Entry 2 CSZ1,CRW1,ADRH1 0 CSZ2,CRW2,ADRH2 0 PCH1 PCH2 Field 1 ADRM1 DATAH1 ADRM2 DATAH2 PCM1 PCM2 Field 0 ADRL1 DATAL1 ADRL2 DATAL2 PCL1 PCL2 8-bits 8-bits 4.31.4.5.4.1 Information Bit Organization The format of the bits is dependent upon the active trace mode, as described by the following. 4.31.4.5.4.2 Field2 Bits in Detail Mode Table 313. Field2 Information Bits in Detail Mode Bit 3 CSZ Bit 2 CRW Bit 1 ADRH17 Bit 0 ADRH16 In Detail mode, the CSZ and CRW bits indicate the type of access being made by the CPU. Table 314. Field Descriptions Field 3 CSZ 2 CRW Description Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail mode 0 Word Access 1 Byte Access Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access when tracing in Detail Mode. 0 Write Access 1 Read Access Address Bus bit 17— Corresponds to system address bus bit 17. Address Bus bit 16— Corresponds to system address bus bit 16. 1 ADRH17 0 ADRH16 MM912F634 Freescale Semiconductor 236 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.5.4.3 Field2 Bits in Normal, Pure PC and Loop1 Modes Table 315. Information Bits PCH Bit 3 CSD Bit 2 CVA Bit 1 PC17 Bit 0 PC16 Table 316. PCH Field Descriptions Field 3 CSD Description Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source or destination address. This bit has no meaning in Pure PC mode. 0 Source Address 1 Destination Address Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no meaning in Pure PC mode. 0 Non-Vector Destination Address 1 Vector Destination Address Program Counter bit 17— In Normal, Pure PC, and Loop1 mode this bit corresponds to program counter bit 17. Program Counter bit 16— In Normal, Pure PC, and Loop1 mode this bit corresponds to program counter bit 16. 2 CVA 1 PC17 0 PC16 4.31.4.5.5 Reading Data from Trace Buffer The data stored in the Trace Buffer can be read, provided the DBG module is not armed, is configured for tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT, the number of valid lines can be determined. DBGCNT will not decrement as data is read. Whilst reading, an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least significant word of line is read out first. This corresponds to the fields 1 and 0 of Table 312. The next word read returns field 2 in the least significant bits [3:0] and “0” for bits [15:4]. Reading the Trace Buffer while the DBG module is armed, will return invalid data and no shifting of the RAM pointer will occur. 4.31.4.5.6 Trace Buffer Reset State The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred, can be read out and the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data, even if a reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set, otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best handled using end trigger alignment, since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. The Trace Buffer contents and DBGCNT bits are undefined following a POR MM912F634 Freescale Semiconductor 237 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue, a tag hit occurs and can initiate a state sequencer transition. Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address. Using Begin trigger together with tagging, if the tagged instruction is about to be executed, then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when the tagged instruction is about to be executed and the next transition is to Final State, then a breakpoint is generated immediately before the tagged instruction is carried out. R/W monitoring is not useful for tagged operations, since the taghit occurs based on the tagged opcode reaching the execution stage of the instruction queue. Similarly access size (SZ) monitoring and data bus monitoring is not useful if tagging is selected, since the tag is attached to the opcode at the matched address, and is not dependent on the data bus nor on the size of access. Thus these bits are ignored if tagging is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. Tagging is disabled when the BDM becomes active. 4.31.4.7 Breakpoints It is possible to generate breakpoints from channel transitions to Final State or using software to write to the TRIG bit in the DBGC1 register. 4.31.4.7.1 Breakpoints From Comparator Channels Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 317). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment. Table 317. Breakpoint Setup For CPU Breakpoints BRK 0 0 0 0 1 1 TALIGN 0 0 1 1 x x DBGBRK 0 1 0 1 1 0 Breakpoint Alignment Fill Trace Buffer until trigger, then disarm (no breakpoints) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints) Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full Terminate tracing and generate breakpoint immediately on trigger Terminate tracing immediately on trigger MM912F634 Freescale Semiconductor 238 Functional Description and Application Information S12S Debug (S12SDBGV1) Module 4.31.4.7.2 Breakpoints Generated Via the TRIG Bit If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 317). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if the DBG module is disarmed. 4.31.4.7.3 Breakpoint Priorities If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator channel match, it has no effect, since tracing has already started. If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is activated by the BGND and the breakpoint to SWI is suppressed. 4.31.4.7.3.1 DBG Breakpoint Priorities and BDM Interfacing NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification, it will return to the instruction whose tag generated the breakpoint. To avoid a repeated breakpoint at the same location, reconfigure the DBG module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface, by executing a TRACE command before the GO to increment the program flow past the tagged instruction. Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests, if the breakpoint happens to coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed. Table 318. Breakpoint Mapping Summary DBGBRK 0 1 X 1 1 BDM Bit (DBGC1[4]) X 0 X 1 1 BDM Enabled X X 1 0 1 BDM Active X 0 1 X 0 Breakpoint Mapping No Breakpoint Breakpoint to SWI No Breakpoint Breakpoint to SWI Breakpoint to BDM BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code, checks the ENABLE, and returns if ENABLE is not set. If not serviced by the monitor, then the breakpoint is re-asserted when the BDM returns to normal CPU flow. If the comparator register contents coincide with the SWI/BDM vector address, then an SWI in user code and DBG breakpoint could occur simultaneously. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine, care must be taken to avoid a repeated breakpoint at the same address. Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes. MM912F634 Freescale Semiconductor 239 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32 4.32.1 S12S Clocks and Reset Generator (S12SCRGV1) Introduction This specification describes the function of the Clocks and Reset Generator (S12SCRGV1). 4.32.1.1 Features The main features of this block are: • Internal 32 kHz reference clock generator: — Trimmable in frequency — ± 2% deviation over voltage and temperature for a fixed trim value. — Factory trimmed value in Flash Memory Optional external crystal or resonator: — Full swing Pierce Oscillator for crystals or resonators from 4.0 MHz to 16 MHz — Oscillator Monitor to detect loss of clock Internal digitally controlled oscillator (DCO): — Allows to generate frequencies in the range from 32 MHz to 40 MHz — Stable frequency by using a reference clock in a Frequency Locked Loop (FLL). — FLL based on either Internal Reference Clock (32 kHz) or optional external crystal/resonator (for higher accuracy). — Interrupt request on entry or exit from FLL locked condition Bus Clock Generator — Clock switch for DCO or optional external crystal/resonator based Bus Clock — Bus Clock divider to choose system speed System Reset generation from the following possible sources: — Power-on detect — Illegal address access — COP timeout — Loss of external Oscillator Clock (Oscillator monitor fail) — External pin RESET • • • • 4.32.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the 9S12I32PIMV1. 4.32.1.2.1 • Run Mode • • FLL Engaged Internal (FEI) — This is the default mode after System Reset and Power-on Reset. — The FLL reference is the Internal Reference Clock. — The Bus Clock is based on the DCO Clock. FLL Engaged External (FEE) — This mode is entered by: – enabling the external Oscillator (OSCEN bit) – programming the reference divider (RDIV[2:0] bits) – selecting the divided down Oscillator Clock as FLL reference clock (REFS bit) — The FLL reference is the Oscillator Clock. — The Bus Clock is based on the DCO Clock. FLL Bypassed External (FBE) — This mode is entered by: – enabling the external Oscillator (OSCEN bit) – selecting the Oscillator Clock as basis for Bus Clock (BCLKS bit) — The DCO Clock is turned off. — The Bus Clock is based on the Oscillator Clock. MM912F634 Freescale Semiconductor 240 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.1.2.2 Wait Mode For 9S12I32PIMV1 Wait mode is same as Run mode. 4.32.1.2.3 • • • • • Stop Mode This mode is entered by executing the CPU STOP instruction. The Bus Clock is turned off. The Oscillator Clock and the Oscillator Monitor is turned off. The DCO Clock is turned off. The Internal Reference Clock can be kept enabled by peripherals like e.g. the Real Time Interrupt module (RTI). See device and other block descriptions for details. 4.32.1.3 Block Diagram Figure 72 shows a block diagram of the 9S12I32PIMV1. MM912F634 Freescale Semiconductor 241 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) S12SMMC VDD Power on detect VSS Illegal Address Access Power-On Detect S12SCRG COP Watchdog Oscillator Monitor EXTAL Full swing Pierce Oscillator 4MHz-16MHz XTAL Reference Divider 128 - 512 RDIV[2:0] REFS UPOSC OSCEN OSC4MHZ PORF COP time out Monitor fail Reset Generator ILAF Power-On Reset System Reset RESET Oscillator Clock TRIM[8:0] Internal Reference Clock DCO Clock Internal Reference Clock divide by 5 Bus Divider 1 - 16 BDM Clock Core Clock divide Bus Clock by 2 BCLKS Digital Controlled Oscillator (DCO) speed adjust LOCKIE LOCKIF LOCKST & FLL Lock Interrupt BDIV[3:0] FLL Reference Clock MULT[6:0] Digital Filter multiply by 1000 + (2*MULT) Frequency locked loop (FLL) Figure 72. Block diagram of 9S12I32PIMV1 4.32.2 Signal Description This section lists and describes the signals that connect off chip. 4.32.2.1 RESET RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that a System Reset or Power-on Reset (internal to MCU) has been triggered. MM912F634 Freescale Semiconductor 242 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the 9S12I32PIMV1. 4.32.3.1 Module Memory Map Table 319 gives an overview on all 9S12I32PIMV1 registers. Table 319. 9S12I32PIMV1 Register Summary Address 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B Name CRGCTL0 CRGCTL1 CRGMULT CRGFLG CRGTRIMH CRGTRIML CRGTEST0 (Reserved) CRGTEST1 (Reserved) R W R W R W R W R W R W R W R W U U U U U U U U 0 0 0 0 TRIM[7:0] 0 0 0 0 0 0 PORF 0 0 0 LOCKIF 0 0 Bit 7 OSCEN 6 5 RDIV[2:0] BDIV[3:0] 4 3 BCLKS 0 2 REFS 0 1 OSC4MHZ LOCKIE Bit 0 0 0 MULT[6:0] LOCKST 0 ILAF 0 UPOSC 0 0 TRIM[8] 4.32.3.2 Register Descriptions This section describes in address order all the 9S12I32PIMV1 registers and their individual bits. MM912F634 Freescale Semiconductor 243 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.3.2.1 9S12I32PIMV1 Control Register 0 (CRGCTL0) Table 320. 9S12I32PIMV1 Control Register 0 (CRGCTL0) 0x0034 7 6 5 4 3 2 1 0 R W Reset OSCEN 0 0 RDIV[2:0] 0 0 BCLKS 0 REFS 0 OSC4MHZ 0 0 0 Read: Anytime Write: See individual bit descriptions. Writing the CRGCTL0 register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register. Table 321. CRGCTL0 Field Descriptions Field 7 OSCEN 6, 5, 4 RDIV[2:0] Oscillator Enable Bit 0 Oscillator Clock and Oscillator Monitor are disabled. 1 Oscillator Clock and Oscillator Monitor are enabled. Reference Divider Bits These bits divide the Oscillator Clock down in frequency. Divided down frequency must be in the allowed range for fFLLREF. See device electrical characteristics for details. 000 divide by 128 001 divide by 160 010 divide by 192 011 divide by 256 100 divide by 320 101 divide by 384 110 divide by 512 111 Reserved Bus Clock Source Select Bit Writing BCLKS = 1 is only possible if oscillator startup flag is set (UPOSC = 1). BCLKS is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop Mode. 0 DCO Clock is selected as basis for the Bus Clock. 1 Oscillator Clock is selected as basis for the Bus Clock. DCO is disabled. Reference Select Bit Writing REFS = 1 is only possible if oscillator startup flag is set (UPOSC = 1). REFS is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop Mode. 0 Internal Reference Clock is selected as FLL Reference Clock. 1 Divided down Oscillator Clock is selected as FLL Reference Clock. 4.0 MHz Oscillator low pass filter select Bit The Oscillator contains a noise filter in its signal path from EXTAL/XTAL to chip internal Oscillator Clock. This is to improve high frequency noise immunity. Writing OSC4MHZ is only possible if OSCEN was zero before. 0 Oscillator uses noise filter with high bandwidth. To be used with crystals/resonators > 4.0 Mhz. 1 Oscillator uses noise filter with low bandwidth. To be used with crystals/resonators = 4.0 Mhz. Choosing a low bandwidth in case of a 4.0 MHz crystal/resonator further improves noise immunity at lower frequencies. Description 3 BCLKS 2 REFS 1 OSC4MHZ MM912F634 Freescale Semiconductor 244 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.3.2.2 9S12I32PIMV1 Control Register 1 (CRGCTL1) Table 322. 9S12I32PIMV1 Control Register (CRGCTL1) 0x0035 7 6 5 4 3 2 1 0 R W Reset 0 0 BDIV[3:0] 0 0 0 0 0 0 LOCKIE 0 0 0 Read: Anytime Write: Anytime Table 323. CRGCTL1 Field Descriptions Field 7, 6, 5, 4 BDIV[3:0] Description Bus Divider Bits Depending on the setting of the BCLKS bit, either the DCO Clock or the Oscillator Clock is divided down in frequency to create the Core Clock. Bus frequency is Core frequency divided by 2. 0000 divide by 1 0001 divide by 2 0010 divide by 3 0011 divide by 4 0100 divide by 5 0101 divide by 6 0110 divide by 7 0111 divide by 8 1000 divide by 9 1001 divide by 10 1010 divide by 11 1011 divide by 12 1100 divide by 13 1101 divide by 14 1110 divide by 15 1111 divide by 16 FLL Lock Interrupt Enable Bit 0 FLL Lock Interrupt requests are disabled. 1 FLL Lock Interrupt will be requested whenever LOCKIF is set. 1 LOCKIE 4.32.3.2.3 9S12I32PIMV1 FLL Multiply Register (CRGMULT) This register determines the multiplication factor to generate the DCO Clock. Table 324. 9S12I32PIMV1 FLL Multiply Register (CRGMULT) 0x0036 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 MULT[6:0] 0 0 0 0 Read: Anytime Write: Anytime Writing the CRGMULT register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register. MM912F634 Freescale Semiconductor 245 Functional Description and Application Information Table 325. CRGMULT Field Descriptions Field S12S Clocks and Reset Generator (S12SCRGV1) Description 6, 5, 4, 3, 2, 1, FLL Multiplier Bits 0 DCO Clock will lock to RDIV Clock multiplied by (1000 + 2*MULT[6:0]. Depending on the REFS bit, RDIV Clock is either the MULT[6:0] Internal Reference Clock or the divided down Oscillator Clock. So multiplication factors can be from 1000 to 1254. MULT[6:0] bits must be chosen so that the minimum and maximum DCO Clock frequency fDCO is not violated. See Electrical Characteristics for frequency range of fDCO. 4.32.3.2.4 9S12I32PIMV1 Flags Register (CRGFLG) This register provides 9S12I32PIMV1 status bits and flags. Table 326. 9S12I32PIMV1 Flags Register (CRGFLG) 0x0037 7 6 5 4 3 2 1 0 R W Reset 0 0 PORF (176) 0 0 LOCKIF 0 LOCKST 0 ILAF (177) UPOSC 0 0 0 Note: 176. PORF is set to 1 when a Power-On Reset occurs. Unaffected by System Reset. 177. ILAF is set to 1 when an illegal address access occurs. Unaffected by System Reset. Cleared by Power-On Reset. Read: Anytime Write: Refer to each bit for individual write conditions Table 327. CRGFLG Field Descriptions Field 6 PORF Description Power-on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power-on Reset has not occurred. 1 Power-on Reset has occurred. FLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCKST status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. Entering Stop mode or writing registers CRGCTL0, CRGMULT, CRGTRIMH, or CRGTRIML while LOCKST = 1, clears the LOCKST bit, but does not set the LOCKIF bit. 0 No change in LOCKST bit. 1 LOCKST bit has changed. Lock Status Bit — LOCKST reflects the current state of FLL lock condition. Writes have no effect. Entering stop mode or writing registers CRGCTL0, CRGMULT, CRGTRIMH, or CRGTRIML clears the LOCKST bit. 0 DCO Clock is not within the desired tolerance of the target frequency. 1 DCO Clock is within the desired tolerance of the target frequency. Illegal Address Reset Flag — ILAF is set to 1 when an illegal address access occurs. Refer to MMC Block Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Illegal address access has not occurred. 1 Illegal address access has occurred. Oscillator Startup Status Bit — UPOSC is set when startup of the oscillator has finished successfully. The oscillator requires a startup time tUPOSC. See Electrical Characteristics for a value. Note that the Oscillator Clock can only be selected as Bus Clock source (BCLKS bit) or FLL Reference Clock (REFS bit) if UPOSC = 1. If despite enabling the Oscillator (OSCEN = 1), the UPOSC flag is not set within tUPOSC, this indicates e.g. a crystal failure. Note that the Oscillator Monitor becomes active after initial oscillator startup, that is only for UPOSC=1. UPOSC is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop mode. Writes have no effect. 0 Oscillator has not started up. Oscillator Monitor is inactive. 1 Oscillator has started up. Oscillator Monitor is active. 4 LOCKIF 3 LOCKST 2 ILAF 1 UPOSC MM912F634 Freescale Semiconductor 246 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.3.2.5 9S12I32PIMV1TRIM register (CRGTRIMH, CRGTRIML) This registers contains the trimmed value for the Internal Reference Clock Table 328. 9S12I32PIMV1 TRIM Register High Byte (CRGTRIMH) 0x0038 15 14 13 12 11 10 9 8 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM[8] F After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIREF_TRIM. Table 329. 9S12I32PIMV1 Trim Register Low Byte (CRGTRIML) 0x0039 7 6 5 4 3 2 1 0 R W Reset F F F F TRIM[7:0] F F F F After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIREF_TRIM. Read: Anytime Write: Anytime Writing the CRGTRIMH or CRGTRIML register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register. Table 330. CRGTRIMH and CRGTRIML Field Descriptions Field Description 8, 7, 6, 5, 4, 3, Trim Bits for Internal Reference Clock After System Reset, the factory programmed trim value is automatically loaded into this register, resulting in a Internal 2, 1, 0 Reference Frequency fIREF_TRIM. See Electrical Characteristics for value of fIREF_TRIM. TRIM[8:0] The TRIM[8:0] bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Decreasing the binary value in TRIM[8:0] will increase the frequency, increasing the value will decrease the frequency. Trimmed frequency must be in the allowed range for fFLLREF. See device electrical characteristics for details. 4.32.3.2.6 9S12I32PIMV1 Test Register 0 (CRGTEST0) Table 331. 9S12I32PIMV1 Test Register 0 (CRGTEST0) 0x003A 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register is reserved for factory test. This register is not writable. Read: Anytime Write: Not possible MM912F634 Freescale Semiconductor 247 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.3.2.7 9S12I32PIMV1 Test Register 1 (CRGTEST1) Table 332. 9S12I32PIMV1 Test Register 1(CRGTEST1) 0x003B 7 6 5 4 3 2 1 0 R W Reset U U U U U U U U U U U U U U U U This register is reserved for factory test. This register is not writable. Read: Anytime 4.32.4 4.32.4.1 Write: Not Possible Functional Description Startup from Reset An example of startup of clock system from Reset is given in Figure 73. System Reset IR Clock IR TRIM load trim from Flash DCO Clock MULT fDCO_MIN fDCO increasing fDCO = 40 MHz $1FF fIREF_TRIM = 32 kHz flash trim value, e.g. $100 $00 $4E2=1250, 32kHz*1250 = 40 MHz CPU reset state vector fetch, program execution tSTAB LOCKST During startup from Reset DCO Clock is the Core Clock and, divided by 2, the Bus Clock. IR Clock = Internal Reference Clock Figure 73. Example for Startup of Clock System After Reset MM912F634 Freescale Semiconductor 248 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.4.2 Stop Mode Using DCO Clock as a Bus Clock An example of what happens going into stop mode and exiting stop mode after an interrupt is shown in Figure 74. Wake-up CPU DCO Clock execution STOP instruction tSTP_REC interrupt continue execution LOCKST IR Clock runs in STOP mode only if enabled by e.g. RTI tSTAB Figure 74. Example of STOP Mode Using DCO Clock as Bus Clock 4.32.4.3 Stop Mode Using Oscillator Clock as Bus Clock An example of what happens going into stop mode and exiting stop mode after an interrupt is shown in Figure 75. Wake-up CPU Core Clock DCO Clock execution STOP instruction tSTP_REC interrupt continue execution tSTAB Oscillator Clock tUPOSC select Oscillator as Core/Bus Clock by writing bit to one BCLKS automatically cleared when going into stop mode runs in STOP mode only if enabled by e.g. RTI UPOSC IR Clock Figure 75. Example of STOP Mode Using Oscillator Clock as a Bus Clock MM912F634 Freescale Semiconductor 249 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.4.4 Enabling the External Oscillator An example of how to use the Oscillator as Bus Clock is shown in Figure 76. enable external Oscillator by writing OSCEN bit to one. OSCEN crystal/resonator starts oscillating EXTAL UPOSC flag is set upon successful start of oscillation UPOSC Oscillator Clock select Oscillator as Core/Bus Clock by writing bit to one BCLKS Core Clock DCO Clock based on DCO Clock based on Oscillator Clock tUPOSC Figure 76. Example for Enabling the External Oscillator 4.32.5 4.32.5.1 Resets General All reset sources are listed in Table 333. Refer to MCU specification for related vector addresses and priorities. Table 333. Reset Summary Reset Source Power-On Detect External pin RESET Illegal Address Access Oscillator Monitor Fail COP Watchdog time out Local Enable None None None CRGCTL0 (OSCEN = 1) see COP Block Guide MM912F634 Freescale Semiconductor 250 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.5.2 Description of Reset Operation NOTE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 256 DCO Clock cycles after the low drive is released. The reset sequence is initiated by any of the following events: • • • • • Low level is detected at the RESET pin (External Reset). Power-on is detected. Illegal Address Access is detected (see MMC Block Guide for details). COP watchdog times out. Oscillator monitor failure is detected. Upon detection of any reset event, an internal circuit drives the RESET pin low for 516 DCO Clock cycles. Depending on internal synchronization latency, it can also be 517 DCO Clock cycles (see Figure 77). Since entry into reset is asynchronous, it does not require a running DCO Clock. However, the internal reset circuit of the 9S12I32PIMV1 cannot sequence out of current reset condition without a running DCO Clock. After 516 DCO Clock cycles, the RESET pin is released. The reset generator of the 9S12I32PIMV1 waits for additional 256 DCO Clock cycles and then samples the RESET pin to determine the originating source. Table 334 shows which vector will be fetched. Table 334. Reset Vector Selection Sampled RESET Pin (256 cycles after release) 1 1 1 0 Oscillator monitor fail pending 0 1 0 X COP timeout pending 0 X 1 X Vector Fetch POR /Illegal Address Access/External pin RESET Oscillator Monitor Fail COP time out POR /Illegal Address Access/ External pin RESET The internal reset of the MCU remains asserted while the reset generator completes the 768 DCO Clock long reset sequence. In case the RESET pin is externally driven low for more than these 768 DCO Clock cycles (External Reset), the internal reset remains asserted longer. RESET )( )( S12SCRG drives RESET pin low RESET pin released DCO Clock ) ( 516 cycles ) ( 256 cycles ) ( possibly DCO Clock n ot running Figure 77. RESET Timing possibly RESET driven low externally 4.32.5.2.1 Oscillator Monitor Reset In case of loss of clock, or the oscillator frequency is below the failure assert frequency fOMFA (see device electrical characteristics for values), the 9S12I32PIMV1 generates a Oscillator Monitor Reset. MM912F634 Freescale Semiconductor 251 Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) 4.32.5.2.2 Computer Operating Properly Watchdog (COP) Reset A COP timeout will generate a reset. See COP description for details. 4.32.5.2.3 Power-On Reset The on-chip voltage POR circuitry detects when VDD to the MCU has reached a certain level and asserts a Power-on reset. 4.32.6 Interrupts The interrupts/reset vectors requested by the 9S12I32PIMV1 are listed in Table 335. Refer to MCU specification for related vector addresses and priorities. Table 335. 9S12I32PIMV1 Interrupt Vectors Interrupt Source FLL LOCK interrupt CCR Mask I bit Local Enable CRGCTL1 (LOCKIE) 4.32.6.1 4.32.6.1.1 Description of Interrupt Operation FLL Lock Interrupt The 9S12I32PIMV1 generates a FLL Lock interrupt when the lock condition (LOCKST status bit) of the FLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to zero. The FLL Lock interrupt flag (LOCKIF) is set to1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit. MM912F634 Freescale Semiconductor 252 Functional Description and Application Information External Oscillator (S12SS12SCRGV1) 4.33 4.33.1 External Oscillator (S12SS12SCRGV1) Introduction The full swing Pierce oscillator (S12SCRG) module provides a robust clock source with an external crystal or ceramic resonator. 4.33.2 Features The S12SCRG module provides the following features: • • • Full rail-to-rail (2.5 V nominal) swing oscillation with low EM susceptibility High noise immunity due to input hysteresis Low power consumption due to operation with 2.5 V (nominal) supply 4.33.3 Modes of Operation The S12SCRG contains the registers and associated bits for controlling and monitoring the oscillator module. Two modes of operation exist: 1. 2. Off (OSCEN=0) Full swing Pierce oscillator (OSCEN=1) 4.33.4 Block Diagram Figure 78 shows a block diagram of the S12SCRG module. VDD = 2.5 V Enable Oscillator Clock EXTAL XTAL Figure 78. S12SCRG Block Diagram MM912F634 Freescale Semiconductor 253 Functional Description and Application Information External Oscillator (S12SS12SCRGV1) 4.33.5 External Signals EXTAL and XTAL — Input and Output Pins NOTE Freescale recommends an evaluation of the application board, and chosen resonator or crystal, by the resonator or crystal supplier. The oscillator circuit is not suited for overtone resonators and crystals. EXTAL is the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. EXTAL C1 MCU XTAL RS* RB Crystal or Ceramic Resonator C2 * Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer’s data. Figure 79. Full Swing Pierce Oscillator Connections EXTAL MCU XTAL Do not connect Figure 80. External Connections, if S12SCRG is Unused The circuit shown in Figure 79 is recommended when using either a crystal or a ceramic resonator. If S12SCRG is not used, it is recommended to pull the EXTAL input pin to GND, as shown in Figure 80. In Off mode the XTAL output will be forced to VDD by the MCU. MM912F634 Freescale Semiconductor 254 Functional Description and Application Information Real Time Interrupt (S12SRTIV1) 4.34 4.34.1 Real Time Interrupt (S12SRTIV1) Introduction This section describes the functionality of the Real Time Interrupt module (RTI), a sub-block of the HCS12S core platform. The RTI (free running real time interrupt) enables the user to generate a hardware interrupt at a fixed periodic rate. If RTI is enabled, the interrupt will occur at the rate selected by the RTICTL and RTICNT register. The RTI counter is clocked by the internal reference clock. At the end of the RTI timeout period the RTIF flag is set to one and a new RTI timeout period starts immediately. The RTI contains two asynchronous clock domains (one for the Modulus Down Counter/Prescaler and one for the register bank). Information exchange between both clock domains is fully synchronized. Therefore modification of the RTI timeout period must be done in appliance to the write protection rules. 4.34.2 Overview A block diagram of the RTI is shown in Figure 81 bus clock . RTIRT[1:0] RTICNT-Register RTIE RTIF RTI request Int_Ref_Clock Prescaler (1, 16, 256) Modulus Down Counter (1,...., 256) Figure 81. Block Diagram 4.34.3 • • • Features Generate hardware interrupt at a fixed periodic rate Software selectable RTI operation in WAIT and STOP mode Software selectable RTI freeze during BDM active mode The RTI includes these distinctive features: 4.34.4 • Modes of Operation Run Mode If RTI functionality is required, the individual bits (RTIRT) of the associated rate select registers (RTICTL) have to be set to a non-zero value. In addition, to generate RTI requests, the RTI must be enabled (RTIE bit set). The RTI counter is stopped if all rate select bits in the RTICTL register are zero. Interrupt requests will be disabled if the corresponding bit (RTIE) is cleared. Wait mode If the respective enable bit (RTISWAI) is cleared, the RTI will continue to run, else RTI will remain frozen. Stop mode If the respective enable bit (RTIRSTP) is set, the RTI will continue to run, else RTI will remain frozen. • • 4.34.5 External Signal Description There are no external signals associated with this module. MM912F634 Freescale Semiconductor 255 Functional Description and Application Information Real Time Interrupt (S12SRTIV1) 4.34.6 4.34.6.1 Memory Map and Register Module Memory Map A summary of the registers associated with the RTI module is shown in Table 336. Table 336. RTI Register Summary Address Name W 0x003C 0x003D RTICTL RTICNT R W R W RTIF RTICNT7 RTIFRZ RTICNT6 0 WRTMASK RTICNT5 RTISWAI RTICNT4 RTIRSTP RTICNT3 RTIE RTICNT2 RTIRT1 RTICNT1 RTIRT0 RTICNT0 Bit 7 6 5 4 3 2 1 Bit 0 4.34.6.2 Register Descriptions This section describes in address order all the S12SCRG registers and their individual bits 4.34.6.2.1 RTI Control Register (RTICTL) This register controls the RTI (Real Time Interrupt). Table 337. RTI Control Register (RTICTL) 0x003C 7 6 5 4 3 2 1 0 R W Reset1 RTIF 0 RTIFRZ 0 0 WRTMASK 0 RTISWAI 0 RTIRSTP 0 RTIE 0 RTIRT1 0 RTIRT0 0 Read: Anytime Write: Refer to each bit for individual write conditions Table 338. RTICTL Field Descriptions Field 7 RTIF Description Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag is cleared by writing a 1. Writing a 0 has no effect The flag cannot be set by writing a 1. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. Real Time Interrupt Freeze — RTIFRZ controls if RTI is frozen during BDM active mode Special modes: Write anytime Normal modes: Write to “1” but not to “0” 0 RTI keeps running in BDM active mode 1 RTI frozen during BDM active mode Write Mask for RTIF, RTISWAI, RTIRSTP, RTIE and RTIRT[1:0] Bits — This write-only bit serves as a mask for bit 7 and bits 4 to 0 of the RTICTL register while writing to this register. It is intended for BDM writing the RTIFRZ without touching the contents of RTIF, RTISWAI, RTIRSTP, RTIE and RTIRT[1:0] Bits. 0 Write of RTIF, RTISWAI, RTIRSTP, RTIE and RTIRT[1:0] Bits has an effect with this write of RTICTL 1 Write of RTIF, RTISWAI, RTIRSTP, RTIE and RTIRT[1:0] Bits has no effect with this write of RTICTL. (Does not count for “write once”.) 6 RTIFRZ 5 WRTMASK MM912F634 Freescale Semiconductor 256 Functional Description and Application Information Table 338. RTICTL Field Descriptions (continued) Field 4 RTISWAI Description RTI Stops in Wait Mode Bit Normal modes: Write once Special modes: Write anytime. 0 RTI keeps running in Wait mode. 1 RTI stops and initializes the RTI counter whenever the part enters Wait mode. Real Time Interrupt (S12SRTIV1) 3 RTIRSTP RTI Runs in Stop Mode Bit Normal modes: Write once Special modes: Write anytime. 0 RTI stops in Stop mode 1 RTI continues in Stop mode Note: If the RTIRSTP bit is cleared the RTI counter will go static while in Stop mode. The RTI counter will not initialize like in Wait mode with RTISWAI bit set. Real Time Interrupt Enable Bit Write anytime. 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. RTI Interrupt Prescaler Rate Select Bits — These bits select the prescaler rate for the RTI. See Table 340., “RTI Frequency Divide Rates“ for selectable ratios in conjunction with RTICNT[7:0] counter select bits Write anytime in appliance of the write protection rules (see 4.34.7.1, “RTI register write protection rules“). 2 RTIE 1–0 RTIRT[1:0] 4.34.6.2.2 RTI Counter select bits (RTICNT) This register is used to restart the RTI time-out period. Table 339. RTICNT Register Diagram 0x003D 7 6 5 4 3 2 1 0 R W Reset RTICNT7 0 RTICNT6 0 RTICNT5 0 RTICNT4 0 RTICNT3 0 RTICNT2 0 RTICNT1 0 RTICNT0 0 Read: Anytime Write: Anytime in appliance of the write protection rules (see 4.34.7.1, “RTI register write protection rules“) When the RTI is turned on the RTIF bit can be set with the following rates: Table 340. RTI Frequency Divide Rates RTIRT[1:0] = RTICNT[7:0] 00 (OFF) OFF(178) OFF OFF OFF .... OFF 01 (1) OFF 2x1 3x1 4x1 .... 255x1 10 (16) 16 2x16 3x16 4x16 .... 255x16 11 (256) 256 2x256 3x256 4x256 .... 255x256 0000 0000 (÷1) 0000 0001 (÷2) 0000 0010 (÷3) 0000 0011 (÷4) ...... 1111 1110 (÷255) MM912F634 Freescale Semiconductor 257 Functional Description and Application Information Table 340. RTI Frequency Divide Rates (continued) RTIRT[1:0] = RTICNT[7:0] 00 (OFF) OFF 01 (1) 256x1 10 (16) 256x16 Real Time Interrupt (S12SRTIV1) 11 (256) 256x256 1111 1111 (÷256) Note: 178. Denotes the default value out of reset.This value disable the RTI. 4.34.7 Functional Description The S12SCRG generates a real time interrupt when the selected interrupt time period elapses. The interrupt period is selected by the RTICTL and RTICNT register (see Table 340). RTI interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to 1 when a time-out occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during Stop mode if the RTIRSTP bit is set. This feature can be used for periodic wake-up from Stop if the RTI interrupt is enabled. Also the RTI continues to run during Wait mode if the RTISWAI bit is cleared. This feature can be used for periodic wake-up from Wait if the RTI interrupt is enabled. If the RTIFRZ bit of the RTICTL register is set the RTI timer is frozen during BDM active mode. Modifying the RTI registers that way that the Frequency Divider Rate changes from OFF condition to any time-out period immediately starts the RTI counter with a full period. When the RTIRT bits are written to modify the current time-out period while the RTI counter is running the new value will be loaded into the Prescaler at the end of the current time-out period. Also when the RTICNT register gets modified while the RTI counter is running the new RTICNT values will be loaded into the Modulus Down Counter at the end of the current RTI period. Hence, frequent modification of the RTIRT bits and RTICNT register faster than the actual selected time-out period will result in ignored values and only the value available at current time-out will be loaded for the next time-out period. The RTI Modulus Down Counter and Prescaler are clocked by the internal reference clock other than the RTI registers which are clocked with the internal bus clock. Both clocks are asynchronous and information exchange between these two clock domains is synchronized. Please refer to the SoC Guide for more information regarding these clocks and see 4.34.7.1, “RTI register write protection rules“ and 4.34.7.2, “Modification of Prescaler rate (RTIRT bits)“ and 4.34.7.3, “Modification of Modulus Down Counter rate (RTICNT register)“ for RTI register access rules. 4.34.7.1 RTI register write protection rules As mentioned, the RTI registers and RTI counter are running on two different asynchronous clock domains. Therefore there is a synchronization delay when modifying the registers with regard to time-out period until the modification takes affect. The synchronization delay is typically three clock cycles on the counter clock domain and two clock cycles on the register clock domain. This means that it takes three cycles in the clock domain of the RTI counter (internal reference clock) to receive the modified time-out values and two cycles in the RTI register clock domain (bus clock) to receive the time-out flag from the counter in the register. Also a write access to the RTICNT register locks this register and a write access to the RTICTL register locks the RTIRT bits against further write accesses for three internal reference clock cycles plus two bus clock cycles after the write access occurred, which is due to synchronization. Therefore modifying the RTICNT register or RTIRT bits faster than they are synchronized results in ignored values. In general it should be avoided to access both registers in a single word access if only one of the registers should be modified. 4.34.7.2 Modification of Prescaler rate (RTIRT bits) Applications which modify the Frequency Divider Rate by modifying the RTIRT bits (Prescaler rate) in the RTICTL register should follow below recommendations. MM912F634 Freescale Semiconductor 258 Functional Description and Application Information Real Time Interrupt (S12SRTIV1) If the Frequency Divider Rate is set lower or equal to three the RTI interrupt service routine will access the RTICTL register with in a timing window which is less or equal the synchronization delay. Hence the interrupt service routine which access the RTICTL register to clear the RTIF bit is executed such frequently that the RTIRT bits are permanently locked. Therefore the following sequence is recommended if RTIRT bits should be changed for a current selected Frequency Divider Rate of two or three: • • • - Access the RTICTL register to clear the RTI interrupt flag (RTIF bit) and disable the RTI interrupt (clear RTIE bit) by a single write access. - Execute a software loop in which the RTICTL register is written to modify the RTIRT bits until the new Frequency Divider Rate is taken (read back value of RTIRT bits equals new value) - Access RTICTL register to enable RTI interrupts again. If the actual Frequency Divider Rate of the RTI is set to a rate higher than three the write access to clear the interrupt flag (RTIF bit) in the RTICTL register can be used to modify the RTIRT bits of the RTICTL register. 4.34.7.3 Modification of Modulus Down Counter rate (RTICNT register) Applications which frequently access the RTICNT register should follow below recommendations. If the RTICNT register is accessed with in a timing window which is less or equal the synchronization delay the following sequence is recommended: • • • - Access the RTICTL register to clear the RTI interrupt flag (RTIF bit) and disable the RTI interrupt (clear RTIE bit) by a single write access. - Execute a software loop in which the RTICNT register is written to modify the rate until the new Frequency Divider Rate is taken (read back value of RTICNT bits equals new value) - Access RTICTL register to enable RTI interrupts again. If the RTICNT register is accessed in a timing window which is higher than the synchronization delay, only the RTICNT register needs to be written and wait until next time-out occurs. MM912F634 Freescale Semiconductor 259 Functional Description and Application Information Computer Operating Properly (S12SCOPV1) 4.35 4.35.1 Computer Operating Properly (S12SCOPV1) Introduction This section describes the functionality of the Computer Operating Properly module (COP), a sub-block of the HCS12S core platform.The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. If the COP times out a system reset is initiated. Two types of COP operation are available: Window COP or Normal COP When COP is enabled, sequential writes of $55 and $AA (in this order) are expected to the ARMCOP register during the selected timeout period. Once this is done, the COP timeout period restarts. If the program fails to do this the S12SCRG will initiate a reset. 4.35.1.1 Overview A block diagram of the COP is shown in Figure 81 SSC_Mode CR[2:0] ARMCOP-Register WCOP Control Logic Int_Ref_Clock COP reset request Modulus Down Counter (26,..., 216) Figure 82. Block Diagram 4.35.1.2 • • • • • Features The COP includes these distinctive features: Watchdog timer with a timeout clear window. Default maximum COP rate and no Window COP in Special Single Chip mode after system reset. Auto COP rate load after system reset in SoC Normal mode. (For source of COP rate bits please refer to the Device User Guide) Software selectable COP operation in WAIT and STOP mode. Customer selectable COP off while BDM active (debugging session). MM912F634 Freescale Semiconductor 260 Functional Description and Application Information Computer Operating Properly (S12SCOPV1) 4.35.1.3 • Modes of Operation • • Run mode If COP functionality is required, the individual bits of the associated rate select registers (COPCTL) have to be set to a non-zero value. The COP is stopped if all rate select bits are zero. Wait mode If the respective enable bit (COPSWAI) is cleared, the COP will continue to run, else COP remains frozen. Stop mode If the respective enable bit (COPRSTP) is set, the COP will continue to run, else COP remains frozen. 4.35.2 External Signal Description There are no external signals associated with this module. 4.35.3 4.35.3.1 Memory Map and Register Module Memory Map A summary of the registers associated with the COP module is shown in Table 336. Table 341. COP Register Summary Address 0x003E 0x003F Name COPCTL ARMCOP R W R W Bit 7 WCOP 0 Bit 7 6 RSBCK 0 Bit 6 5 0 WRTMASK 0 Bit 5 4 COPSWAI 0 Bit 4 3 COPRSTP 0 Bit 3 2 CR2 0 Bit 2 1 CR1 0 Bit 1 Bit 0 CR0 0 Bit 0 4.35.3.2 Register Descriptions This section describes in address order all the S12SCRG registers and their individual bits MM912F634 Freescale Semiconductor 261 Functional Description and Application Information Computer Operating Properly (S12SCOPV1) 4.35.3.2.1 COP Control Register (COPCTL) This register controls the COP (Computer Operating Properly) watchdog. Table 342. COP Control Register (COPCTL) 0x003E 7 6 5 4 3 2 1 0 R W Reset(179) WCOP see note RSBCK 0 0 WRTMASK 0 COPSWAI 0 COPRSTP 0 CR2 see note CR1 see note CR0 see note Note: 179. Refer to Device User Guide (Section 4.35.4.1, “COP Configuration") for reset values of WCOP, CR2, CR1 and CR0. Read: Anytime Write: 1. 2. RSBCK: anytime in special modes; write to “1” but not to “0” in all other modes WCOP, CR2, CR1, CR0: — Anytime in special modes — Write once in all other modes – Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. – Writing WCOP to “0” has no effect, but counts for the “write once” condition. The COP timeout period is restarted if one these two conditions are true: 1. 2. Writing a non-zero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0. or Changing RSBCK bit from “0” to “1”. Table 343. COPCTL Field Descriptions Field 7 WCOP Description Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, $55 can be written as often as desired. Once $AA is written after the $55, the timeout logic restarts and the user must wait until the next window before writing to ARMCOP. Table 344 shows the duration of this window for the seven available COP rates. 0 Normal COP operation 1 Window COP operation COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in Active BDM mode. 1 Stops the COP and RTI counters whenever the part is in Active BDM mode. Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP, CR[2:0], COPSWAI and COPRSTP bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of WCOP, CR[2:0], COPSWAI, and COPRSTP. 0 Write of WCOP, CR[2:0], COPSWAI and COPRSTP has an effect with this write of COPCTL 1 Write of WCOP, CR[2:0], COPSWAI and COPRSTP has no effect with this write of COPCTL. (Does not count for “write once”) COP Stops in Wait mode bit Normal modes: Write once Special modes: Write anytime 0 COP continues in Wait mode. 1 COP stops and initializes the COP counter whenever the part enters Wait mode. 6 RSBCK 5 WRTMASK 4 COPSWAI MM912F634 Freescale Semiconductor 262 Functional Description and Application Information Table 343. COPCTL Field Descriptions (continued) Field 3 COPRSTP Description Computer Operating Properly (S12SCOPV1) COP Runs in Stop Mode Bit Normal modes: Write once Special modes: Write anytime 0 COP stops in Stop mode 1 COP continues in Stop mode Note: If the COPRSTP bit is cleared the COP counter will go static while in Stop mode. The COP counter will not initialize like in Wait mode with COPSWAI bit set. COP Watchdog Timer Rate Select Bits — These bits select the COP timeout rate (see Table 344). Writing a non-zero value to CR[2:0] enables the COP counter and starts the timeout period. A COP counter timeout causes a system reset. This can be avoided by periodically (before timeout) re-initialize the COP counter via the ARMCOP register. While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest timeout period (216 cycles) in normal COP mode (Window COP mode disabled): 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in special mode 2–0 CR[2:0] Table 344. COP Watchdog Rates(180) CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 Input_CLK Cycles to Timeout COP disabled 26 28 210 212 214 215 216 Note: 180. Refer to Device User Guide (Section 4.35.4.1, “COP Configuration") for reset values of WCOP, CR2, CR1 and CR0. MM912F634 Freescale Semiconductor 263 Functional Description and Application Information Computer Operating Properly (S12SCOPV1) 4.35.3.2.2 COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP timeout period. Table 345. ARMCOP Register Diagram 0x003F 7 6 5 4 3 2 1 0 R W Reset 0 Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 Read: Always reads $00 Write: Anytime When the COP is disabled (CR[2:0] = “000”), writing to this register has no effect. When the COP is enabled by setting CR[2:0] non-zero, the following applies: Writing any value other than $55 or $AA causes a COP reset. To restart the COP timeout period, you must write $55 followed by a write of $AA. Other instructions may be executed between these writes, but the sequence ($55, $AA) must be completed prior to the COP end of timeout period to avoid a COP reset. Sequences of $55 writes or sequences of $AA writes are allowed if the WCOP bit is not set. When the WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected timeout period. Writing any value in the first 75% of the selected period will cause a COP reset. Only sequences of $55 are allowed if the WCOP bit is set. 4.35.4 Functional Description The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out, it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated. The COP runs on the CRG internal reference clock. Three control bits in the COPCTL register allow a selection of seven COP timeout periods. When COP is enabled, the program must write $55 and $AA (in this order) to the ARMCOP register during the selected timeout period. Once this is done, the COP timeout period is restarted. If the program fails to do this and the COP times out, the part will reset. Also, if any value other than $55 or $AA is written, the part is immediately reset.Sequences of $55 writes or sequences of $AA writes are allowed if the WCOP bit is not set. The window COP operation is enabled by setting WCOP in the COPCTL register. When the WCOP bit is set while COP is enabled, a write to the ARMCOP register must occur in the last 25% of the selected period. A premature write will immediately reset the part. As long as all writes occur during the 25% window, $55 can be written as often as desired. Once $AA is written after the $55, the timeout logic restarts, and the user must wait until the next window before writing to the ARMCOP register. If the COPRSTP bit is set, the COP will continue to run in Stop mode. The COP continues to run during Wait mode if the COPSWAI bit is cleared. MM912F634 Freescale Semiconductor 264 Functional Description and Application Information Computer Operating Properly (S12SCOPV1) 4.35.4.1 COP Configuration NOTE If the MCU is secured and being started in special single chip mode, the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP reset. The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash register FOPT. See Table 346 and Table 347 for coding. The FOPT register is loaded from the Flash configuration field byte at the global address $03_FF0E during the reset sequence. Table 346. Initial COP Rate Configuration NV[2:0] in FCTL Register 000 001 010 011 100 101 110 111 CR[2:0] in COPCTL Register 111 110 101 100 011 010 001 000 Table 347. Initial WCOP Configuration NV[3] in FCTL Register 1 0 WCOP in COPCTL Register 0 1 MM912F634 Freescale Semiconductor 265 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36 4.36.1 32 kbyte Flash Module (S12SFTSR32KV1) Introduction This document describes the S12SFTSR32K module, that includes a 32 kbyte Flash (nonvolatile) memory. CAUTION A Flash block address must be in the erased state before being programmed. Cumulative programming of bits within a Flash block address is not allowed, except for status field updates required in EEPROM emulation applications. The Flash memory is ideal for single-supply applications, allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. Array read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is not possible to read from a Flash block while any command is executing on that specific Flash block. 4.36.1.1 Glossary Command Write Sequence — A three step MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. Flash Array — The Flash array constitutes the main memory portion of a Flash block. Flash Block — An analog block consisting of the Flash array and Flash IFR with supporting high voltage and parametric test circuitry. Flash IFR — Nonvolatile information memory, consisting of 128 bytes, located in the Flash block outside of Flash main memory. Refer to the SoC Guide on how to make the Flash IFR visible in the global memory map. 4.36.1.2 • • • • • • • • • Features 32 kbytes of Flash memory comprised of one 32 kbyte block divided into 64 sectors of 512 bytes Nonvolatile information memory (Flash IFR) comprised of one 128 byte block Automated program and erase algorithm Interrupt on Flash command completion, command buffer empty Fast program and sector erase operation Burst program command for faster Flash array program times Flexible protection scheme to prevent accidental program or erase Single power supply for all Flash operations including program and erase Security feature to prevent unauthorized access to the Flash memory MM912F634 Freescale Semiconductor 266 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.1.3 Block Diagram A block diagram of the Flash module is shown in Figure 83. Flash Interface Flash Memory Controller Flash IFR 64 * 16 Bits Flash Array 16K * 16 Bits sector 0 sector 1 Command Interrupt Request Registers Protection sector 63 Security Figure 83. S12SFTSR32K Block Diagram 4.36.2 External Signal Description The Flash module has no external signals. MM912F634 Freescale Semiconductor 267 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.3 Memory Map and Register Definition This section describes the Flash array map, Flash IFR map, and Flash register map shown in Figure 84. 4.36.3.1 Flash Array Map The MCU memory map places the Flash array addresses between Flash array base + 0x0000 and 0x7FFF. FLASH REGISTER BASE + 0x0000 FLASH REGISTER BASE + 0x000F FLASH IFR BASE + 0x0000 FLASH IFR BASE + 0x007F FLASH ARRAY BASE + 0x0000 Flash IFR 128 bytes Flash Registers 16 bytes Flash Array 32 kbytes FLASH ARRAY BASE + 0x7FFF Flash Configuration Field 16 bytes (+0x7F00 to +0x7F0F) Figure 84. Flash Memory Map 4.36.3.1.1 Flash Configuration Field Description During the reset sequence, the contents of the 16 byte Flash configuration field are read to set Flash memory protection and Flash security features. The Flash configuration field starts at Flash array base + 0x7F00, as shown in Table 348. Table 348. Flash Configuration Field Address Relative to Flash Array Base 0x7F00 - 0x7F07 0x7F08 - 0x7F0C 0x7F0D Size (bytes) 8 5 1 Description Backdoor Key Refer to Section 4.36.6.1, “Unsecuring the MCU Using Backdoor Key Access"” Reserved Flash Protection byte Refer to Section 4.36.3.3.5, “Flash Protection Register (FPROT)"” MM912F634 Freescale Semiconductor 268 Functional Description and Application Information Table 348. Flash Configuration Field (continued) Address Relative to Flash Array Base 0x7F0E 0x7F0F Size (bytes) 1 1 Flash Nonvolatile byte Refer to the SoC Guide 32 kbyte Flash Module (S12SFTSR32KV1) Description Flash Security byte Refer to Section 4.36.3.3.2, “Flash Security Register (FSEC)"” 4.36.3.2 Flash IFR Map The Flash IFR is a 128 byte nonvolatile information memory that is read accessible as defined in the SoC Guide. The MCU memory map places the Flash IFR addresses between Flash IFR base + 0x0000 and 0x007F as shown in Table 349. Table 349. Flash IFR Description Address Relative to Flash IFR Base(181) 0x0000 - 0x000D 0x000E - 0x003F 0x0040 - 0x004F 0x0050 - 0x007B 0x007C - 0x007F Size (bytes) 14 50 16 44 4 Description Wafer lot number, wafer number, X coordinate, Y coordinate Reserved for wafer test data Flash memory controller parameters Reserved MCU control parameters Note: 181. Refer to the SoC Guide for details on how to enable the Flash IFR 4.36.3.3 Register Descriptions The Flash module contains a set of 16 control and status registers located between Flash register base + 0x0000 and 0x000F. Flash registers are byte and word accessible. A summary of the Flash module registers is given in Table 350. Detailed descriptions of each register bit are provided in the following sections. Table 350. S12SFTSR32K Register Summary (Normal/Special Mode) Register Name 0x0100 FCLKDIV 0x0101 FSEC 0x0102 FRSV0 0x0103 FCNFG 0x0104 FPROT 0x0105 FSTAT 0x0106 FCMD R W R W R W R W R W R W R W CBEIE FPHS4 CBEIF 0 CCIE FPHS3 CCIF KEYACC FPHS2 PVIOL CMDB5 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 FDIVLD KEYEN1 6 PRDIV8 KEYEN0 5 FDIV5 0 4 FDIV4 0 3 FDIV3 0 2 FDIV2 0 1 FDIV1 SEC1 Bit 0 FDIV0 SEC0 FPHS1 ACCERR CMDB4 FPHS0 0 FPLS2 BLANK FPLS1 0 FPLS0 0 CMDB6 CMDB3 CMDB2 CMDB1 CMDB0 MM912F634 Freescale Semiconductor 269 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) Table 350. S12SFTSR32K Register Summary (Normal/Special Mode) (continued) Register Name 0x0107 FRSV1 0x0108 FADDRHI 0x0109 FADDRLO 0x010A FDATAHI 0x010B FDATALO 0x010C FRSV2 0x010D FRSV3 0x010E FRSV4 0x010F FRSV5 R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAB7 FD15 FD7 0 0 FAB6 FD14 FD6 0 0 0 0 FAB13 0 FAB5 FD13 FD5 0 0 FAB12 0 FAB4 FD12 FD4 0 0 FAB11 0 FAB3 FD11 FD3 0 0 FAB10 0 FAB2 FD10 FD2 0 0 FAB9 0 FAB1 FD9 FD1 0 0 FAB8 0 FAB0 FD8 FD0 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 4.36.3.3.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control the length of timed events in program and erase algorithms executed by the Flash memory controller. Table 351. Flash Clock Divider Register (FCLKDIV) 0x0100 7 6 5 4 3 2 1 0 R W Reset FDIVLD 0 PRDIV8 0 0 0 0 FDIV[5:0] 0 0 0 All bits in the FCLKDIV register are readable and writable with restrictions, as determined by the value of FDIVLD when writing to the FCLKDIV register (see Table 352). Table 352. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Load Control — When writing to the FCLKDIV register for the first time after a reset, the value of the FDIVLD bit written controls the future ability to write to the FCLKDIV register: 0 Writing a 0 to FDIVLD locks the FCLKDIV register contents; all future writes to FCLKDIV are ignored. 1 Writing a 1 to FDIVLD keeps the FCLKDIV register writable; next write to FCLKDIV is allowed. When reading the FCLKDIV register, the value of the FDIVLD bit read indicates the following: 0 FCLKDIV register has not been written to since the last reset. 1 FCLKDIV register has been written to since the last reset. MM912F634 Freescale Semiconductor 270 Functional Description and Application Information Table 352. FCLKDIV Field Descriptions (continued) Field 6 PRDIV8 5:0 FDIV[5:0] Description Enable Prescaler by 8. 0 The bus clock is directly fed into the clock divider. 1 The bus clock is divided by 8 before feeding into the clock divider. 32 kbyte Flash Module (S12SFTSR32KV1) Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the bus clock down to a frequency of 150 to 200 kHz. The minimum divide ratio is 2 (PRDIV8 = 0, FDIV = 0x01) and the maximum divide ratio is 512 (PRDIV8 = 1, FDIV = 0x3F). Refer to Section 4.36.4.1.1, “Writing the FCLKDIV Register"” for more information. 4.36.3.3.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Table 353. Flash Security Register (FSEC) 0x0101 7 6 5 4 3 2 1 0 R W Reset F KEYEN[1:0] F 0 0 0 0 0 0 0 0 F SEC[1:0] F All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash configuration field (see Section 4.36.3.1.1) during the reset sequence, indicated by F in Table 353. Table 354. FSEC Field Descriptions Field 7:6 KEYEN[1:0] 1:0 SEC[1:0] Description Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the Flash module as shown in Table 355. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 356. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to the unsecured state. Table 355. Flash KEYEN States KEYEN[1:0] 00 01(182) 10 11 Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED Note: 182. Preferred KEYEN state to disable Backdoor Key Access. Table 356. Flash Security States SEC[1:0] 00 01(183) 10 Status of Security SECURED SECURED UNSECURED Note: 183. Preferred SEC state to set MCU to secured state. MM912F634 Freescale Semiconductor 271 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) The security feature in the Flash module is described in Section 4.36.6, “Flash Module Security"”. 4.36.3.3.3 Flash Reserved0 Register (FRSV0) The FRSV0 register is reserved for factory testing. Table 357. Flash Reserved0 Register (FRSV0) 0x0102 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All bits in the FRSV0 register read 0 and are not writable. 4.36.3.3.4 Flash Configuration Register (FCNFG) NOTE Flash array reads are allowed while KEYACC is set. The FCNFG register enables the Flash interrupts and gates the security backdoor writes. Table 358. Flash Configuration Register (FCNFG) 0x0103 7 6 5 4 3 2 1 0 R W Reset CBEIE 0 CCIE 0 KEYACC 0 0 0 0 0 0 0 0 0 0 0 CBEIE, CCIE, and KEYACC bits are readable and writable, while all remaining bits read 0 and are not writable. KEYACC is only writable if KEYEN is set to the enabled state (see Section 4.36.3.3.2, “Flash Security Register (FSEC)"”. Table 359. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”) is set. Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the Flash module. 0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”) is set. Enable Security Key Writing 0 Writes to the Flash block are interpreted as the start of a command write sequence. 1 Writes to the Flash block are interpreted as keys to open the backdoor. 6 CCIE 5 KEYACC MM912F634 Freescale Semiconductor 272 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.3.3.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase operations. Table 360. Flash Protection Register (FPROT) 0x0104 7 6 5 4 3 2 1 0 R W Reset F F FPHS[4:0] F F F F FPLS[2:0] F F In Normal mode, FPROT bits are readable and writable as long as the size of the protected Flash memory is being increased. Any write to FPROT that attempts to decrease the size of the protected Flash memory will be ignored. In special mode, FPROT bits are readable and writable without restrictions. During the reset sequence, the FPROT register is loaded from the Flash protection byte in the Flash configuration field (see Section 4.36.3.1.1). To change the Flash protection that will be loaded during the reset sequence, the Flash sector containing the Flash configuration field must be unprotected, then the Flash protection byte must be reprogrammed. Trying to alter data in any protected area in the Flash memory will result in a protection violation error, and the PVIOL flag will be set in the FSTAT register. The mass erase of the Flash array is not possible if any of the Flash sectors contained in the Flash array are protected. Table 361. FPROT Field Descriptions Field 7:3 FPHS[4:0] 2:0 FPLS[2:0] Description Flash Protection Higher Address Size — The FPHS bits determine the size of the protected higher Flash address range as shown in Table 362. Flash Protection Lower Address Size — The FPLS bits determine the size of the protected lower Flash address range as shown in Table 363. Table 362. Flash Protection Higher Address Range FPHS[4:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D Protected Address Range Relative to Flash Array Base 0x0400–0x7FFF 0x0800–0x7FFF 0x0C00–0x7FFF 0x1000–0x7FFF 0x1400–0x7FFF 0x1800–0x7FFF 0x1C00–0x7FFF 0x2000–0x7FFF 0x2400–0x7FFF 0x2800–0x7FFF 0x2C00–0x7FFF 0x3000–0x7FFF 0x3400–0x7FFF 0x3800–0x7FFF Protected Size 31 kbytes 30 kbytes 29 kbytes 28 kbytes 27 kbytes 26 kbytes 25 kbytes 24 kbytes 23 kbytes 22 kbytes 21 kbytes 20 kbytes 19 kbytes 18 kbytes MM912F634 Freescale Semiconductor 273 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) Table 362. Flash Protection Higher Address Range (continued) FPHS[4:0] 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Protected Address Range Relative to Flash Array Base 0x3C00–0x7FFF 0x4000–0x7FFF 0x4400–0x7FFF 0x4800–0x7FFF 0x4C00–0x7FFF 0x5000–0x7FFF 0x5400–0x7FFF 0x5800–0x7FFF 0x5C00–0x7FFF 0x6000–0x7FFF 0x6400–0x7FFF 0x6800–0x7FFF 0x6C00–0x7FFF 0x7000–0x7FFF 0x7400–0x7FFF 0x7800–0x7FFF 0x7C00–0x7FFF No Higher Protection Protected Size 17 kbytes 16 kbytes 15 kbytes 14 kbytes 13 bytes 12 bytes 11 bytes 10 bytes 9.0 kbytes 8.0 kbytes 7.0 kbytes 6.0 kbytes 5.0 kbytes 4.0 kbytes 3.0 kbytes 2.0 kbytes 1.0 kbyte 0 kbytes Table 363. Flash Protection Lower Address Range FPLS[2:0] 000 001(185) 010(185) 011 100 101 110 111 Protected Address Range Relative to Flash Array Base 0x0000–0x7FFF (185) (185) Protected Size 32 kbytes(184) (185) (185) 0x0000–0x0FFF 0x0000–0x0BFF 0x0000–0x07FF 0x0000–0x03FF No Lower Protection 4.0 kbytes 3.0 kbytes 2.0 kbytes 1.0 kbyte 0 kbytes Note: 184. Flash memory fully protected. 185. Reserved for future use. If written, these FPLS values will be treated the same as FPLS = 000. MM912F634 Freescale Semiconductor 274 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.3.4 Flash Status Register (FSTAT) The FSTAT register defines the operational status of the Flash module. Table 364. Flash Status Register (FSTAT - Normal Mode) 0x0105 7 6 5 4 3 2 1 0 R W Reset CBEIF 1 CCIF 1 PVIOL 0 ACCERR 0 0 0 BLANK 0 0 0 0 0 Table 365. Flash Status Register (FSTAT - Special Mode) 0x0105 7 6 5 4 3 2 1 0 R W Reset CBEIF 1 CCIF 1 PVIOL 0 ACCERR 0 0 0 BLANK 0 FAIL 0 0 0 In normal mode, CCIF, PVIOL, and ACCERR are readable and writable. CCIF and BLANK are readable and not writable. The remaining bits read 0 and are not writable. In special mode, BLANK and FAIL are readable and writable. FAIL must be clear when starting a command write sequence. Table 366. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the command buffer is empty so that a new command write sequence can be started when performing burst programming. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned address to the Flash array memory, but before CBEIF is cleared, will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is cleared by writing a 1 to CBEIF. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 92). 0 Command buffers are full. 1 Command buffers are ready to accept a new command. Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active program command completes, and a pending burst program command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 92). 0 Command in progress. 1 All commands are completed. Protection Violation Flag —The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the Flash memory or Flash IFR during a command write sequence. Writing a 0 to the PVIOL flag has no effect on PVIOL. The PVIOL flag is cleared by writing a 1 to PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected. 1 Protection violation has occurred. Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the Flash memory or Flash IFR, caused by either a violation of the command write sequence (see Section 4.36.4.1.2, “Command Write Sequence"”), issuing an illegal Flash command (see Table 369), or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). Writing a 0 to the ACCERR flag has no effect on ACCERR. The ACCERR flag is cleared by writing a 1 to ACCERR.While ACCERR is set, it is not possible to launch a command or start a command write sequence. 0 No access error detected. 1 Access error has occurred. 6 CCIF 5 PVIOL 4 ACCERR MM912F634 Freescale Semiconductor 275 Functional Description and Application Information Table 366. FSTAT Field Descriptions (continued) Field 2 BLANK Description 32 kbyte Flash Module (S12SFTSR32KV1) Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK except in special mode where the BLANK flag can be cleared by writing a 1 to BLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased. Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (Flash block verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. 0 Flash operation completed without error. 1 Flash operation failed. 1 FAIL 4.36.3.4.1 Flash Command Register (FCMD) The FCMD register is the Flash command register. Table 367. Flash Command Register (FCMD) 0x0106 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 CMDB[6:0] 0 0 0 0 All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 368. FCMD Field Descriptions Field 6:0 CMDB[6:0] Description Flash Command — Valid Flash commands in normal mode are shown in Table 369. Writing any command other than those listed in Table 369 in normal mode sets the ACCERR flag in the FSTAT register. Table 369. Valid Flash Command List CMDB[6:0] 0x05 0x20 0x25 0x40 0x41 NVM Command Erase Verify Program Burst Program Sector Erase Mass Erase MM912F634 Freescale Semiconductor 276 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.3.4.2 Flash Reserved1 Register (FRSV1) The FRSV1 register is reserved for factory testing. Table 370. Flash Reserved1 Register (FRSV1) 0x0107 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All FRSV1 bits read 0 and are not writable. 4.36.3.4.3 Flash Address Registers (FADDR) NOTE The LSB of the MCU global address is not stored in the FADDR registers, since the Flash block is not byte addressable. The FADDR registers are the Flash address registers. Table 371. Flash Address High Register (FADDRHI - Normal Mode) 0x0108 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 372. Flash Address Low Register (FADDRLO - Normal Mode) 0x0109 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 373. Flash Address High Register (FADDRHI - Special Mode) 0x0108 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 FAB[13:8] 0 0 0 Table 374. Flash Address Low Register (FADDRLO - Special Mode) 0x0109 7 6 5 4 3 2 1 0 R W FAB[7:0] MM912F634 Freescale Semiconductor 277 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) Table 374. Flash Address Low Register (FADDRLO - Special Mode) (continued) Reset 0 0 0 0 0 0 0 0 All FADDR bits read 0 and are not writable in normal mode. All assigned FADDR bits are readable and writable in special mode. 4.36.3.4.4 Flash Data Registers (FDATA) The FDATA registers are the Flash data registers. Table 375. Flash Data High Register (FDATAHI - Normal Mode) 0x010A 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 376. Flash Data Low Register (FDATALO - Normal Mode) 0x010B 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 377. Flash Data High Register (FDATAHI - Special Mode) 0x010A 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FD[15:8] 0 0 0 0 Table 378. Flash Data Low Register (FDATALO - Special Mode) 0x010B 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FD[7:0] 0 0 0 0 All FDATA bits read 0 and are not writable in normal mode. All FDATA bits are readable and writable in special mode. The FDATA bits are indirectly written to when writing to an address within the Flash block, as part of a command write sequence. MM912F634 Freescale Semiconductor 278 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.3.4.5 Flash Reserved2 Register (FRSV2) The FRSV32 register is reserved for factory testing. Table 379. Flash Reserved2 Register (FRSV2) 0x010C 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All FRSV32 bits read 0 and are not writable. 4.36.3.4.6 Flash Reserved3 Register (FRSV3) The FRSV3 register is reserved for factory testing. Table 380. Flash Reserved3 Register (FRSV3) 0x010D 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All FRSV3 bits read 0 and are not writable. 4.36.3.4.7 Flash Reserved4 Register (FRSV4) The FRSV4 register is reserved for factory testing. Table 381. Flash Reserved4 Register (FRSV4) 0x010E 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All FRSV4 bits read 0 and are not writable. MM912F634 Freescale Semiconductor 279 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.3.4.8 Flash Reserved5 Register (FRSV5) The FRSV5 register is reserved for factory testing. Table 382. Flash Reserved5 Register (FRSV5) 0x010F 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All FRSV5 bits read 0 and are not writable. 4.36.4 4.36.4.1 Functional Description Flash Command Operations Flash command operations are used to execute program, erase, and erase verify algorithms described in this section. The program and erase algorithms are controlled by the Flash memory controller whose time base, FCLK, is derived from the bus clock via a programmable divider. The next sections describe: 1. 2. 3. 4. How to write the FCLKDIV register to set FCLK Command write sequences to program, erase, and erase verify operations on the Flash memory Valid Flash commands Effects resulting from illegal Flash command write sequences or aborting Flash operations 4.36.4.1.1 Writing the FCLKDIV Register NOTE The values loaded into the FCLKDIV register are different that those loaded into the FCLKDIV register on prior S12 Flash modules, as they were based on the oscillator frequency. Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the bus clock down to within the 150 to 200 kHz range. If we define: • • FCLK as the clock of the Flash timing control block INT(x) as taking the integer part of x (e.g. INT(4.323) = 4) then FCLKDIV bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 85. For example, if the bus clock frequency is 20 MHz, FCLKDIV bits FDIV[5:0] should be set to 0x0C (001100), and bit PRDIV8 set to 1. The resulting FCLK frequency is then 192 kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target by: (200 - 192)/200 = 4% Eqn. 1 MM912F634 Freescale Semiconductor 280 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) CAUTION Program and erase command execution time will increase proportionally with the period of FCLK. Programming or erasing the Flash memory with FCLK < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash memory due to overstress. Setting FCLKDIV to a value such that FCLK > 200 kHz can result in incomplete programming or erasure of the Flash memory cells. If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. START PRDIV8 = 0 (reset) bus_clock 0.3 MHz? no bus_clock 12.8 MHz? yes set PRDIV8=1 PRDCLK = bus_clock/8 yes ALL PROGRAM AND ERASE COMMANDS IMPOSSIBLE no PRDCLK = bus_clock PRDCLK[kHz]/200 an integer? yes set FDIV[5:0] = PRDCLK[kHz]/200-1 no set FDIV[5:0] = INT(PRDCLK[kHz]/200) FCLK = (PRDCLK)/(1+FDIV[5:0]) END Figure 85. Determination Procedure for PRDIV8 and FDIV Bits MM912F634 Freescale Semiconductor 281 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, and erase verify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear and the CBEIF flag must be set (see Section 4.36.3.4). A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. 2. 3. Write to a valid address in the Flash array memory. Write a valid command to the FCMD register. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register with an interrupt generated, if enabled. The CCIF flag will set upon completion of all active and buffered burst program commands. 4.36.4.2 Flash Commands CAUTION A Flash block address must be in the erased state before being programmed. Cumulative programming of bits within a Flash block address is not allowed except for the status field updates required in EEPROM emulation applications. Table 383 summarizes the valid Flash commands along with the effects of the commands on the Flash block. Table 383. Flash Command Description FCMDB 0x05 0x20 0x25 0x40 0x41 0x75 NVM Command Erase Verify Program Burst Program Sector Erase Mass Erase Function on Flash Memory Verify all memory bytes in the Flash array memory are erased. If the Flash array memory is erased, the BLANK flag in the FSTAT register will set upon command completion. Program an address in the Flash array. Program an address in the Flash array with the internal address incrementing after the program operation. Erase all memory bytes in a sector of the Flash array. Erase all memory bytes in the Flash array. A mass erase of the full Flash array is only possible when no protection is enabled prior to launching the command. Set Verify Margin Set sense-amp margin levels for verifying Flash array contents (special mode only). Level MM912F634 Freescale Semiconductor 282 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.4.2.1 Erase Verify Command The erase verify operation will verify that the entire Flash array memory is erased. An example flow to execute the erase verify operation is shown in Figure 86. The erase verify command write sequence is as follows: 1. 2. 3. Write to an aligned Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored. Write the erase verify command, 0x05, to the FCMD register. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in the Flash array memory plus several bus cycles, as measured from the time the CBEIF flag is cleared, until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the Flash array memory are verified to be erased. If any address in the Flash array memory is not erased, the erase verify operation will terminate, the BLANK flag in the FSTAT register will remain clear, and the FAIL flag in the FSTAT register will set in special mode. MM912F634 Freescale Semiconductor 283 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no Write: FCLKDIV register NOTE: FCLKDIV needs to be set after each reset Read: FSTAT register Command Buffer Empty Check Access Error and Protection Violation Check 1. 2. 3. CBEIF Set? yes ACCERR/PVIOL yes Set? no Write: Flash Block Address and Dummy Data Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check Erase Verify Status CCIF Set? yes BLANK Set? yes EXIT Flash Block Erased EXIT Flash Block Not Erased no no Write: FSTAT register Clear ACCERR/PVIOL 0x30 no Figure 86. Example Erase Verify Command Flow 4.36.4.2.2 Program Command The program operation will program a previously erased address in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 87. The program command write sequence is as follows: 1. 2. 3. Write to an aligned Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written. Write the program command, 0x20, to the FCMD register. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. MM912F634 Freescale Semiconductor 284 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) If an address to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed. START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no Write: FCLKDIV register NOTE: FCLKDIV needs to be set after each reset Read: FSTAT register Command Buffer Empty Check Access Error and Protection Violation Check 1. 2. 3. CBEIF Set? yes ACCERR/PVIOL yes Set? no Write: Flash Array Address and Program Data Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT Figure 87. Example Program Command Flow no Write: FSTAT register Clear ACCERR/PVIOL 0x30 no 4.36.4.2.3 Burst Program Command The burst program operation will program previously erased data in the Flash memory using an embedded algorithm. While burst programming, two internal data registers operate as a buffer and a register (2-stage FIFO), so that a second burst programming command along with the necessary data can be stored to the buffers, while the first burst programming command is still in progress. This pipelined operation allows a time optimization when programming more than one consecutive address on a specific row in the Flash array as the high voltage generation can be kept active in between two programming commands. An example flow to execute the burst program operation is shown in Figure 88. The burst program command write sequence is as follows: 1. Write to an aligned Flash block address to start the command write sequence for the burst program command. The data written will be programmed to the address written. MM912F634 Freescale Semiconductor 285 Functional Description and Application Information 2. 3. 4. 32 kbyte Flash Module (S12SFTSR32KV1) Write the program burst command, 0x25, to the FCMD register. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program burst command. After the CBEIF flag in the FSTAT register returns to a 1 (interrupt generated, if enabled), repeat steps 1 through 3. The address written is ignored but is incremented internally. The burst program procedure can be used to program the entire Flash memory, even while crossing row boundaries within the Flash array. If data to be burst programmed falls within a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the burst program command will not launch. Once the burst program command has successfully launched, the CCIF flag in the FSTAT register will set after the burst program operation has completed, unless a new burst program command write sequence has been buffered. By executing a new burst program command write sequence on sequential addresses after the CBEIF flag in the FSTAT register has been set, greater than 50% faster programming time for the entire Flash array can be effectively achieved, when compared to using the basic program command. MM912F634 Freescale Semiconductor 286 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no Write: FCLKDIV register NOTE: FCLKDIV needs to be set after each reset Read: FSTAT register Command Buffer Empty Check Access Error and Protection Violation Check 1. 2. 3. CBEIF Set? yes ACCERR/PVIOL yes Set? no Write: Flash Array Address and Program Data Write: FCMD register Burst Program Command 0x25 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Buffer Empty Check Sequential Programming Decision CBEIF Set? yes Next Address? no yes no Write: FSTAT register Clear ACCERR/PVIOL 0x30 no Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT Figure 88. Example Burst Program Command Flow no MM912F634 Freescale Semiconductor 287 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.4.2.4 Sector Erase Command NOTE In case the PVIOL or ACCERR flags are asserted by some event occurring in between the erase pulses, the customer application must clear the flags in FSTAT register before resuming the sequence of 16 pulses. The sector erase operation will erase all addresses in a 512 byte sector of Flash memory using an embedded algorithm. The overall erase time has been divided into 16 erase pulses to allow faster system response. The customer application has to guarantee all 16 pulses are performed before writing into the Flash sector being erased. There is no requirement to have those pulses as consecutive operations. An example flow to execute the sector erase operation is shown in Figure 89. The sector erase command write sequence is as follows: 1. 2. 3. 4. 5. Write to an aligned Flash block address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while the data written is ignored. Write the sector erase command, 0x40, to the FCMD register. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. Wait for the CCIF flag in the FSTAT register to set signifying completion of the sector erase operation. Repeat steps 1 through 4 until all 16 sector erase pulses have been executed. Address must be in the same Flash sector. If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed. MM912F634 Freescale Semiconductor 288 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no Write: FCLKDIV register NOTE: FCLKDIV needs to be set after each reset Read: FSTAT register Command Buffer Empty Check Access Error and Protection Violation Check 1. 2. 3. CBEIF Set? yes ACCERR/PVIOL yes Set? no Write: Flash Sector Address and Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check Required Pulse Count Check CCIF Set? yes 16 Erase Pulses? yes EXIT Figure 89. Example Sector Erase Command Flow no no Write: FSTAT register Clear ACCERR/PVIOL 0x30 no Same Flash Sector Address MM912F634 Freescale Semiconductor 289 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.4.2.5 Mass Erase Command The mass erase operation will erase the entire Flash array memory using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 90. The mass erase command write sequence is as follows: 1. 2. 3. Write to an aligned Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored. Write the mass erase command, 0x41, to the FCMD register. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If the Flash array memory to be mass erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed. START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no Write: FCLKDIV register NOTE: FCLKDIV needs to be set after each reset Read: FSTAT register Command Buffer Empty Check Access Error and Protection Violation Check 1. 2. 3. CBEIF Set? yes ACCERR/PVIOL yes Set? no Write: Flash Memory Address and Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT Figure 90. Example Mass Erase Command Flow no Write: FSTAT register Clear ACCERR/PVIOL 0x30 no MM912F634 Freescale Semiconductor 290 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.4.2.6 Set Verify Margin Level Command The set verify margin level operation, available only in special mode, will set the margin level in the Flash array sense-amps to allow content validation with margin to the normal level for subsequent Flash array reads. The set verify margin level command should only be used to validate initial programming of the Flash array. An example flow to execute the set verify margin level operation is shown in Figure 91. The set verify margin level command write sequence is as follows: 1. 2. 3. Write to an aligned Flash block address to start the command write sequence for the set verify margin level command. The address will be ignored while the data written sets the margin level as shown in Table 384. Write the set verify margin level command, 0x75, to the FCMD register. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the set verify margin level command. Once the set verify margin level command has successfully launched, the CCIF flag in the FSTAT register will set after the set verify margin level operation has completed. Table 384. Flash Array Margin Level Settings Command Data Field 0x0000 0x0005 0x0024 Margin Level Setting Normal Margin 0 Margin 1 Description Sets normal level for Flash array reads Sets test level to validate margin to reading 0’s Sets test level to validate margin to reading 1’s MM912F634 Freescale Semiconductor 291 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no Write: FCLKDIV register NOTE: FCLKDIV needs to be set after each reset Read: FSTAT register Command Buffer Empty Check Access Error and Protection Violation Check 1. 2. 3. CBEIF Set? yes Write: FSTAT register ACCERR/PVIOL yes Clear ACCERR/PVIOL 0x30 Set? no Write: Flash Memory Address and Data to Set Verify Margin Level Write: FCMD register Set Verify Margin Level Command 0x75 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT Figure 91. Example Set Verify Margin Level Command Flow (Special Mode only) no no 4.36.4.3 4.36.4.3.1 Illegal Flash Operations Flash Access Violations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. 2. 3. 4. 5. 6. 7. 8. Writing to a Flash address before initializing the FCLKDIV register. Writing a byte or misaligned word to a valid Flash address.Writing to any Flash register other than FCMD after writing to a Flash address. Writing to a second Flash address in the same command write sequence. Writing an invalid command to the FCMD register, unless the address written was in a protected area of the Flash array. Writing a command other than burst program, while CBEIF is set and CCIF is clear. When security is enabled, writing a command other than erase verify or mass erase to the FCMD register, when the write originates from a non-secure memory location or from the background debug mode. Writing to a Flash address after writing to the FCMD register. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register. MM912F634 Freescale Semiconductor 292 Functional Description and Application Information 9. 32 kbyte Flash Module (S12SFTSR32KV1) Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence. The ACCERR flag will also be set if the MCU enters stop mode while any command is active (CCIF=0). The operation is aborted immediately and, if burst programming, any pending burst program command is purged (see Section 4.36.5.2, “Stop Mode"”). The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”). 4.36.4.3.2 Flash Protection Violations The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence, if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. 2. 3. 4. Writing the program command if the address written in the command write sequence was in a protected area of the Flash array. Writing the sector erase command if the address written in the command write sequence was in a protected area of the Flash array. Writing the mass erase command while any Flash protection is enabled. Writing an invalid command if the address written in the command write sequence was in a protected area of the Flash array. If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”). 4.36.5 4.36.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 4.36.8, “Interrupts"”). 4.36.5.2 Stop Mode NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations. If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash array will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 4.36.4.1.2, “Command Write Sequence"”). MM912F634 Freescale Semiconductor 293 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.5.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 383 can be executed. If the MCU is secured and is in special mode, only the erase verify and mass erase commands can be executed. 4.36.6 Flash Module Security The Flash module provides the necessary security information to the MCU. During each reset sequence, the Flash module determines the security state of the MCU as defined in Section 4.36.3.3.2, “Flash Security Register (FSEC)"”. The contents of the Flash security byte in the Flash configuration field (see Section 4.36.3.1.1) must be changed directly by programming the Flash security byte location, when the MCU is unsecured and the sector containing the Flash security byte is unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize into a secure operating mode. 4.36.6.1 Unsecuring the MCU Using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the backdoor keys (see Section 4.36.3.1.1). If the KEYEN[1:0] bits are in the enabled state (see Section 4.36.3.3.2) and the KEYACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison between the written data and the backdoor key data stored in the Flash memory. If all backdoor keys are written to the correct addresses in the correct order, and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially. Values 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return valid data. The user code stored in the Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 4.36.3.3.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. 2. 3. 4. Set the KEYACC bit in the Flash configuration register (FCNFG). Sequentially write the correct four words to the Flash addresses containing the backdoor keys. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEYACC bit. If all data written match the backdoor keys, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to an unsecured state. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. 2. 3. 4. 5. 6. If any of the keys written does not match the backdoor keys programmed in the Flash array. If the keys are written in the wrong sequence. If any of the keys written are all 0’s or all 1’s. If the KEYACC bit does not remain set while the keys are written. If any of the keys are written on successive MCU clock cycles. Executing a STOP instruction before all keys have been written. After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming the associated addresses in the Flash configuration field (see Section 4.36.3.1.1). MM912F634 Freescale Semiconductor 294 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) The security as defined in the Flash security byte is not changed by using the backdoor key access sequence to unsecure. The stored backdoor keys are unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte. The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register (FPROT). It is not possible to unsecure the MCU in special mode by using the backdoor key access sequence in background debug mode (BDM). 4.36.6.2 1. 2. 3. Unsecuring the MCU in Special Mode Using BDM The MCU can be unsecured in special mode by erasing the Flash module by the following method: Reset the MCU into special mode, delay while the erase test is performed by the BDM secure ROM. Send BDM commands to disable protection in the Flash module. Execute a mass erase command write sequence to erase the Flash memory. After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: 1. 2. Send BDM commands to execute a program sequence to program the Flash security byte to the unsecured state. Reset the MCU. 4.36.7 4.36.7.1 Resets Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity, while reading the following resources from the Flash block: • • • • MCU control parameters (see Section 4.36.3.2) Flash protection byte (see Section 4.36.3.1.1 and Section 4.36.3.3.5) Flash nonvolatile byte (see Section 4.36.3.1.1) Flash security byte (see Section 4.36.3.1.1 and Section 4.36.3.3.2) 4.36.7.2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the Flash array address being programmed or the sector/block being erased is not guaranteed. 4.36.8 Interrupts NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data and command buffers are empty. Table 385. Flash Interrupt Sources Interrupt Source Flash Address, Data and Command Buffers empty All Flash commands completed Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE (FCNFG register) CCIE (FCNFG register) Global (CCR) Mask I Bit I Bit MM912F634 Freescale Semiconductor 295 Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) 4.36.8.1 Description of Flash Interrupt Operation The logic used for generating interrupts is shown in Figure 92. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request. CBEIF CBEIE Flash Command Interrupt Request CCIF CCIE Figure 92. Flash Command Interrupt Implementation For a detailed description of the register bits, refer to Section 4.36.3.3.4, “Flash Configuration Register (FCNFG)"” and Section 4.36.3.4, “Flash Status Register (FSTAT)"”. MM912F634 Freescale Semiconductor 296 Functional Description and Application Information Die-to-Die Initiator (D2DIV1) 4.37 4.37.1 Die-to-Die Initiator (D2DIV1) Introduction This section describes the functionality of the die-to-die (D2DIV1) initiator block especially designed for low cost connections between a microcontroller die (Interface Initiator) and an analog die (Interface Target) located in the same package. The D2DI block • • • realizes the initiator part of the D2D interface, including supervision and error interrupt generation generates the clock for this interface disables/enables the interrupt from the D2D interface 4.37.1.1 Overview The D2DI is the initiator for a data transfer to and from a target typically located on another die in the same package. It provides a set of configuration registers and two memory mapped 256 Byte address windows. When writing to a window, a transaction is initiated sending a write command, followed by an 8-bit address and the data byte or word to the target. When reading from a window, a transaction is initiated sending a read command, followed by an 8-bit address to the target. The target then responds with the data. The basic idea is that a peripheral located on another die, can be addressed like an on-chip peripheral, except for a small transaction delay. D2DCW Address Bus Write Data Bus Address and Data Buffer Read Data Bus D2DDAT[7:0] D2DIF D2DINTI D2DERR_INT xfr_wait D2DIE D2DCLKDIV D2DINT Bus Clock /n n=1 … 8 D2DCLK Figure 93. Die-to-Die Initiator (D2DI) Block Diagram 4.37.1.2 • Features The main features of this block are Software transparent, memory mapped access to peripherals on target die — 256 Byte address window — Supports blocking read or write as well as non-blocking write transactions Scalable interface clock divide by 1, 2, 3 of bus clock • MM912F634 Freescale Semiconductor 297 Functional Description and Application Information • • • • • • Clock halt on system STOP Configurable for 4- or 8-bit wide transfers Configurable timeout period Non-maskable interrupt on transaction errors Transaction Status and Error Flags Interrupt enable for receiving interrupt (from D2D target) Die-to-Die Initiator (D2DIV1) 4.37.1.3 4.37.1.3.1 Modes of Operation D2DI in STOP/WAIT Mode The D2DI stops working in STOP/WAIT mode. The D2DCLK signal as well as the data signals used are driven low (only after the end of the current high phase, as defined by D2DCLKDIV). Waking from STOP/WAIT mode, the D2DCLK line starts clocking again and the data lines will be driven low until the first transaction starts. STOP and WAIT mode are entered by different CPU instructions. In the WAIT mode, the behavior of the D2DI can be configured (D2DSWAI). Every (enabled) interrupt can be used to leave the STOP and WAIT mode. 4.37.1.3.2 D2DI in special modes The MCU can enter a special mode (used for test and debugging purposes as well as programming the FLASH). In the D2DI the “write-once” feature is disabled. See the MCU description for details. 4.37.2 External Signal Description The D2DI optionally uses 6 or 10 port pins. The functions of those pins depends on the settings in the D2DCTL0 register, when the D2DI module is enabled. 4.37.2.1 D2DCLK NOTE The maximum allowed D2D target frequency (fD2D) might be lower than the maximum initiator frequency. When the D2DI is enabled this pin is the clock output. This signal is low if the initiator is disabled, in STOP mode or in WAIT mode (with D2DSWAI asserted), otherwise it is a continuos clock. This pin may be shared with general purpose functionality if the D2DI is disabled. 4.37.2.2 D2DDAT[7:4] When the D2DI is enabled and the interface connection width D2DCW is set to be 8-bit wide, those lines carry the data bits 7:4 acting as outputs or inputs. When they act as inputs pull-down elements are enabled. If the D2DI is disabled or if the interface connection width is set as 4-bit wide, the pins may be shared with general purpose pin functionality. 4.37.2.3 D2DDAT[3:0] When the D2DI is enabled those lines carry the data bits 3:0 acting as outputs or inputs. When they act as inputs pull-down elements are enabled. If the D2DI is disabled the pins and may be shared with general purpose pin functionality. 4.37.2.4 D2DINT The D2DINT is an active input interrupt input driven by the target device. The pin has an active pull-down device. If the D2DI is disabled, the pin may be shared with general purpose pin functionality. MM912F634 Freescale Semiconductor 298 Functional Description and Application Information Table 386. Signal Properties Name D2DDAT[7:0] D2DCLK D2DINT Primary (D2DEN=1) Bi-directional Data Lines Interface Clock Signal Active High Interrupt I/O Secondary (D2DEN=0) Reset 0 0 — Comment Die-to-Die Initiator (D2DIV1) Pull-down Active(186) — Active(187) I/O GPIO O I GPIO GPIO driven low if in STOP mode low if in STOP mode — Note: 186. Active if in input state, only if D2DEN=1 187. only if D2DEN=1 See the port interface module (PIM) guide for details of the GPIO function. 4.37.3 4.37.3.1 Memory Map and Register Definition Memory Map The D2DI memory map is split into three sections. 1. 2. 3. An eight byte set of control registers. A 256 byte window for blocking transactions. A 256 byte window for non-blocking transactions. See the chapter “Device Memory Map” for the register layout (distribution of these sections). D2DREGS 8 Byte Control Registers D2DBLK 0x0200-0x02FF D2DNBLK 0x0300-0x03FF 256 Byte Window Blocking Access 256 Byte Window Non-blocking Write Figure 94. D2DI Top Level Memory Map MM912F634 Freescale Semiconductor 299 Functional Description and Application Information Die-to-Die Initiator (D2DIV1) A summary of the registers associated with the D2DI block is shown in Figure 48. Detailed descriptions of the registers and bits are given in the subsections that follow. Table 387. D2DI Register Summary Address 0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE 0x00DF Register Name D2DCTL0 D2DCTL1 R W R W Bit 7 D2DEN D2DIE ERRIF D2DIF R W R W R W R W DATA[7:0] DATA[15:8] ADR[7:0] RWB 6 D2DCW 0 ACKERF D2DBSY SZ8 5 D2DSWAI 0 CNCLF 0 0 4 0 0 TIMEF 0 NBLK TERRF 0 0 3 0 2 0 1 Bit 0 D2DCLKDIV[1:0] TIMEOUT[3:0] PARF 0 0 PAR1 0 0 PAR0 0 0 D2DSTAT0 D2DSTAT1 D2DADRHI D2DADRLO D2DDATAHI D2DDATALO 4.37.3.2 4.37.3.2.1 Register Definition D2DI Control Register 0 (D2DCTL0) This register is used to enable and configure the interface width, the wait behavior and the frequency of the interface clock. Table 388. D2DI Control Register 0 (D2DCTL0) 0x00D8 7 6 5 4 3 2 Access: User read/write 1 0 R W Reset D2DEN 0 D2DCW 0 D2DSWAI 0 0 0 0 0 0 0 D2DCLKDIV[1:0] 0 0 Table 389. D2DCTL0 Register Field Descriptions Field 7 D2DEN Description D2DI Enable — Enables the D2DI module. This bit is write-once in normal mode and can always be written in special modes. 0 D2DI initiator is disabled. No lines are not used, the pins have their GPIO (secondary) function. 1 D2DI initiator is enabled. After setting D2DEN = 1 the D2DDAT[7:0] (or [3:0], see D2DCW) lines are driven low with the IDLE command; the D2DCLK is driven by the divided bus clock. D2D Connection Width — Sets the number of data lines used by the interface. This bit is write-once in normal modes and can always be written in special modes. 0 Lines D2DDAT[3:0] are used for four line data transfer. D2DDAT[7:4] are unused. 1 All eight interface lines D2DDAT[7:0] are used for data transfer. 6 D2DCW MM912F634 Freescale Semiconductor 300 Functional Description and Application Information Table 389. D2DCTL0 Register Field Descriptions (continued) Field 5 D2DSWAI 4:2 1:0 D2DCLKDIV Description D2D Stop In Wait — Controls the WAIT behavior. This bit can be written at any time. 0 Interface clock continues to run if the CPU enters WAIT mode 1 Interface clock stops if the CPU enters WAIT mode. Reserved, should be written to 0 to ensure compatibility with future versions of this interface. Die-to-Die Initiator (D2DIV1) Interface Clock Divider — Determines the frequency of the interface clock. These bits are write-once in normal modes and can be always written in special modes. See Figure 95 for details on the clock waveforms 00 Encoding 0. Bus clock divide by 1. 01 Encoding 1. Bus clock divide by 2. 10 Encoding 2. Bus clock divide by 3. 11 Encoding 3. Bus clock divide by 4. The Clock Divider will provide the waveforms as shown in Figure 95. The duty cycle of the clock is not always 50%, the high cycle is shorter than 50% or equal but never longer, since this is beneficial for the transaction speed. a bus clock 00 01 10 11 Figure 95. Interface Clock Waveforms for Various D2DCLKDIV Encoding 4.37.3.2.2 D2DI Control Register 1 (D2DCTL1) NOTE “Write once“ means that after writing D2DCNTL0.D2DEN = 1 the write accesses to these bits have no effect. This register is used to enable the D2DI interrupt and set number of D2DCLK cycles before a timeout error is asserted. Table 390. D2DI Control Register 1 (D2DCTL1) 0x00D9 7 6 5 4 3 2 Access: User read/write 1 0 R W Reset D2DIE 0 0 0 0 0 0 0 0 0 TIMOUT[3:0] 0 0 Table 391. D2DCTL1 Register Field Descriptions Field 7 D2DIE 6:4 D2D Interrupt Enable — Enables the external interrupt 0 External Interrupt is disabled 1 External Interrupt is enabled Reserved, should be written to 0 to ensure compatibility with future versions of this interface. Description MM912F634 Freescale Semiconductor 301 Functional Description and Application Information Table 391. D2DCTL1 Register Field Descriptions (continued) Field 3:0 TIMOUT Description Die-to-Die Initiator (D2DIV1) Time-out Setting — Defines the number of D2DCLK cycles to wait after the last transaction cycle until a timeout is asserted. In case of a timeout the TIMEF flag in the D2DSTAT0 register will be set. These bits are write once in normal modes and can always be written in special modes. 0000 The acknowledge is expected directly after the last transfer, i.e. the target must not insert a wait cycle. 0001 - 1111: The target may insert up to TIMOUT wait states before acknowledging a transaction until a timeout is asserted 4.37.3.2.3 D2DI Status Register 0 (D2DSTAT0) This register reflects the status of the D2DI transactions. Table 392. D2DI Status Register 0 (D2DSTAT0) 0x00DA 7 6 5 4 3 2 Access: User read/write 1 0 R W Reset ERRIF 0 ACKERF 0 CNCLF 0 TIMEF 0 TERRF 0 PARF 0 PAR1 0 PAR0 0 Table 393. D2DI Status Register 0 Field Descriptions Field 7 ERRIF Description D2DI error interrupt flag — This status bit indicates that the D2D initiator has detected an error condition (summary of the following five flags).This interrupt is not locally maskable. Write a 1 to clear the flag. Writing a 0 has no effect. 0 D2DI has not detected an error during a transaction. 1 D2DI has detected an error during a transaction. Acknowledge Error Flag— This read-only flag indicates that in the acknowledge cycle not all data inputs are sampled high, indicating a potential broken wire. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. CNCLF — This read-only flag indicates the initiator has canceled a transaction and replaced it by an IDLE command due to a pending error flag (ERRIF). This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. Time Out Error Flag — This read-only flag indicates the initiator has detected a timeout error. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. Transaction Error Flag — This read-only flag indicates the initiator has detected the error signal during the acknowledge cycle of the transaction. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. Parity Error Flag — This read-only flag indicates the initiator has detected a parity error. Parity bits[1:0] contain further information. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. Parity Bit — P[1] as received by the D2DI Parity Bit — P[0] as received by the D2DI 6 ACKERF 5 CNCLF 4 TIMEF 3 TERRF 2 PARF 1 PAR1 0 PAR0 4.37.3.2.4 D2DI Status Register 1 (D2DSTAT1) This register holds the status of the external interrupt pin and an indicator about the D2DI transaction status. Table 394. D2DI Status Register 1 (D2DSTAT1) 0x00DB 7 6 5 4 3 2 1 Access: User read 0 MM912F634 Freescale Semiconductor 302 Functional Description and Application Information Table 394. D2DI Status Register 1 (D2DSTAT1) (continued) R W Reset D2DIF 0 D2DBSY 0 0 0 0 0 0 0 0 0 Die-to-Die Initiator (D2DIV1) 0 0 0 0 Table 395. D2DSTAT1 Register Field Descriptions Field 7 D2DIF Description D2D Interrupt Flag — This read-only flag reflects the status of the D2DINT Pin. The D2D interrupt flag can only be cleared by a target specific interrupt acknowledge sequence. 0 External Interrupt is negated 1 External Interrupt is asserted 6 D2D Initiator Busy — This read-only status bit indicates that a D2D transaction is ongoing. D2DBSY 0 D2D initiator idle. 1 D2D initiator transaction ongoing. 5:0 Reserved, should be masked to ensure compatibility with future versions of this interface. 4.37.3.2.5 D2DI Address Buffer Register (D2DADR) This read-only register contains information about the ongoing D2D interface transaction. The register content will be updated when a new transaction starts. In error cases the user can track back, which transaction failed. Table 396. D2DI Address Buffer Register (D2DADR) 0x00DC / 0x00DD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Access: User read 1 0 R W RWB 0 SZ8 0 0 0 NBLK 0 0 0 0 0 0 0 0 0 0 0 0 ADR[7:0] 0 0 0 0 0 Reset Table 397. D2DI Address Buffer Register Bit Descriptions Field 15 RWB 14 SZ8 13 12 NBLK 11:8 Description Transaction Read-Write Direction — This read-only bit reflects the direction of the transaction 0 Write Transaction 1 Read Transaction Transaction Size — This read-only bit reflects the data size of the transaction 0 16-bit transaction. 1 8-bit transaction. Reserved, should be masked to ensure compatibility with future versions of this interface. Transaction Mode — This read-only bit reflects the mode of the transaction 0 Blocking transaction. 1 Non-blocking transaction. Reserved, should be masked to ensure compatibility with future versions of this interface. 7:0 Transaction Address — Those read-only bits contain the address of the transaction ADR[7:0] MM912F634 Freescale Semiconductor 303 Functional Description and Application Information Die-to-Die Initiator (D2DIV1) 4.37.3.2.6 D2DI Data Buffer Register (D2DDATA) This read-only register contains information about the ongoing D2D interface transaction. For a write transaction, the data becomes valid at the begin of the transaction. For a read transaction, the data will be updated during the transaction, and is finalized when the transaction is acknowledged by the target. In error cases, the user can track back what has happened. Table 398. D2DI Data Buffer Register (D2DDATA) 0x00DE / 0x00DF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Access: User read 1 0 R W DATA15:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Table 399. D2DI Data Buffer Register Bit Descriptions Field 15:0 DATA Description Transaction Data — Those read-only bits contain the data of the transaction Both D2DDATA and D2DADR can be read with byte accesses. 4.37.4 4.37.4.1 Functional Description Initialization Out of reset the interface is disabled. The interface must be initialized by setting the interface clock speed, the timeout value, the transfer width, and finally enabling the interface. This should be done using a 16-bit write, or if using 8-bit write, D2DCTL1 must be written before D2D2CTL0.D2DEN = 1 is written. Once it is enabled in normal modes, only a reset can disable it again (write once feature). 4.37.4.2 Transactions A transaction on the D2D Interface is triggered by writing to either the 256 byte address window or reading from the address window (see STAA/LDAA 0/1 in the next figure). Depending on which address window is used, a blocking or a non-blocking transaction is performed. The address for the transaction is the 8-bit wide window relative address. The data width of the CPU read or write instructions determines if 8-bit or 16-bit wide data are transferred. There is always only one transaction active. Figure 96 shows the various types of transactions explained in more detail below. For all 16-bit read/write accesses of the CPU, the addresses are assigned according the big-endian model: word [15:8]: addr word[7:0]: addr+1 addr: byte-address (8 bit wide) inside the blocking or non-blocking window, as provided by the CPU and transferred to the D2D target word: CPU data, to be transferred from/to the D2D target The application must care for the stretched CPU cycles (limited by the TIMOUT value, caused by blocking or consecutive accesses), which could affect time limits, including COP (computer operates properly) supervision. The stretched CPU cycles cause the “CPU halted” phases (see Figure 96). MM912F634 Freescale Semiconductor 304 Functional Description and Application Information Die-to-Die Initiator (D2DIV1) Blocking Write CPU activity D2D activity STAA 0 CPU Halted Write Transaction 0 LDAA # STAA 1 CPU Halted Write Transaction 1 NOP CPU activity Non-blocking Write D2D activity CPU STAA 0 LDAA # STAA 1 Halted Write Transaction 0 NOP Write Transaction 1 CPU activity Blocking Read LDAA 0 CPU Halted Transaction 0 STAA MEM LDAA 1 CPU Halted Transaction 1 NOP D2D activity Figure 96. Blocking and Non-blocking Transfers. 4.37.4.2.1 Blocking Writes When writing to the address window associated with blocking transactions, the CPU is held until the transaction is completed, before completing the instruction. Figure 96 shows the behavior of the CPU for a blocking write transaction shown in the following example. STAA LDAA STAA NOP BLK_WINDOW+OFFS0 ; WRITE0 8-bit as a blocking transaction #BYTE1 BLK_WINDOW+OFFS1 ; WRITE1 is executed after WRITE0 transaction is completed Blocking writes should be used when clearing interrupt flags located in the target, or other writes which require that the operation at the target is completed before proceeding with the CPU instruction stream. 4.37.4.2.2 Non-blocking Writes When writing to the address window associated with non-blocking transactions, the CPU can continue before the transaction is completed. However, if there was a transaction ongoing when doing the 2nd write, the CPU is held until the first one is completed before executing the 2nd one. Figure 96 shows the behavior of the CPU for a blocking write transaction shown in the following example. STAA LDAA STAA NOP NONBLK_WINDOW+OFFS0; write 8-bit as a blocking transaction #BYTE1 ; load next byte NONBLK_WINDOW+OFFS1; executed right after the first As Figure 96 illustrates, non-blocking writes have a performance advantage, but care must be taken that the following instructions are not affected by the change in the target caused by the previous transaction. MM912F634 Freescale Semiconductor 305 Functional Description and Application Information Die-to-Die Initiator (D2DIV1) 4.37.4.2.3 Blocking Read When reading from the address window associated with blocking transactions, the CPU is held until the data is returned from the target, before completing the instruction.Figure 96 shows the behavior of the CPU for a blocking read transaction shown in the following example. LDAA STAA LDAA BLK_WINDOW+OFFS0 ; Read 8-bit as a blocking transaction MEM ; Store result to local Memory BLK_WINDOW+OFFS1 ; Read 8-bit as a blocking transaction 4.37.4.2.4 Non-blocking Read Read access to the non-blocking window is reserved for future use. When reading from the address window associated with non-blocking writes, the read returns an all 0s data byte or word. This behavior can change in future revisions. 4.37.4.3 Transfer Width 8-bit wide writes or reads are translated into 8-bit wide interface transactions. 16-bit wide, aligned writes or reads are translated into 16-bit wide interface transactions. 16-bit wide, misaligned writes or reads are split up into two consecutive 8-bit transactions, with the transaction on the odd address first followed by the transaction on the next higher even address. Due to the much more complex error handling (by the MCU), misaligned 16-bit transfers should be avoided. 4.37.4.4 Error Conditions and Handling faults Since the S12 CPU (as well as the S08) do not provide a method to abort a transfer once started, the D2DI asserts an D2DERRINT. The ERRIF Flag is set in the D2DSTAT0 register. Depending on the error condition, further error flags will be set as described below. The content of the address and data buffers are frozen, and all transactions will be replaced by an IDLE command, until the error flag is cleared. If an error is detected during the read transaction of a read-modify-write instruction, or a non-blocking write transaction was followed by another write or read transaction, the second transaction is cancelled. The CNCLF is set in the D2DSTAT0 register to indicate that a transaction has been cancelled. The D2DERRINT handler can read the address and data buffer register to assess the error situation. Any further transaction will be replaced by IDLE until the ERRIF is cleared. 4.37.4.4.1 Missing Acknowledge If the target detects a wrong command, it will not send back an acknowledge. The same situation occurs if the acknowledge is corrupted. The D2DI detects this missing acknowledge after the timeout period configured in the TIMOUT parameter of the D2DCTL1 register. In case of a timeout, the ERRIF and the TIMEF flags in the D2DSTAT0 register will be set. 4.37.4.4.2 Parity error In the final acknowledge cycle of a transaction, the target sends two parity bits. If this parity does not match the parity calculated by the initiator, the ERRIF and the PARF flags in the D2DSTAT0 register will be set. The PAR[1:0] bits contain the parity value received by the D2DI. 4.37.4.4.3 Error Signal During the acknowledge cycle the target can signal a target specific error condition. If the D2DI finds the error signal asserted during a transaction, the ERRIF and the TERRF flags in the D2DSTAT0 register will be set. MM912F634 Freescale Semiconductor 306 Functional Description and Application Information Die-to-Die Initiator (D2DIV1) 4.37.4.5 4.37.4.5.1 Low Power Mode Options D2DI in Run Mode In run mode with the D2D Interface enable (D2DEN) bit in the D2D control register 0 clear, the D2DI system is in a low-power, disabled state. D2D registers remain accessible, but clocks to the core of this module are disabled. On D2D lines the GPIO function is activated. 4.37.4.5.2 D2DI in Wait Mode D2DI operation in wait mode depends upon the state of the D2DSWAI bit in D2D control register 0. • • If D2DSWAI is clear, the D2DI operates normally when the CPU is in the wait mode If D2DSWAI is set and the CPU enters the wait mode, any pending transmission is completed. When the D2DCLK output is driven low, the clock generation is stopped, all internal clocks to the D2DI module are stopped, and the module enters a power saving state. 4.37.4.5.3 D2DI in Stop Mode If the CPU enters the STOP mode, the D2DI shows the same behavior as with the wait mode with an activated D2DSWAI bit. 4.37.4.6 Reset In case of reset, any transaction is immediately stopped and the D2DI module is disabled. 4.37.4.7 Interrupts The D2DI only originates interrupt requests, when D2DI is enabled (D2DIE bit in D2DCTL0 set). There are two different interrupt requests from the D2D module. The interrupt vector offset and interrupt priority are chip dependent. 4.37.4.7.1 D2D External Interrupt This is a level sensitive active high external interrupt driven by the D2DINT input. This interrupt is enabled if the D2DIE bit in the D2DCTL1 register is set. The interrupt must be cleared using an target specific clearing sequence. The status of the D2D input pin can be observed by reading the D2DIF bit in the D2DSTAT1 register. The D2DINIT signal is asserted also in the wait and stop mode; it can be used to leave these modes. To read data bus (D2DSTAT1.D2DIF) D2DINTI D2DIE Figure 97. D2D External Interrupt Scheme D2DINT 4.37.4.7.2 D2D Error Interrupt Those D2D interface specific interrupts are level sensitive and are all cleared by writing a 1 to the ERRIF flag in the D2DSTAT0 register. This interrupt is not locally maskable and should be tied to the highest possible interrupt level in the system, on an S12 architecture to the XIRQ. See the chapter “Vectors” of the MCU description for details. MM912F634 Freescale Semiconductor 307 Functional Description and Application Information Die-to-Die Initiator (D2DIV1) ACKERF CNCLF ERRIF 1 TIMEF TERRF D2DERRINT D2DEN Figure 98. D2D Internal Interrupts PARF 4.37.5 Initialization Information During initialization the transfer width, clock divider and timeout value must be set according to the capabilities of the target device before starting any transaction. See the D2D Target specification for details. 4.37.6 4.37.6.1 Application Information Entering low power mode The D2DI module is typically used on a microcontroller along with an analog companion device containing the D2D target interface and supplying the power. Interface specification does not provide special wires for signalling low power modes to the target device. The CPU should determine when it is time to enter one of the above power modes.The basic flow is as follows: 1. 2. 3. 4. 5. CPU determines there is no more work pending. CPU writes a byte to a register on the analog die using blocking write configuring which mode to enter. Analog die acknowledges that write sending back an acknowledge symbol on the interface. CPU executes WAIT or STOP command. Analog die can enter low-power mode - (S12 needs some more cycles to stack data!) ; Example shows S12 code SEI ; disable interrupts during test ; check is there is work pending? ; if yes, branch off and re-enable interrupt ; else LDAA #STOP_ENTRY STAA MODE_REG ; store to the analog die mode reg (use blocking write here) CLI ; re-enable right before the STOP instruction STOP ; stack and turn off all clocks inc. interface clock For wake-up from STOP the basic flow is as follows: 1. 2. 3. 4. 5. 6. Analog die detects a wake-up condition e.g. on a switch input or start bit of a LIN message. Analog die exits Voltage Regulator low-power mode. Analog die asserts the interrupt signal D2DINT. CPU starts clock generation. CPU enters interrupt handler routine. CPU services interrupt and acknowledges the source on the analog die. NOTE Entering STOP mode or WAIT mode with D2DSWAI asserted, the clock will complete the high duty cycle portion and settle at low level. MM912F634 Freescale Semiconductor 308 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38 4.38.1 Serial Peripheral Interface (S12SPIV4) Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 4.38.1.1 Glossary of Terms SPI — Serial Peripheral Interface SS — Slave Select SCK — Serial Clock MOSI — Master Output, Slave Input MISO — Master Input, Slave Output MOMI — Master Output, Master Input SISO — Slave Input, Slave Output 4.38.1.2 Features The S12SPIV4 includes these distinctive features: • • • • • • • Master mode and slave mode Bi-directional mode Slave select output Mode fault error flag with CPU interrupt capability Double-buffered data register Serial clock with programmable polarity and phase Control of SPI operation during wait mode 4.38.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. • • Run mode This is the basic mode of operation. Wait mode SPI operation in wait mode is a configurable low-power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. • This is a high level description only, detailed descriptions of operating modes are contained in Section 4.38.4.7, “Low Power Mode Options"”. MM912F634 Freescale Semiconductor 309 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.1.4 Block Diagram Figure 99 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. SPI 2 SPI Control Register 1 2 SPC0 SPI Status Register SPIF MODF SPTEF Interrupt Control SPI Interrupt Request Baud Rate Generator Counter Bus Clock Prescaler SPPR 3 Clock Select SPR 3 LSBFE=1 8 SPI Data Register 8 LSBFE=0 MSB Baud Rate Shift Clock Shifter Data In LSBFE=0 LSBFE=1 LSBFE=0 LSB LSBFE=1 Data Out Sample Clock Slave Control CPOL BIDIROE SPI Control Register 2 CPHA MOSI Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Master Control Port Control Logic SCK SS SPI Baud Rate Register Figure 99. SPI Block Diagram 4.38.2 External Signal Description This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The S12SPIV4 module has a total of four external pins. 4.38.2.1 MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. 4.38.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. MM912F634 Freescale Semiconductor 310 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave. 4.38.2.4 SCK — Serial Clock Pin In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock. 4.38.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the SPI. 4.38.3.1 Module Memory Map The memory map for the S12SPIV4 is given in Table 400. Table 400. SPI Register Summary Register Name 0x00E8 SPICR1 0x00E9 SPICR2 0x00EA SPIBR 0x00EB SPISR 0x00EC Reserved 0x00ED SPIDR 0x00EE Reserved 0x00EF Reserved R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 SPIF 0 SPPR2 0 SPPR1 SPTEF Bit 7 SPIE 0 6 SPE 0 5 SPTIE 0 4 MSTR MODFEN SPPR0 MODF 3 CPOL BIDIROE 0 0 2 CPHA 0 1 SSOE SPISWAI SPR1 0 Bit 0 LSBFE SPC0 SPR0 0 SPR2 0 4.38.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. MM912F634 Freescale Semiconductor 311 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.3.2.1 SPI Control Register 1 (SPICR1) Table 401. SPI Control Register 1 (SPICR1) 0x00E8 7 6 5 4 3 2 1 0 R W Reset SPIE 0 SPE 0 SPTIE 0 MSTR 0 CPOL 0 CPHA 1 SSOE 0 LSBFE 0 Read: Anytime Write: Anytime Table 402. SPICR1 Field Descriptions Field 7 SPIE 6 SPE Description SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if the SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if the SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock. Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 403. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first. 5 SPTIE 4 MSTR 3 CPOL 2 CPHA 1 SSOE 0 LSBFE MM912F634 Freescale Semiconductor 312 Functional Description and Application Information Table 403. SS Input / Output Selection MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode SS not used by the SPI SS not used by the SPI SS input with MODF feature SS is slave select output Serial Peripheral Interface (S12SPIV4) Slave Mode SS input SS input SS input SS input 4.38.3.2.2 SPI Control Register 2 (SPICR2) Table 404. SPI Control Register 2 (SPICR2) 0x00E9 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 MODFEN 0 BIDIROE 0 0 0 SPISWAI 0 SPC0 0 Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 405. SPICR2 Field Descriptions Field 4 MODFEN Description Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration, refer to Table 406. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 SS port pin is not used by the SPI. 1 SS port pin with MODF feature. Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, and in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled. 1 Output buffer enabled. SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 406. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 3 BIDIROE 1 SPISWAI 0 SPC0 MM912F634 Freescale Semiconductor 313 Functional Description and Application Information Table 406. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO Serial Peripheral Interface (S12SPIV4) MOSI Master Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Out Slave In Slave I/O Slave In MOSI not used by SPI Master In MISO not used by SPI Master Out Master In Master I/O 4.38.3.2.3 SPI Baud Rate Register (SPIBR) NOTE For maximum allowed baud rates, refer to Section 3.6.2.4, “SPI Timing" in this data sheet. Table 407. SPI Baud Rate Register (SPIBR) 0x00EA 7 6 5 4 3 2 1 0 R W Reset 0 0 SPPR2 0 SPPR1 0 SPPR0 0 0 0 SPR2 0 SPR1 0 SPR0 0 Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 408. SPIBR Field Descriptions Field 6–4 SPPR[2:0] 2–0 SPR[2:0] Description SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 409. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 409. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. The baud rate divisor equation is as follows: BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) The baud rate can be calculated with the following equation: Eqn. 2 Baud Rate = BusClock / BaudRateDivisor Table 409. Example SPI Baud Rate Selection (20 MHz Bus Clock) SPPR2 0 0 0 SPPR1 0 0 0 SPPR0 0 0 0 SPR2 0 0 0 SPR1 0 0 1 SPR0 0 1 0 Baud Rate Divisor 2 4 8 Eqn. 3 Baud Rate 10.0 MHz 5.00 MHz 2.50 MHz MM912F634 Freescale Semiconductor 314 Functional Description and Application Information Table 409. Example SPI Baud Rate Selection (20 MHz Bus Clock) (continued) SPPR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 SPPR0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 SPR2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 SPR1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SPR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Serial Peripheral Interface (S12SPIV4) Baud Rate Divisor 16 32 64 128 256 4 8 16 32 64 128 256 512 6 12 24 48 96 192 384 768 8 16 32 64 128 256 512 1024 10 20 40 80 160 320 640 1280 12 24 48 96 192 Baud Rate 1.25 MHz 625.00 kHz 312.50 kHz 156.25 kHz 78.13 kHz 5.00 MHz 2.50 MHz 1.25 MHz 625.00 kHz 312.50 kHz 156.25 kHz 78.13 kHz 39.06 kHz 3.33 MHz 1.66 MHz 833.33 kHz 416.67 kHz 208.33 kHz 104.17 kHz 52.08 kHz 26.04 kHz 2.50 MHz 1.25 MHz 625.00 kHz 312.50 kHz 156.25 kHz 78.13 kHz 39.06 kHz 19.53 kHz 2.00 MHz 1.00 MHz 500.00 kHz 250.00 kHz 125.00 kHz 62.50 kHz 31.25 kHz 15.63 kHz 1.66 kHz 833.33 kHz 416.67 kHz 208.33 kHz 104.17 kHz MM912F634 Freescale Semiconductor 315 Functional Description and Application Information Table 409. Example SPI Baud Rate Selection (20 MHz Bus Clock) (continued) SPPR2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Serial Peripheral Interface (S12SPIV4) Baud Rate Divisor 384 768 1536 14 28 56 112 224 448 896 1792 16 32 64 128 256 512 1024 2048 Baud Rate 52.08 kHz 26.04 kHz 13.02 kHz 1.42 MHz 714.29 kHz 357.14 kHz 178.57 kHz 89.29 kHz 44.64 kHz 22.32 kHz 11.16 kHz 1.25 MHz 625.00 kHz 312.50 kHz 156.25 kHz 39.13 kHz 39.06 kHz 19.53 kHz 9.77 kHz 4.38.3.2.4 SPI Status Register (SPISR) Table 410. SPI Status Register (SPISR) 0x00EB 7 6 5 4 3 2 1 0 R W Reset SPIF 0 0 0 SPTEF 1 MODF 0 0 0 0 0 0 0 0 0 Read: Anytime Write: Has no effect MM912F634 Freescale Semiconductor 316 Functional Description and Application Information Table 411. SPISR Field Descriptions Field 7 SPIF Description Serial Peripheral Interface (S12SPIV4) SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 0 Transfer not yet complete. 1 New data copied to SPIDR. SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI data register without reading SPTEF = 1, is effectively ignored. 0 SPI data register not empty. 1 SPI data register empty. Mode Fault Flag — This bit is set if the SS input becomes low, while the SPI is configured as a master and mode fault detection is enabled, the MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 4.38.3.2.2, “SPI Control Register 2 (SPICR2)"”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. 5 SPTEF 4 MODF 4.38.3.2.5 SPI Data Register (SPIDR) Table 412. SPI Data Register (SPIDR) 0x00ED 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 6 0 5 0 4 0 3 0 2 0 2 0 Bit 0 0 Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. If SPIF is cleared and a byte has been received, the received byte is transferred from the receive shift register to the SPIDR and SPIF is set. If SPIF is set and not serviced, and a second byte has been received, the second received byte is kept as valid byte in the receive shift register until the start of another transmission. The byte in the SPIDR does not change. If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 100). If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of a third transmission, the byte in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 101). MM912F634 Freescale Semiconductor 317 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data A Data B Data C SPIF SPI Data Register Data A Data B Data C = Unspecified = Reception in progress Figure 100. Reception with SPIF Serviced in Time Data A Received Data B Received Data C Received Data B Lost SPIF Serviced Receive Shift Register Data A Data B Data C SPIF SPI Data Register Data A Data C = Unspecified = Reception in progress Figure 101. Reception with SPIF Serviced Too Late 4.38.4 Functional Description The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • • • • Slave select (SS) Serial clock (SCK) Master out/slave in (MOSI) Master in/slave out (MISO) The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This 8-bit data register acts as the SPI MM912F634 Freescale Semiconductor 318 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 4.38.4.3, “Transmission Formats"”). NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. 4.38.4.1 Master Mode NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock. • Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. SS pin If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low, this indicates a mode fault error, where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). The result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 4.38.4.3, “Transmission Formats"”). • • MM912F634 Freescale Semiconductor 319 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.4.2 Slave Mode NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear. • • Serial clock In slave mode, SCK is the SPI clock input from the master. MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2. SS pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. • As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. NOTE A change of the CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE bits with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set. MM912F634 Freescale Semiconductor 320 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.4.3 Transmission Formats During a SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. MASTER SPI MISO MOSI SCK BAUD RATE GENERATOR SS MISO MOSI SCK SS SLAVE SPI SHIFT REGISTER SHIFT REGISTER VDD Figure 102. Master/Slave Transfer Block Diagram 4.38.4.3.1 Clock Phase and Polarity Controls Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. 4.38.4.3.2 CPHA = 0 Transfer Format The first edge on the SCK line is used to clock the first data bit of the slave into the master, and the first data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer, and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge: • • Data that was previously in the master SPI data register should now be in the slave data register, and the data that was in the slave data register should be in the master. The SPIF flag in the SPI status register is set, indicating that the transfer is complete. MM912F634 Freescale Semiconductor 321 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) Figure 103 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general purpose output not affecting the SPI. End of Idle State SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) 1 2 Begin 3 4 5 6 Transfer 7 8 9 10 11 12 End 13 14 15 16 Begin of Idle State CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL tT Bit 1 Bit 6 tI tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. LSB Minimum 1/2 SCK for tT, tl, tL MSB Figure 103. SPI Clock Format 0 (CPHA = 0) In slave mode, if the SS line is not de-asserted between the successive transmissions, then the content of the SPI data register is not transmitted. Instead, the last received byte is transmitted. If the SS line is de-asserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted. In master mode, with slave select output enabled the SS line is always de-asserted and reasserted between successive transfers for at least minimum idle time. MM912F634 Freescale Semiconductor 322 If next transfer begins here SAMPLE I MOSI/MISO Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.4.3.3 CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th SCK edge: • • Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 104 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. MM912F634 Freescale Semiconductor 323 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) End of Idle State SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) 1 2 3 Begin 4 5 6 7 Transfer 8 9 10 11 12 End 13 14 15 16 Begin of Idle State CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL tT Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 tI tL MSB first (LSBFE = 0): MSB LSB first (LSBFE = 1): LSB LSB Minimum 1/2 SCK for tT, tl, tL MSB tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 104. SPI Clock Format 1 (CPHA = 1) The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. • Back-to-back transfers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI data register, this byte is sent out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge. 4.38.4.4 SPI Baud Rate Generation NOTE For maximum allowed baud rates, refer to Section 3.6.2.4, “SPI Timing" in this data sheet. Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 4. BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) If next transfer begins here SAMPLE I MOSI/MISO Eqn. 4 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. MM912F634 Freescale Semiconductor 324 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 409 for baud rate calculations for all bit conditions, based on a 20 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. 4.38.4.5 4.38.4.5.1 Special Features SS Output NOTE Care must be taken when using the SS output feature in a multi master system because the mode fault feature is not available for detecting system errors between masters. The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 403. The mode fault feature is disabled while SS output is enabled. 4.38.4.5.2 Bidirectional Mode (MOMI or SISO) NOTE In bidirectional master mode, with mode fault enabled, both MISO and MOSI data pins can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode, and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case, MISO becomes occupied by the SPI and MOSI is not used. This must be considered if the MISO pin is used for another purpose. The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 413). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MM912F634 Freescale Semiconductor 325 Functional Description and Application Information Table 413. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Peripheral Interface (S12SPIV4) Slave Mode MSTR = 0 Serial Out Normal Mode SPC0 = 0 SPI Serial In MOSI Serial In SPI MOSI MISO Serial Out MISO Bidirectional Mode SPC0 = 1 Serial Out SPI Serial In BIDIROE MOMI Serial In SPI Serial Out BIDIROE SISO The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. • • • The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SCK and SS functions. 4.38.4.6 Error Conditions The SPI has one error condition: • Mode fault error 4.38.4.6.1 Mode Fault Error NOTE If a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation. The MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high-impedance inputs, to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set), followed by a write to the SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. MM912F634 Freescale Semiconductor 326 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.4.7 4.38.4.7.1 Low Power Mode Options SPI in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled. 4.38.4.7.2 SPI in Wait Mode NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a transmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur. SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2. • • • • • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else, if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). 4.38.4.7.3 SPI in Stop Mode Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit. MM912F634 Freescale Semiconductor 327 Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) 4.38.4.7.4 Reset The reset values of registers and signals are described in Section 4.28.2, “Memory Map and Registers", which details the registers and their bit fields. • • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. Reading from the SPIDR after reset will always read a byte of zeros. 4.38.4.7.5 Interrupts The S12SPIV4 only originates interrupt requests when the SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the S12SPIV4 makes a request, and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request. 4.38.4.7.5.1 MODF MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 403). After MODF is set, the current transfer is aborted and the following bit is changed: • MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 4.38.3.2.4, “SPI Status Register (SPISR)". 4.38.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 4.38.3.2.4, “SPI Status Register (SPISR)". 4.38.4.7.5.3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 4.38.3.2.4, “SPI Status Register (SPISR)". MM912F634 Freescale Semiconductor 328 Packaging Package Dimensions 5 5.1 Packaging Package Dimensions For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. AE SUFFIX 48-PIN 98ASA00173D REVISION 0 MM912F634 Freescale Semiconductor 329 Packaging Package Dimensions AE SUFFIX 48-PIN 98ASA00173D REVISION 0 MM912F634 Freescale Semiconductor 330 Packaging Package Dimensions AE SUFFIX 48-PIN 98ASA00173D REVISION 0 MM912F634 Freescale Semiconductor 331 Packaging Package Dimensions AP SUFFIX 48-PIN 98ASH00962A REVISION G MM912F634 Freescale Semiconductor 332 Packaging Package Dimensions AP SUFFIX 48-PIN 98ASH00962A REVISION G MM912F634 Freescale Semiconductor 333 Revision History Package Dimensions 6 . Revision History Revision 1.0 2.0 Date 05/2010 7/2010 • • • • • • • • • Initial release. Description MM912F634Cxxxx (Revision C) Introduced MM912F634Cxxxx (Revision C) Lx Input Threshold / Hysteresis Limit added. See Table 23, Static Electrical Characteristics - High Voltage Inputs - Lx VDDXSTOP minimum value deleted. See Table 17, Static Electrical Characteristics - Voltage Regulator 5.0 V (VDDX) IVDDLIMXSTOP ratings changed. See Table 17, Static Electrical Characteristics - Voltage Regulator 5.0 V (VDDX) IVDDLIMRUN minimum value deleted for all values of TJ. See Table 18, Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD) IVDDLIMSTOP minimum value deleted. See Table 18, Static Electrical Characteristics Voltage Regulator 2.5 V (VDD) TSg typical value changed to 9.17 mV/k. See Table 27, Static Electrical Characteristics Temperature Sensor - TSENSE Deleted devices MM912F634BC1AE, MM912F634BV2AE, MM912F634BC2AE, MM912F634BV3AE, MM912F634BC3AE, MM912F634CC1AE, MM912F634CC2AE, MM912F634CV3AE, MM912F634CC3AE from Table 1, Ordering Information, as well as references to these devices in sections 3.5, 3.6 & 3.7 Deleted "Data Flash" column in Table 1, Ordering Information, since this feature is not available for the MM912F634 Deleted all references to Analog Options "A3" & "A4" in Section 4.1.3, Analog Die Options Changed Analog Option designations from "A1" & "A2" to "1" & "2", respectively, in Table 1, Ordering Information, and Table 2, Analog Options Clarified instructions on use of unused pins in devices with Analog Option "2" Changed MM912F634Cxxxx Lx High Detection Threshold VTHH (min) from 2.7 V to 2.6 V for the range 7.0 V ≤ VSUP ≤ 27 V. Changed max & typical Hysteresis VHYS for MM912F634Cxxxx. Applied these new values to the full range of 5.5 V ≤ VSUP ≤ 27 V. See Table 19, Static Electrical Characteristics - High Voltage Inputs – Lx Added separate HBM ESD rating (VHBM) for HSx pins of +/-3000V. See Table 46, ESD and Latch-up Protection Characteristics Added MM912F634CV2AP to the ordering information Updated to standard form and style Added the 98ASA00173D (48-PIN LQFP) package drawing to the Packaging section Added symbol fBUSMAX to Max. Bus Frequency (MHz) column in Table 1. Replaced all references to 20 MHz bus frequency with fBUSMAX, and added a note referring to Table 1. See Table 8 – Operating Conditions, Table 9 – Supply Currents, Table 28 – Dynamic Electrical Characteristics – Die to Die Interface – D2D. Added reference to 16 MHz maximum CPU Bus Frequency for MM1912F634CV2AP to section 4.25.1.1 (MM912F634 – MCU Die Overview: Features) Changed Baud Rate data to reflect a 20 MHz Bus Clock in Table 409 – Example SPI Baud Rate Selection. Removed part number MM912F634BV1AE from data sheet. Corrected several typos throughout the document - No technical changes • • • • • • 3.0 10/2010 • • • • • • • 4.0 5.0 10/2010 11/2010 • • MM912F634 Freescale Semiconductor 334 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2010. All rights reserved. MM912F634 Rev. 5.0 11/2010