Freescale Semiconductor Technical Data
MMA2301D Rev 4, 03/2006
Surface Mount Micromachined Accelerometer
The MMA series of silicon capacitive, micromachined accelerometers feature signal conditioning, a 4-pole low pass filter and temperature compensation. Zero-g offset full scale span and filter cut-off are factory set and require no external devices. A full system self-test capability verifies system functionality. Features • • • • • • • • Integral Signal Conditioning Linear Output Ratiometric Performance 4th Order Bessel Filter Preserves Pulse Shape Integrity Calibrated Self-test Low Voltage Detect, Clock Monitor, and EPROM Parity Check Status Transducer Hermetically Sealed at Wafer Level for Superior Reliability Robust Design, High Shocks Survivability
MMA2301
MMA2301D: X-AXIS SENSITIVITY MICROMACHINED ACCELEROMETER ±200G
Typical Applications • • Vibration Monitoring and Recording Impact Monitoring
D SUFFIX EG SUFFIX (Pb-FREE) 16-LEAD SOIC CASE 475-01
ORDERING INFORMATION
Device Name MMA2301D MMA2301DR2 MMA2301EG MMA2301EGR2 Temperature Range –40° to 125°C –40° to 125°C –40° to 125°C –40° to 125°C Case No. 475-01 475-01 475-01 475-01 Package SOIC-16 SOIC16, Tape & Reel SOIC-16 SOIC16, Tape & Reel
VDD G-Cell Sensor Integrator Gain Filter Temp VOUT N/C N/C N/C ST VOUT STATUS VSS VDD STATUS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 N/C N/C N/C N/C N/C N/C N/C N/C
ST Self-Test
Control Logic and EPROM Trim Circuits
Oscillator
Clock Generator
VSS
Figure 1. Simplified Accelerometer Functional Block Diagram
Figure 2. Pin Connections
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Table 1. Maximum Ratings (Maximum ratings are the limits to which the device can be exposed without causing permanent damage.)
Rating Powered Acceleration (all axes) Unpowered Acceleration (all axes) Supply Voltage Drop Test
(1)
Symbol Gpd Gupd VDD Ddrop Tstg
Value 1500 2000 –0.3 to +7.0 1.2 –40 to +125
Unit g g V m °C
Storage Temperature Range 1. Dropped onto concrete surface from any axis.
ELECTRO STATIC DISCHARGE (ESD)
WARNING: This device is sensitive to electrostatic discharge. Although the accelerometers contain internal 2 kV ESD protection circuitry, extra precaution must be taken by the user to protect the chip from ESD. A charge of over 2000 volts can accumulate on the human body or associated test equipment. A charge of this magnitude can alter the performance or cause failure of the chip. When handling the accelerometer, proper ESD precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance.
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Table 2. Operating Characteristics (Unless otherwise noted: -40°C ≤ TA ≤ +105°C, 4.75 ≤ VDD ≤ 5.25, Acceleration = 0g, Loaded output)(1)
Characteristic Operating Range(2) Supply Voltage(3) Supply Current Operating Temperature Range Acceleration Range Output Signal Zero g (TA = 25°C, VDD = 5.0 V)(4) Zero g Sensitivity (TA = 25°C, VDD = 5.0 V)(5) Sensitivity Bandwidth Response Nonlinearity Noise RMS (.01-1 kHz) Power Spectral Density Clock Noise (without RC load on output)(6) Self-Test Output Response Input Low Input High Input Loading(7) Response Time(8) Status(9) (10) Output Low (Iload = 100 µA) Output High (Iload = 100 µA) Minimum Supply Voltage (LVD Trip) Clock Monitor Fail Detection Frequency Output Stage Performance Electrical Saturation Recovery Time(11) Full Scale Output Range (IOUT = 200 µA) Capacitive Load Drive(12) Output Impedance Mechanical Characteristics Transverse Sensitivity(13) Package Resonance Symbol VDD IDD TA gFS VOFF VOFF,V S SV f -3dB NLOUT nRMS nPSD nCLK gST VIL VIH IIN tST VOL VOH VLVD fmin tDELAY VFSO CL ZO VXZ,YZ fPKG Min 4.75 3.0 -40 — 2.4 0.46 VDD 9.5 1.86 360 -1.0 — — — 24 VSS 0.7 x VDD -30 — — VDD -0.8 2.7 50 — 0.25 — — — — Typ 5.0 — — 225 2.5 0.50 VDD 10.0 2.0 400 — — 110 2.0 30 — — -100 2.0 — — 3.25 — 0.2 — — 300 — 10 Max 5.25 6.0 +125 — 2.6 0.54 VDD 10.5 2.14 440 1.0 2.8 — — 36 0.3 x VDD VDD -260 10 0.4 — 4.0 260 — VDD -0.25 100 — 5.0 — Unit V mA °C g V V mV/g mV/g/V Hz % FSO mVrms µV/(Hz1/2) mVpk g V V µA ms V V V kHz ms V pF Ω % FSO kHz
1. For a loaded output the measurements are observed after an RC filter consisting of a 1 kΩ resistor and a 0.01 µF capacitor to ground.
2. These limits define the range of operation for which the part will meet specification. 3. Within the supply range of 4.75 and 5.25 volts, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the device may operate as a linear device but is not guaranteed to be in calibration. 4. The device can measure both + and - acceleration. With no input acceleration the output is at midsupply. For positive acceleration the output will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2. 5. The device is calibrated at 35g. 6. At clock frequency ≅ 70 kHz. 7. The digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external board level leakages. 8. Time for the output to reach 90% of its final value after a self-test is initiated. 9. The Status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. The Status pin is high whenever the self-test input is high, as a means to check the connectivity of the self-test and Status pins in the application. 10. The Status pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The Status pin can be reset low if the self-test pin is pulsed with a high input for at least 100 us, unless a fault condition continues to exist. 11. Time for amplifiers to recover after an acceleration signal causing them to saturate. 12. Preserves phase margin (60°) to guarantee output amplifier stability. 13. A measure of the device's ability to reject an acceleration applied 90° from the true axis of sensitivity.
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PRINCIPLE OF OPERATION
The Freescale Semiconductor, Inc. accelerometer is a surface-micromachined integrated-circuit accelerometer. The device consists of a surface micromachined capacitive sensing cell (g-cell) and a CMOS signal conditioning ASIC contained in a single integrated circuit package. The sensing element is sealed hermetically at the wafer level using a bulk micromachined cap wafer. The g-cell is a mechanical structure formed from semiconductor materials (polysilicon) using semiconductor processes (masking and etching). It can be modeled as a set of beams attached to a movable central mass that move between fixed beams. The movable beams can be deflected from their rest position by subjecting the system to an acceleration( Figure 3). As the beams attached to the central mass move, the distance from them to the fixed beams on one side will increase by the same amount that the distance to the fixed beams on the other side decreases. The change in distance is a measure of acceleration. The g-cell plates form two back-to-back capacitors (Figure 3). As the central mass moves with acceleration, the distance between the beams change and each capacitor's value will change, (C = NAε/D). Where A is the area of the facing side of the beam, ε is the dielectric constant, D is the distance between the beams, and N is the number of beams. The CMOS ASIC uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the difference between the two capacitors. The ASIC also signal conditions and filters (switched capacitor) the signal, providing a high level output voltage that is ratiometric and proportional to acceleration.
Acceleration
Figure 3. Simplified Transducer Physical Model versus Transducer Physical Model
SPECIAL FEATURES
Filtering The accelerometers contain an onboard 4-pole switched capacitor filter. A Bessel implementation is used because it provides a maximally flat delay response (linear phase) thus preserving pulse shape integrity. Because the filter is realized using switched capacitor techniques, there is no requirement for external passive components (resistors and capacitors) to set the cut-off frequency. Self-Test The sensor provides a self-test feature that allows the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. This feature is critical in applications such as automotive airbag systems where system integrity must be ensured over the life of the vehicle. A fourth plate is used in the g-cell as a self-test plate. When the user applies a logic high input to the self-test pin, a calibrated potential is applied across the self-test plate and the moveable plate. The resulting electrostatic force (Fe = 1/2 AV2/d2) causes the center plate to deflect. The resultant deflection is measured by the accelerometer's control ASIC and a proportional output voltage results. This procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. Ratiometricity Ratiometricity simply means that the output offset voltage and sensitivity will scale linearly with applied supply voltage. That is, as you increase supply voltage the sensitivity and offset increase linearly; as supply voltage decreases, offset and sensitivity decrease linearly. This is a key feature when interfacing to a microcontroller or an A/D converter because it provides system level cancellation of supply induced errors in the analog to digital conversion process. Status Freescale accelerometers include fault detection circuitry and a fault latch. The Status pin is an output from the fault latch, OR'd with self-test, and is set high whenever one (or more) of the following events occur: • Supply voltage falls below the Low Voltage Detect (LVD) voltage threshold • Clock oscillator falls below the clock monitor minimum frequency • Parity of the EPROM bits becomes odd in number. The fault latch can be reset by a rising edge on the self-test input pin, unless one (or more) of the fault conditions continues to exist.
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BASIC CONNECTIONS
PINOUT DESCRIPTION
N/C N/C N/C ST VOUT STATUS VSS VDD
1 2 3 4 5 6 7 8
Accelerometer
12 11 10 9
Microcontroller
16 15 14 13
N/C N/C N/C N/C N/C N/C N/C N/C
PCB Layout STATUS ST VOUT VSS VDD C R 1 kΩ 0.1 µF VRH C 0.1 µF C 0.01 µF P1 P0 A/D In
VSS C 0.1 µF VDD
Table 3. Pin Descriptions
Pin No. 1 thru 3 4 5 6 7 8 9 thru 13 14 thru 16 Pin Name N/C ST VOUT STATUS VSS VDD Trim pins — Description Leave unconnected. Logic input pin used to initiate selftest. Output voltage of the accelerometer. Logic output pin to indicate fault. The power supply ground. The power supply input. Used for factory trim. Leave unconnected. No internal connection. Leave unconnected. Power Supply
Figure 5. Recommend PCB Layout for Interfacing Accelerometer to Microcontroller NOTES: • Use a 0.1 µF capacitor on VDD to decouple the power source. • Physical coupling distance of the accelerometer to the microcontroller should be minimal. • Place a ground plane beneath the accelerometer to reduce noise, the ground plane should be attached to all of the open ended terminals shown in Figure 5 • Use an RC filter of 1 kΩ and 0.01 µF on the output of the accelerometer to minimize clock noise (from the switched capacitor filter circuit). • PCB layout of power and ground should not couple power supply noise. • Accelerometer and microcontroller should not be a high current path. A/D sampling rate and any external power supply switching frequency should be selected such that they do not interfere with the internal accelerometer sampling frequency. This will prevent aliasing errors.
VDD
MMA2301D Logic Input 4 ST 8 VDD
6 R1 1 kΩ
Status Output Signal
VOUT 5
C1 0.1 µF
7 VSS
C2 0.01 µF
Figure 4. SOIC Accelerometer with Recommended Connection Diagram
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Dynamic Acceleration Sensing Direction
Acceleration of the package in the +X direction (center plate moves in the -X direction) will result in an increase in the output.
+x
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
−x
Activation of Self Test moves the center plate in the −X direction, resulting in an increase in the output.
16-Pin SOIC Package
N/C pins are recommended to be left FLOATING
Top View
Static Acceleration Sensing Direction
87
65
43
21 Direction of Earth's gravity field.*
9 10 11 12 13 14 15 16
Front View
Side View
* When positioned as shown, the Earth's gravity will result in a positive 1g output.
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MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. It is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads.
0.380 in. 9.65 mm
0.050 in. 1.27 mm
0.024 in. 0.610 mm
0.080 in. 2.03 mm
Figure 6. Footprint SOIC-16 (Case 475-01)
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PACKAGE DIMENSIONS
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CASE 475-01 ISSUE C 16-LEAD SOIC
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PACKAGE DIMENSIONS
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CASE 475-01 ISSUE C 16-LEAD SOIC
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MMA2301D Rev. 4 03/2006