MMA7450LR2

Freescale Semiconductor Technical Data Document Number: MMA7450L Rev 0, 6/2007 ±2g/±4g/±8g Three Axis Low-g Digital Output Accelerometer The MMA7450L is a Digital Output (I2C/SPI), low power, low profile capacitive micromachined accelerometer featuring signal conditioning, a low pass filter, temperature compensation, self test, configurable to detect 0g through interrupt pins (INT1 or INT2), and pulse (click) detect for quick motion detection. The 0g offset can be customer calibrated using assigned 0g registers and g-Select which allows for command selection for 3 sensitivities (2g/4g/8g). Zero-g offset and sensitivity are factory set and require no external devices. The MMA7450L includes a Standby Mode that makes it ideal for handheld battery powered electronics. Features • • • • • • • • • • • • • • • • Digital Output (I2C/SPI) - 10-Bit at 8g Mode 3mm x 5mm x 0.8mm LGA-14 Package Low Current Consumption: 400 μA Sleep Mode: 5 μA Low Voltage Operation: 2.4 V – 3.6 V Customer Assigned Registers for Offset Calibration Programmable Threshold Interrupt Output Level/Pulse Detection for Motion Recognition (Shock, Vibration, Freefall) Click Detection for Single or Double Click Recognition High Sensitivity (64 LSB/g @ 2g and @ 8g in 10-Bit Mode) Selectable Sensitivity (±2g, ±4g, ±8g) Self Test for X-Axis Robust Design, High Shocks Survivability (10,000 g) RoHS Compliant Environmentally Preferred Product Low Cost MMA7450L MMA7450L: XYZ AXIS ACCELEROMETER ±2G/±4G/±8G Bottom View 14 LEAD LGA CASE 1935-01 Top View CS 7 Typical Applications • • • • • • Cell Phone/PMP/PDA: Image Stability, Text Scroll, Motion Dialing, E-Compass, Tap to Mute HDD: Freefall Detection Laptop PC: Freefall Detection, Anti-Theft Navigation and Dead Reckoning: Position Detection, Pedometer E-Compass Tilt Compensation 3D Gaming: Tilt and Motion Sensing, Event Recorder INT1/DRDY INT2 N/C N/C SDO SDA/SDI/SDO AVdd GND N/C N/C GND DVdd_IO 8 9 10 11 12 13 14 SLC/SPC 6 5 4 3 2 1 ORDERING INFORMATION Part Number MMA7450LT MMA7450LR1 MMA7450LR2 Temperature Range –20 to +65°C –20 to +65°C –20 to +65°C Package LGA-14 LGA-14 LGA-14 Shipping Tray Tape & Reel (7” Reel) Tape & Reel (13” Reel) Figure 1. Pin Connections This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. Figure 2. Simplified Accelerometer Functional Block Diagram Table 1. Maximum Ratings (Maximum ratings are the limits to which the device can be exposed without causing permanent damage.) Rating Maximum Acceleration (all axes) Analog Supply Voltage Digital I/O pins Supply Voltage Drop Test Storage Temperature Range Symbol gmax AVDD DVDD_IO Ddrop Tstg Value 10,000 -0.3 to +3.6 -0.3 to +3.6 1.8 -40 to +125 Unit g V V m °C ELECTRO STATIC DISCHARGE (ESD) WARNING: This device is sensitive to electrostatic discharge. Although the Freescale accelerometer contains internal 2000V ESD protection circuitry, extra precaution must be taken by the user to protect the chip from ESD. A charge of over 2000 volts can accumulate on the human body or associated test equipment. A charge of this magnitude can alter the performance or cause failure of the chip. When handling the accelerometer, proper ESD precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance. MMA7450L 2 Sensors Freescale Semiconductor Table 2. Operating Characteristics Unless otherwise noted: –20°C < TA < 65°C, 2.4 V < AVDD < 3.6 V, Acceleration = 0g, Loaded output Characteristic Analog Supply Voltage Standby Operation Mode Enable Bus Mode Digital I/O Pins Supply Voltage Standby Operation Mode Enable Bus Mode Supply Current Drain (AVDD/GND) Operation Mode Pulse Detect Function Mode Standby Mode (except data loading and I2C/SPI communication period) Operating Temperature Range Acceleration Range X-Axis, Y-Axis, Z-Axis Output Signal (TA=25°C, AVDD=2.8 V) Zero g ±2g range (25°C) 8bit ±4g range (25°C) 8bit ±8g range (25°C) 8bit ±8g range (25°C) 10bit Resolution (TA=25°C, AVDD=2.8 V) ±2g range (25°C) 8bit ±4g range (25°C) 8bit ±8g range (25°C) 8bit ±8g range (25°C) 10bit Sensitivity (TA=25°C, AVDD=2.8 V) ±2g range (25°C) 8bit ±4g range (25°C) 8bit ±8g range (25°C) 8bit ±8g range (25°C) 10bit Self Test Output Response Zout Input High Voltage Input Low Voltage PSRR (AVDD) 0 to 20 kHz 0 to 50 kHz Internal Clock Frequency SPI Frequency DVDD_IO < 2.4 V DVDD_IO > 2.4 V Output Data Rate (X, Y, Z set) Bandwidth for Data Measurement (User Selectable) tCLK — — TBD — — — — — TBD TBD 150 4 8 125 or 250 62.5 125 — — TBD — — — — — dB dB kHz MHz MHz Hz Hz Hz ΔVOUT ΔVOUT ΔVOUT ΔVOUT ΔSTZ VIH VIL — — — — 64 32 16 64 — — — — LSB/g LSB/g LSB/g LSB/g — — — — 15.6 31.2 62.4 15.6 — — — — mg mg mg mg VOFF VOFF VOFF VOFF -16 -8 -4 -16 — — — — +16 +8 +4 +16 LSB LSB LSB LSB IDD IDD IDD TA gFS gFS gFS — — — 400 550 5 TBD TBD TBD μA μA μA °C g g g Symbol AVDD AVDD DVDD_IO DVDD_IO Min 2.4 Typ 2.8 0 1.8 1.8 Max 3.6 Unit V V V V 1.71 1.71 AVDD 3.6 -20 ±2 ±4 ±8 25 — — — +85 — — — — 0.85DVDD_io -0.3V +64 — — — DVDD_io + 0.3 0.3DVDD_io LSB MMA7450L Sensors Freescale Semiconductor 3 Table 2. Operating Characteristics (Continued) Unless otherwise noted: –20°C < TA < 65°C, 2.4 V < AVDD < 3.6 V, Acceleration = 0g, Loaded output Characteristic Control Timing Wait Time for IIC/SPI ready after power on Turn On Response Time (Standby to Normal Mode) Turn Off Response Time (Normal to Standby Mode) Self Test Response Time Sensing Element Resonant Frequency XY Z Internal Sampling Frequency Nonlinearity (2 g range) Cross Axis Sensitivity Orthogonality Error of Channels Package to Die Misalignment RF Field Influence to Sensor 1. These limits define the range of operation for which the part will meet specification. 2. Within the supply range of 2.4 and 3.6 V, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the device may operate as a linear device but is not guaranteed to be in calibration. 3. This value is measured with g-Select in 2g mode. 4. The device can measure both + and - acceleration. The output is at mid-supply with no acceleration. The output will increase above VDD/2 for positive acceleration. The output will decrease below VDD/2 for negative acceleration. 5. The response time is between 10% of full scale Vdd input voltage and 90% of the final operating output voltage. 6. The response time is between 10% of full scale standby mode input voltage and 90% of the final operating output voltage. 7. The response time is between 10% of the full scale self test input voltage and 90% of the self test output voltage. 8. A measure of the device ability to reject acceleration is applied 90° from the true axis of sensitivity. Symbol tsu tru trd tst fGCELLXY fGCELLZ fCLK -1 -5 TBD 1 TBD — +1 +5 TBD Min Typ 1 20 20 Max Unit ms ms ms ms kHz kHz kHz %FS % ° ° LSB Table 3. Function Parameters for Detection VL < VDD < VH; TL < TA < TH unless otherwise specified Characteristic Level Detection Detection Threshold Range Pulse Detection Pulse detection range (Adjustable range) Time step for pulse detection Threshold range for pulses Detection levels for threshold (5) Latency timer (Adjustable range) Time Window (Adjustable range) Measurement bandwidth for detecting interrupt Time step for latency timer and time window 1 1 600 1 0 127 150 250 0.5 0.5 FS 127 ms ms g Levels ms ms Hz ms Symbol Min 0 Typ Max FS Unit G Note: The response time is between 10% of full scale Vdd input voltage and 90% of the final operating output voltage. MMA7450L 4 Sensors Freescale Semiconductor PRINCIPLE OF OPERATION The Freescale accelerometer is a surface-micromachined integrated-circuit accelerometer. The device consists of a surface micromachined capacitive sensing cell (g-cell) and a signal conditioning ASIC contained in a single package. The sensing element is sealed hermetically at the wafer level using a bulk micromachined cap wafer. The g-cell is a mechanical structure formed from semiconductor materials (polysilicon) using semiconductor processes (masking and etching). It can be modeled as a set of beams attached to a movable central mass that move between fixed beams. The movable beams can be deflected from their rest position by subjecting the system to an acceleration (Figure 3). As the beams attached to the central mass move, the distance from them to the fixed beams on one side will increase by the same amount that the distance to the fixed beams on the other side decreases. The change in distance is a measure of acceleration. The g-cell beams form two back-to-back capacitors (Figure 3). As the center beam moves with acceleration, the distance between the beams changes and each capacitor's value will change, (C = Aε/D). Where A is the area of the beam, ε is the dielectric constant, and D is the distance between the beams. The ASIC uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the difference between the two capacitors. The ASIC also signal conditions and filters (switched capacitor) the signal, providing a high level digital output voltage that is ratiometric and proportional to acceleration. Acceleration g-Select The g-Select feature enables the selection between 3 sensitivities for measurement. Depending on the values in the Mode control register ($16), the MMA7450L’s internal gain will be changed allowing it to function with a 2g, 4g or 8g measurement sensitivity. This feature is ideal when a product has applications requiring two or more sensitivities for optimum performance and for enabling multiple functions. The sensitivity can be changed during the operation by modifying the two GLVL bits located in the mode control register. $16: Mode control register (Read/Write) D7 -0 D6 D5 D4 D3 D2 D1 D0 Bit DRPD SPI3W STON GLVL[1] GLVL[0] MODE[1] MODE[0] Function 0 0 0 0 0 0 0 Default GLVL [1:0] 00: 8G is selected for measurement range. 01: 2G is selected for measurement range. 10: 4G is selected for measurement range. Table 4. g-Select Description g-Select 00 01 10 g-Range 8g 2g 4g Sensitivity 16 LSB/g 64 LSB/g 32 LSB/g Table 5. Mode Descriptions MODE [0:1] 00 01 10 11 Function Standby Mode Measurement Mode Level Detection Mode Pulse Detection Mode Figure 3. Simplified Transducer Physical Model FEATURES Self Test The sensor provides a self test feature that allows the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. This feature is critical in applications such as hard disk drive protection where system integrity must be ensured over the life of the product. Customers can use self test to verify the solderability to confirm that the part was mounted to the PCB correctly. To use this feature to verify the 0g-Detect function, the accelerometer should be held upside down so that the z axis experiences -1g. When the self test function is initiated through the mode control register, accessing the “self test” bit, an electrostatic force is applied to each axis to cause it to deflect. The z-axis is trimmed to deflect 1g. This procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. Standby Mode This digital output 3-axis accelerometer provides a standby mode that is ideal for battery operated products. When standby mode is active, the device outputs are turned off, providing significant reduction of operating current. When the device is in standby mode the current will be reduced to 5 µA typical. In standby mode the device can read and write to the registers with the I2C/SPI available, but no new measurements can be taken in this mode as all current consuming parts are off. The mode of the device is controlled through the mode control register by accessing the two mode bits as shown in Table 5. Measurement Mode During measurement mode, continuous measurements on all three axes enabled. The g-range for 2g, 4g, or 8g are selectable with 8-bit data and the g-range of 8g is selectable with 10-bit data. The sample rate during measurement mode is 125 Hz. Therefore, when a conversion is complete (signaled by the DRDY flag), the next measurement will be ready 8 ms later. MMA7450L Sensors Freescale Semiconductor 5 When measurements on all three axes are complete, a logic high level is output to the DRDY pin, indicating “Measurement data is ready.” The DRDY status can be monitored by the DRDY bit in Status Register (Address: $09). The DRDY pin is kept high until one of the three Output Value Registers are read. If the next measurement data is written before the previous data is read, the DOVR bit in the Status Register will be set. Also note that In measurement mode, level detection mode and pulse detection mode are not available. LEVEL DETECTION MODE Level Detection Mode In level detection mode, the measurements for x, y and z are all enabled with 2g/4g and 8g range available.The detection of thresholds for an acceleration signal level for the combinations of x and y or x, y, and z is enabled. This is used for motion detection where the threshold can be user set depending on the application or user specific requirements. When a motion event is detected, one of the interrupt pins (INT1 or INT2) will output a logic high output signaling the event is detected. Setting for Motion Detection To configure the MMA7450L for motion detection, after all three axes are enabled for detection, set the LDPOL bit in Control Register 2 (Address: $19) to 0. When the output value of one of the enabled axes exceeds the threshold limit value, either INT1 or INT2 pin will output a logic High indicating the event was detected. – If LDPOL = 0 and all three axes are enabled for detection – When the specified motion condition is detected, INT1 or INT2 will output a Logic high – “XOUT ≥Threshold” or “YOUT ≥Threshold” or “ZOUT ≥Threshold” NOTE: Measurement period and bandwidth for level detection is different from data output rate and the bandwidth of “measurement.” Please refer to Functional Parameter for Detection for more information. PULSE DETECTION MODE Pulse Detection Mode In pulse detection mode, both 2g/4g and 8g range are available. Measurements for x, y and z in 2g/4g or 8g mode are enabled. The level detection is also enabled in this mode. The pulse detected by the acceleration signal is enabled with single pulse and double pulse detection allowing the choice of either positive, negative or absolute value pulse detection. Setting for Motion Detection For the PDPOL bit in Control Register 2 (Address: $19) the register should be set to “0” for motion detection. When the output value of one of the enabled axes exceeds the threshold limit value, logic high level is output to INT1 or INT2 pin and indicates the event was detected. – If PDPOL = 0 and all three axes are enabled for detection – When the condition below was detected, logic high level outputs to INT1 or INT2 – “XOUT ≥Threshold” or “YOUT ≥Threshold” or “ZOUT ≥Threshold” Setting for Free Fall Detection To configure the MMA7450L for freefall detection, set the PDPOL bit in Control Register 2 (Address: $19) to 1. Threshold limit value is common for all three axes. Positive/negative and absolute value option is available. Assigning and Clearing the Interrupt Pins INT1/INT2 pin assignment for level detection is controlled by Control Register 1 (Address:$18). Next, set the register for Time Window for 2nd pulse value (Address $1E) to 0. When the output values of all enabled axes are below the threshold limit continuously during the period specified in Latency Timer Value Register, logic high level is output to INT1 or INT2 pin indicating freefall was detected. Filtering The 3 axis accelerometer contains digital filtering. INTPIN: 0:INT1 will be used for event 1:INT2 will be used for event Detection status is able to be monitored by Detection Source Register (Address:$0A). Once the configured event is detected, INT pin or register bit will not be cleared until the respective clear bit (CLRINT1 or CLRINT2) in Interrupt Latch Reset Register (Address: $17) is set. CLRINT1 and CLRINT2 should be cleared before starting next detection. Otherwise, INT pin or register will not set. MMA7450L 6 Sensors Freescale Semiconductor Figure 5. Double Pulse Detection Figure 4. Single Pulse Detection Figure 6. Negative Pulse Detection MMA7450L Sensors Freescale Semiconductor 7 DIGITAL INTERFACE The MMA7450L has both an I2C and SPI digital output available for a communication interface. When CS pin is used for Slave Select, SPI communication is selected. When CS is high, I2C communication is selected and SPI is disabled. NOTE: It is recommended to disable I2C during SPI communication to avoid communication errors between devices using a different SPI communication protocol. To disable I2C, set the I2CDIS bit in I2C Device Address register using SPI. I2 C SLAVE INTERFACE Figure 8. Multiple Bytes Read - The Master is reading multiple sequential registers from the MMA7450L SINGLE BYTE WRITE To start a write command, the Master transmits a start condition (ST) to the MMA7450L, slave address ($1D) with the R/W bit set to “0” for a write, the MMA7450L sends an acknowledgement. Then the Master (MCU) transmits the 8bit address of the register to write to, and the MMA7450L sends an acknowledgement. Then the Master (or MCU) transmits the 8-bit data to write to the designated register and the MMA7450L sends an acknowledgement that it has received the data. Since this transmission is complete, the Master transmits a stop condition (SP) to the data transfer. The data sent to the MMA7450L is now stored in the appropriate register. See Figure 9. I2C is a synchronous serial communication between a master device and one or more slave devices. The master is typically a microcontroller, which provides the serial clock signal and addresses the slave device(s) on the bus. The MMA7450L communicates only in slave operation where the device address is $1D. Multiple read and write modes are available. The protocol supports slave only operation. It does not support Hs mode, “10-bit addressing”, “general call” and :”START byte”. SINGLE BYTE READ The MMA7450L has an 8-bit ADC that can sample, convert and return sensor data on request. The transmission of an 8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send the command, note that the data returned is sent with the MSB first once the data is received. Figure 7 shows the timing diagram for the accelerometer 8-bit I2C read operation. The Master (or MCU) transmits a start condition (S) to the MMA7450L, slave address ($1D), with the R/W bit set to “0” for a write, and the MMA7450L sends an acknowledgement. Then the Master (or MCU) transmits the 8-bit address of the register to read and the MMA7450L sends an acknowledgement. The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA7450L ($1D) with the R/W bit set to “1” for a read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. Figure 9. Single Byte Write - The Master (MCU) is writing to a single register of the MMA7450L MULTIPLE BYTES WRITE The MMA7450L automatically increments the received register address commands after a write command is received. Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MMA7450L acknowledgment (ACK) is received. See Figure 10. Figure 10. Multiple Byte Writes - The Master (MCU) is writing to multiple sequential registers of the MMA7450L SPI SLAVE INTERFACE Figure 7. Single Byte Read - The Master is reading one address from the MMA7450L MULTIPLE BYTES READ The MMA7450L automatically increments the received register address commands after a read command is received. Therefore, after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA7450L acknowledgment (ACK) is received until a NACK is received from the Master followed by a stop condition (SP) signalling an end of transmission. See Figure 8. MMA7450L 8 The MMA7450L also uses serial peripheral interface communication as a digital communication. The SPI communication is primarily used for synchronous serial communication between a master device and one or more slave devices. See Figure 16 for an example of how to configure one master with two MMA7450L devices. The MMA7450L is always operated as a slave device. Typically, the master device would be a microcontroller which would drive the clock (SPC) and chip select (CS) signals. The SPI interface consists of two control lines and two data lines: CS, SPC, SDI, and SDO. The CS, also known as Chip Select, is the slave device enable which is controlled by the SPI master. CS is driven low at the start of a transmission. CS Sensors Freescale Semiconductor is then driven high at the end of a transmission. SPC is the Serial Port Clock which is also controlled by the SPI master. SDI and SDO are the Serial Port Data Input and the Serial Port Data Output. The SDI and SDO data lines are driven at the falling edge of the SPC and should be captured at the rising edge of the SPC. Read and write register commands are completed in 16 clock pulses or in multiples of 8, in the case of a multiple byte read/write. SPI READ OPERATION A SPI read transfer consists of a 1-bit Read/Write signal, a 6-bit address, and 1-bit don’t care bit. (1-bit R/W=0 + 6-bits address + 1-bit don’t care). The data to read is sent by the SPI interface during the next transfer. See Figure 11 and Figure 12 for the timing diagram for an 8-bit read in 4 wire and 3 wire modes, respectively. Figure 12. SPI Timing Diagram for 8-Bit Register Read (3 Wire Mode) SPI WRITE OPERATION In order to write to one of the 8-bit registers, an 8-bit write command must be sent to the MMA7450L. The write command consists of an MSB (0=read, 1=write) to indicate writing to the MMA7450L register, followed by a 6-bit address and 1 don’t care bit. The command should then be followed the 8-bit data transfer. See Figure 13 for the timing diagram for an 8-bit data write. Figure 11. SPI Timing Diagram for 8-Bit Register Read (4 Wire Mode) Figure 13. SPI Timing Diagram for 8-Bit Register Write (3 Wire Mode) MMA7450L Sensors Freescale Semiconductor 9 BASIC CONNECTIONS Pin Descriptions Top View CS 7 Recommended PCB Layout for Interfacing Accelerometer to Microcontroller INT1/DRDY INT2 N/C N/C SDO SDA/SDI/SDO AVdd GND N/C N/C GND DVdd_IO 100uF Figure 14. Pinout Description Table 6. Pin Descriptions Pin No. 1 3, 10, 11 4 2, 5 6 7 8 9 12 13 Pin Name DVDD_IO NC IADDR0 GND AVDD CS Description Digital power supply for I/O pads No Connection or connect to GND INT1/DRDY Interrupt1 / Data Ready INT2 SDO SDA/SDI/ SDO Interrupt2 SPI Serial Data Output I2C Serial Data (SDA), SPI Serial Data Input (SDI), 3-wire interface Serial Data Output (SDO) I C Serial Clock (SCL), SPI Serial Clock (SPC) 2 8 9 10 11 12 13 14 SLC/SPC I 2C Address bit 0 (optional) 6 5 4 3 2 1 100uF Figure 15. I2C Connection to MCU 100uF 100uF Ground Analog power supply (main power supply) SPI enable, I2C/SPI mode selection (1:12C, 0:SPI enabled) Figure 16. SPI Connection to MCU 14 SCL/SPC NOTES: 1. Use 100 nF capacitor on VDD to decouple the power source. 2. Physical coupling distance of the accelerometer to the microcontroller should be minimal. 3. Place a ground plane beneath the accelerometer to reduce noise, the ground plane should be attached to all of the open ended terminals shown in Figure 15 and Figure 16. 4. PCB layout of power and ground should not couple power supply noise. MMA7450L 10 5. Accelerometer and microcontroller should not be a high current path. 6. Any external power supply switching frequency should be selected such that they do not interfere with the internal accelerometer sampling frequency (sampling frequency). This will prevent aliasing errors. Sensors Freescale Semiconductor Table 7. User Register Summary Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F I2CAD USRINF WHOAMI XOFFL XOFFH YOFFL YOFFH ZOFFL ZOFFH MCTL INTRST CTL1 CTL2 LDTH PDTH PW LT TW Name XOUTL XOUTH YOUTL YOUTH ZOUTL ZOUTH XOUT8 YOUT8 ZOUT8 STATUS DETSRC TOUT Definition 10 bits output value X LSB 10 bits output value X MSB 10 bits output value Y LSB 10 bits output value Y MSB 10 bits output value Z LSB 10 bits output value Z MSB 8 bits output value X 8 bits output value Y 8 bits output value Z Status registers Detection source registers “Temperature output value” (Optional) (Reserved) I2C device address User information (Optional) “Who am I” value (Optional) Offset drift X value (LSB) Offset drift X value (MSB) Offset drift Y value (LSB) Offset drift Y value (MSB) Offset drift Z value (LSB) Offset drift Z value (MSB) Mode control Interrupt latch reset Control 1 Control 2 Level detection threshold limit value Pulse detection threshold limit value Pulse duration value Latency time value Time window for 2 nd Bit 7 XOUT[7] -YOUT[7] -ZOUT[7] -XOUT[7] YOUT[7] ZOUT[7] -LDX TMP[7] -I2CDIS UI[7] ID[7] XOFF[7] -YOFF[7] -ZOFF[7] -LPEN ---LDTH[7] PDTH[7] PD[7] LT[7] TW[7] -- Bit 6 XOUT[6] -YOUT[6] -ZOUT[6] -XOUT[6] YOUT[6] ZOUT[6] -LDY TMP[6] -DAD[6] UI[6] ID[6] XOFF[6] -YOFF[6] -ZOFF[6] -DRPD -THOPT -LDTH[6] PDTH[6] PD[6] LT[6] TW[6] -- Bit 5 XOUT[5] -YOUT[5] -ZOUT[5] -XOUT[5] YOUT[5] ZOUT[5] -LDZ TMP[5] -DAD[5] UI[5] ID[5] XOFF[5] -YOFF[5] -ZOFF[5] -SPI3W -ZDA -LDTH[5] PDTH[5] PD[5] LT[5] TW[5] -- Bit 4 XOUT[4] -YOUT[4] -ZOUT[4] -XOUT[4] YOUT[4] ZOUT[4] -PDX TMP[4] -DAD[4] UI[4] ID[4] XOFF[4] -YOFF[4] -ZOFF[4] -STON -YDA -LDTH[4] PDTH[4] PD[4] LT[4] TW[4] -- Bit 3 XOUT[3] -YOUT[3] -ZOUT[3] -XOUT[3] YOUT[3] ZOUT[3] -PDY TMP[3] -DAD[3] UI[3] ID[3] XOFF[3] -YOFF[3] -ZOFF[3] -GLVL[1] -XDA -LDTH[3] PDTH[3] PD[3] LT[3] TW[3] -- Bit 2 XOUT[2] -YOUT[2] -ZOUT[2] -XOUT[2] YOUT[2] ZOUT[2] PERR PDZ TMP[2] -DAD[2] UI[2] ID[2] XOFF[2] XOFF[10] YOFF[2] YOFF[10] ZOFF[2] ZOFF[10] GLVL[0] -- Bit 1 XOUT[1] XOUT[9] YOUT[1] YOUT[9] ZOUT[1] ZOUT[9] XOUT[1] YOUT[1] ZOUT[1] DOVR INT1 TMP[1] -DAD[1] UI[1] ID[1] XOFF[1] XOFF[9] YOFF[1] YOFF[9] ZOFF[1] ZOFF[9] MOD[1] Bit 0 XOUT[0] XOUT[8] YOUT[0] YOUT[8] ZOUT[0] ZOUT[8] XOUT[0] YOUT[0] ZOUT[0] DRDY INT2 TMP[0] -DAD[0] UI[0] ID[0] XOFF[0] XOFF[8] YOFF[0] YOFF[8] ZOFF[0] ZOFF[8] MOD[0] CLRINT2 CLRINT1 INTPIN LDPL LDTH[0] PDTH[0] PD[0] LT[0] TW[0] -- INTRG[1] INTRG[0] DRVO LDTH[2] PDTH[2] PD[2] LT[2] TW[2] -PDPL LDTH[1] PDTH[1] PD[1] LT[1] TW[1] -- pulse value (Reserved) MMA7450L Sensors Freescale Semiconductor 11 REGISTER DEFINITIONS $00 : 10bits output value X LSB (Read only) D7 XOUT [7] 0 D6 XOUT [6] 0 D5 XOUT [5] 0 D4 XOUT [4] 0 D3 XOUT [3] 0 D2 XOUT [2] 0 D1 XOUT [1] 0 D0 XOUT[0] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte XOUTL latches high byte XOUTH to allow 10-bit reads. XOUTH should be read directly following XOUTL read. $01 : 10bits output value X MSB (Read only) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 -0 D1 XOUT [9] 0 D0 XOUT[8] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte XOUTL latches high byte XOUTH to allow 10-bit reads. XOUTH should be read directly following XOUTL read. $02 : 10bits output value Y LSB (Read only) D7 YOUT [7] 0 D6 YOUT [6] 0 D5 YOUT [5] 0 D4 YOUT [4] 0 D3 YOUT [3] 0 D2 YOUT [2] 0 D1 YOUT [1] 0 D0 YOUT[0] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte YOUTL latches high byte YOUTH to allow coherent 10-bit reads. YOUTH should be read directly following YOUTL. $03 : 10bits output value Y MSB (Read only) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 -0 D1 YOUT [9] 0 D0 YOUT[8] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte ZOUTL latches high byte ZOUTH to allow coherent 10-bit reads. ZOUTH should be read directly following ZOUTL. $04 : 10bits output value Z LSB (Read only) D7 ZOUT [7] 0 D6 ZOUT [6] 0 D5 ZOUT [5] 0 D4 ZOUT [4] 0 D3 ZOUT [3] 0 D2 ZOUT [2] 0 D1 ZOUT [1] 0 D0 ZOUT[0] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte ZOUTL latches high byte ZOUTH to allow coherent 10-bit reads. ZOUTH should be read directly following ZOUTL. $05 : 10bits output value X MSB (Read only) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 -0 D1 ZOUT [9] 0 D0 ZOUT[8] 0 Bit Function Default $06: 8bits output value X (Read only) D7 XOUT[7] 0 D6 XOUT [6] 0 D5 XOUT [5] 0 D4 XOUT [4] 0 D3 XOUT [3] 0 D2 XOUT [2] 0 D1 XOUT [1] 0 D0 XOUT [0] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 8’h00 MMA7450L 12 Sensors Freescale Semiconductor $07: 8bits output value Y (Read only) D7 YOUT[7] 0 D6 YOUT [6] 0 D5 YOUT [5] 0 D4 YOUT [4] 0 D3 YOUT [3] 0 D2 YOUT [2] 0 D1 YOUT [1] 0 D0 YOUT [0] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 8’h00 $08: 8bits output value Z (Read only) D7 ZOUT[7] 0 D6 ZOUT [6] 0 D5 ZOUT [5] 0 D4 ZOUT [4] 0 D3 ZOUT [3] 0 D2 ZOUT [2] 0 D1 ZOUT [1] 0 D0 ZOUT [0] 0 Bit Function Default Signed byte data (2’s compliment): Zero G = 8’h00 $09: Status register (Read only) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 PERR 0 D1 DOVR 0 D0 DRDY 0 Bit Function Default DRDY 1: Data is ready 0: Data is not ready DOVR 1: Data is over written 0: Data is not over written $0A: Detection source register (Read only) D7 LDX 0 D6 LDY 0 D5 LDZ 0 D4 PDX 0 D3 PDY 0 D2 PDZ 0 PERR 1: Parity error is detected in trim data. Then, self test is disabled 0: Parity error is not detected in trim data D1 INT2 0 D0 INT1 0 Bit Function Default LDX 1: Level detection detected on X axis 0: Level detection not detected on X axis LDY 1: Level detection detected on Y axis 0: Level detection not detected on Y axis LDZ 1: Level detection detected on Z axis 0: Level detection not detected on Z axis PDX *Note 1: Pulse is detected on X axis at single pulse detection 0: Pulse is not detected on X axis at single pulse detection PDY *Note 1: Pulse is detected on Y axis at single pulse detection $0D: I2C Device Address (Bit 6-0: Read only, Bit 7: Read/Write) D7 I2CDIS 0 D6 DVAD[6] 0 D5 DVAD[5] 0 D4 DVAD[4] 1 D3 DVAD[3] 1 D2 DVAD[2] 1 0: Pulse is not detected on Y axis at single pulse detection PDZ *Note 1: Pulse is detected on Z axis at single pulse detection 0: Pulse is not detected on Z axis at single pulse detection Note: This bit value is not valid at double pulse detection INT1 1: Interrupt assigned by “Detection control” register is detected 0: Interrupt assigned by “Detection control” register is not detected INT2 1: Interrupt assigned by “Detection control” register is detected 0: Interrupt assigned by “Detection control” register is not detected D1 DVAD[1] 0 D0 DVAD[0] 1 Bit Function Default I2CDIS 0: I2C and SPI are available. 1: I2C is disabled. DVAD[6:0]: I2C device address MMA7450L Sensors Freescale Semiconductor 13 $0E: User Information (Read Only: Optional) D7 UI[7] 0/OTP D6 UI[6] 0/OTP D5 UI[5] 0/OTP D4 UI[4] 0/OTP D3 UI[3] 0/OTP D2 UI[2] 0/OTP D1 UI[1] 0/OTP D0 UI[0] 0/OTP Bit Function Default UI2[7:0]: User information $0F: “Who Am I” value (Read only: Optional) D7 ID[7] 0/OTP D6 ID [6] 0/OTP D5 ID [5] 0/OTP D4 ID [4] 0/OTP D3 ID [3] 0/OTP D2 ID [2] 0/OTP D1 ID [1] 0/OTP D0 ID [0] 0/OTP Bit Function Default $10: Offset drift X LSB (Read/Write) D7 XOFF[7] 0 D6 XOFF [6] 0 D5 XOFF [5] 0 D4 XOFF [4] 0 D3 XOFF [3] 0 D2 XOFF [2] 0 D1 XOFF [1] 0 D0 XOFF [0] 0 Bit Function Default Signed byte data (2’s compliment): User level offset trim value for X axis Bit Weight (*Note) XOFF[7] 64 LSB XOFF[6] 32 LSB XOFF[5] 16 LSB XOFF[4] 8 LSB XOFF[3] 4 LSB XOFF[2] 2 LSB XOFF[1] 1 LSB XOFF[0] 0.5 LSB *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. $11: Offset drift X MSB (Read/Write) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 XOFF [10] 0 D1 XOFF [9] 0 D0 XOFF [8] 0 Bit Function Default Signed byte data (2’s compliment): User level offset trim value for X axis $12: Offset drift Y LSB (Read/Write) D7 YOFF[7] 0 D6 YOFF [6] 0 D5 YOFF [5] 0 D4 YOFF [4] 0 D3 YOFF [3] 0 D2 YOFF [2] 0 D1 YOFF [1] 0 D0 YOFF [0] 0 Bit Function Default Signed byte data (2’s compliment): User level offset trim value for Y axis Bit Weight (*Note) YOFF[7] 64 LSB YOFF[6] 32 LSB YOFF[5] 16 LSB YOFF[4] 8 LSB YOFF[3] 4 LSB YOFF[2] 2 LSB YOFF[1] 1 LSB YOFF[0] 0.5 LSB *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. $13: Offset drift Y MSB (Read/Write) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 YOFF [10] 0 D1 YOFF [9] 0 D0 YOFF [8] 0 Bit Function Default Signed byte data (2’s compliment): User level offset trim value for Y axis Bit Weight (*Note) YOFF[10] Polarity YOFF[9] 256 LSB YOFF[8] 128 LSB *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. MMA7450L 14 Sensors Freescale Semiconductor $14: Offset drift Z LSB (Read/Write) D7 ZOFF[7] 0 D6 ZOFF[6] 0 D5 ZOFF[5] 0 D4 ZOFF[4] 0 D3 ZOFF[3] 0 D2 ZOFF[2] 0 D1 ZOFF[1] 0 D0 ZOFF[0] 0 Bit Function Default Signed byte data (2’s compliment): User level offset trim value for Z axis Bit Weight (*Note) ZOFF[7] 64 LSB ZOFF[6] 32 LSB ZOFF[5] 16 LSB ZOFF[4] 8 LSB ZOFF[3] 4 LSB ZOFF[2] 2 LSB ZOFF[1] 1 LSB ZOFF[0] 0.5 LSB *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. $15: Offset drift Z MSB (Read/Write) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 ZOFF[10] 0 D1 ZOFF[9] 0 D0 ZOFF[8] 0 Bit Function Default Signed byte data (2’s compliment): User level offset trim value for Z axis Bit Weight (*Note) ZOFF[10] Polarity ZOFF[9] 256 LSB ZOFF[8] 128 LSB *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. $16: Mode control register (Read/Write) D7 -0 D6 DRPD 0 MODE[1:0] 00 01 10 11 D5 SPI3W 0 D4 STON 0 D3 GLVL[1] 0 Function Standby Mode Measurement Mode Level Detection Mode Pulse Detection Mode D2 GLVL[0] 0 D1 MODE[1] 0 D0 MODE[0] 0 Bit Function Default GLVL [1:0] 00: 8G is selected for measurement range. Detection is 8G range. 01: 2G is selected for measurement range. Detection is 8G range. 10: 4G is selected for measurement range. Detection is 8G range. STON 0: Self test is not enabled 1: Self test is enabled SPI3W 0: SPI is 4 wire mode 1: SPI is 3 wire mode DRPD 0: Data ready status is output to INT1/DRDY PIN 1: Data ready status is not output to INT1/DRDY PIN MMA7450L Sensors Freescale Semiconductor 15 $17: Interrupt latch reset (Read/Write D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 -0 D1 0 D0 0 Bit Function Default CLR_INT2 CLR_INT1 CLR_INT1 1: Clear “INT1” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” register setting. 0: Do not clear “INT1” LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register. CLR_INT2 1: Clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” register setting. 0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register. $18: Control 1 (Read/Write) D7 DFBW 0 D6 THOPT 0 D5 ZDA 0 D4 YDA 0 D3 XDA 0 D2 0 D1 0 D0 INTPIN 0 Bit Function Default INTREG[1] INTREG[0] INTPIN 0: INT1 pin is routed to “INT1” register and INT2 pin is routed to “INT2” register. 1: INT2 pin is routed to “INT1” register and INT1 pin is routed to “INT2” register. INTREG[1:0] 00 01 10 “INT1” register bit Level Detection Pulse Detection Single pulse detection (*Note) “INT2” register bit Pulse Detection Level Detection Pulse Detection Note: Assigned to single pulse detection even if double pulse detection is selected. “Double pulse detection selected” means “Time window for 2nd pulse” is not equal zero. When double pulse detection is selected, INT1 register bit is not able to be cleared by setting CLR_INT1 bit. It’s cleared by setting CLR_INT2 bit. In this case, setting CLR_INT2 clears both INT1 and INT2 register bits and reset detecting operation itself. XDA 1: X axis is disabled for detection. 0: X axis is enabled for detection. YDA 1: Y axis is disabled for detection. 0: Y axis is enabled for detection. $19: Control 2 (Read/Write) D7 -0 D6 -0 D5 -0 D4 -0 D3 -0 D2 DRVO 0 ZDA 1: Z axis is disabled for detection. 0: Z axis is enabled for detection. THOPT (This bit is valid for level detection only, not valid for pulse detection) 0: Threshold value is absolute only 1: Positive/Negative threshold value is available. DFBW 0: Digital filter band width is 62.5 Hz 1: Digital filter band width is 125 Hz D1 PDPL 0 D0 LDPL 0 Bit Function Default LDPOL 0: Level detection polarity is positive and detecting condition is OR 3 axes. 1: Level detection polarity is negative detecting condition is AND 3 axes. PDPOL 0: Pulse detection polarity is positive and detecting condition is OR 3 axes. 1: Pulse detection polarity is negative and detecting condition is AND 3 axes. DRVO 0: Standard drive strength on SDA/SDO pin 1: Strong drive strength on SDA/SDO pin MMA7450L 16 Sensors Freescale Semiconductor $1A: Level detection threshold limit value (Read/Write) D7 LDTH[7] 0 D6 LDTH[6] 0 D5 LDTH[5] 0 D4 LDTH[4] 0 D3 LDTH[3] 0 D2 LDTH[2] 0 D1 LDTH[1] 0 D0 LDTH[0] 0 Bit Function Default LDTH[7:0]: Level detection threshold value. If THOPT bit in Detection Control Register is “0”, it is unsigned 7 bits value and LDTH[7] should be “0”. If THOPT bit is “1”, it is signed 8 bits value. $1B: Pulse detection threshold limit value (Read/Write) D7 XPDTH 0 D6 PDTH[6] 0 D5 PDTH[5] 0 D4 PDTH[4] 0 D3 PDTH[3] 0 D2 PDTH[2] 0 D1 PDTH[1] 0 D0 PDTH[0] 0 Bit Function Default PDTH[6:0]: Pulse detection threshold value (unsigned 7 bits). XPDTH: This bit should be “0”. $1C: Pulse duration value (Read/Write) D7 PD[7] 0 D6 PD[6] 0 D5 PD[5] 0 D4 PD[4] 0 D3 PD[3] 0 D2 PD[2] 0 D1 PD[1] 0 D0 PD[0] 1 Bit Function Default Min: PD[7:0] = 4’h01 = 0.5 ms Max: PD[7:0] = 4’hFF = 127 ms 1 LSB = 0.5 ms $1D: Latency time value (Read/Write) D7 LT[7] 0 D6 LT[6] 0 D5 LT[5] 0 D4 LT[4] 0 D3 LT[3] 0 D2 LT[2] 0 D1 LT[1] 0 D0 LT[0] 1 Bit Function Default Min: LT[7:0] = 8’h01 = 1 ms Max: LT[7:0] = 8’hFF = 255 ms 1 LSB = 1 ms $1E: Time window for 2nd pulse value (Read/Write) D7 TW[7] 0 D6 TW[6] 0 D5 TW[5] 0 D4 TW[4] 0 D3 TW[3] 0 D2 TW[2] 0 D1 TW[1] 0 D0 TW[0] 0 Bit Function Default Min: TW[7:0] = 8’h01 = 0 ms (Single pulse detection) Max: TW[7:0] = 8’hFF = 255 ms 1 LSB = 1 ms MMA7450L Sensors Freescale Semiconductor 17 SENSING DIRECTION AND OUTPUT RESPONSE The following figure shows sensing direction and the output response for 2g mode. Direction of Earth's gravity field.* Top View 6 7 8 10 11 12 13 X Z 5 4 3 2 1 14 14 9 OUT OUT 10 11 12 13 7 @ 0g = $00 @ +1g = $3F @ 0g = $00 Side View Top 8 6 1 2 Y Bottom X OUT OUT 5 9 3 OUT @ 0g = $00 @ 0g = $00 @ +1g = $3F 10 11 12 13 4 Y Z 4 3 OUT 5 9 2 6 8 Bottom 1 14 7 X Y Z OUT OUT @ +1g = $3F @ 0g = $00 @ 0g = $00 13 12 11 10 14 1 X Z 9 8 7 X Y Z OUT OUT @ -1g = $C1 @ 0g = $00 @ 0g = $00 X Z OUT OUT Top @ 0g = $00 @ 0g = $00 @ -1g = $C1 Y OUT OUT OUT 2 OUT OUT 3 4 5 6 @ 0g = $00 @ -1g = $C1 @ 0g = $00 Y OUT * When positioned as shown, the Earth’s gravity will result in a positive 1g output. Figure 17. Sensing Direction and Output Response at 2g Mode Table 8. Acceleration vs. Output FS Mode 2g Mode Acceleration -2g -1g 0g +1g +2g -4g -1g 0g +1g +4g -8g -1g 0g +1g +8g Output $80 $C1 $00 $3F $7F $80 $E1 $00 $1F $7F $80 $F1 $00 $0F $7F 4g Mode 8g Mode MMA7450L 18 Sensors Freescale Semiconductor MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. It is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads. MMA7450L Sensors Freescale Semiconductor 19 PACKAGE DIMENSIONS CASE 1935-01 ISSUE 0 14-LEAD LGA MMA7450L 20 Sensors Freescale Semiconductor PACKAGE DIMENSIONS CASE 1935-01 ISSUE 0 14-LEAD LGA MMA7450L Sensors Freescale Semiconductor 21 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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