MMA8450Q

Freescale Semiconductor Technical Data An Energy Efficient Solution by Freescale MMA8450Q Rev 2, 03/2010 3-Axis, 8-bit/12-bit Digital Accelerometer The MMA8450Q is a smart low-power, three-axis, capacitive micromachined accelerometer featuring 12 bits of resolution. This accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins. Embedded interrupt functions allow for overall power savings relieving the host processor from continuously polling data. The MMA8450Q’s Embedded FIFO buffer can be configured to log up to 32 samples of X,Y and Z-axis 12-bit (or 8-bit for faster download) data. The FIFO enables a more efficient analysis of gestures and user programmable algorithms, ensuring no loss of data on a shared I2C bus, and enables system level power saving (up to 96% of the total power consumption savings) by allowing the applications processor to sleep while data is logged. There is access to both low pass filtered data as well as high pass filtered data, which minimizes the data analysis required for jolt detection and faster transitions. The MMA8450Q has user selectable full scales of ±2g/±4g/±8g. The device can be configured to generate inertial wake-up interrupt signals from any combination of the configurable embedded functions allowing the MMA8450Q to monitor events and remain in a low power mode during periods of inactivity. The MMA8450Q is available in a 3 x 3 x 1 mm QFN package. Features • 1.71 V to 1.89 V supply voltage • ±2g/±4g/±8g dynamically selectable full-scale • Output Data Rate (ODR) from 400 Hz to 1.563 Hz • 375 μg/√Hz noise at normal mode ODR = 400 Hz • 12-bit digital output • I2C digital output interface (operates up to 400 kHz Fast Mode) • Programmable 2 interrupt pins for 8 interrupt sources • Embedded 4 channels of motion detection – Freefall or motion detection: 2 channels – Pulse Detection: 1 channel – Transient (Jolt) Detection: 1 channel • Orientation (Portrait/Landscape) detection with hysteresis compensation • Automatic ODR change for auto-wake and return-to-sleep • 32 sample FIFO • Self-Test • 10,000g high shock survivability • RoHS compliant MMA8450Q MMA8450Q: XYZ-AXIS ACCELEROMETER ±2g/±4g/±8g Top and Bottom View 16 PIN QFN CASE 2077-01 Top View VDD NC NC 16 VDD NC NC SCL GND 15 14 13 GND GND INT1 1 2 3 4 5 6 SDA MMA8450Q 16 Pin QFN 3mm x 3 mm x 1mm 12 11 10 GND 9 7 SA0 INT2 8 EN Typical Applications Pin Connections • Static orientation detection (portrait/landscape, up/down, left/right, back/ front position identification) • Real-time orientation detection (virtual reality and gaming 3D user position feedback) • Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup) • Motion detection for portable product power saving (auto-sleep and auto-wake for cell phone, PDA, GPS, gaming) • Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) • User interface (menu scrolling by orientation change, tap detection for button replacement ORDERING INFORMATION Part Number MMA8450QT MMA8450QR1 Temperature Range -40°C - +85°C -40°C - +85°C Package Drawing QFN-16 QFN-16 Package Tray Tape and Reel This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. Contents Application Notes for Reference ...............................................................................................................................................6 1 Block Diagram and Pin Description ..................................................................................................................................6 1.1 Block Diagram .............................................................................................................................................................6 Figure 1. Block Diagram ..............................................................................................................................................6 1.2 Pin Description ............................................................................................................................................................6 Figure 2. Direction of the Detectable Accelerations ....................................................................................................6 Figure 3. Application Diagram .....................................................................................................................................7 Table 1. Pin Description ..............................................................................................................................................7 1.3 Soldering Information ..................................................................................................................................................7 2 Mechanical and Electrical Specifications .........................................................................................................................8 2.1 Mechanical Characteristics .........................................................................................................................................8 Table 2. Mechanical Characteristics ...........................................................................................................................8 2.2 Electrical Characteristics .............................................................................................................................................9 Table 3. Electrical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted. .............................................9 2.3 I2C Interface Characteristic .......................................................................................................................................10 Table 4. I2C Slave Timing Values .............................................................................................................................10 Figure 4. I2C Slave Timing Diagram ..........................................................................................................................11 2.4 Absolute Maximum Ratings .......................................................................................................................................11 Table 5. Maximum Ratings ........................................................................................................................................11 Table 6. ESD and Latch-Up Protection Characteristics ............................................................................................11 3 Terminology .......................................................................................................................................................................12 3.1 Sensitivity ..................................................................................................................................................................12 3.2 Zero-g Offset .............................................................................................................................................................12 3.3 Self-Test ....................................................................................................................................................................12 4 Modes of Operation ...........................................................................................................................................................12 Figure 5. MMA8450Q Mode Transition Diagram .......................................................................................................12 Table 7. Mode of Operation Description ....................................................................................................................12 5 Functionality ......................................................................................................................................................................13 5.1 Device Calibration .....................................................................................................................................................13 5.2 8-bit or 12-bit Data .....................................................................................................................................................13 5.3 Internal FIFO Data Buffer ..........................................................................................................................................13 5.4 Low Power Mode .......................................................................................................................................................13 5.5 Auto-Wake/Sleep Mode ............................................................................................................................................14 5.6 Freefall and Motion Detection ...................................................................................................................................14 5.6.1 Freefall Detection ...........................................................................................................................................14 5.6.2 Motion Detection ............................................................................................................................................14 5.7 Transient Detection ...................................................................................................................................................14 5.8 Orientation Detection .................................................................................................................................................15 Figure 6. Illustration of Landscape-to-Portrait Transition .........................................................................................15 Figure 7. Illustration of Portrait-to-Landscape Transition ..........................................................................................15 Figure 8. Illustration of Z-Tilt Angle Lockout Transition .............................................................................................15 Figure 9. Landscape/Portrait Orientation ..................................................................................................................16 5.9 Interrupt Register Configurations ..............................................................................................................................16 Figure 10. System Interrupt Generation Block Diagram ............................................................................................16 5.10 Serial I2C Interface ....................................................................................................................................................17 Table 8. Serial Interface Pin Description ...................................................................................................................17 5.10.1 I2C Operation .................................................................................................................................................17 Table 9. I2C Address Selection Table .......................................................................................................................17 Single Byte Read .........................................................................................................................................................17 Multiple Byte Read .......................................................................................................................................................18 Single Byte Write ..........................................................................................................................................................18 Multiple Byte Write .......................................................................................................................................................18 Table 10. I2C device Address Sequence ..................................................................................................................18 Figure 11. I2C Timing Diagram ..................................................................................................................................18 MMA8450Q Sensors Freescale Semiconductor 2 6 Register Descriptions .......................................................................................................................................................19 Table 11. Register Address Map ...............................................................................................................................19 6.1 Data Registers ...........................................................................................................................................................21 0x00, 0x04, 0x0B: STATUS Registers .........................................................................................................................21 Alias for DR_Status (0x0B) or F_Status (0x10) ...................................................................................................21 0X00, 0X04, 0X0B STATUS: Data Status Registers (Read Only) ......................................................................21 Table 12. STATUS Description .................................................................................................................................21 0x01, 0x02, 0x03: OUT_MSB 8-Bit XYZ Data Registers .............................................................................................22 0x01 OUT_X_MSB: X_MSB Register (Read Only) .............................................................................................22 0x02 OUT_Y_MSB: Y_MSB Register (Read Only) .............................................................................................22 0x03 OUT_Z_MSB: Z_MSB Register (Read Only) .............................................................................................22 0x05 - 0x0A: OUT_MSB and OUT_LSB 12-Bit XYZ Data Registers ...........................................................................22 0x05 OUT_X_LSB: X_LSB Register (Read Only) ...............................................................................................22 0x06 OUT_X_MSB: X_MSB Register (Read Only) .............................................................................................22 0x07 OUT_Y_LSB: Y_LSB Register (Read Only) ...............................................................................................22 0x08 OUT_Y_MSB: Y_MSB Register (Read Only) .............................................................................................22 0x09 OUT_Z_LSB: Z_LSB Register (Read Only) ...............................................................................................22 0x0A OUT_Z_MSB: Z_MSB Register (Read Only) .............................................................................................22 0x0C - 0x0E: OUT_X_DELTA, OUT_Y_DELTA, OUT_Z_DELTA AC Data Registers ................................................23 0x0C OUT_X_DELTA: AC X 8-Bit Data Register (Read Only) ...........................................................................23 0x0D OUT_Y_DELTA: AC Y 8-Bit Data Register (Read Only) ...........................................................................23 0x0E OUT_Z_DELTA: AC Z 8-Bit Data Register (Read Only) ............................................................................23 0x0F: WHO_AM_I Device ID Register .........................................................................................................................23 0x0F WHO_AM_I: Device ID Register (Read Only) ............................................................................................23 6.2 32 Sample FIFO ........................................................................................................................................................23 0x10: F_STATUS FIFO Status Register ......................................................................................................................23 0x10 F_STATUS: FIFO STATUS Register (Read Only) .....................................................................................23 Table 13. FIFO Flag Event Description .....................................................................................................................23 Table 14. FIFO Sample Count Description ...............................................................................................................24 0x11: F_8DATA 8-Bit FIFO Data .................................................................................................................................24 0x11 F_8DATA: 8-Bit FIFO Data Register Points to Register 0x01 (Read Only) ................................................24 0x12: F_12DATA 12-Bit FIFO Data .............................................................................................................................24 0x12 F_12DATA: 12-Bit FIFO Data Register Points to Register 0x05 (Read Only) ............................................24 0x13: F_SETUP FIFO Setup Register .........................................................................................................................24 0x13 F_SETUP: FIFO Setup Register (Read/Write) ...........................................................................................24 0x14: SYSMOD System Mode Register ......................................................................................................................25 0x14 SYSMOD: System Mode Register (Read Only) .........................................................................................25 Table 15. SYSMOD Description ................................................................................................................................25 Table 16. F_SETUP Description ...............................................................................................................................25 0x15: INT_SOURCE System Interrupt Status Register ...............................................................................................26 0x15 INT_SOURCE: System Interrupt Status Register (Read Only) ..................................................................26 Table 17. INT_SOURCE Description ........................................................................................................................26 0x16: XYZ_DATA_CFG Sensor Data Configuration Register .....................................................................................27 0x16 XYZ_DATA_CFG: Sensor Data Configuration Register (Read/Write) .......................................................27 Table 18. XYZ_DATA_CFG Description ................................................................................................................... 27 0x17: HP_FILTER_CUTOFF High Pass Filter Register ...............................................................................................27 0x17 HP_FILTER_CUTOFF: High Pass Filter Register (Read/Write) .................................................................27 Table 19. HP_FILTER_CUTOFF Setting Options .....................................................................................................27 6.3 Portrait/ Landscape Embedded Function Registers ..................................................................................................27 0x18: PL_STATUS Portrait/Landscape Status Register ..............................................................................................27 0x18 PL_STATUS Register (Read Only) ............................................................................................................27 0x19: PL_PRE_STATUS Portrait/Landscape Previous Data Status Register .............................................................28 0x19 PL_PRE_STATUS Register (Read Only) ...................................................................................................28 0x1A: PL_CFG Portrait/Landscape Configuration Register .........................................................................................28 0x1A PL_CFG Register (Read/Write) ..................................................................................................................28 Table 20. PL_CFG Register Description ...................................................................................................................28 0x1B: PL_COUNT Portrait Landscape Debounce Register .........................................................................................28 0x1B PL_COUNT Register (Read/Write) ............................................................................................................28 Table 21. PL_STATUS Register Description ............................................................................................................28 Table 22. PL_COUNT Relationship with the ODR ....................................................................................................29 MMA8450Q Sensors Freescale Semiconductor 3 0x1C: PL_BF_ZCOMP Back/Front and Z Compensation Register ..............................................................................29 0x1C: PL_BF_ZCOMP Register (Read/Write) ....................................................................................................29 Table 23. PL_BF_ZCOMP Description .....................................................................................................................29 Table 24. Back/Front Orientation Definitions .............................................................................................................29 0x1D - 0x1F: PL_P_L_THS_REG1, 2, 3 Portrait-to-Landscape Threshold Registers .................................................29 0x1D PL_P_L_THS_REG1 Register (Read/Write) ..............................................................................................29 Table 25. PL_P_L_THS_REG1 Description ..............................................................................................................29 0x1E PL_P_L_THS_REG2 Register (Read/Write) ..............................................................................................29 Table 26. PL_P_L_THS_REG2 Description ..............................................................................................................29 0x1F PL_P_L_THS_REG3 Register (Read/Write) ..............................................................................................29 0x20 - 0x22 PL_L_P_THS_REG1, 2, 3 Landscape-to-Portrait Threshold Registers ...................................................30 0x20 PL_L_P_THS_REG1 Register (Read/Write) ..............................................................................................30 Table 27. PL_L_P_THS_REG1 Description ..............................................................................................................30 0x21 PL_L_P_THS_REG2 Register (Read/Write) ..............................................................................................30 Table 28. PL_L_P_THS_REG2 Description ..............................................................................................................30 0x22 PL_L_P_THS_REG3 Register (Read/Write) ..............................................................................................30 Table 29. PL_L_P_THS_REG3 Description ..............................................................................................................30 Table 30. Landscape-to-Portrait Trip Angle Thresholds Look-up Table ....................................................................30 Table 31. PL_P_L_THS_REG3 Description ..............................................................................................................30 Table 32. Portrait-to-Landscape Trip Angle Thresholds Look-up Table ....................................................................30 6.4 Freefall & Motion Detection Registers .......................................................................................................................31 0x23: FF_MT_CFG_1 Freefall and Motion Configuration Register 1 ...........................................................................31 0x23 FF_MT_CFG_1 Register (Read/Write) .......................................................................................................31 Table 33. FF_MT_CFG_1 Description ......................................................................................................................31 0x24 FF_MT_SRC_1 Register (Read Only) ................................................................................................................32 0x24: FF_MT_SRC_ Freefall and Motion Source Register (0x24) ......................................................................32 Table 34. FF_MT_SRC_1 Description ......................................................................................................................32 0x25: FF_MT_THS_1 Freefall and Motion Threshold 1 Register ................................................................................32 0x25 FF_MT_THS_1 Register (Read/Write) .......................................................................................................32 Table 35. FF_MT_THS_1 Description .......................................................................................................................32 Figure 12. DBCNTM Bit Function ..............................................................................................................................33 0x26: FF_MT_COUNT_1 Freefall Motion Count 1 Register ........................................................................................33 0x26 FF_MT_COUNT_1 Register (Read/Write) ..................................................................................................33 Table 36. FF_MT_COUNT_1 Description .................................................................................................................33 Table 37. FF_MT_COUNT_1 and FF_MT_COUNT_2 Relationship with the ODR ..................................................33 0x27: FF_MT_CFG_2 Freefall and Motion Configuration 2 Register ...........................................................................34 0x27 FF_MT_CFG_2 Register (Read/Write) .......................................................................................................34 0x28: FF_MT_SRC_2 Freefall and Motion Source 2 Register .....................................................................................34 0x28 FF_MT_SRC_2 Register (Read Only) ........................................................................................................34 0x29: FF_MT_THS_2 Freefall and Motion Threshold 2 Register ................................................................................34 0x29 FF_MT_THS_2 Register (Read/Write) .......................................................................................................34 0x2A: FF_MT_COUNT_2 Freefall and Motion Debounce 2 Register ..........................................................................34 0x2A FF_MT_COUNT_2 Register (Read/Write) .................................................................................................34 6.5 Transient Detection Registers ...................................................................................................................................34 0x2B: TRANSIENT_CFG Transient Configuration Register ........................................................................................34 0x2B TRANSIENT_ CFG Register (Read/Write) .................................................................................................34 Table 38. TRANSIENT_ CFG Description ................................................................................................................34 0x2C: TRANSIENT_SRC Transient Source Register ..................................................................................................34 0x2C TRANSIENT_SRC Register (Read Only) ..................................................................................................34 0x2D: TRANSIENT_THS Transient Threshold Register ..............................................................................................35 0x2D TRANSIENT_THS Register (Read/Write) ..................................................................................................35 Table 39. TRANSIENT_THS Description ..................................................................................................................35 0x2E: TRANSIENT_COUNT Transient Debounce Register ........................................................................................35 0x2E TRANSIENT_COUNT Register (Read/Write) ............................................................................................35 Table 40. TRANSIENT_COUNT Description ............................................................................................................35 Table 41. TRANSIENT_COUNT relationship with the ODR .....................................................................................35 Table 42. TRANSIENT_SRC Description .................................................................................................................35 6.6 Tap Detection Registers ...........................................................................................................................................36 0x2F: PULSE_CFG Pulse Configuration Register .......................................................................................................36 0x2F PULSE_CFG Register (Read/Write) ..........................................................................................................36 Table 43. PULSE_CFG Description ..........................................................................................................................36 MMA8450Q Sensors Freescale Semiconductor 4 0x30: PULSE_SRC Pulse Source Register .................................................................................................................36 0x30 PULSE_SRC Register (Read Only) ............................................................................................................36 Table 44. TPULSE_SRC Description ........................................................................................................................36 0x31 - 0x33: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers ..................................................................37 0x31 PULSE_THSX Register (Read/Write) .........................................................................................................37 Table 45. PULSE_THSX Description ........................................................................................................................37 0x32 PULSE_THSY Register (Read/Write) .........................................................................................................37 Table 46. PULSE_THSY Description ........................................................................................................................37 0x33 PULSE_THSZ Register (Read/Write) .........................................................................................................37 Table 47. PULSE_THSZ Description ........................................................................................................................37 0x34: PULSE_TMLT Pulse Time Window 1 Register ..................................................................................................37 0x34 PULSE_TMLT Register (Read/Write) .........................................................................................................37 Table 48. Time Step for PULSE Time Limit at ODR and Power Mode .....................................................................37 0x35: PULSE_LTCY Pulse Latency Timer Register ....................................................................................................38 0x35 PULSE_LTCY Register (Read/Write) .........................................................................................................38 Table 49. Time Step for PULSE Latency at ODR and Power Mode .........................................................................38 0x36: PULSE_WIND Second Pulse Time Window Register ........................................................................................38 0x36 PULSE_WIND Register (Read/Write) .........................................................................................................38 Table 50. Time Step for PULSE Detection Window at ODR and Power Mode .........................................................38 6.7 Auto-Sleep Registers ................................................................................................................................................38 0x37: ASLP_COUNT Auto-Sleep Inactivity Timer Register .........................................................................................38 0x37 ASLP_COUNT Register (Read/Write) ........................................................................................................38 Table 51. ASLP_COUNT Description .......................................................................................................................38 Table 52. ASLP_COUNT Relationship with ODR .....................................................................................................39 0x38: CTRL_REG1 System Control 1 Register ...........................................................................................................39 0x38 CTRL_REG1 Register (Read/Write) ...........................................................................................................39 Table 53. CTRL_REG1 Description ..........................................................................................................................39 Table 54. Sleep Mode Poll Rate Description .............................................................................................................39 Table 55. System Output Data Rate Selection ..........................................................................................................39 Table 56. Full Scale Selection ...................................................................................................................................40 0x39: CTRL_REG2 System Control 2 Register ...........................................................................................................40 0x39 CTRL_REG2 Register (Read/Write) ...........................................................................................................40 Table 57. CTRL_REG2 Description ..........................................................................................................................40 0x3A: CTRL_REG3 Interrupt Control Register ............................................................................................................40 0x3A CTRL_REG3 Register (Read/Write) ..........................................................................................................40 Table 58. CTRL_REG3 Description ..........................................................................................................................41 0x3C: CTRL_REG5 Register (Read/Write) ..................................................................................................................41 0x3C CTRL_REG5 Register (Read/Write) ..........................................................................................................41 Table 59. interrupt Enable Register Description ........................................................................................................41 0x3C: CTRL_REG5 Interrupt Configuration Register ..................................................................................................42 0x3C CTRL_REG5 Register (Read/Write) ..........................................................................................................42 Table 60. Interrupt Configuration Register Description .............................................................................................42 6.8 User Offset Correction Registers ..............................................................................................................................42 0x3D: OFF_X Offset Correction X Register .................................................................................................................42 0x3D OFF_X Register (Read/Write) ....................................................................................................................42 Table 61. OFF_X Description ....................................................................................................................................42 0x3E: OFF_Y Offset Correction Y Register .................................................................................................................42 0x3E OFF_Y Register (Read/Write) ....................................................................................................................42 Table 62. OFF_Y Description ....................................................................................................................................42 0x3F: OFF_Z Offset Correction Z Register ..................................................................................................................42 0x3F OFF_Z Register (Read/Write) ....................................................................................................................42 Table 63. OFF_Z Description ....................................................................................................................................42 Appendix A ................................................................................................................................................................................43 Table 64. MMA8450Q Register Map .........................................................................................................................43 Table 65. Accelerometer Output Data .......................................................................................................................45 Appendix B ................................................................................................................................................................................46 Figure 13. Distribution of Pre Board Mounted Devices Tested in Sockets (1 count = 3.9 mg) .................................46 Figure 14. Distribution of Post Board Mounted Devices (1 count = 3.9 mg) .............................................................47 Figure 15. 8g Z-axis TCS ..........................................................................................................................................50 Figure 16. 8g X-axis TCO (mg/°C) ............................................................................................................................51 Figure 17. 8g Y-axis TCO (mg/°C) ............................................................................................................................52 Figure 18. 8g Z-axis TCO (mg/°C) ............................................................................................................................53 Package Dimensions ............................................................................................................................................................... 54 MMA8450Q Sensors Freescale Semiconductor 5 Application Notes for Reference The following is a list of Freescale Application Notes written for the MMA8450Q: • AN3915, Embedded Orientation Detection Using the MMA8450Q • AN3916, Offset Calibration of the MMA8450Q • AN3917, Motion and Freefall Detection Using the MMA8450Q • AN3918, High Pass Filtered Data and Transient Detection Using the MMA8450Q • AN3919, MMA8450Q Single/Double and Directional Tap Detection • AN3920, Using the 32 Sample First In First Out (FIFO) in the MMA8450Q • AN3921, Low Power Modes and Auto-Wake/Sleep Using the MMA8450Q • AN3922, Data Manipulation and Basic Settings of the MMA8450Q • AN3923, MMA8450Q Design Checklist and Board Mounting Guidelines 1 1.1 Block Diagram and Pin Description Block Diagram Internal OSC Clock GEN Embedded DSP Functions SDA SCL VDD VSS X-axis Transducer Y-axis Transducer Z-axis Transducer C to V Converter 12-bit ADC I2 C 32 Data Point Configurable FIFO Buffer with Watermark Freefall and Motion Detection (2 channels) Transient Detection (i.e., fast motion, jolt) Enhanced Orientation with Hysteresis and Z-lockout Shake Detection through Motion Threshold Tap and Double Tap Detection Auto-Wake/Auto-Sleep Configurable with debounce counter and multiple motion interrupts for control Normal Mode Low Power Mode Active Mode Auto-Wake Auto-Sleep SLEEP Mode (Reduced Sampling Rate) Figure 1. Block Diagram 1.2 Pin Description Z X 1 13 1 Y 9 5 (TOP VIEW) DIRECTION OF THE DETECTABLE ACCLERATIONS (BOTTOM VIEW) Figure 2. Direction of the Detectable Accelerations MMA8450Q Sensors Freescale Semiconductor 6 1.8V 4.7μF 16 1 2 NC 15 NC 14 VDD VDD NC NC SCL GND 13 GND 12 11 10 9 SDA 1.8V SCL 1.8V 0.1μF 3 4 5 MMA8450Q INT1 GND SDA SA0 4.7kΩ 4.7kΩ GND EN INT2 6 7 8 INT1 INT2 EN SA0 Figure 3. Application Diagram Table 1. Pin Description Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD NC/GND NC/GND SCL GND SDA SA0 EN INT2 GND INT1 GND GND VDD NC NC Description Power Supply (1.8V only) Connect to Ground or Non Connection Connect to Ground or Non Connection I 2C Pin Status Input Input Input Open Drain Input Open Drain Input Input Output Input Output Input Input Input Input Input Serial Clock Connect to Ground I2C Serial Data I2C Least Significant Bit of the Device Address (0: $1C 0: $1D) Device Enable (1: I2C Bus Enabled; 0: Shutdown Mode) Inertial Interrupt 2 Connect to Ground Inertial Interrupt 1 Connect to Ground Connect to Ground Power Supply (1.8V only) Internally not connected Internally not connected When using MMA8450Q in applications, it is recommended that pin 1 and pin 14 (the VDD pins) be tied together. Power supply decoupling capacitors (100 nF ceramic plus 4.7 µF bulk, or a single 4.7 µF ceramic) should be placed as near as possible to the pins 1 and 5 of the device. The SDA and SCL I2C connections are open drain and therefore require a pull-up resistor as shown in Figure 3 Note: The above application diagram presents the recommended configuration for the MMA8450Q. For information on future products of this product family please review Freescale application note, AN3923, Design Checklist and Board Mounting Guidelines of the MMA8450Q.This application note details the small modifications between the MMA8450Q and the next generation products. 1.3 Soldering Information The QFN package is compliant with the RoHS standard. Please refer to AN3923. MMA8450Q 7 Sensors Freescale Semiconductor 2 2.1 Mechanical and Electrical Specifications Mechanical Characteristics Parameter Test Conditions FS[1:0] set to 01 FS[1:0] set to 10 FS[1:0] set to 11 FS Symbol Min ±1.8 ±3.6 ±7.2 0.878 So 1.758 3.515 TCSo Typ ±2 ±4 ±8 0.976 1.953 3.906 ±0.05 Max ±2.2 ±4.4 ±8.8 1.074 2.148 4.296 %/°C mg/digit g Unit Table 2. Mechanical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted. Full Scale Measurement Range Sensitivity FS[1:0] set to 01 FS[1:0] set to 10 FS[1:0] set to 11 Sensitivity Change vs. Temperature(1) Typical Zero-g Level Offset (2) FS[1:0] set to 01 FS[1:0] set to 01 FS[1:0] set to 10 FS[1:0] set to 11 0g-Off ±40 mg Typical Zero-g Offset Post Board Mount (2), (3) FS[1:0] set to 01 FS[1:0] set to 10 FS[1:0] set to 11 0g-OffBM ±50 mg Typical Zero-g Offset Change vs. Temperature Non Linearity Best Fit Straight Line (2) TCOff FS[1:0] set to 01 FS[1:0] set to 10 FS[1:0] set to 11 NL ±0.5 ±0.25 ±0.5 ±1 -195 mg/°C % FS Self-test Output Change(4) FS[1:0] set to 01, X-axis FS[1:0] set to 01, Y-axis FS[1:0] set to 01, Z-axis Vst -195 +945 LSB Output Noise Operating Temperature Range 1. 2. 3. 4. Normal Mode ODR = 400 Hz Noise Top -40 375 +85 μg/√Hz °C Before board mount. See appendix for distribution graphs. Post board mount offset specification are based on an 8 layer PCB. Self-test in one direction only. These are approximate values and can change by ±100 counts. MMA8450Q Sensors Freescale Semiconductor 8 Table 3. Electrical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted.(1) Parameter Supply Voltage Low Power Mode $39 CTRL_REG2: MOD[0]=1 EN = 1, ODR = 1.563 Hz EN = 1, ODR = 12.5 Hz EN = 1, ODR = 50 Hz EN = 1, ODR = 100 Hz EN = 1, ODR = 200 Hz EN = 1, ODR = 400 Hz Normal Mode $39 CTRL_REG2: MOD[0]=0 EN = 1, ODR = 1.563 Hz EN = 1, ODR = 12.5 Hz EN = 1, ODR = 50 Hz EN = 1, ODR = 100 Hz EN = 1, ODR = 200 Hz EN = 1, ODR = 400 Hz Current Consumption in Shutdown Mode Supply Current Drain in Standby Mode Digital High Level Input Voltage SCL, SDA, SA0, EN Digital Low Level Input Voltage SCL, SDA, SA0, EN High Level Output Voltage INT1, INT2 Low Level Output Voltage INT1, INT2 Low Level Output Voltage SDA Output Data Rate Signal Bandwidth Boot Time from EN = 1 to Boot Complete Turn-on time(1) IO = 500 μA IO = 500 μA IO = 500 μA EN = 0 EN = 1 and FS[1:0] = 00 IddSdn IddStby VIH VIL VOH VOL VOLS ODR BW BT Ton 0.9*ODR ODR ODR/2 1.55 3/ODR 0.9*VDD 0.1*VDD 0.1*VDD 1.1*ODR 0.75*VDD 0.3*VDD Idd IddLP Test Conditions Symbol VDD Min 1.71 Typ 1.8 27 27 27 42 72 120 42 42 42 72 132 225 280° Z < 75° or Z > 285° Z < 70° or Z > 290° Z < 65° or Z > 295° Front → Back Transition Z > 100° and Z < 260° Z > 105° and Z < 255° Z > 110° and Z < 250° Z > 115° and Z < 245° 0x1D - 0x1F: PL_P_L_THS_REG1, 2, 3 Portrait-to-Landscape Threshold Registers The following registers represent the Portrait-to-Landscape trip threshold registers. These registers are used to set the trip angle for the image transition from the Portrait orientation to the Landscape orientation. The angle can be selected from Table 28 and the corresponding values for that angle should be written into the three PL_P_L_THS Registers. 0x1D PL_P_L_THS_REG1 Register (Read/Write) Bit 7 P_L_THS[7] Bit 6 P_L_THS[6] Bit 5 P_L_THS[5] Bit 4 P_L_THS[4] Bit 3 P_L_THS[3] Bit 2 P_L_THS[2] Bit 1 P_L_THS[1] Bit 0 P_L_THS[0] Table 25. PL_P_L_THS_REG1 Description P_L_THS Portrait-to-Landscape Threshold Register 1. Default value: 30° → 0001_1010. 0x1E PL_P_L_THS_REG2 Register (Read/Write) Bit 7 P_L_THS[7] Bit 6 P_L_THS[6] Bit 5 P_L_THS[5] Bit 4 P_L_THS[4] Bit 3 P_L_THS[3] Bit 2 P_L_THS[2] Bit 1 P_L_THS[1] Bit 0 P_L_THS[0] Table 26. PL_P_L_THS_REG2 Description P_L_THS Portrait-to-Landscape Threshold Register 2. Default value: 30° → 0010_0010. 0x1F PL_P_L_THS_REG3 Register (Read/Write) Bit 7 P_L_THS[7] Bit 6 P_L_THS[6] Bit 5 P_L_THS[5] Bit 4 P_L_THS[4] Bit 3 P_L_THS[3] Bit 2 P_L_THS[2] Bit 1 P_L_THS[1] Bit 0 P_L_THS[0] MMA8450Q 29 Sensors Freescale Semiconductor Table 27. PL_P_L_THS_REG3 Description P_L_THS Portrait-to-Landscape Threshold Register 3. Default value: 30°→ 1101_0100. Table 28. Portrait-to-Landscape Trip Angle Thresholds Look-up Table Portrait-to-Landscape Trip Angle 15 20 25 30 35 40 45 50 55 60 PL_P_L_THS_REG1 0x17 0x18 0x18 0x1A 0x1B 0x1D 0x20 0x23 0x27 0x2D PL_P_L_THS_REG2 0x75 0x14 0xF3 0xA2 0x1A 0x92 0x00 0x31 0x71 0x41 PL_P_L_THS_REG3 0x77 0x23 0x59 0x77 0x1A 0x33 0x00 0xD9 0xBA 0xA2 0x20 - 0x22 PL_L_P_THS_REG1, 2, 3 Landscape-to-Portrait Threshold Registers The following registers represent the Landscape-to-Portrait trip threshold registers. These registers are used to set the trip angle for the image transition from the Landscape orientation to the Portrait orientation. The angle can be selected from Table 32 and the corresponding values for that angle should be written into the three PL_L_P_THS Registers. 0x20 PL_L_P_THS_REG1 Register (Read/Write) Bit 7 L_P_THS[7] Bit 6 L_P_THS[6] Bit 5 L_P_THS[5] Bit 4 L_P_THS[4] Bit 3 L_P_THS[3] Bit 2 L_P_THS[2] Bit 1 L_P_THS[1] Bit 0 L_P_THS[0] Table 29. PL_L_P_THS_REG1 Description L_P_THS Landscape-to-Portrait Threshold Register 1. Default value: 60° → 0010_1101. 0x21 PL_L_P_THS_REG2 Register (Read/Write) Bit 7 L_P_THS[7] Bit 6 L_P_THS[6] Bit 5 L_P_THS[5] Bit 4 L_P_THS[4] Bit 3 L_P_THS[3] Bit 2 L_P_THS[2] Bit 1 L_P_THS[1] Bit 0 L_P_THS[0] Table 30. PL_L_P_THS_REG2 Description L_P_THS Landscape-to-Portrait Threshold Register 2. Default value: 60° → 0100_0001. 0x22 PL_L_P_THS_REG3 Register (Read/Write) Bit 7 L_P_THS[7] Bit 6 L_P_THS[6] Bit 5 L_P_THS[5] Bit 4 L_P_THS[4] Bit 3 L_P_THS[3] Bit 2 L_P_THS[2] Bit 1 L_P_THS[1] Bit 0 L_P_THS[0] Table 31. PL_L_P_THS_REG3 Description L_P_THS Landscape-to-Portrait Threshold Register 3. Default value: 60° → 1010_0010. Table 32. Landscape-to-Portrait Trip Angle Thresholds Look-up Table Landscape-to-Portrait Trip Angle 30 35 40 45 50 PL_L_P_THS_REG1 0x1A 0x1B 0x1D 0x20 0x23 PL_L_P_THS_REG2 0x22 0xA2 0x92 0x00 0x31 PL_L_P_THS_REG3 0xD4 0x77 0x33 0x00 0xD9 MMA8450Q Sensors Freescale Semiconductor 30 Table 32. Landscape-to-Portrait Trip Angle Thresholds Look-up Table 55 60 65 70 75 0x27 0x2D 0x35 0x42 0x57 0x71 0x41 0x91 0x31 0x71 0xBA 0xA2 0x8F 0x81 0x77 6.4 Freefall & Motion Detection Registers For details on how to configure the device for Freefall and/or Motion detection and for sample code, refer to application note AN3917. Note: There are two Freefall and Motion Detection Functions. The registers from 0x27 - 0x2A have the same descriptions as registers 0x23 - 0x26. 0x23: FF_MT_CFG_1 Freefall and Motion Configuration Register 1 0x23 FF_MT_CFG_1 Register (Read/Write) Bit 7 ELE Bit 6 OAE Bit 5 ZHEFE Bit 4 ZLEFE Bit 3 YHEFE Bit 2 YLEFE Bit 1 XHEFE Bit 0 XLEFE Table 33. FF_MT_CFG_1 Description ELE Event Latch Enable: Event flag is latched into FF_MT_SRC_1 register. Reading of the FF_MT_SRC_1 register clears the EA event flag. Default value: 0 0: Event flag latch disabled; 1: Event flag latch enabled Logical Or/And combination of events flags. Default value: 0 0: Logical AND combination of events flags; 1: Logical OR combination of events flags Event flag enable on Z High event. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on Z Low event. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on Y High event. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on Y Low event. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on X High event. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on X Low event. Default value: 0 0: Event detection disabled; 1: Event detection enabled OAE ZHEFE ZLEFE YHEFE YLEFE XHEFE XLEFE OAE bit allows the selection between Motion (logical OR combination of X, Y, Z-axis event flags) and Freefall (logical AND combination of X, Y, Z-axis event flags) detection. ELE denotes whether the enabled event flag will be latched in the FF_MT_SRC_1 register or the event flag status in the FF_MT_SRC_1 will indicate the real-time status of the event. If ELE bit is set to a logic 1, then the event active “EA” flag is cleared by reading the FF_MT_SRC_1 source register. ZHEFE, YHEFE, XHEFE enables the detection of a high g event when the measured acceleration data on X, Y, or Z-axis is higher than the threshold set in FF_MT_THS_1 register. ZLEFE, YLEFE, XLEFE enables the detection of a low g event when the measured acceleration data on X, Y, or Z-axis is lower than the threshold set in FF_MT_THS_1 register. FF_MT_THS_1 is the threshold register used by the Freefall/Motion function to detect Freefall or Motion events. The unsigned 7-bit FF_MT_THS_1 threshold register holds the threshold for the low g event detection where the magnitude of the X and Y and Z acceleration values are lower than the threshold value. Conversely the FF_MT_THS_1 also holds the threshold for the high g event detection where the magnitude of the X, or Y, or Z-axis acceleration values is higher than the threshold value. MMA8450Q 31 Sensors Freescale Semiconductor 0x24 FF_MT_SRC_1 Register 0x24: FF_MT_SRC_ Freefall and Motion Source Register (0x24) (Read Only) Bit 7 — Bit 6 EA Bit 5 ZHE Bit 4 ZLE Bit 3 YHE Bit 2 YLE Bit 1 XHE Bit 0 XLE Table 34. FF_MT_SRC_1 Description EA ZHE ZLE YHE YLE XHE XLE Event Active Flag. Default value: 0 0: No event flag has been asserted; 1: one or more event flags have been asserted. Z High Event Flag. Default value: 0 0: No Z High event detected, 1: Z High event has been detected Z Low Event Flag. Default value: 0 0: No Z Low event detected, 1: Z Low event has been detected Y High Event Flag. Default value: 0 0: No Y High event detected, 1: Y High event has been detected Y Low Event Flag. Default value: 0 0: No Y Low event detected, 1: Y Low event has been detected X High Event Flag. Default value: 0 0: No X High event detected, 1: X High event has been detected X Low Event Flag. Default value: 0 0: No X Low event detected, 1: X Low event has been detected This register keeps track of the acceleration event which is triggering (or has triggered, in case of ELE bit in FF_MT_CFG_1 register being set to 1) the event flag. In particular EA is set to a logic 1 when the logical combination of acceleration events flags specified in FF_MT_CFG_1 register is true. This bit is used in combination with the values in INT_EN_FF_MT_1 and INT_CFG_FF_MT_1 register to generate the Freefall/Motion interrupts. An X,Y, or Z high or an X,Y, and Z high event is true when the acceleration value of the X or Y or Z axes is higher than the preset threshold value defined in the FF_MT_THS_1 register. Conversely X,Y, or Z high or an X,Y, and Z low event is true when the acceleration value of the X and Y and Z axes are lower than the preset threshold value defined in the FF_MT_THS_1 register. When the ELE bit is set, only the EA bit is latched. The other bits are not latched. To see the events that have been detected, the register must be read immediately. The EA bit will remain high until the source register is read. 0x25: FF_MT_THS_1 Freefall and Motion Threshold 1 Register 0x25 FF_MT_THS_1 Register (Read/Write) Bit 7 DBCNTM Bit 6 THS6 Bit 5 THS5 Bit 4 THS4 Bit 3 THS3 Bit 2 THS2 Bit 1 THS1 Bit 0 THS0 Table 35. FF_MT_THS_1 Description DBCNTM THS[6:0] Debounce counter mode selection. Default value: 0. 0: increments or decrements debounce, 1: increments or clears counter. Freefall /Motion Threshold: default value: 000 0000 The minimum threshold resolution is dependent on the selected acceleration g range and the threshold register has a range of 0 to 127. Therefore: • If the selected acceleration g range is 8g mode (FS = 11), the minimum threshold resolution is 0.063g/LSB. The maximum value is 8g. • If the selected acceleration g range is 4g mode (FS = 10), the minimum threshold resolution is 0.0315g/LSB. The maximum value is 4g. • If the selected acceleration g range is 2g mode (FS = 01), the minimum threshold resolution is 0.01575g/LSB. The maximum value is 2g. When DBCNTM bit is a logic ‘1’, the debounce counter is cleared to 0 whenever the event of interest is no longer true (Figure 12 part b) while if the DBCNTM bit is set a logic ‘0’ the debounce counter is decremented by 1 whenever the event of interest is no longer true (Figure 12 part c) until the debounce counter reaches 0 or the event of interest becomes active. Decrementing of the debounce counter acts as a median filter enabling the system to filter out irregular spurious events which might impede the detection of the event. MMA8450Q Sensors Freescale Semiconductor 32 Low g Event on all 3-axis (Freefall) Count Threshold FF_MT Counter Value (a) EA FF Low g Event on all 3-axis (Freefall) DBCNTM = 1 Count Threshold FF_MT Counter Value EA FF (b) Low g Event on all 3-axis (Freefall) Count Threshold FF_MT Counter Value DBCNTM = 0 (c) EA FF Figure 12. DBCNTM Bit Function 0x26: FF_MT_COUNT_1 Freefall Motion Count 1 Register This register sets the number of debounce sample counts for the event trigger. 0x26 FF_MT_COUNT_1 Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 36. FF_MT_COUNT_1 Description D[7-0] Count value. Default value: 0000_0000 D7 - D0 define the number of debounce sample counts for the event trigger. When the debounce counter exceeds the FF_MT_COUNT_1 value, a Freefall/Motion event flag is set. The time step used for the debounce sample count depends on the ODR chosen (Table 37). Table 37. FF_MT_COUNT_1 and FF_MT_COUNT_2 Relationship with the ODR Output Data Rate (Hz) 400 200 100 50 12.5 1.56 Step 2.5 ms 5 ms 10 ms 20 ms 80 ms 640 ms Duration Range 2.5 ms – 0.63s 5 ms – 1.275s 10 ms – 2.55s 20 ms – 5.1s 80 ms – 20.4s 640 ms – 163s An ODR of 100 Hz and a FF_MT_COUNT_1 value of 15 would result in a debounce response time of 150 ms. MMA8450Q 33 Sensors Freescale Semiconductor 0x27: FF_MT_CFG_2 Freefall and Motion Configuration 2 Register These registers all have the same descriptions as above for Registers 0x23 - 0x26. 0x27 FF_MT_CFG_2 Register (Read/Write) Bit 7 ELE Bit 6 OAE Bit 5 ZHEFE Bit 4 ZLEFE Bit 3 YHEFE Bit 2 YLEFE Bit 1 XHEFE Bit 0 XLEFE 0x28: FF_MT_SRC_2 Freefall and Motion Source 2 Register 0x28 FF_MT_SRC_2 Register (Read Only) Bit 7 — Bit 6 EA Bit 5 ZHE Bit 4 ZLE Bit 3 YHE Bit 2 YLE Bit 1 XHE Bit 0 XLE 0x29: FF_MT_THS_2 Freefall and Motion Threshold 2 Register 0x29 FF_MT_THS_2 Register (Read/Write) Bit 7 DBCNTM Bit 6 THS6 Bit 5 THS5 Bit 4 THS4 Bit 3 THS3 Bit 2 THS2 Bit 1 THS1 Bit 0 THS0 0x2A: FF_MT_COUNT_2 Freefall and Motion Debounce 2 Register 0x2A FF_MT_COUNT_2 Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 6.5 Transient Detection Registers For more information on the uses of the transient function and sample code, refer to application note AN3918. 0x2B: TRANSIENT_CFG Transient Configuration Register The transient detection mechanism can be configured to raise an interrupt when the magnitude of the high pass filtered data is greater than a user definable threshold. The TRANSIENT_CFG register is used to enable the transient interrupt generation mechanism for each of the 3 axes (X, Y, Z) of acceleration. 0x2B TRANSIENT_ CFG Register (Read/Write) Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 ELE Bit 2 ZTEFE Bit 1 YTEFE Bit 0 XTEFE Table 38. TRANSIENT_ CFG Description ELE Transient event flag is latched into the TRANSIENT_SRC register. Reading of the TRANSIENT_SRC register clears the event flag. Default value: 0 0: event flag latch disabled; 1: Event flag latch enabled Event flag enable on Z-axis. Default value: 0 0: Event detection disabled; 1: Event detection Enabled Event flag enable on Y-axis. Default value: 0 0: Event detection disabled; 1: Event detection Enabled Event flag enable on X-axis. Default value: 0 0: Event detection disabled; 1: Event detection Enabled ZTEFE YTEFE XTEFE 0x2C: TRANSIENT_SRC Transient Source Register The transient source register is read to determine the source of an interrupt. When the ELE bit is set in Register0x2B the “EA” event Active bit in the source register is latched. The other bits in the source register are not latched. The source register must be read immediately following the interrupt to determine the axes the event occurred on. 0x2C TRANSIENT_SRC Register (Read Only) Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 EA Bit 2 ZTRANSE Bit 1 YTRANSE Bit 0 XTRANSE MMA8450Q Sensors Freescale Semiconductor 34 Table 39. TRANSIENT_SRC Description EA ZTRANSE YTRANSE XTRANSE Event Active Flag. Default value: 0 0: No event flag asserted; 1: one or more event flag has been asserted. Z transient event. Default value: 0 0: No Z event detected, 1: Z event detected Y transient event. Default value: 0 0: No Y event detected, 1: Y event detected X transient event. Default value: 0 0: No X event detected, 1: X event detected 0x2D: TRANSIENT_THS Transient Threshold Register The TRANSIENT_THS register sets the threshold limit for the high pass filtered acceleration. The value in the TRANSIENT_THS register corresponds to a g value which is compared against the values of OUT_X_DELTA, OUT_Y_DELTA, and OUT_Z_DELTA. If the acceleration exceeds the threshold limit an event flag is raised and an interrupt is generated if interrupts are enabled. 0x2D TRANSIENT_THS Register (Read/Write) Bit 7 DBCNTM Bit 6 THS6 Bit 5 THS5 Bit 4 THS4 Bit 3 THS3 Bit 2 THS2 Bit 1 THS1 Bit 0 THS0 Table 40. TRANSIENT_THS Description DBCNTM THS[6:0] Debounce counter mode selection. Default value: 0 0: increments or decrements debounce; 1: increments or clears counter Transient Threshold: default value: 000_0000 The minimum threshold resolution is dependent on the selected acceleration g range and the threshold register has a range of 0 to 127. Therefore: • If the selected acceleration g range is 8g mode (FS = 11), the minimum threshold resolution is 0.063g/LSB. The maximum is 8g. • If the selected acceleration g range is 4g mode (FS = 10), the minimum threshold resolution is 0.0315g/LSB. The maximum is 4g. • If the selected acceleration g range is 2g mode (FS = 01), the minimum threshold resolution is 0.01575g/LSB. The maximum is 2g. • The DBCNTM bit behaves in the same manner described previously for the Motion/Freefall 1. 0x2E: TRANSIENT_COUNT Transient Debounce Register The TRANSIENT_COUNT sets the minimum number of debounce counts continuously matching the condition where the unsigned value of OUT_X_DELTA or OUT_Y_DELTA or OUT_Z_DELTA register is greater than the user specified value of TRANSIENT_THS. 0x2E TRANSIENT_COUNT Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 41. TRANSIENT_COUNT Description D[7-0] Count value. Default value: 0000_0000 The time step for the Transient detection debounce counter is set by the value of the system ODR. Table 42. TRANSIENT_COUNT relationship with the ODR Output Data Rate (Hz) 400 200 100 50 12.5 1.56 Step 2.5 ms 5 ms 10 ms 20 ms 80 ms 640 ms Duration Range 2.5 ms – 0.637s 5 ms – 1.275s 10 ms – 2.55s 20 ms – 5.1s 80 ms – 20.4s 640 ms – 163s An ODR of 100 Hz and a TRANSIENT_COUNT value of 15 would result in a debounce response time of 150 ms. MMA8450Q 35 Sensors Freescale Semiconductor 6.6 Tap Detection Registers For more details of how to configure the tap detection and sample code please refer to Freescale application note, AN3919. The tap detection registers are referred to as “Pulse”. 0x2F: PULSE_CFG Pulse Configuration Register This register configures the event flag for the tap detection for enabling/disabling the detection of a single and double pulse on each of the axes. 0x2F PULSE_CFG Register (Read/Write) Bit 7 DPA Bit 6 ELE Bit 5 ZDPEFE Bit 4 ZSPEFE Bit 3 YDPEFE Bit 2 YSPEFE Bit 1 XDPEFE Bit 0 XSPEFE Table 43. PULSE_CFG Description Double Pulse Abort. 0: Double Pulse detection is not aborted if the start of a pulse is detected during the time period specified by the PULSE_LTCY register. 1: Setting the DPA bit momentarily suspends the double tap detection if the start of a pulse is detected during the time period specified by the PULSE_LTCY register and the pulse ends before the end of the time period specified by the PULSE_LTCY register. Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag. Default value: 0 0: Event flag latch disabled; 1: Event flag latch enabled Event flag enable on double pulse event on Z-axis. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on single pulse event on Z-axis. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on double pulse event on Y-axis. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on single pulse event on Y-axis. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on double pulse event on X-axis. Default value: 0 0: Event detection disabled; 1: Event detection enabled Event flag enable on single pulse event on X-axis. Default value: 0 0: Event detection disabled; 1: Event detection enabled DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE 0x30: PULSE_SRC Pulse Source Register This register indicates a double or single pulse event has occurred. The corresponding axis and event must be enabled in Register 0x2F for the event to be seen in the source register. 0x30 PULSE_SRC Register (Read Only) Bit 7 — Bit 6 EA Bit 5 ZDPE Bit 4 ZSPE Bit 3 YDPE Bit 2 YSPE Bit 1 XDPE Bit 0 XSPE Table 44. TPULSE_SRC Description EA ZDPE ZSPE YDPE YSPE XDPE XSPE Event Active Flag. Default value: 0 0: no event flag has been asserted; 1: one or more events have been asserted Double pulse on Z-axis event. Default value: 0 0: no event detected; 1: Double Z event detected Single pulse on Z-axis event. Default value: 0 0: no event detected; 1: Single Z event detected Double pulse on Y-axis event. Default value: 0 0: no event detected; 1: Double Y event detected Single pulse on Y-axis event. Default value: 0 0: no event detected; 1: Single Y event detected Double pulse on X-axis event. Default value: 0 0: no event detected; 1: Double X event detected Single pulse on X-axis event. Default value: 0 0: no event detected; 1: Single X event detected MMA8450Q Sensors Freescale Semiconductor 36 0x31 - 0x33: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers The pulse threshold can be set separately for the X, Y and Z axes. The threshold values range from 0 to 31 counts with steps of 0.258g/LSB at a fixed 8g acceleration range, thus the minimum resolution is always fixed at 0.258g/LSB irrespective of the selected g range. The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold which is used by the system to start the pulse detection procedure. The threshold value is expressed over 5-bits as an unsigned number. 0x31 PULSE_THSX Register (Read/Write) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 THSX4 Bit 3 THSX3 Bit 2 THSX2 Bit 1 THSX1 Bit 0 THSX0 Table 45. PULSE_THSX Description THSX4, THSX0 Pulse Threshold on X-axis. Default value: 0_0000 0x32 PULSE_THSY Register (Read/Write) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 THSY4 Bit 3 THSY3 Bit 2 THSY2 Bit 1 THSY1 Bit 0 THSY0 Table 46. PULSE_THSY Description THSY4, THSY0 Pulse Threshold on Y-axis. Default value: 0_0000 0x33 PULSE_THSZ Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0 Table 47. PULSE_THSZ Description THSZ4, THSZ0 Pulse Threshold on Z-axis. Default value: 0_0000 0x34: PULSE_TMLT Pulse Time Window 1 Register 0x34 PULSE_TMLT Register (Read/Write) Bit 7 Tmlt7 Bit 6 Tmlt6 Bit 5 Tmlt5 Bit 4 Tmlt4 Bit 3 Tmlt3 Bit 2 Tmlt2 Bit 1 Tmlt1 Bit 0 Tmlt0 The bits Tmlt7 through Tmlt0 define the maximum time interval that can elapse between the start of the acceleration on the selected axis exceeding the specified threshold and the end when the acceleration on the selected axis must go below the specified threshold to be considered a valid pulse. The minimum time step for the pulse time limit is defined in Table 48. Maximum time for a given ODR is the minimum time step at the given power mode multiplied by 255. The time steps available are dependent on whether the device is in Normal Power mode or in Low Power mode. Notice in the table below that the time step is twice as long in Low Power mode. Table 48. Time Step for PULSE Time Limit at ODR and Power Mode Output Data Rate (Hz) 400 200 100 50 12.5 1.56 Step at Normal Mode 0.625 ms 1.25 ms 2.5 ms 5 ms 5 ms 5 ms Step at Low Power Mode 1.25 ms 2.5 ms 5.0 ms 10 ms 10 ms 10 ms Therefore an ODR setting of 400 Hz with normal power mode would result in a maximum pulse time limit of (0.625 ms * 255) ≥ 159 ms. MMA8450Q 37 Sensors Freescale Semiconductor 0x35: PULSE_LTCY Pulse Latency Timer Register 0x35 PULSE_LTCY Register (Read/Write) Bit 7 Ltcy7 Bit 6 Ltcy6 Bit 5 Ltcy5 Bit 4 Ltcy4 Bit 3 Ltcy3 Bit 2 Ltcy2 Bit 1 Ltcy1 Bit 0 Ltcy0 The bits Ltcy7 through Ltcy0 define the time interval that starts after the first pulse detection. During this time interval, all pulses are ignored. Note: This timer must be set for single pulse and for double pulse. The minimum time step for the pulse latency is defined in Table 49. The maximum time is the time step at the ODR and Power Mode multiplied by 255. Notice that the time step is twice the duration if the device is operating in Low Power mode, as shown below. Table 49. Time Step for PULSE Latency at ODR and Power Mode Output Data Rate (Hz) 400 200 100 50 12.5 1.56 Step at Normal Mode 1.25 ms 2.5 ms 5.0 ms 10 ms 10 ms 10 ms Step at Low Power Mode 2.5 ms 5.0 ms 20 ms 20 ms 20 ms 20 ms 0x36: PULSE_WIND Second Pulse Time Window Register 0x36 PULSE_WIND Register (Read/Write) Bit 7 Wind7 Bit 6 Wind6 Bit 5 Wind5 Bit 4 Wind4 Bit 3 Wind3 Bit 2 Wind2 Bit 1 Wind1 Bit 0 Wind0 The bits Wind7 through Wind0 define the maximum interval of time that can elapse after the end of the latency interval in which the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The detected second pulse width must be shorter than the time limit constraints specified by the PULSE_TMLT register, but the end of the double pulse need not finish within the time specified by the PULSE_WIND register. The minimum time step for the pulse window is defined in Table 50. The maximum time is the time step at the ODR and Power Mode multiplied by 255. Table 50. Time Step for PULSE Detection Window at ODR and Power Mode Output Data Rate (Hz) 400 200 100 50 12.5 1.56 Step at Normal Mode 1.25 ms 2.5 ms 5.0 ms 10 ms 10 ms 10 ms Step at Low Power Mode 2.5 ms 5.0 ms 20 ms 20 ms 20 ms 20 ms 6.7 Auto-Sleep Registers For additional information on how to configure the device for the Auto-Sleep/Wake feature, refer to AN3921. 0x37: ASLP_COUNT Auto-Sleep Inactivity Timer Register The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value specified in the DR[2:0] to ASLP_RATE (Reg 0x38) value provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register. 0x37 ASLP_COUNT Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 51. ASLP_COUNT Description D[7-0] Duration value. Default value: 0000 0000 MMA8450Q Sensors Freescale Semiconductor 38 D7-D0 defines the minimum duration time to change current ODR value from DR to ASLP_RATE. Time step and maximum value depend on the ODR chosen (see Table 52). Table 52. ASLP_COUNT Relationship with ODR Output Data Rate (ODR) 400 200 100 50 12.5 1.56 Duration 0 to 81s 0 to 81s 0 to 81s 0 to 81s 0 to 81s 0 to 325.125s Step 320 ms 320 ms 320 ms 320 ms 320 ms 640 ms In order to wake the device, the desired function or functions must be enabled and set to “Wake From Sleep”. All enabled functions will still function in sleep mode at the sleep ODR. Only the functions that have been selected for “Wake From Sleep” will wake the device. MMA8450Q has 6 functions that can be used to keep the sensor from falling asleep namely, Transient, Orientation, Tap, Motion/FF1 and Motion/FF2 and the FIFO. One or more of these functions can be enabled. In order to wake the device, functions are provided namely, Transient, Orientation, Tap, and the two Motion/Freefall. Note that the FIFO does not wake the device. The Auto-Wake/Sleep interrupt does not affect the wake/sleep, nor does the data ready interrupt. The FIFO gate (bit 7) in Register 0x3A, when set, will hold the last data in the FIFO before transitioning to a different ODR. After the buffer is flushed, it will accept new sample data at the current ODR. See Register 0x3A for the wake from sleep bits. If the Auto-Sleep bit is disabled, then the device can only toggle between Standby and Wake Mode by writing to the FS0 and FS1 bits in Register 0x38 Ctrl Reg1. If Auto-Sleep interrupt is enabled, transitioning from Active mode to Auto-Sleep mode and vice versa generates an interrupt. 0x38: CTRL_REG1 System Control 1 Register 0x38 CTRL_REG1 Register (Read/Write) Bit 7 ASLP_RATE1 Bit 6 ASLP_RATE0 Bit 5 0 Bit 4 DR2 Bit 3 DR1 Bit 2 DR0 Bit 1 FS1 Bit 0 FS0 Table 53. CTRL_REG1 Description ASLP_RATE [1:0] DR[2:0] FS[1:0] This register configures the Auto-Wake sample frequency when the device is in Sleep Mode. See Table 54 for more information. Data rate selection. Default value: 000 Full Scale selection. Default value: 00 (00: Standby mode; 01: active mode ±2g; 10: active mode ±4g; 11: active mode ±8g) Table 54. Sleep Mode Poll Rate Description ASLP_RATE1 0 0 1 1 ASLP_RATE0 0 1 0 1 Frequency (Hz) 50 25 12.5 1.56 It is important to note that when the device is in Auto-Sleep mode, the system ODR and the data rate for all the system functional blocks are overwritten by the data rate set by the ASLP_RATE field in Register 0x38. DR[2:0] bits select the output data rate (ODR) for acceleration samples. The default value is 000 for a data rate of 400 Hz. Table 55. System Output Data Rate Selection DR2 0 0 DR1 0 0 DR0 0 1 Output Data Rate (ODR) 400 Hz 200 Hz Time Between Data Samples 2.5 ms 5 ms MMA8450Q 39 Sensors Freescale Semiconductor Table 55. System Output Data Rate Selection 0 0 1 1 1 1 0 0 0 1 0 1 100 Hz 50 Hz 12.5 Hz 1.563 Hz 10 ms 20 ms 80 ms 640 ms FS[1:0] bits select between standby mode and active mode. The default value is 00 for standby mode. Table 56. Full Scale Selection FS1 0 0 1 1 FS0 0 1 0 1 Mode Standby Active Active Active g Range — ±2g ±4g ±8g 0x39: CTRL_REG2 System Control 2 Register 0x39 CTRL_REG2 Register (Read/Write) Bit 7 ST Bit 6 BOOT Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 SLPE Bit 0 MODS Table 57. CTRL_REG2 Description ST BOOT SLPE(1) Self-Test Enable. Default value: 0 0: Self-Test disabled; 1: Self-Test enabled Reboot device content (Software Reset). Default value: 0 0: device reboot disabled; 1: device reboot enabled. Auto-Sleep enable. Default value: 0 0: Auto-Sleep is not enabled; 1: Auto-Sleep is enabled. Low power mode / Normal mode selection. Default value: 0 0: normal mode; 1: low power mode. MODS 1. When SLPE = 1, the transitioning between sleep mode and wake mode results in a FIFO flush and a reset of internal functional block counters. All functional block status information are preserve except otherwise stated. See Table 58 for more information about the FIFO_GATE bit in CTRL_REG3 register. ST bit activates the Self-Test function. When ST is set to one, an output change will occur to the device outputs (refer to Table 2 and Table 3) thus allowing host application to check the functionality of the entire signal chain. BOOT bit is used to activate the software reset. The Boot mechanism can be enabled in STANDBY and ACTIVE mode. When the Boot bit is enabled the Boot mechanism resets all functional block registers and loads the respective internal registers with default NVM values. The system will automatically transition to standby mode if not already in standby mode before the software reset (re-BOOT process) can occur. Note: The I2C communication system is reset to avoid accidental corrupted data access. 0x3A: CTRL_REG3 Interrupt Control Register 0x3A CTRL_REG3 Register (Read/Write) Bit 7 FIFO_GATE Bit 6 WAKE_TRANS Bit 5 WAKE_LNDPRT Bit 4 Bit 3 Bit 2 Bit 1 IPOL Bit 0 PP_OD WAKE_PULSE WAKE_FF_MT_1 WAKE_FF_MT_2 MMA8450Q Sensors Freescale Semiconductor 40 Table 58. CTRL_REG3 Description 0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from wake-to-sleep mode or from sleep-towake mode. 1: The FIFO input buffer is blocked when transitioning from “wake-to-sleep” mode or from “sleep-to-wake” mode until the FIFO_GATE FIFO is flushed. Although the system transitions from “wake-to-sleep” or from “sleep-to-wake” the contents of the FIFO buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application. If the FIFO_GATE bit is set to logic 1 and the FIFO buffer is not emptied before the arrival of the next sample, then the FGERR bit in the SYS_MOD register (0x14) will be asserted. The FGERR bit remains asserted as long as the FIFO buffer remains un-emptied. Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register. 0: Transient function is bypassed in sleep mode 1: Transient function interrupt can wake up system 0: Orientation function is bypassed in sleep mode 1: Orientation function interrupt can wake up system 0: Pulse function is bypassed in sleep mode 1: Pulse function interrupt can wake up system 0: Freefall/Motion1 function is bypassed in sleep mode 1: Freefall/Motion1 function interrupt can wake up 0: Freefall/Motion2 function is bypassed in sleep mode 1: Freefall/Motion2 function interrupt can wake up system Interrupt polarity active high, or active low. Default value 0. 0: active low; 1: active high Push-pull/Open Drain selection on interrupt pad. Default value 0. 0: push-pull; 1: open drain WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT_1 WAKE_FF_MT_2 IPOL PP_OD IPOL bit selects the polarity of the interrupt signal. When IPOL is ‘0’ any interrupt event will signalled with a logical 0. PP_OD bit configures the interrupt pin to Push-Pull or in Open Drain mode. The open drain configuration can be used for connecting multiple interrupt signals on the same interrupt line. 0x3C: CTRL_REG5 Register (Read/Write) 0x3C CTRL_REG5 Register (Read/Write) Bit 7 INT_EN_ASLP Bit 6 INT_EN_FIFO Bit 5 INT_EN_TRANS Bit 4 INT_EN_LNDPRT Bit 3 INT_EN_PULSE Bit 2 INT_EN_FF_MT_1 Bit 1 INT_EN_FF_MT_2 Bit 0 INT_EN_DRDY Table 59. interrupt Enable Register Description Interrupt Enable INT_EN_ASLP INT_EN_FIFO INT_EN_TRANS Description Interrupt Enable. Default value: 0 0: Auto-Sleep/Wake interrupt disabled; 1: Auto-Sleep/Wake interrupt enabled. Interrupt Enable. Default value: 0 0: FIFO interrupt disabled; 1: FIFO interrupt enabled. Interrupt Enable. Default value: 0 0: Transient interrupt disabled; 1: Transient interrupt enabled. Interrupt Enable. Default value: 0 0: Orientation (Landscape/Portrait) interrupt disabled. 1: Orientation (Landscape/Portrait) interrupt enabled. Interrupt Enable. Default value: 0 0: Pulse Detection interrupt disabled; 1: Pulse Detection interrupt enabled Interrupt Enable. Default value: 0 0: Freefall/Motion1 interrupt disabled; 1: Freefall/Motion1 interrupt enabled Interrupt Enable. Default value: 0 0: Freefall/Motion2 interrupt disabled; 1: Freefall/Motion2 interrupt enabled Interrupt Enable. Default value: 0 0: Data Ready interrupt disabled; 1: Data Ready interrupt enabled INT_EN_LNDPRT INT_EN_PULSE INT_EN_FF_MT_1 INT_EN_FF_MT_2 INT_EN_DRDY MMA8450Q 41 Sensors Freescale Semiconductor The corresponding functional block interrupt enable bit allows the functional block to route its event detection flags to the system’s interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin. 0x3C: CTRL_REG5 Interrupt Configuration Register 0x3C CTRL_REG5 Register (Read/Write) Bit 7 INT_CFG_ASLP Bit 6 INT_CFG_FIFO Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT_1INT_CFG_FF_MT_2 INT_CFG_DRDY Table 60. Interrupt Configuration Register Description Interrupt Configuration INT_CFG_ASLP INT_CFG_FIFO INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT_1 INT_CFG_FF_MT_2 INT_CFG_DRDY Description INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin The system’s interrupt controller shown in Figure 10 uses the corresponding bit field in the CTRL_REG5 register to determine the routing table for the INT1 and INT2 interrupt pins. If the bit value is logic ‘0’ the functional block’s interrupt is routed to INT2, and if the bit value is logic ‘1’ then the interrupt is routed to INT1. One or more functions can assert an interrupt pin; therefore a host application responding to an interrupt should read the INT_SOURCE (0x15) register to determine the appropriate sources of the interrupt. 6.8 User Offset Correction Registers For more information on how to calibrate the 0g Offset refer to AN3916 Offset Calibration Using the MMA8450Q. The 2’s complement offset correction registers values are used to realign the zero g position of the X, Y, and Z-axis after device board mount. The resolution of the offset registers is 3.906 mg per LSB. The 2’s complement 8-bit value would result in an offset compensation range ±0.5g. 0x3D: OFF_X Offset Correction X Register 0x3D OFF_X Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 61. OFF_X Description D7-D0 X -axis offset trim LSB value. Default value: 0000_0000. 0x3E: OFF_Y Offset Correction Y Register 0x3E OFF_Y Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 62. OFF_Y Description D7-D0 Y-axis offset trim LSB value. Default value: 0000_0000. 0x3F: OFF_Z Offset Correction Z Register 0x3F OFF_Z Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 63. OFF_Z Description D7-D0 Z-axis offset trim LSB value. Default value: 0000_0000. MMA8450Q Sensors Freescale Semiconductor 42 Appendix A Table 64. MMA8450Q Register Map Reg 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 Name STATUS OUT_X_MSB OUT_Y_MSB OUT_Z_MSB STATUS OUT_X_LSB OUT_X_MSB OUT_Y_LSB OUT_Y_MSB OUT_Z_LSB OUT_Z_MSB STATUS OUT_X_DELTA OUT_Y_DELTA OUT_Z_DELTA WHO_AM_I F_STATUS F_8DATA F_12DATA F_SETUP SYSMOD INT_SOURCE XYZ_DATA_CFG HP_FILTER_CUTOFF PL_STATUS PL_PRE_STATUS PL_CFG PL_COUNT PL_BF_ZCOMP PL_P_L_THS_REG1 PL_P_L_THS_REG2 PL_P_L_THS_REG3 PL_L_P_THS_REG1 PL_L_P_THS_REG2 PL_L_P_THS_REG3 FF_MT_CFG_1 FF_MT_SRC_1 FF_MT_THS_1 FF_MT_COUNT_1 FF_MT_CFG_2 FF_MT_SRC_2 Definition Data Status R 8-bit X Data R 8-bit Y Data R 8-bit Z Data R Data Status R 12-bit X Data R 12-bit X Data R 12-bit Y Data R 12-bit Y Data R 12-bit Z Data R 12-bit Z Data R Data Status R 8-bit Transient X Data R 8-bit Transient Y Data R 8-bit Transient Z Data R ID Register R FIFO Status R 8-bit FIFO Data R 12-bit FIFO Data R FIFO Setup R/W System Mode R Interrupt Status R Data Config. R/W HP Filter Setting R/W PL Status R Previous PL Status R PL Configuration R/W PL Debounce R/W PL Back/Front and Z Compensation R/W Portrait-to-Landscape Threshold Setting 1 R/W Portrait-to-Landscape Threshold Setting 2 R/W Portrait-to-Landscape Threshold Setting 3 R/W Landscape-to-Portrait Threshold Setting 1 R/W Landscape-to-Portrait Threshold Setting21 R/W Landscape-to-Portrait Threshold Setting 3 R/W FF/Motion Config. 1 R/W FF/Motion Source 1 R FF/Motion Threshold 1 R/W FF/Motion Debounce 1 R/W FF/Motion Config. 2 R/W FF/Motion Source 2 R Bit 7 ZYXOW XD11 YD11 ZD11 ZYXOW 0 XD11 0 YD11 0 ZD11 ZYXOW XD7 YD7 ZD7 — F_OVF XD11 0 F_MODE1 PERR SRC_ASLP FDE 0 NEWLP DBCNTM DBNCE[7] BKFR[1] P_L_THS[7] P_L_THS[7] P_L_THS[7] L_P_THS[7] L_P_THS[7] L_P_THS[7] ELE — DBCNTM D7 ELE — Bit 6 ZOW XD10 YD10 ZD10 ZOW 0 XD10 0 YD10 0 ZD10 ZOW XD6 YD6 ZD6 — F_WMRK_FLAG XD10 0 F_MODE0 FGERR SRC_FIFO 0 0 LO LO PL_EN DBNCE[6] BKFR[0] P_L_THS[6] P_L_THS[6] P_L_THS[6] L_P_THS[6] L_P_THS[6] L_P_THS[6] OAE EA THS6 D6 OAE EA Bit 5 YOW XD9 YD9 ZD9 YOW 0 XD9 0 YD9 0 ZD9 YOW XD5 YD5 ZD5 — F_CNT5 XD9 0 F_WMRK5 0 SRC_TRANS 0 0 DBNCE[5] P_L_THS[5] P_L_THS[5] P_L_THS[5] L_P_THS[5] L_P_THS[5] L_P_THS[5] ZHEFE ZHE THS5 D5 ZHEFE ZHE Bit 4 XOW XD8 YD8 ZD8 XOW 0 XD8 0 YD8 0 ZD8 XOW XD4 YD4 ZD4 — F_CNT4 XD8 0 F_WMRK4 0 SRC_LNDPRT 0 0 LAPO[2] LAPO[2] DBNCE[4] P_L_THS[4] P_L_THS[4] P_L_THS[4] L_P_THS[4] L_P_THS[4] L_P_THS[4] ZLEFE ZLE THS4 D4 ZLEFE ZLE Bit 3 ZYXDR XD7 YD7 ZD7 ZYXDR XD3 XD7 YD3 YD7 ZD3 ZD7 ZYXDR XD3 YD3 ZD3 — F_CNT3 XD7 XD3 F_WMRK3 0 SRC_PULSE — 0 LAPO[1] LAPO[1] DBNCE[3] P_L_THS[3] P_L_THS[3] P_L_THS[3] L_P_THS[3] L_P_THS[3] L_P_THS[3] YHEFE YHE THS3 D3 YHEFE YHE Bit 2 ZDR XD6 YD6 ZD6 ZDR XD2 XD6 YD2 YD6 ZD2 ZD6 ZDR XD2 YD2 ZD2 — F_CNT2 XD6 XD2 F_WMRK2 0 SRC_FF_MT_1 ZDEFE 0 LAPO[0] LAPO[0] GOFF[2] DBNCE [2] ZLOCK[2] P_L_THS[2] P_L_THS[2] P_L_THS[2] L_P_THS[2] L_P_THS[2] L_P_THS[2] YLEFE YLE THS2 D2 YLEFE YLE Bit 1 YDR XD5 YD5 ZD5 YDR XD1 XD5 YD1 YD5 ZD1 ZD5 YDR XD1 YD1 ZD1 — F_CNT1 XD5 XD1 F_WMRK1 SYSMOD1 SRC_FF_MT_2 YDEFE SEL1 BAFRO[1] BAFRO[1] GOFF[1] DBNCE [1] ZLOCK[1] P_L_THS[1] P_L_THS[1] P_L_THS[1] L_P_THS[1] L_P_THS[1] L_P_THS[1] XHEFE XHE THS1 D1 XHEFE XHE Bit 0 XDR XD4 YD4 ZD4 XDR XD0 XD4 YD0 YD4 ZD0 ZD4 XDR XD0 YD0 ZD0 — F_CNT0 XD4 XD0 F_WMRK0 SYSMOD0 SRC_DRDY XDEFE SEL0 BAFRO[0] BAFRO[0] GOFF[0] DBNCE [0] ZLOCK[0] P_L_THS[0] P_L_THS[0] P_L_THS[0] L_P_THS[0] L_P_THS[0] L_P_THS[0] XLEFE XLE THS0 D0 XLEFE XLE MMA8450Q 43 Sensors Freescale Semiconductor Table 64. MMA8450Q Register Map 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F FF_MT_THS_2 FF_MT_COUNT_2 TRANSIENT_CFG TRANSIENT_SRC TRANSIENT_THS TRANSIENT_COUNT PULSE_CFG PULSE_SRC PULSE_THSX PULSE_THSY PULSE_THSZ PULSE_TMLT PULSE_LTCY PULSE_WIND ASLP_COUNT CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 OFF_X OFF_Y OFF_Z FF/Motion Threshold 2 R/W FF/Motion Debounce 2 R/W Transient Config. R/W Transient Source R Transient Threshold R/W Transient Debounce R/W Pulse Config. R/W Pulse Source R Pulse X Threshold R/W Pulse Y Threshold R/W Pulse Z Threshold R/W Pulse First Timer R/W Pulse Latency R/W Pulse 2nd Window R/W Auto-Sleep Counter R/W Control Reg 1 R/W Control Reg 2 R/W Control Reg3 R/W (Wake Interrupts from Sleep) Control Reg4 R/W (Interrupt Enable Map) Control reg5 R/W (Interrupt Configuration) X 8-bit offset Y 8-bit offset Z 8-bit offset DBCNTM D7 — — DBCNTM D7 DPA — 0 0 0 Tmlt7 Ltcy7 Wind7 D7 ASLP_RATE1 ST FIFO_GATE INT_EN_ASLP THS6 D6 — — THS6 D6 ELE EA 0 0 0 Tmlt6 Ltcy6 Wind6 D6 ASLP_RATE0 RST WAKE_TRANS INT_EN_FIFO THS5 D5 — — THS5 D5 ZDPEFE ZDPE 0 0 0 Tmlt5 Ltcy5 Wind5 D5 0 0 WAKE_LNDPRT INT_EN_TRANS THS4 D4 — — THS4 D4 ZSPEFE ZSPE THSX4 THSY4 THSZ4 Tmlt4 Ltcy4 Wind4 D4 DR2 0 WAKE_PULSE INT_EN_LNDPRT THS3 D3 ELE EA THS3 D3 YDPEFE YDPE THSX3 THSY3 THSZ3 Tmlt3 Ltcy3 Wind3 D3 DR1 0 WAKE_FF_MT_1 INT_EN_PULSE INT_CFG_PULSE D3 D3 D3 THS2 D2 ZTEFE ZTRANSE THS2 D2 YSPEFE YSPE THSX2 THSY2 THSZ2 Tmlt2 Ltcy2 Wind2 D2 DR0 0 WAKE_FF_MT_2 INT_EN_FF_MT_1 THS1 D1 YTEFE YTRANSE THS1 D1 XDPEFE XDPE THSX1 THSY1 THSZ1 Tmlt1 Ltcy1 Wind1 D1 FS1 SLPE IPOL INT_EN_FF_MT_2 THS0 D0 XTEFE XTRANSE THS0 D0 XSPEFE XSPE THSX0 THSY0 THSZ0 Tmlt0 Ltcy0 Wind0 D0 FS0 MODS PP_OD INT_EN_DRDY INT_CFG_ASLP INT_CFG_FIFO INT_CFG_TRANS INT_CFG_LNDPRT D7 D7 D7 D6 D6 D6 D5 D5 D5 D4 D4 D4 INT_CFG_FF_MT_1 INT_CFG_FF_MT_2 INT_CFG_DRDY D2 D2 D2 D1 D1 D1 D0 D0 D0 MMA8450Q Sensors Freescale Semiconductor 44 Table 65. Accelerometer Output Data 12-bit Data 0111 1111 1111 0111 1111 1110 — 0000 0000 0001 0000 0000 0000 1111 1111 1111 — 1000 0000 0001 1000 0000 0000 8- bit Data 0111 1111 0111 1110 — 0000 0001 0000 0000 1111 1111 — 1000 0001 1000 0000 Range ±2g 1.999g 1.998g — 0.001g 0.000g -0.001g — -1.999g -2.000g Range ±2g 1.984g 1.968g — +0.016g 0.000g -0.016g — -1.984g -2.000g Range ±4g +3.998g +3.996g — +0.002g 0.000g -0.002g — -3.998g -4.000g Range ±4g +3.968g +3.936g — +0.032g 0.000g -0.032g — -3.968g -4.000g Range ±8g +7.996g +7.992g — +0.004g 0.000g -0.004g — -7.996g -8.000g Range ±8g +7.936g +7.872g — +0.064g 0.000g -0.064g — -7.936g -8.000g MMA8450Q 45 Sensors Freescale Semiconductor Appendix B Figure 13. Distribution of Pre Board Mounted Devices Tested in Sockets (1 count = 3.9 mg) MMA8450Q Sensors Freescale Semiconductor 46 Figure 14. Distribution of Post Board Mounted Devices (1 count = 3.9 mg) MMA8450Q 47 Sensors Freescale Semiconductor Figure 15. 8g X-axis TCS MMA8450Q Sensors Freescale Semiconductor 48 Figure 16. 8g Y-axis TCS MMA8450Q 49 Sensors Freescale Semiconductor Figure 17. 8g Z-axis TCS MMA8450Q Sensors Freescale Semiconductor 50 Figure 18. 8g X-axis TCO (mg/°C) MMA8450Q 51 Sensors Freescale Semiconductor Figure 19. 8g Y-axis TCO (mg/°C) MMA8450Q Sensors Freescale Semiconductor 52 Figure 20. 8g Z-axis TCO (mg/°C) MMA8450Q 53 Sensors Freescale Semiconductor PACKAGE DIMENSIONS CASE 2077-01 ISSUE O 16-LEAD QFN MMA8450Q Sensors Freescale Semiconductor 54 PACKAGE DIMENSIONS CASE 2077-01 ISSUE O 16-LEAD Q MMA8450Q 55 Sensors Freescale Semiconductor PACKAGE DIMENSIONS CASE 2077-01 ISSUE O 16-LEAD Q MMA8450Q Sensors Freescale Semiconductor 56 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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