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Advance Information
MMM5063/D Rev. 0.2, 09/2003 Tri-Band GSM GPRS 3.5 V Power Amplifier
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MMM5063
(Scale 1:1)
Package Information Plastic Package Case 1383 (Module, 7x7 mm)
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Ordering Information
Device MMM5063 Device Marking See Figure 25 Package Module
The MMM5063 is a tri-band single supply RF Power Amplifier for GSM900/DCS1800/ PCS1900 GPRS handheld radios. This fully integrated Power Amplifier uses a patented concept to realize the 50 Ω matching on-chip through integration of passives on the GaAs die. This allows module functionality in a very small 7 x 7 mm package and achieves best-inclass Power Amplifier performance and multi-band capability. Applications: • • • • • • Tri-Band GSM900 DCS1800 and PCS1900 Guaranteed for 25% Duty Cycle Single Supply Enhancement Mode GaAs MESFET Technology Internal 50 Ω Input/Output Matching High Gain Three Stage Amplifier Design Typical 3.5 V Characteristics: Pout = 35.2 dBm, PAE = 53% for GSM Pout = 33.8 dBm, PAE = 44% for DCS Pout = 34 dBm, PAE = 43% for PCS • • Optimized and Guaranteed for Open-Loop Power Control Applications Small 7 x 7 mm Package
Features:
This document contains information on a pre-production product. Specifications and Pre-production information herein are subject to change without notice. © Motorola, Inc., 2003. All rights reserved.
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Electrical Specifications
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VDCS1 VDCS2 VDCS3 Vreg Vapc
DCS/PCS In
DCS/PCS AMP
DCS/PCS Out
GSM In
GSM AMP
GSM Out
VGSM1
VGSM2
VGSM3
VBS
VdB
This device contains 26 active transistors.
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Figure 1. Simplified Block Diagram
1 Electrical Specifications
Table 1. Maximum Ratings
Rating Supply Voltage Symbol VGSM1,2,3, VDCS1,2,3, VdB GSM IN, DCS/PCS IN Value 6.0 Unit V
RF Input Power RF Output Power GSM Section DCS/PCS Section Operating Case Temperature Range Storage Temperature Range Die Temperature
11
dBm dBm
GSM OUT DCS/PCS OUT TC Tstg TJ
38 36 -35 to 100 -55 to 150 150 °C °C °C
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. 2. ESD (electrostatic discharge) immunity meets Human Body Model (HBM) ≤150 V and Machine Model (MM) ≤50 V. Additional ESD data available upon request. 3. Meets Moisture Sensitivity Level (MSL) 3. See Figure 25 on page 17 for additional details.
2
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Table 2. Recommended Operating Conditions
Characteristic Drain Supply Voltage Bias Supply Voltage Regulated Voltage Power Control Voltage Band Select Input Power GSM Symbol VGSM1,2,3, VDCS1,2,3 VdB VREG Vapc VBS GSM IN DCS/PCS IN Min 2.7 2.7 2.5 0 0 -1.0 2.0 Typ 2.8 1.8 2.8 Max 5.5 5.5 3.0 2.8 3.0 8.0 10 Unit V V V V V dBm dBm
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Input Power DCS/PCS
Table 3. Control Requirements
Characteristic Current for Vreg @ 2.8 V Band Select Low Band Enable Voltage High Band Enable Voltage Current for VBS = 2.8 V Symbol Ireg VBS 2.2 0 IBS 2.8 0.76 0.3 1.0 mA Min Typ 7.7 Max 10 Unit mA V
Table 4. Electrical Characteristics
(Peak measurement at 25% duty cycle, 4.6 ms period, TA = 25°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
GSM 900 Section(Pin = -1.0 dBm, VGSM1,2,3 = 3.5 V pulsed, VdB = 3.5 V, VREG = VBS= 2.8 V, Vramp = 1.8 V pulsed) Frequency Range Output Power Power Added Efficiency Output Power @ Low Voltage (VGSM1,2,3 = 2.8 V pulsed, VdB = 2.8 V) Power Added Efficiency @ Low Voltage (VGSM1,2,3 = 2.8 V pulsed, VdB = 2.8 V) Harmonic Output 2fo ≥3fo BW Pout PAE Pout 880 34.2 48 32.5 35.2 53 33.4 915 MHz dBm % dBm
PAE
48
54
-
%
dBc -37 -60 -33 -45
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Electrical Specifications
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Table 4. Electrical Characteristics (Continued)
(Peak measurement at 25% duty cycle, 4.6 ms period, TA = 25°C, unless otherwise noted.)
Characteristic Second Harmonic Leakage at DCS Output (Crosstalk isolation) Input Return Loss Output Power Isolation (Vramp = 0 V, VGSM1,2,3 = 0 V) Noise Power in Rx Band @ Pin = -1.0 dBm (100 kHz measurement bandwidth) @ fo + 10 MHz (fo = 915 MHz) @ fo + 20 MHz (fo = 915 MHz)
Symbol
Min -
Typ -28 10 -45
Max -15 -40
Unit dBm dB dBm dBm
|S11| Poff NP
-
NP -
-80 -81
dBm
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Noise Power in Rx Band @ Pin = 6.0 dBm (100 kHz measurement bandwidth) @ fo + 10 MHz (fo = 915 MHz) @ fo + 20 MHz (fo = 915 MHz) Stability-Spurious Output (Pout = 5.0 to 35 dBm, Load VSWR = 6:1 all Phase Angles, Adjust Vramp for specified power) Load Mismatch Stress (Pout = 5.0 to 35 dBm, Load VSWR = 10:1 all phase angles, 5 seconds, Adjust Vramp for specified power)
-84 -86
-77 -81
Pspur
-
-
-60
dBc
No Degradation in Output Power Before and After Test
DCS Section(Pin = 2.0 dBm, VDCS1,2,3 = 3.5 V pulsed, VdB = 3.5 V, VREG = 2.8 V, Vramp = 1.8 V pulsed, VBS = 0 V) Frequency Range Output Power Power Added Efficiency Output Power @ Low Voltage (VDCS1,2,3 = 2.8 V pulsed, VdB= 2.8 V) Power Added Efficiency @ Low Voltage (VDCS1,2,3 = 2.8 V pulsed, VdB= 2.8 V) Harmonic Output 2fo ≥3fo Input Return Loss Output Power Isolation (Vramp = 0 V, VDCS1,2,3 = 0 V) Noise Power in Rx Band @ Pin = 2.0 dBm @ fo + 20 MHz (fo = 1785 MHz) (100 kHz measurement bandwidth) Stability-Spurious Output (Pout = 0 to 33 dBm, Load VSWR = 6:1 all Phase Angles, Adjust Vramp for specified power) |S11| Poff BW Pout PAE Pout 1710 32.5 38 31 33.8 44 32 1785 MHz dBm % dBm
PAE
38
45
-
% dBc
-
-65 -50 9.0 -40
-45 -45 -35 dB dBm
NP
-
-78
-75
dBm
Pspur
-
-
-60
dBc
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Table 4. Electrical Characteristics (Continued)
(Peak measurement at 25% duty cycle, 4.6 ms period, TA = 25°C, unless otherwise noted.)
Characteristic Load Mismatch Stress (Pout = 0 to 33 dBm, Load VSWR = 10:1 all phase angles, 5 seconds, Adjust Vramp for specified power)
Symbol
Min
Typ
Max
Unit
No Degradation in Output Power Before and After Test
PCS Section(Pin = 3.0 dBm, VDCS1,2,3 = 3.5 V pulsed, VdB = 3.5 V, VREG = 2.8 V, Vramp = 1.8 V pulsed, VBS = 0 V) Frequency Range Output Power Power Added Efficiency BW Pout PAE Pout 1850 32.5 37 31 34 43 32 1910 MHz dBm % dBm
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Output Power @ Low Voltage (VDCS1,2,3 = 2.8 V pulsed, VdB= 2.8 V) Power Added Efficiency @ Low Voltage (VDCS1,2,3 = 2.8 V pulsed, VdB= 2.8 V) Harmonic Output 2fo ≥3fo Input Return Loss Output Power Isolation (Vramp = 0 V, VDCS1,2,3 = 0 V) Noise Power in Rx Band @ Pin = 3.0 dBm @ fo + 20 MHz (fo = 1910 MHz) (100 kHz measurement bandwidth) Stability-Spurious Output (Pout = 0 to 33 dBm, Load VSWR = 6:1 all Phase Angles, Adjust Vramp for specified power) Load Mismatch Stress (Pout = 0 to 33 dBm, Load VSWR = 10:1 all phase angles, 5 seconds, Adjust Vramp for specified power)
PAE
37
43
-
% dBc
|S11| Poff -
-65 -50 5.0 -35
-45 -45 -32 dB dBm
NP
-
-78
-75
dBm
Pspur
-
-
-60
dBc
No Degradation in Output Power Before and After Test
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Typical Performance Characteristics
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2 Typical Performance Characteristics
2.1 GSM
38
60
PAE, POWER ADDED EFFICIENCY (%)
Pout, OUTPUT POWER (dBm)
37 36 35 34 33 32 880 TA = -35°C 25°C 85°C VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V
TA = -35°C 55 25°C 50 85°C 45 VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V 40 880 887 894 901 908 915
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887
894
901
908
915
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 2. Output Power versus Frequency
-20
H2, SECOND HARMONIC (dBc)
Figure 3. Power Added Efficiency versus Frequency
38
-22
CROSSTALK (dBm)
VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V
37 36 35 34 33 32 880
TA = 85°C 25°C VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V
-24 -26 -28 -30 -32 -34 880 25°C 887 894 901 TA = 85°C
-35°C
-35°C
908
915
887
894
901
908
915
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 4. Crosstalk versus Frequency
Figure 5. Second Harmonic Output versus Frequency
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70
H3, THIRD HARMONIC (dBc)
69 68
TA = -35°C 25°C
67 66 65 64 63 880
VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V
85°C 887 894 901 908 915
f, FREQUENCY (MHz)
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Figure 6. Third Harmonic Output versus Frequency
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2.2 DCS
34.4
Pout, OUTPUT POWER (dBm)
48 TA = -35°C
PAE, POWER ADDED EFFICIENCY (%)
34.2 34 33.8 33.6 33.4 33.2 33 1710
47 46 45 25°C 44 43 42 41 40 1710 85°C VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V TA = -35°C
25°C VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V 85°C 1735 1760 1785
1735
1760
1785
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 7. Output Power versus Frequency
72
H2, SECOND HARMONIC (dBc)
H3, THIRD HARMONIC (dBc)
Figure 8. Power Added Efficiency versus Frequency
60 VGSM1,2,3 = 3.5 V 59 58 57 56 55 54 1710 VdB = 3.5 V Vapc = 2.2 V TA = -35°C 25°C
71 70 69 68 67 66 65 1710 TA = 85°C 25°C VGSM1,2,3 = 3.5 V VdB = 3.5 V 35°C 1760 Vapc = 2.2 V
85°C
1735
1785
1735
1760
1785
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 9. Second Harmonic Output versus Frequency
Figure 10. Third Harmonic Output versus Frequency
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Typical Performance Characteristics
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PAE, POWER ADDED EFFICIENCY (%)
2.3 PCS
34.8 34.6
Pout, OUTPUT POWER (dBm)
TA = -35°C
TA = -35°C 44 25°C 42 40 38 36 1850
34.4 34.2 34 33.8 33.6 33.4 33.2 33 1850 1865 1880 f, FREQUENCY (MHz) 1895 1910 85°C 25°C VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V
85°C VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V 1865 1880 f, FREQUENCY (MHz) 1895 1910
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Figure 11. Output Power versus Frequency
70 TA = 85°C
H2, SECOND HARMONIC (dBc) H3, THIRD HARMONIC (dBc)
Figure 12. Power Added Efficiency versus Frequency
59 58 57 56 55 54 53 52 51 50 1910 49 1850 VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V 1865 1880 f, FREQUENCY (MHz) 1895 1910 85°C TA = -35°C 25°C
69 68 67 66 65 64 1850 25°C -35°C VGSM1,2,3 = 3.5 V VdB = 3.5 V Vapc = 2.2 V 1865 1880 f, FREQUENCY (MHz) 1895
Figure 13. Second Harmonic Output versus Frequency
Figure 14. Third Harmonic Output versus Frequency
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3 Contact Descriptions and Connections
Pin Symbol
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Table 5. Contact Function Description
Description
1 2 3 4 5 6
Vreg VdB DCS/PCS Out VDCS3 VDCS2 VDCS1 Vapc DCS/PCS In GSM In VGSM1 VGSM2 VGSM3 GSM Out VBS
Regulated dc voltage for bias circuit DC supply voltage for active bias circuits connected to the battery DCS/PCS RF output DCS/PCS DC supply voltage for 3rd stage DCS/PCS DC supply voltage for 2nd stage DCS/PCS DC supply voltage for 1st stage Power control for both line-ups (Vapc = 0 V, Pout = Poff, Vapc = 1.8 V, Pout = Pmax) DCS/PCS RF input GSM RF input GSM DC supply voltage for 1st stage GSM DC supply voltage for 2nd stage GSM DC supply voltage for 3rd stage GSM RF output Band selection between GSM and DCS/PCS
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8 9 10 11 12 13 14
Pin 1 Pad Corner Vreg VdB DCS/PCS Out
VBS
VDCS3
VDCS2 GSM Out (0.60) Ground Plane VDCS1 Vramp DCS/PCS In
VGSM3
VGSM2 (0.95)
VGSM1
GSM In
NOTE: For optimum performance VGSM1 and VGSM2, as well as VDCS1 and VDCS2, must be strapped together on the application demobard.
Figure 15. Contact Connections (Bottom View)
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Application Information
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4 Application Information
4.1 Power Control Considerations
The MMM5063 is designed for open loop (drain control) applications. A PMOS FET is used to switch the MMM5063 drain and vary the supply voltage from 0 to the battery voltage setting (Vbat). The simplified concept schematic (see Figure 22) describes the application circuit used to control the device through the drain voltage. A drain control provides a linear transfer function which is repeatable versus control voltage (see Figure 16).
4.0 3.5
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Pout, OUTPUT POWER (W)
3.0 2.5 2.0 1.5 1.0 0.5 0 0 2.0 4.0 6.0 8.0 10 12 14 VD2, DRAIN VOLTAGE SQUARED (V2)
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Figure 16. Output Power versus Drain Voltage
4.2 GSM Second Harmonic (H2) Trap Circuitry
When transmitting in GSM saturated mode, the second harmonic is naturally present at the RF output of the PA and reaches the antenna after additional filtering in the front-end. ETSI specifies that harmonic level cannot exceed -36 dBm. In order to improve H2 rejection in low Band (GSM), an H2 trap has been developed. The topology is based on a Low Pass π Cell Filter (see Figure 17) where the first shunt capacitor is actually part of the PA output match.
GSM Out 8.2 pF 0402 Murata 460 pH 7.5 nH Coilcraft 0603 Switchplexer 2.2 pF 0402 Murata 460 pH
Figure 17. Low Pass Filter
This circuit reduces H2 level by 7 to 8 dB with low in-band insertion losses (mainly due to the series inductor). Moreover, this structure can be used to match Power amplifier module output to the switchplexer.
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4.3 Application Schematics and Printed Circuit Boards
Battery PMOS Vramp CE [Note 1]
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Vreg
VAPC MMM5063
Vd
VdB GSM Out DCS/PCS Out
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VBS GSM In DCS/PCS In
[Note 2]
NOTES: 1. Op/Amp is either external (with an enable pin CE) or in an ASIC. 2. The MMM5063 requires 4 to 6 RF/LF decoupling capacitors (not shown).
Figure 18. Open Loop Control Application Schematic
Figure 18 represents the complete Power Amplifier implementation including the MMM5063 Amplifier Module and the Control Circuitry. This functionality is realized with two separate printed circuit boards; the PA Evaluation Circuit with schematic shown in Figure 21 and PCB Layout shown in Figure 23, and the Power Amplifier Control Loop with schematic shown in Figure 22 and PCB Layout shown in Figure 24. The PA Evaluation Circuit is straightfoward and, due to the MMM5063’s high level of integration, requires only a few passive components around the package. These components are mainly de-coupling capacitors. The Power Amplifier Control Loop is based on an operational amplifier driving a PMOS transistor. The PMOS device functions as a linear drain voltage regulator controlled by Vrampwith a typical gain of 2 which is set through the resistive divider R4 and R5 as shown in Figure 22. To control output power through the drain, Vapc must be indexed to the drain voltage to prevent the PA Section from drawing excessive current especially at low output power. Nevertheless, Vapc should stay above 0.8 V to provide sufficient gain for the line-up. Figure 19 describes the application circuit used to control Vapc through the drain voltage. It uses Vreg to pre-position Vapc at 0.9 V and add a voltage which is dependent on the drain Voltage.
Vreg = 2.8 V 0 V < Vdrain < VBAT
R8 = 1.0 kΩ
Vapc
R7 = 560 Ω
RVAPC = 700 Ω
Internal to the die
Figure 19.
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Application Information
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2.4 2.2 2.0 1.8
Vapc (V)
1.6 1.4 1.2 1.0
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0.8 0 0.5 1.0 1.5 2.0 Vdrain (V) 2.5 3.0 3.5 4.0
Figure 20. Vapc versus Vdrain
It is possible that the Power Control DAC output voltage can be in the 200 mV to 2.0 V range. This raises
a concern for the MMM5063 ramp control voltage (Vramp) which must start at 0 V to get enough output power dynamic range. To overcome this limitation, a resistor (R6 in Figure 22) is used to set an additional offset (200 mV with R6 = 39 kΩ). This residual voltage is then subtracted the DAC output voltage through the differential Operational Amplifier.
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C9 10 nF
C1 N/C C6 N/C C2 330 pF
C11 1.0 nF
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C13 N/C
C15 10 nF DCS/PCS In DCS/ PCS In Vapc VDCS2 VDCS1 VDCS3 C8 22 pF
GSM I n DCS/PCS Out C4 N/C VGSM1 GSM Out VGSM2 C3 N/C GSM In VGSM3 C18 100 pF VdB Vreg VBS C17 3.9 pF
C 7 22 pF
DCS/PCS Out
C14 1 0 nF
C16 6.8 pF
C5 220 pF
C 12 2 2 pF
C10 47 pF NOTE: N/C = No Connect, Do not mount. GSM Out
Figure 21. PA Evaluation Circuit
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Application Information
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C6 47 nF
C5 10 nF C1 68 µF
NOTE: N/C = No Connect, Do not mount.
R8 1.0 k
R10 N/C R7 560 Ω
R3 12 k
C3 15 pF
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R2 150 Ω C2 330 pF C18 10 nF R5 5.6 k R11 150 Ω C12 10 nF C4 330 pF R6 39 k R4 5.6 k
Figure 22. Power Amplifier Control Loop
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Figure 23. PA Evaluation Circuit PCB Table 6. PA Evaluation Circuit PCB Bill of Materials
Reference C1, C3, C4, C6, C13 C2 C5 C7, C8, C12 C9, C14, C15 C10 C11 C16 C17 C18 J2, J3, J4, J5 Value N/C - Do not mount 330 pF 220 pF 22 pF 10 nF 47 pF 1.0 nF 6.8 pF 3.9 pF 100 nF 50 Ω GRM36COG330J50 GRM36X7R221K50 GRM36COG220J50 GRM36X7R103K25 GRM36COG470J50 GRM36X7R102K25 GRM36COG6R8J50 GRM36COG3R9J50 GRM36X7R104K25 142-0711-821 Murata Murata Murata Murata Murata Murata Murata Murata Murata Johnson Part Number Manufacturer
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Application Information
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Figure 24. Power Amplifier Control Loop PCB Table 7. Power Amplifier Control Loop PCB Bill of Materials
Reference C1 C2 C3 C4 C5, C12, C18 C6 J1, J2, J3 Q1 Q2 R1, R8 R2 R3 R4, R5 R6, R10 R7 R11 U1 68 µF 330 pF 15 pF 330 pF 10 nF 47 nF DC connector Power MOSFET N/C - Do not mount 1.0 k 150 Ω 12 k 5.6 k N/C - Do not mount 560 Ω 100 Ω CMOS Op Amp CRG0402 5% 560 O CRG0402 5% 100 O AD8591 NEOHM NEOHM Analog Devices CRG0402 5% 1 kO CRG0402 5% 150 O CRG0402 5% 12 kO CRG0402 5% 5.6 kO NEOHM NEOHM NEOHM NEOHM NTHS5445T ON Semiconductor Value Part Number 293D685X9020C GRM36COG330J50 GRM36COG150J50 GRM36x7R331K50 GRM36X7R103K25 GRM36X7R473K10 Manufacturer Sprague Murata Murata Murata Murata Murata
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5 Packaging Information
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Shipping, Packaging and Marking Information Tape Width: 16.0 mm Tape Pitch 12 mm (part to part) Reel Diameter: 330 mm (13 in) Component Orientation: Parts are to be orientated with pin 1 side closest to the tape's round sprocket holes on the tape's trailing edge. Dry Pack: This device meets Moisture Sensitiviy Level (MSL) 3. Parts will be shipped in Dry Pack. Parts must be stored at 30°C and 60% relative humidity with time out of dry pack not to exceed 168 hours. In the event that parts are not handled or stored within these limits, one of the following dry out procedures must be completed prior to reflow: 1) 40°C Dry Out: Bake devices at 40°C ≤ TA ≤ 45°C, 5% Relative Humidity for at least 192 hours.
MMM5063 LLLLLL WW AWLYYWW
Marking (Top View)
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2) Room Temperature Dry Out: Store devices at less than 20% Relative Humidity for at least 500 hours. Marking: 1st line: 3rd Line: 4th Line: Motorola Logo Wafer lot number (coded on 6 characters) followed by wafer number (coded on 3 digits) Assy site code (on 1 or 2 characters), followed by Wafer Lot Number (coded on 1 or 2 characters), followed by Year (on 2 digits) and Workweek (on 2 digits). 2nd Line: Partnumber coded on 7 characters
Tape & Reel Orientation (Top View)
Figure 25. Packaging Information
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Packaging Information
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7 A
B
0.1
7
Freescale Semiconductor, Inc...
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
1.01 ± 0.1
0.7 ± 0.05
0.1 A
2.95±0.05
2.45±0.05 0.5±0.05
3.15
2.24
0.7
0.3
2.2
2.55
1±0.05 2.9 0.8±0.05 0.97 3±0.05 0
9X
3.15 2.52 1.77 1.02 0.07
0.5±0.05 SQ 2.37±0.05 2.4 0.5±0.05 2.215 2.4 0.5±0.05
1.03
1.65
0 0.5±0.05
3.15
2.8
2.4
PIN ONE IDENT
1.2±0.05 0.8±0.05
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3.
BOTTOM VIEW
0.1
L
ABC
APPLIES TO ALL PAD LOCATIONS.
Figure 26. Outline Dimensions for 7x7 mm Module (Case 1383-02, Issue A)
18
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Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
NOTES
Freescale Semiconductor, Inc...
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
MOTOROLA
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Freescale Semiconductor, Inc.
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
Freescale Semiconductor, Inc...
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MMM5063/D
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