MPC1751MTB

Freescale Semiconductor Advance Information Document Number: MPC17510 Rev. 3.0, 1/2007 1.2 A 15 V H-Bridge Motor Driver IC The 17510 is a monolithic H-Bridge designed to be used in portable electronic applications such as digital and SLR cameras to control small DC motors. The 17510 can operate efficiently with supply voltages as low as 2.0 V to as high as 15 V. Its low RDS(ON) H-Bridge output MOSFETs (0.45 Ω typical) can provide continuous motor drive currents of 1.2 A and handle peak currents up to 3.8 A. It is easily interfaced to lowcost MCUs via parallel 5.0 V compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. The 17510 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Features • • • • • • • • 2.0 V to 15 V Continuous Operation Output Current 1.2 A (DC), 3.8 A (Peak) 450 mΩ RDS(ON) H-Bridge MOSFETs 5.0 V TTL- / CMOS-Compatible Inputs PWM Frequencies up to 200 kHz Undervoltage Shutdown Cross-Conduction Suppression Pb-Free Packaging Designated by Suffix Code EJ Device MPC17510EJ/R2 MPC17510MTB MPC17510MTBEL 17510 H-BRIDGE MOTOR DRIVER MTB SUFFIX EJ SUFFIX (Pb-FREE) 98ASH70455A 24-LEAD TSSOP ORDERING INFORMATION Temperature Range (TA) Package -30°C to 65°C 24 TSSOPW 5.0 V 15 V 17510 VDD VM C1L GOUT C1H C2L C2H CRES OUT1 EN GIN IN1 IN2 MOTOR MCU OUT2 GND Figure 1. 17510 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM C2H C2L C1H C1L TOUT 14 3 13 11 12 15 CRES Charge Pump 21 VM1 8 VDD VM2 23 Low Voltage Detector 1 5 Level Shifter Predriver H-Bridge OUTA OUTA' IN1 IN2 9 10 Control Logic 17 OUTB' 18 OUTB EN TINB 16 24 6 PGND1 LGND 2 4 7 20 22 NC Figure 2. 17510 Simplified Internal Block Diagram 19 PGND2 17510 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS OUT1 LGND CRES NC OUT1 PGND NC VM IN1 IN2 C1H C1L 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GIN VDD NC VM NC PGND OUT2 OUT2 EN GOUT C2H C2L Figure 3. 17510 Pin Connections Table 1. 17510 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 8. Pin Number 1, 5 2 3 4, 7, 20, 22 17, 18 6, 19 8, 21 9 10 11 12 13 14 15 16 23 24 Pin Name OUT1 LGND CRES NC OUT2 PGND VM IN1 IN2 C1H C1L C2L C2H GOUT EN VDD GIN Formal Name Output 1 Logic Ground Charge Pump Output Capacitor Connection No Connect Output 2 Power Ground Motor Drive Power Supply Input Control 1 Input Control 2 Charge Pump 1H Charge Pump 1L Charge Pump 2L Charge Pump 2H Gate Driver Output Enable Control Logic Supply Gate Driver Input Driver output 1 pins. Logic ground. Charge pump reservoir capacitor pin. No connection to these pins. Driver output 2 pins. Power ground. Motor power supply voltage input pins. Control signal input 1 pin. Control signal input 2 pin. Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). Charge pump bucket capacitor 2 (negative pole). Charge pump bucket capacitor 2 (positive pole). Output gate driver signal to external MOSFET switch. Enable control signal input pin. Control circuit power supply pin. LOW = True control signal for GOUT pin. Definition 17510 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage (EN, IN1, IN2, GIN) Driver Output Current Continuous Peak (2) ESD Voltage (3) (1) Symbol VM VCRES Value - 0.5 – - 16 -0.5 to 13 -0.5 to 16 -0.5 to VDD + 0.5 1.2 3.8 Unit V V V V A VDD VIN IO IOPK V VESD1 VESD2 TSTG TJ TA PD RθJA (5) Human Body Model Machine Model Storage Temperature Operating Junction Temperature Operating Ambient Temperature Power Dissipation (4) ±1900 ± 130 -65 to 150 -30 to 150 -30 to 65 1.0 120 260 °C °C °C W °C/W °C Thermal Resistance Soldering Temperature TSOLDER Notes 1. When supplied externally, connect via 3.0 kΩ resistor. 2. TA = 25°C, 10 ms pulse at 200 ms interval. 3. 4. 5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). TA = 25°C, RθJA = 120°C/W, 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB). Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 17510 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25°C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER Motor Supply Voltage Logic Supply Voltage Capacitor for Charge Pump Standby Power Supply Current (6) Motor Supply Standby Current Logic Supply Standby Current Logic Supply Current (7) Low-Voltage Detection Circuit Detection Voltage (VDD) Detection Voltage (VM) Driver Output ON Resistance (9) VM = 2.0 V, 8.0 V, 15 V GATE DRIVE Gate Drive Voltage (10) No Current Load Gate Drive Ability (Internally Supplied) I CRES = -1.0 mA (8) Symbol Min Typ Max Unit VM VDD C1, C2, C3 I I 2.0 4.0 0.001 – – – 15 5.5 0.1 V V µF µA mA mA V VMSTBY – – – – 0.3 3.3 1.0 1.0 4.0 VDDSTBY I VDD VDDDET VMDET RDS(ON) 1.5 4.0 2.5 5.0 3.5 6.0 Ω – 0.45 0.55 VCRES 12 13 13.5 V VCRESLOAD 10 11.2 – V Gate Drive Output IOUT = -50 µA IIN = 50 µA CONTROL LOGIC Logic Input Voltage (EN, IN1, IN2, GIN) Logic Input Function (4.0 V < VDD < 5.5 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current EN / GIN Pin Notes 6. Excluding pull-up resistor current, including current of gate-drive circuit. 7. fIN = 100 kHz. 8. 9. 10. VIH VIL IIH IIL IIL VDD x 0.7 – – -1.0 - 200 – – – – - 50 – VDD x 0.3 1.0 – – VIN 0 – VGOUTHIGH VGOUTLOW V CRES 0.5 LGND V CRES 0.1 LGND + 0.1 V CRES LGND +0.5 V VDD V V V µA µA µA Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate voltage VCRES is applied from an external source, VCRES = 7.5 V. IO = 1.2 A source + sink. Input logic signal not present. 17510 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25°C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic INPUT (EN, IN1, IN2, GIN) Pulse Input Frequency Input Pulse Rise Time (11) Symbol Min Typ Max Unit fIN tR tF – – – – – – 200 1.0 (12) kHz µs µs Input Pulse Fall Time (13) OUTPUT Propagation Delay Time Turn-ON Time Turn-ON Time Turn-OFF Time GOUT Output Delay Time Turn-ON Time Turn-OFF Time Charge Pump Circuit Oscillator Frequency Rise Time (15) Low-Voltage Detection Time Notes 11. 12. 13. 14. 15. (14) 1.0 (12) µs tPZH tPLH tPHL – – – 0.3 1.2 0.5 1.0 2.0 1.0 µs tTON tTOFF – – – – 10 10 tV fOSC 100 – – 200 0.1 – 400 1.0 10 kHz ms ms CRESON tVDDDET Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load is 500 pF. Time to charge CRES to 11 V after application of VDD. 17510 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS IN1, IN2, EN (GIN) tPZH*, tPLH (tTON) 50% VDD VDDDETON 3.5 V 50% VDDDETOFF (tTOFF) tPHL 1.5 V t VDDDET tV 90% 90% OUTn (GOUT) 10% IM DDDET 0% (