MPC17531A

Freescale Semiconductor Technical Data Document Number: MPC17531A Rev. 3.0, 2/2008 700 mA Dual H-Bridge Motor Driver with 3.0 V Compatible Logic I/O The 17531A is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar step motors and/or brush DC-motors (e.g., cameras and disk drive head positioners). The 17531A operates from 2.0 V to 8.6 V using the internal charge pump, with independent control of each H-Bridge via parallel MCU interface. The device features built-in shoot-through current protection and an undervoltage shutdown function. The 17531A has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17531A has a low total RDS(ON) of 1.2 Ω (max @ 25°C). The 17531A efficiently drives many types of micromotors with low power dissipation owing to its low output resistance and high output slew rates. The H-Bridge outputs can be independently pulse width modulated (PWM’ed) at up to 200 kHz for speed/torque and current control. Features • • • • • • • • • Low Total RDS(ON) 0.8 W (Typ), 1.2 Ω (Max) @ 25°C Output Current 0.7 A (DC) Shoot-Through Current Protection Circuit PWM Control Input Frequency up to 200 kHz Built-In Charge Pump Circuit Low Power Consumption Undervoltage Detection and Shutdown Circuit Power Save Mode with Current Draw ≤ 2.0 µA Pb-Free Packaging Designated by Suffix Codes EV and EP 17531A DUAL H-BRIDGE VMFP SUFFIX EV SUFFIX (PB-FREE) 98ASA10616D 20-TERMINAL VMFP QFN SUFFIX EP SUFFIX (PB-FREE) 98ARL10577D 24-TERMINAL QFN ORDERING INFORMATION Device MPC17531AEV/EL MPC17531AEP/R2 Temperature Range (TA) -20°C to 65°C Package 20 VMFP 24 QFN 3.0 V 5.0 V 17531A VDD VM C1L C1H C2L OUT1A C2H CRES OUT1B IN1A OUT2A IN1B OUT2B IN2A IN2B PSAVE GND Bipolar Step Motor S N MCU Figure 1. 17531A Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2005. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM CRES C2H C1H C1L C2L LowVoltage Shutdown Charge Pump VDD VM1 IN1A H-Bridge IN1B VDD Level Shifter Predriver OUT1A OUT1B PGND1 VM2 PSAVE Control Logic IN2A OUT2A H-Bridge IN2B OUT2B LGND PGND2 Figure 2. 17531A Simplified Internal Block Diagram 17531A 2 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS TERMINAL CONNECTIONS VDD IN1A IN1B 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 LGND IN2A IN2B VM2 OUT2B PGND2 OUT1B C2L C1L C1H PSAVE OUT2A PGND1 OUT1A VM1 CRES C2H Figure 3. 17531A, 20-Terminal VMFP Connections Table 1. 17531A, 20-Terminal VMFP Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10. Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal Name VDD IN1A IN1B PSAVE OUT2A PGND1 OUT1A VM1 CRES Formal Name Logic Supply Logic Input Control 1A Logic Input Control 1B Power Save H-Bridge Output 2A Power Ground 1 H-Bridge Output 1A Motor Drive Power Supply 1 Predriver Power Supply Charge Pump 2H Charge Pump 1H Charge Pump 1L Charge Pump 2L H-Bridge Output 1B Power Ground 2 H-Bridge Output 2B Motor Drive Power Supply 2 Logic Input Control 2B Logic Input Control 2A Logic Ground Definition Control circuit power supply terminal. Logic input control of OUT1A (refer to Table 6, Truth Table, page 9). Logic input control of OUT1B (refer to Table 6, Truth Table, page 9). Logic input controlling power save mode. Output A of H-Bridge channel 2. High-current power ground 1. Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Internal triple charge pump output as predriver power supply. Charge pump bucket capacitor 2 (positive pole). Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). Charge pump bucket capacitor 2 (negative pole). Output B of H-Bridge channel 1. High-current power ground 2. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Logic input control of OUT2B (refer to Table 6, Truth Table, page 9). Logic input control of OUT2A (refer to Table 6, Truth Table, page 9). Low-current logic signal ground. C2H C1H C1L C2L OUT1B PGND2 OUT2B VM2 IN2B IN2A LGND 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 3 TERMINAL CONNECTIONS IN1B IN1A IN2A 21 20 24 23 22 NC PSAVE OUT2A PGND1 OUT1A NC 1 2 3 4 5 6 IN2B 19 18 17 16 VDD Transparent Top View of Package LGND VM2 NC OUT2B PGND2 OUT1B C2L MPC17530EP 15 14 13 7 8 9 10 11 12 NC C2H VM1 Figure 4. 17531A, 24-Terminal QFN Connections Table 2. 17531A, 24-Terminal QFN Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10. Terminal Number 1, 6, 7, 17 2 3 4 5 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 Terminal Name NC PSAVE OUT2A PGND1 OUT1A VM1 CRES C2H C1H C1L C2L OUT1B PGND2 OUT2B VM2 IN2B IN2A LGND VDD IN1A IN1B Formal Name No Connect Power Save H-Bridge Output 2A Power Ground 1 H-Bridge Output 1A Motor Drive Power Supply 1 Predriver Power Supply Charge Pump 2H Charge Pump 1H Charge Pump 1L Charge Pump 2L H-Bridge Output 1B Power Ground 2 H-Bridge Output 2B Motor Drive Power Supply 2 Logic Input Control 2B Logic Input Control 2A Logic Ground Logic Supply Logic Input Control 1A Logic Input Control 1B This terminal is not used. Logic input controlling power save mode. Output A of H-Bridge channel 2. High-current power ground 1. Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Internal triple charge pump output as pre-driver power supply. Charge pump bucket capacitor 2 (positive pole). Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). Charge pump bucket capacitor 2 (negative pole). Output B of H-Bridge channel 1. High-current power ground 2. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Logic input control of OUT2B (refer to Table 6, Truth Table, page 9). Logic input control of OUT2A (refer to Table 6, Truth Table, page 9). Low-current logic signal ground. Control circuit power supply terminal. Logic input control of OUT1A (refer to Table 6, Truth Table, page 9). Logic input control of OUT1B (refer to Table 6, Truth Table, page 9). Definition 17531A CRES C1H C1L 4 Analog Integrated Circuit Device Data Freescale Semiconductor MAXIMUM RATINGS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage Driver Output Current Continuous Peak (1) ESD Voltage Human Body Model Machine Model (3) Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range Thermal Resistance (4) (2) Symbol VM VC RES VDD VIN IO IOPK Value -0.5 to 11.0 -0.5 to 14.0 -0.5 to 5.0 -0.5 to VDD + 0.5 0.7 1.4 Unit V V V V A V VESD1 VESD2 TJ TA TSTG RθJA PD 1.0 2.5 TSOLDER 260 °C ±1200 ± 150 -20 to 150 -20 to 65 -65 to 150 50 °C °C °C °C/W W Power Dissipation (5) WMFP QFN Terminal Soldering Temperature (6) Notes 1. TA = 25°C. Pulse width = 10 ms at 200 ms intervals. 2. 3. 4. 5. 6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). For QFN only, mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB). TA = 25°C. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 5 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER INPUT Motor Supply Voltage (Using Internal Charge Pump) (7) Motor Supply Voltage ( CRES Applied Externally) (8) Gate Drive Voltage - Motor Supply Voltage ( CRES Applied Externally) (9) Logic Supply Voltage Driver Quiescent Supply Current No Signal Input Power Save Mode Logic Quiescent Supply Current No Signal Input (10) Symbol Min Typ Max Unit VM-CP VM-NCP 2.0 – 5.0 2.7 5.0 – 6.0 3.0 8.6 10 – 3.6 V V V V µA V V VCRES - VM VDD QM I QM-PSAVE QVDD I QVDDPSAVE (11) I – – – – 100 1.0 mA I – – – – 1.0 1.0 mA Power Save Mode Operating Power Supply Current Logic Supply Current I Charge Pump Circuit Supply Current (12) Low VDD Detection Voltage (13) Driver Output ON Resistance (14) GATE DRIVE Gate Drive Voltage (12) No Current Load Gate Drive Ability (Internally Supplied) ICRES V VDD – – 1.0 – – – 1.6 0.8 3.0 0.7 2.5 1.2 V Ohms DDDET RDS(ON) VCRES 12 13 13.5 V VCRESload 8.5 CCP 0.01 9.2 0.1 – 1.0 V I CRES = -1.0 mA Recommended External Capacitance (C1L – C1H, C2L – C2H, CRES – GND) Notes 7. 8. 9. 10. 11. 12. 13. 14. µF Gate drive voltage VCRES is applied from an external source. 2 x VDD + VM must be < VCRES max (13.5 V). V No internal charge pump used. CRES is applied from an external source. RDS(ON) is not guaranteed if CRES - VM < 5.0 V. Also, function is not guaranteed if CRES - VM < 3.0 V. I QVDD includes the current to pre-driver circuit. I VDD includes the current to predriver circuit at fIN = 100 kHz. At fIN = 20 kHz. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. VCRES is V applied from an external source. 2 x VDD + VM must be < CRES max (13.5 V). IO = 0.7 A source + sink. V V 17531A 6 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic CONTROL LOGIC Logic Input Voltage Logic Inputs (2.7 V < VDD < 3.3 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current PSAVE Terminal Input Current Low VIH VIL IIH IIL IIL- PSAVE VDD x 0.7 – – -1.0 – – – – – 50 – VDD x 0.3 1.0 – 100 V V µA µA µA VIN 0 – Symbol Min Typ Max Unit VDD V 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 7 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic INPUT Pulse Input Frequency Input Pulse Rise Time (15) Input Pulse Fall Time (17) OUTPUT Propagation Delay Time (18) Turn-ON Time Turn-OFF Time Charge Pump Wake-Up Time (19) Low-Voltage Detection Time Notes 15. 16. 17. 18. 19. Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Output load is 8.0 Ω DC. CCP = 0.1 µF. µs f IN tR tF – – – – – – 200 (16) Symbol Min Typ Max Unit kHz µs µs 1.0 1.0 (16) t PLH t PHL t VGON – – – – 0.1 0.1 1.0 – 0.5 0.5 3.0 10 ms ms t VDDDET 17531A 8 Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS TIMING DIAGRAMS IN1, IN2, PSAVE V DDDETon 50% 2.5 V 50% V DDDEToff VDD tPLH OUTA, OUTB 90% 10% tPHL 0.8 V t VDDDET 90% t VDDDET IM 0% (> VDD (e.g., VM = 5.0 V, VDD = 3.3 V), in order to ensure full enhancement of the high-side MOSFET channels. 3.3 V 5.0 V 17531A V CRES < 14 V RG > CRES /0.02 Ω RG V NC NC NC NC 0.01 µF C1L C1H C2L C2H CRES VDD VM OUT1A OUT1B MCU IN1A IN1B IN2A IN2B OUT2B PSAVE GND OUT2A NC = No Connect Figure 8. 17531A Typical Application Diagram CEMF SNUBBING TECHNIQUES Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients via placing a capacitor or zener at the supply terminal (VM) (see Figure 9). 3.3 V 5.0 V 17531A VM VDD C1L C1H C2L C2H CRES OUT GND OUT PCB LAYOUT When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground terminals to ensure proper filtering from transients. For all high-current paths, use wide copper traces and shortest possible distances. 3.3 V 5.0 V 17531A VDD VM C1L C1H C2L C2H CRES OUT GND OUT Figure 9. CEMF Snubbing Techniques 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 11 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” drawing number listed below. EV (Pb-FREE) SUFFIX 20-LEAD VMFP PLASTIC PACKAGE 98ASA10816D ISSUE A 17531A 12 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EV (Pb-FREE) SUFFIX 20-LEAD VMFP PLASTIC PACKAGE 98ASA10816D ISSUE A 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 13 PACKAGING PACKAGE DIMENSIONS EV (Pb-FREE) SUFFIX 20-LEAD VMFP PLASTIC PACKAGE 98ASA10816D ISSUE A 17531A 14 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 15 PACKAGING PACKAGE DIMENSIONS EP (Pb-FREE) SUFFIX 24-LEAD QFN PLASTIC PACKAGE 98ARL10577D ISSUE A 17531A 16 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EP (Pb-FREE) SUFFIX 24-LEAD QFN PLASTIC PACKAGE 98ARL10577D ISSUE A 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 17 PACKAGING PACKAGE DIMENSIONS EP (Pb-FREE) SUFFIX 24-LEAD QFN PLASTIC PACKAGE CASE 1508-01 ISSUE A 17531A 18 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION 2.0 3.0 DATE 9/2005 2/2008 DESCRIPTION OF CHANGES • • • Implemented Revision History page Converted to Freescale format Corrected Table 2, Pin Definitiuons on page 4. 17531A Analog Integrated Circuit Device Data Freescale Semiconductor 19 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2005. All rights reserved. MPC17531A Rev. 3.0 2/2008