MPC17533EVEL

Freescale Semiconductor Advance Information Document Number: MPC17533 Rev. 3.0, 7/2006 0.7 A 6.8 V Dual H-Bridge Motor Driver The 17533 is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar stepper motors and/or brush DC-motors (e.g., cameras and disk drive head positioners). The 17533 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 V- and 5.0 V-compatible logic). The device features built-in shoot-through current protection and an undervoltage shutdown function. The 17533 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17533 has a low total RDS(ON) of 1.2 Ω (max @ 25°C). The 17533’s low output resistance and high slew rates provide efficient drive for many types of micromotors. Features • Low Total RDS(ON) 0.8 Ω (Typ), 1.2 Ω (Max) @ 25°C • Output Current 0.7 A (DC), 1.4 A (Peak) • Shoot-Through Current Protection Circuit • 3.0 V/ 5.0 V CMOS-Compatible Inputs • PWM Control Input Frequency up to 200 kHz • Built-In 2-Channel H-Bridge Driver • Low Power Consumption • Undervoltage Detection and Shutdown Circuit • Pb-Free Packaging Designated by Suffix Code EV 17533 H-BRIDGE MOTOR DRIVER EV SUFFIX (Pb-FREE) 98ASA10614D 16-PIN VMFP ORDERING INFORMATION Device MPC17533EV/EL Temperature Range (TA) -20°C to 65°C Package 16 VMFP 5.0 V 13 V 17533 VDD VG 5.0 V VM OUT1A OUT1B MCU IN1A IN1B IN2A IN2B OE OUT2A OUT2B S N Bipolar Step Motor GND Figure 1. 17533 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VG LowVoltage Shutdown VDD VM1 IN1A H-Bridge 1 OUT1A OUT1B IN1B VDD PGND1 OE Control Logic Level Shifter Predriver VM2 IN2A OUT2A H-Bridge 2 OUT2B IN2B LGND PGND2 Figure 2. 17533 Simplified Internal Block Diagram 17533 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS OUT1A VM1 IN1A IN1B VDD OE LGND OUT1B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PGND2 OUT2A IN2A IN2B VG VM2 OUT2B PGND1 Figure 3. 17533 Pin Connections Table 1. PIN Function Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name OUT1A VM1 IN1A IN1B VDD OE LGND OUT1B PGND1 OUT2B VM2 VG IN2B IN2A OUT2A PGND2 Formal Name H-Bridge Output 1A Motor Drive Power Supply 1 Logic Input Control 1A Logic Input Control 1B Logic Supply Output Enable Logic Ground H-Bridge Output 1B Power Ground 1 H-Bridge Output 2B Motor Drive Power Supply 2 Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Logic input control of OUT1A (refer to Table 5, Truth Table, page 7). Logic input control of OUT1B (refer to Table 5, Truth Table, page 7). Control circuit power supply pin. Logic output Enable control of H-Bridges (Low = True). Low-current logic signal ground. Output B of H-Bridge channel 1. High-current power ground 1. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Definition Gate Driver Circuit Voltage Input Input pin for the gate drive voltage. Logic Input Control 2B Logic Input Control 2A H-Bridge Output 2A Power Ground 2 Logic input control of OUT2B (refer to Table 5, Truth Table, page 7). Logic input control of OUT2A (refer to Table 5, Truth Table, page 7). Output A of H-Bridge channel 2. High-current power ground 2. 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device. Rating Motor Supply Voltage Gate Driver Circuit Power Supply Voltage Logic Supply Voltage Signal Input Voltage Driver Output Current Continuous Peak (1) ESD Voltage (2) Symbol VM VG VDD VIN IO IOPK Value -0.5 to 8.0 -0.5 to 14 -0.5 to 7.0 -0.5 to VDD + 0.5 0.7 1.4 Unit V V V V A V VESD1 VESD2 TJ TA TSTG RθJA PD (5) Human Body Model Machine Model Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range Thermal Resistance Power Dissipation (3) ±1500 ± 200 -55 to 150 -20 to 65 -55 to 150 150 830 260 °C °C °C °C/W mW °C (4) Pin Soldering Temperature TSOLDER Notes 1. TA = 25°C. 10 ms pulse at 200 ms intervals. 2. 3. 4. 5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). Mounted on 37 mm x 50 mm x 1.6 mm glass epoxy board mount. TA = 25°C. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 17533 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER Motor Supply Voltage Logic Supply Voltage Quiescent Power Supply Current Driver Circuit Power Supply Current Logic Supply Current (6) Gate Driver Circuit Power Supply Current Operating Power Supply Current Logic Supply Current (7) Gate Driver Circuit Power Supply Current (8) Low VDD Detection Voltage (9) Driver Output ON Resistance Source + Sink at IO = 0.7 A(10) RDS(ON) RDS(ON)2 – – 0.8 – 1.2 1.5 I IQ M Symbol Min Typ Max Unit VM VDD 2.0 2.7 5.0 5.0 6.8 5.7 V V µA – – – – – – 1.0 20 150 mA QVDD I QVG IV I DD – – 1.5 – – 2.0 3.0 0.7 2.5 V Ω VG VDD DET VG = 9.5 V, VM = 5.0 V, TA = 25°C(11) GATE DRIVE Gate Drive Circuit Power Supply Voltage CONTROL LOGIC Logic Input Voltage Logic Inputs (2.7 V < VDD < 5.7 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current OE Pin Input Current Low VG 12 13 13.5 V VIN VIH VIL IIH IIL IIL-OE 0 – VDD – VDD x 0.3 1.0 – 100 V VDD x 0.7 – – -1.0 – – – – – 50 V V µA µA µA Notes 6. IQVDD includes the current to predriver circuit. 7. 8. 9. 10. 11. IV DD includes the current to predriver circuit at fIN = 100 kHz. At fIN = 20 kHz. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When gate voltage VG is applied from an external source, VG = 7.5 V. The total H-Bridge ON resistance when VG is 13V. Increased RDS(ON) value as the result of a reduced VG value of 9.5 V. 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Characteristic INPUT Pulse Input Frequency Input Pulse Rise Time (12) Symbol Min Typ Max Unit f IN tR tF – – – – – – 200 1.0 (13) kHz µs µs Input Pulse Fall Time (14) OUTPUT Propagation Delay Time (15) Turn-ON Time Turn-OFF Time Low-Voltage Detection Notes 12. 13. 14. 15. 16. Time(16) 1.0 (13) µs t PLH t PHL tV DD DET – – – 0.1 0.1 – 0.5 0.5 10 ms Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load of Output is 8.0 Ω resistance. see figure 4 See figure 5. 17533 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS IN1, IN2, OE VDDDETon 50% VDD 2.5 V 50% VDDDEToff 1.5 V tPLH OUTA, OUTB 90% 10% tPHL t VDDDET 90% t VDDDET 0% (> VDD (e.g., VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement of the high-side MOSFET channels. 5.0 V 17533 V G < 14 V RG > VG /0.02 Ω VDD VM OUT1A VG RG 0.01 µF OUT1B MCU IN1A IN1B IN2A IN2B OE OUT2A OUT2B GND Figure 6. 17533 Typical Application Diagram CEMF SNUBBING TECHNIQUES Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commuting currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a zener or a capacitor at the supply pin (VM) (see Figure 7). 5.0 V 5.0 V 17533 VDD VM 5.0 V 5.0 V 17533 VDD VM PCB LAYOUT When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground pins to ensure proper filtering from transients. For all highcurrent paths, use wide copper traces and shortest possible distances. OUT OUT OUT OUT OUT OUT OUT GND OUT GND Figure 7. CEMF Snubbing Techniques 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 9 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A number listed below. EV (Pb-FREE) SUFFIX 16-LEAD VMFP PLASTIC PACKAGE 98ASA10614D ISSUE B 17533 10 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION 2.0 3.0 DATE 5/2006 7/2006 DESCRIPTION OF CHANGES • • • • • Converted to Freescale format Added Revision History page Updated to the prevailing form and style Corrected device isometric drawing on page 1 Added RoHS compliance 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 11 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2006. All rights reserved. MPC17533 Rev. 3.0 7/2006