MPC5125YVN400

Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5125 Rev. 3, 11/2009 MPC5125 MPC5125 Microcontroller Data Sheet The MPC5125 integrates a high performance e300 CPU core based on the Power Architecture™ Technology with a rich set of peripheral functions focused on communications and systems integration. Major features of the MPC5125 are as follows: • e300 Power Architecture processor core (enhanced version of the MPC603e core), operates as fast as 400 MHz Low power design Display interface unit (DIU) DDR1, DDR2, low-power mobile DDR (LPDDR), and 1.8 V/3.3 V SDR DRAM memory controllers 32 KB on-chip SRAM USB 2.0 OTG controller with ULPI interface DMA subsystem Flexible multi-function external memory bus (EMB) interface NAND flash controller (NFC) LocalPlus interface (LPC) 10/100Base Ethernet MMC/SD/SDIO card host controller (SDHC) Programmable serial controller (PSC) Inter-integrated circuit (I2C) communication interfaces Controller area network (CAN) J1850 byte data link controller (BDLC) interface On-chip real-time clock (RTC) On-chip temperature sensor IC Identification module (IIM) 324 TEPBGA 23 mm x 23 mm • • • • • • • • • • • • • • • • • • This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008–2009. All rights reserved. Table of Contents 1 2 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 MPC5125 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 324-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .5 3.2 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .6 3.2.1 Power and Ground Supply Summary . . . . . . . .35 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . .36 4.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .36 4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . .36 4.1.2 Recommended Operating Conditions . . . . . . . .36 4.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . .37 4.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . .40 4.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .41 4.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . .42 4.2 Oscillator and PLL Electrical Characteristics . . . . . . . .43 4.2.1 System Oscillator Electrical Characteristics . . .44 4.2.2 RTC Oscillator Electrical Characteristics . . . . . .44 4.2.3 System PLL Electrical Characteristics. . . . . . . .45 4.2.4 e300 Core PLL Electrical Characteristics . . . . .45 4.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .46 4.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .46 4.3.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.3.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .50 4.3.5 SDRAM (DDR) . . . . . . . . . . . . . . . . . . . . . . . . .50 4.3.6 LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.3.7 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.10 MMC/SD/SDIO Card Host Controller (SDHC) . 4.3.11 DIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.12 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.13 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.14 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.15 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.16 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 4.3.17 Fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.18 IEEE 1149.1 (JTAG) . . . . . . . . . . . . . . . . . . . . . System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . 5.2 System and CPU Core AVDD Power Supply Filtering . 5.3 Connection Recommendations . . . . . . . . . . . . . . . . . . 5.4 Pullup/Pulldown Resistor Requirements . . . . . . . . . . . 5.4.1 Pulldown Resistor Requirements for TEST Pin 5.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 JTAG_TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 e300 COP / BDM Interface . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 63 66 67 68 71 71 72 72 79 79 80 82 82 82 82 83 83 83 83 83 87 87 88 91 91 4 5 6 7 8 MPC5125 Microcontroller Data Sheet, Rev. 3 2 Freescale Semiconductor Ordering Information 1 Ordering Information M PC 5125 Y VN 400 R Qualification status Core code Device number Temperature range Package identifier Operating frequency (MHz) Tape and reel status Temperature Range Y = –40 °C to 125 °C, junction Package Identifier VN = 324 TEPBGA Pb-free Operating Frequency 400 = 400 MHz Tape and Reel Status R = Tape and reel (blank) = Trays Qualification Status P = Pre qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Note: Not all options are available on all devices. Refer to Table 1. Figure 1. MPC5125 Orderable Part Number Description Table 1 shows the orderable part numbers for the MPC5125. Table 1. MPC5125 Orderable Part Numbers Freescale Part Number1 MPC5125YVN400 Speed (MHz) Package Description MPC5125 324TEPBGA package Lead-free (PbFree) Max3 (fMAX) 400 MHz core 200 MHz bus Operating Temperature2 Min (TL) –40 °C Max (TH) 125 °C NOTES: 1 All packaged devices are PPC5125, rather than MPC125, until product qualifications are complete. 2 The lowest ambient operating temperature (TA) is referenced by TL; the highest junction temperature is referenced by TH. 3 Maximum speed is the maximum frequency allowed including frequency modulation (FM). MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 3 MPC5125 Block Diagrams 2 MPC5125 Block Diagrams Functionally Multiplexed I/O Display SDR, Mobile DDR, DDR1/2 Memory Figure 2 shows a simplified MPC5125 block diagram. DIU LPC EMB NFC 200 MHz CSB Bus (64 bits) 66 MHz IP BUS 32 KB SRAM MPC5125 Multi-Port Memory Controller FEC1 FEC2 USB1 ULPI USB2 ULPI DMA 64-Channel TempSensor Fuse PMC JTAG/COP JTAG/COP e300 Power Architecture 32 KB instruction / 32 KB data cache SDHC × 2 200 MHz AHB (32 bits) PSC × 10 GPIO × 2 CAN × 4 GPT × 2 I2C × 3 J1850 WDT Clock/Reset Figure 2. Simplified MPC5125 Block Diagram MPC5125 Microcontroller Data Sheet, Rev. 3 4 Freescale Semiconductor RTC IPIC Pin Assignments 3 3.1 1 A VSS Pin Assignments 324-ball TEPBGA Pin Assignments 2 VSS 3 EMB_A D01 4 5 6 7 RTC_X TALO 8 RTC_X TALI 9 SYS_X TALI 10 SYS_X TALO AVSS_ OSC_T MPS_S PLL AVDD_ OSC_T MPS AVDD_ CPLL 11 AVDD_ SPLL 12 PSC0_ 1 13 PSC0_ 2 14 VDD_I O 15 PSC1_ 4 16 CAN2_ TX 17 HRESE T_B 18 SRESE T_B 19 I2C1_S DA 20 21 22 VSS This section details pin assignments. Figure 3 shows the 324-ball TEPBGA pin assignments. EMB_A GPIO01 GPIO02 D00 MCAS_ MWE_B B B VSS EMB_A D05 EMB_A D03 EMB_A D02 J1850_ TX GPIO00 VSS CAN2_ RX VDD_I O AVSS_ CPLL VDD_I O PSC0_ 3 PSC1_ 2 CAN1_ TX TDO VDD_I O I2C1_S VDD_I CL O_MEM MA15 MA14 MA11 C EMB_A D11 EMB_A D09 EMB_A D07 EMB_A D06 VDD_I O J1850_ RX GPIO03 HIB_M ODE_B CAN1_ RX PSC0_ 0 PSC1_ 0 PSC1_ 1 VDD_I O TDI TCK PORES ET_B MCKE MRAS_ B MA12 VDD_I O_MEM MA09 D TMPS_ ANAVIZ EMB_A D15 EMB_A D21 EMB_A D25 EMB_A D28 EMB_A D31 EMB_A X00 LPC_A X03 LPC_C S0_B NFC_R B NFC_C E0_B SDHC1 _D2 SDHC1 _CLK FEC1_ CRS FEC1_ MDC FEC1_ TX_CL K FEC1_ TXD_3 FEC1_ TXD_2 EMB_A D10 EMB_A D13 VDD_I O EMB_A D18 VDD_I O EMB_A D26 VSS EMB_A X02 VDD_I O LPC_O E_B VSS SDHC1 _D3 SDHC1 _CMD VSS FEC1_ MDIO FEC1_ TX_ER VDD_I O EMB_A D12 EMB_A D16 EMB_A D17 EMB_A D20 EMB_A D23 EMB_A D24 EMB_A D29 EMB_A D30 LPC_R WB LPC_A CK_B VDD_I O SDHC1 _D0 FEC1_ COL VDD_I O FEC1_ TXD_1 FEC1_ TX_EN FEC1_ RXD_1 FEC1_ RX_DV AVDD_ EMB_A FUSEW D04 R EMB_A D08 VSS VDD_I O EMB_A D14 EMB_A D19 EMB_A D22 VSS EMB_A D27 EMB_A X01 VSS LPC_C LK SDHC1 _D1 I2C2_S DA I2C2_S CL FEC1_ TXD_0 FEC1_ RXD_2 VDD_I O FEC1_ RX_CL K VDD_I O FEC1_ RX_ER USB1_ NEXT USB1_ DATA7 PSC_M CLK_IN VSS VBAT SPLL_A NAVIZ PSC0_ 4 VSS PSC1_ 3 TEST TMS TRST_ B VDD_I VDD_I MCS_B O_MEM O_MEM MA13 MA08 MA06 E MA10 MA07 MA04 MA03 F MA02 VDD_I O_MEM MBA0 MA05 VSS MA01 G TOP DOWN VIEW MA00 MBA2 VDD_I O_MEM MDQ30 MCK_B H MBA1 MCK J VSS VDD VDD VDD VDD VSS MODT MDQ31 MDQ29 K VSS VSS VSS VSS VSS VDD MVTT3 MDQ28 VSS MDM3 L VDD VSS VSS VSS VSS VDD VSS MDQ26 MDQ27 MDQS3 M VDD VSS VSS VSS VSS VDD MVTT2 MDQ23 MDQ24 MDQ25 N VSS VSS VSS VSS VSS VDD MVREF MDQ20 VSS MDQ22 P VSS VDD VDD VDD VDD VSS VDD_I MDQ18 MDQS2 MDQ21 O_MEM MVTT1 MDQ16 VDD_I O_MEM MDQ17 MDM2 R T VDD_I MDQ13 O_MEM MDQ07 MDQS1 VDD_I MDQ10 O_MEM USB1_ STOP USB1_ DATA6 VSS USB1_ DIR USB1_ DATA5 USB1_ DATA4 USB1_ DATA2 USB1_ DATA1 USB1_ DATA0 VDD_I O DIU_HS YNC DIU_LD DIU_LD 08 13 VDD_I O DIU_LD 21 VDD_I MDQ06 O_MEM MDQ19 U VSS MDQ15 V MDM1 MDQ14 W VSS VSS VSS VSS MVTT0 MDQ11 MDQ12 Y VSS FEC1_ RXD_3 FEC1_ RXD_0 USB1_ CLK DIU_DE DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_VS MDQ01 01 03 07 10 14 17 22 YNC DIU_LD DIU_LD 02 04 VDD_I O DIU_LD 11 VDD_I O DIU_LD 16 VDD_I O DIU_LD 23 VSS MDM0 MDQ05 VDD_I MDQ09 O_MEM MDQ08 AA MDQ02 MDQS0 MDQ04 AB VSS USB1_ DATA3 DIU_CL DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD DIU_LD K 00 05 06 09 12 15 18 19 20 VDD_I O MDQ00 VDD_I MDQ03 O_MEM VSS Figure 3. Ball Map for the MPC5125 324 TEPBGA Package MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 5 3.2 Pin Muxing and Reset States Table 2. MPC5125 Pin Multiplexing Pad I/O Alternate Control Register1 Function3 and Offset2 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 GPIO00 — — — GPIO01 — — — GPIO02 — — — GPIO03 — — — RTC_XTALI — — — RTC_XTALO — — — HIB_MODE — — — I/O Power Domain Direction I — — — I — — — I — — — I — — — I — — — O — — — O — — — VBAT 6 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor Pin Assignments Table 2 provides the pinout listing for the MPC5125. Pin Functions4 Peripheral5 Notes Pin GPIO00 GPIO1 — — — GPIO1 — — — GPIO1 — — — GPIO1 — — — RTC — — — RTC — — — RTC — — — Analog Visible Signal Dedicated input can be used to receive an external wakeup. Dedicated input can be used to receive an external wakeup. Dedicated input can be used to receive an external wakeup. Dedicated input can be used to receive an external wakeup. — B6 GPIO01 — VBAT A5 GPIO02 — VBAT A6 GPIO03 — VBAT C7 RTC_XTALI — VBAT A8 RTC_XTALO — VBAT — A7 HIB_MODE — VBAT In Hibernation mode , this pin provides a signal to shut down an external power supply. C8 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction — — — — — — — SysClock — — — SysClock — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — — — — — — — — I — — — O — — — O — — — O — — — O — — — I — — — SYS_PLL _AVDD — A9 — D1 Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 7 Pin Functions4 Peripheral5 Notes Pin SPLL_ANAVIZ SPLL_ANAVIZ — — — TMPS_ANAVIZ — — — SYS_XTALI — — — SYS_XTALO — — — MCS0 — — — MCAS — — — MRAS — — — MVREF — — — — D9 TMPS_ANAVIZ — SYS_XTALI — SYS_XTALO — SYS_PLL _AVDD — A10 MCS 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 — ALT0 ALT1 ALT2 ALT3 VDD_IO_MEM — D18 MCAS VDD_IO_MEM — A20 MRAS VDD_IO_MEM — C19 MVREF VDD_IO_MEM — N19 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 MVTT0 — — — MVTT1 — — — MVTT2 — — — MVTT3 — — — MWE — — — MDQ00 — — — MDQ01 — — — MDQ02 — — — I/O Power Domain Direction I — — — I — — — I — — — I — — — O — — — I/O — — — I/O — — — I/O — — — VDD_IO_MEM 8 Pin MVTT0 MVTT1 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor — MVTT2 — MVTT3 — MWE 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 MDQ00 MDQ01 MDQ02 Pin Assignments Functions4 Peripheral5 Notes Pin DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — — W18 VDD_IO_MEM — R19 VDD_IO_MEM — M19 VDD_IO_MEM — K19 VDD_IO_MEM — A21 VDD_IO_MEM — AB19 VDD_IO_MEM — Y18 VDD_IO_MEM — AA19 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 MDQ03 — — — MDQ04 — — — MDQ05 — — — MDQ06 — — — MDQ07 — — — MDQ08 — — — MDQ09 — — — MDQ10 — — — I/O Power Domain Direction I/O — — — I/O — — — I/O — — — I/O — — — I/O — — — I/O — — — I/O — — — I/O — — — VDD_IO_MEM Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 9 Pin Functions4 Peripheral5 Notes Pin MDQ03 DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — — AB21 MDQ04 VDD_IO_MEM — AA21 MDQ05 VDD_IO_MEM — Y20 MDQ06 VDD_IO_MEM — W20 MDQ07 VDD_IO_MEM — U19 MDQ08 VDD_IO_MEM — AA22 MDQ09 VDD_IO_MEM — Y22 MDQ10 VDD_IO_MEM — V20 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 0x00 ALT0 IO_CONALT1 TROL_MEM ALT2 ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 MDQ11 — — — MDQ12 — — — MDQ13 — — — MDQ14 — — — MDQ15 — — — MDQ16 — — GPT1[0] MDQ17 — — GPT1[1] MDQ18 — — GPT1[2] I/O Power Domain Direction I/O — — — I/O — — — I/O — — — I/O — — — I/O — — — I/O — — I/O I/O — — I/O I/O — — I/O VDD_IO_MEM 10 Pin MDQ11 MDQ12 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor MDQ13 MDQ14 MDQ15 MDQ16 MDQ17 MDQ18 Pin Assignments Functions4 Peripheral5 Notes Pin DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — GPT1 DRAM — — GPT1 DRAM — — GPT1 — W21 VDD_IO_MEM — W22 VDD_IO_MEM — T20 VDD_IO_MEM — V22 VDD_IO_MEM — U22 VDD_IO_MEM — R20 VDD_IO_MEM — T21 VDD_IO_MEM — P20 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 ALT2 IO_CONTROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 0x00 0x00 0x00 0x00 0x00 0x00 MDQ19 — — GPT1[3] MDQ20 — — GPT1[4] MDQ21 — — GPT1[5] MDQ22 — — GPT1[6] MDQ23 — — GPT1[7] MDQ24 — — GPIO21 MDQ25 — — GPIO22 MDQ26 — — GPIO23 I/O Power Domain Direction I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O VDD_IO_MEM Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 11 Pin Functions4 Peripheral5 Notes Pin MDQ19 DRAM — — GPT1 DRAM — — GPT1 DRAM — — GPT1 DRAM — — GPT1 DRAM — — GPT1 DRAM — — GPIO1 DRAM — — GPIO1 DRAM — — GPIO1 — T22 MDQ20 VDD_IO_MEM — N20 MDQ21 VDD_IO_MEM — P22 MDQ22 VDD_IO_MEM — N22 MDQ23 VDD_IO_MEM — M20 MDQ24 VDD_IO_MEM — M21 MDQ25 VDD_IO_MEM — M22 MDQ26 VDD_IO_MEM — L20 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 ALT2 IO_CONTROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 0x00 0x00 0x00 0x00 0x00 0x00 MDQ27 — — GPIO24 MDQ28 — — GPIO25 MDQ29 — — GPIO26 MDQ30 — — GPIO27 MDQ31 — — GPIO28 MDM0 — — — MDM1 — — — MDM2 — — GPIO29 I/O Power Domain Direction I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O O — — — O — — — O — — I/O VDD_IO_MEM 12 Pin MDQ27 MDQ28 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor MDQ29 MDQ30 MDQ31 MDM0 MDM1 MDM2 Pin Assignments Functions4 Peripheral5 Notes Pin DRAM — — GPIO1 DRAM — — GPIO1 DRAM — — GPIO1 DRAM — — GPIO1 DRAM — — GPIO1 DRAM — — — DRAM — — — DRAM — — GPIO1 — L21 VDD_IO_MEM — K20 VDD_IO_MEM — J22 VDD_IO_MEM — J21 VDD_IO_MEM — J20 VDD_IO_MEM — Y19 VDD_IO_MEM — V21 VDD_IO_MEM — R22 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 ALT2 IO_CONTROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 0x00 0x00 0x00 0x00 0x00 0x00 MDM3 — — GPIO30 MDQS0 — — — MDQS1 — — — MDQS2 — — GPIO31 MDQS3 — — GPIO32 MBA0 — — — MBA1 — — — MBA2 — — — I/O Power Domain Direction O — — I/O I/O — — — I/O — — — I/O — — I/O I/O — — I/O O — — — O — — — O — — — VDD_IO_MEM Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 13 Pin Functions4 Peripheral5 Notes Pin MDM3 DRAM — — GPIO1 DRAM — — — DRAM — — — DRAM — — GPIO1 DRAM — — GPIO2 DRAM — — — DRAM — — — DRAM — — — — K22 MDQS0 VDD_IO_MEM — AA20 MDQS1 VDD_IO_MEM — U20 MDQS2 VDD_IO_MEM — P21 MDQS3 VDD_IO_MEM — L22 MBA0 VDD_IO_MEM — H19 MBA1 VDD_IO_MEM — H20 MBA2 VDD_IO_MEM — G21 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 ALT2 IO_CONTROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 0x00 0x00 0x00 0x00 0x00 0x00 MA00 — — — MA01 — — — MA02 — — — MA03 — — — MA04 — — — MA05 — — — MA06 — — — MA07 — — — I/O Power Domain Direction O — — — O — — — O — — — O — — — O — — — O — — — O — — — O — — — VDD_IO_MEM 14 Pin MA00 MA01 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor MA02 MA03 MA04 MA05 MA06 MA07 Pin Assignments Functions4 Peripheral5 Notes Pin DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — — G20 VDD_IO_MEM — F22 VDD_IO_MEM — F19 VDD_IO_MEM — E22 VDD_IO_MEM — E21 VDD_IO_MEM — F20 VDD_IO_MEM — D22 VDD_IO_MEM — E20 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 ALT2 IO_CONTROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 0x00 0x00 0x00 0x00 0x00 0x00 MA08 — — — MA09 — — — MA10 — — — MA11 — — — MA12 — — — MA13 — — — MA14 — — — MA15/MCS1 — — — I/O Power Domain Direction O — — — O — — — O — — — O — — — O — — — O — — — O — — — O — — — VDD_IO_MEM Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 15 Pin Functions4 Peripheral5 Notes Pin MA08 DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — DRAM — — — — D21 MA09 VDD_IO_MEM — C22 MA10 VDD_IO_MEM — E19 MA11 VDD_IO_MEM — B22 MA12 VDD_IO_MEM — C20 MA13 VDD_IO_MEM — D20 MA14 VDD_IO_MEM — B21 MA15 VDD_IO_MEM — B20 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x00 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 ALT0 ALT1 IO_CONALT2 TROL_MEM ALT3 0x04 STD_PU LPC_OE_B 0x05 STD_PU LPC_RWB 0x06 STD_PU LPC_CS0_B 0x07 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 0x00 0x00 0x00 MCK — — — MCK — — — MCKE — — — MODT — — — LPC_CLK TPA1 — GPIO04 LPC_OE PSC3_3 — GPIO05 LPC_R/W PSC3_4 — GPIO06 LPC_CS0 — — GPIO07 I/O Power Domain Direction O — — — O — — — O — — — O — — — O — I/O O I/O — I/O O I/O — I/O O — — I/O VDD_IO — N2 VDD_IO_MEM 16 Pin MCK MCK MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor MCKE MODT LPC_CLK Pin Assignments Functions4 Peripheral5 Notes Pin DRAM — — — DRAM — — — DRAM — — — DRAM — — — LPC — — GPIO1 LPC PSC3 — GPIO1 LPC PSC3 — GPIO1 LPC — — GPIO1 — H22 VDD_IO_MEM — G22 VDD_IO_MEM — C18 VDD_IO_MEM — J19 VDD_IO — R4 VDD_IO — N3 VDD_IO — M1 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x08 STD_PU LPC_AX03 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x09 STD_PU EMB_AD00 0x2C STD_PU EMB_AD01 0x2B STD_PU EMB_AD02 0x2A STD_PU EMB_AD03 0x29 STD_PU EMB_AD04 0x28 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O O O I/O O O O — I/O — — I/O — — I/O — — I/O — — I/O — — Pin Assignments VDD_IO ALT3: Reset configuration LPC Port Size 1 D5 VDD_IO ALT3: Reset configuration LPC Port Size 0 B3 VDD_IO ALT3: Reset configuration Boot Mode Select B4 VDD_IO ALT3: Reset configuration Boot ROM Location 1 A3 VDD_IO Freescale Semiconductor 17 Pin Functions4 Peripheral5 Notes Pin LPC_ACK_B LPC_ACK/LPC_BURST NFC_CE1 LPC_CS1 GPIO08 LPC_AX03/LPC_TS NFC_CE2 LPC_CS2 — LPC_AD00/NFC_AD00 — RST_CONF_LOC0 — LPC_AD01/NFC_AD01 — RST_CONF_LOC1 — LPC_AD02/NFC_AD02 — RST_CONF_BMS — LPC_AD03/NFC_AD03 — RST_CONF_LPCDBW0 — LPC_AD04/NFC_AD04 — RST_CONF_LPCDBW1 — LPC NFC LPC GPIO1 LPC NFC LPC — LPC — — LPC — — LPC — — LPC — — LPC — — — P3 VDD_IO — L1 VDD_IO ALT3: Reset configuration Boot ROM Location 0 A4 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x27 STD_PU EMB_AD06 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x26 STD_PU EMB_AD07 0x25 STD_PU EMB_AD08 0x24 STD_PU EMB_AD09 0x23 STD_PU EMB_AD10 0x22 STD_PU EMB_AD11 0x21 STD_PU EMB_AD12 0x20 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O — — I/O — — I/O — — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO ALT3: Reset configuration E3 VDD_IO ALT3: Reset configuration C1 VDD_IO ALT3: Reset configuration System PLL Multiplication Factor 2 D2 VDD_IO ALT3: Reset configuration System PLL Multiplication Factor 1 C2 VDD_IO ALT3: Reset configuration System PLL Multiplication Factor 0 E4 VDD_IO ALT3: Reset configuration Core PLL Multiplication Factor 2 C3 VDD_IO ALT3: Reset configuration Core PLL Multiplication Factor 1 C4 VDD_IO 18 Pin EMB_AD05 Freescale Semiconductor Pin Assignments Functions4 Peripheral5 Notes Pin LPC_AD05/NFC_AD05 — RST_CONF_COREPLL6 — LPC_AD06/NFC_AD06 — RST_CONF_COREPLL5 — LPC_AD07/NFC_AD07 — RST_CONF_COREPLL4 — LPC_AD08/NFC_AD08 PSC3_2 RST_CONF_SPMF0 GPIO28 LPC_AD09/NFC_AD09 PSC3_1 RST_CONF_SPMF1 GPIO27 LPC_AD10/NFC_AD10 PSC3_0 RST_CONF_SPMF2 GPIO26 LPC_AD11/NFC_AD11 PSC2_4 RST_CONF_SPMF3 GPIO25 LPC_AD12/NFC_AD12 PSC2_3 RST_CONF_PREDIV0 GPIO24 LPC — — LPC — — LPC — — LPC PSC3 GPIO1 LPC PSC3 GPIO1 LPC PSC3 GPIO1 LPC PSC2 GPIO1 LPC PSC2 GPIO1 ALT3: Reset configuration Core PLL Multiplication Factor 0 B2 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x1F STD_PU EMB_AD14 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x1E STD_PU EMB_AD15 0x1D STD_PU EMB_AD16 0x1C STD_PU EMB_AD17 0x1B STD_PU EMB_AD18 0x1A STD_PU EMB_AD19 0x19 STD_PU EMB_AD20 0x18 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — — I/O — — I/O — — I/O — — I/O — — I/O VDD_IO — H3 Pin Assignments VDD_IO ALT3: Reset configuration J4 VDD_IO ALT3: Reset configuration G2 VDD_IO ALT3: Reset configuration G3 VDD_IO — F3 VDD_IO ALT3: Reset configuration E1 VDD_IO ALT3: Reset configuration H4 VDD_IO Freescale Semiconductor 19 Pin Functions4 Peripheral5 Notes Pin EMB_AD13 LPC_AD13/NFC_AD13 PSC2_2 RST_CONF_PREDIV1 GPIO23 LPC_AD14/NFC_AD14 PSC2_1 RST_CONF_PREDIV2 GPIO22 LPC_AD15/NFC_AD15 PSC2_0 RST_CONF_SYSOSCEN GPIO21 LPC PSC2 GPIO1 LPC PSC2 GPIO1 LPC PSC2 GPIO1 ALT3: Reset configuration E2 LPC_AD16/LPC_A01/NFC_WE LPC — — — — — LPC_AD17/LPC_A02/NFC_RE — RST_CONF_PLL_LOCK — LPC — — LPC_AD18/LPC_A03/NFC_CLE LPC — — RST_CONF_LPCMX — — LPC_AD19/LPC_A04/NFC_ALE LPC — — RST_CONF_LPCWA — — LPC_AD20/LPC_A05 — — GPIO20 LPC GPIO1 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x17 STD_PU EMB_AD22 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x16 STD_PU EMB_AD23 0x15 STD_PU EMB_AD24 0x14 STD_PU EMB_AD25 0x13 STD_PU EMB_AD26 0x12 STD_PU EMB_AD27 0x11 STD_PU EMB_AD28 0x10 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O — — I/O I/O — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O VDD_IO — J3 VDD_IO 20 Pin EMB_AD21 Freescale Semiconductor Pin Assignments Functions4 Peripheral5 Notes Pin LPC_AD21/LPC_A06 — — GPIO19 LPC_AD22/LPC_A07 — RST_CONF_LPC_TS GPIO18 LPC_AD23/LPC_A08 — — GPIO17 LPC_AD24/LPC_A09 — — GPIO16 LPC_AD25/LPC_A10 — — GPIO15 LPC_AD26/LPC_A11 — — GPIO14 LPC_AD27/LPC_A12 — — GPIO13 LPC_AD28/LPC_A13 — — GPIO12 LPC — F1 GPIO1 LPC VDD_IO ALT3: Reset configuration K4 GPIO1 LPC GPIO1 LPC VDD_IO — K3 GPIO1 LPC VDD_IO — G1 GPIO1 LPC VDD_IO — J2 GPIO1 LPC VDD_IO — M4 GPIO1 LPC VDD_IO — H1 GPIO1 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x0F STD_PU EMB_AD30 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x0E ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O — — I/O I/O O — I/O I/O I — I/O O — — — O — O — O O O — O — — I/O I — — I/O VDD_IO Freescale Semiconductor 21 Pin Functions4 Peripheral5 Notes Pin EMB_AD29 LPC_AD29/LPC_A14 — — GPIO11 LPC_AD30/LPC_A15 CAN_CLK — GPIO10 LPC_AD31/LPC_A16 PSC_MCLK_IN — GPIO09 LPC_AX00/LPC_ALE — — — LPC_AX01/LPC_TSIZ0 — LPC_CS4 — LPC_AX02/LPC_TSIZ1 NFC_CE3 LPC_CS3 — NFC_CE0 — — GPIO29 NFC_R/B — — GPIO30 LPC — L3 GPIO1 LPC ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x0C STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 0x0D VDD_IO — M3 GPIO1 LPC EMB_AD31 VDD_IO — J1 GPIO1 LPC — — — LPC — LPC — LPC LPC — NFC — — GPIO1 NFC — — GPIO1 EMB_AX00 VDD_IO — K1 EMB_AX01 0x0B STD_PU VDD_IO — N4 EMB_AX02 0x0A STD_PU VDD_IO — L2 NFC_CE0_B 0x02D STD_PU VDD_IO — P1 NFC_RB ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x02E VDD_IO When booting from the NFC, the NFC_RB pin needs an external pullup resistor. N1 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x02F STD_PU DIU_DE MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x030 STD_PU DIU_HSYNC 0x031 STD_PU DIU_VSYNC 0x032 STD_PU DIU_LD00 0x033 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction O I/O I/O O O I/O I/O O O I/O I/O O I/O I/O I/O I/O I O I/O I/O O O I/O I/O I/O I/O O I/O I/O I/O O VDD_IO — Y11 VDD_IO 22 Pin DIU_CLK ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x034 STD_PU DIU_LD02 Freescale Semiconductor 0x035 STD_PU DIU_LD03 0x036 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 DIU_LD01 Pin Assignments Functions4 Peripheral5 Notes Pin DIU_CLK PSC4_0 USB1_DATA0 LPC_AX04 DIU_DE PSC4_1 USB1_DATA1 LPC_AX05 DIU_HSYNC PSC4_2 USB1_DATA2 LPC_AX06 DIU_VSYNC PSC4_3 USB1_DATA3 GPIO31 CAN3_RX CLK_OUT2 DIU_LD00 GPIO32 CAN3_TX CLK_OUT3 DIU_LD01 GPIO33 DIU_LD02 PSC4_4 USB1_DATA4 LPC_AX07 DIU_LD03 PSC5_0 USB1_DATA5 LPC_AX08 DIU PSC4 USB1 LPC DIU PSC4 USB1 LPC DIU PSC4 USB1 LPC DIU PSC4 USB1 GPIO1 CAN3 DIU DIU GPIO2 CAN3 DIU DIU GPIO2 DIU PSC4 USB1 LPC DIU PSC5 USB1 LPC — AB8 VDD_IO — AA8 VDD_IO — W11 VDD_IO — Y17 VDD_IO — AB9 VDD_IO — Y10 VDD_IO — AA10 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x037 STD_PU DIU_LD05 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x038 STD_PU DIU_LD06 0x039 STD_PU DIU_LD07 0x03A ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O I/O I/O O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I I/O I I/O I/O I/O O I/O I/O I/O I/O I/O O I/O I/O I/O I I/O VDD_IO Freescale Semiconductor 23 Pin Functions4 Peripheral5 Notes Pin DIU_LD04 DIU_LD04 PSC5_1 USB1_DATA6 LPC_AX09 DIU_LD05 PSC5_2 USB1_DATA7 GPIO34 DIU_LD06 PSC5_3 USB1_STOP GPIO35 DIU_LD07 PSC5_4 USB1_CLK GPIO36 CAN4_RX PSC6_0 DIU_LD08 GPIO37 CAN4_TX PSC6_1 DIU_LD09 GPIO38 DIU_LD10 PSC6_2 USB1_NEXT GPIO39 DIU_LD11 PSC6_3 USB1_DIR GPIO40 DIU PSC5 USB1 LPC DIU PSC5 USB1 GPIO2 DIU PSC5 USB1 GPIO2 DIU PSC5 USB1 GPIO2 CAN4 PSC6 DIU GPIO2 CAN4 PSC6 DIU GPIO2 DIU PSC6 USB1 GPIO2 DIU PSC6 USB1 GPIO2 — AA11 VDD_IO — AB10 VDD_IO — AB11 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x03C STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 0x03B VDD_IO — Y12 DIU_LD08 VDD_IO — W13 DIU_LD09 VDD_IO — AB12 DIU_LD10 0x03D STD_PU VDD_IO — Y13 DIU_LD11 0x03E STD_PU VDD_IO — AA13 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x03F STD_PU DIU_LD13 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x040 STD_PU DIU_LD14 0x041 STD_PU DIU_LD15 0x042 STD_PU DIU_LD16 0x043 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO 24 Pin DIU_LD12 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x045 STD_PU DIU_LD19 0x046 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 0x044 DIU_LD17 DIU_LD18 Freescale Semiconductor Pin Assignments Functions4 Peripheral5 Notes Pin DIU_LD12 PSC6_4 USB2_DATA0 GPT2[0] DIU_LD13 PSC7_0 USB2_DATA1 GPT2[1] DIU_LD14 PSC7_1 USB2_DATA2 GPT2[2] DIU_LD15 PSC7_2 USB2_DATA3 GPT2[3] CLK_OUT0 I2C3_SCL DIU_LD16 GPIO41 CLK_OUT1 I2C3_SDA DIU_LD17 GPIO42 DIU_LD18 PSC7_3 USB2_DATA4 GPT2[4] DIU_LD19 PSC7_4 USB2_DATA5 GPT2[5] DIU PSC6 USB2 GPT2 DIU PSC7 USB2 GPT2 DIU PSC7 USB2 GPT2 DIU PSC7 USB2 GPT2 DIU I2C2 DIU GPIO2 DIU I2C3 DIU GPIO2 DIU PSC7 USB2 GPT2 DIU PSC7 USB2 GPT2 — AB13 VDD_IO — W14 VDD_IO — Y14 VDD_IO — AB14 VDD_IO — AA15 VDD_IO — Y15 VDD_IO — AB15 VDD_IO — AB16 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x047 STD_PU DIU_LD21 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x048 STD_PU DIU_LD22 0x049 STD_PU DIU_LD23 0x04A STD_PU I2C2_SCL 0x4B ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I I/O I/O I/O I I/O I/O I/O O I/O I/O I/O I I/O I/O I/O O I/O VDD_IO Freescale Semiconductor 25 Pin Functions4 Peripheral5 Notes Pin DIU_LD20 DIU_LD20 PSC8_0 USB2_DATA6 GPT2[6] DIU_LD21 PSC8_1 USB2_DATA7 GPT2[7] DIU_LD22 PSC8_2 USB2_DIR GPIO43 DIU_LD23 PSC8_3 USB2_NEXT GPIO44 I2C2_SCL PSC8_4 USB2_CLK GPIO45 I2C2_SDA PSC9_4 USB2_STOP GPIO46 I2C1_SCL PSC9_2 CAN3_RX GPIO49 I2C1_SDA PSC9_3 CAN3_TX GPIO50 DIU PSC8 USB2 GPT2 DIU PSC8 USB2 GPT2 DIU PSC8 USB2 GPIO2 DIU PSC8 USB2 GPIO2 I2C2 PSC8 USB2 GPIO2 I2C2 PSC9 USB2 GPIO2 I2C1 PSC9 CAN3 GPIO2 I2C1 PSC9 CAN3 GPIO2 — AB17 VDD_IO — W16 VDD_IO — Y16 VDD_IO — AA17 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x50 0x4F 0x4C VDD_IO — V4 I2C2_SDA VDD_IO — U4 I2C1_SCL VDD_IO — B18 I2C1_SDA VDD_IO — A19 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 CAN1_RX — — — CAN2_RX — — — CAN1_TX PSC9_0 I2C2_SCL GPIO47 CAN2_TX PSC9_1 I2C2_SDA GPIO48 FEC1_TXD_2 PSC2_0 USB2_DATA0 GPIO51 FEC1_TXD_3 PSC2_1 USB2_DATA1 GPIO52 FEC1_RXD_2 PSC2_2 USB2_DATA2 GPIO53 FEC1_RXD_3 PSC2_3 USB2_DATA3 GPIO54 I/O Power Domain Direction I — — — I — — — O I/O I/O I/O O I/O I/O I/O O I/O I/O I/O O I/O I/O I/O I I/O I/O I/O I I/O I/O I/O VBAT 26 Pin CAN1_RX CAN2_RX MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor — CAN1_TX ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 0x4E 0x4D CAN2_TX FEC1_TXD_2 0x51 STD_PU FEC1_TXD_3 0x52 STD_PU FEC1_RXD_2 0x53 STD_PU FEC1_RXD_3 0x54 STD_PU Pin Assignments Functions4 Peripheral5 Notes Pin CAN1 — — — CAN2 — — — CAN1 PSC9 I2C2 GPIO2 CAN2 PSC9 I2C2 GPIO2 FEC1 PSC2 USB2 GPIO2 FEC1 PSC2 USB2 GPIO2 FEC1 PSC2 USB2 GPIO2 FEC1 PSC2 USB2 GPIO2 Dedicated input can be used to receive an external wakeup. Dedicated input can be used to receive an external wakeup. — C9 VBAT B8 VDD_IO B15 VDD_IO — A16 VDD_IO — AA1 VDD_IO — Y1 VDD_IO — Y4 VDD_IO — AA2 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x55 STD_PU FEC1_TX_ER 0x56 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 STD_PU FEC1_RXD_1 0x57 STD_PU FEC1_TXD_1 0x58 STD_PU FEC1_MDC 0x59 STD_PU FEC1_RX_ER 0x5A STD_PU FEC1_MDIO 0x5B ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I I/O I/O I/O I I/O I/O I/O I I/O I/O I/O O I/O I/O I/O I I/O I I/O I I/O I I/O I — I I/O I — O I/O VDD_IO Freescale Semiconductor 27 Pin Functions4 Peripheral5 Notes Pin FEC1_CRS FEC1_CRS PSC2_4 USB2_DATA4 GPIO55 FEC1_TX_ER PSC3_0 USB2_DATA5 GPIO56 FEC1_RXD_1/RMII_RX1 PSC3_1 USB2_DATA6 GPIO57 FEC1_TXD_1/RMII_TX1 PSC3_2 USB2_DATA7 GPIO58 FEC1_MDC/RMII_MDC PSC3_3 USB2_DIR GPIO59 FEC1_RX_ER/RMII_RX_ER PSC3_4 USB2_NEXT GPIO60 FEC1_MDIO/RMII_MDIO — USB2_CLK GPIO61 FEC1_RXD_0/RMII_RX0 — USB2_STOP GPIO62 FEC1 PSC2 USB2 GPIO2 FEC1 PSC3 USB2 GPIO2 FEC1 PSC3 USB2 GPIO2 FEC1 PSC3 USB2 GPIO2 FEC1 PSC3 USB2 GPIO2 FEC1 PSC3 USB2 GPIO2 FEC1 — USB2 GPIO2 FEC1 — USB2 GPIO2 — U1 VDD_IO — W2 VDD_IO — AA3 VDD_IO — W3 VDD_IO — V1 VDD_IO — Y5 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 VDD_IO — V2 FEC1_RXD_0 0x5C STD_PU VDD_IO — AB2 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 I/O Power Domain Direction O — I I/O O I/O — I/O I I/O I I/O I I/O I I/O I I/O — I/O I I/O — I/O I/O I/O I — I/O I/O I — VDD_IO 28 Pin FEC1_TXD_0 0x5D FEC1_TX_CLK 0x5E MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor FEC1_RX_CLK 0x5F ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 FEC1_RX_DV 0x60 FEC1_TX_EN 0x61 STD_PU FEC1_COL 0x62 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 USB1_DATA0 0x63 STD_PU USB1_DATA1 0x64 STD_PU Pin Assignments Functions4 Peripheral5 Notes Pin FEC1_TXD_0/RMII_TX0 — NFC_R/B1 GPIO63 FEC1_TX_CLK/RMII_REF_CLK PSC0_0 — GPIO04 FEC1_RX_CLK PSC0_1 NFC_R/B2 GPIO05 FEC1_RX_DV/RMII_CRS_DV PSC0_2 NFC_R/B3 GPIO06 FEC1_TX_EN/RMII_TX_EN PSC0_3 — GPIO07 FEC1_COL PSC0_4 — GPIO08 USB1_DATA0 PSC1_0 FEC2_RXD_1/RMII_RX1 — USB1_DATA1 PSC1_1 FEC2_TXD_1/RMII_TX1 — FEC1 — NFC GPIO2 FEC1 PSC0 — GPIO1 FEC1 PSC0 — GPIO1 FEC1 PSC0 NFC GPIO1 FEC1 PSC0 — GPIO1 FEC1 PSC0 GPIO1 USB2 PSC1 FEC2 USB2 PSC1 FEC2 — W4 VDD_IO — W1 VDD_IO — AB4 VDD_IO — AB3 VDD_IO — Y3 VDD_IO — U3 VDD_IO — Y9 VDD_IO — W9 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I/O I/O I — I/O I/O I — I/O I/O I/O — I/O I/O I — I/O I/O O — I/O I/O I — O I/O I — I I/O I — VDD_IO Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 29 Pin Functions4 Peripheral5 Notes Pin USB1_DATA2 0x65 STD_PU USB1_DATA3 0x66 STD_PU USB1_DATA4 0x67 STD_PU USB1_DATA5 0x68 STD_PU USB1_DATA6 0x69 STD_PU USB1_DATA7 0x6A USB1_DATA2 PSC1_2 FEC2_MDC/RMII_MDC — USB1_DATA3 PSC1_3 FEC2_RX_ER/RMII_RX_ER — USB1_DATA4 PSC1_4 FEC2_MDIO/RMII_MDIO — USB1_DATA5 PSC4_0 FEC2_RXD_0/RMII_RX0 — USB1_DATA6 PSC4_1 FEC2_TXD_0/RMII_TX0 — USB2 PSC1 FEC2 USB2 PSC1 FEC2 USB2 PSC1 FEC2 USB2 PSC4 FEC2 USB2 PSC4 FEC2 — AB7 VDD_IO — AB6 VDD_IO — AA7 VDD_IO — Y7 VDD_IO — Y6 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x6C 0x6B USB1_DATA7 USB2 PSC4_2 PSC4 FEC2_TX_CLK/RMII_REF_CLK FEC2 — USB1_STOP PSC4_3 FEC2_RX_CLK — USB1_CLK PSC4_4 FEC2_RX_DV/RMII_CRS_DV — USB2 PSC4 FEC2 USB2 PSC4 FEC2 VDD_IO — AB5 USB1_STOP VDD_IO — W6 USB1_CLK VDD_IO — Y8 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x6D STD_PU USB1_DIR MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x6E ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I — I I/O I — I I/O VDD_IO 30 Pin USB1_NEXT ALT0 ALT1 STD_PU_ST ALT2 ALT3 SDHC1_CLK 0x6F STD_PU SDHC1_CMD 0x70 STD_PU SDHC1_D0 0x71 STD_PU SDHC1_D1 0x72 STD_PU SDHC1_D2 Freescale Semiconductor 0x73 STD_PU SDHC1_D3 0x74 STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 Pin Assignments Functions4 Peripheral5 Notes Pin USB1_NEXT — FEC2_TX_EN/RMII_TX_EN GPIO09 USB1_DIR — FEC2_COL GPIO10 USB2 — FEC2 GPIO1 USB2 — FEC2 GPIO1 SDHC — AA5 VDD_IO — W7 SDHC1_CLK NFC_CE1 FEC2_TXD_2 GPIO11 SDHC1_CMD PSC5_0 FEC2_TXD_3 GPIO12 SDHC1_D0 PSC5_1 FEC2_RXD_2 GPIO13 SDHC1_D1_IRQ PSC5_2 FEC2_RXD_3 LPC_CS5 SDHC1_D2 PSC5_3 FEC2_CRS LPC_CS6 SDHC1_D3_CD PSC5_4 FEC2_TX_ER LPC_CS7 SDHC1 NFC FEC2 GPIO1 SDHC1 PSC5 FEC2 GPIO1 SDHC1 PSC5 FEC2 GPIO1 SDHC1 PSC5 FEC2 LPC SDHC1 PSC5 FEC2 LPC SDHC1 PSC5 FEC2 LPC O O O I/O I/O I/O O I/O I/O I/O I I/O I/O I/O I O I/O I/O I O I/O I/O I O VDD_IO — T1 VDD_IO — T2 VDD_IO — T3 VDD_IO — T4 VDD_IO — R1 VDD_IO — R2 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x76 STD_PU PSC0_1 0x77 STD_PU PSC0_2 0x78 STD_PU PSC0_3 0x79 STD_PU PSC0_4 0x7A STD_PU PSC1_0 0x7B STD_PU PSC1_1 0x7C STD_PU ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 I/O Power Domain Direction I — — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O O O O I/O I/O I VDD_IO Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 31 Pin Functions4 Peripheral5 Notes Pin PSC_MCLK_IN 0x75 PSC_MCLK_IN — — GPIO14 PSC0_0 SDHC2_CMD GPT1[0] GPIO15 PSC0_1 SDHC2_D0 GPT1[1] GPIO16 PSC0_2 SDHC2_D1_IRQ GPT1[2] GPIO17 PSC0_3 SDHC2_D2 GPT1[3] GPIO18 PSC0_4 SDHC2_D3_CD GPT1[4] CAN1_TX PSC1_0 SDHC2_CLK GPT1[5] CAN2_TX PSC1_1 CAN_CLK GPT1[6] IRQ0 — D6 — — GPIO1 PSC0 SDHC2 GPT1 GPIO1 PSC0 SDHC2 GPT1 GPIO1 PSC0 SDHC2 GPT1 GPIO1 PSC0 SDHC2 GPT1 GPIO1 PSC0 SDHC2 GPT1 CAN1 PSC1 SDHC2 GPT1 CAN2 PSC1 GPT1 PSC0_0 VDD_IO — C11 VDD_IO — A12 VDD_IO — A13 VDD_IO — B13 VDD_IO — D11 VDD_IO — C12 VDD_IO — C13 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 0x7D STD_PU PSC1_3 MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 0x7E STD_PU PSC1_4 0x7F STD_PU J1850_TX 0x80 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 PSC1_2 TPA2 GPT1[7] IRQ1 PSC1_3 CKSTP_IN NFC_R/B2 GPIO19 PSC1_4 CKSTP_OUT NFC_CE2 GPIO20 J1850_TX — NFC_CE3 I2C1_SCL J1850_RX — NFC_R/B3 I2C1_SDA I/O Power Domain Direction I/O I/O I I/O O I/O I/O O I/O O — O I/O I — O I/O VDD_IO — B5 VDD_IO — A15 VDD_IO — D13 VDD_IO 32 Pin PSC1_2 ALT0 ALT1 STD_PU_ST ALT2 ALT3 ALT0 ALT1 STD_PU_ST ALT2 ALT3 0x81 J1850_RX TCK — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 TCK — — — TDI — — — TDO — — — TDI Freescale Semiconductor — TDO — Pin Assignments Functions4 Peripheral5 Notes Pin PSC1 GPT1 PSC1 NFC GPIO1 PSC1 MFC GPIO1 J1850 — NFC I2C1 J1850 — NFC I2C1 JTAG JTAG — — — JTAG — — — JTAG — — — — B14 VDD_IO — C6 I — — — I — — — O — — — VDD_IO 5. This pin contains an enabled internal Schmitt trigger. 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. — C16 VDD_IO C15 VDD_IO B16 Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 TMS — — — TRST — — — I/O Power Domain Direction I — — — I — — — VDD_IO Freescale Semiconductor MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 33 Pin Functions4 Peripheral5 Notes Pin TMS JTAG — — — JTAG — — — System Control 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. 3. This JTAG pin has an internal pullup P-FET, and cannot be configured. D15 TRST — VDD_IO D16 HRESET — ALT0 ALT1 ALT2 ALT3 HRESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 5. This pin contains an enabled internal schmitt-trigger. A17 PORESET — ALT0 ALT1 ALT2 ALT3 PORESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 2. This pin is an input only. This pin cannot be configured. 5. This pin contains an enabled internal schmitt-trigger. C17 SRESET — ALT0 ALT1 ALT2 ALT3 SRESET — — — — — — I — — — VDD_IO 1. This pin is an input or open-drain output, and have internal pull-up P-FETs. This pin can not be configured. 5. This pin contains an enabled internal schmitt-trigger. A18 Pin Assignments Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Alternate Control Register1 Function3 and Offset2 I/O Power Domain Direction 34 Pin TEST — ALT0 ALT1 ALT2 ALT3 TEST — — — MPC5125 Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor l Pin Assignments Functions4 Peripheral5 Notes Pin Test/Debug — — — I — — — VDD_IO 2. This pin is an input only. D14 This pin cannot be configured. 4. This test pin must be tied to VSS. NOTES: 1 Pins controlled by the STD_PU_ST register have a Schmitt trigger input; pins controlled by the STD_PU register do not. Pins controlled by the IO_CONTROL_MEM register access their alternate function ALT3 by setting the IO_CONTROL_MEM[16BIT] bit. This setting applies to all pins controlled by IO_CONTROL_MEM. Pins not controlled by these registers are indicated with a “—”. 2 Offset from IOCONTROL_BASE (default is 0xFF40_A000). 3 Except where noted in the Notes column, ALT0 is the primary (default) function for each pin after reset. 4 Alternate functions are chosen by setting the values of the STD_PU[FUNCMUX] bitfields inside the I/O Control module. – STD_PU[FUNCMUX] = 00 → ALT0 (default) – STD_PU[FUNCMUX] = 01 → ALT1 – STD_PU[FUNCMUX] = 10 → ALT2 – STD_PU[FUNCMUX] = 11→ ALT3 For selecting alternate functions, the STD_PU and STD_PU_ST registers function the same. When no function is available on a pin’s given ALTn function (value of STD_PU[FUNCMUX] ), it is shown as “—”. 5 Module included on the MCU. Pin Assignments 3.2.1 Power and Ground Supply Summary Table 3. MPC5125 324 TEPBGA Power/Ground Pin Name VDD VDD_IO Function Description Supply voltage — e300 core and peripheral logic Supply voltage — I/O buffers Voltage1 1.4 V 3.3 V Package Pin Locations J10, J11, J12, J13, K14, L9, L14, M9, M14, N14, P10, P11, P12, P13 A14, B9, B12, B17, C5, C14, D3, F2, G4, H2, M2, R3, V3, W5, W15, AA4, AA9, AA12, AA14, AA16, AB18 B19, C21, D17, D19, G19, H21, P19, R21, T19, V19, W19, Y21, AB20 D4 D10 A11 C10 D8 B11 B10 N19 W18 R19 M19 K19 A1, A2, A22, B1, B7, D7, D12, F4, F21, J9, J14, K2, K[9:13], K21, L4, L[10:13], L19, M[10:13], N[9:13], N21, P2, P4, P9, P14, U2, U21, W8, W10, W12, W17, Y2, AA6, AA18, AB1, AB22 VDD_IO_MEM AVDD_FUSEWR AVDD_CPLL AVDD_SPLL AVDD_OSC_TMPS VBAT AVSS_CPLL Supply voltage — memory Power Analog power Analog power Analog power Power Analog ground —2 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 0V 0V —2 —2 —2 —2 —2 0V AVSS_OSC_TMPS_SPLL Analog ground—Double-bonded AVSS_OSC_TMPS and AVSS_SPLL MVREF MVTT0 MVTT1 MVTT2 MVTT3 VSS Analog input —Voltage reference for SSTL input pads Analog input —SSTL(DDR2) termination (ODT) voltage Analog input —SSTL(DDR2) termination (ODT) voltage Analog input —SSTL(DDR2) termination (ODT) voltage Analog input —SSTL(DDR2) termination (ODT) voltage Ground NOTES: 1 Nominal voltages. 2 Dependent on external memory type. See Table 5. NOTE This table indicates only the pins with a permanently enabled internal pullup, pulldown, or Schmitt trigger. Most digital I/O pins can be configured to enable internal pullup, pulldown, or Schmitt trigger. See the MPC5125 Reference Manual (MPC5125RM), “I/O Control” chapter. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 35 Electrical and Thermal Characteristics 4 4.1 4.1.1 Electrical and Thermal Characteristics DC Electrical Characteristics Absolute Maximum Ratings Table 4. Absolute Maximum Ratings1 Characteristic Sym VDD VDD_IO, VDD_IO_MEM MVREF MVTT AVDD_SPLL AVDD_OSC_TMPS AVDD_CPLL VBAT AVDD_FUSEWR Vin Vin Vin Vinos Vinus Tstg Min −0.3 −0.3 − 0.3 − 0.3 −0.3 −0.3 – 0.3 − 0.3 − 0.3 − 0.3 − 0.3 − 0.3 — — − 55 Max 1.47 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 VDD_IO + 0.3 VDD_IO_MEM + 0.3 VBAT + 0.3 1 1 150 Unit V V V V V V V V V V V V V V oC The tables in this section describe the MPC5125 DC electrical characteristics. Table 4 gives the absolute maximum ratings. SpecID D1.1 D1.2 D1.15 D1.16 D1.3 D1.4 D1.5 D1.6 D1.7 D1.9 D1.10 D1.11 D1.12 D1.13 D1.14 Supply voltage — e300 core and peripheral logic Supply voltage — I/O buffers Input reference voltage (DDR/DDR2) Termination Voltage (DDR2) Supply voltage — system APLL Supply voltage — system oscillator and temperature sensor Supply voltage — e300 APLL Supply voltage — RTC (hibernation) Supply voltage — FUSE programming Input voltage (VDD_IO) Input voltage (VDD_IO_MEM) Input voltage (VBAT) Input voltage overshoot Input voltage undershoot Storage temperature range NOTES: 1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage. 4.1.2 Recommended Operating Conditions Table 5. Recommended Operating Conditions Characteristic Sym VDD Min1 1.33 1.08 Typ 1.4 Max1 1.47 Unit V V SpecID D2.1 D2.2 Table 5 gives the recommended operating conditions. Supply voltage — e300 core and peripheral logic State retention voltage — e300 core and peripheral logic 2 — — MPC5125 Microcontroller Data Sheet, Rev. 3 36 Freescale Semiconductor Electrical and Thermal Characteristics Table 5. Recommended Operating Conditions (continued) Characteristic Supply voltage — standard I / O buffers Supply voltage — memory I / O buffers (DDR) Supply voltage — memory I/O buffers (DDR2, LPDDR, Mobile SDR) Supply voltage — memory I/O buffers (SDR) Input reference voltage (DDR/DDR2) Termination voltage (DDR2) Supply voltage — system APLL Supply voltage — system oscillator and temperature sensor Supply voltage — e300 APLL Supply voltage — RTC (hibernation) Supply voltage — FUSE programming Input voltage — standard I/O buffers Input voltage — memory I/O buffers (DDR) Input voltage — memory I/O buffers (DDR2) Input voltage — memory I/O buffers (SDR) Input voltage — memory I/O buffers (LPDDR) Ambient operating temperature range Sym VDD_IO VDD_IO_MEM_DDR VDD_IO_MEM_DDR2 VDD_IO_MEM_LPDDR Min1 3.0 2.3 1.7 3.0 0.49 × VDD_IO_MEM MVREF – 0.04 3.0 3.0 3.0 3.0 3.0 0 0 0 0 0 –40 Typ 3.3 2.5 1.8 3.3 0.50 × VDD_IO_MEM MVREF 3.3 3.3 3.3 3.3 3.3 — — — — — — Max1 3.6 2.7 1.9 3.6 0.51 × VDD_IO_MEM MVREF + 0.04 3.6 3.6 3.6 3.6 3.6 VDD_IO VDD_IO_ MEM_DDR Unit V V V V V V V V V V V V V V V V oC SpecID D2.3 D2.4 D2.5 D2.19 D2.6 D2.7 D2.8 D2.9 D2.10 D2.11 D2.12 D2.14 D2.15 D2.16 D2.20 D2.18 D2.17 VDD_IO_MEM_SDR MVREF MVTT AVDD_SPLL AVDD_OSC_TMPS AVDD_CPLL VBAT 3 AVDD_FUSEWR Vin Vin_DDR Vin_DDR2 Vin_SDR Vin_LPDDR TA VDD_IO_ MEM_DDR2 VDD_IO_ MEM_SDR VDD_IO_ MEM_LPDDR +85 NOTES: 1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. 2 The State Retention voltage can be applied to VDD after the device is placed in deep-sleep mode. 3 VBAT should not be supplied by a battery of voltage less than 3.0 V. 4.1.3 DC Electrical Specifications Table 6. DC Electrical Specifications Table 6 gives the DC electrical characteristics for the MPC5125 at recommended operating conditions. Characteristic Input high voltage Input high voltage Condition Input type = TTL VDD_IO Input type = TTL VDD_IO_MEM_DDR Sym VIH VIH Min 0.51 × VDD_IO MVREF + 0.15 Max — — Unit SpecID V V D3.1 D3.2 MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 37 Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) Characteristic Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input leakage current Condition Input type = TTL VDD_IO_MEM_DDR2 Input type = TTL VDD_IO_MEM_LPDDR Input type = TTL VDD_IO_MEM_SDR Input type = Schmitt VDD_IO SYS_XTALI crystal bypass mode2 mode1 Sym VIH VIH VIH VIH CVIH RVIH VIL VIL VIL VIL VIL VIL CVIL RVIL IIN Min MVREF + 0.125 0.7 × VDD_IO_ MEM_LPDDR Max — — — — — — 0.42 × VDD_IO MVREF – 0.15 MVREF – 0.125 0.3 × VDD_IO_ MEM_LPDDR Unit SpecID V V V V V V V V V V V V V V µA D3.3 D3.4 D3.33 D3.5 D3.6 D3.7 D3.8 D3.9 D3.10 D3.11 D3.34 D3.12 D3.13 D3.14 D3.15 0.7 × VDD_IO_ MEM_SDR 0.65 × VDD_IO Vxtal + 0.4 (VDD_IO / 2) + 0.4 (VBAT / 5) + 0.5 (VBAT / 2) + 0.4 — — — — — — — — −2.5 RTC_XTALI crystal mode3 bypass mode4 Input type = TTL VDD_IO Input type = TTL VDD_IO_MEM_DDR Input type = TTL VDD_IO_MEM_DDR2 Input type = TTL VDD_IO_MEM_LPDDR Input type = TTL VDD_IO_MEM_SDR Input type = Schmitt VDD_IO SYS_XTALI crystal mode bypass mode RTC_XTALI crystal mode bypass mode Vin = 0 or VDD_IO/VDD_IO_MEM_DDR/2 (depending on input type)5 SYS_XTAL_IN Vin = 0 or VDD_IO RTC_XTAL_IN Vin = 0 or VDD_IO PULLUP VDD_IO Vin = VIL PULLDOWN VDD_IO Vin = VIH IOH is driver dependent7 VDD_IO IOH is driver dependent VDD_IO_MEM_DDR 7 0.3 × VDD_IO_ MEM_SDR 0.35 × VDD_IO Vxtal – 0.4 × (VDD_IO/2) – 0.4 (VBAT/5) – 0.5 (VBAT/2) – 0.4 2.5 Input leakage current Input leakage current Input current, pullup resistor6 Input current, pulldown resistor 8 Output high voltage Output high voltage Output high voltage Output high voltage IIN IIN IINpu IINpd VOH VOHDDR VOHDDR2 VOHLPDD R — — 25 25 0.8 × VDD_IO 1.94 VDD_IO_ MEM – 0.28 VDD_IO_ MEM – 0.28 20 1.0 150 150 — — — — µA µA µA µA V V V V D3.16 D3.17 D3.18 D3.19 D3.20 D3.21 D3.22 D3.23 IOH is driver dependent7 VDD_IO_MEM_DDR2 IOH is driver dependent7 VDD_IO_MEM_LPDDR MPC5125 Microcontroller Data Sheet, Rev. 3 38 Freescale Semiconductor Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) Characteristic Output high voltage Output low voltage Output low voltage Output low voltage Output low voltage Output low voltage DC injection current per pin8 Input capacitance (digital pins) Input capacitance (analog pins) On-die termination (DDR2) Condition IOH is driver dependent7 VDD_IO_MEM_SDR IOL is driver dependent7 VDD_IO IOL is driver dependent VDD_IO_MEM_DDR 7 Sym Min Max — 0.2 × VDD_IO 0.36 0.28 0.28 0.2 × VDD_IO_MEM 1.0 7 10 180 Unit SpecID V V V V V V mA pF pF W D3.35 D3.24 D3.25 D3.26 D3.27 D3.36 D3.29 D3.30 D3.31 D3.32 VOHSDR 0.8 × VDD_IO_MEM VOL VOLDDR VOLDDR2 VOLLPDD R — — — — — −1.0 — — 120 IOL is driver dependent7 VDD_IO_MEM_DDR2 IOL is driver dependent7 VDD_IO_MEM_LPDDR IOL is driver dependent7 VDD_IO_MEM_SDR — — — — VOLSDR ICS Cin Cin RODT NOTES: 1 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal – Vxtal ≥ 400 mV criteria has to be met for oscillator’s comparator to produce the output clock. 2 This parameter is meant for those who do not use quartz crystals or resonators, but instead use a signal generator clock to drive the clock in bypass mode. In this case, for the oscillator’s comparator to produce the output clock, drive only the EXTAL pin. Do not connect anything to any other oscillator pin. 3 This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode to drive the clock. In that case, for the oscillator’s comparator to produce the output clock, drive one of the XTAL_IN or XTAL_OUT pins. Do not connect anything to the other oscillator pins. 4 This parameter is meant for those who do not use quartz crystals or resonators, but instead use a signal generator clock to drive the clock in bypass mode. In that case, for the oscillator’s comparator to produce the output clock, drive only the XTAL_IN pin. Do not connect anything to any other oscillator pin. 5 Leakage current is measured with output drivers disabled and with pullups and pulldowns inactive. 6 Pullup current is measured at V and pulldown current is measured at V . IL IH 7 See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 2. 8 All injection current is transferred to V DD_IO/VDD_IO_MEM. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 39 Electrical and Thermal Characteristics Table 7. General I/O Pads1 — Drive Current, Slew Rate Pad Type General IO Supply Voltage VDD_IO = 3.3 V Drive Select/Slew Rate Control Configuration 3 (11) Configuration 2 (10) Configuration 1 (01) Configuration 0 (00) NOTES: 1 General I/O—rise and fall times at drive load 50 pF. 1 Rise time max (ns) 1.4 9.8 19 140 Fall time max (ns) 1.6 12 24 183 Current Current Ioh (mA) Iol (mA) 35 35 SpecID D3.41 D3.42 D3.43 D3.44 Table 8. DDR I/O Pads1 — Drive Current, Slew Rate Supply Voltage Drive Select/ Slew Rate Control Rising slew max (ns)2 0.45 0.8 Falling slew max (ns)3 0.45 0.8 Current Current SpecID Ioh (mA) Iol (mA) 16.2 4.6 8.1 0.7 0.7 5.3 13.4 0.45 0.45 8 16.2 4.6 8.1 5.3 13.4 8 D3.45 D3.46 D3.47 D3.48 D3.49 D3.50 Pad Type DDR VDD_IO_MEM = 2.5 V (DDR) Configuration 3 (011) VDD_IO_MEM = 1.8 V (LPDDR Configuration 0 (000) and SDR) Configuration 1 (001) VDD_IO_MEM = 1.8 V (DDR2) Configuration 2 (010) Configuration 6 (110) VDD_IO_MEM = 3.3 V (SDR) Configuration 7 (111) NOTES: 1 DDR—rise and fall times at 50 Ω transmission line impedance terminated to MV TT (0.5 × VDD_IO_MEM) + 4 pF load. 2 Rising slew rate measured between 0.5 × V – 450 mV and 0.5 × VDD_IO_MEM + 50 mV for all modes. DD_IO_MEM 3 Falling slew rate measured between 0.5 × V DD_IO_MEM + 50 mV and 0.5 × VDD_IO_MEM – 450 mV for all modes. 4.1.4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND or VDD ). Table 11 gives package thermal characteristics for this device. Table 9. ESD and Latch-Up Protection Characteristics Sym VHBM VMM VCDM Rating Human body model (HBM) — JEDEC JESD22-A114-B Machine model (MM) — JEDEC JESD22-A115 Charge device model (CDM) — JEDEC JESD22-C101 Min 2000 200 250 Max — — — Unit V V V SpecID D4.1 D4.2 D4.3 MPC5125 Microcontroller Data Sheet, Rev. 3 40 Freescale Semiconductor Electrical and Thermal Characteristics 4.1.5 • • • Power Dissipation Dissipation of the internal or core digital logic (supplied by VDD) Dissipation of the analog circuitry (supplied by AVDD_SPLL and AVDD_CPLL) Dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO) Power dissipation of the MPC5125 is caused by three different components: Table 10 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins cannot be given in general, but must be calculated for each application case using the following formula: P IO = P IOint + ∑ N × C × VDD _IO M 2 ×f Eqn. 1 where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency, and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5125 device must not exceed this value, which would cause the maximum junction temperature to be exceeded. P total = P core + P analog + P IO Table 10. Power Dissipation Core Power Supply (VDD_core)1 High-Performance Mode e300 = 400 MHz, CSB = 200 MHz Operational2 Doze 3 Eqn. 2 Unit 620 580 235 230 38 RTC Power Supply (VBAT) mW mW mW mW mW SpecID D5.1 D5.3 D5.2 D5.4 D5.5 Nap3 Sleep 3 Deep-sleep4 Hibernation 20 µW D5.6 PLL/OSC Power Supplies (AVDD_SPLL, AVDD_CPLL, AVDD_OSC_TMPS)5 Operational Deep-sleep 18 55 Unloaded I/O Power Supplies (VDD_IO, VDD_IO_MEM)6 VDD_IO Operational Deep-sleep 180 5 VDD_IO_MEM 40 1 mW mW D5.9 D5.10 mW µW D5.7 D5.8 NOTES: 1 Typical core power is measured at V DD_core = 1.4 V, TJ = 25 °C. 2 Operational power is measured while running an entirely cache-resident program with floating-point multiplication instructions in parallel with DDR write operation. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 41 Electrical and Thermal Characteristics 3 Doze, Nap, and Sleep power are measured with the e300 core in Doze/Nap/Sleep mode; the system oscillator, system PLL, and core PLL active; and all other system modules inactive. 4 Deep-sleep power is measured with the e300 core in Sleep mode. The system oscillator, system PLL, core PLL, and other system modules are inactive. 5 PLL power is measured at AVDD_SPLL = AVDD_CPLL = AVDD_OSC_TMPS = 3.3 V, TJ = 25 °C. 6 Unloaded typical I/O power is measured at V DD_IO = 3.3 V, VDD_MEM_IO = 1.8 V, TJ = 25 °C. NOTE The maximum power depends on the supply voltage, process corner, junction temperature, and the concrete application and clock configurations. 4.1.6 Thermal Characteristics Table 11. Thermal Resistance Data1 Rating Conditions Single layer board – 1s Four layer board – 2s2p Sym Value Unit SpecID RθJA RθJA 35 25 29 22 16 11 3 °C/W °C/W °C/W °C/W °C/W °C/W °C/W D6.1 D6.2 D6.3 D6.4 D6.5 D6.6 D6.7 Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-moving-air ambient2 Thermal resistance junction-to-moving-air ambient2 Thermal resistance junction-to-board3 Thermal resistance junction-to-case Junction-to-package-top natural 4 @ 200 ft./min., single layer board – 1s RθJMA @ 200 ft./min., four layer board 2s2p — — Natural convection RθJMA RθJB RθJC ΨJT convection5 NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 4.1.6.1 Heat Dissipation TJ = TA + ( R θJA × PD ) An estimation of the chip-junction temperature, TJ, can be obtained from the following equation: Eqn. 3 where: TA = ambient temperature for the package ( º C ) R θJA = junction to ambient thermal resistance ( º C / W ) PD = power dissipation in package (W) MPC5125 Microcontroller Data Sheet, Rev. 3 42 Freescale Semiconductor Electrical and Thermal Characteristics The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R θJA = R θJC + R θCA where: R θJA = junction to ambient thermal resistance ( º C / W ) R θJC = junction to case thermal resistance ( º C / W ) R θCA = case to ambient thermal resistance ( º C / W ) R θJC is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient thermal resistance, R θCA. For instance, you can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: T J = T T + ( Ψ JT × P D ) where: TT = thermocouple temperature on top of package ( º C ) Ψ JT = thermal characterization parameter ( º C / W ) PD = power dissipation in package ( W ) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. Eqn. 5 Eqn. 4 4.2 Oscillator and PLL Electrical Characteristics The MPC5125 system requires a system-level clock input SYS_XTALI. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent real-time clock (RTC) system. The MPC5125 clock generation uses two phase-locked loop (PLL) blocks. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 43 Electrical and Thermal Characteristics • • The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration. 4.2.1 System Oscillator Electrical Characteristics Table 12. System Oscillator Electrical Characteristics Characteristic Sym fsys_xtal Min 15.6 Typical 33.3 Max 35.0 Unit MHz SpecID O1.1 SYS_XTAL frequency The system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference. t CYCLE t DUTY t DUTY t RISE CV IH SYS_XTAL_I CLK VM VM VM CV IL t FALL Figure 4. Timing Diagram — SYS_XTAL_IN Table 13. SYS_XTAL_IN Timing Sym t CYCLE t RISE t FALL t DUTY SYS_XTALI cycle time1,2 SYS_XTALI rise time3 Description Min 64.1 1 1 )5 40 Max 28.57 4 4 60 Units ns ns ns % SpecID O.1.2 O.1.3 O.1.4 O.1.5 SYS_XTALI fall time4 SYS_XTALI duty cycle ( measured at V M NOTES: 1 The SYS_XTALI frequency and system PLL settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5125 Reference Manual (MPC5125RM). 2 The min/max cycle times are calculated using 1/f sys_xtal (MIN/MAX) where the fsys_xtal (MIN/MAX) (15.6 / 35 MHz) are taken from Table 12 (system oscillator electrical characteristics). 3 Rise time is measured from 20% of VDD to 80% of VDD. 4 Fall time is measured from 20% of VDD to 80% of VDD. 5 SYS_XTALI duty cycle is measured at V M. 4.2.2 RTC Oscillator Electrical Characteristics Table 14. RTC Oscillator Electrical Characteristics Characteristic Sym frtc_xtal Min — Typical 32.768 Max — Unit kHz SpecID O2.1 RTC_XTAL frequency MPC5125 Microcontroller Data Sheet, Rev. 3 44 Freescale Semiconductor Electrical and Thermal Characteristics 4.2.3 System PLL Electrical Characteristics Table 15. System PLL Specifications Characteristic Sym fsys_xtal tjitter fVCOsys fVCOjitterDj fVCOjitterRj tlock1 4 Min 16 — 400 — — — — Typical 33.3 — — — — — — Max 67 10 800 40 12 200 170 Unit MHz ps MHz ps ps µs µs SpecID O3.1 O3.2 O3.3 O3.4 O3.5 O3.6 O3.7 Sys PLL input clock frequency1 Sys PLL input clock jitter 2 Sys PLL VCO frequency1 Sys PLL VCO output jitter (Dj), peak to peak / cycle Sys PLL VCO output jitter (Rj), RMS 1 sigma Sys PLL relock time — after power up 3 Sys PLL relock time — when power was on tlock2 NOTES: 1 The SYS_XTAL frequency and PLL configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 2 This represents total input jitter — short term and long term combined. Two different types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the PLL to the internal clock circuitry. 3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. 4 PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently re-enabled during sleep modes. 4.2.4 e300 Core PLL Electrical Characteristics The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Table 16. e300 PLL Specifications Characteristic e300 frequency1, 2 e300 PLL VCO frequency 1 Sym fcore fVCOcore fCSB_CLK tCSB_CLK tlock Min 200 400 50 5 — Typical — — — — — Max 400 800 200 20 200 Unit MHz MHz MHz ns µs SpecID O4.1 O4.3 O4.4 O4.5 O4.6 e300 PLL input clock frequency e300 PLL input clock cycle time e300 PLL relock time 3 NOTES: 1 The frequency and e300 PLL configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in Table 17. 2 The following hard-coded relationship exists between fcore and fVCOcore: (fcore = fVCOcore). 3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable V DD and CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 45 Electrical and Thermal Characteristics 4.3 4.3.1 • • • • • • • • AC Electrical Characteristics Overview AC Operating Frequency Data Resets SDRAM (DDR) LPC NFC FEC USB ULPI MMC/SD/SDIO Card Host Controller (SDHC) • • • • • • • • DIU CAN I2C J1850 PSC GPIOs and Timers Fusebox IEEE 1149.1 (JTAG) The following list provides hyperlinks to the indicated timing specification sections. AC test timing conditions: Unless otherwise noted, all test conditions are as follows: • • • • TA = –40 to 85 oC VDD = 1.33 to 1.47 V VDD_IO = 3.0 to 3.6 V Input conditions: All inputs: trise, tfall ≤ 1 ns Output Loading: All outputs: 50 pF 4.3.2 AC Operating Frequency Data Table 17. Clock Frequencies Min Max 400 200 200 66 66 50 66 50 66 Units MHz MHz MHz MHz MHz MHz MHz MHz MHZ SpecID A1.1 A1.2 A1.3 A1.4 A1.6 A1.7 A1.8 A1.9 A1.10 Table 17 provides the operating frequency information for the MPC5125. e300 Processor Core SDRAM clock CSB bus clock IP bus clock LPC clock NFC clock DIU clock SDHC clock CLKx NOTES: 200 50 50 8.3 2.08 3.13 0.78 0.78 0.78 MPC5125 Microcontroller Data Sheet, Rev. 3 46 Freescale Semiconductor Electrical and Thermal Characteristics 1. The SYS_XTAL_IN frequency, Sys PLL, and Core PLL settings must be chosen so that the resulting e300 clk, csb_clk, and MCK frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The values are valid for the user-operation mode. There can be deviations for test modes. 3. When selecting the peripheral clock frequencies, care needs to be taken about requirements for baud rates and minimum frequency limitation. 4.The DDR data rate is 2x the DDR memory bus frequency. SYS_XTAL_IN is the input clock multiplied by the system phase-locked loop (Sys PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the clocks for the peripherals.The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word, which is loaded at power-on reset. See the MPC5125 Reference Manual (MPC5125RM), for more information on the clock subsystem. 4.3.3 • • • Resets PORESET — Power-on reset HRESET — Hard reset SRESET — Software reset The MPC5125 has three reset pins: These signals are asynchronous I / O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5125 inputs, as specified in Section 4.1, “DC Electrical Characteristics.” As long as VDD is not stable the HRESET output is not stable. Table 18. Reset Rise / Fall Timing Description PORESET fall time PORESET rise time HRESET 2,3 1 Min — — — — — — Max 1 1 1 1 1 1 Unit ms ms ms ms ms ms SpecID A3.4 A3.5 A3.6 A3.7 A3.8 A3.9 fall time HRESET rise time SRESET fall time SRESET rise time NOTES: 1 Make sure that the PORESET does not carry any glitches. The MPC5125 has no filter to prevent them from getting into the chip. 2 HRESET and SRESET must have a monotonous rise time. 3 The assertion of HRESET becomes active at power-on reset without any SYS_XTAL clock. The timing relationship can be seen in the following figures. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 47 Electrical and Thermal Characteristics XTALI CLOCK PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF RST_CONF[31:0] ADDR[31:0] tH_POR_CONF tEXEC Figure 5. Power-Up Behavior XTALI CLOCK tPORHold PORESET tHRVAL HRESET tSRVAL SRESET tS_POR_CONF RST_CONF[31:0] ADDR[31:0] tH_POR_CONF tEXEC Figure 6. Power-On Reset Behavior MPC5125 Microcontroller Data Sheet, Rev. 3 48 Freescale Semiconductor Electrical and Thermal Characteristics XTALI CLOCK PORESET tHRHOLD tHRVAL HRESET tSRVAL SRESET tHR_SR_Delay RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF tEXEC Figure 7. HRESET Behavior XTALI CLOCK PORESET HRESET tSRHOLD tSRMIN SRESET tEXEC RST_CONF[31:0] ADDR[31:0] no new fetch of the RST_CONF Figure 8. SRESET Behavior Table 19. Reset Timing Symbol tPORHOLD tHRVAL tSRVAL tEXEC tS_POR_CONF Description Time PORESET must be held low before a qualified reset occurs. Time HRESET is asserted after a qualified reset occurs. Time SRESET is asserted after assertion of HRESET. Time between SRESET assertion and first core instruction fetch. Reset configuration setup time before assertion of PORESET. Value (XTALI CLOCK) 4 cycles 26810 cycles1 SpecID A3.10 A3.11 A3.12 A3.13 A3.14 21 cycles 4 cycles 1 cycle MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 49 Electrical and Thermal Characteristics Table 19. Reset Timing (continued) Symbol tH_POR_CONF tHR_SR_DELAY tHRHOLD tSRHOLD tSRMIN Description Reset configuration hold time after assertion of PORESET. Time from falling edge of HRESET to falling edge of SRESET. Time HRESET must be held low before a qualified reset occurs. Time SRESET must be held low before a qualified reset occurs. Time SRESET is asserted after it has been qualified. Value (XTALI CLOCK) 1 cycle 4 cycles 4 cycles 4 cycles 1 cycles SpecID A3.15 A3.16 A3.17 A3.18 A3.19 NOTES: 1 The timings will change when using the PLL lock detection circuit. 4.3.4 • • • External Interrupts IRQ interrupts GPIO interrupts with simple interrupt capability (not available in power-down mode) Wakeup interrupts Table 20. IPIC Input AC Timing Specifications Descriptions IPIC inputs — minimum pulse width Symbol tPICWID Min 2T Unit ns Spec ID A4.1 The MPC5125 provides three different kinds of external interrupts: IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge-triggered mode. 4.3.5 • • • • • • • • • SDRAM (DDR) DDR-1 (SSTL_2 class II interface) DDR-2 (SSTL_18 interface) LPDDR (1.8V I/O supply voltage) SDR D-RAM JEDEC standard, DDR2 SDRAM specification, JESD79-2C, May 2006 JEDEC standard, Double Data Rate (DDR) SDRAM specification, JESD79E, May 2005 JEDEC standard, Low Power Double Data Rate (LPDDR) SDRAM specification, JESD79-4, May 2006 Full drive strength Half drive strength (intended for lighter loads or point-to-point environments) The MPC5125 memory controller supports these types of DDR devices: JEDEC standards define the minimum set of requirements for compliant memory devices: The MPC5125 supports the configuration of two output drive strengths for DDR2 and LPDDR: The MPC5125 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device. This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in Section 4.1, “DC Electrical Characteristics.” MPC5125 Microcontroller Data Sheet, Rev. 3 50 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.5.1 DDR SDRAM AC Timing Specifications Table 21. DDR SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of ±5% Parameter Symbol tCK VOX-AC tCH tCL tDQSS tOS(base) tOH(base) tDS1(base) tDH1(base) tDQSQ tDQSEN Min 6000 Max — Unit Notes SpecID ps V tCK tCK tCK ps ps ps ps ps 1 1,3 1,3 2,3 2,3 Clock cycle time, CL = x MCK AC differential crosspoint voltage CK HIGH pulse width CK LOW pulse width Skew between MCK and DQS transitions Address and control output setup time relative to MCK rising edge Address and control output hold time relative to MCK rising edge DQ and DM output setup time relative to DQS DQ and DM output hold time relative to DQS DQS-DQ skew for DQS and associated DQ inputs DQS window position related to CAS read command A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7 A5.8 A5.9 A5.10 A5.11 (VDD_IO_MEM × 0.5)– 0.15 (VDD_IO_MEM × 0.5) + 0.15 0.47 0.47 −0.25 tCK/2 – 1000 tCK/2 – 1000 tCK/4 – 750 tCK/4 – 750 – (tCK/4 – 600) 2tCK + 1500 0.53 0.53 0.25 — — — — tCK/4 – 600 3tCK – 1000 2,3 2,3 2,3 3 ps 1,2,3,4, 5 NOTES: 1 Measured with clock pin loaded with differential 100 Ω termination resistor. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to V DD_IO_MEM/2. 3 All transitions measured at mid-supply (V /2). DD_IO_MEM 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5 The window position is given for t DQSEN = 2.0 tCK (RDLY = 2, HALF DQS DLY = QUART DQS DLY = 0) with CL = 3 DDR SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. 4.3.5.2 MobileDDR/LPDDR SDRAM AC Timing Specifications Table 22. MobileDDR/LPDDR SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of ±5% Parameter Symbol tCK VOX-AC tCH tCL tDQSS tOS(base) Min 6000 Max — Unit Notes SpecID ps V tCK tCK tCK ps 1 1,3 1,3 2,3 Clock cycle time, CL = x MCK AC differential crosspoint voltage CK HIGH pulse width CK LOW pulse width Skew between MCK and DQS transitions Address and control output setup time relative to MCK rising edge A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 (VDD_IO_MEM × 0.5) – 0.1 (VDD_IO_MEM × 0.5) + 0.1 0.47 0.47 −0.25 tCK/2 – 1000 0.53 0.53 0.25 — 2,3 MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 51 Electrical and Thermal Characteristics Table 22. MobileDDR/LPDDR SDRAM Timing Specifications (continued) At recommended operating conditions with VDD_IO_MEM of ±5% Parameter Address and control output hold time relative to MCK rising edge Symbol tOH(base) Min tCK/2 – 1000 tCK/4 – 750 tCK/4 – 750 – (tCK/4 – 600) 2tCK – 500 Max — — — tCK/4 – 600 3tCK – 1000 Unit Notes SpecID ps ps ps ps 2,3 A5.7 A5.8 A5.9 A5.10 DQ and DM output setup time relative to tDS1(base) DQS DQ and DM output hold time relative to DQS DQS-DQ skew for DQS and associated DQ inputs DQS window position related to CAS read command tDH1(base) tDQSQ tDQSEN 2,3 2,3 3 ps 1,2,3,4,5 A5.11 NOTES: 1 Measured with clock pin loaded with differential 100 Ω termination resistor. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to V DD_IO_MEM/2. 3 All transitions measured at mid-supply (V /2). DD_IO_MEM 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5 The window position is given for t DQSEN = 2.0 tCK (RDLY = 2, HALF DQS DLY = QUART DQS DLY = 0) with CL = 3 MobileDDR/LPDDR SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. 4.3.5.3 DDR2 SDRAM AC Timing Specifications Table 23. DDR2 (DDR2-400) SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of ±5% Parameter Symbol tCK VOX-AC tCH tCL tDQSS tOS(base) tOH(base) Min 5000 Max — Unit Notes SpecID ps V tCK tCK tCK ps ps ps ps ps ps 1 1,3 1,3 2,3 2,3 Clock cycle time, CL = x MCK AC differential crosspoint voltage CK HIGH pulse width CK LOW pulse width Skew between MCK and DQS transitions Address and control output setup time relative to MCK rising edge Address and control output hold time relative to MCK rising edge A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7 A5.8 A5.9 A5.10 A5.11 (VDD_IO_MEM × 0.5) – 0.1 (VDD_IO_MEM × 0.5) + 0.1 0.47 0.47 −0.25 tCK/2 − 750 tCK/2 − 750 tCK/4 − 500 tCK/4 − 500 – (tCK/4 – 600) 2.5tCK 0.53 0.53 0.25 — — — — tCK/4 − 600 3tCK + 1500 2,3 DQ and DM output setup time relative to tDS1(base) DQS DQ and DM output hold time relative to DQS DQS-DQ skew for DQS and associated DQ inputs DQS window position related to CAS read command tDH1(base) tDQSQ tDQSEN 2,3 2,3 3 1,2,3,4, 5 MPC5125 Microcontroller Data Sheet, Rev. 3 52 Freescale Semiconductor Electrical and Thermal Characteristics NOTES: 1 Measured with clock pin loaded with differential 100 Ω termination resistor. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to VDD_IO_MEM/2. 3 All transitions measured at mid-supply (VDD_IO_MEM/2). 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. 5 The window position is given for tDQSEN = 2.5 tCK (RDLY = 2, HALF DQS DLY = 1, QUART DQS DLY = 0) with CL = 3 DDR2 SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. 4.3.5.4 SDR SDRAM AC Timing Specifications Table 24. SDR SDRAM Timing Specifications At recommended operating conditions with VDD_IO_MEM of ±5% Parameter Symbol tCK tCH tCL Min 7500 0.43 0.43 tCK/2 – 1000 tCK/2 – 1000 1000 1000 Max — 0.57 0.57 — — — — Unit Notes SpecID ps tCK tCK ps ps ps ps 1,3 1,3 2,3 Clock cycle time, CL = x CK HIGH pulse width CK LOW pulse width A5.1 A5.3 A5.4 A5.6 A5.7 A5.15 A5.16 Address, control, and data output setup time relative tOS(base) to MCK rising edge Address, control, and data output hold time relative to tOH(base) MCK rising edge Input data set-up time, relative to MCK Input data hold time, relative to MCK tIS tIH 2,3 3 3 NOTES: 1 Measured with clock pin loaded with 50 Ω termination resistor to mid-supply. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to V DD_IO_MEM/2. 3 All transitions measured at mid-supply (V DD_IO_MEM/2). NOTE To achieve better timing, balance the loading of DQS as MCK although DQS is not used in SDR mode. Figure 9 shows the DDR SDRAM write timing. tCH MCK tCK DQS tDQSS DQ, DM(out) tDS tDH tCL Figure 9. DDR Write Timing MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 53 Electrical and Thermal Characteristics Figure 10 and Figure 11 show the DDR SDRAM read timing. DQS(in) Any DQ(in) tDQSQ tDQSQ Figure 10. DDR Read Timing, DQ vs DQS MCK Command Address tOS DQS(in) tDQSEN (MIN) tDQSEN (MAX) tOH Figure 11. DDR Read Timing, DQSEN Figure 12 shows the SDR AC timing. MCK Output tOS Input tOH tIS tIH Figure 12. SDR AC Timing Figure 13 provides the AC test load for the DDR bus. Output Z0 = 50 Ω RL= 50 Ω VDD_IO_MEM / 2 Figure 13. DDR AC Test Load MPC5125 Microcontroller Data Sheet, Rev. 3 54 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.6 LPC The local-plus bus is the external bus interface of the MPC5125. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed and MUXed. The reference clock is the LPC CLK. The maximum bus frequency is 66 MHz. Definition of terms: WS = Wait state DC = Dead cycle HC = Hold cycle DS = Data size in bytes BBT =Burst bytes per transfer AL = Address latch enable length ALT = Chip select/Address Latch Timing tLPCck = LPC clock period Table 25. LPC Timing Sym Description Min 0 Max 5 Units SpecID ns A7.1 tOD CS[x], ADDR, R/W, TSIZ, DATA (wr), TS, OE valid after LPC CLK (Output delay related to LPC CLK) t1 t2 t3 t4 t5 t6 t7 t8 t9 Non-burst CS[x] pulse width ADDR, R/W, TSIZ, DATA (wr) valid before CS[x] assertion OE assertion after CS[x] assertion ADDR, R/W, TSIZ, data (wr) hold after CS[x] negation TS pulse width DATA (rd) setup before LPC CLK DATA (rd) input hold Read burst CS[x] pulse width Burst ACK pulse width (2 + WS) × tLPCck tLPCck − tOD tLPCck − tOD tLPCck − tOD tLPCck 5 0 (2 + WS + BBT/DS) × tLPCck (BBT/DS) × tLPCck 0 (2+WS) × tLPCck 0.5 × tLPCck – tOD (2.5 + WS) × tLPCck – tOD tLPCck – tOD 0.5 × tLPCck – tOD AL × 2 × tLPCck – tOD AL × tLPCck (2 + WS) × tLPCck tLPCck + tOD tLPCck + tOD (HC + 1) × tLPCck + tOD tLPCck — (DC + 1) × tLPCck (2 +WS + BBT/DS) × tLPCck (BBT/DS) × tLPCck — (2+WS) × tLPCck (HC + 0.5) × tLPCck + tOD (2.5 + WS) × tLPCck + tOD — 0.5 × tLPCck + tOD AL × 2 × tLPCck AL × tLPCck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns A7.2 A7.3 A7.4 A7.5 A7.6 A7.7 A7.8 A7.9 A7.10 A7.11 A7.12 A7.13 A7.14 A7.15 A7.16 A7.17 A7.18 A7.19 t10 Burst DATA (rd) input hold t11 Read burst ACK assertion after CS[x] assertion t12 Non-MUXed write burst CS[x] pulse width t13 Write burst ADDR, R/W, TSIZ, DATA (wr) hold after CS[x] negation t14 Write burst ACK assertion after CS[x] assertion t15 Write burst DATA valid t16 Non-MUXed mode: asynchronous write burst ADDR valid before write DATA valid t17 MUXed mode: ADDR cycle t18 MUXed mode: ALE cycle (2.5 + WS + BBT/DS) × tLPCck (2.5 + WS + BBT/DS) × tLPCck MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 55 Electrical and Thermal Characteristics Table 25. LPC Timing (continued) Sym Description Min tLPCck – tOD tOD + t6 0 (ALT × (AL × 2) + WS) × tLPCck (ALT × (AL × 2) + WS) + BBT/DS) × tLPCck (ALT × (AL × 2) + 2.5 WS) + BBT/DS)× tLPCck Max tLPCck — — (ALT × (AL × 2) + WS) × tLPCck (ALT × (AL × 2) + WS) + BBT/DS) × tLPCck (ALT × (AL × 2) + 2.5 WS) + BBT/DS)× tLPCck Units SpecID ns ns ns ns ns ns A7.20 A7.21 A7.22 A7.23 A7.23 A7.23 t19 Non-MUXed mode page burst: ADDR cycle t20 Non-MUXed mode page burst: burst DATA (rd) input setup before next ADDR cycle t21 Non-MUXed mode page burst: burst DATA (rd) input hold after next ADDR cycle t22 MUXed mode: non-burst CS[x] pulse width t23 MUXed mode: read-burst CS[x] pulse width t24 MUXed mode: write-burst CS[x] pulse width 4.3.6.1 4.3.6.1.1 Non-MUXed Mode Non-MUXed Non-Burst Mode tLPCck LPC CLK t1 CS [ x] ADDR t2 OE R/W DATA (wr) t6 DATA (rd) t7 t3 t4 ACK t5 TS TSIZ[1:0] Figure 14. Timing Diagram — Non-MUXed non-Burst Mode MPC5125 Microcontroller Data Sheet, Rev. 3 56 Freescale Semiconductor Electrical and Thermal Characteristics NOTE ACK is asynchronous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. 4.3.6.1.2 LPC_CLK Non-MUXed Synchronous Read Burst Mode t8 CS [ x] ADDR t5 TS t3 OE R/W DATA (rd) t11 ACK t9 t6 t10 t7 t2 Valid Address t4 Figure 15. Timing Diagram — Non-MUXed Synchronous Read Burst Mode 4.3.6.1.3 LPC_CLK CS [ x] ADDR Non-MUXed Synchronous Write Burst Mode t12 t2 Valid Address t5 TS R/W t15 t15 t13 DATA (wr) t9 ACK t14 Figure 16. Timing Diagram — Non-MUXed Synchronous Write Burst MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 57 Electrical and Thermal Characteristics 4.3.6.1.4 Non-MUXed Asynchronous Read Burst Mode (Page Mode) t8 CS [ x] t2 Valid Address (Page address) t19 t4 LPC_CLK ADDR[31:n+1] ADDR[n:0] t5 TS t3 OE R/W Valid Address Valid Address t20 t6 t21 t10 t7 DATA (rd) t11 ACK t9 Figure 17. Timing Diagram — Non-MUXed Asynchronous Read Burst 4.3.6.1.5 Non-MUXed Asynchronous Write Burst Mode t12 t2 Valid Address (Page address) t13 LPC_CLK CS [ x] ADDR[31:n+1] ADDR[n:0] t5 TS R/W Valid Address Valid Address t16 t15 DATA (wr) t9 ACK t14 t15 Figure 18. Timing Diagram — Non-MUXed Asynchronous Write Burst MPC5125 Microcontroller Data Sheet, Rev. 3 58 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.6.2 4.3.6.2.1 MUXed Mode MUXed Non-Burst Mode LPC_CLK t17 AD[31:0] (wr) Address Valid Write Data t6 AD[31:0] (rd) Address t4 R/W t18 ALE t5 TS t22 CS[x] t3 OE t7 ACK TSIZ[1:0] Figure 19. Timing Diagram — MUXed non-Burst Mode NOTE ACK is asynchronous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 59 Electrical and Thermal Characteristics 4.3.6.2.2 MUXed Synchronous Read Burst Mode t6 t10 t7 LPC_CLK t17 AD[31:0] (rd) Address t18 ALE t5 TS CS[x] t3 OE t23 R/W t11 t9 ACK Figure 20. Timing Diagram — MUXed Synchronous Read Burst 4.3.6.2.3 MUXed Synchronous Write Burst Mode LPC_CLK t17 AD[31:0] (wr) Address t18 ALE t5 TS CS[x] R/W t14 ACK t9 t24 t15 t15 t13 Figure 21. Timing Diagram — MUXed Synchronous Write Burst MPC5125 Microcontroller Data Sheet, Rev. 3 60 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.7 NFC The NAND flash controller (NFC) implements the interface to standard NAND flash memory devices. This section describes the timing parameters of the NFC. TH is the flash clock high time, TL is flash clock low time, where TH = 5 × NFC_RATIO_H / 8 (ns) TL = 5 × NFC_RATIO_L / 8 (ns) Eqn. 6 Eqn. 7 Refer to the MPC5125 Reference Manual (MPC5125RM) for more information about NFC_RATIO_H and NFC_RATIO_L. Table 26. NFC Target Timing Characteristics Timing Parameter tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tIS Description NFC_CLE setup time NFC_CLE hold time NFC_CE[3:0] setup time NFC_CE[3:0] hold time NFC_WP pulse width NFC_ALE setup time NFC_ALE hold time Data setup time Data hold time Write cycle time NFC_WE hold time Ready to NFC_RE low NFC_RE pulse width READ cycle time NFC_RE high hold time Data input setup time Min. value 2TH + TL – 1 TH + TL – 1 2TH + TL – 1 TH + TL TL – 1 2TH + TL TH + TL TL – 1 TH – 1 TH + TL – 1 TH – 1 4TH + 3TL + 90 TL + 1 TL + TH – 1 TH – 1 6 Max. value — — — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SpecID A8.1 A8.2 A8.3 A8.4 A8.5 A8.6 A8.7 A8.8 A8.9 A8.10 A8.11 A8.12 A8.13 A8.14 A8.15 A8.16 MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 61 Electrical and Thermal Characteristics NFC_CLE tCLS tCS tCLH tCH NFC_CE[3:0] tWP NFC_WE NFIO[7:0] command tDS tDH Figure 22. Command Latch Cycle Timing NFC_ALE tALS tCS tALH tCH NFC_CE[3:0] tWP NFC_WE NFIO[7:0] address tDS tDH Figure 23. Address Latch Cycle Timing tCS NFC_CE[3:0] tWP NFC_WE tWH tWC tCH NFIO[15:0] tDS data tDH data data Figure 24. Write Data Latch Timing MPC5125 Microcontroller Data Sheet, Rev. 3 62 Freescale Semiconductor Electrical and Thermal Characteristics tRC NFC_CE[3:0] tRP NFC_RE tREH tCH NFIO[15:0] tRR NFC_RB data tIS data data Figure 25. Read Data Latch Timing in Non-Fast Mode tRC NFC_CE[3:0] tRP NFC_RE tREH tCH NFIO[15:0] tRR NFC_RB data tIS data data Figure 26. Read Data Latch Timing in Fast Mode 4.3.8 • FEC Output Loading All Outputs: 25 pF Table 27. MII Rx Signal Timing AC test timing conditions: Sym t1 t2 t3 t4 Description RXD [ 3 : 0 ], RX_DV, RX_ER to RX_CLK setup RX_CLK to RXD [ 3 : 0 ], RX_DV, RX_ER hold RX_CLK pulse width high RX_CLK pulse width low Min 5 5 35% 35% Max — — 65% 65% Unit ns ns RX_CLK period1 RX_CLK period1 SpecID A11.1 A11.2 A11.3 A11.4 NOTES: 1 RX_CLK shall have a frequency of 25% of the data rate of the received signal. See the IEEE 802.3 specification. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 63 Electrical and Thermal Characteristics Table 28. RMII Rx Signal Timing Sym t5 t6 t7 t8 Description RXD [ 1 : 0 ], RX_DV, RX_ER to TX_CLK setup TX_CLK to RXD [ 1 : 0 ], RX_DV, RX_ER hold TX_CLK pulse width high TX_CLK pulse width low Min 4 2 35% 35% Max — — 65% 65% Unit ns ns TX_CLK period TX_CLK period 1 1 SpecID A11.5 A11.6 A11.7 A11.8 NOTES: 1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification. t3, t7 REF_CLK (Input) t4, t8 RXD[3:0] (inputs) RX_DV RX_ER t1. t5 t2. t6 REF_CLK is TX_CLK in RMII mode, and is RX_CLK in non-RMII mode Figure 27. Ethernet Timing Diagram — MII and RMII Rx Signal Table 29. MII Tx Signal Timing Sym t9 t10 t11 t12 Description TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER invalid TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width low Min 3 — 35% 35% Max — 25 65% 65% Unit ns ns TX_CLK TX_CLK Period1 Period1 SpecID A11.9 A11.10 A11.11 A11.12 NOTES: 1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, for example, a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 specification. Table 30. RMII Tx Signal Timing Sym t13 t14 t15 t16 Description TX_CLK rising edge to TXD [ 1 : 0 ], TX_EN, TX_ER invalid TX_CLK rising edge to TXD [ 1 : 0 ], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width low Min 3 — 35% 35% Max — 14 65% 65% Unit ns ns TX_CLK Period1 SpecID A11.13 A11.14 A11.15 A11.16 TX_CLK Period1 NOTES: 1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification. MPC5125 Microcontroller Data Sheet, Rev. 3 64 Freescale Semiconductor Electrical and Thermal Characteristics t11, t15 TX_CLK (Input) t9, t13 TXD[3:0] (Outputs) TX_EN TX_ER t10, t14 t12, t16 Figure 28. Ethernet Timing Diagram — MII Tx Signal Table 31. MII Async Signal Timing Sym t17 Description CRS, COL minimum pulse width Min 1.5 Max — Unit TX_CLK Period SpecID A11.17 CRS, COL t17 Figure 29. Ethernet Timing Diagram — MII Async Table 32. MII Serial Management Channel Signal Timing Sym t18 t19 t20 t21 t22 t23 Description MDC falling edge to MDIO output delay MDIO ( input ) to MDC rising edge setup MDIO ( input ) to MDC rising edge hold MDC pulse width MDC pulse width MDC period2 high1 low1 Min 0 10 0 160 160 400 Max 25 — — — — — Unit ns ns ns ns ns ns SpecID A11.18 A11.19 A11.20 A11.21 A11.22 A11.23 NOTES: 1 MDC is generated by the MPC5125 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5125 Reference Manual (MPC5125RM). 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5125 Reference Manual (MPC5125RM). MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 65 Electrical and Thermal Characteristics t21 t22 MDC (Output) t23 t18 MDIO (Output) MDIO (Input) t19 t20 Figure 30. Ethernet Timing Diagram — MII Serial Management 4.3.9 USB ULPI This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004. Clock TSC Control Out (stp) TSD Data Out (8-bit) TDC Control In (dir,nxt) TDD Data In (8-bit) TDC THD THC Figure 31. ULPI Timing Diagram Table 33. Timing Specifications — USB Output Line 1 Sym TCK Clock period Description Min 15 — 0.0 — Max — 6.0 — 9.0 Units ns ns ns ns SpecID A12.1 A12.2 A12.3 A12.4 TSC, TSD Setup time (control in, 8-bit data in) THC, THD Hold time (control in, 8-bit data in) TDC, TDD Output delay (control out, 8-bit data out) MPC5125 Microcontroller Data Sheet, Rev. 3 66 Freescale Semiconductor Electrical and Thermal Characteristics NOTES: 1 Output timing is specified at a nominal 50 pF load. 4.3.10 MMC/SD/SDIO Card Host Controller (SDHC) SD4 SD2 SD5 MMCx_CLK SD3 MMCx_CMD MMCx_DAT_0 Output from SDHC to card MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD6 MMCx_CMD MMCx_DAT_0 Input from card to SDHC MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 SD7 SD8 SD1 Figure 32 depicts the timings of the SDHC. Figure 32. SDHC Timing Diagram Table 34 lists the timing parameters. . Table 34. MMC/SD Interface Timing Parameters ID Parameter Symbols Card Input Clock SD1 Clock frequency (low speed) Clock frequency (SD/SDIO full speed/high speed) Clock frequency (MMC full speed/high speed) Clock frequency (identification mode) SD2 SD3 SD4 SD5 Clock low time (full speed/high speed) Clock high time (full speed/high speed) Clock rise time (full speed/high speed) Clock fall time (full speed/high speed) fPP1 fPP2 fPP3 fOD4 tWL tWH tTLH tTHL TH – 3 5 0 0 0 100 10/7 10/7 10/3 10/3 400 25/50 20/52 400 kHz MHz MHz kHz ns ns ns ns A14.1 A14.2 A14.3 A14.4 A14.5 A14.6 A14.7 A14.8 Min Max Unit SpecID SDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SDHC output delay tOD TH + 3 ns A14.9 SDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD7 SD8 SDHC input setup time SDHC input hold time tISU tIH 2.5 2.5 ns ns A14.10 A14.11 MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 67 Electrical and Thermal Characteristics NOTES: 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0–20 MHz. 4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V. 5 Suggested Clock Period = T, CLK_DIVIDER (in SDHC Clock Rate register) = D, then TH = [(D + 1)/2] / (D + 1) × T where [] is round. 4.3.11 DIU The DIU is a display controller designed to manage the TFT LCD display. 4.3.11.1 Interface to TFT LCD Panels, Functional Description Figure 33 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: • • • • DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, DIU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type. DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse. DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse. DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. DIU_VSYNC DIU_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n DIU_HSYNC DIU_DE 1 DIU_CLK DIU_LD[23:0] 2 3 m-1 m Figure 33. Interface Timing Diagram for TFT LCD Panels 4.3.11.2 Interface to TFT LCD Panels, Electrical Characteristics Figure 34 depicts the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal (meaning the data and sync signals change at its rising edge) and active-high polarity of the DIU_HSYNC, DIU_VSYNC, and DIU_DE signal. Signal polarity of DIU_HSYNC and DIU_VSYNC are selectable via the SYN_POL register, whether active-high or active-low. The default is active-high. The DIU_DE signal is always active-high. Also, pixel clock inversion and a flexible programmable pixel clock delay are also supported, programmed via the DIU Clock Config register (DCCR) in the system clock module. MPC5125 Microcontroller Data Sheet, Rev. 3 68 Freescale Semiconductor Electrical and Thermal Characteristics tHSP Start of line tPWH tPCP DIU_CLK tBPH tSW tFPH DIU_LD[23:0] Invalid Data 1 1 2 3 DELTA_X Invalid Data DIU_HSYNC DIU_DE Figure 34. TFT LCD Interface Timing Diagram — Horizontal Sync Pulse Figure 35 depicts the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown in the diagram are programmable. tVSP Start of Frame tPWV tHSP tBPV tSH tFPV DIU_HSYNC DIU_LD[23:0] (Line Data) Invalid Data 1 1 2 3 DELTA_Y Invalid Data DIU_VSYNC DIU_DE Figure 35. TFT LCD Interface Timing Diagram — Vertical Sync Pulse Table 35 shows timing parameters of signals. Table 35. LCD Interface Timing Parameters — Pixel Level Sym tPCP tPWH tBPH Description Display Pixel Clock Period HSYNC Pulse Width HSYNC Back Porch Width 151 PW_H × tPCP BP_H × tPCP Value ns ns ns Unit SpecID A15.1 A15.2 A15.3 MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 69 Electrical and Thermal Characteristics Table 35. LCD Interface Timing Parameters — Pixel Level Sym tFPH tSW tHSP tPWV tBPV tFPV tSH tVSP Description HSYNC Front Porch Width Screen Width HSYNC (Line) Period VSYNC Pulse Width VSYNC Back Porch Width VSYNC Front Porch Width Screen Height VSYNC (Frame) Period FP_H × tPCP DELTA_X × tPCP (PW_H + BP_H + DELTA_X + FP_H) × tPCP PW_V × tHSP BP_V × tHSP FP_V × tHSP DELTA_Y × tHSP (PW_V + BP_V + DELTA_Y + FP_H) × tHSP Value ns ns ns ns ns ns ns ns Unit SpecID A15.4 A15.5 A15.6 A15.7 A15.8 A15.9 A15.10 A15.11 NOTES: 1 Display interface pixel clock period immediate value (in nanoseconds). The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H parameters are programmed via the HSYN_PARA register; and the PW_V, BP_V, and FP_V parameters are programmed via the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions of these parameters. Figure 36 depicts the synchronous display interface timing for access level, and Table 36 lists the timing parameters. tCHD DIU_HSYNC DIU_VSYNC DIU_DE tCSU DIU_CLK tCKH tCKL tDHD tDSU DIU_LD[23:0] Figure 36. LCD Interface Timing Diagram — Access Level Table 36. LCD Interface Timing Parameters — Access Level Parameter tCKH tCKL tDSU tDHD tCSU tCHD Description LCD interface pixel clock high time LCD interface pixel clock low time LCD interface data setup time LCD interface data hold time LCD interface control signal setup time LCD interface control signal hold time Min tPCP × 0.4 tPCP × 0.4 5.0 6.0 5.0 6.0 Typ tPCP × 0.5 tPCP × 0.5 — — — — Max tPCP × 0.6 tPCP × 0.6 — — — — Unit ns ns ns ns ns ns SpecID A15.12 A15.13 A15.14 A15.15 A15.16 A15.17 MPC5125 Microcontroller Data Sheet, Rev. 3 70 Freescale Semiconductor Electrical and Thermal Characteristics 4.3.12 CAN The CAN functions are available as TX pins at normal IO pads and as RX pins at the VBAT domain. There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup, if configured. 4.3.13 I2C Table 37. I2C Input Timing Specifications — SCL and SDA This section specifies the timing parameters of the inter-integrated circuit (I2C) interface. Refer to the I2C bus specification. Sym 1 2 4 6 7 8 9 Start condition hold time Clock low time Data hold time Clock high time Data setup time Description Min 2 8 0.0 4 0.0 2 2 Max — — — — — — — Units IP bus cycle1 IP bus cycle ns IP bus cycle1 ns IP bus cycle1 1 1 SpecID A18.1 A18.2 A18.3 A18.4 A18.5 A18.6 A18.7 Start condition setup time ( for repeated start condition only ) Stop condition setup time IP bus cycle NOTES: 1 Inter-peripheral clock is defined in the MPC5125 Reference Manual (MPC5125RM) Table 38. I2C Output Timing Specifications — SCL and SDA 1 Sym 12 22 3 4 4 2 Description Start condition hold time Clock low time SCL / SDA rise time Data hold time SCL / SDA fall time Clock high time Data setup time Start condition setup time ( for repeated start condition only ) Stop condition setup time Min 6 10 — 7 — 10 2 20 10 Max — — 7.9 — 7.9 — — — — Units IP bus cycle3 IP bus cycle3 ns IP bus cycle3 SpecID A18.8 A18.9 A18.10 A18.11 A18.12 A18.13 A18.14 A18.15 A18.16 52 62 7 2 ns IP bus cycle3 IP bus IP bus cycle3 cycle3 82 92 IP bus cycle3 NOTES: 1 Output timing is specified at a nominal 50 pF load. 2 Programming IFDR with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time that SCL or SDA takes to reach a high level depends on external signal capacitance and pullup resistor values. 4 Inter -peripheral Clock is defined in the MPC5125 Reference Manual (MPC5125RM). MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 71 Electrical and Thermal Characteristics 2 SCL 6 5 1 4 7 8 3 9 SDA Figure 37. Timing Diagram — I2C Input / Output 4.3.14 J1850 See the MPC5125 Reference Manual (MPC5125RM). 4.3.15 PSC The programmable serial controllers (PSC) support different modes of operation (UART, codec, AC97, SPI). All the timing numbers specified for different PSC modes are design targets. 4.3.15.1 Codec Mode (8-, 16-, 24-, and 32-Bit) / I2S Mode Table 39. Timing Specifications — 8-, 16-, 24-, and 32-Bit CODEC/I2S Master Mode1 Sym 1 2 3 4 5 6 7 8 Description Bit clock cycle time, programmed in CCS register Clock duty cycle Bit clock fall time Bit clock rise time FrameSync valid after clock edge FrameSync invalid after clock edge Output data valid after clock edge Input data setup time Min 40.0 45 — — — — — 6.0 Typ — 50 — — — — — — Max — 55 7.9 7.9 8.4 8.4 9.3 — Units ns %2 ns ns ns ns ns ns SpecID A20.1 A20.2 A20.3 A20.4 A20.5 A20.6 A20.7 A20.8 NOTES: 1 Output timing is specified at a nominal 50 pF load. 2 Bit clock cycle time. MPC5125 Microcontroller Data Sheet, Rev. 3 72 Freescale Semiconductor Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Output BitClk (CLKPOL=1) Output 5 FrameSync (SyncPol= 1) Output FrameSync (SyncPol= 0) Output 7 TxD Output 8 RxD Input 3 2 2 4 4 3 6 Figure 38. Timing Diagram — 8-,16-, 24-, and 32-bit CODEC/I2S Master Mode Table 40. Timing Specifications — 8-,16-, 24-, and 32-bit CODEC/I2S Slave Mode 1 Sym 1 2 3 4 5 6 Bit clock cycle time Clock duty cycle Frame sync setup time Output data valid after clock edge Input data setup time Input data hold time Description Min 40.0 — 1.0 — 1.0 1.0 Typ — 50 — — — — Max — — — 14.0 — — Units ns %2 ns ns ns ns SpecID A20.9 A20.10 A20.11 A20.12 A20.13 A20.14 NOTES: 1 Output timing is specified at a nominal 50 pF load. 2 Bit clock cycle time. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 73 Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input BitClk (CLKPOL=1) Input 2 2 3 FrameSync (SyncPol= 1) Input FrameSync (SyncPol= 0) Input 4 TxD Output 5 RxD Input 6 Figure 39. Timing Diagram — 8-,16-, 24-, and 32-bit CODEC/I2S Slave Mode 4.3.15.2 AC97 Mode Table 41. Timing Specifications — AC97 Mode 1 Sym 1 2 3 4 5 6 7 Bit clock cycle time Clock pulse high time Clock pulse low time Description Min — — — — — 1.0 1.0 Typ 81.4 40.7 40.7 — — — — Max — — — 13.0 14.0 — — Units ns ns ns ns ns ns ns SpecID A20.15 A20.16 A20.17 A20.18 A20.19 A20.20 A20.21 Frame sync valid after rising clock edge Output data valid after rising clock edge Input data setup time Input data hold time NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 3 74 Freescale Semiconductor Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input FrameSync (SyncPol= 1) Output Sdata_out Output 3 4 2 5 6 Sdata_in Input 7 Figure 40. Timing Diagram — AC97 Mode 4.3.15.3 SPI Mode Table 42. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) 1 Sym 1 2 3 4 5 6 7 8 9 10 11 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programable in the PSC CCS register Output data valid after slave select (SS) Output data valid after SCK Input data setup time Input data hold time Slave disable lag time Sequential transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time Min 30.0 15.0 30.0 — — 6.0 1.0 — 15.0 — — Max — — — 8.9 8.9 — — TSCK — 7.9 7.9 Units ns ns ns ns ns ns ns ns ns ns ns SpecID A20.26 A20.27 A20.28 A20.29 A20.30 A20.31 A20.32 A20.33 A20.34 A20.35 A20.36 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 75 Electrical and Thermal Characteristics 1 10 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 11 2 2 11 10 8 9 4 MOSI Output 6 MISO Input 5 6 7 7 Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 43. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) 1 Sym 1 2 3 4 5 6 7 8 9 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Input data setup time Input data hold time Output data valid after SS Output data valid after SCK Slave disable lag time Minimum sequential transfer delay = 2 × IP bus clock cycle time Min 30.0 15.0 1.0 1.0 1.0 — — 0.0 30.0 Max — — — — — 14.0 14.0 — — Units ns ns ns ns ns ns ns ns — SpecID A20.37 A20.38 A20.39 A20.40 A20.41 A20.42 A20.43 A20.44 A20.45 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 3 76 Freescale Semiconductor Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 2 2 8 9 4 MOSI Input 6 MISO Output 7 5 Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 44. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) 1 Sym 1 2 3 4 5 6 7 8 9 10 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programmable in the PSC CCS register Output data valid Input data setup time Input data hold time Slave disable lag time Sequential transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time Min 30.0 15.0 30.0 — 6.0 1.0 — 15.0 — — Max — — — 8.9 — — TSCK — 7.9 7.9 Units SpecID ns ns ns ns ns ns ns ns ns ns A20.46 A20.47 A20.48 A20.49 A20.50 A20.51 A20.52 A20.53 A20.54 A20.55 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 77 Electrical and Thermal Characteristics 1 9 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 10 2 2 10 9 7 8 4 MOSI Output 5 MISO Input 6 Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 45. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) 1 Sym 1 2 3 4 5 6 7 8 Description SCK cycle time, programmable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Output data valid Input data setup time Input data hold time Slave disable lag time Minimum sequential transfer delay = 2 × IP bus clock cycle time Min 30.0 15.0 0.0 — 2.0 1.0 0.0 30.0 Max — — — 14.0 — — — — Units ns ns ns ns ns ns ns ns SpecID A20.56 A20.57 A20.58 A20.59 A20.60 A20.61 A20.62 A20.63 NOTES: 1 Output timing is specified at a nominal 50 pF load. MPC5125 Microcontroller Data Sheet, Rev. 3 78 Freescale Semiconductor Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 2 2 7 8 5 MOSI Input 4 MISO Output 6 Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 4.3.16 GPIOs and Timers The MPC5125 contains several sets of I/Os that do not require special setup, hold, or valid requirements. The external events (GPIO or timer inputs) are asynchronous to the system clock. The inputs must be valid for at least tIOWID to ensure proper capture by the internal IP clock. Table 46. GPIO/Timers Input AC Timing Specifications Symbol tIOWID Description GPIO/Timers inputs — minimum pulse width Min 2T1 Unit ns SpecID A21.1 NOTES: 1 T is the IP bus clock cycle. T = 15 ns is the minimum value (for the maximum IP bus frequency of 66 MHz). 4.3.17 Fusebox Table 47. Fusebox Timing Characteristics Table 47 gives the Fusebox timing specification. Sym tFUSEWR Program time1 for fuse Description Min 62.5 — Max — 10 Units μs mA SpecID A22.1 A22.2 IFUSEWR Program current to program one fuse bit NOTES: 1 The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 79 Electrical and Thermal Characteristics 4.3.18 Sym — 1 2 3 4 5 6 7 8 9 10 11 12 13 IEEE 1149.1 (JTAG) Table 48. JTAG Timing Specification Characteristic TCK frequency of operation TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TRST setup time to TCK falling edge TRST assert time Input data setup time Input data hold time2 TCK to output data valid 3 3 2 1 Min 0 40 1.08 0 10 5 5 15 0 0 5 4.5 0 0 Max 25 — — 3 — — — — 30 30 — — 15 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns SpecID A23.1 A23.2 A23.3 A23.4 A23.5 A23.6 A23.7 A23.8 A23.9 A23.10 A23.11 A23.12 A23.13 A23.14 TCK to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance NOTES: 1 TRST is an asynchronous signal. The setup time is for test purposes only. 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK. 1 2 2 TCK VM VM VM 3 3 VM = Midpoint Voltage Numbers shown reference JTAG Timing Specification T Figure 45. Timing Diagram — JTAG Clock Input MPC5125 Microcontroller Data Sheet, Rev. 3 80 Freescale Semiconductor Electrical and Thermal Characteristics TCK 4 TRST 5 Numbers shown reference JTAG Timing Specification Table Figure 46. Timing Diagram — JTAG TRST TCK 6 Data Inputs 8 Output Data Valid 9 Data Outputs Numbers shown reference JTAG Timing Specification Table 7 Input Data Valid Data Outputs Figure 47. Timing Diagram — JTAG Boundary Scan TCK 10 TDI, TMS 12 Output Data Valid 13 TDO Numbers shown reference JTAG Timing Specification Table 11 Input Data Valid TDO Figure 48. Timing Diagram — Test Access Port MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 81 System Design Information 5 5.1 System Design Information Power Up/Down Sequencing Power sequencing between the 1.4 V power supply VDD and the remaining supplies is required to prevent excessive current during power-up phase. The required power sequence is as follows: • • • • • Use 12 V/ms or slower time for all supplies. Power up VDD_IO, AVDD_PLLs, VBAT (if not applied permanently), and VDD_IO_MEM supplies first in any order, and then power up VDD. If required AVDD_FUSEWR should be powered up afterwards. All the supplies must reach the specified operating conditions before the PORESET can be released. For power down, drop AVDD_FUSEWR to 0 V first, drop VDD to 0 V, and then drop all other supplies. VDD should not exceed VDD_IO, VDD_IO_MEM, VBAT, or AVDD_PLLs by more than 0.4 V at any time, including power-up. 5.2 System and CPU Core AVDD Power Supply Filtering Each of the independent PLL power supplies require filtering external to the device. Figure 49 shows a recommendation for the required filter circuit. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. All traces should be as low impedance as possible, especially ground pins to the ground plane. The filter for system/core PLLVDD to VSS should be connected to the power and ground planes, respectively, not fingers of the planes. In addition to keeping the filter components for system/core PLLVDD as close as practical to the body of the MPC5125 as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise onto the portion of that supply between the filter and the MPC5125. The capacitors for C2 in the figure below should be rated X5R or better due to temperature performance. It is recommended to add a bypass capacitance of at least 1 µF for the VBAT pin. R1= 10 Ω Power supply source C1= 1 µF C2= 0.1 µF AVDD device pin Figure 49. Power Supply Filtering 5.3 Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD and VSS pins of the MPC5125. The unused AVDD_FUSEWR power should be connected to VSS directly or via a resistor. For DDR or LPDDR modes, the unused pins VTT[3:0] for DDR2 termination voltage can be unconnected. MPC5125 Microcontroller Data Sheet, Rev. 3 82 Freescale Semiconductor System Design Information 5.4 Pullup/Pulldown Resistor Requirements The MPC5125 requires external pullup or pulldown resistors on certain pins. 5.4.1 Pulldown Resistor Requirements for TEST Pin The MPC5125 requires a pulldown resistor on the test pin TEST. 5.5 JTAG The MPC5125 has an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a common on-chip processor (COP) interface, which shares the IEEE 1149.1 JTAG port. The COP interface provides access to the MPC5125’s embedded e300 processor and to other on-chip resources. This interface provides a means for executing test routines and for performing software development and debug functions. 5.5.1 JTAG_TRST Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted during power-on reset. 5.5.1.1 TRST and PORESET The JTAG interface can control the direction of the MPC5125 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5125 comes out of power-on reset; do this by asserting TRST before PORESET is released. For more details, see the Reset and JTAG Timing Specification. PORESET Required assertion of TRST Optional assertion of TRST TRST Figure 50. PORESET vs. TRST 5.5.2 e300 COP / BDM Interface There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector. 5.5.2.1 Boards Interfacing the JTAG Port via a COP Connector The MPC5125 functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale standard COP / BDM interface. Table 49 gives the COP / BDM interface signals. The pin order shown reflects only the COP / BDM connector order. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 83 System Design Information Table 49. COP / BDM Interface Signals BDM Pin # 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 See I / O Pin — CKSTP_OUT — HRESET — SRESET — TMS CKSTP_IN TCK — Note3 BDM Connector GND ckstp_out KEY hreset GND sreset N/C tms ckstp_in tck VDD 2 halted trst tdi qack4 tdo 3 Internal External Pullup / Pulldown Pullup / Pulldown — — — Pullup — Pullup — Pullup — Pullup — — Pullup Pullup — — — 10 kΩ Pullup — 10 kΩ Pullup — 10 kΩ Pullup — 10 kΩ Pullup 10 kΩ Pullup 10 kΩ Pullup — — 10 kΩ Pullup 10 kΩ Pullup — — I/O1 — I — O — O — O O O — I O O O I TRST TDI See Notepci_frame TDO NOTES: 1 With respect to the emulator tool’s perspective: Input is really an output from the embedded e300 core. Output is really an input to the core. 2 From the board under test, power sense for chip power. 3 HALTED is not available from e300 core. For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG module, it is not recommended to wire only TRST and PORESET. To reset the MPC5125 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5125. The circuitry shown in Figure 51 allows the COP to assert HRESET or TRST separately, while any other board sources can drive PORESET. MPC5125 Microcontroller Data Sheet, Rev. 3 84 Freescale Semiconductor System Design Information PORESET COP Header 13 11 16 COP Connector Physical Pinout 1 3 5 7 9 11 13 15 2 4 6 8 7 10 12 K 16 15 6 (2) 1 3 HRESET SRESET 10 kΩ 10 kΩ TRST PORESET HRESET VDD_IO VDD_IO SRESET VDD_IO 4 14 9 12 TCK VDD_IO TDO TDI 10 kΩ 10 kΩ VDD_IO TCK TDO VDD_IO TDI CKSTP_OUT 10 k Ω VDD_IO 10 k Ω CKSTP_OUT VDD_IO CKSTP_IN NC NC NC TMS 10 k Ω VDD_IO TMS 10 kΩ TRST 8 5 (3) 2 (4) 10 CKSTP_IN halted qack Figure 51. COP Connector Diagram 5.5.2.2 Boards Without COP Connector If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal (PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 52 shows the connection of the JTAG interface without COP connector. MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 85 System Design Information PORESET HRESET SRESET 10 kΩ 10 kΩ PORESET HRESET VDD_IO VDD_IO SRESET TRST 10 kΩ VDD_IO JTAG_TMS 10 kΩ VDD_IO TCK 10 kΩ VDD_IO TDI CKSTP_OUT TDO Figure 52. TRST Wiring for Boards without COP Connector MPC5125 Microcontroller Data Sheet, Rev. 3 86 Freescale Semiconductor Package Information 6 Package Information This section details package parameters and dimensions. The MPC5125 is available in a thermally enhanced plastic ball grid array (TEPBGA). Section 6.1, “Package Parameters,” and Section 6.2, “Mechanical Dimensions,” provide information on the TEPBGA. 6.1 Package Parameters Table 50. TEPBGA Parameters Package outline Interconnects Pitch Module height (typical) Solder balls Ball diameter (typical) 23 mm × 23 mm 324 1.00 mm 2.25 mm 96.5 Sn/3.5Ag (VN package) 0.6 mm MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 87 Package Information 6.2 Mechanical Dimensions Figure 3 shows the mechanical dimensions and bottom surface nomenclature of the MPC5125 324 TEPBGA package. Figure 53. Mechanical Drawing of MPC5125 PBGA (1 of 3) MPC5125 Microcontroller Data Sheet, Rev. 3 88 Freescale Semiconductor Package Information Figure 54. Mechanical Drawing of MPC5125 PBGA (2 of 3) MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 89 Package Information Figure 55. Mechanical Drawing of MPC5125 PBGA (3 of 3) MPC5125 Microcontroller Data Sheet, Rev. 3 90 Freescale Semiconductor Product Documentation 7 Product Documentation This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com . The following documents are required for a complete description of the device and are necessary to design properly with the parts: • • MPC5125 Microprocessor Reference Manual (document number MPC5125RM) MPC5125 (0M01S) Errata (document number MSE5125_0M01S) 8 Revision History Table 51. Revision History Revision 1 2 Date October 2008 October 2009 Description Initial public release, NDA required, Advance Information. Public release, Technical Data. — Updated specifications according to characterized data. — Updated Table 1, orderable part numbers. — Updated Table 2, pin multiplexing. — Editorial updates. Table 51 describes the changes made to this document between revisions. 3 November 2009 Public release, Technical Data. — Corrected part number. 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