MPC5200B

Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5200BDS Rev. 3, 10/2008 MPC5200B Data Sheet Key features are shown below. • MPC603e series e300 core – Superscalar architecture – 760 MIPS at 400 MHz (-40 to +85 oC) – 16 K-byte Instruction cache, 16 K-byte Data cache – Double precision FPU – Instruction and Data MMU – Standard and Critical interrupt capability • SDRAM / DDR Memory Interface – up to 133-MHz operation – SDRAM and DDR SDRAM support – 256-MByte addressing range per CS, two CS available – 32-bit data bus – Built-in initialization and refresh • Flexible multi-function External Bus Interface – Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices – 8 programmable Chip Selects – Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address – Short or Long Burst capable – Multiplexed data access using 8/16/32 bit databus with up to 25-bit address • Peripheral Component Interconnect (PCI) Controller – Version 2.2 PCI compatibility – PCI initiator and target operation – 32-bit PCI Address/Data bus – 33- and 66-MHz operation – PCI arbitration function • ATA Controller – Version 4 ATA compatible external interface—IDE Disk Drive connectivity • BestComm DMA subsystem – Intelligent virtual DMA Controller – Dedicated DMA channels to control peripheral reception and transmission – Local memory (SRAM 16 kBytes) • 6 Programmable Serial Controllers (PSC) – UART or RS232 interface – CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97 TEPBGA–272 27 mm x 27 mm • • • • • • • • • • • • – Full duplex SPI mode – IrDA mode from 2400 bps to 4 Mbps Fast Ethernet Controller (FEC) – Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface Universal Serial Bus Controller (USB) – USB Revision 1.1 Host – Open Host Controller Interface (OHCI) – Integrated USB Hub, with two ports. Two Inter-Integrated Circuit Interfaces (I2C) Serial Peripheral Interface (SPI) Dual CAN 2.0 A/B Controller (MSCAN) – Implementation of version 2.0A/B CAN protocol – Standard and extended data frames J1850 Byte Data Link Controller (BDLC) J1850 Class B data communication network interface compatible and ISO compatible for low speed ( LB = 1 Data bus width is 8 bit. => DS = 8 => 41*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line. Wait State is set to 10. => WS = 10 1+10+32 = 43 => CS is asserted for 43 PCI cycles. 3. ACK is output and indicates the burst. 4. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration happens the bus can be driven within 4 IPB clocks by an other modules. PCI CLK CS [x] ADDR t4 OE R/W DATA (rd) t11 ACK t14 TS t15 t13 t9 t12 t6 t8 t10 t5 t7 t2 t1 t3 Figure 12. Timing Diagram—Burst Mode MPC5200B Data Sheet, Rev. 3 26 Freescale Semiconductor 1.3.8.3 MUXed Mode Table 26. MUXed Mode Timing Sym t CSA t CSN tALEA t1 t2 t3 t4 t5 t6 t7 tTSA t8 t9 tOEA tOEN t10 t11 t12 t13 t14 t15 t16 Description PCI CLK to CS assertion PCI CLK to CS negation PCI CLK to ALE assertion ALE assertion before Address, Bank, TSIZ assertion CS assertion before Address, Bank, TSIZ negation CS assertion before Data wr valid Data wr hold after CS negation Data rd setup before CS negation Data rd hold after CS negation ALE pulse width CS assertion after TS assertion TS pulse width CS pulse width OE assertion before CS assertion OE negation before CS negation RW assertion before ALE assertion RW negation after CS negation ACK assertion after CS assertion ACK negation after CS negation ALE negation to CS assertion ACK change before PCI clock ACK change after PCI clock Min 4.6 2.9 tIPBIck 8.5 0 (2+WS)*tPCIck tIPBIck tIPBIck Max 10.6 7.0 3.6 5.7 -1.2 -1.2 (DC+1)*tPCIck tPCIck 6.9 tPCIck (2+WS)*tPCIck 4.7 5.9 tPCIck tPCIck tPCIck 2.0 4.4 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (2) (2) (2) (2) (1),(3) Notes SpecID A7.39 A7.40 A7.41 A7.42 A7.43 A7.44 A7.45 A7.46 A7.47 A7.48 A7.49 A7.50 A7.51 A7.52 A7.53 A7.54 A7.55 A7.56 A7.57 A7.58 A7.59 A7.60 NOTES: 1. ACK can shorten the CS pulse width. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from 0 65535. 2. ACK is input and can be used to shorten the CS pulse width. 3. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration happens the bus can be driven within 4 IPB clocks by an other modules. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 27 PCI CLK t1 AD[31,27] (wr) AD[30:28] (wr) AD[26:25] (wr) AD[24:0] (wr) TSIZ[0:2] bits Bank[0:1] bits Address[7:31] t3 AD[31:0] (rd) t7 ALE Address latch TS t9 CSx OE t10 R/W t16 ACK t12 t15 Address tenure Data tenure t13 t11 t8 t14 t2 Data Data Data Data t5 t6 Data t4 Figure 13. Timing Diagram—MUXed Mode 1.3.9 ATA The MPC5200B ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units (nanoseconds). ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5200B User Manual. The MPC5200B ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes. • • Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that required by the ATA-4 specification. Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that required by the ATA-4 specification. MPC5200B Data Sheet, Rev. 3 28 Freescale Semiconductor All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive. Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates. Adequate data transfer rates are a function of the following: • The MPC5200B operating frequency (IP bus clock frequency) • Internal MPC5200B bus latencies • Other system load dependent variables The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User Manual. NOTE All output timing numbers are specified for nominal 50 pF loads. Table 27. PIO Mode Timing Specifications Sym t0 t1 t2 t2i t3 t4 t5 t6 t9 tA tB PIO Timing Parameter Cycle Time Address valid to DIOR/DIOW setup DIOR/DIOW pulse width 16-bit 8-bit DIOR/DIOW recovery time DIOW data setup DIOW data hold DIOR data setup DIOR data hold DIOR/DIOW to address valid hold IORDY setup IORDY pulse width Min/Max (ns) min min min min min min min min min min max max Mode 0 (ns) 600 70 165 290 — 60 30 50 5 20 35 1250 Mode 1 (ns) 383 50 125 290 — 45 20 35 5 15 35 1250 Mode 2 (ns) 240 30 100 290 — 30 15 20 5 10 35 1250 Mode 3 (ns) 180 30 80 80 70 30 10 20 5 10 35 1250 Mode 4 (ns) 120 25 70 70 25 20 10 20 5 10 35 1250 SpecID A8.1 A8.2 A8.3 A8.4 A8.5 A8.6 A8.7 A8.8 A8.9 A8.10 A8.11 MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 29 CS[0]/CS[3]/DA[2:0] t2 DIOR/DIOW t1 t0 t9 t3 WDATA t5 RDATA t4 t6 tA IORDY tB Figure 14. PIO Mode Timing Table 28. Multiword DMA Timing Specifications Sym t0 tC tD tE tG tF tH tI tJ tKr tKw tLr tLw Multiword DMA Timing Parameters Cycle Time DMACK to DMARQ delay DIOR/DIOW pulse width (16-bit) DIOR data access DIOR/DIOW data setup DIOR data hold DIOW data hold DMACK to DIOR/DIOW setup DIOR/DIOW to DMACK hold DIOR negated pulse width DIOW negated pulse width DIOR to DMARQ delay DIOW to DMARQ delay Min/Max min max min max min min min min min min min max max Mode 0(ns) 480 — 215 150 100 5 20 0 20 50 215 120 40 Mode 1(ns) 150 — 80 60 30 5 15 0 5 50 50 40 40 Mode 2(ns) 120 — 70 50 20 5 10 0 5 25 25 35 35 SpecID A8.12 A8.13 A8.14 A8.15 A8.16 A8.17 A8.18 A8.19 A8.20 A8.21 A8.22 A8.23 A8.24 MPC5200B Data Sheet, Rev. 3 30 Freescale Semiconductor t0 DMARQ (Drive) tC DMACK (Host) tI DIOR DIOW (Host) tE RDATA (Drive) tF WDATA (Host) tG tH tD tK tJ tL Figure 15. Multiword DMA Timing NOTE The direction of signal assertion is towards the top of the page, and the direction of negation is towards the bottom of the page, irrespective of the electrical properties of the signal. Table 29. Ultra DMA Timing Specification MODE 0 (ns) Min t CYC t 2CYC 114 235 Max — — MODE 1 (ns) Min 75 156 Max — — MODE 2 (ns) Min 55 117 Max — — Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge Two-cycle time allowing for clock variations, from rising edge to next rising edge or from falling edge to next falling edge of STROBE. Data setup time at recipient. Data hold time at recipient. Data valid setup time at sender, to STROBE edge. Data valid hold time at sender, from STROBE edge. First STROBE time for drive to first negate DSTROBE from STOP during a data-in burst. Limited Interlock time. Interlock time with minimum. Unlimited interlock time. A8.26 A8.27 Sym Comment SpecID t DS t DH t DVS t DVH t FS t LI t MLI t UI 15 5 70 6 0 0 20 0 — — — — 230 150 — — 10 5 48 6 0 0 20 0 — — — — 200 150 — — 7 5 34 6 0 0 20 0 — — — — 170 150 — — A8.28 A8.29 A8.30 A8.31 A8.32 A8.33 A8.34 A8.35 MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 31 Table 29. Ultra DMA Timing Specification (continued) MODE 0 (ns) Min t AZ t ZAH t ZAD t ENV t SR — 20 0 20 — Max 10 — — 70 50 MODE 1 (ns) Min — 20 0 20 — Max 10 — — 70 30 MODE 2 (ns) Min — 20 0 20 — Max 10 — — 70 20 Maximum time allowed for output drivers to release from being asserted or negated Minimum delay time required for output drivers to assert or negate from released state Envelope time—from DMACK to STOP and HDMARDY during data out burst initiation. STROBE to DMARDY time, if DMARDY is negated before this long after STROBE edge, the recipient receives no more than one additional data word. Ready-to-Final STROBE time—no STROBE edges are sent this long after negation of DMARDY. Ready-to-Pause time—the time recipient waits to initiate pause after negating DMARDY. Pull-up time before allowing IORDY to be released. Minimum time drive waits before driving IORDY Setup and hold times for DMACK, before assertion or negation. Time from STROBE edge to negation of DMARQ or assertion of STOP, when sender terminates a burst. A8.36 A8.37 A8.38 A8.39 A8.40 Sym Comment SpecID t RFS t RP t IORDYZ t ZIORDY t ACK t SS — 160 — 0 20 50 75 — 20 — — — — 125 — 0 20 50 60 — 20 — — — — 100 — 0 20 50 50 — 20 — — — A8.41 A8.42 A8.43 A8.44 A8.45 A8.46 NOTES: 1 t UI, t MLI, t LI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (sender or recipient) is waiting for the other agent to respond with a signal before proceeding. • t UI is an unlimited interlock that has no maximum time value. • t MLI is a limited time-out that has a defined minimum. • t LI is a limited time-out that has a defined maximum. 2 All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender shall stop generating STROBE edges t RFS after negation of DMARDY. STROBE and DMARDY timing measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at 1.5 V. MPC5200B Data Sheet, Rev. 3 32 Freescale Semiconductor DMARQ (device) t UI DMACK (device) t ACK STOP (host) t ACK HDMARDY (host) t ZIORDY DSTROBE (device) t AZ DD(0:15) t ACK DA0, DA1, DA2, CS [0:1]1 t DVS t DVH t ZAD t ENV t ENV t ZAD t FS t FS Figure 16. Timing Diagram—Initiating an Ultra DMA Data In Burst t 2CYC t CYC t CYC t 2CYC DSTROBE at device tDVH DD(0:15) at device DSTROBE at host tDH DD(0:15) at host tDS tDH tDS tDH tDVS tDVH tDVS tDVH Figure 17. Timing Diagram—Sustained Ultra DMA Data In Burst MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 33 DMARQ (device) DMARQ (host) STOP (host) t SR HDMARDY (host) t RFS DSTROBE (device) DD[0:15] (device) t RP Figure 18. Timing Diagram—Host Pausing an Ultra DMA Data In Burst DMARQ (device) DMACK (host) t LI STOP (host) tLI HDMARDY (host) t SS DSTROBE (device) t ZAH t AZ DD[0:15] DA0,DA1,DA2, CS [0:1] CRC t ACK t DVS t DVH t IORDYZ t ACK t LI t MLI t ACK Figure 19. Timing Diagram—Drive Terminating Ultra DMA Data In Burst MPC5200B Data Sheet, Rev. 3 34 Freescale Semiconductor DMARQ (device) t LI DMACK (host) t RP STOP (host) t AZ HDMARDY (host) t RFS DSTROBE (device) t LI t MLI t IORDYZ t DVS t DVH DD[0:15] CRC t ACK DA0,DA1,DA2, CS [0:1] t ZAH t ACK t MLI tACK Figure 20. Timing Diagram—Host Terminating Ultra DMA Data In Burst DMARQ (device) DMACK (host) tACK STOP (host) tZIORDY DDMARDY (host) tACK HSTROBE (device) tDVS tDVH DD[0:15] (host) tACK DA0,DA1,DA2, CS [0:1] tLI tUI tENV tUI Figure 21. Timing Diagram—Initiating an Ultra DMA Data Out Burst MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 35 t 2CYC t CYC HSTROBE (host) t DVH DD[0:15] (host) HSTROBE (device) t DH DD[0:15] (device) t DS t DH t DS t DH t DVS t DVH t DVS t DVH t CYC t 2CYC Figure 22. Timing Diagram—Sustained Ultra DMA Data Out Burst t RP DMARQ (device) DMACK (host) STOP (host) t SR DDMARDY (device) t RFS HSTROBE DD[0:15] (host) Figure 23. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst MPC5200B Data Sheet, Rev. 3 36 Freescale Semiconductor DMARQ (device) t LI DMACK (host) t SS STOP (host) t LI DDMARDY (device) tACK HSTROBE (host) t DVS DD[0:15] (host) DA0,DA1,DA2, CS [0:1] CRC t ACK t DVH t IORDYZ t LI t ACK t MLI Figure 24. Timing Diagram—Host Terminating Ultra DMA Data Out Burst DMARQ (device) DMACK (host) t LI STOP (host) t RP DDMARDY (device) t RFS HSTROBE (host) t DVS DD[0:15] (host) CRC t ACK t DVH t LI t MLI t ACK t IORDYZ t MLI t ACK DA0,DA1,DA2, CS [0:1] Figure 25. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 37 Table 30. Timing Specification ata_isolation Sym 1 2 Description ata_isolation setup time ata_isolation hold time Min 7 Max 19 Units IP Bus cycles IP Bus cycles SpecID A8.48 A8.49 DIOR ATA_ISOLATION 1 2 Figure 26. Timing Diagram-ATA-ISOLATION 1.3.10 • Ethernet AC Test Timing Conditions: Output Loading All Outputs: 25 pF Table 31. MII Rx Signal Timing Sym t1 t2 t3 t4 1 Description RXD[3:0], RX_DV, RX_ER to RX_CLK setup RX_CLK to RXD[3:0], RX_DV, RX_ER hold RX_CLK pulse width high RX_CLK pulse width low Min 10 10 35% 35% Max — — 65% 65% Unit ns ns RX_CLK RX_CLK Period(1) Period(1) SpecID A9.1 A9.2 A9.3 A9.4 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification. t3 RX_CLK (Input) t4 RXD[3:0] (inputs) RX_DV RX_ER t1 t2 Figure 27. Ethernet Timing Diagram—MII Rx Signal MPC5200B Data Sheet, Rev. 3 38 Freescale Semiconductor Table 32. MII Tx Signal Timing Sym t5 t6 t7 t8 1 Description TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER invalid TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width low Min 5 — 35% 35% Max — 25 65% 65% Unit ns ns TX_CLK Period(1) TX_CLK Period (1) SpecID A9.5 A9.6 A9.7 A9.8 The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification. t7 TX_CLK (Input) t5 TXD[3:0] (Outputs) TX_EN TX_ER t6 t8 Figure 28. Ethernet Timing Diagram—MII Tx Signal Table 33. MII Async Signal Timing Sym t9 Description CRS, COL minimum pulse width Min 1.5 Max — Unit TX_CLK Period SpecID A9.9 CRS, COL t9 Figure 29. Ethernet Timing Diagram—MII Async MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 39 Table 34. MII Serial Management Channel Signal Timing Sym t10 t11 t12 t13 t14 t15 1 Description MDC falling edge to MDIO output delay MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width high (1) Min 0 10 10 160 160 400 Max 25 — — — — — Unit ns ns ns ns ns ns SpecID A9.10 A9.11 A9.12 A9.13 A9.14 A9.15 MDC pulse width low(1) MDC period(2) MDC is generated by MPC5200B with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5200B User Manual. 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5200B User Manual. t13 t14 MDC (Output) t15 t10 MDIO (Output) MDIO (Input) t11 t12 Figure 30. Ethernet Timing Diagram—MII Serial Management 1.3.11 Sym 1 2 3 4 1 USB Table 35. Timing Specifications—USB Output Line Description USB Bit width(1) Transceiver enable time Signal falling time Signal rising time Min 83.3 83.3 — — Max 667 667 7.9 7.9 Units ns ns ns ns SpecID A10.1 A10.2 A10.3 A10.4 Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode). NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 40 Freescale Semiconductor 2 USB_OE 3 USB_TXN 1 USB_TXP 1 4 4 3 Figure 31. Timing Diagram—USB Output Line 1.3.12 Sym 1 2 3 4 5 6 7 8 9 10 11 1 SPI Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Description Cycle time Clock high or low time Slave select to clock delay Output Data valid after Slave Select (SS) Output Data valid after SCK Input Data setup time Input Data hold time Slave disable lag time Sequential transfer delay Clock falling time Clock rising time Min 4 2 15.0 — — 20.0 20.0 15.0 1 — — Max 1024 512 — 20.0 20.0 — — — — 7.9 7.9 Units IP-Bus Cycle(1) IP-Bus Cycle(1) SpecID A11.1 A11.2 A11.3 A11.4 A11.5 A11.6 A11.7 A11.8 A11.9 A11.10 A11.11 ns ns ns ns ns ns IP-Bus Cycle(1) ns ns Inter Peripheral Clock is defined in the MPC5200B User Manual. NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 41 1 10 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 11 2 2 11 10 8 9 4 MOSI Output 6 MISO Input 5 6 7 7 Figure 32. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym 1 2 3 4 5 6 7 8 9 1 Description Cycle time Clock high or low time Slave select to clock delay Output Data valid after Slave Select (SS) Output Data valid after SCK Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay Min 4 2 15.0 — — 50.0 0.0 15.0 1 Max 1024 512 — 50.0 50.0 — — — — Units IP-Bus Cycle(1) IP-Bus Cycle ns ns ns ns ns ns IP-Bus Cycle (1) (1) SpecID A11.12 A11.13 A11.14 A11.15 A11.16 A11.17 A11.18 A11.19 A11.20 Inter Peripheral Clock is defined in the MPC5200B User Manual. NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 42 Freescale Semiconductor 1 SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 2 2 8 9 6 MOSI Input 4 MISO Output 5 7 Figure 33. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym 1 2 3 4 5 6 7 8 9 10 1 Description Cycle time Clock high or low time Slave select to clock delay Output data valid Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay Clock falling time Clock rising time Min 4 2 15.0 — 20.0 20.0 15.0 1 — — Max 1024 512 — 20.0 — — — — 7.9 7.9 Units SpecID IP-Bus Cycle(1) A11.21 IP-Bus Cycle(1) A11.22 ns ns ns ns ns IP-Bus Cycle ns ns (1) A11.23 A11.24 A11.25 A11.26 A11.27 A11.28 A11.29 A11.30 Inter Peripheral Clock is defined in the MPC5200B User Manual. NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 43 1 9 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 10 2 2 10 9 7 8 4 MOSI Output 5 MISO Input 6 Figure 34. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) Sym 1 2 3 4 5 6 7 8 1 Description Cycle time Clock high or low time Slave select to clock delay Output data valid Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay Min 4 2 15.0 — 50.0 0.0 15.0 1 Max 1024 512 — 50.0 — — — — Units SpecID IP-Bus Cycle(1) A11.31 IP-Bus Cycle(1) ns ns ns ns ns IP-Bus Cycle(1) A11.32 A11.33 A11.34 A11.35 A11.36 A11.37 A11.38 Inter Peripheral Clock is defined in the MPC5200B User Manual. NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 44 Freescale Semiconductor 1 SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 2 2 7 8 5 MOSI Input 4 MISO Output 6 Figure 35. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 1.3.13 MSCAN The CAN functions are available as RX and TX pins at normal IO pads (I2C1+GPTimer or PSC2). There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured. 1.3.14 Sym 1 2 4 6 7 8 9 1 I2C Table 40. I2C Input Timing Specifications—SCL and SDA Description Start condition hold time Clock low time Data hold time Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 0.0 4 0.0 2 2 Max — — — — — — — Units IP-Bus Cycle(1) IP-Bus Cycle(1) SpecID A13.1 A13.2 A13.3 A13.4 A13.5 (1) ns IP-Bus Cycle(1) ns IP-Bus Cycle A13.6 A13.7 IP-Bus Cycle(1) Inter Peripheral Clock is defined in the MPC5200B User Manual. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 45 Table 41. I2C Output Timing Specifications—SCL and SDA Sym 1 (1) Description Start condition hold time Clock low time SCL/SDA rise time Data hold time SCL/SDA fall time Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 6 10 — 7 — 10 2 20 10 Max — — 7.9 — 7.9 — — — — Units IP-Bus Cycle(3) SpecID A13.8 A13.9 A13.10 (3) 2(1) 3 (2) (1) IP-Bus Cycle(3) ns IP-Bus Cycle ns 4 A13.11 A13.12 5(1) 6(1) 7(1) 8(1) 9(1) 1 IP-Bus Cycle(3) A13.13 IP-Bus Cycle(3) A13.14 IP-Bus Cycle(3) A13.15 IP-Bus Cycle(3) A13.16 Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values 3 Inter Peripheral Clock is defined in the MPC5200B User Manual. NOTE Output timing is specified at a nominal 50 pF load. 2 SCL 3 6 5 1 4 7 8 9 SDA Figure 36. Timing Diagram—I2C Input/Output 1.3.15 J1850 See the MPC5200B User Manual. MPC5200B Data Sheet, Rev. 3 46 Freescale Semiconductor 1.3.16 1.3.16.1 PSC Codec Mode (8,16,24 and 32-bit)/I2S Mode Table 42. Timing Specifications—8,16, 24, and 32-bit CODEC / I2S Master Mode Sym 1 2 3 4 5 6 7 8 1 Description Bit Clock cycle time, programmed in CCS register Clock duty cycle Bit Clock fall time Bit Clock rise time FrameSync valid after clock edge FrameSync invalid after clock edge Output Data valid after clock edge Input Data setup time Min 40.0 — — — — — — 6.0 Typ — 50 — — — — — — Max — — 7.9 7.9 8.4 8.4 9.3 — Units ns % (1) SpecID A15.1 A15.2 A15.3 A15.4 A15.5 A15.6 A15.7 A15.8 ns ns ns ns ns ns Bit Clock cycle time NOTE Output timing is specified at a nominal 50 pF load. 1 BitClk (CLKPOL=0) Output BitClk (CLKPOL=1) Output 5 FrameSync (SyncPol = 1) Output FrameSync (SyncPol = 0) Output 7 TxD Output 3 2 2 4 4 3 6 8 RxD Input Figure 37. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Master Mode MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 47 Table 43. Timing Specifications — 8,16, 24, and 32-bit CODEC / I2S Slave Mode Sym 1 2 3 4 5 6 1 Description Bit Clock cycle time Clock duty cycle FrameSync setup time Output Data valid after clock edge Input Data setup time Input Data hold time Min 40.0 — 1.0 — 1.0 1.0 Typ — 50 — — — — Max — — — 14.0 — — Units ns %(1) ns ns ns ns SpecID A15.9 A15.10 A15.11 A15.12 A15.13 A15.14 Bit Clock cycle time NOTE Output timing is specified at a nominal 50 pF load. 1 BitClk (CLKPOL=0) Input BitClk (CLKPOL=1) Input 2 2 3 FrameSync (SyncPol = 1) Input FrameSync (SyncPol = 0) Input 4 TxD Output 5 RxD Input 6 Figure 38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Slave Mode MPC5200B Data Sheet, Rev. 3 48 Freescale Semiconductor 1.3.16.2 AC97 Mode Table 44. Timing Specifications — AC97 Mode Sym 1 2 3 4 5 6 7 Description Bit Clock cycle time Clock pulse high time Clock pulse low time FrameSync valid after rising clock edge Output Data valid after rising clock edge Input Data setup time Input Data hold time Min — — — — — 1.0 1.0 Typ 81.4 40.7 40.7 — — — — Max — — — 13.0 14.0 — — Units ns ns ns ns ns ns ns SpecID A15.15 A15.16 A15.17 A15.18 A15.19 A15.20 A15.21 NOTE Output timing is specified at a nominal 50 pF load. 1 BitClk (CLKPOL=0) Input FrameSync (SyncPol = 1) Output Sdata_out Output 3 4 2 5 6 Sdata_in Input 7 Figure 39. Timing Diagram — AC97 Mode 1.3.16.3 IrDA Mode Table 45. Timing Specifications — IrDA Transmit Line Sym 1 2 3 4 Description Pulse high time, defined in the IrDA protocol definition Pulse low time, defined in the IrDA protocol definition Transmitter rising time Transmitter falling time Min 0.125 0.125 — — Max 10000 10000 7.9 7.9 Units μs μs ns ns SpecID A15.22 A15.23 A15.24 A15.25 NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 49 3 IrDA_TX (SIR / FIR / MIR) 1 2 4 Figure 40. Timing Diagram — IrDA Transmit Line 1.3.16.4 SPI Mode Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Sym 1 2 3 4 5 6 7 8 9 10 11 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programable in the PSC CCS register Output Data valid after Slave Select (SS) Output Data valid after SCK Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time Min 30.0 15.0 30.0 — — 6.0 1.0 — 15.0 — — Max — — — 8.9 8.9 — — 8.9 — 7.9 7.9 Units ns ns ns ns ns ns ns ns ns ns ns SpecID A15.26 A15.27 A15.28 A15.29 A15.30 A15.31 A15.32 A15.33 A15.34 A15.35 A15.36 NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 50 Freescale Semiconductor 1 10 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 11 2 2 11 10 8 9 4 MOSI Output 6 MISO Input 5 6 7 7 Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym 1 2 3 4 5 6 7 8 9 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Input Data setup time Input Data hold time Output data valid after SS Output data valid after SCK Slave disable lag time Minimum Sequential Transfer delay = 2 * IP Bus clock cycle time Min 30.0 15.0 1.0 1.0 1.0 — — 0.0 30.0 Max — — — — — 14.0 14.0 — — Units ns ns ns ns ns ns ns ns — SpecID A15.37 A15.38 A15.39 A15.40 A15.41 A15.42 A15.43 A15.44 A15.45 NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 51 1 SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 2 2 8 9 4 MOSI Input 6 MISO Output 7 5 Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym 1 2 3 4 5 6 7 8 9 10 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programable in the PSC CCS register Output data valid Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time Min 30.0 15.0 30.0 — 6.0 1.0 — 15.0 — — Max — — — 8.9 — — 8.9 — 7.9 7.9 Units ns ns ns ns ns ns ns ns ns ns SpecID A15.46 A15.47 A15.48 A15.49 A15.50 A15.51 A15.52 A15.53 A15.54 A15.55 NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 52 Freescale Semiconductor 1 9 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 10 2 2 10 9 7 8 4 MOSI Output 5 MISO Input 6 Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) Sym 1 2 3 4 5 6 7 8 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Output data valid Input Data setup time Input Data hold time Slave disable lag time Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time Min 30.0 15.0 0.0 — 2.0 1.0 0.0 30.0 Max — — — 14.0 — — — — Units ns ns ns ns ns ns ns ns SpecID A15.56 A15.57 A15.58 A15.59 A15.60 A15.61 A15.62 A15.63 NOTE Output timing is specified at a nominal 50 pF load. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 53 1 SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 2 2 7 8 5 MOSI Input 4 MISO Output 6 Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 1.3.17 1.3.17.1 GPIOs and Timers General and Asynchronous Signals The MPC5200B contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume a 133 MHz internal bus frequency. Figure 45 shows the GPIO Timing Diagram. Table 50 gives the timing specifications. Table 50. Asynchronous Signals Sym tCK tIS tIH tDV tDH Description Clock Period Input Setup Input Hold Output Valid Output Hold Min 7.52 12 1 — 1 Max — — — 15.33 — Units ns ns ns ns ns SpecID A16.1 A16.2 A16.3 A16.4 A16.5 MPC5200B Data Sheet, Rev. 3 54 Freescale Semiconductor tCK tDV Output tIS Input valid valid tIH tDH Figure 45. Timing Diagram—Asynchronous Signals MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 55 1.3.18 Sym — 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 IEEE 1149.1 (JTAG) AC Specifications Table 51. JTAG Timing Specification Characteristic TCK frequency of operation. TCK cycle time. TCK clock pulse width measured at 1.5V. TCK rise and fall times. TRST setup time to tck falling edge . TRST assert time. Input data setup time . Input data hold time(2) . (3). (2) (1) Min 0 40 1.08 0 10 5 5 15 0 0 5 1 0 0 Max 25 — — 3 — — — — 30 30 — — 15 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns SpecID A17.1 A17.2 A17.3 A17.4 A17.5 A17.6 A17.7 A17.8 A17.9 A17.10 A17.11 A17.12 A17.13 A17.14 TCK to output data valid(3). TCK to output high impedance TMS, TDI data setup time. TMS, TDI data hold time. TCK to TDO data valid. TCK to TDO high impedance. TRST is an asynchronous signal. The setup time is for test purposes only. Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK. 1 2 2 TCK VM VM VM 3 3 VM = Midpoint Voltage Numbers shown reference Table 51. Figure 46. Timing Diagram—JTAG Clock Input TCK 4 TRST 5 Numbers shown reference Table 51. Figure 47. Timing Diagram—JTAG TRST MPC5200B Data Sheet, Rev. 3 56 Freescale Semiconductor TCK 6 DATA INPUTS 8 OUTPUT DATA VALID 9 DATA OUTPUTS Numbers shown reference Table 51. 7 INPUT DATA VALID DATA OUTPUTS Figure 48. Timing Diagram—JTAG Boundary Scan TCK 10 TDI, TMS 12 OUTPUT DATA VALID 13 TDO Numbers shown reference Table 51. 11 INPUT DATA VALID TDO Figure 49. Timing Diagram—Test Access Port 2 2.1 • • • Package Description Package Parameters Package outline: 27 mm x 27 mm Interconnects: 2 Pitch: 1.27 mm The MPC5200B uses a 27 mm x 27 mm TE-PBGA package. The package parameters are as provided in the following list: MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 57 2.2 Mechanical Dimensions Figure 50 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200B, 272 TE-PBGA package. PIN A1 INDEX D C 4X 0.2 A 272X 0.2 A E E2 0.35 A D2 B TOP VIEW (D1) 19X 0.2 M ABC NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A. 4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS MIN MAX 2.05 2.65 0.50 0.70 0.50 0.70 1.05 1.25 0.60 0.90 27.00 BSC 24.13 REF 23.30 24.70 27.00 BSC 24.13 REF 23.30 24.70 1.27 BSC e Y W V U T R P N M L K J H G F E D C B A 19X e DIM A A1 A2 A3 b D D1 D2 E E1 E2 e (E1) 4X A1 A3 A2 A SIDE VIEW 272X e /2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 b3 0.3 M M BOTTOM VIEW ABC A 0.15 CASE 1135A–01 ISSUE B DATE 10/15/1997 Figure 50. Mechanical Dimensions and Pinout Assignments for the MPC5200B, 272 TE-PBGA MPC5200B Data Sheet, Rev. 3 58 Freescale Semiconductor 2.3 Pinout Listings Table 52. MPC5200B Pinout Listing Name Alias Type Power Supply SDRAM MEM_CAS MEM_CLK_EN MEM_CS MEM_DQM[3:0] MEM_MA[12:0] MEM_MBA[1:0] MEM_MDQS[3:0] MEM_MDQ[31:0] MEM_CLK MEM_CLK MEM_RAS MEM_WE RAS DQM MA MBA MDQS MDQ CAS CLK_EN I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO PCI EXT_AD[31:0] PCI_CBE_0 PCI_CBE_1 PCI_CBE_2 PCI_CBE_3 PCI_CLOCK PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_IRDY PCI_PAR PCI_PERR PCI_REQ PCI_RESET PCI_SERR PCI_STOP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO PCI PCI PCI PCI PCI PCI PCI PCI DRV8 DRV8 PCI PCI PCI DRV8 PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI TTL TTL PCI PCI PCI TTL PCI PCI PCI DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Output Driver Type Input Type Pull-up/ down See details in the MPC5200B User Manual. MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 59 Table 52. MPC5200B Pinout Listing (continued) Name PCI_TRDY Alias Type I/O Power Supply VDD_IO Local Plus LP_ACK LP_ALE LP_OE LP_RW LP_TS LP_CS0 LP_CS1 LP_CS2 LP_CS3 LP_CS4 LP_CS5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ATA ATA_DACK ATA_DRQ ATA_INTRQ ATA_IOCHRDY ATA_IOR ATA_IOW ATA_ISOLATION I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Ethernet ETH_0 ETH_1 ETH_2 ETH_3 ETH_4 ETH_5 ETH_6 ETH_7 TX, TX_EN RTS, TXD[0] USB_TXP, RTX, TXD[1] USB_PRTPWR, TXD[2] USB_SPEED, TXD[3] USB_SUPEND, TX_ER USB_OE, RTS, MDC TXN, MDIO I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 TTL TTL TTL TTL TTL TTL TTL TTL DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 TTL TTL TTL TTL TTL TTL TTL PULLDOWN PULLDOWN PULLUP DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL PULLUP Output Driver Type PCI Input Type PCI Pull-up/ down MPC5200B Data Sheet, Rev. 3 60 Freescale Semiconductor Table 52. MPC5200B Pinout Listing (continued) Name ETH_8 ETH_9 ETH_10 ETH_11 ETH_12 ETH_13 ETH_14 ETH_15 ETH_16 ETH_17 Alias RX_DV CD, RX_CLK CTS, COL TX_CLK RXD[0] USB_RXD, CTS, RXD[1] USB_RXP, UART_RX, RXD[2] USB_RXN, RX, RXD[3] USB_OVRCNT, CTS, RX_ER CD, CRS Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO IRDA PSC6_0 PSC6_1 PSC6_2 PSC6_3 IRDA_RX, RxD Frame, CTS IRDA_TX, TxD IR_USB_CLK,BitC lk, RTS I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO USB USB_0 USB_1 USB_2 USB_3 USB_4 USB_5 USB_6 USB_7 USB_8 USB_9 USB_OE USB_TXN USB_TXP USB_RXD USB_RXP USB_RXN USB_PRTPWR USB_SPEED USB_SUPEND USB_OVRCNT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO I2C I2C_0 I2C_1 I2C_2 SCL SDA SCL I/O I/O I/O VDD_IO VDD_IO VDD_IO DRV4 DRV4 DRV4 Schmitt Schmitt Schmitt DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL DRV4 DRV4 DRV4 DRV4 TTL TTL TTL Schmitt Output Driver Type DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 Input Type TTL Schmitt TTL Schmitt TTL TTL TTL TTL TTL TTL Pull-up/ down MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 61 Table 52. MPC5200B Pinout Listing (continued) Name I2C_3 Alias SDA Type I/O Power Supply VDD_IO PSC PSC1_0 PSC1_1 PSC1_2 PSC1_3 PSC1_4 PSC2_0 PSC2_1 PSC2_2 PSC2_3 PSC2_4 PSC3_0 PSC3_1 PSC3_2 PSC3_3 PSC3_4 PSC3_5 PSC3_6 PSC3_7 PSC3_8 PSC3_9 TxD, Sdata_out, MOSI, TX RxD, Sdata_in, MISO, TX Mclk, Sync, RTS BitClk, SCK, CTS Frame, SS, CD TxD, Sdata_out, MOSI, TX RxD, Sdata_in, MISO, TX Mclk, Sync, RTS BitClk, SCK, CTS Frame, SS, CD USB_OE, TxDS, TX USB_TXN, RxD, RX USB_TXP, BitClk, RTS USB_RXD, Frame, SS, CTS USB_RXP, CD USB_RXN USB_PRTPWR, Mclk, MOSI USB_SPEED. MISO USB_SUPEND, SS USB_OVRCNT, SCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO GPIO/TIMER GPIO_WKUP_6 GPIO_WKUP_7 TIMER_0 MEM_CS1 I/O I/O I/O VDD_MEM_IO VDD_IO VDD_IO DRV16_MEM DRV8 DRV4 TTL TTL TTL PULLUP_MEM DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 TTL TTL TTL Schmitt TTL TTL TTL TTL Schmitt TTL TTL TTL Schmitt TTL TTL TTL TTL TTL TTL TTL Output Driver Type DRV4 Input Type Schmitt Pull-up/ down MPC5200B Data Sheet, Rev. 3 62 Freescale Semiconductor Table 52. MPC5200B Pinout Listing (continued) Name TIMER_1 TIMER_2 TIMER_3 TIMER_4 TIMER_5 TIMER_6 TIMER_7 MOSI MISO SS SCK Alias Type I/O I/O I/O I/O I/O I/O I/O Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Clock SYS_XTAL_IN SYS_XTAL_OUT RTC_XTAL_IN RTC_XTAL_OUT Input Output Input Output VDD_IO VDD_IO VDD_IO VDD_IO Misc PORRESET HRESET SRESET IRQ0 IRQ1 IRQ2 IRQ3 Input I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO DRV4 DRV8_OD 1 Output Driver Type DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 Input Type TTL TTL TTL TTL TTL TTL TTL Pull-up/ down Schmitt Schmitt Schmitt TTL TTL TTL TTL DRV8_OD1 DRV4 DRV4 DRV4 DRV4 Test/Configuration SYS_PLL_TPA TEST_MODE_0 TEST_MODE_1 TEST_SEL_0 TEST_SEL_1 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST TCK TDI TDO TMS TRST I/O Input Input I/O I/O Input Input I/O Input Input VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO DRV4 DRV4 DRV4 DRV4 DRV8 DRV4 DRV4 DRV8 DRV4 DRV4 TTL TTL TTL TTL TTL Schmitt TTL TTL TTL TTL PULLUP PULLUP PULLUP PULLUP PULLUP Power and Ground VDD_IO - MPC5200B Data Sheet, Rev. 3 Freescale Semiconductor 63 Table 52. MPC5200B Pinout Listing (continued) Name VDD_MEM_IO VDD_CORE VSS_IO/CORE SYS_PLL_AVDD CORE_PLL_AVDD 1 Alias Type - Power Supply Output Driver Type Input Type Pull-up/ down All “open drain” outputs of the MPC5200B are actually regular three-state output drivers with the output data tied low and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200B I/O power rail if the external signal is driven above the MPC5200B I/O power rail voltage. 3 3.1 System Design Information Power Up/Down Sequencing Figure 51 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL VDD (PLL_AVDD), and Core VDD (VDD_CORE). DC Power Supply Voltage 3.3V VDD_IO, VDD_IO_MEM (SDR) VDD_IO_MEM (DDR) 2.5V 1 1.5V VDD_CORE, PLL_AVDD 2 0 Time Note: VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time, including power-up. Note: It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V then separate for completion of ramps. Note: Input voltage must not be greater than the supply voltage (VDD_IO) VDD_IO_MEM, VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up. Note: Use 1 microsecond or slower rise time for all supplies. Figure 51. Supply Voltage Sequencing MPC5200B Data Sheet, Rev. 3 64 Freescale Semiconductor The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down sequences. VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE. 3.1.1 Power Up Sequence If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: Use one microsecond or slower rise time for all supplies. VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. 3.1.2 Power Down Sequence If VDD_CORE/PLL_AVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.5V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. 2. Drop VDD_CORE/PLL_AVDD to 0V. Drop VDD_IO/VDD_IO_MEM supplies. 3.2 System and CPU Core AVDD Power Supply Filtering Each of the independent PLL power supplies require filtering external to the device. The following drawing is a recommendation for the required filter circuit. 10 W Power Supply source