MPC5553MZQ112R2

Freescale Semiconductor Data Sheet: Product Preview Document Number: MPC5553 Rev. 0, 06/2006 MPC5553 Microcontroller Data Sheet by: Microcontroller Division This document provides electrical specifications, pin assignments, and package diagrams for the MPC5553 microcontroller device. For functional characteristics, refer to the MPC5553/MPC5554 Microcontroller Reference Manual. Contents 1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5 3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 EMI (Electromagnetic Interference) Characteristics 9 3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10 3.7 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . 11 3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13 3.9 Oscillator & FMPLL Electrical Characteristics . . . . 19 3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 20 3.11 H7Fa Flash Memory Electrical Characteristics . . . 21 3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 45 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 55 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1 Overview The MPC5553 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers based on the PowerPC™ Book E architecture. This family of parts contains many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family. The host processor core of this device is compatible with the PowerPC Book E architecture. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture has enhancements that improve the PowerPC architecture’s fit in embedded applications. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the classic 4 5 This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. • Preliminary—Subject to Change Without Notice Overview PowerPC instruction set. This family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the 8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM and 1.5 Mbyte internal Flash memory. Both the internal SRAM and the Flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family. The complex I/O timer functions of the MPC5500 family are performed by an enhanced time processor unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of the MPC5500 family are performed by the enhanced modular input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double action, pulse width modulation (PWM), and modulus counter operation. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIO) signals. The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter (eQADC). The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing. MPC5553 Microcontroller Data Sheet, Rev. 0 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor Ordering Information 2 Ordering Information M PC 5553 M ZP 80 R2 Qualification Status Core Code Device Number Temperature Range Package Identifier Operating Frequency (MHz) Tape and Reel Status Temperature Range M = -40° C to 125° C A = -55° C to 125° C Package Identifier ZP = 416PBGA SnPb VR = 416PBGA Pb-free VF = 208MAPBGA SnPb VM = 208MAPBGA Pb-free ZQ = 324PBGA SnPb VZ = 324PBGA Pb-free Operating Frequency 80 = 80MHz 112 = 112MHz 132 = 132MHz Tape and Reel Status R2 = Tape and Reel (blank) = Trays Qualification Status P = Pre Qualification M = Full Spec Qualified Note: Not all options are available on all devices. Refer to Table 1. Figure 1. MPC5500 Family Part Number Example Table 1. Orderable Part Numbers Freescale Part Number MPC5553MVR132 MPC5553MZP132 MPC5553MVZ132 MPC5553MZQ132 MPC5553MVF132 MPC5553MVM132 MPC5553MVR112 MPC5553MZP112 MPC5553MVZ112 MPC5553MZQ112 MPC5553MVF112 MPC5553MVM112 MPC5553MVR80 MPC5553MZP80 MPC5553MVZ80 MPC5553MZQ80 Description MPC5553 Lead free 416 package MPC5553 Lead 416 package MPC5553 Lead free 324 package MPC5553 Lead 324 package MPC5553 Lead 208 package MPC5553 Lead free 208 package MPC5553 Lead free 416 package MPC5553 Lead 416 package MPC5553 Lead free 324 package MPC5553 Lead 324 package MPC5553 Lead 208 package MPC5553 Lead free 208 package MPC5553 Lead free 416 package MPC5553 Lead 416 package MPC5553 Lead free 324 package MPC5553 Lead 324 package Speed (MHz) 132 132 132 132 132 132 112 112 112 112 112 112 80 80 80 80 Max Speed1 (MHz) (fMAX) 132 132 132 132 132 132 114 114 114 114 114 114 82 82 82 82 Temperature -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C -40° C to 125° C MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3 Electrical Characteristics Table 1. Orderable Part Numbers (continued) MPC5553MVF80 MPC5553MVM80 1 MPC5553 Lead 208 package MPC5553 Lead free 208 package 80 80 82 82 -40° C to 125° C -40° C to 125° C Speed is the nominal maximum frequency. Max Speed is the maximum speed allowed including any frequency modulation. 80-MHz parts allow for 80 MHz + 2% modulation. However, 132-MHz allows only 128 MHz + 2% FM. 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Maximum Ratings Table 2. Absolute Maximum Ratings1 Num 1 2 3 4 5 6 7 8 9 10 11 12 Characteristic 1.5V Core Supply Voltage 3 Flash Program/Erase Voltage Flash Core Voltage Flash Read Voltage SRAM Standby Voltage Clock Synthesizer Voltage 3.3V I/O Buffer Voltage Voltage Regulator Control Input Voltage Analog Supply Voltage (reference to VSSA) I/O Supply Voltage (Fast I/O Pads) Voltage5 4 4 Symbol VDD VPP VDDF VFLASH VSTBY VDDSYN VDD33 VRC33 VDDA VDDE VDDEH VIN Min – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 –0.3 –0.3 – 0.3 – 0.3 – 0.3 –1.06 –0.37 –1.06 Max2 1.7 6.5 1.7 4.6 1.7 4.6 4.6 4.6 5.5 4.6 6.5 6.58 Unit V V V V V V V V V V V I/O Supply Voltage (Slow/Medium I/O Pads) DC Input VDDEH powered I/O Pads, except eTPUB15 and SINB (DSPI_B_SIN) VDDEH powered I/O Pads (eTPUB15 and SINB) VDDE powered I/O Pads Analog Reference High Voltage (reference to VRL) VSS Differential Voltage VDD Differential Voltage VREF Differential Voltage VRH to VDDA Differential Voltage VRL to VSSA Differential Voltage VDDEH to VDDA Differential Voltage VDDF to VDD Differential Voltage This spec has been moved to Table 9, spec 43a. VSSSYN to VSS Differential Voltage V 6.58 4.69 5.5 0.1 VDD 5.5 5.5 0.3 VDDEH 0.3 V V V V V V V V 13 14 15 16 17 18 19 20 21 22 VRH VSS – VSSA VDD – VDDA VRH – VRL VRH – VDDA VRL – VSSA VDDEH – VDDA VDDF – VDD VSSSYN – VSS – 0.3 – 0.1 – VDDA – 0.3 – 5.5 – 0.3 –VDDA –0.3 –0.1 0.1 V MPC5553 Microcontroller Data Sheet, Rev. 0 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 2. Absolute Maximum Ratings1 (continued) Num 23 24 25 26 27 28 29 1 Characteristic VRCVSS to VSS Differential Voltage Maximum DC Digital Input Current digital pins)5 10 Symbol VRCVSS – VSS Min –0.1 –2 –3 – 40.0 – 55.0 — — Max2 0.1 2 3 150.0 150.0 260.0 3 Unit V mA mA o (per pin, applies to all IMAXD IMAXA TJ TSTG Maximum DC Analog Input Current 11 (per pin, applies to all analog pins) Maximum Operating Temperature Range 12 — Die Junction Temperature Storage Temperature Range Maximum Solder Temperature Moisture Sensitivity Level 14 13 C C C o o TSDR MSL Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 1.5V +/– 10% for proper operation. This parameter is specified at a maximum junction temperature of 150C. 4 All functional non-supply I/O pins are clamped to VSS and VDDE or VDDEH. 5 AC signal over and undershoot of the input voltages of up to +/– 2.0 volts is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 6 Internal structures will hold the voltage above –1.0 volt if the injection current limit of 1 mA is met. 7 Internal structures will not clamp to a safe voltage. External protection must be used to ensure that voltage on the pin stays above –0.3 volts. 8 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDEH supplies, if the maximum injection current specification is met (1 mA for all pins) and VDDEH is within Operating Voltage specifications. 9 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (1 mA for all pins) and VDDE is within Operating Voltage specifications. 10 Total injection current for all pins (including both digital and analog) must not exceed 25mA. 11 Total injection current for all analog input pins must not exceed 15mA. 12 Lifetime operation at these specification limits is not guaranteed. 13 Solder profile per CDF-AEC-Q100. 14 Moisture sensitivity per JEDEC test method A112. 3.2 Thermal Characteristics Table 3. Thermal Characteristics Value Num 1 Characteristic Junction to Ambient 1, 2 Natural Convection (Single layer board) Junction to Ambient 1, 3 Natural Convection (Four layer board 2s2p) Symbol RθJA Unit 208 MAPBGA 324 PBGA 416 PBGA °C/W 41 30 29 2 RθJA °C/W 25 21 21 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 5 Electrical Characteristics Table 3. Thermal Characteristics (continued) Value Num 3 Characteristic Junction to Ambient 1, 3 (@200 ft./min., Single layer board) Junction to Ambient 1, 3 (@200 ft./min., Four layer board 2s2p) Junction to Board 4 (Four layer board 2s2p) Junction to Case 5 Junction to Package Top Natural Convection 6 Symbol RθJMA Unit 208 MAPBGA 324 PBGA 416 PBGA °C/W 33 24 23 4 RθJMA °C/W 22 17 18 5 6 7 1 RθJB RθJC ΨJT °C/W °C/W °C/W 15 7 2 12 8 2 13 9 2 2 3 4 5 6 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 3.2.1 General Notes for Specifications at Maximum Junction Temperature An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJA × PD) where: TA = ambient temperature for the package (oC) RθJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It depends on the construction of the application board (number of planes), the effective size of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the power being dissipated by adjacent components. Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal MPC5553 Microcontroller Data Sheet, Rev. 0 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics performance. When the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 W/cm2. The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RθJB = junction to board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction to ambient thermal resistance (oC/W) RθJC = junction to case thermal resistance (oC/W) RθCA = case to ambient thermal resistance (oC/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7 Electrical Characteristics to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TT = thermocouple temperature on top of the package (oC) ΨJT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. • 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. • 2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. • 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220. 3.3 Package The MPC5553 is available in packaged form. Package options are listed in Section 2, “Ordering Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings. MPC5553 Microcontroller Data Sheet, Rev. 0 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.4 Num 1 2 3 4 5 6 7 1 EMI (Electromagnetic Interference) Characteristics Table 4. EMI Testing Specifications1 Characteristic Scan Range Operating Frequency VDD Operating Voltages VDDSYN, VRC33, VDD33, VFLASH, VDDE Operating Voltages VPP, VDDEH, VDDA Operating Voltages Maximum Amplitude Operating Temperature Min. Value 0.15 — — — — — — Typ. Value — — 1.5 3.3 5.0 — — Max. Value 1000 132 — — — 142 323 25 o Unit MHz MHz V V V dBuV C EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing is performed on the MPC5554 and applied to MPC5500 family as generic EMI performance data. 2 As measured with “single-chip” EMI program. 3 As measured with “expanded” EMI program. 3.5 ESD Characteristics Table 5. ESD Ratings1, 2 Characteristic Symbol Value 2000 R1 C 1500 100 500 (all pins) 750 (corner pins) V Unit V Ohm pF ESD for Human Body Model (HBM) HBM Circuit Description ESD for Field Induced Charge Model (FDCM) Number of Pulses per pin: Positive Pulses (HBM) Negative Pulses (HBM) Interval of Pulses 1 2 — — — 1 1 1 — — second All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9 Electrical Characteristics 3.6 VRC/POR Electrical Specifications Table 6. VRC/POR Electrical Specifications Num 1 2 3 4 5 6 7 Characteristic 1.5V (VDD) POR Negated (Ramp Up) 1.5V (VDD) POR Asserted (Ramp Down) 3.3V (VDDSYN) POR Negated (Ramp Up) 3.3V (VDDSYN) POR Asserted (Ramp Down) RESET Pin Supply (VDDEH6) POR Negated (Ramp Up) RESET Pin Supply (VDDEH6) POR Asserted (Ramp Down) VRC33 voltage before regulator controller allows the pass transistor to start turning on VRC33 voltage when regulator controller allows the pass transistor to completely turn on1, 2 VRC33 voltage above which the regulator controller will keep the 1.5V supply in regulation3, 4 Current which can be sourced by VRCCTL – 40C 25C 150C (Tj) Symbol V_POR15 V_POR33 V_POR5 V_TRANS_ START V_TRANS_ON V_VRC33REG I_VRCCTL5 Min 1.1 1.1 2.0 2.0 2.0 2.0 1.0 2.0 3.0 Max 1.35 1.35 2.85 2.85 2.85 2.85 2.0 2.85 — Units V V V V V V mA 11.0 9.0 7.5 VDD33_LAG — — — — 1.0 mA mA mA V 8 Voltage differential during power up that VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach V_POR33 and V_POR5 minimums respectively Absolute value of Slew Rate on power supply pins Required Gain: Idd / I_VRCCTL (@vdd = 1.35v, fsys = 132MHz)4, 6 – 40C 25C 150C (Tj) 9 10 — BETA7 55.08 58.0 8 50 V/ms — — 500 — — — 70.08 1 2 3 4 5 6 7 8 User must be able to supply full operating current for the 1.5V supply when the 3.3V supply reaches this range. Current limit may be reached during ramp up and should not be treated as short circuit current. At peak current for device. Assumes that the Freescale recommended board requirements and transistor recommendations are met. Board signal traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals should have a maximum of 100 nH inductance and minimal resistance ( 4 µF over all conditions, including lifetime). High frequency bypass capacitors consisting of eight 0.01 µF, two 0.1 µF, and one 1 µF capacitors should be place around the package on the VDD supply signals. I_VRCCTL measured at the following conditions: VDD=1.35V, VRC33=3.1V, V_VRCCTL=2.2V. Values are based on IDD from high use applications as explained in the IDD Electrical Specification. BETA is measured on a per part basis and is calculated as IDD / I_VRCCTL and represents the worst case external transistor BETA. Preliminary value. Final specification pending characterization. MPC5553 Microcontroller Data Sheet, Rev. 0 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.7 Power Up/Down Sequencing Power sequencing between the 1.5-V power supply and VDDSYN or the RESET power supplies is required if the user provides an external 1.5-V power supply and ties VRC33 to ground. To avoid this power sequencing requirement, power up VRC33 within the specified operating range, even if not using the on-chip voltage regulator controller. Refer to Section 3.7.1, “Power Up Sequence (If VRC33 Grounded)” and Section 3.7.2, “Power Down Sequence (If VRC33 Grounded).” Another power sequencing requirement is that VDD33 must be of sufficient voltage before POR negates, so that the values on certain pins are treated as 1s when POR does negate. Refer to Section 3.7.3, “Input Value of Pins During POR Dependent on VDD33.” Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV. Higher spikes in the emitter current of the pass transistor will occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV, this increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for the VRC to operate within specification. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all pins with pad type pad_mh (medium type) and pad_sh (slow type). Table 7. Power Sequence Pin States (Fast Pads) VDDE LOW VDDE VDDE VDDE VDD33 X LOW VDD33 VDD33 VDD X X LOW VDD pad_fc (Fast) Output Driver State Low High High Impedance Functional POR asserted. No POR asserted Comment Functional I/O pins are clamped to VSS and VDDE MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 Electrical Characteristics Table 8. Power Sequence Pin States (Medium and Slow Pads) VDDEH LOW VDDEH VDDEH VDD X LOW VDD pad_mh/pad_sh (Medium and Slow) Output Driver Low High Impedance Functional Comment Functional I/O pins are clamped to VSS and VDDEH POR asserted No POR asserted 3.7.1 Power Up Sequence (If VRC33 Grounded) In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to operate below the specified operation range lower limit of 1.35 V. Since the internal 1.5-V POR is disabled, the internal 3.3-V POR or the RESET power POR must be depended on to hold the device in reset. Since they may negate as low as 2.0 V, it is necessary for VDD to be within spec before the 3.3-V POR and the RESET POR negate. VDDSYN and RESET Power VDD 2.0V 1.35V VDD must reach 1.35V before VDDSYN and the RESET power reach 2.0V Figure 2. Power Up Sequence if VRC33 Grounded 3.7.2 Power Down Sequence (If VRC33 Grounded) In this case, the only requirement is that if VDD falls below its operating range, VDDSYN or the RESET power must fall below 2.0 V before VDD is allowed to rise back into its operating range. This ensures that digital 1.5-V logic that is only reset by ORed_POR, which may have been affected by the 1.5V supply falling below spec, is reset properly. 3.7.3 Input Value of Pins During POR Dependent on VDD33 In order to avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as 1s when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the device by more than the VDD33 lag specification in Table 6. VDD33 individually can lag either VDDSYN or the RESET pin power (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag requirements when powering down. MPC5553 Microcontroller Data Sheet, Rev. 0 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.8 DC Electrical Specifications Table 9. DC Electrical Specifications Num 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Characteristic Core Supply Voltage (average DC RMS voltage) I/O Supply Voltage (Fast I/O) I/O Supply Voltage (Slow/Medium I/O) 3.3V I/O Buffer Voltage Voltage Regulator Control Input Voltage Analog Supply Voltage 1 Symbol VDD VDDE VDDEH VDD33 VRC33 VDDA VPP VFLASH VSTBY VDDSYN VIH_F VIL_F VIH_S VIL_S VHYS_F VHYS_S VINDC VOH_F VOH_S VOL_F VOL_S CL Min 1.35 1.62 3.0 3.0 3.0 4.5 4.5 3.0 0.8 3.0 0.65 * VDDE VSS – 0.3 0.65 * VDDEH VSS – 0.3 Max 1.65 3.6 5.25 3.6 3.6 5.25 5.25 3.6 1.2 3.6 VDDE + 0.3 0.35 * VDDE VDDEH + 0.3 0.35 * VDDEH Unit V V V V V V V V V V V V V V V V V V V V V Flash Programming Voltage2 Flash Read Voltage SRAM Standby Voltage3 Clock Synthesizer Operating Voltage Fast I/O Input High Voltage Fast I/O Input Low Voltage Medium/Slow I/O Input High Voltage Medium/Slow I/O Input Low Voltage Fast I/O Input Hysteresis Medium/Slow I/O Input Hysteresis Analog Input Voltage Fast I/O Output High Voltage (IOH_F = –2.0mA) Slow/Medium I/O Output High Voltage (IOH_S = –2.0mA) Fast I/O Output Low Voltage (IOL_F = 2.0mA) Slow/Medium I/O Output Low Voltage (IOL_S = 2.0mA) Load Capacitance (Fast I/O)4 DSC(SIU_PCR[8:9]) = 0b00 DSC(SIU_PCR[8:9]) = 0b01 DSC(SIU_PCR[8:9]) = 0b10 DSC(SIU_PCR[8:9]) = 0b11 Input Capacitance (Digital Pins) Input Capacitance (Analog Pins) 0.1 * VDDE 0.1 * VDDEH VSSA – 0.3 0.8 * VDDE 0.8 * VDDEH — — VDDA + 0.3 — — 0.2 * VDDE 0.2 * VDDEH 10 20 30 50 7 10 — — — CIN CIN_A — — pF pF pF pF pF pF 24 25 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 Electrical Characteristics Table 9. DC Electrical Specifications (continued) Num 26 Characteristic Input Capacitance (Shared digital and analog pins AN12_MA0_SDS, AN12_MA1_SDO, AN14_MA2_SDI, and AN15_FCK) Symbol CIN_M Min — Max 12 Unit pF 27a Operating Current5 1.5V Supplies @ 132MHz: VDD (including VDDF max current)6, 7 @1.65V Typical Use VDD (including VDDF max current)6, 7 @1.35V Typical Use VDD (including VDDF max current) 7, 8 @1.65V High Use VDD (including VDDF max current)7, 8@1.35V High Use 27b Operating Current 51.5V Supplies @ 114MHz: VDD (including VDDF max current)6, 7@1.65V Typical Use VDD (including VDDF max current)6, 7@1.35V Typical Use VDD (including VDDF max current)7, 8 @1.65V High Use VDD (including VDDF max current)7, 8 @1.35V High Use 27c Operating Current5 1.5V Supplies @ 82MHz: VDD (including VDDF max current)6, 7 @1.65V Typical Use VDD (including VDDF max current)6, 7 @1.35V Typical Use VDD (including VDDF max current)7, 8 @1.65V High Use VDD (including VDDF max current)7, 8 @1.35V High Use 27d IDDSTBY @ 25C VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V IDDSTBY @ 60C VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V IDDSTBY @ 150C (Tj) VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V 28 Operating Current 3.3V Supplies @ 132MHz: VDD3310 IDD33 — 2 + values derived from procedure of Footnote 10 IDD IDD IDD IDD — — — — 5509 4509 6009 4909 mA mA mA mA IDD IDD IDD IDD — — — — 4609 3809 5209 4209 mA mA mA mA IDD IDD IDD IDD — — — — 3509 2909 4009 3309 mA mA mA mA IDDSTBY IDDSTBY IDDSTBY — — — 20 30 50 µA µA µA µA µA µA µA µA µA IDDSTBY IDDSTBY IDDSTBY — — — 70 100 200 IDDSTBY IDDSTBY IDDSTBY — — — 1200 1500 2000 mA VFLASH VDDSYN IVFLASH IDDSYN — — 10 15 mA mA MPC5553 Microcontroller Data Sheet, Rev. 0 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 9. DC Electrical Specifications (continued) Num 29 Characteristic Operating Current 5.0V Supplies @ 132MHz (12MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog Reference Supply Current (VRH, VRL) VPP 30 Operating Current VDDE11 Supplies: VDDEH1 VDDE2 VDDE3 VDDEH4 VDDE5 VDDEH6 VDDE7 VDDEH8 VDDEH9 Fast I/O Weak Pull Up Current12 1.62V – 1.98V 2.25V – 2.75V 3.0V – 3.6V Fast I/O Weak Pull Down Current12 1.62V – 1.98V 2.25V – 2.75V 3.0V – 3.6V 32 Slow/Medium I/O Weak Pull Up/Down Current13 3.0V – 3.6V 4.5V – 5.5V I/O Input Leakage Current14 DC Injection Current (per pin) Analog Input Current, Channel Off15 IACT_S 10 20 IINACT_D IIC IINACT_A IINACT_AD VSS – VSSA VRL VRL – VSSA VRH VRH – VRL VSSSYN – VSS VRCVSS – VSS VDDF – VDD – 2.5 – 2.0 –150 – 2.5 – 100 VSSA – 0.1 –100 VDDA – 0.1 4.5 –50 –50 –100 150 170 2.5 2.0 150 2.5 100 VSSA + 0.1 100 VDDA + 0.1 5.25 50 50 100 IDDA IREF IPP — — — — 20.0 1.0 25 mA mA mA Symbol Min Max Unit IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 IDD9 IACT_F — — — — — — — — — 10 20 20 10 20 20 See Footnote 11 mA mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA mA nA µA mV V mV V V mV mV mV 31 110 130 170 100 130 170 33 34 35 35a Analog Input Current, Shared Analog/Digital pins (AN12, AN13, AN14, AN15) 36 37 38 39 40 41 42 43 VSS Differential Voltage16 Analog Reference Low Voltage VRL Differential Voltage Analog Reference High Voltage VREF Differential Voltage VSSSYN to VSS Differential Voltage VRCVSS to VSS Differential Voltage VDDF to VDD Differential Voltage2 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15 Electrical Characteristics Table 9. DC Electrical Specifications (continued) Num Characteristic Symbol VRC33 – VDDSYN VIDIFF TA (TL to TH) — Min –0.1 – 2.5 – 40.0 — Max 0.117 2.5 125.0 50 Unit V V ο 43a VRC33 to VDDSYN Differential Voltage 44 45 46 1 2 Analog Input Differential Signal Range (with common mode 2.5V) Operating Temperature Range — Ambient (Packaged) Slew rate on power supply pins C V/ms | VDDA0–VDDA1 | must be < 0.1V VPP can drop to 3.0 volts during read operations. 3 During standby operation. If standby operation is not required, VSTBY can be connected to ground. 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Average current measured on Automotive benchmark. 7 Peak currents may be higher on specialized code. 8 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents could be seen if an “idle” loop that crosses cache lines is run from cache. Code should be written to avoid this condition. 9 Preliminary. Final specification pending characterization. 10 Power requirements for the VDD33 supply are dependent on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Table 11 for values to calculate power dissipation for specific operation. 11 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 12 Absolute value of current, measured at V and V . IL IH 13 Absolute value of current, measured at V and V . IL IH 14 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. 15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae. 16 VSSA refers to both VSSA0 and VSSA1. | VSSA0–VSSA1 | must be < 0.1V 17 Up to 0.6 volts during power up and power down. 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. MPC5553 Microcontroller Data Sheet, Rev. 0 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 10. I/O Pad Average DC Current1 Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 Pad Type Slow Symbol IDRV_SH Frequency (MHz) 25 10 2 2 Load2 (pF) 50 50 50 200 50 50 50 200 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 Voltage (V) 5.25 5.25 5.25 5.25 5.25 5.25 5.25 5.25 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 Drive Select / Slew Rate Control 11 01 00 00 11 01 00 00 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Current (mA) 8.0 3.2 0.7 2.4 17.3 6.5 1.1 3.9 2.8 5.2 8.5 11.0 1.6 2.9 4.2 6.7 2.4 4.4 7.2 9.3 1.3 2.5 3.5 5.7 1.7 3.1 5.1 6.6 1.0 1.8 2.5 4.0 Medium IDRV_MH 50 20 3.33 3.33 Fast IDRV_FC 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 These values are estimated from simulation and are not tested. Currents apply to output pins only. All loads are lumped. 3.8.2 I/O Pad VDD33 Current Specifications The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17 Electrical Characteristics frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. VDD33 Pad Average DC Current1 Num Pad Type Symbol Frequency (MHz) Load2 (pF) Inputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 VDD33 (V) VDDE (V) Drive Select Current (mA) Slow Medium Fast I33_SH I33_MH I33_FC 66 66 66 66 66 66 66 66 66 66 56 56 56 56 56 56 56 56 40 40 40 40 40 40 40 40 0.5 0.5 Outputs 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 10 20 30 50 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 5.5 5.5 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 3.6 3.6 3.6 3.6 1.98 1.98 1.98 1.98 NA NA 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0.003 0.003 0.35 0.53 0.62 0.79 0.35 0.44 0.53 0.7 0.30 0.45 0.52 0.67 0.30 0.37 0.45 0.60 0.21 0.31 0.37 0.48 0.21 0.27 0.32 0.42 These values are estimated from simulation and not tested. Currents apply to output pins only for the fast pads and to input pins only for the slow and medium pads. 2 All loads are lumped. MPC5553 Microcontroller Data Sheet, Rev. 0 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.9 Oscillator & FMPLL Electrical Characteristics Table 12. HiP7 FMPLL Electrical Specifications (VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Num 1 Characteristic PLL Reference Frequency Range: Crystal reference External reference Dual Controller (1:1 mode) System Frequency 1 System Clock Period Loss of Reference Frequency 3 4 Symbol Min. Value 8 8 24 fico(min) ÷ 2RFD — 100 7.4 Vxtal + 0.4v ((VDDE5/2) + 0.4v) Max. Value 20 20 fsys/2 fMAX 2 1 / fsys 1000 17.5 — — Unit MHz fref_crystal fref_ext fref_1:1 fsys tCYC fLOR fSCM VIHEXT VIHEXT 2 3 4 5 6 MHz ns kHz MHz V V Self Clocked Mode (SCM) Frequency EXTAL Input High Voltage Crystal Mode 5 All other modes (Dual Controller (1:1), Bypass, External Reference) 7 EXTAL Input Low Voltage Crystal Mode 6 All other modes (Dual Controller (1:1), Bypass, External Reference) 8 9 10 11 12 13 14 15 16 17 18 19 XTAL Current 7 Total On-chip stray capacitance on XTAL Total On-chip stray capacitance on EXTAL Crystal manufacturer’s recommended capacitive load Discrete load capacitance to be connected to EXTAL Discrete load capacitance to be connected to XTAL PLL Lock Time9 Dual Controller (1:1) Clock Skew (between CLKOUT and EXTAL) 10, 11 Duty Cycle of reference Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, Measured at fSYS Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) 12, 13 VILEXT VILEXT IXTAL CS_XTAL CS_EXTAL CL CL_EXTAL CL_XTAL tlpll tskew tdc fUL fLCK Cjitter — — 0.8 — — See crystal specification — — — –2 40 – 4.0 – 2.0 Vxtal – 0.4v ((VDDE5/2) – 0.4v) 3 1.5 1.5 See crystal specification 2*CL – CS_EXTAL – CPCB_EXTAL8 2*CL – CS_XTAL – CPCB_XTAL8 750 2 60 4.0 2.0 V V mA pF pF pF pF pF µs ns % % fsys % fsys % fclkout — — 5.0 .01 MPC5553 Microcontroller Data Sheet, Rev. 0 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 Electrical Characteristics Table 12. HiP7 FMPLL Electrical Specifications (continued) (VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Num 20 21 22 1 2 Characteristic Frequency Modulation Range Limit 14 (fsysMax must not be exceeded) ICO Frequency. fico=[fref*(MFD+4)]/(PREDIV+1)15 Predivider Output Frequency (to PLL) Symbol Cmod fico fPREDIV Min. Value 0.8 48 4 Max. Value 2.4 fsys fMAX Unit %fsys MHz MHz All internal registers retain data at 0 Hz. Up to the maximum frequency rating of the device (see Table 1). 3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below f LOR. This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed. 5 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vextal – Vxtal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock. 6 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vxtal – Vextal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock. 7I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 8C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively 9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal startup time. 10 PLL is operating in 1:1 PLL mode. 11 VDDE = 3.0 to 3.6V 12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider set to divide-by-2. 13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod. 14 Modulation depth selected must not result in f sys value greater than the fsys maximum specified value. 15 f RFD) sys = fico / (2 3.10 Num 1 2 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications (Operating) Characteristic ADC Clock (ADCLK) Frequency1 Conversion Cycles Differential Single Ended Stop Mode Recovery Time2 Resolution3 INL: 6 MHz ADC Clock INL: 12 MHz ADC Clock Symbol FADCLK CC 13+2 (or 15) 14+2 (or 16) TSR — INL6 INL12 10 1.25 –4 –8 13+128 (or 141) 14+128 (or 142) — — 4 8 Min 1 Max 12 Unit MHz ADCLK cycles µs mV Counts3 Counts 3 4 5 6 MPC5553 Microcontroller Data Sheet, Rev. 0 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 13. eQADC Conversion Specifications (Operating) (continued) Num 7 8 9 10 11 12 Characteristic DNL: 6 MHz ADC Clock DNL: 12 MHz ADC Clock Offset Error with Calibration Full Scale Gain Error with Calibration Disruptive Input Injection Current 7, 8, 9, 10 Symbol DNL6 DNL12 OFFWC GAINWC IINJ EINJ Min –3 4 –6 –4 –8 4 5 6 Max 34 6 4 8 4 5 6 Unit Counts Counts Counts Counts mA Counts –1 –4 1 4 Incremental Error due to injection current. All channels have same 10kΩ < Rs