MPC5602D

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5602D Rev. 3.1, 02/2011 MPC5602D 100 LQFP 14 mm x 14 mm 64 LQFP 10 mm x 10 mm MPC5602D Microcontroller Data Sheet • Single issue, 32-bit CPU core complex (e200z0) — Compliant with the Power Architecture® embedded category — Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. Up to 256 KB on-chip Code Flash supported with Flash controller and ECC 64 KB on-chip Data Flash with ECC Up to 16 KB on-chip SRAM with ECC Interrupt controller (INTC) with multiple interrupt vectors, including 20 external interrupt sources and 18 external interrupt/wakeup sources Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, Flash, or SRAM from multiple bus masters Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) Up to 33 channel 12-bit analog-to-digital converter (ADC) 2 serial peripheral interface (DSPI) modules 3 serial communication interface (LINFlex) modules 1 enhanced full CAN (FlexCAN) module with configurable buffers Up to 79 configurable general purpose pins supporting input and output operations (package dependent) • Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds Up to 4 periodic interrupt timers (PIT) with 32-bit counter resolution 1 System Module Timer (STM) Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class 1 standard Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator (VREG) for regulation of input supply for all internal levels • • • • • • • • • • • • • • • • • • This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009, 2010. All rights reserved. Preliminary—Subject to Change Without Notice Table of Contents 1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .20 4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .20 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21 4.5 Recommended operating conditions . . . . . . . . . . . . . .22 4.6 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .24 4.6.1 Package thermal characteristics . . . . . . . . . . . .24 4.6.2 Power considerations. . . . . . . . . . . . . . . . . . . . .25 4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .25 4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . .26 4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .26 4.7.4 Output pin transition times . . . . . . . . . . . . . . . . .29 4.7.5 I/O pad current specification . . . . . . . . . . . . . . .29 4.8 RESET electrical characteristics. . . . . . . . . . . . . . . . . .34 4.9 Power management electrical characteristics. . . . . . . .36 4.9.1 Voltage regulator electrical characteristics . . . .36 4.9.2 Voltage monitor electrical characteristics. . . . . .38 4.10 Low voltage domain power consumption . . . . . . . . . . .39 4.11 Flash memory electrical characteristics . . . . . . . . . . . 40 4.11.1 Program/Erase characteristics . . . . . . . . . . . . . 40 4.11.2 Flash power supply DC characteristics . . . . . . 42 4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 43 4.12 Electromagnetic compatibility (EMC) characteristics. . 43 4.12.1 Designing hardened software to avoid noise problems. . . . . . . . . . . . . . . . . . . . . . . . 44 4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 44 4.12.3 Absolute maximum ratings (electrical sensitivity)44 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 49 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 52 4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.17.2 Input impedance and ADC accuracy . . . . . . . . 52 4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 57 4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 60 4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 62 4.18.3 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 68 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 69 5.1.1 100 LQFP mechanical outline drawing. . . . . . . 69 5.1.2 64 LQFP mechanical outline drawing. . . . . . . . 73 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4 5 6 MPC5602D Microcontroller Data Sheet, Rev. 3.1 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor Introduction 1 1.1 1.2 Introduction Document overview Description This document describes the device features and highlights the important electrical and physical characteristics. These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications. This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications. The advanced and cost-efficient e200z0 host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations. The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory. Table 1. MPC5602D device comparison Device Feature MPC5601DxLH CPU Execution speed Code Flash Data Flash SRAM eDMA ADC CTU Total timer I/O eMIOS • Type X2 • Type Y 3 1 MPC5601DxLL MPC5602DxLH e200z0 MPC5602DxLL Static – up to 48 MHz 128 KB 64 KB (4 × 16 KB) 12 KB 16 ch 16 ch, 12-bit 33 ch, 12-bit 16 ch 13 ch, 16-bit 2 ch — 7 ch 4 ch 28 ch, 16-bit 5 ch 9 ch 7 ch 7 ch 3 2 1 45 79 45 79 13 ch, 16-bit 2 ch — 7 ch 4 ch 28 ch, 16-bit 5 ch 9 ch 7 ch 7 ch 16 ch, 12-bit 33 ch, 12-bit 16 KB 256 KB • Type G4 • Type H 5 SCI (LINFlex) SPI (DSPI) CAN (FlexCAN) GPIO6 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3 Introduction Table 1. MPC5602D device comparison (continued) Device Feature MPC5601DxLH Debug Package 1 2 3 4 5 6 MPC5601DxLL JTAG MPC5602DxLH MPC5602DxLL 64 LQFP 100 LQFP 64 LQFP 100 LQFP Refer to eMIOS section of device reference manual for information on the channel configuration and functions. Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC Type Y = OPWMT + OPWMB + SAIC + SAOC Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC I/O count based on multiplexing with peripherals MPC5602D Microcontroller Data Sheet, Rev. 3.1 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor Block diagram 2 Block diagram Figure 1. MPC5602D series block diagram JTAG JTAG Port Instructions Nexus 1 e200z0h NMI SIUL Voltage Regulator NMI Interrupt requests from peripheral blocks INTC Clocks FMPLL CMU eDMA (Master) Data (Master) (Master) 64-bit 3 x 3 Crossbar Switch SRAM 16 KB Code Flash 256 KB Data Flash 64 KB Figure 1 shows a top-level block diagram of the MPC5602D device series. SRAM Controller Flash Controller (Slave) (Slave) (Slave) RTC STM SWT ECSM PIT MC_RGM MC_CGM MC_ME MC_PCU BAM SSCM Peripheral Bridge Interrupt Request SIUL Reset Control External Interrupt Request IMUX GPIO & Pad Control 33 ch. ADC CTU 1x eMIOS 3x LINFlex 2x DSPI 1x FlexCAN WKPU Interrupt Request I/O Legend: ADC BAM CMU CTU DSPI ECSM eDMA eMIOS Flash FlexCAN FMPLL IMUX INTC JTAG LINFlex ... ... ... ... Analog-to-Digital Converter Boot Assist Module Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Error Correction Status Module Enhanced Direct Memory Access Enhanced Modular Input Output System Flash memory Controller Area Network (FlexCAN) Frequency-Modulated Phase-Locked Loop Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) MC_CGM MC_ME MC_PCU MC_RGM NMI PIT RTC SIUL SRAM SSCM STM SWT WKPU XBAR Clock Generation Module Mode Entry Module Power Control Unit Reset Generation Module Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit Crossbar switch MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 5 Block diagram Table 2 summarizes the functions of all blocks present in the MPC5602D series of microcontrollers. Please note that the presence and number of blocks varies by device and package. Table 2. MPC5602D series block summary Block Function Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to digital-converter Boot assist module (BAM) Clock monitor unit (CMU) Cross triggering unit (CTU) Crossbar switch (XBAR) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Monitors clock source (internal and external) integrity Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor (eDMA) via “n” programmable channels. Enhanced modular input output system (eMIOS) Flash memory Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phase-locked loop (FMPLL) Internal multiplexer (IMUX) SIU subblock Interrupt controller (INTC) JTAG controller LINFlex controller Clock generation module (MC_CGM) Mode entry module (MC_ME) Generates high-speed system clocks and supports programmable frequency modulation Allows flexible mapping of peripheral interface on the different pins of the device Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Provides logic and control required for the generation of system and peripheral clocks Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU Power control unit (MC_PCU) MPC5602D Microcontroller Data Sheet, Rev. 3.1 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 2. MPC5602D series block summary (continued) Block Reset generation module (MC_RGM) Non-Maskable Interrupt (NMI) Periodic interrupt timer (PIT) Real-time counter (RTC) Function Centralizes reset sources and manages the device reset sequence of the device Handles external events that must produce an immediate response, such as power down detection Produces periodic interrupts and triggers Provides a free-running counter and interrupt generation capability that can be used for timekeeping applications System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Static random-access memory (SRAM) System status and configuration module (SSCM) System timer module (STM) System watchdog timer (SWT) Wakeup Unit (WKPU) Provides storage for program code, constants, and variables Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable Provides a set of output compare events to support AUTOSAR and operating system tasks Provides protection from runaway code Supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. 3 3.1 Package pinouts and signal descriptions Package pinouts The available LQFP pinouts are provided in the following figures. For pin signal descriptions, please refer to Table 3. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7 Package pinouts and signal descriptions Figure 2 shows the MPC5602D in the 100 LQFP package. Figure 2. 100 LQFP pin configuration (top view) PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12] 100 LQFP PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC MPC5602D Microcontroller Data Sheet, Rev. 3.1 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Package pinouts and signal descriptions Figure 3 shows the MPC5602D in the 64 LQFP package. Figure 3. 64 LQFP pin configuration (top view) PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC 3.2 Pin muxing Table 3 defines the pin list and muxing for this device. Each entry of Table 3 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0. Table 3. Functional port pin descriptions Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PA[0] PCR[0] AF0 AF1 AF2 AF3 — GPIO[0] E0UC[0] CLKOUT E0UC[13] WKUP[19]3 PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Port A SIUL eMIOS_0 CGL eMIOS_0 WKPU I/O I/O O I/O I M Tristate 5 12 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PA[1] PCR register PCR[1] Alternate function1 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — —‘ AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — N/A5 Function Pad RESET I/O Peripheral direction2 type config. SIUL eMIOS_0 — — WKPU WKPU SIUL eMIOS_0 — — WKPU SIUL eMIOS_0 — — SIUL ADC SIUL eMIOS_0 — — WKPU SIUL eMIOS_0 — — SIUL eMIOS_0 — — SIUL SIUL eMIOS_0 — — SIUL ADC SIUL eMIOS_0 eMIOS_0 — SIUL BAM I/O I/O — — I I I/O I/O — — I I/O I/O — — I I I/O I/O — — I I/O I/O — — I/O I/O — — I I/O I/O — — I I I/O I/O — — I I S Tristate 4 64 LQFP 7 100 LQFP GPIO[1] E0UC[1] — — NMI4 WKUP[2]3 GPIO[2] E0UC[2] — — WKUP[3]3 GPIO[3] E0UC[3] — — EIRQ[0] ADC1_S[0] GPIO[4] E0UC[4] — — WKUP[9]3 GPIO[5] E0UC[5] — — GPIO[6] E0UC[6] — — EIRQ[1] GPIO[7] E0UC[7] — — EIRQ[2] ADC1_S[1] GPIO[8] E0UC[8] E0UC[14] — EIRQ[3] ABS[0] PA[2] PCR[2] S Tristate 3 5 PA[3] PCR[3] S Tristate 43 68 PA[4] PCR[4] S Tristate 20 29 PA[5] PCR[5] M Tristate 51 79 PA[6] PCR[6] S Tristate 52 80 PA[7] PCR[7] S Tristate 44 71 PA[8] PCR[8] S Input, weak pull-up 45 72 MPC5602D Microcontroller Data Sheet, Rev. 3.1 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PA[9] PCR register PCR[9] Alternate function1 AF0 AF1 AF2 AF3 N/A5 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — Function Pad RESET I/O Peripheral direction2 type config. SIUL eMIOS_0 — — BAM SIUL eMIOS_0 — LINFlex_1 ADC SIUL eMIOS_0 — — SIUL ADC LINFlex_2 SIUL — — — SIUL DSPI_0 SIUL DSPI_0 — — SIUL DSPI_0 DSPI_0 eMIOS_0 SIUL SIUL DSPI_0 DSPI_0 eMIOS_0 WKPU I/O I/O — — I I/O I/O — O I I/O I/O — — I I I I/O — — — I I I/O O — — I/O I/O I/O I/O I I/O I/O I/O I/O I S Pulldown 64 LQFP 46 100 LQFP 73 GPIO[9] E0UC[9] — — FAB GPIO[10] E0UC[10] — LIN1TX ADC1_S[2] GPIO[11] E0UC[11] — — EIRQ[16] ADC1_S[3] LIN2RX GPIO[12] — — — EIRQ[17] SIN_0 GPIO[13] SOUT_0 — — GPIO[14] SCK_0 CS0_0 E0UC[0] EIRQ[4] GPIO[15] CS0_0 SCK_0 E0UC[1] WKUP[10]3 PA[10] PCR[10] S Tristate 47 74 PA[11] PCR[11] S Tristate 48 75 PA[12] PCR[12] S Tristate 22 31 PA[13] PCR[13] M Tristate 21 30 PA[14] PCR[14] M Tristate 19 28 PA[15] PCR[15] M Tristate 18 27 Port B PB[0] PCR[16] AF0 AF1 AF2 AF3 GPIO[16] CAN0TX — — SIUL FlexCAN_0 — — I/O O — — M Tristate 14 23 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PB[1] PCR register PCR[17] Alternate function1 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — Function Pad RESET I/O Peripheral direction2 type config. SIUL — — — WKPU FlexCAN_0 SIUL LINFlex_0 — — SIUL — — — WKPU LINFlex_0 SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC WKPU I/O — — — I I I/O O — — I/O — — — I I I — — — I I — — — I I — — — I I — — — I I — — — I I S 64 LQFP 100 LQFP 24 GPIO[17] — — — WKUP[4]3 CAN0RX GPIO[18] LIN0TX — — GPIO[19] — — — WKUP[11]3 LIN0RX GPIO[20] — — — ADC1_P[0] GPIO[21] — — — ADC1_P[1] GPIO[22] — — — ADC1_P[2] GPIO[23] — — — ADC1_P[3] GPIO[24] — — — ADC1_S[4] WKUP[25]3 Tristate 15 PB[2] PCR[18] M Tristate 64 100 PB[3] PCR[19] S Tristate 1 1 PB[4] PCR[20] I Tristate 32 50 PB[5] PCR[21] I Tristate 35 53 PB[6] PCR[22] I Tristate 36 54 PB[7] PCR[23] I Tristate 37 55 PB[8] PCR[24] I Tristate 30 39 MPC5602D Microcontroller Data Sheet, Rev. 3.1 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PB[9] PCR register PCR[25] Alternate function1 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — Function Pad RESET I/O Peripheral direction2 type config. SIUL — — — ADC WKPU SIUL — — — ADC WKPU SIUL eMIOS_0 — DSPI_0 ADC SIUL eMIOS_0 — DSPI_0 ADC SIUL eMIOS_0 — DSPI_0 ADC SIUL eMIOS_0 — DSPI_0 ADC SIUL eMIOS_0 — DSPI_0 ADC I — — — I I I/O — — — I I I/O I/O — I/O I I/O I/O — O I I/O I/O — O I I/O I/O — O I I/O I/O — O I I 64 LQFP 100 LQFP 38 GPIO[25] — — — ADC1_S[5] WKUP[26]3 GPIO[26] — — — ADC1_S[6] WKUP[8]3 GPIO[27] E0UC[3] — CS0_0 ADC1_S[12] GPIO[28] E0UC[4] — CS1_0 ADC1_X[0] GPIO[29] E0UC[5] — CS2_0 ADC1_X[1] GPIO[30] E0UC[6] — CS3_0 ADC1_X[2] GPIO[31] E0UC[7] — CS4_0 ADC1_X[3] Tristate 29 PB[10] PCR[26] J Tristate 31 40 PB[11] PCR[27] J Tristate 38 59 PB[12] PCR[28] J Tristate 39 61 PB[13] PCR[29] J Tristate 40 63 PB[14] PCR[30] J Tristate 41 65 PB[15] PCR[31] J Tristate 42 67 Port C PC[0]6 PCR[32] AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 GPIO[32] — TDI — GPIO[33] — TDO — SIUL — JTAGC — SIUL — JTAGC — I/O — I — I/O — O — M Input, weak pull-up 59 87 PC[1]6 PCR[33] F Tristate 54 82 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PC[2] PCR register PCR[34] Alternate function1 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 Function Pad RESET I/O Peripheral direction2 type config. SIUL DSPI_1 — — SIUL SIUL DSPI_1 ADC — SIUL SIUL — — — DSPI_1 SIUL SIUL DSPI_1 — — SIUL SIUL LINFlex_1 — — SIUL — — — LINFlex_1 WKPU SIUL LINFlex_2 — — SIUL — — — LINFlex_2 WKPU SIUL — — ADC I/O I/O — — I I/O I/O O — I I/O — — — I I I/O O — — I I/O O — — I/O — — — I I I/O O — — I/O — — — I I I/O — — O M 64 LQFP 100 LQFP 78 GPIO[34] SCK_1 — — EIRQ[5] GPIO[35] CS0_1 MA[0] — EIRQ[6] GPIO[36] — — — SIN_1 EIRQ[18] GPIO[37] SOUT_1 — — EIRQ[7] GPIO[38] LIN1TX — — GPIO[39] — — — LIN1RX WKUP[12]3 GPIO[40] LIN2TX — — GPIO[41] — — — LIN2RX WKUP[13]3 GPIO[42] — — MA[1] Tristate 50 PC[3] PCR[35] S Tristate 49 77 PC[4] PCR[36] M Tristate 62 92 PC[5] PCR[37] M Tristate 61 91 PC[6] PCR[38] S Tristate 16 25 PC[7] PCR[39] S Tristate 17 26 PC[8] PCR[40] S Tristate 63 99 PC[9] PCR[41] S Tristate 2 2 PC[10] PCR[42] M Tristate 13 22 MPC5602D Microcontroller Data Sheet, Rev. 3.1 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PC[11] PCR register PCR[43] Alternate function1 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — Function Pad RESET I/O Peripheral direction2 type config. SIUL — — ADC WKPU SIUL eMIOS_0 — — SIUL SIUL eMIOS_0 — — SIUL eMIOS_0 — — SIUL SIUL eMIOS_0 — — SIUL I/O — — O I I/O I/O — — I I/O I/O — — I/O I/O — — I I/O I/O — — I S 64 LQFP 100 LQFP 21 GPIO[43] — — MA[2] WKUP[5]3 GPIO[44] E0UC[12] — — EIRQ[19] GPIO[45] E0UC[13] — — GPIO[46] E0UC[14] — — EIRQ[8] GPIO[47] E0UC[15] — — EIRQ[20] Tristate — PC[12] PCR[44] M Tristate — 97 PC[13] PCR[45] S Tristate — 98 PC[14] PCR[46] S Tristate — 3 PC[15] PCR[47] M Tristate — 4 Port D PD[0] PCR[48] AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — GPIO[48] — — — WKUP[27]3 ADC1_P[4] GPIO[49] — — — WKUP[28]3 ADC1_P[5] GPIO[50] — — — ADC1_P[6] SIUL — — — WKPU ADC SIUL — — — WKPU ADC SIUL — — — ADC I — — — I I I — — — I I I — — — I I Tristate — 41 PD[1] PCR[49] I Tristate — 42 PD[2] PCR[50] I Tristate — 43 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PD[3] PCR register PCR[51] Alternate function1 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — Function Pad RESET I/O Peripheral direction2 type config. SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I I 64 LQFP 100 LQFP 44 GPIO[51] — — — ADC1_P[7] GPIO[52] — — — ADC1_P[8] GPIO[53] — — — ADC1_P[9] GPIO[54] — — — ADC1_P[10] GPIO[55] — — — ADC1_P[11] GPIO[56] — — — ADC1_P[12] GPIO[57] — — — ADC1_P[13] GPIO[58] — — — ADC1_P[14] GPIO[59] — — — ADC1_P[15] Tristate — PD[4] PCR[52] I Tristate — 45 PD[5] PCR[53] I Tristate — 46 PD[6] PCR[54] I Tristate — 47 PD[7] PCR[55] I Tristate — 48 PD[8] PCR[56] I Tristate — 49 PD[9] PCR[57] I Tristate — 56 PD[10] PCR[58] I Tristate — 57 PD[11] PCR[59] I Tristate — 58 MPC5602D Microcontroller Data Sheet, Rev. 3.1 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PD[12] PCR register PCR[60] Alternate function1 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — Function Pad RESET I/O Peripheral direction2 type config. SIUL DSPI_0 eMIOS_0 — ADC SIUL DSPI_1 eMIOS_0 — ADC SIUL DSPI_1 eMIOS_0 — ADC SIUL DSPI_1 eMIOS_0 — ADC I/O O I/O — I I/O I/O I/O — I I/O O I/O — I I/O O I/O — I J 64 LQFP 100 LQFP 60 GPIO[60] CS5_0 E0UC[24] — ADC1_S[8] GPIO[61] CS0_1 E0UC[25] — ADC1_S[9] GPIO[62] CS1_1 E0UC[26] — ADC1_S[10] GPIO[63] CS2_1 E0UC[27] — ADC1_S[11] Tristate — PD[13] PCR[61] J Tristate — 62 PD[14] PCR[62] J Tristate — 64 PD[15] PCR[63] J Tristate — 66 Port E PE[0] PCR[64] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — GPIO[64] E0UC[16] — — WKUP[6]3 GPIO[65] E0UC[17] — — GPIO[66] E0UC[18] — — EIRQ[21] SIN_1 GPIO[67] E0UC[19] SOUT_1 — GPIO[68] E0UC[20] SCK_1 — EIRQ[9] SIUL eMIOS_0 — — WKPU SIUL eMIOS_0 — — SIUL eMIOS_0 — — SIUL DSPI_1 SIUL eMIOS_0 DSPI_1 — SIUL eMIOS_0 DSPI_1 — SIUL I/O I/O — — I I/O I/O — — I/O I/O — — I I I/O I/O O — I/O I/O I/O — I S Tristate — 6 PE[1] PCR[65] M Tristate — 8 PE[2] PCR[66] M Tristate — 89 PE[3] PCR[67] M Tristate — 90 PE[4] PCR[68] M Tristate — 93 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PE[5] PCR register PCR[69] Alternate function1 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — Function Pad RESET I/O Peripheral direction2 type config. SIUL eMIOS_0 DSPI_1 ADC SIUL eMIOS_0 DSPI_0 ADC SIUL SIUL eMIOS_0 DSPI_0 ADC SIUL SIUL — eMIOS_0 — SIUL — eMIOS_0 — WKPU SIUL — DSPI_1 — SIUL SIUL eMIOS_0 DSPI_1 — WKPU SIUL — — — ADC SIUL I/O I/O I/O O I/O I/O O O I I/O I/O O O I I/O — I/O — I/O — I/O — I I/O — O — I I/O I/O O — I I/O — — — I I M 64 LQFP 100 LQFP 94 GPIO[69] E0UC[21] CS0_1 MA[2] GPIO[70] E0UC[22] CS3_0 MA[1] EIRQ[21] GPIO[71] E0UC[23] CS2_0 MA[0] EIRQ[21] GPIO[72] — E0UC[22] — GPIO[73] — E0UC[23] — WKUP[7]3 GPIO[74] — CS3_1 — EIRQ[10] GPIO[75] E0UC[24] CS4_1 — WKUP[14]3 GPIO[76] — — — ADC1_S[7] EIRQ[11] Tristate — PE[6] PCR[70] M Tristate — 95 PE[7] PCR[71] M Tristate — 96 PE[8] PCR[72] M Tristate — 9 PE[9] PCR[73] S Tristate — 10 PE[10] PCR[74] S Tristate — 11 PE[11] PCR[75] S Tristate — 13 PE[12] PCR[76] S Tristate — 76 Port H PH[9]6 PCR[121] AF0 AF1 AF2 AF3 GPIO[121] — TCK — SIUL — JTAGC — I/O — I — S Input, weak pull-up 60 88 MPC5602D Microcontroller Data Sheet, Rev. 3.1 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. SIUL — JTAGC — I/O — I — S Input, weak pull-up 64 LQFP 53 100 LQFP 81 PH[10]6 PCR[122] AF0 AF1 AF2 AF3 1 GPIO[122] — TMS — 2 3 4 5 6 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00  AF0; PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. All WKUP pins also support external interrupt capability. See “wakeup unit” chapter for further details. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. “Not applicable” because these functions are available only while the device is booting. Refer to “BAM” chapter of the device reference manual for details. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed. 4 4.1 Electrical characteristics Introduction This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This can be done by the internal pull-up or pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column. CAUTION All of the following parameter values can vary depending on the application and must be confirmed during silicon validation, silicon characterization or silicon reliability trial. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 Electrical characteristics 4.2 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 4 are used and the parameters are tagged accordingly in the tables where appropriate. Table 4. Parameter classifications Classification tag P C T Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. D NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 4.3 NVUSRO register Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the non-volatile user options register (NVUSRO) register. For a detailed description of the NVUSRO register, please refer to the MPC5602D reference manual. 4.3.1 NVUSRO[PAD3V5V] field description Table 5. PAD3V5V field description1 Value2 0 1 1 2 Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration. Description High voltage supply is 5.0 V High voltage supply is 3.3 V See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V bit value. 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. MPC5602D Microcontroller Data Sheet, Rev. 3.1 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 6. OSCILLATOR_MARGIN field description1 Value2 0 1 1 2 Description Low consumption configuration (4 MHz/8 MHz) High margin configuration (4 MHz/16 MHz) See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. 4.4 Absolute maximum ratings Table 7. Absolute maximum ratings Value Symbol VSS VDD VSS_LV VDD_BV C Parameter Conditions Min SR — Digital ground on VSS_HV pins SR — Voltage on VDD_HV pins with respect to ground (VSS) SR — Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR — Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) — — — — Relative to VDD — — Relative to VDD — Relative to VDD — — VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 ICORELV SR — Low voltage static current sink through VDD_BV — — 0 0.3 Max 0 6.0 V V V V Unit VSS  0.1 VSS + 0.1 0.3 6.0 VDD  0.3 VDD + 0.3 VSS  0.1 VSS + 0.1 0.3 6.0 V V VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) VDD_ADC SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) VIN SR — Voltage on any GPIO pin with respect to ground (VSS) SR — Injected input current on any pin during overload condition SR — Absolute sum of all injected input currents during overload condition VDD  0.3 VDD + 0.3 0.3 6.0 V VDD  0.3 VDD + 0.3 10 50 — — — 55 10 50 70 64 150 150 mA °C mA mA mA IINJPAD IINJSUM IAVGSEG SR — Sum of all the static I/O current within a supply segment1 TSTORAGE SR — Storage temperature 1 Supply segments are described in Section 4.7.5, “I/O pad current specification. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 21 Electrical characteristics NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. 4.5 Recommended operating conditions Table 8. Recommended operating conditions (3.3 V) Value Symbol VSS VDD1 VSS_LV2 C Parameter Conditions Min SR — Digital ground on VSS_HV pins SR — Voltage on VDD_HV pins with respect to ground (VSS) SR — Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) — — — — 0 3.0 Max 0 3.6 V V V V Unit VSS  0.1 VSS + 0.1 3.0 3.6 VDD_BV3 SR — Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) VDD_ADC4 SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) VIN SR — Voltage on any GPIO pin with respect to ground (VSS) SR — Injected input current on any pin during overload condition SR — Absolute sum of all injected input currents during overload condition SR — VDD slope to ensure correct power up6 SR — Ambient temperature under bias SR — Junction temperature under bias Relative to VDD VDD  0.1 VDD + 0.1 — — VSS  0.1 VSS + 0.1 3.05 3.6 V V Relative to VDD VDD  0.1 VDD + 0.1 — Relative to VDD — — — fCPU  48 MHz — VSS  0.1 — 5 50 TBD 40 40 — VDD + 0.1 5 50 0.25 125 150 mA mA V/µs °C V IINJPAD IINJSUM TVDD TA TJ 1 2 3 4 5 6 100 nF capacitance needs to be provided between each VDD/VSS pair. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. Guaranteed by device validation MPC5602D Microcontroller Data Sheet, Rev. 3.1 22 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 9. Recommended operating conditions (5.0 V) Value Symbol VSS VDD1 VSS_LV3 C Parameter Conditions Min SR — Digital ground on VSS_HV pins SR — Voltage on VDD_HV pins with respect to ground (VSS) SR — Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) — — Voltage drop2 — — Voltage drop (2) Unit Max 0 5.5 5.5 V V V V 0 4.5 3.0 VSS  0.1 VSS + 0.1 4.5 3.0 5.5 5.5 VDD_BV4 SR — Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Relative to VDD VDD  0.1 VDD + 0.1 VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS VDD_ADC5 SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) — — Voltage drop (2) VSS  0.1 VSS + 0.1 4.5 3.0 5.5 5.5 V V Relative to VDD VDD  0.1 VDD + 0.1 VIN SR — Voltage on any GPIO pin with respect to ground (VSS) SR — Injected input current on any pin during overload condition SR — Absolute sum of all injected input currents during overload condition SR — VDD slope to ensure correct power up6 SR — Ambient temperature under bias SR — Junction temperature under bias — Relative to VDD — — — fCPU  48 MHz — VSS  0.1 — 5 50 TBD 40 40 — VDD + 0.1 5 50 0.25 125 150 V/µs °C mA V IINJPAD IINJSUM TVDD TA TJ 1 2 3 4 5 6 100 nF capacitance needs to be provided between each VDD/VSS pair. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Guaranteed by device validation NOTE SRAM data retention is guaranteed with VDD_LV not below 1.08 V. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23 Electrical characteristics 4.6 4.6.1 Thermal characteristics Package thermal characteristics Table 10. LQFP thermal characteristics1 Symbol RJA CC C D Parameter Thermal resistance, junction-to-ambient natural convection4 Conditions2 Single-layer board —1s Pin count 64 100 Four-layer board — 2s2p 64 100 RJB CC D Thermal resistance, junction-to-board5 Single-layer board — 1s 64 100 Four-layer board — 2s2p 64 100 RJC CC D Thermal resistance, junction-to-case6 Single-layer board — 1s 64 100 Four-layer board — 2s2p 64 100 JB CC D Junction-to-board thermal characterization parameter, natural convection Single-layer board — 1s 64 100 Four-layer board — 2s2p 64 100 JC CC D Junction-to-case thermal characterization parameter, natural convection Single-layer board — 1s 64 100 Four-layer board — 2s2p 64 100 1 2 3 4 Value3 72.1 65.2 57.3 51.8 45.6 42.6 44.1 41.3 26.5 23.9 26.2 23.7 41 41.6 43 43.4 11.5 10.4 11.1 10.2 Unit °C/W °C/W °C/W °C/W °C/W 5 6 Thermal characteristics are targets based on simulation that are subject to change per device characterization. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C All values need to be confirmed during device validation. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters are not available, the symbols are typed as RthJC. MPC5602D Microcontroller Data Sheet, Rev. 3.1 24 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 4.6.2 Power considerations TJ = TA + (PD x RJA) Where: TA is the ambient temperature in °C. RJA is the package junction-to-ambient thermal resistance, in °C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Eqn. 1 The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 °C) Therefore, solving equations 1 and 2: K = PD x (TA + 273 °C) + RJA x PD2 Eqn. 3 Eqn. 2 Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA. 4.7 4.7.1 • • • I/O pad electrical characteristics I/O pad types Slow pads—These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads—These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Input only pads—These pads are associated to ADC channels (ADC_P[X]) providing low input leakage. The device provides four main I/O pad types depending on the associated alternate functions: Medium pads can use slow configuration to reduce electromagnetic emission except for PC[1], that is medium only, at the cost of reducing AC performance. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25 Electrical characteristics 4.7.2 I/O input DC characteristics Figure 4. I/O input DC electrical characteristics definition VIN VDD VIH Table 11 provides input DC electrical characteristics as described in Figure 4. VHYS VIL PDIx = ‘1’ (GPDI register of SIUL) PDIx = ‘0’ Table 11. I/O input DC electrical characteristics Symbol VIH VIL C Parameter Conditions1 Min SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) — — — No injection on adjacent pin TA = 40 °C TA = 25 °C TA = 105 °C TA = 125 °C — — 0.65VDD 0.4 0.1VDD — — — — — 1000 Value2 Unit Typ — — — 2 2 12 70 — — Max VDD+0.4 0.35VDD — — — 500 1000 40 — ns ns nA V VHYS CC C Input hysteresis CMOS (Schmitt Trigger) ILKG CC P Digital input leakage P D P WFI 1 2 3 SR P Digital input filtered pulse WNFI3 SR P Digital input not filtered pulse VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. 4.7.3 I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads: MPC5602D Microcontroller Data Sheet, Rev. 3.1 26 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics • • • Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 13 provides output driver characteristics for I/O pads when in SLOW configuration. Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 12. I/O pull-up/pull-down DC electrical characteristics Symbol C Parameter Conditions1 VIN = VIL, PAD3V5V = 0 VDD = 5.0 V ± 10% PAD3V5V = 12 PAD3V5V = 1 VIN = VIL, VDD = 3.3 V ± 10% VIN = VIH, PAD3V5V = 0 VDD = 5.0 V ± 10% PAD3V5V = 12 VIN = VIH, PAD3V5V = 1 VDD = 3.3 V ± 10% 10 10 10 10 10 10 Value Unit Min Typ Max |IWPU| CC P Weak pull-up current absolute value C P |IWPD| CC P Weak pull-down current absolute value C P 1 2 — — — — — — 150 250 150 150 250 150 µA µA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. Table 13. SLOW configuration output buffer electrical characteristics Symbol C Parameter Conditions1 Min Push Pull IOH = 2 mA, VOH CC P Output high level SLOW configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) C C IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) 0.8VDD Value Unit Typ — Max — V 0.8VDD VDD  0.8 — — — — VOL CC P Output low level Push Pull IOL = 2 mA, SLOW configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) C C IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(2) IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — — 0.1VDD V — — — 0.1VDD — 0.5 1 2 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 27 Electrical characteristics Table 14. MEDIUM configuration output buffer electrical characteristics Symbol C Parameter Conditions1 Min Push Pull IOH = 3.8 mA, VOH CC C Output high level MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 P IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOH = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) IOH = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD 0.8VDD Value Unit Typ — — Max — — V C C 0.8VDD — — — VDD  0.8 — C 0.8VDD — — — — V VOL CC C Output low level Push Pull IOL = 3.8 mA, MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 P IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(2) IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) IOH = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 — 0.2VDD — 0.1VDD C C — — — 0.1VDD — 0.5 C 1 2 — — 0.1VDD VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. MPC5602D Microcontroller Data Sheet, Rev. 3.1 28 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 4.7.4 Output pin transition times Table 15. Output pin transition times Value2 Unit Min Typ Max — 50 ns Symbol C Parameter Conditions1 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — VDD = 5.0 V ± 10%, PAD3V5V = 0 — SIUL.PCRx.SRC = 1 — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — SIUL.PCRx.SRC = 1 — — Ttr CC D Output transition time output pin3 CL = 25 pF SLOW configuration T CL = 50 pF D D T D CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF — 100 — 125 — 50 — 100 — 125 — — — — — — 10 20 40 12 25 40 ns Ttr CC D Output transition time output pin(3) CL = 25 pF MEDIUM configuration T CL = 50 pF D D T D 1 2 CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 C includes device and package capacitances (C L PKG < 5 pF). 4.7.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 16. Table 17 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. Table 16. I/O supply segment Supply segment Package 1 100 LQFP 64 LQFP pin 16 – pin 35 pin 8 – pin 26 2 pin 37 – pin 69 pin 28 – pin 55 3 pin 70 – pin 83 pin 56 – pin 7 4 pin 84 – pin 15 — MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 29 Electrical characteristics Table 17. I/O consumption Symbol ISWTSLW,3 C Parameter CL = 25 pF Conditions1 Min CC D Dynamic I/O current for SLOW configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — — — — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — — — — — — — — — Value2 Unit Typ — — — — — — — — — — — — — — — — — — Max 20 16 29 17 2.3 3.2 6.6 1.6 2.3 4.7 6.6 13.4 18.3 5 8.5 11 70 65 mA mA mA mA mA ISWTMED(3) CC D Dynamic I/O current for MEDIUM configuration IRMSSLW CC D Root medium square CL = 25 pF, 2 MHz I/O current for SLOW CL = 25 pF, 4 MHz configuration CL = 100 pF, 2 MHz CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz CL = 100 pF, 2 MHz IRMSMED CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%, I/O current for PAD3V5V = 0 CL = 25 pF, 40 MHz MEDIUM configuration CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz CL = 100 pF, 13 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 IAVGSEG SR D Sum of all the static I/O current within a supply segment VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 2 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. 1 Table 18 provides the weight of concurrent switching I/Os. In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below 100%. MPC5602D Microcontroller Data Sheet, Rev. 3.1 30 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 18. I/O weight1 100/64 LQFP PAD Weight 5V SRC = 0 9% 8% 8% 8% 8% 7% 7% 7% 6% 6% 6% 5% 5% 7% 8% 8% 8% 8% 8% 8% 7% 7% 7% 7% 1% 1% 5% 1% 1% 1% 1% 1% 1% Weight 5V SRC = 1 9% 8% 8% 11% 8% 7% 7% 10% 9% 6% 6% 7% 5% 7% 11% 11% 8% 8% 8% 11% 11% 7% 10% 7% 1% 1% 5% 1% 1% 1% 1% 1% 1% Weight 3.3V SRC = 0 10% 10% 10% 9% 9% 9% 8% 8% 8% 7% 7% 6% 6% 9% 9% 9% 10% 10% 10% 9% 9% 8% 8% 8% 1% 1% 6% 1% 1% 1% 1% 1% 1% Weight 3.3V SRC = 1 10% 10% 10% 10% 9% 9% 8% 8% 8% 7% 7% 7% 6% 9% 10% 10% 10% 10% 10% 10% 9% 8% 9% 8% 1% 1% 6% 1% 1% 1% 1% 1% 1% PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] PC[11] PC[10] PB[0] PB[1] PC[6] PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 31 Electrical characteristics Table 18. I/O weight1 (continued) 100/64 LQFP PAD Weight 5V SRC = 0 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 9% 8% 8% 8% 8% 7% 7% 7% 6% 6% 4% 4% 4% 5% 5% 5% 5% 5% 5% 4% 5% 6% 7% Weight 5V SRC = 1 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 9% 8% 8% 8% 8% 7% 7% 7% 6% 6% 4% 4% 4% 5% 5% 5% 5% 7% 6% 4% 17% 9% 10% Weight 3.3V SRC = 0 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 11% 10% 10% 9% 9% 9% 8% 8% 7% 7% 5% 5% 5% 6% 6% 6% 6% 6% 5% 5% 4% 7% 8% Weight 3.3V SRC = 1 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 11% 10% 10% 9% 9% 9% 8% 8% 7% 7% 5% 5% 5% 6% 6% 6% 6% 6% 6% 5% 12% 8% 9% PD[6] PD[7] PD[8] PB[4] PB[5] PB[6] PB[7] PD[9] PD[10] PD[11] PB[11] PD[12] PB[12] PD[13] PB[13] PD[14] PB[14] PD[15] PB[15] PA[3] PA[7] PA[8] PA[9] PA[10] PA[11] PE[12] PC[3] PC[2] PA[5] PA[6] PC[1] PC[0] PE[2] MPC5602D Microcontroller Data Sheet, Rev. 3.1 32 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 18. I/O weight1 (continued) 100/64 LQFP PAD Weight 5V SRC = 0 7% 8% 8% 8% 8% 9% 9% 9% 9% 9% 9% Weight 5V SRC = 1 10% 11% 11% 12% 12% 12% 12% 13% 9% 9% 13% Weight 3.3V SRC = 0 9% 9% 9% 10% 10% 10% 10% 11% 11% 11% 11% Weight 3.3V SRC = 1 9% 10% 10% 10% 11% 11% 11% 11% 11% 11% 12% PE[3] PC[5] PC[4] PE[4] PE[5] PE[6] PE[7] PC[12] PC[13] PC[8] PB[2] 1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 33 Electrical characteristics 4.8 RESET electrical characteristics Figure 5. Start-up reset requirements VDD VDDMIN The device implements a dedicated bidirectional RESET pin. RESET VIH VIL device reset forced by RESET device start-up phase Figure 6. Noise filtering on reset signal VRESET hw_rst VDD ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset MPC5602D Microcontroller Data Sheet, Rev. 3.1 34 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 19. Reset electrical characteristics Symbol VIH VIL VHYS VOL C Parameter Conditions1 Min SR P Input High Level CMOS (Schmitt Trigger) SR P Input low Level CMOS (Schmitt Trigger) CC C Input hysteresis CMOS (Schmitt Trigger) CC P Output low level — — — Push Pull, IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 13 Push Pull, IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) Ttr CC D Output transition time output pin4 MEDIUM configuration CL = 25 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 50 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 100 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 50 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 WFRST SR P RESET input filtered pulse WNFRST SR P RESET input not filtered pulse |IWPU| CC P Weak pull-up current absolute value — — VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 5.0 V ± 10%, PAD3V5V = 15 1 2 Value2 Unit Typ — — — — Max VDD + 0.4 0.35VDD — 0.1VDD V V V V 0.65VDD 0.4 0.1VDD — — — — — 0.1VDD 0.5 — — — — — — — 1000 10 10 10 — — — — — — — — — — — 10 20 40 12 25 40 40 — 150 150 250 ns ns ns µA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the device reference manual). 4 CL includes device and package capacitance (CPKG < 5 pF). 5 The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 35 Electrical characteristics 4.9 4.9.1 Power management electrical characteristics Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: • • • HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: — LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. — LV_CFLA: Low voltage supply for Code Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. — LV_DFLA: Low voltage supply for Data Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. — LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Figure 7. Voltage regulator capacitance connection CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_LV VDD_BV VREF CDEC1 (Ballast decoupling) CREG1 (LV_COR/LV_DFLA) VDD_BV VDD_LV VDD_LVn Voltage Regulator DEVICE I VSS_LVn VSS_LV VSS_LV VDD_LV VSS VDD GND DEVICE GND GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling) The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. MPC5602D Microcontroller Data Sheet, Rev. 3.1 36 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.5, “Recommended operating conditions). Table 20. Voltage regulator electrical characteristics Symbol CREGn RREG CDEC1 C Parameter Conditions1 Min SR — Internal voltage regulator external capacitance SR — Stability capacitor equivalent serial resistance SR — Decoupling capacitance3 ballast — — VDD_BV/VSS_LV pair: VDD_BV = 4.5 V to 5.5 V VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V CDEC2 VMREG SR — Decoupling capacitance regulator supply CC T Main regulator output voltage P IMREG IMREGINT SR — Main regulator current provided to VDD_LV domain CC D Main regulator module current consumption CC P Low power regulator output voltage SR — Low power regulator current provided to VDD_LV domain VDD/VSS pair Before exiting from reset After trimming — IMREG = 200 mA IMREG = 0 mA After trimming — 200 — 1004 Value2 Unit Typ — — 4705 Max 500 0.2 — nF  nF 400 10 — TBD — — — TBD — — — TBD — — — — 100 1.32 1.28 — — — 1.23 — — 5 1.23 — — 2 — — — — TBD 150 2 1 TBD 15 600 — TBD 5 100 — 4006 mA V mA µA V mA µA mA mA nF V VLPREG ILPREG ILPREGINT CC D Low power regulator module current ILPREG = 15 mA; consumption TA = 55 °C — ILPREG = 0 mA; TA = 55 °C After trimming — IULPREG = 5 mA; TA = 55 °C IULPREG = 0 mA; TA = 55 °C VULPREG IULPREG IULPREGINT CC P Ultra low power regulator output voltage SR — Ultra low power regulator current provided to VDD_LV domain CC D Ultra low power regulator module current consumption IDD_BV 1 2 CC D In-rush current on VDD_BV during power-up — VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 37 Electrical characteristics 3 This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 4 This value is acceptable to guarantee operation from 4.5 V to 5.5 V. 5 External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 6 In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external capacitances to be load). 4.9.2 Voltage monitor electrical characteristics The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied: • • • • • POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0 NOTE When enabled, power domain No. 2 is monitored through LVD_DIGBKP. Figure 8. Low voltage monitor vs. reset VDD VLVDHVxH VLVDHVxL RESET MPC5602D Microcontroller Data Sheet, Rev. 3.1 38 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 21. Low voltage monitor electrical characteristics Symbol VPORUP VPORH C Parameter Conditions1 Min SR P Supply for functional POR module CC P Power-on reset threshold T VLVDHV3H VLVDHV3L CC T LVDHV3 low voltage detector high threshold CC P LVDHV3 low voltage detector low threshold — TA = 25 °C, after trimming — — — — — — — 1.0 1.5 1.5 — 2.6 — 3.8 1.08 1.08 Value2 Unit Typ — — — — — — — — — Max 5.5 2.6 2.6 2.9 TBD 4.4 TBD — 1.11 V VLVDHV5H3 CC T LVDHV5 low voltage detector high threshold VLVDHV5L CC P LVDHV5 low voltage detector low threshold VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold 1 2 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Data based on characterization results, not tested in production 4.10 Low voltage domain power consumption Table 22. Low voltage power domain electrical characteristics Symbol IDDMAX2 IDDRUN4 C Parameter Conditions1 Min CC D RUN mode maximum average current CC T RUN mode typical average current5 T T P IDDHALT CC C HALT mode current6 P IDDSTOP CC P STOP mode current D D D P 7 Table 22 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Value Unit Typ 100 TBD TBD TBD TBD TBD TBD 150 TBD TBD TBD TBD Max TBD3 mA — — — — TBD TBD TBD8 — — — TBD8 mA µA mA mA — — — — — — — — — — — — — fCPU = 8 MHz fCPU = 16 MHz fCPU = 32 MHz fCPU = 48 MHz Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 125 °C Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 55 °C TA = 85 °C TA = 105 °C TA = 125 °C MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 39 Electrical characteristics Table 22. Low voltage power domain electrical characteristics (continued) Symbol IDDSTDBY C Parameter Conditions1 Min CC P STANDBY mode current9 Slow internal RC oscillator TA = 25 °C (128 kHz) running D TA = 55 °C D D P 1 2 Value Unit Typ 25 TBD Max TBD — — — TBD µA — — — — — TA = 85 °C TA = 105 °C TA = 125 °C 3 4 5 6 7 8 9 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from Code Flash while modify operation on-going on Data Flash. Note that this value can be significantly reduced by application: switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from SRAM most used functions, use low power mode when possible. Higher current may be sinked by device during power-up and standby exit. Please refer to in rush current on Table 20. RUN current measured with typical application with accesses on both Flash and SRAM. Only for the “P” classification: Code fetched from SRAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. Data Flash Power Down. Code Flash in Low Power. RC-OSC 128 kHz & RC-OSC 16 MHz on. 10 MHz XTAL clock. FlexCAN: 0 ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception or transmission), instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs. Only for the “P” classification: No clock, RC-OSC 16 MHz off, RC-OSC 128 kHz on, PLL off, HPVreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum consumption, all possible modules switched off. 4.11 Flash memory electrical characteristics The Data Flash operation depends strongly on the Code Flash operation. If Code Flash is switched-off, the Data Flash is disabled. 4.11.1 Program/Erase characteristics Table 23 shows the program and erase characteristics. MPC5602D Microcontroller Data Sheet, Rev. 3.1 40 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 23. Program and erase specifications (Code Flash) Value Symbol C Parameter Min Tdwprogram T16KpperaseC T32KpperaseC T128KpperaseC Tesus 1 Typ1 22 300 400 800 TBD Initial max2 50 500 600 1300 TBD Max3 500 5000 5000 7500 TBD Unit CC C Double word (64 bits) program time4 16 KB block preprogram and erase time 32 KB block preprogram and erase time 128 KB block preprogram and erase time Erase suspend latency — — — — TBD µs ms ms ms µs Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. Table 24. Program and erase specifications (Data Flash) Value Symbol C Parameter Min Tswprogram CC C Single word (32 bits) program time4 T16Kpperase TBank_D 1 Typ1 30 700 1900 Initial max2 70 800 2300 Max3 300 1500 4800 Unit — — — µs ms ms 16 KB block preprogram and erase time 64 KB block preprogram and erase time Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 41 Electrical characteristics Table 25. Flash module life Value Symbol P/E C Parameter Conditions Min CC C Number of program/erase cycles per block for 16 KB blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 32 KB blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (TJ) — 100 Typ — Max — kcycles Unit P/E — 10 1001 — kcycles P/E — 1 100(1) — kcycles Retention CC C Minimum data retention at 85 °C average ambient temperature2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–10,000 P/E cycles Blocks with 10,001–100,000 P/E cycles 20 10 5 — — — — — — years years years 1 2 To be confirmed Ambient temperature averaged over application duration. It is recommended not to exceed the product operating temperature range. ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 26. Flash read access timing Symbol fREAD CC C Parameter Conditions1 2 wait states 1 wait state 0 wait states Max 48 40 20 Unit MHz P Maximum frequency for Flash reading C C 1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 4.11.2 Flash power supply DC characteristics NOTE Power supply for Data Flash is actually provided by Code Flash, this means that Data Flash cannot work if Code Flash is not powered. Table 27 shows the power supply DC characteristics on external supply. MPC5602D Microcontroller Data Sheet, Rev. 3.1 42 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 27. Flash power supply DC electrical characteristics Symbol C Parameter Conditions1 Code Flash — Data Flash — Value2 Unit Min Typ Max ICFREAD CC D Sum of the current consumption on Flash module read VDDHV and VDDBV on read access fCPU = 48 MHz IDFREAD — — — — 33 4 33 6 mA mA Code Flash — ICFMOD CC D Sum of the current consumption on Program/Erase on-going while reading Flash registers, VDDHV and VDDBV on matrix IDFMOD Data Flash — modification (program/erase) fCPU = 48 MHz IFLPW CC D Sum of the current consumption on VDDHV and VDDBV during Flash low-power mode — Code Flash — — 910 µA ICFPWD CC D Sum of the current consumption on VDDHV and VDDBV during IDFPWD Flash power-down mode 1 2 — Code Flash — Data Flash — — 125 µA — 25 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 4.11.3 Start-up/Switch-off timings Table 28. Start-up time/Switch-off time Symbol C Parameter Conditions1 Min Code Flash Data Flash — — — — Value Unit Typ — — — — Max 125 150 0.5 30 303 — — — — — — 0.5 1.5 4(3) µs TFLARSTEXIT CC T Delay for Flash module to exit reset mode TFLALPEXIT TFLAPDEXIT CC T Delay for Flash module to exit low-power mode2 CC T Delay for Flash module to exit power-down mode Code Flash Code Flash Data Flash Code Flash Code Flash Data Flash TFLALPENTRY CC T Delay for Flash module to enter low-power mode TFLAPDENTRY CC T Delay for Flash module to enter power-down mode 1 2 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified Data Flash does not support low-power mode 3 If Code Flash is already switched-on. 4.12 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 43 Electrical characteristics 4.12.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application. • Software recommendations The software flowchart must include the management of runaway conditions such as: — Corrupted program counter — Unexpected reset — Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. • 4.12.2 Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements. Table 29. EMI radiated emission measurement1,2 Value Symbol — C Parameter Conditions Min SR — Scan range — — — No PLL frequency VDD = 5 V, TA = 25 °C, modulation 100 LQFP package Test conforming to IEC 61967-2, ± 2% PLL frequency fOSC = 8 MHz/fCPU = 48 MHz modulation 0.150 — — — — Typ — 48 1.28 — — Max 1000 MHz — — MHz V Unit fCPU SR — Operating frequency VDD_LV SR — LV operating voltages SEMI CC T Peak level TBD dBµV TBD3 dBµV 1 2 EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 3 All values need to be confirmed during device validation 4.12.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 4.12.3.1 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts * (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. MPC5602D Microcontroller Data Sheet, Rev. 3.1 44 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 30. ESD absolute maximum ratings1 2 Symbol C Ratings Conditions TA = 25 °C conforming to AEC-Q100-002 TA = 25 °C conforming to AEC-Q100-003 TA = 25 °C conforming to AEC-Q100-011 Class H1C M2 C3A Max value 2000 200 500 750 (corners) Unit V VESD(HBM) CC T Electrostatic discharge voltage (Human Body Model) VESD(MM) CC T Electrostatic discharge voltage (Machine Model) VESD(CDM) CC T Electrostatic discharge voltage (Charged Device Model) 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 4.12.3.2 • • Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 31. Latch-up results Symbol LU CC C Parameter Conditions TA = 125 °C conforming to JESD 78 Class II level A These tests are compliant with the EIA/JESD 78 IC latch-up standard. T Static latch-up class 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 45 Electrical characteristics Table 32 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. Figure 9. Crystal oscillator and resonator connection scheme EXTAL C1 Crystal XTAL EXTAL DEVICE VDD C2 I R EXTAL XTAL Resonator XTAL DEVICE DEVICE Note: XTAL/EXTAL must not be directly used to drive external circuits. MPC5602D Microcontroller Data Sheet, Rev. 3.1 46 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 32. Crystal description Crystal equivalent series resistance ESR  300 300 150 120 120 Crystal motional capacitance (Cm) fF 2.68 2.46 2.93 3.11 3.90 Crystal motional inductance (Lm) mH 591.0 160.7 86.6 56.5 25.3 Load on xtalin/xtalout C1 = C2 (pF)1 21 17 15 15 10 Shunt capacitance between xtalout and xtalin C02 (pF) 2.93 3.01 2.91 2.93 3.00 Nominal frequency (MHz) NDK crystal reference 4 8 10 12 16 1 NX8045GB NX5032GA The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, 0 package, etc.). Figure 10. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics S_MTRANS bit (ME_GS register) ‘1’ ‘0’ VXTAL VFXOSC VFXOSCOP 10% TFXOSCSU valid internal clock 1/fFXOSC 90% MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 47 Electrical characteristics Table 33. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Symbol fFXOSC FXOSC C Parameter Conditions1 Min SR — Fast external crystal oscillator frequency CC T Fast external crystal oscillator frequency duty cycle CC T Fast external crystal oscillator jitter CC C Fast external crystal oscillator transconductance CC P — — 4.0 30 Value2 Unit Typ — — Max 16.0 70 MHz % tFXJIT gmFXOSC — VDD = 3.3 V ± 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 — 2.2 — — TBD 8.2 ns mA/V 2.0 — 7.4 CC C 2.7 — 9.7 CC C 2.5 — 9.2 VFXOSC CC T Oscillation amplitude at EXTAL 1.3 1.3 — — — — 0.65VDD 0.4 — — 0.95 2 — — — — — — V VFXOSCOP CC P Oscillation operating point IFXOSC,3 TFXOSCSU CC T Fast external crystal oscillator consumption CC T Fast external crystal oscillator start-up time — — fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 V 3 6 1.8 VDD+0.4 0.35VDD V V mA ms VIH VIL 1 2 SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode Oscillator bypass mode VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals) MPC5602D Microcontroller Data Sheet, Rev. 3.1 48 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 4.14 FMPLL electrical characteristics Table 34. FMPLL electrical characteristics Symbol fPLLIN C Parameter Conditions — — — — — — — Stable oscillator (fPLLIN = 16 MHz) fPLLIN = 16 MHz (resonator), fPLLCLK at 48 MHz, 4,000 cycles TA = 25 °C 1 The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Value2 Unit Min Typ — — — — — — — 40 — — Max 48 60 48 512 532.48 48 150 100 10 4 MHz MHz µs ns mA MHz % MHz MHz 4 40 16 256 245.76 — 20 — — — SR — FMPLL reference clock3 SR — FMPLL reference clock duty cycle(3) PLLIN fPLLOUT CC D FMPLL output clock frequency fVCO4 CC P VCO frequency without frequency modulation VCO frequency with frequency modulation fCPU fFREE tLOCK SR — System clock frequency CC P Free-running frequency CC P FMPLL lock time tLTJIT CC — FMPLL long term jitter IPLL 1 2 CC C FMPLL consumption VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 4 Frequency modulation is considered ±4%. 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics Symbol fFIRC 3, The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device. C Parameter Conditions1 Min — 12 — Value2 Unit Typ 16 Max — 20 — 200 µA MHz CC P Fast internal RC oscillator high TA = 25 °C, trimmed frequency SR — — CC T Fast internal RC oscillator high TA = 25 °C, trimmed frequency current in running mode CC D Fast internal RC oscillator high TA = 25 °C frequency current in power down mode IFIRCRUN IFIRCPWD — — 10 µA MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 49 Electrical characteristics Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics (continued) Symbol C Parameter Conditions 1 Value2 Unit Min Typ 500 600 700 900 1250 1.1 1.2 — — — Max — — — — — 2.0 TBD 2.0 TBD 1 % µs µA — — — — — — — — — 1 IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C frequency and system clock current in stop mode sysclk = off sysclk = 2 MHz sysclk = 4 MHz sysclk = 8 MHz sysclk = 16 MHz TFIRCSU CC C Fast internal RC oscillator start-up time — — — TA = 55 °C VDD = 5.0 V ± 10% VDD = 3.3 V ± 10% TA = 125 °C VDD = 5.0 V ± 10% VDD = 3.3 V ± 10% TA = 25 °C FIRCPRE CC C Fast internal RC oscillator precision after software trimming of fFIRC FIRCTRIM CC C Fast internal RC oscillator trimming step FIRCVAR CC C Fast internal RC oscillator variation in temperature and supply with respect to fFIRC at TA = 55 °C in high-frequency configuration TA = 25 °C — — 5 1.6 — 5 % % VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 1 2 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics Symbol fSIRC ISIRC3, TSIRCSU C Parameter Conditions1 Min CC P Slow internal RC oscillator low frequency SR — CC C Slow internal RC oscillator low frequency current TA = 25 °C, trimmed — TA = 25 °C, trimmed — 100 — — Value2 Unit Typ 128 — — 8 Max — 150 5 12 µA µs kHz The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module. CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10% time MPC5602D Microcontroller Data Sheet, Rev. 3.1 50 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics (continued) Symbol SIRCPRE SIRCTRIM SIRCVAR C Parameter Conditions 1 Value2 Unit Min Typ — 2.7 — Max 2 — 10 % % 2 CC C Slow internal RC oscillator precision TA = 25 °C after software trimming of fSIRC CC C Slow internal RC oscillator trimming step — — 10 CC P Slow internal RC oscillator variation High frequency configuration in temperature and supply with respect to fSIRC at TA = 55 °C in high frequency configuration VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 1 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 51 Electrical characteristics 4.17 4.17.1 ADC electrical characteristics Introduction Figure 11. ADC characteristic and error definitions Offset Error OSE 1023 Gain Error GE The device provides a 12-bit Successive Approximation Register (SAR) analog-to-digital converter. 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE 4.17.2 Input impedance and ADC accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as MPC5602D Microcontroller Data Sheet, Rev. 3.1 52 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Eqn. 4 R S + R F + R L + R SW + R AD - -V A  --------------------------------------------------------------------------  1 LSB R EQ 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 53 Electrical characteristics Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 12. Input equivalent circuit (precise channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Sampling Source RS Filter RF Current Limiter RL RAD VA CF CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 13. Input equivalent circuit (extended channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Extended Switch RSW2 Sampling Source RS Filter RF Current Limiter RL RAD VA CF CP1 CP3 CP2 CS RS RF CF RL RSW RAD CP CS Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance MPC5602D Microcontroller Data Sheet, Rev. 3.1 54 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit in Figure 13): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Figure 14. Transient behavior during sampling phase VCS VA VA2 Voltage transient on CS V