MPC5602D Microcontroller Reference Manual
Devices Supported:
MPC5602D MPC5601D
MPC5602DRM Rev. 3.1 23 Feb 2011
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 1
MPC5602D Microcontroller Reference Manual, Rev. 3.1 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Chapter 1 Overview
1.1 1.2 1.3 1.4 Introduction .....................................................................................................................................31 MPC5602D Device Comparison .....................................................................................................31 Device Block Diagram ....................................................................................................................33 Feature Summary ............................................................................................................................34 1.4.1 e200z0h core processor ..................................................................................................34 1.4.2 Crossbar Switch (XBAR) ...............................................................................................34 1.4.3 Interrupt Controller (INTC) ............................................................................................35 1.4.4 System Integration Unit Lite (SIUL) ..............................................................................35 1.4.5 Flash Memory .................................................................................................................35 1.4.6 SRAM .............................................................................................................................36 1.4.7 Boot Assist Module (BAM) ...........................................................................................37 1.4.8 Enhanced Modular Input Output System (eMIOS) ........................................................37 1.4.9 Deserial Serial Peripheral Interface Module (DSPI) ......................................................38 1.4.10 Controller Area Network Module (FlexCAN) ...............................................................39 1.4.11 System clocks and clock generation ...............................................................................40 1.4.12 System timers .................................................................................................................40 1.4.12.1 Introduction ......................................................................................................40 1.4.12.2 Periodic interrupt timer module (PIT) .............................................................41 1.4.12.3 Real-time counter (RTC) ..................................................................................41 1.4.13 System watchdog timer ..................................................................................................41 1.4.14 On-chip voltage regulator (VREG) ................................................................................41 1.4.15 Analog to Digital Converter Module (ADC) ..................................................................42 1.4.16 Enhanced Direct Memory Access Controller (eDMA) ..................................................43 1.4.17 Cross Trigger Unit (CTU) ..............................................................................................43 1.4.18 Serial Communication Interface Module (LINFlex) ......................................................43 1.4.19 JTAG controller (JTAGC) ..............................................................................................45 Developer Support ...........................................................................................................................45 Memory Map ...................................................................................................................................45
1.5 1.6
Chapter 2 Signal Description
2.1 2.2 2.3 2.4 2.5 2.6 Package Pinouts ...............................................................................................................................49 Pad configuration during reset phases .............................................................................................50 Voltage supply pins .........................................................................................................................51 Pad types .........................................................................................................................................51 System pins .....................................................................................................................................51 Functional ports A, B, C, D, E, H ...................................................................................................52
Chapter 3 Reset Generation Module (MC_RGM)
3.1 Introduction .....................................................................................................................................63 3.1.1 Overview ........................................................................................................................63 3.1.2 Features ...........................................................................................................................64
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 3
3.2 3.3
3.4
3.1.3 Reset Sources ..................................................................................................................65 External Signal Description ............................................................................................................66 Memory Map and Register Definition ............................................................................................66 3.3.1 Register Descriptions ......................................................................................................68 3.3.1.1 Functional Event Status Register (RGM_FES) ................................................69 3.3.1.2 Destructive Event Status Register (RGM_DES) ..............................................70 3.3.1.3 Functional Event Reset Disable Register (RGM_FERD) ................................71 3.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ..............................73 3.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) .........................73 3.3.1.6 Functional Event Short Sequence Register (RGM_FESS) ..............................74 3.3.1.7 STANDBY0 Reset Sequence Register (RGM_STDBY) .................................76 3.3.1.8 Functional Bidirectional Reset Enable Register (RGM_FBRE) ......................76 Functional Description ....................................................................................................................77 3.4.1 Reset State Machine .......................................................................................................77 3.4.1.1 PHASE0 Phase ................................................................................................79 3.4.1.2 PHASE1 Phase ................................................................................................80 3.4.1.3 PHASE2 Phase ................................................................................................80 3.4.1.4 PHASE3 Phase ................................................................................................80 3.4.1.5 IDLE Phase ......................................................................................................80 3.4.2 Destructive Resets ..........................................................................................................80 3.4.3 External Reset .................................................................................................................81 3.4.4 Functional Resets ............................................................................................................81 3.4.5 STANDBY0 Entry Sequence ..........................................................................................82 3.4.6 Alternate Event Generation ............................................................................................82 3.4.7 Boot Mode Capturing .....................................................................................................83
Chapter 4 Clock description
4.1 4.2 4.3 Clock architecture ...........................................................................................................................85 Clock gating ....................................................................................................................................86 Fast external crystal oscillator (FXOSC) digital interface ..............................................................87 4.3.1 Main features ..................................................................................................................87 4.3.2 Functional description ....................................................................................................87 4.3.3 Register description ........................................................................................................88 Slow internal RC oscillator (SIRC) digital interface .....................................................................89 4.4.1 Introduction ....................................................................................................................89 4.4.2 Functional description ....................................................................................................89 4.4.3 Register description ........................................................................................................90 Fast internal RC oscillator (FIRC) digital interface ........................................................................91 4.5.1 Introduction ....................................................................................................................91 4.5.2 Functional description ....................................................................................................91 4.5.3 Register description ........................................................................................................92 Frequency-modulated phase-locked loop (FMPLL) .......................................................................92 4.6.1 Introduction ....................................................................................................................92 4.6.2 Overview ........................................................................................................................93
MPC5602D Microcontroller Reference Manual, Rev. 3.1 4 Preliminary Freescale Semiconductor
4.4
4.5
4.6
4.7
Features ...........................................................................................................................93 Memory map ..................................................................................................................94 Register description ........................................................................................................94 4.6.5.1 Control Register (CR) ......................................................................................94 4.6.5.2 Modulation Register (MR) ...............................................................................97 4.6.6 Functional description ....................................................................................................98 4.6.6.1 Normal mode ....................................................................................................98 4.6.6.2 Progressive clock switching .............................................................................98 4.6.6.3 Normal mode with frequency modulation .......................................................99 4.6.6.4 Powerdown mode ...........................................................................................100 4.6.7 Recommendations ........................................................................................................100 Clock monitor unit (CMU) ............................................................................................................100 4.7.1 Introduction ..................................................................................................................100 4.7.2 Main features ................................................................................................................101 4.7.3 Block diagram ..............................................................................................................101 4.7.4 Functional description ..................................................................................................102 4.7.4.1 Crystal clock monitor .....................................................................................103 4.7.4.2 FMPLL clock monitor ...................................................................................103 4.7.4.3 Frequency meter .............................................................................................104 4.7.5 Memory map and register description ..........................................................................104 4.7.5.1 Control Status Register (CMU_CSR) ............................................................105 4.7.5.2 Frequency Display Register (CMU_FDR) ....................................................106 4.7.5.3 High Frequency Reference Register FMPLL (CMU_HFREFR) ..................106 4.7.5.4 Low Frequency Reference Register FMPLL (CMU_LFREFR) ....................107 4.7.5.5 Interrupt Status Register (CMU_ISR) ............................................................107 4.7.5.6 Measurement Duration Register (CMU_MDR) ............................................108 4.7.6 Register map .................................................................................................................108
4.6.3 4.6.4 4.6.5
Chapter 5 Clock Generation Module (MC_CGM)
5.1 Introduction ................................................................................................................................... 111 5.1.1 Overview ...................................................................................................................... 111 5.1.2 Features .........................................................................................................................112 External Signal Description ..........................................................................................................113 Memory Map and Register Definition ..........................................................................................113 5.3.1 Register Descriptions ....................................................................................................117 5.3.1.1 Output Clock Enable Register (CGM_OC_EN) ............................................118 5.3.1.2 Output Clock Division Select Register (CGM_OCDS_SC) ..........................118 5.3.1.3 System Clock Select Status Register (CGM_SC_SS) ...................................119 5.3.1.4 System Clock Divider Configuration Registers (CGM_SC_DC0…2) ..........120 Functional Description ..................................................................................................................121 5.4.1 System Clock Generation .............................................................................................121 5.4.1.1 System Clock Source Selection .....................................................................122 5.4.1.2 System Clock Disable ....................................................................................123 5.4.1.3 System Clock Dividers ...................................................................................123
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5.2 5.3
5.4
5.4.2 5.4.3 5.4.4
Dividers Functional Description ...................................................................................123 Output Clock Multiplexing ...........................................................................................123 Output Clock Division Selection ..................................................................................123
Chapter 6 Mode Entry Module (MC_ME)
6.1 Introduction ...................................................................................................................................125 6.1.1 Overview ......................................................................................................................125 6.1.2 Features .........................................................................................................................127 6.1.3 Modes of Operation ......................................................................................................127 External Signal Description ..........................................................................................................128 Memory Map and Register Definition ..........................................................................................128 6.3.1 Memory Map ................................................................................................................129 6.3.2 Register Description .....................................................................................................136 6.3.2.1 Global Status Register (ME_GS) ...................................................................137 6.3.2.2 Mode Control Register (ME_MCTL) ............................................................139 6.3.2.3 Mode Enable Register (ME_ME) ..................................................................140 6.3.2.4 Interrupt Status Register (ME_IS) .................................................................142 6.3.2.5 Interrupt Mask Register (ME_IM) .................................................................143 6.3.2.6 Invalid Mode Transition Status Register (ME_IMTS) ..................................144 6.3.2.7 Debug Mode Transition Status Register (ME_DMTS) ..................................145 6.3.2.8 RESET Mode Configuration Register (ME_RESET_MC) ...........................148 6.3.2.9 TEST Mode Configuration Register (ME_TEST_MC) ................................148 6.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC) ................................149 6.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC) .............................149 6.3.2.12 RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) .................150 6.3.2.13 HALT0 Mode Configuration Register (ME_HALT0_MC) ...........................151 6.3.2.14 STOP0 Mode Configuration Register (ME_STOP0_MC) ............................151 6.3.2.15 STANDBY0 Mode Configuration Register (ME_STANDBY0_MC) ...........152 6.3.2.16 Peripheral Status Register 0 (ME_PS0) .........................................................154 6.3.2.17 Peripheral Status Register 1 (ME_PS1) .........................................................154 6.3.2.18 Peripheral Status Register 2 (ME_PS2) .........................................................155 6.3.2.19 Peripheral Status Register 3 (ME_PS3) .........................................................155 6.3.2.20 Run Peripheral Configuration Registers (ME_RUN_PC0…7) .....................156 6.3.2.21 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) .............157 6.3.2.22 Peripheral Control Registers (ME_PCTL0…143) .........................................158 Functional Description ..................................................................................................................159 6.4.1 Mode Transition Request ..............................................................................................159 6.4.2 Modes Details ...............................................................................................................160 6.4.2.1 RESET Mode .................................................................................................160 6.4.2.2 DRUN Mode ..................................................................................................160 6.4.2.3 SAFE Mode ...................................................................................................161 6.4.2.4 TEST Mode ....................................................................................................162 6.4.2.5 RUN0…3 Modes ...........................................................................................162 6.4.2.6 HALT0 Mode .................................................................................................163
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6.2 6.3
6.4
6.4.3
6.4.4 6.4.5
6.4.6 6.4.7
6.4.2.7 STOP0 Mode .................................................................................................163 6.4.2.8 STANDBY0 Mode .........................................................................................164 Mode Transition Process ..............................................................................................165 6.4.3.1 Target Mode Request .....................................................................................165 6.4.3.2 Target Mode Configuration Loading .............................................................165 6.4.3.3 Peripheral Clocks Disable ..............................................................................166 6.4.3.4 Processor Low-Power Mode Entry ................................................................167 6.4.3.5 Processor and System Memory Clock Disable ..............................................167 6.4.3.6 Clock Sources (Main Voltage Regulator Independent) Switch-On ...............167 6.4.3.7 Main Voltage Regulator Switch-On ...............................................................167 6.4.3.8 Flash Modules Switch-On ..............................................................................168 6.4.3.9 Clock Sources (Main Voltage Regulator Dependent) Switch-On ..................168 6.4.3.10 Pad Outputs-On ..............................................................................................168 6.4.3.11 Peripheral Clocks Enable ...............................................................................168 6.4.3.12 Processor and Memory Clock Enable ............................................................169 6.4.3.13 Processor Low-Power Mode Exit ..................................................................169 6.4.3.14 System Clock Switching ................................................................................169 6.4.3.15 Pad Switch-Off ...............................................................................................170 6.4.3.16 Clock Sources Switch-Off ..............................................................................170 6.4.3.17 Flash Switch-Off ............................................................................................171 6.4.3.18 Main Voltage Regulator Switch-Off ..............................................................171 6.4.3.19 Current Mode Update .....................................................................................171 Protection of Mode Configuration Registers ................................................................174 Mode Transition Interrupts ...........................................................................................174 6.4.5.1 Invalid Mode Configuration Interrupt ............................................................174 6.4.5.2 Invalid Mode Transition Interrupt ..................................................................175 6.4.5.3 SAFE Mode Transition Interrupt ...................................................................176 6.4.5.4 Mode Transition Complete interrupt ..............................................................176 Peripheral Clock Gating ...............................................................................................176 Application Example ....................................................................................................177
Chapter 7 e200z0h Core
7.1 7.2 Overview .......................................................................................................................................179 Features .........................................................................................................................................179 7.2.1 Microarchitecture summary ..........................................................................................180 7.2.1.1 Block diagram ................................................................................................181 7.2.1.2 Instruction unit features .................................................................................181 7.2.1.3 Integer unit features .......................................................................................182 7.2.1.4 Load/Store unit features .................................................................................182 7.2.1.5 e200z0h system bus features ..........................................................................182 7.2.1.6 Nexus 2+ features ...........................................................................................183 Core registers and programmer’s model .......................................................................................183
7.3
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Chapter 8 Enhanced Direct Memory Access (eDMA)
8.1 Device-specific information ..........................................................................................................187 8.1.1 Device-specific features ..............................................................................................187 8.1.2 Registers unavailable on this device .............................................................................188 Introduction ...................................................................................................................................188 8.2.1 Features .........................................................................................................................189 Memory map/register definition ....................................................................................................189 8.3.1 Register descriptions ....................................................................................................193 8.3.1.1 DMA Control Register (EDMA_CR) ............................................................193 8.3.1.2 DMA Error Status (EDMA_ESR) .................................................................195 8.3.1.3 DMA Enable Request (EDMA_ERQRL) ......................................................197 8.3.1.4 DMA Enable Error Interrupt (EDMA_EEIRL) .............................................198 8.3.1.5 DMA Set Enable Request (EDMA_SERQR) ................................................199 8.3.1.6 DMA Clear Enable Request (EDMA_CERQR) ............................................200 8.3.1.7 DMA Set Enable Error Interrupt (EDMA_SEEIR) .......................................200 8.3.1.8 DMA Clear Enable Error Interrupt (EDMA_CEEIR) ...................................200 8.3.1.9 DMA Clear Interrupt Request (EDMA_CIRQR) ..........................................201 8.3.1.10 DMA Clear Error (EDMA_CER) ..................................................................201 8.3.1.11 DMA Set START Bit (EDMA_SSBR) ..........................................................202 8.3.1.12 DMA Clear DONE Status (EDMA_CDSBR) ...............................................202 8.3.1.13 DMA Interrupt Request (EDMA_IRQRL) ....................................................203 8.3.1.14 DMA Error (EDMA_ERL) ............................................................................204 8.3.1.15 DMA Hardware Request Status (EDMA_HRSL) .........................................205 8.3.1.16 DMA Channel n Priority (EDMA_CPRn) .....................................................206 8.3.1.17 Transfer Control Descriptor (TCD) ...............................................................207 Functional Description ..................................................................................................................214 8.4.1 eDMA Basic Data Flow ...............................................................................................216 Initialization / Application Information ........................................................................................219 8.5.1 eDMA Initialization ......................................................................................................219 8.5.2 DMA Programming Errors ...........................................................................................221 8.5.3 DMA Request Assignments .........................................................................................222 8.5.4 DMA Arbitration Mode Considerations .......................................................................222 8.5.4.1 Fixed-Channel Arbitration .............................................................................222 8.5.4.2 Round-Robin Channel Arbitration .................................................................222 8.5.5 DMA Transfer ..............................................................................................................223 8.5.5.1 Single Request ................................................................................................223 8.5.5.2 Multiple Requests ..........................................................................................224 8.5.5.3 Modulo Feature ..............................................................................................225 8.5.6 TCD Status ...................................................................................................................226 8.5.6.1 Minor Loop Complete ....................................................................................226 8.5.6.2 Active Channel TCD Reads ...........................................................................227 8.5.6.3 Preemption Status ...........................................................................................227 8.5.7 Channel Linking ...........................................................................................................227 8.5.8 Dynamic Programming ................................................................................................228
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8.2 8.3
8.4 8.5
8.5.8.1
Dynamic Channel Linking and Dynamic Scatter-Gather Operation .............228
Chapter 9 DMA Channel Multiplexer (DMA_MUX)
9.1 Introduction ...................................................................................................................................231 9.1.1 Overview ......................................................................................................................231 9.1.2 Features .........................................................................................................................231 9.1.3 Modes of operation .......................................................................................................232 External signal description ............................................................................................................232 9.2.1 Overview ......................................................................................................................232 Memory map and register definition .............................................................................................232 9.3.1 Register descriptions ....................................................................................................233 9.3.1.1 Channel configuration registers (CHCONFIG#n) .........................................233 9.3.2 DMA_MUX inputs .......................................................................................................234 9.3.2.1 DMA_MUX peripheral sources .....................................................................234 9.3.2.2 DMA_MUX periodic trigger inputs ..............................................................236 Functional description ...................................................................................................................236 9.4.1 DMA channels with periodic triggering capability ......................................................237 9.4.2 DMA channels with no triggering capability ...............................................................238 Initialization/Application information ...........................................................................................239 9.5.1 Reset .............................................................................................................................239 9.5.2 Enabling and configuring sources ................................................................................239 9.5.2.1 Enabling a source with periodic triggering ....................................................239 9.5.2.2 Enabling a source without periodic triggering ...............................................240 9.5.2.3 Disabling a source ..........................................................................................241 9.5.2.4 Switching the source of a DMA channel .......................................................241
9.2 9.3
9.4
9.5
Chapter 10 Multi-Layer AHB Crossbar Switch (XBAR)
10.1 Information specific to this device ................................................................................................243 10.1.1 Device-specific features ...............................................................................................243 10.1.2 Device-specific register information ............................................................................243 10.2 Introduction ...................................................................................................................................244 10.2.1 Overview ......................................................................................................................244 10.2.2 Features .........................................................................................................................246 10.2.3 Limitations ....................................................................................................................246 10.2.4 General Operation ........................................................................................................246 10.3 XBAR Registers ............................................................................................................................247 10.3.1 Register Summary ........................................................................................................247 10.3.2 XBAR Register Descriptions .......................................................................................249 10.3.2.1 Master Priority Register .................................................................................250 10.3.2.2 Alternate Master Priority Register .................................................................252 10.3.2.3 Slave General Purpose Control Register ........................................................253 10.3.2.4 Alternate Slave General Purpose Control Register ........................................255 10.3.2.5 Master General Purpose Control Register .....................................................256
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10.3.3 Coherency .....................................................................................................................257 10.4 Function .........................................................................................................................................258 10.4.1 Arbitration ....................................................................................................................258 10.4.1.1 Arbitration During Undefined Length Bursts ................................................258 10.4.1.2 Fixed Priority Operation ................................................................................258 10.4.1.3 Round-Robin Priority Operation ....................................................................259 10.4.2 Priority Assignment ......................................................................................................260 10.4.2.1 Context Switching ..........................................................................................260 10.4.2.2 Priority Elevation ...........................................................................................260 10.4.3 Master Port Functionality .............................................................................................260 10.4.3.1 General ...........................................................................................................260 10.4.3.2 Master Port Decoders .....................................................................................262 10.4.3.3 Master Port Capture Unit ...............................................................................263 10.4.3.4 Master Port Registers .....................................................................................263 10.4.3.5 Master Port State Machine .............................................................................263 10.4.4 Slave Port Functionality ...............................................................................................264 10.4.4.1 General ...........................................................................................................264 10.4.4.2 Slave Port Muxes ...........................................................................................265 10.4.4.3 Slave Port Registers .......................................................................................266 10.4.4.4 Slave Port State Machine ...............................................................................266 10.5 Initialization/Application Information ..........................................................................................271 10.6 Interface .........................................................................................................................................271 10.6.1 Overview ......................................................................................................................272 10.6.2 Master Ports ..................................................................................................................272 10.6.2.1 Ignored Accesses ............................................................................................272 10.6.2.2 Terminated Accesses ......................................................................................272 10.6.2.3 Taken Accesses ..............................................................................................272 10.6.2.4 Stalled Accesses .............................................................................................272 10.6.2.5 Error Response Terminated Accesses ............................................................273 10.6.3 Slave Ports ....................................................................................................................273
Chapter 11 Peripheral Bridge (PBRIDGE)
11.1 Introduction ...................................................................................................................................275 11.1.1 Block Diagram ..............................................................................................................275 11.1.2 Overview ......................................................................................................................276 11.1.3 Features .........................................................................................................................276 11.2 Functional Description ..................................................................................................................276 11.2.1 Access Support .............................................................................................................276 11.2.1.1 Peripheral Write Buffering .............................................................................276 11.2.1.2 Read Cycles ....................................................................................................276 11.2.1.3 Write Cycles ...................................................................................................276 11.2.2 General Operation ........................................................................................................276
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Chapter 12 Flash memory
12.1 Introduction ...................................................................................................................................279 12.2 Code Flash .....................................................................................................................................279 12.2.1 Introduction ..................................................................................................................279 12.2.2 Main features ................................................................................................................280 12.2.3 Block diagram ..............................................................................................................280 12.2.4 Functional description ..................................................................................................281 12.2.4.1 Module structure ............................................................................................281 12.2.4.2 Flash module sectorization .............................................................................281 12.2.4.3 User mode operation ......................................................................................284 12.2.4.4 Reset ...............................................................................................................285 12.2.4.5 Power-down mode .........................................................................................285 12.2.4.6 Low power mode ...........................................................................................285 12.2.5 Register description ......................................................................................................286 12.2.6 Module Configuration Register (MCR) .......................................................................287 12.2.7 Low/Mid address space block Locking register (LML) ...............................................293 12.2.7.1 Non-volatile Low/Mid address space block Locking register (NVLML) .....293 12.2.8 High address space Block Locking register (HBL) ......................................................295 12.2.8.1 Non-volatile High address space Block Locking register (NVHBL) ............295 12.2.9 Secondary Low/mid address space block Locking register (SLL) ...............................296 12.2.9.1 Non-volatile Secondary Low/mid address space block Locking register (NVSLL) 297 12.2.10 Low/Mid address space block Select register (LMS) ...................................................299 12.2.11 High address space Block Select register (HBS) .........................................................300 12.2.12 Address Register (ADR) ...............................................................................................301 12.2.13 Bus Interface Unit 0 register (BIU0) ............................................................................302 12.2.14 Bus Interface Unit 1 register (BIU1) ............................................................................303 12.2.15 Bus Interface Unit 2 register (BIU2) ............................................................................303 12.2.15.1 Non-volatile Bus Interface Unit 2 register (NVBIU2) ...................................304 12.2.16 Bus Interface Unit 3 register (BIU3) ............................................................................304 12.2.16.1 Non Volatile Bus Interface Unit 3 register (NVBIU3) ...................................304 12.2.17 User Test 0 register (UT0) ............................................................................................305 12.2.18 User Test 1 register (UT1) ............................................................................................307 12.2.19 User Test 2 register (UT2) ............................................................................................308 12.2.20 User Multiple Input Signature Register 0 (UMISR0) ..................................................309 12.2.21 User Multiple Input Signature Register 1 (UMISR1) ..................................................309 12.2.22 User Multiple Input Signature Register 2 (UMISR2) ..................................................310 12.2.23 User Multiple Input Signature Register 3 (UMISR3) ..................................................311 12.2.24 User Multiple Input Signature Register 4 (UMISR4) ..................................................311 12.2.25 Non-volatile private censorship PassWord 0 register (NVPWD0) ..............................312 12.2.26 Non-volatile private censorship PassWord 1 register (NVPWD1) ..............................313 12.2.27 Non-volatile System Censoring Information 0 register (NVSCI0) ..............................313 12.2.28 Non-volatile System Censoring Information 1 register (NVSCI1) ..............................314 12.2.29 Non-volatile User Options register (NVUSRO) ...........................................................315
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12.2.30 Register map .................................................................................................................316 12.2.31 Programming considerations ........................................................................................317 12.2.31.1 Modify operation ............................................................................................317 12.2.31.2 Error correction code .....................................................................................325 12.2.31.3 EEprom emulation .........................................................................................326 12.2.31.4 Eprom Emulation ...........................................................................................326 12.2.31.5 Protection strategy ..........................................................................................327 12.3 Data Flash ......................................................................................................................................328 12.3.1 Introduction ..................................................................................................................328 12.3.2 Main features ................................................................................................................329 12.3.3 Block diagram ..............................................................................................................329 12.3.4 Functional description ..................................................................................................330 12.3.4.1 Module structure ............................................................................................330 12.3.4.2 Flash module sectorization .............................................................................331 12.3.5 User mode operation .....................................................................................................332 12.3.5.1 Reset ...............................................................................................................333 12.3.5.2 Power-down mode .........................................................................................333 12.3.5.3 Slave Mode. ...................................................................................................334 12.3.6 Register description ......................................................................................................334 12.3.7 Module Configuration Register (MCR) .......................................................................335 12.3.8 Low/Mid address space block Locking register (LML) ...............................................340 12.3.8.1 Non-volatile Low/Mid address space block Locking register (NVLML) .....341 12.3.9 Secondary Low/mid address space block Locking register (SLL) ...............................342 12.3.9.1 Non-volatile Secondary Low/mid address space block Locking reg (NVSLL) .. 342 12.3.10 Low/Mid address space block Select register (LMS) ...................................................344 12.3.11 Address Register (ADR) ...............................................................................................345 12.3.12 User Test 0 register (UT0) ............................................................................................346 12.3.13 User Test 1 register (UT1) ............................................................................................348 12.3.14 User Multiple Input Signature Register 0 (UMISR0) ..................................................348 12.3.15 User Multiple Input Signature Register 1 (UMISR1) ..................................................349 12.3.16 Register map .................................................................................................................350 12.3.17 Programming considerations ........................................................................................350 12.3.17.1 Modify operation ............................................................................................350 12.3.17.2 Word program ................................................................................................352 12.3.17.3 Sector erase ....................................................................................................353 12.3.17.4 User Test Mode ..............................................................................................355 12.3.18 Error correction code ....................................................................................................358 12.3.18.1 ECC algorithms ..............................................................................................358 12.3.19 Protection strategy ........................................................................................................358 12.3.19.1 Modify protection ..........................................................................................358 12.4 Platform Flash controller ...............................................................................................................359 12.4.1 Introduction ..................................................................................................................359 12.4.1.1 Overview ........................................................................................................361 12.4.1.2 Features ..........................................................................................................361
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12.4.2 Modes of operation .......................................................................................................362 12.4.3 External signal descriptions ..........................................................................................362 12.4.4 Memory map and register description ..........................................................................362 12.4.4.1 Memory map ..................................................................................................363 12.4.4.2 Register description ........................................................................................364 12.4.5 Programming model connections .................................................................................372 12.5 Functional description ...................................................................................................................374 12.5.1 Basic interface protocol ................................................................................................374 12.5.2 Access protections ........................................................................................................375 12.5.3 Read cycles – Buffer miss ............................................................................................375 12.5.4 Read cycles – Buffer hit ...............................................................................................375 12.5.5 Write cycles ..................................................................................................................375 12.5.6 Error termination ..........................................................................................................376 12.5.7 Access pipelining ..........................................................................................................376 12.5.8 Flash error response operation ......................................................................................376 12.5.9 Bank0 page read buffers and prefetch operation ..........................................................377 12.5.9.1 Instruction/Data prefetch triggering ...............................................................378 12.5.9.2 Per-master prefetch triggering ........................................................................378 12.5.9.3 Buffer allocation .............................................................................................378 12.5.9.4 Buffer invalidation .........................................................................................379 12.5.10 Bank1 Temporary Holding Register .............................................................................379 12.5.11 Read-while-write functionality .....................................................................................380 12.5.12 Wait-state emulation .....................................................................................................381 12.5.13 Timing diagrams ...........................................................................................................382
Chapter 13 Static RAM (SRAM)
13.1 Introduction ...................................................................................................................................389 13.2 Register memory map ...................................................................................................................389 13.3 SRAM ECC mechanism ................................................................................................................389 13.3.1 Access timing ...............................................................................................................390 13.3.2 Reset effects on SRAM accesses ..................................................................................391 13.4 Functional description ...................................................................................................................391 13.5 Initialization and application information .....................................................................................391
Chapter 14 Interrupt Controller (INTC)
14.1 14.2 14.3 14.4 Introduction ...................................................................................................................................393 Features .........................................................................................................................................393 Block diagram ...............................................................................................................................394 Modes of operation ........................................................................................................................395 14.4.1 Normal mode ................................................................................................................395 14.4.1.1 Software vector mode ....................................................................................395 14.4.1.2 Hardware vector mode ...................................................................................396 14.4.1.3 Debug mode ...................................................................................................396
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14.4.1.4 Stop mode .......................................................................................................396 14.5 Memory map and register description ...........................................................................................396 14.5.1 Module memory map ...................................................................................................396 14.5.2 Register description ......................................................................................................397 14.5.2.1 INTC Module Configuration Register (INTC_MCR) ...................................397 14.5.2.2 INTC Current Priority Register for Processor (INTC_CPR) .........................398 14.5.2.3 INTC Interrupt Acknowledge Register (INTC_IACKR) ..............................400 14.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ............................................401 14.5.2.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7) 401 14.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR152_154) ........403 14.6 Functional description ...................................................................................................................404 14.6.1 Interrupt request sources ...............................................................................................411 14.6.1.1 Peripheral interrupt requests ..........................................................................411 14.6.1.2 Software configurable interrupt requests .......................................................411 14.6.1.3 Unique vector for each interrupt request source ............................................411 14.6.2 Priority management ....................................................................................................412 14.6.2.1 Current priority and preemption ....................................................................412 14.6.2.2 Last-In First-Out (LIFO) ................................................................................413 14.6.3 Handshaking with processor .........................................................................................413 14.6.3.1 Software vector mode handshaking ...............................................................413 14.6.3.2 Hardware vector mode handshaking ..............................................................414 14.7 Initialization/application information ............................................................................................415 14.7.1 Initialization flow .........................................................................................................415 14.7.2 Interrupt exception handler ...........................................................................................416 14.7.2.1 Software vector mode ....................................................................................416 14.7.2.2 Hardware vector mode ...................................................................................417 14.7.3 ISR, RTOS, and task hierarchy .....................................................................................417 14.7.4 Order of execution ........................................................................................................418 14.7.5 Priority ceiling protocol ................................................................................................419 14.7.5.1 Elevating priority ...........................................................................................419 14.7.5.2 Ensuring coherency ........................................................................................419 14.7.6 Selecting priorities according to request rates and deadlines .......................................420 14.7.7 Software configurable interrupt requests ......................................................................420 14.7.7.1 Scheduling a lower priority portion of an ISR ...............................................420 14.7.7.2 Scheduling an ISR on another processor .......................................................421 14.7.8 Lowering priority within an ISR ..................................................................................421 14.7.9 Negating an interrupt request outside of its ISR ..........................................................422 14.7.9.1 Negating an interrupt request as a side effect of an ISR ................................422 14.7.9.2 Negating multiple interrupt requests in one ISR ............................................422 14.7.9.3 Proper setting of interrupt request priority .....................................................422 14.7.10 Examining LIFO contents ............................................................................................422
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Chapter 15 System Integration Unit Lite (SIUL)
15.1 15.2 15.3 15.4 Introduction ...................................................................................................................................423 Overview .......................................................................................................................................423 Features .........................................................................................................................................425 External signal description ............................................................................................................425 15.4.1 Detailed signal descriptions ..........................................................................................426 15.4.1.1 General-purpose I/O pins (GPIO[0:122]) ......................................................426 15.4.1.2 External interrupt request input pins (EIRQ[0:23]) .......................................426 15.5 Memory map and register description ...........................................................................................427 15.5.1 SIUL memory map .......................................................................................................427 15.5.2 Register protection ........................................................................................................428 15.5.3 Register description ......................................................................................................429 15.5.3.1 MCU ID Register #1 (MIDR1) ......................................................................429 15.5.3.2 MCU ID Register #2 (MIDR2) ......................................................................430 15.5.3.3 Interrupt Status Flag Register (ISR) ...............................................................431 15.5.3.4 Interrupt Request Enable Register (IRER) .....................................................432 15.5.3.5 Interrupt Rising-Edge Event Enable Register (IREER) .................................432 15.5.3.6 Interrupt Falling-Edge Event Enable Register (IFEER) ................................433 15.5.3.7 Interrupt Filter Enable Register (IFER) .........................................................434 15.5.3.8 Pad Configuration Registers (PCR0–PCR122) ..............................................434 15.5.3.9 Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63) ....436 15.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123) ...................440 15.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123) .........................441 15.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3) .....................441 15.5.3.13 Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI3) ...........................442 15.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO7) ....443 15.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23) .................444 15.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR) .........................................445 15.6 Functional description ...................................................................................................................446 15.6.1 Pad control ....................................................................................................................446 15.6.2 General purpose input and output pads (GPIO) ...........................................................446 15.6.3 External interrupts ........................................................................................................447 15.7 Pin muxing ....................................................................................................................................448
Chapter 16 Error Correction Status Module (ECSM)
16.1 16.2 16.3 16.4 Introduction ...................................................................................................................................449 Overview .......................................................................................................................................449 Features .........................................................................................................................................449 Memory map and register description ...........................................................................................449 16.4.1 Memory map ................................................................................................................449 16.4.2 Register description ......................................................................................................451 16.4.2.1 Processor Core Type (PCT) register ..............................................................452 16.4.2.2 Revision (REV) register .................................................................................452
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16.4.2.3 IPS Module Configuration (IMC) register .....................................................453 16.4.2.4 Miscellaneous Wakeup Control Register (MWCR) .......................................453 16.4.2.5 Miscellaneous Interrupt Register (MIR) ........................................................455 16.4.2.6 Miscellaneous User-Defined Control Register (MUDCR) ............................456 16.4.2.7 ECC registers .................................................................................................457 16.4.2.8 Flash ECC Attributes (FEAT) register ...........................................................466 16.4.3 Spp_ips_reg_protection ................................................................................................474
Chapter 17 System Timer Module (STM)
17.1 Introduction ...................................................................................................................................475 17.1.1 Overview ......................................................................................................................475 17.1.2 Features .........................................................................................................................475 17.1.3 Modes of Operation ......................................................................................................475 17.2 External Signal Description ..........................................................................................................475 17.3 Memory Map and Register Definition ..........................................................................................475 17.3.1 Memory Map ................................................................................................................475 17.3.2 Register Descriptions ....................................................................................................476 17.3.2.1 STM Control Register (STM_CR) .................................................................476 17.3.2.2 STM Count Register (STM_CNT) ................................................................477 17.3.2.3 STM Channel Control Register (STM_CCRn) ..............................................478 17.3.2.4 STM Channel Interrupt Register (STM_CIRn) .............................................478 17.3.2.5 STM Channel Compare Register (STM_CMPn) ...........................................479 17.4 Functional Description ..................................................................................................................480
Chapter 18 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
Overview .......................................................................................................................................481 Features .........................................................................................................................................481 Device-specific information ..........................................................................................................483 Modes of operation ........................................................................................................................483 18.4.1 Functional mode ...........................................................................................................483 18.4.2 Debug mode ..................................................................................................................484 18.5 Register descriptions .....................................................................................................................484 18.5.1 RTC Supervisor Control Register (RTCSUPV) ...........................................................484 18.5.2 RTC Control Register (RTCC) .....................................................................................486 18.5.3 RTC Status Register (RTCS) ........................................................................................488 18.5.4 RTC Counter Register (RTCCNT) ...............................................................................489 18.6 RTC functional description ...........................................................................................................489 18.7 API functional description ............................................................................................................490 18.1 18.2 18.3 18.4
Chapter 19 Boot Assist Module (BAM)
19.1 Overview .......................................................................................................................................491 19.1.1 Features .........................................................................................................................491
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19.1.2 Boot modes ...................................................................................................................491 19.2 Memory map .................................................................................................................................491 19.3 Functional description ...................................................................................................................492 19.3.1 Entering boot modes .....................................................................................................492 19.3.2 Reset Configuration Half Word Source (RCHW) ........................................................493 19.3.3 Single chip boot mode ..................................................................................................493 19.3.3.1 Boot and alternate boot ..................................................................................494 19.3.4 Boot through BAM .......................................................................................................494 19.3.4.1 Executing BAM .............................................................................................494 19.3.4.2 BAM software flow .......................................................................................494 19.3.4.3 BAM resources ..............................................................................................495 19.3.4.4 Download and execute the new code .............................................................496 19.3.4.5 Download 64-bit password and password check ...........................................496 19.3.4.6 Download start address, VLE bit and code size .............................................497 19.3.4.7 Download data ...............................................................................................498 19.3.4.8 Execute code ..................................................................................................498 19.3.5 Boot from UART ..........................................................................................................499 19.3.5.1 Configuration .................................................................................................499 19.3.5.2 Protocol ..........................................................................................................499 19.3.6 Boot from FlexCAN .....................................................................................................500 19.3.6.1 Configuration .................................................................................................500 19.3.6.2 Protocol ..........................................................................................................500 19.3.7 Interrupts .......................................................................................................................501
Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
20.1 Introduction ...................................................................................................................................503 20.1.1 Overview of the eMIOS module ..................................................................................503 20.1.2 Features of the eMIOS module .....................................................................................503 20.1.3 Modes of operation .......................................................................................................503 20.1.4 Channel implementation ...............................................................................................504 20.1.5 Unified channel block ...................................................................................................506 20.1.5.1 Channel mode selection .................................................................................506 20.2 External signal description ............................................................................................................506 20.3 Memory map and register description ...........................................................................................506 20.3.1 Memory map ................................................................................................................506 20.3.1.1 Unified Channel memory map .......................................................................507 20.3.2 Register description ......................................................................................................508 20.3.2.1 eMIOS Module Configuration Register (EMIOSMCR) ................................508 20.3.2.2 eMIOS Global FLAG (EMIOSGFLAG) Register .........................................509 20.3.2.3 eMIOS Output Update Disable (EMIOSOUDIS) Register ...........................510 20.3.2.4 eMIOS Disable Channel (EMIOSUCDIS) Register ......................................511 20.3.2.5 eMIOS UC A (EMIOSA[n]) Register ...........................................................511 20.3.2.6 eMIOS UC B (EMIOSB[n]) Register ............................................................512 20.3.2.7 eMIOS UC Counter (EMIOSCNT[n]) Register ............................................513
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20.3.2.8 eMIOS UC Control (EMIOSC[n]) Register ..................................................513 20.3.2.9 eMIOS UC Status (EMIOSS[n]) Register .....................................................518 20.3.2.10 eMIOS UC Alternate A Register (EMIOSALTA[n]) ....................................519 20.4 Functional description ...................................................................................................................519 20.4.1 Unified Channel (UC) ..................................................................................................520 20.4.1.1 UC modes of operation ..................................................................................522 20.4.1.2 Input Programmable Filter (IPF) ....................................................................549 20.4.1.3 Clock Prescaler (CP) ......................................................................................550 20.4.1.4 Effect of Freeze on the Unified Channel ........................................................550 20.4.2 IP Bus Interface Unit (BIU) .........................................................................................551 20.4.2.1 Effect of Freeze on the BIU ...........................................................................551 20.4.3 Global Clock Prescaler Submodule (GCP) ..................................................................551 20.4.3.1 Effect of Freeze on the GCP ..........................................................................551 20.5 Initialization/Application information ...........................................................................................551 20.5.1 Considerations ..............................................................................................................551 20.5.2 Application information ...............................................................................................552 20.5.2.1 Time base generation .....................................................................................552 20.5.2.2 Coherent accesses ..........................................................................................554 20.5.2.3 Channel/Modes initialization .........................................................................554
Chapter 21 Wakeup Unit (WKPU)
21.1 21.2 21.3 21.4 Overview .......................................................................................................................................555 Features .........................................................................................................................................556 External signal description ............................................................................................................557 Memory map and register description ...........................................................................................557 21.4.1 Memory map ................................................................................................................557 21.4.2 Register description ......................................................................................................558 21.4.2.1 NMI Status Flag Register (NSR) ...................................................................559 21.4.2.2 NMI Configuration Register (NCR) ..............................................................560 21.4.2.3 Wakeup/Interrupt Status Flag Register (WISR) .............................................561 21.4.2.4 Interrupt Request Enable Register (IRER) .....................................................562 21.4.2.5 Wakeup Request Enable Register (WRER) ...................................................562 21.4.2.6 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) ...............563 21.4.2.7 Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) ..............563 21.4.2.8 Wakeup/Interrupt Filter Enable Register (WIFER) .......................................564 21.4.2.9 Wakeup/Interrupt Pullup Enable Register (WIPUER) ...................................564 21.5 Functional description ...................................................................................................................565 21.5.1 General .........................................................................................................................565 21.5.2 Non-maskable interrupts ..............................................................................................565 21.5.2.1 NMI management ..........................................................................................566 21.5.3 External wakeups/interrupts .........................................................................................567 21.5.3.1 External interrupt management ......................................................................568 21.5.4 On-chip wakeups ..........................................................................................................568 21.5.4.1 On-chip wakeup management ........................................................................568
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Chapter 22 System Status and Configuration Module (SSCM)
22.1 Introduction ...................................................................................................................................569 22.1.1 Overview ......................................................................................................................569 22.1.2 Features .........................................................................................................................569 22.1.3 Modes of operation .......................................................................................................570 22.2 Memory map and register description ...........................................................................................570 22.2.1 Memory map ................................................................................................................570 22.2.2 Register description ......................................................................................................571 22.2.2.1 System Status Register (STATUS) .................................................................571 22.2.2.2 System Memory Configuration Register (MEMCONFIG) ...........................572 22.2.2.3 Error Configuration (ERROR) .......................................................................573 22.2.2.4 Debug Status Port Register (DEBUGPORT) .................................................575 22.2.2.5 Password comparison registers ......................................................................576 22.3 Functional description ...................................................................................................................577
Chapter 23 Analog-to-Digital Converter (ADC)
23.1 Overview .......................................................................................................................................579 23.1.1 Device-specific features ...............................................................................................579 23.1.2 Device-specific implementation ...................................................................................580 23.2 Introduction ...................................................................................................................................580 23.3 Functional description ...................................................................................................................581 23.3.1 Analog channel conversion ..........................................................................................581 23.3.1.1 Normal conversion .........................................................................................581 23.3.1.2 Start of normal conversion .............................................................................581 23.3.1.3 Normal conversion operating modes .............................................................581 23.3.1.4 Injected channel conversion ...........................................................................582 23.3.1.5 Abort conversion ............................................................................................583 23.3.2 Analog clock generator and conversion timings ..........................................................584 23.3.3 ADC sampling and conversion timing .........................................................................584 23.3.3.1 ADC_1 ...........................................................................................................584 23.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................587 23.3.4.1 Overview ........................................................................................................587 23.3.4.2 CTU in trigger mode ......................................................................................587 23.3.5 Presampling ..................................................................................................................588 23.3.5.1 Introduction ....................................................................................................588 23.3.5.2 Presampling channel enable signals ...............................................................588 23.3.6 Programmable analog watchdog ..................................................................................589 23.3.6.1 Introduction ....................................................................................................589 23.3.7 DMA functionality .......................................................................................................590 23.3.8 Interrupts .......................................................................................................................590 23.3.9 External decode signals delay ......................................................................................591 23.3.10 Power-down mode ........................................................................................................591 23.3.11 Auto-clock-off mode ....................................................................................................591
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23.4 Register descriptions .....................................................................................................................592 23.4.1 Introduction ..................................................................................................................592 23.4.2 Control logic registers ..................................................................................................597 23.4.2.1 Main Configuration Register (MCR) .............................................................597 23.4.2.2 Main Status Register (MSR) ..........................................................................599 23.4.3 Interrupt registers ..........................................................................................................600 23.4.3.1 Interrupt Status Register (ISR) .......................................................................600 23.4.3.2 Channel Pending Registers (CEOCFR[0..2]) ................................................601 23.4.3.3 Interrupt Mask Register (IMR) ......................................................................602 23.4.3.4 Channel Interrupt Mask Register (CIMR[0..2]) .............................................604 23.4.3.5 Watchdog Threshold Interrupt Status Register (WTISR) ..............................605 23.4.3.6 Watchdog Threshold Interrupt Mask Register (WTIMR) ..............................606 23.4.4 DMA registers ..............................................................................................................608 23.4.4.1 DMA Enable Register (DMAE) ....................................................................608 23.4.4.2 DMA Channel Select Register (DMAR[0..2]) ...............................................609 23.4.5 Threshold registers .......................................................................................................611 23.4.5.1 Threshold Register (THRHLR) .....................................................................611 23.4.6 Presampling registers ....................................................................................................612 23.4.6.1 Presampling Control Register (PSCR) ...........................................................612 23.4.6.2 Presampling Register (PSR[0..]) ....................................................................612 23.4.7 Conversion timing registers CTR[0..2] ........................................................................615 23.4.8 Mask registers ...............................................................................................................616 23.4.8.1 Introduction ....................................................................................................616 23.4.8.2 Normal Conversion Mask Registers (NCMR[0..2]) ......................................616 23.4.8.3 Injected Conversion Mask Registers (JCMR[0..2]) .......................................618 23.4.9 Delay registers ..............................................................................................................620 23.4.9.1 Decode Signals Delay Register (DSDR) .......................................................620 23.4.9.2 Power-down Exit Delay Register (PDEDR) ..................................................620 23.4.10 Data registers ................................................................................................................622 23.4.10.1 Introduction ....................................................................................................622 23.4.10.2 Channel Data Register (CDR[0..95]) .............................................................622 23.4.11 Watchdog register .........................................................................................................623 23.4.11.1 Channel Watchdog Select Register (CWSELR[0..11]) ..................................623 23.4.11.2 Channel Watchdog Enable Register (CWENRx, x = [0..2]) ..........................624 23.4.11.3 Analog Watchdog Out of Range Register (AWORRx, x = [0..2]) .................625
Chapter 24 Safety
24.1 Register protection ........................................................................................................................629 24.1.1 Introduction ..................................................................................................................629 24.1.1.1 Overview ........................................................................................................629 24.1.1.2 Features ..........................................................................................................629 24.1.1.3 Modes of operation ........................................................................................630 24.1.2 External signal description ...........................................................................................630 24.1.3 Memory map and register description ..........................................................................630
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24.1.3.1 Memory map ..................................................................................................631 24.1.3.2 Register description ........................................................................................632 24.1.4 Functional description ..................................................................................................634 24.1.4.1 General ...........................................................................................................634 24.1.4.2 Change lock settings ......................................................................................635 24.1.4.3 Access errors ..................................................................................................638 24.1.5 Reset .............................................................................................................................639 24.2 Software Watchdog Timer (SWT) .................................................................................................639 24.2.1 Overview ......................................................................................................................639 24.2.2 Features .........................................................................................................................639 24.2.3 Modes of operation .......................................................................................................639 24.2.4 External signal description ...........................................................................................640 24.2.5 Memory map and register description ..........................................................................640 24.2.5.1 Memory map ..................................................................................................640 24.2.5.2 Register description ........................................................................................641 24.2.6 Functional description ..................................................................................................645
Chapter 25 Deserial Serial Peripheral Interface (DSPI)
Introduction ...................................................................................................................................647 Block diagram ...............................................................................................................................647 Overview .......................................................................................................................................648 Features .........................................................................................................................................648 Modes of operation ........................................................................................................................649 25.5.1 Master mode .................................................................................................................649 25.5.2 Slave mode ...................................................................................................................649 25.5.3 Module Disable mode ...................................................................................................650 25.5.4 External Stop mode ......................................................................................................650 25.5.5 Debug mode ..................................................................................................................650 25.6 External signal description ............................................................................................................650 25.6.1 Signal overview ............................................................................................................650 25.6.2 Signal names and descriptions ......................................................................................651 25.6.2.1 Peripheral Chip Select / Slave Select (CS0_x) ..............................................651 25.6.2.2 Peripheral Chip Selects 1–3 (CS1:3_x) .........................................................651 25.6.2.3 Peripheral Chip Select 4 (CS4_x) ..................................................................651 25.6.2.4 Peripheral Chip Select 5 / Peripheral Chip Select Strobe (CS5_x) 651 25.6.2.5 Serial Input (SIN_x) .......................................................................................651 25.6.2.6 Serial Output (SOUT_x) ................................................................................651 25.6.2.7 Serial Clock (SCK_x) .....................................................................................651 25.7 Memory map and register description ...........................................................................................652 25.7.1 Memory map ................................................................................................................652 25.7.2 Register description ......................................................................................................653 25.7.2.1 DSPI Module Configuration Register (DSPIx_MCR) ...................................653 25.7.2.2 DSPI Transfer Count Register (DSPIx_TCR) ...............................................656
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25.1 25.2 25.3 25.4 25.5
25.7.2.3 DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) ...........657 25.7.2.4 DSPI Status Register (DSPIx_SR) .................................................................665 25.7.2.5 DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) ..... 667 25.7.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ........................................669 25.7.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) ..............................................671 25.7.2.8 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) ...................................672 25.7.2.9 DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn) ....................................673 25.8 Functional description ...................................................................................................................673 25.8.1 Modes of operation .......................................................................................................674 25.8.1.1 Master mode ...................................................................................................675 25.8.1.2 Slave mode .....................................................................................................675 25.8.1.3 Module Disable mode ....................................................................................675 25.8.1.4 External Stop mode ........................................................................................675 25.8.1.5 Debug mode ...................................................................................................675 25.8.2 Start and stop of DSPI transfers ...................................................................................676 25.8.3 Serial peripheral interface (SPI) configuration .............................................................677 25.8.3.1 SPI Master mode ............................................................................................677 25.8.3.2 SPI Slave mode ..............................................................................................678 25.8.3.3 FIFO disable operation ...................................................................................678 25.8.3.4 Transmit First In First Out (TX FIFO) buffering mechanism ........................678 25.8.3.5 Receive First In First Out (RX FIFO) buffering mechanism .........................679 25.8.4 DSPI baud rate and clock delay generation ..................................................................680 25.8.4.1 Baud rate generator ........................................................................................680 25.8.4.2 CS to SCK delay (tCSC) ................................................................................681 25.8.4.3 After SCK delay (tASC) ................................................................................681 25.8.4.4 Delay after transfer (tDT) ..............................................................................682 25.8.4.5 Peripheral chip select strobe enable (CS5_x) ................................................682 25.8.5 Transfer formats ...........................................................................................................683 25.8.5.1 Classic SPI transfer format (CPHA = 0) ........................................................685 25.8.5.2 Classic SPI transfer format (CPHA = 1) ........................................................686 25.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) ..................................687 25.8.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1) ..................................688 25.8.5.5 Continuous selection format ..........................................................................689 25.8.5.6 Clock polarity switching between DSPI transfers .........................................691 25.8.6 Continuous serial communications clock .....................................................................691 25.8.7 Interrupt/DMA requests ................................................................................................693 25.8.7.1 End of Queue Interrupt Request (EOQF) ......................................................693 25.8.7.2 Transmit FIFO Fill Interrupt or DMA Request (TFFF) .................................693 25.8.7.3 Transfer Complete Interrupt Request (TCF) ..................................................693 25.8.7.4 Transmit FIFO Underflow Interrupt Request (TFUF) ...................................694 25.8.7.5 Receive FIFO Drain Interrupt or DMA Request (RFDF) ..............................694 25.8.7.6 Receive FIFO Overflow Interrupt Request (RFOF) ......................................694 25.8.7.7 FIFO Overrun Request (TFUF) or (RFOF) ...................................................694 25.8.8 Power saving features ...................................................................................................694
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25.8.8.1 External Stop mode ........................................................................................694 25.8.8.2 Module Disable mode ....................................................................................695 25.8.8.3 Slave interface signal gating ..........................................................................695 25.9 Initialization and application information .....................................................................................695 25.9.1 How to change queues ..................................................................................................695 25.9.2 Baud rate settings .........................................................................................................696 25.9.3 Delay settings ...............................................................................................................697 25.9.4 Calculation of FIFO pointer addresses .........................................................................697 25.9.4.1 Address calculation for the first-in entry and last-in entry in the TX FIFO 698 25.9.4.2 Address calculation for the first-in entry and last-in entry in the RX FIFO 698
Chapter 26 FlexCAN module
26.1 Device-Specific Features ...............................................................................................................701 26.2 Introduction ...................................................................................................................................701 26.2.1 Overview ......................................................................................................................702 26.2.2 FlexCAN module features ............................................................................................703 26.2.3 Modes of operation .......................................................................................................704 26.3 External signal description ............................................................................................................705 26.3.1 Overview ......................................................................................................................705 26.3.2 Signal descriptions ........................................................................................................705 26.3.2.1 CAN Rx ..........................................................................................................705 26.3.2.2 CAN Tx ..........................................................................................................705 26.4 Memory map/register definition ....................................................................................................705 26.4.1 FlexCAN memory mapping .........................................................................................705 26.4.2 Message Buffer Structure .............................................................................................708 26.4.3 Rx FIFO structure .........................................................................................................711 26.4.4 Register descriptions ....................................................................................................712 26.4.4.1 Module Configuration Register (MCR) .........................................................712 26.4.4.2 Control Register (CTRL) ...............................................................................716 26.4.4.3 Free Running Timer (TIMER) .......................................................................719 26.4.4.4 Rx Global Mask (RXGMASK) ......................................................................720 26.4.4.5 Rx 14 Mask (RX14MASK) ...........................................................................722 26.4.4.6 Rx 15 Mask (RX15MASK) ...........................................................................723 26.4.4.7 Error Counter Register (ECR) ........................................................................723 26.4.4.8 Error and Status Register (ESR) ....................................................................724 26.4.4.9 Interrupt Masks 2 Register (IMASK2) ..........................................................727 26.4.4.10 Interrupt Masks 1 Register (IMASK1) ..........................................................728 26.4.4.11 Interrupt Flags 2 Register (IFLAG2) .............................................................728 26.4.4.12 Interrupt Flags 1 Register (IFLAG1) .............................................................729 26.4.4.13 Rx Individual Mask Registers (RXIMR0–RXIMR63) ..................................730 26.5 Functional Description ..................................................................................................................731 26.5.1 Overview ......................................................................................................................731
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26.5.2 Local Priority Transmission .........................................................................................732 26.5.3 Transmit Process ...........................................................................................................732 26.5.4 Arbitration process .......................................................................................................733 26.5.5 Receive Process ............................................................................................................734 26.5.6 Matching Process ..........................................................................................................735 26.5.7 Data Coherence ............................................................................................................736 26.5.7.1 Transmission Abort Mechanism ....................................................................736 26.5.7.2 Message Buffer Deactivation .........................................................................737 26.5.7.3 Message Buffer Lock Mechanism .................................................................738 26.5.8 Rx FIFO ........................................................................................................................739 26.5.9 CAN Protocol Related Features ...................................................................................740 26.5.9.1 Remote Frames ..............................................................................................740 26.5.9.2 Overload Frames ............................................................................................740 26.5.9.3 Time Stamp ....................................................................................................740 26.5.9.4 Protocol Timing .............................................................................................741 26.5.9.5 Arbitration and Matching Timing ..................................................................743 26.5.10 Modes of Operation details ..........................................................................................744 26.5.10.1 Freeze mode ...................................................................................................744 26.5.10.2 Module Disable mode ....................................................................................744 26.5.10.3 Stop mode .......................................................................................................745 26.5.11 Interrupts .......................................................................................................................746 26.5.12 Bus interface .................................................................................................................746 26.6 Initialization/Application Information ..........................................................................................747 26.6.1 FlexCAN initialization sequence ..................................................................................747 26.6.2 FlexCAN Addressing and RAM size configurations ...................................................748
Chapter 27 Periodic Interrupt Timer (PIT)
27.1 Introduction ...................................................................................................................................749 27.1.1 Overview ......................................................................................................................749 27.1.2 Features .........................................................................................................................749 27.2 Signal description ..........................................................................................................................750 27.3 Memory map and register description ...........................................................................................750 27.3.1 Memory map ................................................................................................................750 27.3.2 Register description ......................................................................................................750 27.3.2.1 PIT Module Control Register (PITMCR) ......................................................751 27.3.2.2 Timer Load Value Register (LDVAL) ............................................................752 27.3.2.3 Current Timer Value Register (CVAL) ..........................................................753 27.3.2.4 Timer Control Register (TCTRL) ..................................................................754 27.3.2.5 Timer Flag Register (TFLG) ..........................................................................755 27.4 Functional description ...................................................................................................................755 27.4.1 General .........................................................................................................................755 27.4.1.1 Timers ............................................................................................................755 27.4.1.2 Debug mode ...................................................................................................756 27.4.2 Interrupts .......................................................................................................................756
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27.5 Initialization and application information .....................................................................................757 27.5.1 Example configuration .................................................................................................757
Chapter 28 Cross Triggering Unit (CTU)
Introduction ...................................................................................................................................759 Main features .................................................................................................................................759 Block diagram ...............................................................................................................................759 Register descriptions .....................................................................................................................759 28.4.1 Event Configuration Register (CTU_EVTCFGRx) (x = 0...31) ..................................761 28.5 Functional description ...................................................................................................................762 28.5.1 Trigger interrupt request ...............................................................................................763 28.5.2 Channel value ...............................................................................................................763 28.1 28.2 28.3 28.4
Chapter 29 LIN Controller (LINFlex)
29.1 Introduction ...................................................................................................................................767 29.2 Main features .................................................................................................................................767 29.2.1 LIN mode features ........................................................................................................767 29.2.2 UART mode features ....................................................................................................767 29.2.3 Features common to LIN and UART ...........................................................................767 29.3 General description .......................................................................................................................768 29.4 Fractional baud rate generation .....................................................................................................769 29.5 Operating modes ...........................................................................................................................771 29.5.1 Initialization mode ........................................................................................................772 29.5.2 Normal mode ................................................................................................................772 29.5.3 Low power mode (Sleep) .............................................................................................772 29.6 Test modes .....................................................................................................................................772 29.6.1 Loop Back mode ...........................................................................................................772 29.6.2 Self Test mode ..............................................................................................................773 29.7 Memory map and registers description .........................................................................................773 29.7.1 Memory map ................................................................................................................773 29.7.2 Register description ......................................................................................................775 29.7.2.1 LIN control register 1 (LINCR1) ...................................................................775 29.7.2.2 LIN interrupt enable register (LINIER) .........................................................778 29.7.2.3 LIN status register (LINSR) ...........................................................................780 29.7.2.4 LIN error status register (LINESR) ...............................................................783 29.7.2.5 UART mode control register (UARTCR) ......................................................784 29.7.2.6 UART mode status register (UARTSR) .........................................................786 29.7.2.7 LIN timeout control status register (LINTCSR) ............................................788 29.7.2.8 LIN output compare register (LINOCR) .......................................................789 29.7.2.9 LIN timeout control register (LINTOCR) ......................................................789 29.7.2.10 LIN fractional baud rate register (LINFBRR) ...............................................790 29.7.2.11 LIN integer baud rate register (LINIBRR) ....................................................791 29.7.2.12 LIN checksum field register (LINCFR) .........................................................792
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29.7.2.13 LIN control register 2 (LINCR2) ...................................................................792 29.7.2.14 Buffer identifier register (BIDR) ...................................................................794 29.7.2.15 Buffer data register LSB (BDRL) ..................................................................795 29.7.2.16 Buffer data register MSB (BDRM) ................................................................795 29.7.2.17 Identifier filter enable register (IFER) ...........................................................796 29.7.2.18 Identifier filter match index (IFMI) ...............................................................797 29.7.2.19 Identifier filter mode register (IFMR) ............................................................798 29.7.2.20 Identifier filter control register (IFCR2n) ......................................................799 29.7.2.21 Identifier filter control register (IFCR2n + 1) ................................................800 29.7.3 Register map and reset values ......................................................................................802 29.8 Functional description ...................................................................................................................806 29.8.1 UART mode ..................................................................................................................806 29.8.1.1 Buffer in UART mode ....................................................................................806 29.8.1.2 UART transmitter ...........................................................................................807 29.8.1.3 UART receiver ...............................................................................................807 29.8.1.4 Clock gating ...................................................................................................808 29.8.2 LIN mode ......................................................................................................................808 29.8.2.1 Master mode ...................................................................................................808 29.8.2.2 Slave mode .....................................................................................................810 29.8.2.3 Slave mode with identifier filtering ...............................................................812 29.8.2.4 Slave mode with automatic resynchronization ..............................................814 29.8.2.5 Clock gating ...................................................................................................816 29.8.3 8-bit timeout counter ....................................................................................................816 29.8.3.1 LIN timeout mode ..........................................................................................816 29.8.3.2 Output compare mode ....................................................................................817 29.8.4 Interrupts .......................................................................................................................818
Chapter 30 LIN Controller (LINFlexD)
30.1 Introduction ...................................................................................................................................819 30.2 Main features .................................................................................................................................819 30.2.1 LIN mode features ........................................................................................................820 30.2.2 UART mode features ....................................................................................................820 30.3 The LIN protocol ...........................................................................................................................821 30.3.1 Dominant and recessive logic levels ............................................................................821 30.3.2 LIN frames ....................................................................................................................821 30.3.3 LIN header ....................................................................................................................822 30.3.3.1 Break field ......................................................................................................822 30.3.3.2 Sync byte field ...............................................................................................822 30.3.4 Response .......................................................................................................................823 30.3.4.1 Data field ........................................................................................................823 30.3.4.2 Identifier .........................................................................................................823 30.3.4.3 Checksum .......................................................................................................823 30.4 LINFlexD and software intervention ............................................................................................824 30.5 Summary of operating modes .......................................................................................................824
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30.6 Controller-level operating modes ..................................................................................................825 30.6.1 Initialization mode ........................................................................................................825 30.6.2 Normal mode ................................................................................................................826 30.6.3 Sleep (low-power) mode ..............................................................................................826 30.7 LIN modes .....................................................................................................................................826 30.7.1 Master mode .................................................................................................................826 30.7.1.1 LIN header transmission ................................................................................826 30.7.1.2 Data transmission (transceiver as publisher) .................................................827 30.7.1.3 Data reception (transceiver as subscriber) .....................................................827 30.7.1.4 Data discard ....................................................................................................827 30.7.1.5 Error detection and handling ..........................................................................827 30.7.2 Slave mode ...................................................................................................................828 30.7.2.1 Data transmission (transceiver as publisher) .................................................828 30.7.2.2 Data reception (transceiver as subscriber) .....................................................829 30.7.2.3 Data discard ....................................................................................................829 30.7.2.4 Error detection and handling ..........................................................................829 30.7.2.5 Valid header ....................................................................................................830 30.7.2.6 Valid message .................................................................................................830 30.7.2.7 Overrun ..........................................................................................................830 30.7.3 Slave mode with identifier filtering ..............................................................................831 30.7.3.1 Filter submodes ..............................................................................................831 30.7.3.2 Identifier filter submode configuration ..........................................................832 30.7.4 Slave mode with automatic resynchronization .............................................................833 30.7.4.1 Automatic resynchronization method ............................................................833 30.7.4.2 Deviation error on the sync field ....................................................................834 30.7.4.3 Clock gating ...................................................................................................835 30.8 Test modes .....................................................................................................................................835 30.8.1 Loop Back mode ...........................................................................................................835 30.8.2 Self Test mode ..............................................................................................................835 30.9 UART mode ..................................................................................................................................836 30.9.1 Data frame structure .....................................................................................................836 30.9.1.1 8-bit data frame ..............................................................................................836 30.9.1.2 9-bit data frame ..............................................................................................836 30.9.1.3 16-bit data frame ............................................................................................837 30.9.1.4 17-bit data frame ............................................................................................837 30.9.2 Buffer ............................................................................................................................837 30.9.3 UART transmitter .........................................................................................................838 30.9.4 UART receiver ..............................................................................................................839 30.10 Memory map and register description ...........................................................................................841 30.10.1 LIN control register 1 (LINCR1) .................................................................................843 30.10.2 LIN interrupt enable register (LINIER) .......................................................................846 30.10.3 LIN status register (LINSR) .........................................................................................847 30.10.4 LIN error status register (LINESR) ..............................................................................850 30.10.5 UART mode control register (UARTCR) .....................................................................851 30.10.6 UART mode status register (UARTSR) .......................................................................854
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 27
30.10.7 LIN timeout control status register (LINTCSR) ..........................................................856 30.10.8 LIN output compare register (LINOCR) ......................................................................857 30.10.9 LIN timeout control register (LINTOCR) ....................................................................858 30.10.10 LIN fractional baud rate register (LINFBRR) ..............................................................859 30.10.11 LIN integer baud rate register (LINIBRR) ...................................................................860 30.10.12 LIN checksum field register (LINCFR) .......................................................................861 30.10.13 LIN control register 2 (LINCR2) .................................................................................861 30.10.14 Buffer identifier register (BIDR) ..................................................................................862 30.10.15 Buffer data register least significant (BDRL) ..............................................................864 30.10.16 Buffer data register most significant (BDRM) .............................................................865 30.10.17 Identifier filter enable register (IFER) ..........................................................................866 30.10.18 Identifier filter match index (IFMI) ..............................................................................866 30.10.19 Identifier filter mode register (IFMR) ..........................................................................867 30.10.20 Identifier filter control registers (IFCR0–IFCR15) ......................................................868 30.10.21 Global control register (GCR) ......................................................................................869 30.10.22 UART preset timeout register (UARTPTO) .................................................................871 30.10.23 UART current timeout register (UARTCTO) ...............................................................871 30.10.24 DMA Tx enable register (DMATXE) ...........................................................................872 30.10.25 DMA Rx enable register (DMARXE) ..........................................................................873 30.11 DMA interface ...............................................................................................................................873 30.11.1 Master node, TX mode .................................................................................................874 30.11.2 Master node, RX mode .................................................................................................877 30.11.3 Slave node, TX mode ...................................................................................................879 30.11.4 Slave node, RX mode ...................................................................................................881 30.11.5 UART node, TX mode .................................................................................................884 30.11.6 UART node, RX mode .................................................................................................886 30.11.7 Use cases and limitations ..............................................................................................888 30.12 Functional description ...................................................................................................................889 30.12.1 8-bit timeout counter ....................................................................................................889 30.12.1.1 LIN timeout mode ..........................................................................................889 30.12.1.2 Output compare mode ....................................................................................890 30.12.2 Interrupts .......................................................................................................................890 30.12.3 Fractional baud rate generation ....................................................................................892 30.13 Programming considerations .........................................................................................................894 30.13.1 Master node ..................................................................................................................894 30.13.2 Slave node ....................................................................................................................895 30.13.3 Extended frames ...........................................................................................................898 30.13.4 Timeout .........................................................................................................................899 30.13.5 UART mode ..................................................................................................................899
Chapter 31 Power Control Unit (MC_PCU)
31.1 Introduction ...................................................................................................................................901 31.1.1 Overview ......................................................................................................................901 31.1.2 Features .........................................................................................................................902
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31.2 External Signal Description ..........................................................................................................902 31.3 Memory Map and Register Definition ..........................................................................................903 31.3.1 Memory Map ................................................................................................................903 31.3.2 Register Descriptions ....................................................................................................904 31.3.2.1 Power Domain #0 Configuration Register (PCU_PCONF0) ........................904 31.3.2.2 Power Domain #1 Configuration Register (PCU_PCONF1) ........................906 31.3.2.3 Power Domain Status Register (PCU_PSTAT) ..............................................906 31.4 Functional Description ..................................................................................................................907 31.4.1 General .........................................................................................................................907 31.4.2 Reset / Power-On Reset ................................................................................................907 31.4.3 MC_PCU Configuration ...............................................................................................907 31.4.4 Mode Transitions ..........................................................................................................907 31.4.4.1 STANDBY0 Mode Transition ........................................................................907 31.4.4.2 Power Saving for Memories During STANDBY0 Mode ...............................909 31.5 Initialization Information ..............................................................................................................909 31.6 Application Information ................................................................................................................909 31.6.1 STANDBY0 Mode Considerations ...............................................................................909
Chapter 32 Voltage Regulators and Power Supplies
32.1 Voltage regulators ..........................................................................................................................911 32.1.1 High power regulator (HPREG) ...................................................................................911 32.1.2 Low power regulator (LPREG) ....................................................................................911 32.1.3 Ultra low power regulator (ULPREG) .........................................................................912 32.1.4 LVDs and POR .............................................................................................................912 32.1.5 VREG digital interface .................................................................................................912 32.1.6 Register description ......................................................................................................913 32.2 Power supply strategy ...................................................................................................................913 32.3 Power domain organization ...........................................................................................................914
Chapter 33 IEEE 1149.1 Test Access Port Controller (JTAGC)
Introduction ...................................................................................................................................915 Block Diagram ..............................................................................................................................915 Overview .......................................................................................................................................915 Features .........................................................................................................................................916 Modes of Operation .......................................................................................................................916 33.5.1 Reset .............................................................................................................................916 33.5.2 IEEE 1149.1-2001 Defined Test Modes .......................................................................916 33.5.2.1 Bypass Mode ..................................................................................................917 33.5.2.2 TAP Sharing Mode .........................................................................................917 33.6 External Signal Description ..........................................................................................................917 33.7 Memory Map and Register Description ........................................................................................917 33.7.1 Instruction Register ......................................................................................................918 33.7.2 Bypass Register ............................................................................................................918
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33.1 33.2 33.3 33.4 33.5
33.7.3 Device Identification Register ......................................................................................918 33.7.4 Boundary Scan Register ...............................................................................................919 33.8 Functional Description ..................................................................................................................919 33.8.1 JTAGC Reset Configuration .........................................................................................919 33.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................919 33.8.3 TAP Controller State Machine .....................................................................................920 33.8.3.1 Selecting an IEEE 1149.1-2001 Register .......................................................921 33.8.4 JTAGC Instructions ......................................................................................................921 33.8.4.1 BYPASS Instruction .......................................................................................921 33.8.4.2 ACCESS_AUX_TAP_x Instructions .............................................................922 33.8.4.3 EXTEST — External Test Instruction ...........................................................922 33.8.4.4 IDCODE Instruction ......................................................................................922 33.8.4.5 SAMPLE Instruction ......................................................................................922 33.8.4.6 SAMPLE/PRELOAD Instruction ..................................................................922 33.8.5 Boundary Scan ..............................................................................................................923 33.9 e200z0 OnCE Controller ...............................................................................................................923 33.9.1 e200z0 OnCE Controller Block Diagram .....................................................................923 33.9.2 e200z0 OnCE Controller Functional Description ........................................................924 33.9.2.1 Enabling the TAP Controller ..........................................................................924 33.9.3 e200z0 OnCE Controller Register Description ............................................................924 33.9.3.1 OnCE Command Register (OCMD) ..............................................................924 33.10 Initialization/Application Information ..........................................................................................926
Appendix A Register Under Protection Appendix B Revision History
MPC5602D Microcontroller Reference Manual, Rev. 3.1 30 Preliminary Freescale Semiconductor
Chapter 1 Overview
Chapter 1 Overview
1.1 Introduction
The MPC5602D is a Power Architecture™ based microcontroller that targets automotive vehicle body applications such as: • Central body electronics • Vehicle body controllers • Smart junction boxes • Front modules • Body peripherals • Door control • Seat control The MPC5602D family expands the range of the MPC560xB/C microcontroller family. It provides the scalability needed to implement platform approaches and delivers the performance required through the use of increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the MPC5602D automotive controller complies with the Power Architecture™ specification, and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power consumption. It also capitalizes on the available development infrastructure of current Power Architecture™ devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. This document describes the features of the MPC5602D and options available within the family members, and highlights important electrical and physical characteristics of the device.
1.2
MPC5602D Device Comparison
Table 1-1. MPC5602D device comparison
Device Feature MPC560 1DxLH MPC560 1DxLL e200z0 Up to 48 MHz 128 KB 64 KB (4 × 16 KB) 12 KB 16 KB 256 KB MPC560 2DxLH MPC560 2DxLL
Table 1-1 summarizes the MPC5602D family of microcontrollers.
CPU Execution speed Code Flash Data Flash RAM
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Chapter 1 Overview
Table 1-1. MPC5602D device comparison (continued)
Device Feature MPC560 1DxLH MPC560 1DxLL 16 ch 16 ch, 12-bit 33 ch, 12-bit 16 ch, 12-bit 33 ch, 12-bit MPC560 2DxLH MPC560 2DxLL
eDMA ADC CTU Total timer I/O eMIOS • Type X2 • Type Y3 • Type G4 • Type H5 SCI (LINFlex) SPI (DSPI) CAN (FlexCAN) GPIO6 Debug Package
1 2 3 4 5 6 1
16 ch 13 ch, 16-bit 2 ch — 7 ch 4 ch 28 ch, 16-bit 5 ch 9 ch 7 ch 7 ch 3 2 1 45 79 JTAG 64 LQFP 100 LQFP 64 LQFP 100 LQFP 45 79 13 ch, 16-bit 2 ch — 7 ch 4 ch 28 ch, 16-bit 5 ch 9 ch 7 ch 7 ch
Refer to eMIOS section of device reference manual for information on the channel configuration and functions Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC Type Y = OPWMT + OPWMB + SAIC + SAOC Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC I/O count based on multiplexing with peripherals
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Chapter 1 Overview
1.3
Device Block Diagram
Figure 1-1. MPC5602D series block diagram
JTAG JTAG Port Instructions Nexus 1 e200z0h NMI SIUL Voltage Regulator NMI Interrupt requests from peripheral blocks INTC Clocks FMPLL CMU DMA (Master) Data (Master) (Master) 64-bit 2 x 3 Crossbar Switch RAM 16 KB Code Flash 256 KB Data Flash 64 KB
Figure 1-1 shows a top-level block diagram of the MPC5602D.
SRAM Controller
Flash Controller
(Slave) (Slave) (Slave)
RTC
STM
SWT
ECSM
PIT
MC_RGM MC_CGM MC_ME MC_PCU
BAM
SSCM
Peripheral Bridge
Interrupt Request
SIUL Reset Control External Interrupt Request IMUX GPIO & Pad Control
33 ch. ADC
CTU
1x eMIOS
3x LINFlex
2x DSPI
1x FlexCAN
WKPU
Interrupt Request
I/O Legend: ADC BAM CAN MC_CGM CMU CTU DMA DSPI eMIOS FMPLL GPIO IMUX INTC JTAG LINFlex
...
...
...
...
Analog-to-Digital Converter Boot Assist Module Controller Area Network (FlexCAN) Clock Generation Module Clock Monitor Unit Cross Triggering Unit Direct Memory Access Deserial Serial Peripheral Interface Enhanced Modular Input Output System Frequency-Modulated Phase-Locked Loop General Purpose I/O Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support)
ECSM MC_ME Nexus NMI MC_PCU PIT MC_RGM RTC SIUL SRAM SSCM STM SWT WKPU
Miscellaneous Control Module Mode Entry Module NexuS Development Interface (NDI) Level Non-Maskable Interrupt Power Control Unit Periodic Interrupt Timer Reset Generation Module Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit
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Chapter 1 Overview
1.4
1.4.1
Feature Summary
e200z0h core processor
The e200z0h core includes the following features: • High performance, low cost e200z0h core processor for managing peripherals and interrupts • Single issue 4-stage pipelined in-order execution, 32-bit Power Architecture™ CPU • Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions — Results in efficient code size footprint — Minimizes impact on performance • Branch processing acceleration using lookahead instruction buffer • Load/store unit — 1-cycle load latency — Misaligned access support — No load-to-use pipeline bubbles • Thirty-two 32-bit general purpose registers (GPRs) • Separate instruction bus and load/store bus Harvard architecture with separate instruction and load/store buses • Hardware vectored interrupt support • Reservation instructions for implementing read-modify-write constructs • Multi-cycle divide word (divw) and load multiple word (lmw) store multiple word (smw) multiple class instructions, can be interrupted to prevent increases in interrupt latency • Extensive system development support through Nexus debug port
1.4.2
Crossbar Switch (XBAR)
The following summarizes the MPC5602D’s implementation of the crossbar switch: • 3 master ports: — CPU instruction bus — CPU load/store bus — eDMA • Multiple bus slaves to enable access to flash memory, SRAM and peripherals • Crossbar supports up to 2 consecutive transfers at any one time • 32-bit internal address bus, 32-bit internal data bus • Fixed priority arbitration based on port master
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Chapter 1 Overview
1.4.3
Interrupt Controller (INTC)
The MPC5602D implements an interrupt controller that features the following: • Unique 9-bit vector for each of the 231 separate interrupt sources • 8 software triggerable interrupt sources • 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source • Ability to modify the ISR or task priority — Modifying the priority can be used to implement Priority Ceiling Protocol for accessing shared resources • External high priority interrupt directly accessing the main core critical interrupt mechanism
1.4.4
System Integration Unit Lite (SIUL)
The SIUL features the following: • Up to 4 levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for each package • Centralized general purpose input output (GPIO) control of up to 79 input/output pins (package dependent) • All GPIO pins independently configurable to support pull-up pull down, or no pull • Reading and writing to GPIO supported both as individual pins and 16-bit wide ports • All peripheral pins can be alternatively configured as both general purpose input or output pins except ADC channels which support alternative configuration as general purpose inputs, with selected pins able to also support outputs • Direct readback of the pin value supported on all digital output pins through the SIUL • Configurable digital input filter that can be applied to up to 16 general purpose input pins for noise elimination on external interrupts • Register configuration protected against change with soft lock for temporary guard or hard lock to prevent modification until next reset • Support for two 32-bit virtual ports via the DSPI serialization
1.4.5
Flash Memory
The on-chip flash memory on the MPC5602D features the following: • Up to 256 Kbyte burst flash memory — 2 x 128-bit page buffers with programmable prefetch control — Typical flash-memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 48 MHz — Page buffers can be allocated for code-only, fixed partitions of code and data, all available for any access — 64-bit ECC with single-bit correction, double-bit detection for data integrity • Censorship protection scheme to prevent flash-memory content visibility
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Chapter 1 Overview
•
• • • •
Separate dedicated data flash for EEPROM emulation — 4 erase sectors each containing 16 KB of memory — Offers read-while-write functionality from main program space Small block flash-memory arrangement in main array to support features such as boot block, operating system block Hardware managed flash memory writes, erase and verify sequence Flash-memory partitioning (see Table 1-2) Error correction status — Configurable error-correcting codes (ECC) reporting for RAM and flash memory — Supports optional reporting of single-bit errors — Protected mechanism for reporting of corrected ECC values — Error address recorded including Access type and Master — Flash-memory ECC reporting registers mirrored into ECSM address space but data comes from the flash-memory module — Flash-memory module can be interrogated to provide ECC bit error location — Margin read for flash-memory array supported for initial program verification
Table 1-2. Flash Partitioning
MPC5601D Array Address 128 KB Array_A Flash_Base + 0x0000_0000 Flash_Base + 0x0000_8000 Flash_Base + 0x0000_C000 Flash_Base + 0x0001_0000 Flash_Base + 0x0001_8000 Flash_Base + 0x0002_0000 Array_D Data Flash Block + 0x0000_0000 Data Flash Block + 0x0000_4000 Data Flash Block + 0x0000_8000 Data Flash Block + 0x0000_C000 32 KB 16 KB 16 KB 32 KB 32 KB — 16 KB 16 KB 16 KB 16 KB 256 KB 32 KB 16 KB 16 KB 32 KB 32 KB 128 KB 16 KB 16 KB 16 KB 16 KB MPC5602D
1.4.6
SRAM
The on-chip SRAM on the MPC5602D features the following: • Up to 16 KB general purpose RAM
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Chapter 1 Overview
• • • •
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block 32-bit ECC with single-bit correction, double-bit detection for data integrity Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory User transparent ECC encoding and decoding for byte, half word, and word accesses
1.4.7
Boot Assist Module (BAM)
The device implements a Boot Assist Module (BAM): • Block of read-only memory containing VLE code which is executed according to boot mode of the device • Download of code into internal SRAM possible via FlexCAN or LINFlex, afterwhich code can be executed
1.4.8
Enhanced Modular Input Output System (eMIOS)
The MPC5602D implements a scaled-down version of the eMIOS module: • Up to 28 timed I/O channels with 16-bit counter resolution • Buffered updates • Support for shifted PWM outputs to minimize occurrence of concurrent edges • Supports configurable trigger outputs for ADC conversion for synchronization to channel output waveforms • Edge-aligned output pulse width modulation — Programmable pulse period and duty cycle — Supports 0% and 100% duty cycle — Shared or independent time bases • DMA transfer support available Table 1-3 shows the supported eMIOS modes.
Table 1-3. Supported eMIOS Channel Modes
Mode Channel type O(I)PWM / Counter / OPWFMB / O(I)PWM / OPWM / OPWMCB / ICOC ICOC ICOC x x x x x x x x x x x x x x x
Description
Name
OPWM / ICOC
Double action output compare General purpose input / output Input filter Input period measurement Input pulse width measurement
DAOC GPIO IPF IPM IPWM
— x x — —
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Chapter 1 Overview
Table 1-3. Supported eMIOS Channel Modes (continued)
Mode Channel type O(I)PWM / Counter / OPWFMB / O(I)PWM / OPWM / OPWMCB / ICOC ICOC ICOC x x x — — x x x x x x — x x x x x — — — x x — — — x — x — — — x x
Description
Name
OPWM / ICOC
Modulus counter Modulus counter buffered (up / down) Output pulse width and frequency modulation buffered Output pulse width modulation buffered
MC MCB OPWFMB OPWMB
— — — x — x — — — x x
Center aligned output PWM buffered with dead time OPWMCB Output pulse width modulation trigger Pulse edge accumulation Pulse edge counting Quadrature decode Single action input capture Single action output compare OPWMT PEA PEC QDEC SAIC SAOC
Table 1-4 shows the maximum eMIOS channel allocation.
Table 1-4. eMIOS Configuration
Channel type Counter / OPWM / ICOC1 O(I)PWM / OPWFMB / OPWMCB / O(I)PWM / ICOC3 OPWM / ICOC
1 4
Maximum number of channels 5
ICOC2
7 7 9
Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare. 2 Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare. 3 Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width measurement. 4 Each channel supports a range of modes including PWM generation, Input Capture, Output Compare.
1.4.9
Deserial Serial Peripheral Interface Module (DSPI)
The DSPI features the following: • 2 DSPI modules supported
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Chapter 1 Overview
• • • • • • • • • • • • • •
Full duplex, synchronous transfers Master or slave operation Programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Programmable transfer baud rate Programmable data frames from 4 to 16 bits 6 chip select lines for DSPI0 and 5 for DSPI1, depending on package and pin multiplexing, to enable 64 external devices to be selected using external muxing from a single DSPI Up to 8 transfer types, independently configurable for each DSPI using the clock and transfer attributes registers Chip select strobe available as alternate function on one of the chip select pins for deglitching FIFOs for buffering up to 4 transfers on the transmit and receive side General purpose I/O functionality on pins when not used for SPI Queueing operation possible through use of eDMA 32-bit serialization of data enabling virtual GPIO ports on two DSPI modules
1.4.10
Controller Area Network Module (FlexCAN)
The enhanced FlexCAN module features the following: • 1 FlexCAN modules supported • Compliant with CAN protocol specification, version 2.0B active • 32 mailboxes per FlexCAN module — Mailboxes configurable while module remains synchronized to CAN bus — Each mailbox configurable as transmit or receive • Transmit features — Supports configuration of multiple mailboxes to form message queues of scalable depth — Arbitration scheme according to message ID or message buffer number — Internal arbitration to guarantee no inner or outer priority inversion — Transmit abort procedure and notification • Receive features — 8 mailboxes configurable as a 6-entry receive FIFO — 8 programmable acceptance filters for receive FIFO • Programmable clock source — System clock — Direct oscillator clock to avoid PLL jitter • Listen only mode capabilities
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Chapter 1 Overview
1.4.11
System clocks and clock generation
The following list summarizes the system clock and clock generation on the MPC5602D: • System clock can be derived from the following sources — External crystal oscillator — FMPLL — 16 MHz fast internal RC oscillator • Programmable output clock divider of system clock (1, 2, 4) • Separate programmable peripheral bus clock divider ratio (1, 2, 4) applied to system clock • Frequency modulated phase-locked loop (FMPLL) — Input clock frequency from 4 MHz to 16 MHz — Clock source: external oscillator — Lock detect circuitry continuously monitors lock status — Loss of clock (LOC) detection for reference and feedback clocks — On-chip loop filter Improves electromagnetic interference performance Reduces number of external components required • On-chip fast external crystal oscillator supporting 4 MHz to 16 MHz • Dedicated 16 MHz fast internal RC oscillator — Used as default clock source out of reset — Provides clock for rapid startup from low power modes — Provides back-up clock in the event of FMPLL or external oscillator clock failure — Offers independent clock source for the watchdog timer — 5% accuracy over the operating temperature range — Trimming registers to support frequency adjustment with in-application calibration • Dedicated 128 kHz slow internal RC oscillator for low power mode operation and self wakeup — 10% accuracy — Trimming registers to support improve accuracy with in-application calibration
1.4.12
1.4.12.1
System timers
Introduction
The system timers include: • Peripheral Interrupt Timer (PIT) timers (including ADC trigger) • 1 Real-time Counter (RTC) timer The PIT is an array of timers that can be used to raise interrupts, trigger CTU channels and ADC conversions. The RTC supports wakeup from low power modes or real-time clock generation.
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Chapter 1 Overview
1.4.12.2
Periodic interrupt timer module (PIT)
The PIT features the following: • 4 general purpose interrupt timers • 1 interrupt timers for triggering ADC injected conversions (12-bit ADC) • Up to 2 interrupt timers for triggering DMA transfers • 1 interrupt timers for triggering CTU • 32-bit counter resolution • Clocked by system clock frequency
1.4.12.3
Real-time counter (RTC)
The RTC features the following: • Configurable resolution for different timeout periods — 1 sec resolution for > 1 hour period — 1 ms resolution for 2 second period • Selectable clock sources — 128 kHz slow internal RC oscillator — Divided 16 MHz fast internal RC oscillator • Supports continued operation through all resets except POR (power-on reset)
1.4.13
System watchdog timer
The watchdog on the MPC5602D features the following: • Activation by software or out of reset • 32-bit modulus counter • Clock source: robust 128 kHz slow internal RC oscillator (divisible by 1 to 32) • Supports normal or windowed mode • Configurable response on timeout: reset, interrupt, or interrupt followed by reset • Reset by writing a software key to memory mapped register • Support for protected access to watchdog control registers with optional soft and hard locks — Soft lock allows temporary locking of configuration — Once enabled, hard lock prevents any changes until after a reset • Supports halting during low power modes
1.4.14
On-chip voltage regulator (VREG)
The on-chip voltage regulator includes the following features: • Optional support for internal and external ballast resistor based on power consumption • Regulates 3.3 or 5 V ±10% input to generate all internal supplies for internal control
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Chapter 1 Overview
• • • •
Manages power gating Low power regulators support operation when in STOP and STANDBY modes to minimize power consumption Fast startup on-chip regulators for rapid exit from low power modes Low voltage reset supported on all internal supplies
1.4.15
Analog to Digital Converter Module (ADC)
The ADC features the following: • One 12-bit ADC module supporting synchronous conversions on channels • 0–VDD common mode conversion range • Conversions times of < 1 µs available • Up to 33 single ended inputs channels, expandable to 61 channels with external multiplexers • Internally multiplexed channels — up to 33 channels. 16 channels are high accuracy ones — Dedicated result register available for every internally muxed channel • Externally multiplexed channels — Internal control to support generation of external analog multiplexor selection — 4 internal channels optionally used to support externally multiplex inputs, providing transparent control for additional ADC channels — Each of the 4 channels supports up to 8 externally muxed inputs — Individual dedicated result register also available for externally muxed conversion channels — 3 independently configurable sample and conversion times for high occurrence channels, internally muxed channels and externally muxed channels • Support for one-shot, scan and injection conversion modes • Independently configurable sampling duration for each type of channel • Conversion triggering support — Internal conversion triggering from periodic interrupt timer (PIT) or timed I/O module (eMIOS) through cross triggering unit (CTU) — Internal conversion triggering from periodic interrupt timer (PIT) — 1 input pin configurable as external conversion trigger source • Up to 6 configurable analog comparator channels offering range comparison with triggered alarm — Greater than — Less than — Out of range • All unused analog pins available as general purpose input pins • Unused 12-bit ADC analog pins, with the exception of the 16 dedicated high accuracy channels, available as general purpose output pins • Power-down mode
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Chapter 1 Overview
• •
Supports DMA transfer of results based on end of conversion chain or each conversion Separate dedicated DMA request for injection mode
1.4.16
Enhanced Direct Memory Access Controller (eDMA)
The following summarizes the MPC5602D’s implementation of the eDMA controller: • 16 channels to support independent 8-, 16- or 32-bit single value or block transfers • Support of variable sized queues and circular queues • Source and destination address registers independently configured to post-increment or remain constant • Each transfer initiated by peripheral, CPU, periodic timer interrupt or eDMA channel request • Peripheral DMA request sources possible from SPIs, 12-bit ADC, eMIOS and GPIOs • Each eDMA channel able to optionally send interrupt request to CPU on completion of single value or block transfer • DMA transfers possible between system memories and all accessible memory mapped locations including peripheral and registers • Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with total of up to 64 potential request sources
1.4.17
Cross Trigger Unit (CTU)
The CTU enables the synchronization of ADC conversions with a timer event. Its key features are: • Single cycle delayed trigger output; trigger output is a combination of 29 (generic value) input flags/events connected to different timers in the system • Triggers ADC conversions from any eMIOS channel • Triggers ADC conversions from one dedicated PIT • Maskable interrupt generation whenever a trigger output is generated • 1 event configuration register dedicated to each timer event allows to define the corresponding ADC channel • Acknowledgment signal to eMIOS/PIT for clearing the flag • Synchronization with ADC to avoid collision
1.4.18
Serial Communication Interface Module (LINFlex)
The LINFlex on the MPC5602D features the following: • 3 LINFlex modules supported • Supports LIN master mode, LIN slave mode and UART mode • 1 module supporting LIN master and slave mode; 2 modules supporting LIN master mode • LIN state machine compliant to LIN 1.3, 2.0 and 2.1 specifications • Handles LIN frame transmission and reception without CPU intervention
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 43
Chapter 1 Overview
•
•
•
LIN features — Autonomous LIN frame handling — Message buffer to store identified and up to 8 data bytes — Supports message length of up to 64 bytes — Detection and flagging of LIN errors – Sync field; delimiter; ID parity; bit, framing; checksum and timeout errors — Classic or extended checksum calculation — Configurable break duration of up to 36-bit times — Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) — Diagnostic features – Loop back; Self Test; LIN bus stuck dominant detection — Interrupt driven operation with 16 interrupt sources LIN slave mode features — Autonomous LIN header handling — Autonomous LIN response handling — 16 ID filters for discarding irrelevant LIN responses UART mode — Full-duplex operation — Standard non return-to-zero (NRZ) mark/space format — Data buffers with 4-bytes receive, 4-bytes transmit — Configurable word length (8-bit or 9-bit words) — Error detection and flagging – Parity, noise and framing errors — Interrupt driven operation with 4 interrupt sources — Separate transmitter and receiver CPU interrupt sources — 16-bit programmable baud rate modulus counter and 16-bit fractional — 2 receiver wakeup methods
MPC5602D devices include two functionally-different LINFlex controller types. These are distinguished in the documentation by the abbreviations "LINFlex" and "LINFlexD". The MPC5602D devices combine these two types to provide up to 3 modules supporting the LINFlex protocol. Table 1-5 shows the module (instance) numbers and the corresponding functional controller type.
Table 1-5. LINFlex numbering and naming
Module numbers 0 1 and 2 LINFlexD LINFlex Module version
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Chapter 1 Overview
1.4.19
JTAG controller (JTAGC)
JTAG features the following: • JTAG low pin count interface (IEEE 1149.1) test access port (TAP) interface • Backward compatible to standard JTAG IEEE 1149.1-2001 test access port (TAP) interface • Supports boundary scan testing • All JTAG pins reusable in application as standard IOs
1.5
Developer Support
The MPC5602D MCU tools and third-party developers are similar to those used for the Freescale MPC5500 product family, offering a widespread, established network of tool and software vendors. It also features a high-performance Nexus debug interface. The following development support will be available: • Automotive evaluation boards (EVB) featuring CAN, LIN interfaces, and more • Compilers • Debuggers • JTAG and Nexus interfaces The following software support will be available: • OSEK solutions will be available from multiple third parties • CAN and LIN drivers • AutoSAR package
1.6
Memory Map
Table 1-6 shows the memory map for the MPC5602D. All addresses on the device, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block.
Table 1-6. MPC5602D Memory Map
Start Address 0x00000000 0x00008000 0x0000C000 0x00010000 0x00018000 0x00020000 0x00040000 0x00200000 End Address 0x00007FFF 0x0000BFFF 0x0000FFFF 0x00017FFF 0x0001FFFF 0x0003FFFF 0x001FFFFF 0x00203FFF Size (KB) 32 16 16 32 32 128 512 16 Region Name Code Flash Array 0 Code Flash Array 0 Code Flash Array 0 Code Flash Array 0 Code Flash Array 0 Code Flash Array 0 Reserved Flash Shadow Array
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Chapter 1 Overview
Table 1-6. MPC5602D Memory Map (continued)
Start Address 0x00204000 0x00400000 0x00404000 0x00800000 0x00804000 0x00808000 0x0080C000 0x00810000 0x00C02000 0x00C04000 0x01000000 0x20000000 0x40000000 0x40004000 0x80000000 End Address 0x003FFFFF 0x00403FFF 0x007FFFFF 0x00803FFF 0x00807FFF 0x0080BFFF 0x0080FFFF 0x00BFFFFF 0x00C03FFF 0x00FFFFFF 0x1FFFFFFF 0x3FFFFFFF 0x40003FFF 0x7FFFFFFF 0xBFFFFFFF Size (KB) 2032 16 4080 16 16 16 16 4032 8 4080 507904 524288 16 1048560 1048576 Reserved Code Flash Array 0 Test Sector Reserved Data Flash Array 0 Data Flash Array 0 Data Flash Array 0 Data Flash Array 0 Reserved Test Sector Data Flash Array 0 Reserved Flash Emulation Mapping Reserved for External Bus Interface SRAM Reserved Reserved Region Name
Off-Platform Peripherals AIPS(1) 0xC0000000 0xC3F80000 0xC3F84000 0xC3F88000 0xC3F8C00 0xC3F90000 0xC3F94000 0xC3F98000 0xC3FA0000 0xC3FA4000 0xC3FD8000 0xC3FDC000 0xC3FE0000 0xC3FE4000 0xC3FE8000 0xC3FEC000 0xC3F7FFFF 0xC3F83FFF 0xC3F87FFF 0xC3F8BFFF 0xC3F8FFFF 0xC3F93FFF 0xC3F97FFF 0xC3F9FFFF 0xC3FA3FFF 0xC3FD7FFF 0xC3FDBFFF 0xC3FDFFFF 0xC3FE3FFF 0xC3FE7FFF 0xC3FEBFFF 0xC3FEFFFF 65024 16 16 16 16 16 16 32 16 208 16 16 16 16 16 16 Reserved Reserved Frequency Modulated PLL Reserved Code Flash 0 Configuration Data Flash 0 Configuration System Integration Unit Lite (SIUL) WakeUp Unit Reserved eMIOS 0 Reserved System Status and Configuration Module (SSCM) Mode Entry Module (MC_ME) Clock Generation Module (MC_CGM) Reset Generation Module (MC_RGM) Power Control Unit (MC_PCU) Real Time Counter (RTC/API)
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Chapter 1 Overview
Table 1-6. MPC5602D Memory Map (continued)
Start Address 0xC3FF0000 0xC3FF4000 0xC4000000 End Address 0xC3FF3FFF 0xC3FFFFFF 0xDFFFFFFF Size (KB) 16 48 458752 Region Name Periodic Interrupt Timer (PIT/RTI) Reserved Reserved
Off-Platform Peripherals AIPS(0) 0xE0000000 0xFFE00000 0xFFE04000 0xFFE08000 0xFFE40000 0xFFE44000 0xFFE48000 0xFFE4C000 0xFFE64000 0xFFE68000 0xFFE70000 0xFFE74000 0xFFE80000 0xFFF00000 0xFFF04000 0xFFF08000 0xFFF10000 0xFFF14000 0xFFF38000 0xFFF3C000 0xFFF40000 0xFFF44000 0xFFF48000 0xFFF4C000 0xFFF90000 0xFFF94000 0xFFF98000 0xFFFC0000 0xFFDFFFFF 0xFFE03FFF 0xFFE07FFF 0xFFE3FFFF 0xFFE43FFF 0xFFE47FFF 0xFFE4BFFF 0xFFE63FFF 0xFFE67FFF 0xFFE6FFFF 0xFFE73FFF 0xFFE7FFFF 0xFFEFFFFF 0xFFF03FFF 0xFFF07FFF 0xFFF0FFFF 0xFFF13FFF 0xFFF37FFF 0xFFF3BFFF 0xFFF3FFFF 0xFFF43FFF 0xFFF47FFF 0xFFF4BFFF 0xFFF8FFFF 0xFFF93FFF 0xFFF97FFF 0xFFFBFFFF 0xFFFC3FFF 522240 16 16 224 16 16 16 96 16 32 16 48 512 16 16 32 16 144 16 16 16 16 16 272 16 16 160 16 Reserved Reserved ADC 1 Reserved LINFlex 0 LINFlex 1 LINFlex 2 Reserved CTU-LITE Reserved Reserved Reserved Mirrored Range 0x3F80000-0xC3FFFFFF Reserved AIPS0 Reserved AXBS Reserved Reserved Reserved SWT STM ECSM DMA INTC Reserved DSPI 0 DSPI 1 Reserved FlexCan 0 (CAN0)
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Chapter 1 Overview
Table 1-6. MPC5602D Memory Map (continued)
Start Address 0xFFFC4000 0xFFFC8000 0xFFFDC000 0xFFFE0000 0xFFFFC000 End Address 0xFFFC7FFF 0xFFFDBFFF 0xFFFDFFFF 0xFFFFBFFF 0xFFFFFFFF Size (KB) 16 80 16 144 16 Reserved Reserved DMA Channel Multiplexer Reserved BAM Region Name
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Chapter 2 Signal Description
Chapter 2 Signal Description
2.1 Package Pinouts
Figure 2-2 and Figure 2-3 show the location of the signals on the packages that this device is available in. For more information on pin multiplexing on this device, refer to Table 2-1 through Table 2-3.
Figure 2-2. LQFP64 pin configuration (top view)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3]
PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 LQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 49
PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Chapter 2 Signal Description
Figure 2-3. LQFP100 pin configuration (top view)
PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12]
100 LQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC
2.2
Pad configuration during reset phases
All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are forced to tristate with the following exceptions: • PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash. • PA[8] (ABS[0]) is pull-up. • RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
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PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Chapter 2 Signal Description
• • •
JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate. Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available). Main oscillator pads (EXTAL, XTAL) are tristate.
2.3
Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
Table 2-1. Voltage supply pin descriptions
Pin No. Port pin Function 64 LQFP VDD_HV VSS_HV VDD_LV Digital supply voltage Digital ground 1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VSS_LV pin.1 1.2V decoupling pins. Decoupling capacitor must be connected between these pins and the nearest VDD_LV pin.1 Internal regulator supply voltage 7, 28, 34, 56 6, 8, 26, 33, 55 11, 23, 57 100 LQFP 15, 37, 52, 70, 84 14, 16, 35, 51, 69, 83 19, 32, 85
VSS_LV
10, 24, 58
18, 33, 86
VDD_BV
1
12
20
A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details).
2.4
Pad types
In the device the following types of pads are available for system pins and functional port pins: S = Slow1 M = Medium1 2 F = Fast1 2 I = Input only with analog feature1 J = Input/Output with analog feature X = Oscillator
2.5
System pins
The system pins are listed in Table 2-2.
1. See the I/O pad electrical characteristics in the device datasheet for details. 2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC in Section 15.5.3.8, “Pad Configuration Registers (PCR0–PCR122)). MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 51
Chapter 2 Signal Description
Table 2-2. System pin descriptions
I/O Pad directio typ n e I/O M Pin No. RESET config. 64 LQFP 9 100 LQFP 17
Port pin
Function
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter.
Input, weak pull-up only after PHASE2 Tristate
EXTAL
Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. Analog input for the clock generator when the oscillator is in bypass mode. 1 Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator is used in bypass mode. 1
I/O
X
27
36
XTAL
I
X
Tristate
25
34
1
Refer to the relevant section of the datasheet
2.6
Functional ports A, B, C, D, E, H
Table 2-3. Functional port pin descriptions
Port pin PCR register Alternate function1 RESE Pad I/O Periphera T direction typ l config 2 e . SIUL eMIOS0 CGL eMIOS0 WKPU SIUL eMIOS0 — — WKPU WKPU SIUL eMIOS0 — — WKPU I/O I/O O I/O I I/O I/O — — I I I/O I/O — — I M Tristat e Pin No. 64 LQFP 5 100 LQFP 12
The functional port pins are listed in Table 2-3.
Function
PA[0]
PCR[0]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 —
GPIO[0] E0UC[0] CLKOUT E0UC[13] WKUP[19]3 GPIO[1] E0UC[1] — — NMI4 WKUP[2]3 GPIO[2] E0UC[2] — — WKUP[3]3
PA[1]
PCR[1]
S
Tristat e
4
7
PA[2]
PCR[2]
S
Tristat e
3
5
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Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL eMIOS0 — — SIUL ADC SIUL eMIOS0 — — WKPU SIUL eMIOS0 — — SIUL eMIOS0 — — SIUL SIUL eMIOS0 — — SIUL ADC SIUL eMIOS0 eMIOS0 — SIUL BAM SIUL eMIOS 0 — — BAM SIUL eMIOS 0 — LINFlex 1 ADC I/O I/O — — I I I/O I/O — — I I/O I/O — — I/O I/O — — I I/O I/O — — I I I/O I/O — — I I I/O I/O — — I I/O I/O — O I S Tristat e Pin No. 64 LQFP 43 100 LQFP 68
Function
PA[3]
PCR[3]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — N/A5 AF0 AF1 AF2 AF3 N/A5 AF0 AF1 AF2 AF3 —
GPIO[3] E0UC[3] — — EIRQ[0] ADC1_S[0] GPIO[4] E0UC[4] — — WKUP[9]3 GPIO[5] E0UC[5] — — GPIO[6] E0UC[6] — — EIRQ[1] GPIO[7] E0UC[7] — — EIRQ[2] ADC1_S[1] GPIO[8] E0UC[8] E0UC[14] — EIRQ[3] ABS[0] GPIO[9] E0UC[9] — — FAB GPIO[10] E0UC[10] — LIN1TX ADC1_S[2]
PA[4]
PCR[4]
S
Tristat e
20
29
PA[5]
PCR[5]
M
Tristat e
51
79
PA[6]
PCR[6]
S
Tristat e
52
80
PA[7]
PCR[7]
S
Tristat e
44
71
PA[8]
PCR[8]
S
Input, weak pull-up
45
72
PA[9]
PCR[9]
S
Pulldown
46
73
PA[10]
PCR[10]
S
Tristat e
47
74
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 53
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL eMIOS0 — — SIUL ADC LINFlex 2 SIUL — — — SIUL DSPI0 SIUL DSPI 0 — — SIUL DSPI 0 DSPI 0 eMIOS0 SIUL SIUL DSPI 0 DSPI 0 eMIOS0 WKPU SIUL FlexCAN 0 — — SIUL — — — WKPU FlexCAN 0 SIUL LINFlex 0 — — I/O I/O — — I I I I/O — — — I I I/O O — — I/O I/O I/O I/O I I/O I/O I/O I/O I I/O O — — I/O — — — I I I/O O — — S Tristat e Pin No. 64 LQFP 48 100 LQFP 75
Function
PA[11]
PCR[11]
AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3
GPIO[11] E0UC[11] — — EIRQ[16] ADC1_S[3] LIN2RX GPIO[12] — — — EIRQ[17] SIN_0 GPIO[13] SOUT_0 — — GPIO[14] SCK_0 CS0_0 E0UC[0] EIRQ[4] GPIO[15] CS0_0 SCK_0 E0UC[1] WKUP[10]3 GPIO[16] CAN0TX — — GPIO[17] — — — WKUP[4]3 CAN0RX GPIO[18] LIN0TX — —
PA[12]
PCR[12]
S
Tristat e
22
31
PA[13]
PCR[13]
M
Tristat e
21
30
PA[14]
PCR[14]
M
Tristat e
19
28
PA[15]
PCR[15]
M
Tristat e
18
27
PB[0]
PCR[16]
M
Tristat e
14
23
PB[1]
PCR[17]
S
Tristat e
15
24
PB[2]
PCR[18]
M
Tristat e
64
100
MPC5602D Microcontroller Reference Manual, Rev. 3.1 54 Preliminary Freescale Semiconductor
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL — — — WKPU LINFlex 0 SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC WKPU SIUL — — — ADC WKPU SIUL — — — ADC WKPU I/O — — — I I I — — — I I — — — I I — — — I I — — — I I — — — I I I — — — I I I/O — — — I I S Tristat e Pin No. 64 LQFP 1 100 LQFP 1
Function
PB[3]
PCR[19]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — —
GPIO[19] — — — WKUP[11]3 LIN0RX GPIO[20] — — — ADC1_P[0] GPIO[21] — — — ADC1_P[1] GPIO[22] — — — ADC1_P[2] GPIO[23] — — — ADC1_P[3] GPIO[24] — — — ADC1_S[4] WKUP[25]3 GPIO[25] — — — ADC1_S[5] WKUP[26]3 GPIO[26] — — — ADC1_S[6] WKUP[8]3
PB[4]
PCR[20]
I
Tristat e
32
50
PB[5]
PCR[21]
I
Tristat e
35
53
PB[6]
PCR[22]
I
Tristat e
36
54
PB[7]
PCR[23]
I
Tristat e
37
55
PB[8]
PCR[24]
I
Tristat e
30
39
PB[9]
PCR[25]
I
Tristat e
29
38
PB[10]
PCR[26]
J
Tristat e
31
40
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 55
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL eMIOS 0 — DSPI 0 ADC SIUL eMIOS — DSPI 0 ADC SIUL eMIOS 0 — DSPI 0 ADC SIUL eMIOS0 — DSPI 0 ADC SIUL eMIOS 0 — DSPI 0 ADC SIUL — JTAGC — SIUL — JTAGC — SIUL DSPI 1 — — SIUL SIUL DSPI 1 ADC — SIUL I/O I/O — I/O I I/O I/O — O I I/O I/O — O I I/O I/O — O I I/O I/O — O I I/O — I — I/O — O — I/O I/O — — I I/O I/O O — I J Tristat e Pin No. 64 LQFP 38 100 LQFP 59
Function
PB[11]
PCR[27]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[27] E0UC[3] — CS0_0 ADC1_S[12] GPIO[28] E0UC[4] — CS1_0 ADC1_X[0] GPIO[29] E0UC[5] — CS2_0 ADC1_X[1] GPIO[30] E0UC[6] — CS3_0 ADC1_X[2] GPIO[31] E0UC[7] — CS4_0 ADC1_X[3] GPIO[32] — TDI — GPIO[33] — TDO — GPIO[34] SCK_1 — — EIRQ[5] GPIO[35] CS0_1 MA[0] — EIRQ[6]
PB[12]
PCR[28]
J
Tristat e
39
61
PB[13]
PCR[29]
J
Tristat e
40
63
PB[14]
PCR[30]
J
Tristat e
41
65
PB[15]
PCR[31]
J
Tristat e
42
67
PC[0]6
PCR[32]
M
Input, weak pull-up Tristat e
59
87
PC[1]6
PCR[33]
F
54
82
PC[2]
PCR[34]
M
Tristat e
50
78
PC[3]
PCR[35]
S
Tristat e
49
77
MPC5602D Microcontroller Reference Manual, Rev. 3.1 56 Preliminary Freescale Semiconductor
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL — — — DSPI 1 SIUL SIUL DSPI1 — — SIUL SIUL LINFlex 1 — — SIUL — — — LINFlex 1 WKPU SIUL LINFlex 2 — — SIUL — — — LINFlex 2 WKPU SIUL — — ADC SIUL — — ADC WKPU SIUL eMIOS 0 — — SIUL I/O — — — I I I/O O — — I I/O O — — I/O — — — I I I/O O — — I/O — — — I I I/O — — O I/O — — O I I/O I/O — — I M Tristat e Pin No. 64 LQFP 62 100 LQFP 92
Function
PC[4]
PCR[36]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[36] — — — SIN_1 EIRQ[18] GPIO[37] SOUT_1 — — EIRQ[7] GPIO[38] LIN1TX — — GPIO[39] — — — LIN1RX WKUP[12]3 GPIO[40] LIN2TX — — GPIO[41] — — — LIN2RX WKUP[13]3 GPIO[42] — — MA[1] GPIO[43] — — MA[2] WKUP[5]3 GPIO[44] E0UC[12] — — EIRQ[19]
PC[5]
PCR[37]
M
Tristat e
61
91
PC[6]
PCR[38]
S
Tristat e
16
25
PC[7]
PCR[39]
S
Tristat e
17
26
PC[8]
PCR[40]
S
Tristat e
63
99
PC[9]
PCR[41]
S
Tristat e
2
2
PC[10]
PCR[42]
M
Tristat e
13
22
PC[11]
PCR[43]
S
Tristat e
—
21
PC[12]
PCR[44]
M
Tristat e
—
97
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 57
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL eMIOS 0 — — SIUL eMIOS 0 — — SIUL SIUL eMIOS 0 — — SIUL SIUL — — — WKPU ADC SIUL — — — WKPU ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC I/O I/O — — I/O I/O — — I I/O I/O — — I I — — — I I I — — — I I I — — — I I — — — I I — — — I S Tristat e Pin No. 64 LQFP — 100 LQFP 98
Function
PC[13]
PCR[45]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[45] E0UC[13] — — GPIO[46] E0UC[14] — — EIRQ[8] GPIO[47] E0UC[15] — — EIRQ[20] GPIO[48] — — — WKUP[27]3 ADC1_P[4] GPIO[49] — — — WKUP[28]3 ADC1_P[5] GPIO[50] — — — ADC1_P[6] GPIO[51] — — — ADC1_P[7] GPIO[52] — — — ADC1_P[8]
PC[14]
PCR[46]
S
Tristat e
—
3
PC[15]
PCR[47]
M
Tristat e
—
4
PD[0]
PCR[48]
I
Tristat e
—
41
PD[1]
PCR[49]
I
Tristat e
—
42
PD[2]
PCR[50]
I
Tristat e
—
43
PD[3]
PCR[51]
I
Tristat e
—
44
PD[4]
PCR[52]
I
Tristat e
—
45
MPC5602D Microcontroller Reference Manual, Rev. 3.1 58 Preliminary Freescale Semiconductor
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL DSPI 0 eMIOS 0 — ADC SIUL DSPI 1 eMIOS 0 — ADC I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I I/O O I/O — I I/O I/O I/O — I I Tristat e Pin No. 64 LQFP — 100 LQFP 46
Function
PD[5]
PCR[53]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[53] — — — ADC1_P[9] GPIO[54] — — — ADC1_P[10] GPIO[55] — — — ADC1_P[11] GPIO[56] — — — ADC1_P[12] GPIO[57] — — — ADC1_P[13] GPIO[58] — — — ADC1_P[14] GPIO[59] — — — ADC1_P[15] GPIO[60] CS5_0 E0UC[24] — ADC1_S[8] GPIO[61] CS0_1 E0UC[25] — ADC1_S[9]
PD[6]
PCR[54]
I
Tristat e
—
47
PD[7]
PCR[55]
I
Tristat e
—
48
PD[8]
PCR[56]
I
Tristat e
—
49
PD[9]
PCR[57]
I
Tristat e
—
56
PD[10]
PCR[58]
I
Tristat e
—
57
PD[11]
PCR[59]
I
Tristat e
—
58
PD[12]
PCR[60]
J
Tristat e
—
60
PD[13]
PCR[61]
J
Tristat e
—
62
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 59
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL DSPI 1 eMIOS 0 — ADC SIUL DSPI 1 eMIOS 0 — ADC SIUL eMIOS 0 — — WKPU SIUL eMIOS 0 — — SIUL eMIOS0 — — SIUL DSPI 1 SIUL eMIOS0 DSPI 1 — SIUL eMIOS0 DSPI 1 — SIUL SIUL eMIOS 0 DSPI 1 ADC SIUL eMIOS 0 DSPI 0 ADC SIUL I/O O I/O — I I/O O I/O — I I/O I/O — — I I/O I/O — — I/O I/O — — I I I/O I/O O — I/O I/O I/O — I I/O I/O I/O O I/O I/O O O I J Tristat e Pin No. 64 LQFP — 100 LQFP 64
Function
PD[14]
PCR[62]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 —
GPIO[62] CS1_1 E0UC[26] — ADC1_S[10] GPIO[63] CS2_1 E0UC[27] — ADC1_S[11] GPIO[64] E0UC[16] — — WKUP[6]3 GPIO[65] E0UC[17] — — GPIO[66] E0UC[18] — — EIRQ[21] SIN_1 GPIO[67] E0UC[19] SOUT_1 — GPIO[68] E0UC[20] SCK_1 — EIRQ[9] GPIO[69] E0UC[21] CS0_1 MA[2] GPIO[70] E0UC[22] CS3_0 MA[1] EIRQ[21]
PD[15]
PCR[63]
J
Tristat e
—
66
PE[0]
PCR[64]
S
Tristat e
—
6
PE[1]
PCR[65]
M
Tristat e
—
8
PE[2]
PCR[66]
M
Tristat e
—
89
PE[3]
PCR[67]
M
Tristat e
—
90
PE[4]
PCR[68]
M
Tristat e
—
93
PE[5]
PCR[69]
M
Tristat e
—
94
PE[6]
PCR[70]
M
Tristat e
—
95
MPC5602D Microcontroller Reference Manual, Rev. 3.1 60 Preliminary Freescale Semiconductor
Chapter 2 Signal Description
Table 2-3. Functional port pin descriptions (continued)
Port pin PCR register Alternate function1 RESE Pad I/O T Periphera direction typ l config 2 e . SIUL eMIOS 0 DSPI 0 ADC SIUL SIUL — I/O — SIUL — eMIOS 0 — WKPU SIUL — DSPI 1 — SIUL SIUL eMIOS 0 DSPI 1 — WKPU SIUL — — — ADC SIUL SIUL — JTAGC — SIUL — JTAGC — I/O I/O O O I I/O — eMIOS0 — I/O — I/O — I I/O — O — I I/O I/O O — I I/O — — — I I I/O — I — I/O — I — M Tristat e Pin No. 64 LQFP — 100 LQFP 96
Function
PE[7]
PCR[71]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3
GPIO[71] E0UC[23] CS2_0 MA[0] EIRQ[21] GPIO[72] — E0UC[22] — GPIO[73] — E0UC[23] — WKUP[7]3 GPIO[74] — CS3_1 — EIRQ[10] GPIO[75] E0UC[24] CS4_1 — WKUP[14]3 GPIO[76] — — — ADC1_S[7] EIRQ[11] GPIO[121] — TCK — GPIO[122] — TMS —
PE[8]
PCR[72]
M
Tristat e
—
9
PE[9]
PCR[73]
S
Tristat e
—
10
PE[10]
PCR[74]
S
Tristat e
—
11
PE[11]
PCR[75]
S
Tristat e
—
13
PE[12]
PCR[76]
S
Tristat e
—
76
PH[9]6 PCR[121]
S
Input, weak pull-up Input, weak pull-up
60
88
PH[10] PCR[122]
6
S
53
81
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 -> AF0; PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11 -> AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. 2 Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 61
Chapter 2 Signal Description
3 4
All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. 5 “Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details. 6 Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 62 Preliminary Freescale Semiconductor
Chapter 3 Reset Generation Module (MC_RGM)
Chapter 3 Reset Generation Module (MC_RGM)
3.1
3.1.1
Introduction
Overview
The reset generation module (MC_RGM) centralizes the different reset sources and manages the reset sequence of the device. It provides a register interface and the reset sequencer. Various registers are available to monitor and control the device reset sequence. The reset sequencer is a state machine which controls the different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence and controls the reset signals generated in the system. Figure 3-1 depicts the MC_RGM block diagram.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 63
Chapter 3 Reset Generation Module (MC_RGM)
power-on 1.2V low-voltage detected (power domain #0) 1.2V low-voltage detected (power domain #1) software watchdog timer 2.7V low-voltage detected 2.7V low-voltage detected (VREG) Destructive Reset Filter
MC_RGM
MC_ME Registers Platform Interface MC_CGM
peripherals
RESET JTAG initiated reset core reset software reset checkstop reset FMPLL fail FXOSC frequency lower than reference CMU clock frequency higher/lower than reference 4.5V low-voltage detected code or data flash fatal error
Reset State Machine core Functional Reset Filter Boot Mode Capture
PA[9:8]
SSCM
Figure 3-1. MC_RGM Block Diagram
3.1.2
Features
The MC_RGM contains the functionality for the following features: • ‘destructive’ resets management • ‘functional’ resets management • signalling of reset events after each reset sequence (reset status flags) • conversion of reset events to SAFE mode or interrupt request events • short reset sequence configuration
MPC5602D Microcontroller Reference Manual, Rev. 3.1 64 Preliminary Freescale Semiconductor
Chapter 3 Reset Generation Module (MC_RGM)
• • •
bidirectional reset behavior configuration selection of alternate boot via the backup RAM on STANDBY0 mode exit boot mode capture on RESET deassertion
3.1.3
Reset Sources
The different reset sources are organized into two families: ‘destructive’ and ‘functional’. • A ‘destructive’ reset source is associated with an event related to a critical - usually hardware error or dysfunction. When a ‘destructive’ reset event occurs, the full reset sequence is applied to the device starting from PHASE0. This resets the full device ensuring a safe start-up state for both digital and analog modules. ‘Destructive’ resets are – power-on reset – 1.2V low-voltage detected (power domain #0) – 1.2V low-voltage detected (power domain #1) – software watchdog timer – 2.7V low-voltage detected – 2.7V low-voltage detected (VREG) • A ‘functional’ reset source is associated with an event related to a less-critical - usually non-hardware - error or dysfunction. When a ‘functional’ reset event occurs, a partial reset sequence is applied to the device starting from PHASE1. In this case, most digital modules are reset normally, while analog modules or specific digital modules’ (e.g., debug modules, flash modules) state is preserved. ‘Functional’ resets are – external reset – JTAG initiated reset – core reset – software reset – checkstop reset – FMPLL fail – FXOSC frequency lower than reference – CMU clock frequency higher/lower than reference – 4.5V low-voltage detected – code or data flash fatal error When a reset is triggered, the MC_RGM state machine is activated and proceeds through the different phases (i.e., PHASEn states). Each phase is associated with a particular device reset being provided to the system. A phase is completed when all corresponding phase completion gates from either the system or internal to the MC_RGM are acknowledged. The device reset associated with the phase is then released, and the state machine proceeds to the next phase up to entering the IDLE phase. During this entire process, the MC_ME state machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE phase is reached, does the MC_ME enter the DRUN mode.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 65
Chapter 3 Reset Generation Module (MC_RGM)
Alternatively, it is possible for software to configure some reset source events to be converted from a reset to either a SAFE mode request issued to the MC_ME or to an interrupt issued to the core (see Section 3.3.1.3, “Functional Event Reset Disable Register (RGM_FERD) and Section 3.3.1.5, “Functional Event Alternate Request Register (RGM_FEAR) for ‘functional’ resets).
3.2
External Signal Description
The MC_RGM interfaces to the bidirectional reset pin RESET and the boot mode pins PA[9:8].
3.3
Memory Map and Register Definition
Table 3-1. MC_RGM Register Description
Access Address Name Description Size User 0xC3FE RGM_FES _4000 0xC3FE RGM_DES _4002 0xC3FE RGM_FERD _4004 0xC3FE RGM_DERD _4006 0xC3FE RGM_FESS _4018 Functional Event Status Destructive Event Status Functional Event Reset Disable Destructive Event Reset Disable Functional Event Short Sequence half-word half-word half-word half-word half-word half-word half-word read read read read read read read Supervisor Test on page 69 on page 70 on page 71 on page 73 on page 74 on page 76 on page 76 read/write1 read/write1 read/write1 read/write1 read/write2 read/write2 read read/write read/write read/write read read/write read/write read/write
Location
0xC3FE RGM_STDBY STANDBY0 Reset _401A Sequence 0xC3FE RGM_FBRE _401C
1 2
Functional Bidirectional Reset Enable
individual bits cleared on writing ‘1’ write once: ‘0’ = enable, ‘1’ = disable.
NOTE Any access to unused registers as well as write accesses to read-only registers will: • • not change register content cause a transfer error
MPC5602D Microcontroller Reference Manual, Rev. 3.1 66 Preliminary Freescale Semiconductor
Chapter 3 Reset Generation Module (MC_RGM)
Table 3-2. MC_RGM Memory Map
Address Name
0 16 1 17 2 18 3 19 27 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
F_CMU_OLR
F_FMPLL
F_FLASH
F_LVD45
F_CORE F_LVD12_PD1 D_CORE D_LVD12_PD1 AR_CORE 0
F_SOFT
R
W w1c
w1c w1c w1c w1c w1c w1c w1c w1c w1c F_LVD27_VREG F_LVD12_PD0 AR_JTAG 0 67 Preliminary D_LVD12_PD0 D_JTAG
F_LVD27
R
W w1c D_CMU_OLR D_FLASH D_LVD45 D_EXR 0xC3FE RGM_ _4004 FERD / RGM_ R DERD W D_CMU_FHL
w1c w1c w1c w1c w1c D_CHKSTOP D_FMPLL D_SOFT
D_LVD27_VREG
D_LVD27
R
0
W 0xC3FE _4008 … 0xC3FE _400C 0xC3FE RGM_ _4010 FEAR R
reserved
AR_CMU_OLR
AR_CMU_FHL
W R W 0xC3FE _4014 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor
AR_FMPLL
AR_LVD45
D_SWT
F_SWT
F_POR
F_JTAG
0xC3FE RGM_ _4000 FES / RGM_ DES
F_CHKSTOP
F_CMU_FHL
F_EXR
Chapter 3 Reset Generation Module (MC_RGM)
Table 3-2. MC_RGM Memory Map (continued)
Address Name
0 16 1 17 2 18 3 19 27 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
SS_CMU_OLR
0xC3FE RGM_ _4018 FESS / RGM_ STDB Y
SS_CHKSTOP
SS_CMU_FHL
SS_FMPLL
SS_FLASH
SS_LVD45
SS_CORE 0 BE_CORE 0
SS_SOFT
R
W BOOT_FROM_BKP_RAM
R
0
0
0
0
0
0
0
0
0
0
0
0
0
W BE_CMU_OLR BE_FMPLL BE_FLASH BE_LVD45 BE_SOFT BE_JTAG 0 BE_EXR 0xC3FE RGM_ _401C FBRE R BE_CHKSTOP BE_CMU_FHL
W R W 0xC3FE _4020 … 0xC3FE _7FFC 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reserved
3.3.1
Register Descriptions
Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the RGM_DES[8:15] register bits may be accessed as a word at address 0xC3FE_4000, as a half-word at address 0xC3FE_4002, or as a byte at address 0xC3FE_4004.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 68 Preliminary Freescale Semiconductor
SS_JTAG 0
SS_EXR
Chapter 3 Reset Generation Module (MC_RGM)
3.3.1.1
Functional Event Status Register (RGM_FES)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FE_4000
0 1 2
F_CMU_OLR
F_FMPLL
F_FLASH
F_LVD45
F_CORE w1c 0
F_SOFT
W w1c POR 0 0 0 0 0 0 0
w1c 0
w1c 0
w1c 0
w1c 0
w1c 0
w1c 0
w1c 0
w1c 0
Figure 3-2. Functional Event Status Register (RGM_FES)
This register contains the status of the last asserted functional reset sources. It can be accessed in read/write on either supervisor mode or test mode. Register bits are cleared on write ‘1’.
Table 3-3. Functional Event Status Register (RGM_FES) Field Descriptions
Field F_EXR Description Flag for External Reset 0 No external reset event has occurred since either the last clear or the last destructive reset assertion 1 An external reset event has occurred Flag for code or data flash fatal error 0 No code or data flash fatal error event has occurred since either the last clear or the last destructive reset assertion 1 A code or data flash fatal error event has occurred Flag for 4.5V low-voltage detected 0 No 4.5V low-voltage detected event has occurred since either the last clear or the last destructive reset assertion 1 A 4.5V low-voltage detected event has occurred
F_FLASH
F_LVD45
F_CMU_FHL Flag for CMU clock frequency higher/lower than reference 0 No CMU clock frequency higher/lower than reference event has occurred since either the last clear or the last destructive reset assertion 1 A CMU clock frequency higher/lower than reference event has occurred F_CMU_OL Flag for FXOSC frequency lower than reference R 0 No FXOSC frequency lower than reference event has occurred since either the last clear or the last destructive reset assertion 1 A FXOSC frequency lower than reference event has occurred F_FMPLL Flag for FMPLL fail 0 No FMPLL fail event has occurred since either the last clear or the last destructive reset assertion 1 A FMPLL fail event has occurred
F_CHKSTOP Flag for checkstop reset 0 No checkstop reset event has occurred since either the last clear or the last destructive reset assertion 1 A checkstop reset event has occurred
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 69
F_JTAG
R F_EXR
F_CHKSTOP
F_CMU_FHL
Chapter 3 Reset Generation Module (MC_RGM)
Table 3-3. Functional Event Status Register (RGM_FES) Field Descriptions (continued)
Field F_SOFT Description Flag for software reset 0 No software reset event has occurred since either the last clear or the last destructive reset assertion 1 A software reset event has occurred Flag for core reset 0 No core reset event has occurred since either the last clear or the last destructive reset assertion 1 A core reset event has occurred Flag for JTAG initiated reset 0 No JTAG initiated reset event has occurred since either the last clear or the last destructive reset assertion 1 A JTAG initiated reset event has occurred
F_CORE
F_JTAG
3.3.1.2
Destructive Event Status Register (RGM_DES)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FE_4002
0 1 2
F_LVD12_PD1 w1c 0
W w1c POR 1 0 0 0 0 0 0 0 0 0 0
w1c 0
w1c 0
w1c 0
w1c 0
Figure 3-3. Destructive Event Status Register (RGM_DES)
This register contains the status of the last asserted destructive reset sources. It can be accessed in read/write on either supervisor mode or test mode. Register bits are cleared on write ‘1’.
Table 3-4. Destructive Event Status Register (RGM_DES) Field Descriptions
Field F_POR Description Flag for Power-On reset 0 No power-on event has occurred since the last clear 1 A power-on event has occurred
F_LVD27_V Flag for 2.7V low-voltage detected (VREG) REG 0 No 2.7V low-voltage detected (VREG) event has occurred since either the last clear or the last power-on reset assertion 1 A 2.7V low-voltage detected (VREG) event has occurred F_LVD27 Flag for 2.7V low-voltage detected 0 No 2.7V low-voltage detected event has occurred since either the last clear or the last power-on reset assertion 1 A 2.7V low-voltage detected event has occurred
MPC5602D Microcontroller Reference Manual, Rev. 3.1 70 Preliminary Freescale Semiconductor
F_LVD12_PD0
R F_POR
F_LVD27_VREG
F_LVD27
F_SWT
Chapter 3 Reset Generation Module (MC_RGM)
Table 3-4. Destructive Event Status Register (RGM_DES) Field Descriptions (continued)
Field F_SWT Description Flag for software watchdog timer 0 No software watchdog timer event has occurred since either the last clear or the last power-on reset assertion 1 A software watchdog timer event has occurred
F_LVD12_P Flag for 1.2V low-voltage detected (power domain #1) D1 0 No 1.2V low-voltage detected (power domain #1) event has occurred since either the last clear or the last power-on reset assertion 1 A 1.2V low-voltage detected (power domain #1) event has occurred F_LVD12_P Flag for 1.2V low-voltage detected (power domain #0) D0 0 No 1.2V low-voltage detected (power domain #0) event has occurred since either the last clear or the last power-on reset assertion 1 A 1.2V low-voltage detected (power domain #0) event has occurred
NOTE The F_POR flag is automatically cleared on a 1.2V low-voltage detected (power domain #0 or #1) or a 2.7V low-voltage detected. This means that if the power-up sequence is not monotonic (i.e., the voltage rises and then drops enough to trigger a low-voltage detection), the F_POR flag may not be set but instead the F_LVD12_PD0, F_LVD12_PD1, or F_LVD27 flag is set on exiting the reset sequence. Therefore, if the F_POR, F_LVD12_PD0, F_LVD12_PD1, or F_LVD27 flags are set on reset exit, software should interpret the reset cause as power-on.
3.3.1.3
Functional Event Reset Disable Register (RGM_FERD)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FE_4004
0 1 2
D_CMU_OLR
D_CMU_FHL
D_FLASH
D_FMPLL
D_LVD45
D_CORE 0
R D_EXR
D_CHKSTOP
D_SOFT
W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-4. Functional Event Reset Disable Register (RGM_FERD)
This register provides dedicated bits to disable functional reset sources.When a functional reset source is disabled, the associated functional event will trigger either a SAFE mode request or an interrupt request (see Section 3.3.1.5, “Functional Event Alternate Request Register (RGM_FEAR)). It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Each byte can be written only once after power-on reset.
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D_JTAG
Chapter 3 Reset Generation Module (MC_RGM)
Table 3-5. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions
Field D_EXR D_FLASH D_LVD45 Description Disable External Reset 0 An external reset event triggers a reset sequence Disable code or data flash fatal error 0 A code or data flash fatal error event triggers a reset sequence Disable 4.5V low-voltage detected 0 A 4.5V low-voltage detected event triggers a reset sequence 1 A 4.5V low-voltage detected event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_LVD45
D_CMU_FH Disable CMU clock frequency higher/lower than reference L 0 A CMU clock frequency higher/lower than reference event triggers a reset sequence 1 A CMU clock frequency higher/lower than reference event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CMU_FHL D_CMU_OL Disable FXOSC frequency lower than reference R 0 A FXOSC frequency lower than reference event triggers a reset sequence 1 A FXOSC frequency lower than reference event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CMU_OLR D_FMPLL Disable FMPLL fail 0 A FMPLL fail event triggers a reset sequence 1 A FMPLL fail event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_FMPLL
D_CHKSTO Disable checkstop reset P 0 A checkstop reset event triggers a reset sequence D_SOFT D_CORE Disable software reset 0 A software reset event triggers a reset sequence Disable core reset 0 A core reset event triggers a reset sequence 1 A core reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CORE Disable JTAG initiated reset 0 A JTAG initiated reset event triggers a reset sequence 1 A JTAG initiated reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_JTAG
D_JTAG
MPC5602D Microcontroller Reference Manual, Rev. 3.1 72 Preliminary Freescale Semiconductor
Chapter 3 Reset Generation Module (MC_RGM)
3.3.1.4
Destructive Event Reset Disable Register (RGM_DERD)
Access: User read, Supervisor read, Test read
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FE_4006
0 1 2
D_LVD12_PD1 0
14
0
W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-5. Destructive Event Reset Disable Register (RGM_DERD)
This register provides dedicated bits to disable particular destructive reset sources. It can be accessed in read-only in supervisor mode, test mode, and user mode.
Table 3-6. Destructive Event Reset Disable Register (RGM_DERD) Field Descriptions
Field Description
D_LVD27_V Disable 2.7V low-voltage detected (VREG) REG 0 A 2.7V low-voltage detected (VREG) event triggers a reset sequence D_LVD27 D_SWT Disable 2.7V low-voltage detected 0 A 2.7V low-voltage detected event triggers a reset sequence Disable software watchdog timer 0 A software watchdog timer event triggers a reset sequence
D_LVD12_P Disable 1.2V low-voltage detected (power domain #1) D1 0 A 1.2V low-voltage detected (power domain #1) event triggers a reset sequence D_LVD12_P Disable 1.2V low-voltage detected (power domain #0) D0 0 A 1.2V low-voltage detected (power domain #0) event triggers a reset sequence
3.3.1.5
Functional Event Alternate Request Register (RGM_FEAR)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 15
Address 0xC3FE_4010
0 1 2
AR_CMU_FHL
AR_FMPLL
AR_LVD45
AR_CORE 0 0 0
R
AR_CMU_OLR
W POR 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-6. Functional Event Alternate Request Register (RGM_FEAR)
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 73
AR_JTAG
D_LVD12_PD0
R
D_LVD27_VREG
D_LVD27
D_SWT
Chapter 3 Reset Generation Module (MC_RGM)
This register defines an alternate request to be generated when a reset on a functional event has been disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to the system. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read only in user mode.
Table 3-7. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions
Field AR_LVD45 Description Alternate Request for 4.5V low-voltage detected 0 Generate a SAFE mode request on a 4.5V low-voltage detected event if the reset is disabled 1 Generate an interrupt request on a 4.5V low-voltage detected event if the reset is disabled
AR_CMU_F Alternate Request for CMU clock frequency higher/lower than reference HL 0 Generate a SAFE mode request on a CMU clock frequency higher/lower than reference event if the reset is disabled 1 Generate an interrupt request on a CMU clock frequency higher/lower than reference event if the reset is disabled AR_CMU_O Alternate Request for FXOSC frequency lower than reference LR 0 Generate a SAFE mode request on a FXOSC frequency lower than reference event if the reset is disabled 1 Generate an interrupt request on a FXOSC frequency lower than reference event if the reset is disabled AR_FMPLL Alternate Request for FMPLL fail 0 Generate a SAFE mode request on a FMPLL fail event if the reset is disabled 1 Generate an interrupt request on a FMPLL fail event if the reset is disabled Alternate Request for core reset 0 Generate a SAFE mode request on a core reset event if the reset is disabled 1 Generate an interrupt request on a core reset event if the reset is disabled Alternate Request for JTAG initiated reset 0 Generate a SAFE mode request on a JTAG initiated reset event if the reset is disabled 1 Generate an interrupt request on a JTAG initiated reset event if the reset is disabled
AR_CORE
AR_JTAG
3.3.1.6
Functional Event Short Sequence Register (RGM_FESS)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FE_4018
0 1 2
SS_CMU_OLR
SS_FLASH
SS_FMPLL
SS_LVD45
SS_CORE 0
R SS_EXR
SS_CHKSTOP
SS_CMU_FHL
SS_SOFT
W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-7. Functional Event Short Sequence Register (RGM_FESS)
This register defines which reset sequence will be done when a functional reset sequence is triggered. The functional reset sequence can either start from PHASE1 or from PHASE3, skipping PHASE1 and PHASE2.
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SS_JTAG
Chapter 3 Reset Generation Module (MC_RGM)
NOTE This could be useful for fast reset sequence, for example to skip flash reset. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user mode.
Table 3-8. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions
Field SS_EXR SS_FLASH SS_LVD45 Description Short Sequence for External Reset 0 The reset sequence triggered by an external reset event will start from PHASE1 Short Sequence for code or data flash fatal error 0 The reset sequence triggered by a code or data flash fatal error event will start from PHASE1 Short Sequence for 4.5V low-voltage detected 0 The reset sequence triggered by a 4.5V low-voltage detected event will start from PHASE1 1 The reset sequence triggered by a 4.5V low-voltage detected event will start from PHASE3, skipping PHASE1 and PHASE2
SS_CMU_F Short Sequence for CMU clock frequency higher/lower than reference HL 0 The reset sequence triggered by a CMU clock frequency higher/lower than reference event will start from PHASE1 1 The reset sequence triggered by a CMU clock frequency higher/lower than reference event will start from PHASE3, skipping PHASE1 and PHASE2 SS_CMU_O Short Sequence for FXOSC frequency lower than reference LR 0 The reset sequence triggered by a FXOSC frequency lower than reference event will start from PHASE1 1 The reset sequence triggered by a FXOSC frequency lower than reference event will start from PHASE3, skipping PHASE1 and PHASE2 SS_FMPLL Short Sequence for FMPLL fail 0 The reset sequence triggered by a FMPLL fail event will start from PHASE1 1 The reset sequence triggered by a FMPLL fail event will start from PHASE3, skipping PHASE1 and PHASE2 Short Sequence for checkstop reset 0 The reset sequence triggered by a checkstop reset event will start from PHASE1 Short Sequence for software reset 0 The reset sequence triggered by a software reset event will start from PHASE1 Short Sequence for core reset 0 The reset sequence triggered by a core reset event will start from PHASE1 1 The reset sequence triggered by a core reset event will start from PHASE3, skipping PHASE1 and PHASE2 Short Sequence for JTAG initiated reset 0 The reset sequence triggered by a JTAG initiated reset event will start from PHASE1 1 The reset sequence triggered by a JTAG initiated reset event will start from PHASE3, skipping PHASE1 and PHASE2
SS_CHKST OP SS_SOFT SS_CORE
SS_JTAG
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Chapter 3 Reset Generation Module (MC_RGM)
3.3.1.7
STANDBY0 Reset Sequence Register (RGM_STDBY)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FE_401A
0 1 2
R
BOOT_FROM_BKP_RAM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-8. STANDBY0 Reset Sequence Register (RGM_STDBY)
This register defines reset sequence to be applied on STANDBY0 mode exit. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read only in user mode.
Table 3-9. STANDBY0 Reset Sequence Register (RGM_STDBY) Field Descriptions
Field BOOT_ FROM_ BKP_RAM Description Boot from Backup RAM indicator — This bit indicates whether the system will boot from backup RAM or flash out of STANDBY0 exit. 0 Boot from flash on STANDBY0 exit 1 Boot from backup RAM on STANDBY0 exit
NOTE This register is reset on any enabled ‘destructive’ or ‘functional’ reset event.
3.3.1.8
Functional Bidirectional Reset Enable Register (RGM_FBRE)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FE_401C
0 1 2
BE_CMU_OLR
BE_FMPLL
BE_FLASH
BE_LVD45
BE_CORE 0
R BE_EXR
BE_CHKSTOP
BE_CMU_FHL
BE_SOFT
W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-9. Functional Bidirectional Reset Enable Register (RGM_FBRE)
This register enables the generation of an external reset on functional reset. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user mode.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 76 Preliminary Freescale Semiconductor
BE_JTAG
Chapter 3 Reset Generation Module (MC_RGM)
Table 3-10. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions
Field BE_EXR Description Bidirectional Reset Enable for External Reset 0 RESET is asserted on an external reset event if the reset is enabled 1 RESET is not asserted on an external reset event Bidirectional Reset Enable for code or data flash fatal error 0 RESET is asserted on a code or data flash fatal error event if the reset is enabled 1 RESET is not asserted on a code or data flash fatal error event Bidirectional Reset Enable for 4.5V low-voltage detected 0 RESET is asserted on a 4.5V low-voltage detected event if the reset is enabled 1 RESET is not asserted on a 4.5V low-voltage detected event
BE_FLASH
BE_LVD45
BE_CMU_F Bidirectional Reset Enable for CMU clock frequency higher/lower than reference HL 0 RESET is asserted on a CMU clock frequency higher/lower than reference event if the reset is enabled 1 RESET is not asserted on a CMU clock frequency higher/lower than reference event BE_CMU_O Bidirectional Reset Enable for FXOSC frequency lower than reference LR 0 RESET is asserted on a FXOSC frequency lower than reference event if the reset is enabled 1 RESET is not asserted on a FXOSC frequency lower than reference event BE_FMPLL Bidirectional Reset Enable for FMPLL fail 0 RESET is asserted on a FMPLL fail event if the reset is enabled 1 RESET is not asserted on a FMPLL fail event Bidirectional Reset Enable for checkstop reset 0 RESET is asserted on a checkstop reset event if the reset is enabled 1 RESET is not asserted on a checkstop reset event Bidirectional Reset Enable for software reset 0 RESET is asserted on a software reset event if the reset is enabled 1 RESET is not asserted on a software reset event Bidirectional Reset Enable for core reset 0 RESET is asserted on a core reset event if the reset is enabled 1 RESET is not asserted on a core reset event Bidirectional Reset Enable for JTAG initiated reset 0 RESET is asserted on a JTAG initiated reset event if the reset is enabled 1 RESET is not asserted on a JTAG initiated reset event
BE_CHKST OP BE_SOFT
BE_CORE
BE_JTAG
3.4
3.4.1
Functional Description
Reset State Machine
The main role of MC_RGM is the generation of the reset sequence which ensures that the correct parts of the device are reset based on the reset source event. This is summarized in Table 3-11.
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Chapter 3 Reset Generation Module (MC_RGM)
Table 3-11. MC_RGM Reset Implications
Source power-on reset ‘destructive’ resets external reset ‘functional’ resets all all except some clock/reset management all except some clock/reset management and debug all except some clock/reset management and debug What Gets Reset External Reset Assertion1 yes yes programmable2 Boot Mode Capture yes yes yes
programmable2 programmable3 programmable2 programmable3
shortened ‘functional’ resets4 flip-flops except some clock/reset management
1 2
‘external reset assertion’ means that the RESET pin is asserted by the MC_RGM until the end of reset PHASE3 the assertion of the external reset is controlled via the RGM_FBRE register 3 the boot mode is captured if the external reset is asserted 4 the short sequence is enabled via the RGM_FESS register
NOTE JTAG logic has its own independent reset control and is not controlled by the MC_RGM in any way. The reset sequence is comprised of five phases managed by a state machine, which ensures that all phases are correctly processed through waiting for a minimum duration and until all processes that need to occur during that phase have been completed before proceeding to the next phase. The state machine used to produce the reset sequence is shown in Figure 3-10.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 78 Preliminary Freescale Semiconductor
Chapter 3 Reset Generation Module (MC_RGM)
power-on or enabled ‘destructive’ reset
PHASE0
duration 3 fast internal RC oscillator (16 MHz) clock cycles FIRC stable, VREG voltage okay done
enabled non-shortened external or ‘functional’ reset1
PHASE1
duration 10 fast internal RC oscillator (16 MHz) clock cycles
PHASE2
duration fast internal RC oscillator (16 MHz) clock cycles code and data flash initialization done
PHASE3 enabled shortened external or ‘functional’ reset
duration 40fast internal RC oscillator (16 MHz) clock cycles RESET released code and data flash initialization done
IDLE
Figure 3-10. MC_RGM State Machine
3.4.1.1
PHASE0 Phase
This phase is entered immediately from any phase on a power-on or enabled ‘destructive’ reset event. The reset state machine exits PHASE0 and enters PHASE1 on verification of the following: • all enabled ‘destructive’ resets have been processed • all processes that need to be done in PHASE0 are completed
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Chapter 3 Reset Generation Module (MC_RGM)
•
— FIRC stable, VREG voltage okay a minimum of 3 fast internal RC oscillator (16 MHz) clock cycles have elapsed since power-up completion and the last enabled ‘destructive’ reset event
3.4.1.2
PHASE1 Phase
This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE on a non-masked external or ‘functional’ reset event if it has not been configured to trigger a ‘short’ sequence. The reset state machine exits PHASE1 and enters PHASE2 on verification of the following: • all enabled, non-shortened ‘functional’ resets have been processed • a minimum of 10 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last enabled external or non-shortened ‘functional’ reset event
3.4.1.3
PHASE2 Phase
This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and enters PHASE3 on verification of the following: • all processes that need to be done in PHASE2 are completed — code and data flash initialization • a minimum of 8 fast internal RC oscillator (16 MHz) clock cycles have elapsed since entering PHASE2
3.4.1.4
PHASE3 Phase
This phase is a entered either on exit from PHASE2 or immediately from IDLE on an enabled, shortened ‘functional’ reset event. The reset state machine exits PHASE3 and enters IDLE on verification of the following: • all processes that need to be done in PHASE3 are completed — code and data flash initialization • a minimum of 40 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last enabled, shortened ‘functional’ reset event 3.4.1.5 IDLE Phase
This is the final phase and is entered on exit from PHASE3. When this phase is reached, the MC_RGM releases control of the system to the platform and waits for new reset events that can trigger a reset sequence.
3.4.2
Destructive Resets
A ‘destructive’ reset indicates that an event has occurred after which critical register or memory content can no longer be guaranteed.
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Chapter 3 Reset Generation Module (MC_RGM)
The status flag associated with a given ‘destructive’ reset event (RGM_DES.F_ bit) is set when the ‘destructive’ reset is asserted and the power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is the most critical for the application. The device’s low-voltage detector threshold ensures that, when 1.2V low-voltage detected (power domain #0) is enabled, the supply is sufficient to have the destructive event correctly propagated through the digital logic. Therefore, if a given ‘destructive’ reset is enabled, the MC_RGM ensures that the associated reset event will be correctly triggered to the full system. However, if the given ‘destructive’ reset is disabled and the voltage goes below the digital functional threshold, functionality can no longer be ensured, and the reset may or may not be asserted. An enabled destructive reset will trigger a reset sequence starting from the beginning of PHASE0.
3.4.3
External Reset
The MC_RGM manages the external reset coming from RESET. The detection of a falling edge on RESET will start the reset sequence from the beginning of PHASE1. The status flag associated with the external reset falling edge event (RGM_FES.F_EXR bit) is set when the external reset is asserted and the power-on reset is not asserted. The external reset can optionally be disabled by writing bit RGM_FERD.D_EXR. NOTE The RGM_FERD register can be written only once between two power-on reset events. An enabled external reset will normally trigger a reset sequence starting from the beginning of PHASE1. Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by the external reset. When RGM_FESS.SS_EXR is set, the external reset will trigger a reset sequence starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2. This can be useful especially when an external reset should not reset the flash. The MC_RGM may also assert the external reset if the reset sequence was triggered by one of the following: • a power-on reset • a ‘destructive’ reset event • an external reset event • a ‘functional’ reset event configured via the RGM_FBRE register to assert the external reset In this case, the external reset is asserted until the end of PHASE3.
3.4.4
Functional Resets
A ‘functional’ reset indicates that an event has occurred after which it can be guaranteed that critical register and memory content is still intact.
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Chapter 3 Reset Generation Module (MC_RGM)
The status flag associated with a given ‘functional’ reset event (RGM_FES.F_ bit) is set when the ‘functional’ reset is asserted and the power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is the most critical for the application. The ‘functional’ reset can be optionally disabled by software writing bit RGM_FERD.D_. NOTE The RGM_FERD register can be written only once between two power-on reset events. An enabled functional reset will normally trigger a reset sequence starting from the beginning of PHASE1. Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by a functional reset. When RGM_FESS.SS_ is set, the associated ‘functional’ reset will trigger a reset sequence starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2. This can be useful especially in case a functional reset should not reset the flash module.
3.4.5
STANDBY0 Entry Sequence
STANDBY0 mode can be entered only when the MC_RGM is in IDLE. On STANDBY0 entry, the MC_RGM moves to PHASE1. The minimum duration counter in PHASE1 does not start until STANDBY0 mode is exited. On entry to PHASE1 due to STANDBY0 mode entry, the resets for all power domains except power domain #0 are asserted. During this time, RESET is not asserted as the external reset can act as a wakeup for the device. There is an option to keep the flash inaccessible and in low-power mode on STANDBY0 exit by configuring the DRUN mode before STANDBY0 entry so that the flash is in power-down or low-power mode. If the flash is to be inaccessible, the PHASE2 and PHASE3 states do not wait for the flash to complete initialization before exiting, and the reset to the flash remains asserted. See the MC_ME chapter for details on the STANDBY0 and DRUN modes.
3.4.6
Alternate Event Generation
The MC_RGM provides alternative events to be generated on reset source assertion. When a reset source is asserted, the MC_RGM normally enters the reset sequence. Alternatively, it is possible for some reset source events to be converted from a reset to either a SAFE mode request issued to the MC_ME or to an interrupt request issued to the core. Alternate event selection for a given reset source is made via the RGM_FERD and RGM_FEAR registers as shown in Table 3-12.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 82 Preliminary Freescale Semiconductor
Chapter 3 Reset Generation Module (MC_RGM)
Table 3-12. MC_RGM Alternate Event Selection
RGM_FERD Bit Value 0 1 1 RGM_FEAR Bit Value X 0 1 reset SAFE mode request interrupt request Generated Event
The alternate event is cleared by deasserting the source of the request (i.e., at the reset source that caused the alternate request) and also clearing the appropriate RGM_FES status bit. NOTE Alternate requests (SAFE mode as well as interrupt requests) are generated regardless of whether the system clock is running. NOTE If a masked ‘functional’ reset event which is configured to generate a SAFE mode/interrupt request occurs during PHASE1, it is ignored, and the MC_RGM will not send any safe mode/interrupt request to the MC_ME.
3.4.7
Boot Mode Capturing
The MC_RGM provides sampling of the boot mode PA[9:8] for use by the system. This sampling is done five fast internal RC oscillator (16 MHz) clock cycles before the rising edge of RESET. The result of the sampling is then provided to the system. For each bit, a value of ‘1’ is produced only if each of the oldest three of the five samples have the value ‘1’, otherwise a value of ‘0’ is produced. NOTE In order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode value to the device at least five fast internal RC oscillator (16 MHz) clock periods before the external reset deassertion crosses the VIH threshold. NOTE RESET can be low as a consequence of the internal reset generation. This will force re-sampling of the boot mode pins. (See Table 3-11 for details.)
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 83
Chapter 3 Reset Generation Module (MC_RGM)
MPC5602D Microcontroller Reference Manual, Rev. 3.1 84 Preliminary Freescale Semiconductor
Chapter 4 Clock description
Chapter 4 Clock description
This chapter describes the clock architectural implementation for MPC5602D.
4.1
Clock architecture
System clocks are generated from three sources: • Fast external crystal oscillator 4-16 MHz (FXOSC) • Fast internal RC oscillator 16 MHz (FIRC) • Frequency modulated phase locked loop (FMPLL) Additionally, there is a slow internal RC oscillator 128 kHz (SIRC) The clock architecture is shown in Figure 4-1.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 85
Chapter 4 Clock description
FXOSC
FXOSC_clk (4–16 MHz) FIRC_clk
/1 to /32
FXOSC_clk_div (e.g. 8 MHz) FIRC_clk_div System Clock Selector FMPLL FMPLL_clk (e.g. 48 MHz) /1 to /16 Peripheral Set 1 Clock Monitor Unit Peripheral Set 2 Peripheral Set 3 DMA sys_clk Core Platform
FIRC
(16 MHz)
/1 to /32
(e.g. 16 MHz)
Reset Safe Interrupt
/1 to /16
/1 to /16
FIRC_div rtc_clk SIRC SIRC_clk (128 kHz) /1 to /32 SIRC_clk_div SIRC_clk_div API/RTC
SIRC_clk
Watchdog
FXOSC_clk FIRC_clk FMPLL_clk (e.g. 48 MHz) sys_clk r tc_clk CLKOUT Selector /1, /2, /4, /8 CLKOUT
Figure 4-1. MPC5602D system clock generation
4.2
Clock gating
The MPC5602D provides the user with the possibility of gating the clock to the peripherals. Table 4-1 describes for each peripheral the associated gating register address. See Section 6.3.2.22, “Peripheral Control Registers (ME_PCTL0…143).” Additionally, peripheral set (1, 2 or 3) frequency can be configured to be an integer (1 to 16) divided version of the main system clock. See Section 5.3.1.4, “System Clock Divider Configuration Registers (CGM_SC_DC0…2) for details.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 86 Preliminary Freescale Semiconductor
Chapter 4 Clock description
Table 4-1. MPC5602D - Peripheral clock sources
Peripheral RPP_Z0H Platform DSPI_n FlexCAN ADC LINFLEX_n CTU CANS SIUL WKUP eMIOS RTC/API PIT CMU
1 2
Register gating address offset (base = 0xC3FDC0C0)1 none (managed through ME mode) 4+n (n = 0..1) 16 32 48+n(n = 0..2) 57 60 68 69 72 91 92 104
Peripheral set2 — 2 2 3 1 3 — — — 3 — — —
See Section 6.3.2.22, “Peripheral Control Registers (ME_PCTL0…143) for details. “—” means undivided system clock.
4.3
Fast external crystal oscillator (FXOSC) digital interface
The FXOSC digital interface controls the operation of the 4–16 MHz fast external crystal oscillator (FXOSC). It holds control and status registers accessible for application.
4.3.1
• • • •
Main features
Oscillator powerdown control and status reporting through MC_ME block Oscillator clock available interrupt Oscillator bypass mode Output clock division factors ranging from 1, 2, 3....32
4.3.2
Functional description
The FXOSC circuit includes an internal oscillator driver and an external crystal circuitry. It provides an output clock that can be provided to the FMPLL or used as a reference clock to specific modules depending on system needs. The FXOSC can be controlled by the MC_ME module. The ME_xxx_MC[FXOSCON] bit controls the powerdown of the oscillator based on the current device mode while ME_GS[S_XOSC] register provides the oscillator clock available status.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 87
Chapter 4 Clock description
After system reset, the oscillator is put into powerdown state and software has to switch on when required. Whenever the crystal oscillator is switched on from the off state, the OSCCNT counter starts and when it reaches the value EOCV[7:0]×512, the oscillator clock is made available to the system. Also, an interrupt pending FXOSC_CTL[I_OSC] bit is set. An interrupt is generated if the interrupt mask bit M_OSC is set. The oscillator circuit can be bypassed by setting FXOSC_CTL[OSCBYP]. This bit can only be set by software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the same polarity as the external clock applied on the EXTAL pin and the oscillator status is forced to ‘1’. The bypass configuration is independent of the powerdown mode of the oscillator. Table 4-2 shows the truth table of different oscillator configurations.
Table 4-2. Truth table of crystal oscillator
ME_xxx_MC[FXOSCON] FXOSC_CTL[OSCBYP] 0 x 1 0 1 0 XTAL No crystal, High Z x Crystal Gnd EXTAL No crystal, High Z Ext clock Crystal Ext clock FXOSC 0 EXTAL EXTAL EXTAL Oscillator MODE Powerdown, IDDQ Bypass, OSC disabled Normal, OSC enabled Normal, OSC enabled
The FXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. This division factor is specified by FXOSC_CTL[OSCDIV] field.
4.3.3
Register description
Base Address: 0xC3FE0000
2 3 4 Reserved 5 6 7 8 9 10 11 12 13 14 15
Address offset: 0x0000
0 OSCBYP 1
EOCV[7:0]
Access Reset
rs
—
rw
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16 M_OSC
17
18
19
20
21 OSCDIV[4:0]
22
23
24 I_OSC
25
26
27
28 Reserved
29
30
31
Reserved
Access Reset
rw
—
rw
rc
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-2. Fast External Crystal Oscillator Control Register (FXOSC_CTL)
MPC5602D Microcontroller Reference Manual, Rev. 3.1 88 Preliminary Freescale Semiconductor
Chapter 4 Clock description
Table 4-3. Fast External Crystal Oscillator Control Register (FXOSC_CTL) field descriptions
Field 0 OSCBYP Description Crystal Oscillator bypass This bit specifies whether the oscillator should be bypassed or not. Only software can set this bit. System reset is needed to clear this bit. 0: Oscillator output is used as root clock 1: EXTAL is used as root clock Reserved End of Count Value These bits specify the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state (OSCCNT runs on the FXOSC). This counting period ensures that external oscillator clock signal is stable before it can be selected by the system. When oscillator counter reaches the value EOCV[7:0] × 512, the crystal oscillator clock interrupt (I_OSC) request is generated. The OSCCNT counter will be kept under reset if oscillator bypass mode is selected. Crystal oscillator clock interrupt mask 0: Crystal oscillator clock interrupt is masked 1: Crystal oscillator clock interrupt is enabled Reserved Crystal oscillator clock division factor These bits specify the crystal oscillator output clock division factor. The output clock is divided by the factor OSCDIV+1. Crystal oscillator clock interrupt This bit is set by hardware when OSCCNT counter reaches the count value EOCV[7:0]×512. It is cleared by software by writing ‘1’. 0: No oscillator clock interrupt occurred 1: Oscillator clock interrupt pending Reserved
1-7 8-15 EOCV[7:0]
16 M_OSC 17-18 19-23 OSCDIV[4:0] 24 I_OSC
25-31
4.4
4.4.1
Slow internal RC oscillator (SIRC) digital interface
Introduction
The SIRC digital interface controls the 128 kHz slow internal RC oscillator (SIRC). It holds control and status registers accessible for application.
4.4.2
Functional description
The SIRC provides a low frequency (fSIRC) clock of 128 kHz requiring very low current consumption. This clock can be used as the reference clock when a fixed base time is required for specific modules. SIRC is always on in all device modes except STANDBY0 mode. In STANDBY0 mode, it is controlled by SIRC_CTL[SIRCON_STDBY] bit. The clock source status is updated in SIRC_CTL[S_SIRC] bit. The SIRC clock can be further divided by a configurable division factor in the range from 1 to 32 to generate the divided clock to match system requirements. This division factor is specified by SIRC_CTL[SIRCDIV] bits.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 89
Chapter 4 Clock description
The SIRC output frequency can be trimmed by SIRC_CTL[SIRCTRIM] bits. After power on reset, the trimming bits are provided by the Flash options. Only after a first write access will the value specified by bits SIRCTRIM control the trimming. In this oscillator, two's complement trimming method is implemented. So the trimming code increases from -16 to 15. As the trimming code increases, the internal time constant increases and frequency reduces. Please refer to device datasheet for average frequency variation of the trimming step.
4.4.3
Register description
Base Address: 0xC3FE_0080 2 3 4 5 Reserved 6 7 8 9 10 11 12 13 14 15
Address offset: 0x0000 0 1
SIRCTRIM[4:0] rw 0 0 0 0 0 0 0 0 0 0
Access Reset 0 0 0 0 0
— 0
16
17 Reserved
18
19
20
21
22
23
24
25 Reserved
26
27
28
29 Reserved
30
31 SIRCON_STDBY rw
SIRCDIV[4:0]
Access Reset 0
— 0 0 0 0
rw 0 1 1 0
— 0 0
S_SIRC r 0 0
— 0 0
0
Figure 4-3. Low Power RC Control Register (SIRC_CTL) Table 4-4. Low Power RC Control Register (SIRC_CTL) field descriptions
Field 0-10 11-15 SIRCTRIM[4:0] 16-18 19-23 SIRCDIV[4:0] 24-26 27 S_SIRC Reserved SIRC trimming bits Note: Not all configurations can be used. Please refer to data sheet. Reserved SIRC clock division factor These bits specify the SIRC oscillator output clock division factor. The output clock is divided by the factor SIRCDIV+1. Reserved SIRC clock status 0: SIRC is not providing a stable clock 1: SIRC is providing a stable clock Description
MPC5602D Microcontroller Reference Manual, Rev. 3.1 90 Preliminary Freescale Semiconductor
Chapter 4 Clock description
Table 4-4. Low Power RC Control Register (SIRC_CTL) field descriptions (continued)
Field 28-30 31 SIRCON_STDBY Reserved SIRC control in STANDBY0 mode 0: SIRC is switched off in STANDBY0 mode 1: SIRC is switched on in STANDBY0 mode Description
4.5
4.5.1
Fast internal RC oscillator (FIRC) digital interface
Introduction
The FIRC digital interface controls the 16 MHz fast internal RC oscillator (FIRC). It holds control and status registers accessible for application.
4.5.2
Functional description
The FIRC provides a high frequency (fFIRC) clock of 16 MHz. This clock can be used to accelerate the exit from reset and wakeup sequence from low power modes of the system. It is controlled by the MC_ME module based on the current device mode. The clock source status is updated in ME_GS[S_RC]. Please refer to the MC_ME chapter for further details. The FIRC can be further divided by a configurable division factor in the range from 1 to 32 to generate the divided clock to match system requirements. This division factor is specified by RC_CTL[RCDIV] bits. The FIRC output frequency can be trimmed by RC_CTL[FIRCTRIM] bits. These bits can be programmed to modify internal capacitor/resistor values. After power on reset, the trimming bits are provided by the flash options. Only after a first write access will the value specified by bits FIRCTRIM control the trimming. In this oscillator, two's complement trimming method is implemented. So the trimming code increases from -32 to 31. As the trimming code increases, the internal time constant increases and frequency reduces. Please refer to device datasheet for average frequency variation of the trimming step. During STANDBY0 mode entry process, the FIRC is controlled based on ME_STANDBY_MC[RCON] bit. This is the last step in the standby entry sequence. On any system wake-up event, the device exits STANDBY0 mode and switches on the FIRC. The actual powerdown status of the FIRC when the device is in standby is provided by RC_CTL[FIRC_STDBY] bit.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 91
Chapter 4 Clock description
4.5.3
Register description
Base Address: 0xC3FE_0060 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address offset: 0x0000 0 1
Reserved Access Reset 0 0 0 0 0 — 0 0 0 0 0 0 0
FIRCTRIM[5:0] rw 0 0 0 0
16
17 Reserved
18
19
20
21
22
23
24
25
26 FIRCON_STDBY
27
28
29
30
31
FIRCDIV[4:0]
Reserved
Reserved
Access Reset 0
— 0 0 0 0
rw 0 0 0 0
— 0
rw
— 0 0 0 0 0
0
Figure 4-4. RC Oscillator Control Register (RC_CTL) Table 4-5. RC Oscillator Control Register (RC_CTL) field descriptions
Field 0-9 10-15 FIRCTRIM[5:0] 16-18 19-23 FIRCDIV[4:0] 24-26 Reserved FIRC trimming bits Note: All configurations cannot be used. Please refer to data sheet. Reserved FIRC clock division factor These bits specify the FIRC oscillator output clock division factor. The output clock is divided by the factor FIRCDIV+1. Reserved Description
26 FIRC control in STANDBY0 mode FIRCON_STDB 0: FIRC is switched off in STANDBY0 mode Y 1: FIRC is in STANDBY0 mode 27-31 Reserved
4.6
4.6.1
Frequency-modulated phase-locked loop (FMPLL)
Introduction
This section describes the features and functions of the FMPLL module implemented in the device.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 92 Preliminary Freescale Semiconductor
Chapter 4 Clock description
4.6.2
Overview
The FMPLL enables the generation of high speed system clocks from a common 4–16 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor and output clock divider ratio are all software configurable. MPC5602D has one FMPLL that can generate the system clock and takes advantage of the FM mode. NOTE The user must take care not to program device with a frequency higher than allowed (no hardware check). The FMPLL block diagram is shown in Figure 4-5.
FXOSC IDF Charge Pump Low Pass Filter NDIV Loop Frequency Divider PHI VCO ODF
BUFFER
Figure 4-5. FMPLL block diagram
4.6.3
Features
The FMPLL has the following major features: • Input clock frequency 4 MHz – 16 MHz • Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz • Frequency divider (FD) for reduced frequency operation without forcing the FMPLL to relock • Frequency modulated FMPLL — Modulation enabled/disabled through software — Triangle wave modulation • Programmable modulation depth — ±0.25% to ±4% deviation from center spread frequency1 — 0.5% to +8% deviation from down spread frequency — Programmable modulation frequency dependent on reference frequency • Self-clocked mode (SCM) operation • 5 available modes — Normal mode — Progressive clock switching — Normal mode with SSCG — Powerdown mode
1. Spread spectrum should be programmed in line with maximum datasheet frequency figures. MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 93
Chapter 4 Clock description
4.6.4
Memory map1
Table 4-6. FMPLL memory map
Base address: 0xC3FE00A0 (FMPLL_0) Address offset 0x0000 Register Control Register (CR) Access R/W (write access in supervisor mode only) R/W (write access in supervisor mode only) Location on page 94
Table 4-6 shows the memory map of the FMPLL.
0x0004
Modulation Register (MR)
on page 97
4.6.5
Register description
The FMPLL operation is controlled by two registers. Those registers can be accessed and written in supervisor mode only.
4.6.5.1
Control Register (CR)
Access: Supervisor read/write 1 0 2 3 4 5 6 7 8 0 9 10 11 12 NDIV[6:0] 13 14 15
Offset 0x0000 0 R W Reset 0 0 0 0 0 0 0 0 0 1 0 0
IDF[3:0]
ODF[1:0]
0
0
0
0
0
16 R 0
17 0
18 0
19 0
20 0
21 0
22 0
23
EN_ PLL_ SW
24 0
25
UN LOCK_ ONCE
26 0
27
i_ LOCK
28
S_ LOCK
29
PLL_ FAIL_ MASK
30
PLL_ FAIL_ FLAG
31 0
W Reset1 0 0 0 0 0 0 0 0 0 0 0
w1c 0 0 0
w1c 0 0
Figure 4-6. Control Register (CR)
1
Reset value is determined by the SoC integration.
1. FMPLL_x are mapped through the ME_CGM register slot MPC5602D Microcontroller Reference Manual, Rev. 3.1 94 Preliminary Freescale Semiconductor
Chapter 4 Clock description
Table 4-7. CR field descriptions
Field 2-5 IDF[3:0] 6-7 ODF[1:0] 9-15 NDIV[6:0] 23 EN_PLL_SW Description The value of this field sets the FMPLL input division factor as described in Table 4-8. The reset value is set during integration. The value of this field sets the FMPLL output division factor as described in Table 4-9. The reset value is set during integration. The value of this field sets the FMPLL loop division factor as described in Table 4-10. The reset value is set during integration. This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially is divided by 8, and then progressively decreases until it reaches divide-by-1. 0: Progressive clock switching disabled 1: Progressive clock switching enabled Note: Progressive clock switching should not be used if a non-changing clock is needed, such as for serial communications, until the division has finished.
25 This bit is a sticking indication of FMPLL loss of lock condition. UNLOCK_ONCE is set when the UNLOCK_ONCE FMPLL loses lock. Whenever the FMPLL reacquires lock, UNLOCK_ONCE remains set. Only a power-on reset clears this bit. 27 I_LOCK 28 S_LOCK This bit is set by hardware whenever there is a lock/unlock event. It is cleared by software writing ‘1’. This bit is an indication of whether the FMPLL has acquired lock. 0: FMPLL unlocked 1: FMPLL locked
29 This bit is used to mask the pll_fail output. PLL_FAIL_MASK 0: pll_fail not masked 1: pll_fail masked 30 This bit is asynchronously set by hardware whenever a loss of lock event occurs while FMPLL PLL_FAIL_FLAG is switched on. It is cleared by software writing ‘1’.
Table 4-8. Input divide ratios
IDF[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Input divide ratios Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 95
Chapter 4 Clock description
Table 4-8. Input divide ratios (continued)
IDF[3:0] 1010 1011 1100 1101 1110 1111 Input divide ratios Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 Clock Inhibit
Table 4-9. Output divide ratios
ODF[1:0] 00 01 10 11 Output divide ratios Divide by 2 Divide by 4 Divide by 8 Divide by 16
Table 4-10. Loop divide ratios
NDIV[6:0] 0000000–0011111 0100000 0100001 0100010 ... 1011111 1100000 1100001–1111111 Loop divide ratios — Divide by 32 Divide by 33 Divide by 34 ... Divide by 95 Divide by 96 —
MPC5602D Microcontroller Reference Manual, Rev. 3.1 96 Preliminary Freescale Semiconductor
Chapter 4 Clock description
4.6.5.2
Modulation Register (MR)
Access: Supervisor read/write
1 SPRD_SEL 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset 0x0004
0 R W STRB_BYPASS
MOD_PERIOD[12:0]
Rese t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 R W Rese t FM_EN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
INC_STEP[14:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-7. Modulation Register (MR) Table 4-11. MR field descriptions
Field Description
0 Strobe bypass STRB_BYPASS The STRB_BYPASS signal is used to bypass the strobe signal used inside FMPLL to latch the correct values for control bits (INC_STEP, MOD_PERIOD and SPRD_SEL). 0: Strobe is used to latch FMPLL modulation control bits 1: Strobe is bypassed. In this case control bits need to be static. The control bits must be changed only when FMPLL is in powerdown mode. 2 SPRD_SEL Spread type selection The SPRD_SEL control the spread type in Frequency Modulation mode. 0: Center SPREAD 1: Down SPREAD
3-15 Modulation period MOD_PERIOD The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following [12:0] formula: f ref modperiod = ------------------4 f mod where: fref: represents the frequency of the feedback divider fmod: represents the modulation frequency
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 97
Chapter 4 Clock description
Table 4-11. MR field descriptions (continued)
Field 16 FM_EN Description Frequency Modulation Enable The FM_EN enables the frequency modulation. 0: Frequency modulation disabled 1: Frequency modulation enabled Increment step The INC_STEP field is the binary equivalent of the value incstep derived from following formula: 2 – 1 md MDF incstep = round -------------------------------------------------------------- 100 5 MODPERIOD where: md: represents the peak modulation depth in percentage (Center spread -- pk-pk=+/-md, Downspread -- pk-pk=-2×md) MDF: represents the nominal value of loop divider (NDIV in FMPLL Control Register)
15
17-31 INC_STEP [14:0]
4.6.6
4.6.6.1
Functional description
Normal mode
In Normal Mode the FMPLL inputs are driven by the CR. This means that, when the FMPLL is in lock state, the FMPLL output clock (PHI) is derived by the reference clock () through this relation:
phi = clkin NDIV --------------------------------IDF ODF
where the value of IDF, NDIV and ODF are set in the CR and can be derived from Table 4-8, Table 4-9 and Table 4-10.
4.6.6.2
Progressive clock switching
Progressive clock switching allows to switch the system clock to FMPLL output clock stepping through different division factors. This means that the current consumption gradually increases and, in turn, voltage regulator response is improved. This feature can be enabled by programming CR[EN_PLL_SW] bit. When enabled, the system clock is switched to divided PHI. The FMPLL_clk divider is then progressively decreased to the target divider as shown in Table 4-12.
Table 4-12. Progressive clock switching on pll_select rising edge
Number of FMPLL output clock cycles 8 16 FMPLL_clk frequency (FMPLL output clock frequency) (FMPLL output clock frequency)/8 (FMPLL output clock frequency)/4
MPC5602D Microcontroller Reference Manual, Rev. 3.1 98 Preliminary Freescale Semiconductor
Chapter 4 Clock description
Table 4-12. Progressive clock switching on pll_select rising edge
Number of FMPLL output clock cycles 32 onward FMPLL_clk frequency (FMPLL output clock frequency) (FMPLL output clock frequency)/2 FMPLL output clock frequency
FMPLL output clock
Division factors of 8, 4, 2 or 1
FMPLL_clk
Figure 4-8. FMPLL output clock division flow during progressive switching
4.6.6.3
Normal mode with frequency modulation
The FMPLL default mode is without frequency modulation enabled. When frequency modulation is enabled, however, two parameters must be set to generate the desired level of modulation: the PERIOD, and the STEP. The modulation waveform is always a triangle wave and its shape is not programmable. FM mode is activated in two steps: 1. Configure the FM mode characteristics: MOD_PERIOD, INC_STEP. 2. Enable the FM mode by programming bit FM_EN of the MR to ‘1’. FM mode can only be enabled when FMPLL is in lock state. There are two ways to latch these values inside the FMPLL, depending on the value of bit STRB_BYPASS in the MR. If STRB_BYPASS is low, the modulation parameters are latched in the FMPLL only when the strobe signal goes high for at least two cycles of CLKIN clock. The strobe signal is automatically generated in the FMPLL digital interface when the modulation is enabled (FM_EN goes high) if the FMPLL is locked (S_LOCK = 1) or when the modulation has been enabled (FM_EN = 1) and FMPLL enters lock state (S_LOCK goes high). If STRB_BYPASS is high, the strobe signal is bypassed. In this case, control bits (MOD_PERIOD[12:0], INC_STEP[14:0], SPREAD_CONTROL) need to be static or hardwired to constant values. The control bits must be changed only when the FMPLL is in powerdown mode. The modulation depth in % is
100 5 INCSTEPxMODPERIOD ModulationDepth = -------------------------------------------------------------------------------------------- 15 2 – 1 MDF
NOTE The user must ensure that the product of INCTEP and MODPERIOD is less than (215-1).
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 99
Chapter 4 Clock description
Figure 4-9. Frequency modulation
4.6.6.4
Powerdown mode
To reduce consumption, the FMPLL can be switched off when not required by programming the registers ME_x_MC on the MC_ME module.
4.6.7
Recommendations
To avoid any unpredictable behavior of the FMPLL clock, it is recommended to follow these guidelines: • The FMPLL VCO frequency should reside in the range 256 MHz to 512 MHz. Care is required when programming the multiplication and division factors to respect this requirement. • The user must change the multiplication, division factors only when the FMPLL output clock is not selected as system clock. Use progressive clock switching if system clock changes are required while the PLL is being used as the system clock source. MOD_PERIOD, INC_STEP, SPREAD_SEL bits should be modified before activating the FM mode. Then strobe has to be generated to enable the new settings. If STRB_BYP is set to ‘1’ then MOD_PERIOD, INC_STEP and SPREAD_SEL can be modified only when FMPLL is in powerdown mode. • Use progressive clock switching (FMPLL output clock can be changed when it is the system clock, but only when using progressive clock switching).
4.7
4.7.1
Clock monitor unit (CMU)
Introduction
The Clock Monitor Unit (CMU), also referred to as Clock Quality Checker or Clock Fault Detector, serves two purposes. The main task is to permanently supervise the integrity of the various clock sources, for example a crystal oscillator or FMPLL. In case the FMPLL leaves an upper or lower frequency boundary
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Chapter 4 Clock description
or the crystal oscillator fails it can detect and forward these kind of events towards the mode and clock management unit. The clock management unit in turn can then switch to a SAFE mode where it uses the default safe clock source (FIRC), reset the device or generate the interrupt according to the system needs. It can also monitor the external crystal oscillator clock, which must be greater than the internal RC clock divided by a division factor given by CMU_CSR[RCDIV], and generates a system clock transition request or an interrupt when enabled. The second task of the CMU is to provide a frequency meter, which allows to measure the frequency of one clock source vs. a reference clock. This is useful to allow the calibration of the on-chip RC oscillator(s), as well as being able to correct/calculate the time deviation of a counter which is clocked by the RC oscillator.
S X O S C v a lid F X O S C v a lid SXOSC S IR C F IR C FXOSC FM PLL C K_32K C K _ IR C s lo w C K _ IR C fa s t C K_XO SC O LR C K_PLL FHH FLL S IR C v a lid F IR C v a lid
( o n A N D s t a b le ) /o f f
( o n A N D s t a b le ) /o f f
( o n A N D lo c k e d ) /o ff
M E, CG M , RG M , PCU m o d u le
( o n A N D s ta b le ) /o ff
CMU
F M P L L v a lid
( o n A N D lo c k e d ) /o f f
L o s s o f C ry s ta l
F M P L L fre q . o u t o f ra n g e
L o g ic a l O R
F M P L L lo s s - o f- L o c k ( p ll_ fa il fr o m d ig . F M P L L )
Figure 4-10. CMU block diagram
4.7.2
• • • •
Main features
FIRC, SIRC, SXOSC oscillator frequency measurement using FXOSC as reference clock External oscillator clock monitoring with respect to FIRC_clk/n clock FMPLL clock frequency monitoring for a high and low frequency range with FIRC as reference clock Event generation for various failures detected inside monitoring unit
4.7.3
Block diagram
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Chapter 4 Clock description
CKSEL1[1:0] FIRC_clk SIRC_clk 01 reserved 10 FIRC_clk 11 FXOSC_clk MUX1 00
CMU_MDR
Frequency Meter
CMU_FDR
XOSC Supervisor FXOSC < FIRC / n
OLR_evt
FXOSC ON/OFF From MC_ME CMU_HFREFR
FMPLL
FMPLL > hfref OR FMPLL < lfref
FHH_FLL_OR_evt_a FMPLL ON/OFF From MC_ME
CMU_LFREFR
FMPLL Supervisor
OLR_evt : It is the event signalling XOSC failure when asserted. When this signal is asserted, RGM may generate reset, interrupt or SAFE request based on the RGM configuration. FHH_FLL_OR_evt_a : It is the event signalling FMPLL failure when asserted. Based on the CMU_HFREFR and CMU_LFREFR configuration, if the FMPLL is greater than hign frequency range or less than the low frequency range configuration, this signal is generated. When this signal is asserted, RGM may generate reset, interrupt or SAFE request based on the RGM configuration.
Figure 4-11. Clock Monitor Unit diagram
4.7.4
Functional description
The clock and frequency names referenced in this block are defined as follows: • FXOSC_clk: clock coming from the fast external crystal oscillator
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Chapter 4 Clock description
• • • • • • •
SIRC_clk: clock coming from the slow (low frequency) internal RC oscillator FIRC_clk: clock coming from the fast (high frequency) internal RC oscillator FMPLL_clk: clock coming from the FMPLL fFXOSC_clk: frequency of fast external crystal oscillator clock fSIRC_clk: frequency of slow (low frequency) internal RC oscillator fFIRC_clk: frequency of fast (high frequency) internal RC oscillator fFMPLL_clk: frequency of FMPLL clock
4.7.4.1
Crystal clock monitor
If fFXOSC_clk is less than fFIRC_clk divided by 2RCDIV bits of the CMU_CSR and the FXOSC_clk is ‘ON’ as signalled by the MC_ME then: • An event pending bit OLRI in CMU_ISR is set. • A failure event OLR is signalled to the MC_RGM which in turn can automatically switch to a safe fallback clock and generate an interrupt or reset.
4.7.4.2
FMPLL clock monitor
The fFMPLL_clk can be monitored by programming bit CME of the CMU_CSR register to ‘1’. The FMPLL_clk monitor starts as soon as bit CME is set. This monitor can be disabled at any time by writing bit CME to ‘0’. If fFMPLL_clk is greater than a reference value determined by bits HFREF[11:0] of the CMU_HFREFR and the FMPLL_clk is ‘ON’, as signalled by the MC_ME, then: • An event pending bit FHHI in CMU_ISR is set. • A failure event is signalled to the MC_RGM which in turn can generate an interrupt or safe mode request or functional reset depending on the programming model. If fFMPLL_clk is less than a reference value determined by bits LFREF[11:0] of the CMU_LFREFR and the FMPLL_clk is ‘ON’, as signaled by the MC_ME, then: • An event pending bit FLLI in CMU_ISR is set. • A failure event FLL is signalled to the MC_RGM which in turn can generate an interrupt or safe mode request or functional reset depending on the programming model. NOTE The internal RC oscillator is used as reliable reference clock for the clock supervision. In order to avoid false events, proper programming of the dividers is required. These have to take into account the accuracy and frequency deviation of the internal RC oscillator. NOTE If PLL frequency goes out of range, the CMU shall generate FMPLL fll/fhh event. It takes approximately 5 us to generate this event.
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Chapter 4 Clock description
4.7.4.3
Frequency meter
The purpose of the frequency meter is twofold: • to measure the frequency of the oscillators SIRC or FIRC • to calibrate an internal RC oscillator (SIRC or FIRC) using a known frequency Hint: This value can then be stored into the flash so that application software can reuse it later on. The reference clock is always the FXOSC_clk. The frequency meter returns a precise value of frequencies fFIRC_clk or fSIRC_clk according to CKSEL1 bit value. The measure starts when bit SFM (Start Frequency Measure) in the CMU_CSR is set to ‘1’. The measurement duration is given by the CMU_MDR in numbers of clock cycles of the selected clock source with a width of 20 bits. Bit SFM is reset to ‘0’ by hardware once the frequency measurement is done and the count is loaded in the CMU_FDR. The frequency fx1 can be derived from the value loaded in the CMU_FDR as follows:
fx = (fFXOSC × MD) / n Eqn. 4-1
where n is the value in the CMU_FDR and MD is the value in the CMU_MDR. The frequency meter by default evaluates fFIRC_clk, but software can swap to fSIRC_clk or fSXOSC_clk by programming the CKSEL bits in the CMU_CSR.
4.7.5
Memory map and register description
Table 4-13. CMU memory map
The memory map of the CMU is shown in Table 4-13.
Base address: 0xC3FE_0100
Register name Address offset Reset value Location
Control Status Register (CMU_CSR) Frequency Display Register (CMU_FDR) High Frequency Reference Register FMPLL (CMU_HFREFR) Low Frequency Reference Register FMPLL (CMU_LFREFR) Interrupt Status Register (CMU_ISR) Reserved Measurement Duration Register (CMU_MDR)
0x00 0x04 0x08 0x0C 0x10 0x14 0x18
0x00000006 0x00000000
on page 105 on page 106
0x00000FFF on page 106 0x00000000 0x00000000 0x00000000 0x00000000 on page 107 on page 107 — on page 108
1. x = FIRC or SIRC MPC5602D Microcontroller Reference Manual, Rev. 3.1 104 Preliminary Freescale Semiconductor
Chapter 4 Clock description
4.7.5.1
Control Status Register (CMU_CSR)
Reset value: 0x00000006 3 4 5 6 7 8 SFM rs 9 10 11 12 Reserved — 13 14 15
Address offset: 0x00 0 1 2
Reserved —
16
17
18
19
20
21
22
23
24
25
26 Reserved
27
28
29
30
31 CME_A rw 105
Reserved
CKSEL1[1:0]
RCDIV[1:0]
—
rw
—
rw
Figure 4-12. Control Status Register (CMU_CSR) Table 4-14. Control Status Register (CMU_CSR) field descriptions
Field 8 SFM Description Start frequency measure The software can only set this bit to start a clock frequency measure. It is reset by hardware when the measure is ready in the CMU_FDR register. 0: Frequency measurement completed or not yet started 1: Frequency measurement not completed
22-23 Clock oscillator selection bit CKSEL1[1:0] CKSEL1 selects the clock to be measured by the frequency meter. 00: FIRC_clk selected 01: SIRC_clk selected 10: reserved 11: FIRC_clk selected 29-30 RCDIV[1:0] RC clock division factor These bits specify the RC clock division factor. The output clock is FIRC_clk divided by the factor 2RCDIV. This output clock is used to compare with FXOSC_clk for crystal clock monitor feature.The clock division coding is as follows. 00: Clock divided by 1 (No division) 01: Clock divided by 2 10: Clock divided by 4 11: Clock divided by 8 FMPLL_0 clock monitor enable 0: FMPLL_0 monitor disabled 1: FMPLL_0 monitor enabled
31 CME_A
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary
Chapter 4 Clock description
4.7.5.2
.
Frequency Display Register (CMU_FDR)
Reset value: 0x00000000 3 4 5 6 7 8 9 10 11 12 13 14 15
Address offset: 0x04 0 1 2
Reserved —
FD[19:16] r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FD[15:0] r
Figure 4-13. Frequency Display Register (CMU_FDR) Table 4-15. Frequency Display Register (CMU_FDR) field descriptions
Field 12-31 FD[19:0] Description Measured frequency bits This register displays the measured frequency fx with respect to fFXOSC. The measured value is given by the following formula: fx = (fFXOSC × MD) / n, where n is the value in CMU_FDR register. Note: x = FIRC or SIRC
4.7.5.3
High Frequency Reference Register FMPLL (CMU_HFREFR)
Reset value: 0x00000FFF 3 4 5 6 7 8 9 10 11 12 13 14 15
Address offset: 0x08 0 1 2
Reserved —
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved —
HFREF[11:0] rw
Figure 4-14. High Frequency Reference Register FMPLL Table 4-16. High Frequency Reference Register FMPLL field descriptions
Field Description
20-31 High Frequency reference value HFREF[11:0] These bits determine the high reference value for the FMPLL clock. The reference value is given by: (HFREF[11:0]/16) × (fFIRC/4).
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Chapter 4 Clock description
4.7.5.4
Low Frequency Reference Register FMPLL (CMU_LFREFR)
Reset value: 0x00000000 3 4 5 6 7 8 9 10 11 12 13 14 15
Address offset: 0x0C 0 1 2
Reserved —
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved —
LFREF[11:0] rw
Figure 4-15. Low Frequency Reference Register FMPLL Table 4-17. Low Frequency Reference Register FMPLL field descriptions
Field Description
20-31 Low Frequency reference value LFREF[11:0 These bits determine the low reference value for the FMPLL. The reference value is given by: ] (LFREF[11:0]/16) × (fFIRC/4).
4.7.5.5
Interrupt Status Register (CMU_ISR)
Reset value: 0x00000000 3 4 5 6 7 8 9 10 11 12 13 14 15
Address offset: 0x10 0 1 2
Reserved —
16
17
18
19
20
21
22 Reserved —
23
24
25
26
27
28
29 FHHI rc
30 FLLI rc
31 OLRI rc
Figure 4-16. Interrupt Status Register (CMU_ISR) Table 4-18. Interrupt Status Register (CMU_ISR) field descriptions
Field 29 FHHI Description FMPLL clock frequency higher than high reference interrupt This bit is set by hardware when fFMPLL_clk becomes higher than HFREF value and FMPLL_clk is ‘ON’ as signalled by the MC_ME. It can be cleared by software by writing ‘1’. 0: No FHH event 1: FHH event is pending
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Chapter 4 Clock description
Table 4-18. Interrupt Status Register (CMU_ISR) field descriptions (continued)
30 FLLI FMPLL clock frequency lower than low reference event This bit is set by hardware when fFMPLL_clk becomes lower than LFREF value and FMPLL_clk is ‘ON’ as signalled by the MC_ME. It can be cleared by software by writing ‘1’. 0: No FLL event 1: FLL event is pending Oscillator frequency lower than RC frequency event This bit is set by hardware when fFXOSC_clk is lower than FIRC_clk/2RCDIV frequency and FXOSC_clk is ‘ON’ as signalled by the MC_ME. It can be cleared by software by writing ‘1’. 0: No OLR event 1: OLR event is pending
31 OLRI
4.7.5.6
Measurement Duration Register (CMU_MDR)
Reset value: 0x00000000 3 4 5 6 7 8 9 10 11 12 13 14 15
Address offset: 0x18 0 1 2
Reserved —
MD[19:16] rw
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MD[15:0] rw
Figure 4-17. Measurement Duration Register (CMU_MDR) Table 4-19. Measurement Duration Register (CMU_MDR) field descriptions
Field 12-31 MD[19:0] Description Measurement duration bits This register displays the measurement duration in numbers of clock cycles of the selected clock source. This value is loaded in the frequency meter downcounter. When SFM bit in CMU_CSR is set to ‘1’, downcounter starts counting.
4.7.6
Address offset 00
Register map
Table 4-20. CMU register map
Register name CMU_CSR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CKSEL1 [1:0] Reserved Reserved RCDIV [1:0]
04 08 0C
CMU_FDR CMU_HFREFR CMU_LFREFR
Reserved Reserved Reserved
FD[19:0] HFREF[11:0] LFREF[11:0]
MPC5602D Microcontroller Reference Manual, Rev. 3.1 108 Preliminary Freescale Semiconductor
CME
SFM
Reserved
Chapter 4 Clock description
Table 4-20. CMU register map
Address offset 10 Register name CMU_ISR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FHHI_A MD[19:0] OLRI Reserved FLLI_A
14 18
Reserved CMU_MDR Reserved
Reserved
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Chapter 4 Clock description
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Chapter 5 Clock Generation Module (MC_CGM)
Chapter 5 Clock Generation Module (MC_CGM)
5.1 Introduction
This document serves as the block guide for the Clock Generation Module (MC_CGM) which includes, but is not limited to, the funtionality, pin description, and registers of the MC_CGM module.
5.1.1
Overview
The clock generation module (MC_CGM) generates reference clocks for all the SoC blocks. The MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the system clock selection (see the MC_ME chapter for more details). A set of MC_CGM registers controls the clock dividers which are used for divided system and peripheral clock generation. The memory spaces of system and peripheral clock sources which have addressable memory spaces are accessed through the MC_CGM memory space. The MC_CGM also selects and generates an output clock. Figure 5-1 depicts the MC_CGM Block Diagram.
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Chapter 5 Clock Generation Module (MC_CGM)
FIRC
MC_CGM
MC_ME
FXOSC
Registers Platform Interface MC_RGM
FMPLL
System Clock Multiplexer/Divider
peripherals
PA[0]
core Output Clock Selector/Divider
Mapped Modules Interface
mapped peripherals
Figure 5-1. MC_CGMBlock Diagram
5.1.2
Features
The MC_CGM includes the following features: • generates system and peripheral clocks • selects and enables/disables the system clock supply from system clock sources according to MC_ME control
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Chapter 5 Clock Generation Module (MC_CGM)
• • • • •
contains a set of registers to control clock dividers for divided clock generation supports multiple clock sources and maps their address spaces to its memory map generates an output clock guarantees glitch-less clock transitions when changing the system clock selection supports 8, 16 and 32-bit wide read/write accesses
5.2
External Signal Description
The MC_CGM delivers an output clock to the PA[0] pin for off-chip use and/or observation.
5.3
Memory Map and Register Definition
Table 5-1. MC_CGM Register Description
Access Address Name Description Size User 0xC3FE CGM_OC_EN _0370 0xC3FE CGM_OCDS_SC _0374 0xC3FE CGM_SC_SS _0378 0xC3FE CGM_SC_DC0 _037C 0xC3FE CGM_SC_DC1 _037D 0xC3FE CGM_SC_DC2 _037E Output Clock Enable Output Clock Division Select System Clock Select Status System Clock Divider Configuration 0 System Clock Divider Configuration 1 System Clock Divider Configuration 2 word byte byte byte byte byte read read read read read read Supervisor read/write read/write read read/write read/write read/write Test read/write on page 118 read/write on page 118 read on page 119 Location
read/write on page 120 read/write on page 120 read/write on page 120
NOTE Any access to unused registers as well as write accesses to read-only registers will: • • not change register content cause a transfer error
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 113
Chapter 5 Clock Generation Module (MC_CGM)
Table 5-2. MC_CGM Memory Map
Address 0xC3FE _0000 … 0xC3FE _001C 0xC3FE _0020 … 0xC3FE _003C 0xC3FE _0040 … 0xC3FE _005C 0xC3FE _0060 … 0xC3FE _007C 0xC3FE _0080 … 0xC3FE _009C 0xC3FE _00A0 … 0xC3FE _00BC 0xC3FE _00C0 … 0xC3FE _00DC 0xC3FE _00E0 … 0xC3FE _00FC 0xC3FE _0100 … 0xC3FE _011C Name
0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
FXOSC registers
reserved
SXOSC registers
FIRC registers
SIRC registers
FMPLL registers
reserved
reserved
CMU registers
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Chapter 5 Clock Generation Module (MC_CGM)
Table 5-2. MC_CGM Memory Map (continued)
Address 0xC3FE _0120 … 0xC3FE _013C 0xC3FE _0140 … 0xC3FE _015C 0xC3FE _0160 … 0xC3FE _017C 0xC3FE _0180 … 0xC3FE _019C 0xC3FE _01A0 … 0xC3FE _01BC 0xC3FE _01C0 … 0xC3FE _01DC 0xC3FE _01E0 … 0xC3FE _01FC 0xC3FE _0200 … 0xC3FE _021C 0xC3FE _0220 … 0xC3FE _023C Name
0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
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Chapter 5 Clock Generation Module (MC_CGM)
Table 5-2. MC_CGM Memory Map (continued)
Address 0xC3FE _0240 … 0xC3FE _025C 0xC3FE _0260 … 0xC3FD _C27C 0xC3FE _0280 … 0xC3FE _029C 0xC3FE _02A0 … 0xC3FE _02BC 0xC3FE _02C0 … 0xC3FE _02DC 0xC3FE _02E0 … 0xC3FE _02FC 0xC3FE _0300 … 0xC3FE _031C 0xC3FE _0320 … 0xC3FE _033C 0xC3FE _0340 … 0xC3FE _035C Name
0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
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Chapter 5 Clock Generation Module (MC_CGM)
Table 5-2. MC_CGM Memory Map (continued)
Address 0xC3FE _0360 … 0xC3FE _036C 0xC3FE CGM_OC_EN R _0370 W R W 0xC3FE CGM_OCDS_ R _0374 SC W R W 0xC3FE CGM_SC_SS _0378 R W R W 0xC3FE CGM_SC_DC R _037C 0…2 W R W 0xC3FE _0380 … 0xC3FE _3FFC DE0 DIV0 0 0 0 DIV2 DE1 0 0 0 0 0 0 DIV1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELSTAT 0 0 0 0 0 0 0 0 0 0 SELDIV 0 0 0 0 0 SELCTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name
0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 EN
DE2
0
reserved
5.3.1
Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address 0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373.
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Chapter 5 Clock Generation Module (MC_CGM)
5.3.1.1
Output Clock Enable Register (CGM_OC_EN)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
Address 0xC3FE_0370 R W Reset 0
16
0
0 0
17
0 0
18
0 0
19
0 0
20
0 0
21
0 0
22
0 0
23
0 0
24
0 0
25
0 0
26
0 0
27
0 0
28
0 0
29
0 0
30
0 0
31
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
EN 0
Figure 5-2. Output Clock Enable Register (CGM_OC_EN)
This register is used to enable and disable the output clock.
Table 5-3. Output Clock Enable Register (CGM_OC_EN) Field Descriptions
Field EN Output Clock Enable control 0 Output Clock is disabled 1 Output Clock is enabled Description
5.3.1.2
Output Clock Division Select Register (CGM_OCDS_SC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
Address 0xC3FE_0374 R W Reset 0
16
0
0 0
17
SELDIV 0
18
SELCTL 0
20
0 0
23
0 0
25
0 0
26
0 0
27
0 0
28
0 0
29
0 0
30
0 0
31
0
19
0
21
0
22
0
24
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Figure 5-3. Output Clock Division Select Register (CGM_OCDS_SC)
This register is used to select the current output clock source and by which factor it is divided before being delivered at the output clock.
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Chapter 5 Clock Generation Module (MC_CGM)
Table 5-4. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions
Field Description
SELDIV Output Clock Division Select 00 output selected Output Clock without division 01 output selected Output Clock divided by 2 10 output selected Output Clock divided by 4 11 output selected Output Clock divided by 8 SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock. 0000 4-16 MHz ext. xtal osc. 0001 16 MHz int. RC osc. 0010 freq. mod. PLL 0011 system clock 0100 RTC clock 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
5.3.1.3
System Clock Select Status Register (CGM_SC_SS)
Access: User read, Supervisor read, Test read
3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2
Address 0xC3FE_0378 R W Reset 0
16
0
0 0
17
0 0
18
0 0
19
SELSTAT 0
20
0 0
23
0 0
25
0 0
26
0 0
27
0 0
28
0 0
29
0 0
30
0 0
31
0
21
0
22
0
24
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Figure 5-4. System Clock Select Status Register (CGM_SC_SS)
This register provides the current system clock source selection.
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Chapter 5 Clock Generation Module (MC_CGM)
Table 5-5. System Clock Select Status Register (CGM_SC_SS) Field Descriptions
Field SELSTAT Description System Clock Source Selection Status — This value indicates the current source for the system clock. 0000 16 MHz int. RC osc. 0001 div. 16 MHz int. RC osc. 0010 4-16 MHz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled
5.3.1.4
System Clock Divider Configuration Registers (CGM_SC_DC0…2)
Access: User read, Supervisor read/write, Test read/write
28 3 27 4 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 18 13 17 14 16 15
Address 0xC3FE_037C
31 0 30 1 29 2
R W Reset
DE0 1
15 16
0 0
14 17
0 0
13 18
0 0
12 19
DIV0 0
11 20
DE1 0
9
0 0
6 25
0 0
5 26
0 0
4 27
DIV1 0
3 28
0
10 21
0
8 23
1
7 24
0
2 29
0
1 30
0
0 31
22
R W Reset
DE2 1
0 0
0 0
0 0 0 0
DIV2 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Figure 5-5. System Clock Divider Configuration Registers (CGM_SC_DC0…2)
These registers control the system clock dividers.
Table 5-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions
Field DE0 Divider 0 Enable 0 Disable system clock divider 0 1 Enable system clock divider 0 Divider 0 Division Value — The resultant peripheral set 1 clock will have a period DIV0 + 1 times that of the system clock. If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is ignored and the peripheral set 1 clock remains disabled. Description
DIV0
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Chapter 5 Clock Generation Module (MC_CGM)
Table 5-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions (continued)
Field DE1 Divider 1 Enable 0 Disable system clock divider 1 1 Enable system clock divider 1 Divider 1 Division Value — The resultant peripheral set 2 clock will have a period DIV1 + 1 times that of the system clock. If the DE1 is set to ‘0’ (Divider 1 is disabled), any write access to the DIV1 field is ignored and the peripheral set 2 clock remains disabled. Divider 2 Enable 0 Disable system clock divider 2 1 Enable system clock divider 2 Divider 2 Division Value — The resultant peripheral set 3 clock will have a period DIV2 + 1 times that of the system clock. If the DE2 is set to ‘0’ (Divider 2 is disabled), any write access to the DIV2 field is ignored and the peripheral set 3 clock remains disabled. Description
DIV1
DE2
DIV2
5.4
5.4.1
Functional Description
System Clock Generation
Figure 5-6 shows the block diagram of the system clock generation logic. The MC_ME provides the system clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides the safe clock request (see MC_RGM chapter for more details). The safe clock request forces the selector to select the 16 MHz int. RC osc. as the system clock and to ignore the system clock select.
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Chapter 5 Clock Generation Module (MC_CGM)
16 MHz int. RC osc. div. 16 MHz int. RC osc. 4-16 MHz ext. xtal osc. div. ext. xtal osc. freq. mod. PLL
0 1 2 3 4
system clock is disabled if ME__MC.SYSCLK = “1111”
’0’ system clock
CGM_SC_DC0 Register
MC_RGM SAFE mode request “0000” ME_ _MC.SYSCLK 1 0
clock divider
peripheral set 1 clock
CGM_SC_DC1 Register
CGM_SC_SS Register clock divider peripheral set 2 clock
CGM_SC_DC2 Register
clock divider
peripheral set 3 clock
Figure 5-6. MC_CGM System Clock Generation Overview
5.4.1.1
System Clock Source Selection
During normal operation, the system clock selection is controlled • on a SAFE mode or reset event, by the MC_RGM • otherwise, by the MC_ME
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Chapter 5 Clock Generation Module (MC_CGM)
5.4.1.2
System Clock Disable
During the STOP0 and TEST modes, the system clock can be disabled by the MC_ME.
5.4.1.3
• • •
System Clock Dividers
The MC_CGM generates the following derived clocks from the system clock: peripheral set 1 clock - controlled by the CGM_SC_DC0 register peripheral set 2 clock - controlled by the CGM_SC_DC1 register peripheral set 3 clock - controlled by the CGM_SC_DC2 register
5.4.2
Dividers Functional Description
Dividers are used for the generation of divided system and peripheral clocks. The MC_CGM has the following control registers for built-in dividers: • Section 5.3.1.4, “System Clock Divider Configuration Registers (CGM_SC_DC0…2) The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set to ‘0’ (the divider is disabled), any value in its DIVn field is ignored.
5.4.3
Output Clock Multiplexing
The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as output clock sources. The selection is done via the CGM_OCDS_SC register.
5.4.4
Output Clock Division Selection
4-16 MHz ext. xtal osc. 16 MHz int. RC osc. freq. mod. PLL system clock RTC clock 0 1 2 3 4
CGM_OC_EN Register
3 2 1 0 ’0’ PA[0]
CGM_OCDS_SC.SELCTL Register
CGM_OCDS_SC.SELDIV Register
Figure 5-7. MC_CGM Output Clock Multiplexer and PA[0] Generation
The MC_CGM provides the following output signals for the output clock generation:
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 123
Chapter 5 Clock Generation Module (MC_CGM)
•
PA[0] (see Figure 5-7). This signal is generated by using one of the 3-stage ripple counter outputs or the selected signal without division. The non-divided signal is not guaranteed to be 50% duty cycle by the MC_CGM.
the MC_CGM also has an output clock enable register (see Section 5.3.1.1, “Output Clock Enable Register (CGM_OC_EN)) which contains the output clock enable/disable control bit.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 124 Preliminary Freescale Semiconductor
Chapter 6 Mode Entry Module (MC_ME)
Chapter 6 Mode Entry Module (MC_ME)
6.1
6.1.1
Introduction
Overview
The MC_ME controls the SoC mode and mode transition sequences in all functional states. It also contains configuration, control and status registers accessible for the application. Figure 6-1 depicts the MC_ME Block Diagram.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 125
Chapter 6 Mode Entry Module (MC_ME)
VREG
MC_ME
MC_PCU
Flashes
Registers Platform Interface MC_RGM
FIRC
FXOSC
MC_CGM
FMPLL
core Device Mode State Machine peripherals
WKPU
Figure 6-1. MC_ME Block Diagram
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Chapter 6 Mode Entry Module (MC_ME)
6.1.2
Features
The MC_ME includes the following features: • control of the available modes by the ME_ME register • definition of various device mode configurations by the ME__MC registers • control of the actual device mode by the ME_MCTL register • capture of the current mode and various resource status within the contents of the ME_GS register • optional generation of various mode transition interrupts • status bits for each cause of invalid mode transitions • peripheral clock gating control based on the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers • capture of current peripheral clock gated/enabled status
6.1.3
Modes of Operation
The MC_ME is based on several device modes corresponding to different usage models of the device. Each mode is configurable and can define a policy for energy and processing power management to fit particular system requirements. An application can easily switch from one mode to another depending on the current needs of the system. The operating modes controlled by the MC_ME are divided into system and user modes. The system modes are modes such as RESET, DRUN, SAFE, and TEST. These modes aim to ease the configuration and monitoring of the system. The user modes are modes such as RUN0…3, HALT0, STOP0, and STANDBY0 which can be configured to meet the application requirements in terms of energy management and available processing power. The modes DRUN, SAFE, TEST, and RUN0…3 are the device software running modes. Table 6-1 describes the MC_ME modes.
Table 6-1. MC_ME Mode Descriptions Name
RESET
Description
This is a chip-wide virtual mode during which the application is not active. The system remains in this mode until all resources are available for the embedded software to take control of the device. It manages hardware initialization of chip configuration, voltage regulators, clock sources, and flash modules. This is the entry mode for the embedded software. It provides full accessibility to the system and enables the configuration of the system at startup. It provides the unique gate to enter user modes. BAM when present is executed in DRUN mode.
Entry
system reset assertion from MC_RGM
Exit
system reset deassertion from MC_RGM
DRUN
system reset deassertion from MC_RGM, software request from SAFE, TEST and RUN0…3, wakeup request from STANDBY0
system reset assertion, RUN0…3, TEST, STANDBY0 via software, SAFE via software or hardware failure.
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Chapter 6 Mode Entry Module (MC_ME)
Table 6-1. MC_ME Mode Descriptions (continued) Name
SAFE
Description
This is a chip-wide service mode which may be entered on the detection of a recoverable error. It forces the system into a pre-defined safe configuration from which the system may try to recover. This is a chip-wide service mode which is intended to provide a control environment for device software teting. These are software running modes where most processing activity is done. These various run modes allow to enable different clock & power configurations of the system with respect to each other.
Entry
Exit
hardware failure, system reset software request assertion, DRUN from DRUN, TEST, via software and RUN0…3 software request from DRUN software request from DRUN or other RUN0…3, interrupt event from HALT0, interrupt or wakeup event from STOP0 system reset assertion, DRUN via software system reset assertion, SAFE via software or hardware failure, other RUN0…3 modes, HALT0, STOP0, STANDBY0 via software system reset assertion, SAFE on hardware failure, RUN0…3 on interrupt event system reset assertion, SAFE on hardware failure, RUN0…3 on interrupt event or wakeup event system reset assertion, DRUN on wakeup event
TEST
RUN0…3
HALT0
This is a reduced-activity low-power mode during which the software request clock to the core is disabled. It can be configured to switch from RUN0…3 off analog peripherals like clock sources, flash, main regulator, etc. for efficient power management at the cost of higher wakeup latency. This is an advanced low-power mode during which the software request clock to the core is disabled. It may be configured to switch from RUN0…3 off most of the peripherals including clock sources for efficient power management at the cost of higher wakeup latency. software request from RUN0…3, DRUN modes
STOP0
STANDBY0 This is a reduced-leakage low-power mode during which power supply is cut off from most of the device. Wakeup from this mode takes a relatively long time, and content is lost or must be restored from backup.
6.2
External Signal Description
The MC_ME has no connections to any external pins.
6.3
Memory Map and Register Definition
The MC_ME contains registers for: • mode selection and status reporting • mode configuration • mode transition interrupts status and mask control • scalable number of peripheral sub-mode selection and status reporting
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Chapter 6 Mode Entry Module (MC_ME)
6.3.1
Memory Map
Table 6-2. MC_ME Register Description
Access
Address
Name
Description
Size User Supervisor read read/write read/write read/write read/write read/write read read read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read read read read Test read
Location
0xC3FD_C000 ME_GS 0xC3FD_C004 ME_MCTL 0xC3FD_C008 ME_ME 0xC3FD_C00C ME_IS 0xC3FD_C010 ME_IM 0xC3FD_C014 ME_IMTS 0xC3FD_C018 ME_DMTS 0xC3FD_C020 ME_RESET_MC 0xC3FD_C024 ME_TEST_MC 0xC3FD_C028 ME_SAFE_MC 0xC3FD_C02C ME_DRUN_MC 0xC3FD_C030 ME_RUN0_MC 0xC3FD_C034 ME_RUN1_MC 0xC3FD_C038 ME_RUN2_MC 0xC3FD_C03C ME_RUN3_MC 0xC3FD_C040 ME_HALT0_MC 0xC3FD_C048 ME_STOP0_MC
Global Status Mode Control Mode Enable Interrupt Status Interrupt Mask Invalid Mode Transition Status Debug Mode Transition Status RESET Mode Configuration TEST Mode Configuration SAFE Mode Configuration DRUN Mode Configuration RUN0 Mode Configuration RUN1 Mode Configuration RUN2 Mode Configuration RUN3 Mode Configuration HALT0 Mode Configuration STOP0 Mode Configuration
word word word word word word word word word word word word word word word word word word word word word word
read read read read read read read read read read read read read read read read read read read read read read
on page 137
read/write on page 139 read/write on page 140 read/write on page 142 read/write on page 143 read/write on page 144 read read on page 145 on page 148
read/write on page 148 read/write on page 149 read/write on page 149 read/write on page 150 read/write on page 150 read/write on page 150 read/write on page 150 read/write on page 151 read/write on page 151 read/write on page 152 read read read read on page 154 on page 154 on page 155 on page 155
0xC3FD_C054 ME_STANDBY0_MC STANDBY0 Mode Configuration 0xC3FD_C060 ME_PS0 0xC3FD_C064 ME_PS1 0xC3FD_C068 ME_PS2 0xC3FD_C06C ME_PS3 Peripheral Status 0 Peripheral Status 1 Peripheral Status 2 Peripheral Status 3
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 129
Chapter 6 Mode Entry Module (MC_ME)
Table 6-2. MC_ME Register Description (continued)
Access Address Name Description Size User 0xC3FD_C080 ME_RUN_PC0 0xC3FD_C084 ME_RUN_PC1 Run Peripheral Configuration 0 Run Peripheral Configuration 1 word word read read Supervisor read/write read/write Test read/write on page 156 read/write on page 156 Location
…
0xC3FD_C09C ME_RUN_PC7 0xC3FD_C0A0 ME_LP_PC0 0xC3FD_C0A4 ME_LP_PC1 Run Peripheral Configuration 7 Low-Power Peripheral Configuration 0 Low-Power Peripheral Configuration 1 word word word read read read read/write read/write read/write read/write on page 156 read/write on page 157 read/write on page 157
…
0xC3FD_C0BC ME_LP_PC7 0xC3FD_C0C4 ME_PCTL4 0xC3FD_C0C5 ME_PCTL5 0xC3FD_C0D0 ME_PCTL16 0xC3FD_C0D7 ME_PCTL23 0xC3FD_C0E1 ME_PCTL33 0xC3FD_C0F0 ME_PCTL48 0xC3FD_C0F1 ME_PCTL49 0xC3FD_C0F2 ME_PCTL50 0xC3FD_C0F9 ME_PCTL57 0xC3FD_C104 ME_PCTL68 0xC3FD_C105 ME_PCTL69 0xC3FD_C108 ME_PCTL72 0xC3FD_C11B ME_PCTL91 0xC3FD_C11C ME_PCTL92 0xC3FD_C128 ME_PCTL104 Low-Power Peripheral Configuration 7 DSPI0 Control DSPI1 Control FlexCAN0 Control DMA_CH_MUX Control ADC1 Control LINFlex0 Control LINFlex1 Control LINFlex2 Control CTUL Control SIUL Control WKPU Control eMIOS0 Control RTC_API Control PIT_RTI Control CMU Control word byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte read read read read read read read read read read read read read read read read read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write on page 157 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158 read/write on page 158
NOTE Any access to unused registers as well as write accesses to read-only registers will: • not change register content
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Chapter 6 Mode Entry Module (MC_ME)
•
cause a transfer error
Table 6-3. MC_ME Memory Map
Address
Name
0 16
1 17
2 18
3 19
27 20
5 21
6 22
7 23
8 24
9 25
10 26
11 27
12 28
13 29
14 30
15 31
R S_CURRENT_MODE
0
0
0
0
S_MVR
S_PDO
S_DC
0xC3FD ME_GS _C000
S_MTRANS
S_DFLA
S_CFLA
W S_FXOSC S_FMPLL S_FIRC
R
S_SYSCLK
W 0xC3FD ME_MCTL _C004 R TARGET_MODE W R W 0xC3FD ME_ME _C008 R W STANDBY0 STOP0 RUN3 RUN2 RUN1 TEST 0 I_SAFE 0 M_SAFE R W 0xC3FD ME_IS _C00C R W I_IMODE I_ICONF R W 0xC3FD ME_IM _C010 R W M_MTC 131 Preliminary R W 0 0 0 0 0 0 0 0 0 0 0 0 M_IMODE M_ICONF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I_MTC 0 0 0 0 0 0 0 0 HALT0 RESET 0 DRUN RUN0 SAFE 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 KEY 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
w1c w1c w1c w1c 0 0
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor
Chapter 6 Mode Entry Module (MC_ME)
Table 6-3. MC_ME Memory Map (continued)
Address Name R W S_DMA S_NMA 0 CDP_PRPH_32_63 R W 0xC3FD ME_DMTS _C018 R PREVIOUS_MODE 0 0 0 0 MPH_BUSY 0 0 0 0 0 0 0 0 0 0 0 S_SEA CDP_PRPH_0_31 SMR S_MRI S_MTI
0 16 1 17 2 18 3 19 27 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
0xC3FD ME_IMTS _C014
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
w1c w1c w1c w1c w1c PMC_PROG CORE_DBG CDP_PRPH_96_127 MVRON
0
0
0
W CDP_PRPH_0_143 CDP_PRPH_64_95 CSRC_CSRC_SC VREG_CSRC_SC
SYSCLK_SW
DFLASH_SC
R
0
CFLASH_SC
SCSRC_SC
FIRC_SC
0
0
W 0xC3FD _C01C 0xC3FD ME_RESET_ _C020 MC R W FXOSCON FMPLLON FIRCON 0 0 0 0 0 reserved PDO
0
0
0
0
0
DFLAON
CFLAON
R
SYSCLK
W 0xC3FD ME_TEST_M _C024 C R W FIRCON R W 0 0 0 0 0 0 0 0 0 FXOSCON FMPLLON 0 0 0 0 0 0 0 0 0 0 MVRON
PDO
DFLAON
CFLAON
SYSCLK
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Chapter 6 Mode Entry Module (MC_ME)
Table 6-3. MC_ME Memory Map (continued)
Address Name
0 16 1 17 2 18 3 19 27 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
W FXOSCON FMPLLON FIRCON
R
PDO
0xC3FD ME_SAFE_M _C028 C
R
0
0
0
0
0
0
0
0
0
0
MVRON
DFLAON
CFLAON
SYSCLK
W 0 0 0 0 0 0 0 0 PDO 0xC3FD ME_DRUN_M _C02C C R W R W 0xC3FD ME_RUN0…3 _C030 _MC R … 0xC3FD W _C03C R W 0xC3FD ME_HALT0_ _C040 MC PDO R W R W 0xC3FD _C044 0 0 0 0 0 0 0 0 0 FXOSCON FMPLLON 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO 0 0 0 0 0 0 0 0 0 FXOSCON FMPLLON FIRCON 0 0 MVRON
DFLAON
CFLAON
SYSCLK
0
0
MVRON
DFLAON
CFLAON
0
0
0
0
0
0
0
0
0
FXOSCON
FMPLLON
FIRCON
SYSCLK
0
0
MVRON
DFLAON
CFLAON
FIRCON
SYSCLK
reserved
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Chapter 6 Mode Entry Module (MC_ME)
Table 6-3. MC_ME Memory Map (continued)
Address Name R W
0 16 1 17 2 18 3 19 27 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
PDO
0xC3FD ME_STOP0_ _C048 MC
0
0
0
0
0
0
0
0
0
0
MVRON
DFLAON
CFLAON
FXOSCON
FMPLLON
R
0
0
0
0
0
0
0
0
0
FIRCON
SYSCLK
W 0xC3FD _C04C … 0xC3FD _C050 0xC3FD ME_STANDB _C054 Y0_MC R W FXOSCON FMPLLON FIRCON 0 0 0 0 0
reserved
0
0
0
0
0
MVRON
PDO
DFLAON
CFLAON
R
SYSCLK
W 0xC3FD _C058 … 0xC3FD _C05C 0xC3FD ME_PS0 _C060 R
reserved
S_DMA_CH_MUX
W S_DSPI1 R W S_DSPI0
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S_FlexCAN0
Chapter 6 Mode Entry Module (MC_ME)
Table 6-3. MC_ME Memory Map (continued)
Address Name
0 16 1 17 2 18 3 19 27 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
S_LINFlex2
S_LINFlex1 S_ADC1 0 TEST
R
W R W S_PIT_RTI 0xC3FD ME_PS2 _C068 S_RTC_API
R
W S_eMIOS0 S_WKPU S_SIUL
R
W 0xC3FD ME_PS3 _C06C R W R W 0xC3FD _C070 0xC3FD _C074 … 0xC3FD _C07C 0xC3FD ME_RUN_PC R _C080 0…7 W … 0xC3FD _C09C R W 0 0 0 0 0 reserved S_CMU
reserved
0
0
S_CTUL
0xC3FD ME_PS1 _C064
0
0
0
0
0
0
0
DRUN
RUN3
RUN2
RUN1
RUN0
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 135
SAFE
0
0
0
0
0
0
0
0
RESET
S_LINFlex0 0
Chapter 6 Mode Entry Module (MC_ME)
Table 6-3. MC_ME Memory Map (continued)
Address Name R W STOP0 R W DBG_F DBG_F 0xC3FD ME_PCTL0… R _C0C0 143 W … 0xC3FD R _C14C W 0xC3FD _C150 … 0xC3FD _FFFC 0 0 0 STANDBY0 0 0 0 HALT0 0 0 0 0 0 0 0 0
0 16 1 17 2 18 3 19 27 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
0xC3FD ME_LP_PC0 _C0A0 …7 … 0xC3FD _C0BC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 LP_CFG RUN_CFG 0 LP_CFG RUN_CFG
DBG_F DBG_F
LP_CFG
RUN_CFG
0
LP_CFG
RUN_CFG
reserved
6.3.2
Register Description
Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the ME_RUN_PC0 register may be accessed as a word at address 0xC3FD_C080, as a half-word at address 0xC3FD_C082, or as a byte at address 0xC3FD_C083.
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Chapter 6 Mode Entry Module (MC_ME)
6.3.2.1
Global Status Register (ME_GS)
Access: User read, Supervisor read, Test read
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C000
0 1 2
S_CURRENT_MODE
0
0
0
0
S_MVR
S_PDO
R
S_MTRANS
S_DC
S_DFLA
S_CFLA
W Reset 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S_FIRC
R
S_FXOSC
S_FMPLL
S_SYSCLK
W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 6-2. Global Status Register (ME_GS)
This register contains global mode status.
Table 6-4. Global Status Register (ME_GS) Field Descriptions
Field S_CURREN Current device mode status T_MODE 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT0 1001 reserved 1010 STOP0 1011 reserved 1100 reserved 1101 STANDBY0 1110 reserved 1111 reserved S_MTRANS Mode transition status 0 Mode transition process is not active 1 Mode transition is ongoing S_DC Device current consumption status 0 Device consumption is low enough to allow powering down of main voltage regulator 1 Device consumption requires main voltage regulator to remain powered regardless of mode configuration Description
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Chapter 6 Mode Entry Module (MC_ME)
Table 6-4. Global Status Register (ME_GS) Field Descriptions (continued)
Field S_PDO Description Output power-down status — This bit specifies output power-down status of I/Os. This bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off. 0 No automatic safe gating of I/Os used and pads power sequence driver is enabled 1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and the pads power sequence driver is disabled. The inputs are level unchanged. In STOP0 mode, only the pad power sequence driver is disabled, but the state of the output remains functional. In STANDBY0 mode, the power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. Wakeup lines configuration remains unchanged Main voltage regulator status 0 Main voltage regulator is not ready 1 Main voltage regulator is ready for use Data flash availability status 00 Data flash is not available 01 Data flash is in power-down mode 10 Data flash is not available 11 Data flash is in normal mode and available for use Code flash availability status 00 Code flash is not available 01 Code flash is in power-down mode 10 Code flash is in low-power mode 11 Code flash is in normal mode and available for use frequency modulated phase locked loop status 0 frequency modulated phase locked loop is not stable 1 frequency modulated phase locked loop is providing a stable clock fast external crystal oscillator (4-16 MHz) status 0 fast external crystal oscillator (4-16 MHz) is not stable 1 fast external crystal oscillator (4-16 MHz) is providing a stable clock fast internal RC oscillator (16 MHz) status 0 fast internal RC oscillator (16 MHz) is not stable 1 fast internal RC oscillator (16 MHz) is providing a stable clock System clock switch status — These bits specify the system clock currently used by the system. 0000 16 MHz int. RC osc. 0001 div. 16 MHz int. RC osc. 0010 4-16 MHz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled
S_MVR
S_DFLA
S_CFLA
S_FMPLL
S_FXOSC
S_FIRC
S_SYSCLK
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Chapter 6 Mode Entry Module (MC_ME)
6.3.2.2
Mode Control Register (ME_MCTL)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C004
0 1 2
R TARGET_MODE W Reset 0 0 1 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R W Reset
1
0
1
0
0
1
0
1 KEY
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
1
Figure 6-3. Mode Control Register (ME_MCTL)
This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to ME__MC registers must respect this for successful mode requests. NOTE Byte and half-word write accesses are not allowed for this register as a predefined key is required to change its value.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 139
Chapter 6 Mode Entry Module (MC_ME)
Table 6-5. Mode Control Register (ME_MCTL) Field Descriptions
Field TARGET_M ODE Description Target device mode — These bits provide the target device mode to be entered by software programming. The mechanism to enter into any mode by software requires the write operation twice: first time with key, and second time with inverted key. These bits are automatically updated by hardware while entering SAFE on hardware request. Also, while exiting from the HALT0 and STOP0 modes on hardware exit events, these are updated with the appropriate RUN0…3 mode value. 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT0 1001 reserved 1010 STOP0 1011 reserved 1100 reserved 1101 STANDBY0 1110 reserved 1111 reserved Control key — These bits enable write access to this register. Any write access to the register with a value different from the keys is ignored. Read access will always return inverted key. KEY:0101101011110000 (0x5AF0) INVERTED KEY:1010010100001111 (0xA50F)
KEY
6.3.2.3
Mode Enable Register (ME_ME)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C008
0 1 2
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
STANDBY0
STOP0
RUN3
RUN2
RUN1
W Reset 0 0
0
0
0
0
0
0
0
0
0
1
1
1
TEST 0
0
0
0
0
0
HALT0
R
Figure 6-4. Mode Enable Register (ME_ME)
This register allows a way to disable the device modes which are not required for a given device. RESET, SAFE, DRUN, and RUN0 modes are always enabled.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 140 Preliminary Freescale Semiconductor
RESET 1
DRUN
RUN0
SAFE
Chapter 6 Mode Entry Module (MC_ME)
Table 6-6. Mode Enable Register (ME_ME) Field Descriptions
Field STANDBY0 STANDBY0 mode enable 0 STANDBY0 mode is disabled 1 STANDBY0 mode is enabled STOP0 mode enable 0 STOP0 mode is disabled 1 STOP0 mode is enabled HALT0 mode enable 0 HALT0 mode is disabled 1 HALT0 mode is enabled RUN3 mode enable 0 RUN3 mode is disabled 1 RUN3 mode is enabled RUN2 mode enable 0 RUN2 mode is disabled 1 RUN2 mode is enabled RUN1 mode enable 0 RUN1 mode is disabled 1 RUN1 mode is enabled RUN0 mode enable 0 RUN0 mode is disabled 1 RUN0 mode is enabled DRUN mode enable 0 DRUN mode is disabled 1 DRUN mode is enabled SAFE mode enable 0 SAFE mode is disabled 1 SAFE mode is enabled TEST mode enable 0 TEST mode is disabled 1 TEST mode is enabled RESET mode enable 0 RESET mode is disabled 1 RESET mode is enabled Description
STOP0
HALT0
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
RESET
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 141
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.4
Interrupt Status Register (ME_IS)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C00C
0 1 2
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
I_IMODE
I_ICONF
0 W Reset 0
0
0
0
0
0
0
0
0
0
0
0
w1c 0 0 0 0 0 0 0 0 0 0 0 0
w1c 0
w1c 0
w1c 0
Figure 6-5. Interrupt Status Register (ME_IS)
This register provides the current interrupt status.
Table 6-7. Interrupt Status Register (ME_IS) Field Descriptions
Field I_ICONF Description Invalid mode configuration interrupt — This bit is set whenever a write operation to ME__MC registers with invalid mode configuration is attempted. It is cleared by writing a ‘1’ to this bit. 0 No invalid mode configuration interrupt occurred 1 Invalid mode configuration interrupt is pending Invalid mode interrupt — This bit is set whenever an invalid mode transition is requested. It is cleared by writing a ‘1’ to this bit. 0 No invalid mode interrupt occurred 1 Invalid mode interrupt is pending SAFE mode interrupt — This bit is set whenever the device enters SAFE mode on hardware requests generated in the system. It is cleared by writing a ‘1’ to this bit. 0 No SAFE mode interrupt occurred 1 SAFE mode interrupt is pending Mode transition complete interrupt — This bit is set whenever the mode transition process completes (S_MTRANS transits from 1 to 0). It is cleared by writing a ‘1’ to this bit. This mode transition interrupt bit will not be set while entering low-power modes HALT0, STOP0, or STANDBY0. 0 No mode transition complete interrupt occurred 1 Mode transition complete interrupt is pending
I_IMODE
I_SAFE
I_MTC
MPC5602D Microcontroller Reference Manual, Rev. 3.1 142 Preliminary Freescale Semiconductor
I_MTC
R
I_SAFE
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.5
Interrupt Mask Register (ME_IM)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C010
0 1 2
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
M_IMODE
M_ICONF
W Reset 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
Figure 6-6. Interrupt Mask Register (ME_IM)
This register controls whether an event generates an interrupt or not.
Table 6-8. Interrupt Mask Register (ME_IM) Field Descriptions
Field M_ICONF Description Invalid mode configuration interrupt mask 0 Invalid mode interrupt is masked 1 Invalid mode interrupt is enabled Invalid mode interrupt mask 0 Invalid mode interrupt is masked 1 Invalid mode interrupt is enabled SAFE mode interrupt mask 0 SAFE mode interrupt is masked 1 SAFE mode interrupt is enabled Mode transition complete interrupt mask 0 Mode transition complete interrupt is masked 1 Mode transition complete interrupt is enabled
M_IMODE
M_SAFE
M_MTC
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 143
M_MTC 0
R
0
0
0
0
0
0
0
0
0
0
0
0
M_SAFE
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.6
Invalid Mode Transition Status Register (ME_IMTS)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C014
0 1 2
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S_DMA
S_NMA w1c 0
R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
w1c 0
w1c 0
w1c 0
w1c 0
Figure 6-7. Invalid Mode Transition Status Register (ME_IMTS)
This register provides the status bits for the possible causes of an invalid mode interrupt.
Table 6-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions
Field S_MTI Description Mode Transition Illegal status — This bit is set whenever a new mode is requested while some other mode transition process is active (S_MTRANS is ‘1’). Please refer to Section 6.4.5, “Mode Transition Interrupts for the exceptions to this behavior. It is cleared by writing a ‘1’ to this bit. 0 Mode transition requested is not illegal 1 Mode transition requested is illegal Mode Request Illegal status — This bit is set whenever the target mode requested is not a valid mode with respect to current mode. It is cleared by writing a ‘1’ to this bit. 0 Target mode requested is not illegal with respect to current mode 1 Target mode requested is illegal with respect to current mode Disabled Mode Access status — This bit is set whenever the target mode requested is one of those disabled modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit. 0 Target mode requested is not a disabled mode 1 Target mode requested is a disabled mode Non-existing Mode Access status — This bit is set whenever the target mode requested is one of those non existing modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit. 0 Target mode requested is an existing mode 1 Target mode requested is a non-existing mode SAFE Event Active status — This bit is set whenever the device is in SAFE mode, SAFE event bit is pending and a new mode requested other than RESET/SAFE modes. It is cleared by writing a ‘1’ to this bit. 0 No new mode requested other than RESET/SAFE while SAFE event is pending 1 New mode requested other than RESET/SAFE while SAFE event is pending
S_MRI
S_DMA
S_NMA
S_SEA
MPC5602D Microcontroller Reference Manual, Rev. 3.1 144 Preliminary Freescale Semiconductor
S_SEA
S_MRI
S_MTI
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.7
Debug Mode Transition Status Register (ME_DMTS)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C018
0 1 2
PMC_PROG
R PREVIOUS_MODE 0 0 0 0
CORE_DBG
MPH_BUSY
0
0
0
0
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CDP_PRPH_96_127
CDP_PRPH_64_95
0
0
0
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-8. Debug Mode Transition Status Register (ME_DMTS)
This register provides the status of different factors which influence mode transitions. It is used to give an indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than expected. NOTE The ME_DMTS register does not indicate whether a mode transition is ongoing. Therefore, some ME_DMTS bits may still be asserted after the mode transition has completed.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 145
CDP_PRPH_0_31
CSRC_CSRC_SC
VREG_CSRC_SC
R
CDP_PRPH_0_143
CDP_PRPH_32_63
SYSCLK_SW
DFLASH_SC
CFLASH_SC
SCSRC_SC
FIRC_SC
SMR
Chapter 6 Mode Entry Module (MC_ME)
Table 6-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions
Field Description
PREVIOUS_ Previous device mode — These bits show the mode in which the device was prior to the latest MODE change to the current mode. 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT0 1001 reserved 1010 STOP0 1011 reserved 1100 reserved 1101 STANDBY0 1110 reserved 1111 reserved MPH_BUSY MC_ME/MC_PCU Handshake Busy indicator — This bit is set if the MC_ME has requested a mode change from the MC_PCU and the MC_PCU has not yet responded. It is cleared when the MC_PCU has responded. 0 Handshake is not busy 1 Handshake is busy PMC_PROG MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the process of powering up or down power domains. It is cleared when all power-up/down processes have completed. 0 Power-up/down transition is not in progress 1 Power-up/down transition is in progress CORE_DBG Processor is in Debug mode indicator — This bit is set while the processor is in debug mode. 0 The processor is not in debug mode 1 The processor is in debug mode SMR SAFE mode request from MC_RGM is active indicator — This bit is set if a hardware SAFE mode request has been triggered. It is cleared when the hardware SAFE mode request has been cleared. 0 A SAFE mode request is not active 1 A SAFE mode request is active
VREG_CSR Main VREG dependent Clock Source State Change during mode transition indicator — This bit is set C_SC when a clock source which depends on the main voltage regulator to be powered-up is requested to change its power up/down state. It is cleared when the clock source has completed its state change. 0 No state change is taking place 1 A state change is taking place CSRC_CSR (Other) Clock Source dependent Clock Source State Change during mode transition indicator — This C_SC bit is set when a clock source which depends on another clock source to be powered-up is requested to change its power up/down state. It is cleared when the clock source has completed its state change. 0 No state change is taking place 1 A state change is taking place FIRC_SC FIRC State Change during mode transition indicator — This bit is set when the fast internal RC oscillator (16 MHz) is requested to change its power up/down state. It is cleared when the fast internal RC oscillator (16 MHz) has completed its state change. 0 No state change is taking place 1 A state change is taking place
MPC5602D Microcontroller Reference Manual, Rev. 3.1 146 Preliminary Freescale Semiconductor
Chapter 6 Mode Entry Module (MC_ME)
Table 6-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued)
Field SYSCLK_S W Description System Clock Switching pending status — 0 No system clock source switching is pending 1 A system clock source switching is pending
DFLASH_SC DFLASH State Change during mode transition indicator — This bit is set when the DFLASH is requested to change its power up/down state. It is cleared when the DFLASH has completed its state change. 0 No state change is taking place 1 A state change is taking place CFLASH_SC CFLASH State Change during mode transition indicator — This bit is set when the CFLASH is requested to change its power up/down state. It is cleared when the DFLASH has completed its state change. 0 No state change is taking place 1 A state change is taking place CDP_PRPH Clock Disable Process Pending status for Peripherals 0…143 — This bit is set when any peripheral _0_143 has been requested to have its clock disabled. It is cleared when all the peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral CDP_PRPH Clock Disable Process Pending status for Peripherals 96…127 — This bit is set when any peripheral _96_127 appearing in ME_PS3 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral CDP_PRPH Clock Disable Process Pending status for Peripherals 64…95 — This bit is set when any peripheral _64_95 appearing in ME_PS2 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral CDP_PRPH Clock Disable Process Pending status for Peripherals 32…63 — This bit is set when any peripheral _32_63 appearing in ME_PS1 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral CDP_PRPH Clock Disable Process Pending status for Peripherals 0…31 — This bit is set when any peripheral _0_31 appearing in ME_PS0 has been requested to have its clock disabled. It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one peripheral
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 147
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.8
RESET Mode Configuration Register (ME_RESET_MC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C020
0 1 2
R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO 0 0
MVRON
DFLAON
CFLAON
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIRCON
R
FXOSCON
FMPLLON
SYSCLK
W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 6-9. RESET Mode Configuration Register (ME_RESET_MC)
This register configures system behavior during RESET mode. Please refer to Table 6-11 for details.
6.3.2.9
TEST Mode Configuration Register (ME_TEST_MC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C024
0 1 2
R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO 0 0
MVRON
DFLAON
CFLAON
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIRCON
R W
0
0
0
0
0
0
0
0
0
FXOSCON
FMPLLON
SYSCLK
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 6-10. TEST Mode Configuration Register (ME_TEST_MC)
This register configures system behavior during TEST mode. Please refer to Table 6-11 for details. NOTE Byte write accesses are not allowed to this register.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 148 Preliminary Freescale Semiconductor
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.10
SAFE Mode Configuration Register (ME_SAFE_MC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C028
0 1 2
R 0 W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 PDO 0 0
MVRON
DFLAON
CFLAON
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIRCON
R
FXOSCON
FMPLLON
SYSCLK
W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 6-11. SAFE Mode Configuration Register (ME_SAFE_MC)
This register configures system behavior during SAFE mode. Please refer to Table 6-11 for details. NOTE Byte write accesses are not allowed to this register.
6.3.2.11
DRUN Mode Configuration Register (ME_DRUN_MC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C02C
0 1 2
R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO 0 0
MVRON
DFLAON
CFLAON
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 W Reset 0
0
0
0
0
0
0
0
0
FXOSCON
FMPLLON
R
FIRCON
SYSCLK
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 6-12. DRUN Mode Configuration Register (ME_DRUN_MC)
This register configures system behavior during DRUN mode. Please refer to Table 6-11 for details.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 149
Chapter 6 Mode Entry Module (MC_ME)
NOTE Byte write accesses are not allowed to this register. NOTE The clock source and flash configuration values are retained through STANDBY0 mode.
6.3.2.12
RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)
Access: User read, Supervisor read/write, Test read/write
5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C030 - 0xC3FD_C03C
0 1 2 3 4
R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO 0 0
MVRON
DFLAON
CFLAON
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0 W Reset 0
0
0
0
0
0
0
0
0
FXOSCON
FMPLLON
R
FIRCON
SYSCLK
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 6-13. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)
This register configures system behavior during RUN0…3 modes. Please refer to Table 6-11 for details. NOTE Byte write accesses are not allowed to this register.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 150 Preliminary Freescale Semiconductor
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.13
HALT0 Mode Configuration Register (ME_HALT0_MC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C040
0 1 2
R W Reset
0
0
0
0
0
0
0
0
PDO
0
0
MVRON
DFLAON 1 1
CFLAON 1 0
0
0
0
0
0
0
0
0
0
0
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIRCON
R W
0
0
0
0
0
0
0
0
0
FXOSCON
FMPLLON
SYSCLK
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 6-14. HALT0 Mode Configuration Register (ME_HALT0_MC)
This register configures system behavior during HALT0 mode. Please refer to Table 6-11 for details. NOTE Byte write accesses are not allowed to this register.
6.3.2.14
STOP0 Mode Configuration Register (ME_STOP0_MC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C048
0 1 2
R W Reset
0
0
0
0
0
0
0
0 PDO
0
0
MVRON
DFLAON 0 1
CFLAON 0 1
0
0
0
0
0
0
0
0
0
0
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIRCON
R 0 0 0 0 0 0 0 0 0
FXOSCON
FMPLLON
SYSCLK
W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 6-15. STOP0 Mode Configuration Register (ME_STOP0_MC)
This register configures system behavior during STOP0 mode. Please refer to Table 6-11 for details. NOTE Byte write accesses are not allowed to this register.
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 151
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.15
STANDBY0 Mode Configuration Register (ME_STANDBY0_MC)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C054
0 1 2
R 0 W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 PDO 0 0
MVRON
DFLAON
CFLAON
0
0
1
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
FXOSCON
FMPLLON
FIRCON
SYSCLK
W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Figure 6-16. STANDBY0 Mode Configuration Register (ME_STANDBY0_MC)
This register configures system behavior during STANDBY0 mode. Please refer to Table 6-11 for details. NOTE Byte write accesses are not allowed to this register.
Table 6-11. Mode Configuration Registers (ME__MC) Field Descriptions
Field PDO Description I/O output power-down control — This bit controls the output power-down of I/Os. 0 No automatic safe gating of I/Os used and pads power sequence driver is enabled 1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power sequence driver is disabled. The inputs are level unchanged. In STOP0 mode, only the pad power sequence driver is disabled, but the state of the output remains functional. In STANDBY0 mode, power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. Wakeup line configuration remains unchanged Main voltage regulator control — This bit specifies whether main voltage regulator is switched off or not while entering this mode. 0 Main voltage regulator is switched off 1 Main voltage regulator is switched on Data flash power-down control — This bit specifies the operating mode of the data flash after entering this mode. 00 reserved 01 Data flash is in power-down mode 10 reserved 11 Data flash is in normal mode
MVRON
DFLAON
MPC5602D Microcontroller Reference Manual, Rev. 3.1 152 Preliminary Freescale Semiconductor
Chapter 6 Mode Entry Module (MC_ME)
Table 6-11. Mode Configuration Registers (ME__MC) Field Descriptions (continued)
Field CFLAON Description Code flash power-down control — This bit specifies the operating mode of the code flash after entering this mode. 00 reserved 01 Code flash is in power-down mode 10 Code flash is in low-power mode 11 Code flash is in normal mode frequency modulated phase locked loop control 0 frequency modulated phase locked loop is switched off 1 frequency modulated phase locked loop is switched on fast external crystal oscillator (4-16 MHz) control 0 fast external crystal oscillator (4-16 MHz) is switched off 1 fast external crystal oscillator (4-16 MHz) is switched on fast internal RC oscillator (16 MHz) control 0 fast internal RC oscillator (16 MHz) is switched off 1 fast internal RC oscillator (16 MHz) is switched on System clock switch control — These bits specify the system clock to be used by the system. 0000 16 MHz int. RC osc. 0001 div. 16 MHz int. RC osc. 0010 4-16 MHz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled in STOP0 and TEST modes, reserved in all other modes
FMPLLON
FXOSCON
FIRCON
SYSCLK
MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 153
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.16
Peripheral Status Register 0 (ME_PS0)
Access: User read, Supervisor read, Test read
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C060
0 1 2
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S_DSPI1
R
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-17. Peripheral Status Register 0 (ME_PS0)
This register provides the status of the peripherals. Please refer to Table 6-12 for details.
6.3.2.17
Peripheral Status Register 1 (ME_PS1)
Access: User read, Supervisor read, Test read
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C064
0 1 2
S_DSPI0
S_LINFlex2
S_LINFlex1 0
30
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
S_CTUL
R
23
24
25
26
27
28
29
31
R
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-18. Peripheral Status Register 1 (ME_PS1)
This register provides the status of the peripherals. Please refer to Table 6-12 for details.
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S_ADC1
S_LINFlex0
S_FlexCAN0
R
S_DMA_CH_MUX
Chapter 6 Mode Entry Module (MC_ME)
6.3.2.18
Peripheral Status Register 2 (ME_PS2)
Access: User read, Supervisor read, Test read
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C068
0 1 2
R
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
S_RTC_API
21
S_PIT_RTI
22
23
24
25
26
27
28
29
30
31
S_eMIOS0
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-19. Peripheral Status Register 2 (ME_PS2)
This register provides the status of the peripherals. Please refer to Table 6-12 for details.
6.3.2.19
Peripheral Status Register 3 (ME_PS3)
Access: User read, Supervisor read, Test read
3 4 5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C06C
0 1 2
R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
S_SIUL
28
R
S_WKPU
29
30
31
R
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-20. Peripheral Status Register 3 (ME_PS3)
This register provides the status of the peripherals. Please refer to Table 6-12 for details.
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S_CMU
Chapter 6 Mode Entry Module (MC_ME)
Table 6-12. Peripheral Status Registers 0…4 (ME_PS0…4) Field Descriptions
Field S_ Description Peripheral status — These bits specify the current status of the peripherals in the system. If no peripheral is mapped on a particular position (i.e., the corresponding MODS bit is ‘0’), the corresponding bit is always read as ‘0’. 0 Peripheral is frozen 1 Peripheral is active
6.3.2.20
Run Peripheral Configuration Registers (ME_RUN_PC0…7)
Access: User read, Supervisor read/write, Test read/write
5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C080 - 0xC3FD_C09C
0 1 2 3 4
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RUN3
RUN2
RUN1
RUN0
SAFE
W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-21. Run Peripheral Configuration Registers (ME_RUN_PC0…7)
These registers configure eight different types of peripheral behavior during run modes.
Table 6-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions
Field RUN3 Peripheral control during RUN3 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RUN2 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RUN1 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RUN0 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during DRUN 0 Peripheral is frozen with clock gated 1 Peripheral is active Description
RUN2
RUN1
RUN0
DRUN
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TEST
0
0
0
0
0
0
0
0
DRUN
R
RESET
Chapter 6 Mode Entry Module (MC_ME)
Table 6-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions (continued)
Field SAFE Peripheral control during SAFE 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during TEST 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during RESET 0 Peripheral is frozen with clock gated 1 Peripheral is active Description
TEST
RESET
6.3.2.21
Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
Access: User read, Supervisor read/write, Test read/write
5 6 7 8 9 10 11 12 13 14 15
Address 0xC3FD_C0A0 - 0xC3FD_C0BC
0 1 2 3 4
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
STOP0
W
Reset
0
0
0
0
0
0
0
HALT0
R
0
0
STANDBY0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-22. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
These registers configure eight different types of peripheral behavior during non-run modes.
Table 6-14. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions
Field STANDBY0 Peripheral control during STANDBY0 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during STOP0 0 Peripheral is frozen with clock gated 1 Peripheral is active Peripheral control during HALT0 0 Peripheral is frozen with clock gated 1 Peripheral is active Description
STOP0
HALT0
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6.3.2.22
Peripheral Control Registers (ME_PCTL0…143)
Access: User read, Supervisor read/write, Test read/write
3 4 5 6 7
Address 0xC3FD_C0C0 - 0xC3FD_C14F
0 1 2
R W Reset
0 DBG_F 0 0 0 LP_CFG 0 0 0 RUN_CFG 0 0
Figure 6-23. Peripheral Control Registers (ME_PCTL0…143)
These registers select the configurations during run and non-run modes for each peripheral.
Table 6-15. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions
Field DBG_F Description Peripheral control in debug mode — This bit controls the state of the peripheral in debug mode 0 Peripheral state depends on RUN_CFG/LP_CFG bits and the device mode 1 Peripheral is frozen if not already frozen in device modes.
NOTE This feature is useful to freeze the peripheral state while entering debug. For example, this may be used to prevent a reference timer from running while making a debug accesses.
LP_CFG Peripheral configuration select for non-run modes — These bits associate a configuration as defined in the ME_LP_PC0…7 registers to the peripheral. 000 Selects ME_LP_PC0 configuration 001 Selects ME_LP_PC1 configuration 010 Selects ME_LP_PC2 configuration 011 Selects ME_LP_PC3 configuration 100 Selects ME_LP_PC4 configuration 101 Selects ME_LP_PC5 configuration 110 Selects ME_LP_PC6 configuration 111 Selects ME_LP_PC7 configuration Peripheral configuration select for run modes — These bits associate a configuration as defined in the ME_RUN_PC0…7 registers to the peripheral. 000 Selects ME_RUN_PC0 configuration 001 Selects ME_RUN_PC1 configuration 010 Selects ME_RUN_PC2 configuration 011 Selects ME_RUN_PC3 configuration 100 Selects ME_RUN_PC4 configuration 101 Selects ME_RUN_PC5 configuration 110 Selects ME_RUN_PC6 configuration 111 Selects ME_RUN_PC7 configuration
RUN_CFG
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Chapter 6 Mode Entry Module (MC_ME)
6.4
6.4.1
Functional Description
Mode Transition Request
The transition from one mode to another mode is normally handled by software by accessing the mode control register ME_MCTL. But the in case of special events, the mode transition can be automatically managed by hardware. In order to switch from one mode to another, the application should access the ME_MCTL register twice by writing • the first time with the value of the key (0x5AF0) into the KEY bit field and the required target mode into the TARGET_MODE bit field, • and the second time with the inverted value of the key (0xA50F) into the KEY bit field and the required target mode into the TARGET_MODE bit field. Once a valid mode transition request is detected, the target mode configuration information is loaded from the corresponding ME__MC register. The mode transition request may require a number of cycles depending on the programmed configuration, and software should check the S_CURRENT_MODE bit field and the S_MTRANS bit of the global status register ME_GS to verify when the mode has been correctly entered and the transition process has completed. For a description of valid mode requests, please refer to Section 6.4.5, “Mode Transition Interrupts“. Any modification of the mode configuration register of the currently selected mode will not be taken into account immediately but on the next request to enter this mode. This means that transition requests such as RUN0…3 RUN0…3, DRUN DRUN, SAFE SAFE, and TEST TEST are considered valid mode transition requests. As soon as the mode request is accepted as valid, the S_MTRANS bit is set till the status in the ME_GS register matches the configuration programmed in the respective ME__MC register. NOTE It is recommended that software poll the S_MTRANS bit in the ME_GS register after requesting a transition to HALT0, STOP0, or STANDBY0 modes.
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SYSTEM MODES
recoverable hardware failure
USER MODES
RUN0 software request SAFE HALT0 RUN1
RESET
DRUN
RUN2 STOP0
RUN3 non-recoverable failure TEST
STANDBY0
Figure 6-24. MC_ME Mode Diagram
6.4.2
6.4.2.1
Modes Details
RESET Mode
The device enters this mode on the following events: • from SAFE, DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0000” • from any mode due to a system reset by the MC_RGM because of some non-recoverable hardware failure in the system (see the MC_RGM chapter for details) Transition to this mode is instantaneous, and the system remains in this mode until the reset sequence is finished. The mode configuration information for this mode is provided by the ME_RESET_MC register. This mode has a pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock. All power domains are made active in this mode.
6.4.2.2
DRUN Mode
The device enters this mode on the following events: • automatically from RESET mode after completion of the reset sequence
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• •
from RUN0…3, SAFE, or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0011” from the STANDBY0 mode after an external wakeup event or internal wakeup alarm (e.g., RTC/API event)
As soon as any of the above events has occurred, a DRUN mode transition request is generated. The mode configuration information for this mode is provided by the ME_DRUN_MC register. In this mode, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. After system reset, the software execution starts with the default configuration selecting the 16 MHz int. RC osc. as the system clock. This mode is intended to be used by software • to initialize all registers as per the system needs • to execute small routines in a ‘ping-pong’ with the STANDBY0 mode When this mode is entered from STANDBY0 after a wakeup event, the ME_DRUN_MC register content is restored to its pre-STANDBY0 values, and the mode starts in that configuration. All power domains are active when this mode is entered due to a system reset sequence initiated by a destructive reset event. the exit from STANDBY0 after a wakeup event, NOTE Software must ensure that the code executes from RAM before changing to this mode if the flashes are configured to be in the low-power or power-down state in this mode.
6.4.2.3
SAFE Mode
The device enters this mode on the following events: • from DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0010” • from any mode except RESET due to a SAFE mode request generated by the MC_RGM because of some potentially recoverable hardware failure in the system (see the MC_RGM chapter for details) As soon as any of the above events has occurred, a SAFE mode transition request is generated. The mode configuration information for this mode is provided by the ME_SAFE_MC register. This mode has a pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock. All power domains are made active in this mode. If the SAFE mode is requested by software while some other mode transition process is ongoing, the new target mode becomes the SAFE mode regardless of other pending requests or new requests during the mode transition. No new mode request made during a transition to the SAFE mode will cause an invalid mode interrupt.
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NOTE If software requests to change to the SAFE mode and then requests to change back to the parent mode before the mode transition is completed, the device’s final mode after mode transition will be the SAFE mode. As long as a SAFE event is active, the system remains in the SAFE mode, and any software mode request during this time is ignored and lost. This mode is intended to be used by software • to assess the severity of the cause of failure and then to either — re-initialize the device via the DRUN mode, or — completely reset the device via the RESET mode. If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the PDO bit of the ME_SAFE_MC register should be set. In this case, the pads’ power sequence driver cell is also disabled. The input levels remain unchanged.
6.4.2.4
TEST Mode
The device enters this mode on the following events: • from the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0001” As soon as any of the above events has occurred, a TEST mode transition request is generated. The mode configuration information for this mode is provided by the ME_TEST_MC register. Except for the main voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole system can be stopped by programming the SYSCLK bit field to “1111”, and in this case, the only way to exit this mode is via a device reset. This mode is intended to be used by software • to execute software test routines NOTE Software must ensure that the code executes from RAM before changing to this mode if the flashes are configured to be in the low-power or power-down state in this mode.
6.4.2.5
RUN0…3 Modes
The device enters one of these modes on the following events: • from the DRUN, SAFE, or another RUN0…3 mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0100…0111” • from the HALT0 mode due to an interrupt event • from the STOP0 mode due to an interrupt or wakeup event As soon as any of the above events has occurred, a RUN0…3 mode transition request is generated. The mode configuration information for these modes is provided by the ME_RUN0…3_MC registers. In these
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modes, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. These modes are intended to be used by software • to execute application routines NOTE Software must ensure that the code executes from RAM before changing to this mode if the flashes are configured to be in the low-power or power-down state in this mode.
6.4.2.6
HALT0 Mode
The device enters this mode on the following events: • from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with “1000”. As soon as any of the above events has occurred, a HALT0 mode transition request is generated. The mode configuration information for this mode is provided by ME_HALT0_MC register. This mode is quite configurable, and the ME_HALT0_MC register should be programmed according to the system needs. The main voltage regulator and the flashes can be put in low-power or power-down mode as needed. If there is a HALT0 mode request while an interrupt request is active, the transition to HALT0 is aborted with the resultant mode being the current mode, SAFE (on SAFE mode request), or DRUN (on reset), and an invalid mode interrupt is not generated. This mode is intended as a first-level low-power mode with • the core clock frozen • only a few peripherals running and to be used by software • to wait until it is required to do something and then to react quickly (i.e., within a few system clock cycles of an interrupt event)
6.4.2.7
STOP0 Mode
The device enters this mode on the following events: • from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with “1010”. As soon as any of the above events has occurred, a STOP0 mode transition request is generated. The mode configuration information for this mode is provided by the ME_STOP0_MC register. This mode is fully configurable, and the ME_STOP0_MC register should be programmed according to the system needs. The main voltage regulator and the flashes can be put in power-down mode as needed. If there is a STOP0 mode request while any interrupt or wakeup event is active, the transition to STOP0 is aborted with the resultant mode being the current mode, SAFE (on SAFE mode request), or DRUN (on reset), and an invalid mode interrupt is not generated.
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This can be used as an advanced low-power mode with the core clock frozen and almost all peripherals stopped. This mode is intended as an advanced low-power mode with • the system clock frozen • almost all peripherals stopped and to be used by software • to wait until it is required to do something with no need to react quickly (e.g., allow for system clock source to be re-started) If the pads’ power sequence driver cell needs to be disabled while entering this mode, the PDO bit of the ME_STOP0_MC register should be set. The state of the outputs is kept. This mode can be used to stop all clock sources and thus preserve the device status. When exiting the STOP0 mode, the fast internal RC oscillator (16 MHz) clock is selected as the system clock until the target clock is available.
6.4.2.8
STANDBY0 Mode
The device enters this mode on the following events: • from the DRUN or one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with “1101”. As soon as any of the above events occur, a STANDBY0 mode transition request is generated. The mode configuration information for this mode is provided by the ME_STANDBY0_MC register. In this mode, the power supply is turned off for most of the device. The only parts of the device that are still powered during this mode are pads mapped on wakeup lines and power domain #0 which contains the MC_RGM, MC_PCU, WKPU, 8K RAM, RTC_API, CANSampler, SIRC, FIRC, and device and user option bits. The FIRC can be optionally switched off. This is the lowest power consumption mode possible on the device. This mode is intended as an extreme low-power mode with • the core, the flashes, and almost all peripherals and memories powered down and to be used by software • to wait until it is required to do something with no need to react quickly (i.e., allow for system power-up and system clock source to be re-started) The exit sequence of this mode is similar to the reset sequence. However, in addition to booting from the default location, the device can also be configured to boot from the backup RAM (see the RGM_STDBY register description in the MC_RGM chapter for details). In the case of booting from backup RAM, it is also possible to keep the flashes disabled by writing “01” to the CFLAON and DFLAON fileds in the ME_DRUN_MC register prior to STANDBY0 entry. If there is a STANDBY0 mode request while any wakeup event is active, the device mode does not change. All power domains except power domain #0 are configurable in this mode in order to reduce leakage consumption.
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Chapter 6 Mode Entry Module (MC_ME)
6.4.3
Mode Transition Process
The process of mode transition follows the following steps in a pre-defined manner depending on the current device mode and the requested target mode. In many cases of mode transition, not all steps need to be executed based on the mode control information, and some steps may not be applicable according to the mode definition itself.
6.4.3.1
Target Mode Request
The target mode is requested by accessing the ME_MCTL register with the required keys. This mode transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the process. If the request fails to satisfy these rules, it is ignored, and the TARGET_MODE bit field is not updated. An optional interrupt can be generated for invalid mode requests. Refer to Section 6.4.5, “Mode Transition Interrupts for details. In the case of mode transitions occurring because of hardware events such as a reset, a SAFE mode request, or interrupt requests and wakeup events to exit from low-power modes, the TARGET_MODE bit field of the ME_MCTL register is automatically updated with the appropriate target mode. The mode change process start is indicated by the setting of the mode transition status bit S_MTRANS of the ME_GS register. A RESET mode requested via the ME_MCTL register is passed to the MC_RGM, which generates a global system reset and initiates the reset sequence. The RESET mode request has the highest priority, and the MC_ME is kept in the RESET mode during the entire reset sequence. The SAFE mode request has the next highest priority after reset. It can be generated either by software via the ME_MCTL register from all software running modes including DRUN, RUN0…3, and TEST or by the MC_RGM after the detection of system hardware failures, which may occur in any mode.
6.4.3.2
Target Mode Configuration Loading
On completion of the Target Mode Request step, the target mode configuration from the ME__MC register is loaded to start the resources (voltage sources, clock sources, flashes, pads, etc.) control process. An overview of resource control possibilities for each mode is shown in Table 6-16. A ‘’ indicates that a given resource is configurable for a given mode.
Table 6-16. MC_ME Resource Control Overview
Mode Resource RESET FIRC on FXOSC off TEST on off off on on off on off SAFE DRUN RUN0…3 HALT0 on off STOP0 on off off STANDBY0 on
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Table 6-16. MC_ME Resource Control Overview (continued)
Mode Resource RESET FMPLL off CFLASH normal DFLASH normal MVREG on PDO off on off on on off off off on on TEST off normal normal normal normal off SAFE DRUN off normal normal RUN0…3 off normal normal HALT0 off low-power low-power on off powerdown powerdown on off on off powerdown powerdown off STOP0 STANDBY0
6.4.3.3
Peripheral Clocks Disable
On completion of the Target Mode Request step, the MC_ME requests each peripheral to enter its stop mode when: • the peripheral is configured to be disabled via the target mode, the peripheral configuration registers ME_RUN_PC0…7 and ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143 WARNING The MC_ME does not automatically request peripherals to enter their stop modes if the power domains in which they are residing are to be turned off due to a mode change. Therefore, it is software’s responsibility to ensure that those peripherals that are to be powered down are configured in the MC_ME to be frozen. Each peripheral acknowledges its stop mode request after closing its internal activity. The MC_ME then disables the corresponding clock(s) to this peripheral. In the case of a SAFE mode transition request, the MC_ME does not wait for the peripherals to acknowledge the stop requests. The SAFE mode clock gating configuration is applied immediately regardless of the status of the peripherals’ stop acknowledges. Please refer to Section 6.4.6, “Peripheral Clock Gating“ for more details. Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive state when the device enters the SAFE mode.
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6.4.3.4
Processor Low-Power Mode Entry
If, on completion of the Peripheral Clocks Disable step, the mode transition is to the HALT0 mode, the MC_ME requests the processor to enter its halted state. The processor acknowledges its halt state request after completing all outstanding bus transactions. If, on completion of the Peripheral Clocks Disable step, the mode transition is to the STOP0 or STANDBY0 mode, the MC_ME requests the processor to enter its stopped state. The processor acknowledges its stop state request after completing all outstanding bus transactions.
6.4.3.5
Processor and System Memory Clock Disable
If, on completion of the Processor Low-Power Mode Entry step, the mode transition is to the HALT0, STOP0, or STANDBY0 mode and the processor is in its appropriate halted or stopped state, the MC_ME disables the processor and system memory clocks to achieve further power saving. The clocks to the processor and system memory are unaffected while transitioning between software running modes such as DRUN, RUN0…3, and SAFE. WARNING Clocks to the whole device including the processor and system memory can be disabled in TEST mode.
6.4.3.6
Clock Sources (Main Voltage Regulator Independent) Switch-On
On completion of the Processor Low-Power Mode Entry step, the MC_ME switches on all clock sources, which do not need the main voltage regulator to be on, based on the ON bits of the ME__MC and ME__MC registers. The following clock sources are switched on at this step: NOTE Clock sources which need the main voltage regulator to be stable are not controlled by this step. The clock sources that are required by the target mode are switched on. The duration required for the output clocks to be stable depends on the type of source, and all further steps of mode transition depending on one or more of these clocks waits for the stable status of the respective clocks. The availability status of these clocks is updated in the S_ bits of ME_GS register. The clock sources which need to be switched off are unaffected during this process in order to not disturb the system clock which might require one of these clocks before switching to a different target clock.
6.4.3.7
Main Voltage Regulator Switch-On
On completion of the Target Mode Request step, if the main voltage regulator needs to be switched on from its off state based on the MVRON bit of the ME__MC and ME__MC registers, the MC_ME requests the MC_PCU to power-up the regulator and waits for the output voltage stable status in order to update the S_MVR bit of the ME_GS register.
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This step is required only during the exit of the low-power modes HALT0 and STOP0. In this step, the fast internal RC oscillator (16 MHz) is switched on regardless of the target mode configuration, as the main voltage regulator requires the 16 MHz int. RC osc. during power-up in order to generate the voltage status. During the STANDBY0 exit sequence, the MC_PCU alone manages the power-up of the main voltage regulator, and the MC_ME is kept in RESET or shut off (depending on the power domain #1 status).
6.4.3.8
Flash Modules Switch-On
On completion of the Main Voltage Regulator Switch-On step, if one or more of the flashes needs to be switched to normal mode from its low-power or power-down mode based on the CFLAON and DFLAON bit fields of the ME__MC and ME__MC registers, the MC_ME requests the flash to exit from its low-power/power-down mode. When the flashes are available for access, the S_CFLA and S_DFLA bit fields of the ME_GS register are updated to “11” by hardware. If the main regulator is also off in device low-power modes, then during the exit sequence, the flash is kept in its low-power state and is switched on only when the Main Voltage Regulator Switch-On process has completed. WARNING It is illegal to switch the flashes from low-power mode to power-down mode and from power-down mode to low-power mode. The MC_ME, however, does not prevent this nor does it flag it.
6.4.3.9
Clock Sources (Main Voltage Regulator Dependent) Switch-On
On completion of the Clock Sources (Main Voltage Regulator Independent) Switch-On and Main Voltage Regulator Switch-On, the MC_ME controls all clock sources, which need the main voltage regulator to be on, based on the ON bits of the ME__MC and ME__MC registers. The following clock sources are switched on at this step:
6.4.3.10
Pad Outputs-On
On completion of the Main Voltage Regulator Switch-On step, if the PDO bit of the ME__MC register is cleared, then • all pad outputs are enabled to return to their previous state • the I/O pads power sequence driver is switched on
6.4.3.11
Peripheral Clocks Enable
Based on the current and target device modes, the peripheral configuration registers ME_RUN_PC0…7, ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143, the MC_ME enables the clocks for selected modules as required. This step is executed only after the Main Voltage Regulator Switch-On process is completed.
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Also, if a mode change translates to a power up of one or more power domains, the MC_PCU indicates the MC_ME after completing the power-up sequence upon which the MC_ME may assert the peripheral clock enables of the peripherals residing in those power domains.
6.4.3.12
Processor and Memory Clock Enable
If the mode transition is from any of the low-power modes HALT0 or STOP0 to RUN0…3, the clocks to the processor and system memory are enabled. The process of enabling these clocks is executed only after the Flash Modules Switch-On process is completed.
6.4.3.13
Processor Low-Power Mode Exit
If the mode transition is from any of the low-power modes HALT0, STOP0, or STANDBY0 to RUN0…3, the MC_ME requests the processor to exit from its halted or stopped state. This step is executed only after the Processor and Memory Clock Enable process is completed.
6.4.3.14
System Clock Switching
Based on the SYSCLK bit field of the ME__MC and ME__MC registers, if the target and current system clock configurations differ, the following method is implemented for clock switching. • The target clock configuration for the 16 MHz int. RC osc. takes effect only after the S_FIRC bit of the ME_GS register is set by hardware (i.e., the fast internal RC oscillator (16 MHz) has stabilized). • The target clock configuration for the div. 16 MHz int. RC osc. takes effect only after the S_FIRC bit of the ME_GS register is set by hardware (i.e., the fast internal RC oscillator (16 MHz) has stabilized). • The target clock configuration for the 4-16 MHz ext. xtal osc. takes effect only after the S_FXOSC bit of the ME_GS register is set by hardware (i.e the fast external crystal oscillator (4-16 MHz) has stabilized). • The target clock configuration for the div. ext. xtal osc. takes effect only after the S_FXOSC bit of the ME_GS register is set by hardware (i.e the fast external crystal oscillator (4-16 MHz) has stabilized). • The target clock configuration for the freq. mod. PLL takes effect only after the S_FMPLL bit of the ME_GS register is set by hardware (i.e., the frequency modulated phase locked loop has stabilized). • If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is possible only in the STOP0 and TEST modes. In the STANDBY0 mode, the clock configuration is fixed, and the system clock is automatically forced to ‘0’. The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GS register, which is updated after every system clock switching. Until the target clock is available, the system uses the previous clock configuration. System clock switching starts only after
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•
the Peripheral Clocks Disable process has completed in order not to change the system clock frequency before peripherals close their internal activities
An overview of system clock source selection possibilities for each mode is shown in Table 6-17. A ‘’ indicates that a given clock source is selectable for a given mode.
Table 6-17. MC_ME System Clock Selection Overview
System Clock Source 16 MHz int. RC osc. div. 16 MHz int. RC osc. 4-16 MHz ext. xtal osc. div. ext. xtal osc. freq. mod. PLL system clock is disabled
1
Mode RESET (default) TEST (default) SAFE (default) DRUN (default) RUN0…3 (default) HALT0 (default) STOP0 (default) STANDBY0
(default)
disabling the system clock during TEST mode will require a reset in order to exit TEST mode
6.4.3.15
Pad Switch-Off
If the PDO bit of the ME__MC register is ‘1’ then • the outputs of the pads are forced to the high impedance state if the target mode is SAFE or TEST • I/O pads power sequence driver is switched off if the target mode is one of SAFE, TEST, or STOP0 modes In STANDBY0 mode, the power sequence driver and all pads except the external reset and those mapped on wakeup lines are not powered and therefore high impedance. The wakeup line configuration remains unchanged. This step is executed only after the Peripheral Clocks Disable process has completed.
6.4.3.16
Clock Sources Switch-Off
Based on the device mode and the ON bits of the ME__MC registers, if a given clock source is to be switched off, the MC_ME requests the clock source to power down and updates its availability status bit S_ of the ME_GS register to ‘0’. The following clock sources switched off at this step:
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This step is executed only after the System Clock Switching process has completed.
6.4.3.17
Flash Switch-Off
Based on the CFLAON and DFLAON bit fields of the ME__MC and ME__MC registers, if any of the flashes is to be put in its low-power or power-down mode, the MC_ME requests the flash to enter the corresponding power mode and waits for the flash to acknowledge. The exact power mode status of the flashes is updated in the S_CFLA and S_DFLA bit fields of the ME_GS register. This step is executed only when the Processor and System Memory Clock Disable process has completed.
6.4.3.18
Main Voltage Regulator Switch-Off
Based on the MVRON bit of the ME__MC and ME__MC registers, if the main voltage regulator is to be switched off, the MC_ME requests it to power down and clears the availability status bit S_MVR of the ME_GS register. This step is required only during the entry of low-power modes like HALT0 and STOP0. This step is executed only after completing the following processes: • Clock Sources Switch-Off • Flash Switch-Off • the device consumption is less than the pre-defined threshold value (i.e., the S_DC bit of the ME_GS register is ‘0’). If the target mode is STANDBY0, the main voltage regulator is not switched off by the MC_ME and the STANDBY0 request is asserted after the above processes have completed upon which the MC_PCU takes control of the main regulator. As the MC_PCU needs the 16 MHz int. RC osc., the fast internal RC oscillator (16 MHz) remains active until all the STANDBY0 steps are executed by the MC_PCU after which it may be switched off depending on the FIRCON bit of the ME_STANDBY0_MC register.
6.4.3.19
Current Mode Update
The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated with the target mode bit field TARGET_MODE of the ME_MCTL register when: • all the updated status bits in the ME_GS register match the configuration specified in the ME__MC register • power sequences are done • clock disable/enable process is finished • processor low-power mode (halt/stop) entry and exit processes are finished Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register. The mode transition latency can differ from one mode to another depending on the resources’ availability before the new mode request and the target mode’s requirements. If a mode transition is taking longer to complete than is expected, the ME_DMTS register can indicate which process is still in progress.
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Start Write ME_MCTL register SAFE mode request interrupt/wakeup event
Target Mode Request
S_MTRANS = ‘1’
Main VREG FLASH Dependent Switch-On Clock Sources Switch-On Peripheral Clocks Disable Processor & Memory Clock Enable
Power Domain Switch-On
Pad Outputs On
Processor Low-Power Entry System Clock Switching
Peripheral Clocks Enable Processor Low-Power Exit
Processor & Memory Clock Disable
Clock Sources Without Dependencies Switch-Off FLASH Switch-Off Power Domain Switch-Off PAD Outputs Off Clock Sources With Dependencies Switch-Off
Main VREG Switch-Off
N
Target STANDBY0
Y
STANDBY0 Request
Current Mode Update
S_MTRANS = ‘0’
End
Figure 6-25. MC_ME Transition Diagram
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ANALOG OFF
DIGITAL CONTROL
ANALOG ON
Clock Sources Switch-On
Main VREG Switch-On
Chapter 6 Mode Entry Module (MC_ME)
6.4.4
Protection of Mode Configuration Registers
While programming the mode configuration registers ME__MC, the following rules must be respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be generated. • If the 16 MHz int. RC osc. is selected as the system clock, FIRC must be on. • If the div. 16 MHz int. RC osc. clock is selected as the system clock, RC must be on. • If the 4-16 MHz ext. xtal osc. clock is selected as the system clock, OSC must be on. • If the div. ext. xtal osc. clock is selected as the system clock, OSC must be on. • If the freq. mod. PLL clock is selected as the system clock, PLL must be on. NOTE Software must ensure that clock sources with dependencies other than those mentioned above are swithced on as needed. There is no automatic protection mechanism to check this in the MC_ME. • • • • Configuration “00” for the CFLAON and DFLAON bit fields is reserved. Configuration “10” for the DFLAON bit field is reserved. If the DFLAON bit field is set to “11”, the CFLAON field must also be set to “11”. MVREG must be on if any of the following is active: — CFLASH — DFLASH System clock configurations marked as ‘reserved’ may not be selected. Configuration “1111” for the SYSCLK bit field is allowed only for the STOP0 and TEST modes, and only in this case may all system clock sources be turned off. WARNING If the system clock is stopped during TEST mode, the device can exit only via a system reset.
• •
6.4.5
Mode Transition Interrupts
The MC_ME provides interrupts for incorrectly configuring a mode, requesting an invalid mode transition, indicating a SAFE mode transition not due to a software request, and indicating when a mode transition has completed.
6.4.5.1
Invalid Mode Configuration Interrupt
Whenever a write operation is attempted to the ME__MC registers violating the protection rules mentioned in the Section 6.4.4, “Protection of Mode Configuration Registers, the interrupt pending bit I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of ME_IM register is ‘1’.
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6.4.5.2
Invalid Mode Transition Interrupt
The mode transition request is considered invalid under the following conditions: • If the system is in the SAFE mode and the SAFE mode request from MC_RGM is active, and if the target mode requested is other than RESET or SAFE, then this new mode request is considered to be invalid, and the S_SEA bit of the ME_IMTS register is set. • If the TARGET_MODE bit field of the ME_MCTL register is written with a value different from the specified mode values (i.e., a non-existing mode), an invalid mode transition event is generated. When such a non existing mode is requested, the S_NMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the proper key mechanism is followed while writing the ME_MCTL register. • If some of the device modes are disabled as programmed in the ME_ME register, their respective configurations are considered reserved, and any access to the ME_MCTL register with those values results in an invalid mode transition request. When such a disabled mode is requested, the S_DMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the proper key mechanism is followed while writing the ME_MCTL register. • If the target mode is not a valid mode with respect to the current mode, the mode request illegal status bit S_MRI of the ME_IMTS register is set. This condition is detected only when the proper key mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation is ignored. • If further new mode requests occur while a mode transition is in progress (the S_MTRANS bit of the ME_GS register is ‘1’), the mode transition illegal status bit S_MTI of the ME_IMTS register is set. This condition is detected only when the proper key mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation is ignored. NOTE As the causes of invalid mode transitions may overlap at the same time, the priority implemented for invalid mode transition status bits of the ME_IMTS register in the order from highest to lowest is S_SEA, S_NMA, S_DMA, S_MRI, and S_MTI. As an exception, the mode transition request is not considered as invalid under the following conditions: • A new request is allowed to enter the RESET or SAFE mode irrespective of the mode transition status. • As the exit of HALT0 and STOP0 modes depends on the interrupts of the system which can occur at any instant, these requests to return to RUN0…3 modes are always valid. • In order to avoid any unwanted lockup of the device modes, software can abort a mode transition by requesting the parent mode if, for example, the mode transition has not completed after a software determined ‘reasonable’ amount of time for whatever reason. The parent mode is the device mode before a valid mode request was made. • Self-transition requests (e.g., RUN0 RUN0) are not considered as invalid even when the mode transition process is active (i.e., S_MTRANS is ‘1’). During the low-power mode exit process, if the system is not able to enter the respective RUN0…3 mode properly (i.e., all status bits of the ME_GS register match with configuration bits in the ME__MC register), then software
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can only request the SAFE or RESET mode. It is not possible to request any other mode or to go back to the low-power mode again. Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register is set, and an interrupt request is generated if the mask bit M_IMODE of the ME_IM register is ‘1’.
6.4.5.3
SAFE Mode Transition Interrupt
Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is generated if the mask bit M_SAFE of ME_IM register is ‘1’. The SAFE mode interrupt pending bit can be cleared only when the SAFE mode request is deasserted by the MC_RGM (see the MC_RGM chapter for details on how to clear a SAFE mode request). If the system is already in SAFE mode, any new SAFE mode request by the MC_RGM also sets the interrupt pending bit I_SAFE. However, the SAFE mode interrupt pending bit is not set when the SAFE mode is entered by a software request (i.e., programming of ME_MCTL register).
6.4.5.4
Mode Transition Complete interrupt
Whenever the system fully completes a mode transition (i.e., the S_MTRANS bit of ME_GS register transits from ‘1’ to ‘0’), the interrupt pending bit I_MTC of the ME_IS register is set, and an interrupt request is generated if the mask bit M_MTC of the ME_IM register is ‘1’. The interrupt bit I_MTC is not set when entering low-power modes HALT0 and STOP0 in order to avoid the same event requesting the immediate exit of these low-power modes.
6.4.6
Peripheral Clock Gating
During all device modes, each peripheral can be associated with a particular clock gating policy determined by two groups of peripheral configuration registers. The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the software running modes DRUN, TEST, SAFE, and RUN0…3. All configurations are programmable by software according to the needs of the application. Each configuration register contains a mode bit which determines whether or not a peripheral clock is to be gated. Run configuration selection for each peripheral is done by the RUN_CFG bit field of the ME_PCTL0…143 registers. The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during the low-power modes HALT0, STOP0, and STANDBY0. All configurations are programmable by software according to the needs of the application. Each configuration register contains a mode bit which determines whether or not a peripheral clock is to be gated. Low-power configuration selection for each peripheral is done by the LP_CFG bit field of the ME_PCTL0…143 registers. Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers do not affect the clock gating behavior until a new mode transition request is generated. Whenever the processor enters a debug session during any mode, the following occurs for each peripheral:
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•
The clock is gated if the DBG_F bit of the associated ME_PCTL0…143 register is set. Otherwise, the peripheral clock gating status depends on the RUN_CFG and LP_CFG bits. Any further modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers during a debug session will take affect immediately without requiring any new mode request.
6.4.7
Application Example
Figure 6-26 shows an example application flow for requesting a mode change and then waiting until the mode transition has completed.
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START of mode change
config for target mode okay?
N
Y
write ME__MC, ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers
write ME_MCTL with target mode and key
write ME_MCTL with target mode and inverted key
start timer
S_MTRANS cleared?
N
Y timer expired? stop timer Y mode change DONE
N
write ME_MCTL with current or SAFE mode and key
write ME_MCTL with current or SAFE mode and inverted key
Figure 6-26. MC_ME Application Example Flow Diagram
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Chapter 7 e200z0h Core
Chapter 7 e200z0h Core
7.1 Overview
The e200 processor family is a set of CPU cores that implement cost-efficient versions of the Power Architecture™ Book E architecture. e200 processors are designed for deeply embedded control applications which require low cost solutions rather than maximum performance. The e200z0h processors integrate an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the branch unit to allow single-cycle branches in some cases. The e200z0h core is a single-issue, 32-bit Power Architecture technology VLE-only design with 32-bit general purpose registers (GPRs). All arithmetic instructions that execute in the core operate on data in the general purpose registers (GPRs). Instead of the base Power Architecture technology support, the e200z0h core only implements the VLE (variable-length encoding) APU, providing improved code density.
7.2
Features
The following is a list of some of the key features of the e200z0h cores: • 32-bit Power Architecture Book E VLE-only programmer’s model • Single issue, 32-bit CPU • Implements the VLE APU for reduced code footprint • In-order execution and retirement • Precise exception handling • Branch processing unit — Dedicated branch address calculation adder — Branch acceleration using Branch Target Buffer • Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data bus interface units (BIUs) (e200z0h only). • Load/store unit — 1 cycle load latency — Fully pipelined — Big-endian support only — Misaligned access support — Zero load-to-use pipeline bubbles for aligned transfers • Power management
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•
— Low power design — Power saving modes: nap, sleep, and wait — Dynamic power management of execution units Testability — Synthesizeable, full MuxD scan design — ABIST/MBIST for optional memory arrays
7.2.1
Microarchitecture summary
The e200z0h processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), an 8x32 Hardware Multiplier array, result feed-forward hardware, and a hardware divider. Arithmetic and logical operations are executed in a single cycle with the exception of the divide and multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching from the BTB is performed to accelerate certain taken branches in the e200z0h. Prefetched instructions are placed into an instruction buffer with 4entries in e200z0h, each capable of holding a single 32-bit instruction or a pair of 16-bit instructions. Conditional branches which are not taken execute in a single clock. Branches with successful target prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an execution time of two clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture platform. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
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7.2.1.1
Block diagram
OnCE/NEXUS CONTROL LOGIC
CPU CONTROL LOGIC
LR SPR
CR
CTR XER
GPR
INTEGER EXECUTION UNIT
ADDRESS
INSTRUCTION BUS INTERFACE UNIT
INSTRUCTION UNIT INSTRUCTION BUFFER
MULTIPLY UNIT CONTROL EXTERNAL SPR INTERFACE (MTSPR/MFSPR)
DATA
32
CONTROL
32
DATA
PC UNIT
BRANCH UNIT
LOAD/ STORE UNIT
N
DATA BUS INTERFACE UNIT
32 ADDRESS DATA
32
N CONTROL
Figure 7-1. e200z0h block diagram
7.2.1.2
Instruction unit features
The features of the e200 Instruction unit are: • 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or up to two 16-bit VLE instructions per clock
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• • •
Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of 16-bit instructions Dedicated PC incrementer supporting instruction prefetches Branch unit with dedicated branch address adder supporting single cycle of execution of certain branches, two cycles for all others
7.2.1.3
Integer unit features
The e200 integer unit supports single cycle execution of most integer instructions: • 32-bit AU for arithmetic and comparison operations • 32-bit LU for logical operations • 32-bit priority encoder for count leading zero’s function • 32-bit single cycle barrel shifter for shifts and rotates • 32-bit mask unit for data masking and insertion • Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing • 8x32 hardware multiplier array supports 1 to 4 cycle 32x32->32 multiply (early out)
7.2.1.4
Load/Store unit features
The e200 load/store unit supports load, store, and the load multiple / store multiple instructions: • 32-bit effective address adder for data memory address calculations • Pipelined operation supports throughput of one load or store operation per cycle • 32-bit interface to memory (dedicated memory interface on e200z0h)
7.2.1.5
e200z0h system bus features
The features of the e200z0h system bus interface are as follows: • Independent instruction and data buses • AMBA1 AHB2 Lite Rev 2.0 specification with support for ARM v6 AMBA extensions — Exclusive access monitor — Byte lane strobes — Cache allocate support • 32-bit address bus plus attributes and control on each bus • 32-bit read data bus for instruction interface • Separate uni-directional 32-bit read data bus and 32-bit write data bus for data interface • Overlapped, in-order accesses
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7.2.1.6
Nexus 2+ features
The Nexus 2+ module is compliant with Class 2 of the IEEE-ISTO 5001-2003 standard, with additional Class 3 and Class 4 features available. The following features are implemented: • Program Trace via Branch Trace Messaging (BTM)—Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. • Ownership Trace via Ownership Trace Messaging (OTM)—OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An Ownership Trace Message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. • Run-time access to the processor memory map via the JTAG port. This allows for enhanced download/upload capabilities. • Watchpoint Messaging via the auxiliary interface • Watchpoint Trigger enable of Program Trace Messaging • Auxiliary interface for higher data input/output — Configurable (min/max) Message Data Out pins (nex_mdo[n:0]) — One (1) or two (2) Message Start/End Out pins (nex_mseo_b[1:0]) — One (1) Read/Write Ready pin (nex_rdy_b) pin — One (1) Watchpoint Event pin (nex_evto_b) — One (1) Event In pin (nex_evti_b) — One (1) MCKO (Message Clock Out) pin • Registers for Program Trace, Ownership Trace and Watchpoint Trigger control • All features controllable and configurable via the JTAG port
7.3
Core registers and programmer’s model
This section describes the registers implemented in the e200z0h cores. It includes an overview of registers defined by the Power Architecture platform, highlighting differences in how these registers are implemented in the e200 core, and provides a detailed description of e200-specific registers. Full descriptions of the architecture-defined register set are provided in Power Architecture Book E Specification. The Power Architecture™ Book E defines register-to-register operations for all computational instructions. Source data for these instructions are accessed from the on-chip registers or are provided as immediate values embedded in the opcode. The three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions. Data is transferred between memory and registers with explicit load and store instructions only. Figure 7-2, and Figure 7-1 show the e200 register set including the registers which are accessible while in supervisor mode, and the registers which are accessible in user mode. The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1).
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NOTE e200z0h is a 32-bit implementation of the Power Architecture™ Book E specification. In this document, register bits are sometimes numbered from bit 0 (Most Significant Bit) to 31 (Least Significant Bit), rather than the Book E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses.
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SUPERVISOR Mode Program Model SPRs General Registers
Condition Register CR Count Register CTR Link Register LR XER XER SPR 1 SPR 8 GPR31 SPR 9 General-Purpose Registers GPR0 GPR1
Exception Handling/Control Registers
SPR General SPRG0 SPRG1 SPR 272 SPR 273 Save and Restore SRR0 SRR1 CSRR0 CSRR1 DSRR01 DSRR11 SPR 26 SPR 27 SPR 58 SPR 59
SPR 574 SPR 575
Interrupt Vector Prefix IVPR SPR 63
Exception Syndrome ESR SPR 62 Machine Check Syndrome Register MCSR
SPR 572
Processor Control Registers
Machine State MSR Processor Version PVR Processor ID PIR SPR 286 SPR 287 Hardware Implementation Dependent1 HID0 SPR 1008 HID1 SPR 1009
Data Exception Address DEAR
SPR 61
BTB Register
BTB Control1 BUCSR SPR 1013
System Version1 SVR
SPR 1023
Memory Management Registers
Process ID PID0 SPR 48
Debug Registers2
Debug Control DBCR0 DBCR1 DBCR2 DBCR31 Debug Status DBSR SPR 304 SPR 308 SPR 309 SPR 310 SPR 561 Instruction Address Compare IAC1 IAC2 IAC3 IAC4 SPR 312 SPR 313 SPR 314 SPR 315
Configuration (read only)
MMUCFG
SPR 1015
Cache Registers
Cache Configuration (Read-only) L1CFG0 SPR 515
Data Address Compare DAC1 DAC2 DVC1 DVC2 SPR 316 SPR 317 SPR 318 SPR 319
1 - These e200-specific registers may not be supported by other Power Architecture processors. 2 - Optional registers defined by the Power Architecture technology 3 - Read-only registers
Figure 7-2. e200z0 SUPERVISOR Mode Program Model SPRs
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Chapter 8 Enhanced Direct Memory Access (eDMA)
Chapter 8 Enhanced Direct Memory Access (eDMA)
8.1
8.1.1
• • • • •
Device-specific information
Device-specific features
16 programmable channels to support independent 8, 16 or 32-bit single value or block transfers Support of variable sized queues and circular queues Source and destination address registers independently configured to post-incrementor remain constant Each transfer initiated by peripheral, CPU, periodic timer interrupt or eDMA channel request Peripheral eDMA request sources possible from: — DSPI — 12-bit ADC — eMIOS Each eDMA channel able to optionally send interrupt request to CPU on completion of single value or block transfer DMA transfers possible between system memories and all accessible memory mapped locations including peripheral and registers Programmable eDMA Channel Mux allows assignment of any eDMA source to any available eDMA channel with total of up to 32 request sources DMA supports the following functionality: — Scatter Gather — Channel Linking — Inner Loop Offset — Arbitration Fixed Group, fixed channel Round Robin Group, fixed channel Round Robin Group, Round Robin Channel Fixed Group, Round Robin Channel — Channel preemption — Cancel channel transfer Interrupts – The eDMA has a single interrupt request for each implemented channel and a combined eDMA Error interrupt to flag transfer errors to the system. Each channel eDMA interrupt can be enabled or disabled and provides notification of a completed transfer. Refer to the Interrupt Vector table of in the Interrupts chapter of the reference manual for the allocation of these interrupts.
• • • •
•
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8.1.2
Registers unavailable on this device
The following registers are unavailable on this device: • DMA Channel 16–63 Priority (DCHPRI16–DCHPRI63) • Transfer Control Descriptors 16–63 (TCD16–TCD63)
8.2
Introduction
The enhanced direct memory access controller (eDMA) is a second-generation platform block capable of performing complex data movements through 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture includes a DMA engine that performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation minimizes the overall block size. Figure 8-1 is a block diagram of the eDMA module.
eDMA
SRAM transfer control descriptor (TCD) Slave write address Slave write data
SRAM System bus
TCD0 Slave interface
TCDn-1* eDMA engine Bus read data Program model/ channel arbitration Address path Control Slave read data
Data path Bus write data Bus address
*n = 16 channels eDMA Peripheral Request eDMA Done
Figure 8-1. DMA block diagram
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8.2.1
Features
The eDMA module supports the following features: • All data movement via dual-address transfers: read from source, write to destination — Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes • Transfer control descriptor organized to support two-deep, nested transfer operations — An inner data transfer loop defined by a “minor” byte transfer count — An outer data transfer loop defined by a “major” iteration count • Channel service request via one of three methods: — Explicit software initiation — Initiation via a channel-to-channel linking mechanism for continuous transfers – Independent channel linking at end of minor loop and/or major loop — Peripheral-paced hardware requests (one per channel) — For all three methods, one service request per execution of the minor loop is required • Support for fixed-priority and round-robin channel arbitration • Channel completion reported via optional interrupt requests — One interrupt per channel, optionally asserted at completion of major iteration count — Error terminations are optionally enabled per channel, and logically summed together to form a small number of error interrupt outputs • Support for scatter/gather eDMA processing • Support for complex data structures • Support to cancel transfers via software or hardware
8.3
Memory map/register definition
The eDMA memory map is shown in Table 8-1. The address of each register is given as an offset to the eDMA base address. Registers are listed in address order, identified by complete name and mnemonic, and list the type of accesses allowed. The eDMA’s programming model is partitioned into two regions—the first region defines a number of registers providing control functions; the second region corresponds to the local transfer control descriptor memory. Table 8-2 is a 32-bit view of the eDMA’s memory map.
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Table 8-1. eDMA Memory Map
Offset from EDMA_BASE (0xFFF4_4000) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 – 0x01FC 0x0100 0x0101 Register Access Reset Value Section/Page Size
EDMA_CR — eDMA control register EDMA_ESR — eDMA error status register Reserved EDMA_ERQRL — eDMA enable request low register (channels 15–00) Reserved EDMA_EEIRL — eDMA enable error interrupt low register (channels 15–00) EDMA_SERQR — eDMA set enable request register EDMA_CERQR — eDMA clear enable request register EDMA_SEEIR — eDMA set enable error interrupt register EDMA_CEEIR — eDMA clear enable error interrupt register EDMA_CIRQR — eDMA clear interrupt request register EDMA_CER — eDMA clear error register EDMA_SSBR — eDMA set start bit register EDMA_CDSBR — eDMA clear done status bit register Reserved EDMA_IRQRL — eDMA interrupt request low register Reserved EDMA_ERL — eDMA error low register Reserved EDMA_HRSL — eDMA hardware request status register Reserved EDMA_CPR0 — eDMA channel 0 priority register EDMA_CPR1 — eDMA channel 1 priority register
R/W R
0x0000_0000 0x0000_0000
8.3.1.1/8-193 8.3.1.2/8-195
32 32
R/W
0x0000_0000
8.3.1.3/8-197
32
R/W W W W W W W W W
0x0000_0000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
8.3.1.4/8-198 8.3.1.5/8-199 8.3.1.6/8-200 8.3.1.7/8-200 8.3.1.8/8-200 8.3.1.9/8-201 8.3.1.10/8-201 8.3.1.11/8-202 8.3.1.12/8-202
32 8 8 8 8 8 8 8 8
R/W
0x0000_0000 8.3.1.13/8-203
32
R/W
0x0000_0000 8.3.1.14/8-204
32
R/W
0x0000_0000 8.3.1.15/8-205
32
R/W R/W
—1 —1
Table 8-16./8205 Table 8-16./8205
8 8
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Table 8-1. eDMA Memory Map (continued)
Offset from EDMA_BASE (0xFFF4_4000) 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010A 0x010B 0x010C 0x010D 0x010E 0x010F 0x0110 0x1000 0x1020 0x1040 0x1060 0x1080 0x10A0 0x10C0 0x10E0 Register Access Reset Value —1 —1 —1 —1 —1 —1 —1 —1 —1 —1 —1 —1 —1 —1 Section/Page Size
EDMA_CPR2 — eDMA channel 2 priority register EDMA_CPR3 — eDMA channel 3 priority register EDMA_CPR4 — eDMA channel 4 priority register EDMA_CPR5 — eDMA channel 5 priority register EDMA_CPR6 — eDMA channel 6 priority register EDMA_CPR7 — eDMA channel 7 priority register EDMA_CPR8 — eDMA channel 8 priority register EDMA_CPR9 — eDMA channel 9 priority register EDMA_CPR10 — eDMA channel 10 priority register EDMA_CPR11 — eDMA channel 11 priority register EDMA_CPR12 — eDMA channel 12 priority register EDMA_CPR13 — eDMA channel 13 priority register EDMA_CPR14 — eDMA channel 14 priority register EDMA_CPR15 — eDMA channel 15 priority register Reserved TCD00 — eDMA transfer control descriptor 00 TCD01 — eDMA transfer control descriptor 01 TCD02 — eDMA transfer control descriptor 02 TCD03 — eDMA transfer control descriptor 03 TCD04 — eDMA transfer control descriptor 04 TCD05 — eDMA transfer control descriptor 05 TCD06 — eDMA transfer control descriptor 06 TCD07 — eDMA transfer control descriptor 07
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205 Table 8-16./8205
8 8 8 8 8 8 8 8 8 8 8 8 8 8
R/W R/W R/W R/W R/W R/W R/W R/W
—1 —1 —1 —1 —1 —1 —1 —1
8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207
256 256 256 256 256 256 256 256
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Table 8-1. eDMA Memory Map (continued)
Offset from EDMA_BASE (0xFFF4_4000) 0x1100 0x1120 0x1140 0x1160 0x1180 0x11A0 0x11C0 0x11E0 0x1200
1
Register
Access Reset Value —1 —
1
Section/Page Size
TCD08 — eDMA transfer control descriptor 08 TCD09 — eDMA transfer control descriptor 09 TCD10 — eDMA transfer control descriptor 10 TCD11 — eDMA transfer control descriptor 11 TCD12 — eDMA transfer control descriptor 12 TCD13 — eDMA transfer control descriptor 13 TCD14 — eDMA transfer control descriptor 14 TCD15 — eDMA transfer control descriptor 15 Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207 8.3.1.17/8-207
256 256 256 256 256 256 256 256
—1 —
1
—1 —
1
—1 —1
Refer to the register description for the reset value.
Table 8-2. eDMA 32-bit memory map
DMA Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 DMA Set Enable Request (EDMA_SERQR) DMA Clear Interrupt Request (EDMA_CIRQR) Register DMA Control Register (EDMA_CR) DMA Error Status (EDMA_ESR) Reserved DMA Enable Request Low (EDMA_ERQRL, Channels 15-0) Reserved DMA Enable Error Interrupt Low (EDMA_EEIRL, Channels 15-0) DMA Clear Enable Request (EDMA_CERQR) DMA Clear Error (EDMA_CER) DMA Set Enable Error Interrupt (EDMA_SEEIR) DMA Set Start Bit (EDMA_SSBR) Reserved DMA Interrupt Request Low (EDMA_IRQRL, Channels 15-0) Reserved DMA Error Low (EDMA_ERL, Channels 15-0) Reserved DMA Hardware Request Status Low (EDMA_HRSL, Channels 15-0) Reserved DMA Channel 0 Priority (EDMA_CPR0) DMA Channel 4 Priority (EDMA_CPR4) DMA Channel 1 Priority (EDMA_CPR1) DMA Channel 5 Priority (EDMA_CPR5) DMA Channel 2 Priority (EDMA_CPR2) DMA Channel 6 Priority (EDMA_CPR6) DMA Channel 3 Priority (EDMA_CPR3) DMA Channel 7 Priority (EDMA_CPR7) DMA Clear Enable Error Interrupt (EDMA_CEEIR) DMA Clear Done Status Bit (EDMA_CDSBR)
0x001C
0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 – 0x00FC 0x0100
0x0104
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Table 8-2. eDMA 32-bit memory map (continued)
DMA Offset 0x0108 DMA Channel 8 Priority (EDMA_CPR8) DMA Channel 12 Priority (EDMA_CPR12) Register DMA Channel 9 Priority (EDMA_CPR9) DMA Channel 13 Priority (EDMA_CPR13) DMA Channel 10 Priority (EDMA_CPR10) DMA Channel 14 Priority (EDMA_CPR14) DMA Channel 11 Priority (EDMA_CPR11) DMA Channel 15 Priority (EDMA_CPR15)
0x010C
0x0110 – 0x011C 0x0120 – 0x013C 0x0140 – 0x0FFC 0x1000 – 0x11FC 0x1200 – 0x17FC
Reserved Reserved Reserved TCD00-TCD15 Reserved
8.3.1
8.3.1.1
Register descriptions
DMA Control Register (EDMA_CR)
The 32-bit EDMA_CR defines the basic operating configuration of the eDMA. Arbitration among the channels can be configured to use a fixed priority or a round robin. In fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The priorities are assigned by the channel priority registers (see Section 8.3.1.16, “DMA Channel n Priority (EDMA_CPRn)”). In round-robin arbitration mode, the channel priorities are ignored and the channels are cycled through, from channel 15 down to channel 0, without regard to priority. See Figure 8-2 and Table 8-3 for the EDMA_CR definition.
Register address: EDMA_Offset + 0x0000 (EDMA_CR) R W RESET: R W RESET: 0 0 0 16 0 0 1 0 0 17 0 0 2 0 0 18 0 0 3 0 0 19 0 0 4 0 0 20 0 0 5 0 0 21 0 0 6 0 0 7 0 0 EMLM 8 0 0 24 9 0 0 25 CLM 10 0 0 26 HALT 11 0 0 27 HOE ERGA 12 0 0 28 ERCA 13 0 0 29 EDBG 14 CX 0 30 15 ECX 0 31 EBW 0 0
22 23 GRP0PRI 0 0
0
0
0
0
0
0
= Unimplemented
Figure 8-2. DMA Control Register (EDMA_CR)
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Table 8-3. DMA Control Register (EDMA_CR) field descriptions
Name CX Description Cancel Transfer 0 1 Value Normal operation. Cancel the remaining data transfer. Stop the executing channel and force the minor loop to be finished. The cancel takes effect after the last write of the current read/write sequence. The CXFR bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
ECX
Error Cancel Transfer
0 Normal operation. 1 Cancel the remaining data transfer in the same fashion as the CX cancel transfer. Stop the executing channel and force the minor loop to be finished. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel has been honored. In addition to cancelling the transfer, the ECX treats the cancel as an error condition; thus updating the EDMA_ESR register and generating an optional error interrupt (see Section 8.3.1.2, “DMA Error Status (EDMA_ESR)”). Group 0 priority level when fixed priority group arbitration is enabled. Minor loop mapping disabled. TCDn.word2 is defined as a 32-bit nbytes field. 1 Minor loop mapping enabled. When set, TCDn.word2 is redefined to include individual enable fields, an offset field and the nbytes field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The nbytes field is reduced when either offset is enabled. A minor loop channel link made to itself will go through channel arbitration before being activated again. 1 A minor loop channel link made to itself will not go through channel arbitration before being activated again. Upon minor loop completion the channel will active again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. 0 1 Normal operation. Stall the start of any new channels. Executing channels are allowed to complete. Channel execution will resume when the HALT bit is cleared. Normal operation. Any error will cause the HALT bit to be set. Subsequently, all service requests will be ignored until the HALT bit is cleared. 0 0
GRP0PRI EMLM
Channel Group 0 Priority Enable Minor Loop Mapping
CLM
Continuous Link Mode
HALT
Halt DMA Operations
HOE
Halt On Error
0 1
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Table 8-3. DMA Control Register (EDMA_CR) field descriptions (continued)
Name ERGA Description Enable Round Robin Group Arbitration Value 0 Fixed priority arbitration is used for selection among the groups. 1 Round robin arbitration is used for selection among the groups. Fixed priority arbitration is used for channel selection within each group. 1 Round robin arbitration is used for channel selection within each group.
ERCA
Enable Round Robin Channel Arbitration 0
EDBG
Enable Debug
0 The assertion of the device debug mode is ignored. 1 The assertion of the device debug mode causes the eDMA to stall the start of a new channel. Executing channels are allowed to complete. Channel execution will resume when either the device comes out of debug mode or the EDBG bit is cleared. 0 The bufferable write signal (hprot[2]) is not asserted during AMBA AHB writes. 1 The bufferable write signal (hprot[2]) is asserted on all AMBA AHB writes except for the last write sequence.
EBW
Enable Buffered Writes
8.3.1.2
DMA Error Status (EDMA_ESR)
The EDMA_ESR provides information about the last recorded channel error. Channel errors can be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle. A configuration error is caused when the starting source or destination address, source or destination offsets, minor loop byte count, and the transfer size represent an inconsistent state. The addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destination transfer sizes. All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. In fixed-arbitration mode, a configuration error is generated when any two channel priority levels are equal and any channel is activated. The ERRCHN field is undefined for this type of error. All channel priority levels must be unique before any service requests are made. If a scatter-gather operation is enabled on channel completion, a configuration error is reported if the scatter-gather address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking is enabled on channel completion, a configuration error is reported when the link is attempted if the TCD.CITER.E_LINK bit is not equal to the TCD.BITER.E_LINK bit. All configuration error conditions except scatter-gather and minor loop link error are reported as the channel is activated and assert an error interrupt request if enabled. When properly enabled, a scatter-gather configuration error is reported when the scatter-gather operation begins at major loop completion. A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated by the DMA engine with the current source address, destination address, and minor loop byte count at the
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point of the fault. If a bus error occurs on the last read prior to beginning the write sequence, the write will execute using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence will execute before the channel is terminated due to the destination bus error. The occurrence of any type of error causes the DMA engine to stop the active channel and the appropriate channel bit in the eDMA error register to be asserted. At the same time, the details of the error condition are loaded into the EDMA_ESR. The major loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the DMA engine continues to operate by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel will execute and terminate with the same error condition.
Register address: EDMA_Offset + 0x0004 (EDMA_ESR) 0 R VLD W RESET: 0 16 0 0 1 0 0 17 CPE 0 2 0 0 18 3 0 0 19 4 0 0 5 0 0 6 0 0 7 0 0 23 8 0 0 9 0 0 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0
R W RESET:
20 21 22 ERRCHN[0:5] 0 0 0
24 25 26 27 28 29 30 31 SAE SOE DAE DOE NCE SGE SBE DBE 0 0 0 0 0 0 0 0
0
0
0
= Unimplemented
Figure 8-3. DMA Error Status (EDMA_ESR) Register Table 8-4. DMA Error Status (EDMA_ESR) field descriptions
Name VLD Description Value
Logical OR of all EDMA_ERL status bits. 0 No EDMA_ERL bits are set. 1 At least one EDMA_ERL bit is set indicating a valid error exists that has not been cleared. Channel Priority Error 0 No channel priority error. 1 The last recorded error was a configuration error in the channel priorities within a group. All channel priorities within a group are not unique. The channel number of the last recorded error (excluding GPE and CPE errors) or last recorded transfer that was error cancelled. 0 1 No source address configuration error. The last recorded error was a configuration error detected in the TCD.saddr field. TCD.saddr is inconsistent with TCD.ssize. No source offset configuration error. The last recorded error was a configuration error detected in the TCD.soff field. TCD.soff is inconsistent with TCD.ssize.
CPE
ERRCHN[0:5]
Error Channel Number or Cancelled Channel Number Source Address Error
SAE
SOE
Source Offset Error
0 1
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Table 8-4. DMA Error Status (EDMA_ESR) field descriptions (continued)
Name DAE Description Destination Address Error 0 1 Value No destination address configuration error. The last recorded error was a configuration error detected in the TCD.daddr field. TCD.daddr is inconsistent with TCD.dsize. No destination offset configuration error. The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff is inconsistent with TCD.dsize. No nbytes/citer configuration error. The last recorded error was a configuration error detected in the TCD.nbytes or TCD.citer fields. TCD.nbytes is not a multiple of TCD.ssize and TCD.dsize, or TCD.citer is equal to zero, or TCD.citer.e_link is not equal to TCD.biter.e_link. No scatter/gather configuration error. The last recorded error was a configuration error detected in the TCD.dlast_sga field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCD.e_sg is enabled. TCD.dlast_sga is not on a 32 byte boundary.
DOE
Destination Offset Error
0 1
NCE
Nbytes/Citer Configuration Error
0 1
SGE
Scatter/Gather Configuration Error
0 1
SBE
Source Bus Error
0 No source bus error. 1 The last recorded error was a bus error on a source read. 0 1 No destination bus error. The last recorded error was a bus error on a destination write.
DBE
Destination Bus Error
8.3.1.3
DMA Enable Request (EDMA_ERQRL)
The EDMA_ERQRL provides a bit map for the 16 channels to enable the request signal for each channel. EDMA_ERQRL maps to channels 15–0. The state of any given channel enable is directly affected by writes to this register; the state is also affected by writes to the EDMA_SERQR, and EDMA_CERQR registers. The EDMA_CERQR and EDMA_SERQR registers are provided so the request enable for a single channel can be modified without performing a read-modify-write sequence to the EDMA_ERQRL register. Both the eDMA request input signal and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the eDMA enable request flag does not affect a channel service request made through software or a linked channel request.
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Register address: EDMA_Offset +0x000C (EDMA_ERQRL) 0 R W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 ERQ15 R W RESET:
17 ERQ14
18 ERQ13
19 ERQ12
20 ERQ11
21 ERQ10
22 ERQ09
23 ERQ08
24 ERQ07
25 ERQ06
26 ERQ05
27 ERQ04
28 ERQ03
29 ERQ02
30 ERQ01 0
31 ERQ00 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-4. DMA Enable Request (EDMA_ERQRL) Registers Table 8-5. DMA Enable Request (EDMA_ERQRL) field descriptions
Name ERQn Description Enable eDMA Request n 0 1 Value The eDMA request signal for channel n is disabled. The eDMA request signal for channel n is enabled.
As a given channel completes the processing of its major iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the EDMA_ERQRL bit for that channel. If the TCD.d_req bit is set, then the corresponding EDMA_ERQRL bit is cleared, disabling the eDMA request; else if the d_req bit is cleared, the state of the EDMA_ERQRL bit is unaffected.
8.3.1.4
DMA Enable Error Interrupt (EDMA_EEIRL)
The EDMA_EEIRL provides a bit map for the 16 channels to enable the error interrupt signal for each channel. EDMA_EEIRL maps to channels 15–0. The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is also affected by writes to the EDMA_SEEIR and EDMA_CEEIR registers. The EDMA_SEEIR and EDMA_CEEIR registers are provided so that the error interrupt enable for a single channel can be modified without the performing a read-modify-write sequence to the EDMA_EEIRL register. Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. See Figure 8-5 and Table 8-6 for the EDMA_EEIRL definition.
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Register address: EDMA_Offset + 0x0014 (EDMA_EEIRL) 0 R W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 EEI15 R W RESET:
17 EEI14
18 EEI13
19 EEI12
20 EEI11
21 EEI10
22 EEI09
23 EEI08
24 EEI07
25 EEI06
26 EEI05
27 EEI04
28 EEI03
29 EEI02
30 EEI01 0
31 EEI00 0 7 0 0 199
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-5. DMA Enable Error Interrupt (EDMA_EEIRL) Register Table 8-6. DMA Enable Error Interrupt (EDMA_EEIRL) field descriptions
Name EEIn Description Enable Error Interrupt n Value 0 The error signal for channel n does not generate an error interrupt. 1 The assertion of the error signal for channel n generate an error interrupt request.
8.3.1.5
DMA Set Enable Request (EDMA_SERQR)
The EDMA_SERQR provides a simple memory-mapped mechanism to set a given bit in the EDMA_ERQRL to enable the eDMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQRL to be set. Setting bit 1 (SERQ[0]) provides a global set function, forcing the entire contents of EDMA_ERQRL to be asserted. Reads of this register return all zeroes.
Register address: EDMA_Offset + 0x0018 (EDMA_SERQR) R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 SERQ[0:6] 0 5 0 0 6 0 0
= Unimplemented
Figure 8-6. DMA Set Enable Request (EDMA_SERQR) Register Table 8-7. DMA Set Enable Request (EDMA_SERQR) field descriptions
Name SERQ[0:6] Description Set Enable Request Value 0- Set the corresponding bit in EDMA_ERQRL 64-127 Set all bits in EDMA_ERQRL
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8.3.1.6
DMA Clear Enable Request (EDMA_CERQR)
The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERQRL to disable the eDMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1 (CERQ[0]) provides a global clear function, forcing the entire contents of the EDMA_ERQRL to be zeroed, disabling all eDMA request inputs. Reads of this register return all zeroes. See Figure 8-7 and Table 8-8 for the EDMA_CERQR definition.
Register address: EDMA_Offset + 0x0019 (EDMA_CERQR) R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 CERQ[0:6] 0 5 0 0 6 0 0 7 0 0
= Unimplemented
Figure 8-7. DMA Clear Enable Request (EDMA_CERQR) Register Table 8-8. DMA Clear Enable Request (EDMA_CERQR) field descriptions
Name CERQ[0:6] Description Clear Enable Request Value 0-63 Clear corresponding bit in EDMA_ERQRL 64-127 Clear all bits in EDMA_ERQRL
8.3.1.7
DMA Set Enable Error Interrupt (EDMA_SEEIR)
The EDMA_SEEIR provides a memory-mapped mechanism to set a given bit in the EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEI[0]) provides a global set function, forcing the entire contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes. See Figure 8-8 and Table 8-9 for the EDMA_SEEIR definition.
Register address: EDMA_Offset + 0x001A (EDMA_SEEIR) R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 SEEI[0:6] 0 5 0 0 6 0 0 7 0 0
= Unimplemented
Figure 8-8. DMA Set Enable Error Interrupt (EDMA_SEEIR) Register Table 8-9. DMA Set Enable Error Interrupt (EDMA_SEEIR) field descriptions
Name SEEI[0:6] Description Set Enable Error Interrupt Value 0-63 Set the corresponding bit in EDMA_EEIRL 64-127 Set all bits in EDMA_EEIRL
8.3.1.8
DMA Clear Enable Error Interrupt (EDMA_CEEIR)
The EDMA_CEEIR provides a memory-mapped mechanism to clear a given bit in the EDMA_EEIRL to disable the error interrupt for a given channel. The data value on a register write causes the corresponding
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bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEI[0]) provides a global clear function, forcing the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of this register returns all zeroes. See Figure 8-9 and Table 8-10 for the EDMA_CEEIR definition.
Register address: EDMA_Offset + 0x001B (EDMA_CEEIR) R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 CEEI[0:6] 0 5 0 0 6 0 0 7 0 0
= Unimplemented
Figure 8-9. DMA Clear Enable Error Interrupt (EDMA_CEEIR) Register Table 8-10. DMA Clear Enable Error Interrupt (EDMA_CEEIR) field descriptions
Name CEEI[0:6] Description Clear Enable Error Interrupt Value 0-63 Clear corresponding bit in EDMA_EEIRL 64-127 Clear all bits in EDMA_EEIRL
8.3.1.9
DMA Clear Interrupt Request (EDMA_CIRQR)
The EDMA_CIRQR provides a memory-mapped mechanism to clear a given bit in the EDMA_IRQRL to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1 (CINT[0]) provides a global clear function, forcing the entire contents of the EDMA_IRQRL to be zeroed, disabling all eDMA interrupt requests. Reads of this register return all zeroes. See Figure 8-10 and Table 8-11 for the EDMA_CIRQR definition.
Register address: EDMA_Offset + 0x001C R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 CINT[0:6] 0 5 0 0 6 0 0 7 0 0
= Unimplemented
Figure 8-10. DMA Clear Interrupt Request (EDMA_CIRQR) Fields Table 8-11. DMA Clear Interrupt Request (EDMA_CIRQR) field descriptions
Name CINT[0:6] Description Clear Interrupt Request Value 0-63 Clear the corresponding bit in EDMA_IRQRL 64-127 Clear all bits in EDMA_IRQRL
8.3.1.10
DMA Clear Error (EDMA_CER)
The EDMA_CER provides a memory-mapped mechanism to clear a given bit in the EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the EDMA_ERL to be cleared. Setting bit 1 (CERR[0]) provides a global clear function, forcing the entire contents of the EDMA_ERL to be zeroed, clearing all channel error indicators. Reads of this register return all zeroes. See Figure 8-11 and Table 8-12 for the EDMA_CER definition.
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Register address: EDMA_Offset + 0x001E (EDMA_CER) R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 CERR[0:6] 0 5 0 0 6 0 0 7 0 0
= Unimplemented
Figure 8-11. DMA Clear Error (EDMA_CER) Register Table 8-12. DMA Clear Error (EDMA_CER) field descriptions
Name CERR[0:6] Description Clear Error Indicator Value 0-63 Clear corresponding bit in EDMA_ERL 64-127 Clear all bits in EDMA_ERL
8.3.1.11
DMA Set START Bit (EDMA_SSBR)
The EDMA_SSBR provides a memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting bit 1 (SSB[0]) provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. See Table 8-20 for the TCD START bit definition.
Register address: EDMA_Offset + 0x001E R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 SSRT[0:6] 0 5 0 0 6 0 0 7 0 0
= Unimplemented
Figure 8-12. DMA Set START Bit (EDMA_SSBR) Register Table 8-13. DMA Set START Bit (EDMA_SSBR) field descriptions
Name SSRT[0:6] Description Set START Bit (Channel Service Request) Value 0-63 Set the corresponding channel’s TCD.start 64-127 Set all TCD.start bits
8.3.1.12
DMA Clear DONE Status (EDMA_CDSBR)
The EDMA_CDSBR provides a memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting bit 1 (CDSB[0]) provides a global clear function, forcing all DONE bits to be cleared. See Table 8-20 for the TCD DONE bit definition.
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Register address: EDMA_Offset + 0x001F (EDMA_CDSBR) R W RESET: 0 0 0 1 0 0 2 0 0 3 0 0 4 0 CDNE[0:6] 0 5 0 0 6 0 0 7 0 0
= Unimplemented
Figure 8-13. DMA Clear DONE Status (EDMA_CDSBR) Register Table 8-14. DMA Clear DONE Status (EDMA_CDSBR) field descriptions
Name CDNE[0:6] Description Clear DONE Status Bit Value 0-63 Clear the corresponding channel’s DONE bit 64-127 Clear all TCD DONE bits
8.3.1.13
DMA Interrupt Request (EDMA_IRQRL)
The EDMA_IRQRL provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel. EDMA_IRQRL maps to channels 15–0. The DMA engine signals the occurrence of a programmed interrupt on the completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt service routine associated with any given channel, software must clear the appropriate bit, negating the interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine is used for this purpose. The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRL, a 1 in any bit position clears the corresponding channel’s interrupt request. A 0 in any bit position has no affect on the corresponding channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt request for a single channel can be cleared without performing a read-modify-write sequence to the EDMA_IRQRL. See Figure 8-14 and Table 8-15 for the EDMA_IRQL definition.
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Register address: EDMA_Offset + 0x0024 (EDMA_IRQRL) 0 R W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 INT15 R W RESET:
17 INT14
18 INT13
19 INT12
20 INT11
21 INT10
22 INT09
23 INT08
24 INT07
25 INT06
26 INT05
27 INT04
28 INT03
29 INT02
30 INT01 0
31 INT00 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-14. DMA Interrupt Request (EDMA_IRQRL) Registers Table 8-15. DMA Interrupt Request (EDMA_IRQRL) field descriptions
Name INTn Description DMA Interrupt Request n 0 1 Value The interrupt request for channel n is cleared. The interrupt request for channel n is active.
8.3.1.14
DMA Error (EDMA_ERL)
The EDMA_ERL provides a bit map for the 16 channels signaling the presence of an error for each channel. EDMA_ERL maps to channels 15-0. The DMA engine signals the occurrence of a error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across 16 channels to form an error interrupt request, which is then routed to the interrupt controller. During the execution of the interrupt service routine associated with any eDMA errors, it is software’s responsibility to clear the appropriate bit, negating the error interrupt request. Typically, a write to the EDMA_CER in the interrupt service routine is used for this purpose. The normal eDMA channel completion indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. The contents of this register can also be polled and a non-zero value indicates the presence of a channel error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in this register and it provides a single bit indication of any errors. The state of any given channel’s error indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes to EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CER is provided so the error indicator for a single channel can be cleared. See Figure 8-15 and Table 8-16 for the EDMA_ERL definition.
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Register address: EDMA_Offset + 0x002C (EDMA_ERL) 0 R W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 ERR15 R W RESET:
17 ERR14
18 ERR13
19 ERR12
20 ERR11
21 ERR10
22 ERR09
23 ERR08
24 ERR07
25 ERR06
26 ERR05
27 ERR04
28 ERR03
29 ERR02
30 ERR01 0
31 ERR00 0 205
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-15. DMA Error (EDMA_ERL) Registers Table 8-16. DMA Error (EDMA_ERL) field descriptions
Name ERRn Description DMA Error n 0 1 Value An error in channel n has not occurred. An error in channel n has occurred.
8.3.1.15
DMA Hardware Request Status (EDMA_HRSL)
The EDMA_HRSL register provides a bit map for the implemented channels to show the current hardware request status for each channel. This view into the hardware request signals may be used for debug purposes. See Figure 8-16 and Figure 8-17 for the EDMA_HRSL definition.
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Register address: EDMA_Offset + 0x0034 (EDMA_HRSL) 0 R W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 HRS15 R W RESET:
17 HRS14
18 HRS13
19 HRS12
20 HRS11
21 HRS10
22 HRS09
23 HRS08
24 HRS07
25 HRS06
26 HRS05
27 HRS04
28 HRS03
29 HRS02
30 HRS01 0
31 HRS00 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-16. DMA Hardware Request Status (EDMA_HRSL) Register
Table 8-17. DMA Hardware Request Status (EDMA_HRSL) field descriptions
Name HRSn Description DMA Hardware Request Status n 0 Value A hardware service request for channel n is not present. 1 A hardware service request for channel n is present. Note: The hardware request status reflects the state of the request as seen by the arbitration logic. Therefore, this status is affected by the EDMA_ERQRL[n] bit.
8.3.1.16
DMA Channel n Priority (EDMA_CPRn)
When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel. The channel priorities are evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. If software modifies channel priority values, then the software must ensure that the channel priorities contain unique values, otherwise a configuration error will be reported. The range of the priority value is limited to the values of 0 through 15. Channel preemption is enabled on a per-channel basis by setting the ECP bit in the EDMA_CPRn register. Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. After the restored channel completes one read/write sequence, it is again eligible for preemption. If any higher priority channel requests service, the restored channel will be suspended and the higher priority channel will be serviced. Nested preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel begins
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execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected for channel arbitration mode A channel’s ability to preempt another channel can be disabled by setting the DPA bit in the EDMA_CPRn register. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of low priority, large data moving channels to be defined. These low priority channels can be configured to not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally available a true, high priority channel. See Figure 8-17 and Table 8-18 for the EDMA_CPRn definition.
Register address: EDMA_Offset + 0x100 + n (EDMA_CPRn) R W RESET: 0 ECP 0 1 DPA 0 2 3 GRPPRI[0:1] * * 4 5 6 CHPRI[0:3] * * 7
*
*
*
= Unimplemented, = defaults to channel number (n) after reset
Figure 8-17. DMA Channel n Priority (EDMA_CPRn) Register Table 8-18. DMA Channel n Priority (EDMA_CPRn) field descriptions
Name ECP Description Enable Channel Preemption Value 0 Channel n cannot be suspended by a higher priority channel’s service request. 1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0 Channel n can suspend a lower priority channel. 1 Channel n cannot suspend any channel, regardless of channel priority. Channel priority when fixed-priority arbitration is enabled.
DPA
Disable Preempt Ability
CHPRI[0:3]
Channel n Arbitration Priority
8.3.1.17
Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 15. The definitions of the TCD are presented as eight 32-bit values. Table 8-19 is a field list of the basic TCD structure.
Table 8-19. TCDn 32-bit Memory Structure
eDMA Offset 0x1000+(32 x n)+0x0000 0x1000+(32 x n)+0x0004 0x1000+(32 x n)+0x0008 0x1000+(32 x n)+0x000C 0x1000+(32 x n)+0x0010 Transfer attributes TCDn Field Source address (saddr) Signed source address offset (soff) Inner minor byte count (nbytes) Last source address adjustment (slast) Destination address (daddr)
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Table 8-19. TCDn 32-bit Memory Structure (continued)
eDMA Offset 0x1000+(32 x n)+0x0014 0x1000 (32 x n) 0x0018 0x1000+(32 x n)+0x001c Current major iteration count (citer) TCDn Field Signed destination address offset (doff)
Last destination address adjustment / scatter-gather address (dlast_sga) Beginning major iteration count (biter) Channel control/status
Figure 8-18 and Table 8-20 define the fields of the TCDn structure.
Word Offset 0x0000 0x0004 0x0008 DMLOE1 SMLOE1 0x8 0x000C 0x0010 CITER.E_ LINK SMOD SSIZE DMOD
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SADDR DSIZE NBYTES1 MLOFF or NBYTES 1 SLAST DADDR NBYTES1 SOFF
0x0014
CITER or CITER.LINKCH
CITER
DOFF
0x0018 BITER.E_ LINK
DLAST_SGA MAJOR.E_LINK INT_HALF INT_MAJ
ACTIVE
D_REQ
0x001C
BITER or BITER.LINKCH
BITER
BWC
MAJOR LINKCH
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15 16 17 18 19 20
21 22 23 24 25 26 27
28 29 30 31
Figure 8-18. TCD Structure
1
The fields implemented in Word 2 depend on whether EDMA_CR(EMLM) is set to 0 or 1. Refer to Table 8-3.
NOTE The TCD structures for the eDMA channels shown in Figure 8-18 are implemented in internal SRAM. These structures are not initialized at reset; therefore, all channel TCD parameters must be initialized by the application code before activating that channel.
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START
DONE
E_SG
Chapter 8 Enhanced Direct Memory Access (eDMA)
Table 8-20. TCDn Field Descriptions
Bits / Word Offset [n:n] 0–31 / 0x0 [0:31] 32–36 / 0x4 [0:4] Name Description
SADDR [0:31] SMOD [0:4]
Source address. Memory address pointing to the source data. Word 0x0, bits 0–31. Source address modulo. 0 Source address modulo feature is disabled. non-0 This value defines a specific address range that is specified to be the value after SADDR + SOFF calculation is performed or the original register value. The setting of this field provides the ability to easily implement a circular data queue. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits that are allowed to change. For this circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. Source data transfer size. 000 8-bit 001 16-bit 010 32-bit 011 Reserved 100 16-byte (32-bit, 4-beat, WRAP4 burst) 101 32-byte (32-bit, 8 beat, WRAP8 burst) 110 Reserved 111 Reserved The attempted specification of a reserved encoding causes a configuration error. Destination address modulo. See the SMOD[0:5] definition. Destination data transfer size. See the SSIZE[0:2] definition. Source address signed offset. Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. Inner “minor” byte transfer count. Number of bytes to be transferred in each service request of the channel. As a channel is activated, the contents of the appropriate TCD is loaded into the DMA engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. This is an indivisible operation and cannot be stalled or halted. After the minor count is exhausted, the current values of the SADDR and DADDR are written back into the local memory, the major iteration count is decremented and restored to the local memory. If the major iteration count is completed, additional processing is performed. Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 GB transfer.
37–39 / 0x4 [5:7]
SSIZE [0:2]
40–44 / 0x4 [8:12] 45–47 / 0x4 [13:15] 48–63 / 0x4 [16:31] 64–95 / 0x8 [0:31]
DMOD [0:4] DSIZE [0:2] SOFF [0:15] NBYTES [0:31]
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Table 8-20. TCDn Field Descriptions (continued)
Bits / Word Offset [n:n] 64–95 / 0x8 [0:31] Name NBYTES1 [0:31] Description
Inner “minor” byte transfer count. Number of bytes to be transferred in each service request of the channel. As a channel is activated, the contents of the appropriate TCD is loaded into the eDMA engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. This is an indivisible operation and cannot be stalled or halted. Once the minor count is exhausted, the current values of the SADDR and DADDR are written back into the local memory, the major iteration count is decremented and restored to the local memory. If the major iteration count is completed, additional processing is performed. Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 Gbyte transfer. Source minor loop offset enable This flag selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 1 The minor loop offset is not applied to the saddr. The minor loop offset is applied to the saddr.
64 0x8 [0]
SMLOE 1 0
65 0x8 [1]
DMLOE 1 1
Destination minor loop offset enable This flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 1 The minor loop offset is not applied to the daddr. The minor loop offset is applied to the daddr.
66–85 0x8 [2-21]
MLOFF or NBYTES 1 [0:19]
Inner “minor” byte transfer count or Minor loop offset If both SMLOE and DMLOE are cleared, this field is part of the byte transfer count. If either SMLOE or DMLOE are set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop is completed.
86–95 / 0x8 [22:31]
NBYTES 1
Inner “minor” byte transfer count. Number of bytes to be transferred in each service request of the channel. As a channel is activated, the contents of the appropriate TCD is loaded into the eDMA engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. This is an indivisible operation and cannot be stalled or halted. Once the minor count is exhausted, the current values of the SADDR and DADDR are written back into the local memory, the major iteration count is decremented and restored to the local memory. If the major iteration count is completed, additional processing is performed. Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 GByte transfer. Last source address adjustment. Adjustment value added to the source address at the completion of the outer major iteration count. This value can be applied to “restore” the source address to the initial value, or adjust the address to reference the next data structure. Destination address. Memory address pointing to the destination data.
96–127 / 0xC [0:31]
SLAST [0:31]
128–159 / 0x10 [0:31]
DADDR [0:31]
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Table 8-20. TCDn Field Descriptions (continued)
Bits / Word Offset [n:n] 160 / 0x14 [0] Name Description
CITER.E_LINK
Enable channel-to-channel linking on minor loop completion. As the channel completes the inner minor loop, this flag enables the linking to another channel, defined by CITER.LINKCH[0:5]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD.START bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR.E_LINK channel linking. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. Note: This bit must be equal to the BITER.E_LINK bit otherwise a configuration error will be reported.
161–166 / 0x14 [1:6]
CITER [0:5] or CITER.LINKCH [0:5]
Current major iteration count or link channel number. If channel-to-channel linking is disabled (TCD.CITER.E_LINK = 0), then • No channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. TCD bits [161:175] are used to form a 15-bit CITER field. Otherwise, • After the minor loop is exhausted, the DMA engine initiates a channel service request at the channel defined by CITER.LINKCH[0:5] by setting that channel’s TCD.START bit. Current major iteration count. This 9 or 15-bit count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (for example, final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count (BITER) field. Note: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. Destination address signed Offset. Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed.
167–175 / 0x14 [7:15]
CITER [6:14]
176–191 / 0x14 [16:31]
DOFF [0:15]
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Table 8-20. TCDn Field Descriptions (continued)
Bits / Word Offset [n:n] 192–223 / 0x18 [0:31] Name Description
DLAST_SGA [0:31]
Last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter-gather). If scatter-gather processing for the channel is disabled (TCD.E_SG = 0) then • Adjustment value added to the destination address at the completion of the outer major iteration count. This value can be applied to restore the destination address to the initial value, or adjust the address to reference the next data structure. Otherwise, • This address points to the beginning of a 0-modulo-32 byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter-gather address must be 0-modulo-32 byte, otherwise a configuration error is reported. Enables channel-to-channel linking on minor loop complete. As the channel completes the inner minor loop, this flag enables the linking to another channel, defined by BITER.LINKCH[0:5]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD.START bit of the specified channel. If channel linking is disabled, the BITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR.E_LINK channel linking. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field, otherwise a configuration error will be reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. Starting major iteration count or link channel number. If channel-to-channel linking is disabled (TCD.BITER.E_LINK = 0), then • No channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. TCD bits [225:239] are used to form a 15-bit BITER field. Otherwise, • After the minor loop is exhausted, the DMA engine initiates a channel service request at the channel, defined by BITER.LINKCH[0:5], by setting that channel’s TCD.START bit. Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field, otherwise a configuration error will be reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. Starting major iteration count. As the transfer control descriptor is first loaded by software, this field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.
224 / 0x1C [0]
BITER.E_LINK
225–230 / 0x1C [1:6]
BITER [0:5] or BITER.LINKCH[0:5]
231–239 / 0x1C [7:15]
BITER [6:14]
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Table 8-20. TCDn Field Descriptions (continued)
Bits / Word Offset [n:n] 240–241 / 0x1C [16:17] Name Description
BWC [0:1]
Bandwidth control. This two-bit field provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the inner minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the system bus crossbar switch (XBAR). 00 No DMA engine stalls 01 Reserved 10 DMA engine stalls for 4 cycles after each r/w 11 DMA engine stalls for 8 cycles after each r/w Link channel number. If channel-to-channel linking on major loop complete is disabled (TCD.MAJOR.E_LINK = 0) then, • No channel-to-channel linking (or chaining) is performed after the outer major loop counter is exhausted. Otherwise • After the major loop counter is exhausted, the DMA engine initiates a channel service request at the channel defined by MAJOR.LINKCH[0:5] by setting that channel’s TCD.START bit. Channel done. This flag indicates the eDMA has completed the outer major loop. It is set by the DMA engine as the CITER count reaches zero; it is cleared by software or hardware when the channel is activated (when the DMA engine has begun processing the channel, not when the first data transfer occurs). Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits. Channel active. This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared by the DMA engine as the inner minor loop completes or if any error condition is detected. Enable channel-to-channel linking on major loop completion. As the channel completes the outer major loop, this flag enables the linking to another channel, defined by MAJOR.LINKCH[0:5]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD.START bit of the specified channel. NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCD.DONE bit is set. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled.
242–247 / 0x1C [18:23]
MAJOR.LINKCH [0:5]
248 / 0x1C [24]
DONE
249 / 0x1C [25] 250 / 0x1C [26]
ACTIVE
MAJOR.E_LINK
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Table 8-20. TCDn Field Descriptions (continued)
Bits / Word Offset [n:n] 251 / 0x1C [27] Name Description
E_SG
Enable scatter-gather processing. As the channel completes the outer major loop, this flag enables scatter-gather processing in the current channel. If enabled, the DMA engine uses DLAST_SGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter-gather coherency model, this field is forced to zero when written to while the TCD.DONE bit is set. 0 The current channel’s TCD is normal format. 1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field provides a memory pointer to the next TCD to be loaded into this channel after the outer major loop completes its execution. Disable hardware request. If this flag is set, the eDMA hardware automatically clears the corresponding EDMA_ERQRL bit when the current major iteration count reaches zero. 0 The channel’s EDMA_ERQRL bit is not affected. 1 The channel’s EDMA_ERQRL bit is cleared when the outer major loop is complete. Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the EDMA_ERQRL when the current major iteration count reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is provided to support double-buffered (aka ping-pong) schemes, or other types of data movement where the processor needs an early indication of the transfer’s progress. CITER = BITER = 1 with INT_HALF enabled will generate an interrupt as it satisfies the equation (CITER == (BITER >> 1)) after a single activation. 0 The half-point interrupt is disabled. 1 The half-point interrupt is enabled. Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the EDMA_ERQRL when the current major iteration count reaches zero. 0 The end-of-major loop interrupt is disabled. 1 The end-of-major loop interrupt is enabled. Channel start. If this flag is set the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. 0 The channel is not explicitly started. 1 The channel is explicitly started via a software initiated service request.
252 / 0x1C [28]
D_REQ
253 / 0x1C [29]
INT_HALF
254 / 0x1C [30]
INT_MAJ
255 / 0x1C [31]
START
1
The fields implemented at 0x8 depend on whether EDMA_CR(EMLM) is set to 0 or 1. Refer to Table 8-3.
8.4
Functional Description
This section provides an overview of the microarchitecture and functional operation of the eDMA block.
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The eDMA module is partitioned into two major modules: the DMA engine and the transfer control descriptor local memory. The DMA engine is further partitioned into four submodules, which are detailed below. • DMA engine — Address path: This module implements registered versions of two channel transfer control descriptors: channel x and channel y, and is responsible for all the master bus address calculations. All the implemented channels provide the same functionality. This hardware structure allows the data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel service request is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed unless preempted by a higher priority channel. This capability provides a mechanism (optionally enabled by EDMA_CPRn[ECP]) where a large data move operation can be preempted to minimize the time another channel is blocked from execution. When another channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the registers of the other address path channel{x,y}. After the inner minor loop completes execution, the address path hardware writes the new values for the TCDn.{SADDR, DADDR, CITER} back into the local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory as part of a scatter-gather operation. — Data path: This module implements the actual bus master read/write datapath. It includes 32 bytes of register storage (matching the maximum transfer size) and the necessary mux logic to support any required data alignment. The system read data bus is the primary input, and the system write data bus is the primary output. The address and data path modules directly support the two-stage pipelined system bus. The address path module represents the 1st stage of the bus pipeline (the address phase), while the data path module implements the second stage of the pipeline (the data phase). — Program model/channel arbitration: This module implements the first section of eDMA’s programming model and also the channel arbitration logic. The programming model registers are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA interrupt request outputs are also connected to this module (via the control logic). — Control: This module provides all the control functions for the DMA engine. For data transfers where the source and destination sizes are equal, the DMA engine performs a series of source read, destination write operations until the number of bytes specified in the inner minor loop byte count has been moved. A minor loop interaction is defined as the number of bytes to transfer (nbytes) divided by the transfer size. Transfer size is defined as: if (SSIZE < DSIZE) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes)
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•
Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR, BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER, BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF. For descriptors where the sizes are not equal, multiple access of the smaller size data are required for each reference of the larger size. For example, if the source size references 16-bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. TCD local memory — Memory controller: This logic implements the required dual-ported controller, handling accesses from both the DMA engine as well as references from the slave bus. As noted earlier, in the event of simultaneous accesses, the DMA engine is given priority and the slave transaction is stalled. The hooks to a BIST controller for the local TCD memory are included in this module. — Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM memory array.
8.4.1
eDMA Basic Data Flow
The eDMA transfers data based on a two-deep, nested flow. The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 8-19, the first segment involves the channel service request. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel service request via software and the TCDn.START bit follows the same basic flow as an eDMA peripheral request. The eDMA peripheral request input signal is registered internally and then routed to through the DMA engine, first through the control module, then into the program model/channel arbitration module. In the next cycle, the channel arbitration is performed using the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the TCD local memory. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the DMA engine address path channel{x,y} registers. The TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine address path channel{x,y} registers.
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eDMA
SRAM Transfer control descriptor (TCD) Slave write address Slave write data
SRAM System bus
TCD0 Slave interface 217
TCDn-1* eDMA engine Bus read data Program model/ channel arbitration Address path Control Slave read data
Data path Bus write data Bus address
*n = 16 channels
eDMA interrupt request eDMA done handshake
eDMA peripheral request
Figure 8-19. eDMA Operation, Part 1
In the second part of the basic data flow as shown in Figure 8-20, the modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path module until it is gated onto the system bus during the destination write. This source read/destination write processing continues until the inner minor byte count has been transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer.
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eDMA
SRAM Transfer control descriptor (TCD) Slave write address Slave write data
SRAM System bus
TCD0 Slave interface
TCDn-1* eDMA engine Bus read data Program model/ channel arbitration Address path Control Slave read data
Data path Bus write data Bus address
*n = 16 channels
eDMA peripheral request
eDMA interrupt request eDMA done handshake
Figure 8-20. eDMA Operation, Part 2
After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In this segment, the address path logic performs the required updates to certain fields in the channel’s TCD; for example, SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then there are additional operations performed. These include the final address adjustments and reloading of the BITER field into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of a new TCD from memory using the scatter-gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 8-21.
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eDMA
SRAM Transfer control descriptor (TCD) Slave write address Slave write data
SRAM System bus
TCD0 Slave interface 219
TCDn-1* eDMA engine Bus read data Program model/ channel arbitration Address path Control Slave read data
Data path Bus write data Bus address
*n = 16 channels
eDMA peripheral request
eDMA done
Figure 8-21. eDMA Operation, Part 3
8.5
8.5.1
Initialization / Application Information
eDMA Initialization
A typical initialization of the eDMA has the following sequence: 1. Write the EDMA_CR if a configuration other than the default is desired. 2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers if desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers. 6. Request channel service by software (setting the TCD.START bit) or by hardware (slave device asserting its DMA peripheral request signal). After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The DMA engine will read the entire TCD, including the
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primary transfer control parameter shown in Table 8-21, for the selected channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the system bus unless a configuration error is detected. Transfers from the source (as defined by the source address, TCD.SADDR) to the destination (as defined by the destination address, TCD.DADDR) continue until the specified number of bytes (TCD.NBYTES) have been transferred. When the transfer is complete, the DMA engine's local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing is executed; for example, interrupts, major loop channel linking, and scatter-gather operations, if enabled.
Table 8-21. TCD Primary Control and Status Fields
TCD Field Name START ACTIVE DONE D_REQ BWC E_SG INT_HALF INT_MAJ Description Control bit to start channel when using a software initiated DMA service (Automatically cleared by hardware) Status bit indicating the channel is currently in execution Status bit indicating major loop completion (cleared by software when using a software initiated DMA service) Control bit to disable DMA request at end of major loop completion when using a hardware-initiated DMA service Control bits for throttling bandwidth control of a channel Control bit to enable scatter-gather feature Control bit to enable interrupt when major loop is half complete Control bit to enable interrupt when major loop completes
Figure 8-22 shows how each DMA request initiates one minor loop transfer (iteration) without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter).
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Example memory array DMA request • • • DMA request • • • DMA request • • • Minor loop Minor loop Major loop Minor loop
Current major loop iteration count (CITER)
3
2
1
Figure 8-22. Example of Multiple Loop Iterations
Figure 8-23 lists the memory array terms and how the TCD settings interrelate.
xADDR: (Starting address) xSIZE: (Size of one data transfer) • • • • • • • • • Minor loop (NBYTES in minor loop, often the same value as xSIZE) Offset (xOFF): Number of bytes added to current address after each transfer (Often the same value as xSIZE) Each DMA source (S) and destination (D) has its own: • Address (xADDR) • Size (xSIZE) • Offset (xOFF) • Modulo (xMOD) • Last address adjustment (xLAST) where x = S or D Peripheral queues typically have size and offset equal to NBYTES
Minor loop
xLAST: Number of bytes added to current address after major loop (typically used to loop back)
• • •
Last minor loop
Figure 8-23. Memory Array Terms
8.5.2
DMA Programming Errors
The DMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per-channel basis with the exception of channel-priority error, or EDMA_ESR[CPE]. For all error types other than channel-priority errors, the channel number causing the error is recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem channel, the error will be detected and recorded again.
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If priority levels are not unique, the highest (channel) priority that has an active request is selected, but the lowest numbered (channel) with that priority is selected by arbitration and executed by the DMA engine. The hardware service request handshake signals, error interrupts, and error reporting are associated with the selected channel.
8.5.3
DMA Request Assignments
The assignments between the DMA requests from the modules to the channels of the eDMA are shown in Table 8-22. The source column is written in C language syntax. The syntax is module_instance.register[bit].
Table 8-22. DMA Request Summary for eDMA
DMA Request DMA_MUX_CHCONFIG0_SOURCE DMA_MUX_CHCONFIG1_SOURCE DMA_MUX_CHCONFIG2_SOURCE DMA_MUX_CHCONFIG3_SOURCE DMA_MUX_CHCONFIG4_SOURCE DMA_MUX_CHCONFIG5_SOURCE DMA_MUX_CHCONFIG6_SOURCE DMA_MUX_CHCONFIG7_SOURCE DMA_MUX_CHCONFIG8_SOURCE DMA_MUX_CHCONFIG9_SOURCE DMA_MUX_CHCONFIG10_SOURCE DMA_MUX_CHCONFIG11_SOURCE DMA_MUX_CHCONFIG12_SOURCE DMA_MUX_CHCONFIG13_SOURCE DMA_MUX_CHCONFIG14_SOURCE DMA_MUX_CHCONFIG15_SOURCE Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Source DMA_MUX.CHCONFIG0[SOURCE] DMA_MUX.CHCONFIG1[SOURCE] DMA_MUX.CHCONFIG2[SOURCE] DMA_MUX.CHCONFIG3[SOURCE] DMA_MUX.CHCONFIG4[SOURCE] DMA_MUX.CHCONFIG5[SOURCE] DMA_MUX.CHCONFIG6[SOURCE] DMA_MUX.CHCONFIG7[SOURCE] DMA_MUX.CHCONFIG8[SOURCE] DMA_MUX.CHCONFIG9[SOURCE] DMA_MUX.CHCONFIG10[SOURCE] DMA_MUX.CHCONFIG11[SOURCE] DMA_MUX.CHCONFIG12[SOURCE] DMA_MUX.CHCONFIG13[SOURCE] DMA_MUX.CHCONFIG14[SOURCE] DMA_MUX.CHCONFIG15[SOURCE] Description DMA MUX channel 0 source DMA MUX channel 1 source DMA MUX channel 2 source DMA MUX channel 3 source DMA MUX channel 4 source DMA MUX channel 5 source DMA MUX channel 6 source DMA MUX channel 7 source DMA MUX channel 8 source DMA MUX channel 9 source DMA MUX channel 10 source DMA MUX channel 11 source DMA MUX channel 12 source DMA MUX channel 13 source DMA MUX channel 14 source DMA MUX channel 15 source
8.5.4
8.5.4.1
DMA Arbitration Mode Considerations
Fixed-Channel Arbitration
In this mode, the channel service request from the highest priority channel is selected to execute. Preemption is available in this scenario only.
8.5.4.2
Round-Robin Channel Arbitration
In this mode, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the assigned channel priority levels.
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8.5.5
8.5.5.1
DMA Transfer
Single Request
To perform a simple transfer of n bytes of data with one activation, set the major loop to 1 (TCD.CITER = TCD.BITER = 1). The data transfer will begin after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCD.DONE bit will be set and an interrupt will be generated if properly enabled. For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a word wide port located at 0x2000. The address offsets are programmed in increments to match the size of the transfer; one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCD.CITER = TCD.BITER = 1 TCD.NBYTES = 16 TCD.SADDR = 0x1000 TCD.SOFF = 1 TCD.SSIZE = 0 TCD.SLAST = –16 TCD.DADDR = 0x2000 TCD.DOFF = 4 TCD.DSIZE = 2 TCD.DLAST_SGA= -16 TCD.INT_MAJ = 1 TCD.START = 1 (Must be written last after all other fields have been initialized) All other TCD fields = 0 This would generate the following sequence of events: 1. Slave write to the TCD.START bit requests channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000) first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008) third iteration of the minor loop
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g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c) last iteration of the minor loop major loop complete 6. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 1 (TCD.BITER). 7. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1. 8. The channel retires. The eDMA goes idle or services the next channel.
8.5.5.2
Multiple Requests
The next example is the same as previous, excepting transferring 32 bytes via two hardware requests. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s hardware requests are enabled in the EDMA_ERQR, channel service requests are initiated by the slave device (ERQR should be set after TCD). Note that TCD.START = 0. TCD.CITER = TCD.BITER = 2 TCD.NBYTES = 16 TCD.SADDR = 0x1000 TCD.SOFF = 1 TCD.SSIZE = 0 TCD.SLAST = –32 TCD.DADDR = 0x2000 TCD.DOFF = 4 TCD.DSIZE = 2 TCD.DLAST_SGA= –32 TCD.INT_MAJ = 1 TCD.START = 0 (Must be written last after all other fields have been initialized) All other TCD fields = 0 This generates the following sequence of events: 1. First hardware (eDMA peripheral request) request for channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000) first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) second iteration of the minor loop
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e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008) third iteration of the minor loop g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c) last iteration of the minor loop 6. eDMA engine writes: TCD.SADDR = 0x1010, TCD.DADDR = 0x2010, TCD.CITER = 1. 7. eDMA engine writes: TCD.ACTIVE = 0. 8. The channel retires one iteration of the major loop. The eDMA goes idle or services the next channel. 9. Second hardware (eDMA peripheral request) requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 12. eDMA engine reads: channel TCD data from local memory to internal register file. 13. The source to destination transfers are executed as follows: a) read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013) b) write_word(0x2010) first iteration of the minor loop c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017) d) write_word(0x2014) second iteration of the minor loop e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b) f) write_word(0x2018) third iteration of the minor loop g) read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f) h) write_word(0x201c) last iteration of the minor loop major loop complete 14. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 2 (TCD.BITER). 15. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1. 16. The channel retires major loop complete. The eDMA goes idle or services the next channel.
8.5.5.3
Modulo Feature
The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of two. MOD is a 5-bit bitfield for both the source and destination in the TCD and specifies which lower address bits are allowed to increment from their original value after the address + offset calculation. All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature. Table 8-23 shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 24 byte (16-byte) size queue.
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Table 8-23. Modulo Feature Example
Transfer Number 1 2 3 4 5 6 Address 0x12345670 0x12345674 0x12345678 0x1234567C 0x12345670 0x12345674
8.5.6
8.5.6.1
TCD Status
Minor Loop Complete
There are two methods to test for minor loop completion when using software initiated service requests. The first method is to read the TCD.CITER field and test for a change. Another method may be extracted from the sequence below. The second method is to test the TCD.START bit AND the TCD.ACTIVE bit. The minor loop complete condition is indicated by both bits reading zero after the TCD.START was written to a 1. Polling the TCD.ACTIVE bit may be inconclusive because the active status may be missed if the channel execution is short in duration. The TCD status bits execute the following sequence for a software activated channel: 1. TCD.START = 1, TCD.ACTIVE = 0, TCD.DONE = 0 (channel service request via software). 2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (channel is executing). 3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (channel has completed the minor loop and is idle), or 4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (channel has completed the major loop and is idle). The best method to test for minor loop completion when using hardware initiated service requests is to read the TCD.CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model. The TCD status bits execute the following sequence for a hardware activated channel: 1. eDMA peripheral request asserts (channel service request via hardware). 2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (channel is executing). 3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (channel has completed the minor loop and is idle), or 4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (channel has completed the major loop and is idle). For both activation types, the major loop complete status is explicitly indicated via the TCD.DONE bit.
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The TCD.START bit is cleared automatically when the channel begins execution, regardless of how the channel was activated.
8.5.6.2
Active Channel TCD Reads
The eDMA will read back the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while a channel is executing. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine is currently using in its internal register file and not the values in the TCD local memory for that channel. The addresses (SADDR and DADDR) and NBYTES (decrements to zero as the transfer progresses) can give an indication of the progress of the transfer. All other values are read back from the TCD local memory.
8.5.6.3
Preemption Status
Preemption is available only when fixed arbitration is selected for channel-arbitration modes. A preempt-able situation is one in which a preempt-enabled channel is running and a higher priority request becomes active. When the eDMA engine is not operating in fixed-channel arbitration mode, the determination of the relative priority of the actively running and the outstanding requests become undefined. Channel priorities are treated as equal (or more exactly, constantly rotating) when round-robin arbitration mode is selected. The TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one iteration of the major loop. Two TCD.ACTIVE bits set at the same time in the overall TCD map indicates a higher priority channel is actively preempting a lower priority channel.
8.5.7
Channel Linking
Channel linking (or chaining) is a mechanism in which one channel sets the TCD.START bit of another channel (or itself), thus initiating a service request for that channel. This operation is automatically performed by the eDMA engine at the conclusion of the major or minor loop when properly enabled. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCD.CITER.E_LINK field are used to determine whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the minor loop except for the last. When the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. For example, with the initial fields of: TCD.CITER.E_LINK = 1 TCD.CITER.LINKCH = 0xC TCD.CITER value = 0x4 TCD.MAJOR.E_LINK = 1 TCD.MAJOR.LINKCH = 0x7 will execute as: 1. Minor loop done set channel 12 TCD.START bit 2. Minor loop done set channel 12 TCD.START bit
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3. Minor loop done set channel 12 TCD.START bit 4. Minor loop done, major loop done set channel 7 TCD.START bit When minor loop linking is enabled (TCD.CITER.E_LINK = 1), the TCD.CITER field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCD.CITER.E_LINK = 0), the TCD.CITER field uses a 15-bit vector to form the current iteration count. The bits associated with the TCD.CITER.LINKCH field are concatenated onto the CITER value to increase the range of the CITER. NOTE After configuration, the TCD.CITER.E_LINK bit and the TCD.BITER.E_LINK bit must be equal or a configuration error will be reported. The CITER and BITER vector widths must be equal to calculate the major loop, halfway done interrupt point. Table 8-24 summarizes how a DMA channel can link to another DMA channel, i.e, use another channel’s TCD, at the end of a loop.
Table 8-24. Channel Linking Parameters
Desired Link Behavior Link at end of minor loop TCD Control Field Name citer.e_link citer.linkch Link at end of major loop major.e_link major.linkch Description Enable channel-to-channel linking on minor loop completion (current iteration). Link channel number when linking at end of minor loop (current iteration). Enable channel-to-channel linking on major loop completion. Link channel number when linking at end of major loop.
8.5.8
Dynamic Programming
This section provides recommended methods to change the programming model during channel execution.
8.5.8.1
Dynamic Channel Linking and Dynamic Scatter-Gather Operation
Dynamic channel linking and dynamic scatter-gather operation is the process of changing the TCD.MAJOR.E_LINK or TCD.E_SG bits during channel execution. These bits are read from the TCD local memory at the end of channel execution thus allowing the user to enable either feature during channel execution. Because the user is allowed to change the configuration during execution, a coherency model is needed. Consider a scenario where the user attempts to execute a dynamic channel link by enabling the TCD.MAJOR.E_LINK bit at the same time the eDMA engine is retiring the channel. The TCD.MAJOR.E_LINK would be set in the programmer’s model, but it would be unclear whether the actual link was made before the channel retired.
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The following coherency model is recommended when executing a dynamic channel link or dynamic scatter-gather request: 1. Set the TCD.MAJOR.E_LINK bit. 2. Read back the TCD.MAJOR.E_LINK bit 3. Test the TCD.MAJOR.E_LINK request status: a) If the bit is set, the dynamic link attempt was successful. b) If the bit is cleared, the attempted dynamic link did not succeed, the channel was already retiring. This same coherency model is true for dynamic scatter-gather operations. For both dynamic requests, the TCD local memory controller forces the TCD.MAJOR.E_LINK and TCD.E_SG bits to zero on any writes to a channel’s TCD after that channel’s TCD.DONE bit is set indicating the major loop is complete. NOTE The user must clear the TCD.DONE bit before writing the TCD.MAJOR.E_LINK or TCD.E_SG bits. The TCD.DONE bit is cleared automatically by the eDMA engine after a channel begins execution.
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Chapter 9 DMA Channel Multiplexer (DMA_MUX)
Chapter 9 DMA Channel Multiplexer (DMA_MUX)
9.1
9.1.1
Introduction
Overview
The DMA channel multiplexer (DMA_MUX) allows the routing of 16 DMA sources (slots) to 16 DMA channels. This is illustrated in Figure 9-1.
DMA Channel #0 DMA Channel #1
Source #1 Source #2 Source #3
DMA_MUX
Source #63 Always enabled #1
Always enabled #2 Trigger #1
DMA Channel #15 Trigger #2
Figure 9-1. DMA_MUX block diagram
9.1.2
Features
The DMA_MUX has these major features: • 16 independently selectable DMA channel routers — 2 channels with normal or periodic triggering capability — 12 channels with normal capability
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• •
Capability to assign each channel router to one of 16 possible peripheral DMA sources, 2 always enabled sources or 1 always disabled source 3 modes of operation: — Disabled — Normal — Periodic Trigger
9.1.3
Modes of operation
The following operation modes are available: • Disabled Mode — In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA_MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place (for example, changing the period of a DMA trigger). • Normal Mode — In this mode, a DMA source (such as DSPI_0_TX or DSPI_0_RX example) is routed directly to the specified DMA channel. The operation of the DMA_MUX in this mode is completely transparent to the system. • Periodic Trigger Mode — In this mode, a DMA source may only request a DMA transfer (such as when a transmit buffer becomes empty or a receive buffer becomes full) periodically. The period is configured in the registers of the Periodic Interrupt Timer (PIT). DMA channels 0–3 may be used in all three modes, but channels 4–15 may only be configured to disabled or normal mode.
9.2
9.2.1
External signal description
Overview
The DMA_MUX has no external pins.
9.3
Memory map and register definition
This section provides a detailed description of all memory-mapped registers in the DMA_MUX. Table 9-1 shows the memory map for the DMA_MUX. Note that all addresses are offsets; the absolute address may be computed by adding the specified offset to the base address of the DMA_MUX.
Table 9-1. Module memory map
Address Base + $0x00 Base + $0x01 Use Channel #0 Configuration (CHCONFIG0) Channel #1 Configuration (CHCONFIG1) Access R/W R/W
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Table 9-1. Module memory map (continued)
.. Base + $0x0F .. Channel #15 Configuration (CHCONFIG15) .. R/W
All registers are accessible via 8, 16 or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit READ/WRITE to address ‘Base + 0x00’, but performing a 32-bit access to address ‘Base + 0x01’ is illegal.
9.3.1
Register descriptions
The following memory-mapped registers are available in the DMA_MUX.
9.3.1.1
Channel configuration registers (CHCONFIG#n)
Each of the total of 16 DMA channels can be independently enabled/disabled and associated with 1 of the 28 peripheral DMA sources + 1 of the 4 always enabled DMA sources in the system.
Address: Base + #n 7 R W Reset 0 0 0 0 0 0 0 0 ENBL 6 TRIG 5 4 3 2 Access: User read/write 1 0
SOURCE[5:0]
Figure 9-2. Channel Configuration Registers (CHCONFIG#n) Table 9-2. CHCONFIG#n field descriptions
Field 7 ENBL Description DMA Channel Enable ENBL enables the DMA channel. 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA_MUX. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 1 DMA channel is enabled DMA Channel Trigger Enable (for triggered channels only) TRIG enables the periodic trigger capability for the DMA channel. 0 Periodic triggering is disabled. If periodic triggering is disabled, and the ENBL bit is set, the DMA_MUX will simply route the specified source to the DMA channel. 1 Triggering is enabled
6 TRIG
5:0 DMA Channel Source (slot) SOURCE[5:0 SOURCE specifies which DMA source, if any, is routed to a particular DMA channel. Please refer to ] Table 9-4 for DMA_MUX inputs mapping.
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Table 9-3. Channel and trigger enabling
ENBL 0 1 1 TRIG X 0 1 Function DMA channel is disabled DMA channel is enabled with no triggering (transparent) DMA channel is enabled with triggering Mode Disabled Mode Normal Mode Periodic Trigger Mode
NOTE Setting multiple CHCONFIG registers with the same Source value results in unpredictable behavior. NOTE Before changing the trigger or source settings a DMA channel must be disabled via the CHCONFIG[#n].ENBL bit.
9.3.2
9.3.2.1
DMA_MUX inputs
DMA_MUX peripheral sources
Table 9-4. DMA channel mapping
DMA_MUX channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Module — DSPI 0 DSPI 0 DSPI 1 DSPI 1 — — — — — — — — — — — — DMA requesting module Always disabled DSPI_0 TX DSPI_0 RX DSPI_1 TX DSPI_1 RX — — — — — — — — — — — — — DMA_MUX Source #1 DMA_MUX Source #2 DMA_MUX Source #3 DMA_MUX Source #4 DMA_MUX Source #5 DMA_MUX Source #6 DMA_MUX Source #7 DMA_MUX Source #8 DMA_MUX Source #9 DMA_MUX Source #10 DMA_MUX Source #11 DMA_MUX Source #12 DMA_MUX Source #13 DMA_MUX Source #14 DMA_MUX Source #15 DMA_MUX Source #16 DMA_MUX input #
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Table 9-4. DMA channel mapping (continued)
DMA_MUX channel 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Module eMIOS 0 eMIOS 0 eMIOS 0 eMIOS 0 eMIOS 0 eMIOS 0 — — — — — — — ADC 1 — — LINFLEX 0 LINFLEX 0 — — — — — — — — — — — — — DMA requesting module EMIOS0_CH0 EMIOS0_CH1 EMIOS1_CH9 EMIOS1_CH18 EMIOS1_CH25 EMIOS1_CH26 — — — — — — — ADC1_EOC — — LINFLEX0_RX LINFLEX0_TX — — — — — — — — — — — — — DMA_MUX input # DMA_MUX Source #17 DMA_MUX Source #18 DMA_MUX Source #19 DMA_MUX Source #20 DMA_MUX Source #21 DMA_MUX Source #22 DMA_MUX Source #23 DMA_MUX Source #24 DMA_MUX Source #25 DMA_MUX Source #26 DMA_MUX Source #27 DMA_MUX Source #28 DMA_MUX Source #29 DMA_MUX Source #30 DMA_MUX Source #31 DMA_MUX Source #32 DMA_MUX Source #33 DMA_MUX Source #34 DMA_MUX Source #35 DMA_MUX Source #36 DMA_MUX Source #37 DMA_MUX Source #38 DMA_MUX Source #39 DMA_MUX Source #40 DMA_MUX Source #41 DMA_MUX Source #42 DMA_MUX Source #43 DMA_MUX Source #44 DMA_MUX Source #45 DMA_MUX Source #46 DMA_MUX Source #47
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Table 9-4. DMA channel mapping (continued)
DMA_MUX channel 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Module — — — — — — — — — — — — PIT_0 PIT_1 — — — — — — — — — — — — — — ALWAYS ENABLED ALWAYS ENABLED — — DMA requesting module DMA_MUX input # DMA_MUX Source #48 DMA_MUX Source #49 DMA_MUX Source #50 DMA_MUX Source #51 DMA_MUX Source #52 DMA_MUX Source #53 DMA_MUX Source #54 DMA_MUX Source #55 DMA_MUX Source #56 DMA_MUX Source #57 DMA_MUX Source #58 DMA_MUX Source #59 DMA_MUX Source #60 DMA_MUX Source #61 DMA_MUX Source #62 DMA_MUX Source #63
9.3.2.2
DMA_MUX periodic trigger inputs
Table 9-5. DMA_MUX periodic trigger inputs
DMA_MUX trigger input Trigger #1 Trigger #2 PIT channel PIT0 PIT1
9.4
Functional description
This section provides a complete functional description of the DMA_MUX. The primary purpose of the DMA_MUX is to provide flexibility in the system’s use of the available DMA channels. As such, configuration of the DMA_MUX is intended to be a static procedure done during execution of the system boot code. However, if the procedure outlined in Section 9.5.2, “Enabling and configuring sources, is followed, the configuration of the DMA_MUX may be changed during the normal operation of the system. Functionally, the DMA_MUX channels may be divided into two classes: Channels, which implement the normal routing functionality plus periodic triggering capability, and channels, which implement only the normal routing functionality.
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9.4.1
DMA channels with periodic triggering capability
Besides the normal routing functionality, the first four channels of the DMA_MUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames or packets at fixed intervals without the need for processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. Please refer to the periodic interrupt timer chapter of the reference manual for more information on this topic. NOTE Because of the dynamic nature of the system (such as DMA channel priorities, bus arbitration, or interrupt service routine lengths), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed.
Source #1 Source #2 Source #3 Trigger #1 Trigger #2
DMA Channel #0
Source #28 Always enabled Trigger #4 DMA Channel #3
Always enabled
Figure 9-3. DMA_MUX channel 0–3 block diagram
The DMA channel triggering capability allows the system to “schedule” regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in Figure 9-4.
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Periph Request
Trigger DMA Request
Figure 9-4. DMA_MUX channel triggering: Normal operation
Once the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, that triggered will be ignored. This situation is illustrated in Figure 9-5.
Periph Request
Trigger DMA Request
Figure 9-5. DMA_MUX channel triggering: Ignored trigger
This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for periodically polling external devices on a particular bus. As an example, the transmit side of a DSPI is assigned to a DMA channel with a trigger, as described above. Once set up, the SPI will request DMA transfers (presumably from memory) as long as its transmit buffer is empty. By using a trigger on this channel, the DSPI transfers can be automatically performed every 5µs (as an example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. A more detailed description of the capability of each trigger (such as resolution, or range of values) may be found in the periodic interrupt timer chapter of the reference manual.
9.4.2
DMA channels with no triggering capability
Channels 4–15 of the DMA_MUX provide the normal routing functionality as described in Section 9.1.3, “Modes of operation.
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Source #1 Source #2 Source #3 DMA Channel #4
Source #28 DMA Channel #15 Always enabled
Always enabled
Figure 9-6. DMA_MUX channel 4–15 block diagram
9.5
9.5.1
Initialization/Application information
Reset
The reset state of each individual bit is shown in Section 9.3.1, “Register descriptions. In summary, after reset, all channels are disabled and must be explicitly enabled before use.
9.5.2
9.5.2.1
Enabling and configuring sources
Enabling a source with periodic triggering
The following describes how to enable a source with periodic triggering: 1. Determine with which DMA channel the source will be associated. Remember that only the first four DMA channels have periodic triggering capability. 2. Clear the ENBL and TRIG bits of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.
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4. In the PIT, configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG register, ensuring that the ENBL and TRIG bits are set.
Example 9-1. Configure source #3 Transmit for use with DMA Channel 2, with periodic triggering capability
1. 2. 3. 4.
Write 0x00 to CHCONFIG2 (Base Address + 0x02) Configure Channel 2 in the DMA, including enabling the channel Configure Timer 4 in the Periodic Interrupt Timer (PIT) for the desired trigger interval Write 0xC3 to CHCONFIG2 (Base Address + 0x02)
In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); In File main.c: #include "registers.h" : : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0xC3;
The following code example illustrates steps #1 and #4 above:
9.5.2.2
Enabling a source without periodic triggering
The following describes how to enable a source without periodic triggering: 1. Determine with which DMA channel the source will be associated. Remember that only DMA channels 0–3 have periodic triggering capability. 2. Clear the ENBL and TRIG bits of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG register, ensuring that the ENBL is set and the TRIG bit is cleared.
Example 9-2. Configure source #5 Transmit for use with DMA Channel 2, without periodic triggering capability
1. Write 0x00 to CHCONFIG2 (Base Address + 0x02) 2. Configure Channel 2 in the DMA, including enabling the channel 3. Write 0x85 to CHCONFIG2 (Base Address + 0x02) The following code example illustrates steps #1 and #3 above:
In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); In File main.c: #include "registers.h"
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: : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0x85;
9.5.2.3
Disabling a source
A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCONFIG registers. Additionally, some module specific configuration may be necessary. Please refer to the appropriate section for more details.
9.5.2.4
Switching the source of a DMA channel
The following describes how to switch the source of a DMA channel: 1. Disable the DMA channel in the DMA and reconfigure the channel for the new source. 2. Clear the ENBL and TRIG bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG register, ensuring that the ENBL and TRIG bits are set.
Example 9-3. Switch DMA Channel 8 from source #5 transmit to source #7 transmit
1. In the DMA configuration registers, disable DMA channel 8 and re-configure it to handle the transfers to peripheral slot 7. This example assumes channel 8 doesn’t have triggering capability. 2. Write 0x00 to CHCONFIG8 (Base Address + 0x08) 3. Write 0x87 to CHCONFIG8 (Base Address + 0x08). The following code example illustrates steps #2 and #3 above:
In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); In File main.c: #include "registers.h" : : *CHCONFIG8 = 0x00; *CHCONFIG8 = 0x87;
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Chapter 10 Multi-Layer AHB Crossbar Switch (XBAR)
Chapter 10 Multi-Layer AHB Crossbar Switch (XBAR)
10.1 Information specific to this device
This section presents device-specific parameterization, customization, and feature availability information not specifically referenced in the remainder of this chapter.
10.1.1
Device-specific features
The following summarizes the device-specific implementation of the crossbar switch: • 3 master ports: — CPU instruction bus — CPU load/store bus — eDMA • Multiple bus slaves to enable access to flash memory, SRAM and peripherals • Crossbar supports up to 2 consecutive transfers at any one time • 32-bit internal address bus, 32-bit internal data bus • Fixed priority arbitration based on port master
Table 10-1. Master/Slave mappings
Port Module Type e200z0 core—CPU instructions e200z0 core—CPU data / Nexus eDMA Flash Internal SRAM Peripheral bridge Master Master Master Slave Slave Slave Logical number 0 0 2 0 2 7 0 1 2 — — — Physical master ID
10.1.2
Device-specific register information
Table 10-2. Device-specific XBAR register implementation
The memory map for the XBAR program-visible registers on this device is shown in Table 10-2.
XBAR base offset 0x000 0x004 Register MPR0 AMPR0 Use Master Priority Register for Slave port 0 Alternate Master Priority Register for Slave port 0 Location on page 250 on page 252
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Table 10-2. Device-specific XBAR register implementation (continued)
XBAR base offset 0x010 0x014 0x200 0x204 0x210 0x214 0x700 0x704 0x710 0x714 0x800 0x900 0xA00 Register SGPCR0 MPR2 AMPR2 SGPCR2 MPR7 AMPR7 SGPCR7 MGPCR0 MGPCR1 MGPCR2 Use General Purpose Control Register for Slave port 0 Master Priority Register for Slave port 2 Alternate Master Priority Register for Slave port 2 General Purpose Control Register for Slave port 2 Master Priority Register for Slave port 7 Alternate Master Priority Register for Slave port 7 General Purpose Control Register for Slave port 7 General Purpose Control Register for Master port 0 General Purpose Control Register for Master port 1 General Purpose Control Register for Master port 2 Location on page 253 on page 255 on page 250 on page 252 on page 253 on page 255 on page 250 on page 252 on page 253 on page 255 on page 256 on page 256 on page 256
ASGPCR0 Alternate General Purpose Control Register for Slave port 0
ASGPCR2 Alternate General Purpose Control Register for Slave port 2
ASGPCR7 Alternate General Purpose Control Register for Slave port 7
10.2
10.2.1
Introduction
Overview
This section provides an overview of the generic multi-layer AHB crossbar switch (XBAR1). The purpose of the XBAR is to concurrently support up to eight simultaneous connections between master ports and slave ports. The XBAR supports a 32-bit address bus width and almost any data bus width at all master and slave ports. Only a single data bus width is supported (via a synthesis parameter) throughout the design, thus, all master and slave ports have the same data bus width.
1.An alternate abbreviation for this module is MAX.
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Master Port 0 IP cntrl IP wdata IP rdata IP term Mstr Port request Mstr Port addr Mstr Port cntrl Slv port hready(s) Slv port hresp(s) Slv port hrdata(s) Master 0 write data Slave Port 0 Mstr port(s) request Mstr port(s) addr Mstr port(s) cntrl Mstr port(s) wdata Hready to mstr(s) Hresp to mstr(s) IP cntrl IP wdata IP rdata IP term halt request halt grant Slave 0 read data Slv addr Slv cntrl Slv wdata Slv hready Slv hresp
Mstr addr Mstr control Mstr hready Mstr hresp Mstr read data
Master Port 7 IP cntrl IP wdata IP rdata IP term Mstr Port request Mstr Port addr Mstr Port cntrl Slv port hready(s) Slv port hresp(s) Slv port hrdata(s) Master 7 write data Max halt request General Purpose Logic Slv IP cntrl IP cntrl IP wdata(s) IP wdata IP rdata(s) IP rdata IP term IP term(s) Max_halted halt grant(s)
Mstr addr Mstr control Mstr hready Mstr hresp Mstr read data
Slave Port 7 Mstr port(s) request Mstr port(s) addr Mstr port(s) cntrl Mstr port(s) wdata Hready to mstr(s) Hresp to mstr(s) IP cntrl IP wdata IP rdata IP term halt request halt grant Slave 7 read data Slv addr Slv cntrl Slv wdata Slv hready Slv hresp
Figure 10-1. XBAR Block Diagram
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10.2.2
Features
The XBAR has the ability to gain control of all the slave ports and prevent any masters from making accesses to the slave ports. This feature is useful when the user wishes to turn off the clocks to the system and needs to ensure that no bus activity will be interrupted. The XBAR can put each slave port into a low power park mode so that slave port will not dissipate any power transitioning address, control or data signals when not being actively accessed by a master port. Each slave port can also support multiple master priority schemes. Each slave port has a hardware input which selects the master priority scheme so the user can dynamically change master priority levels on a slave port by slave port basis. The XBAR will allow for concurrent transactions to occur from any master port to any slave port. It is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. If a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting that slave port will stalled until the higher priority master completes its transactions.
10.2.3
Limitations
The XBAR routes bus transactions initiated on the master ports to the appropriate slave ports. There is no provision included to route transactions initiated on the slave ports to other slave ports or to master ports. Simply put, the slave ports do not support the bus request/bus grant protocol, the XBAR assumes it is the sole master of each slave port. Since the XBAR does not support the bus request/bus grant protocol, if multiple masters are to be connected to a single master port an external arbiter will need to be used. In the case of a single master connecting to a master port the single master’s bus grant signal must be tied off in the asserted state. Each master and slave port is fully AHB-Lite + AMBA V6 extensions compliant. The ports are not fully AHB compliant because the XBAR does not support SPLITs or RETRYs.
10.2.4
General Operation
When a master makes an access to the XBAR the access will be immediately taken by the XBAR. If the targeted slave port of the access is available then the access will be immediately presented on the slave port. It is possible to make single clock (zero wait state) accesses through the XBAR. If the targeted slave port of the access is busy or parked on a different master port the requesting master will simply see wait states inserted (hready held negated) until the targeted slave port can service the master’s request. The latency in servicing the request will depend on each master’s priority level and the responding peripheral’s access time. Since the XBAR appears to be just another slave to the master device, the master device will have no knowledge of whether or not it actually owns the slave port it is targeting. While the master does not have control of the slave port it is targeting it will simply be wait stated. A master will be given control of the targeted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from
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occurring when a master has an outstanding request to one slave port that has a long response time, has a pending access to a different slave port, and a lower priority master is also making a request to the same slave port as the pending access of the higher priority master. Once the master has control of the slave port it is targeting the master will remain in control of that slave port until it gives up the slave port by running an IDLE cycle or by leaving that slave port for its next access. The master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is running a locked or fixed length burst transfer it will retain control of the slave port until that transfer is completed. Based on the AULB bit in the MGPCR (Master General Purpose Control Register) the master will either retain control of the slave port when doing undefined length incrementing burst transfers or will lose the bus to a higher priority master. The XBAR will terminate all master IDLE transfers (as opposed to allowing the termination to come from one of the slave busses). Additionally, when no master is requesting access to a slave port the XBAR will drive IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When the XBAR is controlling the slave bus (that is, during low power park or halt mode) the hmaster field will indicate 4’b0000. When a slave bus is being IDLEd by the XBAR it can park the slave port on the master port indicated by the PARK bits in the SGPCR (Slave General Purpose Control Register) or ASGPCR (Alternate SGPCR). This can be done in an attempt to save the initial clock of arbitration delay that would otherwise be seen if the master had to arbitrate to gain control of the slave port. The slave port can also be put into low power park mode in attempt to save power.
10.3
XBAR Registers
This section provides information on XBAR registers.
10.3.1
Register Summary
There are four registers that reside in each slave port of the XBAR and one register that resides in each master port of the XBAR. These registers are IP bus compliant registers. Read and write transfers both require two IP bus clock cycles. The registers can only be read from and written to in supervisor mode. Additionally, these registers can only be read from or written to by 32-bit accesses. The registers are fully decoded and an error response is returned if an unimplemented location is accessed within the XBAR. The slave registers also feature a bit, which when written with a 1, will prevent the registers from being written to again. The registers will still be readable, but future write attempts will have no effect on the registers and will be terminated with an error response. The memory map for the XBAR program-visible registers is shown in Table 10-3. Table 10-4 shows the XBAR register summary.
Table 10-3. XBAR Register Configuration Summary
XBAR base offset 0x000 Register MPR0 Use Master Priority Register for Slave port 0
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Table 10-3. XBAR Register Configuration Summary (continued)
XBAR base offset 0x004 0x010 0x014 0x100 0x104 0x110 0x114 0x200 0x204 0x210 0x214 0x300 0x304 0x310 0x314 0x400 0x404 0x410 0x414 0x500 0x504 0x510 0x514 0x600 0x604 0x610 0x614 0x700 0x704 0x710 0x714 0x800 0x900 0xA00 0xB00 0xC00 0xD00 0xE00 0xF00 Register AMPR0 SGPCR0 ASGPCR0 MPR1 AMPR1 SGPCR1 ASGPCR1 MPR2 AMPR2 SGPCR2 ASGPCR2 MPR3 AMPR3 SGPCR3 ASGPCR3 MPR4 AMPR4 SGPCR4 ASGPCR4 MPR5 AMPR5 SGPCR5 ASGPCR5 MPR6 AMPR6 SGPCR6 ASGPCR6 MPR7 AMPR7 SGPCR7 ASGPCR7 MGPCR0 MGPCR1 MGPCR2 MGPCR3 MGPCR4 MGPCR5 MGPCR6 MGPCR7 Use Alternate Master Priority Register for Slave port 0 General Purpose Control Register for Slave port 0 Alternate General Purpose Control Register for Slave port 0 Master Priority Register for Slave port 1 Alternate Master Priority Register for Slave port 1 General Purpose Control Register for Slave port 1 Alternate General Purpose Control Register for Slave port 1 Master Priority Register for Slave port 2 Alternate Master Priority Register for Slave port 2 General Purpose Control Register for Slave port 2 Alternate General Purpose Control Register for Slave port 2 Master Priority Register for Slave port 3 Alternate Master Priority Register for Slave port 3 General Purpose Control Register for Slave port 3 Alternate General Purpose Control Register for Slave port 3 Master Priority Register for Slave port 4 Alternate Master Priority Register for Slave port 4 General Purpose Control Register for Slave port 4 Alternate General Purpose Control Register for Slave port 4 Master Priority Register for Slave port 5 Alternate Master Priority Register for Slave port 5 General Purpose Control Register for Slave port 5 Alternate General Purpose Control Register for Slave port 5 Master Priority Register for Slave port 6 Alternate Master Priority Register for Slave port 6 General Purpose Control Register for Slave port 6 Alternate General Purpose Control Register for Slave port 6 Master Priority Register for Slave port 7 Alternate Master Priority Register for Slave port 7 General Purpose Control Register for Slave port 7 Alternate General Purpose Control Register for Slave port 7 General Purpose Control Register for Master port 0 General Purpose Control Register for Master port 1 General Purpose Control Register for Master port 2 General Purpose Control Register for Master port 3 General Purpose Control Register for Master port 4 General Purpose Control Register for Master port 5 General Purpose Control Register for Master port 6 General Purpose Control Register for Master port 7
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Always reads 1
1
Always reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0 bit only bit only bit BIT to clear w1c bit BIT
N/A ‘
Figure 10-2. Key to Register Fields Table 10-4. XBAR Register Summary
0 Name 16 MPRn R ($BASE + 0x000 W + n*0x100) R W AMPRn R ($BASE + 0x004 W + n*0x100) R W SGPCRn R0 0 ($BASE + 0x010 W RO HLP + n*0x100) R W ASGPCRn R ($BASE + 0x014 W + n*0x100) R W MGPCRn R ($BASE + 0x800 W + n*0x100 R W Note: for n = 0 to 7 0 0 0 0 0 0 0 0 0 HLP 0 0 0 0 0 0 0 ARB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPE7HPE6HPE5HPE4HPE3HPE2HPE1HPE0 0 0 0 0 0 ARB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARK 0 0 0 0 MSTR_7 0 MSTR_6 0 MSTR_5 0 MSTR_4 0 17 18 MSTR_7 19 20 0 21 22 MSTR_6 23 24 0 25 26 MSTR_5 27 28 0 29 30 MSTR_4 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0
MSTR_3
0
MSTR_2
0
MSTR_1
0
MSTR_0
0
MSTR_3
0
MSTR_2
0
MSTR_1
0
MSTR_0
PCTL
HPE7HPE6HPE5HPE4HPE3HPE2HPE1HPE0 0 0 0 0 0 0 0 0 0 0 0 PARK 0 0 0
PCTL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 AULB
0
10.3.2
XBAR Register Descriptions
The following paragraphs provide detailed descriptions of the various XBAR registers. Table 10-5 provides a key to the terms found in XBAR registers.
Table 10-5. Register Terms
Term Gray bit Access S Supervisor mode only Supervisor or user mode Description Unimplemented bit; always reads as zero;writing has no effect
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Table 10-5. Register Terms (continued)
Term Type r w rw rwm w1c slfclr Reset 0 1 u ? Resets to a logic 0 Resets to a logic 1 Unaffected by reset Reset state is unknown. Read only; writing to this bit has no effect Write only Standard read/write bit. Only software can change a bit’s value (other than a hardware reset). A read/write bit that may be modified by hardware in some fashion other than reset. A status bit that can be read and cleared by writing a logic 1 Self-clearing bit. Writing a 1 has some effect on module, but it always reads as a 0. Description
10.3.2.1
Master Priority Register
The Master Priority Register (MPR) sets the priority of each master port on a per slave port basis and resides in each slave port.
Addr $BASE + 0x000 + n*100 Wait State: 0 Access: S 10 MSTR_5 rw r rw rw rw r rw 11 12 13 14 MSTR_4 rw rw 15
MPRn
Master Priority Register n
0
1
2 MSTR_7
3
4
5
6 MSTR_6
7
8
9
TYPE: Note:
r
rw
rw
rw
r
rw
rw
The reset value for this register is device-dependent 16 17 18 MSTR_3 19 20 21 22 MSTR_2 rw 1 r 0 rw 0 rw 1 rw 0 r 0 rw 0 23 24 25 26 MSTR_1 rw 0 rw 1 r 0 rw 0 27 28 29 30 MSTR_0 rw 0 rw 0 31
TYPE: RESET: Note:
r 0
rw 0
rw 1
The reset value for this register is device-dependent
Note: for n = 0 to 7
Figure 10-3. Master Priority Register n
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Table 10-6. Master Priority Register Descriptions
Name Bit 0 Description Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 7 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 7 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 111 Bit 4 111This master has the lowest priority when accessing the slave port. Settings
MSTR_7
Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 6 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 6 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 110 111This master has the lowest priority when accessing the slave port.
MSTR_6
Bit 8
Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 5 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 5 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 101 111This master has the lowest priority when accessing the slave port.
MSTR_5
Bit 12
Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 4 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 4 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 100 111This master has the lowest priority when accessing the slave port.
MSTR_4
Bit 16
Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 3 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 3 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 011 111This master has the lowest priority when accessing the slave port.
MSTR_3
Bit 20
Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 2 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 2 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 010 111This master has the lowest priority when accessing the slave port.
MSTR_2
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Table 10-6. Master Priority Register Descriptions (continued)
Name Bit 24 Description Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 1 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 1 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 001 Bit 28 111This master has the lowest priority when accessing the slave port. Settings
MSTR_1
Master Priority Register Reserved - This bit is reserved NA for future expansion. It is read as zero and should be written with zero for upward compatibility. Master 0 Priority - These bits set the arbitration priority 000This master has the highest priority for master port 0 on the associated slave port. when accessing the slave port. These bits are initialized by hardware reset. The reset value is 000 111This master has the lowest priority when accessing the slave port.
MSTR_0
The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO (Read Only) bit has been set in the slave General Purpose Control Register the Master Priority Register can only be read from, attempts to write to it will have no effect on the MPR and result in an error response. NOTE No two available master ports may be programmed with the same priority level. Attempts to program two or more available masters with the same priority level will result in an error response and the MPR will not be updated.
10.3.2.2
Alternate Master Priority Register
The Alternate Master Priority Register (AMPR) sets the alternate priority of each master port on a per slave port basis. The AMPR has identical function as the MPR. The purpose of the AMPR is to allow the user to set up an alternate set of priorities in the event they want to do some sort of context switching. A hardware input to the XBAR controls (on a slave port by slave port basis) whether or not the slave port uses the MPR or the AMPR.
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AMPRn
Alternate Master Priority Register n
Addr $BASE + 0x004 + n*100 Wait State: 0 Access: S 11 12 13 14 MSTR_4 rw 1 27 r 0 28 rw 1 29 rw 0 30 MSTR_0 rw 1 r 0 rw 0 rw 0 rw 0 rw 0 31 15
0
1
2 MSTR_7
3
4
5
6 MSTR_6
7
8
9
10 MSTR_5
TYPE: RESET: Note:
r 0 16
rw 1 17
rw 1 18 MSTR_3
rw 1 19
r 0 20
rw 1 21
rw 1 22 MSTR_2
rw 0 23
r 0 24
rw 1 25
rw 0 26 MSTR_1
TYPE: RESET: Note:
r 0 -
rw 0 -
rw 1 -
rw 1 -
r 0 -
rw 0 -
rw 1 -
rw 0 -
r 0 -
rw 0 -
rw 0 -
Note: for n = 0 to 7
Figure 10-4. Alternate Master Priority Register n
See Table 10-6 for descriptions of bit fields in the AMPR as they are identical. The Alternate Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. Once the RO (Read Only) bit has been set in the General Purpose Control Register the Alternate Master Priority Register can only be read from, attempts to write to it will have no effect on the AMPR and result in an error response. Additionally, no two available master ports may be programmed with the same priority level. Attempts to program two or more available masters with the same priority level will result in an error response and the AMPR will not be updated.
10.3.2.3
Slave General Purpose Control Register
The Slave General Purpose Control Register (SGPCR) controls several features of each slave port. The Read Only (RO) bit will prevent any registers associated with this slave port from being written to once set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only a reset condition will allow it to be written again. The Halt Low Priority (HLP) bit will set the priority of the max_halt_request input to the lowest possible priority for initial arbitration of the slave ports. By default it is the highest priority. Setting this bit will not effect the max_halt_request from attaining highest priority once it has control of the slave ports. The PCTL bits determine how the slave port will park when no master is actively making a request. The available options are to park on the master defined by the PARK bits, park on the last master to use the slave port, or go into a low power park mode which will force all the outputs of the slave port to inactive states when no master is requesting an access. The low power park feature can result in an overall power
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savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any master tries to access it when it is not in use because it will not be parked on any master. The PARK bits determine which master the slave will park on when no master is making an active request and the max_halt_request input is negated. Please use caution to only select master ports that are actually present in the design. If the user programs the PARK bits to a master not present in the current design implementation undefined behavior will result.
Addr $BASE + 0x010 + n*100 Wait State: 0 Access: S 11 12 13 14 15
SGPCRn
Slave General Purpose Control Register n
0 RO TYPE: RESET: Note: rw 0
1 HLP rw 0
2
3
4
5
6
7
8
9
10
HPE HPE HPE HPE HPE HPE HPE HPE 7 6 5 4 3 2 1 0 r 0 r 0 r 0 r 0 r 0 r 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0
Once the RO bit is written to a 1, only hardware reset will return it to a 0. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PARK r 0 rw 0 rw 0 rw 0 31
ARB TYPE: RESET: Note: r 0 r 0 r 0 r 0 r 0 r 0 rw 0 rw 0 r 0 r 0 -
PCTL rw 0 rw 0 -
Note: for n = 0 to 7
Figure 10-5. Slave General Purpose Control Register n Table 10-7. Slave General Purpose Control Register Descriptions
Name RO Description Setting
Read Only - This bit is used to force all of a slave port’s 0 All this slave port’s registers can be registers to be read only. Once written to 1 it can only be written. cleared by hardware reset. 1 All this slave port’s registers are read only and cannot be written (attempted writes have This bit is initialized by hardware reset. no effect and result in an error response). The reset value is 0 Halt Low Priority - This bit is used to set the initial arbitration priority of the max_halt_request input. This bit is initialized by hardware reset. The reset value is 0 0 The max_halt_request input has the highest priority for arbitration on this slave port 1 The max_halt_request input has the lowest initial priority for arbitration on this slave port.
HLP
Bits 2–7
Slave General Purpose Control Register Reserved - NA These bits are reserved for future expansion. They read as zero and should be written with zero for upward compatibility.
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Table 10-7. Slave General Purpose Control Register Descriptions (continued)
Name HPEx Description Setting
High Priority Enable - These bits are used to enable the 0 The mX_high_priority input is disabled on mX_high_priority inputs for the respective master. this slave port 1 The mX_high_priority input is enabled on These bits are initialized by hardware reset. this slave port. The reset value is 0 Slave General Purpose Control Register Reserved These bits are reserved for future expansion. They are read as zero and should be written with zero for upward compatibility. Arbitration Mode - These bits are used to select the arbitration policy for the slave port. These bits are initialized by hardware reset. The reset value is 00 NA
Bits 16–21
ARB
00 Fixed Priority. 01 Round Robin (rotating) Priority. 10 Reserved 11 Reserved NA
Bits 24–25
Slave General Purpose Control Register Reserved These bits are reserved for future expansion. They are read as zero and should be written with zero for upward compatibility. Parking Control - These bits determine the parking control used by this slave port. These bits are initialized by hardware reset. The reset value is 00.
PCTL
00 When no master is making a request the arbiter will park the slave port on the master port defined by the PARK bit field. 01 When no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10 When no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11 Reserved
Bit 28
Slave General Purpose Control Register Reserved - NA This bit is reserved for future expansion. It is read as zero and should be written with zero for upward compatibility. PARK - These bits are used to determine which master 000Park on Master Port 0 port this slave port parks on when no masters are actively 001Park on Master Port 1 making requests and the PCTL bits are set to 00. 010Park on Master Port 2 011Park on Master Port 3 These bits are initialized by hardware reset. 100Park on Master Port 4 The reset value is 000 101Park on Master Port 5 110Park on Master Port 6 111Park on Master Port 7
PARK
The SGPCR can only be accessed in supervisor mode with 32-bit accesses. Once the RO (Read Only) bit has been set in the SGPCR the SGPCR can only be read, attempts to write to it will have no effect on the SGPCR and result in an error response.
10.3.2.4
Alternate Slave General Purpose Control Register
The Alternate Slave General Purpose Control Register (ASGPCR) has identical function as the SGPCR with the notable exception that it lacks the RO (Read Only) bit contained in the SGPCR. The purpose of the ASGPCR is the same as the AMPR, to allow the user to set up an alternate set of general control fields
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in the event they want to do some sort of context switching. A hardware input to the XBAR controls (on a slave port by slave port basis) whether or not the slave port uses the SGPCR or ASGPCR. NOTE The ASGPCR does not contain a RO (Read Only) bit. The RO bit in the SGPCR has control over the ASGPCR’s ability to be written.
Addr $BASE + 0x014 + n*100 Wait State: 0 Access: S 12 13 14 15
ASGPCRn
Alternate Slave General Purpose Control Register n
0
1 HLP
2
3
4
5
6
7
8
9
10
11
HPE HPE HPE HPE HPE HPE HPE HPE 7 6 5 4 3 2 1 0 r 0 18 r 0 19 r 0 20 r 0 21 r 0 22 r 0 23 rw 0 24 rw 0 25 rw 0 26 rw 0 27 rw 0 28 rw 0 29 rw 0 30 PARK r 0 rw 0 rw 0 rw 0 rw 0 31
TYPE: RESET: Note:
r 0 16
rw 0 17
ARB TYPE: RESET: Note: r 0 r 0 r 0 r 0 r 0 r 0 rw 0 rw 0 r 0 r 0 -
PCTL rw 0 rw 0 -
Note: for n = 0 to 7
Figure 10-6. Alternate Slave General Purpose Control Register n
See Table 10-7 for descriptions of bit fields in the ASGPCR as they are identical except for the RO bit. The ASGPCR can only be accessed in supervisor mode with 32-bit accesses. Once the RO (Read Only) bit has been set in the SGPCR the ASGPCR can only be read from, attempts to write to it will have no effect on the ASGPCR and result in an error response.
10.3.2.5
Master General Purpose Control Register
The Master General Purpose Control Register (MGPCR) presently controls only whether or not the master’s undefined length burst accesses will be allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters. The AULB (Arbitrate on Undefined Length Bursts) bit field determines whether (and when) or not the XBAR will arbitrate away the slave port the master owns when the master is performing undefined length burst accesses. If the user has configured the XBAR to have less than eight master ports only the registers associated with the remaining master ports will be present, all other registers will become reserved locations in memory.
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MGPCRn
Master General Purpose Control Register n
Addr $BASE + 0x800 + n*100 Wait State: 0 Access: S 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10
TYPE: RESET: Note:
r 0 16
r 0 17
r 0 18
r 0 19
r 0 20
r 0 21
r 0 22
r 0 23
r 0 24
r 0 25
r 0 26
r 0 27
r 0 28
r 0 29
r 0 30 AULB
r 0 31
TYPE: RESET: Note:
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
r 0 -
rw 0 -
rw 0 -
rw 0 -
Note: for n = 0 to 7
Figure 10-7. Master General Purpose Control Register n Table 10-8. Master General Purpose Control Register Descriptions
Name Bits 0–28 Description Master General Purpose Control Register Reserved - These bits are reserved for future expansion. They read as zero and should be written with zero for upward compatibility. Arbitrate on Undefined Length Bursts - These bits are used to select the arbitration policy during undefined length bursts by this master. These bits are initialized by hardware reset. The reset value is 000 NA Setting
AULB
000No arbitration will be allowed during an undefined length burst. 001Arbitration will be allowed at any time during an undefined length burst. 010Arbitration will be allowed after four beats of an undefined length burst. 011Arbitration will be allowed after eight beats of an undefined length burst. 100Arbitration will be allowed after 16 beats of an undefined length burst. 101Reserved 110Reserved 111Reserved
The MGPCR can only be accessed in supervisor mode with 32-bit accesses.
10.3.3
Coherency
Since the content of the registers has a real time effect on the operation of the XBAR it is important for the user to understand that any register modifications take effect as soon as the register is written. The values of the registers do not track with slave port related AHB accesses but instead track only with IP bus accesses.
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The exception to this rule are the AULB bits in the MGPCR. These update of these bits is only recognized when the master on that master port runs an IDLE cycle, even though the IP bus cycle to write them will have long since terminated successfully. If the AULB bits in the MGPCR are written in between two burst accesses the new AULB encodings will not take effect until an IDLE cycle has been initiated by the master on that master port.
10.4
Function
This section describes in more detail the functionality of the XBAR.
10.4.1
Arbitration
The XBAR supports two arbitration schemes; a simple fixed-priority comparison algorithm, and a simple round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave port.
10.4.1.1
Arbitration During Undefined Length Bursts
Arbitration points during an undefined length burst are defined by the current master’s MGPCR AULB field setting. When a defined length is imposed on the burst via the AULB bits the undefined length burst will be treated as a single or series of single back to back fixed length burst accesses. Example: A master runs an undefined length burst and the AULB bits in the MGPCR indicate arbitration will occur after the fourth beat of the burst. The master runs two sequential beats and then starts what will be an 12 beat undefined length burst access to a new address within the same slave port region as the previous access. The XBAR will not allow an arbitration point until the fourth overall access (second beat of the second burst). At that point all remaining accesses will be open for arbitration until the master loses control of the slave port. Assume the master loses control of the slave port after the fifth beat of the second burst. Once the master regains control of the slave port no arbitration point will be available until after the master has run four more beats of its burst. After the fourth beat of the (now continued) burst (ninth beat of the second burst from the master’s perspective) is taken all beats of the burst will once again be open for arbitration until the master loses control of the slave port. Assume the master again loses control of the slave port on the fifth beat of the third (now continued) burst (10th beat of the second burst from the master’s perspective). Once the master regains control of the slave port it will be allowed to complete its final two beats of its burst without facing arbitration. Note that fixed length burst accesses are not affected by the AULB bits. All fixed length burst accesses lock out arbitration until the last beat of the fixed length burst.
10.4.1.2
Fixed Priority Operation
When operating in fixed-priority mode, each master is assigned a unique priority level in the MPR (Master Priority Register) and AMPR (Alternate Master Priority Register). If two masters both request access to a
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slave port the master with the highest priority in the selected priority register will gain control over the slave port. Any time a master makes a request to a slave port the slave port checks to see if the new requesting master’s priority level is higher than that of the master that currently has control over the slave port (unless the slave port is in a parked state). The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. If the new requesting master’s priority level is higher than that of the master that currently has control of the slave port the new requesting master will be granted control over the slave port at the next clock edge. The exception to this rule is if the master that currently has control over the slave port is running a fixed length burst transfer or a locked transfer. In this case the new requesting master will have to wait until the end of the burst transfer or locked transfer before it will be granted control of the slave port. If the master is running an undefined length burst transfer the new requesting master must wait until an arbitration point for the undefined length burst transfer before it will be granted control of the slave port. Arbitration points for an undefined length burst are defined in the MGPCR for each master. If the new requesting master’s priority level is lower than that of the master that currently has control of the slave port the new requesting master will be forced to wait until the master that currently has control of the slave port either runs an IDLE cycle or runs a non IDLE cycle to a location other than the current slave port.
10.4.1.3
Round-Robin Priority Operation
When operating in round-robin mode, each master is assigned a relative priority based on the master number.This relative priority is compared to the ID of the last master to perform a transfer on the slave bus. The highest priority requesting master will become owner of the slave bus as the next transfer boundary (accounting for locked and fixed-length burst transfers). Priority is based on how far ahead the ID of the requesting master is to the ID of the last master (ID is defined by master port number, not the hmaster field). Once granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line will be granted access to the slave port at the next assertion of sX_hready, or possibly on the next clock cycle if the current master has no pending access request. As an example of arbitration in round-robin mode, assume the XBAR is implemented with master ports 0, 1, 4 and 5. If the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, they will be serviced in the order 4, 5 and then 0. Parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the parked master actually performs a transfer. Handoff will occur to the next master in line after one cycle of arbitration. If the slave port is put into low power park mode the round-robin pointer will be reset to point at master port 0, giving it the highest priority. Each master port has an mX_high_priority input which can be enabled by writing the correct data to the SGPCR or ASGPCR. If a master’s mX_high_priority input is enabled for a slave port programmed for round-robin mode, that master can force the slave port into fixed priority mode by asserting its mX_high_priority input while making a request to that particular slave port. While that (or any enabled)
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master’s mX_high_priority input is asserted while making an access attempt to that particular slave port, the slave port will remain in fixed priority mode. Once that (or any enabled) master’s mX_high_priority input is negated, or the master no longer attempts to make accesses to that particular slave port, the slave port will revert back to round-robin priority mode and the pointer will be set on the last master to access the slave port.
10.4.2
Priority Assignment
Each master port needs to be assigned a unique 3-Bit priority level. If an attempt is made to program multiple master ports with the same priority level within a register (MPR or AMPR) the XBAR will respond with an error and the registers will not be updated.
10.4.2.1
Context Switching
The XBAR has a hardware input per slave port (sX_ampr_sel) which is used to select which registers the master priority levels and general purpose control bits will be taken from. When sX_ampr_sel is 0 the MPR and SGPCR will be selected, when sX_ampr_sel is 1 the AMPR and the ASGPCR will be selected. This hardware input is useful for context switching so the user does not have to rewrite the MPR or SGPCR if a particular slave port would temporarily benefit from modifying the master priority levels or functions affected by the bits in the SGPCR.
10.4.2.2
Priority Elevation
The XBAR has a hardware input per master port (mX_high_priority) which is used to temporarily elevate the master’s priority level on all slave ports. When the master’s mX_high_priority input is asserted the master port will automatically have higher priority than all other master ports that do not have their mX_high_priority input asserted regardless of the priority levels programmed in the MPR and AMPR. If multiple master ports have their mX_high_priority input asserted they will have higher priority than all master ports which do not have their mX_high_priority inputs asserted. The MPR or AMPR priority level (dependent on the state of sX_ampr_sel) will determine which master port that has its mX_high_priority input asserted has the highest priority on a slave port by slave port basis. This functionality is useful because it allows the user to automatically elevate a master port’s priority level throughout the XBAR in order to quickly perform temporary tasks such as servicing interrupts. Please note that the HPEx bits must be set in the SGPCR or ASGPCR in the slave port in order for the mX_high_priority inputs to be received by the slave port.
10.4.3
10.4.3.1
Master Port Functionality
General
Each master port consists of two decoders, a capture unit, a register slice, a mux and a small state machine. The first decoder is used to decode the mX_hsel_slv and control signals coming directly from the master, telling the state machine where the master’s next access will be and if it is in fact a legal access. The second decoder receives its input from the capture unit, so it may be looking directly at the signals coming from
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the master or it may be looking at captured signals coming from the master, depending entirely on the state of the targeted slave port. The second decoder is then used to generate the access requests that go to the slave ports. The capture unit is used to capture the address and control information coming from the master in the event that the targeted slave port cannot immediately service the master. The capture unit is controlled by outputs from the state machine which tell it to either pass through the original master signals or the captured signals. The register slice contains the registers associated with the specific master port. The registers have a quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine. The mux is used simply to select which slave’s read data is sent back to the master. The mux is controlled by the state machine. The state machine controls all aspects of the master port. It knows which slave port the master wants to make a request to and controls when that request is made. It also has knowledge of each slave port, knowing whether or not the slave port is ready to accept an access from the master port. This will determine whether or not the master may immediately have its request taken by the slave port or whether the master port will have to capture the master’s request and queue it at the slave port boundary. A block diagram of a master port can be seen in Figure 10-8.
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Capture Unit Addr/Cntrl Addr/Cntrl Async/Flopped_sel
Decoder Addr/Cntrl Slave_port_rqst[7:0] Request_enable
Decoder Addr/Cntrl Next_slave_port[7:0] Illegal_access
State Machine Next_slave_port[7:0] Async/Flopped_sel Illegal_access Request_enable Hready_in Slv_hready[7:0] Hready_out Slv_hresp[7:0] Hresp Slv_is_mine[7:0] Rdata_sel Control_bits Registers Read_sel Write_sel Wdata Control_bits Xfr_wait Xfr_error Rdata Mux
Sel Hrdata Slv_hrdata[7:0]
Figure 10-8. XBAR Master Port Block Diagram
10.4.3.2
Master Port Decoders
The decoders are very simple as they ensure an access request is allowed to be made and that the slave port targeted is actually present in the design. The decoders feeding the state machine are always enabled. The
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decoders that select the slave are enabled only when the master port controlling state machine wants to make a request to a slave port. This is necessary so that if a master port is making an access to a slave port and is being wait stated, and its next access is to a different slave port, the request to the second slave port can be held off until the access to the first slave port is terminated. The decoders also output a “hole decode” or illegal access signal which tells the state machine that the master is trying to access a slave port that does not exist.
10.4.3.3
Master Port Capture Unit
The capture unit simply captures the state of the master’s address and control signals if the XBAR cannot immediately pass the master’s request through to the proper slave port. The capture unit consists of a set of flops and a mux which selects either the asynchronous path from address and control or the flopped (captured) address and control information.
10.4.3.4
Master Port Registers
The registers in the master port are only those registers associated with this particular master port. The read and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level because not all the IP bus signals are routed this deep in the design. There is a register control block at the same level of the master port and slave port instantiations in the XBAR. This control block ensures that all accesses are 32-bit supervisor accesses before passing them on to the master ports. The register outputs are connected directly to the state machine.
10.4.3.5
10.4.3.5.1
Master Port State Machine
Master Port State Machine States
The master side state machine’s main function is to monitor the activities of the master port. The state machine has six states: busy, idle, waiting, stalled, steady state, first cycle error response and second cycle error response. The busy state is used when the master runs a BUSY cycle to the master port. The master port maintains its request to the slave port if it currently owns the slave port; however, if it loses control of the slave port it will no longer maintain its request. If the master port loses control of the slave port it will not be allowed to make another request to the slave port until it runs a NSEQ or SEQ cycle. The idle state is used when the master runs a valid IDLE cycle to the master port. The master port makes no requests to the slave ports (disables the slave port decoder) and terminates the IDLE cycle. The waiting state is used when the hsel signal is negated to the master port, indicating the master is running valid cycles to a local slave other than the XBAR. In this case the max disables the slave port decoder and holds hresp and hready negated. The stalled state is used when the master makes a request to a slave port that is not immediately ready to receive the request. In this case the state machine will direct the capture unit to send out the captured
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address and control signals and will enable the slave port decoder to indicate a pending request to the appropriate slave port. The steady state state is used when the master port and slave port are in fully asynchronous mode, making the XBAR completely transparent in the access. The state machine selects the appropriate slave’s hresp, hready and hrdata to pass back to the master. The first cycle error response and second cycle error response states are self explanatory. The XBAR will respond with an error response to the master if the master tries to access an unimplemented memory location through the XBAR (that is, a slave port that does not exist). 10.4.3.5.2 Master Port State Machine Slave Swapping
The design of the master side state machine is fairly straightforward. The one real decision to be made is how to handle the master moving from one slave port access to another slave port access. The approach that was taken is to minimize or eliminate when possible any “bubbles” that would be inserted into the access due to switching slave ports. The state machine will not allow the master to request access to another slave port until the current access being made is terminated. This prevents a single master from owning two slave ports at the same time (the slave port it is currently accessing and the slave port it wishes to access next). The state machine also maintains watch on the slave port the master is accessing as well as the slave port the master wishes to switch to. If the new slave port is parked on the master then the master will be able to make the switch without incurring any delays. The termination of the current access will also act as the launch of the new access on the new slave port. If the new slave port is not parked on the master then the master will incur a minimum one clock delay before it can launch its access on the new slave port. This is the same for switching from the busy, idle or waiting state to actively accessing a slave port. If the slave port is parked on the master the state machine will go to the steady state state and the access will begin immediately. If the slave port is not parked on the master (serving another master, parked on another master or in low power park mode) then the state machine will transition to the stalled state and at least a one clock penalty will be paid.
10.4.4
10.4.4.1
Slave Port Functionality
General
Each slave port consists of a register slice, a bank of muxes and a state machine. The register slice contains the registers associated with the specific slave port. The registers have a quasi-IP bus interface at this level for reads and writes and the outputs feed directly into the state machine. The muxes are a series of 8 to 1 muxes that take in all the address, control and write data information from each of the master ports and then pass the correct master’s signals to the slave port. The state machine controls all the muxes. The state machine is where the main slave port arbitration occurs, it decides which master is in control of the slave port and which master will be in control of the slave port in the next bus cycle.
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A block diagram of a slave port can be seen in Figure 10-9. Registers Read_sel Write_sel ampr_sel Wdata Control_bits Xfr_wait Xfr_error Rdata State Machine Master_requests[7:0] Control_bits m[7:0]_high_priority Slv_hready halt_request Slv_hresp Master_sel[7:0] slave_halted Current_master[7:0] Force_idle Master_hready[7:0] Force_nseq Master_hresp[7:0] Muxes Force_nseq Force_idle Master_addr[7:0] Master_sel[7:0] Master_cntrl[7:0] Slv_addr_signals Master_wdata[7:0] Slv_cntrl_signals Slv_wdata
Figure 10-9. XBAR Slave Port Block Diagram
10.4.4.2
Slave Port Muxes
The block diagram (Figure 10-9) shows only one block for all the muxes. In reality that block instantiates many 8 to 1 muxes, one for each master-to-slave signal in fact. All the muxes are designed in an AND OR fashion, so that if no master is selected the output of the muxes will be zero. (This is an important feature for low power park mode.) The muxes also have an override signal which is used by the slave port to asynchronously force IDLE cycles onto the slave bus. When the state machine forces an IDLE cycle it zeros out htrans and hmastlock, making sure the slave bus sees a valid IDLE cycle being run by the XBAR. The enable to the mux controlling htrans also contains an additional control signal from the state machine so that a NSEQ transaction can be forced. This is done any time the slave port switches masters to ensure
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that no IDLE-SEQ, BUSY-SEQ or NSEQ-SEQ transactions are seen on the slave port when they shouldn’t be. If the state machine indicates to run both an IDLE and an NSEQ cycle, the IDLE directive will have priority. NOTE IDLE-SEQ is in fact an illegal access, but a possible scenario given the multi-master environment in the XBAR unless corrected by the XBAR.
10.4.4.3
Slave Port Registers
There is a register control block at the same level of the master port and slave port instantiations in the XBAR. This control block ensures that all accesses are 32-bit supervisor accesses before passing them on to the master and slave ports. The registers in the slave port are only those registers associated with this particular slave port. The read and write interface for the registers is a quasi-IP bus interface. It is not a full IP bus interface at this level because not all the IP bus signals are routed this deep in the design. The register outputs are connected directly to the slave state machine with the sX_ampr_sel input determining which priority register values, halt priority value, arbitration algorithm and parking control bits are passed to the state machine. The registers can be read from an unlimited number of times. The registers can only be written to as long as the RO bit is written to 0 in the SGPCR, once it is written to a 1 only a hardware reset will allow the registers to be written again.
10.4.4.4
10.4.4.4.1
Slave Port State Machine
Slave Port State Machine States
At the heart of the slave port is the state machine. The state machine is simplicity itself, requiring only four states - steady state, transition state, transition hold state and hold state. Either the slave port is owned by the same master it was in the last clock cycle (either by active use or by parking), it is transitioning to a new master (either for active use or parking), it is transitioning to a new master during wait states or it is being held on the same master pending a transition to a new master. 10.4.4.4.2 Slave Port State Machine Arbitration
The real work in the state machine is determining which master port will be in control of the slave port in the next clock cycle, the arbitration. Each master is programmed with a fixed 3 bit priority level. A fourth priority bit is derived from the mX_high_priority inputs on the master ports, effectively making each master’s priority level a 4 bit field with mX_high_priority being the MSB. The XBAR uses these bits in determining priority levels when programmed for fixed priority mode of operation or when one of the enabled mX_high_priority inputs is asserted. Arbitration always occurs on a clock edge, but only occurs on edges when a change in mastership will not violate AHB-Lite protocols. Valid arbitrations points include any clock cycle in which sX_hready is asserted (provide the master is not performing a burst or locked cycle) and any wait state in which the master owning the bus indicates a transfer type of IDLE (provided the master is not performing a locked cycle).
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Since arbitration can occur on every clock cycle the slave port masks off all master requests if the current master is performing a locked transfer or a protected burst transfer, guaranteeing that no matter how low its priority level it will be allowed to finish its locked or protected portion of a burst sequence. 10.4.4.4.3 Slave Port State Machine Master Handoff
The only times the slave port will switch masters when programmed for fixed priority mode of operation is when a higher priority master makes a request or when the current master is the highest priority and it gives up the slave port by either running and IDLE cycle to the slave port or running a valid access to a location other than the slave port. If the current master loses control of the slave port because a higher priority master takes it away, the slave port will not incur any wasted cycles. The current master has its current cycle terminated by the slave port at the same time the new master’s address and control information are recognized by the slave port. This appears as a seamless transition on the slave port. If the current master is being wait-stated when the higher priority master makes its request, then the current master will be allowed to make one more transaction on the slave bus before giving it up to the new master. Figure 10-10 illustrates the effect of a higher priority master taking control of the bus when the slave port is programmed for a fixed priority mode of operation.
1
hclk m2 request m3 request m4 request m5 request Highest Priority Requester Address/Cntrl owner htrans hready Master 5 Master 5 Master 4 Master 3 Master 2 XBAR IDLE Master 5 NSEQ Master 5 NSEQ Master 3 Master 2 NSEQ Master 4 None XBAR IDLE
2
3
4
5
6
7
8
9
10
Master 3 Master 4 NSEQ NSEQ
Figure 10-10. Low to high priority mastership change
If the current master is the highest priority master and it gives up the slave port by running an IDLE cycle or by running a valid cycle to another location other than the slave port the next highest priority master will gain control of the slave port. If the current access incurs any wait states then the transition will be seamless and no bandwidth will be lost; however, if the current transaction is terminated without wait states then one IDLE cycle will be forced onto the slave bus by the XBAR before the new master will be able to take control of the slave port. If no other master is requesting the bus then IDLE cycles will be run
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by the XBAR but no bandwidth will truly be lost since no master is making a request. Figure 10-11 illustrates the effect of a higher priority master giving up control of the bus.
1
hclk m0 request m2 request m4 request Highest Priority Requester Address/Cntrl owner htrans hready XBAR IDLE Master 0 Master 0 NSEQ Master 2 XBAR IDLE None Master 2 NSEQ Master 4 XBAR IDLE None Master 4 NSEQ XBAR IDLE
2
3
4
5
6
7
8
9
Figure 10-11. High to low priority mastership change
When the slave port is programmed for round-robin mode of arbitration then the slave port will switch masters any time there is more than one master actively making a request to the slave port. This will happen because any master other than the one which presently owns the bus will be considered to have higher priority. Figure 10-12 shows an example of round-robin mode of operation.
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1
hclk m0 request m1 request m4 request m5 request Highest Priority Requester Address/Cntrl owner htrans hready
2
3
4
5
6
7
8
9
10
Master 1 Master 4 XBAR IDLE Master 1 NSEQ
Master 5 Master 4 NSEQ
Master 0 Master 5 NSEQ
Master 4 Master 0 NSEQ
Master 5
None
Master 4 Master 5 XBAR NSEQ NSEQ IDLE
Figure 10-12. Round-robin mastership change
10.4.4.4.4
Slave Port State Machine Parking
If no master is currently making a request to the slave port then the slave port will be parked. It will park in one of four places, dictated by the PCTL and PARK bits in the GPCR or AGPCR (depending on the state of the sX_ampr_sel) and the locked state of the last master to access it. If the last master to access the slave port ran a locked cycle and continues to run locked cycles even after leaving the slave port the slave port will park on that master without regard to the bit settings in the GPCR and without regard to pending requests from other masters. This is done so a master can run a locked transfer to the slave port, leave it, and return to it and be guaranteed that no other master has had access to it (provided the master maintains all transfers are locked transfers). If locking is not an issue for parking the GPCR bits will dictate the parking method. If the PCTL bits are set for “low power park” mode then the slave port will enter low power park mode. It will not recognize any master as being in control of it and it will not select any master’s signals to pass through to the slave bus. In this case all slave bus activity will effectively halt because all slave bus signals being driven from the XBAR will be 0. This of course can save quite a bit of power if the slave port will not be in use for some time. The down side is that when a master does make a request to the slave port it will be delayed by one clock since it will have to arbitrate to acquire ownership of the slave port. If the PCTL bits are set to “park on last” mode then the slave port will park on the last master to access it, passing all that masters signals through to the slave bus. The XBAR will asynchronously force htrans[1:0], hmaster[3:0], hburst[2:0] and hmastlock to 0 for all access that the master does not run to the slave port. When that master access the slave port again it will not pay any arbitration penalty; however, if any other master wishes to access the slave port a one clock arbitration penalty will be imposed.
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If the PCTL bits are set to “use PARK/APARK” mode then the slave port will park on the master designated by the PARK bits. The behavior here is the same as for the “park on last” mode with the exception that a specific master will be parked on instead of the last master to access the slave port. If the master designated by the PARK bits tries to access the slave port it will not pay an arbitration penalty while any other master will pay a one clock penalty. Figure 10-13 illustrates parking on a specific master.
1
hclk m0 request m2 request m4 request Park Highest Priority Requester Address/Cntrl owner htrans hready Master 0 XBAR IDLE None Master 0 NSEQ Master 2 Master 2 NSEQ None XBAR IDLE Master 2 Master 4 XBAR IDLE None Master 4 NSEQ Master 2 Master 2 NSEQ None XBAR IDLE
2
3
4
5
6
7
8
9
Figure 10-13. Parking on a specific master
Figure 10-14 illustrates parking on the last master. Note that in cycle 6 simultaneous requests are made by master 2 and master 4. Although master 2 has higher priority, the slave bus is parked on master 4 so master 4’s access will be taken first. The slave port parks on master 2 once it has given control to master 2. This same situation can occur when parking on a specific master as well.
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1
hclk m0 request m2 request m4 request Park Highest Priority Requester Address/Cntrl owner htrans hready Last Master Master 0 XBAR IDLE
2
3
4
5
6
7
8
9
Master 0 None Master 0 NSEQ Master 4 XBAR IDLE
Master 4 None Master 4 NSEQ XBAR IDLE Master 2 Master 4 NSEQ
Master 2 None Master 2 NSEQ XBAR IDLE
Figure 10-14. Parking on last master
10.4.4.4.5
Slave Port State Machine Halt Mode
If the max_halt_request input is asserted the slave port will eventually halt all slave bus activity and go into halt mode, which is almost identical to low power park mode. The HLP bit in the GPCR controls the priority level of the max_halt_request in the arbitration algorithm. If the HLP bit is cleared then the max_halt_request will have the highest priority of any master and will gain control of the slave port at the next arbitration point (most likely the next bus cycle, unless the current master is running a locked or fixed length burst transfer). If the HLP bit is set then the slave port will wait until no masters are actively making requests before moving to halt mode. Regardless of the state of the HLP bit, once the slave port has gone into halt mode as a result of max_halt_request being asserted, it will remain in halt mode until max_halt_request is negated, regardless of the priority level of any masters that may make requests. In halt mode no master is selected to own the slave port so all the outputs of the slave port are set to 0.
10.5
Initialization/Application Information
No initialization is required by or for the XBAR. Hardware reset ensures all the register bits used by the XBAR are properly initialized.
10.6
Interface
This section provides information on the XBAR interface.
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10.6.1
Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate in parallel with multiple slaves. In order to maximize data throughput it is essential to keep arbitration delays to a minimum. This section examines data throughput from the point of view of masters and slaves, detailing when the XBAR will stall the masters or insert bubbles on the slave side.
10.6.2
Master Ports
Master accesses will receive one of four responses from the XBAR. They will either be ignored, terminated, taken, stalled or responded to with an error.
10.6.2.1
Ignored Accesses
A master access will be ignored if the hsel input of the XBAR is not asserted. The XBAR will respond to IDLE transfers when the hsel input is asserted but will not allow the access to pass through the XBAR.
10.6.2.2
Terminated Accesses
A master access will be terminated if the hsel input of the XBAR is asserted and the transfer type is IDLE. The XBAR will terminated the access and it will not be allowed to pass through the XBAR.
10.6.2.3
Taken Accesses
A master access will be taken if the hsel input of the XBAR is asserted and the transfer type is non IDLE and the slave port to which the access decodes is either currently servicing the master or is parked on the master. In this case the XBAR will be completely transparent and the master’s access will be immediately seen on the slave bus and no arbitration delays will be incurred.
10.6.2.4
Stalled Accesses
A master access will be stalled if the hsel input of the XBAR is asserted and the transfer type is non IDLE and the access decodes to a slave port that is busy serving another master, parked on another master or is in low power park mode. The XBAR will indicate to the master that the address phase of the access has been taken but will then queue the access to the appropriate slave port to enter into arbitration for access to that slave port. If the slave port is currently parked on another master or is in low power park mode and no other master is requesting access to the slave port then only one clock of arbitration will be incurred. If the slave port is currently serving another master of a lower priority and the master has a higher priority than all other requesting masters then the master will gain control over the slave port as soon as the data phase of the current access is completed (burst and locked transfers excluded). If the slave port is currently servicing another master of a higher priority then the master will gain control of the slave port once the other master releases control of the slave port if no other higher priority master is also waiting for the slave port.
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10.6.2.5
Error Response Terminated Accesses
A master access will be responded to with an error if the hsel input of the XBAR is asserted and the transfer type is non IDLE and the access decodes to a location not occupied by a slave port. This is the only time the XBAR will respond with an error response. All other error responses received by the master are the result of error responses on the slave ports being passed through the XBAR.
10.6.3
Slave Ports
The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are actively making requests. In order to do this the XBAR must not insert any bubbles onto the slave bus unless absolutely necessary. There is only one instance when the XBAR will force a bubble onto the slave bus when a master is actively making a request. This occurs when a higher priority master has control of the slave port and is running single clock (zero wait state) accesses while a lower priority master is stalled waiting for control of the slave port. When the higher priority master either leaves the slave port or runs an IDLE cycle to the slave port the XBAR will take control of the slave bus and run a single IDLE cycle before giving the slave port to the lower priority master that was waiting for control of the slave port. The only other times the XBAR will have control of the slave port is when the XBAR is halting or when no masters are making access requests to the slave port and the XBAR is forced to either park the slave port on a specific master or put the slave port into low power park mode. In most instances when the XBAR has control of the slave port it will indicate IDLE for the transfer type, negate all control signals and indicate ownership of the slave bus via the hmaster encoding of 4’b0000. One exception to this rule is when a master running locked cycles has left the slave port but continues to run locked cycles. In this case the XBAR will control the slave port and will indicate IDLE for the transfer type but it will not affect any other signals. NOTE When a master runs a locked cycle through the XBAR, the master will be guaranteed ownership of all slave ports it accesses while running locked cycles for one cycle beyond when the master finishes running locked cycles.
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Chapter 11 Peripheral Bridge (PBRIDGE)
Chapter 11 Peripheral Bridge (PBRIDGE)
11.1 Introduction
The peripheral bridge (PBRIDGE1) is the interface between the system bus and on-chip peripherals. The PBRIDGE on this device is the same as the one of all other PPC55xx and PPC56xx products except that it cannot be configured by software and that it has a hard-wired configuration.
11.1.1
Block Diagram
The PBRIDGE block diagram is shown in Figure 11-1. It differs from similar Power Architecture™ products in the fact that its has a hard-wired configuration.
System Bus Crossbar Switch (XBAR)
System Bus
System Bus
Peripheral Bridge PBRIDGE0
Peripheral Bridge PBRIDGE1
ECSM STM SWT INTC
BAM SIUL ADC FlexCAN LINFlex DSPI PIT CTU ...
Figure 11-1. PBRIDGE Interface
1. Other parts of this document may also refer to this module as “AIPS”.
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11.1.2
Overview
There are two PBRIDGEs (PBRIDGE0 and PBRIDGE1), which act as interface between the system bus and lower bandwidth peripherals. Accesses that fall within the address space of the PBRIDGEs are decoded to provide individual module selects for peripheral devices on the slave bus interface.
11.1.3
Features
The following list summarizes the key features of the PBRIDGEs: • Supports the slave interface signals. This interface is only meant for slave peripherals. • Supports 32-bit slave peripherals. (Byte, halfword, and word reads and writes are supported to each.)
11.2
Functional Description
Each PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as a protocol translator. Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for peripheral devices on the slave bus interface.
11.2.1
Access Support
Aligned 32-bit word accesses, halfword accesses, and byte accesses are supported for the peripherals. Peripheral registers must not be misaligned, although no explicit checking is performed by the PBRIDGE. NOTE Data accesses that cross a 32-bit boundary are not supported.
11.2.1.1
Peripheral Write Buffering
Buffered writes are not supported by the PBRIDGEs on this device.
11.2.1.2
Read Cycles
Two-clock read accesses are possible with the PBRIDGE when the requested access size is 32 bits or smaller, and is not misaligned across a 32-bit boundary.
11.2.1.3
Write Cycles
Three clock write accesses are possible with the PBRIDGE when the requested access size is 32 bits or smaller. Misaligned writes that cross a 32-bit boundary are not supported.
11.2.2
General Operation
Slave peripherals are modules that contain readable/writable control and status registers. The system bus master reads and writes these registers through the PBRIDGE. The PBRIDGE generates module enables,
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the module address, transfer attributes, byte enables, and write data as inputs to the slave peripherals. The PBRIDGE captures read data from the slave interface and drives it on the system bus. The PBRIDGE occupies a 64 MB portion of the address space. The register maps of the slave peripherals are located on 16-KB boundaries. Each slave peripheral is allocated one 16-KB block of the memory map, and is activated by one of the module enables from the PBRIDGE. The PBRIDGE is responsible for indicating to slave peripherals if an access is in supervisor or user mode.
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Chapter 12 Flash memory
Chapter 12 Flash memory
12.1 Introduction
The Flash memory comprises a platform Flash controller (PFlash) interface and two Flash memory arrays: one array of 256 Kbyte for code (CFlash) and one array of 64 Kbyte for data (DFlash). The Flash architecture of this device is illustrated in Figure 12-1.
AHB Crossbar Switch
AHB ports
32
4x128 Page Buffer
1x128 Page Buffer
PFlash Controller
256 KB Flash
Data Flash (for EEPROM emulation) Array 0
Array 0
Bank0 (CFlash)
Bank1 (DFlash)
Figure 12-1. Flash memory architecture
12.2
12.2.1
Code Flash
Introduction
The primary function of the Code Flash module is to serve as electrically programmable and erasable non-volatile memory. Non-volatile memory may be used for instruction and/or data storage. The module is a non-volatile solid-state silicon memory device consisting of blocks (also called “sectors”) of single transistor storage elements, an electrical means for selectively adding (programming) and
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removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements. The Flash module is arranged as two functional units: the Flash core and the memory interface. The Flash core is composed of arrayed non-volatile storage elements, sense amplifiers, row decoders, column decoders and charge pumps. The arrayed storage elements in the Flash core are subdivided into physically separate units referred to as blocks (or sectors). The memory interface contains the registers and logic which control the operation of the Flash core. The memory interface is also the interface between the Flash module and a Bus Interface Unit (BIU) and contains the ECC logic and redundancy logic. A BIU connects the Flash module to a system bus, and contains all system level customization required for the device application.
12.2.2
• • • • • • • • • •
Main features
High Read parallelism (128 bits) Error Correction Code (SEC-DED) to enhance Data Retention Double Word Program (64 bits) Sector erase Single bank—Read-While-Write (RWW) not available Erase Suspend available (Program Suspend not available) Software programmable program/erase protection to avoid unwanted writings Censored Mode against piracy Shadow Sector available One-Time Programmable (OTP) area in Test Flash block
12.2.3
Block diagram
The Flash module contains one Matrix Module, composed of a single bank: Bank 0, normally used for code storage. RWW operations are not possible. Modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands to the FPEC are given through a User Registers Interface. The read data bus is 128 bits wide, while the Flash registers are on a separate bus 32 bits wide addressed in the user memory map. The high voltages needed for program/erase operations are generated internally.
Figure 12-2. Flash module structure
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12.2.4
12.2.4.1
Functional description
Module structure
The Flash module is addressable by Double Word (64 bits) for program, and page (128 bits) for read. Reads to the Flash always return 128 bits, although read page buffering may be done in the platform BIU. Each read of the Flash module retrieves a page, or four consecutive words (128 bits) of information. The address for each word retrieved within a page differs from the other addresses in the page only by address bits (3:2). The Flash module supports fault tolerance through Error Correction Code (ECC) or error detection, or both. The ECC implemented within the Flash module will correct single bit failures and detect double bit failures. The Flash module uses an embedded hardware algorithm implemented in the Memory Interface to program and erase the Flash core. The embedded hardware algorithm includes control logic that works with software block enables and software lock mechanisms to guard against accidental program/erase. The hardware algorithm performs the steps necessary to ensure that the storage elements are programmed and erased with sufficient margin to guarantee data integrity and reliability. In the Flash module, logic levels are defined as follows: • A programmed bit reads as logic level 0 (or low). • An erased bit reads as logic level 1 (or high). Program and erase of the Flash module requires multiple system clock cycles to complete. The erase sequence may be suspended. The program and erase sequences may be aborted.
12.2.4.2
Flash module sectorization
The code Flash module supports 256 Kbyte of user memory, plus 16 Kbyte of test memory (a portion of which is One-Time Programmable by the user). An extra 16 Kbyte sector is available as Shadow space usable for user option bits and censorship settings. The Flash module is composed of a single bank (Bank 0): Read-While-Write is not supported. Bank 0 of the Flash module is divided in 4 sectors including a reserved sector, named TestFlash, in which some One-Time Programmable (OTP) user data are stored, as well as a Shadow Sector in which user erasable configuration values can be stored. The matrix module sectorization is shown in Table 12-1.
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Table 12-1. Flash module sectorization
Bank B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 Sector B0F0 B0F1 B0F2 B0F3 B0F4 B0F5 Reserved Reserved B0SH Reserved B0TF Reserved Addresses 0x000000 to 0x007FFF 0x008000 to 0x00BFFF 0x00C000 to 0x00FFFF 0x010000 to 0x017FFF 0x018000 to 0x01FFFF 0x020000 to 0x03FFFF 0x040000 to 0x07FFFF 0x080000 to 0x1FFFFF 0x200000 to 0x203FFF 0x204000 to 0x3FFFFF 0x400000 to 0x403FFF 0x404000 to 0x7FFFFF Size 32Kbyte 16Kbyte 16Kbyte 32Kbyte 32Kbyte 128Kbyte 256Kbyte 1536Kbyte 16Kbyte 2032Kbyte 16Kbyte 4080Kbyte Address space Low Address Space Low Address Space Low Address Space Low Address Space Low Address Space Low Address Space Mid Address Space High Address Space Shadow Address Space Shadow Address Space Test Address Space Test Address Space
The division into blocks of the Flash module is also used to implement independent erase/program protection. A software mechanism is provided to independently lock/unlock each block in low, mid and high address space (as reported in Table 12-1) against program and erase. 12.2.4.2.1 TestFlash block
The TestFlash block exists outside the normal address space and is programmed and read independently of the other blocks. The independent TestFlash block is included to also support systems which require non-volatile memory for security or to store system initialization information, or both. A section of the TestFlash is reserved to store the non-volatile information related to Redundancy, Configuration and Protection. The ECC is also applied to TestFlash. The structure of the TestFlash sector is detailed in Table 12-2.
Table 12-2. TestFlash structure
Name — — — NVLML NVHBL NVSLL Description User OTP area Reserved User reserved Non-volatile Low/Mid address space block Locking register Non-volatile High address space Block Locking register Non-volatile Secondary Low/mid address space block Lock register Addresses 0x400000–0x401FFF 0x402000–0x403CFF 0x403D00–0x403DE7 0x403DE8–0x403DEF 0x403DF0–0x403DF7 0x403DF8–0x403DFF Size 8192 byte 7424 byte 232 byte 8 byte 8 byte 8 byte
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Table 12-2. TestFlash structure (continued)
Name — — Description User reserved Reserved Addresses 0x403E00–0x403EFF 0x403F00–0x403FFF Size 256 byte 256 byte
Erase of the Test Flash block is always locked. Programming of the TestFlash block has similar restrictions as the array in terms of how ECC is calculated. Only one programming operation is allowed per 64-bit ECC segment. The first 8 Kbyte of TestFlash block may be used for user defined functions (possibly to store serial numbers, other configuration words or factory process codes). Locations of the TestFlash other than the first 8 Kbyte of OTP area cannot be programmed by the user application. 12.2.4.2.2 Shadow block
A Shadow block is present in the 544 Kbyte Flash module. The Shadow block can be enabled by the BIU. When the Shadow space is enabled, all the operations are mapped to the Shadow block. User Mode program and erase of the shadow block are enabled only when MCR.PEAS is high. The Shadow block may be locked/unlocked against program or erase by using the LML.TSLK and SLL.STSLK registers. Programming of the Shadow block has similar restrictions as the array in terms of how ECC is calculated. Only one programming operation is allowed per 64-bit ECC segment between erases. Erase of the Shadow block is done similarly to a sector erase. The Shadow block contains specified data that are needed for user features. The user area of Shadow block may be used for user defined functions (possibly to store boot code, other configuration words or factory process codes). The structure of the Shadow sector is detailed in Table 12-3.
Table 12-3. Shadow sector structure
Name NVSRC — — NVPWD0– 1 NVSCI0–1 — Description Non-volatile System Reset Configuration register User area Reserved Non-volatile Private Censorship PassWord 0–1 registers Non-volatile System Censorship Information 0–1 registers Reserved Addresses 0x200000–0x200007 0x200008–0x203DCF 0x203DD0–0x203DD7 0x203DD8–0x203DDF 0x203DE0–0x203DE7 0x203DE8–0x203DFF Size 8 byte 15816 byte 8 byte 8 byte 8 byte 24 byte
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Table 12-3. Shadow sector structure (continued)
Name NVBIU2–3 — NVUSRO — Description Non-volatile Bus Interface Unit 2–3 registers Reserved Non-volatile User Options register Reserved Addresses 0x203E00–0x203E0F 0x203E10–0x203E17 0x203E18–0x203E1F 0x203E20–0x203FFF Size 16 byte 8 byte 8 byte 480 byte
12.2.4.3
User mode operation
In User Mode the Flash module may be read and written (register writes and interlock writes), programmed or erased. The default state of the Flash module is read. The main, shadow and test address space can be read only in the read state. The Flash registers are always available for read, also when the module is in power-down mode (except few documented registers). Most of the Flash registers are mapped on Flip-Flops and can be read on IPS bus also when the Flash macrocell is forced in disable mode. Few Flash registers (bits MRE, MRV, AIS, EIE and DSI7-0 of UT0, whole UT1 and UT2) are mapped in Flash SRAM and cannot be read when the Flash is in disable mode (reading returns indeterminate data). The Flash module enters the read state on reset. The module is in the read state under two sets of conditions: • The read state is active when the module is enabled (User Mode Read). • The read state is active when MCR.ERS and MCR.ESUS are high and MCR.PGM is low (Erase Suspend). Notice that Read-While-Write is not available. Flash core reads return 128 bits (1 Page = 2 Double Words). Registers reads return 32 bits (1 Word). Flash core reads are done through the Bus Interface Unit. Registers reads to unmapped register address space will return all 0’s. Registers writes to unmapped register address space will have no effect. Attempted array reads to invalid locations will result in indeterminate data. Invalid locations occur when blocks that do not exist in non 2n array sizes are addressed. Attempted interlock writes to invalid locations will result in an interlock occurring, but attempts to program these blocks will not occur since they are forced to be locked. Erase will occur to selected and unlocked blocks even if the interlock write is to an invalid location.
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Simultaneous Read cycle on the Flash Matrix and Read/Write cycles on the registers are possible. On the contrary, registers read/write accesses simultaneous to a Flash Matrix interlock write are forbidden.
12.2.4.4
Reset
A reset is the highest priority operation for the Flash module and terminates all other operations. The Flash Module uses reset to initialize register and status bits to their default reset values. If the Flash Module is executing a Program or Erase operation (MCR.PGM = 1 or MCR.ERS =1) and a reset is issued, the operation will be suddenly terminated and the module will disable the high voltage logic without damage to the high voltage circuits. Reset terminates all operations and forces the Flash Module into User Mode ready to receive accesses. Reset and power-off must not be used as a systematic way to terminate a Program or Erase operation. After reset is negated, read register access may be done, although it should be noted that registers that require updating from shadow information, or other inputs, may not read updated values until MCR.DONE transitions. MCR.DONE may be polled to determine if the Flash module has transitioned out of reset. Notice that the registers cannot be written until MCR.DONE is high.
12.2.4.5
Power-down mode
All Flash DC current sources can be turned off in power-down mode, so that all power dissipation is due only to leakage in this mode. Reads from or writes to the module are not possible in power-down mode. The user may not read some registers (UMISR0–4, UT1–2 and part of UT0) until the power-down mode is exited. When enabled the Flash module returns to its pre-disable state in all cases unless in the process of executing an erase high voltage operation at the time of disable. If the Flash module is disabled during an erase operation, MCR.ESUS bit is set to ‘1’. The user may resume the erase operation at the time the module is enabled by clearing MCR.ESUS bit. MCR.EHV must be high to resume the erase operation. If the Flash module is disabled during a program operation, the operation will in any case be completed and the power-down mode will be entered only after the programming ends. The user should realize that, if the Flash module is put in power-down mode and the interrupt vectors remain mapped in the Flash address space, the Flash module will greatly increase the interrupt response time by adding several wait-states. It is forbidden to enter in low power mode when the power-down mode is active.
12.2.4.6
Low power mode
The low power mode turns off most of the DC current sources within the Flash module. The module (Flash core and registers) is not accessible for read or write once it enters low power mode.
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Wake-up time from low power mode is faster than wake-up time from power-down mode. The user may not read some registers (UMISR0–4, UT1–2 and part of UT0) until the low power mode is exited. When exiting from low power mode the Flash module returns to its pre-sleep state in all cases unless it is executing an erase high voltage operation at the time low power mode is entered. If the Flash module enters low power mode during an erase operation, bit MCR.ESUS is set to ‘1’. The user may resume the erase operation at the time the module exits low power mode by clearing bit MCR.ESUS. MCR.EHV must be high to resume the erase operation. If the Flash module enters low power mode during a program operation, the operation will be in any case completed and the low power mode will be entered only after the programming end. It is forbidden to enter power-down mode when the low power mode is active.
12.2.5
Register description
Table 12-4. Flash user registers
Register name Module Configuration Register (MCR) Low/Mid address space block Locking register (LML) High address space Block Locking register (HBL) Address offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 Reset value 0x0120_0600 Location on page 287
The Flash user registers mapping is shown in Table 12-4.
0x00XX_XXXX on page 293 0x0000_00XX on page 295
Secondary Low/mid address space block Locking register (SLL) Low/Mid address space block Select register (LMS) High address space Block Select register (HBS) Address Register (ADR) Bus Interface Unit 0 register (BIU0) Bus Interface Unit 1 register (BIU1) Bus Interface Unit 2 register (BIU2) Bus Interface Unit 3 register (BIU3) Reserved Reserved Reserved Reserved User Test 0 register (UT0) User Test 1 register (UT1) User Test 2 register (UT2) User Multiple Input Signature Register 0 (UMISR0)
0x00XX_XXXX on page 296 0x0000_0000 0x0000_0000 0x0000_0000 0XX on page 299 on page 300 on page 301 on page 302
0xXXXX_XXXX on page 303 0xXXXX_XXXX on page 303 0xXXXXXXXX — — — — 0x0000_0001 0x0000_0000 0x0000_0000 0x0000_0000 on page 304 — — — — on page 305 on page 307 on page 308 on page 309
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Table 12-4. Flash user registers (continued)
Register name User Multiple Input Signature Register 1 (UMISR1) User Multiple Input Signature Register 2 (UMISR2) User Multiple Input Signature Register 3 (UMISR3) User Multiple Input Signature Register 4 (UMISR4) Address offset 0x004C 0x0050 0x0054 0x0058 Reset value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Location on page 309 on page 310 on page 311 on page 311
In the following some non-volatile registers are described. Please notice that such entities are not Flip-Flops, but locations of TestFlash or Shadow sectors with a special meaning. During the Flash initialization phase, the FPEC reads these non-volatile registers and updates the corresponding volatile registers. When the FPEC detects ECC double errors in these special locations, it behaves in the following way: • In case of a failing system locations (configurations, device options, redundancy, embedded firmware), the initialization phase is interrupted and a Fatal Error is flagged. • In case of failing user locations (protections, censorship, BIU, ...), the volatile registers are filled with all ‘1’s and the Flash initialization ends setting low the PEG bit of MCR. Table 12-5 lists bit access type abbreviations used in this section.
Table 12-5. Abbreviations
Abbreviation rw rc r w Case read/write read/clear read-only write-only Description The software can read and write to these bits. The software can read and clear to these bits. The software can only read these bits. The software should only write to these bits.
12.2.6
Module Configuration Register (MCR)
Reset value: 0x0120_0600
3 0 r/0 19 0 r/0 4 0 r/0 20 PEAS r/0 5 SIZE2 r/0 21 DONE r/1 6 SIZE1 r/0 22 PEG r/1 7 SIZE0 r/1 23 0 r/0 8 0 r/0 24 0 r/0 9 LAS2 r/0 25 0 r/0 10 LAS1 r/1 26 0 r/0 11 LAS0 r/0 27 PGM rw/0 12 0 r/0 28 PSUS rw/0 13 0 r/0 29 ERS rw/0 14 0 r/0 30 ESUS rw/0 15 MAS r/0 31 EHV rw/0
Address offset: 0x0000
0 EDC rc/0 16 EER rc/0 1 0 r/0 17 RWE rc/0 2 0 r/0 18 0 r/0
Figure 12-3. Module Configuration Register (MCR)
The Module Configuration Register is used to enable and monitor all modify operations of the Flash module.
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Table 12-6. MCR field descriptions
Field 0 Description EDC: Ecc Data Correction (Read/Clear) EDC provides information on previous reads. If an ECC Single Error detection and correction occurred, the EDC bit is set to ‘1’. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may not be set to ‘1’ by the user. In the event of an ECC Double Error detection, this bit will not be set. If EDC is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of EDC) were not corrected through ECC. Since this bit is an error flag, it must be cleared to ‘0’ by writing 1 to the register location. A write of 0 will have no effect. 0: Reads are occurring normally. 1: An ECC Single Error occurred and was corrected during a previous read. Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0. SIZE[2:0]: array space SIZE 2-0 (Read Only) The value of SIZE field is dependent upon the size of the Flash module; see Table 12-7. Reserved (Read Only). Write this bit has no effect and read this bit always outputs 0. LAS[2:0]: Low Address Space 2-0 (Read Only) The value of the LAS field corresponds to the configuration of the Low Address Space; see Table 12-8.
1:4 5:7 8 9:11
12:14 Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0. 15 16 MAS: Mid Address Space (Read Only) The value of the MAS field corresponds to the configuration of the Mid Address Space; see Table 12-9. EER: Ecc event ERror (Read/Clear) EER provides information on previous reads. If an ECC Double Error detection occurred, the EER bit is set to ‘1’. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may not be set to ‘1’ by the user. In the event of an ECC Single Error detection and correction, this bit will not be set. If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of EER) were correct. Since this bit is an error flag, it must be cleared to ‘0’ by writing 1 to the register location. A write of 0 will have no effect. 0: Reads are occurring normally. 1: An ECC Double Error occurred during a previous read. RWE: Read-while-Write event Error (Read/Clear) RWE provides information on previous reads when a Modify operation is on going. If a RWW Error occurs, the RWE bit is set to ‘1’. Read-While-Write Error means that a read access to the Flash Matrix has occurred while the FPEC was performing a program or erase operation or an Array Integrity Check. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may not be set to ‘1’ by the user. If RWE is not set, or remains 0, this indicates that all previous RWW reads (from the last reset, or clearing of RWE) were correct. Since this bit is an error flag, it must be cleared to ‘0’ by writing 1 to the register location. A write of 0 will have no effect. 0: Reads are occurring normally. 1: A RWW Error occurred during a previous read.
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Table 12-6. MCR field descriptions (continued)
Field Description
18:19 Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0. 20 PEAS: Program/Erase Access Space (Read Only) PEAS is used to indicate which space is valid for program and erase operations: main array space or shadow/test space. PEAS = 0 indicates that the main address space is active for all Flash module program and erase operations. PEAS = 1 indicates that the test or shadow address space is active for program and erase. The value in PEAS is captured and held with the first interlock write done for Modify operations. The value of PEAS is retained between sampling events (that is, subsequent first interlock writes). 0: Shadow/Test address space is disabled for program/erase and main address space enabled. 1: Shadow/Test address space is enabled for program/erase and main address space disabled. DONE: modify operation DONE (Read Only) DONE indicates if the Flash Module is performing a high voltage operation. DONE is set to 1 on termination of the Flash Module reset. DONE is cleared to 0 just after a 0 to 1 transition of EHV, which initiates a high voltage operation, or after resuming a suspended operation. DONE is set to 1 at the end of program and erase high voltage sequences. DONE is set to 1 (within tPABT or tEABT, equal to P/E Abort Latency) after a 1 to 0 transition of EHV, which aborts a high voltage Program/Erase operation. DONE is set to 1 (within tESUS, time equals to Erase Suspend Latency) after a 0 to 1 transition of ESUS, which suspends an erase operation. 0: Flash is executing a high voltage operation. 1: Flash is not executing a high voltage operation. PEG: Program/Erase Good (Read Only) The PEG bit indicates the completion status of the last Flash Program or Erase sequence for which high voltage operations were initiated. The value of PEG is updated automatically during the Program and Erase high voltage operations. Aborting a Program/Erase high voltage operation will cause PEG to be cleared to 0, indicating the sequence failed. PEG is set to 1 when the Flash Module is reset, unless a Flash initialization error has been detected. The value of PEG is valid only when PGM=1 and/or ERS=1 and after DONE transitions from 0 to 1 due to an abort or the completion of a Program/Erase operation. PEG is valid until PGM/ERS makes a 1 to 0 transition or EHV makes a 0 to 1 transition. The value in PEG is not valid after a 0 to 1 transition of DONE caused by ESUS being set to logic 1. If Program or Erase are attempted on blocks that are locked, the response will be PEG=1, indicating that the operation was succesful, and the content of the block were properly protected from the Program or Erase operation. If a Program operation tries to program at ‘1’ bits that are at ‘0’, the program operation is correctly executed on the new bits to be programmed at ‘0’, but PEG is cleared, indicating that the requested operation has failed. In Array Integrity Check or Margin Read PEG is set to 1 when the operation is completed, regardless the occurrence of any error. The presence of errors can be detected only comparing checksum value stored in UMIRS0-1. Aborting an Array Integrity Check or a Margin Read operation will cause PEG to be cleared to 0, indicating the sequence failed. 0: Program, Erase operation failed or Program, Erase, Array Integrity Check or Maring Mode aborted. 1: Program or Erase operation succesful or Array Integrity Check or Maring Mode completed.
21
22
23:26 Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0.
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Table 12-6. MCR field descriptions (continued)
Field 27 Description PGM: ProGraM (Read/Write) PGM is used to set up the Flash module for a Program operation. A 0 to 1 transition of PGM initiates a Program sequence. A 1 to 0 transition of PGM ends the Program sequence. PGM can be set only under User Mode Read (ERS is low and UT0.AIE is low). PGM can be cleared by the user only when EHV is low and DONE is high. PGM is cleared on reset. 0: Flash is not executing a Program sequence. 1: Flash is executing a Program sequence. PSUS: Program SUSpend (Read/Write) Write this bit has no effect, but the written data can be read back. ERS: ERaSe (Read/Write) ERS is used to set up the Flash module for an erase operation. A 0 to 1 transition of ERS initiates an erase sequence. A 1 to 0 transition of ERS ends the erase sequence. ERS can be set only under User Mode Read (PGM is low and UT0.AIE is low). ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0: Flash is not executing an erase sequence. 1: Flash is executing an erase sequence. ESUS: Erase SUSpend (Read/Write) ESUS is used to indicate that the Flash module is in Erase Suspend or in the process of entering a Suspend state. The Flash module is in Erase Suspend when ESUS = 1 and DONE = 1. ESUS can be set high only when ERS and EHV are high and PGM is low. A 0 to 1 transition of ESUS starts the sequence which sets DONE and places the Flash in Erase Suspend. The Flash module enters Suspend within tESUS of this transition. ESUS can be cleared only when DONE and EHV are high and PGM is low. A 1 to 0 transition of ESUS with EHV = 1 starts the sequence which clears DONE and returns the module to Erase. The Flash module cannot exit Erase Suspend and clear DONE while EHV is low. ESUS is cleared on reset. 0: Erase sequence is not suspended. 1: Erase sequence is suspended.
28 29
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Table 12-6. MCR field descriptions (continued)
Field 31 Description EHV: Enable High Voltage (Read/Write) The EHV bit enables the Flash module for a high voltage program/erase operation. EHV is cleared on reset. EHV must be set after an interlock write to start a program/erase sequence. EHV may be set under one of the following conditions: Erase (ERS = 1, ESUS = 0, UT0.AIE = 0) Program (ERS = 0, ESUS = 0, PGM = 1, UT0.AIE = 0) In normal operation, a 1 to 0 transition of EHV with DONE high and ESUS low terminates the current program/erase high voltage operation. When an operation is aborted, there is a 1 to 0 transition of EHV with DONE low and the eventual Suspend bit low. An abort causes the value of PEG to be cleared, indicating a failing program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. A suspended operation cannot be aborted. Aborting a high voltage operation will leave the Flash module addresses in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. EHV may be written during Suspend. EHV must be high to exit Suspend. EHV may not be written after ESUS is set and before DONE transitions high. EHV may not be cleared after ESUS is cleared and before DONE transitions low. 0: Flash is not enabled to perform an high voltage operation. 1: Flash is enabled to perform an high voltage operation.
Table 12-7. Array space size
SIZE[2:0] 000 001 010 011 100 101 110 111 Array space size 128 KB 256 KB Reserved (512 KB) Reserved (1024 KB) Reserved (1536 KB) Reserved (2048 KB) 64 KB Reserved
Table 12-8. Low address space configuration
LAS[2:0] 000 001 010 011 100 101 Low address space sectorization 0 KB 2 x 128 KB 32 KB + 2 x 16 KB + 2 x 32 KB + 128 KB Reserved Reserved Reserved
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Table 12-8. Low address space configuration (continued)
LAS[2:0] 110 111 Low address space sectorization 4 x 16 KB 2 x 16 KB + 2 x 32 KB + 2 x 16 KB + 2 x 64 KB
Table 12-9. Mid address space configuration
MAS 0 1 Mid address space sectorization 2 x 128 KB or 0 KB Reserved
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state. These write locks are covered on a bit by bit basis in the preceding description, but those locks do not consider the effects of trying to write two or more bits simultaneously. The Flash module does not allow the user to write bits simultaneously which would put the device into an illegal state. This is implemented through a priority mechanism among the bits. The bit changing priorities are detailed in the Table 12-10.
Table 12-10. MCR bits set/clear priority levels
Priority level 1 2 3 4 MCR bits ERS PGM EHV ESUS
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority level is written. If Stall/Abort-While-Write is enabled and an erase operation is started on one sector while fetching code from another then the following sequence is executed: • CPU is stalled when flash is unavailable • PEG flag set (stall case) or reset (abort case) • Interrupt triggered if enabled However, in all cases also the RWE flag is set, indicating a RWW error. If Stall/Abort-While-Write is used then application software should ignore the setting of the RWE flag. The RWE flag should be cleared after each HV operation. If Stall/Abort-While-Write is not used the application software should handle RWE error.
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12.2.7
Low/Mid address space block Locking register (LML)
Address offset: 0x0004 Reset value: 0x00XX_XXXX, initially determined by NVLML value from test sector.
12.2.7.1
Non-volatile Low/Mid address space block Locking register (NVLML)
Delivery value: 0xFFFF_FFFF
4 0 r/0 20 LLK11 rw/X 5 0 r/0 21 LLK10 rw/X 6 0 r/0 22 LLK9 rw/X 7 0 r/0 23 LLK8 rw/X 8 0 r/0 24 LLK7 rw/X 9 0 r/0 25 LLK6 rw/X 10 0 r/0 26 LLK5 rw/X 11 TSLK rw/X 27 LLK4 rw/X 12 0 r/0 28 LLK3 rw/X 13 0 r/0 29 LLK2 rw/X 14 MLK1 rw/X 30 LLK1 rw/X 15 MLK0 rw/X 31 LLK0 rw/X
Address offset: 0x403DE8
0 LME r/0 16 LLK15 rw/X 1 0 r/0 17 LLK14 rw/X 2 0 r/0 18 LLK13 rw/X 3 0 r/0 19 LLK12 rw/X
Figure 12-4. Non-volatile Low/Mid address space block Locking register (NVLML)
The Low/Mid Address Space Block Locking register provides a means to protect blocks from being modified. These bits, along with bits in the SLL register, determine if the block is locked from Program or Erase. An “OR” of LML and SLL determine the final lock status. The LML register has a related Non-volatile Low/Mid Address Space Block Locking register located in TestFlash that contains the default reset value for LML. During the reset phase of the Flash module, the NVLML register content is read and loaded into the LML. The NVLML register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and eventually used to manage ECC codes.
Table 12-11. LML field descriptions
Field 0 Description LME: Low/Mid address space block Enable (Read Only) This bit is used to enable the Lock registers (TSLK, MLK1-0 and LLK15-0) to be set or cleared by registers writes. This bit is a status bit only. The method to set this bit is to write a password, and if the password matches, the LME bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. For LME the password 0xA1A11111 must be written to the LML register. 0: Low Address Locks are disabled: TSLK, MLK1-0 and LLK15-0 cannot be written. 1: Low Address Locks are enabled: TSLK, MLK1-0 and LLK15-0 can be written. Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
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Table 12-11. LML field descriptions (continued)
Field 11 Description TSLK: Test/Shadow address space block LocK (Read/Write) This bit is used to lock the block of Test and Shadow Address Space from Program and Erase (Erase is any case forbidden for Test block). A value of 1 in the TSLK register signifies that the Test/Shadow block is locked for Program and Erase. A value of 0 in the TSLK register signifies that the Test/Shadow block is available to receive program and erase pulses. The TSLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the TSLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the TSLK register. The TSLK bit may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The default value of the TSLK bit (assuming erased fuses) would be locked. TSLK is not writable unless LME is high. 0: Test/Shadow Address Space Block is unlocked and can be modified (also if SLL.STSLK = 0). 1: Test/Shadow Address Space Block is locked and cannot be modified.
12:13 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. 14:15 MLK[1:0]: Mid address space block LocK 1-0 (Read/Write) These bits are used to lock the blocks of Mid Address Space from Program and Erase. All the MLK[1:0] are not used for this memory cut that is all mapped in mid and low address space. A value of 1 in a bit of the MLK register signifies that the corresponding block is locked for Program and Erase. A value of 0 in a bit of the MLK register signifies that the corresponding block is available to receive program and erase pulses. The MLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the MLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the MLK registers. The MLK bits may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The default value of the MLK bits (assuming erased fuses) would be locked. In the event that blocks are not present (due to configuration or total memory size), the MLK bits will default to locked, and will not be writable. The reset value will always be 1 (independent of the TestFlash block), and register writes will have no effect. In the 288 Kbyte Flash module bits MLK[1:0] are read-only and locked at ‘1’. MLK is not writable unless LME is high. 0: Mid Address Space Block is unlocked and can be modified (also if SLL.SMLK = 0). 1: Mid Address Space Block is locked and cannot be modified.
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Table 12-11. LML field descriptions (continued)
Field Description
16:31 LLK[15:0]: Low address space block LocK 15-0 (Read/Write) These bits are used to lock the blocks of Low Address Space from Program and Erase. LLK[5:0] are related to sectors B0F5-0, respectively. LLK[15:6] are not used for this memory cut. A value of 1 in a bit of the LLK register signifies that the corresponding block is locked for Program and Erase. A value of 0 in a bit of the LLK register signifies that the corresponding block is available to receive program and erase pulses. The LLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the LLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the LLK registers. The LLK bits may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The default value of the LLK bits (assuming erased fuses) would be locked. In the event that blocks are not present (due to configuration or total memory size), the LLK bits will default to locked, and will not be writable. The reset value will always be 1 (independent of the TestFlash block), and register writes will have no effect. In the 288 Kbyte Flash module bits LLK[15:6] are read-only and locked at ‘1’. LLK is not writable unless LME is high. 0: Low Address Space Block is unlocked and can be modified (also if SLL.SLK = 0). 1: Low Address Space Block is locked and cannot be modified.
12.2.8
High address space Block Locking register (HBL)
Address offset: 0x0008 Reset value: , initially determined by NVHBL, located in test sector.
12.2.8.1
Non-volatile High address space Block Locking register (NVHBL)
Delivery value: 0xFFFF_FFFF
4 0 r/0 20 0 r/0 5 0 r/0 21 0 r/0 6 0 r/0 22 0 r/0 7 0 r/0 23 0 r/0 8 0 r/0 24 0 r/0 9 0 r/0 25 0 r/0 10 0 r/0 26 HLK5 rw/X 11 0 r/0 27 HLK4 rw/X 12 0 r/0 28 HLK3 rw/X 13 0 r/0 29 HLK2 rw/X 14 0 r/0 30 HLK1 rw/X 15 0 r/0 31 HLK0 rw/X
Address offset: 0x403DF0
0 HBE r/0 16 0 r/0 1 0 r/0 17 0 r/0 2 0 r/0 18 0 r/0 3 0 r/0 19 0 r/0
Figure 12-5. Non-volatile High address space Block Locking register (NVHBL)
The High Address Space Block Locking register provides a means to protect blocks from being modified. The HBL register has a related Non-volatile High Address Space Block Locking register located in TestFlash that contains the default reset value for HBL. During the reset phase of the Flash module, the NVHBL register content is read and loaded into the HBL. The NVHBL register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and eventually used to manage ECC codes.
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Table 12-12. HBL field descriptions
Field 0 Description High address space Block Enable (Read Only) This bit is used to enable the Lock registers (HLK5-0) to be set or cleared by registers writes. This bit is a status bit only. The method to set this bit is to write a password, and if the password matches, the HBE bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. For HBE the password 0xB2B22222 must be written to the HBL register. 0: High Address Locks are disabled: HLK5-0 cannot be written. 1: High Address Locks are enabled: HLK5-0 can be written. Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
1:25
26:31 HLK[5:0]: High address space block LocK 5-0 (Read/Write) These bits are used to lock the blocks of High Address Space from Program and Erase. All the HLK[5:0] are not used for this memory cut that is all mapped in mid and low address space. A value of 1 in a bit of the HLK register signifies that the corresponding block is locked for Program and Erase. A value of 0 in a bit of the HLK register signifies that the corresponding block is available to receive program and erase pulses. The HLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the HLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the HLK registers. The HLK bits may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The default value of the HLK bits (assuming erased fuses) would be locked. In the event that blocks are not present (due to configuration or total memory size), the HLK bits will default to locked, and will not be writable. The reset value will always be 1 (independent of the TestFlash block), and register writes will have no effect. In the 288 Kbyte Flash module bits HLK[5:0] are read-only and locked at ‘1’. HLK is not writable unless HBE is high. 0: High Address Space Block is unlocked and can be modified. 1: High Address Space Block is locked and cannot be modified.
12.2.9
Secondary Low/mid address space block Locking register (SLL)
Address offset: 0x000C Reset value: 0x00XX_XXXX, initially determined by NVSLL, located in test sector.
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12.2.9.1
Non-volatile Secondary Low/mid address space block Locking register (NVSLL)
Delivery value: 0xFFFF_FFFF
4 0 r/0 20 SLK11 rw/X 5 0 r/0 21 SLK10 rw/X 6 0 r/0 22 SLK9 rw/X 7 0 r/0 23 SLK8 rw/X 8 0 r/0 24 SLK7 rw/X 9 0 r/0 25 SLK6 rw/X 10 0 r/0 26 SLK5 rw/X 11 STSLK rw/X 27 SLK4 rw/X 12 0 r/0 28 SLK3 rw/X 13 0 r/0 29 SLK2 rw/X 14 SMK1 rw/X 30 SLK1 rw/X 15 SMK0 rw/X 31 SLK0 rw/X
Address offset: 0x403DF8
0 SLE r/0 16 SLK15 rw/X 1 0 r/0 17 SLK14 rw/X 2 0 r/0 18 SLK13 rw/X 3 0 r/0 19 SLK12 rw/X
Figure 12-6. Non-volatile Secondary Low/mid address space block Locking register (NVSLL)
The Secondary Low/Mid Address Space Block Locking register provides an alternative means to protect blocks from being modified. These bits, along with bits in the LML register, determine if the block is locked from Program or Erase. An “OR” of LML and SLL determine the final lock status. The SLL register has a related Non-volatile Secondary Low/Mid Address Space Block Locking register located in TestFlash that contains the default reset value for SLL. During the reset phase of the Flash module, the NVSLL register content is read and loaded into the SLL. The NVSLL register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and eventually used to manage ECC codes.
Table 12-13. SLL field descriptions
Field 0 Description SLE: Secondary Low/mid address space block Enable (Read Only) This bit is used to enable the Lock registers (STSLK, SMK1-0 and SLK15-0) to be set or cleared by registers writes. This bit is a status bit only. The method to set this bit is to write a password, and if the password matches, the SLE bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. For SLE the password 0xC3C33333 must be written to the SLL register. 0: Secondary Low/Mid Address Locks are disabled: STSLK, SMK1-0 and SLK15-0 cannot be written. 1: Secondary Low/Mid Address Locks are enabled: STSLK, SMK1-0 and SLK15-0 can be written. Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
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Table 12-13. SLL field descriptions (continued)
Field 11 Description STSLK: Secondary Test/Shadow address space block LocK (Read/Write) This bit is used as an alternate means to lock the block of Test and Shadow Address Space from Program and Erase (Erase is any case forbidden for Test block). A value of 1 in the STSLK register signifies that the Test/Shadow block is locked for Program and Erase. A value of 0 in the STSLK register signifies that the Test/Shadow block is available to receive program and erase pulses. The STSLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the STSLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the STSLK register. The STSLK bit may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The default value of the STSLK bit (assuming erased fuses) would be locked. STSLK is not writable unless SLE is high. 0: Test/Shadow Address Space Block is unlocked and can be modified (also if LML.TSLK = 0). 1: Test/Shadow Address Space Block is locked and cannot be modified.
12:13 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. 14:15 SMK[1:0]: Secondary Mid address space block locK 1-0 (Read/Write) These bits are used as an alternate means to lock the blocks of Mid Address Space from Program and Erase. All the SMK[1:0] are not used for this memory cut that is all mapped in mid and low address space. A value of 1 in a bit of the SMK register signifies that the corresponding block is locked for Program and Erase. A value of 0 in a bit of the SMK register signifies that the corresponding block is available to receive program and erase pulses. The SMK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the SMK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the SMK registers. The SMK bits may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The default value of the SMK bits (assuming erased fuses) would be locked. In the event that blocks are not present (due to configuration or total memory size), the SMK bits will default to locked, and will not be writable. The reset value will always be 1 (independent of the TestFlash block), and register writes will have no effect. In the 288 Kbyte Flash module bits SMK[1:0] are read-only and locked at ‘1’. SMK is not writable unless SLE is high. 0: Mid Address Space Block is unlocked and can be modified (also if LML.MLK = 0). 1: Mid Address Space Block is locked and cannot be modified.
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Table 12-13. SLL field descriptions (continued)
Field Description
16:31 SLK[15:0]: Secondary Low address space block locK 15-0 (Read/Write) These bits are used as an alternate means to lock the blocks of Low Address Space from Program and Erase. SLK[5:0] are related to sectors B0F5-0, respectively. SLK[15:6] are not used for this memory cut. A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for Program and Erase. A value of 0 in a bit of the SLK register signifies that the corresponding block is available to receive program and erase pulses. The SLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the SLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the SLK registers. The SLK bits may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The default value of the SLK bits (assuming erased fuses) would be locked. In the event that blocks are not present (due to configuration or total memory size), the SLK bits will default to locked, and will not be writable. The reset value will always be 1 (independent of the TestFlash block), and register writes will have no effect. In the 288 Kbyte Flash module bits SLK[15:6] are read-only and locked at ‘1’. SLK is not writable unless SLE is high. 0: Low Address Space Block is unlocked and can be modified (also if LML.LLK = 0). 1: Low Address Space Block is locked and cannot be modified.
12.2.10 Low/Mid address space block Select register (LMS)
Address offset: 0x00010
0 0 r/0 16 LSL15 rw/0 1 0 r/0 17 LSL14 rw/0 2 0 r/0 18 LSL13 rw/0 3 0 r/0 19 LSL12 rw/0 4 0 r/0 20 LSL11 rw/0 5 0 r/0 21 LSL10 rw/0 6 0 r/0 22 LSL9 rw/0 7 0 r/0 23 LSL8 rw/0 8 0 r/0 24 LSL7 rw/0 9 0 r/0 25 LSL6 rw/0 10 0 r/0 26 LSL5 rw/0 11 0 r/0 27 LSL4 rw/0
Reset value: 0x0000_0000
12 0 r/0 28 LSL3 rw/0 13 0 r/0 29 LSL2 rw/0 14 MSL1 rw/0 30 LSL1 rw/0 15 MSL0 rw/0 31 LSL0 rw/0
Figure 12-7. Low/Mid address space block Select register (LMS)
The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on during erase.
Table 12-14. LMS field descriptions
Field 0:13 Description Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
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Table 12-14. LMS field descriptions (continued)
Field Description
14:15 MSL[1:0]: Mid address space block SeLect 1-0 (Read/Write) A value of 1 in the select register signifies that the block is selected for erase. A value of 0 in the select register signifies that the block is not selected for erase. The reset value for the select register is 0, or unselected. All the MSL[1:0] are not used for this memory cut that is all mapped in mid and low address space. The blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. The select register is not writable once an interlock write is completed or if a high voltage operation is suspended. In the event that blocks are not present (due to configuration or total memory size), the corresponding MSL bits will default to unselected, and will not be writable. The reset value will always be 0, and register writes will have no effect. In the 288 Kbyte Flash module bits SMK[1:0] are read-only and locked at ‘1’. 0: Mid Address Space Block is unselected for erase. 1: Mid Address Space Block is selected for erase. 16:31 LSL[15:0]: Low address space block SeLect 15-0 (Read/Write) A value of 1 in the select register signifies that the block is selected for erase. A value of 0 in the select register signifies that the block is not selected for erase. The reset value for the select register is 0, or unselected. LSL[5:0] are related to sectors B0F5-0, respectively. LSL[15:6] are not used for this memory cut. The blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. The select register is not writable once an interlock write is completed or if a high voltage operation is suspended. In the event that blocks are not present (due to configuration or total memory size), the corresponding LSL bits will default to unselected, and will not be writable. The reset value will always be 0, and register writes will have no effect. In the 288 Kbyte Flash module bits LSL[15:6] are read-only and locked at ‘0’. 0: Low Address Space Block is unselected for erase. 1: Low Address Space Block is selected for erase.
12.2.11 High address space Block Select register (HBS)
Address offset: 0x00014
0 0 r/0 16 0 r/0 1 0 r/0 17 0 r/0 2 0 r/0 18 0 r/0 3 0 r/0 19 0 r/0 4 0 r/0 20 0 r/0 5 0 r/0 21 0 r/0 6 0 r/0 22 0 r/0 7 0 r/0 23 0 r/0 8 0 r/0 24 0 r/0 9 0 r/0 25 0 r/0 10 0 r/0 26 HSL5 rw/0 11 0 r/0 27 HSL4 rw/0
Reset value: 0x0000_0000
12 0 r/0 28 HSL3 rw/0 13 0 r/0 29 HSL2 rw/0 14 0 r/0 30 HSL1 rw/0 15 0 r/0 31 HSL0 rw/0
Figure 12-8. High address space Block Select register (HBS)
The High Address Space Block Select register provides a means to select blocks to be operated on during erase.
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Table 12-15. HBS field descriptions
Field 0:25 Description Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
26:31 HSL[5:0]: High address space block SeLect 5-0 (Read/Write) A value of 1 in the select register signifies that the block is selected for erase. A value of 0 in the select register signifies that the block is not selected for erase. The reset value for the select register is 0, or unselected. All the HSL[5:0] are not used for this memory cut that is all mapped in mid and low address space. The blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. The select register is not writable once an interlock write is completed or if a high voltage operation is suspended. In the event that blocks are not present (due to configuration or total memory size), the corresponding HSL bits will default to unselected, and will not be writable. The reset value will always be 0, and register writes will have no effect. In the 288 Kbyte Flash module bits HSL[5:0] are read-only and locked at ‘0’. 0: High Address Space Block is unselected for erase. 1: High Address Space Block is selected for erase.
12.2.12 Address Register (ADR)
Address offset: 0x00018
0 0 r/0 16 AD15 r/0 1 0 r/0 17 AD14 r/0 2 0 r/0 18 AD13 r/0 3 0 r/0 19 AD12 r/0 4 0 r/0 20 AD11 r/0 5 0 r/0 21 AD10 r/0 6 0 r/0 22 AD9 r/0 7 0 r/0 23 AD8 r/0 8 0 r/0 24 AD7 r/0 9 AD22 r/0 25 AD6 r/0 10 AD21 r/0 26 AD5 r/0 11 AD20 r/0 27 AD4 r/0
Reset value: 0x0000_0000
12 AD19 r/0 28 AD3 r/0 13 AD18 r/0 29 0 r/0 14 AD17 r/0 30 0 r/0 15 AD16 r/0 31 0 r/0
Figure 12-9. Address Register (ADR)
The Address Register provides the first failing address in the event module failures (ECC, RWW or FPEC) occur or the first address at which an ECC single error correction occurs.
Table 12-16. ADR field descriptions
Field 0:8 Description Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
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Table 12-16. ADR field descriptions (continued)
Field 9:28 Description AD[22:3]: ADdress 22-3 (Read Only) The Address Register provides the first failing address in the event of ECC error (MCR.EER set) or the first failing address in the event of RWW error (MCR.RWE set), or the address of a failure that may have occurred in a FPEC operation (MCR.PEG cleared). The Address Register also provides the first address at which an ECC single error correction occurs (MCR.EDC set). The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC error and the ECC single error correction. When accessed ADR will provide the address related to the first event occurred with the highest priority. The priorities between these four possible events is summarized in the Table 12-17. This address is always a Double Word address that selects 64 bits. In case of a simultaneous ECC Double Error Detection on both Double Words of the same page, bit AD3 will output 0. The same is valid for a simultaneous ECC Single Error Correction on both Double Words of the same page. In User Mode the Address Register is read only.
29:31 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
Table 12-17. ADR content: priority list
Priority level 1 2 3 4 Error flag MCR.EER = 1 MCR.RWE = 1 MCR.PEG = 0 MCR.EDC = 1 ADR content Address of first ECC Double Error Address of first RWW Error Address of first FPEC Error Address of first ECC Single Error Correction
12.2.13 Bus Interface Unit 0 register (BIU0)
Address offset: 0x0001C
0 BI031 rw/X 16 BI015 rw/X 1 BI030 rw/X 17 BI014 rw/X 2 BI029 rw/X 18 BI013 rw/X 3 BI028 rw/X 19 BI012 rw/X 4 BI027 rw/X 20 BI011 rw/X 5 BI026 rw/X 21 BI010 rw/X 6 BI025 rw/X 22 BI009 rw/X 7 BI024 rw/X 23 BI008 rw/X 8 BI023 rw/X 24 BI007 rw/X 9 BI022 rw/X 25 BI006 rw/X 10 BI021 rw/X 26 BI005 rw/X 11 BI020 rw/X 27 BI004 rw/X
Reset value: 0xXXXX_XXXX
12 BI019 rw/X 28 BI003 rw/X 13 BI018 rw/X 29 BI002 rw/X 14 BI017 rw/X 30 BI001 rw/X 15 BI016 rw/X 31 BI000 rw/X
Figure 12-10. Bus Interface Unit 0 register (BIU0)
The Bus Interface Unit 0 Register provides a means for BIU specific information or BIU configuration information to be stored. Please refer to Section 12.4.4.2.1, “Platform Flash Configuration Register 0 (PFCR0) for more information about register description.
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Table 12-18. BIU0 field descriptions
Field Description
0:31 BI0[31:00]: Bus Interface unit 0 31-00 (Read/Write) The writability of the bits in this register can be locked.
12.2.14 Bus Interface Unit 1 register (BIU1)
Address offset: 0x00020
0 BI131 rw/X 16 BI115 rw/X 1 BI130 rw/X 17 BI114 rw/X 2 BI129 rw/X 18 BI113 rw/X 3 BI128 rw/X 19 BI112 rw/X 4 BI127 rw/X 20 BI111 rw/X 5 BI126 rw/X 21 BI110 rw/X 6 BI125 rw/X 22 BI109 rw/X 7 BI124 rw/X 23 BI108 rw/X 8 BI123 rw/X 24 BI107 rw/X 9 BI122 rw/X 25 BI106 rw/X 10 BI121 rw/X 26 BI105 rw/X 11 BI120 rw/X 27 BI104 rw/X
Reset value: 0xXXXX_XXXX
12 BI119 rw/X 28 BI103 rw/X 13 BI118 rw/X 29 BI102 rw/X 14 BI117 rw/X 30 BI101 rw/X 15 BI116 rw/X 31 BI100 rw/X
Figure 12-11. Bus Interface Unit 1 register (BIU1)
The Bus Interface Unit 1 Register provides a means for BIU specific information or BIU configuration information to be stored. Please refer to Section 12.4.4.2.2, “Platform Flash Configuration Register 1 (PFCR1) for more information about register description.
Table 12-19. BIU1 field descriptions
Field 0:31 Description BI1[31:00]: Bus Interface unit 1 31-00 (Read/Write) The writability of the bits in this register can be locked.
12.2.15 Bus Interface Unit 2 register (BIU2)
Address offset: 0x00024 Reset value: 0xXXXX XXXX
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12.2.15.1 Non-volatile Bus Interface Unit 2 register (NVBIU2)
Address offset: 0x203E00
0 BI231 rw/X 16 BI215 rw/X 1 BI230 rw/X 17 BI214 rw/X 2 BI229 rw/X 18 BI213 rw/X 3 BI228 rw/X 19 BI212 rw/X 4 BI227 rw/X 20 BI211 rw/X 5 BI226 rw/X 21 BI210 rw/X 6 BI225 rw/X 22 BI209 rw/X 7 BI224 rw/X 23 BI208 rw/X 8 BI223 rw/X 24 BI207 rw/X 9 BI222 rw/X 25 BI206 rw/X 10 BI221 rw/X 26 BI205 rw/X
Delivery value: 0xXXXX_XXXX
11 BI220 rw/X 27 BI204 rw/X 12 BI219 rw/X 28 BI203 rw/X 13 BI218 rw/X 29 BI202 rw/X 14 BI217 rw/X 30 BI201 rw/X 15 BI216 rw/X 31 BI200 rw/X
Figure 12-12. Non-volatile Bus Interface Unit 2 register (NVBIU2)
The Bus Interface Unit 2 Register provides a means for BIU specific information or BIU configuration information to be stored. Please refer to Section 12.4.4.2.3, “Platform Flash Access Protection Register (PFAPR) for more information about register description. The BIU2 register has a related Non-volatile Bus Interface Unit 2 register located in the Shadow Sector that contains the default reset value for BIU2. During the reset phase of the Flash module, the NVBIU2 register content is read and loaded into the BIU2. The NVBIU2 register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and eventually used to manage ECC codes.
Table 12-20. BIU2 field descriptions
Field 0:31 Description BI2[31:00]: Bus Interface unit 2 31-00 (Read/Write) The BI2[31:00] generic registers are reset based on the information stored in NVBIU2. The writability of the bits in this register can be locked.
12.2.16 Bus Interface Unit 3 register (BIU3)
Address Offset: 0x00028 Reset value: 0xXXXXXXXX
12.2.16.1 Non Volatile Bus Interface Unit 3 register (NVBIU3)
Address Offset: 0x203E08 Delivery value: 0xXXXXXXXX
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0 BI331 rw/X 16 BI315 rw/X
1 BI330 rw/X 17 BI314 rw/X
2 BI329 rw/X 18 BI313 rw/X
3 BI328 rw/X 19 BI312 rw/X
4 BI327 rw/X 20 BI311 rw/X
5 BI326 rw/X 21 BI310 rw/X
6 BI325 rw/X 22 BI309 rw/X
7 BI324 rw/X 23 BI308 rw/X
8 BI323 rw/X 24 BI307 rw/X
9 BI322 rw/X 25 BI306 rw/X
10 BI321 rw/X 26 BI305 rw/X
11 BI320 rw/X 27 BI304 rw/X
12 BI319 rw/X 28 BI303 rw/X
13 BI318 rw/X 29 BI302 rw/X
14 BI317 rw/X 30 BI301 rw/X
15 BI316 rw/X 31 BI300 rw/X
The Bus Interface Unit 3 Register provides a means for BIU specific information or BIU configuration information to be stored. The BIU3 register has a related Non-Volatile Bus Interface Unit 3 register located in the Shadow Sector that contains the default reset value for BIU3. the NVBIU3 register is read during the reset phase of the Flash Module and loaded into the BIU3. The NVBIU3 register is a 64-bit register, the 32 most significative bits of which (bits 63:32) are ‘don’t care’ and eventually used to manage ECC codes. The availability of this register is SoC dependent.
Table 12-21. BIU3 field descriptions
Field 0:31 Description BI331-00: Bus Interface unit 3 31-00 (Read/Write) The BI331-00 generic registers are reset based on the information stored in NVBIU3. The writability of the bits in this register can be locked. The use of this bus is SoC specific.
12.2.17 User Test 0 register (UT0)
Address offset: 0x0003C
0 UTE rw/0 16 0 r/0 1 0 r/0 17 0 r/0 2 0 r/0 18 0 r/0 3 0 r/0 19 0 r/0 4 0 r/0 20 0 r/0 5 0 r/0 21 0 r/0 6 0 r/0 22 0 r/0 7 0 r/0 23 0 r/0 8 DSI7 rw/0 24 0 r/0 9 DSI6 rw/0 25 X rw/0 10 DSI5 rw/0 26 MRE rw/0 11 DSI4 rw/0 27 MRV rw/0
Reset value: 0x0000_0001
12 DSI3 rw/0 28 EIE rw/0 13 DSI2 rw/0 29 AIS rw/0 14 DSI1 rw/0 30 AIE rw/0 15 DSI0 rw/0 31 AID r/1
Figure 12-13. User Test 0 register (UT0)
The User Test Registers provide the user with the ability to test features on the Flash module. The User Test 0 Register allows to control the way in which the Flash content check is done. Bits MRE, MRV, AIS, EIE and DSI[7:0] of the User Test 0 Register are not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
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Table 12-22. UT0 field descriptions
Field 0 Description UTE: User Test Enable (Read/Clear) This status bit gives indication when User Test is enabled. All bits in UT0-2 and UMISR0-4 are locked when this bit is 0. This bit is not writeable to a 1, but may be cleared. The reset value is 0. The method to set this bit is to provide a password, and if the password matches, the UTE bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write. For UTE the password 0xF9F99999 must be written to the UT0 register. Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. DSI[7:0]: Data Syndrome Input 7-0 (Read/Write) These bits represent the input of Syndrome bits of ECC logic used in the ECC Logic Check. Bits DSI[7:0] correspond to the 8 syndrome bits on a double word. These bits are not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: The syndrome bit is forced at 0. 1: The syndrome bit is forced at 1.
1:7 8:15
16:24 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. 25 Reserved (Read/Write). This bit can be written and its value can be read back, but there is no function associated. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. MRE: Margin Read Enable (Read/Write) MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode reads to be replaced by margin reads inside the Array Integrity Checks sequences. Margin reads are only active during Array Integrity Checks; Normal User reads are not affected by MRE. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: Margin reads are not enabled 1: Margin reads are enabled. MRV: Margin Read Value (Read/Write) If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an erased level (MRV = 1) or to a programmed level (MRV = 0). This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: Zero’s (programmed) margin reads are requested (if MRE = 1). 1: One’s (erased) margin reads are requested (if MRE = 1). EIE: ECC data Input Enable (Read/Write) EIE enables the ECC Logic Check operation to be done. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: ECC Logic Check is not enabled. 1: ECC Logic Check is enabled.
26
27
28
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Table 12-22. UT0 field descriptions (continued)
Field 29 Description AIS: Array Integrity Sequence (Read/Write) AIS determines the address sequence to be used during array integrity checks or Margin Read . The default sequence (AIS=0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. This sequence is proprietary. The alternative sequence (AIS=1) is just logically sequential. It should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. The usage of proprietary sequence is forbidden in Margin Read. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. In Margin Read only the linear sequence (AIS = 1) is allowed, while the proprietary sequence (AIS = 0) is forbidden. 0: Array Integrity sequence is proprietary sequence. 1: Array Integrity or f sequence is sequential. AIE: Array Integrity Enable (Read/Write) AIE set to ‘1’ starts the Array Integrity Check done on all selected and unlocked blocks. The pattern is selected by AIS, and the MISR (UMISR0-4) can be checked after the operation is complete, to determine if a correct signature is obtained. AIE can be set only if MCR.ERS, MCR.PGM and MCR.EHV are all low. 0: Array Integrity Checks, Margin Read and ECC Logic Checks are not enabled. 1: Array Integrity Checks, Margin Read and ECC Logic Checks are enabled. AID: Array Integrity Done (Read Only) AID will be cleared upon an Array Integrity Check being enabled (to signify the operation is on-going). Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the MISR (UMISR0-4) can be checked. 0: Array Integrity Check is on-going. 1: Array Integrity Check is done.
31
31
12.2.18 User Test 1 register (UT1)
Address offset: 0x00040
0 DAI31 rw/0 16 DAI15 rw/0 1 DAI30 rw/0 17 DAI14 rw/0 2 DAI29 rw/0 18 DAI13 rw/0 3 DAI28 rw/0 19 DAI12 rw/0 4 DAI27 rw/0 20 DAI11 rw/0 5 DAI26 rw/0 21 DAI10 rw/0 6 DAI25 rw/0 22 DAI09 rw/0 7 DAI24 rw/0 23 DAI08 rw/0 8 DAI23 rw/0 24 DAI07 rw/0 9 DAI22 rw/0 25 DAI06 rw/0 10 DAI21 rw/0 26 DAI05 rw/0 11 DAI20 rw/0 27 DAI04 rw/0
Reset value: 0x0000_0000
12 DAI19 rw/0 28 DAI03 rw/0 13 DAI18 rw/0 29 DAI02 rw/0 14 DAI17 rw/0 30 DAI01 rw/0 15 DAI16 rw/0 31 DAI00 rw/0
Figure 12-14. User Test 1 register (UT1)
The User Test 1 Register allows to enable the checks on the ECC logic related to the 32 LSB of the Double Word. The User Test 1 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
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Table 12-23. UT1 field descriptions
Field 0:31 Description DAI[31:00]: Data Array Input 31-0 (Read/Write) These bits represent the input of even word of ECC logic used in the ECC Logic Check. Bits DAI[31:00] correspond to the 32 array bits representing Word 0 within the double word. 0: The array bit is forced at 0. 1: The array bit is forced at 1.
12.2.19 User Test 2 register (UT2)
Address offset: 0x00044
0 DAI63 rw/0 16 DAI47 rw/0 1 DAI62 rw/0 17 DAI46 rw/0 2 DAI61 rw/0 18 DAI45 rw/0 3 DAI60 rw/0 19 DAI44 rw/0 4 DAI59 rw/0 20 DAI43 rw/0 5 DAI58 rw/0 21 DAI42 rw/0 6 DAI57 rw/0 22 DAI41 rw/0 7 DAI56 rw/0 23 DAI40 rw/0 8 DAI55 rw/0 24 DAI39 rw/0 9 DAI54 rw/0 25 DAI38 rw/0 10 DAI53 rw/0 26 DAI37 rw/0 11 DAI52 rw/0 27 DAI36 rw/0
Reset value: 0x0000_0000
12 DAI51 rw/0 28 DAI35 rw/0 13 DAI50 rw/0 29 DAI34 rw/0 14 DAI49 rw/0 30 DAI33 rw/0 15 DAI48 rw/0 31 DAI32 rw/0
Figure 12-15. User Test 2 register (UT2)
The User Test 2 Register allows to enable the checks on the ECC logic related to the 32 MSB of the Double Word. The User Test 2 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-24. UT2 field descriptions
Field 0:31 Description DAI[63:32]: Data Array Input 63-32 (Read/Write) These bits represent the input of odd word of ECC logic used in the ECC Logic Check. Bits DAI[63:32] correspond to the 32 array bits representing Word 1 within the double word. 0: The array bit is forced at 0. 1: The array bit is forced at 1.
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12.2.20 User Multiple Input Signature Register 0 (UMISR0)
Address offset: 0x00048
0 1 2 3 4 5 6 7 8 9 10 11
Reset value: 0x0000_0000
12 13 14 15
MS031 MS030 MS029 MS028 MS027 MS026 MS025 MS024 MS023 MS022 MS021 MS020 MS019 MS018 MS017 MS016 rw/0 16 rw/0 17 rw/0 18 rw/0 19 rw/0 20 rw/0 21 rw/0 22 rw/0 23 rw/0 24 rw/0 25 rw/0 26 rw/0 27 rw/0 28 rw/0 29 rw/0 30 rw/0 31
MS015 MS014 MS013 MS012 MS011 MS010 MS009 MS008 MS007 MS006 MS005 MS004 MS003 MS002 MS001 MS000 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 12-16. User Multiple Input Signature Register 0 (UMISR0)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity. The User Multiple Input Signature Register 0 represents the bits 31:0 of the whole 144 bits word (2 Double Words including ECC). The UMISR0 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-25. UMSIR0 field descriptions
Field 0:31 Description MS031:000: Multiple input Signature 031-000 (Read/Write) These bits represent the MISR value obtained accumulating the bits 31:0 of all the pages read from the Flash memory. The MS can be seeded to any value by writing the UMISR0 register.
12.2.21 User Multiple Input Signature Register 1 (UMISR1)
Address offset: 0x0004C
0 1 2 3 4 5 6 7 8 9 10 11
Reset value: 0x0000_0000
12 13 14 15
MS063 MS062 MS061 MS060 MS059 MS058 MS057 MS056 MS055 MS054 MS053 MS052 MS051 MS050 MS049 MS048 rw/0 16 rw/0 17 rw/0 18 rw/0 19 rw/0 20 rw/0 21 rw/0 22 rw/0 23 rw/0 24 rw/0 25 rw/0 26 rw/0 27 rw/0 28 rw/0 29 rw/0 30 rw/0 31
MS047 MS046 MS045 MS044 MS043 MS042 MS041 MS040 MS039 MS038 MS037 MS036 MS035 MS034 MS033 MS032 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 12-17. User Multiple Input Signature Register 1 (UMISR1)
The Multiple Input Signature Register provides a means to evaluate the Array Integrity. The User Multiple Input Signature Register 1 represents the bits 63:32 of the whole 144 bits word (2 Double Words including ECC).
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The UMISR1 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-26. UMISR1 field descriptions
Field 0:31 Description MS063:032: Multiple input Signature 063-032 (Read/Write) These bits represent the MISR value obtained accumulating the bits 63:32 of all the pages read from the Flash memory. The MS can be seeded to any value by writing the UMISR1 register.
12.2.22 User Multiple Input Signature Register 2 (UMISR2)
Address offset: 0x00050
0 1 2 3 4 5 6 7 8 9 10 11
Reset value: 0x0000_0000
12 13 14 15
MS095 MS094 MS093 MS092 MS091 MS090 MS089 MS088 MS087 MS086 MS085 MS084 MS083 MS082 MS081 MS080 rw/0 16 rw/0 17 rw/0 18 rw/0 19 rw/0 20 rw/0 21 rw/0 22 rw/0 23 rw/0 24 rw/0 25 rw/0 26 rw/0 27 rw/0 28 rw/0 29 rw/0 30 rw/0 31
MS079 MS078 MS077 MS076 MS075 MS074 MS073 MS072 MS071 MS070 MS069 MS068 MS067 MS066 MS065 MS064 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 12-18. User Multiple Input Signature Register 2 (UMISR2)
The Multiple Input Signature Register provides a means to evaluate the Array Integrity. The User Multiple Input Signature Register 2 represents the bits 95:64 of the whole 144 bits word (2 Double Words including ECC). The UMISR2 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-27. UMISR2 field descriptions
Field 0:31 Description MS095:064: Multiple input Signature 095-064 (Read/Write) These bits represent the MISR value obtained accumulating the bits 95:64 of all the pages read from the Flash memory. The MS can be seeded to any value by writing the UMISR2 register.
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12.2.23 User Multiple Input Signature Register 3 (UMISR3)
Address offset: 0x00054
0 1 2 3 4 5 6 7 8 9 10 11
Reset value: 0x0000_0000
12 13 14 15
MS127 MS126 MS125 MS124 MS123 MS122 MS121 MS120 MS119 MS118 MS117 MS116 MS115 MS114 MS113 MS112 rw/0 16 rw/0 17 rw/0 18 rw/0 19 rw/0 20 rw/0 21 rw/0 22 rw/0 23 rw/0 24 rw/0 25 rw/0 26 rw/0 27 rw/0 28 rw/0 29 rw/0 30 rw/0 31
MS111 MS110 MS109 MS108 MS107 MS106 MS105 MS104 MS103 MS102 MS101 MS100 MS099 MS098 MS097 MS096 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 12-19. User Multiple Input Signature Register 3 (UMISR3)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity. The User Multiple Input Signature Register 3 represents the bits 127:96 of the whole 144 bits word (2 Double Words including ECC). The UMISR3 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-28. UMISR3 field descriptions
Field 0:31 Description MS127:096: Multiple input Signature 127-096 (Read/Write) These bits represent the MISR value obtained accumulating the bits 127:96 of all the pages read from the Flash memory. The MS can be seeded to any value by writing the UMISR3 register.
12.2.24 User Multiple Input Signature Register 4 (UMISR4)
Address offset: 0x00058
0 1 2 3 4 5 6 7 8 9 10 11
Reset value: 0x0000_0000
12 13 14 15
MS159 MS158 MS157 MS156 MS155 MS154 MS153 MS152 MS151 MS150 MS149 MS148 MS147 MS146 MS145 MS144 rw/0 16 rw/0 17 rw/0 18 rw/0 19 rw/0 20 rw/0 21 rw/0 22 rw/0 23 rw/0 24 rw/0 25 rw/0 26 rw/0 27 rw/0 28 rw/0 29 rw/0 30 rw/0 31
MS143 MS142 MS141 MS140 MS139 MS138 MS137 MS136 MS135 MS134 MS133 MS132 MS131 MS130 MS129 MS128 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 12-20. User Multiple Input Signature Register 4(UMISR4)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity. The User Multiple Input Signature Register 4 represents the ECC bits of the whole 144 bits word (2 Double Words including ECC): bits 8:15 are ECC bits for the odd Double Word and bits 24:31 are the ECC bits
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for the even Double Word; bits 4:5 and 20:21 of MISR are respectively the double and single ECC error detection for odd and even Double Word. The UMISR4 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-29. UMISR4 field descriptions
Field 0:31 Description MS159:128: Multiple input Signature 159-128 (Read/Write) These bits represent the MISR value obtained accumulating: the 8 ECC bits for the even Double Word (on MS[135:128]); the single ECC error detection for even Double Word (on MS138); the double ECC error detection for even Double Word (on MS139); the 8 ECC bits for the odd Double Word (on MS[151:144]); the single ECC error detection for odd Double Word (on MS154); the double ECC error detection for odd Double Word (on MS155). The MS can be seeded to any value by writing the UMISR4 register.
12.2.25 Non-volatile private censorship PassWord 0 register (NVPWD0)
Address offset: 0x203DD8
0 1 2 3 4 5 6 7 8 9 10 11
Delivery value: 0xFEED_FACE
12 13 14 15
PWD31 PWD30 PWD29 PWD28 PWD27 PWD26 PWD25 PWD24 PWD23 PWD22 PWD21 PWD20 PWD19 PWD18 PWD17 PWD16 rw/X 16 rw/X 17 rw/X 18 rw/X 19 rw/X 20 rw/X 21 rw/X 22 rw/X 23 rw/X 24 rw/X 25 rw/X 26 rw/X 27 rw/X 28 rw/X 29 rw/X 30 rw/X 31
PWD15 PWD14 PWD13 PWD12 PWD11 PWD10 PWD09 PWD08 PWD07 PWD06 PWD05 PWD04 PWD03 PWD02 PWD01 PWD00 rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X
Figure 12-21. Non-volatile private censorship PassWord 0 register (NVPWD0)
The non-volatile private censorship password 0 register contains the 32 LSB of the Password used to validate the Censorship information contained in NVSCI0–1 registers.
Table 12-30. NVPWD0 field descriptions
Field 0:31 Description PWD[31:00]: PassWorD 31-00 (Read/Write) The PWD31-00 registers represent the 32 LSB of the Private Censorship Password.
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12.2.26 Non-volatile private censorship PassWord 1 register (NVPWD1)
Address offset: 0x203DDC
0 1 2 3 4 5 6 7 8 9 10 11
Delivery value: 0xCAFE_BEEF
12 13 14 15
PWD63 PWD62 PWD61 PWD60 PWD59 PWD58 PWD57 PWD56 PWD55 PWD54 PWD53 PWD52 PWD51 PWD50 PWD49 PWD48 rw/X 16 rw/X 17 rw/X 18 rw/X 19 rw/X 20 rw/X 21 rw/X 22 rw/X 23 rw/X 24 rw/X 25 rw/X 26 rw/X 27 rw/X 28 rw/X 29 rw/X 30 rw/X 31
PWD47 PWD46 PWd45 PWD44 PWD43 PWD42 PWD41 PWD40 PWD39 PWD38 PWD37 PWD36 PWD35 PWD34 PWD33 PWD32 rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X rw/X
Figure 12-22. Non-volatile private censorship PassWord 1 register (NVPWD1)
The non-volatile private censorship password 1 register contains the 32 MSB of the Password used to validate the Censorship information contained in NVSCI0–1 registers.
Table 12-31. NVPWD1 field descriptions
Field 0:31 Description PWD[63:32]: PassWorD 63-32 (Read/Write) The PWD63-32 registers represent the 32 MSB of the Private Censorship Password.
NOTE In a secured device, starting with a serial boot, it is possible to read the content of the four flash locations where the RCHW can be stored. For example if the RCHW is stored at address 0x00000000, the reads at address 0x00000000, 0x00000004, 0x00000008 and 0x0000000C will return a correct value. Any other flash address cannot be accessed.
12.2.27 Non-volatile System Censoring Information 0 register (NVSCI0)
Address offset: 0x203DE0
0 SC15 rw/X 16 CW15 rw/X 1 SC14 rw/X 17 CW14 rw/X 2 SC13 rw/X 18 CW13 rw/X 3 SC12 rw/X 19 CW12 rw/X 4 SC11 rw/X 20 CW11 rw/X 5 SC10 rw/X 21 CW10 rw/X 6 SC9 rw/X 22 CW9 rw/X 7 SC8 rw/X 23 CW8 rw/X 8 SC7 rw/X 24 CW7 rw/X 9 SC6 rw/X 25 CW6 rw/X 10 SC5 rw/X 26 CW5 rw/X 11 SC4 rw/X 27 CW4 rw/X
Delivery value: 0x55AA_55AA
12 SC3 rw/X 28 CW3 rw/X 13 SC2 rw/X 29 CW2 rw/X 14 SC1 rw/X 30 CW1 rw/X 15 SC0 rw/X 31 CW0 rw/X
Figure 12-23. Non-volatile System Censoring Information 0 register (NVSCI0)
The non-volatile system censoring information 0 register stores the 32 LSB of the Censorship Control Word of the device.
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The NVSCI0 is a non-volatile register located in the Shadow sector: it is read during the reset phase of the Flash module and the protection mechanisms are activated consequently. The parts are delivered uncensored to the user.
Table 12-32. NVSCI0 field descriptions
Field 0:15 Description SC[15:0]: Serial Censorship control word 15-0 (Read/Write) These bits represent the 16 LSB of the Serial Censorship Control Word (SCCW). If SC15-0 = 0x55AA and NVSCI1 = NVSCI0 the Public Access is disabled. If SC15-0 0x55AA or NVSCI1 NVSCI0 the Public Access is enabled.
16:31 CW[15:0]: Censorship control Word 15-0 (Read/Write) These bits represent the 16 LSB of the Censorship Control Word (CCW). If CW15-0 = 0x55AA and NVSCI1 = NVSCI0 the Censored Mode is disabled. If CW15-0 0x55AA or NVSCI1 NVSCI0 the Censored Mode is enabled.
12.2.28 Non-volatile System Censoring Information 1 register (NVSCI1)
Address offset: 0x203DE4
0 SC31 rw/X 16 CW31 rw/X 1 SC30 rw/X 17 CW30 rw/X 2 SC29 rw/X 18 CW29 rw/X 3 SC28 rw/X 19 CW28 rw/X 4 SC27 rw/X 20 CW27 rw/X 5 SC26 rw/X 21 CW26 rw/X 6 SC25 rw/X 22 CW25 rw/X 7 SC24 rw/X 23 CW24 rw/X 8 SC23 rw/X 24 CW23 rw/X 9 SC22 rw/X 25 CW22 rw/X 10 SC21 rw/X 26 CW21 rw/X 11 SC20 rw/X 27 CW20 rw/X
Delivery value: 0x55AA_55AA
12 SC19 rw/X 28 CW19 rw/X 13 SC18 rw/X 29 CW18 rw/X 14 SC17 rw/X 30 CW17 rw/X 15 SC16 rw/X 31 CW16 rw/X
Figure 12-24. Non-volatile System Censoring Information 1 register (NVSCI1)
The non-volatile System Censoring Information 1 register stores the 32 MSB of the Censorship Control Word of the device. The NVSCI1 is a non-volatile register located in the Shadow sector: it is read during the reset phase of the Flash module and the protection mechanisms are activated consequently. The parts are delivered uncensored to the user.
Table 12-33. NVSCI1 field descriptions
Field 0:15 Description SC[31:16]: Serial Censorship control word 31-16 (Read/Write) These bits represent the 16 MSB of the Serial Censorship Control Word (SCCW). If SC15-0 = 0x55AA and NVSCI1 = NVSCI0 the Public Access is disabled. If SC15-0 0x55AA or NVSCI1 NVSCI0 the Public Access is enabled.
16:31 CW[31:16]: Censorship control Word 31-16 (Read/Write) These bits represent the 16 MSB of the Censorship Control Word (CCW). If CW15-0 = 0x55AA and NVSCI1 = NVSCI0 the Censored Mode is disabled. If CW15-0 0x55AA or NVSCI1 NVSCI0 the Censored Mode is enabled.
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Chapter 12 Flash memory
12.2.29 Non-volatile User Options register (NVUSRO)
Address offset: 0x203E18
0 UO31 rw/X 16 UO15 1 UO30 rw/X 17 UO14 2 UO29 rw/X 18 UO13 3 UO28 rw/X 19 UO12 4 UO27 rw/X 20 UO11 5 UO26 rw/X 21 UO10 6 UO25 rw/X 22 UO09 7 UO24 rw/X 23 UO08 8 UO23 rw/X 24 UO07 9 UO22 rw/X 25 UO06 10 UO21 rw/X 26 UO05 11 UO20 rw/X 27 UO04
Delivery value: 0xXXXX_XXXX
12 UO19 rw/X 28 UO03 PAD3V5V 13 UO18 rw/X 29 14 UO17 rw/X 30 OSCILLATOR_MARGIN 15 UO16 rw/X 31 WATCHDOG_EN rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
Figure 12-25. Non-volatile User Options register (NVUSRO)
The non-volatile User Options Register contains configuration information for the user application. The NVUSRO register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and eventually used to manage ECC codes.
Table 12-34. NVUSRO field descriptions
Field 0:28 2 Description UO[31:03]: User Options 31-03 (Read/Write) The UO31-03 generic registers are reset based on the information stored in NVUSRO. PAD3V5V 0: High voltage supply is 5.0 V 1: High voltage supply is 3.3 V Default manufacturing value before Flash initialization is ‘1’ (3.3 V) which should ensure correct minimum slope for boundary scan. OSCILLATOR_MARGIN 0: Low consumption configuration (4 MHz/8 MHz) 1: High margin configuration (4 MHz/16 MHz) Default manufacturing value before Flash initialization is ‘1’ WATCHDOG_EN 0: Disable after reset 1: Enable after reset Default manufacturing value before Flash initialization is ‘1’
1
0
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12.2.30 Register map
Table 12-35. Flash 528 KB Single Bankregister map
Addres s offset 0x00 Registe r name MCR 0 16 EDC 1 17 0 2 18 0 3 19 0 4 20 0 5 21 SIZE 2 DON E 0 LLK1 0 0 0 0 6 22 SIZE 1 PEG 7 23 SIZE 0 0 8 24 0 9 25 LAS2 10 26 LAS1 11 27 LAS0 12 28 0 13 29 0 14 30 0 15 31 MAS
EER
RWE
0
0
PEAS
0
0
0
PGM
PSU S 0 LLK3
ERS
ESU S
EHV
0x04
LML
LME LLK1 5
0 LLK1 4 0 0 0
0 LLK1 3 0 0 0
0 LLK1 2 0 0 0
0 LLK1 1 0 0 0
0 LLK9
0 LLK8
0 LLK7
0 LLK6
0 LLK5
TSLK LLK4
0 LLK2
MLK1 MLK0 LLK1 LLK0
0x08
HBL
HBE 0
0 0 0
0 0 0
0 0 0
0 0 0
0 HLK5 0
0 HLK4 ST SLK SLK 4 0 LSL4
0 HLK3 0
0 HLK2 0
0 HLK1 SMK 1 SLK 1
0 HLK0 SMK 0 SLK 0
0x0C
SLL
SLE
SLK 15 0x10 LMS 0 LSL1 5 0x14 HBS 0 0 0x18 ADR 0 AD15 0x1C BIU0
SLK 14 0 LSL1 4 0 0 0 AD14
SLK 13 0 LSL1 3 0 0 0 AD13
SLK 12 0 LSL1 2 0 0 0 AD12
SLK 11 0 LSL1 1 0 0 0 AD11
SLK 10 0 LSL1 0 0 0 0 AD10
SLK 9 0 LSL9
SLK 8 0 LSL8
SLK 7 0 LSL7
SLK 6 0 LSL6
SLK 5 0 LSL5
SLK 3 0 LSL3
SLK 2 0 LSL2
MSL1 MSL0 LSL1 LSL0
0 0 0 AD9
0 0 0 AD8
0 0 0 AD7
0 0 AD22 AD6
0 HSL5 AD21 AD5
0 HSL4 AD20 AD4
0 HSL3 AD19 AD3
0 HSL2 AD18 0
0 HSL1 AD17 0
0 HSL0 AD16 0
BI031 BI030 BI029 BI028 BI027 BI026 BI025 BI024 BI023 BI022 BI021 BI020 BI019 BI018 BI017 BI016 BI015 BI014 BI013 BI012 BI011 BI010 BI009 BI008 BI007 BI006 BI005 BI004 BI003 BI002 BI001 BI000
0x20
BIU1
BI131 BI130 BI129 BI128 BI127 BI126 BI125 BI124 BI123 BI122 BI121 BI120 BI119 BI118 BI117 BI116 BI115 BI114 BI113 BI112 BI111 BI110 BI109 BI108 BI107 BI106 BI105 BI104 BI103 BI102 BI101 BI100
0x24
BIU2
BI231 BI230 BI229 BI228 BI227 BI226 BI225 BI224 BI223 BI222 BI221 BI220 BI219 BI218 BI217 BI216 BI215 BI214 BI213 BI212 BI211 BI210 BI209 BI208 BI207 BI206 BI205 BI204 BI203 BI202 BI201 BI200
0x28
BIU3
BI33 1 BI31 5
BI33 0 BI31 4
0 0 DAI3 0 DAI1 4 DAI6 2 DAI4 6
BI32 9 BI31 3
0 0 DAI2 9 DAI1 3 DAI6 1 DAI4 5
BI32 8 BI31 2
0 0 DAI2 8 DAI1 2 DAI6 0 DAI4 4
BI32 7 BI31 1
0 0 DAI2 7 DAI1 1 DAI5 9 DAI4 3
BI32 6 BI31 0
0 0 DAI2 6 DAI1 0 DAI5 8 DAI4 2
BI32 5 BI30 9
0 0 DAI2 5 DAI0 9 DAI5 7 DAI4 1
BI32 4 BI30 8
0 0 DAI2 4 DAI0 8 DAI5 6 DAI4 0
BI32 3 BI30 7
DSI7 0 DAI2 3 DAI0 7 DAI5 5 DAI3 9
BI32 2 BI30 6
DSI6 X DAI2 2 DAI0 6 DAI5 4 DAI3 8
BI32 1 BI30 5
DSI5 MRE DAI2 1 DAI0 5 DAI5 3 DAI3 7
BI32 0 BI30 4
DSI4 MRV DAI2 0 DAI0 4 DAI5 2 DAI3 6
BI31 9 BI30 3
DSI3 EIE DAI1 9 DAI0 3 DAI5 1 DAI3 5
BI31 8 BI30 2
DSI2 AIS DAI1 8 DAI0 2 DAI5 0 DAI3 4
BI31 7 BI30 1
DSI1 AIE DAI1 7 DAI0 1 DAI4 9 DAI3 3
BI31 6 BI30 0
DSI0 AID DAI1 6 DAI0 0 DAI4 8 DAI3 2
0x3C
UT0
UTE 0
0x40
UT1
DAI3 1 DAI1 5
0x44
UT2
DAI6 3 DAI4 7
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Table 12-35. Flash 528 KB Single Bankregister map (continued)
Addres s offset 0x48 Registe r name UMISR 0 0 16 MS 031 MS 015 0x4C UMISR 1 MS 063 MS 047 0x50 UMISR 2 MS 095 MS 079 0x54 UMISR 3 MS 127 MS 111 0x58 UMISR 4 MS 159 MS 143 1 17 MS 030 MS 014 MS 062 MS 046 MS 094 MS 078 MS 126 MS 110 MS 158 MS 142 2 18 MS 029 MS 013 MS 061 MS 045 MS 093 MS 077 MS 125 MS 109 MS 157 MS 141 3 19 MS 028 MS 012 MS 060 MS 044 MS 092 MS 076 MS 124 MS 108 MS 156 MS 140 4 20 MS 027 MS 011 MS 059 MS 043 MS 091 MS 075 MS 123 MS 107 MS 155 MS 139 5 21 MS 026 MS 010 MS 058 MS 042 MS 090 MS 074 MS 122 MS 106 MS 154 MS 138 6 22 MS 025 MS 009 MS 057 MS 041 MS 089 MS 073 MS 121 MS 105 MS 153 MS 137 7 23 MS 024 MS 008 MS 056 MS 040 MS 088 MS 072 MS 120 MS 104 MS 152 MS 136 8 24 MS 023 MS 007 MS 055 MS 039 MS 087 MS 071 MS 119 MS 103 MS 151 MS 135 9 25 MS 022 MS 006 MS 054 MS 038 MS 086 MS 070 MS 118 MS 102 MS 150 MS 134 10 26 MS 021 MS 005 MS 053 MS 037 MS 085 MS 069 MS 117 MS 101 MS 149 MS 133 11 27 MS 020 MS 004 MS 052 MS 036 MS 084 MS 068 MS 116 MS 100 MS 148 MS 132 12 28 MS 019 MS 003 MS 051 MS 035 MS 083 MS 067 MS 115 MS 099 MS 147 MS 131 13 29 MS 018 MS 002 MS 050 MS 034 MS 082 MS 066 MS 114 MS 098 MS 146 MS 130 14 30 MS 017 MS 001 MS 049 MS 033 MS 081 MS 065 MS 113 MS 097 MS 145 MS 129 15 31 MS 016 MS 000 MS 048 MS 032 MS 080 MS 064 MS 112 MS 096 MS 144 MS 128
12.2.31 Programming considerations
12.2.31.1 Modify operation
All modify operations of the Flash module are managed through the Flash User Registers Interface. All the sectors of the Flash module belong to the same partition (Bank), therefore when a Modify operation is active on some sectors no read access is possible on any other sector (Read-While-Write is not supported). During a Flash modify operation any attempt to read any Flash location will output invalid data and bit RWE of the MCR will be automatically set. This means that the Flash module is not fetchable when a modify operation is active and these commands must be executed from another memory (internal SRAM or another Flash module). If during a Modify Operation a reset occurs, the operation is suddenly terminated and the Macrocell is reset to Read Mode. The data integrity of the Flash section where the Modify Operation has been terminated is not guaranteed: the interrupted Flash Modify Operation must be repeated. In general each modify operation is started through a sequence of three steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in MCR (PGM or ERS) or UT0 (MRE or EIE). 2. The second step is the definition of the operands: the Address and the Data for programming or the Sectors for erase or margin read.
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3. The third instruction is used to start the modify operation, by setting EHV in MCR or AIE in UT0. Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. A summary of the available Flash modify operations is shown in Table 12-36.
Table 12-36. Flash modify operations
Operation Double word program Sector erase Array integrity check Margin read ECC Logic Check Select bit MCR.PGM MCR.ERS None UT0.MRE UT0.EIE Operands Address and data by interlock writes LMS, HBS LMS, HBS UT0.MRV + LMS, HBS UT0.DSI, UT1, UT2 Start bit MCR.EHV MCR.EHV UT0.AIE UT0.AIE UT0.AIE
Once bit MCR.EHV (or UT0.AIE) is set, all the operands can no more be modified until bit MCR.DONE (or UT0.AID) is high. In general each modify operation is completed through a sequence of four steps: 1. Wait for operation completion: wait for bit MCR.DONE (or UT0.AID) to go high. 2. Check operation result: check bit MCR.PEG (or compare UMISR0-4 with expected value). 3. Switch off FPEC by resetting MCR.EHV (or UT0.AIE). 4. Deselect current operation by clearing MCR.PGM/ERS (or UT0.MRE/EIE). If the device embeds more than one Flash module and a modify operation is on-going on one of them, then it is forbidden to start any other modify operation on the other Flash modules. In the following all the possible modify operations are described and some examples of the sequences needed to activate them are presented. 12.2.31.1.1 Double word program A Flash Program sequence operates on any Double Word within the Flash core. Up to two words within the Double Word may be altered in a single Program operation. ECC is handled on a 64-bit boundary. Thus, if only one word in any given 64-bit ECC segment is programmed, the adjoining word (in that segment) should not be programmed since ECC calculation has already completed for that 64-bit segment. Attempts to program the adjoining word will probably result in an operation failure. It is recommended that all programming operations be of 64 bits. The programming operation should completely fill selected ECC segments within the Double Word. Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot change a stored logic 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. The user may program the values in any or all of two words, of a Double Word, with a single program sequence.
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Double Word-bound words have addresses which differ only in address bit 2. The Program operation consists of the following sequence of events: 1. Change the value in the MCR.PGM bit from 0 to 1. 2. Ensure the block that contains the address to be programmed is unlocked. Write the first address to be programmed with the program data. The Flash module latches address bits (22:3) at this time. The Flash module latches data written as well. This write is referred to as a program data interlock write. An interlock write may be as large as 64 bits, and as small as 32 bits (depending on the CPU bus). 3. If more than 1 word is to be programmed, write the additional address in the Double Word with data to be programmed. This is referred to as a program data write. The Flash module ignores address bits (22:3) for program data writes. The eventual unwritten data word default to 0xFFFFFFFF. 4. Write a logic 1 to the MCR.EHV bit to start the internal program sequence or skip to step 9 to terminate. 5. Wait until the MCR.DONE bit goes high. 6. Confirm MCR.PEG = 1. 7. Write a logic 0 to the MCR.EHV bit. 8. If more addresses are to be programmed, return to step 2. 9. Write a logic 0 to the MCR.PGM bit to terminate the program operation. Program may be initiated with the 0 to 1 transition of the MCR.PGM bit or by clearing the MCR.EHV bit at the end of a previous program. The first write after a program is initiated determines the page address to be programmed. This first write is referred to as an interlock write. The interlock write determines if the shadow, test or normal array space will be programmed by causing MCR.PEAS to be set/cleared. An interlock write must be performed before setting MCR.EHV. The user may terminate a program sequence by clearing MCR.PGM prior to setting MCR.EHV. After the interlock write, additional writes only affect the data to be programmed at the word location determined by address bit 2. Unwritten locations default to a data value of 0xFFFFFFFF. If multiple writes are done to the same location the data for the last write is used in programming. While MCR.DONE is low and MCR.EHV is high, the user may clear EHV, resulting in a program abort. A Program abort forces the module to step 8 of the program sequence. An aborted program will result in MCR.PEG being set low, indicating a failed operation. MCR.DONE must be checked to know when the aborting command has completed. The data space being operated on before the abort will contain indeterminate data. This may be recovered by repeating the same program instruction or executing an erase of the affected blocks.
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Example 12-1. Double word program of data 0x55AA55AA at address 0x00AAA8 and data 0xAA55AA55 at address 0x00AAAC
MCR = 0x00000010; (0x00AAA8) = 0x55AA55AA; (0x00AAAC) = 0xAA55AA55; MCR = 0x00000011; do { tmp = MCR; } while ( !(tmp & 0x00000400) ); status = MCR & 0x00000200; MCR = 0x00000010; MCR = 0x00000000; /* /* /* /* /* /* Set PGM in MCR: Select Operation */ Latch Address and 32 LSB data */ Latch 32 MSB data */ Set EHV in MCR: Operation Start */ Loop to wait for DONE=1 */ Read MCR */
/* Check PEG flag */ /* Reset EHV in MCR: Operation End */ /* Reset PGM in MCR: Deselect Operation */
12.2.31.1.2Sector erase Erase changes the value stored in all bits of the selected block(s) to logic 1. An erase sequence operates on any combination of blocks (sectors) in the low, mid or high address space, or the shadow block (if available). The test block cannot be erased. The erase sequence is fully automated within the Flash. The user only needs to select the blocks to be erased and initiate the erase sequence. Locked/disabled blocks cannot be erased. If multiple blocks are selected for erase during an erase sequence, no specific operation order must be assumed. The erase operation consists of the following sequence of events: 1. Change the value in the MCR.ERS bit from 0 to 1. 2. Select the block(s) to be erased by writing ‘1’s to the appropriate register(s) in LMS or HBS registers. If the shadow block is to be erased, this step may be skipped, and LMS and HBS are ignored. Note that Lock and Select are independent. If a block is selected and locked, no erase will occur. 3. Write to any address in Flash. This is referred to as an erase interlock write. 4. Write a logic 1 to the MCR.EHV bit to start the internal erase sequence or skip to step 9 to terminate. 5. Wait until the MCR.DONE bit goes high. 6. Confirm MCR.PEG = 1. 7. Write a logic 0 to the MCR.EHV bit. 8. If more blocks are to be erased, return to step 2. 9. Write a logic 0 to the MCR.ERS bit to terminate the erase operation. After setting MCR.ERS, one write, referred to as an interlock write, must be performed before MCR.EHV can be set to ‘1’. Data words written during erase sequence interlock writes are ignored. The user may terminate the erase sequence by clearing ERS before setting EHV.
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An erase operation may be aborted by clearing MCR.EHV assuming MCR.DONE is low, MCR.EHV is high and MCR.ESUS is low. An erase abort forces the module to step 8 of the erase sequence. An aborted erase will result in MCR.PEG being set low, indicating a failed operation. MCR.DONE must be checked to know when the aborting command has completed. The block(s) being operated on before the abort contain indeterminate data. This may be recovered by executing an erase on the affected blocks. The user may not abort an erase sequence while in erase suspend.
Example 12-2. Erase of sectors B0F1 and B0F2
MCR = 0x00000004; LMS = 0x00000006; (0x000000) = 0xFFFFFFFF; MCR = 0x00000005; do { tmp = MCR; } while ( !(tmp & 0x00000400) ); status = MCR & 0x00000200; MCR = 0x00000004; MCR = 0x00000000; /* /* /* /* /* /* Set ERS in MCR: Select Operation */ Set LSL2-1 in LMS: Select Sectors to erase */ Latch a Flash Address with any data */ Set EHV in MCR: Operation Start */ Loop to wait for DONE=1 */ Read MCR */
/* Check PEG flag */ /* Reset EHV in MCR: Operation End */ /* Reset ERS in MCR: Deselect Operation */
Erase suspend/resume The erase sequence may be suspended to allow read access to the Flash core. It is not possible to program or to erase during an erase suspend. During erase suspend, all reads to blocks targeted for erase return indeterminate data. An erase suspend can be initiated by changing the value of the MCR.ESUS bit from 0 to 1. MCR.ESUS can be set to ‘1’ at any time when MCR.ERS and MCR.EHV are high and MCR.PGM is low. A 0 to 1 transition of MCR.ESUS causes the module to start the sequence which places it in erase suspend. The user must wait until MCR.DONE = 1 before the module is suspended and further actions are attempted. MCR.DONE will go high no more than tESUS after MCR.ESUS is set to ‘1’. Once suspended, the array may be read. Flash core reads while MCR.ESUS = 1 from the block(s) being erased return indeterminate data.
Example 12-3. Sector erase suspend
MCR = 0x00000007; do { tmp = MCR; } while ( !(tmp & 0x00000400) ); /* Set ESUS in MCR: Erase Suspend */ /* Loop to wait for DONE=1 */ /* Read MCR */
Notice that there is no need to clear MCR.EHV and MCR.ERS in order to perform reads during erase suspend. The erase sequence is resumed by writing a logic 0 to MCR.ESUS.
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MCR.EHV must be set to ‘1’ before MCR.ESUS can be cleared to resume the operation. The module continues the erase sequence from one of a set of predefined points. This may extend the time required for the erase operation.
Example 12-4. Sector erase resume
MCR = 0x00000005; /* Reset ESUS in MCR: Erase Resume */
12.2.31.1.3 User Test mode The user can perform specific tests to check Flash module integrity by putting the Flash module in User Test Mode. Three kinds of test can be performed: • Array Integrity Self Check • Margin Read • ECC Logic Check The User Test Mode is equivalent to a Modify operation: read accesses attempted by the user during User Test Mode generates a Read-While-Write Error (RWE of MCR set). It is not allowed to perform User Test operations on the Test and Shadow blocks. Array integrity self check Array Integrity is checked using a predefined address sequence (proprietary), and this operation is executed on selected and unlocked blocks. Once the operation is completed, the results of the reads can be checked by reading the MISR value (stored in UMISR0-), to determine if an incorrect read, or ECC detection was noted. The internal MISR calculator is a 32-bit register. The 128 bit data, the 16 ECC data and the single and double ECC errors of the two Double Words are therefore captured by the MISR through five different read accesses at the same location. The whole check is done through five complete scans of the memory address space: 1. The first pass will scan only bits 31:0 of each page. 2. The second pass will scan only bits 63:32 of each page. 3. The third pass will scan only bits 95:64 of each page. 4. The fourth pass will scan only bits 127:96 of each page. 5. The fifth pass will scan only the ECC bits (8 + 8) and the single and double ECC errors (2 + 2) of both Double Words of each page. The 128 bit data and the 16 ECC data are sampled before the eventual ECC correction, while the single and double error flags are sampled after the ECC evaluation. Only data from existing and unlocked locations are captured by the MISR. The MISR can be seeded to any value by writing the UMISR0–4 registers.
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The Array Integrity Self Check consists of the following sequence of events: 1. Set UTE in UT0 by writing the related password in UT0. 2. Select the block(s) to be checked by writing ‘1’s to the appropriate register(s) in LMS or HBS registers. Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity Check will occur. 3. Set eventually UT0.AIS bit for a sequential addressing only. 4. Write a logic 1 to the UT0.AIE bit to start the Array Integrity Check. 5. Wait until the UT0.AID bit goes high. 6. Compare UMISR0-4 content with the expected result. 7. Write a logic 0 to the UT0.AIE bit. 8. If more blocks are to be checked, return to step 2. It is recommended to leave UT0.AIS at 0 and use the proprietary address sequence that checks the read path more fully, although this sequence takes more time. During the execution of the Array Integrity Check operation it is forbidden to modify the content of Block Select (LMS, HBS) and Lock (LML, SLL, HBL) registers, otherwise the MISR value can vary in an unpredictable way. While UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Array Integrity Check abort. UT0.AID must be checked to know when the aborting command has completed.
Example 12-5. Array integrity check of sectors B0F1 and B0F2
UT0 = 0xF9F99999; LMS = 0x00000006; UT0 = 0x80000002; do { tmp = UT0; } while ( !(tmp & 0x00000001) ); data0 = UMISR0; data1 = UMISR1; data2 = UMISR2; data3 = UMISR3; data4 = UMISR4; UT0 = 0x00000000; /* /* /* /* /* /* /* /* /* /* /* Set UTE in UT0: Enable User Test */ Set LSL2-1 in LMS: Select Sectors */ Set AIE in UT0: Operation Start */ Loop to wait for AID=1 */ Read UT0 */ Read UMISR0 content*/ Read UMISR1 content*/ Read UMISR2 content*/ Read UMISR3 content*/ Read UMISR4 content*/ Reset UTE and AIE in UT0: Operation End */
Margin read Margin read procedure (either Margin 0 or Margin 1), can be run on unlocked blocks in order to unbalance the Sense Amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin vs ‘0’ (UT0.MRV = ‘0’) or vs ‘1’ (UT0.MRV = ‘1’). Locked sectors are ignored by MISR calculation and ECC flagging. The results of the margin reads can be checked comparing checksum value in UMISR0-4. Since Margin reads are done at voltages that differ than the normal read voltage, lifetime expectancy of the Flash macrocell is impacted by the execution of Margin reads. Doing Margin reads repetitively results in degradation of the Flash Array, and shorten expected lifetime experienced at normal read levels. For these reasons the Margin Read usage is allowed only in Factory, while it is forbidden to use it inside the User Application.
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In any case the charge losses detected through the Margin Read cannot be considered failures of the device and no Failure Analysis will be opened on them. The Margin Read Setup operation consists of the following sequence of events: 1. Set UTE in UT0 by writing the related password in UT0. 2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS or HBS registers. Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity Check will occur. 3. Set T0.AIS bit for a sequential addressing only. 4. Change the value in the UT0.MRE bit from 0 to 1. 5. Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin. 6. Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate. 7. Wait until the UT0.AID bit goes high. 8. Compare UMISR0-4 content with the expected result. 9. Write a logic 0 to the UT0.AIE, UT0.MRE and UT0.MRV bits. 10. If more blocks are to be checked, return to step 2. It is mandatory to leave UT0.AIS at 1 and use the linear address sequence, the usage of the proprietary sequence in Margin Read is forbidden. During the execution of the Margin Read operation it is forbidden to modify the content of Block Select (LMS, HBS) and Lock (LML, SLL, HBL) registers, otherwise the MISR value can vary in an unpredictable way. The read accesses will be done with the addition of a proper number of Wait States to guarantee the correctness of the result. While UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Array Integrity Check abort. UT0.AID must be checked to know when the aborting command has completed.
Example 12-6. Margin read setup versus ‘1’s
UMISR0 = 0x00000000; UMISR1 = 0x00000000; UMISR2 = 0x00000000; UMISR3 = 0x00000000; UMISR4 = 0x00000000; UT0 = 0xF9F99999; LMS = 0x00000006; UT0 = 0x80000004; UT0 = 0x80000024; UT0 = 0x80000034; UT0 = 0x80000036; do { tmp = UT0; } while ( !(tmp & 0x00000001) ); data0 = UMISR0; /* /* /* /* /* /* /* /* /* /* /* /* /* Reset UMISR0 content */ Reset UMISR1 content */ Reset UMISR2 content */ Reset UMISR3 content */ Reset UMISR4 content */ Set UTE in UT0: Enable User Test */ Set LSL2-1 in LMS: Select Sectors */ Set AIS in UT0: Select Operation */ Set MRE in UT0: Select Operation */ Set MRV in UT0: Select Margin versus 1’s */ Set AIE in UT0: Operation Start */ Loop to wait for AID=1 */ Read UT0 */
/* Read UMISR0 content*/
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data1 data2 data3 data4 UT0 UT0
= = = = = =
UMISR1; UMISR2; UMISR3; UMISR4; 0x80000034; 0x00000000;
/* /* /* /* /* /*
Read UMISR1 content*/ Read UMISR2 content*/ Read UMISR3 content*/ Read UMISR4 content*/ Reset AIE in UT0: Operation End */ Reset UTE, MRE, MRV, AIS in UT0: Deselect Op. */
To exit from the Margin Read Mode a Read Reset operation must be executed. ECC logic check ECC logic can be checked by forcing the input of ECC logic: The 64 bits of data and the 8 bits of ECC syndrome can be individually forced and they will drive simultaneously at the same value the ECC logic of the whole page (2 Double Words). The results of the ECC Logic Check can be verified by reading the MISR value. The ECC Logic Check operation consists of the following sequence of events: 1. Set UTE in UT0 by writing the related password in UT0. 2. Write in UT1.DAI31–0 and UT2.DAI63–32 the Double Word Input value. 3. Write in UT0.DSI7–0 the Syndrome Input value. 4. Select the ECC Logic Check: write a logic 1 to the UT0.EIE bit. 5. Write a logic 1 to the UT0.AIE bit to start the ECC Logic Check. 6. Wait until the UT0.AID bit goes high. 7. Compare UMISR0–4 content with the expected result. 8. Write a logic 0 to the UT0.AIE bit. Notice that when UT0.AID is low UMISR0–4, UT1–2 and bits MRE, MRV, EIE, AIS and DSI7–0 of UT0 are not accessible: reading returns indeterminate data and write has no effect.
Example 12-7. ECC logic check
UT0 = 0xF9F99999; UT1 = 0x55555555; UT2 = 0xAAAAAAAA; UT0 = 0x80FF0000; UT0 = 0x80FF0008; UT0 = 0x80FF000A; do { tmp = UT0; } while ( !(tmp & 0x00000001) ); data0 = UMISR0; data1 = UMISR1; data2 = UMISR2; data3 = UMISR3; data4 = UMISR4; UT0 = 0x00000000; /* /* /* /* /* /* /* /* /* /* /* /* /* /* Set UTE in UT0: Enable User Test */ Set DAI31-0 in UT1: Even Word Input Data */ Set DAI63-32 in UT2: Odd Word Input Data */ Set DSI7-0 in UT0: Syndrome Input Data */ Set EIE in UT0: Select ECC Logic Check */ Set AIE in UT0: Operation Start */ Loop to wait for AID=1 */ Read UT0 */ Read UMISR0 content (expected Read UMISR1 content (expected Read UMISR2 content (expected Read UMISR3 content (expected Read UMISR4 content (expected Reset UTE, AIE and EIE in UT0: 0x55555555) */ 0xAAAAAAAA) */ 0x55555555) */ 0xAAAAAAAA) */ 0x00FF00FF) */ Operation End */
12.2.31.2 Error correction code
The Flash module provides a method to improve the reliability of the data stored in Flash: the usage of an Error Correction Code. The word size is fixed at 64 bits.
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Eight ECC bits, programmed to guarantee a Single Error Correction and a Double Error Detection (SEC-DED), are associated to each 64-bit Double Word. ECC circuitry provides correction of single bit faults and is used to achieve automotive reliability targets. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. 12.2.31.2.1 ECC algorithms The Flash module supports one ECC Algorithm: “All ‘1’s No Error”. A modified Hamming code is used that ensures the all erased state (that is, 0xFFFF.....FFFF) data is a valid state, and will not cause an ECC error. This allows the user to perform a blank check after a sector erase operation. 12.2.31.3 12.2.31.4 EEprom emulation Eprom Emulation
The choosen ECC algorithm allows some bit manipulations so that a Double Word can be rewritten several times without needing an erase of the sector. This allows to use a Double Word to store flags useful for the Eeprom Emulation. As an example the choosen ECC algorithm allows to start from an All ‘1’s Double Word value and rewrite whichever of its four 16-bits Half-Words to an All ‘0’s content by keeping the same ECC value. The following table shows a set of Double Words sharing the same ECC value:
Table 12-37. Bits Manipulation: Double Words with the same ECC value
Double Word 0xFFFF_FFFF_FFFF_FFFF 0xFFFF_FFFF_FFFF_0000 0xFFFF_FFFF_0000_FFFF 0xFFFF_0000_FFFF_FFFF 0x0000_FFFF_FFFF_FFFF 0xFFFF_FFFF_0000_0000 0xFFFF_0000_FFFF_0000 0x0000_FFFF_FFFF_0000 0xFFFF_0000_0000_FFFF 0x0000_FFFF_0000_FFFF 0x0000_0000_FFFF_FFFF 0xFFFF_0000_0000_0000 0x0000_FFFF_0000_0000 0x0000_0000_0000_0000 ECC All ‘1’s No Error 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
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When some Flash sectors are used to perform an Eeprom Emulation, it is reccomended for safety reasons to reserve at least 3 sectors to this purpose. 12.2.31.4.1 All ‘1’s No Error The All ‘1’s No Error Algorithm detects as valid any Double Word read on a just erased sector (all the 72 bits are ‘1’s). This option allows to perform a Blank Check after a Sector Erase operation.
12.2.31.5 Protection strategy
Two kinds of protection are available: Modify Protection to avoid unwanted program/erase in Flash sectors and Censored Mode to avoid piracy. 12.2.31.5.1 Modify protection The Flash Modify Protection information is stored in non-volatile Flash cells located in the TestFlash. This information is read once during the Flash initialization phase following the exiting from Reset and is stored in volatile registers that act as actuators. The reset state of all the volatile modify protection registers is the protected state. All the non-volatile modify protection registers can be programmed through a normal Double Word Program operation at the related locations in TestFlash. The non-volatile modify protection registers cannot be erased. • The non-volatile Modify Protection Registers are physically located in TestFlash their bits can be programmed to ‘0’ only once and they can no more be restored to ‘1’. • The Volatile Modify Protection Registers are Read/Write registers which bits can be written at ‘0’ or ‘1’ by the user application. A software mechanism is provided to independently lock/unlock each Low, Mid and High Address Space Block against program and erase. Software locking is done through the LML (Low/Mid Address Space Block Lock Register) or HBL (High Address Space Block Lock Register) registers. An alternate means to enable software locking for blocks of Low Address Space only is through the SLL (Secondary Low/Mid Address Space Block Lock Register). All these registers have a non-volatile image stored in TestFlash (NVLML, NVHBL, NVSLL), so that the locking information is kept on reset. On delivery the TestFlash non-volatile image is at all ‘1’s, meaning all sectors are locked. By programming the non-volatile locations in TestFlash the selected sectors can be unlocked. Being the TestFlash One Time Programmable (that is, not erasable), once unlocked the sectors cannot be locked again.
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Of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the user application can lock and unlock sectors when desired. 12.2.31.5.2 Censored mode The Censored Mode information is stored in non-volatile Flash cells located in the Shadow Sector. This information is read once during the Flash initialization phase following the exiting from Reset and is stored in volatile registers that act as actuators. The reset state of all the Volatile Censored Mode Registers is the protected state. All the non-volatile Censored Mode registers can be programmed through a normal Double Word Program operation at the related locations in the Shadow Sector. The non-volatile Censored Mode registers can be erased by erasing the Shadow Sector. • The non-volatile Censored Mode Registers are physically located in the Shadow Sector their bits can be programmed to ‘0’ and eventually restored to ‘1’ by erasing the Shadow Sector. • The Volatile Censored Mode Registers are registers not accessible by the user application. The Flash module provides two levels of protection against piracy: • If bits CW15:0 of NVSCI0 are programmed at 0x55AA and NVSC1 = NVSCI0 the Censored Mode is disabled, while all the other possible values enable the Censored Mode. • If bits SC15:0 of NVSCI0 are programmed at 0x55AA and NVSC1 = NVSCI0 the Public Access is disabled, while all the other possible values enable the Public Access. The parts are delivered to the user with Censored Mode and Public Access disabled.
12.3
12.3.1
Data Flash
Introduction
The primary function of the Data Flash module is to serve as electrically programmable and erasable non-volatile memory. Non-volatile memory may be used for instruction and/or data storage. The module is a non-volatile solid-state silicon memory device consisting of blocks (also called “sectors”) of single transistor storage elements, an electrical means for selectively adding (programming) and removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements. The Data Flash module is arranged as two functional units: the Flash core and the memory interface. The Flash core is composed of arrayed non-volatile storage elements, sense amplifiers, row decoders, column decoders and charge pumps. The arrayed storage elements in the Flash core are subdivided into physically separate units referred to as blocks (or sectors).
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The memory interface contains the registers and logic which control the operation of the Flash core. The memory interface is also the interface between the Flash module and a Bus Interface Unit (BIU) and contains the ECC logic and redundancy logic. A BIU connects the Flash module to a system bus, and contains all system level customization required for the device application.
12.3.2
• • • • • • • • •
Main features
120 ns Access Time 32 bits Read/Write parallelism 7 bits Error Correction Code (SEC-DED) to enhance Data Retention Sector erase Single Bank: Read-While-Write not available Erase Suspend available (Program Suspend not available) Software programmable Program/Erase Protection to avoid unwanted writings Shadow Sector not available Optimized Data Flash is a slave IP that requires clocks and reference current coming from Master LC Data Flash.
12.3.3
Block diagram
The Flash module contains one Matrix Module, composed of a single bank: Bank 0, normally used for code storage. No Read-While-Write operations are possible. Modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands to the FPEC are given through a User Registers Interface. The read data bus is 32 bits wide, while the Flash registers are on a separate bus 32 bits wide. The high voltages needed for program/erase operations are internally generated addressed in user memory map.
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HV generator
Flash Bank 0 64 Kbyte + 8 KB TestFlash
Flash Program/Erase Controller Flash Registers
Matrix Interface
Registers Interface
Figure 12-26. Flash module structure
12.3.4
12.3.4.1
Functional description
Module structure
The Flash Module is addressable by Word (32 bits) for program and for read. The Flash module supports fault tolerance through Error Correction Code (ECC) and/or error detection. The ECC implemented within the Flash module will correct single bit failures and detect double bit failures. The Flash module uses an embedded hardware algorithm implemented in the Memory Interface to program and erase the Flash core. Control logic that works with the software block enables, and software lock mechanisms, is included in the embedded hardware algorithm to guard against accidental program/erase. The hardware algorithm perform the steps necessary to ensure that the storage elements are programmed and erased with sufficient margin to guarantee data integrity and reliability. A programmed bit in the Flash module reads as logic level 0 (or low). An erased bit in the Flash module reads as logic level 1 (or high). Program and erase of the Flash module requires multiple system clock cycles to complete. The erase sequence may be suspended. The program and erase sequences may be aborted.
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Being a slave IP, Data Flash requires Code Flash to be active (means not under reset or in Disable Mode or in Sleep Mode) in order to be active.
12.3.4.2
Flash module sectorization
The Flash Module supports memory sizes of 72Kbyte of User Memory, plus 8 Kbyte of Test Memory. The Flash module is composed of a single bank (Bank 0): Read-While-Write is not supported. Bank 0 of the 72 Kbyte Flash module is divided in four sectors. Bank 0 also contains a reserved sector named TestFlash in which some One-Time Programmable user data are stored. The sectorization of the 72 Kbyte Matrix Module is shown in the Table 12-38.
Table 12-38. 72 Kbyte Flash module sectorization
Bank B0 B0 B0 B0 B0 B0 B0 B0 Sector B0F0 B0F1 B0F2 B0F3 Reserved Reserved B0TF Reserved Addresses 0x000000 to 0x003FFF 0x004000 to 0x007FFF 0x008000 to 0x00BFFF 0x00C000 to 0x00FFFF 0x010000 to 0x03FFFF 0x040000 to 0x07FFFF 0x402000 to 0x403FFF 0x404000 to 0x7FFFFF Size 16Kbyte 16Kbyte 16Kbyte 16Kbyte 192Kbyte 256Kbyte 8Kbyte 4080Kbyte Address space Low Address Space Low Address Space Low Address Space Low Address Space Low Address Space Mid Address Space Test Address Space Test Address Space
The Flash module is divided into blocks also to implement independent erase/program protection. A software mechanism is provided to independently lock/unlock each block in low and mid address space against program and erase. 12.3.4.2.1 Test Flash Block
The TestFlash block exists outside the normal address space and is programmed and read independently of the other blocks. The independent TestFlash block is reserved to store the non-volatile information related to redundancy, configuration and protection. The ECC is also applied to TestFlash. The structure of the TestFlash sector is detailed in Table 12-39.
Table 12-39. TestFlash structure
Name — — NVLML — Description Reserved User reserved Non-volatile Low/Mid address space block Locking register Reserved Addresses 0x402000–0x403CFF 0x403D00–0x403DE7 0x403DE8–0x403DEF 0x403DF0–0x403DF7 Size 7424 byte 232 byte 8 byte 8 byte
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Table 12-39. TestFlash structure (continued)
Name NVSLL — — Description Non-volatile Secondary Low/Mid address space block Lock register User reserved Reserved Addresses 0x403DF8–0x403DFF 0x403E00–0x403EFF 0x403F00–0x403FFF Size 8 byte 256 byte 256 byte
When the Test space is enabled, all the operations are mapped to the Test block. User mode program of the test block are enabled only when MCR.PEAS is high. The Test Flash block may be locked/unlocked against program by using the LML.TSLK and SLL.STSLK registers. Erase of Test Flash block is always locked in user mode. Programming of the TestFlash block has similar restrictions as the array in terms of how ECC is calculated. Only one programming operation is allowed per 32-bit ECC segment.
12.3.5
User mode operation
In User mode the Flash module may be read and written (register writes and interlock writes), programmed or erased. The default state of the Flash module is read. The main and test address space can be read only in the read state. The Flash registers are always available for read, also when the module is in power-down mode (except few documented registers). Most of the Flash registers are mapped on Flip-Flops and can be read on IPS bus also when the Flash macrocell is forced in disable mode. Few Flash registers (bits MRE, MRV, AIS, EIE and DSI7-0 of UT0, whole UT1 and UT2) are mapped in Flash SRAM and cannot be read when the Flash is in disable mode (reading returns indeterminate data). The Flash module enters the read state on reset. The module is in the read state under two sets of conditions: • The read state is active when the module is enabled (User Mode Read) • The read state is active when MCR.ERS and MCR.ESUS are high and MCR.PGM is low (Erase Suspend). Notice that Read-While-Write is not available. Flash core reads return 32 bits (1 Word). Registers reads return 32 bits (1 Word). Flash core reads are done through the Bus Interface Unit. Registers reads to unmapped register address space will return all ‘0’s. Registers writes to unmapped register address space will have no effect.
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Attempted array reads to invalid locations will result in indeterminate data. Invalid locations occur when blocks that do not exist in non 2n array sizes are addressed. Attempted interlock writes to invalid locations will result in an interlock occurring, but attempts to program these blocks will not occur since they are forced to be locked. Erase will occur to selected and unlocked blocks even if the interlock write is to an invalid location. Simultaneous Read cycle on the Flash Matrix and Read/Write cycles on the Registers are possible. On the contrary, Registers Read/Write accesses simultaneous to a Flash Matrix interlock write are forbidden.
12.3.5.1
Reset
A reset is the highest priority operation for the Flash module and terminates all other operations. The Flash Module uses reset to initialize register and status bits to their default reset values. If the Flash Module is executing a Program or Erase operation (MCR.PGM = 1 or MCR.ERS = 1) and a reset is issued, the operation will be suddently terminated and the module will disable the high voltage logic without damage to the high voltage circuits. Reset terminates all operations and forces the Flash Module into User mode ready to receive accesses. After reset is negated, read register access may be done, although it should be noted that registers that require updating from Test block or KRAM information, or other inputs, may not read updated values until MCR.DONE transitions. MCR.DONE may be polled to determine if the Flash module has transitioned out of reset. Notice that the registers cannot be written until MCR.DONE is high.
12.3.5.2
Power-down mode
The power-down mode allows to turn off all Flash DC current sources, so that all power dissipation is due only to leakage in this mode. Reads from or writes to the module are not possible in power-down mode. The user may not read some registers (UMISR0–1, UT1 and part of UT0) until the power-down mode is exited. When enabled the Flash module returns to its pre-disable state in all cases unless in the process of executing an erase high voltage operation at the time of disable. If the Flash module enters power-down mode during an erase operation, bit MCR.ESUS is set to ‘1’. The user may resume the erase operation at the time the module is enabled by clearing bit MCR.ESUS. MCR.EHV must be high to resume the erase operation. If the Flash module enters power-down mode during a program operation, the operation will be in any case completed and the power-down mode will be entered only after the programming end. The user should realize that, if the Flash module is put in power-down mode and the interrupt vectors remain mapped in the Flash address space, the Flash module will greatly increase the interrupt response time by adding several wait-states. It is forbidden to enter low power mode when the power-down mode is active.
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12.3.5.3
Slave Mode.
Being a slave IP, Data Flash requires Code Flash to be active (means not under reset or in Disable Mode or in Sleep Mode) in order to be active. It is forbidden to put Code Flash in Disable Mode or in Sleep mode or under reset when the Data Flash is active
12.3.6
Register description
Table 12-40. Flash 528 KB Single Bank Registers
Register name Module Configuration Register (MCR) Low/Mid address space block Locking register (LML) Reserved Secondary Low/mid address space block Locking register (SLL) Low/Mid address space block Select register (LMS) Reserved Address Register (ADR) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved User Test 0 register (UT0) User Test 1 register (UT1) Reserved User Multiple Input Signature Register 0 (UMISR0) User Multiple Input Signature Register 1 (UMISR1) Address offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C Location on page 335 on page 340 — on page 342 on page 344 — on page 345 — — — — — — — — on page 346 on page 348 — on page 348 on page 349
The Flash user registers mapping is shown in the Table 12-40.
Locations 0x0044, 0x0050, 0x0054 and 0x0058 are Write/Read from user point of view but no functionaly is associated. Registers are not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. In the following some non-volatile registers are described. Please notice that such entities are not Flip-Flops, but locations of TestFlash sector with a special meaning.
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During the Flash initialization phase, the FPEC reads these non-volatile registers and update the corresponding volatile registers. When the FPEC detects ECC double errors in these special locations, it behaves in the following way: • In case of a failing system locations (configurations, redundancy, embedded firmware), the initialization phase is interrupted and a Fatal Error is flagged. • In case of failing user locations (protections, censorship, BIU, ...), the volatile registers are filled with all ‘1’s and the Flash initialization ends setting low the PEG bit of MCR. Table 12-41 lists bit access type abbreviations used in this section.
Table 12-41. Abbreviations
Abbreviation rw rc r w Case read/write read/clear read-only write-only Description The software can read and write to these bits. The software can read and clear to these bits. The software can only read these bits. The software should only write to these bits.
12.3.7
Module Configuration Register (MCR)
Reset value:0x0667_0X00
3 0 r/0 19 0 r/0 4 0 r/0 20 PEAS r/0 5 SIZE2 r/1 21 DONE r/X 6 SIZE1 r/1 22 PEG r/1 7 SIZE0 r/0 23 0 r/0 8 0 r/0 24 0 r/0 9 LAS2 r/1 25 0 r/0 10 LAS1 r/1 26 0 r/0 11 LAS0 r/0 27 PGM rw/0 12 0 r/0 28 PSUS rw/0 13 MAS2 r/1 29 ERS rw/0 14 MAS1 r/1 30 ESUS rw/0 15 MAS0 r/1 31 EHV rw/0
Address offset: 0x0000
0 EDC rc/0 16 EER rc/0 1 0 r/0 17 RWE rc/0 2 0 r/0 18 0 r/0
Figure 12-27. Module Configuration Register (MCR)
The Module Configuration Register is used to enable and monitor all modify operations of the Flash module.
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Table 12-42. MCR field descriptions
Field 0 Description EDC: ECC Data Correction (Read/Clear) EDC provides information on previous reads. If an ECC Single Error detection and correction occurred, the EDC bit is set to ‘1’. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may not be set to ‘1’ by the user. In the event of an ECC Double Error detection, this bit will not be set. If EDC is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of EDC) were not corrected through ECC. Since this bit is an error flag, it must be cleared to ‘0’ by writing 1 to the register location. A write of 0 will have no effect. The function of this bit is device dependent and it can be configured to be disabled. 0: Reads are occurring normally. 1: An ECC Single Error occurred and was corrected during a previous read. Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0. SIZE[2:0]: array space SIZE 2-0 (Read Only) The value of SIZE field is dependent upon the size of the Flash module; see Table 12-43. Reserved (Read Only). Write this bit has no effect and read this bit always outputs 0. LAS[2:0]: Low Address Space 2-0 (Read Only) The value of the LAS field corresponds to the configuration of the Low Address Space; see Table 12-44. Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0.
1:4 5:7 8 9:11 12
13:15 MAS[2:0]: Mid Address Space (Read Only) The value of the MAS field corresponds to the configuration of the Mid Address Space; see Table 12-45. 16 EER: ECC event Error (Read/Clear) EER provides information on previous reads. If an ECC Double Error detection occurred, the EER bit is set to ‘1’. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may not be set to ‘1’ by the user. In the event of an ECC Single Error detection and correction, this bit will not be set. If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of EER) were correct. Since this bit is an error flag, it must be cleared to ‘0’ by writing 1 to the register location. A write of 0 will have no effect. 0: Reads are occurring normally. 1: An ECC Double Error occurred during a previous read. RWE: Read-while-Write event Error (Read/Clear) RWE provides information on previous reads when a Modify operation is on going. If a RWW Error occurs, the RWE bit will be set to ‘1’. Read-While-Write Error means that a read access to the Flash Matrix has occurred while the FPEC was performing a program or erase operation or an Array Integrity Check. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may not be set to ‘1’ by the user. If RWE is not set, or remains 0, this indicates that all previous RWW reads (from the last reset, or clearing of RWE) were correct. Since this bit is an error flag, it must be cleared to ‘0’ by writing 1 to the register location. A write of 0 will have no effect. 0: Reads are occurring normally. 1: A RWW Error occurred during a previous read.
17
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Table 12-42. MCR field descriptions (continued)
Field Description
18:19 Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0. 20 PEAS: Program/Erase Access Space (Read Only) PEAS is used to indicate which space is valid for program and erase operations: main array space or test space. PEAS = 0 indicates that the main address space is active for all Flash module program and erase operations. PEAS = 1 indicates that the main address space is active for program and erase. The value in PEAS is captured and held with the first interlock write done for Modify operations. The value of PEAS is retained between sampling events (that is, subsequent first interlock writes). 0: Test address space is disabled for program/erase and main address space enabled. 1: Test address space is enabled for program/erase and main address space disabled. DONE: modify operation DONE (Read Only) DONE indicates if the Flash Module is performing a high voltage operation. DONE is set to 1 on termination of the Flash Module reset. DONE is cleared to 0 just after a 0 to 1 transition of EHV, which initiates a high voltage operation, or after resuming a suspended operation. DONE is set to 1 at the end of program and erase high voltage sequences. DONE is set to 1 (within tPABT or tEABT, equal to P/E Abort Latency) after a 1 to 0 transition of EHV, which aborts a high voltage Program/Erase operation. DONE is set to 1 (within tESUS, time equals to Erase Suspend Latency) after a 0 to 1 transition of ESUS, which suspends an erase operation. 0: Flash is executing a high voltage operation. 1: Flash is not executing a high voltage operation. PEG: Program/Erase Good (Read Only) The PEG bit indicates the completion status of the last Flash program or erase sequence for which high voltage operations were initiated. The value of PEG is updated automatically during the program and erase high voltage operations. Aborting a program/erase high voltage operation will cause PEG to be cleared to ‘0’, indicating the sequence failed. PEG is set to ‘1’ when the Flash module is reset, unless a Flash initialization error has been detected. The value of PEG is valid only when PGM = 1 and/or ERS = 1 and after DONE transitions from 0 to 1 due to an abort or the completion of a program/erase operation. PEG is valid until PGM/ERS makes a 1 to 0 transition or EHV makes a 0 to 1 transition. The value in PEG is not valid after a 0 to 1 transition of DONE caused by ESUS being set to logic 1. If program or erase are attempted on blocks that are locked, the response will be PEG = 1, indicating that the operation was successful, and the content of the block were properly protected from the program or erase operation. If a Program operation tries to program at ‘1’ bits that are at ‘0’, the program operation is correctly executed on the new bits to be programmed at ‘0’, but PEG is cleared, indicating that the requested operation has failed. In Array Integrity Check or Margin Read PEG is set to 1 when the operation is completed, regardless the occurrence of any error. The presence of errors can be detected only comparing checksum value stored in UMIRS0-1. Aborting an Array Integrity Check or a Margin Read operation will cause PEG to be cleared to 0, indicating the sequence failed. 0: Program, Erase operation failed or Program, Erase, Array Integrity Check or Maring Mode aborted. 1: Program or Erase operation succesful or Array Integrity Check or Maring Mode completed.
21
22
23:26 Reserved (Read Only) Write these bits has no effect and read these bits always outputs 0.
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Table 12-42. MCR field descriptions (continued)
Field 27 Description PGM: ProGraM (Read/Write) PGM is used to set up the Flash module for a Program operation. A 0 to 1 transition of PGM initiates a Program sequence. A 1 to 0 transition of PGM ends the Program sequence. PGM can be set only under User Mode Read (ERS is low and UT0.AIE is low). PGM can be cleared by the user only when EHV is low and DONE is high. PGM is cleared on reset. 0: Flash is not executing a Program sequence. 1: Flash is executing a Program sequence. PSUS: Program SUSpend (Read/Write) Write this bit has no effect, but the written data can be read back. ERS: ERaSe (Read/Write) ERS is used to set up the Flash module for an erase operation. A 0 to 1 transition of ERS initiates an erase sequence. A 1 to 0 transition of ERS ends the erase sequence. ERS can be set only under User Mode Read (PGM is low and UT0.AIE is low). ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0: Flash is not executing an erase sequence. 1: Flash is executing an erase sequence. ESUS: Erase SUSpend (Read/Write) ESUS is used to indicate that the Flash module is in Erase Suspend or in the process of entering a Suspend state. The Flash module is in Erase Suspend when ESUS = 1 and DONE = 1. ESUS can be set high only when ERS and EHV are high and PGM is low. A 0 to 1 transition of ESUS starts the sequence which sets DONE and places the Flash in Erase Suspend. The Flash module enters Suspend within tESUS of this transition. ESUS can be cleared only when DONE and EHV are high and PGM is low. A 1 to 0 transition of ESUS with EHV = 1 starts the sequence which clears DONE and returns the module to Erase. The Flash module cannot exit Erase Suspend and clear DONE while EHV is low. ESUS is cleared on reset. 0: Erase sequence is not suspended. 1: Erase sequence is suspended.
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Table 12-42. MCR field descriptions (continued)
Field 31 Description EHV: Enable High Voltage (Read/Write) The EHV bit enables the Flash module for a high voltage program/erase operation. EHV is cleared on reset. EHV must be set after an interlock write to start a program/erase sequence. EHV may be set under one of the following conditions: Erase (ERS = 1, ESUS = 0, UT0.AIE = 0) Program (ERS = 0, ESUS = 0, PGM = 1, UT0.AIE = 0) In normal operation, a 1 to 0 transition of EHV with DONE high and ESUS low terminates the current program/erase high voltage operation. When an operation is aborted, there is a 1 to 0 transition of EHV with DONE low and the eventual Suspend bit low. An abort causes the value of PEG to be cleared, indicating a failing program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. A suspended operation cannot be aborted. Aborting a high voltage operation will leave the Flash module addresses in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. EHV may be written during Suspend. EHV must be high to exit Suspend. EHV may not be written after ESUS is set and before DONE transitions high. EHV may not be cleared after ESUS is cleared and before DONE transitions low. 0: Flash is not enabled to perform an high voltage operation. 1: Flash is enabled to perform an high voltage operation.
Table 12-43. Array space size
SIZE[2:0] 000 001 010 011 100 101 110 111 Array space size 128 KB 256 KB Reserved (512 KB) Reserved (1024 KB) Reserved (1536 KB) Reserved (2048 KB) 64 KB Reserved
Table 12-44. Low address space configuration
LAS[2:0] 000 001 010 011 100 101 Low address space sectorization 0 KB 2 x 128KB 32 KB + 2 x 16 KB + 2 x 32 KB + 128 KB Reserved Reserved Reserved
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Table 12-44. Low address space configuration (continued)
LAS[2:0] 110 111 Low address space sectorization 4 x 16 KB 2 x 16KB + 2 x 32KB + 2 x 16KB + 2 x 64KB
Table 12-45. Mid address space configuration
MAS 000 111 Others Mid address space sectorization 2 x 128KB MID not present Reserved
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state. These write locks are covered on a bit by bit basis in the preceding description, but those locks do not consider the effects of trying to write two or more bits simultaneously. The Flash module does not allow the user to write bits simultaneously which would put the device into an illegal state. This is implemented through a priority mechanism among the bits. The bit changing priorities are detailed in the Table 12-46.
Table 12-46. MCR bits set/clear priority levels
Priority Level 1 2 3 4 MCR bits ERS PGM EHV ESUS
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority level is written.
12.3.8
Low/Mid address space block Locking register (LML)
Address offset: 0x0004 Reset value: 0x00X0_00XX, initially determined by NVLML value from test sector.
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12.3.8.1
Non-volatile Low/Mid address space block Locking register (NVLML)
Delivery value: 0xFFFF_FFFF
4 0 r/0 20 LLK11 rw/X 5 0 r/0 21 LLK10 rw/X 6 0 r/0 22 LLK9 rw/X 7 0 r/0 23 LLK8 rw/X 8 0 r/0 24 LLK7 rw/X 9 0 r/0 25 LLK6 rw/X 10 0 r/0 26 LLK5 rw/X 11 TSLK rw/X 27 LLK4 rw/X 12 0 r/0 28 LLK3 rw/X 13 0 r/0 29 LLK2 rw/X 14 0 r/0 30 LLK1 rw/X 15 0 r/0 31 LLK0 rw/X
Address offset: 0x403DE8
0 LME r/0 16 LLK15 rw/X 1 0 r/0 17 LLK14 rw/X 2 0 r/0 18 LLK13 rw/X 3 0 r/0 19 LLK12 rw/X
Figure 12-28. Non-volatile Low/Mid address space block Locking register (NVLML)
The Low/Mid Address Space Block Locking register provides a means to protect blocks from being modified. These bits, along with bits in the SLL register, determine if the block is locked from Program or Erase. An “OR” of LML and SLL determine the final lock status. The LML register has a related Non-volatile Low/Mid Address Space Block Locking register located in TestFlash that contains the default reset value for LML. During the reset phase of the Flash module, the NVLML register content is read and loaded into the LML.
Table 12-47. LML field descriptions
Field 0 Description LME: Low/Mid address space block Enable (Read Only) This bit is used to enable the Lock registers (TSLK and LLK15-0) to be set or cleared by registers writes. This bit is a status bit only. The method to set this bit is to write a password, and if the password matches, the LME bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. For LME the password 0xA1A11111 must be written to the LML register. 0: Low Address Locks are disabled: TSLK and LLK15-0 cannot be written. 1: Low Address Locks are enabled: TSLK and LLK15-0 can be written. Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. TSLK: Test address space block LocK (Read/Write) This bit is used to lock the block of Test Address Space from Program and Erase (Erase is any case forbidden for Test block). A value of 1 in the TSLK register signifies that the Test block is locked for Program and Erase. A value of 0 in the TSLK register signifies that the Test block is available to receive program and erase pulses. The TSLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the TSLK register is not writable if a high voltage operation is suspended or if a Margin Read is on going. Upon reset, information from the TestFlash block is loaded into the TSLK register. The TSLK bit may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The default value of the TSLK bit (assuming erased fuses) would be locked. TSLK is not writable unless LME is high. 0: Test Address Space Block is unlocked and can be modified (also if SLL.STSLK = 0). 1: Test Address Space Block is locked and cannot be modified.
1:10 11
12:15 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
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Table 12-47. LML field descriptions (continued)
Field Description
16:31 LLK[15:0]: Low address space block LocK 15-0 (Read/Write) These bits are used to lock the blocks of Low Address Space from Program and Erase. LLK[3:0] are related to sectors B0F3-0, respectively. LLK[15:4] are not used for this memory cut. A value of 1 in a bit of the LLK register signifies that the corresponding block is locked for Program and Erase. A value of 0 in a bit of the LLK register signifies that the corresponding block is available to receive program and erase pulses. The LLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the LLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the LLK registers. The LLK bits may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The default value of the LLK bits (assuming erased fuses) would be locked. In the event that blocks are not present (due to configuration or total memory size), the LLK bits will default to locked, and will not be writable. The reset value will always be 1 (independent of the TestFlash block), and register writes will have no effect. In the 72 Kbyte Flash module bits LLK[15:4] are read-only and locked at ‘1’. LLK is not writable unless LME is high. 0: Low Address Space Block is unlocked and can be modified (also if SLL.SLK = 0). 1: Low Address Space Block is locked and cannot be modified.
12.3.9
Secondary Low/mid address space block Locking register (SLL)
Address offset: 0x000C Reset value: 0x00X0_00XX, initially determined by NVSLL, located in test sector
12.3.9.1
Non-volatile Secondary Low/mid address space block Locking reg (NVSLL)
Delivery value: 0xFFFF_FFFF
4 0 r/0 20 SLK11 rw/X 5 0 r/0 21 SLK10 rw/X 6 0 r/0 22 SLK9 rw/X 7 0 r/0 23 SLK8 rw/X 8 0 r/0 24 SLK7 rw/X 9 0 r/0 25 SLK6 rw/X 10 0 r/0 26 SLK5 rw/X 11 STSLK rw/X 27 SLK4 rw/X 12 0 r/0 28 SLK3 rw/X 13 0 r/0 29 SLK2 rw/X 14 0 r/0 30 SLK1 rw/X 15 0 r/0 31 SLK0 rw/X
Address offset: 0x403DF8
0 SLE r/0 16 SLK15 rw/X 1 0 r/0 17 SLK14 rw/X 2 0 r/0 18 SLK13 rw/X 3 0 r/0 19 SLK12 rw/X
Figure 12-29. Non-volatile Secondary Low/mid address space block Locking reg (NVSLL)
The Secondary Low/Mid Address Space Block Locking register provides an alternative means to protect blocks from being modified. These bits, along with bits in the LML register, determine if the block is locked from Program or Erase. An “OR” of LML and SLL determine the final lock status. The SLL register has a related Non-volatile Secondary Low/Mid Address Space Block Locking register located in TestFlash that contains the default reset value for SLL. During the reset phase of the Flash module, the NVSLL register content is read and loaded into the SLL.
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Table 12-48. SLL field descriptions
Field 0 Description SLE: Secondary Low/mid address space block Enable (Read Only) This bit is used to enable the Lock registers (STSLK, SLK15-0) to be set or cleared by registers writes. This bit is a status bit only. The method to set this bit is to write a password, and if the password matches, the SLE bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. For SLE the password 0xC3C33333 must be written to the SLL register. 0: Secondary Low/Mid Address Locks are disabled: STSLK, SLK15-0 cannot be written. 1: Secondary Low/Mid Address Locks are enabled: STSLK, SLK15-0 can be written. Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. STSLK: Secondary Test address space block LocK (Read/Write) This bit is used as an alternate means to lock the block of Test and Shadow Address Space from Program and Erase (Erase is any case forbidden for Test block). A value of 1 in the STSLK register signifies that the Test block is locked for Program and Erase. A value of 0 in the STSLK register signifies that the Test block is available to receive program and erase pulses. The STSLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the STSLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the STSLK register. The STSLK bit may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The default value of the STSLK bit (assuming erased fuses) would be locked. STSLK is not writable unless SLE is high. 0: Test Address Space Block is unlocked and can be modified (also if LML.TSLK = 0). 1: Test Address Space Block is locked and cannot be modified.
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12:15 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. 16:31 SLK[15:0]: Secondary Low address space block locK 15-0 (Read/Write) These bits are used as an alternate means to lock the blocks of Low Address Space from Program and Erase. SLK[3:0] are related to sectors B0F3-0, respectively. SLK[15:4] are not used for this memory cut. A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for Program and Erase. A value of 0 in a bit of the SLK register signifies that the corresponding block is available to receive program and erase pulses. The SLK register is not writable once an interlock write is completed until MCR.DONE is set at the completion of the requested operation. Likewise, the SLK register is not writable if a high voltage operation is suspended. Upon reset, information from the TestFlash block is loaded into the SLK registers. The SLK bits may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The default value of the SLK bits (assuming erased fuses) would be locked. In the event that blocks are not present (due to configuration or total memory size), the SLK bits will default to locked, and will not be writable. The reset value will always be 1 (independent of the TestFlash block), and register writes will have no effect. In the 72 Kbyte Flash module bits SLK[15:4] are read-only and locked at ‘1’. SLK is not writable unless SLE is high. 0: Low Address Space Block is unlocked and can be modified (also if LML.LLK = 0). 1: Low Address Space Block is locked and cannot be modified.
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12.3.10 Low/Mid address space block Select register (LMS)
Address offset: 0x00010
0 0 r/0 16 LSL15 rw/0 1 0 r/0 17 LSL14 rw/0 2 0 r/0 18 LSL13 rw/0 3 0 r/0 19 LSL12 rw/0 4 0 r/0 20 LSL11 rw/0 5 0 r/0 21 LSL10 rw/0 6 0 r/0 22 LSL9 rw/0 7 0 r/0 23 LSL8 rw/0 8 0 r/0 24 LSL7 rw/0 9 0 r/0 25 LSL6 rw/0 10 0 r/0 26 LSL5 rw/0 11 0 r/0 27 LSL4 rw/0
Reset value: 0x0000_0000
12 0 r/0 28 LSL3 rw/0 13 0 r/0 29 LSL2 rw/0 14 0 r/0 30 LSL1 rw/0 15 0 r/0 31 LSL0 rw/0
Figure 12-30. Low/Mid address space block Select register (LMS)
The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on during erase.
Table 12-49. LMS field descriptions
Field 0:15 Description Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
16:31 LSL[15:0]: Low address space block SeLect 15-0 (Read/Write) A value of 1 in the select register signifies that the block is selected for erase. A value of 0 in the select register signifies that the block is not selected for erase. The reset value for the select register is 0, or unselected. LSL[3:0] are related to sectors B0F3-0, respectively. LSL[15:4] are not used for this memory cut. The blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. The select register is not writable once an interlock write is completed or if a high voltage operation is suspended. In the event that blocks are not present (due to configuration or total memory size), the corresponding LSL bits will default to unselected, and will not be writable. The reset value will always be 0, and register writes will have no effect. In the 72 Kbyte Flash module bits LSL[15:4] are read-only and locked at ‘0’. 0: Low Address Space Block is unselected for Erase. 1: Low Address Space Block is selected for Erase.
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12.3.11 Address Register (ADR)
Address offset: 0x00018
0 0 r/0 16 AD15 r/0 1 0 r/0 17 AD14 r/0 2 0 r/0 18 AD13 r/0 3 0 r/0 19 AD12 r/0 4 0 r/0 20 AD11 r/0 5 0 r/0 21 AD10 r/0 6 0 r/0 22 AD9 r/0 7 0 r/0 23 AD8 r/0 8 0 r/0 24 AD7 r/0 9 AD22 r/0 25 AD6 r/0 10 AD21 r/0 26 AD5 r/0 11 AD20 r/0 27 AD4 r/0
Reset value: 0x0000_0000
12 AD19 r/0 28 AD3 r/0 13 AD18 r/0 29 AD2 r/0 14 AD17 r/0 30 0 r/0 15 AD16 r/0 31 0 r/0
Figure 12-31. Address Register (ADR)
The Address Register provides the first failing address in the event module failures (ECC, RWW or FPEC) occur or the first address at which an ECC single error correction occurs.
Table 12-50. ADR field descriptions
Field 0:8 9:29 Description Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. AD[22:2]: ADdress 22-2 (Read Only) The Address Register provides the first failing address in the event of ECC error (MCR.EER set) or the first failing address in the event of RWW error (MCR.RWE set), or the address of a failure that may have occurred in a FPEC operation (MCR.PEG cleared). The Address Register also provides the first address at which an ECC single error correction occurs (MCR.EDC set), if the device is configured to show this feature. The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC error and the ECC single error correction. When accessed ADR will provide the address related to the first event occurred with the highest priority. The priorities between these four possible events is summarized in the Table 12-51. In User Mode the Address Register is read only.
30:31 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0.
Table 12-51. ADR content: priority list
Priority Level 1 2 3 4 Error Flag MCR.EER = 1 MCR.RWE = 1 MCR.PEG = 0 MCR.EDC = 1 ADR content Address of first ECC Double Error Address of first RWW Error Address of first FPEC Error Address of first ECC Single Error Correction
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12.3.12 User Test 0 register (UT0)
Address offset: 0x0003C
0 UTE rw/0 16 0 r/0 1 0 r/0 17 0 r/0 2 0 r/0 18 0 r/0 3 0 r/0 19 0 r/0 4 0 r/0 20 0 r/0 5 0 r/0 21 0 r/0 6 0 r/0 22 0 r/0 7 0 r/0 23 0 r/0 8 0 r/0 24 0 r/0 9 DSI6 rw/0 25 X rw/0 10 DSI5 rw/0 26 MRE rw/0 11 DSI4 rw/0 27 MRV rw/0
Reset value: 0x0000_0001
12 DSI3 rw/0 28 EIE rw/0 13 DSI2 rw/0 29 AIS rw/0 14 DSI1 rw/0 30 AIE rw/0 15 DSI0 rw/0 31 AID r/1
Figure 12-32. User Test 0 register (UT0)
The User Test Registers provide the user with the ability to test features on the Flash module. The User Test 0 Register allows to control the way in which the Flash content check is done. Bits MRE, MRV, AIS, EIE and DSI[6:0] of the User Test 0 Register are not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-52. UT0 field descriptions
Field 0 Description UTE: User Test Enable (Read/Clear) This status bit gives indication when User Test is enabled. All bits in UT0-2 and UMISR0-1 are locked when this bit is 0. This bit is not writeable to a 1, but may be cleared. The reset value is 0. The method to set this bit is to provide a password, and if the password matches, the UTE bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write. For UTE the password 0xF9F99999 must be written to the UT0 register. Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. DSI[6:0]: Data Syndrome Input 6-0 (Read/Write) These bits represent the input of Syndrome bits of ECC logic used in the ECC Logic Check. Bits DSI[6:0] correspond to the 7 syndrome bits on a single word. These bits are not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: The syndrome bit is forced at 0. 1: The syndrome bit is forced at 1.
1:8 9:15
16:24 Reserved (Read Only). Write these bits has no effect and read these bits always outputs 0. 25 Reserved (Read/Write). This bit can be written and its value can be read back, but there is no function associated. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
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Table 12-52. UT0 field descriptions (continued)
Field 26 Description MRE: Margin Read Enable (Read/Write) MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode reads to be replaced by margin reads. Margin reads are only active during Array Integrity Checks; Normal User reads are not affected by MRE. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: Margin reads are not enabled, all reads are User mode reads. 1: Margin reads are enabled. MRV: Margin Read Value (Read/Write) If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an erased level (MRV = 1) or to a programmed level (MRV = 0). This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: Zero’s (programmed) margin reads are requested (if MRE = 1). 1: One’s (erased) margin reads are requested (if MRE = 1). EIE: ECC data Input Enable (Read/Write) EIE enables the ECC Logic Check operation to be done. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: ECC Logic Check is not enabled. 1: ECC Logic Check is enabled. AIS: Array Integrity Sequence (Read/Write) AIS determines the address sequence to be used during array integrity checks. The default sequence (AIS = 0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. This sequence is proprietary. The alternative sequence (AIS = 1) is just logically sequential. Proprietary sequence is forbidden in Margin Read. It should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. This bit is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect. 0: Array Integrity equence is proprietary sequence. 1: Array Integrity sequence is sequential. AIE: Array Integrity Enable (Read/Write) AIE set to ‘1’ starts the Array Integrity Check done on all selected and unlocked blocks. The pattern is selected by AIS, and the MISR (UMISR0-1) can be checked after the operation is complete, to determine if a correct signature is obtained. AIE can be set only if MCR.ERS, MCR.PGM and MCR.EHV are all low. 0: Array Integrity Checks are not enabled. 1: Array Integrity Checks are enabled. AID: Array Integrity Done (Read Only) AID will be cleared upon an Array Integrity Check being enabled (to signify the operation is on-going). Once completed, AID will be set to indicate that the Array Integrity Check is complete. At this time the MISR (UMISR0-1) can be checked. 0: Array Integrity Check is on-going. 1: Array Integrity Check is done.
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12.3.13 User Test 1 register (UT1)
Address offset: 0x00040
0 DAI31 rw/0 16 DAI15 rw/0 1 DAI30 rw/0 17 DAI14 rw/0 2 DAI29 rw/0 18 DAI13 rw/0 3 DAI28 rw/0 19 DAI12 rw/0 4 DAI27 rw/0 20 DAI11 rw/0 5 DAI26 rw/0 21 DAI10 rw/0 6 DAI25 rw/0 22 DAI09 rw/0 7 DAI24 rw/0 23 DAI08 rw/0 8 DAI23 rw/0 24 DAI07 rw/0 9 DAI22 rw/0 25 DAI06 rw/0 10 DAI21 rw/0 26 DAI05 rw/0 11 DAI20 rw/0 27 DAI04 rw/0
Reset value: 0x0000_0000
12 DAI19 rw/0 28 DAI03 rw/0 13 DAI18 rw/0 29 DAI02 rw/0 14 DAI17 rw/0 30 DAI01 rw/0 15 DAI16 rw/0 31 DAI00 rw/0
Figure 12-33. User Test 1 register (UT1)
The User Test 1 Register allows to enable the checks on the ECC logic related to the Word. The User Test 1 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-53. UT1 field descriptions
Field 0:31 Description DAI[31:00]: Data Array Input 31-0 (Read/Write) These bits represent the input of even word of ECC logic used in the ECC Logic Check. Bits DAI[31:00] correspond to the 32 array bits Word. 0: The array bit is forced at 0. 1: The array bit is forced at 1.
12.3.14 User Multiple Input Signature Register 0 (UMISR0)
Address offset: 0x00048
0 1 2 3 4 5 6 7 8 9 10 11
Reset value: 0x0000_0000
12 13 14 15
MS031 MS030 MS029 MS028 MS027 MS026 MS025 MS024 MS023 MS022 MS021 MS020 MS019 MS018 MS017 MS016 rw/0 16 rw/0 17 rw/0 18 rw/0 19 rw/0 20 rw/0 21 rw/0 22 rw/0 23 rw/0 24 rw/0 25 rw/0 26 rw/0 27 rw/0 28 rw/0 29 rw/0 30 rw/0 31
MS015 MS014 MS013 MS012 MS011 MS010 MS009 MS008 MS007 MS006 MS005 MS004 MS003 MS002 MS001 MS000 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 12-34. User Multiple Input Signature Register 0 (UMISR0)
The Multiple Input Signature Register provides a means to evaluate the Array Integrity. The User Multiple Input Signature Register 0 represents the bits 31:0 of the Word. The UMISR0 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
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Table 12-54. UMSIR0 field descriptions
Field 0:31 Description MS[31:00]: Multiple input Signature 31-00 (Read/Write) These bits represent the MISR value obtained accumulating the bits 31:0 of all the pages read from the Flash memory. The MS can be seeded to any value by writing the UMISR0 register.
12.3.15 User Multiple Input Signature Register 1 (UMISR1)
Address offset: 0x0004C
0 1 2 3 4 5 6 7 8 9 10 11
Reset value: 0x0000_0000
12 13 14 15
MS063 MS062 MS061 MS060 MS059 MS058 MS057 MS056 MS055 MS054 MS053 MS052 MS051 MS050 MS049 MS048 rw/0 16 rw/0 17 rw/0 18 rw/0 19 rw/0 20 rw/0 21 rw/0 22 rw/0 23 rw/0 24 rw/0 25 rw/0 26 rw/0 27 rw/0 28 rw/0 29 rw/0 30 rw/0 31
MS047 MS046 MS045 MS044 MS043 MS042 MS041 MS040 MS039 MS038 MS037 MS036 MS035 MS034 MS033 MS032 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 12-35. User Multiple Input Signature Register 1 (UMISR1)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity. The User Multiple Input Signature Register 1 represent the ECC bits of the 32 bits word: bits 6-0 are the ECC bits for the Word; bits 7 and 8 of MISR are respectively the double and single ECC error detection. The UMISR1 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate data while writing has no effect.
Table 12-55. UMISR1 field descriptions
Field 0:31 Description MS[63:32]: Multiple input Signature 63-32 (Read/Write) These bits represents the MISR value obtained accumulating: 7 ECC bits for the Word (on MS38-32); single ECC error detection (on MS42); double ECC error detection (on MS43); The MS can be seeded to any value by writing the UMISR1 register.
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12.3.16 Register map
Table 12-56. Flash 528 KB Single Bank register map
Addres s offset 0x00 Registe r name MCR 0 16 EDC 1 17 0 2 18 0 3 19 0 4 20 0 5 21 SIZE 2 DON E 0 LLK1 0 0 0 0 6 22 SIZE 1 PEG 7 23 SIZE 0 0 8 24 0 9 25 LAS2 10 26 LAS1 11 27 LAS0 12 28 0 13 29 MAS 2 ERS 14 30 MAS 1 ESU S 0 LLK1 15 31 MAS 0 EHV
EER
RWE
0
0
PEA S 0 LLK1 1 0 0 0
0
0
0
PGM
PSU S 0 LLK3
0x04
LML
LME LLK1 5
0 LLK1 4 0 0 0
0 LLK1 3 0 0 0
0 LLK1 2 0 0 0
0 LLK9
0 LLK8
0 LLK7
0 LLK6
0 LLK5
TSLK LLK4
0 LLK2
0 LLK0
0x08
Res.
0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 ST SLK SLK4
0 0 0
0 0 0
0 0 0
0 0 0
0x0C
SLL
SLE
SLK1 5 0x10 LMS 0 LSL1 5 0x14 Res. 0 0 0x18 ADR 0 AD15 0x3C UT0 UTE 0 0x40 UT1 DAI3 1 DAI1 5 0x44 Res. 0 0 0x48
SLK1 4 0 LSL1 4 0 0 0 AD14 0 0 DAI3 0 DAI1 4 0 0
SLK1 3 0 LSL1 3 0 0 0 AD13 0 0 DAI2 9 DAI1 3 0 0
SLK1 2 0 LSL1 2 0 0 0 AD12 0 0 DAI2 8 DAI1 2 0 0
SLK1 1 0 LSL1 1 0 0 0 AD11 0 0 DAI2 7 DAI1 1 0 0
SLK1 0 0 LSL1 0 0 0 0 AD10 0 0 DAI2 6 DAI1 0 0 0
SLK9
SLK8
SLK7
SLK6
SLK5
SLK3
SLK2
SLK1
SLK0
0 LSL9
0 LSL8
0 LSL7
0 LSL6
0 LSL5
0 LSL4
0 LSL3
0 LSL2
0 LSL1
0 LSL0
0 0 0 AD9 0 0 DAI2 5 DAI0 9 0 0
0 0 0 AD8 0 0 DAI2 4 DAI0 8 0 0
0 0 0 AD7 0 0 DAI2 3 DAI0 7 0 0
0 0 AD22 AD6 DSI6 X DAI2 2 DAI0 6 0 0
0 0 AD21 AD5 DSI5 MRE DAI2 1 DAI0 5 0 0
0 0 AD20 AD4 DSI4 MRV DAI2 0 DAI0 4 0 0
0 0 AD19 AD3 DSI3 EIE DAI1 9 DAI0 3 0 0
0 0 AD18 AD2 DSI2 AIS DAI1 8 DAI0 2 0 0
0 0 AD17 0 DSI1 AIE DAI1 7 DAI0 1 0 0
0 0 AD16 0 DSI0 AID DAI1 6 DAI0 0 0 0
UMISR0 MS31 MS30 MS29 MS28 MS27 MS26 MS25 MS24 MS23 MS22 MS21 MS20 MS19 MS18 MS17 MS16 MS15 MS14 MS13 MS12 MS11 MS10 MS09 MS08 MS07 MS06 MS05 MS04 MS03 MS02 MS01 MS00
0x4C
UMISR1 MS63 MS62 MS61 MS60 MS59 MS58 MS57 MS56 MS55 MS54 MS53 MS52 MS51 MS50 MS49 MS48 MS47 MS46 MS45 MS44 MS43 MS42 MS41 MS40 MS39 MS38 MS37 MS36 MS35 MS34 MS33 MS32
12.3.17 Programming considerations
12.3.17.1 Modify operation
All modify operations of the Flash module are managed through the Flash User Registers Interface.
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All the sectors of the Flash module belong to the same partition (Bank), therefore when a Modify operation is active on some sectors no read access is possible on any other sector (Read-While-Write is not supported). During a Flash modify operation any attempt to read any Flash location will output invalid data and bit RWE of the MCR will be automatically set. This means that the Flash module is not fetchable when a modify operation is active: Modify operation commands must be executed from another memory (internal SRAM or external memory). If during a Modify Operation a reset occurs, the operation is suddenly terminated and the Macrocell is reset to Read Mode. The data integrity of the Flash section where the Modify Operation has been terminated is not guaranteed: the interrupted Flash Modify Operation must be repeated. In general each modify operation is started through a sequence of three steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in MCR (PGM or ERS) or UT0 (MRE or EIE). 2. The second step is the definition of the operands: the Address and the Data for programming or the Sectors for erase or margin read. 3. The third instruction is used to start the modify operation, by setting EHV in MCR or AIE in UT0. Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. A summary of the available Flash modify operations is shown in the Table 12-36.
Table 12-57. Flash modify operations
Operation Double word program Sector erase Array integrity check Margin read ECC logic check Select bit MCR.PGM MCR.ERS None UT0.MRE UT0.EIE Operands Address and data by interlock writes LMS LMS UT0.MRV + LMS UT0.DSI, UT1, UT2 Start bit MCR.EHV MCR.EHV UT0.AIE UT0.AIE UT0.AIE
Once bit MCR.EHV (or UT0.AIE) is set, all the operands can no more be modified until bit MCR.DONE (or UT0.AID) is high. In general each modify operation is completed through a sequence of four steps: 1. Wait for operation completion: wait for bit MCR.DONE (or UT0.AID) to go high. 2. Check operation result: check bit MCR.PEG (or compare UMISR0-1 with expected value). 3. Switch off FPEC by resetting MCR.EHV (or UT0.AIE). 4. Deselect current operation by clearing MCR.PGM/ERS (or UT0.MRE/EIE). If the device embeds more than one Flash module and a modify operation is on-going on one of them, then it is forbidden to start any other modify operation on the other Flash modules. In the following all the possible modify operations are described and some examples of the sequences needed to activate them are presented.
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12.3.17.2 Word program
A Flash program sequence operates on any Word within the Flash core. Whenever you program, ECC bits also get programmed (unless the selected address belongs to a sector in which the ECC has been disabled in order to allow bit manipulation). ECC is handled on a 32 bit boundary. Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot change a stored logic 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. The user may program the values in any words with a single program sequence. The Program operation consists of the following sequence of events: 1. Change the value in the MCR.PGM bit from 0 to 1. 2. Ensure the block that contains the address to be programmed is unlocked. Write the first address to be programmed with the program data. The Flash module latches address bits (22:2) at this time. The Flash module latches data written as well. This write is referred to as a program data interlock write. An interlock is at 32 bits. 3. Write a logic 1 to the MCR.EHV bit to start the internal program sequence or skip to step 9 to terminate. 4. Wait until the MCR.DONE bit goes high. 5. Confirm MCR.PEG = 1. 6. Write a logic 0 to the MCR.EHV bit. 7. If more addresses are to be programmed, return to step 2. 8. Write a logic 0 to the MCR.PGM bit to terminate the program operation. Program may be initiated with the 0 to 1 transition of the MCR.PGM bit or by clearing the MCR.EHV bit at the end of a previous program. The first write after a program is initiated determines the page address to be programmed. This first write is referred to as an interlock write. The interlock write determines if the test or normal array space will be programmed by causing MCR.PEAS to be set/cleared. An interlock write must be performed before setting MCR.EHV. The user may terminate a program sequence by clearing MCR.PGM prior to setting MCR.EHV. After the interlock write, additional writes only affect the data to be programmed in the word . If multiple writes are done to the same location the data for the last write is used in programming. While MCR.DONE is low and MCR.EHV is high, the user may clear EHV, resulting in a program abort. A Program abort forces the module to step 8 of the program sequence. An aborted program will result in MCR.PEG being set low, indicating a failed operation. MCR.DONE must be checked to know when the aborting command has completed. The data space being operated on before the abort will contain indeterminate data. This may be recovered by repeating the same program instruction or executing an erase of the affected blocks.
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Example 12-8. Double word program of data 0x55AA55AA at address 0x00AAA8
MCR = 0x00000010; (0x00AAA8) = 0x55AA55AA; MCR = 0x00000011; do { tmp = MCR; } while ( !(tmp & 0x00000400) ); status = MCR & 0x00000200; MCR = 0x00000010; MCR = 0x00000000; /* /* /* /* /* Set PGM in MCR: Select Operation */ Latch 32 data */ Set EHV in MCR: Operation Start */ Loop to wait for DONE=1 */ Read MCR */
/* Check PEG flag */ /* Reset EHV in MCR: Operation End */ /* Reset PGM in MCR: Deselect Operation */
12.3.17.3 Sector erase
Erase changes the value stored in all bits of the selected block(s) to logic 1. An erase sequence operates on any combination of blocks (sectors). The test block cannot be erased. The erase sequence is fully automated within the Flash. The user only needs to select the blocks to be erased and initiate the erase sequence. Locked/disabled blocks cannot be erased. If multiple blocks are selected for erase during an erase sequence, no specific operation order must be assumed. The erase operation consists of the following sequence of events: 1. Change the value in the MCR.ERS bit from 0 to 1. 2. Select the block(s) to be erased by writing ‘1’s to the appropriate register(s) in LMS register. Note that Lock and Select are independent. If a block is selected and locked, no erase will occur. 3. Write to any address in Flash. This is referred to as an erase interlock write. 4. Write a logic 1 to the MCR.EHV bit to start the internal erase sequence or skip to step 9 to terminate. 5. Wait until the MCR.DONE bit goes high. 6. Confirm MCR.PEG = 1. 7. Write a logic 0 to the MCR.EHV bit. 8. If more blocks are to be erased, return to step 2. 9. Write a logic 0 to the MCR.ERS bit to terminate the erase operation. After setting MCR.ERS, one write, referred to as an interlock write, must be performed before MCR.EHV can be set to ‘1’. Data words written during erase sequence interlock writes are ignored. The user may terminate the erase sequence by clearing ERS before setting EHV. An erase operation may be aborted by clearing MCR.EHV assuming MCR.DONE is low, MCR.EHV is high and MCR.ESUS is low. An erase abort forces the module to step 8 of the erase sequence. An aborted erase will result in MCR.PEG being set low, indicating a failed operation. MCR.DONE must be checked to know when the aborting command has completed.
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The block(s) being operated on before the abort contain indeterminate data. This may be recovered by executing an erase on the affected blocks. The user may not abort an erase sequence while in erase suspend.
Example 12-9. Erase of sectors B0F1 and B0F2
MCR = 0x00000004; LMS = 0x00000006; (0x000000) = 0xFFFFFFFF; MCR = 0x00000005; do { tmp = MCR; } while ( !(tmp & 0x00000400) ); status = MCR & 0x00000200; MCR = 0x00000004; MCR = 0x00000000; /* /* /* /* /* /* Set ERS in MCR: Select Operation */ Set LSL2-1 in LMS: Select Sectors to erase */ Latch a Flash Address with any data */ Set EHV in MCR: Operation Start */ Loop to wait for DONE=1 */ Read MCR */
/* Check PEG flag */ /* Reset EHV in MCR: Operation End */ /* Reset ERS in MCR: Deselect Operation */
12.3.17.3.1 Erase suspend/resume The erase sequence may be suspended to allow read access to the Flash core. It is not possible to program or to erase during an erase suspend. During erase suspend, all reads to blocks targeted for erase return indeterminate data. An erase suspend can be initiated by changing the value of the MCR.ESUS bit from 0 to 1. MCR.ESUS can be set to ‘1’ at any time when MCR.ERS and MCR.EHV are high and MCR.PGM is low. A 0 to 1 transition of MCR.ESUS causes the module to start the sequence which places it in erase suspend. The user must wait until MCR.DONE = 1 before the module is suspended and further actions are attempted. MCR.DONE will go high no more than tESUS after MCR.ESUS is set to ‘1’. Once suspended, the array may be read. Flash core reads while MCR.ESUS = 1 from the block(s) being erased return indeterminate data.
Example 12-10. Sector erase suspend
MCR = 0x00000007; do { tmp = MCR; } while ( !(tmp & 0x00000400) ); /* Set ESUS in MCR: Erase Suspend */ /* Loop to wait for DONE=1 */ /* Read MCR */
Notice that there is no need to clear MCR.EHV and MCR.ERS in order to perform reads during erase suspend. The erase sequence is resumed by writing a logic 0 to MCR.ESUS. MCR.EHV must be set to ‘1’ before MCR.ESUS can be cleared to resume the operation. The module continues the erase sequence from one of a set of predefined points. This may extend the time required for the erase operation.
Example 12-11. Sector erase resume
MCR = 0x00000005; /* Reset ESUS in MCR: Erase Resume */
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12.3.17.4 User Test Mode
The user can perform specific tests to check Flash module integrity by putting the Flash module in User Test Mode. Three kinds of test can be performed: • Array Integrity Self Check • Margin Read • ECC Logic Check The User Test Mode is equivalent to a Modify operation: read accesses attempted by the user during User Test Mode generates a Read-While-Write Error (RWE of MCR set). It is not allowed to perform User Test operations on the Test blocks. 12.3.17.4.1 Array integrity self check Array integrity is checked using a predefined address sequence (proprietary), and this operation is executed on selected and unlocked blocks. Once the operation is completed, the results of the reads can be checked by reading the MISR value (stored in UMISR0-1), to determine if an incorrect read, or ECC detection was noted. The internal MISR calculator is a 32-bit register. The 32 bit data, the 7 ECC data and the single and double ECC errors of the Word are therefore captured by the MISR through two different read accesses at the same location. The whole check is done through two complete scans of the memory address space: 1. The first pass will scan only bits 31:0 of each word. 2. The second pass will scan only the ECC bits (7) and the single and double ECC errors (1 + 1) of each word. The 32 bit data and the 7 ECC data are sampled before the eventual ECC correction, while the single and double error flags are sampled after the ECC evaluation. Only data from existing and unlocked locations are captured by the MISR. The MISR can be seeded to any value by writing the UMISR0–1 registers. The Array Integrity Self Check consists of the following sequence of events: 1. Set UTE in UT0 by writing the related password in UT0. 2. Select the block(s) to be checked by writing ‘1’s to the appropriate register(s) in LMS register. Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity Check will occur. 3. Set eventually UT0.AIS bit for a sequential addressing only. 4. Clear (or insert seed) UMISR0-1 5. Write a logic 1 to the UT0.AIE bit to start the Array Integrity Check. 6. Wait until the UT0.AID bit goes high.
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7. Compare UMISR0-1 content with the expected result. 8. Write a logic 0 to the UT0.AIE bit. 9. If more blocks are to be checked, return to step 2. 10. Clear UT0 writing UT0.UTE to ‘0’ It is recommended to leave UT0.AIS at 0 and use the proprietary address sequence that checks the read path more fully, although this sequence takes more time. During the execution of the Array Integrity Check operation it is forbidden to modify the content of Block Select (LMS) and Lock (LML, SLL) registers, otherwise the MISR value can vary in an unpredictable way. While UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Array Integrity Check abort. UT0.AID must be checked to know when the aborting command has completed.
Example 12-12. Array integrity check of sectors B0F1 and B0F2
UT0 = 0xF9F99999; LMS = 0x00000006; UT0 = 0x80000002; do { tmp = UT0; } while ( !(tmp & 0x00000001) ); data0 = UMISR0; data1 = UMISR1; UT0 = 0x00000000; /* /* /* /* /* Set UTE in UT0: Enable User Test */ Set LSL2-1 in LMS: Select Sectors */ Set AIE in UT0: Operation Start */ Loop to wait for AID=1 */ Read UT0 */
/* Read UMISR0 content*/ /* Read UMISR1 content*/ /* Reset UTE and AIE in UT0: Operation End */
12.3.17.4.2 Margin read Margin read procedure (either Margin 0 or Margin 1), can be run on unlocked blocks in order to unbalance the Sense Amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin vs ‘0’ (UT0.MRV = ‘0’) or vs ‘1’ (UT0.MRV = ‘1’). Locked sectors are ignored by MISR calculation and ECC flagging. The results of the margin reads can be checked comparing checksum value in UMISR0-1. Since Margin reads are done at voltages that differ than the normal read voltage, lifetime expectancy of the Flash macrocell is impacted by the execution of Margin reads. Doing Margin reads repetitively results in degradation of the Flash Array, and shorten expected lifetime experienced at normal read levels. For these reasons the Margin Read usage is allowed only in Factory, while it is forbidden to use it inside the User Application. In any case the charge losses detected through the Margin Read cannot be considered failures of the device and no Failure Analysis will be opened on them. The Margin Read Setup operation consists of the following sequence of events: 1. Set UTE in UT0 by writing the related password in UT0. 2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS or HBS registers. Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity Check will occur. 3. Set UT0.AIS bit for a sequential addressing only. 4. Change the value in the UT0.MRE bit from 0 to 1. 5. Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
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6. Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate. 7. Wait until the UT0.AID bit goes high. 8. Compare UMISR0-1 content with the expected result. 9. Write a logic 0 to the UT0.AIE, UT0.MRE and UT0.MRV bits. 10. If more blocks are to be checked, return to step 2. It is madatory to leave UT0.AIS at 1 and use the linear address sequence, the proprietary sequence is forbidden in Margin Read. During the execution of the Margin Read operation it is forbidden to modify the content of Block Select (LMS) and Lock (LML, SLL) registers, otherwise the MISR value can vary in an unpredictable way. The read accesses will be done with the addition of a proper number of Wait States to guarantee the correctness of the result. While UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Array Integrity Check abort. UT0.AID must be checked to know when the aborting command has completed.
Example 12-13. Margin read setup versus ‘1’s
UT0 = 0xF9F99999; UT0 = 0x80000020; UT0 = 0x80000030; UT0 = 0x80000032; do { tmp = UT0; } while ( !(tmp & 0x00000001) ); UT0 = 0x80000030; UT0 = 0x00000000; /* /* /* /* /* /* Set UTE in UT0: Enable User Test */ Set MRE in UT0: Select Operation */ Set MRV in UT0: Select Margin versus 1’s */ Set AIE in UT0: Operation Start */ Loop to wait for AID=1 */ Read UT0 */
/* Reset AIE in UT0: Operation End */ /* Reset UTE, MRE, MRV in UT0: Deselect Operation */
12.3.17.4.3 ECC logic check ECC logic can be checked by forcing the input of ECC logic: The 32 bits of data and the 7 bits of ECC syndrome can be individually forced and they will drive simultaneously at the same value the ECC logic of the word. The results of the ECC Logic Check can be verified by reading the MISR value. The ECC Logic Check operation consists of the following sequence of events: 1. Set UTE in UT0 by writing the related password in UT0. 2. Write in UT1.DAI[31:0] Word Input value. 3. Write in UT0.DSI[6:0] the Syndrome Input value. 4. Select the ECC Logic Check: write a logic 1 to the UT0.EIE bit. 5. Write a logic 1 to the UT0.AIE bit to start the ECC Logic Check. 6. Wait until the UT0.AID bit goes high. 7. Compare UMISR0-1 content with the expected result. 8. Write a logic 0 to the UT0.AIE bit.
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Notice that when UT0.AID is low UMISR0-1, UT1 and bits MRE, MRV, EIE, AIS and DSI[6:0] of UT0 are not accessible: reading returns indeterminate data and write has no effect.
Example 12-14. ECC logic check
UT0 = 0xF9F99999; UT1 = 0x55555555; UT0 = 0x80FF0000; UT0 = 0x80FF0008; UT0 = 0x80FF000A; do { tmp = UT0; } while ( !(tmp & 0x00000001) ); data0 = UMISR0; UT0 = 0x00000000; /* /* /* /* /* /* /* Set UTE in UT0: Enable User Test */ Set DAI31-0 in UT1: Even Word Input Data */ Set DSI6-0 in UT0: Syndrome Input Data */ Set EIE in UT0: Select ECC Logic Check */ Set AIE in UT0: Operation Start */ Loop to wait for AID=1 */ Read UT0 */
/* Read UMISR0 content (expected 0x55555555) */ /* Reset UTE, AIE and EIE in UT0: Operation End */
12.3.18 Error correction code
The Flash module provides a method to improve the reliability of the data stored in Flash: the usage of an Error Correction Code. The word size is fixed at 32 bits. At each Word of 32 bits there are associated 7 ECC bits that are programmed in such a way to guarantee a Single Error Correction and a Double Error Detection (SEC-DED). ECC circuitry provides correction of single bit faults and is used to achieve automotive reliability targets. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability.
12.3.18.1 ECC algorithms
The Flash module supports one ECC Algorithm: “All ‘1’s No Error”. A modified Hamming code is used that ensures the all erased state (that is, 0xFFFF.....FFFF) data is a valid state, and will not cause an ECC error. This allows the user to perform a blank check after a sector erase operation.
12.3.19 Protection strategy
Two kinds of protection are available: Modify Protection to avoid unwanted program/erase in Flash sectors and Censored Mode to avoid piracy must be managed by the associated Code Flash module embedded in the same SoC.
12.3.19.1 Modify protection
The Flash Modify Protection information is stored in non-volatile Flash cells located in the TestFlash. This information is read once during the Flash initialization phase following the exiting from Reset and is stored in volatile registers that act as actuators. The reset state of all the Volatile Modify Protection Registers is the protected state. All the non-volatile Modify Protection registers can be programmed through a normal Word Program operation at the related locations in TestFlash.
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The non-volatile Modify Protection registers cannot be erased. • The non-volatile Modify Protection Registers are physically located in TestFlash their bits can be programmed to ‘0’ only once and they can no more be restored to ‘1’. • The Volatile Modify Protection Registers are Read/Write registers which bits can be written at ‘0’ or ‘1’ by the user application. A software mechanism is provided to independently lock/unlock each Low and MidAddress Space Block against program and erase. Software locking is done through the LML (Low/Mid Address Space Block Lock Register) register. An alternate means to enable software locking for blocks of Low Address Space only is through the SLL (Secondary Low/Mid Address Space Block Lock Register). All these registers have a non-volatile image stored in TestFlash (NVLML, NVSLL), so that the locking information is kept on reset. On delivery the TestFlash non-volatile image is at all ‘1’s, meaning all sectors are locked. By programming the non-volatile locations in TestFlash the selected sectors can be unlocked. Being the TestFlash One-Time Programmable (that is, not erasable), once unlocked the sectors cannot be locked again. Of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the user application can lock and unlock sectors when desired.
12.4
12.4.1
Platform Flash controller
Introduction
This section provides an introduction of the Platform Flash Controller for Reduced Product Platforms (RPP). The Platform Flash Controller acts as the interface between the system bus (AHB-Lite 2.v6) and up to two banks of integrated Flash memory arrays (Program and Data). It intelligently converts the protocols between the system bus and the dedicated Flash array interfaces. A block diagram of the e200z0h Power Architecture reduced product platform (RPP) reference design is shown below in Figure 12-36 with the Platform Flash Controller module and its attached off-platform Flash memory arrays highlighted.
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e200z0h Core
Branch Unit Load/Store Unit I-Fetcher Dispatch Debug Nexus1, GPR Integer Nexus2+ Unit AHB BIU p_i_h*
RPP_Z0H_REF
p_d_h*
MemArray Bank1 Flash Regs
m0 m1
s0
PFlash
MemArray Bank0 Flash Regs
XBAR MPU
m3 m2 s2 s7
PRAM
MemArray
IPS/APB
IPS Bus IPS+APB Bus
STM
IPS+APB Slave Modules
Off-Platform IRQs
On-platform IRQs
SWT
INTC
ECSM
Figure 12-36. Power Architecture e200z0h RPP reference platform block diagram
The module list includes: • Power Architecture e200z0h(Harvard) core with Nexus1 or optional Nexus2+ debug • AHB crossbar switch “lite” (XBAR) • Memory Protection Unit (MPU) • Platform Flash memory controller with connections to 2 memory banks • Platform SRAM memory controller (PRAM) • AHB-to-IPS/APB bus controller (PBRIDGE) for access to on- and off-platform slave modules • Interrupt Controller (INTC) • 4-channel System Timers (STM) • Software Watchdog Timer (SWT) • Error Correction Status Module (ECSM)
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Chapter 12 Flash memory
Throughout this document, several important terms are used to describe the Platform Flash Controller module and its connections. These terms are defined here: • Port — This is used to describe the AMBA-AHB connection(s) into the Platform Flash Controller. From an architectural and programming model viewpoint, the definition supports up to two AHB ports, even though this specific controller only supports a single AHB connection. • Bank — This term is used to describe the attached Flash memories. From the Platform Flash Controller’s perspective, there may be one or two attached banks of Flash memory. The “code Flash” is required and always attached to bank0. Additionally, there is a “data Flash” attached to bank1. The Platform Flash Controller interface supports two separate connections, one to each memory bank. • Array — Within each memory bank, there is one Flash array instantiations. Recall the maximum capacity of the array is 512 Kbytes. • Page — This value defines the number of bits read from the Flash array in a single access. For this controller and memory, the page size is 128 bits (16 bytes). The nomenclature “page buffers and “line buffers” are used interchangeably.
12.4.1.1
Overview
The Platform Flash Controller supports a 32-bit data bus width at the AHB port and connections to 128-bit read data interfaces from two memory banks, where each bank contains one instantiations of the Flash memory array. One Flash bank is connected to the code Flash memory and the other bank is connected to the optional data Flash memory. The memory controller capabilities vary between the two banks with each bank’s functionality optimized with the typical use cases associated with the attached Flash memory. As an example, the Platform Flash Controller logic associated with the code Flash bank contains a four-entry “page” buffer, each entry containing 128 bits of data (1 Flash page) plus an associated controller which prefetches sequential lines of data from the Flash array into the buffer, while the controller logic associated with the data Flash bank only supports a 128-bit register which serves as a temporary page holding register and does not support any prefetching. Prefetch buffer hits from the code Flash bank support zero-wait AHB data phase responses. AHB read requests which miss the buffers generate the needed Flash array access and are forwarded to the AHB upon completion, typically incurring two wait-states at an operating frequency of 60–64 MHz. This memory controller is optimized for applications where a cacheless processor core, e.g., the Power e200z0h, is connected through the platform to on-chip memories, e.g., Flash and SRAM, where the processor and platform operate at the same frequency. For these applications, the 2-stage pipeline AMBA-AHB system bus is effectively mapped directly into stages of the processor’s pipeline and zero wait-state responses for most memory accesses are critical for providing the required level of system performance.
12.4.1.2
Features
The following list summarizes the key features of the Platform Flash Controller: • Dual array interfaces support up to a total of 16 Mbytes of Flash memory, partitioned as two separate 8 Mbyte banks
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• • •
•
•
• • • •
Single AHB port interface supports a 32-bit data bus. All AHB aligned and unaligned reads within the 32-bit container are supported. Only aligned word writes are supported. Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank Interface with code Flash (bank0) provides configurable read buffering and page prefetch support. Four page read buffers (each 128 bits wide) and a prefetch controller are used to support single-cycle read responses (zero AHB data phase wait-states) for hits in the buffers. The buffers implement a least-recently-used replacement algorithm to maximize performance. Interface with optional data Flash (bank1) includes a 128-bit register to temporarily hold a single Flash page. This logic supports single-cycle read responses (zero AHB data phase wait-states) for accesses that hit in the holding register. There is no support for prefetching associated with this bank. Programmable response for read-while-write sequences including support for stall-while-write, optional stall notification interrupt, optional Flash operation abort, and optional abort notification interrupt Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies Support of address-based read access timing for emulation of other memory types Support for reporting of single- and multi-bit Flash ECC events Typical operating configuration loaded into programming model by system reset
12.4.2
Modes of operation
The Platform Flash Controller module does not support any special modes of operation. Its operation is driven from the AMBA-AHB memory references it receives from the platform’s bus masters. Its configuration is defined by the setting of the programming model registers, physically located as part of the Flash array modules.
12.4.3
External signal descriptions
The Platform Flash Controller does not directly interface with any external signals. As shown in Figure 12-36, its primary internal interfaces include a connection to an AMBA-AHB crossbar (or memory protection unit) slave port and connections with up to two banks (code and data) of Flash memory, each containing one instantiation of the Flash array. Additionally, the operating configuration for the Platform Flash Controller is defined by the contents of certain code Flash array0 registers which are inputs to the module.
12.4.4
Memory map and register description
Two memory maps are associated with the Platform Flash Controller: one for the Flash memory space and another for the program-visible control and configuration registers. The Flash memory space is accessed via the AMBA-AHB port and the program-visible registers are accessed via the slave peripheral bus. Details on both memory spaces are provided in Section 12.4.4.1, “Memory map”.
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Chapter 12 Flash memory
There are no program-visible registers that physically reside inside the Platform Flash Controller. Rather, the Platform Flash Controller receives control and configuration information from the Flash array controller(s) to determine the operating configuration. These are part of the Flash array’s configuration registers mapped into its slave peripheral (IPS) address space but are described here.
12.4.4.1
Memory map
First, consider the Flash memory space accessed via transactions from the Platform Flash Controller’s AHB port. To support the two separate Flash memory banks, each up to 8 Mbytes in size, the Platform Flash Controller uses address bit 23 (haddr[23]) to steer the access to the appropriate memory bank. In addition to the actual Flash memory regions, the system memory map includes shadow and test sectors. The program-visible control and configuration registers associated with each memory array are included in the slave peripheral address region. The system memory map defines one code Flash array and one data Flash array. See Table 12-58.
Table 12-58. Flash-related regions in the system memory map
Start address 0x0000_0000 0x0008_0000 0x0020_0000 0x0028_0000 0x0040_0000 0x0048_0000 0x0080_0000 0x0088_0000 0x00A0_0000 0x00A8_0000 0x00C0_0000 0x00C8_0000 0x0100_0000 0xFFE8_8000 0xFFE8_C000 0xFFEB_0000
1
End address 0x0007_FFFF 0x001F_FFFF 0x0027_FFFF 0x002F_FFFF 0x0047_FFFF 0x007F_FFFF 0x0087_FFFF 0x009F_FFFF 0x00A7_FFFF 0x00BF_FFFF 0x00C7_FFFF 0x00FF_FFFF 0x1FFF_FFFF 0xFFE8_BFFF 0xFFE8_FFFF 0xFFEB_BFFF
Size [Kbytes] 512 1536 512 1536 512 3584 512 1536 512 1536 512 3584 507904 16 16 48 Code Flash array 0 Reserved
Region
Code Flash array 0: shadow sector Reserved Code Flash array 0: test sector Reserved Data Flash array 0 Reserved Data Flash array 0: shadow sector Reserved Data Flash array 0: test sector Reserved Emulation mapping Code Flash array 0 configuration1 Data Flash array 0 configuration1 Reserved
This region is also aliased to address 0xC3F8_nnnn.
For additional information on the address-based read access timing for emulation of other memory types, see Section 12.5.12, “Wait-state emulation”. Next, consider the memory map associated with the control and configuration registers.
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Chapter 12 Flash memory
There are multiple registers that control operation of the Platform Flash Controller. These registers are generically defined as “Bus Interface Unit n (BIU n) Register” in the Flash array documentation, where n = 0,1,2,3 and are to be only referenced with 32-bit accesses. Note the first two Flash array registers (BIU0, BIU1) are reset to an SoC-defined value, while the remaining two array registers (BIU2, BIU3) are loaded at reset from specific locations in the array’s shadow region. Regardless of the number of populated banks or the number of Flash arrays included in a given bank, the configuration of the Platform Flash Controller is wholly specified by the BIU registers associated with code Flash array 0. The code array0 register settings define the operating behavior of both Flash banks; it is recommended that the BIU registers for all physically-present arrays be set to the array0 values. NOTE To perform program and erase operations, the control registers in the actual referenced Flash array must be programmed, but the configuration of the Platform Flash Controller module is defined by the BIUn registers of code array0. The 32-bit memory map for the Platform Flash Controller control registers is shown in Table 12-59.
Table 12-59. Platform Flash Controller 32-bit memory map
Address Register Access R/W R/W R/W Reset value 0x18C7_80ED 0x18C7_8081 0xFFFF_FFFF Location on page 364 on page 369 on page 371
0xFFE8_8000 Platform Flash Configuration Register 0 (PFCR0) + 0x01C 0xFFE8_8000 Platform Flash Configuration Register 1 (PFCR1) + 0x020 0xFFE8_8000 Platform Flash Access Protection Register (PFAPR) + 0x024
Please, refer to the MPC5602D data sheet for detailed settings for different values of frequency.
12.4.4.2
Register description
This section details the individual registers of the Platform Flash Controller. 12.4.4.2.1 Platform Flash Configuration Register 0 (PFCR0)
This register defines the configuration associated with Flash memory bank0. This corresponds to the “code Flash”. It includes fields that provide specific information for up to two separate AHB ports (p0 and the optional p1). For the Platform Flash Controller module, the fields associated with AHB port p1 are ignored. The register is described below in Table 12-37 and Table 12-60.
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Offset 0x01c
0 1 2 3 4 5 6 7 8 9 10 11 12
Access: Read/write
13 14 15
BK0_R WWC
R W Reset 0
16
BK0_APC 0
17
BK0_WWSC 1
19
BK0_RWSC 1
25
0
18
1
20
0
21
0
22
0
23
1
24
0
26
0
27
0
28
1
29
1
30
1
31
B0_P1_DPFE
B0_P1_IPFE
B0_P0_IPFE
BK0_RWWC
BK0_RWWC
B0_P1_BFE
W
B0_P1_ BCFG
B0_P1_ PFLM
B0_P0_ BCFG
B0_P0_ PFLM
Reset
1
0
0
0
0
0
0
0
1
1
1
0
1
1
0
Figure 12-37. PFlash Configuration Register 0 (PFCR0) Table 12-60. PFCR0 field descriptions
Field 0-4 BK0_APC Description Bank0 Address Pipelining Control This field is used to control the number of cycles between Flash array access requests. This field must be set to a value appropriate to the operating frequency of the PFlash. The required settings are documented in the device data sheet. Higher operating frequencies require non-zero settings for this field for proper Flash operation. This field is set to 0b00010 by hardware reset. 00000: Accesses may be initiated on consecutive (back-to-back) cycles 00001: Access requests require one additional hold cycle 00010: Access requests require two additional hold cycles ... 11110: Access requests require 30 additional hold cycles 11111: Access requests require 31 additional hold cycles 5-9 BK0_WWSC Bank0 Write Wait-State Control This field is used to control the number of wait-states to be added to the Flash array access time for writes. This field must be set to a value appropriate to the operating frequency of the PFlash. The required settings are documented in the device data sheet. Higher operating frequencies require non-zero settings for this field for proper Flash operation. This field is set to an appropriate value by hardware reset. This field is set to 0b00010 by hardware reset. 00000: No additional wait-states are added 00001: One additional wait-state is added 00010: Two additional wait-states are added ... 11111: 31 additional wait-states are added
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R
B0_P0_DPFE
Chapter 12 Flash memory
Table 12-60. PFCR0 field descriptions (continued)
Field 10-14 BK0_RWSC Description Bank0 Read Wait-State Control This field is used to control the number of wait-states to be added to the Flash array access time for reads. This field must be set to a value corresponding to the operating frequency of the PFlash and the actual read access time of the PFlash. The required settings are documented in the device datasheet. This field is set to 0b00010 by hardware reset. 00000: No additional wait-states are added 00001: One additional wait-state is added 00010: Two additional wait-states are added ... 11111: 31 additional wait-states are added 15-16,24 BK0_RWWC Bank0 Read-While-Write Control This 3-bit field defines the controller response to Flash reads while the array is busy with a program (write) or erase operation. 0––: Terminate any attempted read while write/erase with an error response 111: Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable the abort + abort notification interrupt 110: Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable the abort + abort notification interrupt 101: Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100: Generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. 17-18 Bank0, Port 1 Page Buffer Configuration B0_P1_BCFG This field controls the configuration of the four page buffers in the PFlash controller. The buffers can be organized as a “pool” of available resources, or with a fixed partition between instruction and data buffers. If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and the just-fetched entry then marked as most-recently-used. If the Flash access is for the next-sequential line, the buffer is not marked as most-recently-used until the given address produces a buffer hit. 00: All four buffers are available for any Flash access, that is, there is no partitioning of the buffers based on the access type. 01: Reserved 10: The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11: The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. This field is ignored in the Platform Flash Controller implementation.
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Table 12-60. PFCR0 field descriptions (continued)
Field Description
19 Bank0, Port 1 Data Prefetch Enable B0_P1_DPFE This field enables or disables prefetching initiated by a data read access. This field is set by hardware reset. 0: No prefetching is triggered by a data read access 1: If page buffers are enabled (B0_P1_BFE = 1), prefetching is triggered by any data read access This field is ignored in the Platform Flash Controller implementation. 20 B0_P1_IPFE Bank0, Port 1 Instruction Prefetch Enable This field enables or disables prefetching initiated by an instruction fetch read access. This field is cleared by hardware reset. 0: No prefetching is triggered by an instruction fetch read access 1: If page buffers are enabled (B0_P1_BFE = 1), prefetching is triggered by any instruction fetch read access This field is ignored in the Platform Flash Controller implementation. 21-22 Bank0, Port 1 Prefetch Limit B0_P1_PFLM This field controls the prefetch algorithm used by the PFlash controller. This field defines the prefetch behavior. In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is set to 2b01 by hardware reset. 00: No prefetching is performed. 01: The referenced line is prefetched on a buffer miss, that is, prefetch on miss. 1–: The referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit. This field is ignored in the Platform Flash Controller implementation. 23 B0_P1_BFE Bank0, Port 1 Buffer Enable This bit enables or disables page buffer read hits. It is also used to invalidate the buffers. This bit is set by hardware reset, enabling the page buffers. 0: The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1: The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled. This field is ignored in the Platform Flash Controller implementation.
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Chapter 12 Flash memory
Table 12-60. PFCR0 field descriptions (continued)
Field Description
25-26 Bank0, Port 0 Page Buffer Configuration B0_P0_BCFG This field controls the configuration of the four page buffers in the PFlash controller. The buffers can be organized as a “pool” of available resources, or with a fixed partition between instruction and data buffers. If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and the just-fetched entry then marked as most-recently-used. If the Flash access is for the next-sequential line, the buffer is not marked as most-recently-used until the given address produces a buffer hit. 00: All four buffers are available for any Flash access, that is, there is no partitioning of the buffers based on the access type. 01: Reserved 10: The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11: The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. This field is set to 2b11 by hardware reset. 27 Bank0, Port 0 Data Prefetch Enable B0_P0_DPFE This field enables or disables prefetching initiated by a data read access. This field is cleared by hardware reset. 0: No prefetching is triggered by a data read access 1: If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any data read access 28 B0_P0_IPFE Bank0, Port 0 Instruction Prefetch Enable This field enables or disables prefetching initiated by an instruction fetch read access. This field is set by hardware reset. 0: No prefetching is triggered by an instruction fetch read access 1: If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch read access 29-30 Bank0, Port 0 Prefetch Limit B0_P0_PFLM This field controls the prefetch algorithm used by the PFlash controller. This field defines the prefetch behavior. In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is set to 2b10 by hardware reset. 00: No prefetching is performed. 01: The referenced line is prefetched on a buffer miss, that is, prefetch on miss. 1–: The referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit. 31 B0_P0_BFE Bank0, Port 0 Buffer Enable This bit enables or disables page buffer read hits. It is also used to invalidate the buffers. This bit is set by hardware reset. 0: The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1: The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled.
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12.4.4.2.2
Platform Flash Configuration Register 1 (PFCR1)
This register defines the configuration associated with Flash memory bank1. This corresponds to the “data Flash”. The register is described below in Table 12-38 and Table 12-61.
Offset 0x020
0 1 2 3 4 5 6 7 8 9 10 11 12
Access: Read/write
13 14 15
R W BK1_APC BK1_WWSC BK1_RWSC
Reset
0
16
0
17
0
18
1
19
1
20
0
21
0
22
0
23
1
24
1
25
0
26
0
27
0
28
1
29
1
30
BK1_RWWC
B1_P1_BFE
W
Reset
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 12-38. PFlash Configuration Register 1 (PFCR1) Table 12-61. PFCR1 field descriptions
Field 0-4 BK1_APC Description Bank1 Address Pipelining Control This field is used to control the number of cycles between Flash array access requests. This field must be set to a value appropriate to the operating frequency of the PFlash. The required settings are documented in the device data sheet. Higher operating frequencies require non-zero settings for this field for proper Flash operation. This field is set to 0b00010 by hardware reset. 00000: Accesses may be initiated on consecutive (back-to-back) cycles 00001: Access requests require one additional hold cycle 00010: Access requests require two additional hold cycles ... 11110: Access requests require 30 additional hold cycles 11111: Access requests require 31 additional hold cycles This field is ignored in single bank Flash configurations.
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B1_P0_BFE 1
R
0
0
0
0
0
0
BK1_RWWC
0
0
0
0
0
0
BK1_RWWC 1
31
Chapter 12 Flash memory
Table 12-61. PFCR1 field descriptions (continued)
Field 5-9 BK1_WWSC Description Bank1 Write Wait-State Control This field is used to control the number of wait-states to be added to the Flash array access time for writes. This field must be set to a value appropriate to the operating frequency of the PFlash. The required settings are documented in the device data sheet. Higher operating frequencies require non-zero settings for this field for proper Flash operation. This field is set to an appropriate value by hardware reset. This field is set to 0b00010 by hardware reset. 00000: No additional wait-states are added 00001: One additional wait-state is added 00010: Two additional wait-states are added ... 11111: 31 additional wait-states are added This field is ignored in single bank Flash configurations. 10-14 BK1_RWSC Bank1 Read Wait-State Control This field is used to control the number of wait-states to be added to the Flash array access time for reads. This field must be set to a value corresponding to the operating frequency of the PFlash and the actual read access time of the PFlash. The required settings are documented in the device data sheet. This field is set to 0b00010 by hardware reset. 00000: No additional wait-states are added 00001: One additional wait-state is added 00010: Two additional wait-states are added ... 11111: 31 additional wait-states are added This field is ignored in single bank Flash configurations. 15-16,24 BK1_RWWC Bank1 Read-While-Write Control This 3-bit field defines the controller response to Flash reads while the array is busy with a program (write) or erase operation. 0––: Terminate any attempted read while write/erase with an error response 111: Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable the abort + abort notification interrupt 110: Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable the abort + abort notification interrupt 101: Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100: Generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. This field is ignored in single bank Flash configurations. 17-22 Reserved, should be cleared.
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Table 12-61. PFCR1 field descriptions (continued)
Field 23 B1_P1_BFE Description Bank1, Port 1 Buffer Enable This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate the contents of the holding register. This bit is set by hardware reset, enabling the use of the holding register. 0: The holding register is disabled from satisfying read requests. 1: The holding register is enabled to satisfy read requests on hits. This field is ignored in the Platform Flash Controller implementation. 25-30 31 B1_P0_PFE Reserved, should be cleared. Bank1, Port 0 Buffer Enable This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate the contents of the holding register. This bit is set by hardware reset, enabling the use of the holding register. 0: The holding register is disabled from satisfying read requests. 1: The holding register is enabled to satisfy read requests on hits.
12.4.4.2.3
Platform Flash Access Protection Register (PFAPR)
The PFlash Access Protection Register (PFAPR) is used to control read and write accesses to the Flash based on system master number. Prefetching capabilities are defined on a per master basis. This register also defines the arbitration mode for controllers supporting two AHB ports. The register is described below in Figure 12-39 and Table 12-62. The contents of the register are loaded from location 0x203E00 of the shadow region in the code Flash (bank0) array at reset. To temporarily change the values of any of the fields in the PFAPR, a write to the IPS-mapped register is performed. To change the values loaded into the PFAPR at reset, the word location at address 0x203E00 of the shadow region in the Flash array must be programmed using the normal sequence of operations. The reset value shown in Table 12-39 reflects an erased or unprogrammed value from the shadow region.
Offset 0x024
0 1 2 3 4 5 6 7 8 9 10 11 12
Access: Read/write
13 14 15
R W Reset
0 *
16
0 *
17
0 *
18
0 *
19
0 *
20
0 *
21
ARBM 1
22
M7 PFD 1
24
M6 PFD 1
25
M5 PFD 1
26
M4 PFD 1
27
M3 PFD 1
28
M2 PFD 1
29
M1 PFD 1
30
M0 PFD 1
31
1
23
R W Reset
M7AP 1 1
M6AP 1 1
M5AP 1 1
M4AP 1 1
M3AP 1 1
M2AP 1 1
M1AP 1 1
M0AP 1 1
Figure 12-39. PFlash Access Protection Register (PFAPR)
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Table 12-62. PFAPR field descriptions
Field 0-5 6-7 ARBM Reserved, should be cleared. Arbitration Mode This 2-bit field controls the arbitration for PFlash controllers supporting two AHB ports. 00: Fixed priority arbitration with AHB p0 > p1 01: Fixed priority arbitration with AHB p1 > p0 1–: Round-robin arbitration This field is ignored in the Platform Flash Controller implementation. 8-15 MxPFD Master x Prefetch Disable (x = 0,1,2,...,7) These bits control whether prefetching may be triggered based on the master number of the requesting AHB master. This field is further qualified by the PFCR0[B0_Px_DPFE, B0_Px_IPFE, Bx_Py_BFE] bits. 0: Prefetching may be triggered by this master 1: No prefetching may be triggered by this master 16-31 MxAP Master x Access Protection (x = 0,1,2,...,7) These fields control whether read and write accesses to the Flash are allowed based on the master number of the initiating module. 00: No accesses may be performed by this master 01: Only read accesses may be performed by this master 10: Only write accesses may be performed by this master 11: Both read and write accesses may be performed by this master Description
12.4.5
Programming model connections
In this section, the internal connections between the two programming model “views” and the basic Platform Flash Controller functionality is defined. This is shown to aid in the understanding of the programming model compatibility considerations. The required wiring connections are internally handled by the Platform Flash Controller design. Table 12-63 shows the internal Platform Flash Controller internal signal name and the required bit fields from the Flash array’s BIUn register outputs (shown here as biun_regout[*]) to provide the specified functionality. In this definition, bit field concatenation is shown as “field1, field2”.
Table 12-63. Programming model internal connections
PFLASH_LCA Internal signal name bk0_apc[4:0] bk0_wwsc[4:0] bk0_rwsc[4:0] bk0_rwwc[2:0] bk0_p1_bcfg[1:0] Body applications biu0_regout[31:27] biu0_regout[26:22] biu0_regout[21:17] biu0_regout[16:15], biu0_regout[7] biu0_regout[14:13]
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Table 12-63. Programming model internal connections (continued)
PFLASH_LCA Internal signal name bk0_p1_dpfen bk0_p1_ipfen bk0_p1_pflim[1:0] bk0_p1_bfen bk0_p0_bcfg[1:0] bk0_p0_dpfen bk0_p0_ipfen bk0_p0_pflim[1:0] bk0_p0_bfen bk1_apc[4:0] bk1_wwsc[4:0] bk1_rwsc[4:0] bk1_rwwc[2:0] bk1_p0_bfen arbm[1:0] m7pfd m6pfd m5pfd m4pfd m3pfd m2pfd m1pfd m0pfd m7ap[1:0] m6ap[1:0] m5ap[1:0] m4ap[1:0] m3ap[1:0] m2ap[1:0] m1ap[1:0] m0ap[1:0] Body applications biu0_regout[12] biu0_regout[11] biu0_regout[10:9] biu0_regout[8] biu0_regout[6:5] biu0_regout[4] biu0_regout[3] biu0_regout[2:1] biu0_regout[0] biu1_regout[31:27] biu1_regout[26:22] biu1_regout[21:17] biu1_regout[16:15], biu1_regout[7] biu1_regout[0] biu2_regout[25:24] biu2_regout[23] biu2_regout[22] biu2_regout[21] biu2_regout[20] biu2_regout[19] biu2_regout[18] biu2_regout[17] biu2_regout[16] biu2_regout[15:14] biu2_regout[13:12] biu2_regout[11:10] biu2_regout[9:8] biu2_regout[7:6] biu2_regout[5:4] biu2_regout[3:2] biu2_regout[1:0]
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12.5
Functional description
The Platform Flash Controller interfaces between the AHB-Lite 2.v6 system bus and the Flash memory arrays. The Platform Flash Controller generates read and write enables, the Flash array address, write size, and write data as inputs to the Flash array. The Platform Flash Controller captures read data from the Flash array interface and drives it onto the AHB. Up to four pages of data (128-bit width) from bank0 are buffered by the Platform Flash Controller. Lines may be prefetched in advance of being requested by the AHB interface, allowing single-cycle (zero AHB wait-states) read data responses on buffer hits. Several prefetch control algorithms are available for controlling page read buffer fills. Prefetch triggering may be restricted to instruction accesses only, data accesses only, or may be unrestricted. Prefetch triggering may also be controlled on a per-master basis. Buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch. Access protections may be applied on a per-master basis for both reads and writes to support security and privilege mechanisms. Throughout this discussion, bkn_ is used as a prefix to refer to two signals, each for each bank: bk0_ and bk1_. Also, the nomenclature Bx_Py_RegName is used to reference a program-visible register field associated with bank “x” and port “y”.
12.5.1
Basic interface protocol
The Platform Flash Controller interfaces to the Flash array by driving addresses (bkn_fl_addr[23:0]) and read or write enable signals (bkn_fl_rd_en, bkn_fl_wr_en). The read or write enable signal (bkn_fl_rd_en, bkn_fl_wr_en) is asserted in conjunction with the reference address for a single rising clock when a new access request is made. Addresses are driven to the Flash array in a flow-through fashion to minimize array access time. When no outstanding access is in progress, the Platform Flash Controller drives addresses and asserts bkn_fl_rd_en or bkn_fl_wr_en and then may change to the next outstanding address in the next cycle. Accesses are terminated under control of the appropriate read/write wait-state control setting. Thus, the access time of the operation is determined by the settings of the wait-state control fields. Access timing can be varied to account for the operating conditions of the device (frequency, voltage, temperature) by appropriately setting the fields in the programming model for either bank. The Platform Flash Controller also has the capability of extending the normal AHB access time by inserting additional wait-states for reads and writes. This capability is provided to allow emulation of other memories which have different access time characteristics. The added wait-state specifications are provided by haddr[28:24]. These wait-states are applied in addition to the normal wait-states incurred for Flash accesses. Refer to Section 12.5.12, “Wait-state emulation” for more details. Prefetching of next sequential page is blocked when haddr[28:24] is non-zero. Buffer hits are also blocked as well, regardless of whether the access corresponds to valid data in one of the page read buffers. These steps are taken to ensure that timing emulation is correct and that excessive prefetching is avoided. In
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addition, to prevent erroneous operation in certain rare cases, the buffers are invalidated on any non-sequential AHB access with a non-zero value on haddr[28:24].
12.5.2
Access protections
The Platform Flash Controller provides programmable configurable access protections for both read and write cycles from masters via the PFlash Access Protection Register (PFAPR). It allows restriction of read and write requests on a per-master basis. This functionality is described in Section 12.4.4.2.3, “Platform Flash Access Protection Register (PFAPR)”. Detection of a protection violation results in an error response from the Platform Flash Controller on the AHB transfer.
12.5.3
Read cycles – Buffer miss
Read cycles from the Flash array are initiated by driving a valid access address on bkn_fl_addr[23:0] and asserting bkn_fl_rd_en for the required setup (and hold) time before (and after) the rising edge of hclk. The Platform Flash Controller then waits for the programmed number of read wait-states before sampling the read data on bkn_fl_rdata[127:0]. This data is normally stored in the least-recently updated page read buffer for bank0 in parallel with the requested data being forwarded to the AHB. For bank1, the data is captured in the page-wide temporary holding register as the requested data is forwarded to the AHB bus. Timing diagrams of basic read accesses from the Flash array are shown in Figure 12-40 through Figure 12-43. If the Flash access was the direct result of an AHB transaction, the page buffer is marked as most-recently-used as it is being loaded. If the Flash access was the result of a speculative prefetch to the next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is not changed to most-recently-used until a subsequent buffer hit occurs.
12.5.4
Read cycles – Buffer hit
Single cycle read responses to the AHB are possible with the Platform Flash Controller when the requested read access was previously loaded into one of the bank0 page buffers. In these “buffer hit” cases, read data is returned to the AHB data phase with a zero wait-state response. Likewise, the bank1 logic includes a single 128-bit temporary holding register and sequential accesses which “hit” in this register are also serviced with a zero wait-state response.
12.5.5
Write cycles
In a write cycle, address, write data, and control signals are launched off the same edge of hclk at the completion of the first AHB data phase cycle. Write cycles to the Flash array are initiated by driving a valid access address on bkn_fl_addr[23:0], driving write data on bkn_fl_wdata[63:0], and asserting bkn_fl_wr_en. Again, the controller drives the address and control information for the required setup time before the rising edge of hclk, and provides the required amount of hold time. The Platform Flash Controller then waits for the appropriate number of write wait-states before terminating the write operation. On the cycle following the programmed wait-state value, the Platform Flash Controller asserts hready_out to indicate to the AHB port that the cycle has terminated.
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12.5.6
Error termination
The Platform Flash Controller follows the standard procedure when an AHB bus cycle is terminated with an ERROR response. First, the Platform Flash Controller asserts hresp[0] and negates hready_out to signal an error has occurred. On the following clock cycle, the Platform Flash Controller asserts hready_out and holds both hresp[0] and hready_out asserted until hready_in is asserted. The first case that can cause an error response to the AHB is when an access is attempted by an AHB master whose corresponding Read Access Control or Write Access Control settings do not allow the access, thus causing a protection violation. In this case, the Platform Flash Controller does not initiate a Flash array access. The second case that can cause an error response to the AHB is when an access is performed to the Flash array and is terminated with a Flash error response. See Section 12.5.8, “Flash error response operation”. This may occur for either a read or a write operation. The third case that can cause an error response to the AHB is when a write access is attempted to the Flash array and is disallowed by the state of the bkn_fl_ary_access control input. This case is similar to case 1. A fourth case involves an attempted read access while the Flash array is busy doing a write (program) or erase operation if the appropriate read-while-write control field is programmed for this response. The 3-bit read-while-write control allows for immediate termination of an attempted read, or various stall-while-write/erase operations are occurring. The Platform Flash Controller can also terminate the current AHB access if hready_in is asserted before the end of the current bus access. While this circumstance should not occur, this does not result in an error condition being reported, as this behavior is initiated by the AHB. In this circumstance, the Platform Flash Controller control state machine completes any Flash array access in progress (without signaling the AHB) before handling a new access request.
12.5.7
Access pipelining
The Platform Flash Controller does not support access pipelining since this capability is not supported by the Flash array. As a result, the APC (Address Pipelining Control) field should typically be the same value as the RWSC (Read Wait-State Control) field for best performance, that is, BKn_APC = BKn_RWSC. It cannot be less than the RWSC.
12.5.8
Flash error response operation
The Flash array may signal an error response by asserting bkn_fl_xfr_err to terminate a requested access with an error. This may occur due to an uncorrectable ECC error, or because of improper sequencing during program/erase operations. When an error response is received, the Platform Flash Controller does not update or validate a bank0 page read buffer nor the bank1 temporary holding register. An error response may be signaled on read or write operations. For more information on the specifics related to signaling of errors, including Flash ECC, refer to the Flash array documentation. For additional information on the system registers which capture the faulting address, attributes, data and ECC information, see the chapter “Error Correction Status Module (ECSM).”
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12.5.9
Bank0 page read buffers and prefetch operation
The logic associated with bank0 of the Platform Flash Controller contains four 128-bit page read buffers which are used to hold data read from the Flash array. Each buffer operates independently, and is filled using a single array access. The buffers are used for both prefetch and normal demand fetches. The organization of each page buffer is described below in a pseudo-code representation. The hardware structure includes the buffer address and valid bit, along with 128 bits of page read data and several error flags.
struct { // bk0_page_bufferregaddr[23:4];// page address reg valid; // valid bit reg rdata[127:0];// page read data reg xfr_error; // transfer error indicator from flash array reg multi_ecc_error;// multi-bit ECC error indicator from flash array reg single_ecc_error;// single-bit correctable ECC indicator from flash array bk0_page_buffer[4];
}
For the general case, a page buffer is written at the completion of an error-free Flash access and the valid bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the current access address matches the address stored in the buffer, can be serviced in 0 AHB wait-states as the stored read data is routed from the given page buffer back to the requesting bus master. As noted in Section 12.5.8, “Flash error response operation”, a page buffer is not marked as valid if the Flash array access terminated with any type of transfer error. However, the result is that Flash array accesses that are tagged with a single-bit correctable ECC event are loaded into the page buffer and validated. For additional comments on this topic, see Section 12.5.9.4, “Buffer invalidation”. Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or disabled from triggering prefetches, and triggering may be further restricted based on whether a read access is for instruction or data. A read access to the Platform Flash Controller may trigger a prefetch to the next sequential page of array data on the first idle cycle following the request. The access address is incremented to the next-higher 16-byte boundary, and a Flash array prefetch is initiated if the data is not already resident in a page buffer. Prefetched data is always loaded into the least-recently-used buffer. Buffers may be in one of six states, listed here in order of priority: 1. Invalid — The buffer contains no valid data. 2. Used — The buffer contains valid data which has been provided to satisfy an AHB burst type read. 3. Valid — The buffer contains valid data which has been provided to satisfy an AHB single type read. 4. Prefetched — The buffer contains valid data which has been prefetched to satisfy a potential future AHB access. 5. Busy AHB — The buffer is currently being used to satisfy an AHB burst read. 6. Busy Fill — The buffer has been allocated to receive data from the Flash array, and the array access is still in progress.
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Selection of a buffer to be loaded on a miss is based on the following replacement algorithm: 1. First, the buffers are examined to determine if there are any invalid buffers. If there are multiple invalid buffers, the one to be used is selected using a simple numeric priority, where buffer 0 is selected first, then buffer 1, etc. 2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement. Once the candidate page buffer has been selected, the Flash array is accessed and read data loaded into the buffer. If the buffer load was in response to a miss, the just-loaded buffer is immediately marked as most-recently-used. If the buffer load was in response to a speculative fetch to the next-sequential line address after a buffer hit, the recently-used status is not changed. Rather, it is marked as most-recently-used only after a subsequent buffer hit. This policy maximizes performance based on reference patterns of Flash accesses and allows for prefetched data to remain valid when non-prefetch enabled bus masters are granted Flash access. Several algorithms are available for prefetch control which trade off performance versus power. They are defined by the Bx_Py_PFLM (prefetch limit) register field. More aggressive prefetching increases power slightly due to the number of wasted (discarded) prefetches, but may increase performance by lowering average read latency. In order for prefetching to occur, a number of control bits must be enabled. Specifically, the global buffer enable (Bx_Py_BFE) must be set, the prefetch limit (Bx_Py_PFLM) must be non-zero and either instruction prefetching (Bx_Py_IPFE) or data prefetching (Bx_Py_DPFE) enabled. Refer to Section 12.4.4.2, “Register description” for a description of these control fields.
12.5.9.1
Instruction/Data prefetch triggering
Prefetch triggering may be enabled for instruction reads via the Bx_Py_IPFE control field, while prefetching for data reads is enabled via the Bx_Py_DPFE control field. Additionally, the Bx_Py_PFLIM field must be set to enable prefetching. Prefetches are never triggered by write cycles.
12.5.9.2
Per-master prefetch triggering
Prefetch triggering may be also controlled for individual bus masters. AHB accesses indicate the requesting master via the hmaster[3:0] inputs. Refer to Section 12.4.4.2.3, “Platform Flash Access Protection Register (PFAPR) for details on these controls.
12.5.9.3
Buffer allocation
Allocation of the line read buffers is controlled via page buffer configuration (Bx_Py_BCFG) field. This field defines the operating organization of the four page buffers. The buffers can be organized as a “pool” of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated to instruction or data accesses. For the fixed partition, two configurations are supported. In one configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. In the second configuration, buffers 0, 1 and 2 are allocated for instruction fetches and buffer 3 reserved for data accesses.
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12.5.9.4
Buffer invalidation
The page read buffers may be invalidated under hardware or software control. Any falling edge transition of the array’s bkn_fl_done signal causes the page read buffers to be marked as invalid. This input is negated by the Flash array at the beginning of all program/erase operations as well as in certain other cases. Buffer invalidation occurs at the next AHB non-sequential access boundary, but does not affect a burst from a page read buffer which is in progress. Software may invalidate the buffers by clearing the Bx_Py_BFE bit, which also disables the buffers. Software may then re-assert the Bx_Py_BFE bit to its previous state, and the buffers will have been invalidated. One special case needing software invalidation relates to page buffer “hits” on Flash data which was tagged with a single-bit ECC event on the original array access. Recall that the page buffer structure includes an status bit signaling the array access detected and corrected a single-bit ECC error. On all subsequent buffer hits to this type of page data, a single-bit ECC event is signaled by the Platform Flash Controller. Depending on the specific hardware configuration, this reporting of a single-bit ECC event may generate an ECC alert interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ECC event. Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on haddr[28:24] to support wait-state emulation.
12.5.10 Bank1 Temporary Holding Register
Recall the bank1 logic within the Platform Flash Controller includes a single 128-bit data register, used for capturing read data. Since this bank does not support prefetching, the read data for the referenced address is bypassed directly back to the AHB data bus. The page is also loaded into the temporary data register and subsequent accesses to this page can hit from this register, if it is enabled (B1_Py_BFE). The organization of the temporary holding register is described below in a pseudo-code representation. The hardware structure includes the buffer address and valid bit, along with 128 bits of page read data and several error flags and is the same as an individual bank0 page buffer.
struct { // bk1_page_buffer reg addr[23:4];// page address reg valid; // valid bit reg rdata[127:0];// page read data reg xfr_error; // transfer error indicator from flash array reg multi_ecc_error;// multi-bit ECC error indicator from flash array reg single_ecc_error;// single-bit correctable ECC indicator from flash array bk1_page_buffer;
}
For the general case, a temporary holding register is written at the completion of an error-free Flash access and the valid bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the current access address matches the address stored in the temporary holding register, can be serviced in 0 AHB wait-states as the stored read data is routed from the temporary register back to the requesting bus master. The contents of the holding register are invalidated by the falling edge transition of bk1_fl_done and on any non-sequential access with a non-zero value on haddr[28:24] (to support wait-state emulation) in the
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same manner as the bank0 page buffers. Additionally, the B1_Py_BFE register bit can be cleared by software to invalidate the contents of the holding register. As noted in Section 12.5.8, “Flash error response operation”, the temporary holding register is not marked as valid if the Flash array access terminated with any type of transfer error. However, the result is that Flash array accesses that are tagged with a single-bit correctable ECC event are loaded into the temporary holding register and validated. Accordingly, one special case needing software invalidation relates to holding register “hits” on Flash data which was tagged with a single-bit ECC event. Depending on the specific hardware configuration, the reporting of a single-bit ECC event may generate an ECC alert interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ECC event. The bank1 temporary holding register effectively operates like a single page buffer.
12.5.11 Read-while-write functionality
The Platform Flash Controller supports various programmable responses for read accesses while the Flash is busy performing a write (program) or erase operation. For all situations, the Platform Flash Controller uses the state of the Flash array’s bkn_fl_done output to determine if it is busy performing some type of high voltage operation, namely, if bkn_fl_done = 0, the array is busy. Specifically, two 3-bit read-while-write (BKn_RWWC) control register fields define the Platform Flash Controller’s response to these types of access sequences. Five unique responses are defined by the BKn_RWWC setting: one that immediately reports an error on an attempted read and four settings that support various stall-while-write capabilities. Consider the details of these settings. • BKn_RWWC = 0b0-For this mode, any attempted Flash read to a busy array is immediately terminated with an AHB error response and the read is blocked in the controller and not seen by the Flash array. • BKn_RWWC = 0b111 This defines the basic stall-while-write capability and represents the default reset setting. For this mode, the Platform Flash Controller module simply stalls any read reference until the Flash has completed its program/erase operation. If a read access arrives while the array is busy or if a falling-edge on bkn_fl_done occurs while a read is still in progress, the AHB data phase is stalled by negating hready_out and saving the address and attributes into holding registers. Once the array has completed its program/erase operation, the Platform Flash Controller uses the saved address and attribute information to create a pseudo address phase cycle to “retry” the read reference and sends the registered information to the array as bkn_fl_rd_en is asserted. Once the retried address phase is complete, the read is processed normally and once the data is valid, it is forwarded to the AHB bus and hready_out negated to terminate the system bus transfer. • BKn_RWWC = 0b110 This setting is similar to the basic stall-while-write capability provided when BKn_RWWC = 0b111 with the added ability to generate a notification interrupt if a read arrives while the array is busy with a program/erase operation. There are two notification interrupts, one for each bank (see Chapter 14, “Interrupt Controller (INTC)”). • BKn_RWWC = 0b101
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•
Again, this setting provides the basic stall-while-write capability with the added ability to abort any program/erase operation if a read access is initiated. For this setting, the read request is captured and retried as described for the basic stall-while-write, plus the program/erase operation is aborted by the Platform Flash Controller’s assertion of the bkn_fl_abort signal. The bkn_fl_abort signal remains asserted until bkn_fl_done is driven high. For this setting, no notification interrupts are generated. BKn_RWWC = 0b100 This setting provides the basic stall-while-write capability with the ability to abort any program/erase operation if a read access is initiated plus the generation of an abort notification interrupt. For this setting, the read request is captured and retried as described for the basic stall-while-write, the program/erase operation is aborted by the Platform Flash Controller’s assertion of the bkn_fl_abort signal and an abort notification interrupt generated. There are two abort notification interrupts, one for each bank.
As detailed above, a total of four interrupt requests are associated with the stall-while-write functionality. These interrupt requests are captured as part of ECSM’s interrupt register and logically summed together to form a single request to the interrupt controller.
Table 12-64. Platform Flash Controller stall-while-write interrupts
MIR[n] ECSM.MIR[7] ECSM.MIR[6] ECSM.MIR[5] ECSM.MIR[4] Interrupt description Platform Flash bank0 abort notification, MIR[FB0AI] Platform Flash bank0 stall notification, MIR[FB0SI] Platform Flash bank1 abort notification, MIR[FB1AI] Platform Flash bank1 stall notification, MIR[FB1S1]
For example timing diagrams of the stall-while-write and abort-while-write operations, see Table 12-44 and Figure 12-45 respectively.
12.5.12 Wait-state emulation
Emulation of other memory array timings are supported by the Platform Flash Controller on read cycles to the Flash. This functionality may be useful to maintain the access timing for blocks of memory which were used to overlay Flash blocks for the purpose of system calibration or tuning during code development. The Platform Flash Controller inserts additional wait-states according to the values of haddr[28:24]. When these inputs are non-zero, additional cycles are added to AHB read cycles. Write cycles are not affected. In addition, no page read buffer prefetches are initiated, and buffer hits are ignored. Table 12-65 and Table 12-66 show the relationship of haddr[28:24] to the number of additional primary wait-states. These wait-states are applied to the initial access of a burst fetch or to single-beat read accesses on the AHB system bus. Note that the wait-state specification consists of two components: haddr[28:26] and haddr[25:24] and effectively extends the Flash read by (8 * haddr[25:24] + haddr[28:26]) cycles.
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Table 12-65. Additional wait-state encoding
Memory address haddr[28:26] 000 001 010 011 100 101 110 111 Additional wait-states 0 1 2 3 4 5 6 7
Table 12-66 shows the relationship of haddr[25:24] to the number of additional wait-states. These are applied in addition to those specified by haddr[28:26] and thus extend the total wait-state specification capability.
Table 12-66. Extended additional wait-state encoding
Memory address haddr[25:24] 00 01 10 11 Additional wait-states (added to those specified by haddr[28:26]) 0 8 16 24
12.5.13 Timing diagrams
Since Platform Flash Controller is typically used in platform configurations with a cacheless core, the operation of the processor accesses to the platform memories, for example Flash and SRAM, plays a major role in the overall system performance. Given the core/platform pipeline structure, the platform’s memory controllers (PFlash, PRAM) are designed to provide a zero wait-state data phase response to maximize processor performance. The following diagrams illustrate operation of various cycle types and responses referenced earlier in this chapter including stall-while-read (Figure 12-44) and abort-while-read (Figure 12-45) diagrams.
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Read, no buffering, no prefetch, APC = 0, RWSC = 0, PFLM = 0 1 hclk htrans haddr,hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en addr y bkn_fl_wr_en bkn_fl_rdata C(y) C(y+4) C(y+8) C(y+12) addr y+4 addr y+8 addr+12 okay y okay y+4 okay y+8 okay y+12 okay okay okay okay C(y) C(y+4) C(y+8) C(y+12) nonseq addr y seq addr y+4 seq addr y+8 seq addr y+12 2 3 4 5 6 7 8
Figure 12-40. 1-cycle access, no buffering, no prefetch
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Burst Read, buffer miss, no prefetch, APC = 2, RWSC = 2, PFLM = 0 1 hclk nonseq seq seq seq 2 3 4 5 6
7
8
htrans
haddr,hprot
addr y
addr y+4
addr y+8
addr y+12
hwrite C(y) C(y+4)
hrdata
hwdata
hready_out okay okay okay okay okay okay okay okay
hresp
bkn_fl_addr
y
y+4
y+8
bkn_fl_rd_en addr y bkn_fl_wr_en addr y+4 addr y+8
bkn_fl_rdata
C(y)
C(y+4)
bkn_fl_xfr_err
Figure 12-41. 3-cycle access, no prefetch, buffering disabled
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Burst Read, buffer miss, no prefetch, APC = 2, RWSC = 2, PFLM = 0 1 hclk htrans haddr,hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_wr_en addr y bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err C(y) okay Y okay okay okay okay okay okay okay C(y) C(y+4) C(y+8) C(y+12) nonseq addr y seq addr y+4 seq addr y+8 seq addr y+12 2 3 4 5 6 7 8
Figure 12-42. 3-cycle access, no prefetch, buffering enabled
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Burst Read, buffer miss, prefetch, APC = 2, RWSC = 2, PFLM = 2
1 hclk nonseq
2
3
4
5
6
7
8
htrans
seq
seq
seq
seq
seq
haddr,hprot
addr y
addr y+4
addr y+8
addr y+12
addr y+16
addr y+20
hwrite C(y+4) C(y+16)
hrdata
C(y)
C(y+8)
C(y+12)
hwdata
hready_out
hresp
okay
okay
okay y+16
okay
okay
okay
okay y+32
okay
bkn_fl_addr
y
bkn_fl_rd_en addr y bkn_fl_wr_en C(y+16) addr y+16 addr y+32
bkn_fl_rdata
C(y)
bkn_fl_xfr_err
Figure 12-43. 3-cycle access, prefetch and buffering enabled
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Burst Read, Stall-and-Retry, APC = 2, RWSC = 2, PFLM = 2 1 hclk htrans haddr,hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en addr y bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err bkn_done bkn_abort ecsm_mir[fbnsi] ecsm_mir[fbnai] C(y) addr y (retry) addr y+16 okay y okay okay y+16 okay okay okay y okay okay y+16 okay okay C(y) C(y+4) nonseq addr y seq addr y+4 seq addr y+8 2 3 4 5 6 7 8 9 10
Figure 12-44. 3-cycle access, stall-and-retry with BKn_RWWC = 11x
As shown in Figure 12-44, the 3-cycle access to address y is interrupted when an operation causes the bkn_done signal to be negated signaling that the array bank is busy with a high voltage program or erase event. Eventually, this array operation completes (at the end of cycle 4) and bkn_done returns to a logical 1. In cycle 6, the Platform Flash Controller module retries the read to address y which was interrupted by the negation of bkn_done in cycle 3. Note that throughout cycles 2–9, the AHB bus pipeline is stalled with a read to address y in the AHB data phase and a read to address y+4 in the address phase. Depending on the state of the least-significant-bit of the BKn_RWWC control field, the hardware may also signal a stall notification interrupt (if BKn_RWWC = 110). The stall notification interrupt is shown as the optional assertion of ECSM’s MIR[FBnSI] (Flash bank n stall interrupt).
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Chapter 12 Flash memory
Burst Read, Abort-and-Retry, APC = 2, RWSC = 2, PFLM = 2 1 hclk htrans haddr,hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en addr y bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err bkn_done bkn_abort ecsm_mir[fbnsi] ecsm_mir[fbnai] C(y) addr y (retry) addr y+16 okay y okay okay y+16 okay okay okay y okay y+16 okay okay okay C(y) C(y+4) nonseq addr y seq addr y+4 seq addr y+8 2 3 4 5 6 7 8 9 10
Figure 12-45. 3-cycle access, abort-and-retry with BKn_RWWC = 10x
Figure 12-45 shows the abort-while-write timing diagram. In this example, the 3-cycle access to address y is interrupted when an operation causes the bkn_done signal to be negated signaling that the array bank is busy with a high voltage program or erase event. Based on the setting of BKn_RWWC, once the bkn_done signal is detected as negated, the Platform Flash Controller asserts bkn_abort which forces the Flash array to cancel the high voltage program or erase event. The array operation completes (at the end of cycle 4) and bkn_done returns to a logical 1. It should be noted that the time spent in cycle 4 for Figure 12-45 is considerably less than the time in the same cycle in Figure 12-44 (because of the abort operation). In cycle 6, the Platform Flash Controller module retries the read to address y which was interrupted by the negation of bkn_done in cycle 3. Note that throughout cycles 2–9, the AHB bus pipeline is stalled with a read to address y in the AHB data phase and a read to address y+4 in the address phase. Depending on the state of the least-significant-bit of the BKn_RWWC control field, the hardware may also signal an abort notification interrupt (if BKn_RWWC = 100). The stall notification interrupt is shown as the optional assertion of ECSM’s MIR[FBnAI] (Flash bank n abort interrupt).
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Chapter 13 Static RAM (SRAM)
Chapter 13 Static RAM (SRAM)
13.1 Introduction
This device has up to 16 KB of general-purpose static RAM (SRAM). The SRAM provides the following features: • SRAM can be read/written from any bus master • Byte, halfword and word addressable • ECC (error correction code) protected with single-bit correction and double-bit detection The SRAM has only one operating mode. The RAM domain (all 16 KB) will be joined directly to the ‘always_on’ digital domain.
13.2
Register memory map
Table 13-1. SRAM memory map
Address 0x4000_0000 (Base) Register name — Register description SRA Size up to 16 KB
The L2SRAM occupies 16 KB of memory starting at the base address as shown in Table 13-1.
The internal SRAM has no registers. Registers for the SRAM ECC are located in the ECSM (see the Error Correction Status Module (ECSM) chapter of the reference manual for more information).
13.3
SRAM ECC mechanism
The SRAM ECC detects the following conditions and produces the following results: • Detects and corrects all 1-bit errors • Detects and flags all 2-bit errors as non-correctable errors • Detects 39-bit reads (32-bit data bus plus the 7-bit ECC) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag SRAM does not detect all errors greater than 2 bits. Internal SRAM write operations are performed on the following byte boundaries: • 1 byte (0:7 bits) • 2 bytes (0:15 bits) • 4 bytes or 1 word (0:31 bits)
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Chapter 13 Static RAM (SRAM)
If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated across the 32-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM. If the write operation is less than the entire 32-bit data width (1 or 2-byte segment), the following occurs: 1. The ECC mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or flagging errors. 2. The write data bytes (1 or 2-byte segment) are merged with the corrected 32 bits on the data bus. 3. The ECC is then calculated on the resulting 32 bits formed in the previous step. 4. The 7-bit ECC result is appended to the 32 bits from the data bus, and the 39-bit value is then written to SRAM.
13.3.1
Access timing
The system bus is a two-stage pipelined bus, which makes the timing of any access dependent on the access during the previous clock. Table 13-2 lists the various combinations of read and write operations to SRAM and the number of wait states used for the each operation. The table columns contain the following information: • Current operation — Lists the type of SRAM operation currently executing • Previous operation — Lists the valid types of SRAM operations that can precede the current SRAM operation (valid operation during the preceding clock) • Wait states — Lists the number of wait states (bus clocks) the operation requires which depends on the combination of the current and previous operation
Table 13-2. Number of wait states required for SRAM operations
Operation type Read Current operation Read Previous operation Idle Pipelined read 8, 16 or 32-bit write 0 (read from the same address) 1 (read from a different address) Pipelined read Read 0 Number of wait states required 1
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Chapter 13 Static RAM (SRAM)
Table 13-2. Number of wait states required for SRAM operations (continued)
Operation type Write Current operation 8 or 16-bit write Previous operation Idle Read Pipelined 8 or 16-bit write 32-bit write 8 or 16-bit write Pipelined 8, 16 or 32-bit write 32-bit write 8, 16 or 32-bit write Idle 32-bit write Read 0 (write to the same address) 0 0 2 Number of wait states required 1
13.3.2
Reset effects on SRAM accesses
Asynchronous reset will possibly corrupt SRAM if it asserts during a read or write operation to SRAM. The completion of that access depends on the cycle at which the reset occurs. Data read from or written to SRAM before the reset event occurred is retained, and no other address locations are accessed or changed. In case of no access ongoing when reset occurs, the SRAM corruption does not happen. Instead, synchronous reset (SW reset) should be used in controlled function (without SRAM accesses) in case an initialization procedure without SRAM initialization is needed.
13.4
Functional description
ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and ECC calculations are performed during the write portion of a R/W operation. Because the ECC bits can contain random data after the device is powered on, the SRAM must be initialized by executing 32-bit write operations prior to any read accesses. This is also true for implicit read accesses caused by any write accesses of less than 32 bits as discussed in Section 13.3, “SRAM ECC mechanism.
13.5
Initialization and application information
To use the SRAM, the ECC must check all bits that require initialization after power on. All writes must specify an even number of registers performed on 32-bit word-aligned boundaries. If the write is not the entire 32 bits (8 or 16 bits), a read / modify / write operation is generated that checks the ECC value upon the read. See Section 13.3, “SRAM ECC mechanism.
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Chapter 13 Static RAM (SRAM)
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Chapter 14 Interrupt Controller (INTC)
Chapter 14 Interrupt Controller (INTC)
14.1 Introduction
The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 95 interrupt requests. It is targeted to work with a Power Architecture technology processor and automotive powertrain applications where the ISRs nest to multiple levels, but it also can be used with other processors and applications. For high priority interrupt requests in these target applications, the time from the assertion of the peripheral’s interrupt request from the peripheral to when the processor is performing useful work to service the interrupt request needs to be minimized. The INTC supports this goal by providing a unique vector for each interrupt request source. It also provides 16 priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. Since each individual application will have different priorities for each source of interrupt request, the priority of each interrupt request is configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. Multiple processors can assert interrupt requests to each other through software configurable interrupt requests. These same software configurable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR can assert a software configurable interrupt request to finish the servicing in a lower priority ISR. Therefore these software configurable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS.
14.2
• • • •
Features
Supports 87 peripheral and 8 software-configurable interrupt request sources Unique 9-bit vector per interrupt source Each interrupt source can be programmed to one of 16 priorities Preemption — Preemptive prioritized interrupt requests to processor — ISR at a higher priority preempts ISRs or tasks at lower priorities — Automatic pushing or popping of preempted priority to or from a LIFO — Ability to modify the ISR or task priority; modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. Low latency – 3 clocks from receipt of interrupt request from peripheral to interrupt request to processor
•
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Chapter 14 Interrupt Controller (INTC)
Table 14-1. Interrupt sources available
Interrupt sources (95) Software ECSM eDMA Software Watchdog (SWT) STM Flash/SRAM ECC (SEC-DED) Real Time Counter (RTC/API) System Integration Unit Lite (SIUL) WakeUp Unit (WKUP) MC_ME MC_RGM FXOSC Periodic Interrupt Timer (PIT) Analog to Digital Converter 1 (ADC1) FlexCAN_0 (CAN0) LINFlex_0 LINFlex_1 LINFlex_2 DSPI_0 DSPI_1 Enhanced Modular I/O Subsystem 0 (eMIOS_0) Number available 8 1 17 1 4 2 2 3 4 4 1 1 4 3 7 3 3 3 5 5 14
14.3
Block diagram
Figure 14-1 provides a block diagram of the interrupt controller (INTC).
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Chapter 14 Interrupt Controller (INTC)
Software Set/Clear Interrupt Registers
Priority Select Registers End of Interrupt Register
Module Configuration Register
Hardware Vector Enable 1
Flag Bits Peripheral Interrupt Requests 8 n
1
n1 x 4-bits
Priority Arbitrator 4
Highest Priority Interrupt Requests n1
Request Selector
Lowest Vector Interrupt Request n1
Vector Table Entry Size 1 Interrupt Vector 9 Interrupt Vector 9
Vector Encoder
Highest Priority New Priority 4
Processor 0 Interrupt Acknowledge Register
Pushed Priority 4 Processor 0 Priority LIFO Popped Priority 4 Processor 0 Current Priority Register
Update Interrupt Vector Current Priority 4 Priority Comparator
1
Interrupt Request to Processor 1
Interrupt Acknowledge Push/Update/Acknowledge Pop Memory Mapped Registers Non-Memory Mapped Logic 1 1 Slave Interface for Reads & Writes
1 Peripheral Bus
Figure 14-1. INTC block diagram
14.4
14.4.1
Modes of operation
Normal mode
In normal mode, the INTC has two handshaking modes with the processor: software vector mode and hardware vector mode.
14.4.1.1
Software vector mode
In software vector mode, software, that is the interrupt exception handler, must read a register in the INTC to obtain the vector associated with the interrupt request to the processor. The INTC will use software vector mode for a given processor when its associated HVEN bit in INTC_MCR is negated. The hardware vector enable signal to processor 0 or processor 1 is driven as negated when its associated HVEN bit is negated. The vector is read from INC_IACKR. Reading the INTC_IACKR negates the interrupt request to the associated processor. Even if a higher priority interrupt request arrived while waiting for this interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. The reading also pushes the PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated INTC_CPR with the new priority. Furthermore, the interrupt vector to the processor is driven as all 0s. The interrupt acknowledge signal from the associated processor is ignored.
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Chapter 14 Interrupt Controller (INTC)
14.4.1.2
Hardware vector mode
In hardware vector mode, the hardware is the interrupt vector signal from the INTC in conjunction with a processor with the capability use that vector. In hardware vector mode, this hardware causes the first instruction to be executed in handling the interrupt request to the processor to be specific to that vector. Therefore the interrupt exception handler is specific to a peripheral or software configurable interrupt request rather than being common to all of them. The INTC uses hardware vector mode for a given processor when the associated HVEN bit in the INTC_MCR is asserted. The hardware vector enable signal to the associated processor is driven as asserted. When the interrupt request to the associated processor asserts, the interrupt vector signal is updated. The value of that interrupt vector is the unique vector associated with the preempting peripheral or software configurable interrupt request. The vector value matches the value of the INTVEC field in the INTC_IACKR field in the INTC_IACKR, depending on which processor was assigned to handle a given interrupt source. The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for the interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in the associated INTC_CPR register onto the associated LIFO and updates the associated PRI in the associated INTC_CPR register with the new priority. This pushing of the PRI value onto the associated LIFO and updating PRI in the associated INTC_CPR does not occur when the associated interrupt acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI value in the associated INTC_CPR register would need to be pushed and the previously last pushed PRI value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR is updated with the new priority, and the associated LIFO is neither pushed or popped.
14.4.1.3
Debug mode
The INTC operation in debug mode is identical to its operation in normal mode.
14.4.1.4
Stop mode
The INTC supports STOP mode. The INTC can have its clock input disabled at any time by the clock driver on the device. While its clocks are disabled, the INTC registers are not accessible. The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to the processor. Since the INTC is not clocked in STOP mode, peripheral interrupt requests can not be used as a wakeup source, unless the device supports that interrupt request as a wakeup source.
14.5
14.5.1
Memory map and register description
Module memory map
Table 14-2 shows the INTC memory map.
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Chapter 14 Interrupt Controller (INTC)
Table 14-2. INTC memory map
Offset from INTC_BASE_ADDR1 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020–0x0027 0x0028–0x003C 0x0040–0x00D0
1 2
Register INTC Module Configuration Register (INTC_MCR) Reserved INTC Current Priority Register for Processor (INTC_CPR) Reserved INTC Interrupt Acknowledge Register (INTC_IACKR) Reserved INTC End-of-Interrupt Register (INTC_EOIR) Reserved INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7) Reserved INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR152_154)3
Access R/W — R/W — R/W 2 — W — R/W — R/W
Reset value
Location
0x0000_0000 on page 397 — —
0x0000_000F on page 398 — —
0x0000_0000 on page 400 — —
0x0000_0000 on page 401 — —
0x0000_0000 on page 401 — —
0x0000_0000 on page 403
INTC_BASE_ADDR = 0xFFF4_8000 When the HVEN bit in the INTC module configuration register (INTC_MCR) is asserted, a read of the INTC_IACKR has no side effects. 3 The PRI fields are “reserved” for peripheral interrupt requests whose vectors are labeled ‘Reserved’ in Figure 14-3.
14.5.2
Register description
With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination of accessing the four bytes of a register with a single access is supported, provided that the access does not cross a register boundary. These supported accesses include types and sizes of eight bits, aligned 16 bits, misaligned 16 bits to the middle two bytes, and aligned 32 bits. Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. In software vector mode, the side effects of a read of INTC_IACKR are the same regardless of the size of the read. In either software or hardware vector mode, the size of a write to either INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write.
14.5.2.1
INTC Module Configuration Register (INTC_MCR)
The module configuration register is used to configure options of the INTC.
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Chapter 14 Interrupt Controller (INTC)
Offset: 0x0000
0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0
Access: User read/write
12 0 13 0 14 0 15 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17 0
18 0
19 0
20 0
21 0
22 0
23 0
24 0
25 0
26 VTES
27 0
28 0
29 0
30 0
31 HVEN
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-2. INTC Module Configuration Register (INTC_MCR) Table 14-3. INTC_MCR field descriptions
Field 26 VTES Description Vector table entry size Controls the number of ‘0’s to the right of INTVEC in Section 14.5.2.3, “INTC Interrupt Acknowledge Register (INTC_IACKR). If the contents of INTC_IACKR are used as an address of an entry in a vectortable as in software vector mode, then the number of rightmost ‘0’s will determine the size of each vector table entry. VTES impacts software vector mode operation but also affects INTC_IACKR[INTVEC] position in both hardware vector mode and software vector mode. 0 4 bytes 1 8 bytes Hardware vector enable Controls whether the INTC is in hardware vector mode or software vector mode. Refer to Section 14.4, “Modes of operation, for the details of the handshaking with the processor in each mode. 0 Software vector mode 1 Hardware vector mode
31 HVEN
14.5.2.2
INTC Current Priority Register for Processor (INTC_CPR)
Access: User read/write
2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI
Offset: 0x0008
0 1 0
R0 W Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Figure 14-3. INTC Current Priority Register (INTC_CPR) Table 14-4. INTC_CPR field descriptions
Field 28–31 PRI[0:3] Description Priority PRI is the priority of the currently executing ISR according to the field values defined in Table 14-5.
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Chapter 14 Interrupt Controller (INTC)
The INTC_CPR masks any peripheral or software configurable interrupt request set at the same or lower priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the INTC_CPR’s PRI field. The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to Section 14.7.5, “Priority ceiling protocol. NOTE A store to modify the PRI field which closely precedes or follows an access to a shared resource can result in a non-coherent access to that resource. Refer to Section 14.7.5.2, “Ensuring coherency for example code to ensure coherency.
Table 14-5. PRI values
PRI 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Meaning Priority 15—highest priority Priority 14 Priority 13 Priority 12 Priority 11 Priority 10 Priority 9 Priority 8 Priority 7 Priority 6 Priority 5 Priority 4 Priority 3 Priority 2 Priority 1 Priority 0—lowest priority
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Chapter 14 Interrupt Controller (INTC)
14.5.2.3
INTC Interrupt Acknowledge Register (INTC_IACKR)
Access: User read/write
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset: 0x0010
0
R W Reset
0 0 0 0 0 0
VTBA (most significant 16 bits)
0
0
0
0
0
0
0
0
0
0
16
17
18 VTBA
19
20
21
22
23
24
25 INTVEC 1
26
27
28
29
30 0
31 0
R W Reset
1 0
(least significant five bits)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When the VTES bit in INTC_MCR is asserted, INTVEC is shifted to the left one bit. Bit 29 is read as a 0. VTBA is narrowed to 20 bits in width.
Figure 14-4. INTC Interrupt Acknowledge Register (INTC_IACKR) Table 14-6. INTC_IACKR field descriptions
Field 0–20 or 0–19 VTBA 21–29 or 20–28 INTVEC Description Vector Table Base Address Can be the base address of a vector table of addresses of ISRs. The VTBA only uses the leftmost 20 bits when the VTES bit in INTC_MCR is asserted. Interrupt Vector It is the vector of the peripheral or software configurable interrupt request that caused the interrupt request to the processor. When the interrupt request to the processor asserts, the INTVEC is updated, whether the INTC is in software or hardware vector mode. Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28. VTBA is then shortened by one bit to bits 0–19.
The interrupt acknowledge register provides a value which can be used to load the address of an ISR from a vector table. The vector table can be composed of addresses of the ISRs specific to their respective interrupt vectors. In software vector mode, the INTC_IACKR has side effects from reads. Therefore, it must not be speculatively read while in this mode. The side effects are the same regardless of the size of the read. Reading the INTC_IACKR does not have side effects in hardware vector mode.
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Chapter 14 Interrupt Controller (INTC)
14.5.2.4
INTC End-of-Interrupt Register (INTC_EOIR)
Access: Write only
2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Offset: 0x0018
0 1 0
R0 W Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-5. INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. An exception to this behavior is described in Section 14.4.1.2, “Hardware vector mode. The values and size of data written to the INTC_EOIR are ignored. The values and sizes written to this register neither update the INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR. Reading the INTC_EOIR has no effect on the LIFO.
14.5.2.5
INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7)
Access: User read/write
1 0 2 0 3 0 4 0 5 0 6 0 SET0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 CLR0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 SET1 0 0 15 CLR1
Offset: 0x0020
0
R W Reset
0
16
17 0
18 0
19 0
20 0
21 0
22 0 SET2
23 CLR2
24 0
25 0
26 0
27 0
28 0
29 0
30 0 SET3
31 CLR3
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-6. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])
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Offset: 0x0024
0 1 0 2 0 3 0 4 0 5 0 6 0 SET4 0 0 0 0 0 0 0 0 0 0 0 0 7 CLR4 8 0 9 0 10 0 11 0
Access: User read/write
12 0 13 0 14 0 SET5 0 0 0 0 15 CLR5
R W Reset
0
16
17 0
18 0
19 0
20 0
21 0
22 0 SET6
23 CLR6
24 0
25 0
26 0
27 0
28 0
29 0
30 0 SET7
31 CLR7
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-7. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7]) Table 14-7. INTC_SSCIR[0:7] field descriptions
Field Description
6, 14, 22, 30 Set Flag Bits SET[0:7] Writing a 1 sets the corresponding CLRx bit. Writing a 0 has no effect. Each SETx always will be read as a 0. 7, 15, 23, 31 Clear Flag Bits CLR[0:7] CLRx is the flag bit. Writing a 1 to CLRx clears it provided that a 1 is not written simultaneously to its corresponding SETx bit. Writing a 0 to CLRx has no effect. 0 Interrupt request not pending within INTC 1 Interrupt request pending within INTC
The software set/clear interrupt registers support the setting or clearing of software configurable interrupt request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. Excepting being set by software, this flag bit behaves the same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC like a peripheral interrupt request. Writing a 1 to SETx will leave SETx unchanged at 0 but sets CLRx. Writing a 0 to SETx has no effect. CLRx is the flag bit. Writing a 1 to CLRx clears it. Writing a 0 to CLRx has no effect. If a 1 is written simultaneously to a pair of SETx and CLRx bits, CLRx will be asserted, regardless of whether CLRx was asserted before the write.
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Chapter 14 Interrupt Controller (INTC)
14.5.2.6
INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR152_154)
Access: User read/write
1 0 2 0 3 0 4 5 PRI0 6 7 8 0 9 0 10 0 11 0 12 13 PRI1 14 15
Offset: 0x0040
0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17 0
18 0
19 0
20
21 PRI2
22
23
24 0
25 0
26 0
27 0
28
29 PRI3
30
31
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-8. INTC Priority Select Register 0–3 (INTC_PSR[0:3])
Offset: 0x0D8C
0 1 0 2 0 3 0 4 5 6 7 8 0 9 0 10 0 11 0
Access: User read/write
12 13 14 15
R W Reset
0
PRI152
PRI153
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17 0
18 0
19 0
20
21
22
23
24 0
25 0
26 0
27 0
28 0
29 0
30 0
31 0
R W Reset
0
PRI154
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-9. INTC Priority Select Register 152-154 (INTC_PSR[152:154]) Table 14-8. INTC_PSR0_3–INTC_PSR152_154 field descriptions
Field Description
4–7, 12–15, Priority Select 20–23, PRIx selects the priority for interrupt requests. Refer to Section 14.6, “Functional description. 28–31 PRI[0:3]– PRI152:154
Table 14-9. INTC Priority Select Register Address Offsets
INTC_PSRx_x INTC_PSR0_3 INTC_PSR4_7 Offset address 0x0040 0x0044 INTC_PSRx_x INTC_PSR80_83 INTC_PSR84_87 Offset address 0x0090 0x0094
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Table 14-9. INTC Priority Select Register Address Offsets (continued)
INTC_PSRx_x INTC_PSR8_11 INTC_PSR12_15 INTC_PSR16_19 INTC_PSR20_23 INTC_PSR24_27 INTC_PSR28_31 INTC_PSR32_35 INTC_PSR36_39 INTC_PSR40_43 INTC_PSR44_47 INTC_PSR48_51 INTC_PSR52_55 INTC_PSR56_59 INTC_PSR60_63 INTC_PSR64_67 INTC_PSR68_71 INTC_PSR72_75 INTC_PSR76_79 Offset address 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C INTC_PSRx_x INTC_PSR88_91 INTC_PSR92_95 INTC_PSR96_99 INTC_PSR100_103 INTC_PSR104_107 INTC_PSR108_111 INTC_PSR112_115 INTC_PSR116_119 INTC_PSR120_123 INTC_PSR124_127 INTC_PSR128_131 INTC_PSR132_135 INTC_PSR136_139 INTC_PSR140_143 INTC_PSR144_147 INTC_PSR148_151 INTC_PSR152_154 Offset address 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8
14.6
Functional description
The functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor.
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NOTE The INTC has no spurious vector support. Therefore, if an asserted peripheral or software settable interrupt request, whose PRIn value in INTC_PSR0–INTC_PSR154 is higher than the PRI value in INTC_CPR, negates before the interrupt request to the processor for that peripheral or software settable interrupt request is acknowledged, the interrupt request to the processor still can assert or will remain asserted for that peripheral or software settable interrupt request. In this case, the interrupt vector will correspond to that peripheral or software settable interrupt request. Also, the PRI value in the INTC_CPR will be updated with the corresponding PRIn value in INTC_PSRn. Furthermore, clearing the peripheral interrupt request’s enable bit in the peripheral or, alternatively, setting its mask bit has the same consequences as clearing its flag bit. Setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC as an interrupt event setting the flag bit.
Table 14-10. Interrupt vector table
IRQ # Offset Size (bytes) Interrupt Section A (Core Section) — — — — — — — — — — — — 0x0000 0x0010 0x0020 0x0030 0x0040 0x0050 0x0060 0x0070 0x0080 0x0090 0x00F0 0x0100 16 16 16 16 16 16 16 16 16 96 16 1792 Critical Input (INTC software vector mode) / NMI Machine check / NMI Data Storage Instruction Storage External Input (INTC software vector mode) Alignment Program Reserved System call Unused Debug Unused Core Core Core Core Core Core Core Core Core Core Core Core Section B (On-Platform Peripherals) 0 1 2 3 4 0x0800 0x0804 0x0808 0x080C 0x0810 4 4 4 4 4 Software configurable flag 0 Software configurable flag 1 Software configurable flag 2 Software configurable flag 3 Software configurable flag 4 Software Software Software Software Software Module
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Table 14-10. Interrupt vector table (continued)
IRQ # 5 6 7 8 9 Offset 0x0814 0x0818 0x081C 0x0820 0x0824 Size (bytes) 4 4 4 4 4 Platform Flash Bank 0 Abort | Platform Flash Bank 0 Stall | Platform Flash Bank 1 Abort | Platform Flash Bank 1 Stall | Combined Error Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Interrupt Software configurable flag 5 Software configurable flag 6 Software configurable flag 7 Software Software Software Reserved ECSM Module
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
0x0828 0x082C 0x0830 0x0834 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C 0x0850 0x0854 0x0858 0x085C 0x0860 0x0864 0x0868 0x086C 0x0870 0x0874 0x0878 0x087C 0x0880 0x0884 0x0888
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA eDMA Reserved
Timeout
Software Watchdog (SWT) Reserved
Match on channel 0 Match on channel 1 Match on channel 2 Match on channel 3
STM STM STM STM Reserved
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Table 14-10. Interrupt vector table (continued)
IRQ # 35 36 37 Offset 0x088C 0x0890 0x0894 Size (bytes) 4 4 4 Section C 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0x0898 0x089C 0x08A0 0x08A4 0x08A8 0x08AC 0x08B0 0x08B4 0x08B8 0x08BC 0x08C0 0x08C4 0x08C8 0x08CC 0x08D0 0x08D4 0x08D8 0x08DC 0x08E0 0x08E4 0x08E8 0x08EC 0x08F0 0x08F4 0x08F8 0x08FC 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PITimer Channel 0 PITimer Channel 1 PITimer Channel 2 Safe Mode Interrupt Mode Transition Interrupt Invalid Mode Interrupt Invalid Mode Config WakeUp_IRQ_0 WakeUp_IRQ_1 WakeUp_IRQ_2 WakeUp_IRQ_3 SIU External IRQ_0 SIU External IRQ_1 SIU External IRQ_2 RTC API Real Time Counter (RTC/API) Real Time Counter (RTC/API) Reserved System Integration Unit Lite (SIUL) System Integration Unit Lite (SIUL) System Integration Unit Lite (SIUL) Reserved Reserved WakeUp Unit (WKUP) WakeUp Unit (WKUP) WakeUp Unit (WKUP) WakeUp Unit (WKUP) Reserved MC_ME MC_ME MC_ME MC_ME Reserved Functional and destructive reset alternate MC_RGM event interrupt (ipi_int) FXOSC counter expired (ipi_int_osc) FXOSC Reserved Periodic Interrupt Timer (PIT) Periodic Interrupt Timer (PIT) Periodic Interrupt Timer (PIT) Reserved Reserved Interrupt ECC_DBD_PlatformFlash | ECC_DBD_PlatformRAM ECC_SBC_PlatformFlash | ECC_SBC_PlatformRAM Module Platform ECC Double Bit Detection Platform ECC Single Bit Correction Reserved
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Table 14-10. Interrupt vector table (continued)
IRQ # 64 65 66 Offset 0x0900 0x0904 0x0908 Size (bytes) 4 4 4 FlexCAN_ESR[ERR_INT] FlexCAN_ESR_BOFF | FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning Interrupt Reserved FlexCAN_0 (CAN0) FlexCAN_0 (CAN0) Module
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
0x090C 0x0910 0x0914 0x0918 0x091C 0x0920 0x0924 0x0928 0x092C 0x0930 0x0934 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C 0x0950 0x0954 0x0958 0x095C 0x0960 0x0964 0x0968 0x096C 0x0970 0x0974
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 DSPI_SR[TFUF] DSPI_SR[RFOF] DSPI_SR[EOQF] DSPI_SR[TFFF] DSPI_SR[TCF] DSPI_SR[RFDF] LINFlex_RXI LINFlex_TXI LINFlex_ERR ADC_EOC ADC_ER ADC_WD FlexCAN_BUF_00_03 FlexCAN_BUF_04_07 FlexCAN_BUF_08_11 FlexCAN_BUF_12_15 FlexCAN_BUF_16_31
Reserved FlexCAN_0 (CAN0) FlexCAN_0 (CAN0) FlexCAN_0 (CAN0) FlexCAN_0 (CAN0) FlexCAN_0 (CAN0) Reserved DSPI_0 DSPI_0 DSPI_0 DSPI_0 DSPI_0 LINFlex_0 LINFlex_0 LINFlex_0 Analog to Digital Converter 1(ADC_1) Analog to Digital Converter 1(ADC_1) Analog to Digital Converter 1(ADC_1) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Table 14-10. Interrupt vector table (continued)
IRQ # 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 Offset 0x0978 0x097C 0x0980 0x0984 0x0988 0x098C 0x0990 0x0994 0x0998 0x099C 0x09A0 0x09A4 0x09A8 0x09AC 0x09B0 0x09B4 0x09B8 0x09BC 0x09C0 0x09C4 0x09C8 0x09CC 0x09D0 0x09D4 0x09D8 0x09DC 0x09E0 0x09E4 0x09E8 0x09EC 0x09F0 Size (bytes) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LINFlex_RXI LINFlex_TXI LINFlex_ERR Interrupt DSPI_SR[TFUF] DSPI_SR[RFOF] DSPI_SR[EOQF] DSPI_SR[TFFF] DSPI_SR[TCF] DSPI_SR[RFDF] LINFlex_RXI LINFlex_TXI LINFlex_ERR DSPI_1 DSPI_1 DSPI_1 DSPI_1 DSPI_1 LINFlex_1 LINFlex_1 LINFlex_1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LINFlex_2 LINFlex_2 LINFlex_2 Reserved Reserved Reserved Module
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Table 14-10. Interrupt vector table (continued)
IRQ # 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Offset 0x09F4 0x09F8 0x09FC 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 0x0A14 0x0A18 0x0A1C 0x0A20 0x0A24 0x0A28 0x0A2C 0x0A30 0x0A34 0x0A38 0x0A3C 0x0A40 0x0A44 0x0A48 0x0A4C 0x0A50 0x0A54 0x0A58 Size (bytes) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 EMIOS_GFR[F0,F1] EMIOS_GFR[F2,F3] EMIOS_GFR[F4,F5] EMIOS_GFR[F6,F7] EMIOS_GFR[F8,F9] EMIOS_GFR[F10,F11] EMIOS_GFR[F12,F13] EMIOS_GFR[F14,F15] EMIOS_GFR[F16,F17] EMIOS_GFR[F18,F19] PITimer Channel 3 Interrupt Reserved Reserved Periodic Interrupt Timer (PIT) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Module
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Table 14-10. Interrupt vector table (continued)
IRQ # 151 152 153 154 Offset 0x0A5C 0x0A60 0x0A64 0x0A68 Size (bytes) 4 4 4 4 Interrupt EMIOS_GFR[F20,F21] EMIOS_GFR[F22,F23] EMIOS_GFR[F24,F25] EMIOS_GFR[F26,F27] Module Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0) Enhanced Modular I/O Subsystem 0 (eMIOS_0)
14.6.1
Interrupt request sources
The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt requests can assert on any clock cycle.
14.6.1.1
Peripheral interrupt requests
An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt request from the peripheral is driven by that flag bit. The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time that the INTC starts to drive the interrupt request to the processor is three clocks. External interrupts are handled by the SIU (see Section 15.6.3, “External interrupts).
14.6.1.2
Software configurable interrupt requests
An interrupt request is triggered by software by writing a 1 to a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the interrupt request. The interrupt request is cleared by writing a 1 to the CLRx bit. The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks.
14.6.1.3
Unique vector for each interrupt request source
Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector. Software configurable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. The peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired vectors within the INTC (see Table 14-1).
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14.6.2
Priority management
The asserted interrupt requests are compared to each other based on their PRIx values set in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR152_154). The result is compared to PRI in the associated INTC_CPR. The results of those comparisons manage the priority of the ISR executed by the associated processor. The associated LIFO also assists in managing that priority.
14.6.2.1
Current priority and preemption
The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 14-1 compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or software configurable interrupt request is higher than the current priority for a given processor, then the interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or software configurable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor. 14.6.2.1.1 Priority arbitrator subblock
The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt requests assigned to that processor, both peripheral and software configurable. The output of the priority arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the associated request selector subblock. 14.6.2.1.2 Request selector subblock
If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated priority arbitrator subblock are asserted, the only the one with the lowest vector is passed as asserted to the associated vector encoder subblock. The lower vector is chosen regardless of the time order of the assertions of the peripheral or software configurable interrupt requests. 14.6.2.1.3 Vector encoder subblock
The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the request selector subblock for the associated processor. 14.6.2.1.4 Priority Comparator subblock
The priority comparator subblock compares the highest priority output from the priority arbitrator subblock with PRI in INTC_CPR. If the priority comparator subblock detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the associated processor. This interrupt request to the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or the PRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the new priority which will be written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a preemption because their PRIn will not be higher than PRI in INTC_CPR.
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14.6.2.2
Last-In First-Out (LIFO)
The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the INTC_CPR. The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in softwarevector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written. Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 will not be preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO will pop ‘0’s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty LIFO. The LIFO is not memory mapped.
14.6.3
14.6.3.1
Handshaking with processor
Software vector mode handshaking
This section describes handshaking in software vector mode. 14.6.3.1.1 Acknowledging interrupt request to processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 14-10. The INTC examines the peripheral and software configurable interrupt requests. When it finds an asserted peripheral or software configurable interrupt request with a higher priority than PRI in the associated INTC_CPR, it asserts the interrupt request to the processor. The INTVEC field in the associated INTC_IACKR is updated with the preempting interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The rest of the handshaking is described in Section 14.4.1.1, “Software vector mode. 14.6.3.1.2 End of interrupt exception handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be written.When written, the associated LIFO is popped so the preempted priority is restored into PRI of the INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configurable interrupt request is negated.
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NOTE To ensure proper operation across all eSys MCUs, execute an MBAR or MSYNC instruction between the access to clear the flag bit and the write to the INTC_EOIR. When returning from the preemption, the INTC does not search for the peripheral or software settable interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt request may no longer even be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration of the preempted context, the processor will return to the instruction address that it was to next execute before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog.
Clock
Interrupt request to processor Hardware vector enable Interrupt vector Interrupt acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR PRI in INTC_CPR Peripheral interrupt request 100 0 0 108 1 0 0
Figure 14-10. Software vector mode handshaking timing diagram
14.6.3.2
Hardware vector mode handshaking
A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 14-11. As in software vector mode, the INTC examines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request to the processor. The INTVEC field in the INTC_IACKR is updated with the preempting peripheral or software settable interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. In
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addition, the value of the interrupt vector to the processor matches the value of the INTVEC field in the INTC_IACKR. The rest of the handshaking is described in Section 14.7.2.2, “Hardware vector mode. The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 14.6.3.1.2, “End of interrupt exception handler.
Clock
Interrupt request to processor Hardware vector enable Interrupt vector Interrupt acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR PRI in INTC_CPR Peripheral interrupt request 100 0 0 108 1 0 0 108
Figure 14-11. Hardware vector mode handshaking timing diagram
14.7
14.7.1
Initialization/application information
Initialization flow
After exiting reset, all of the PRIn fields in INTC priority select registers (INTC_PSR0–INTC_PSR154) will be zero, and PRI in INTC current priority register (INTC_CPR) will be 15. These reset values will prevent the INTC from asserting the interrupt request to the processor. The enable or mask bits in the peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is:interrupt_request_initialization:
interrupt_request_initialization: configure VTES and HVEN in INTC_MCR configure VTBA in INTC_IACKR raise the PRIn fields in INTC_PSRn set the enable bits or clear the mask bits for the peripheral interrupt requests lower PRI in INTC_CPR to zero enable processor recognition of interrupts
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14.7.2
Interrupt exception handler
These example interrupt exception handlers use Power Architecture™ assembly code.
14.7.2.1
Software vector mode
interrupt_exception_handler: code to create stack frame, save working register, and save SRR0 and SRR1 lis r3,INTC_IACKR@ha # form adjusted upper half of INTC_IACKR address lwz r3,INTC_IACKR@l(r3) # load INTC_IACKR, which clears request to processor lwz r3,0x0(r3) # load address of ISR from vector table wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 EABI mtlr blrl r3 # move INTC_IACKR contents into link register # branch to ISR; link register updated with epilog # address
epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei 0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi
vector_table_base_address: address of ISR for interrupt address of ISR for interrupt . . . address of ISR for interrupt address of ISR for interrupt
with vector 0 with vector 1
with vector 510 with vector 511
ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr # return to epilog
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14.7.2.2
Hardware vector mode
This interrupt exception handler is useful with processor and system bus implementations which support a hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed.
interrupt_exception_handlerx: b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue interrupt_exception_handler_continuedx: code to create stack frame, save working register, and save SRR0 and SRR1 wrteei 1 # enable processor recognition of interrupts
code to save rest of context required by e500 EABI bl ISRx # branch to ISR for interrupt with vector x
epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei 0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr # branch to epilog
14.7.3
ISR, RTOS, and task hierarchy
The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register (INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority scheme that it may have, but that priority scheme is independent and has a lower priority of execution than the priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0. If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed. An ISR whose PRIn in INTC priority select registers (INTC_PSR0–INTC_PSR154) has a value of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request
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is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause it to remain negated, which consequently also will not cause an interrupt request to the processor. Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR.
14.7.4
Order of execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors associated with each of their peripheral or software configurable interrupt requests. However, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software configurable interrupt requests asserted. The example in Table 14-11 shows the order of execution of both ISRs with different priorities and the same priority.
Table 14-11. Order of ISR execution example
PRI in INTC_CPR Interrupt at End of RTOS ISR1081 ISR208 ISR308 ISR408 exception Step handler X X X X X X 0 1 4 4 4 1 Code Executing at End of Step
Step No.
Step description
1 2 3 4 5 6
RTOS at priority 0 is executing. Peripheral interrupt request 100 at priority 1 asserts. Interrupt taken. Peripheral interrupt request 400 at priority 4 is asserts. Interrupt taken. Peripheral interrupt request 300 at priority 3 is asserts. Peripheral interrupt request 200 at priority 3 is asserts. ISR408 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR208 starts to execute, even though peripheral interrupt request 300 asserted first. ISR208 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR308 starts to execute.
7
X
3
8
X
1
9
X
3
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Table 14-11. Order of ISR execution example (continued)
PRI in INTC_CPR Interrupt at End of RTOS ISR1081 ISR208 ISR308 ISR408 exception Step handler X 1 Code Executing at End of Step
Step No.
Step description
10
ISR308 completes. Interrupt exception handler writes to INTC_EOIR. ISR108 completes. Interrupt exception handler writes to INTC_EOIR. RTOS continues execution. X
11
X
0
12
1
0
ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable interrupt requests.
14.7.5
14.7.5.1
Priority ceiling protocol
Elevating priority
The PRI field in INTC_CPR is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This protocol allows coherent accesses of the ISRs to that shared resource. For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They share the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI value in INTC_CPR can be lowered. If they do not raise their priority, ISR2 can preempt ISR1, and ISR3 can preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is deadlock if the higher priority ISR needs the lower priority ISR to release the resource before it can continue, but the lower priority ISR cannot release the resource until the higher priority ISR completes and execution returns to the lower priority ISR. Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can preempt ISR1.
14.7.5.2
Ensuring coherency
A scenario can cause non-coherent accesses to the shared resource. For example, ISR1 and ISR2 are both running on the same core and both share a resource. ISR1 has a lower priority than ISR2. ISR1 is executing and writes to the INTC_CPR. The instruction following this store is a store to a value in a shared coherent data block. Either immediately before or at the same time as the first store, the INTC asserts the interrupt request to the processor because the peripheral interrupt request for ISR2 has asserted. As the processor is responding to the interrupt request from the INTC, and as it is aborting transactions and flushing its
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pipeline, it is possible that both stores will be executed. ISR2 thereby thinks that it can access the data block coherently, but the data block has been corrupted. OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource. To prevent corruption of a coherent data block, modifications to PRI in INTC_CPR can be made by those system services with the code sequence:
disable processor recognition of interrupts PRI modification enable processor recognition of interrupts
14.7.6
Selecting priorities according to request rates and deadlines
The selection of the priorities for the ISRs can be made using rate monotonic scheduling (RMS) or a superset of it, deadline monotonic scheduling (DMS). In RMS, the ISRs which have higher request rates have higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is assigned a priority according to the time from the request for the ISR to the deadline, not from the time of the request for the ISR to the next request for it. For example, ISR1 executes every 100 µs, ISR2 executes every 200 µs, and ISR3 executes every 300 µs. ISR1 has a higher priority than ISR2 which has a higher priority than ISR3; however, if ISR3 has a deadline of 150 µs, then it has a higher priority than ISR2. The INTC has 16 priorities, which may be less than the number of ISRs. In this case, the ISRs should be grouped with other ISRs that have similar deadlines. For example, a priority could be allocated for every time the request rate doubles. ISRs with request rates around 1 ms would share a priority, ISRs with request rates around 500 µs would share a priority, ISRs with request rates around 250 µs would share a priority, etc. With this approach, a range of ISR request rates of 216 could be included, regardless of the number of ISRs. Reducing the number of priorities reduces the processor’s ability to meet its deadlines. However, reducing the number of priorities can reduce the size and latency through the interrupt controller. It also allows easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP to access the shared resource.
14.7.7
Software configurable interrupt requests
The software configurable interrupt requests can be used in two ways. They can be used to schedule a lower priority portion of an ISR and they may also be used by processors to interrupt other processors in a multiple processor system.
14.7.7.1
Scheduling a lower priority portion of an ISR
A portion of an ISR needs to be executed at the PRIx value in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR152_154), which becomes the PRI value in INTC_CPR with the interrupt acknowledge. The ISR, however, can have a portion that does not need to be executed at this higher priority. Therefore, executing the later portion that does not need to be executed at this higher priority can prevent the execution of ISRs which do not have a higher priority than the earlier portion of the ISR but
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do have a higher priority than what the later portion of the ISR needs. This preemptive scheduling inefficiency reduces the processor’s ability to meet its deadlines. One option is for the ISR to complete the earlier higher priority portion, but then schedule through the RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher priority portion, to set a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. Writing a 1 to SETx causes a software configurable interrupt request. This software configurable interrupt request will usually have a lower PRIx value in the INTC_PSRx_x and will not cause preemptive scheduling inefficiencies. After generating a software settable interrupt request, the higher priority ISR completes. The lower priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the completion of the lower priority ISR.
14.7.7.2
Scheduling an ISR on another processor
Because the SETx bits in the INTC_SSCIRx_x are memory mapped, processors in multiple-processor systems can schedule ISRs on the other processors. One application is that one processor wants to command another processor to perform a piece of work and the initiating processor does not need to use the results of that work. If the initiating processor is concerned that the processor executing the software configurable ISR has not completed the work before asking it to again execute the ISR, it can check if the corresponding CLRx bit in INTC_SSCIRx_x is asserted before again writing a 1 to the SETx bit. Another application is the sharing of a block of data. For example, a first processor has completed accessing a block of data and wants a second processor to then access it. Furthermore, after the second processor has completed accessing the block of data, the first processor again wants to access it. The accesses to the block of data must be done coherently. To do this, the first processor writes a 1 to a SETx bit on the second processor. After accessing the block of data, the second processor clears the corresponding CLRx bit and then writes 1 to a SETx bit on the first processor, informing it that it can now access the block of data.
14.7.8
Lowering priority within an ISR
A common method for avoiding preemptive scheduling inefficiencies with an ISR whose work spans multiple priorities (see Section 14.7.7.1, “Scheduling a lower priority portion of an ISR) is to lower the current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities. NOTE Lowering the PRI value in INTC_CPR within an ISR to below the ISR’s corresponding PRI value in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR152_154) allows more preemptions than the LIFO depth can support. Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid preemptive scheduling inefficiencies.
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14.7.9
14.7.9.1
Negating an interrupt request outside of its ISR
Negating an interrupt request as a side effect of an ISR
Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt request. For example, reading a specific register can clear the flag bits and their corresponding interrupt requests. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect.
14.7.9.2
Negating multiple interrupt requests in one ISR
An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed.
14.7.9.3
Proper setting of interrupt request priority
Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. Their PRIx values in the INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR152_154) must be selected to be at or lower than the priority of the ISR that cleared their flag bits. Otherwise, those flag bits can cause the interrupt request to the processor to assert. Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to INTC_SSCIR0_3–INTC_SSCIR4_7 as the clearing of the flag bit that caused the present ISR to be executed (see Section 14.6.3.1.2, “End of interrupt exception handler). A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be cleared at any time, regardless of the peripheral interrupt request’s PRIx value in INTC_PSRx_x.
14.7.10 Examining LIFO contents
In normal mode, the user does not need to know the contents of the LIFO. He may not even know how deeply the LIFO is nested. However, if he wants to read the contents, such as in debug mode, they are not memory mapped. The contents can be read by popping the LIFO and reading the PRI field in either INTC_CPR. The code sequence is:
pop_lifo: store to INTC_EOIR load INTC_CPR, examine PRI, and store onto stack if PRI is not zero or value when interrupts were enabled, branch to pop_lifo
When the examination is complete, the LIFO can be restored using this code sequence:
push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo
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Chapter 15 System Integration Unit Lite (SIUL)
Chapter 15 System Integration Unit Lite (SIUL)
15.1 Introduction
This chapter describes the System Integration Unit Lite (SIUL), which is used for the management of the pads and their configuration. It controls the multiplexing of the alternate functions used on all pads as well as being responsible for the management of the external interrupts to the device.
15.2
Overview
The System Integration Unit Lite (SIUL) controls the MCU pad configuration, ports, general-purpose input and output (GPIO) signals and external interrupts with trigger event configuration. Figure 15-1 provides a block diagram of the SIUL and its interfaces to other system components. The module provides the capability to configure, read, and write to the device’s general-purpose I/O pads that can be configured as either inputs or outputs. • When a pad is configured as an input, the state of the pad (logic high or low) is obtained by reading an associated data input register. • When a pad is configured as an output, the value driven onto the pad is determined by writing to an associated data output register. Enabling the input buffers when a pad is configured as an output allows the actual state of the pad to be read. • To enable monitoring of an output pad value, the pad can be configured as both output and input so the actual pad value can be read back and compared with the expected value.
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SIUL Module Pad Configuration (IOMUXC) Pad Config (PCRs)
79 (1)
GPIO Functionality Data
79 (1)
IO MUX
79 (1)
Pads
79 (1)
Pad Input IPS Master
Interrupt Functionality
20 (2)
Interrupt - Configuration - Glitch Filter IPS BUS
Interrupt Controller
3
Notes: 1 Up to 45 I/O pins in 64-pin packages; up to 79 I/O pins in 100-pin packages 2 Up to 11 I/O pins in 64-pin packages; up to 20 I/O pins in 100-pin packages
Figure 15-1. System Integration Unit Lite block diagram
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15.3
Features
The System Integration Unit Lite supports these distinctive features: • GPIO — GPIO function on up to 79 I/O pins — Dedicated input and output registers for most GPIO pins1 • External interrupts — 3 interrupt vectors dedicated to 20 external interrupts — 24 programmable digital glitch filters — Independent interrupt mask — Edge detection • System configuration — Pad configuration control
15.4
External signal description
Most device pads support multiple device functions. Pad configuration registers are provided to enable selection between GPIO and other signals. These other signals, also referred to as alternate functions, are typically peripheral functions. GPIO pads are grouped in “ports”, with each port containing up to 16 pads. With appropriate configuration, all pins in a port can be read or written to in parallel with a single R/W access. NOTE In order to use GPIO port functionality, all pads in the port must be configured as GPIO rather than as alternate functions. Table 15-1 lists the external pins configurable via the SIUL.
(
Table 15-1. SIUL signal properties
GPIO[0:122]1 category System configuration Name GPIO [0:19] [26:47] [60:76] [121:122] GPIO [20:25] [48:59] External interrupt PA[3], PA[6:8], PA[11:12], PA[14], PC[2:5], PC[12], PC[14:15], PE[2], PE[4], PE[6:7], PE[10], PE[12]2 I/O direction Function
Input/Output General-purpose input/output Input Input Analog precise channels, low power oscillator pins Pins with External Interrupt Request functionality. Please refer to the signal description chapter of this reference manual for details.
1 2
GPIO[77:120] not available in MPC5602D; GPIO[43:120] not available in 64-pin LQFP PC[12], PC[14:15], PE[2], PE[4], PE[6:7], PE[10] and PE[12] not available in 64-pin
1.Some device pins, e.g., analog pins, do not have both input and output functionality.
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15.4.1
15.4.1.1
Detailed signal descriptions
General-purpose I/O pins (GPIO[0:122])1
The GPIO pins provide general-purpose input and output function. The GPIO pins are generally multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input (GPDIn_n) or output (GPDOn_n) register.
15.4.1.2
External interrupt request input pins (EIRQ[0:23])2
The EIRQ[0:23] pins are connected to the SIUL inputs. Rising- or falling-edge events are enabled by setting the corresponding bits in the SIUL_IREER or the SIUL_IFEER register.
1. GPIO[0–76] and GPIO[121–122] in 100-pin LQFP; GPIO[0–43] and GPIO[121–122] in 64-pin LQFP 2. EIRQ[0:11] plus EIRQ[16:23] in 100-pin LQFP; EIRQ[0:7] plus EIRQ[16:18] in 64-pin LQFP MPC5602D Microcontroller Reference Manual, Rev. 3.1 426 Preliminary Freescale Semiconductor
Chapter 15 System Integration Unit Lite (SIUL)
15.5
Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
15.5.1
SIUL memory map
Table 15-2. SIUL memory map
Register address Register name Reserved MCU ID Register #1 (MIDR1) MCU ID Register #2 (MIDR2) Reserved Interrupt Status Flag Register (ISR) Interrupt Request Enable Register (IRER) Reserved Interrupt Rising-Edge Event Enable Register (IREER) Interrupt Falling-Edge Event Enable Register (IFEER) Interrupt Filter Enable Register (IFER) Reserved Size (bits) — 32 32 — 32 32 — 32 32 32 — 16 — 32 — 32 — 32 — 32 — 32 — 32 — Location — on page 429 on page 430 — on page 431 on page 432 — on page 432 on page 433 on page 434 — on page 435 — on page 437 — on page 440 — on page 441 — on page 441 — on page 442 — on page 443 —
Table 15-2 gives an overview of the SIUL registers implemented.
Base (0xC3F9_0000) Base + 0x0004 Base + 0x0008 Base + (0x000C–0x0013) Base + 0x0014 Base + 0x0018 Base + (0x001C–0x0027) Base + 0x0028 Base + 0x002C Base + 0x0030 Base + (0x0034–0x003F)
Base + 0x0040–Base + 0x0134 Pad Configuration Registers (PCR0–PCR122)1 Base + (0x0136–0x04FF) Reserved
Base + 0x0500–Base + 0x053C Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63) Base + (0x0540–0x05FF) Reserved
Base + 0x0600–Base + 0x0678 GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123)2 Base + (0x067C–0x07FF) Reserved
Base + 0x0800–Base + 0x0878 GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123)3,4 Base + (0x087C–0x0BFF) Reserved
Base + 0x0C00–Base + 0x0C0C Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3) Base + (0x0C10–0x0C3F) Reserved
Base + 0x0C40–Base + 0x0C4C Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI3) Base + (0x0C50–0x0C7F) Reserved
Base + 0x0C80–Base + 0x0C9C Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO7) Base + (0x0CA0–0x0FFF) Reserved
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Table 15-2. SIUL memory map (continued)
Register address Register name Size (bits) 32 — 32 — Location on page 445 — on page 446 —
Base + 0x1000–Base + 0x105C Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23)5 Base + (0x1060–0x107C) Base + 0x1080 Base + (0x1084–0x3FFF)
1 2 3
Reserved Interrupt Filter Clock Prescaler Register (IFCPR) Reserved
4 5
PCR[0:76] and PCR[121:122] is valid in 100-pin LQFP package, while in the 64-pin LQFP package is PCR[0:43] and PCR[121:122], so all the remaining registers are reserved. GPDO[0:76] and GPDO[121:122] is valid in 100-pin LQFP package, while in the 64-pin LQFP package is GPDO[0:43] and GPDO[121:122], so all the remaining registers are reserved. Not all registers are used. The registers, although byte-accessible are allocated on 32-bit boundaries. There are some unused registers at the end of the space. The number of unused registers is further reduced in packages with reduced GPIO pin count. GPDI0[0:76] and GPDI0[121:122] is valid in 100-pin LQFP package, while in the 64-pin LQFP package is GPDI0[0:43] and GPDI0[121:122], so all the remaining registers are reserved. IFMC[0:11] plus IFMC[16:23] in 100-pin LQFP, while in the 64-pin LQFP package is IFMC[0:7] plus IFMC[16:18]—all remaining registers are reserved.
NOTE A transfer error will be issued when trying to access completely reserved register space.
15.5.2
Register protection
Individual registers in System Integration Unit Lite can be protected from accidental writes using the Register Protection module. The following registers can be protected: • Interrupt Request Enable Register (IRER) • Interrupt Rising-Edge Event Enable Register (IREER) • Interrupt Falling-Edge Event Enable Register (IFEER) • Interrupt Filter Enable Register (IFER), • Pad Configuration Registers (PCR0–PCR122). Note that only the following registers can be protected: — PCR[0:15] (Port A) — PCR[16:19] (Port B[0:3]) — PCR[34:47] (Port C[2:15]) • Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63) • Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23). Note that only IFMC[0:15] can be protected. • Interrupt Filter Clock Prescaler Register (IFCPR) Refer to Appendix A, “Register Under Protection for more details.
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15.5.3
Register description
This section describes in address order all the SIUL registers. Each description includes a standard register diagram. Details of register bit and field function follow the register diagrams, in bit order. The numbering convention of the registers is MSB = 0, however the numbering of the internal fields is LSB = 0, for example, PARTNUM[5] = MIDR1[10].
Always reads 1 1 Always reads 0 0 R/W BIT bit only bit only bit BIT to clear ReadBIT WriteWrite 1 BIT w1 c Selfclear bit 0 BIT N/A
Figure 15-2. Key to register fields
15.5.3.1
MCU ID Register #1 (MIDR1)
This register holds identification information about the device.
Address: Base + 0x0004 0 R W Reset 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Access: None 14 15
PARTNUM[15:0]
16 R CSP W Reset 0
17
18
19 PKG[4:0]
20
21
22
23
24
25
26
27
28
29
30
31
MAJOR_MASK[3:0]
MINOR_MASK[3:0]
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
Figure 15-3. MCU ID Register #1 (MIDR1) Table 15-3. MIDR1 field descriptions
Field PARTNUM[15:0] Description MCU Part Number Device part number of the MCU. 0101_0110_0000_0001 (5601):128 KB 0101_0110_0000_0010 (5602): 256 KB (5603) (5604) (5605) (5606) (5607)For the full part number this field needs to be combined with MIDR2.PARTNUM[23:16] Always reads back 0 Package Settings Can be read by software to determine the package type that is used for the particular device: 0b00001: 64-pin LQFP 0b01001: 100-pin LQFP
CSP PKG[4:0]
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Table 15-3. MIDR1 field descriptions
Field MAJOR_MASK[3:0] MINOR_MASK[3:0] Description Major Mask Revision Counter starting at 0x0. Incremented each time there is a resynthesis. Minor Mask Revision Counter starting at 0x0. Incremented each time a mask change is done.
15.5.3.2
MCU ID Register #2 (MIDR2)
Access: None 3 4 5 6 7 8 9 10 11 12 13 14 15
Address: Base + 0x0008 0 R W Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 SF 1 2
FLASH_SIZE_1[3:0]
FLASH_SIZE_2[3:0]
0
0
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27 EE
28
29
30
31
PARTNUM[23:16]
1
0
0
0
1
0
0
0
0
0
1
01
01
01
0
Figure 15-4. MCU ID Register #2 (MIDR2)
1
Static bit fixed in hardware
Table 15-4. MIDR2 field descriptions
Field SF Manufacturer 0: Freescale 1:Reserved Description
FLASH_SIZE_1 Coarse granularity for Flash memory size [3:0] Needs to be combined with FLASH_SIZE_2 to calculate the actual memory size. 0b0011: 128 KB 0b0100: 256 KB 0b0101: 512 KB FLASH_SIZE_2 Fine granularity for Flash memory size [3:0] Needs to be combined with FLASH_SIZE_1 to calculate the actual memory size. 0b0000: 0 x (FLASH_SIZE_1 / 8) 0b0010: 2 x (FLASH_SIZE_1 / 8) 0b0100: 4 x (FLASH_SIZE_1 / 8) PARTNUM [23:16] ASCII character in MCU Part Number 0x44h: Character ‘D’ For the full part number this field needs to be combined with MIDR1.PARTNUM[15:0]
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Table 15-4. MIDR2 field descriptions
Field EE Data Flash present 0: No Data Flash is present 1: Data Flash is present FlexRay present 0: No FlexRay is present 1: FlexRay is present Description
FR
15.5.3.3
Interrupt Status Flag Register (ISR)
This register holds the interrupt flags.
Address: Base + 0x0014 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 Access: User read/write (write 1 to clear) 10 11 12 13 14 15
EIF[23:16]1 w1c 0 0 0 0
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
EIF[11:0]1 w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-5. Interrupt Status Flag Register (ISR)
1
20 flags in 100-pin LQFP; 11 flags in 64-pin LQFP: EIF[18:16] plus EIF[7:0] (register bits 8-12 and 20–23 reserved).
Table 15-5. ISR field descriptions
Field EIF[x] Description External Interrupt Status Flag x This flag can be cleared only by writing a ‘1’. Writing a ‘0’ has no effect. If enabled (IRER[x]), EIF[x] causes an interrupt request. 0: No interrupt event has occurred on the pad 1: An interrupt event as defined by IREER[x] and IFEER[x] has occurred
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15.5.3.4
Interrupt Request Enable Register (IRER)
This register is used to enable the interrupt messaging to the interrupt controller.
Address: Base + 0x0018 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 Access: User read/write 12 13 14 15
IRE[23:16]1
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
1
27
28
29
30
31
IRE[11:0] w1c 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
Figure 15-6. Interrupt Request Enable Register (IRER)
1
20 enable requests in 100-pin LQFP; 11 enable requests in 64-pin LQFP: IRE[18:16] plus IRE[7:0] (register bits 8-12 and 20–23 reserved).
Table 15-6. IRER field descriptions
Field IRE[x] Description External Interrupt Request Enable x 0: Interrupt requests from the corresponding ISR.EIF[x] bit are disabled. 1: Interrupt requests from the corresponding ISR.EIF[x] bit are enabled.
15.5.3.5
Interrupt Rising-Edge Event Enable Register (IREER)
This register is used to enable rising-edge triggered events on the corresponding interrupt pads.
Address: Base + 0x0028 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 Access: User read/write 12 13 14 15
IREE[23:16]1
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IREE[11:0]1 w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-7. Interrupt Rising-Edge Event Enable Register (IREER)
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1
20 enable events in 100-pin LQFP; 11 enable events in 64-pin LQFP: IREE[18:16] plus IREE[7:0] (register bits 8-12 and 20–23 reserved).
Table 15-7. IREER field descriptions
Field IREE[x] Description Enable rising-edge events to cause the ISR.EIF[x] bit to be set. 0: Rising-edge event is disabled 1: Rising-edge event is enabled
15.5.3.6
Interrupt Falling-Edge Event Enable Register (IFEER)
This register is used to enable falling-edge triggered events on the corresponding interrupt pads.
Address: Base + 0x002C 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 Access: User read/write 12 13 14 15
IFEE[23:16]1
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IFEE[11:0]1 w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-8. Interrupt Falling-Edge Event Enable Register (IFEER)
1
20 enabling events in 100-pin LQFP; 11 enabling events in 64-pin LQFP: IFEE[18:16] plus IFEE[7:0] (register bits 8-12 and 20–23 reserved).
Table 15-8. IFEER field descriptions
Field IFEE[x] Description Enable falling-edge events to cause the ISR.EIF[x] bit to be set. 0: Falling-edge event is disabled 1: Falling-edge event is enabled
NOTE If both the IREER.IREE and IFEER.IFEE bits are cleared for the same interrupt source, the interrupt status flag for the corresponding external interrupt will never be set. If IREER.IREE and IFEER.IFEE bits are set for the same source the interrupts are triggered by both rising edge events and falling edge events.
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15.5.3.7
Interrupt Filter Enable Register (IFER)
This register is used to enable a digital filter counter on the corresponding interrupt pads to filter out glitches on the inputs.
Address: Base + 0x0030 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 Access: User read/write 12
1
13
14
15
IFE[23:16]
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IFE[11:0]1 w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-9. Interrupt Filter Enable Register (IFER)
1
20 bits in 100-pin LQFP; 11 bits in 64-pin LQFP: IFE[18:16] plus IEE[7:0] (register bits 8-12 and 20–23 reserved).
Table 15-9. IFER field descriptions
Field IFE[x] Description Enable digital glitch filter on the interrupt pad input 0: Filter is disabled 1: Filter is enabled Refer to the IFMC field descriptions in Table 15-19 for details on how the filter works.
15.5.3.8
Pad Configuration Registers (PCR0–PCR122)
The Pad Configuration Registers allow configuration of the static electrical and functional characteristics associated with I/O pads. Each PCR controls the characteristics of a single pad. Please note that input and output peripheral muxing are separate. • For output pads: — Select the appropriate alternate function in Pad Config Register (PCR) — OBE is not required for functions other than GPIO • For INPUT pads: — Select the feature location from PSMI register — Set the IBE bit in the appropriate PCR • For normal GPIO (not alternate function): — Configure PCR — Read from GPDI or write to GPDO
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Address: Base + 0x0040 (PCR0)( registers) Base + 0x0042 (PCR1) ... Base + 0x0 (PCR) 0 R W Reset 0 01 0 0 01 0 02 03 0 0 0 0 1 2 3 4 5 6 OBE 7 IBE 8 9 10 ODE 11
Access: User read/write
12
13
14
15
SMC APC
PA[1:0]
SRC WPE WPS
0
0
03
14
Figure 15-10. Pad Configuration Registers (PCRx)
SMC and PA[1] are ‘1’ for JTAG pads 2 OBE is ‘1’ for TDO 3 IBE and WPE are ‘1’ for TCK, TMS, TDI, FAB and ABS 4 WPS is ‘0’ for input only pad with analog feature and FAB
1
NOTE 16/32-bit access supported In addition to the bit map above, the following Table 15-10 describes the PCR depending on the pad type (pad types are defined in Chapter 2, “Signal Description, Section 2.4, “Pad types of the device reference manual). The bits in shaded fields are not implemented for the particular I/O type. The PA field selecting the number of alternate functions may or may not be present depending on the number of alternate functions actually mapped on the pad.
Table 15-10. PCRx field descriptions
Field SMC Description Safe Mode Control This bit supports the overriding of the automatic deactivation of the output buffer of the associated pad upon entering SAFE mode of the device. 0: In SAFE mode, the output buffer of the pad is disabled. 1: In SAFE mode, the output buffer remains functional. Analog Pad Control This bit enables the usage of the pad as analog input. 0: Analog input path from the pad is gated and cannot be used 1: Analog input path switch can be enabled by the ADC Pad Output Assignment This field is used to select the function that is allowed to drive the output of a multiplexed pad. 00: Alternative Mode 0 — GPIO 01: Alternative Mode 1 — See the signal description chapter 10: Alternative Mode 2 — See the signal description chapter 11: Alternative Mode 3 — See the signal description chapter Note: Number of bits depends on the actual number of actual alternate functions. Please refer to data sheet. OBE Output Buffer Enable This bit enables the output buffer of the pad in case the pad is in GPIO mode. 0: Output buffer of the pad is disabled when PA[1:0] = 00 1: Output buffer of the pad is enabled when PA[1:0] = 00
APC
PA[1:0]
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Table 15-10. PCRx field descriptions (continued)
Field IBE Description Input Buffer Enable This bit enables the input buffer of the pad. 0: Input buffer of the pad is disabled 1: Input buffer of the pad is enabled Open Drain Output Enable This bit controls output driver configuration for the pads connected to this signal. Either open drain or push/pull driver configurations can be selected. This feature applies to output pads only. 0: Pad configured for push/pull output 1: Pad configured for open drain Slew Rate Control This field controls the slew rate of the associated pad when it is slew rate selectable. Its usage is the following: 0: (default) Pad configured as slow 1: Pad is configured as medium or fast (depending on the pad) Note: PC[1] (TDO pad) is medium only. By default SRC = 0, and writing ‘1’ has no effect. WPE Weak Pull Up/Down Enable This bit controls whether the weak pull up/down devices are enabled/disabled for the pad connected to this signal. 0: Weak pull down disabled for pad 1: Weak pull down enabled for pad Weak Pull Up/Down Select This bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 0: Weak pull up disabled for pad 1: Weak pull up enabled for pad
ODE
SRC
WPS
15.5.3.9
Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63)
In some cases, a peripheral input signal can be selected from more than one pin. For example, the CAN1_RXD signal can be selected on three different pins: PC[3], PC[11] and PF[15]. Only one can be active at a time. To select the pad to be used as input to the peripheral: • Select the signal via the pad’s PCR register using the PA field. • Specify the pad to be used via the appropriate PSMI field.
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Address: Base + (0x0500–)0x053C (16 registers) 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 5 6 7 8 0 9 0 10 0 11 0
Access: User read/write 12 13 14 15
PADSEL0
PADSEL1
0
0
0
0
16 R W Reset 0 0
17 0
18 0
19 0
20
21
22
23
24 0
25 0
26 0
27 0
28
29
30
31
PADSEL2
PADSEL3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-11. Pad Selection for Multiplexed Inputs Register (PSMI0_3) Table 15-11. PSMI0_3 field descriptions
Field Description
PADSEL0–3, Pad Selection Bits PADSEL4–7, Each PADSEL field selects the pad currently used for a certain input function. See Table 15-12. ... PADSEL60–63
In order to multiplex different pads to the same peripheral input, the SIUL provides a register that controls the selection between the different sources.
Table 15-12. Peripheral input pin selection
PSMI registers PADSEL fields SIUL address offset PSMI0_3 PADSEL0 PADSEL1 PADSEL2 PADSEL3 PSMI4_7 PADSEL4 PADSEL5 PADSEL6 0x500 0x501 0x502 0x503 0x504 0x505 0x506 Function / Peripheral Reserved Reserved Reserved Reserved Reserved SCK_0 / DSPI_0 CS0_0 / DSPI_0 Mapping1 — — — — — 00: PCR[14] 01: PCR[15] 00: PCR[14] 01: PCR[15] 10: PCR[27] 00: PCR[34] 01: PCR[68]
PADSEL7
0x507
SCK_1 / DSPI_1
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Table 15-12. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset PSMI8_11 PADSEL8 PADSEL9 0x508 0x509 Function / Peripheral SIN_1 / DSPI_1 CS0_1 / DSPI_1 Mapping1 00: PCR[36] 01: PCR[66] 00: PCR[35] 01: PCR[61] 10: PCR[69] 11: PCR[4] — — — 00: PCR[3] 01: PCR[27] 10: PCR[40] 00: PCR[4] 01: PCR[28] 00: PCR[5] 01: PCR[29] 00: PCR[6] 01: PCR[30] 00: PCR[7] 01: PCR[31] 10: PCR[41] — — — 00: PCR[45] 10: PCR[0] 00: PCR[46] 10: PCR[8] 00: PCR[70] 01: PCR[72] 00: PCR[71] 01: PCR[73] 00: PCR[60] 10: PCR[75] — —
PADSEL10 PADSEL11 PSMI12_15 PADSEL12 PADSEL13
0x50A 0x50B 0x50C 0x50D
Reserved Reserved Reserved E1UC[3] / eMIOS_0
PADSEL14 PADSEL15 PSMI16_19 PADSEL16 PADSEL17
0x50E 0x50F 0x510 0x511
E0UC[4] / eMIOS_0 E0UC[5] / eMIOS_0 E0UC[6] / eMIOS_0 E0UC[7] / eMIOS_0
PADSEL18 PADSEL19 PSMI20_23 PADSEL20 PADSEL21 PADSEL22 PADSEL23 PSMI24_27 PADSEL24 PADSEL25 PADSEL26 PADSEL27
0x512 0x513 0x514 0x515 0x516 0x517 0x518 0x519 0x51A 0x51B
Reserved Reserved Reserved E0UC[13] / eMIOS_0 E0UC[14] / eMIOS_0 E0UC[22] / eMIOS_0 E0UC[23] / eMIOS_0 E0UC[24] / eMIOS_0 Reserved Reserved
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Table 15-12. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset PSMI28_31 PADSEL28 PADSEL29 PADSEL30 PADSEL31 PSMI32_35 PADSEL32 PADSEL33 PADSEL34 PADSEL35 PSMI36_39 PADSEL36 PADSEL37 PADSEL38 PADSEL39 PSMI40_43 PADSEL40 PADSEL41 PADSEL42 PADSEL43 PSMI44_47 PADSEL44 PADSEL45 PADSEL46 PADSEL47 PSMI48_51 PADSEL48 PADSEL49 PADSEL50 PADSEL51 PSMI52_55 PADSEL52 PADSEL53 PADSEL54 PADSEL55 0x51C 0x51D 0x51E 0x51F 0x520 0x521 0x522 0x523 0x524 0x525 0x526 0x527 0x528 0x529 0x52A 0x52B 0x52C 0x52D 0x52E 0x52F 0x530 0x531 0x532 0x533 0x534 0x535 0x536 0x537 Function / Peripheral Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved E0UC[0] / eMIOS_0 E0UC[1] / eMIOS_0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Mapping1 — — — — — — — — — — 00: PCR[0] 01: PCR[14] 00: PCR[1] 01: PCR[15] — — — — — — — — — — — — — — — —
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Table 15-12. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset PSMI56_59 PADSEL56 PADSEL57 PADSEL58 PADSEL59 PSMI60_63
2
Function / Peripheral Reserved Reserved LIN2RX / LINFlex _2 Reserved Reserved Reserved LIN0RX / LINFlex _0
Mapping1 — — 00: PCR[41] 01: PCR[11] — — — 00: PCR[19] 01: PCR[17]
0x538 0x539 0x53A 0x53B 0x53C 0x53D 0x53E
PADSEL60 PADSEL61 PADSEL62
1
See the signal description chapter of this reference manual for correspondence between PCR and pinout 2 PADSEL63 is not implemented
15.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123)
These registers are used to set or clear GPIO pads. Each pad data out bit can be controlled separately with a byte access.
Address: Base + (0x0600–0x0678) (31 registers) 0 R W Reset 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 PDO [0] 0 8 0 9 0 10 0 11 0 Access: User read/write 12 0 13 0 14 0 15 PDO [1] 0
0
0
0
0
0
0
0
16 R W Reset 0 0
17 0
18 0
19 0
20 0
21 0
22 0
23 PDO [2] 0
24 0
25 0
26 0
27 0
28 0
29 0
30 0
31 PDO [3] 0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-12. Port GPIO Pad Data Output Register 0–3 (GPDO0_3) Table 15-13. GPDO0_3 field descriptions
Field PDO[x] Description Pad Data Out This bit stores the data to be driven out on the external GPIO pad controlled by this register. 0: Logic low value is driven on the corresponding GPIO pad when the pad is configured as an output 1: Logic high value is driven on the corresponding GPIO pad when the pad is configured as an output
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WARNING Toggling several IOs at the same time can significantly increase the current in a pad group. Caution must be taken to avoid exceeding maximum current thresholds. Please refer to data sheet.
15.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123)
These registers are used to read the GPIO pad data with a byte access.
Address: Base + (0x0800–0x0878) (31 registers) 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 PDI [0] 8 0 9 0 10 0 11 0 12 0 Access: User read 13 0 14 0 15 PDI [1]
16 R W Reset 0 0
17 0
18 0
19 0
20 0
21 0
22 0
23 PDI [2]
24 0
25 0
26 0
27 0
28 0
29 0
30 0
31 PDI [3]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-13. Port GPIO Pad Data Input Register 0–3 (GPDI0_3) Table 15-14. GPDO0_3 field descriptions
Field PDI[x] Description Pad Data In This bit stores the value of the external GPIO pad associated with this register. 0: Value of the data in signal for the corresponding GPIO pad is logic low 1: Value of the data in signal for the corresponding GPIO pad is logic high
15.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3)
MPC5602D devices ports are constructed such that they contain 16 GPIO pins, for example PortA[0..15]. Parallel port registers for input (PGPDI) and output (PGPDO) are provided to allow a complete port to be written or read in one operation, dependent on the individual pad configuration. Writing a parallel PGPDO register directly sets the associated GPDO register bits. There is also a masked parallel port output register allowing the user to determine which pins within a port are written. While very convenient and fast, this approach does have implications regarding current consumption for the device power segment containing the port GPIO pads. Toggling several GPIO pins simultaneously can significantly increase current consumption.
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WARNING Caution must be taken to avoid exceeding maximum current thresholds when toggling multiple GPIO pins simultaneously. Please refer to data sheet. Table 15-15 shows the locations and structure of the PGPDOx registers.
Table 15-15. PGPDO0 – PGPDO3 Register Map
Offset1 Register 0x0C00 PGPDO0 0x0C04 PGPDO1 0x0C08 PGPDO2 0x0C0C PGPDO3
1
Field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Port A Port C Port E Port G Port B Port D Port F Port H
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of the parallel port register corresponds to the least significant pin in the port. For example in Table 15-15, the PGPDO0 register contains fields for Port A and Port B. • Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is mapped to Port A[15] • Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is mapped to Port B[15].
15.5.3.13 Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI3)
The SIU_PGPDI registers are similar in operation to the PGPDIO registers, described in the previous section (Section 15.5.3.12, “Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3)) but they are used to read port pins simultaneously. NOTE The port pins to be read need to be configured as inputs but even if a single pin within a port has IBE set, then you can still read that pin using the parallel port register. However, this does mean you need to be very careful. Reads of PGPDI registers are equivalent to reading the corresponding GPDI registers but significantly faster since as many as two ports can be read simultaneously with a single 32-bit read operation. Table 15-16 shows the locations and structure of the PGPDIx registers. Each 32-bit PGPDIx register contains two 16-bit fields, each field containing the values for a separate port.
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Table 15-16. PGPDI0 – PGPDI3 Register Map
Offset1 Register 0x0C40 0x0C44 0x0C48 0x0C4C
1
Field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PGPDI0 PGPDI1 PGPDI2 PGPDI3
Port A Port C Port E Port G
Port B Port D Port F Port H
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of the parallel port register corresponds to the least significant pin in the port. For example in Table 15-16, the PGPDI0 register contains fields for Port A and Port B. • Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is mapped to Port A[15] • Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is mapped to Port B[15].
15.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO7)
The MPGPDOx registers are similar in operation to the PGPDOx ports described in Section 15.5.3.12, “Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO3), but with two significant differences: • The MPGPDOx registers support masked port-wide changes to the data out on the pads of the respective port. Masking effectively allows selective bitwise writes to the full 16-bit port. • Each 32-bit MPGPDOx register is associated to only one port. NOTE The MPGPDOx registers may only be accessed with 32-bit writes. 8-bit or 16-bit writes will not modify any bits in the register and will cause a transfer error response by the module. Read accesses return ‘0’. Table 15-17 shows the locations and structure of the MPGPDOx registers. Each 32-bit MPGPDOx register contains two 16-bit fields (MASKx and MPPDOx). The MASK field is a bitwise mask for its associated port. The MPPDO0 field contains the data to be written to the port.
Table 15-17. MPGPDO0 – MPGPDO7 Register Map
Offset1 Register MASK0 (Port A) MASK1 (Port B) MASK2 (Port C) MASK3 (Port D) Field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0C80 MPGPDO0 0x0C84 MPGPDO1 0x0C88 MPGPDO2 0x0C8C MPGPDO3 MPPDO0 (Port A) MPPDO1 (Port B) MPPDO2 (Port C) MPPDO3 (Port D) MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 443
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Table 15-17. MPGPDO0 – MPGPDO7 Register Map (continued)
Offset1 Register MASK4 (Port E) MASK5 (Port F) MASK6 (Port G) MASK7 (Port H) Field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0C90 MPGPDO4 0x0C94 MPGPDO5 0x0C98 MPGPDO6 0x0C9C MPGPDO7
1
MPPDO4 (Port E) MPPDO5 (Port F) MPPDO6 (Port G) MPPDO7 (Port H)
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of the parallel port register corresponds to the least significant pin in the port. For example in Table 15-17, the MPGPDO0 register contains field MASK0, which is the bitwise mask for Port A and field MPPDO0, which contains data to be written to Port A. • MPGPDO0[0] is the mask bit for Port A[0], MPGPDO0[1] is the mask bit for Port A[1] and so on, through MPGPDO0[15], which is the mask bit for Port A[15] • MPGPDO0[16] is the data bit mapped to Port A[0], MPGPDO0[17] is mapped to Port A[1] and so on, through MPGPDO0[31], which is mapped to Port A[15].
Table 15-18. MPGPDO0..MPGPDO7 field descriptions
Field MASKx [15:0] Description Mask Field Each bit corresponds to one data bit in the MPPDOx register at the same bit location. 0: Associated bit value in the MPPDOxfield is ignored 1: Associated bit value in the MPPDOx field is written Masked Parallel Pad Data Out Write the data register that stores the value to be driven on the pad in output mode. Accesses to this register location are coherent with accesses to the bitwise GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123). The x and bit index define which MPPDO register bit is equivalent to which PDO register bit according to the following equation: MPPDO[x][y] = PDO[(x*16)+y]
MPPDOx [15:0]
WARNING Toggling several IOs at the same time can significantly increase the current in a pad group. Caution must be taken to avoid exceeding maximum current thresholds. Please refer to data sheet.
15.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23)
These registers are used to configure the filter counter associated with each digital glitch filter.
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NOTE For the pad transition to trigger an interrupt it must be steady for at least the filter period.
Address: Base + (0x1000–) ( registers) 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 Access: User read/write 12 0 13 0 14 0 15 0
16 R W Reset 0 0
17 0
18 0
19 0
20 0
21 0
22 0
23 0
24 0
25 0
26 0
27 0
28
29
30
31
MAXCNTx[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-14. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23) Table 15-19. IFMC field descriptions
Field MAXCNTx [3:0] Description Maximum Interrupt Filter Counter setting Filter Period = T(CK)*MAXCNTx + n*T(CK) Where (n can be 1 to 3) MAXCNTx can be 0 to 15 T(CK): Prescaled Filter Clock Period, which is FIRC clock prescaled to IFCP value T(FIRC): Basic Filter Clock Period: 62.5 ns (fFIRC = 16 MHz)
15.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR)
This register is used to configure a clock prescaler which is used to select the clock for all digital filter counters in the SIUL.
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Address: Base + 0x1080 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0
Access: User read/write 12 0 13 0 14 0 15 0
0
0
0
0
16 R W Reset 0 0
17 0
18 0
19 0
20 0
21 0
22 0
23 0
24 0
25 0
26 0
27 0
28
29
30
31
IFCP[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-15. Interrupt Filter Clock Prescaler Register (IFCPR) Table 15-20. IFCPR field descriptions
Field IFCP[3:0] Description Interrupt Filter Clock Prescaler setting Prescaled Filter Clock Period = T(FIRC) x (IFCP + 1) T(FIRC) is the fast internal RC oscillator period. IFCP can be 0 to 15.
15.6
15.6.1
Functional description
Pad control
The SIUL controls the configuration and electrical characteristic of the device pads. It provides a consistent interface for all pads, both on a by-port and a by-bit basis. The pad configuration registers (PCRn, see Section 15.5.3.8, “Pad Configuration Registers (PCR0–PCR122)) allow software control of the static electrical characteristics of external pins with a single write. These are used to configure the following pad features: • Open drain output enable • Slew rate control • Pull control • Pad assignment • Control of analog path switches • Safe mode behavior configuration
15.6.2
General purpose input and output pads (GPIO)
The SIUL manages up to 123 GPIO pads organized as ports that can be accessed for data reads and writes as 32, 16 or 8-bit1.
1.There are exceptions. Some pads, e.g., precision analog pads, are input only.
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Chapter 15 System Integration Unit Lite (SIUL)
NOTE Ports are organized as groups of 16 GPIO pads, with the exception of Port J, which has 5. A 32-bit R/W operation accesses two ports simultaneously. A 16-bit operation accesses a full port and an 8-bit access either the upper or lower byte of a port. As shown in Figure 15-16, all port accesses are identical with each read or write being performed only at a different location to access a different port width.
31 SIUL Base+ 0x0C00 SIUL Base+ 0x0C02 SIUL Base+ 0x0C03 7 8-bit Access (half port) 15 7 16-bit Access (full port) 0 SIUL Base+ 0x0C02 7 8-bit Access (half port) 0 23 15 32-bit Access (2 ports) 0 SIUL Base+ 0x0C00 SIUL Base+ 0x0C01 7 8-bit Access (half port) 15 7 16-bit Access (full port) 0 SIUL Base+ 0x0C00 7 8-bit Access (half port) 0 0 7 0
Figure 15-16. Data Port example arrangement showing configuration for different port width accesses
The SIUL has separate data input (GPDIn_n, see Section 15.5.3.11, “GPIO Pad Data Input Registers (GPDI0_3–GPDI120_123)) and data output (GPDOn_n, see Section 15.5.3.10, “GPIO Pad Data Output Registers (GPDO0_3–GPDO120_123)) registers for all pads, allowing the possibility of reading back an input or output value of a pad directly. This supports the ability to validate what is present on the pad rather than simply confirming the value that was written to the data register by accessing the data input registers. Data output registers allow an output pad to be driven high or low (with the option of push-pull or open drain drive). Input registers are read-only and reflect the respective pad value. When the pad is configured to use one of its alternate functions, the data input value reflects the respective value of the pad. If a write operation is performed to the data output register for a pad configured as an alternate function (non-GPIO), this write will not be reflected by the pad value until reconfigured to GPIO. The allocation of what input function is connected to the pin is defined by the PSMI registers (PCRn, see Section 15.5.3.9, “Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63)).”
15.6.3
External interrupts
The SIUL supports 24 external interrupts, EIRQ0–EIRQ23. In the signal description chapter of this reference manual, mapping is shown for external interrupts to pads. The SIUL supports threeinterrupt vectors to the interrupt controller. Each vector interrupt has eight external interrupts combined together with the presence of flag generating an interrupt for that vector if enabled. All of the external interrupt pads within a single group have equal priority. Refer to Figure 15-17 for an overview of the external interrupt implementation.
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Interrupt Vectors
Interrupt Controller
IRQ_23_16
IRQ_15_08
IRQ_07_00
OR
OR Interrupt enable
OR IRE[23:0](1)
Glitch filter Prescaler IFCP[3:0] Glitch filter Counter_n MAXCOUNT[x] IRQ Glitch Filter enable IFE[23:0]
EIF[23:16]
EIF[15:8]
EIF[7:0] Interrupt Edge Enable Rising IREE[23:0](1) Falling IFEE[23:0](1)
Edge Detection Glitch Filter
Pads
Figure 15-17. External interrupt pad diagram
3
20 interrupts in 100-pin LQFP; 11 interrupts in 64-pin LQFP.
Each interrupt can be enabled or disabled independently. This can be performed using the Interrupt Request Enable Register (IRER). A pad defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an active falling edge or both edges being active. A setting of having both edge events disabled is reserved and should not be configured. The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER. Each external interrupt supports an individual flag which is held in the Interrupt Status Flag Register (ISR). This register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the same register.
15.7
Pin muxing
For pin muxing, please refer to the signal description chapter of this reference manual.
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Chapter 16 Error Correction Status Module (ECSM)
Chapter 16 Error Correction Status Module (ECSM)
16.1 Introduction
The Error Correction Status Module (ECSM) provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes. The spp_ips_reg_protection module provides access protection for slave modules INTC, ECSM, MPU, STM, and SWT.
16.2
Overview
The Error Correction Status Module is mapped into the IPS space and supports a number of miscellaneous control functions for the device.
16.3
Features
The ECSM includes these features: • Program-visible information on the device configuration and revision • Optional registers for capturing information on memory errors if error-correcting codes (ECC) are implemented • Optional registers to specify the generation of single- and double-bit memory data inversions for test purposes if error-correcting codes are implemented • Spp_ips_reg_protection provides privileged-only access to selected on-platform slave devices: INTC, ECSM, MPU, STM, and SWT.
16.4
Memory map and register description
This section details the programming model for the Error Correction Status Module. This is a 128-byte space mapped to the region serviced by an IPS bus controller.
16.4.1
Memory map
The Error Correction Status Module does not include any logic which provides access control. Rather, this function is supported using the standard access control logic provided by the IPS controller. Table 16-1 is a 32-bit view of the ECSM’s memory map.
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Table 16-1. ECSM 32-bit memory map
ECSM base address: 0xFFF4_0000 Address offset 0x0000 0x0004 0x0008 0x000C 0x0010 Reserved Processor Core Type (PCT) register Reserved IPS Module Configuration (IMC) register Reserved Miscellaneous Wakeup Control Register (MWCR) Reserved Reserved Reserved Miscellaneous Interrupt Register (MIR) Reserved Miscellaneous User-Defined Control Register (MUDCR) Reserved Reserved Reserved Reserved Reserved ECC Configuration Register (ECR) ECC Status Register (ESR) ECC Error Generation Register (EEGR) Reserved Flash ECC Address Register (FEAR) Reserved Flash ECC Master Number Register (FEMR) Reserved Flash ECC Data Register (FEDR) RAM ECC Address Register (REAR) Reserved RAM ECC Syndrome Register (RESR) RAM ECC Master Number Register (REMR) RAM ECC Attributes (REAT) register Flash ECC Attributes (FEAT) register Register Revision (REV) register
0x0014 0x0018 0x001C
0x0020 0x0024 0x0028 0x002C – 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054
0x0058 0x005C 0x0060 0x0064
0x0068 0x006C 0x0070 – 0x007C
Reserved RAM ECC Data Register (REDR) Reserved
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16.4.2
Register description
Attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes, etc. Attempted writes of a different size than the register width produce an error termination of the bus cycle and no change to the targeted register.
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16.4.2.1
Processor Core Type (PCT) register
The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The state of this register is defined by a module input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
Register address: ECSM Base + 0x00 0 R W Reset: 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PCT[15:0]
= Unimplemented
Figure 16-1. Processor Core Type (PCT) Register Table 16-2. Processor Core Type (PCT) field descriptions
Name 0–15 PCT[15:0] Processor Core Type Description
16.4.2.2
Revision (REV) register
The REV is a 16-bit read-only register specifying a revision number. The state of this register is defined by an input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
Register address: ECSM Base + 0x02 0 R W Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REV[15:0]
= Unimplemented
Figure 16-2. Revision (REV) Register Table 16-3. Revision (REV) field descriptions
Name 0–15 REV[15:0] Description Revision The REV[15:0] field is specified by an input signal to define a software-visible revision number.
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16.4.2.3
IPS Module Configuration (IMC) register
The IMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order IPS peripheral modules connected to the primary IPI SkyBlue bus controller. The state of this register is defined by a module input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
Register address: ECSM Base + 0x08 0 R W Reset: 0 16 R W Reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 17 0 18 0 19 0 20 0 21 0 22 0 23 0 24 0 25 0 26 0 27 0 28 0 29 1 30 1 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MC[31:16]
MC[15:0]
= Unimplemented
Figure 16-3. IPS Module Configuration (IMC) Register Table 16-4. IPS Module Configuration (IMC) field descriptions
Name 0–31 MC[31:0] Description IPS Module Configuration MC[n] = 0 if an IPS module connection to decoded slot “n” is absent MC[n] = 1 if an IPS module connection to decoded slot “n” is present
16.4.2.4
Miscellaneous Wakeup Control Register (MWCR)
Implementation of low-power sleep modes and exit from these modes via an interrupt require communication between the ECSM, the interrupt controller and external logic typically associated with phase-locked loop clock generation circuitry. The Miscellaneous Wakeup Control Register (MWCR) provides an 8-bit register controlling entry into these types of low-power modes as well as definition of the interrupt level needed to exit the mode. The following sequence of operations is generally needed to enable this functionality. Note that the exact details are likely to be system-specific. 1. The processor core loads the appropriate data value into the MWCR, setting the ENBWCR bit and the desired interrupt priority level. 2. At the appropriate time, the processor ceases execution. The exact mechanism varies by processor core. In some cases, a processor-is-stopped status is signaled to the ECSM and external logic. This assertion, if properly enabled by MWCR[ENBWCR], causes the ECSM output signal “enter_low_power_mode” to be set. This, in turn, causes the selected external, low-power mode, to be entered, and the appropriate clock signals disabled. In most implementations, there are multiple low-power modes, where the exact clocks to be disabled vary across the different modes.
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3. After entering the low-power mode, the interrupt controller enables a special combinational logic path which evaluates all unmasked interrupt requests. The device remains in this mode until an event which generates an unmasked interrupt request with a priority level greater than the value programmed in the MWCR[PRILVL] occurs. 4. Once the appropriately-high interrupt request level arrives, the interrupt controller signals its presence, and the ECSM responds by asserting an “exit_low_power_mode” signal. 5. The external logic senses the assertion of the “exit” signal, and re-enables the appropriate clock signals. 6. With the processor core clocks enabled, the core handles the pending interrupt request.
Register address: ECSM Base + 0x13 0 R W Reset: 0 0 0 0 0 0 0 0 ENBWCR 1 0 2 0 3 0 4 5 PRILVL[3:0] 6 7
= Unimplemented
Figure 16-4. Miscellaneous Wakeup Control (MWCR) Register Table 16-5. Miscellaneous Wakeup Control (MWCR) field descriptions
Name 0 ENBWCR 4–7 PRILVL[3:0] Enable WCR 0 = MWCR is disabled. 1 = MWCR is enabled. Interrupt Priority Level The interrupt priority level is a core-specific definition. It specifies the interrupt priority level needed to exit the low-power mode. Specifically, an unmasked interrupt request of a priority level greater than the PRILVL value is required to exit the mode. Certain interrupt controller implementations include logic associated with this priority level that restricts the data value contained in this field to a [0, maximum - 1] range. See the specific interrupt controller module for details. Description
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16.4.2.5
Miscellaneous Interrupt Register (MIR)
All interrupt requests associated with ECSM are collected in the MIR. This includes the processor core system bus fault interrupt. During the appropriate interrupt service routine handling these requests, the interrupt source contained in the MIR must be explicitly cleared. See Figure 16-5 and Table 16-6.
Register address: ECSM Base + 0x1F 0 R W Reset: FB0AI 1 0 1 FB0SI 1 0 2 FB1AI 1 0 3 FB1SI 1 0 4 0 XXXXXXX 0 5 0 XXXXXXX 0 6 0 XXXXXXX 0 7 0 XXXXXXX 0
XXXXXXX = Unimplemented
Figure 16-5. Miscellaneous Interrupt (MIR) Register Table 16-6. Miscellaneous Interrupt (MIR) field descriptions
Name 0 FB0AI Description Flash Bank 0 Abort Interrupt 0: A flash bank 0 abort has not occurred. 1: A flash bank 0 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect. Flash Bank 0 Stall Interrupt 0: A flash bank 0 stall has not occurred. 1: A flash bank 0 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect. Flash Bank 1 Abort Interrupt 0: A flash bank 1 abort has not occurred. 1: A flash bank 1 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect. Flash Bank 1 Stall Interrupt 0: A flash bank 1 stall has not occurred. 1: A flash bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect.
1 FB0SI
2 FB1AI
3 FB1SI
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16.4.2.6
Miscellaneous User-Defined Control Register (MUDCR)
The MUDCR provides a program-visible register for user-defined control functions. It typically is used as configuration control for miscellaneous SoC-level modules. The contents of this register is simply output from the ECSM to other modules where the user-defined control functions are implemented.
Register address: ECSM Base + 0x24 0 MUDCR[31] R W 1 MUDCR[30] 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 R W Reset: 0 0
17 0
18 0
19 0
20 0
21 0
22 0
23 0
24 0
25 0
26 0
27 0
28 0
29 0
30 0
31 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-6. Miscellaneous User-Defined Control (MUDCR) Register Table 16-7. Miscellaneous User-Defined Control Register (MUDCR) field descriptions
Name 0 MUDCR[31] Description XBAR force_round_robin bit This bit is used to drive the force_round_robin bit of the XBAR. This will force the slaves into round robin mode of arbitration rather than fixed mode (unless a master is using priority elevation, which forces the design back into fixed mode regardless of this bit). By setting the hardware definition to ENABLE_ROUND_ROBIN_RESET, this bit will reset to 1. 1 = XBAR is in round robin mode 0 = XBAR is in fixed priority mode Unused
1 MUDCR[30]
2–31 Unused MUDCR[29:0]
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16.4.2.7
ECC registers
For designs including error-correcting code (ECC) implementations to improve the quality and reliability of memories, there are a number of program-visible registers for the sole purpose of reporting and logging of memory failures. These optional registers include: • ECC Configuration Register (ECR) • ECC Status Register (ESR) • ECC Error Generation Register (EEGR) • Flash ECC Address Register (FEAR) • Flash ECC Master Number Register (FEMR) • Flash ECC Attributes Register (FEAT) • Flash ECC Data Register (FEDR) • RAM ECC Address Register (REAR) • RAM ECC Syndrome Register (RESR) • RAM ECC Master Number Register (REMR) • RAM ECC Attributes Register (REAT) • RAM ECC Data Register (REDR) The details on the ECC registers are provided in the subsequent sections. If the design does not include ECC on the memories, these addresses are reserved locations within the ECSM’s programming model. 16.4.2.7.1 ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. In many cases, this error termination is reported directly by the initiating bus master. However, there are certain situations where the occurrence of this type of non-correctable error is not reported by the master. Examples include speculative instruction fetches which are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting logic in the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In addition to the interrupt generation, the ECSM captures specific information (memory address, attributes and data, bus master number, etc.) which may be useful for subsequent failure analysis.
Register address: ECSM Base + 0x43 0 R W Reset: 0 0 0 0 0 0 0 0 0 1 0 2 ER1BR 3 EF1BR 4 0 5 0 6 ERNCR 7 EFNCR
= Unimplemented
Figure 16-7. ECC Configuration (ECR) Register
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Table 16-8. ECC Configuration (ECR) field descriptions
Name 2 ER1BR Description Enable SRAM 1-bit Reporting 0 = Reporting of single-bit SRAM corrections is disabled. 1 = Reporting of single-bit SRAM corrections is enabled. This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a single-bit SRAM correction generates a ECSM ECC interrupt request as signalled by the assertion of ESR[R1BC]. The address, attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers. 3 EF1BR Enable Flash 1-bit Reporting 0 = Reporting of single-bit flash corrections is disabled. 1 = Reporting of single-bit flash corrections is enabled. This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a single-bit flash correction generates a ECSM ECC interrupt request as signalled by the assertion of ESR[F1BC]. The address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers. 6 ERNCR Enable SRAM Non-Correctable Reporting 0 = Reporting of non-correctable SRAM errors is disabled. 1 = Reporting of non-correctable SRAM errors is enabled. The occurrence of a non-correctable multi-bit SRAM error generates a ECSM ECC interrupt request as signalled by the assertion of ESR[RNCE]. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers. 7 EFNCR Enable Flash Non-Correctable Reporting 0 = Reporting of non-correctable flash errors is disabled. 1 = Reporting of non-correctable flash errors is enabled. The occurrence of a non-correctable multi-bit flash error generates a ECSM ECC interrupt request as signalled by the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers.
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16.4.2.7.2
ECC Status Register (ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC events have been detected. The ESR signals the last, properly-enabled memory event to be detected. ECC interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection and the combination of the two as defined by the following boolean equations: ECSM_ECC1BIT_IRQ = ECR[ER1BR] & ESR[R1BC]// ram, 1-bit correction | ECR[EF1BR] & ESR[F1BC]// flash, 1-bit correction ECSM_ECCRNCR_IRQ = ECR[ERNCR] & ESR[RNCE]// ram, noncorrectable error ECSM_ECCFNCR_IRQ = ECR[EFNCR] & ESR[FNCE]// flash, noncorrectable error ECSM_ECC2BIT_IRQ = ECSM_ECCRNCR_IRQ// ram, noncorrectable error | ECSM_ECCFNCR_IRQ// flash, noncorrectable error ECSM_ECC_IRQ = ECSM_ECC1BIT_IRQ // 1-bit correction | ECSM_ECC2BIT_IRQ// noncorrectable error where the combination of a properly-enabled category in the ECR and the detection of the corresponding condition in the ESR produces the interrupt request. The ECSM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the association between the ESR and the corresponding address and attribute registers, which are loaded on each occurrence of an properly-enabled ECC event. If there is a pending ECC interrupt and another properly-enabled ECC event occurs, the ECSM hardware automatically handles the ESR reporting, clearing the previous data and loading the new state and thus guaranteeing that only a single flag is asserted. To maintain the coherent software view of the reported event, the following sequence in the ECSM error interrupt service routine is suggested: 1. Read the ESR and save it. 2. Read and save all the address and attribute reporting registers. 3. Re-read the ESR and verify the current contents matches the original contents. If the two values are different, go back to step 1 and repeat. 4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.
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Register address: ECSM Base + 0x47 0 R W Reset: 0 0 0 0 0 0 0 0 0 1 0 2 R1BC 3 F1BC 4 0 5 0 6 RNCE 7 FNCE
= Unimplemented
Figure 16-8. ECC Status (ESR) Register Table 16-9. ECC Status (ESR) field descriptions
Name 2 R1BC Description SRAM 1-bit Correction 0 = No reportable single-bit SRAM correction has been detected. 1 = A reportable single-bit SRAM correction has been detected. This bit can only be set if ECR[EPR1BR] is asserted. The occurrence of a properly-enabled single-bit SRAM correction generates a ECSM ECC interrupt request. The address, attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect. 3 F1BC Flash 1-bit Correction 0 = No reportable single-bit flash correction has been detected. 1 = A reportable single-bit flash correction has been detected. This bit can only be set if ECR[EPF1BR] is asserted. The occurrence of a properly-enabled single-bit flash correction generates a ECSM ECC interrupt request. The address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect. 6 RNCE SRAM Non-Correctable Error 0 = No reportable non-correctable SRAM error has been detected. 1 = A reportable non-correctable SRAM error has been detected. The occurrence of a properly-enabled non-correctable SRAM error generates a ECSM ECC interrupt request. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect. 7 FNCE Flash Non-Correctable Error 0 = No reportable non-correctable flash error has been detected. 1 = A reportable non-correctable flash error has been detected. The occurrence of a properly-enabled non-correctable flash error generates a ECSM ECC interrupt request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
In the event that multiple status flags are signaled simultaneously, ECSM records the event with the R1BC as highest priority, then F1BC, then RNCE, and finally FNCE.
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16.4.2.7.3
ECC Error Generation Register (EEGR)
The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and double-bit data inversions in the memories with ECC, most notably the SRAM. This capability is provided for two purposes: • It provides a software-controlled mechanism for “injecting” errors into the memories during data writes to verify the integrity of the ECC logic. • It provides a mechanism to allow testing of the software service routines associated with memory error logging. It should be noted that while the EEGR is associated with the SRAM, similar capabilities exist for the flash, that is, the ability to program the non-volatile memory with single- or double-bit errors is supported for the same two reasons previously identified. For both types of memories (SRAM and flash), the intent is to generate errors during data write cycles, such that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections or double-bit non-correctable errors that are terminated with an error response.
Register address: ECSM Base + 0x4a 0 R W Reset: 0 0 0 1 0 2 3 4 0 5 0 6 7 8 0 9 10 11 12 13 14 15
FRC FR1 1BI 1BI 0 0
FRC FR1 NCI NCI 0 0
ERRBIT[6:0]
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-9. ECC Error Generation (EEGR) Register Table 16-10. ECC Error Generation (EEGR) field descriptions
Name 2 FRC1BI Description Force SRAM Continuous 1-bit Data Inversions 0 = No SRAM continuous 1-bit data inversions are generated. 1 = 1-bit data inversions in the SRAM are continuously generated. The assertion of this bit forces the SRAM controller to create 1-bit data inversions, as defined by the bit position specified in ERRBIT[6:0], continuously on every write operation. The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit position defined by ERRBIT is inverted to introduce a 1-bit ECC event in the SRAM. After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit correction reporting) is asserted.
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Table 16-10. ECC Error Generation (EEGR) field descriptions (continued)
Name 3 FR11BI Description Force SRAM One 1-bit Data Inversion 0 = No SRAM single 1-bit data inversion is generated. 1 = One 1-bit data inversion in the SRAM is generated. The assertion of this bit forces the SRAM controller to create one 1-bit data inversion, as defined by the bit position specified in ERRBIT[6:0], on the first write operation after this bit is set. The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit position defined by ERRBIT is inverted to introduce a 1-bit ECC event in the SRAM. After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. 6 FRCNCI Force SRAM Continuous Non-correctable Data Inversions 0 = No SRAM continuous 2-bit data inversions are generated. 1 = 2-bit data inversions in the SRAM are continuously generated. The assertion of this bit forces the SRAM controller to create 2-bit data inversions, as defined by the bit position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation. After this bit has been enabled to generate another continuous non-correctable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the SRAM. 7 FR1NCI Force SRAM One Non-correctable Data Inversions 0 = No SRAM single 2-bit data inversions are generated. 1 = One 2-bit data inversion in the SRAM is generated. The assertion of this bit forces the SRAM controller to create one 2-bit data inversion, as defined by the bit position specified in ERRBIT[6:0] and the overall odd parity bit, on the first write operation after this bit is set. The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the SRAM. After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic.
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Chapter 16 Error Correction Status Module (ECSM)
Table 16-10. ECC Error Generation (EEGR) field descriptions (continued)
Name 9–15 ERRBIT [6:0] Description Error Bit Position The vector defines the bit position which is complemented to create the data inversion on the write operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of the ECC code are inverted. The SRAM controller follows a vector bit ordering scheme where LSB = 0. Errors in the ECC syndrome bits can be generated by setting this field to a value greater than the SRAM width. For example, consider a 32-bit SRAM implementation. The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the actual SRAM (32b data + 7b for ECC) = 39 bits. The following association between the ERRBIT field and the corrupted memory bit is defined: if ERRBIT = 0, then SRAM[0] of the odd bank is inverted if ERRBIT = 1, then SRAM[1] of the odd bank is inverted ... if ERRBIT = 31, then SRAM[31] of the odd bank is inverted if ERRBIT = 64, then ECC Parity[0] of the odd bank is inverted if ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted ... if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI]) and EEGR[ERRBIT] equals 64, then no data inversion will be generated. The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.7.4
Flash ECC Address Register (FEAR)
The FEAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x50 0 R W Reset: – – – – – – – – – – – – – – – – 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FEAR[31:16]
16 R W Reset: –
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FEAR[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
= Unimplemented
Figure 16-10. Flash ECC Address (FEAR) Register Table 16-11. Flash ECC Address (FEAR) field descriptions
Name 0–31 FEAR[31:0] Description Flash ECC Address Register This 32-bit register contains the faulting access address of the last, properly-enabled flash ECC event.
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.7.5
Flash ECC Master Number Register (FEMR)
The FEMR is a 4-bit register for capturing the XBAR bus master number of the last, properly-enabled ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored.
.
Register address: ECSM Base + 0x56 0 R W Reset: 0 0 0 0 – – – – 0 1 0 2 0 3 0 4 5 FEMR[3:0] 6 7
= Unimplemented
Figure 16-11. Flash ECC Master Number (FEMR) Register Table 16-12. Flash ECC Master Number (FEMR) field descriptions
Name 4–7 FEMR[3:0] Description Flash ECC Master Number Register This 4-bit register contains the XBAR bus master number of the faulting access of the last, properly-enabled flash ECC event.
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.8
Flash ECC Attributes (FEAT) register
The FEAT is an 8-bit register for capturing the XBAR bus master attributes of the last, properly-enabled ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x57 0 R W Reset: – – – – – – – – WRITE 1 2 SIZE[2:0] 3 4 5 6 7
PROTECTION[3:0]
= Unimplemented
Figure 16-12. Flash ECC Attributes (FEAT) Register Table 16-13. Flash ECC Attributes (FEAT) field descriptions
Name 0 WRITE 1–3 SIZE[2:0] AMBA-AHB HWRITE 0 = AMBA-AHB read access 1 = AMBA-AHB write access AMBA-AHB HSIZE[2:0] 0b000 = 8-bit AMBA-AHB access 0b001 = 16-bit AMBA-AHB access 0b010 = 32-bit AMBA-AHB access 0b1xx = Reserved Description
4–7 AMBA-AHB HPROT[3:0] PROTECTION Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable [3:0] Protection[2]: Bufferable 0 = Non-bufferable, 1 = Bufferable Protection[1]: Mode 0 = User mode, 1 = Supervisor mode Protection[0]: Type 0 = I-Fetch, 1 = Data
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.8.1
Flash ECC Data Register (FEDR)
The FEDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base +0x5C 0 R W Reset: – – – – – – – – – – – – – – – – 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FEDR[31:16]
16 R W Reset: –
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FEDR[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
= Unimplemented
Figure 16-13. Flash ECC Data (FEDR) Register Table 16-14. Flash ECC Data (FEDR) field descriptions
Name 0–31 FEDR[31:0] Description Flash ECC Data Register This 32-bit register contains the data associated with the faulting access of the last, properly-enabled flash ECC event. The register contains the data value taken directly from the data bus.
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.8.2
RAM ECC Address Register (REAR)
The REAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the SRAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x60 0 R W Reset: – – – – – – – – – – – – – – – – 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REAR[31:16]
16 R W Reset: –
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
REAR[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
= Unimplemented
Figure 16-14. RAM ECC Address (REAR) Register Table 16-15. RAM ECC Address (REAR) field descriptions
Name 0–31 REAR[31:0] Description SRAM ECC Address Register This 32-bit register contains the faulting access address of the last, properly-enabled SRAM ECC event.
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.8.3
RAM ECC Syndrome Register (RESR)
The RESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC event in the SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the SRAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x65 0 R W Reset: – – – – – – – – 1 2 3 RESR[7:0] 4 5 6 7
= Unimplemented
Figure 16-15. RAM ECC Syndrome (RESR) Register Table 16-16. RAM ECC Syndrome (RESR) field descriptions
Name 0–7 RESR[7:0] Description SRAM ECC Syndrome Register This 8-bit syndrome field includes 6 bits of Hamming decoded parity plus an odd-parity bit for the entire 39-bit (32-bit data + 7 ECC) code word. The upper 7 bits of the syndrome specify the exact bit position in error for single-bit correctable codewords, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error. For correctable single-bit errors, the mapping shown in Table 16-17 associates the upper 7 bits of the syndrome with the data bit in error.
Table 16-17 associates the upper 7 bits of the ECC syndrome with the exact data bit in error for single-bit correctable codewords. This table follows the bit vectoring notation where the LSB = 0. Note that the syndrome value of 0x01 implies no error condition but this value is not readable when the PRESR is read for the no error case.
Table 16-17. RAM syndrome mapping for single-bit correctable errors
RESR[7:0] 0x00 0x01 0x02 0x04 0x06 0x08 Data bit in error ECC ODD[0] No error ECC ODD[1] ECC ODD[2] DATA ODD BANK[31] ECC ODD[3]
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Chapter 16 Error Correction Status Module (ECSM)
Table 16-17. RAM syndrome mapping for single-bit correctable errors (continued)
RESR[7:0] 0x0a 0x0c 0x0e 0x10 0x12 0x14 0x16 0x18 0x1a 0x1c 0x50 0x20 0x22 0x24 0x26 0x28 0x2a 0x2c 0x58 0x30 0x32 0x34 0x64 0x38 0x62 0x70 0x60 0x40 0x42 0x44 0x46 0x48 0x4a Data bit in error DATA ODD BANK[30] DATA ODD BANK[29] DATA ODD BANK[28] ECC ODD[4] DATA ODD BANK[27] DATA ODD BANK[26] DATA ODD BANK[25] DATA ODD BANK[24] DATA ODD BANK[23] DATA ODD BANK[22] DATA ODD BANK[21] ECC ODD[5] DATA ODD BANK[20] DATA ODD BANK[19] DATA ODD BANK[18] DATA ODD BANK[17] DATA ODD BANK[16 DATA ODD BANK[15] DATA ODD BANK[14] DATA ODD BANK[13] DATA ODD BANK[12] DATA ODD BANK[11] DATA ODD BANK[10] DATA ODD BANK[9] DATA ODD BANK[8] DATA ODD BANK[7] DATA ODD BANK[6] ECC ODD[6] DATA ODD BANK[5] DATA ODD BANK[4] DATA ODD BANK[3] DATA ODD BANK[2] DATA ODD BANK[1]
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Chapter 16 Error Correction Status Module (ECSM)
Table 16-17. RAM syndrome mapping for single-bit correctable errors (continued)
RESR[7:0] 0x4c 0x03,0x05........0x4d > 0x4d Data bit in error DATA ODD BANK[0] Multiple bit error Multiple bit error
16.4.2.8.4
RAM ECC Master Number Register (REMR)
The REMR is a 4-bit register for capturing the XBAR bus master number of the last, properly-enabled ECC event in the SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the SRAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x66 0 R W Reset: 0 0 0 0 – – – – 0 1 0 2 0 3 0 4 5 REMR[3:0] 6 7
= Unimplemented
Figure 16-16. RAM ECC Master Number (REMR) Register Table 16-18. RAM ECC Master Number (REMR) field descriptions
Name 4–7 REMR[3:0] Description SRAM ECC Master Number Register This 4-bit register contains the XBAR bus master number of the faulting access of the last, properly-enabled SRAM ECC event.
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.8.5
RAM ECC Attributes (REAT) register
The REAT is an 8-bit register for capturing the XBAR bus master attributes of the last, properly-enabled ECC event in the SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the SRAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x67 0 R W Reset: – – – – – – – – WRITE 1 2 SIZE[2:0] 3 4 5 6 7
PROTECTION[3:0]
= Unimplemented
Figure 16-17. RAM ECC Attributes (REAT) Register Table 16-19. RAM ECC Attributes (REAT) field descriptions
Name 0 WRITE 1–3 SIZE[2:0] AMBA-AHB HWRITE 0 = AMBA-AHB read access 1 = AMBA-AHB write access AMBA-AHB HSIZE[2:0] 0b000 = 8-bit AMBA-AHB access 0b001 = 16-bit AMBA-AHB access 0b010 = 32-bit AMBA-AHB access 0b1xx = Reserved Description
4–7 AMBA-AHB HPROT[3:0] PROTECTION Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable [3:0] Protection[2]: Bufferable 0 = Non-bufferable, 1 = Bufferable Protection[1]: Mode 0 = User mode, 1 = Supervisor mode Protection[0]: Type 0 = I-Fetch, 1 = Data
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Chapter 16 Error Correction Status Module (ECSM)
16.4.2.8.6
RAM ECC Data Register (REDR)
The REDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event in the SRAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the SRAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base +0x6c 0 R W Reset: – – – – – – – – – – – – – – – – 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
REDR[31:16]
16 R W Reset: –
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
REDR[15:0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
= Unimplemented
Figure 16-18. RAM ECC Data (REDR) Register Table 16-20. RAM ECC Data (REDR) field descriptions
Name 0–31 REDR[31:0] Description SRAM ECC Data Register This 32-bit register contains the data associated with the faulting access of the last, properly-enabled SRAM ECC event. The register contains the data value taken directly from the data bus.
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Chapter 16 Error Correction Status Module (ECSM)
16.4.3
Spp_ips_reg_protection
The spp_ips_reg_protection logic provides hardware enforcement of supervisor mode access protection for five on-platform IPS modules: INTC, ECSM, MPU, STM, and SWT. This logic resides between the on-platform bus sourced by the PBRIDGE bus controller and the individual slave modules. It monitors the bus access type (supervisor or user) and if a user access is attempted, the transfer is terminated with an error and inhibited from reaching the slave module. Identical logic is replicated for each of the five, targeted slave modules. A block diagram of the spp_ips_reg_protection module is shown in Figure 16-19.
ips_xfr_wait[0] ips_xfr_err[0] qual_ips_mod_en[0]
INTC
ips_supervisor_access
ips_xfr_wait[1] ips_xfr_err[1]
ips_module_en[4:0]
qual_ips_mod_en[1]
ECSM
final_ips_xfr_wait[4:0]
ips_xfr_wait[2] ips_xfr_err[2]
PBRIDGE
final_ips_xfr_err[4:0]
SPP_IPS_REG_PROTECTION
qual_ips_mod_en[2]
MPU
ips_xfr_wait[3] ips_xfr_err[3] qual_ips_mod_en[3]
STM
ips_xfr_wait[4] ips_xfr_err[4] qual_ips_mod_en[4]
SWT
Figure 16-19. Spp_Ips_Reg_Protection block diagram
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Chapter 17 System Timer Module (STM)
Chapter 17 System Timer Module (STM)
17.1
17.1.1
Introduction
Overview
The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256).
17.1.2
Features
The STM has the following features: • One 32-bit up counter with 8-bit prescaler • Four 32-bit compare channels • Independent interrupt source for each channel • Counter can be stopped in debug mode
17.1.3
Modes of Operation
The STM supports two device modes of operation: normal and debug. When the STM is enabled in normal mode, its counter runs continuously. In debug mode, operation of the counter is controlled by the FRZ bit in the STM_CR register. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it continues to run.
17.2
External Signal Description
The STM does not have any external interface signals.
17.3
Memory Map and Register Definition
The STM programming model has fourteen 32-bit registers. The STM registers can only be accessed using 32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus error termination.
17.3.1
Memory Map
The STM memory map is shown in Table 17-1.
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Table 17-1. STM Memory Map
Address Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x3FFF STM_CCR3 STM_CIR3 STM_CMP3 STM_CCR2 STM_CIR2 STM_CMP2 STM_CCR1 STM_CIR1 STM_CMP1 STM_CCR0 STM_CIR0 STM_CMP0 Register Name STM_CR STM_CNT Register Description STM Control Register STM Counter Value Reserved Reserved STM Channel 0 Control Register STM Channel 0 Interrupt Register STM Channel 0 Compare Register Reserved STM Channel 1 Control Register STM Channel 1 Interrupt Register STM Channel 1 Compare Register Reserved STM Channel 2 Control Register STM Channel 2 Interrupt Register STM Channel 2 Compare Register Reserved STM Channel 3 Control Register STM Channel 3 Interrupt Register STM Channel 3 Compare Register Reserved Size (bits) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W on page 478 on page 478 on page 479 on page 478 on page 478 on page 479 on page 478 on page 478 on page 479 on page 478 on page 478 on page 479 Location on page 476 on page 477
17.3.2
Register Descriptions
The following sections detail the individual registers within the STM programming model. Figure 17-1 shows the conventions used in the register figures.
Always reads 1 1 Always reads 0 0 Write 1 BIT Self-clear 0 R/W BIT Read- BIT Writebit BIT bit only bit only bit BIT to clear w1c N/A
Figure 17-1. Key to register fields
17.3.2.1
STM Control Register (STM_CR)
The STM Control Register (STM_CR) includes the prescale value, freeze control and timer enable bits.
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Offset 0x000
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R CPS W Reset 0 0 0 0 0 0 0 0
0
0
0
0
0
0 FRZ TEN 0
0
0
0
0
0
0
0
Figure 17-2. STM Control Register (STM_CR) Table 17-2. STM_CR Field Descriptions
Field CPS Description Counter Prescaler. Selects the clock divide value for the prescaler (1 - 256). 0x00 = Divide system clock by 1 0x01 = Divide system clock by 2 ... 0xFF = Divide system clock by 256 Freeze. Allows the timer counter to be stopped when the device enters debug mode. 0 = STM counter continues to run in debug mode. 1 = STM counter is stopped in debug mode. Timer Counter Enabled. 0 = Counter is disabled. 1 = Counter is enabled.
FRZ
TEN
17.3.2.2
STM Count Register (STM_CNT)
Access: Read/Write
The STM Count Register (STM_CNT) holds the timer count value.
Offset 0x004
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-3. STM Count Register (STM_CNT)
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Chapter 17 System Timer Module (STM)
Table 17-3. STM_CNT Field Descriptions
Field CNT Description Timer count value used as the time base for all channels. When enabled, the counter increments at the rate of the system clock divided by the prescale value.
17.3.2.3
STM Channel Control Register (STM_CCRn)
The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the timer.
Offset 0x10+0x10*n Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27 0
28
29
30
31
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0 CEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-4. STM Channel Control Register (STM_CCRn) Table 17-4. STM_CCRn Field Descriptions
Field CEN Channel Enable. 0 = The channel is disabled. 1 = The channel is enabled. Description
17.3.2.4
STM Channel Interrupt Register (STM_CIRn)
The STM Channel Interrupt Register (STM_CIRn) has the interrupt flag for channel n of the timer.
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Offset 0x14+0x10*n
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27 0
28
29
30
31
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CIF w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-5. STM Channel Interrupt Register (STM_CIRn) Table 17-5. STM_CIRn Field Descriptions
Field CIF Description Channel Interrupt Flag 0 = No interrupt request. 1 = Interrupt request due to a match on the channel.
17.3.2.5
STM Channel Compare Register (STM_CMPn)
Access: Read/Write
The STM channel compare register (STM_CMPn) holds the compare value for channel n.
Offset 0x18+0x10*n
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CMP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000
Figure 17-6. STM Channel Compare Register (STM_CMPn) Table 17-6. STM_CMPn Register Field Descriptions
Field CMP Description Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the STM_CNT register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set.
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Chapter 17 System Timer Module (STM)
17.4
Functional Description
The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The STM has one 32-bit up counter (STM_CNT) that is used as the time base for all channels. When enabled, the counter increments at the system clock frequency divided by a prescale value. The STM_CR[CPS] field sets the divider to any value in the range from 1 to 256. The counter is enabled with the STM_CR[TEN] bit. When enabled in normal mode the counter continuously increments. When enabled in debug mode the counter operation is controlled by the STM_CR[FRZ] bit. When the STM_CR[FRZ] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug mode. The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary. The STM has four identical compare channels. Each channel includes a channel control register (STM_CCRn), a channel interrupt register (STM_CIRn) and a channel compare register (STM_CMPn). The channel is enabled by setting the STM_CCRn[CEN] bit. When enabled, the channel will set the STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer counter. The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to the STM_CIRn[CIF] bit has no effect. NOTE STM counter does not advance when the system clock is stopped.
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Chapter 18 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
Chapter 18 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
18.1 Overview
The RTC is a free running counter used for time keeping applications. The RTC may be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low power mode). If in a low power mode when the RTC interval is reached, the RTC first generates a wakeup and then assert the interrupt request. The RTC also supports an autonomous periodic interrupt (API) function used to generate a periodic wakeup request to exit a low power mode or an interrupt request.
18.2
Features
Features of the RTC/API include: • 2 selectable counter clock sources — SIRC (128 kHz) — FIRC (16 MHz) • Optional 512 prescaler and optional 32 prescaler • 32-bit counter — Supports times up to 1.5 months with 1 ms resolution — Runs in all modes of operation — Reset when disabled by software and by POR • 12-bit compare value to support interrupt intervals of 1 s up to greater than 1 hr with 1 s resolution • RTC compare value changeable while counter is running • RTC status and control register are reset only by POR • Autonomous periodic interrupt (API) — 10-bit compare value to support wakeup intervals of 1.0 ms to 1 s — Compare value changeable while counter is running • Configurable interrupt for RTC match, API match, and RTC rollover • Configurable wakeup event for RTC match, API match, and RTC rollover
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RTCCNT
sync
APIVAL
22:31 +
APIEN reset 22:31
offset reg
load
== Reserved FIRC SIRC Reserved 3
API wakeup
sync
1
2
div512
0
32-bit counter div32 reset 10:21 == div512en div32en RTCVAL
APIF APIIE API interrupt
CLKSEL[0:1]
CNTEN
RTC wakeup sync sync RTCF RTCIE RTC interrupt ROVRF RTCIE ROVREN
Figure 18-1. RTC/API block diagram
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(cnten & clksel== 2’b11) en Reserved C.G. CELL
(cnten & clksel== 2’b10) en FIRC 2 C.G. CELL 3
(cnten & clksel== 2’b01) en SIRC C.G. CELL 0 1
0 0 C.G. CELL en div 512 1 C.G. CELL en div512en div 32 1 CNTEN 32-bit counter
(cnten & clksel== 2’b00) en Reserved C.G. CELL CLKSEL[0:1]
div32en
Figure 18-2. Clock gating for RTC clocks
18.3
Device-specific information
For MPC5602D, the device specific information is the following: • FIRC and SIRC clocks are provided as counter clocks for the RTC. Default clock on reset is SIRC divided by 4. • The RTC will be reset on destructive reset, with the exception of software watchdog reset. • The RTC provides a configurable divider by 512 to be optionally used when FIRC source is selected.
18.4
18.4.1
Modes of operation
Functional mode
There are two functional modes of operation for the RTC: normal operation and low power mode. In normal operation, all RTC registers can read or written and the input isolation is disabled. The RTC/API
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Chapter 18 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
and associated interrupts are optionally enabled. In low power mode, the bus interface is disabled and the input isolation is enabled. The RTC/API is enabled if enabled prior to entry into low power mode.
18.4.2
Debug mode
On entering into the debug mode the RTC counter freezes on the last valid count if the RTCC[FRZEN] is set. On exit from debug mode counter continues from the frozen value.
18.5
Register descriptions
Table 18-1. RTC/API register map
Address offset 0x0000 0x0004 0x0008 0x000C Register name RTC Supervisor Control Register (RTCSUPV) RTC Control Register (RTCC) RTC Status Register (RTCS) RTC Counter Register (RTCCNT) 0 R/W BIT bit Read- BIT only bit Writeonly bit BIT Write 1 BIT to clear w1c Location on page 484 on page 486 on page 488 on page 489 Self- 0 clear BIT bit N/A
The registers listed in Table 18-1 are described in the following sections.
Always reads 1
1
Always reads 0
Figure 18-3. Key to register fields
18.5.1
RTC Supervisor Control Register (RTCSUPV)
The RTCSUPV register contains the SUPV bit which determines whether other registers are accessible in supervisor mode or user mode. NOTE RTCSUPV register is accessible only in supervisor mode.
Offset: RTC_BASE + 0x0000 0 SUPV R W POR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-4. RTC Supervisor Control Register (RTCSUPV)
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Chapter 18 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
Table 18-2. RTCSUPV register field descriptions
Field 0 SUPV Description RTC Supervisor Bit 0 All registers are accessible in both user as well as supervisor mode. 1 All other registers are accessible in supervisor mode only.
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18.5.2
RTC Control Register (RTCC)
The RTCC register contains: • RTC counter enable • RTC interrupt enable • RTC clock source select • RTC compare value • API enable • API interrupt enable • API compare value
Offset: RTC_BASE + 0x0004 0 R W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT EN 1 RTCIE 2 FRZ EN 3 ROVR EN 4 5 6 7 8 9 10 11 12 Access: User read/write 13 14 15
RTCVAL[0:11]
16 R W POR 0 API EN
17 APIIE
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CLKSEL[0:1]
DIV512 DIV32 EN EN
APIVAL[0:9]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-5. RTC Control Register (RTCC) Table 18-3. RTCC register field descriptions
Field 0 CNTEN Description Counter Enable The CNTEN bit enables the RTC counter. Making CNTEN bit 1’b0 has the effect of asynchronously resetting (synchronous reset negation) all the RTC and API logic. This allows for the RTC configuration and clock source selection to be updated without causing synchronization issues. 1 Counter enabled 0 Counter disabled RTC Interrupt Enable The RTCIE bit enables interrupts requests to the system if RTCF is asserted. 1 RTC interrupts enabled 0 RTC interrupts disabled Freeze Enable Bit The counter freezes on entering the debug mode (as the ipg_debug is detected active) on the last valid count value if the FRZEN bit is set. After coming of the debug mode counter starts from the frozen value. 0 Counter does not freeze in debug mode. 1 Counter freezes in debug mode.
1 RTCIE
2 FRZEN
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Table 18-3. RTCC register field descriptions (continued)
Field 3 ROVREN Description Counter Roll Over Wakeup/Interrupt Enable The ROVREN bit enables wakeup and interrupt requests when the RTC has rolled over from 0xFFFF_FFFF to 0x0000_0000. The RTCIE bit must also be set in order to generate an interrupt from a counter rollover. 1 RTC rollover wakeup/interrupt enabled 0 RTC rollover wakeup/interrupt disabled
4:15 RTC Compare Value RTCVAL[0:11] The RTCVAL bits are compared to bits 10:21 of the RTC counter and if match sets RTCF. RTCVAL can be updated when the counter is running. 16 APIEN Autonomous Periodic Interrupt Enable The APIEN bit enables the autonomous periodic interrupt function. 1 API enabled 0 API disabled API Interrupt Enable The APIIE bit enables interrupts requests to the system if APIF is asserted. 1 API interrupts enabled 0 API interrupts disabled Clock Select The CLKSEL[0:1] bits select the clock source for the RTC. CLKSEL may only be updated when CNTEN is 0. The user should ensure that oscillator is enabled before selecting it as a clock source for RTC. 00 Reserved 01 SIRC 10 FIRC 11 Reserved Divide by 512 enable The DIV512EN bit enables the 512 clock divider. DIV512EN may only be updated when CNTEN is 0. 0 Divide by 512 is disabled. 1 Divide by 512 is enabled. Divide by 32 enable The DIV32EN bit enables the 32 clock divider. DIV32EN may only be updated when CNTEN is 0. 0 Divide by 32 is disabled. 1 Divide by 32 is enabled. API Compare Value The APIVAL bits are compared with bits 22:31 of the RTC counter and if match asserts an interrupt/wakeup request. APIVAL may only be updated when APIEN is 0 or API function is undefined. Note: API functionality starts only when APIVAL is non zero. The first API interrupt takes two more cycles because of synchronization of APIVAL to the RTC clock. After that interrupts are periodic in nature. The minimum supported value of APIVAL is 4.
17 APIIE
18:19 CLKSEL[0:1]
20 DIV512EN
21 DIV32EN
22:31 APIVAL[0:9]
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18.5.3
RTC Status Register (RTCS)
The RTCS register contains: • RTC interrupt flag • API interrupt flag • ROLLOVR Flag
Offset: RTC_BASE + 0x0008 0 R W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 RTC F 3 4 5 6 7 8 9 10 11 12 Access: User read/write 13 14 15
16 R W POR 0
17
18 API F
19
20
21 ROVR F
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-6. RTC Status Register (RTCS) Table 18-4. RTCS register field descriptions
Field 2 RTCF Description RTC Interrupt Flag The RTCF bit indicates that the RTC counter has reached the counter value matching RTCVAL. RTCF is cleared by writing a 1 to RTCF. Writing a 0 to RTCF has no effect. 1 RTC counter matches RTCVAL 0 RTC counter is not equal to RTCVAL API Interrupt Flag The APIF bit indicates that the RTC counter has reached the counter value matching API offset value. APIF is cleared by writing a 1 to APIF. Writing a 0 to APIF has no effect. 1 API interrupt 0 No API interrupt Note: The periodic interrupt comes after APIVAL[0:9] + 1’b1 RTC counts Counter Roll Over Interrupt Flag The ROVRF bit indicates that the RTC has rolled over from 0xffff_ffff to 0x0000_0000. ROVRF is cleared by writing a 1 to ROVRF. 1 RTC has rolled over 0 RTC has not rolled over
18 APIF
21 ROVRF
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18.5.4
RTC Counter Register (RTCCNT)
The RTCCNT register contains the current value of the RTC counter.
Offset: RTC_BASE + 0x000C 0 R W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RTCCNT[0:31]
Figure 18-7. RTC Counter Register (RTCCNT) Table 18-5. RTCCNT register field descriptions
Field Description
0:31 RTC Counter Value RTCCNT[0:31] Due to the clock synchronization, the RTCCNT value may actually represent a previous counter value.
18.6
RTC functional description
The RTC consists of a 32-bit free running counter enabled with the RTCC[CNTEN] bit (CNTEN when negated asynchronously resets the counter and synchronously enables the counter when enabled). The value of the counter may be read via the RTCCNT register. Note that due to the clock synchronization, the RTCCNT value may actually represent a previous counter value. The difference between the counter and the read value depends on ratio of counter clock and ipg_clk. Maximum possible difference between the two is 6 count values. The clock source to the counter is selected with the RTCC[CLKSEL] field, which gives three options for clocking the RTC/API. The three clock sources are assumed to be one 16 MHz source, one 32 kHz source and one 128 kHz source. The output of the clock mux can be optionally divided by combination of 512 and 32 to give a 1 ms RTC/API count period for different clock sources. Note that the RTCC[CNTEN] bit must be disabled when the RTC/API clock source is switched. When the counter value for counter bits 10:21 match the 12-bit value in the RTCC[RTCVAL] field, then the RTCS[RTCF] interrupt flag bit is set (after proper clock synchronization). If the RTCC[RTCIE] interrupt enable bit is set, then the RTC interrupt request is generated. The RTC supports interrupt requests in the range of 1 s to 4096 s (> 1 hr) with a 1 s resolution. The RTCC[RTCVAL] field may only be updated when the RTCC[CNTEN] bit is cleared to disable the counter. If there is a match while in low power mode then the RTC will first generate a wakeup request to force a wakeup to run mode, then the RTCF flag will be set. A rollover wakeup and/or interrupt can be generated when the RTC transitions from a count of 0xFFFF_FFFF to 0x0000_0000. The rollover flag is enabled by setting the RTCC[ROVREN] bit. An RTC counter rollover with this bit will cause a wakeup from low power mode. An interrupt request is generated for an RTC counter rollover when both the RTCC[ROVREN] and RTCC[RTCIE] bits are set. All the flags and counter values are synchronized with ipg_clk. It is assumed that ipg_clk frequency is always more than or equal to the rtc_clk used to run the counter.
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18.7
API functional description
Setting the RTCC[APIEN] bit enables the autonomous interrupt function. The 10-bit RTCC[APIVAL] field selects the time interval for triggering an interrupt and/or wakeup event. Since the RTC is a free running counter, the APIVAL is added to the current count to calculate an offset. When the counter reaches the offset count, a interrupt and/or wakeup request is generated. Then the offset value is recalculated and again re-triggers a new request when the new value is reached. APIVAL may only be updated when APIEN is disabled. When a compare is reached, the RTCS[APIF] interrupt flag bit is set (after proper clock synchronization). If the RTCC[APIIE] interrupt enable bit is set, then the API interrupt request is generated. If there is a match while in low power mode, then the API will first generate a wakeup request to force a wakeup into normal operation, then the APIF flag will be set.
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Chapter 19 Boot Assist Module (BAM)
Chapter 19 Boot Assist Module (BAM)
This chapter describes the Boot Assist Module (BAM).
19.1
Overview
The Boot Assist Module is a block of read-only memory containing VLE code which is executed according to the boot mode of the device. The BAM allows to download code into internal SRAM through the following serial communication interfaces and to execute it afterwards: • FlexCAN • LINFlex
19.1.1
Features
The BAM provides the following features: • Locate and detect application boot code • MPC5602D in static mode if internal flash is not initialized or invalid • Programmable 64-bit password protection for serial boot mode • Serial boot loads the application boot code from a FlexCAN or LINFlex interface into internal SRAM • Censorship protection for internal flash module
19.1.2
Boot modes
The MPC5602D supports the following boot modes: • Single Chip (SC) — The device boots from the first bootable section of the Flash main array. • Serial Boot (SBL) — The device downloads boot code from either LINFlex or FlexCAN interface and then executes it (see Section 19.3.1, “Entering boot modes). If booting is not possible with the selected configuration (for example, if no Boot ID is found in the selected boot location) then the device enters the static mode.
19.2
Memory map
The BAM code resides in a reserved 8 Kbyte ROM mapped from address 0xFFFF_C000. Table 19-1 shows the address space and memory used by the BAM application.
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Table 19-1. BAM memory organization
Parameter BAM entry point Downloaded code base address Address 0xFFFF_C000 0x4000_0100
The code is downloaded to a SRAM location which can be any 4-byte aligned location starting from the address 0x4000_0100.
19.3
19.3.1
Functional description
Entering boot modes
The MPC5602D detects the boot mode based on external pins and device status. The boot sequence is shown in Figure 19-1. To boot either from FlexCAN or LINFlex, the device must be forced into an Alternate Boot Loader Mode via the FAB (Force Alternate Boot Mode) which must be asserted before initiating the reset sequence. The type of alternate boot mode is selected according to the ABS (Alternate Boot Selector) pin (see Table 19-2).
POR
FABM = 1
Y
ABS = ?
ABS=0
Serial Boot (SBL) LINFlex
N
ABS=1
Serial Boot (SBL) FlexCAN
Flash Boot-ID in any boot sector?
Flash Boot from lowest sector
no Boot-ID
Static Mode
Figure 19-1. Boot mode selection
1
The gray blocks represent action done by hardware; the white ones action done by software (BAM).
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Table 19-2. Hardware configuration to select boot mode
FAB 1 1 0 0 ABS 0 1 — — BOOT_FROM_BKP_RAM 0 0 0 0 Boot ID — — Valid Not found Boot mode LINFlex FlexCAN SC (Single Chip) Static mode
19.3.2
Reset Configuration Half Word Source (RCHW)
MPC5602D Flash is partitioned into boot sectors as shown in Table 19-4. Each boot sector contains at offset 0x00 the Reset Configuration Half-Word (RCHW).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 19-2. Reset Configuration Half Word (RCHW) Table 19-3. RCHW field descriptions
Field 0-70-7 7 8-15 BOOT_ID[0:7] Reserved VLE Bit Is valid if its value is 0x5A, then the sector is considered bootable Description
Figure 19-3. MPC5602D Flash partitioning and RCHW search Table 19-4. Flash boot sector
Block 0 1 2 3 4 Address 0x0000_0000 0x0000_8000 0x0000_C000 0x0001_0000 0x0001_8000
19.3.3
Single chip boot mode
In single chip boot mode the hardware searches a flash boot sector for a valid boot ID. As soon the device detects a bootable sector, it jumps within this sector and reads the 32-bit word at offset 0x4. This word is the address where the startup code is located (reset boot vector). Then the device executes this startup code. A user application should have a valid instruction at the reset boot vector address.
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If a valid RCHW is not found, the BAM code is executed. In this case, BAM moves the MPC5602D into static mode1.
19.3.3.1
Boot and alternate boot
Some applications require an alternate boot sector so that the main boot can be erased and reprogrammed in the field. When an alternate boot is needed, the user can create two bootable sectors; the lowest sector is the main boot sector and the highest is the alternate boot sector. The alternate boot sector does not need to be contiguous with the main boot sector. This scheme ensures that there is always one active boot sector by erasing one of the boot sectors only.
19.3.4
19.3.4.1
Boot through BAM
Executing BAM
Single chip boot mode is managed by hardware, not by the BAM application. BAM is executed only in the following two cases: • Serial boot mode has been selected by FAB pin • Hardware has not found a valid Boot-ID in any Flash boot locations If one of these conditions is true, the device fetches code at location 0xFFFF_C000 and BAM application starts.
19.3.4.2
BAM software flow
Figure 1-4 illustrates the BAM logic flow. The BMODE field of the SSCM_STATUS register indicates which boot has to be executed (see Table 19-5). If the BMODE field shows either a single chip value (011) or the reserved values, the boot mode is not considered valid and the BAM pushes the device into static mode. In all other cases the code of the relative boot is called. Data is downloaded and saved into proper SRAM location.
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Chapter 19 Boot Assist Module (BAM)
Table 19-5. Fields of SSCM STATUS register used by BAM
Field 8-10 Device Boot Mode BMODE 000 Reserved [0:2] 001 FlexCAN_0 Serial Boot Loader 011 Single Chip 100 Reserved 101 Reserved 110 Reserved 111 Reserved This field is only updated during reset. Description
Then, the initial device configuration is restored and the code jumps to the address of downloaded code. At this point BAM has just finished its task. If there is any error (such as communication error, wrong boot selected), BAM restores the default configuration and puts the device into static mode. Static mode means the device enters the low power mode SAFE and the processor executes a wait instruction. It is needed if the device cannot boot in the mode which was selected. During BAM execution and after, the mode reported by the field S_CURRENT_MODE of the register ME_GS in the MC_ME module is “DRUN.”
19.3.4.3
BAM resources
BAM uses/initializes the following MCU resources: • MC_ME and MC_CGM to initialize mode and clock sources • FlexCAN_0, LINFlex _0 and their pads when performing serial boot mode • SSCM during password check (see Figure 19-4) • SSCM to check the boot mode (see Table 19-5) • xternal crystal oscillator As already mentioned, the initial configuration is restored before executing the downloaded code. The system clock is selected directly from the external crystal oscillator. Thus, the oscillator frequency defines baud rates for serial interfaces used to download the user application (see Table 19-6).
Table 19-6. Serial boot mode – baud rates
FXOSC frequency (MHz) fFXOSC 8 12 16 LINFlex baud rate (baud) fFXOSC/833 9600 14400 19200 CAN bit rate (bit/s) fFXOSC/40 200K 300K 400K
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19.3.4.4
Download and execute the new code
From a high level perspective, the download protocol follows these steps: 1. Send 64-bit password 2. Send start address, size of downloaded code in bytes and VLE bit 3. Download data 4. Execute code from start address Each step must be completed before the next step starts. The communication is done in half duplex manner, any transmission from the host is followed by the MCU transmission: • Host sends data to MCU and starts waiting • MCU echoes to host the data received • Host verifies if echoes is correct — If data is correct host can continue to send data — If data is not correct host stops to transmit and MCU need to be reset All multi-byte data structures are sent with MSB first. A more detailed description of these steps follows.
19.3.4.5
Download 64-bit password and password check
The first 64 bits received represent the password. This password is sent to the Password Check procedure which verifies if it is correct. Password check data flow is shown in Figure 19-4. In case of flash with public access, the received password is compared with the public password 0xFEED_FACE_CAFE_BEEF. If public access is not allowed but the flash is not secured, the received password is compared with the value saved on NVPWD0 and NVPWD1 registers. In both previous cases, comparison is done by the BAM the application. If it goes wrong, BAM pushes the MCU into static mode. If public access is not allowed and flash is secured, the password is written into the SSCM.PWCMPH-L registers. After a fixed waiting time, BAM verifies again the Flash censorship mode status: • : Flash is now unsecured and BAM continues its task. • : Flash is still secured because password was wrong; BAM puts MCU to SAFE mode.
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SSCM. STATUS. Flash public access disabled
enabled
Comparison with FEEDFACE CAFEBEEF
SSCM. STATUS. Flash censor ship
disabled
Comparison with password saved on NVPWD[0:1]
enabled
Write received password to SSCM.PWCMPH-L
Wait
Verify whether Flash is unsecured
Figure 19-4. Password check flow
NOTE
If public access is not allowed and the flash memory is secured, the received password is compared by hardware against the password stored in NVPWD0 and NVPWD1. Only in this case (no public password and secured flash) the provided words must be swapped (NVPWD1|NVPWD0). NOTE In a secured device, starting with a serial boot, it is possible to read the content of the four flash locations where the RCHW can be stored. For example, if the RCHW is stored at address 0x00000000, the reads at address 0x00000000, 0x00000004, 0x00000008 and 0x0000000C will return a correct value. Any other flash address cannot be accessed.
19.3.4.6
Download start address, VLE bit and code size
The next 8 bytes received by the MCU contain a 32-bit Start Address, the VLE mode bit and a 31-bit code Length as shown in Figure 19-5. The VLE bit (Variable Length Instruction) is used to indicate which instruction set the code has been compiled for. This device family supports only VLE = 1; the bit is used for backward compatibility.
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The Start Address defines where the received data will be stored and where the MCU will branch after the download is finished. The two LSB bits of the Start Address are ignored by the BAM program, such that the loaded code should be 32-bit word aligned. The Length defines how many data bytes have to be loaded.
START_ADDRESS[31:16]
START_ADDRESS[15:0]
VLE
CODE_LENGTH[30:16]
CODE_LENGTH[15:0]
Figure 19-5. Start address, VLE bit and download size in bytes
19.3.4.7
Download data
Each byte of data received is stored in the device’s SRAM, starting from the address specified in the previous protocol step. The address increments until the number of bytes of data received matches the number of bytes specified in the previous protocol step. Since the SRAM is protected by 32-bit wide Error Correction Code (ECC), BAM always writes bytes into SRAM grouped into 32-bit words. If the last byte received does not fall onto a 32-bit boundary, BAM fills it with 0 bytes. Then a “dummy” word (0x0000_0000) is written to avoid ECC error during core prefetch. NOTE In uncensored devices it is possible to download code via LINFlex or FlexCAN (Serial Boot Mode) into internal SRAM even if the 64-bit private password stored in the flash and provided during the boot sequence is an illegal password.
19.3.4.8
Execute code
The BAM program waits for the last echo message transmission being completed. Then it restores the initial MCU configuration and jumps to the loaded code at Start Address which was received in step 2 of the protocol. At this point BAM has finished its tasks and MCU is controlled by new code executing from SRAM. NOTE Watchdog is disabled at the start of BAM execution. In the case of an unexpected issue during BAM execution, the CPU may be stalled and an external reset needs to be generated to recover.
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19.3.5
19.3.5.1
Boot from UART
Configuration
Boot according to the UART boot mode download protocol (see Section 19.3.5.2, “Protocol) is performed by the LINFlex_0 module. Pins used are: • • LIN0TX mapped on PB[2] LIN0RX mapped on PB[3]
Boot from UART uses the system clock driven by the external crystal oscillator. The LINFlex controller is configured to operate at a baud rate = system clock frequency/833 (see Table 19-6 for baud rate example), using an 8-bit data frame without parity bit and 1 stop bit.
Figure 19-6. LINFlex bit timing in UART mode
19.3.5.2
Protocol
Table 19-7. UART boot mode download protocol
Table 19-7 summarizes the protocol and BAM action during this boot mode.
Protocol Host sent message step 1 2 3 64-bit password (MSB first) 32-bit store address VLE bit + 31-bit number of bytes (MSB first) 8 bits of raw binary data
BAM response message 64-bit password 32-bit store address VLE bit + 31-bit number of bytes (MSB first) 8 bits of raw binary data
Action Password checked for validity and compared against stored password. Load address is stored for future use. Size of download are stored for future use. Verify if VLE bit is set to 1 8-bit data are packed into a 32-bit word. This word is saved into SRAM starting from the “Load address”. “Load address” increments until the number of data received and stored matches the size as specified in the previous step. Branch to downloaded code
4
5
None
None
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19.3.6
19.3.6.1
Boot from FlexCAN
Configuration
Boot according to the FlexCAN boot mode download protocol (see Section 19.3.6.2, “Protocol) is performed by the FlexCAN_0 module. Pins used are: • • mapped on PB[0] mapped on PB[1] NOTE When the serial download via FlexCAN is selected and the device is part of a CAN network, in case of CAN traffic, the serial download protocol may unexpectedly stop . If so it is necessary that CAN traffic is not present on the bus, to not disturb the serial boot process. Boot from FlexCAN uses the system clock driven by the external crystal oscillator. The FlexCAN controller is configured to operate at a baud rate = system clock frequency/40 (see Table 19-6 for examples of baud rate). It uses the standard 11-bit identifier format detailed in FlexCAN 2.0A specification. FlexCAN controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta before the end, as shown in Figure 19-7.
NRZ signal
SYNC_SEG
Time segment 1
Time segment 2
1 time quanta
7 time quanta 1 bit time
2 time quanta
Transmit point 1 time quanta = 4 system clock periods
Sample point
Figure 19-7. FlexCAN bit timing
19.3.6.2
Protocol
Table 19-8 summarizes the protocol and BAM action during this boot mode. All data are transmitted byte wise.
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Table 19-8. FlexCAN boot mode download protocol
Protoco l Host sent message step 1 2 CAN ID 0x011 + 64-bit password CAN ID 0x012 + 32-bit store address + VLE bit + 31-bit number of bytes CAN ID 0x013 + 8 to 64 bits of raw binary data BAM response message CAN ID 0x001 + 64-bit password Action
Password checked for validity and compared against stored password
CAN ID 0x002 + Load address is stored for future use. 32-bit store Size of download are stored for future use. address + VLE Verify if VLE bit is set to 1 bit + 31-bit number of bytes CAN ID 0x003 + 8 to 64 bits of raw binary data 8-bit data are packed into 32-bit words. These words are saved into SRAM starting from the “Load address”. “Load address” increments until the number of data received and stored matches the size as specified in the previous step. Branch to downloaded code
3
5
None
None
Table 19-9. System clock frequency related to external clock frequency
fFXOSC (MHz) 4–8 8–12 12–16
1
fFIRC/fFXOSC1 4–2 2–4/3 4/3–1
fsys (MHz) 16–32 32–48 36–48
These values and consequently the fsys suffer from the precision of the 16 MHz fast internal RC oscillator used to measure fFXOSC through CMU module.
19.3.7
Interrupts
No interrupts are generated by or are enabled by the BAM.
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Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
20.1
20.1.1
Introduction
Overview of the eMIOS module
The eMIOS provides functionality to generate or measure time events. The eMIOS uses timer channels that are reduced versions of the unified channel (UC) module used on MPC555x devices. Each channel provides a subset of the functionality available in the unified channel, at a resolution of 16 bits, and provides a user interface that is consistent with previous eMIOS implementations.
20.1.2
• • • •
Features of the eMIOS module
• • • •
1 eMIOS block with 28 channel — All 28 channels with OPWMT, which can be connected to the CTU One global prescaler 16-bit data registers 10 x 16-bit wide counter buses — Counter buses B, C, D, and E can be driven by Unified Channel 0, 8, 16, and 24, respectively — Counter bus A is driven by the Unified Channel #23 — Several channels have their own time base, alternative to the counter buses — Shared timebases through the counter buses — Synchronization among timebases Control and Status bits grouped in a single register Shadow FLAG register State of the UC can be frozen for debug purposes Motor control capability
20.1.3
Modes of operation
The Unified Channels can be configured to operate in the following modes: • General purpose input/output • Single Action Input Capture • Single Action Output Compare • Input Pulse Width Measurement • Input Period Measurement • Double Action Output Compare • Modulus Counter • Modulus Counter Buffered
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• • • •
Output Pulse Width and Frequency Modulation Buffered Output Pulse Width Modulation Buffered Output Pulse Width Modulation with Trigger Center Aligned Output Pulse Width Modulation Buffered
These modes are described in Section 20.4.1.1, “UC modes of operation. Each channel can have a specific set of modes implemented, according to device requirements. If an unimplemented mode (reserved) is selected, the results are unpredictable such as writing a reserved value to MODE[0:6] in Section 20.3.2.8, “eMIOS UC Control (EMIOSC[n]) Register.
20.1.4
Channel implementation
Figure 20-1 shows the channel configuration of the two eMIOS blocks.
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Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Ch9 Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16 Ch17 Ch18 Ch19 Ch20 Ch21 Ch22 Ch23 Ch24 Ch25 Ch26 Ch27
Channel Functionality Counter Bus_B
TYPE G • • • • • • • • • MCB OPWMT OPWMB OPWFMB OPWMCB IPWM, IPM DAOC SAIC, SAOC GPIO
Bus Clk
Global Prescaler 8-bit Counter
Counter Bus_C
TYPE X • • • • • • MC, MCB OPWMT OPWMB OPWFMB SAIC, SAOC GPIO
Counter Bus_A
Counter Bus_D
TYPE H • • • • • • OPWMT OPWMB IPWM, IPM DAOC SAIC, SAOC GPIO
Counter Bus_E
TYPE Y • • • • OPWMT OPWMB SAIC, SAOC GPIO
eMIOS_0
Key DAOC GPIO IPM IPWM MC MCB OPWMB OPWMT OPWFMB OPWMCB SAIC SAOC Dual Action Output Compare General Purpose Input Output Input Period Measurement Input Pulse Width Measurement Modulus Counter Buffered Modulus Counter Buffered Output Pulse Width Modulation Buffered Output Pulse Width Modulation with Trigger Buffered Output Pulse Width and Frequency Modulation Center Aligned Output PWM Buffered with Dead-Time Single Action Input Capture Single Action Output Compare
Figure 20-1. Channel configuration
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20.1.5
Unified channel block
Figure 20-12 shows the block diagram of the Unified Channel Block as it is implemented on this device.
20.1.5.1
Channel mode selection
Channel modes are selected using the mode selection bits MODE[0:6] in the eMIOS UC Control (EMIOSC[n]) Register. Table 20-13 provides the specific mode selection settings for the eMIOS implementation on this device.
20.2
External signal description
For information on eMIOS external signals on this device, please refer to the signal description chapter of the reference manual.
20.3
20.3.1
Memory map and register description
Memory map
The overall address map organization is shown in Table 20-1.
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20.3.1.1
Unified Channel memory map
Table 20-1. eMIOS memory map
eMIOS base address 0x000–0x003 0x004–0x007 0x008–0x00B 0x00C–0x00F 0x010–0x01F 0x020–0x11F Description eMIOS Module Configuration Register (EMIOSMCR) eMIOS Global FLAG (EMIOSGFLAG) Register Location on page 508 on page 509
eMIOS Output Update Disable (EMIOSOUDIS) Register on page 510 eMIOS Disable Channel (EMIOSUCDIS) Register Reserved Channel [0] to Channel [7] Channel [8] to Channel [15] Channel [16] to Channel [23] Channel [24] to Channel [27] Reserved on page 511 — —
0x120–0x21F
—
0x220–0x31F
—
0x320–0x39F
—
0x3A0–0xFFF
—
Addresses of Unified Channel registers are specified as offsets from the channel’s base address; otherwise the eMIOS base address is used as reference. Table 20-2 describes the Unified Channel memory map.
Table 20-2. Unified Channel memory map
UC base address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18–0x1F Description eMIOS UC A (EMIOSA[n]) Register eMIOS UC B (EMIOSB[n]) Register eMIOS UC Counter (EMIOSCNT[n]) Register eMIOS UC Control (EMIOSC[n]) Register eMIOS UC Status (EMIOSS[n]) Register eMIOS UC Alternate A Register (EMIOSALTA[n]) Reserved Location on page 511 on page 512 on page 513 on page 513 on page 518 on page 519 —
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20.3.2
Register description
All control registers are 32 bits wide. Data registers and counter registers are 16 bits wide.
20.3.2.1
eMIOS Module Configuration Register (EMIOSMCR)
The EMIOSMCR contains global control bits for the eMIOS block.
Address: eMIOS base address +0x00 0 R W Reset 0 0 0 0 1 2 3 GTBE 4 0 5 GPREN 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
MDIS FRZ
0
0
0
0
0
0
0
0
0
0
0
0
0
16 R W Reset 0
17
18
19
20
21
22
23
24 0
25 0
26 0
27 0
28 0
29 0
30 0
31 0
GPRE[0:7]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-2. eMIOS Module Configuration Register (EMIOSMCR) Table 20-3. EMIOSMCR field descriptions
Field 1 MDIS Description Module Disable Puts the eMIOS in low power mode. The MDIS bit is used to stop the clock of the block, except the access to registers EMIOSMCR, EMIOSOUDIS and EMIOSUCDIS. 1 = Enter low power mode 0 = Clock is running Freeze Enables the eMIOS to freeze the registers of the Unified Channels when Debug Mode is requested at MCU level. Each Unified Channel should have FREN bit set in order to enter freeze state. While in Freeze state, the eMIOS continues to operate to allow the MCU access to the Unified Channels registers. The Unified Channel will remain frozen until the FRZ bit is written to ‘0’ or the MCU exits Debug mode or the Unified Channel FREN bit is cleared. 1 = Stops Unified Channels operation when in Debug mode and the FREN bit is set in the EMIOSC[n] register 0 = Exit freeze state Global Time Base Enable The GTBE bit is used to export a Global Time Base Enable from the module and provide a method to start time bases of several blocks simultaneously. 1 = Global Time Base Enable Out signal asserted 0 = Global Time Base Enable Out signal negated Note: The Global Time Base Enable input pin controls the internal counters. When asserted, Internal counters are enabled. When negated, Internal counters disabled.
2 FRZ
3 GTBE
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Table 20-3. EMIOSMCR field descriptions
Field 5 GPREN Description Global Prescaler Enable The GPREN bit enables the prescaler counter. 1 = Prescaler enabled 0 = Prescaler disabled (no clock) and prescaler counter is cleared Global Prescaler The GPRE[0:7] bits select the clock divider value for the global prescaler, as shown in Table 20-4.
13:23 GPRE[0:7]
Table 20-4. Global prescaler clock divider
GPRE[0:7] 00000000 00000001 00000010 00000011 . . . . 11111110 11111111 Divide ratio 1 2 3 4 . . . . 255 256
20.3.2.2
eMIOS Global FLAG (EMIOSGFLAG) Register
The EMIOSGFLAG is a read-only register that groups the flag bits (F[27:0]) from all channels. This organization improves interrupt handling on simpler devices. Each bit relates to one channel. For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register.
Address: eMIOS base address +0x04 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 F27 5 F26 6 F25 7 F24 8 F23 9 F22 10 F21 11 F20 12 F19 13 F18 14 F17 15 F16
16 R F15 W Reset 0
17 F14
18 F13
19 F12
20 F11
21 F10
22 F9
23 F8
24 F7
25 F6
26 F5
27 F4
28 F3
29 F2
30 F1
31 F0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-3. eMIOS Global FLAG (EMIOSGFLAG) Register
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Table 20-5. EMIOSGFLAG register field descriptions
Field 4–31 F27:F0 Channel [n] Flag bit Description
20.3.2.3
eMIOS Output Update Disable (EMIOSOUDIS) Register
Address: eMIOS base address +0x08 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4
OU27
5
OU26
6
OU25
7
OU24
8
OU23
9
OU22
10
OU21
11
OU20
12
OU19
13
OU18
14
OU17
15
OU16
16 R W Reset 0
OU15
17
OU14
18
OU13
19
OU12
20
OU11
21
OU10
22
OU9
23
OU8
24
OU7
25
OU6
26
OU5
27
OU4
28
OU3
29
OU2
30
OU1
31
OU0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-4. eMIOS Output Update Disable (EMIOSOUDIS) Register Table 20-6. EMIOSOUDIS register field descriptions
Field 4:31 OU27:OU0 Description Channel [n] Output Update Disable bit When running MC, MCB or an output mode, values are written to registers A2 and B2. OU[n] bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel. 1 = Transfers disabled 0 = Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the next period. Unless stated otherwise, transfer occurs immediately.
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20.3.2.4
eMIOS Disable Channel (EMIOSUCDIS) Register
Address: eMIOS base address +0x0C 0 R W Reset 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1 0 2 0 3 0 4 5 6 7 8 9 10 11 12 13 14 15
CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS 27 26 25 24 23 22 21 20 19 18 17 16
16 R W Reset 0/1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS CHDIS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Figure 20-5. eMIOS Enable Channel (EMIOSUCDIS) Register Table 20-7. EMIOSUCDIS register field descriptions
Field 4:31 CHDIS27:0 Description Enable Channel [n] bit The CHDIS[n] bit is used to disable each of the channels by stopping its respective clock. 1 = Channel [n] disabled 0 = Channel [n] enabled
20.3.2.5
eMIOS UC A (EMIOSA[n]) Register
Address: UC[n] base address + 0x00 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A[0:15]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-6. eMIOS UC A Register (EMIOSA[n])
Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be assigned to address EMIOSA[n]. Both A1 and A2 are cleared by reset. Figure 20-8 summarizes the EMIOSA[n] writing and reading accesses for all operation modes. For more information see Section 20.4.1.1, “UC modes of operation.
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20.3.2.6
eMIOS UC B (EMIOSB[n]) Register
Address: UC[n] base address + 0x04 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
B[0:15]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-7. eMIOS UC B (EMIOSB[n]) Register
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address EMIOSB[n]. Both B1 and B2 are cleared by reset. Table 20-8 summarizes the EMIOSB[n] writing and reading accesses for all operation modes. For more information see Section 20.4.1.1, “UC modes of operation. Depending on the channel configuration, it may have EMIOSB register or not. This means that, if at least one mode that requires the register is implemented, then the register is present; otherwise it is absent.
Table 20-8. EMIOSA[n], EMIOSB[n] and EMIOSALTA[n] values assignment
Register access Operation mode write GPIO SAIC1 SAOC1 IPWM IPM DAOC MC1 OPWMT MCB1 OPWFMB OPWMCB OPWMB
1
read A1 A2 A1 A2 A2 A1 A1 A1 A1 A1 A1 A1
write B1,B2 B2 B2 — — B2 B2 B2 B2 B2 B2 B2
read B1 B2 B2 B1 B1 B1 B2 B1 B2 B1 B1 B1
alt write A2 — — — — — — A2 — — — —
alt read A2 — — — — — — A2 — — — —
A1, A2 — A2 — — A2 A2 A1 A2 A2 A2 A2
In these modes, the register EMIOSB[n] is not used, but B2 can be accessed.
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20.3.2.7
eMIOS UC Counter (EMIOSCNT[n]) Register
Address: UC[n] base address + 0x08 0 R W
1
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
10 0
11 0
12 0
13 0
14 0
15 0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 R W1 Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
C[0:15]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-8. eMIOS UC Counter (EMIOSCNT[n]) Register
1
In GPIO mode or Freeze action, this register is writable.
The EMIOSCNT[n] register contains the value of the internal counter. When GPIO mode is selected or the channel is frozen, the EMIOSCNT[n] register is read/write. For all others modes, the EMIOSCNT[n] is a read-only register. When entering some operation modes, this register is automatically cleared (refer to Section 20.4.1.1, “UC modes of operation for details). Depending on the channel configuration it may have an internal counter or not. It means that if at least one mode that requires the counter is implemented, then the counter is present; otherwise it is absent. Channels of type X and G have the internal counter enabled, so their timebase can be selected by channel's BSL[1:0]=11:eMIOS_A - channels 0 to 8, 16, 23 and 24, eMIOS_B = channels 0, 8, 16, 23 and 24. Other channels from the above list don't have internal counters.
20.3.2.8
eMIOS UC Control (EMIOSC[n]) Register
The Control register gathers bits reflecting the status of the UC input/output signals and the overflow condition of the internal counter, as well as several read/write control bits.
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Address: UC[n] base address + 0x0C 0 FREN R W Reset 1 0 2 0 3 0 4 5 6 UCPREN 7 DMA 8 0 9 10 11 12 13 FCK 14 FEN 15 0
UCPRE[0:1]
IF[0:3]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 R W 0
17 0
18 0 FORCMA
19 0 FORCMB
20 0
21
22
23 EDSEL
24 EDPOL
25
26
27
28
29
30
31
BSL[0:1]
MODE[0:6]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-9. eMIOS UC Control (EMIOSC[n]) Register Table 20-9. EMIOSC[n] register field descriptions
Field 0 FREN Description Freeze Enable bit The FREN bit, if set and validated by FRZ bit in EMIOSMCR register allows the channel to enter freeze state, freezing all registers values when in debug mode and allowing the MCU to perform debug functions. 1 = Freeze UC registers values 0 = Normal operation Prescaler bits The UCPRE[0:1] bits select the clock divider value for the internal prescaler of Unified Channel, as shown in Table 20-10. Prescaler Enable bit The UCPREN bit enables the prescaler counter. 1 = Prescaler enabled 0 = Prescaler disabled (no clock) Direct Memory Access bit The DMA bit selects if the FLAG generation will be used as an interrupt request, as a DMA request or as a CTU trigger. The choice between a DMA request or a CTU trigger is determined by the value of bit TM in the register CTU_EVTCFGRx (refer to the CTU chapter of the reference manual). 1 = Flag/overrun assigned to DMA request or CTU trigger 0 = Flag/overrun assigned to interrupt request Input Filter bits The IF[0:3] bits control the programmable input filter, selecting the minimum input pulse width that can pass through the filter, as shown in Table 20-11. For output modes, these bits have no meaning. Filter Clock select bit The FCK bit selects the clock source for the programmable input filter. 1 = Main clock 0 = Prescaled clock
4:5 UCPRE[0:1] 6 UCPREN
7 DMA
9:12 IF[0:3] 13 FCK
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Table 20-9. EMIOSC[n] register field descriptions (continued)
Field 14 FEN Description FLAG Enable bit The FEN bit allows the Unified Channel FLAG bit to generate an interrupt signal or a DMA request signal or a CTU trigger signal (The type of signal to be generated is defined by the DMA bit). 1 = Enable (FLAG will generate an interrupt request or DMA request or a CTU trigger) 0 = Disable (FLAG does not generate an interrupt request or DMA request or a CTU trigger) Force Match A bit For output modes, the FORCMA bit is equivalent to a successful comparison on comparator A (except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is valid for every output operation mode which uses comparator A, otherwise it has no effect. 1 = Force a match at comparator A 0 = Has no effect Note: For input modes, the FORCMA bit is not used and writing to it has no effect. Force Match B bit For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B (except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is valid for every output operation mode which uses comparator B, otherwise it has no effect. 1 = Force a match at comparator B 0 = Has not effect Note: For input modes, the FORCMB bit is not used and writing to it has no effect. Bus Select bits The BSL[0:1] bits are used to select either one of the counter buses or the internal counter to be used by the Unified Channel. Refer to Table 20-12 for details. Edge Selection bit For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a pulse or just by a single edge as defined by the EDPOL bit. When not shown in the mode of operation description, this bit has no effect. 1 = Both edges triggering 0 = Single edge triggering defined by the EDPOL bit For GPIO in mode, the EDSEL bit selects if a FLAG can be generated. 1 = No FLAG is generated 0 = A FLAG is generated as defined by the EDPOL bit For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 1 = The output flip-flop is toggled 0 = The EDPOL value is transferred to the output flip-flop 24 EDPOL Edge Polarity bit For input modes, the EDPOL bit asserts which edge triggers either the internal counter or an input capture or a FLAG. When not shown in the mode of operation description, this bit has no effect. 1 = Trigger on a rising edge 0 = Trigger on a falling edge For output modes, the EDPOL bit is used to select the logic level on the output pin. 1 = A match on comparator A sets the output flip-flop, while a match on comparator B clears it 0 = A match on comparator A clears the output flip-flop, while a match on comparator B sets it 25:31 MODE[0:6] Mode selection bits The MODE[0:6] bits select the mode of operation of the Unified Channel, as shown in Table 20-13. Note: If a reserved value is written to mode the results are unpredictable.
18 FORCMA
19 FORCMB
21:22 BSL[0:1] 23 EDSEL
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Table 20-10. UC internalprescaler clock divider
UCPRE[0:1 ] 00 01 10 11 Divide ratio 1 2 3 4
Table 20-11. UC input filter bits
IF[0:3]1 0000 0001 0010 0100 1000 all others
1 2
Minimum input pulse width [FLT_CLK periods] Bypassed2 02 04 08 16 Reserved
Filter latency is 3 clock edges. The input signal is synchronized before arriving to the digital filter.
Table 20-12. UC BSL bits
BSL[0:1] 00 01 Selected bus All channels: counter bus[A] Channels 0 to 7: counter bus[B] Channels 8 to 15: counter bus[C] Channels 16 to 23: counter bus[D] Channels 24 to 27: counter bus[E] Reserved All channels: internal counter
10 11
Table 20-13. Channel mode selection
MODE[0:6]1 0000000 0000001 0000010 0000011 0000100 0000101 Mode of operation General purpose Input/Output mode (input) General purpose Input/Output mode (output) Single Action Input Capture Single Action Output Compare Input Pulse Width Measurement Input Period Measurement
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Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
Table 20-13. Channel mode selection (continued)
MODE[0:6]1 0000110 0000111 0001000 – 0001111 001000b 001001b 00101bb 0011000 – 0100101 0100110 0100111 – 1001111 101000b 101001b 10101bb 10110b0 10110b1 10111b0 10111b1 11000b0 1100001 – 1111111
1
Mode of operation Double Action Output Compare (with FLAG set on B match) Double Action Output Compare (with FLAG set on both match) Reserved Modulus Counter (Up counter with clear on match start) Modulus Counter (Up counter with clear on match end) Modulus Counter (Up/Down counter) Reserved Output Pulse Width Modulation with Trigger Reserved Modulus Counter Buffered (Up counter) Reserved Modulus Counter Buffered (Up/Down counter) Output Pulse Width and Frequency Modulation Buffered Reserved Center Aligned Output Pulse Width Modulation Buffered (with trail edge dead-time) Center Aligned Output Pulse Width Modulation Buffered (with lead edge dead-time) Output Pulse Width Modulation Buffered Reserved
b = adjust parameters for the mode of operation. Refer to Section 20.4.1.1, “UC modes of operation for details.
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Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
20.3.2.9
eMIOS UC Status (EMIOSS[n]) Register
Address: UC[n] base address + 0x10 0 R OVR W Reset OVRC 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 R OVFL
17 0
18 0
19 0
20 0
21 0
22 0
23 0
24 0
25 0
26 0
27 0
28 0
29 UCIN
30 UCOUT 0
31 FLAGC FLAG 0
W
Reset
OVFLC 0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-10. eMIOS UC Status (EMIOSS[n]) Register Table 20-14. EMIOSS[n] register field descriptions
Field 0 (Read) OVR Description Overrun bit The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set. 1 = Overrun has occurred 0 = Overrun has not occurred Overrun Clear bit The OVR bit can be cleared either by clearing the FLAG bit or by writing a 1 to the OVRC bit. 1 = Clear OVR bit 0 = Do not change OVR bit Overflow bit The OVFL bit indicates that an overflow has occurred in the internal counter. OVFL must be cleared by software writing a 1 to the OVFLC bit. 1 = An overflow had occurred 0 = No overflow Overflow Clear bit The OVFL bit must be cleared by writing a 1 to the OVFLC. 1 = Clear OVFL bit 0 = Do not change OVFL bit Unified Channel Input pin bit The UCIN bit reflects the input pin state after being filtered and synchronized. UCOUT — Unified Channel Output pin bit The UCOUT bit reflects the output pin state.
0 (Write) OVRC
16 (Read) OVFL
16 (Write) OVFLC
29 UCIN 30 UCOUT
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Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
Table 20-14. EMIOSS[n] register field descriptions
Field 31 (Read) FLAG Description FLAG bit The FLAG bit is set when an input capture or a match event in the comparators occurred. 1 = FLAG set event has occurred 0 = FLAG cleared Note: When DMA bit is set, the FLAG bit can be cleared by the DMA controller or the CTU. FLAG Clear bit The FLAG bit must be cleared by writing a 1 to FLAGC. 1 = Clear FLAG bit 0 = Do not change FLAG bit
31 (Write) FLAGC
20.3.2.10 eMIOS UC Alternate A Register (EMIOSALTA[n])
Address: UC[n] base address + 0x14 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0
16 R W Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ALTA[0:15]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-11. eMIOS UC Alternate A register (EMIOSALTA[n])
The EMIOSALTA[n] register provides an alternate address to access A2 channel registers in restricted modes (GPIO, OPWMT) only. If EMIOSA[n] register is used along with EMIOSALTA[n], both A1 and A2 registers can be accessed in these modes. Figure 20-8 summarizes the EMIOSALTA[n] writing and reading accesses for all operation modes. Please, see Section 20.4.1.1.1, “General purpose Input/Output (GPIO) mode, Section 20.4.1.1.12, “Output Pulse Width Modulation with Trigger (OPWMT) mode for a more detailed description of the use of EMIOSALTA[n] register.
20.4
Functional description
The four types of channels of the eMIOS (types X, Y, G and H) can operate in the modes as listed in Figure 20-1. The eMIOS provides independently operating unified channels (UC) that can be configured and accessed by a host MCU. Up to three time bases1 can be shared by the channels through five counter
1. Time bases can be supplied by: a) channel 23 to all unified channels b) channel 0 to channels 0 to 7, by channel 8 to channels 8 to 15, by channel 16 to channels 16 to 23, by channel 24 to channels 24 to 31 c) channel's internal counter when available. MPC5602D Microcontroller Reference Manual, Rev. 3.1 Freescale Semiconductor Preliminary 519
Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
buses1 and each unified channel can generate its own time base2. The eMIOS block is reset at positive edge of the clock (synchronous reset). All registers are cleared on reset.
20.4.1
Unified Channel (UC)
Figure 20-12 shows the Unified Channel block diagram. Each Unified Channel consists of: • Counter bus selector, which selects the time base to be used by the channel for all timing functions • A programmable clock prescaler • Two double buffered data registers A and B that allow up to two input capture and/or output compare events to occur before software intervention is needed. • Two comparators (equal only) A and B, which compares the selected counter bus with the value in the data registers • Internal counter, which can be used as a local time base or to count input events • Programmable input filter, which ensures that only valid pin transitions are received by channel • Programmable input edge detector, which detects the rising, falling or either edges • An output flip-flop, which holds the logic level to be applied to the output pin • eMIOS Status and Control register
RQB
ipd_done ipd_req uc_int_flag ips_wdata[0:31] biu_channel_en biu_a_en biu_b_en biu_cnt_en biu_control_en biu_status_en uc_rd_data[0:31] ips_byte_7_0 ips_byte_15_8 ips_byte_23_16 ips_byte_31_24 ips_rwb ips_addr[27:29]
Unified Channel
Clock Prescaler Programmable Filter
uc_ctrl
uc_datapath
Comparator A Comparator B Global Counter [A] Local Counter [B/C/D/E] Counter Bus
IIB
mode logic
Figure 20-12. Unified Channel block diagram
1. Internal eMIOS architecture have one global counter bus A and four local counter buses B, C, D, and E, that distribute the time bases described in Note 1 (a) and (b). 2. Channels of type X and G have the internal counter enabled, so their timebase can be selected by channel's BSL[1:0]=11: eMIOS_A - channels 0 to 8, 16, 23 and 24 eMIOS_B = channels 0, 8, 16, 23 and 24. MPC5602D Microcontroller Reference Manual, Rev. 3.1 520 Preliminary Freescale Semiconductor
Internal Counter
RWCB
Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
Figure 20-13 shows both the Unified Channel Control and Datapath block diagram. The Control block is responsible for the generation of signals to control the multiplexes in the Datapath sub-block. Each mode is implemented by a dedicated logic independent from others modes, thus allowing to optimize the logic by disabling the mode and therefore its associated logic. The unused gates are removed during the synthesis phase. Targeting the logic optimization a set of registers is shared by the modes thus providing sequential events to be stored. The Datapath block provides the channel A and B registers, the internal time base and comparators. Multiplexors select the input of comparators and data for the registers inputs, thus configuring the datapath in order to implement the channel modes. The outputs of A and B comparators are connected to the uc_ctrl control block.
input input filter MODE register
mode 0 logic
mode 1 logic
mode n logic control signals
MODE decoder
General Purpose Registers
uc_ctrl
global counter bus [A] BSL[1]+logic local counter bus [B/C/D/E] internal counter BSL[0] A Comparator
==
A2 CNT
BSL[1]+logic
A1
B1 B2
B Comparator
==
uc_datapath
BSL[1]+logic
Figure 20-13. Unified Channel Control and Datapath block diagrams
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Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
20.4.1.1
UC modes of operation
The mode of operation of the Unified Channel is determined by the mode select bits MODE[0:6] in the eMIOS UC Control (EMIOSC[n]) Register (see Figure 20-9 for details). As the internal counter EMIOSCNT[n] continues to run in all modes (except for GPIO mode), it is possible to use this as a time base if the resource is not used in the current mode. In order to provide smooth waveform generation even if A and B registers are changed on the fly, it is available the MCB, OPWFMB, OPWMB and OPWMCB modes. In these modes A and B registers are double buffered. 20.4.1.1.1 General purpose Input/Output (GPIO) mode
In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter (EMIOSCNT[n] register) is cleared and disabled. All control bits remain accessible. In order to prepare the UC for a new operation mode, writing to registers EMIOSA[n] or EMIOSB[n] stores the same value in registers A1/A2 or B1/B2, respectively. Writing to register EMIOSALTA[n] stores a value only in register A2. MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes. It is required that when changing MODE[0:6], the application software goes to GPIO mode first in order to reset the UC’s internal functions properly. Failure to do this could lead to invalid and unexpected output compare or input capture results or the FLAGs being set incorrectly. In GPIO input mode (MODE[0:6] = 0000000), the FLAG generation is determined according to EDPOL and EDSEL bits and the input pin status can be determined by reading the UCIN bit. In GPIO output mode (MODE[0:6] = 0000001), the Unified Channel is used as a single output port pin and the value of the EDPOL bit is permanently transferred to the output flip-flop. 20.4.1.1.2 Single Action Input Capture (SAIC) mode
In SAIC mode (MODE[0:6] = 0000010), when a triggering event occurs on the input pin, the value on the selected time base is captured into register A2. The FLAG bit is set along with the capture event to indicate that an input capture has occurred. Register EMIOSA[n] returns the value of register A2. As soon as the SAIC mode is entered coming out from GPIO mode the channel is ready to capture events. The events are captured as soon as they occur thus reading register A always returns the value of the latest captured event. Subsequent captures are enabled with no need of further reads from EMIOSA[n] register. The FLAG is set at any time a new event is captured. The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL and EDSEL bits in EMIOSC[n] register. Figure 20-14 and Figure 20-15 show how the Unified Channel can be used for input capture.
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Chapter 20 Configurable Enhanced Modular IO Subsystem (eMIOS)
EDSEL = 0 EDPOL = 1 input signal1 selected counter bus FLAG pin/register A2 (captured) value2 Notes: 1. After input filter 2. EMIOSA[n] THRH converted data < THRL THRL
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