MPC5603PEFMLQ

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5604P Rev. 5, 11/2009 MPC5604P 144 LQFP 20 mm x 20 mm MPC5604P Microcontroller Data Sheet • High performance 64 MHz e200z0h CPU – 32-bit Power Architecture Book E CPU – Variable Length Encoding (VLE) • Available memory – As much as 512 KB on-chip code flash memory with additional 64 KB for EEPROM emulation (data flash), with ECC, with erase/program controller – As much as 40 KB on-chip RAM with ECC • Fail safe protection – Programmable watchdog timer – Junction temperature sensor – Non-maskable interrupt – Fault collection unit • Nexus L2+ interface • Interrupts – 16 priority level controller • 16-channel eDMA controller • General purpose I/Os – Individually programmable as input, output or special function • Two general purpose eTimer units – Six timers each with up/down count capabilities – 16-bit resolution, cascadable counters – Quadrature decode with rotation direction flag – Double buffer input capture and output compare • Communications interfaces – Two LINFlex channels (LIN 2.1) – Four DSPI channels with automatic chip select generation – FlexCAN interface (2.0B Active) with 32 message objects – Safety port based on FlexCAN with 32 message objects and up to 7.5 Mbit/s capability; usable as second CAN when not used as safety port – FlexRay™ module (V2.1) with dual or single channel, 32 message objects and up to 10 Mbit/s 100 LQFP 14 mm_x_14 mm • Two 10-bit A/D converters – Two × 15 input channels, four channels shared among the two A/D converters – Conversion time < 1 µs including sampling time at full precision – Programmable Cross Triggering Unit (CTU) – Four analog watchdogs with interrupt capability • On-chip CAN/UART/FlexRay Bootstrap loader with Boot Assist Module (BAM) • FlexPWM unit – Eight complementary or independent outputs with ADC synchronization signals – Polarity control, reload unit – Integrated configurable dead time unit and inverter fault input pins – 16-bit resolution, up to 2 × fCPU – Lockable configuration – Clock generation – 4–40 MHz main oscillator – 16 MHz internal RC oscillator – Software controlled FMPLL capable of speeds as fast as 64 MHz • Voltage supply – 3.3 V or 5 V supply for I/Os and ADC – On-chip single supply voltage regulator with external ballast transistor – Operating temperature ranges: –40 to 125 °C or –40 to 105 °C This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008, 2009. All rights reserved. Preliminary—Subject to Change Without Notice Table of Contents 1 2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .6 2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2 Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.1 Power supply and reference voltage pins . . . . . .8 2.2.2 System Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.2.3 Pin Muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .23 3.2 Recommended operating conditions . . . . . . . . . . . . . .26 3.3 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.1 General notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . . .30 3.4 Electromagnetic interference (EMI) characteristics. . . .32 3.5 Electrostatic discharge (ESD) characteristics . . . . . . . .32 3.6 Power management electrical characteristics. . . . . . . .33 3.6.1 Voltage regulator electrical characteristics . . . .33 3.6.2 Voltage monitor electrical characteristics. . . . . .35 3.7 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . .36 3.8 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . .39 3.8.1 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . .39 3.8.2 DC electrical characteristics (5 V) . . . . . . . . . . .39 3.8.3 DC Electrical characteristics (3.3 V) . . . . . . . . .41 3.8.4 I/O pad current specification . . . . . . . . . . . . . . 44 Temperature sensor electrical characteristics . . . . . . . 48 Main oscillator electrical characteristics . . . . . . . . . . . 48 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 49 16 MHz RC oscillator electrical characteristics . . . . . . 50 Analog-to-digital converter (ADC) electrical characteristics 51 3.13.1 Input impedance and ADC accuracy . . . . . . . . 51 3.13.2 ADC conversion characteristics . . . . . . . . . . . . 56 3.14 Flash memory electrical characteristics . . . . . . . . . . . 57 3.15 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.15.1 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 58 3.16 AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . 59 3.16.1 RESET Pin Characteristics . . . . . . . . . . . . . . . 59 3.16.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 61 3.16.3 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.16.4 External interrupt timing (IRQ pin) . . . . . . . . . . 66 3.16.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 73 4.1.1 144 LQFP mechanical outline drawing. . . . . . . 73 4.1.2 100 LQFP Mechanical Outline Drawing . . . . . . 75 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.9 3.10 3.11 3.12 3.13 3 4 5 6 MPC5604P Microcontroller Data Sheet, Rev. 5 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor 1 Overview This document provides electrical specifications, pin assignments, and package diagrams for the MPC5604P series of microcontroller units (MCUs). For functional characteristics, refer to the MPC5604P Microcontroller Reference Manual. MPC5604P microcontrollers are members of a new family of next generation microcontrollers built on the Power Architecture™. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. The MPC5604P family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5604P automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original PowerPC user instruction set architecture (UISA). It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 1.1 Device comparison Table 1. MPC5604P device comparison Feature Code Flash memory (with ECC) Data Flash / EE (with ECC) RAM (with ECC) Processor core Instruction set CPU performance FMPLL (frequency-modulated phase-locked loop) modules INTC (interrupt controller) channels PIT (periodic interrupt timer) Enhanced DMA (direct memory access) channels FlexRay FlexCAN (controller area network) Safety port FCU (fault collection unit) CTU (cross triggering unit) eTimer channels FlexPWM (pulse-width modulation) channels Analog-to-digital converters (ADC) LINFlex modules DSPI (deserial serial peripheral interface) modules MPC5603P 384 KB 64 KB 36 KB 32-bit e200z0h VLE 0–64 MHz 2 147 1 (includes four 32-bit timers) 16 Yes1 22,3 Yes (via second FlexCAN module) Yes Yes 2×6 8 Two (10-bit, 16-channel) 2 4 MPC5604P 512 KB 64 KB 40 KB Table 1 provides a summary of different members of the MPC5604P family and their features to enable a comparison among the family members and an understanding of the range of functionality offered within this family. MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3 Table 1. MPC5604P device comparison (continued) Feature CRC (cyclic redundancy check) unit Junction temperature sensor JTAG interface Nexus port controller (NPC) Supply Digital power supply 4 MPC5603P Yes Yes Yes Yes (Level 2+) MPC5604P 3.3 V or 5 V single supply with external transistor 3.3 V or 5 V 16 MHz 4–40 MHz 100 LQFP 144 LQFP Analog power supply Internal RC oscillator External crystal oscillator Packages Temperature Standard ambient temperature Extended ambient temperature 1 2 5 –40 to 125 °C –40 to 145 °C 32 message buffers, dual-channel. Each FlexCAN module has 32 message buffers. 3 One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s. 4 3.3 V range and 5 V range correspond to different orderable parts. 5 Thermally enhanced 100-pin and 144-pin LQFP packages are under analysis to support an extended ambient temperature range of –40 to 145 °C. The packages are not yet available. MPC5604P Microcontroller Data Sheet, Rev. 5 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor 1.2 Block diagram Figure 1 shows a top-level block diagram of the MPC5604P MCU. 1.2 V Regulator Control XOSC 16 MHz RC Oscillator FMPLL_0 (System) FMPLL_1 (FlexRay, MotCtrl) JTAG Nexus Port Controller eDMA2 ¥ 16 channels Master Instruction (32-bit) Master Data (32-bit) Master FlexRay Master Integer Execution Unit e200z0 Core 32-bit General Purpose Registers Special Purpose Registers Instruction Unit Branch Prediction Unit Exception Handler Variable Length Encoded Instructions Load/Store Unit Interrupt Controller Crossbar Switch (XBAR, AMBA 2.0 v6 AHB) Slave Slave Slave Boot Assist Module System Integration Unit-Lite ECSM Peripheral Bridge Junc. Temp. Sensor STM Flash memory (with ECC) SRAM (with ECC) SWT PIT 4 ch. 11 4 11 CTUCross Triggering Unit DSPIDeserial Serial Peripheral Interface ECSMError Correction Status Module eTimerEnhanced Timer FlexCANFlexible Controller Area Network FlexPWMFlexible Pulse Width Modulation FMPLLFrequency-Modulated Phase-Locked Loop LINFlexSerial Communication Interface (LIN support) PITPeriodic Interrupt Timer SRAMStatic Random-Access Memory STMSystem Timer Module SWTSoftware Watchdog Timer Figure 1. MPC5604P block diagram MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 5 Fault Collection Unit 2¥ eTimer (6 ch) 1.2 V Rail Vreg Safety Port FlexPWM FlexCAN 2¥ LINFlex 4¥ DSPI 2¥ ADC CTU 2 2.1 Package pinouts and signal descriptions Package pinouts A[15]/safetyport0 RXD/etimer1 ETC[5]/IRQ14 A[14]/safetyport0 TXD/etimer1 ETC[4]/IRQ13 C[6]/dspi0 SOUT/flexpwm0 B[1]/sscm DEBUG[6]/IRQ24 G[1]/fcu0 F[1]/IRQ31 D[2]/flexray0 CB RX/etimer1 ETC[3]/flexpwm0 X[3] F[3]/flexray0 DBG3/dspi3 CS0 B[6]/CLKOUT/dspi2 CS2/IRQ18 F[2]/flexray0 DBG2/dspi3 CS1 A[13]/dspi2 SIN/flexpwm0 B[2]/flexpwm0 FAULT[0]/IRQ12 F[1]/flexray0 DBG1/dspi3 CS2/IRQ29 A[9]/dspi2 CS1/flexpwm0 FAULT[0]/flexpwm0 B[3] F[0]/flexray0 DBG0/dspi3 CS3/IRQ28 VSS_LV_COR2 VDD_LV_COR2 C[8]/dspi1 CS1/flexpwm0 FAULT[2]/dspi0 CS6 D[4]/flexray0 CB TR EN/etimer1 ETC[5]/flexpwm0 B[3] D[3]/flexray0 CB TX/etimer1 ETC[4]/flexpwm0 A[3] VSS_HV_IO3 VDD_HV_IO3 D[0]/flexray0 CA TX/etimer1 ETC[1]/flexpwm0 B[1] C[15]/flexray0 CA TR EN/etimer1 ETC[0]/flexpwm0 A[1]/ctu0 EXT IN/flexpwm0 ext. sync C[9]/dspi2 CS3/flexpwm0 FAULT[2]/flexpwm0 X[3] A[12]/dspi2 SOUT/flexpwm0 A[2]/flexpwm0 B[2]/IRQ11 E[15]/dspi3 SIN/IRQ27 A[11]/dspi2 SCK/flexpwm0 A[0]/flexpwm0 A[2]/IRQ10 E[14]/dspi3 SOUT/IRQ26 A[10]/dspi2 CS0/flexpwm0 B[0]/flexpwm0 X[2]/IRQ9 E[13]/dspi3 SCK/IRQ25 B[3]/lin0 RXD/sscm DEBUG[3] F[14]/lin1 TXD B[2]/lin0 TXD/sscm DEBUG[2]/IRQ17 F[15]/lin1 RXD F[13]/etimer1 ETC[4] C[10]/dspi2 CS2/flexpwm0 FAULT[1]/flexpwm0 A[3] B[1]/can0 RXD/etimer1 ETC[3]/sscm DEBUG[1]/IRQ16 B[0]/can0 TXD/etimer1 ETC[2]/sscm DEBUG[0]/IRQ15 NMI IRQ6/dspi1 SCK/A[6] flexray0 CA RX/etimer1 ETC[2]/ctu0 EXT TRG/D[1] nexus0 MDO[3]/F[4] nexus0 MDO[2]/F[5] VDD_HV_IO0 VSS_HV_IO0 nexus0 MDO[1]/F[6] nexus0 MDO 0 IRQ7/dspi1 SOUT/A[7] IRQ22/sscm DEBUG[4]/dspi0 CS0/flexpwm0 X[1]/C[4] IRQ8/dspi1 SIN/A[8] IRQ23/sscm DEBUG[5]/dspi0 SCK/flexpwm0 FAULT[3]/C[5] IRQ5/dspi1 CS0/etimer1 ETC[5]/dspi0 CS7/A[5] sscm DEBUG[7]/dspi0 SIN/flexpwm0 A[1]/C[7] IRQ21/dspi0 CS1/etimer1 ETC[4]/lin1 TXD/C[3] VSS_LV_COR0 VDD_LV_COR0 nexus0 MCKO/F[7] nexus0 MSEO1/F[8] VDD_HV_IO1 VSS_HV_IO1 nexus0 MSEO0/F[9] nexus0 EVTO/F[10] nexus0 EVTI/F[11] flexpwm0 X[0]/lin1 TXD/D[9] VDD_HV_OSC VSS_HV_OSC XTAL EXTAL RESET dspi1 CS2/flexpwm0 FAULT[3]/dspi0 CS5/D[8] dspi0 CS3/fcu0 F[0]/dspi3 SOUT/D[5] dspi0 CS2/dspi3 SCK/flexpwm0 FAULT[1]/D[6] VSS_LV_PLL VDD_LV_PLL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 The LQFP pinouts are shown in the following figures. 144 LQFP 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 A[4]/etimer1 ETC[0]/dspi2 CS1/etimer0 ETC[4]/FAB/IRQ4 VPP TEST F[12]/etimer1 ETC[3] D[14]/flexpwm0 B[1]/dspi3 CS3/dspi3 SIN G[3]/flexpwm0 A[2] C[14]/etimer1 ETC[2]/ctu0 EXT TGR G[2]/flexpwm0 X[2] C[13]/etimer1 ETC[1]/ctu0 EXT IN/flexpwm0 ext. sync G[4]/flexpwm0 B[2] D[12]/flexpwm0 X[1]/lin1 RXD G[6]/flexpwm0 A[3] VDD_HV_FL VSS_HV_FL D[13]/flexpwm0 A[1]/dspi3 CS2/dspi3 SOUT VSS_LV_COR1 VDD_LV_COR1 A[3]/etimer0 ETC[3]/dspi2 CS0/flexpwm0 B[3]/ABS1/IRQ3 VDD_HV_IO2 VSS_HV_IO2 jtag0 TDO jtag0 TCK jtag0 TMS jtag0 TDI G[5]/flexpwm0 X[3] A[2]/etimer0 ETC[2]/dspi2 SIN/flexpwm0 A[3]/ABS0/IQR2 G[7]/flexpwm0 B[3] C[12]/etimer0 ETC[5]/dspi2 CS3/dspi3 CS1 G[8]/flexpwm0 FAULT[0] C[11]/etimer0 ETC[4]/dspi2 CS2/dspi3 CS0 G[9]/flexpwm0 FAULT[1] D[11]/flexpwm0 B[0]/dspi3 CS1/dspi3 SCK G[10]/flexpwm0 FAULT[2] D[10]/flexpwm0 A[0]/dspi3 CS0 G[11]/flexpwm0 FAULT[3] A[1]/etimer0 ETC[1]/dspi2 SOUT/fcu0 F[1]/IRQ1 A[0]/etimer0 ETC[0]/dspi2 SCK/fcu0 F[0]/IRQ0 dspi1 CS3/fcu0 F[1]/dspi3 SIN/dspi0 CS4/D[7] IRQ30/fcu0 F[0]/G[0] adc0 AN[4]/E[1] adc0 AN[6]/E[3] adc0 AN[2]/C[1] adc0 AN[7]/E[4] adc0 AN[0]/lin0 RXD/B[7] adc0 AN[8]/E[5] adc0 AN[3]/C[2] adc0 AN[9]/E[6] adc0 AN[1]/etimer0 ETC[5]/B[8] adc0 AN[10]/E[7] adc0 AN[5]/E[2] VDD_HV_AD0 VSS_HV_AD0 adc0-adc1 AN[11]/B[9] adc0-adc1 AN[12]/B[10] adc0-adc1 AN[13]/B[11] adc0-adc1 AN[14]/B[12] VDD_HV_AD1 VSS_HV_AD1 adc1 AN[4]/D[15] adc1 AN[6]/E[8] adc1 AN[0]/lin1 RXD/B[13] adc1 AN[7]/E[9] IRQ20/adc1 AN[2]/B[15] adc1 AN[8]/E[10] IRQ19/adc1 AN[1]/etimer0 ETC[4]/B[14] adc1 AN[9]/E[11] adc1 AN[3]/C[0] adc1 AN[10]/E[12] adc1 AN[5]/E[0] BCTRL VDD_LV_REGCOR VSS_LV_REGCOR Figure 2. 144-pin LQFP pinout (top view)1 1. Availability of port pin alternate functions depends on product selection MPC5604P Microcontroller Data Sheet, Rev. 5 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor VDD_HV_REG 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A[15]/safetyport0 RXD/etimer1 ETC[5]/IRQ14 A[14]/safetyport0 TXD/etimer1 ETC[4]/IRQ13 C[6]/dspi0 SOUT/flexpwm0 B[1]/sscm DEBUG[6]/IRQ24 D[2]/flexray0 CB RX/etimer1 ETC[3]/flexpwm0 X[3] B[6]/CLKOUT/dspi2 CS2/IRQ18 A[13]/dspi2 SIN/flexpwm0 B[2]/flexpwm0 FAULT[0]/IRQ12 A[9]/dspi2 CS1/flexpwm0 FAULT[0]/flexpwm0 B[3] VSS_LV_COR2 VDD_LV_COR2 C[8]/dspi1 CS1/flexpwm0 FAULT[2]/dspi0 CS6 D[4]/flexray0 CB TR EN/etimer1 ETC[5]/flexpwm0 B[3] D[3]/flexray0 CB TX/etimer1 ETC[4]/flexpwm0 A[3] VSS_HV_IO3 VDD_HV_IO3 D[0]/flexray0 CA TX/etimer1 ETC[1]/flexpwm0 B[1] C[15]/flexray0 CA TR EN/etimer1 ETC[0]/flexpwm0 A[1]/ctu0 EXT IN/flexpwm0 ext. sync C[9]/dspi2 CS3/flexpwm0 FAULT[2]/flexpwm0 X[3] A[12]/dspi2 SOUT/flexpwm0 A[2]/flexpwm0 B[2]/IRQ11 A[11]/dspi2 SCK/flexpwm0 A[0]/flexpwm0 A[2]/IRQ10 A[10]/dspi2 CS0/flexpwm0 B[0]/flexpwm0 X[2]/IRQ9 B[3]/lin0 RXD/sscm DEBUG[3] B[2]/lin0 TXD/sscm DEBUG[2]/IRQ17 C[10]/dspi2 CS2/flexpwm0 FAULT[1]/flexpwm0 A[3] B[1]/can0 RXD/etimer1 ETC[3]/sscm DEBUG[1]/IRQ16 B[0]/can0 TXD/etimer1 ETC[2]/sscm DEBUG[0]/IRQ15 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NMI IRQ6/dspi1 SCK/A[6] flexray0 CA RX/etimer1 ETC[2]/ctu0 EXT TRG/D[1] IRQ7/dspi1 SOUT/A[7] IRQ22/sscm DEBUG[4]/dspi0 CS0/flexpwm0 X[1]/C[4] IRQ8/dspi1 SIN/A[8] IRQ23/sscm DEBUG[5]/dspi0 SCK/flexpwm0 FAULT[3]/C[5] IRQ5/dspi1 CS0/etimer1 ETC[5]/dspi0 CS7/A[5] sscm DEBUG[7]/dspi0 SIN/flexpwm0 A[1]/C[7] IRQ21/dspi0 CS1/etimer1 ETC[4]/lin1 TXD/C[3] VSS_LV_COR0 VDD_LV_COR0 VDD_HV_IO1 VSS_HV_IO1 flexpwm0 X[0]/lin1 TXD/D[9] VDD_HV_OSC VSS_HV_OSC XTAL EXTAL RESET dspi1 CS2/flexpwm0 FAULT[3]/dspi0 CS5/D[8] dspi0 CS3/fcu0 F[0]/dspi3 SOUT/D[5] dspi0 CS2/dspi3 SCK/flexpwm0 FAULT[1]/D[6] VSS_LV_PLL VDD_LV_PLL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 LQFP A[4]/etimer1 ETC[0]/dspi2 CS1/etimer0 ETC[4]/FAB/IRQ4 VPP TEST D[14]/flexpwm0 B[1]/dspi3 CS3/dspi3 SIN C[14]/etimer1 ETC[2]/ctu0 EXT TGR C[13]/etimer1 ETC[1]/ctu0 EXT IN/flexpwm0 ext. sync D[12]/flexpwm0 X[1]/lin1 RXD VDD_HV_FL VSS_HV_FL D[13]/flexpwm0 A[1]/dspi3 CS2/dspi3 SOUT VSS_LV_COR1 VDD_LV_COR1 A[3]/etimer0 ETC[3]/dspi2 CS0/flexpwm0 B[3]/ABS[1]/IRQ3 VDD_HV_IO2 VSS_HV_IO2 jtag0 TDO jtag0 TCK jtag0 TMS jtag0 TDI A[2]/etimer0 ETC[2]/dspi2 SIN/flexpwm0 A[3]/ABS[0]/IRQ2 C[12]/etimer0 ETC[5]/dspi2 CS3/dspi3 CS1 C[11]/etimer0 ETC[4]/dspi2 CS2/dspi3 CS0 D[11]/flexpwm0 B[0]/dspi3 CS1/dspi3 SCK D[10]/flexpwm0 A[0]/dspi3 CS0 A[1]/etimer0 ETC[1]/dspi2 SOUT/fcu0 F[1]/sscm /IRQ1 A[0]/etimer0 ETC[0]/dspi2 SCK/fcu0 F[0]/IRQ0 Figure 3. 100-pin LQFP pinout (top view)1 1. Availability of port pin alternate functions depends on product selection MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7 dspi1 CS3/fcu0 F[1]/dspi3 SIN/dspi0 CS4/D[7] adc0 AN[4]/E[1] adc0 AN[2]/C[1] adc0 AN[0]/lin0 RXD/B[7] adc0 AN[3]/C[2] adc0 AN[1]/etimer0 ETC[5]/B[8] adc0 AN[5]/E[2] VDD_HV_AD0 VSS_HV_AD0 adc0-adc1 AN[11]/B[9] adc0-adc1 AN[12]/B[10] adc0-adc1 AN[13]/B[11] adc0-adc1 AN[14]/B[12] VDD_HV_AD1 VSS_HV_AD1 adc1 AN[4]/D[15] adc1 AN[0]/lin1 RXD/B[13] IRQ20/adc1 AN[2]/B[15] adc1 AN[1]/etimer0 ETC[4]/B[14] adc1 AN[3]/C[0] adc1 AN[5]/E[0] BCTRL VDD_LV_REGCOR VSS_LV_REGCOR VDD_HV_REG 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2.2 Pin descriptions The following sections provide signal descriptions and related information about the functionality and configuration of the MPC5604P devices. 2.2.1 Power supply and reference voltage pins Table 2. Supply pins Supply Symbol Description 100-pin Pin 144-pin Table 2 lists the power supply and reference voltage for the MPC5604P devices. VREG control and power supply pins. Pins available on 100-pin and 144-pin package. BCTRL Voltage regulator external NPN Ballast base control pin 47 50 48 69 72 70 VDD_HV_REG (3.3 V Voltage regulator supply voltage or 5.0 V) VDD_LV_REGCOR 1.2 V decoupling1 pins for core logic supply and voltage regulator feedback. Decoupling capacitor must be connected between this pins and VSS_LV_REGCOR. 1.2 V decoupling1 pins for core logic GND and voltage regulator feedback. Decoupling capacitor must be connected between this pins and VDD_LV_REGCOR. VSS_LV_REGCOR 49 71 ADC0/ADC1 reference and supply voltage. Pins available on 100-pin and 144-pin package. VDD_HV_AD02 VSS_HV_AD0 VDD_HV_AD1 VSS_HV_AD1 ADC0 supply and high reference voltage ADC0 ground and low reference voltage ADC1 supply and high reference voltage ADC1 ground and low reference voltage 33 34 39 40 50 51 56 57 Power supply pins (3.3 V or 5.0 V). All pins available on 144-pin package. Five pairs (VDD; VSS) available on 100-pin package. VDD_HV_IO03 VSS_HV_IO0 3 Input/Output supply voltage Input/Output ground Input/Output supply voltage Input/Output ground Input/Output supply voltage Input/Output ground Input/Output supply voltage Input/Output ground Code and data flash supply voltage Code and data flash supply ground Crystal oscillator amplifier supply voltage Crystal oscillator amplifier ground — — 13 14 63 62 87 88 69 68 16 17 6 7 21 22 91 90 126 127 97 96 27 28 VDD_HV_IO1 VSS_HV_IO1 VDD_HV_IO2 VSS_HV_IO2 VDD_HV_IO3 VSS_HV_IO3 VDD_HV_FL VSS_HV_FL VDD_HV_OSC VSS_HV_OSC MPC5604P Microcontroller Data Sheet, Rev. 5 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 2. Supply pins (continued) Supply Symbol Description 100-pin Pin 144-pin Power supply pins (1.2 V). All pins available on 100-pin and 144-pin package. VDD_LV_COR0 1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR0 pin. 1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR0 pin. 1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR1 pin. 1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR1 pin. 1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR2 pin. 1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR 2pin. 1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest VSS_LV_COR3 pin. 1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest VDD_LV_COR 3 pin. 12 18 VSS_LV_COR0 11 17 VDD_LV_COR1 65 93 VSS_LV_COR1 66 94 VDD_LV_COR2 92 131 VSS_LV_COR2 93 132 VDD_LV_COR3 25 36 VSS_LV_COR3 24 35 1 2 See Section 3.6.1, “Voltage regulator electrical characteristics for more details Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a double-bonding connection on VDD_HV_ADx/VSS_HV_ADx pins. 3 Not available on 100-pin package 2.2.2 System Pins Table 3 and Table 4 contain information on pin functions for the MPC5604P devices. The pins listed in Table 3 are single-function pins. The pins shown in Table 4 are multi-function pins, programmable via their respective Pad Configuration Register (PCR) values. MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9 Table 3. System Pins Pad Speed1 Symbol Description Direction SRC=0 SRC=1 100-pin 144-pin Pin Dedicated pins. All pins available on 144-pin package. MDO 0 not available on 100-pin package. MDO 0 NMI XTAL Nexus Message Data Output—line 0 Non Maskable Interrupt Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator is used in bypass mode. Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. Analog input for the clock generator when the oscillator is in bypass mode. JTAG state machine control JTAG clock JTAG data input 2 Output Only Input Only — — — Fast — — — 1 18 9 1 29 EXTAL — — — 19 30 TMS2 TCK2 TDI 2 Input Only Input Only Input Only Output Only — — — Slow — — — Fast 59 60 58 61 87 88 86 89 TDO JTAG data output Reset pin, available on 100-pin and 144-pin package. RESET Bidirectional reset with Schmitt trigger characteristics and noise filter Bidirectional Medium — 20 31 Test pin, available on 100-pin and 144-pin package. VPP TEST 1 2 Pin for testing purpose only. To be tied to ground in normal operating mode. — — — 74 107 SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register In this pin there is an internal pull, refer to JTAGC chapter on MPC5604P Reference Manual for pull direction. 2.2.3 Pin Muxing Table 4 defines the pin list and muxing for the MPC5604P devices. Each row of Table 4 shows all the possible ways of configuring each pin, via “alternate functions”. The default function assigned to each pin after reset is the ALT0 function. Pins marked as external interrupt capable can also be used to resume from STOP and HALT mode. MPC5604P devices provide four main I/O pad types depending of the associated functions: • • • • Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission. Medium pads provide fast enough transition for serial communication channels with controlled current to reduce electromagnetic emission. Fast pads provide maximum speed. They are used for improved NEXUS debugging capability. Symmetric pads are designed to meet FlexRay requirements. Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. MPC5604P Microcontroller Data Sheet, Rev. 5 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 4. Pin muxing Port pin PCR register Alternate function1,2 Functions Peripheral3 I/O direction4 Pad speed5 SRC = 0 SRC = 1 Pin 100-pin 144-pin Port A (16-bit). Fully available on 100-pin and 144-pin package. A[0] PCR[0] ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — — ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — GPIO[0] ETC[0] SCK F[0] EIRQ[0] GPIO[1] ETC[1] SOUT F[1] EIRQ[1] GPIO[2] ETC[2] — A[3] SIN ABS[0] EIRQ[2] GPIO[3] ETC[3] CS0 B[3] ABS[1] EIRQ[3] GPIO[4] ETC[0] CS1 ETC[4] FAB EIRQ[4] GPIO[5] CS0 ETC[5] CS7 EIRQ[5] GPIO[6] SCK — — EIRQ[6] GPIO[7] SOUT — — EIRQ[7] SIU Lite eTimer0 DSPI2 FCU0 SIU Lite SIU Lite eTimer0 DSPI2 FCU0 SIU Lite SIU Lite eTimer0 — FlexPWM0 DSPI2 mc_rgm SIU Lite SIU Lite eTimer0 DSPI2 FlexPWM0 mc_rgm SIU Lite SIU Lite eTimer1 DSPI2 eTimer0 mc_rgm SIU Lite SIU Lite DSPI1 eTimer1 DSPI0 SIU Lite SIU Lite DSPI1 — — SIU Lite SIU Lite DSPI1 — — SIU Lite I/O I/O I/O O I I/O I/O O O I I/O I/O — O I I I I/O I/O I/O O I I I/O I/O O I/O I I I/O I/O I/O O I I/O I/O — — I I/O O — — I Slow Medium 51 73 A[1] PCR[1] Slow Medium 52 74 A[2]6 PCR[2] Slow Medium 57 84 A[3]6 PCR[3] Slow Medium 64 92 A[4]6 PCR[4] Slow Medium 75 108 A[5] PCR[5] Slow Medium 8 14 A[6] PCR[6] Slow Medium 2 2 A[7] PCR[7] Slow Medium 4 10 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 Table 4. Pin muxing (continued) Port pin A[8] PCR register PCR[8] Alternate function1,2 ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — Functions GPIO[8] — — — SIN EIRQ[8] GPIO[9] CS1 — B[3] FAULT[0] GPIO[10] CS0 B[0] X[2] EIRQ[9] GPIO[11] SCK A[0] A[2] EIRQ[10] GPIO[12] SOUT A[2] B[2] EIRQ[11] GPIO[13] — B[2] — SIN FAULT[0] EIRQ[12] GPIO[14] TXD ETC[4] — EIRQ[13] GPIO[15] — ETC[5] — RXD EIRQ[14] Peripheral SIU Lite — — — DSPI1 SIU Lite SIU Lite DSPI2 — FlexPWM0 FlexPWM0 SIU Lite DSPI2 FlexPWM0 FlexPWM0 SIU Lite SIU Lite DSPI2 FlexPWM0 FlexPWM0 SIU Lite SIU Lite DSPI2 FlexPWM0 FlexPWM0 SIU Lite SIU Lite — FlexPWM0 — DSPI2 FlexPWM0 SIU Lite SIU Lite Safety Port0 eTimer1 — SIU Lite SIU Lite — eTimer1 — Safety Port0 SIU Lite 3 I/O direction4 I/O — — — I I I/O O — O I I/O I/O O I/O I I/O I/O O O I I/O O O O I I/O — O — I I I I/O O I/O — I I/O — I/O — I I Pad speed5 SRC = 0 Slow SRC = 1 Medium Pin 100-pin 144-pin 6 12 A[9] PCR[9] Slow Medium 94 134 A[10] PCR[10] Slow Medium 81 118 A[11] PCR[11] Slow Medium 82 120 A[12] PCR[12] Slow Medium 83 122 A[13] PCR[13] Slow Medium 95 136 A[14] PCR[14] Slow Medium 99 143 A[15] PCR[15] Slow Medium 100 144 MPC5604P Microcontroller Data Sheet, Rev. 5 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 4. Pin muxing (continued) Port pin PCR register Alternate function1,2 Functions Peripheral 3 I/O direction4 Pad speed5 SRC = 0 SRC = 1 Pin 100-pin 144-pin Port B (16-bit). Fully available on 100-pin and 144-pin package. B[0] PCR[16] ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — GPIO[16] TXD ETC[2] DEBUG[0] EIRQ[15] GPIO[17] — ETC[3] DEBUG[1] RXD EIRQ[16] GPIO[18] TXD — DEBUG[2] EIRQ[17] GPIO[19] — — DEBUG[3] RXD GPIO[22] CLKOUT CS2 — EIRQ[18] GPIO[23] — — — AN[0] RXD GPIO[24] — — — AN[1] ETC[5] GPIO[25] — — — AN[11] SIU Lite CAN0 eTimer1 SSCM SIU Lite SIU Lite — eTimer1 SSCM CAN0 SIU Lite SIU Lite LIN0 — SSCM SIU Lite SIU Lite — — SSCM LIN0 SIU Lite Control DSPI2 — SIU Lite SIU Lite — — — ADC0 LIN0 SIU Lite — — — ADC0 eTimer0 I/O O I/O — I I/O — I/O — I I I/O O — — I I/O — — — I I/O O O — I Input Only Slow Medium 76 109 B[1] PCR[17] Slow Medium 77 110 B[2] PCR[18] Slow Medium 79 114 B[3] PCR[19] Slow Medium 80 116 B[6] PCR[22] Slow Medium 96 138 B[7] PCR[23] — — 29 43 B[8] PCR[24] Input Only — — 31 47 B[9] PCR[25] SIU Lite Input Only — — — ADC0 – ADC1 — — 35 52 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 Table 4. Pin muxing (continued) Port pin B[10] PCR register PCR[26] Alternate function1,2 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — — — ALT0 ALT1 ALT2 ALT3 — — Functions GPIO[26] — — — AN[12] GPIO[27] — — — AN[13] GPIO[28] — — — AN[14] GPIO[29] — — — AN[0] RXD GPIO[30] — — — AN[1] ETC[4] EIRQ[19] GPIO[31] — — — AN[2] EIRQ[20] Peripheral 3 I/O direction4 Pad speed5 SRC = 0 — SRC = 1 — Pin 100-pin 144-pin 36 53 SIU Lite Input Only — — — ADC0 – ADC1 SIU Lite Input Only — — — ADC0 – ADC1 SIU Lite Input Only — — — ADC0 – ADC1 SIU Lite — — — ADC1 LIN1 SIU Lite — — — ADC1 eTimer0 SIU Lite SIU Lite — — — ADC1 SIU Lite Input Only B[11] PCR[27] — — 37 54 B[12] PCR[28] — — 38 55 B[13] PCR[29] — — 42 60 B[14] PCR[30] Input Only — — 44 64 B[15] PCR[31] Input Only — — 43 62 Port C (16-bit). Fully available on 100-pin and 144-pin package. C[0] PCR[32] ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — GPIO[32] — — — AN[3] GPIO[33] — — — AN[2] SIU Lite — — — ADC1 SIU Lite — — — ADC0 Input Only — — 45 66 C[1] PCR[33] Input Only — — 28 41 MPC5604P Microcontroller Data Sheet, Rev. 5 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 4. Pin muxing (continued) Port pin C[2] PCR register PCR[34] Alternate function1,2 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — Functions GPIO[34] — — — AN[3] GPIO[35] CS1 ETC[4] TXD EIRQ[21] GPIO[36] CS0 X[1] DEBUG[4] EIRQ[22] GPIO[37] SCK — DEBUG[5] FAULT[3] EIRQ[23] GPIO[38] SOUT B[1] DEBUG[6] EIRQ[24] GPIO[39] — A[1] DEBUG[7] SIN GPIO[40] CS1 — CS6 FAULT[2] GPIO[41] CS3 — X[3] FAULT[2] GPIO[42] CS2 — A[3] FAULT[1] Peripheral SIU Lite — — — ADC0 SIU Lite DSPI0 eTimer1 LIN1 SIU Lite SIU Lite DSPI0 FlexPWM0 SSCM SIU Lite SIU Lite DSPI0 — SSCM FlexPWM0 SIU Lite SIU Lite DSPI0 FlexPWM0 SSCM SIU Lite SIU Lite — FlexPWM0 SSCM DSPI0 SIU Lite DSPI1 — DSPI0 FlexPWM0 SIU Lite DSPI2 — FlexPWM0 FlexPWM0 SIU Lite DSPI2 — FlexPWM0 FlexPWM0 3 I/O direction4 Input Only Pad speed5 SRC = 0 — SRC = 1 — Pin 100-pin 144-pin 30 45 C[3] PCR[35] I/O O I/O O I I/O I/O I/O — I I/O I/O — — I I I/O O O — I I/O — O — I I/O O — O I I/O O — I/O I I/O O — O I Slow Medium 10 16 C[4] PCR[36] Slow Medium 5 11 C[5] PCR[37] Slow Medium 7 13 C[6] PCR[38] Slow Medium 98 142 C[7] PCR[39] Slow Medium 9 15 C[8] PCR[40] Slow Medium 91 130 C[9] PCR[41] Slow Medium 84 123 C[10] PCR[42] Slow Medium 78 111 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15 Table 4. Pin muxing (continued) Port pin PCR register Alternate function1,2 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — — Functions GPIO[43] ETC[4] CS2 CS0 GPIO[44] ETC[5] CS3 CS1 GPIO[45] ETC[1] — — EXT IN EXT. SYNC GPIO[46] ETC[2] EXT TGR — GPIO[47] CA TR EN ETC[0] A[1] EXT IN EXT. SYNC Peripheral SIU Lite eTimer0 DSPI2 DSPI3 SIU Lite eTimer0 DSPI2 DSPI3 SIU Lite eTimer1 — — ctu0 FlexPWM0 SIU Lite eTimer1 ctu0 — SIU Lite FlexRay0 eTimer1 FlexPWM0 ctu0 FlexPWM0 3 I/O direction4 I/O I/O O I/O I/O I/O O O I/O I/O — — I I I/O I/O O — I/O O I/O O I I Pad speed5 SRC = 0 Slow SRC = 1 Medium Pin 100-pin 144-pin 55 80 C[11] PCR[43] C[12] PCR[44] Slow Medium 56 82 C[13] PCR[45] Slow Medium 71 101 C[14] PCR[46] Slow Medium 72 103 C[15] PCR[47] Slow Symmetric 85 124 Port D (16-bit). Fully available on 100-pin and 144-pin package. D[0] PCR[48] ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 GPIO[48] CA TX ETC[1] B[1] GPIO[49] — ETC[2] EXT TRG CA RX GPIO[50] — ETC[3] X[3] CB RX GPIO[51] CB TX ETC[4] A[3] GPIO[52] CB TR EN ETC[5] B[3] SIU Lite FlexRay0 eTimer1 FlexPWM0 SIU Lite — eTimer1 ctu0 FlexRay0 SIU Lite — eTimer1 FlexPWM0 FlexRay0 SIU Lite FlexRay0 eTimer1 FlexPWM0 SIU Lite FlexRay0 eTimer1 FlexPWM0 I/O O I/O O I/O — I/O O I I/O — I/O I/O I I/O O I/O I/O I/O O I/O O Slow Symmetric 86 125 D[1] PCR[49] Slow Medium 3 3 D[2] PCR[50] Slow Medium 97 140 D[3] PCR[51] Slow Symmetric 89 128 D[4] PCR[52] Slow Symmetric 90 129 MPC5604P Microcontroller Data Sheet, Rev. 5 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 4. Pin muxing (continued) Port pin D[5] PCR register PCR[53] Alternate function1,2 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — Functions GPIO[53] CS3 F[0] SOUT GPIO[54] CS2 SCK — FAULT[1] GPIO[55] CS3 F[1] CS4 SIN GPIO[56] CS2 — CS5 FAULT[3] GPIO[57] X[0] TXD — GPIO[58] A[0] CS0 — GPIO[59] B[0] CS1 SCK GPIO[60] X[1] — — RXD GPIO[61] A[1] CS2 SOUT GPIO[62] B[1] CS3 — SIN Peripheral SIU Lite DSPI0 FCU0 DSPI3 SIU Lite DSPI0 DSPI3 — FlexPWM0 SIU Lite DSPI1 FCU0 DSPI0 DSPI3 SIU Lite DSPI1 — DSPI0 FlexPWM0 SIU Lite FlexPWM0 LIN1 — SIU Lite FlexPWM0 DSPI3 — SIU Lite FlexPWM0 DSPI3 DSPI3 SIU Lite FlexPWM0 — — LIN1 SIU Lite FlexPWM0 DSPI3 DSPI3 SIU Lite FlexPWM0 DSPI3 — DSPI3 3 I/O direction4 I/O O O O I/O O I/O — I I/O O O O I I/O O — O I I/O I/O O — I/O O I/O — I/O O O I/O I/O I/O — — I I/O O O O I/O O O — I Pad speed5 SRC = 0 Slow SRC = 1 Medium Pin 100-pin 144-pin 22 33 D[6] PCR[54] Slow Medium 23 34 D[7] PCR[55] Slow Medium 26 37 D[8] PCR[56] Slow Medium 21 32 D[9] PCR[57] Slow Medium 15 26 D[10] PCR[58] Slow Medium 53 76 D[11] PCR[59] Slow Medium 54 78 D[12] PCR[60] Slow Medium 70 99 D[13] PCR[61] Slow Medium 67 95 D[14] PCR[62] Slow Medium 73 105 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17 Table 4. Pin muxing (continued) Port pin PCR register Alternate function1,2 ALT0 ALT1 ALT2 ALT3 — Functions GPIO[63] — — — AN[4] Peripheral SIU Lite — — — ADC1 3 I/O direction4 Input Only Pad speed5 SRC = 0 — SRC = 1 — Pin 100-pin 144-pin 41 58 D[15] PCR[63] Port E(16-bit). Fully available on 144-pin package. E[0], E[1] and E[2] available on 100-pin package. E[0] PCR[64] ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — GPIO[64] — — — AN[5] GPIO[65] — — — AN[4] GPIO[66] — — — AN[5] GPIO[67] — — — AN[6] GPIO[68] — — — AN[7] GPIO[69] — — — AN[8] GPIO[70] — — — AN[9] GPIO[71] — — — AN[10] SIU Lite — — — ADC1 SIU Lite — — — ADC0 SIU Lite — — — ADC0 SIU Lite — — — ADC0 SIU Lite — — — ADC0 SIU Lite — — — ADC0 SIU Lite — — — ADC0 SIU Lite — — — ADC0 Input Only — — 46 68 E[1] PCR[65] Input Only — — 27 39 E[2] PCR[66] Input Only — — 32 49 E[3] PCR[67] Input Only — — — 40 E[4] PCR[68] Input Only — — — 42 E[5] PCR[69] Input Only — — — 44 E[6] PCR[70] Input Only — — — 46 E[7] PCR[71] Input Only — — — 48 MPC5604P Microcontroller Data Sheet, Rev. 5 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 4. Pin muxing (continued) Port pin E[8] PCR register PCR[72] Alternate function1,2 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — — Functions GPIO[72] — — — AN[6] GPIO[73] — — — AN[7] GPIO[74] — — — AN[8] GPIO[75] — — — AN[9] GPIO[76] — — — AN[10] GPIO[77] SCK — — EIRQ[25] GPIO[78] SOUT — — EIRQ[26] GPIO[79] — — — SIN EIRQ[27] Peripheral SIU Lite — — — ADC1 SIU Lite — — — ADC1 SIU Lite — — — ADC1 SIU Lite — — — ADC1 SIU Lite — — — ADC1 SIU Lite DSPI3 — — SIU Lite SIU Lite DSPI3 — — SIU Lite SIU Lite — — — DSPI3 SIU Lite 3 I/O direction4 Input Only Pad speed5 SRC = 0 — SRC = 1 — Pin 100-pin 144-pin — 59 E[9] PCR[73] Input Only — — — 61 E[10] PCR[74] Input Only — — — 63 E[11] PCR[75] Input Only — — — 65 E[12] PCR[76] Input Only — — — 67 E[13] PCR[77] I/O I/O — — I I/O O — — I I/O — — — I I Slow Medium — 117 E[14] PCR[78] Slow Medium — 119 E[15] PCR[79] Slow Medium — 121 Port F (16-bit). Fully available on 144-pin package F[0] PCR[80] ALT0 ALT1 ALT2 ALT3 — GPIO[80] DBG0 CS3 — EIRQ[28] SIU Lite FlexRay0 DSPI3 — SIU Lite I/O O O — I Slow Medium — 133 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 Table 4. Pin muxing (continued) Port pin F[1] PCR register PCR[81] Alternate function1,2 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — Functions GPIO[81] DBG1 CS2 — EIRQ[29] GPIO[82] DBG2 CS1 — GPIO[83] DBG3 CS0 — GPIO[84] MDO[3] — — GPIO[85] MDO[2] — — GPIO[86] MDO[1] — — GPIO[87] MCKO — — GPIO[88] MSEO1 — — GPIO[89] MSEO0 — — GPIO[90] EVTO — — GPIO[91] — — — EVTI Peripheral SIU Lite FlexRay0 DSPI3 — SIU Lite SIU Lite FlexRay0 DSPI3 — SIU Lite FlexRay0 DSPI3 — SIU Lite nexus0 — — SIU Lite nexus0 — — SIU Lite nexus0 — — SIU Lite nexus0 — — SIU Lite nexus0 — — SIU Lite nexus0 — — SIU Lite nexus0 — — SIU Lite — — — nexus0 3 I/O direction4 I/O O O — I I/O O O — I/O O I/O — I/O O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O — — — I Pad speed5 SRC = 0 Slow SRC = 1 Medium Pin 100-pin 144-pin — 135 F[2] PCR[82] Slow Medium — 137 F[3] PCR[83] Slow Medium — 139 F[4] PCR[84] Slow Fast — 4 F[5] PCR[85] Slow Fast — 5 F[6] PCR[86] Slow Fast — 8 F[7] PCR[87] Slow Fast — 19 F[8] PCR[88] Slow Fast — 20 F[9] PCR[89] Slow Fast — 23 F[10] PCR[90] Slow Fast — 24 F[11] PCR[91] Slow Medium — 25 MPC5604P Microcontroller Data Sheet, Rev. 5 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 4. Pin muxing (continued) Port pin F[12] PCR register PCR[92] Alternate function1,2 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — Functions GPIO[92] ETC[3] — — GPIO[93] — — — ETC[4] GPIO[94] TXD — — GPIO[95] — — — RXD Peripheral SIU Lite eTimer1 — — SIU Lite — — — eTimer1 SIU Lite LIN1 — — SIU Lite — — — LIN1 3 I/O direction4 I/O I/O — — I/O — — — I I/O O — — I/O — — — I Pad speed5 SRC = 0 Slow SRC = 1 Medium Pin 100-pin 144-pin — 106 F[13] PCR[93] Slow Medium — 112 F[14] PCR[94] Slow Medium — 115 F[15] PCR[95] Slow Medium — 113 Port G (12-bit). Fully available on 144-pin package. G[0] PCR[96] ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 GPIO[96] F[0] — — EIRQ[30] GPIO[97] F[1] — — EIRQ[31] GPIO[98] X[2] — — GPIO[99] A[2] — — GPIO[100] B[2] — — GPIO[101] X[3] — — SIU Lite FCU0 — — SIU Lite SIU Lite FCU0 — — SIU Lite SIU Lite FlexPWM0 — — SIU Lite FlexPWM0 — — SIU Lite FlexPWM0 — — SIU Lite FlexPWM0 — — I/O O — — I I/O O — — I I/O I/O — — I/O O — — I/O O — — I/O I/O — — Slow Medium — 38 G[1] PCR[97] Slow Medium — 141 G[2] PCR[98] Slow Medium — 102 G[3] PCR[99] Slow Medium — 104 G[4] PCR[100] Slow Medium — 100 G[5] PCR[101] Slow Medium — 85 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 21 Table 4. Pin muxing (continued) Port pin PCR register Alternate function1,2 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — ALT0 ALT1 ALT2 ALT3 — Functions GPIO[102] A[3] — — GPIO[103] B[3] — — GPIO[104] — — — FAULT[0] GPIO[105] — — — FAULT[1] GPIO[106] — — — FAULT[2] GPIO[107] — — — FAULT[3] Peripheral 3 I/O direction4 I/O O — — I/O O — — I/O — — — I I/O — — — I I/O — — — I I/O — — — I Pad speed5 SRC = 0 Slow SRC = 1 Medium Pin 100-pin 144-pin — 98 G[6] PCR[102] SIU Lite FlexPWM0 — — SIU Lite FlexPWM0 — — SIU Lite — — — FlexPWM0 SIU Lite — — — FlexPWM0 SIU Lite — — — FlexPWM0 SIU Lite — — — FlexPWM0 G[7] PCR[103] Slow Medium — 83 G[8] PCR[104] Slow Medium — 81 G[9] PCR[105] Slow Medium — 79 G[10] PCR[106] Slow Medium — 77 G[11] PCR[107] Slow Medium — 75 1 2 3 4 5 6 ALT0 is the primary (default) function for each port after reset. Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module. PCR[PA] = 00 → ALT0; PCR[PA] = 01 → ALT1; PCR[PA] = 10 → ALT2; PCR[PA] = 11 → ALT3. This is intended to select the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”. Module included on the MCU. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMI[PADSELx] bitfields inside the SIUL module. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register. Weak pull down during reset. MPC5604P Microcontroller Data Sheet, Rev. 5 22 Preliminary—Subject to Change Without Notice Freescale Semiconductor 3 Electrical characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5604P MCU. The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “P”, “C”, “T” or “D”. • • “SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An example is the input voltage of a voltage regulator. “P”, “C”, “T” or “D” apply only to controller characteristics—specifications that define normal device operation. They specify how each characteristic is guaranteed. — P: parameter is guaranteed by production testing of each individual device. — C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process variations. — T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category. — D: parameters are derived mainly from simulations. NOTE All values are preliminary and subject to change during characterization. 3.1 Absolute maximum ratings Table 5. Absolute maximum ratings1 Symbol VSS_HV VDD_HV_IOx3 Parameter SR Digital ground SR 3.3 V / 5.0 V input/output supply voltage with respect to ground (VSS_HV) SR Input/output ground voltage with respect to ground (VSS_HV) Conditions — — Min 0 –0.3 Max2 0 6.0 Unit V V VSS_HV_IOx VDD_HV_FL — –0.1 –0.3 –0.3 –0.1 –0.3 –0.3 –0.1 0.1 6.0 VDD_HV_IOx + 0.3 0.1 6.0 VDD_HV_IOx + 0.3 0.1 V V — SR 3.3 V / 5.0 V code and data flash supply voltage with respect to ground Relative to (VSS_HV) VDD_HV_IOx SR Code and data flash ground with respect to ground (VSS_HV) — VSS_HV_FL VDD_HV_OSC V V — SR 3.3 V / 5.0 V crystal oscillator amplifier supply voltage with respect to ground Relative to (VSS_HV) VDD_HV_IOx SR 3.3 V / 5.0 V crystal oscillator amplifier reference voltage with respect to ground (VSS_HV) — VSS_HV_OSC V VDD_HV_REG — SR 3.3 V / 5.0 V voltage regulator supply voltage with respect to ground Relative to (VSS_HV) VDD_HV_IOx – 0.3 – 0.3 6.0 VDD_HV_IOx + 0.3 V MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23 Table 5. Absolute maximum ratings1 (continued) Symbol VDD_HV_AD04 Parameter SR 3.3 V / 5.0 V ADC0 supply and high reference voltage with respect to ground (VSS_HV) Conditions VDD_HV_REG < 2.7 V VDD_HV_REG > 2.7 V — Min – 0.3 – 0.3 –0.1 Max2 VDD_HV_REG + 0.3 6.0 0.1 V Unit V VSS_HV_AD0 SR ADC0 ground and low reference voltage with respect to ground (VSS_HV) SR 3.3 V / 5.0 V ADC0 supply and high reference voltage with respect to ground (VSS_HV) VDD_HV_AD14 VDD_HV_REG < 2.7 V VDD_HV_REG > 2.7 V — – 0.3 – 0.3 –0.1 VDD_HV_REG + 0.3 6.0 0.1 V VSS_HV_AD1 SR ADC1 ground and low reference voltage with respect to ground (VSS_HV) SR Slope characteristics on all VDD during power up5 with respect to ground (VSS_HV) SR Voltage on any pin with respect to ground (VSS_HV_IOx) with respect to ground (VSS_HV) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR Low voltage static current sink through VDD_LV SR Storage temperature V TVDD — 0.5 V/µs 3 V/S — VIN — Relative to VDD_HV_IOx — — — — –0.3 –0.3 –10 –50 — –55 6.0 VDD_HV_IOx + 0.3 10 50 155 150 V IINJPAD IINJSUM IVDD_LV TSTG 1 mA mA mA °C 2 3 4 5 Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. The difference between each couple of voltage supplies must be less that 300 mV, |VDD_HV_IOy – VDD_HV_IOx | < 300 mV. The difference between ADC voltage supplies must be less that 300 mV, |VDD_HV_ADC1 - VDD_HV_ADC0| < 300 mV. Guaranteed by device validation MPC5604P Microcontroller Data Sheet, Rev. 5 24 Preliminary—Subject to Change Without Notice Freescale Semiconductor Figure 4 shows the constraints of the different power supplies. VDD_HV_xxx 6.0V -0.3V -0.3V 6.0V VDD_HV_IOx Figure 4. Power supplies constraints The MPC5604P supply architecture allows of having ADC supply managed independently from standard VDD_HV supply. Figure 5 shows the constraints of the ADC power supply. VDD_HV_ADCx 6.0V -0.3V -0.3V 2.7V 6.0V VDD_HV_REG Figure 5. Independent ADC supply MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25 3.2 Recommended operating conditions Table 6. Recommended operating conditions (5.0 V) Symbol VSS_HV VDD_HV_IOx2 VSS_HV_IOx VDD_HV_FL SR Digital ground SR 5.0 V input/output supply voltage SR Input/output ground voltage SR 5.0 V code and data flash supply voltage Parameter Conditions — — — — Relative to VDD_HV_IOx VSS_HV_FL VDD_HV_OSC SR Code and data flash ground SR 5.0 V crystal oscillator amplifier supply voltage — — Relative to VDD_HV_IOx — — Relative to VDD_HV_IOx VDD_HV_AD03 SR 5.0 V ADC0 supply and high reference voltage — Relative to VDD_HV_REG — — Relative to VDD_HV_REG — — — — — fCPU = 64 MHz fCPU = 60 MHz TJ 1 Min 0 4.5 0 4.5 Max1 0 5.5 0 5.5 Unit V V V V VDD_HV_IO VDD_HV_IO x – 0.1 x + 0.1 0 4.5 0 5.5 V V VDD_HV_IO VDD_HV_IO x – 0.1 x + 0.1 0 4.5 0 5.5 V V VSS_HV_OSC VDD_HV_REG SR 5.0 V crystal oscillator amplifier reference voltage SR 5.0 V voltage regulator supply voltage VDD_HV_IO VDD_HV_IO x – 0.1 x + 0.1 4.5 VDD_HV_R EG – 0.1 0 4.5 VDD_HV_R EG – 0.1 0 — 0 — 0 –40 –40 –40 5.5 — 0 5.5 — 0 — 0 — 0 105 125 150 °C V V V V V °C V V V VSS_HV_AD0 VDD_HV_AD13 SR ADC0 ground and low reference voltage SR 5.0 V ADC1 supply and high reference voltage VSS_HV_AD1 VDD_LV_REGCOR4,5 VSS_LV_REGCOR VSS_LV_CORx4 TA 4 SR ADC1 ground and low reference voltage SR Internal supply voltage SR Internal reference voltage SR Internal supply voltage SR Internal reference voltage SR Ambient temperature under bias VDD_LV_CORx4,5 SR Junction temperature under bias — Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. 2 The difference between each couple of voltage supplies must be less that 300 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV. 3 The power supply voltage must be identical for ADC0 and ADC1 MPC5604P Microcontroller Data Sheet, Rev. 5 26 Preliminary—Subject to Change Without Notice Freescale Semiconductor 4 To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter. 5 The low voltage supplies (VDD_LV_xxx) are not all independent. VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted. VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx. Table 7. Recommended operating conditions (3.3 V) Symbol VSS_HV VDD_HV_IOx2 VSS_HV_IOx VDD_HV_FL SR Digital ground SR 3.3 V input/output supply voltage SR Input/output ground voltage SR 3.3 V code and data flash supply voltage Parameter Conditions — — — — Relative to VDD_HV_IOx VSS_HV_FL VDD_HV_OSC SR Code and data flash ground SR 3.3 V crystal oscillator amplifier supply voltage — — Relative to VDD_HV_IOx — — Relative to VDD_HV_IOx VDD_HV_AD03 SR 3.3 V ADC0 supply and high reference voltage — Relative to VDD_HV_REG — — Relative to VDD_HV_REG — — — — Min 0 3.0 0 3.0 Max1 0 3.6 0 3.6 Unit V V V V VDD_HV_IO VDD_HV_IO x – 0.1 x + 0.1 0 3.0 0 3.6 V V VDD_HV_IO VDD_HV_IO x – 0.1 x + 0.1 0 3.0 0 3.6 V V VSS_HV_OSC VDD_HV_REG SR 3.3 V crystal oscillator amplifier reference voltage SR 3.3 V voltage regulator supply voltage VDD_HV_IO VDD_HV_IO x – 0.1 x + 0.1 3.0 VDD_HV_R EG – 0.1 0 3.0 VDD_HV_R EG – 0.1 0 — 0 — 5.5 5.5 0 5.5 5.5 0 — 0 — V V V V V V V VSS_HV_AD0 VDD_HV_AD1 3 SR ADC0 ground and low reference voltage SR 3.3 V ADC1 supply and high reference voltage VSS_HV_AD1 VDD_LV_REGCOR4,5 VSS_LV_REGCOR 4 SR ADC1 ground and low reference voltage SR Internal supply voltage SR Internal reference voltage SR Internal supply voltage VDD_LV_CORx4,5 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 27 Table 7. Recommended operating conditions (3.3 V) (continued) Symbol VSS_LV_CORx4 TA Parameter SR Internal reference voltage SR Ambient temperature under bias Conditions — fCPU = 64 MHz fCPU = 60 MHz TJ 1 2 3 4 Min 0 –40 –40 –40 Max1 0 105 125 150 Unit V °C SR Junction temperature under bias — °C 5 Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. The difference between each couple of voltage supplies must be less that 300 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV. The power supply voltage must be identical for ADC0 and ADC1 To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter. The low voltage supplies (VDD_LV_xxx) are not all independent. VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted. VDD_LV_REGCOR and VDD_LV_RECORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx. Figure 6 shows the constraints of the different power supplies: VDD_HV_xxx 5.5V 3.0V VDD_HV_IOx 3.0V 5.5V Figure 6. Power supplies constraints The MPC5604P supply architecture allows of having ADC supply managed independently from standard VDD_HV supply. Figure 7 shows the constraints of the ADC power supply. MPC5604P Microcontroller Data Sheet, Rev. 5 28 Preliminary—Subject to Change Without Notice Freescale Semiconductor 5.5V 3.0V VDD_HV_REG 3.0V 5.5V Figure 7. Independent ADC supply 3.3 Thermal characteristics Table 8. Thermal characteristics for 144-pin LQFP1 No. Symbol 1 2 3 4 5 6 7 1 2 3 4 5 6 Parameter Thermal resistance junction-to-ambient, natural convection2 Thermal resistance junction-to-ambient, natural convection2 Thermal resistance junction-to-ambient2 Thermal resistance junction-to-ambient2 Thermal resistance junction to board4 5 Conditions Single layer board—1s Four layer board—2s2p @ 200 ft./min.3, single layer board—1s @ 200 ft./min.3, four layer board—2s2p — — — Typical Unit Value 52 43 43 37 31 12 2 °C/W °C/W °C/W °C/W °C/W °C/W °C/W RθJA RθJA RθJMA RθJMA RθJB ΨJT RθJCtop Thermal resistance junction to case (top) Junction to package top natural convection6 Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. Flow rate of forced air flow. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 29 Table 9. Thermal characteristics for 100-pin LQFP1 No. 1 2 3 4 5 6 7 1 2 3 4 5 6 Symbol RθJA RθJA RθJMA RθJMA RθJB ΨJT Parameter Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-ambient natural convection2 Thermal resistance junction-to-ambient2 Thermal resistance junction-to-ambient2 Thermal resistance junction to board4 Conditions Single layer board—1s Four layer board—2s2p @ 200 ft./min.3, single layer board—1s @ 200 ft./min.3, four layer board—2s2p — — — Typical Unit Value 56,3 43,4 43 35 27 14 3 °C/W °C/W °C/W °C/W °C/W °C/W °C/W RθJCtop Thermal resistance junction to case (Top)5 Junction to package top natural convection6 Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. Flow rate of forced air flow. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3.3.1 General notes for specifications at maximum junction temperature TJ = TA + (RθJA * PD) where: TA = ambient temperature for the package (oC) RθJA= junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) Eqn. 1 An estimation of the chip junction temperature, TJ, can be obtained from Equation 1: The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA Eqn. 2 MPC5604P Microcontroller Data Sheet, Rev. 5 30 Preliminary—Subject to Change Without Notice Freescale Semiconductor where: RθJA = junction to ambient thermal resistance (°C/W) RθJC= junction to case thermal resistance (°C/W) RθCA= case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: TJ = TT + (ΨJT x PD) where: TT = thermocouple temperature on top of the package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134U.S.A. (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic Packaging and Production, pp. 53-58, March 1998. 3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. Eqn. 3 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 31 3.4 Electromagnetic interference (EMI) characteristics Table 10. EMI Testing Specifications1 Symbol Radiated emissions, electric field Parameter VRE_TEM Conditions VDD = 5.5 V; TA = +25 °C 150 kHz–30 MHz RBW 9 kHz, Step Size 5 kHz 30 MHz–1 GHz RBW 120 kHz, Step Size 80 kHz fOSC/fBUS Frequency Level (Max) 20 20 26 26 K 3 18 18 15 15 M 2 — — — — dBμV Unit dBμV 16 MHz crystal 150 kHz–50 MHz 40 MHz bus 50–150 MHz No PLL frequency modulation 150–500 MHz 500–1000 MHz IEC Level SAE Level 16 MHz crystal 40 MHz bus ±2% PLL frequency modulation 150 kHz–50 MHz 50–150 MHz 15–500 MHz 500–1000 MHz IEC Level SAE Level 1 EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. 3.5 Electrostatic discharge (ESD) characteristics Table 11. ESD ratings1,2 Symbol VESD(HBM) VESD(CDM) 1 Parameter SR Electrostatic discharge (Human Body Model) SR Electrostatic discharge (Charged Device Model) Conditions — — Value 2000 750 (corners) 500 (other) Unit V V All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification MPC5604P Microcontroller Data Sheet, Rev. 5 32 Preliminary—Subject to Change Without Notice Freescale Semiconductor 3.6 3.6.1 Power management electrical characteristics Voltage regulator electrical characteristics The internal voltage regulator requires an external NPN (BCP56, BCP68, BCX68 or BC817) ballast to be connected as shown in Figure 8 and Figure 9. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. NOTE The voltage regulator output cannot be used to drive external circuits. Output pins are to be used only for decoupling capacitance. VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is not possible to provide VDD_LV_COR through external regulator. For the MPC5604P microcontroller, 10 µF should be placed between each of the three VDD_LV_CORx/VSS_LV_CORx supply pairs and also between the VDD_LV_REGCOR/VSS_LV_REGCOR pair. Additionally, 40 μF should be placed between the VDD_HV_REG/VSS_HV_REG pins. VDD = 3.0 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 to 125 °C, unless otherwise specified. VDD_HV_REG CDEC3 BCTRL MPC5604P VDD_LV_COR CDEC2 BCP56, BCP68, BCX68, BC817 CDEC1 Figure 8. Configuration without resistor on base MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 33 Table 12. Voltage regulator electrical characteristics Symbol VDD_LV_REGCOR CDEC1 RREG Parameter Conditions Min 1.145 Typ — 56 Max 1.4 Unit V µF mΩ — — 45 nF µF P Output voltage under maximum load Post-trimming run supply current configuration SR External decoupling/stability ceramic 4 capacitances capacitor SR Resulting ESR of all four CDEC1 absolute maximum value between 100 kHz and 10 MHz 40 — CDEC2 CDEC3 SR External decoupling/stability ceramic 4 capacitances of capacitor 100 nF each SR External decoupling/stability ceramic capacitor on VDD_HV_REG — 400 40 — — — — VDD_HV_REG CDEC3 BCTRL MPC5604P VDD_LV_COR RB BCP68, BCX68, BC817su CDEC2 CDEC1 Figure 9. Configuration without resistor on base MPC5604P Microcontroller Data Sheet, Rev. 5 34 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 13. Voltage regulator electrical characteristics Symbol VDD_LV_REGCOR RB CDEC1 Parameter Conditions Min 1.145 18 Typ — — Max 1.4 22 Unit V kΩ µF 19.5 30 — P Output voltage under maximum load Post-trimming run supply current configuration SR External Resistance on BJT base — SR External decoupling/stability ceramic Bipolar BCP68 or capacitor BCX68 or BC817. Three capacitances of 10uF Bipolar BC817. One capacitance of 22uF µF 14.3 22 — mΩ — — 45 nF µF RREG SR Resulting ESR of all four CDEC1 absolute maximum value between 100 kHz and 10 MHz CDEC2 CDEC3 SR External decoupling/stability ceramic 4 capacitances of capacitor 440 nF each 1760 1200 — — — SR External decoupling/stability ceramic 2 capacitances of 10 µF 2 × 10 capacitor on VDD_HV_REG each Table 14. Voltage regulator electrical characteristics Symbol VDD_LV_REGCOR RB CDEC1 Parameter Conditions Min 1.145 18 Typ — — Max 1.4 22 Unit V kΩ µF 19.5 30 — P Output voltage under maximum load Post-trimming run supply current configuration SR External Resistance on BJT base — SR External decoupling/stability ceramic Bipolar BCP68 or capacitor BCX68 or BC817. Three capacitances of 10uF Bipolar BC817. One capacitance of 22uF µF 14.3 22 — mΩ — — 45 nF µF RREG SR Resulting ESR of all four CDEC1 absolute maximum value between 100 kHz and 10 MHz CDEC2 CDEC3 SR External decoupling/stability ceramic 4 capacitances of capacitor 440 nF each 1760 1200 — — — SR External decoupling/stability ceramic 2 capacitances of 10 µF 2 × 10 capacitor on VDD_HV_REG each 3.6.2 • Voltage monitor electrical characteristics POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state The device implements a Power On Reset module to ensure correct power-up initialization, as well as three low voltage detectors to monitor the VDD and the VDD_LV voltage while device is supplied: MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 35 • • • LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range LVDLVCOR monitors low voltage digital power domain Table 15. Low voltage monitor electrical characteristics Symbol VPORH VPORUP VREGLVDMOK_H VREGLVDMOK_L VFLLVDMOK_H VFLLVDMOK_L VIOLVDMOK_H VIOLVDMOK_L VIOLVDM5OK_H VIOLVDM5OK_L VMLVDDOK_H VMLVDDOK_L 1 Parameter T Power-on reset threshold P Supply for functional POR module P Regulator low voltage detector high threshold P Regulator low voltage detector low threshold P Flash low voltage detector high threshold P Flash low voltage detector low threshold P I/O low voltage detector high threshold P I/O low voltage detector low threshold P I/O 5V low voltage detector high threshold P I/O 5V low voltage detector low threshold P Digital supply low voltage detector high P Digital supply low voltage detector low Conditions1 — TA = 25°C — — — — — — — — — — Value Unit Min 1.5 1.0 — 2.6 — 2.6 — 2.6 — 3.8 — 1.08 Max 2.7 — 2.95 — 2.95 — 2.95 — 4.4 — 1.14 — V V V V V V V V V V V V VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 to 125°C, unless otherwise specified 3.7 Power up/down sequencing The MPC5604P implements a precise sequence to ensure each module is started only when all conditions for switching it ON are available. This prevents overstress event or miss-functionality within and outside the device: • a POWER_ON module working on voltage regulator supply is controlling the correct start-up of the regulator. This is a key module ensuring safe configuration for all Voltage regulator functionality when supply is below 1.5V. Associated POWER_ON (or POR) signal is active low. Several Low Voltage Detectors, working on voltage regulator supply are monitoring the voltage of the critical modules (Voltage regulator, I/Os, Flash and Low voltage domain). LVDs are gated low when POWER_ON is active. a POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active high and released to all modules including I/Os, Flash and RC16 oscillator needed during power-up phase and reset phase. When POWER_OK is low the associated module are set into a safe state. • • MPC5604P Microcontroller Data Sheet, Rev. 5 36 Preliminary—Subject to Change Without Notice Freescale Semiconductor VDD_HV_REG VPOR_UP VPORH VLVDHV3H 3.3V 0V 3.3V 0V 3.3V 0V VMLVDOK_H POWER_ON LVDM (HV) VDD_LV_REGCOR 1.2V 0V 3.3V 0V 3.3V 0V LVDD (LV) POWER_OK RC16MHz Oscillator ~1us 1.2V 0V Internal Reset Generation Module FSM P0 P1 1.2V 0V Figure 10. Power-up typical sequence VLVDHV3L VDD_HV_REG VPORH 3.3V 0V 3.3V LVDM (HV) 0V 3.3V 0V 1.2V 0V 3.3V 0V 3.3V POWER_ON VDD_LV_REGCOR LVDD (LV) POWER_OK RC16MHz Oscillator 0V 1.2V 0V Internal Reset Generation Module FSM IDLE P0 1.2V 0V Figure 11. Power-down typical sequence MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 37 VLVDHV3L VDD_HV_REG VLVDHV3H 3.3V 0V 3.3V LVDM (HV) 0V 3.3V 0V 1.2V 0V 3.3V 0V 3.3V POWER_ON VDD_LV_REGCOR LVDD (LV) POWER_OK RC16MHz Oscillator ~1us Internal Reset Generation Module FSM 0V 1.2V 0V IDLE P0 P1 1.2V 0V Figure 12. Brown-out typical sequence MPC5604P Microcontroller Data Sheet, Rev. 5 38 Preliminary—Subject to Change Without Notice Freescale Semiconductor 3.8 3.8.1 DC electrical characteristics NVUSRO register Portions of the MPC5604P device configuration (that is, high voltage supply, oscillator margin, and watchdog enable/disable after reset) are controlled via bit values in the NVUSRO register. NVUSRO[PAD3V5V] controls the device configuration as follows: Table 16. NVUSRO[PAD3V5V] field description1 Value2 0 1 1 2 Description High Voltage supply is 5.0 V High Voltage supply is 3.3 V See the MPC5604P Reference Manual for more information on the NVUSRO register. Default manufacturing value before flash initialization is '1' (3.3 V). The DC electrical characteristics in the following sections are dependent on the PAD3V5V value as described above. 3.8.2 DC electrical characteristics (5 V) Table 17 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V, NVUSRO[PAD3V5V]=0) as described in Figure 13. VIN VDD VIH VHYS VIL PDIx = ‘1’ (GPDI register of SIUL) PDIx = ‘0’ Figure 13. I/O input DC electrical characteristics definition MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 39 Table 17. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) Symbol VIL VIL VIH VIH VHYS VOL_S VOH_S VOL_M VOH_M VOL_F VOH_F VOL_SYM VOH_SYM IPU Parameter D Minimum low level input voltage P Maximum level input voltage P Minimum high level input voltage D Maximum high level input voltage T Schmitt trigger hysteresis P Slow, low level output voltage P Slow, high level output voltage Conditions — — — — — IOL = 3 mA IOH = –3 mA Min –0.1 — 0.65 VDD_HV_IOx — 0.1 VDD_HV_IOx — 0.8VDD_HV_IOx — 0.8 VDD_HV_IOx — 0.8 VDD_HV_IOx — 0.8 VDD_HV_IOx –130 — 10 — –1 –0.5 –5 — 1 Max — 0.35 VDD_HV_IOx — VDD_HV_IOx + 0.1 — 0.1 VDD_HV_IOx — 0.1 VDD_HV_IOx — 0.1 VDD_HV_IOx — 0.1 VDD_HV_IOx — — –10 — 130 1 0.5 5 10 1 Unit V V V V V V V V V V V V V µA P Medium, low level output voltage IOL = 3 mA P Medium, high level output voltage P Fast, low level output voltage P Fast, high level output voltage P Symmetric, low level output voltage P Symmetric, high level output voltage P Equivalent pull-up current IOH = –3 mA IOL = 3 mA IOH = –3 mA IOL = 3 mA IOH = –3 mA VIN = VIL VIN = VIH IPD P Equivalent pull-down current VIN = VIL VIN = VIH µA IIL IIL IVPP CIN 1 P Input leakage current (all bidirectional ports) P Input leakage current (all ADC input-only ports) P Input leakage current on VPP leakage pad D Input capacitance TA = –40 to 125 °C TA = –40 to 125 °C — — µA µA μA pF “SR” parameter values must not exceed the absolute maximum ratings shown in Table 5. MPC5604P Microcontroller Data Sheet, Rev. 5 40 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 18. Supply current (5.0 V, NVUSRO[PAD3V5V]=0) Value1 Symbol I DD_LV_CORE Parameter T Supply RUN - Maximum Mode2 current RUN - Typical Mode3 Conditions Typ V DD_LV_CORE Unit Max 77 88 56 65 TBD 10 10 12 19 mA 40 MHz 64 MHz 40 MHz 64 MHz 62 71 45 52 60 1.5 1 10 15 externally forced at 1.3 V P RUN - Maximum Mode4 HALT Mode5 STOP Mode6 V DD_LV_CORE 64 MHz — — — — externally forced at 1.3 V V DD_LV_CORE externally forced at 1.3 V VDD_LV_CORE externally forced at 1.3 V VDD_HV_FL at 5.0 V VDD_HV_FL at 5.0 V IDD_FLASH T FLASH supply current during read FLASH supply current during erase operation on 1 flash module IDD_ADC T ADC supply current - Maximum Mode2 VDD_HV_AD0 at 5.0 V VDD_HV_AD1 at 5.0 V ADC Freq = 16MHz ADC supply current - Typical Mode3 ADC17 ADC0 ADC17 ADC0 3.5 3 0.8 5 4 1 0.005 0.006 2.6 3.2 I DD_OSC 1 2 3 4 5 6 7 T OSC supply current VDD_OSC at 5.0 V 8 MHz All values to be confirmed after characterization/data collection. Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled, 125 °C ambient. I/O supply current excluded. Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only, 105 °C ambient. I/O supply current excluded. Code fetched from Ram, PLL0: 64 MHz system clock (x4 multiplier with 16MHz XTAL), PLL1 is ON @ PHI_div2 = 120 Mhz and PHI_div3 = 80 Mhz, auxiliary clock sources set that all peripherals receive maximum frequency, all peripheral enabled. Halt mode configurations: Code fetched from RAM, C & D FLASH in low power mode, OSC/PLL0/PLL1 are OFF, Core clock frozen, all peripherals are disabled. STOP "P" mode DUT configuration: Code fetched from RAM, C & D FLASH off, OSC/PLL0/PLL1 are OFF, Core clock frozen, all peripherals are disabled. Includes Temperature Sensor current consumption. 3.8.3 DC Electrical characteristics (3.3 V) Table 19 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V, NVUSRO[PAD3V5V]=1) as described in Figure 14. MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 41 VIN VDD VIH VHYS VIL PDIx = ‘1’ (GPDI register of SIUL) PDIx = ‘0’ Figure 14. I/O input DC electrical characteristics definition Table 19. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)1 Symbol VIL VIL VIH VIH VHYS VOL_S VOH_S VOL_M VOH_M VOL_F VOH_F VOL_SYM VOH_SYM IPU Parameter D Minimum low level input voltage P Maximum low level input voltage P Minimum high level input voltage D Maximum high level input voltage T Schmitt trigger hysteresis Conditions — — — — — IOL = 1.5 mA IOH = –1.5 mA Min –0.12 — 0.65 VDD_HV_IOx — 0.1 VDD_HV_IOx — VDD_HV_IOx – 0.8 — VDD_HV_IOx – 0.8 — VDD_HV_IOx – 0.8 — VDD_HV_IOx – 0.8 –130 — Max — 0.35 VDD_HV_IOx — VDD_HV_IOx + — 0.5 — 0.5 — 0.5 — 0.5 — — –10 0.12 Unit V V V V V V V V V V V V V µA P Slow, low level output voltage P Slow, high level output voltage P Medium, low level output voltage IOL = 2 mA P Medium, high level output voltage P Fast, high level output voltage P Fast, high level output voltage P Symmetric, high level output voltage P Symmetric, high level output voltage P Equivalent pull-up current IOH = –2 mA IOL = 1.5 mA IOH = –1.5 mA IOL = 1.5 mA IOH = –1.5 mA VIN = VIL VIN = VIH MPC5604P Microcontroller Data Sheet, Rev. 5 42 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 19. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)1 (continued) Symbol IPD Parameter P Equivalent pull-down current Conditions VIN = VIL VIN = VIH IIL IIL IVPP CIN 1 2 Min 10 — — — –5 — Max — 130 1 0.5 5 — Unit µA P Input leakage current (all bidirectional ports) P Input leakage current (all ADC input-only ports) P Input leakage current on VPP leakage pad D Input capacitance TA = –40 to 125 °C TA = –40 to 125 °C — — µA µA μA pF These specifications are design targets and subject to change per device characterization. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 5. Table 20. Supply current (3.3 V, NVUSRO[PAD3V5V]=1) Value1 Symbol I DD_LV_CORE Parameter T Supply RUN - Maximum Mode2 current RUN - Typical Mode 3 Conditions Typ V DD_LV_CORE Unit Max 77 89 56 66 TBD 10 10 10 12 mA 40 MHz 64 MHz 40 MHz 64 MHz 62 71 45 53 60 1.5 1 8 10 externally forced at 1.3 V P RUN - Maximum HALT Mode5 STOP Mode6 Mode4 V DD_LV_CORE 64 MHz — — — — externally forced at 1.3 V V DD_LV_CORE externally forced at 1.3 V VDD_LV_CORE externally forced at 1.3 V IDD_FLASH T FLASH supply current during read on VDD_HV_FL at 3.3 V single mode FLASH supply current during erase operation on single mode VDD_HV_FL at 3.3 V IDD_ADC T ADC supply current - Maximum Mode2 VDD_HV_AD0 at 3.3 V VDD_HV_AD1 at 3.3 V ADC Freq = 16MHz ADC supply current - Typical Mode3 ADC17 ADC0 ADC1 7 2.5 2 0.8 4 4 1 ADC0 I DD_OSC 1 2 0.005 0.006 2.4 3 T OSC supply current VDD_OSC at 3.3 V 8 MHz All values to be confirmed after characterization/data collection. Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled, 125 °C ambient. I/O supply current excluded. MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 43 3 4 Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only, 105 °C ambient. I/O supply current excluded. Code fetched from Ram, PLL0: 64 MHz system clock (x4 multiplier with 16MHz XTAL), PLL1 is ON @ PHI_div2 = 120 Mhz and PHI_div3 = 80 Mhz, auxiliary clock sources set that all peripherals receive maximum frequency, all peripheral enabled. 5 Halt mode configurations: Code fetched from RAM, C & D FLASH in low power mode, OSC/PLL0/PLL1 are OFF, Core clock frozen, all peripherals are disabled. 6 STOP "P" mode DUT configuration: Code fetched from RAM, C & D FLASH off, OSC/PLL0/PLL1 are OFF, Core clock frozen, all peripherals are disabled. 7 Includes Temperature Sensor current consumption. 3.8.4 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 21. Table 21. I/O supply segment Supply segment Package 1 144 LQFP 100 LQFP pin8 – pin20 2 3 4 5 6 7 pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5 — pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10 Table 22 provides the weight of concurrent switching I/Os. In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below the 100%. Table 22. I/O weight 144 LQFP PAD Weight 5V Weight 3.3V Weight 5V Weight 3.3V NMI PAD[6] PAD[49] PAD[84] PAD[85] PAD[86] MODO0 PAD[7] PAD[36] PAD[8] PAD[37] PAD[5] PAD[39] PAD[35] PAD[87] 1% 6% 5% 14% 9% 9% 12% 4% 5% 5% 5% 5% 5% 5% 12% 1% 5% 4% 10% 7% 6% 8% 4% 4% 4% 4% 4% 4% 4% 9% 1% 14% 14% — — — — 11% 11% 10% 10% 9% 9% 8% — 1% 13% 12% — — — — 10% 9% 9% 9% 8% 8% 7% — 100 LQFP MPC5604P Microcontroller Data Sheet, Rev. 5 44 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 22. I/O weight 144 LQFP PAD Weight 5V Weight 3.3V Weight 5V Weight 3.3V PAD[88] PAD[89] PAD[90] PAD[91] PAD[57] PAD[56] PAD[53] PAD[54] PAD[55] PAD[96] PAD[65] PAD[67] PAD[33] PAD[68] PAD[23] PAD[69] PAD[34] PAD[70] PAD[24] PAD[71] PAD[66] PAD[25] PAD[26] PAD[27] PAD[28] PAD[63] PAD[72] PAD[29] PAD[73] PAD[31] PAD[74] PAD[30] PAD[75] 9% 10% 15% 6% 8% 13% 14% 15% 25% 27% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 6% 7% 11% 5% 7% 11% 12% 13% 22% 24% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% — — — — 8% 13% 14% 15% 25% — 1% — 1% — 1% — 1% — 1% — 1% 1% 1% 1% 1% 1% — 1% — 1% — 1% — — — — — 7% 11% 12% 13% 22% — 1% — 1% — 1% — 1% — 1% — 1% 1% 1% 1% 1% 1% — 1% — 1% — 1% — 100 LQFP MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 45 Table 22. I/O weight 144 LQFP PAD Weight 5V Weight 3.3V Weight 5V Weight 3.3V PAD[32] PAD[76] PAD[64] PAD[0] PAD[1] PAD[107] PAD[58] PAD[106] PAD[59] PAD[105] PAD[43] PAD[104] PAD[44] PAD[103] PAD[2] PAD[101] PAD[21] TMS TCK PAD[20] PAD[3] PAD[61] PAD[102] PAD[60] PAD[100] PAD[45] PAD[98] PAD[46] PAD[99] PAD[62] PAD[92] VPP_TEST PAD[4] 1% 1% 1% 23% 21% 20% 19% 18% 17% 16% 15% 14% 13% 12% 11% 11% 10% 1% 1% 16% 4% 9% 11% 11% 12% 12% 12% 12% 13% 13% 13% 1% 14% 1% 1% 1% 20% 18% 17% 16% 16% 15% 14% 13% 13% 12% 11% 10% 9% 8% 1% 1% 11% 3% 8% 10% 10% 10% 10% 11% 11% 11% 11% 12% 1% 12% 1% — 1% 23% 21% — 19% — 17% — 15% — 13% — 11% — 10% 1% 1% 16% 4% 9% — 11% — 12% — 12% — 13% — 1% 14% 1% — 1% 20% 18% — 16% — 15% — 13% — 12% — 10% — 8% 1% 1% 11% 3% 8% — 10% — 10% — 11% — 11% — 1% 12% 100 LQFP MPC5604P Microcontroller Data Sheet, Rev. 5 46 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 22. I/O weight 144 LQFP PAD Weight 5V Weight 3.3V Weight 5V Weight 3.3V PAD[16] PAD[17] PAD[42] PAD[93] PAD[95] PAD[18] PAD[94] PAD[19] PAD[77] PAD[10] PAD[78] PAD[11] PAD[79] PAD[12] PAD[41] PAD[47] PAD[48] PAD[51] PAD[52] PAD[40] PAD[80] PAD[9] PAD[81] PAD[13] PAD[82] PAD[22] PAD[83] PAD[50] PAD[97] PAD[38] PAD[14] PAD[15] 13% 13% 13% 12% 12% 12% 11% 11% 10% 10% 9% 9% 8% 7% 7% 5% 4% 4% 5% 5% 9% 10% 10% 10% 10% 10% 10% 10% 10% 10% 9% 9% 12% 11% 11% 11% 11% 10% 10% 10% 9% 9% 8% 8% 7% 7% 6% 4% 4% 4% 4% 5% 8% 9% 9% 9% 9% 9% 9% 9% 9% 9% 8% 8% 13% 13% 13% — — 12% — 11% — 10% — 9% — 7% 7% 5% 4% 4% 5% 6% — 11% — 12% — 13% — 14% — 14% 14% 15% 12% 11% 11% — — 10% — 10% — 9% — 8% — 7% 6% 4% 4% 4% 4% 5% — 10% — 11% — 12% — 12% — 13% 13% 13% 100 LQFP MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 47 3.9 Temperature sensor electrical characteristics Table 23. Temperature sensor electrical characteristics Symbol — Parameter P Accuracy Conditions TJ = –40 °C to TA = 25 °C TJ = TA to 125 °C TS D Minimum sampling period Min TBD TBD 1.5 Max TBD TBD — Unit °C °C µs 3.10 Main oscillator electrical characteristics Table 24. Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) Symbol fOSC gm VOSC SR Oscillator frequency P Transconductance T Oscillation amplitude on EXTAL pin T Start-up time1,2 Parameter Min 4 6.5 1 8 Max 40 25 — — Unit MHz mA/V V ms The MPC5604P provides an oscillator/resonator driver. tOSCSU 1 The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive loads can cause long start-up time. 2 Value captured when amplitude reaches 90% of EXTAL Table 25. Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) Symbol fOSC gm VOSC tOSCSU 1 Parameter Min 4 4 1 8 Max 40 20 — — Unit MHz mA/V V ms SR Oscillator frequency P Transconductance T Oscillation amplitude on EXTAL pin T Start-up time1,2 The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive loads can cause long start-up time. 2 Value captured when amplitude reaches 90% of EXTAL Table 26. Input clock characteristics Symbol fOSC fCLK trCLK tDC SR Oscillator frequency SR Frequency in bypass SR Rise/fall time in bypass SR Duty cycle Parameter Min 4 — — 47.5 Typ — — — 50 Max 40 64 1 52.5 Unit MHz MHz ns % MPC5604P Microcontroller Data Sheet, Rev. 5 48 Preliminary—Subject to Change Without Notice Freescale Semiconductor 3.11 FMPLL electrical characteristics Table 27. PLLMRFM electrical specifications1 (VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) Value Symbol Parameter PLL reference frequency range2 Phase detector input frequency range (after pre-divider) Clock frequency range in normal mode Free running frequency Conditions min max 40 16 120 150 MHz MHz MHz MHz Unit fref_crystal fref_ext fpll_in fFMPLLO UT D D D P Crystal reference — — Measured using clock division — typically /16 — — Lower limit Upper limit 4 4 4 20 fFREE fsys tCYC fLORL fLORH fSCM CJITTER D D D On-chip PLL frequency2 System clock period Loss of reference frequency window3 16 — 1.6 24 20 -4 — 120 1 / fsys 3.7 56 150 4 10 MHz ns MHz D T Self-clocked mode frequency4,5 CLKOUT period jitter6,7,8,9 Short-term jitter10 Long-term jitter (avg. over 2 ms interval) — fSYS maximum fPLLIN = 16 MHz (resonator), fPLLCLK @ 64 MHz, 4000 cycles — — — — Center spread Down Spread MHz % fCLKOUT ns tlpll tdc fLCK fUL fCS fDS fMOD 1 2 D D D D D PLL lock time 11, 12 Duty cycle of reference Frequency LOCK range Frequency un-LOCK range Modulation Depth — 40 -6 -18 ±0.25 -0.5 — 200 60 6 18 ±4.013 -8.0 70 μs % % fsys % fsys %fsys D Modulation frequency14 — kHz All values given are initial design targets and subject to change. Considering operation with PLL not bypassed. 3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode. 4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR window. MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 49 5 fVCO self clock range is 20-150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced mode. 6 This value is determined by the crystal manufacturer and board design. 7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 8 Proper PC board layout procedures must be followed to achieve specifications. 9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 10 Short term jitter is measured on the clock rising edge at cycle n and cycle n+4. 11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this PLL, load capacitors should not exceed these limits. 12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 13 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz). 14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50kHz. 3.12 16 MHz RC oscillator electrical characteristics Table 28. 16 MHz RC oscillator electrical characteristics Symbol fRC Parameter P RC oscillator frequency P Fast internal RC oscillator variation over temperature and supply with respect to fRC at TA = 25 °C in high-frequency configuration P Post Trim Accuracy: The variation of the PTF1 from the 16 MHz P Fast internal RC oscillator trimming step Conditions TA = 25 °C — Min — -5 Typ 16 — Max — 5 Unit MHz % ΔRCMVAR ΔRCMTRIM ΔRCMSTEP 1 TA = 25 °C TA = 25 °C -1 — — 1.6 1 — % % PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and temperature MPC5604P Microcontroller Data Sheet, Rev. 5 50 Preliminary—Subject to Change Without Notice Freescale Semiconductor 3.13 Analog-to-digital converter (ADC) electrical characteristics Offset Error OSE 1023 Gain Error GE The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter. 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE Figure 15. ADC characteristics and error definitions 3.13.1 Input impedance and ADC accuracy To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 51 be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 kΩ is obtained (REQ = 1 / (fc×CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Eqn. 4 R S + R F + R L + R SW + R AD - -V A • -------------------------------------------------------------------------- < 1 LSB R EQ 2 Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Sampling Source RS Filter RF Current Limiter RL RAD VA CF CP1 CP2 RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 16. Input equivalent circuit A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). MPC5604P Microcontroller Data Sheet, Rev. 5 52 Preliminary—Subject to Change Without Notice Freescale Semiconductor VCS VA VA2 Voltage Transient on CS ΔV < 0.5 LSB 1 2 τ1 < (RSW + RAD) CS 2048 • C S MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 55 3.13.2 ADC conversion characteristics Table 29. ADC conversion characteristics Value Unit Min Typ — Max 60 MHz 33 Symbol fCK Parameter Conditions1 — SR ADC Clock frequency (depends on ADC configuration) (The duty cycle depends on AD_clk2 frequency) SR Sampling frequency D Sample time4 fADC = 20 MHz, INPSAMP = 3 fs tADC_S — — 125 — 1.53 MHz ns fADC = 9 MHz, INPSAMP = 255 tADC_C CS7 CP17 CP2 7 7 28.2 0.650 — — — — — — -5 — — — — — — — — — 2.5 3 1 0.6 3 2 5 µs µs pF pF pF kΩ kΩ kΩ mA P Conversion time5 D ADC input sampling capacitance D ADC input pin capacitance 1 D ADC input pin capacitance 2 D Internal resistance of analog source D Internal resistance of analog source T Input current injection fADC = 20 MHz6, INPCMP = 1 — — — VDD_HV_ADC = 5 V+/-10% VDD_HV_ADC = 3.3 V+/-10% — Current injection on one ADC input, different from the converted one. Remains within TUE spec. No overload No overload — — — — RSW1 RAD7 IINJ INL DNL OFS GNE TUE TUE 1 P Integral Non Linearity P Differential Non Linearity T Offset error T Gain error P Total unadjusted error without current injection T Total unadjusted error with current injection –1.5 –1.0 — — -2.5 -3 — — ±1 ±1 — — 1.5 1.0 — — 2.5 3 LSB LSB LSB LSB LSB LSB VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 to +125 °C, unless otherwise specified and analog input voltage from VSS_HV_ADCx to VDD_HV_ADCx. 2 AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC. 3 When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost. 4 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. MPC5604P Microcontroller Data Sheet, Rev. 5 56 Preliminary—Subject to Change Without Notice Freescale Semiconductor 5 6 This parameter includes the sample time tADC_S. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC. 7 See Figure 16. 3.14 Flash memory electrical characteristics Table 30. Program and erase specifications Symbol Tdwprogram TBKPRG Parameter P Double Word (64 bits) Program Time4 P Bank Program (512KB)4, 5 P Bank Program (64KB) T16kpperase T32kpperase T128kpperase 4, 5 Min Value — — — — — — Typical Value1 22 1.45 0.18 300 400 800 Initial Max2 50 1.65 0.21 500 600 1300 Max3 500 33 4.10 5000 5000 7500 Unit μs s s ms ms ms P 16 KB Block Pre-program and Erase Time P 32 KB Block Pre-program and Erase Time P 128 KB Block Pre-program and Erase Time 1 2 3 4 5 Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. The maximum program & erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. Actual hardware programming times. This does not include software overhead. Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column). Table 31. Flash module life1 Value Symbol P/E Parameter C Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (TJ) C Number of program/erase cycles per block for 32 Kbyte blocks over the operating temperature range (TJ) C Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) C Minimum data retention at 85 °C average ambient temperature2 Conditions Min — 100,000 Typ — cycles Unit P/E — 10,000 100,000 cycles (TBC) 100,000 cycles (TBC) — — — years years years P/E — 1,000 Retention Blocks with 0 – 1,000 P/E cycles Blocks with 10,000 P/E cycles Blocks with 100,000 P/E cycles 20 10 5 1 TBD: To be defined MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 57 2 Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. Table 32. Flash read access timing Symbol Fmax C Parameter Conditions1 2 wait states 0 wait states Max 66 18 Unit MHz C Maximum working frequency at given number of WS in worst conditions 1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified 3.15 3.15.1 AC Specifications Pad AC Specifications Table 33. Output pin transition times Value2 Unit Min Typ — — — — — — — — — — — — — — — — — — — — Max 50 100 125 40 50 75 10 20 40 12 25 40 4 6 12 4 7 12 4 5 ns ns ns ns — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 — — — — — — — — — — — — — — Symbol C Parameter Conditions1 CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF pin3 CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF pin3 CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 Ttr CC D Output transition time output pin3 SLOW configuration T D D T D Ttr CC D Output transition time output MEDIUM configuration T D D T D Ttr CC D Output transition time output FAST configuration Tsim CC T Symmetric, same drive strength between N and P transistor 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified MPC5604P Microcontroller Data Sheet, Rev. 5 58 Preliminary—Subject to Change Without Notice Freescale Semiconductor 2 3 All values need to be confirmed during device validation. CL includes device and package capacitances (CPKG < 5 pF). 3.16 3.16.1 AC Timing Characteristics RESET Pin Characteristics The MPC5604P implements a dedicated bidirectional RESET pin. VDD VDDMIN VRESET VIH VIL device reset forced by VRESET device start-up phase TPOR Figure 19. Start-up reset requirements MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 59 VRESET hw_rst VDD ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset Figure 20. Noise filtering on reset signal Table 34. RESET electrical characteristics Symbol VIH VIL VHYS VOL C Parameter Conditions1 Min SR P Input High Level CMOS (Schmitt Trigger) SR P Input low Level CMOS (Schmitt Trigger) CC C Input hysteresis CMOS (Schmitt Trigger) CC P Output low level — — — Push Pull, IOL = 2mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1mA, VDD = 5.0 V ± 10%, PAD3V5V = 13 Push Pull, IOL = 1mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) 0.65VDD −0.4 0.1VDD — Value2 Unit Typ — — — — Max VDD+0.4 0.35VDD — 0.1VDD V V V V — — — — 0.1VDD 0.5 MPC5604P Microcontroller Data Sheet, Rev. 5 60 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 34. RESET electrical characteristics (continued) Symbol Ttr C Parameter Conditions 1 Value2 Unit Min Typ — — — — — — — — — Max 10 20 40 12 25 40 40 — 1 ns ns ms ns — — — — — — — 500 — CC D Output transition time output pin4 MEDIUM configuration CL = 25pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 50pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 100pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 25pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 50pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 WFRST SR P RESET input filtered pulse WNFRST SR P RESET input not filtered pulse TPOR — — CC D maximum delay before monotonic VDD_HV supply ramp internal reset is released after all VDD_HV reach nominal supply VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 5.0 V ± 10%, PAD3V5V = 15 |IWPU| CC P Weak pull-up current absolute value 10 10 10 — — — 150 150 250 µA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device reference manual). 4 C includes device and package capacitance (C L PKG < 5 pF). 5 The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 1 2 3.16.2 No. 1 2 3 4 IEEE 1149.1 interface timing Table 35. JTAG pin AC electrical characteristics Symbol tJCYC tJDC tTCKRISE CC CC CC C D TCK cycle time D TCK clock pulse width (measured at VDD_HV_IOx/2) D TCK rise and fall times (40% - 70%) D TMS, TDI data setup time Parameter Conditions Min Max Unit — — — — 100 40 — 5 — 60 3 — ns ns ns ns tTMSS, tTDIS CC MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 61 Table 35. JTAG pin AC electrical characteristics (continued) No. Symbol C Parameter Conditions Min Max Unit — — — — — — — — — 25 — 0 40 — — — 50 50 — 40 — — 50 50 50 — — ns ns ns ns ns ns ns ns ns 5 tTMSH, tTDIH CC 6 7 8 11 12 13 14 15 tTDOV tTDOI tTDOHZ tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT CC CC CC CC CC CC CC CC D TMS, TDI data hold time D TCK low to TDO data valid D TCK low to TDO data invalid D TCK low to TDO high impedance D TCK falling edge to output valid D TCK falling edge to output valid out of high impedance D TCK falling edge to output high impedance D Boundary scan input valid to TCK rising edge D TCK rising edge to boundary scan input invalid TCK 2 3 1 3 2 Figure 21. JTAG test clock input timing MPC5604P Microcontroller Data Sheet, Rev. 5 62 Preliminary—Subject to Change Without Notice Freescale Semiconductor TCK 4 5 TMS, TDI 6 7 8 TDO Figure 22. JTAG test access port timing MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 63 TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 23. JTAG boundary scan timing 3.16.3 Nexus timing Table 36. Nexus debug port timing1 Value No. 1 2 3 4 5 Symbol tMCYC tMDOV tMSEOV tEVTOV tTCYC C Parameter Min Typ — — — — — Max — 6 6 6 — 32 valid2 — — — 643 Unit ns ns ns ns ns CC D MCKO cycle time CC D MCKO low to MDO data CC D MCKO low to MSEO data valid2 CC D MCKO low to EVTO data valid2 CC D TCK cycle time MPC5604P Microcontroller Data Sheet, Rev. 5 64 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 36. Nexus debug port timing1 (continued) Value No. 6 Symbol tNTDIS tNTMSS 7 tNTDIH tNTMSH 8 9 1 2 C Parameter Min Typ — — — — — — Max — — — — 35 — 6 6 10 10 — 6 Unit ns ns ns ns ns ns CC D TDI data setup time CC D TMS data setup time CC D TDI data hold time CC D TMS data hold time CC D TCK low to TDO data valid CC D TCK low to TDO data invalid tTDOV tTDOI All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3 Lower frequency is required to be fully compliant to standard. 1 MCKO 2 3 4 MDO MSEO EVTO Output Data Valid Figure 24. Nexus output timing TCK EVTI EVTO 5 Figure 25. Nexus event trigger and test clock timings MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 65 TCK 6 7 TMS, TDI 9 8 TDO Figure 26. Nexus TDI, TMS, TDO timing 3.16.4 No. 1 2 3 1 2 External interrupt timing (IRQ pin) Table 37. External interrupt timing1 Symbol tIPWL CC CC CC C D D D Parameter IRQ pulse width low IRQ pulse width high IRQ edge to edge time2 Conditions — — — Min 4 4 4+N 3 Max Unit — — — tCYC tCYC tCYC tIPWH tICYC IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200pF with SRC = 0b00. Applies when IRQ pins are configured for rising edge or falling edge events, but not both. 3 N= ISR time to clear the flag MPC5604P Microcontroller Data Sheet, Rev. 5 66 Preliminary—Subject to Change Without Notice Freescale Semiconductor IRQ 1 2 3 Figure 27. External interrupt timing 3.16.5 No. 1 2 3 4 5 6 7 8 DSPI timing Table 38. DSPI timing C D Parameter DSPI cycle time Conditions Master (MTFE = 0) Slave (MTFE = 0) CC CC CC CC CC D D D D D D D CS to SCK delay After SCK delay SCK duty cycle Slave access time Slave SOUT disable time PCSx to PCSS time PCSS to PCSx time Data setup time for inputs D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) CC Data hold time for inputs D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) 11 -5 — — Master (MTFE = 0) Slave 35 35 -5 4 — — — — ns — — — SS active to SOUT valid SS inactive to SOUT High-Z or invalid — — Master (MTFE = 0) Slave Min 60 60 16 26 Max — ns — — — ns ns ns ns ns ns ns Unit Symbol CC tSCK tCSC tASC tSDC tA tDIS 0.4 * tSCK 0.6 * tSCK — — 13 13 35 4 TBD 16 — — — — tPCSC CC tPASC CC CC 9 tSUI ns 10 tHI MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 67 Table 38. DSPI timing (continued) No. Symbol C Parameter Data valid (after SCK edge) 11 tSUO CC D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data hold time for outputs 12 tHO CC D Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) 6 -2 — — Master (MTFE = 0) Slave — — -2 6 12 12 — — ns Conditions Master (MTFE = 0) Slave Min — — Max 12 36 ns Unit 2 PCSx 4 SCK Output (CPOL=0) 4 1 3 SCK Output (CPOL=1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data First Data Figure 28. DSPI classic SPI timing - master, CPHA = 0 MPC5604P Microcontroller Data Sheet, Rev. 5 68 Preliminary—Subject to Change Without Notice Freescale Semiconductor PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data Figure 29. DSPI classic SPI timing - master, CPHA = 1 2 SS 1 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4 3 6 Last Data First Data Last Data Figure 30. DSPI classic SPI timing - slave, CPHA = 0 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 69 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 5 SOUT 11 12 First Data 9 10 Data Last Data Data Last Data 6 SIN First Data Figure 31. DSPI classic SPI timing - slave, CPHA = 1 3 PCSx 4 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1 10 Figure 32. DSPI modified transfer format timing - master, CPHA = 0 MPC5604P Microcontroller Data Sheet, Rev. 5 70 Preliminary—Subject to Change Without Notice Freescale Semiconductor PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data Data 12 SOUT First Data Data 10 Last Data 11 Last Data Figure 33. DSPI modified transfer format timing - master, CPHA = 1 SS 2 1 3 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4 Figure 34. DSPI modified transfer format timing - slave, CPHA = 0 MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 71 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 5 SOUT 11 12 First Data 9 10 Data Last Data Data Last Data 6 SIN First Data Figure 35. DSPI modified transfer format timing - slave, CPHA = 1 7 PCSS PCSx 8 Figure 36. DSPI PCS strobe (PCSS) timing MPC5604P Microcontroller Data Sheet, Rev. 5 72 Preliminary—Subject to Change Without Notice Freescale Semiconductor 4 4.1 4.1.1 L Package characteristics Package mechanical data 144 LQFP mechanical outline drawing Figure 37. 144 LQFP package mechanical drawing (part 1) MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 73 Figure 38. 144 LQFP package mechanical drawing (part 2) MPC5604P Microcontroller Data Sheet, Rev. 5 74 Preliminary—Subject to Change Without Notice Freescale Semiconductor 4.1.2 100 LQFP Mechanical Outline Drawing Figure 39. 100 LQFP package mechanical drawing (part 1) MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 75 Figure 40. 100 LQFP package mechanical drawing (part 2) MPC5604P Microcontroller Data Sheet, Rev. 5 76 Preliminary—Subject to Change Without Notice Freescale Semiconductor Figure 41. 100 LQFP package mechanical drawing (part 3) MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 77 5 Ordering Information Table 39. Orderable Part Number Summary Part Number MPC5604PEFMLQ MPC5604PEFMLL MPC5603PEFMLQ MPC5603PEFMLL Code Flash / Data Flash (EE) (KB) 512 / 64 512 / 64 384 / 64 384 / 64 SRAM (KB) 40 40 36 36 Package 144 LQFP 100 LQFP 144 LQFP 100 LQFP Characteristics FlexRay FlexRay FlexRay FlexRay Table 39 shows the orderable part numbers for the MPC5604P series. Commercial product code structure Example code: Qualification Status PowerPC Core Automotive Platform Core Version Flash Size (core dependent) Product Optional Fields Fab & Mask Revision Temperature spec. Package Code Frequency R = Tape & Reel (blank if Tray) M PC 56 0 4 P G F0 M LQ 7 R Qualification Status M = MC status S = Automotive qualified P = PC status Flash Size (z0 core) 3 = 384 KB 4 = 512 KB Temperature spec. V = –40°C to 105°C M = –40°C to 125°C Product Automotive Platform 56 = PPC in 90nm P = Pictus Package Code LL = 100 LQFP LQ = 144 LQFP Optional fields Core Version 0 = e200z0 E = Data Flash (blank if none) F = FlexRay Frequency 7= 64 MHz MPC5604P Microcontroller Data Sheet, Rev. 5 78 Preliminary—Subject to Change Without Notice Freescale Semiconductor 6 Document revision history Table 40. Revision history Revision Rev. 1 Rev. 2 Date 8/2008 11/2008 Initial release Table 4: TDO and TDI pins (Port pins B[4:5] are single function pins. Table 8, Table 9: Thermal characteristics added. Table 11, Table 12: EMI testing specifications split into separate tables for Normal mode and Airbag mode; data to be added in a later revision. Table 16, Table 17, Table 19, Table 20: Supply current specifications split into separate tables for Normal mode and Airbag mode; data to be added in a later revision. Table 19: Substantive changes Table 40 summarizes revisions to this document. • • • • Values for IOL and IOH (in Conditions column) changed. Max values for VOH_S, VOH_M, VOH_F and VOH_SYM deleted. VILR max value changed. IPUR min and max values changed. Table 23: Sensitivity value changed. Table 30: Most values in table changed. Rev. 3 2/2009 • • • • • • Description of system requirements, controller characteristics and how controller characteristics are guaranteed updated. Electrical parameters updated. EMI characteristics are now in one table; values have been updated. ESD characteristics are now in one table. Electrical parameters are identified as either system requirements or controller characteristics. Method used to guarantee each controller characteristic is noted in table. AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and DSPI Timing sections deleted MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 79 Table 40. Revision history (continued) Revision Rev. 4 Date 24/6/2009 Substantive changes Through all document: – Replaced all “RESET_B” occurrences with “RESET” through all document. – AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and DSPI Timing sections inserted again. – Electrical parameters updated. Section 1, “Overview: – Minor editorial clean-up. – Specified LIN 2.1 in communications interfaces feature. Table 2 – Added row for Data Flash. Table 2 – Added a footnote regarding the decoupling capacitors. Table 4 – Removed the “other function“ column. – Rearranged the contents. Table 12 – Updated definition of Condition column. Table 18 – merged in an unique Table the power consumption data related to "Maximum mode" and "Airbag mode". Table 20 – merged in an unique Table the power consumption data related to "Maximum mode" and "Airbag mode". Table 28 – Updated the parameter definition of ΔRCMVAR. – Removed the condition definition of ΔRCMVAR. Table 28 – Added tADC_C and TUE rows. Table 29 – Added tADC_C and TUE rows. – Removed Rsw2. Table 32 – Added. Table 29 – Updated and added footnotes. Section 3.16.1, “RESET Pin Characteristics – Replaces whole section. Table 38 – Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash (EE) (KB)“ – Replaced the value of RAM from 32 to 36KB in the last four rows. MPC5604P Microcontroller Data Sheet, Rev. 5 80 Preliminary—Subject to Change Without Notice Freescale Semiconductor Table 40. Revision history (continued) Revision Rev. 5 Date 06/10/2009 Substantive changes - Removed B[4] and B[5] rows from “Pin muxing” table and inserted them on “System pins” table. - Updated package pinout. - Rewrote entirely section “Power Up/dpwn Sequencing“ section. - Renamend “VDD_LV_PLL“ and “VSS_LV_PLL“ supply pins with respectively “VDD_LV_COR3“ and “VSS_LV_COR3”. - Added explicative figures on “Electrical characteristics” section. - Updated “Thermal characteristics“ for 100-pin. - Proposed two different configuration of “voltage regulator. - Inserted Power Up/Down sequence. - Added explicative figures on “DC Electrical characteristics”. - Added “I/O pad current specification” section. - Renamed the “Airbag mode” with “Typical mode“and updated the values on “supply current” tables. MPC5604P Microcontroller Data Sheet, Rev. 5 Freescale Semiconductor Preliminary—Subject to Change Without Notice 81 MPC5604P Microcontroller Data Sheet, Rev. 5 82 Preliminary—Subject to Change Without Notice Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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